1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* Number of attempts to combine instructions in this function. */
96 static int combine_attempts
;
98 /* Number of attempts that got as far as substitution in this function. */
100 static int combine_merges
;
102 /* Number of instructions combined with added SETs in this function. */
104 static int combine_extras
;
106 /* Number of instructions combined in this function. */
108 static int combine_successes
;
110 /* Totals over entire compilation. */
112 static int total_attempts
, total_merges
, total_extras
, total_successes
;
115 /* Vector mapping INSN_UIDs to cuids.
116 The cuids are like uids but increase monotonically always.
117 Combine always uses cuids so that it can compare them.
118 But actually renumbering the uids, which we used to do,
119 proves to be a bad idea because it makes it hard to compare
120 the dumps produced by earlier passes with those from later passes. */
122 static int *uid_cuid
;
123 static int max_uid_cuid
;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) \
128 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
130 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
131 BITS_PER_WORD would invoke undefined behavior. Work around it. */
133 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
134 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
136 #define nonzero_bits(X, M) \
137 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
139 #define num_sign_bit_copies(X, M) \
140 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno
;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx
*reg_last_death
;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx
*reg_last_set
;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set
;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid
;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn
;
172 /* This is the lowest CUID that `subst' is currently dealing with.
173 get_last_value will not return a value if the register was set at or
174 after this CUID. If not for this mechanism, we could get confused if
175 I2 or I1 in try_combine were an insn that used the old value of a register
176 to obtain a new value. In that case, we might erroneously get the
177 new value of the register when we wanted the old one. */
179 static int subst_low_cuid
;
181 /* This contains any hard registers that are used in newpat; reg_dead_at_p
182 must consider all these registers to be always live. */
184 static HARD_REG_SET newpat_used_regs
;
186 /* This is an insn to which a LOG_LINKS entry has been added. If this
187 insn is the earlier than I2 or I3, combine should rescan starting at
190 static rtx added_links_insn
;
192 /* Basic block in which we are performing combines. */
193 static basic_block this_basic_block
;
195 /* A bitmap indicating which blocks had registers go dead at entry.
196 After combine, we'll need to re-do global life analysis with
197 those blocks as starting points. */
198 static sbitmap refresh_blocks
;
200 /* The next group of arrays allows the recording of the last value assigned
201 to (hard or pseudo) register n. We use this information to see if an
202 operation being processed is redundant given a prior operation performed
203 on the register. For example, an `and' with a constant is redundant if
204 all the zero bits are already known to be turned off.
206 We use an approach similar to that used by cse, but change it in the
209 (1) We do not want to reinitialize at each label.
210 (2) It is useful, but not critical, to know the actual value assigned
211 to a register. Often just its form is helpful.
213 Therefore, we maintain the following arrays:
215 reg_last_set_value the last value assigned
216 reg_last_set_label records the value of label_tick when the
217 register was assigned
218 reg_last_set_table_tick records the value of label_tick when a
219 value using the register is assigned
220 reg_last_set_invalid set to nonzero when it is not valid
221 to use the value of this register in some
224 To understand the usage of these tables, it is important to understand
225 the distinction between the value in reg_last_set_value being valid
226 and the register being validly contained in some other expression in the
229 Entry I in reg_last_set_value is valid if it is nonzero, and either
230 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
232 Register I may validly appear in any expression returned for the value
233 of another register if reg_n_sets[i] is 1. It may also appear in the
234 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
235 reg_last_set_invalid[j] is zero.
237 If an expression is found in the table containing a register which may
238 not validly appear in an expression, the register is replaced by
239 something that won't match, (clobber (const_int 0)).
241 reg_last_set_invalid[i] is set nonzero when register I is being assigned
242 to and reg_last_set_table_tick[i] == label_tick. */
244 /* Record last value assigned to (hard or pseudo) register n. */
246 static rtx
*reg_last_set_value
;
248 /* Record the value of label_tick when the value for register n is placed in
249 reg_last_set_value[n]. */
251 static int *reg_last_set_label
;
253 /* Record the value of label_tick when an expression involving register n
254 is placed in reg_last_set_value. */
256 static int *reg_last_set_table_tick
;
258 /* Set nonzero if references to register n in expressions should not be
261 static char *reg_last_set_invalid
;
263 /* Incremented for each label. */
265 static int label_tick
;
267 /* Some registers that are set more than once and used in more than one
268 basic block are nevertheless always set in similar ways. For example,
269 a QImode register may be loaded from memory in two places on a machine
270 where byte loads zero extend.
272 We record in the following array what we know about the nonzero
273 bits of a register, specifically which bits are known to be zero.
275 If an entry is zero, it means that we don't know anything special. */
277 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
279 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
280 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
282 static enum machine_mode nonzero_bits_mode
;
284 /* Nonzero if we know that a register has some leading bits that are always
285 equal to the sign bit. */
287 static unsigned char *reg_sign_bit_copies
;
289 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
290 It is zero while computing them and after combine has completed. This
291 former test prevents propagating values based on previously set values,
292 which can be incorrect if a variable is modified in a loop. */
294 static int nonzero_sign_valid
;
296 /* These arrays are maintained in parallel with reg_last_set_value
297 and are used to store the mode in which the register was last set,
298 the bits that were known to be zero when it was last set, and the
299 number of sign bits copies it was known to have when it was last set. */
301 static enum machine_mode
*reg_last_set_mode
;
302 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
303 static char *reg_last_set_sign_bit_copies
;
305 /* Record one modification to rtl structure
306 to be undone by storing old_contents into *where.
307 is_int is 1 if the contents are an int. */
313 union {rtx r
; int i
;} old_contents
;
314 union {rtx
*r
; int *i
;} where
;
317 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
318 num_undo says how many are currently recorded.
320 other_insn is nonzero if we have modified some other insn in the process
321 of working on subst_insn. It must be verified too. */
330 static struct undobuf undobuf
;
332 /* Number of times the pseudo being substituted for
333 was found and replaced. */
335 static int n_occurrences
;
337 static void do_SUBST (rtx
*, rtx
);
338 static void do_SUBST_INT (int *, int);
339 static void init_reg_last_arrays (void);
340 static void setup_incoming_promotions (void);
341 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
342 static int cant_combine_insn_p (rtx
);
343 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
344 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
345 static int contains_muldiv (rtx
);
346 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
347 static void undo_all (void);
348 static void undo_commit (void);
349 static rtx
*find_split_point (rtx
*, rtx
);
350 static rtx
subst (rtx
, rtx
, rtx
, int, int);
351 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
352 static rtx
simplify_if_then_else (rtx
);
353 static rtx
simplify_set (rtx
);
354 static rtx
simplify_logical (rtx
, int);
355 static rtx
expand_compound_operation (rtx
);
356 static rtx
expand_field_assignment (rtx
);
357 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
358 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
359 static rtx
extract_left_shift (rtx
, int);
360 static rtx
make_compound_operation (rtx
, enum rtx_code
);
361 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
362 unsigned HOST_WIDE_INT
*);
363 static rtx
force_to_mode (rtx
, enum machine_mode
,
364 unsigned HOST_WIDE_INT
, rtx
, int);
365 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
366 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
367 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
368 static rtx
make_field_assignment (rtx
);
369 static rtx
apply_distributive_law (rtx
);
370 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
371 unsigned HOST_WIDE_INT
);
372 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
373 rtx
, enum machine_mode
,
374 unsigned HOST_WIDE_INT
);
375 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
377 unsigned HOST_WIDE_INT
);
378 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
381 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
382 enum machine_mode
, unsigned int);
383 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
384 HOST_WIDE_INT
, enum machine_mode
, int *);
385 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
387 static int recog_for_combine (rtx
*, rtx
, rtx
*);
388 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
389 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
390 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
391 static void update_table_tick (rtx
);
392 static void record_value_for_reg (rtx
, rtx
, rtx
);
393 static void check_promoted_subreg (rtx
, rtx
);
394 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
395 static void record_dead_and_set_regs (rtx
);
396 static int get_last_value_validate (rtx
*, rtx
, int, int);
397 static rtx
get_last_value (rtx
);
398 static int use_crosses_set_p (rtx
, int);
399 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
400 static int reg_dead_at_p (rtx
, rtx
);
401 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
402 static int reg_bitfield_target_p (rtx
, rtx
);
403 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
404 static void distribute_links (rtx
);
405 static void mark_used_regs_combine (rtx
);
406 static int insn_cuid (rtx
);
407 static void record_promoted_value (rtx
, rtx
);
408 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
409 static enum rtx_code
combine_reversed_comparison_code (rtx
);
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (rtx
*into
, rtx newval
)
423 if (oldval
== newval
)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
432 && GET_CODE (newval
) == CONST_INT
)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval
) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
448 || (GET_CODE (oldval
) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
454 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
456 buf
= xmalloc (sizeof (struct undo
));
460 buf
->old_contents
.r
= oldval
;
463 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (int *into
, int newval
)
478 if (oldval
== newval
)
482 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
484 buf
= xmalloc (sizeof (struct undo
));
488 buf
->old_contents
.i
= oldval
;
491 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
494 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
496 /* Main entry point for combiner. F is the first insn of the function.
497 NREGS is the first unused pseudo-reg number.
499 Return nonzero if the combiner has turned an indirect jump
500 instruction into a direct jump. */
502 combine_instructions (rtx f
, unsigned int nregs
)
509 rtx links
, nextlinks
;
511 int new_direct_jump_p
= 0;
513 combine_attempts
= 0;
516 combine_successes
= 0;
518 combine_max_regno
= nregs
;
520 /* It is not safe to use ordinary gen_lowpart in combine.
521 See comments in gen_lowpart_for_combine. */
522 gen_lowpart
= gen_lowpart_for_combine
;
524 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
525 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
527 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
531 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
532 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
533 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
534 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
535 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
537 init_reg_last_arrays ();
539 init_recog_no_volatile ();
541 /* Compute maximum uid value so uid_cuid can be allocated. */
543 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
544 if (INSN_UID (insn
) > i
)
547 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
550 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
552 /* Don't use reg_nonzero_bits when computing it. This can cause problems
553 when, for example, we have j <<= 1 in a loop. */
555 nonzero_sign_valid
= 0;
557 /* Compute the mapping from uids to cuids.
558 Cuids are numbers assigned to insns, like uids,
559 except that cuids increase monotonically through the code.
561 Scan all SETs and see if we can deduce anything about what
562 bits are known to be zero for some registers and how many copies
563 of the sign bit are known to exist for those registers.
565 Also set any known values so that we can use it while searching
566 for what bits are known to be set. */
570 setup_incoming_promotions ();
572 refresh_blocks
= sbitmap_alloc (last_basic_block
);
573 sbitmap_zero (refresh_blocks
);
575 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
577 uid_cuid
[INSN_UID (insn
)] = ++i
;
583 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
585 record_dead_and_set_regs (insn
);
588 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
589 if (REG_NOTE_KIND (links
) == REG_INC
)
590 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
595 if (GET_CODE (insn
) == CODE_LABEL
)
599 nonzero_sign_valid
= 1;
601 /* Now scan all the insns in forward order. */
606 init_reg_last_arrays ();
607 setup_incoming_promotions ();
609 FOR_EACH_BB (this_basic_block
)
611 for (insn
= BB_HEAD (this_basic_block
);
612 insn
!= NEXT_INSN (BB_END (this_basic_block
));
613 insn
= next
? next
: NEXT_INSN (insn
))
617 if (GET_CODE (insn
) == CODE_LABEL
)
620 else if (INSN_P (insn
))
622 /* See if we know about function return values before this
623 insn based upon SUBREG flags. */
624 check_promoted_subreg (insn
, PATTERN (insn
));
626 /* Try this insn with each insn it links back to. */
628 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
629 if ((next
= try_combine (insn
, XEXP (links
, 0),
630 NULL_RTX
, &new_direct_jump_p
)) != 0)
633 /* Try each sequence of three linked insns ending with this one. */
635 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
637 rtx link
= XEXP (links
, 0);
639 /* If the linked insn has been replaced by a note, then there
640 is no point in pursuing this chain any further. */
641 if (GET_CODE (link
) == NOTE
)
644 for (nextlinks
= LOG_LINKS (link
);
646 nextlinks
= XEXP (nextlinks
, 1))
647 if ((next
= try_combine (insn
, link
,
649 &new_direct_jump_p
)) != 0)
654 /* Try to combine a jump insn that uses CC0
655 with a preceding insn that sets CC0, and maybe with its
656 logical predecessor as well.
657 This is how we make decrement-and-branch insns.
658 We need this special code because data flow connections
659 via CC0 do not get entered in LOG_LINKS. */
661 if (GET_CODE (insn
) == JUMP_INSN
662 && (prev
= prev_nonnote_insn (insn
)) != 0
663 && GET_CODE (prev
) == INSN
664 && sets_cc0_p (PATTERN (prev
)))
666 if ((next
= try_combine (insn
, prev
,
667 NULL_RTX
, &new_direct_jump_p
)) != 0)
670 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
671 nextlinks
= XEXP (nextlinks
, 1))
672 if ((next
= try_combine (insn
, prev
,
674 &new_direct_jump_p
)) != 0)
678 /* Do the same for an insn that explicitly references CC0. */
679 if (GET_CODE (insn
) == INSN
680 && (prev
= prev_nonnote_insn (insn
)) != 0
681 && GET_CODE (prev
) == INSN
682 && sets_cc0_p (PATTERN (prev
))
683 && GET_CODE (PATTERN (insn
)) == SET
684 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
686 if ((next
= try_combine (insn
, prev
,
687 NULL_RTX
, &new_direct_jump_p
)) != 0)
690 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
691 nextlinks
= XEXP (nextlinks
, 1))
692 if ((next
= try_combine (insn
, prev
,
694 &new_direct_jump_p
)) != 0)
698 /* Finally, see if any of the insns that this insn links to
699 explicitly references CC0. If so, try this insn, that insn,
700 and its predecessor if it sets CC0. */
701 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
702 if (GET_CODE (XEXP (links
, 0)) == INSN
703 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
704 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
705 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
706 && GET_CODE (prev
) == INSN
707 && sets_cc0_p (PATTERN (prev
))
708 && (next
= try_combine (insn
, XEXP (links
, 0),
709 prev
, &new_direct_jump_p
)) != 0)
713 /* Try combining an insn with two different insns whose results it
715 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
716 for (nextlinks
= XEXP (links
, 1); nextlinks
;
717 nextlinks
= XEXP (nextlinks
, 1))
718 if ((next
= try_combine (insn
, XEXP (links
, 0),
720 &new_direct_jump_p
)) != 0)
723 if (GET_CODE (insn
) != NOTE
)
724 record_dead_and_set_regs (insn
);
733 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
734 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
735 new_direct_jump_p
|= purge_all_dead_edges (0);
736 delete_noop_moves (f
);
738 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
739 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
740 | PROP_KILL_DEAD_CODE
);
743 sbitmap_free (refresh_blocks
);
744 free (reg_nonzero_bits
);
745 free (reg_sign_bit_copies
);
746 free (reg_last_death
);
748 free (reg_last_set_value
);
749 free (reg_last_set_table_tick
);
750 free (reg_last_set_label
);
751 free (reg_last_set_invalid
);
752 free (reg_last_set_mode
);
753 free (reg_last_set_nonzero_bits
);
754 free (reg_last_set_sign_bit_copies
);
758 struct undo
*undo
, *next
;
759 for (undo
= undobuf
.frees
; undo
; undo
= next
)
767 total_attempts
+= combine_attempts
;
768 total_merges
+= combine_merges
;
769 total_extras
+= combine_extras
;
770 total_successes
+= combine_successes
;
772 nonzero_sign_valid
= 0;
773 gen_lowpart
= gen_lowpart_general
;
775 /* Make recognizer allow volatile MEMs again. */
778 return new_direct_jump_p
;
781 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
784 init_reg_last_arrays (void)
786 unsigned int nregs
= combine_max_regno
;
788 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
789 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
790 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
791 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
792 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
793 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
794 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
795 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
796 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
799 /* Set up any promoted values for incoming argument registers. */
802 setup_incoming_promotions (void)
806 enum machine_mode mode
;
808 rtx first
= get_insns ();
810 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
812 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
813 /* Check whether this register can hold an incoming pointer
814 argument. FUNCTION_ARG_REGNO_P tests outgoing register
815 numbers, so translate if necessary due to register windows. */
816 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
817 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
820 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
823 gen_rtx_CLOBBER (mode
, const0_rtx
)));
828 /* Called via note_stores. If X is a pseudo that is narrower than
829 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
831 If we are setting only a portion of X and we can't figure out what
832 portion, assume all bits will be used since we don't know what will
835 Similarly, set how many bits of X are known to be copies of the sign bit
836 at all locations in the function. This is the smallest number implied
840 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
841 void *data ATTRIBUTE_UNUSED
)
845 if (GET_CODE (x
) == REG
846 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
847 /* If this register is undefined at the start of the file, we can't
848 say what its contents were. */
849 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
850 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
852 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
854 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
855 reg_sign_bit_copies
[REGNO (x
)] = 1;
859 /* If this is a complex assignment, see if we can convert it into a
860 simple assignment. */
861 set
= expand_field_assignment (set
);
863 /* If this is a simple assignment, or we have a paradoxical SUBREG,
864 set what we know about X. */
866 if (SET_DEST (set
) == x
867 || (GET_CODE (SET_DEST (set
)) == SUBREG
868 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
869 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
870 && SUBREG_REG (SET_DEST (set
)) == x
))
872 rtx src
= SET_SRC (set
);
874 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
875 /* If X is narrower than a word and SRC is a non-negative
876 constant that would appear negative in the mode of X,
877 sign-extend it for use in reg_nonzero_bits because some
878 machines (maybe most) will actually do the sign-extension
879 and this is the conservative approach.
881 ??? For 2.5, try to tighten up the MD files in this regard
882 instead of this kludge. */
884 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
885 && GET_CODE (src
) == CONST_INT
887 && 0 != (INTVAL (src
)
889 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
890 src
= GEN_INT (INTVAL (src
)
891 | ((HOST_WIDE_INT
) (-1)
892 << GET_MODE_BITSIZE (GET_MODE (x
))));
895 /* Don't call nonzero_bits if it cannot change anything. */
896 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
897 reg_nonzero_bits
[REGNO (x
)]
898 |= nonzero_bits (src
, nonzero_bits_mode
);
899 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
900 if (reg_sign_bit_copies
[REGNO (x
)] == 0
901 || reg_sign_bit_copies
[REGNO (x
)] > num
)
902 reg_sign_bit_copies
[REGNO (x
)] = num
;
906 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
907 reg_sign_bit_copies
[REGNO (x
)] = 1;
912 /* See if INSN can be combined into I3. PRED and SUCC are optionally
913 insns that were previously combined into I3 or that will be combined
914 into the merger of INSN and I3.
916 Return 0 if the combination is not allowed for any reason.
918 If the combination is allowed, *PDEST will be set to the single
919 destination of INSN and *PSRC to the single source, and this function
923 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
924 rtx
*pdest
, rtx
*psrc
)
927 rtx set
= 0, src
, dest
;
932 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
933 && next_active_insn (succ
) == i3
)
934 : next_active_insn (insn
) == i3
);
936 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
937 or a PARALLEL consisting of such a SET and CLOBBERs.
939 If INSN has CLOBBER parallel parts, ignore them for our processing.
940 By definition, these happen during the execution of the insn. When it
941 is merged with another insn, all bets are off. If they are, in fact,
942 needed and aren't also supplied in I3, they may be added by
943 recog_for_combine. Otherwise, it won't match.
945 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
948 Get the source and destination of INSN. If more than one, can't
951 if (GET_CODE (PATTERN (insn
)) == SET
)
952 set
= PATTERN (insn
);
953 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
954 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
956 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
958 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
961 switch (GET_CODE (elt
))
963 /* This is important to combine floating point insns
966 /* Combining an isolated USE doesn't make sense.
967 We depend here on combinable_i3pat to reject them. */
968 /* The code below this loop only verifies that the inputs of
969 the SET in INSN do not change. We call reg_set_between_p
970 to verify that the REG in the USE does not change between
972 If the USE in INSN was for a pseudo register, the matching
973 insn pattern will likely match any register; combining this
974 with any other USE would only be safe if we knew that the
975 used registers have identical values, or if there was
976 something to tell them apart, e.g. different modes. For
977 now, we forgo such complicated tests and simply disallow
978 combining of USES of pseudo registers with any other USE. */
979 if (GET_CODE (XEXP (elt
, 0)) == REG
980 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
982 rtx i3pat
= PATTERN (i3
);
983 int i
= XVECLEN (i3pat
, 0) - 1;
984 unsigned int regno
= REGNO (XEXP (elt
, 0));
988 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
990 if (GET_CODE (i3elt
) == USE
991 && GET_CODE (XEXP (i3elt
, 0)) == REG
992 && (REGNO (XEXP (i3elt
, 0)) == regno
993 ? reg_set_between_p (XEXP (elt
, 0),
994 PREV_INSN (insn
), i3
)
995 : regno
>= FIRST_PSEUDO_REGISTER
))
1002 /* We can ignore CLOBBERs. */
1007 /* Ignore SETs whose result isn't used but not those that
1008 have side-effects. */
1009 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1010 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1011 || INTVAL (XEXP (note
, 0)) <= 0)
1012 && ! side_effects_p (elt
))
1015 /* If we have already found a SET, this is a second one and
1016 so we cannot combine with this insn. */
1024 /* Anything else means we can't combine. */
1030 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1031 so don't do anything with it. */
1032 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1041 set
= expand_field_assignment (set
);
1042 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1044 /* Don't eliminate a store in the stack pointer. */
1045 if (dest
== stack_pointer_rtx
1046 /* Don't combine with an insn that sets a register to itself if it has
1047 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1048 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1049 /* Can't merge an ASM_OPERANDS. */
1050 || GET_CODE (src
) == ASM_OPERANDS
1051 /* Can't merge a function call. */
1052 || GET_CODE (src
) == CALL
1053 /* Don't eliminate a function call argument. */
1054 || (GET_CODE (i3
) == CALL_INSN
1055 && (find_reg_fusage (i3
, USE
, dest
)
1056 || (GET_CODE (dest
) == REG
1057 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1058 && global_regs
[REGNO (dest
)])))
1059 /* Don't substitute into an incremented register. */
1060 || FIND_REG_INC_NOTE (i3
, dest
)
1061 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1063 /* Don't combine the end of a libcall into anything. */
1064 /* ??? This gives worse code, and appears to be unnecessary, since no
1065 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1066 use REG_RETVAL notes for noconflict blocks, but other code here
1067 makes sure that those insns don't disappear. */
1068 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1070 /* Make sure that DEST is not used after SUCC but before I3. */
1071 || (succ
&& ! all_adjacent
1072 && reg_used_between_p (dest
, succ
, i3
))
1073 /* Make sure that the value that is to be substituted for the register
1074 does not use any registers whose values alter in between. However,
1075 If the insns are adjacent, a use can't cross a set even though we
1076 think it might (this can happen for a sequence of insns each setting
1077 the same destination; reg_last_set of that register might point to
1078 a NOTE). If INSN has a REG_EQUIV note, the register is always
1079 equivalent to the memory so the substitution is valid even if there
1080 are intervening stores. Also, don't move a volatile asm or
1081 UNSPEC_VOLATILE across any other insns. */
1083 && (((GET_CODE (src
) != MEM
1084 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1085 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1086 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1087 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1088 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1089 better register allocation by not doing the combine. */
1090 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1091 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1092 /* Don't combine across a CALL_INSN, because that would possibly
1093 change whether the life span of some REGs crosses calls or not,
1094 and it is a pain to update that information.
1095 Exception: if source is a constant, moving it later can't hurt.
1096 Accept that special case, because it helps -fforce-addr a lot. */
1097 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1100 /* DEST must either be a REG or CC0. */
1101 if (GET_CODE (dest
) == REG
)
1103 /* If register alignment is being enforced for multi-word items in all
1104 cases except for parameters, it is possible to have a register copy
1105 insn referencing a hard register that is not allowed to contain the
1106 mode being copied and which would not be valid as an operand of most
1107 insns. Eliminate this problem by not combining with such an insn.
1109 Also, on some machines we don't want to extend the life of a hard
1112 if (GET_CODE (src
) == REG
1113 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1114 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1115 /* Don't extend the life of a hard register unless it is
1116 user variable (if we have few registers) or it can't
1117 fit into the desired register (meaning something special
1119 Also avoid substituting a return register into I3, because
1120 reload can't handle a conflict with constraints of other
1122 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1123 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1126 else if (GET_CODE (dest
) != CC0
)
1129 /* Don't substitute for a register intended as a clobberable operand.
1130 Similarly, don't substitute an expression containing a register that
1131 will be clobbered in I3. */
1132 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1133 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1134 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1135 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1137 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1140 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1141 or not), reject, unless nothing volatile comes between it and I3 */
1143 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1145 /* Make sure succ doesn't contain a volatile reference. */
1146 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1149 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1150 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1154 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1155 to be an explicit register variable, and was chosen for a reason. */
1157 if (GET_CODE (src
) == ASM_OPERANDS
1158 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1161 /* If there are any volatile insns between INSN and I3, reject, because
1162 they might affect machine state. */
1164 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1165 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1168 /* If INSN or I2 contains an autoincrement or autodecrement,
1169 make sure that register is not used between there and I3,
1170 and not already used in I3 either.
1171 Also insist that I3 not be a jump; if it were one
1172 and the incremented register were spilled, we would lose. */
1175 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1176 if (REG_NOTE_KIND (link
) == REG_INC
1177 && (GET_CODE (i3
) == JUMP_INSN
1178 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1179 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1184 /* Don't combine an insn that follows a CC0-setting insn.
1185 An insn that uses CC0 must not be separated from the one that sets it.
1186 We do, however, allow I2 to follow a CC0-setting insn if that insn
1187 is passed as I1; in that case it will be deleted also.
1188 We also allow combining in this case if all the insns are adjacent
1189 because that would leave the two CC0 insns adjacent as well.
1190 It would be more logical to test whether CC0 occurs inside I1 or I2,
1191 but that would be much slower, and this ought to be equivalent. */
1193 p
= prev_nonnote_insn (insn
);
1194 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1199 /* If we get here, we have passed all the tests and the combination is
1208 /* LOC is the location within I3 that contains its pattern or the component
1209 of a PARALLEL of the pattern. We validate that it is valid for combining.
1211 One problem is if I3 modifies its output, as opposed to replacing it
1212 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1213 so would produce an insn that is not equivalent to the original insns.
1217 (set (reg:DI 101) (reg:DI 100))
1218 (set (subreg:SI (reg:DI 101) 0) <foo>)
1220 This is NOT equivalent to:
1222 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1223 (set (reg:DI 101) (reg:DI 100))])
1225 Not only does this modify 100 (in which case it might still be valid
1226 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1228 We can also run into a problem if I2 sets a register that I1
1229 uses and I1 gets directly substituted into I3 (not via I2). In that
1230 case, we would be getting the wrong value of I2DEST into I3, so we
1231 must reject the combination. This case occurs when I2 and I1 both
1232 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1233 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1234 of a SET must prevent combination from occurring.
1236 Before doing the above check, we first try to expand a field assignment
1237 into a set of logical operations.
1239 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1240 we place a register that is both set and used within I3. If more than one
1241 such register is detected, we fail.
1243 Return 1 if the combination is valid, zero otherwise. */
1246 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1247 int i1_not_in_src
, rtx
*pi3dest_killed
)
1251 if (GET_CODE (x
) == SET
)
1254 rtx dest
= SET_DEST (set
);
1255 rtx src
= SET_SRC (set
);
1256 rtx inner_dest
= dest
;
1258 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1259 || GET_CODE (inner_dest
) == SUBREG
1260 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1261 inner_dest
= XEXP (inner_dest
, 0);
1263 /* Check for the case where I3 modifies its output, as discussed
1264 above. We don't want to prevent pseudos from being combined
1265 into the address of a MEM, so only prevent the combination if
1266 i1 or i2 set the same MEM. */
1267 if ((inner_dest
!= dest
&&
1268 (GET_CODE (inner_dest
) != MEM
1269 || rtx_equal_p (i2dest
, inner_dest
)
1270 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1271 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1272 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1274 /* This is the same test done in can_combine_p except we can't test
1275 all_adjacent; we don't have to, since this instruction will stay
1276 in place, thus we are not considering increasing the lifetime of
1279 Also, if this insn sets a function argument, combining it with
1280 something that might need a spill could clobber a previous
1281 function argument; the all_adjacent test in can_combine_p also
1282 checks this; here, we do a more specific test for this case. */
1284 || (GET_CODE (inner_dest
) == REG
1285 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1286 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1287 GET_MODE (inner_dest
))))
1288 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1291 /* If DEST is used in I3, it is being killed in this insn,
1292 so record that for later.
1293 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1294 STACK_POINTER_REGNUM, since these are always considered to be
1295 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1296 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1297 && reg_referenced_p (dest
, PATTERN (i3
))
1298 && REGNO (dest
) != FRAME_POINTER_REGNUM
1299 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1300 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1302 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1303 && (REGNO (dest
) != ARG_POINTER_REGNUM
1304 || ! fixed_regs
[REGNO (dest
)])
1306 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1308 if (*pi3dest_killed
)
1311 *pi3dest_killed
= dest
;
1315 else if (GET_CODE (x
) == PARALLEL
)
1319 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1320 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1321 i1_not_in_src
, pi3dest_killed
))
1328 /* Return 1 if X is an arithmetic expression that contains a multiplication
1329 and division. We don't count multiplications by powers of two here. */
1332 contains_muldiv (rtx x
)
1334 switch (GET_CODE (x
))
1336 case MOD
: case DIV
: case UMOD
: case UDIV
:
1340 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1341 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1344 return contains_muldiv (XEXP (x
, 0))
1345 || contains_muldiv (XEXP (x
, 1));
1348 return contains_muldiv (XEXP (x
, 0));
1354 /* Determine whether INSN can be used in a combination. Return nonzero if
1355 not. This is used in try_combine to detect early some cases where we
1356 can't perform combinations. */
1359 cant_combine_insn_p (rtx insn
)
1364 /* If this isn't really an insn, we can't do anything.
1365 This can occur when flow deletes an insn that it has merged into an
1366 auto-increment address. */
1367 if (! INSN_P (insn
))
1370 /* Never combine loads and stores involving hard regs that are likely
1371 to be spilled. The register allocator can usually handle such
1372 reg-reg moves by tying. If we allow the combiner to make
1373 substitutions of likely-spilled regs, we may abort in reload.
1374 As an exception, we allow combinations involving fixed regs; these are
1375 not available to the register allocator so there's no risk involved. */
1377 set
= single_set (insn
);
1380 src
= SET_SRC (set
);
1381 dest
= SET_DEST (set
);
1382 if (GET_CODE (src
) == SUBREG
)
1383 src
= SUBREG_REG (src
);
1384 if (GET_CODE (dest
) == SUBREG
)
1385 dest
= SUBREG_REG (dest
);
1386 if (REG_P (src
) && REG_P (dest
)
1387 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1388 && ! fixed_regs
[REGNO (src
)]
1389 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1390 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1391 && ! fixed_regs
[REGNO (dest
)]
1392 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1398 /* Adjust INSN after we made a change to its destination.
1400 Changing the destination can invalidate notes that say something about
1401 the results of the insn and a LOG_LINK pointing to the insn. */
1404 adjust_for_new_dest (rtx insn
)
1408 /* For notes, be conservative and simply remove them. */
1409 loc
= ®_NOTES (insn
);
1412 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1413 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1414 *loc
= XEXP (*loc
, 1);
1416 loc
= &XEXP (*loc
, 1);
1419 /* The new insn will have a destination that was previously the destination
1420 of an insn just above it. Call distribute_links to make a LOG_LINK from
1421 the next use of that destination. */
1422 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1425 /* Try to combine the insns I1 and I2 into I3.
1426 Here I1 and I2 appear earlier than I3.
1427 I1 can be zero; then we combine just I2 into I3.
1429 If we are combining three insns and the resulting insn is not recognized,
1430 try splitting it into two insns. If that happens, I2 and I3 are retained
1431 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1434 Return 0 if the combination does not work. Then nothing is changed.
1435 If we did the combination, return the insn at which combine should
1438 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1439 new direct jump instruction. */
1442 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1444 /* New patterns for I3 and I2, respectively. */
1445 rtx newpat
, newi2pat
= 0;
1446 int substed_i2
= 0, substed_i1
= 0;
1447 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1448 int added_sets_1
, added_sets_2
;
1449 /* Total number of SETs to put into I3. */
1451 /* Nonzero if I2's body now appears in I3. */
1453 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1454 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1455 /* Contains I3 if the destination of I3 is used in its source, which means
1456 that the old life of I3 is being killed. If that usage is placed into
1457 I2 and not in I3, a REG_DEAD note must be made. */
1458 rtx i3dest_killed
= 0;
1459 /* SET_DEST and SET_SRC of I2 and I1. */
1460 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1461 /* PATTERN (I2), or a copy of it in certain cases. */
1463 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1464 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1465 int i1_feeds_i3
= 0;
1466 /* Notes that must be added to REG_NOTES in I3 and I2. */
1467 rtx new_i3_notes
, new_i2_notes
;
1468 /* Notes that we substituted I3 into I2 instead of the normal case. */
1469 int i3_subst_into_i2
= 0;
1470 /* Notes that I1, I2 or I3 is a MULT operation. */
1478 /* Exit early if one of the insns involved can't be used for
1480 if (cant_combine_insn_p (i3
)
1481 || cant_combine_insn_p (i2
)
1482 || (i1
&& cant_combine_insn_p (i1
))
1483 /* We also can't do anything if I3 has a
1484 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1487 /* ??? This gives worse code, and appears to be unnecessary, since no
1488 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1489 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1495 undobuf
.other_insn
= 0;
1497 /* Reset the hard register usage information. */
1498 CLEAR_HARD_REG_SET (newpat_used_regs
);
1500 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1501 code below, set I1 to be the earlier of the two insns. */
1502 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1503 temp
= i1
, i1
= i2
, i2
= temp
;
1505 added_links_insn
= 0;
1507 /* First check for one important special-case that the code below will
1508 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1509 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1510 we may be able to replace that destination with the destination of I3.
1511 This occurs in the common code where we compute both a quotient and
1512 remainder into a structure, in which case we want to do the computation
1513 directly into the structure to avoid register-register copies.
1515 Note that this case handles both multiple sets in I2 and also
1516 cases where I2 has a number of CLOBBER or PARALLELs.
1518 We make very conservative checks below and only try to handle the
1519 most common cases of this. For example, we only handle the case
1520 where I2 and I3 are adjacent to avoid making difficult register
1523 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1524 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1525 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1526 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1527 && GET_CODE (PATTERN (i2
)) == PARALLEL
1528 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1529 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1530 below would need to check what is inside (and reg_overlap_mentioned_p
1531 doesn't support those codes anyway). Don't allow those destinations;
1532 the resulting insn isn't likely to be recognized anyway. */
1533 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1534 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1535 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1536 SET_DEST (PATTERN (i3
)))
1537 && next_real_insn (i2
) == i3
)
1539 rtx p2
= PATTERN (i2
);
1541 /* Make sure that the destination of I3,
1542 which we are going to substitute into one output of I2,
1543 is not used within another output of I2. We must avoid making this:
1544 (parallel [(set (mem (reg 69)) ...)
1545 (set (reg 69) ...)])
1546 which is not well-defined as to order of actions.
1547 (Besides, reload can't handle output reloads for this.)
1549 The problem can also happen if the dest of I3 is a memory ref,
1550 if another dest in I2 is an indirect memory ref. */
1551 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1552 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1553 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1554 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1555 SET_DEST (XVECEXP (p2
, 0, i
))))
1558 if (i
== XVECLEN (p2
, 0))
1559 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1560 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1561 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1562 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1567 subst_low_cuid
= INSN_CUID (i2
);
1569 added_sets_2
= added_sets_1
= 0;
1570 i2dest
= SET_SRC (PATTERN (i3
));
1572 /* Replace the dest in I2 with our dest and make the resulting
1573 insn the new pattern for I3. Then skip to where we
1574 validate the pattern. Everything was set up above. */
1575 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1576 SET_DEST (PATTERN (i3
)));
1579 i3_subst_into_i2
= 1;
1580 goto validate_replacement
;
1584 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1585 one of those words to another constant, merge them by making a new
1588 && (temp
= single_set (i2
)) != 0
1589 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1590 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1591 && GET_CODE (SET_DEST (temp
)) == REG
1592 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1593 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1594 && GET_CODE (PATTERN (i3
)) == SET
1595 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1596 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1597 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1598 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1599 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1601 HOST_WIDE_INT lo
, hi
;
1603 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1604 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1607 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1608 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1611 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1613 /* We don't handle the case of the target word being wider
1614 than a host wide int. */
1615 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1618 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1619 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1620 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1622 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1623 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1624 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1626 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1627 >> (HOST_BITS_PER_WIDE_INT
- 1));
1629 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1630 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1631 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1632 (INTVAL (SET_SRC (PATTERN (i3
)))));
1634 hi
= lo
< 0 ? -1 : 0;
1637 /* We don't handle the case of the higher word not fitting
1638 entirely in either hi or lo. */
1643 subst_low_cuid
= INSN_CUID (i2
);
1644 added_sets_2
= added_sets_1
= 0;
1645 i2dest
= SET_DEST (temp
);
1647 SUBST (SET_SRC (temp
),
1648 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1650 newpat
= PATTERN (i2
);
1651 goto validate_replacement
;
1655 /* If we have no I1 and I2 looks like:
1656 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1658 make up a dummy I1 that is
1661 (set (reg:CC X) (compare:CC Y (const_int 0)))
1663 (We can ignore any trailing CLOBBERs.)
1665 This undoes a previous combination and allows us to match a branch-and-
1668 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1669 && XVECLEN (PATTERN (i2
), 0) >= 2
1670 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1671 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1673 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1674 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1675 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1676 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1677 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1678 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1680 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1681 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1686 /* We make I1 with the same INSN_UID as I2. This gives it
1687 the same INSN_CUID for value tracking. Our fake I1 will
1688 never appear in the insn stream so giving it the same INSN_UID
1689 as I2 will not cause a problem. */
1691 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1692 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1693 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1696 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1697 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1698 SET_DEST (PATTERN (i1
)));
1703 /* Verify that I2 and I1 are valid for combining. */
1704 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1705 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1711 /* Record whether I2DEST is used in I2SRC and similarly for the other
1712 cases. Knowing this will help in register status updating below. */
1713 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1714 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1715 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1717 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1719 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1721 /* Ensure that I3's pattern can be the destination of combines. */
1722 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1723 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1730 /* See if any of the insns is a MULT operation. Unless one is, we will
1731 reject a combination that is, since it must be slower. Be conservative
1733 if (GET_CODE (i2src
) == MULT
1734 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1735 || (GET_CODE (PATTERN (i3
)) == SET
1736 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1739 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1740 We used to do this EXCEPT in one case: I3 has a post-inc in an
1741 output operand. However, that exception can give rise to insns like
1743 which is a famous insn on the PDP-11 where the value of r3 used as the
1744 source was model-dependent. Avoid this sort of thing. */
1747 if (!(GET_CODE (PATTERN (i3
)) == SET
1748 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1749 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1750 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1751 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1752 /* It's not the exception. */
1755 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1756 if (REG_NOTE_KIND (link
) == REG_INC
1757 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1759 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1766 /* See if the SETs in I1 or I2 need to be kept around in the merged
1767 instruction: whenever the value set there is still needed past I3.
1768 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1770 For the SET in I1, we have two cases: If I1 and I2 independently
1771 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1772 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1773 in I1 needs to be kept around unless I1DEST dies or is set in either
1774 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1775 I1DEST. If so, we know I1 feeds into I2. */
1777 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1780 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1781 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1783 /* If the set in I2 needs to be kept around, we must make a copy of
1784 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1785 PATTERN (I2), we are only substituting for the original I1DEST, not into
1786 an already-substituted copy. This also prevents making self-referential
1787 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1790 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1791 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1795 i2pat
= copy_rtx (i2pat
);
1799 /* Substitute in the latest insn for the regs set by the earlier ones. */
1801 maxreg
= max_reg_num ();
1805 /* It is possible that the source of I2 or I1 may be performing an
1806 unneeded operation, such as a ZERO_EXTEND of something that is known
1807 to have the high part zero. Handle that case by letting subst look at
1808 the innermost one of them.
1810 Another way to do this would be to have a function that tries to
1811 simplify a single insn instead of merging two or more insns. We don't
1812 do this because of the potential of infinite loops and because
1813 of the potential extra memory required. However, doing it the way
1814 we are is a bit of a kludge and doesn't catch all cases.
1816 But only do this if -fexpensive-optimizations since it slows things down
1817 and doesn't usually win. */
1819 if (flag_expensive_optimizations
)
1821 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1824 subst_low_cuid
= INSN_CUID (i1
);
1825 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1829 subst_low_cuid
= INSN_CUID (i2
);
1830 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1835 /* Many machines that don't use CC0 have insns that can both perform an
1836 arithmetic operation and set the condition code. These operations will
1837 be represented as a PARALLEL with the first element of the vector
1838 being a COMPARE of an arithmetic operation with the constant zero.
1839 The second element of the vector will set some pseudo to the result
1840 of the same arithmetic operation. If we simplify the COMPARE, we won't
1841 match such a pattern and so will generate an extra insn. Here we test
1842 for this case, where both the comparison and the operation result are
1843 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1844 I2SRC. Later we will make the PARALLEL that contains I2. */
1846 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1847 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1848 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1849 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1851 #ifdef SELECT_CC_MODE
1853 enum machine_mode compare_mode
;
1856 newpat
= PATTERN (i3
);
1857 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1861 #ifdef SELECT_CC_MODE
1862 /* See if a COMPARE with the operand we substituted in should be done
1863 with the mode that is currently being used. If not, do the same
1864 processing we do in `subst' for a SET; namely, if the destination
1865 is used only once, try to replace it with a register of the proper
1866 mode and also replace the COMPARE. */
1867 if (undobuf
.other_insn
== 0
1868 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1869 &undobuf
.other_insn
))
1870 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1872 != GET_MODE (SET_DEST (newpat
))))
1874 unsigned int regno
= REGNO (SET_DEST (newpat
));
1875 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1877 if (regno
< FIRST_PSEUDO_REGISTER
1878 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1879 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1881 if (regno
>= FIRST_PSEUDO_REGISTER
)
1882 SUBST (regno_reg_rtx
[regno
], new_dest
);
1884 SUBST (SET_DEST (newpat
), new_dest
);
1885 SUBST (XEXP (*cc_use
, 0), new_dest
);
1886 SUBST (SET_SRC (newpat
),
1887 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1890 undobuf
.other_insn
= 0;
1897 n_occurrences
= 0; /* `subst' counts here */
1899 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1900 need to make a unique copy of I2SRC each time we substitute it
1901 to avoid self-referential rtl. */
1903 subst_low_cuid
= INSN_CUID (i2
);
1904 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1905 ! i1_feeds_i3
&& i1dest_in_i1src
);
1908 /* Record whether i2's body now appears within i3's body. */
1909 i2_is_used
= n_occurrences
;
1912 /* If we already got a failure, don't try to do more. Otherwise,
1913 try to substitute in I1 if we have it. */
1915 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1917 /* Before we can do this substitution, we must redo the test done
1918 above (see detailed comments there) that ensures that I1DEST
1919 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1921 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1929 subst_low_cuid
= INSN_CUID (i1
);
1930 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1934 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1935 to count all the ways that I2SRC and I1SRC can be used. */
1936 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1937 && i2_is_used
+ added_sets_2
> 1)
1938 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1939 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1941 /* Fail if we tried to make a new register (we used to abort, but there's
1942 really no reason to). */
1943 || max_reg_num () != maxreg
1944 /* Fail if we couldn't do something and have a CLOBBER. */
1945 || GET_CODE (newpat
) == CLOBBER
1946 /* Fail if this new pattern is a MULT and we didn't have one before
1947 at the outer level. */
1948 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1955 /* If the actions of the earlier insns must be kept
1956 in addition to substituting them into the latest one,
1957 we must make a new PARALLEL for the latest insn
1958 to hold additional the SETs. */
1960 if (added_sets_1
|| added_sets_2
)
1964 if (GET_CODE (newpat
) == PARALLEL
)
1966 rtvec old
= XVEC (newpat
, 0);
1967 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1968 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1969 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1970 sizeof (old
->elem
[0]) * old
->num_elem
);
1975 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1976 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1977 XVECEXP (newpat
, 0, 0) = old
;
1981 XVECEXP (newpat
, 0, --total_sets
)
1982 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1983 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1987 /* If there is no I1, use I2's body as is. We used to also not do
1988 the subst call below if I2 was substituted into I3,
1989 but that could lose a simplification. */
1991 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1993 /* See comment where i2pat is assigned. */
1994 XVECEXP (newpat
, 0, --total_sets
)
1995 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1999 /* We come here when we are replacing a destination in I2 with the
2000 destination of I3. */
2001 validate_replacement
:
2003 /* Note which hard regs this insn has as inputs. */
2004 mark_used_regs_combine (newpat
);
2006 /* Is the result of combination a valid instruction? */
2007 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2009 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2010 the second SET's destination is a register that is unused and isn't
2011 marked as an instruction that might trap in an EH region. In that case,
2012 we just need the first SET. This can occur when simplifying a divmod
2013 insn. We *must* test for this case here because the code below that
2014 splits two independent SETs doesn't handle this case correctly when it
2015 updates the register status.
2017 It's pointless doing this if we originally had two sets, one from
2018 i3, and one from i2. Combining then splitting the parallel results
2019 in the original i2 again plus an invalid insn (which we delete).
2020 The net effect is only to move instructions around, which makes
2021 debug info less accurate.
2023 Also check the case where the first SET's destination is unused.
2024 That would not cause incorrect code, but does cause an unneeded
2027 if (insn_code_number
< 0
2028 && !(added_sets_2
&& i1
== 0)
2029 && GET_CODE (newpat
) == PARALLEL
2030 && XVECLEN (newpat
, 0) == 2
2031 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2032 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2033 && asm_noperands (newpat
) < 0)
2035 rtx set0
= XVECEXP (newpat
, 0, 0);
2036 rtx set1
= XVECEXP (newpat
, 0, 1);
2039 if (((GET_CODE (SET_DEST (set1
)) == REG
2040 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2041 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2042 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2043 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2044 || INTVAL (XEXP (note
, 0)) <= 0)
2045 && ! side_effects_p (SET_SRC (set1
)))
2048 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2051 else if (((GET_CODE (SET_DEST (set0
)) == REG
2052 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2053 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2054 && find_reg_note (i3
, REG_UNUSED
,
2055 SUBREG_REG (SET_DEST (set0
)))))
2056 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2057 || INTVAL (XEXP (note
, 0)) <= 0)
2058 && ! side_effects_p (SET_SRC (set0
)))
2061 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2063 if (insn_code_number
>= 0)
2065 /* If we will be able to accept this, we have made a
2066 change to the destination of I3. This requires us to
2067 do a few adjustments. */
2069 PATTERN (i3
) = newpat
;
2070 adjust_for_new_dest (i3
);
2075 /* If we were combining three insns and the result is a simple SET
2076 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2077 insns. There are two ways to do this. It can be split using a
2078 machine-specific method (like when you have an addition of a large
2079 constant) or by combine in the function find_split_point. */
2081 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2082 && asm_noperands (newpat
) < 0)
2084 rtx m_split
, *split
;
2085 rtx ni2dest
= i2dest
;
2087 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2088 use I2DEST as a scratch register will help. In the latter case,
2089 convert I2DEST to the mode of the source of NEWPAT if we can. */
2091 m_split
= split_insns (newpat
, i3
);
2093 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2094 inputs of NEWPAT. */
2096 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2097 possible to try that as a scratch reg. This would require adding
2098 more code to make it work though. */
2100 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2102 /* If I2DEST is a hard register or the only use of a pseudo,
2103 we can change its mode. */
2104 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2105 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2106 && GET_CODE (i2dest
) == REG
2107 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2108 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2109 && ! REG_USERVAR_P (i2dest
))))
2110 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2113 m_split
= split_insns (gen_rtx_PARALLEL
2115 gen_rtvec (2, newpat
,
2116 gen_rtx_CLOBBER (VOIDmode
,
2119 /* If the split with the mode-changed register didn't work, try
2120 the original register. */
2121 if (! m_split
&& ni2dest
!= i2dest
)
2124 m_split
= split_insns (gen_rtx_PARALLEL
2126 gen_rtvec (2, newpat
,
2127 gen_rtx_CLOBBER (VOIDmode
,
2133 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2135 m_split
= PATTERN (m_split
);
2136 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2137 if (insn_code_number
>= 0)
2140 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2141 && (next_real_insn (i2
) == i3
2142 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2145 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2146 newi2pat
= PATTERN (m_split
);
2148 i3set
= single_set (NEXT_INSN (m_split
));
2149 i2set
= single_set (m_split
);
2151 /* In case we changed the mode of I2DEST, replace it in the
2152 pseudo-register table here. We can't do it above in case this
2153 code doesn't get executed and we do a split the other way. */
2155 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2156 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2158 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2160 /* If I2 or I3 has multiple SETs, we won't know how to track
2161 register status, so don't use these insns. If I2's destination
2162 is used between I2 and I3, we also can't use these insns. */
2164 if (i2_code_number
>= 0 && i2set
&& i3set
2165 && (next_real_insn (i2
) == i3
2166 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2167 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2169 if (insn_code_number
>= 0)
2172 /* It is possible that both insns now set the destination of I3.
2173 If so, we must show an extra use of it. */
2175 if (insn_code_number
>= 0)
2177 rtx new_i3_dest
= SET_DEST (i3set
);
2178 rtx new_i2_dest
= SET_DEST (i2set
);
2180 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2181 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2182 || GET_CODE (new_i3_dest
) == SUBREG
)
2183 new_i3_dest
= XEXP (new_i3_dest
, 0);
2185 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2186 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2187 || GET_CODE (new_i2_dest
) == SUBREG
)
2188 new_i2_dest
= XEXP (new_i2_dest
, 0);
2190 if (GET_CODE (new_i3_dest
) == REG
2191 && GET_CODE (new_i2_dest
) == REG
2192 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2193 REG_N_SETS (REGNO (new_i2_dest
))++;
2197 /* If we can split it and use I2DEST, go ahead and see if that
2198 helps things be recognized. Verify that none of the registers
2199 are set between I2 and I3. */
2200 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2202 && GET_CODE (i2dest
) == REG
2204 /* We need I2DEST in the proper mode. If it is a hard register
2205 or the only use of a pseudo, we can change its mode. */
2206 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2207 || GET_MODE (*split
) == VOIDmode
2208 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2209 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2210 && ! REG_USERVAR_P (i2dest
)))
2211 && (next_real_insn (i2
) == i3
2212 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2213 /* We can't overwrite I2DEST if its value is still used by
2215 && ! reg_referenced_p (i2dest
, newpat
))
2217 rtx newdest
= i2dest
;
2218 enum rtx_code split_code
= GET_CODE (*split
);
2219 enum machine_mode split_mode
= GET_MODE (*split
);
2221 /* Get NEWDEST as a register in the proper mode. We have already
2222 validated that we can do this. */
2223 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2225 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2227 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2228 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2231 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2232 an ASHIFT. This can occur if it was inside a PLUS and hence
2233 appeared to be a memory address. This is a kludge. */
2234 if (split_code
== MULT
2235 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2236 && INTVAL (XEXP (*split
, 1)) > 0
2237 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2239 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2240 XEXP (*split
, 0), GEN_INT (i
)));
2241 /* Update split_code because we may not have a multiply
2243 split_code
= GET_CODE (*split
);
2246 #ifdef INSN_SCHEDULING
2247 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2248 be written as a ZERO_EXTEND. */
2249 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2251 #ifdef LOAD_EXTEND_OP
2252 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2253 what it really is. */
2254 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2256 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2257 SUBREG_REG (*split
)));
2260 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2261 SUBREG_REG (*split
)));
2265 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2266 SUBST (*split
, newdest
);
2267 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2269 /* If the split point was a MULT and we didn't have one before,
2270 don't use one now. */
2271 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2272 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2276 /* Check for a case where we loaded from memory in a narrow mode and
2277 then sign extended it, but we need both registers. In that case,
2278 we have a PARALLEL with both loads from the same memory location.
2279 We can split this into a load from memory followed by a register-register
2280 copy. This saves at least one insn, more if register allocation can
2283 We cannot do this if the destination of the first assignment is a
2284 condition code register or cc0. We eliminate this case by making sure
2285 the SET_DEST and SET_SRC have the same mode.
2287 We cannot do this if the destination of the second assignment is
2288 a register that we have already assumed is zero-extended. Similarly
2289 for a SUBREG of such a register. */
2291 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2292 && GET_CODE (newpat
) == PARALLEL
2293 && XVECLEN (newpat
, 0) == 2
2294 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2295 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2296 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2297 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2298 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2299 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2300 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2301 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2303 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2304 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2305 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2306 (GET_CODE (temp
) == REG
2307 && reg_nonzero_bits
[REGNO (temp
)] != 0
2308 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2309 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2310 && (reg_nonzero_bits
[REGNO (temp
)]
2311 != GET_MODE_MASK (word_mode
))))
2312 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2313 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2314 (GET_CODE (temp
) == REG
2315 && reg_nonzero_bits
[REGNO (temp
)] != 0
2316 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2317 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2318 && (reg_nonzero_bits
[REGNO (temp
)]
2319 != GET_MODE_MASK (word_mode
)))))
2320 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2321 SET_SRC (XVECEXP (newpat
, 0, 1)))
2322 && ! find_reg_note (i3
, REG_UNUSED
,
2323 SET_DEST (XVECEXP (newpat
, 0, 0))))
2327 newi2pat
= XVECEXP (newpat
, 0, 0);
2328 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2329 newpat
= XVECEXP (newpat
, 0, 1);
2330 SUBST (SET_SRC (newpat
),
2331 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2332 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2334 if (i2_code_number
>= 0)
2335 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2337 if (insn_code_number
>= 0)
2342 /* If we will be able to accept this, we have made a change to the
2343 destination of I3. This requires us to do a few adjustments. */
2344 PATTERN (i3
) = newpat
;
2345 adjust_for_new_dest (i3
);
2347 /* I3 now uses what used to be its destination and which is
2348 now I2's destination. That means we need a LOG_LINK from
2349 I3 to I2. But we used to have one, so we still will.
2351 However, some later insn might be using I2's dest and have
2352 a LOG_LINK pointing at I3. We must remove this link.
2353 The simplest way to remove the link is to point it at I1,
2354 which we know will be a NOTE. */
2356 for (insn
= NEXT_INSN (i3
);
2357 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2358 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2359 insn
= NEXT_INSN (insn
))
2361 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2363 for (link
= LOG_LINKS (insn
); link
;
2364 link
= XEXP (link
, 1))
2365 if (XEXP (link
, 0) == i3
)
2366 XEXP (link
, 0) = i1
;
2374 /* Similarly, check for a case where we have a PARALLEL of two independent
2375 SETs but we started with three insns. In this case, we can do the sets
2376 as two separate insns. This case occurs when some SET allows two
2377 other insns to combine, but the destination of that SET is still live. */
2379 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2380 && GET_CODE (newpat
) == PARALLEL
2381 && XVECLEN (newpat
, 0) == 2
2382 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2383 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2384 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2385 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2387 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2388 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2390 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2391 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2392 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2393 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2394 XVECEXP (newpat
, 0, 0))
2395 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2396 XVECEXP (newpat
, 0, 1))
2397 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2398 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2400 /* Normally, it doesn't matter which of the two is done first,
2401 but it does if one references cc0. In that case, it has to
2404 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2406 newi2pat
= XVECEXP (newpat
, 0, 0);
2407 newpat
= XVECEXP (newpat
, 0, 1);
2412 newi2pat
= XVECEXP (newpat
, 0, 1);
2413 newpat
= XVECEXP (newpat
, 0, 0);
2416 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2418 if (i2_code_number
>= 0)
2419 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2422 /* If it still isn't recognized, fail and change things back the way they
2424 if ((insn_code_number
< 0
2425 /* Is the result a reasonable ASM_OPERANDS? */
2426 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2432 /* If we had to change another insn, make sure it is valid also. */
2433 if (undobuf
.other_insn
)
2435 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2436 rtx new_other_notes
;
2439 CLEAR_HARD_REG_SET (newpat_used_regs
);
2441 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2444 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2450 PATTERN (undobuf
.other_insn
) = other_pat
;
2452 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2453 are still valid. Then add any non-duplicate notes added by
2454 recog_for_combine. */
2455 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2457 next
= XEXP (note
, 1);
2459 if (REG_NOTE_KIND (note
) == REG_UNUSED
2460 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2462 if (GET_CODE (XEXP (note
, 0)) == REG
)
2463 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2465 remove_note (undobuf
.other_insn
, note
);
2469 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2470 if (GET_CODE (XEXP (note
, 0)) == REG
)
2471 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2473 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2474 undobuf
.other_insn
, NULL_RTX
);
2477 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2478 they are adjacent to each other or not. */
2480 rtx p
= prev_nonnote_insn (i3
);
2481 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2482 && sets_cc0_p (newi2pat
))
2490 /* We now know that we can do this combination. Merge the insns and
2491 update the status of registers and LOG_LINKS. */
2494 rtx i3notes
, i2notes
, i1notes
= 0;
2495 rtx i3links
, i2links
, i1links
= 0;
2499 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2501 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2502 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2504 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2506 /* Ensure that we do not have something that should not be shared but
2507 occurs multiple times in the new insns. Check this by first
2508 resetting all the `used' flags and then copying anything is shared. */
2510 reset_used_flags (i3notes
);
2511 reset_used_flags (i2notes
);
2512 reset_used_flags (i1notes
);
2513 reset_used_flags (newpat
);
2514 reset_used_flags (newi2pat
);
2515 if (undobuf
.other_insn
)
2516 reset_used_flags (PATTERN (undobuf
.other_insn
));
2518 i3notes
= copy_rtx_if_shared (i3notes
);
2519 i2notes
= copy_rtx_if_shared (i2notes
);
2520 i1notes
= copy_rtx_if_shared (i1notes
);
2521 newpat
= copy_rtx_if_shared (newpat
);
2522 newi2pat
= copy_rtx_if_shared (newi2pat
);
2523 if (undobuf
.other_insn
)
2524 reset_used_flags (PATTERN (undobuf
.other_insn
));
2526 INSN_CODE (i3
) = insn_code_number
;
2527 PATTERN (i3
) = newpat
;
2529 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2531 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2533 reset_used_flags (call_usage
);
2534 call_usage
= copy_rtx (call_usage
);
2537 replace_rtx (call_usage
, i2dest
, i2src
);
2540 replace_rtx (call_usage
, i1dest
, i1src
);
2542 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2545 if (undobuf
.other_insn
)
2546 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2548 /* We had one special case above where I2 had more than one set and
2549 we replaced a destination of one of those sets with the destination
2550 of I3. In that case, we have to update LOG_LINKS of insns later
2551 in this basic block. Note that this (expensive) case is rare.
2553 Also, in this case, we must pretend that all REG_NOTEs for I2
2554 actually came from I3, so that REG_UNUSED notes from I2 will be
2555 properly handled. */
2557 if (i3_subst_into_i2
)
2559 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2560 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2561 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2562 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2563 && ! find_reg_note (i2
, REG_UNUSED
,
2564 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2565 for (temp
= NEXT_INSN (i2
);
2566 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2567 || BB_HEAD (this_basic_block
) != temp
);
2568 temp
= NEXT_INSN (temp
))
2569 if (temp
!= i3
&& INSN_P (temp
))
2570 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2571 if (XEXP (link
, 0) == i2
)
2572 XEXP (link
, 0) = i3
;
2577 while (XEXP (link
, 1))
2578 link
= XEXP (link
, 1);
2579 XEXP (link
, 1) = i2notes
;
2593 INSN_CODE (i2
) = i2_code_number
;
2594 PATTERN (i2
) = newi2pat
;
2598 PUT_CODE (i2
, NOTE
);
2599 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2600 NOTE_SOURCE_FILE (i2
) = 0;
2607 PUT_CODE (i1
, NOTE
);
2608 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2609 NOTE_SOURCE_FILE (i1
) = 0;
2612 /* Get death notes for everything that is now used in either I3 or
2613 I2 and used to die in a previous insn. If we built two new
2614 patterns, move from I1 to I2 then I2 to I3 so that we get the
2615 proper movement on registers that I2 modifies. */
2619 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2620 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2623 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2626 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2628 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2630 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2632 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2634 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2636 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2637 know these are REG_UNUSED and want them to go to the desired insn,
2638 so we always pass it as i3. We have not counted the notes in
2639 reg_n_deaths yet, so we need to do so now. */
2641 if (newi2pat
&& new_i2_notes
)
2643 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2644 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2645 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2647 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2652 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2653 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2654 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2656 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2659 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2660 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2661 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2662 in that case, it might delete I2. Similarly for I2 and I1.
2663 Show an additional death due to the REG_DEAD note we make here. If
2664 we discard it in distribute_notes, we will decrement it again. */
2668 if (GET_CODE (i3dest_killed
) == REG
)
2669 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2671 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2674 NULL_RTX
, i2
, NULL_RTX
);
2676 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2678 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2681 if (i2dest_in_i2src
)
2683 if (GET_CODE (i2dest
) == REG
)
2684 REG_N_DEATHS (REGNO (i2dest
))++;
2686 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2687 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2688 NULL_RTX
, i2
, NULL_RTX
);
2690 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2691 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2694 if (i1dest_in_i1src
)
2696 if (GET_CODE (i1dest
) == REG
)
2697 REG_N_DEATHS (REGNO (i1dest
))++;
2699 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2700 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2701 NULL_RTX
, i2
, NULL_RTX
);
2703 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2704 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2707 distribute_links (i3links
);
2708 distribute_links (i2links
);
2709 distribute_links (i1links
);
2711 if (GET_CODE (i2dest
) == REG
)
2714 rtx i2_insn
= 0, i2_val
= 0, set
;
2716 /* The insn that used to set this register doesn't exist, and
2717 this life of the register may not exist either. See if one of
2718 I3's links points to an insn that sets I2DEST. If it does,
2719 that is now the last known value for I2DEST. If we don't update
2720 this and I2 set the register to a value that depended on its old
2721 contents, we will get confused. If this insn is used, thing
2722 will be set correctly in combine_instructions. */
2724 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2725 if ((set
= single_set (XEXP (link
, 0))) != 0
2726 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2727 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2729 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2731 /* If the reg formerly set in I2 died only once and that was in I3,
2732 zero its use count so it won't make `reload' do any work. */
2734 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2735 && ! i2dest_in_i2src
)
2737 regno
= REGNO (i2dest
);
2738 REG_N_SETS (regno
)--;
2742 if (i1
&& GET_CODE (i1dest
) == REG
)
2745 rtx i1_insn
= 0, i1_val
= 0, set
;
2747 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2748 if ((set
= single_set (XEXP (link
, 0))) != 0
2749 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2750 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2752 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2754 regno
= REGNO (i1dest
);
2755 if (! added_sets_1
&& ! i1dest_in_i1src
)
2756 REG_N_SETS (regno
)--;
2759 /* Update reg_nonzero_bits et al for any changes that may have been made
2760 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2761 important. Because newi2pat can affect nonzero_bits of newpat */
2763 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2764 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2766 /* Set new_direct_jump_p if a new return or simple jump instruction
2769 If I3 is now an unconditional jump, ensure that it has a
2770 BARRIER following it since it may have initially been a
2771 conditional jump. It may also be the last nonnote insn. */
2773 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2775 *new_direct_jump_p
= 1;
2776 mark_jump_label (PATTERN (i3
), i3
, 0);
2778 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2779 || GET_CODE (temp
) != BARRIER
)
2780 emit_barrier_after (i3
);
2783 if (undobuf
.other_insn
!= NULL_RTX
2784 && (returnjump_p (undobuf
.other_insn
)
2785 || any_uncondjump_p (undobuf
.other_insn
)))
2787 *new_direct_jump_p
= 1;
2789 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2790 || GET_CODE (temp
) != BARRIER
)
2791 emit_barrier_after (undobuf
.other_insn
);
2794 /* An NOOP jump does not need barrier, but it does need cleaning up
2796 if (GET_CODE (newpat
) == SET
2797 && SET_SRC (newpat
) == pc_rtx
2798 && SET_DEST (newpat
) == pc_rtx
)
2799 *new_direct_jump_p
= 1;
2802 combine_successes
++;
2805 if (added_links_insn
2806 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2807 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2808 return added_links_insn
;
2810 return newi2pat
? i2
: i3
;
2813 /* Undo all the modifications recorded in undobuf. */
2818 struct undo
*undo
, *next
;
2820 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2824 *undo
->where
.i
= undo
->old_contents
.i
;
2826 *undo
->where
.r
= undo
->old_contents
.r
;
2828 undo
->next
= undobuf
.frees
;
2829 undobuf
.frees
= undo
;
2835 /* We've committed to accepting the changes we made. Move all
2836 of the undos to the free list. */
2841 struct undo
*undo
, *next
;
2843 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2846 undo
->next
= undobuf
.frees
;
2847 undobuf
.frees
= undo
;
2853 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2854 where we have an arithmetic expression and return that point. LOC will
2857 try_combine will call this function to see if an insn can be split into
2861 find_split_point (rtx
*loc
, rtx insn
)
2864 enum rtx_code code
= GET_CODE (x
);
2866 unsigned HOST_WIDE_INT len
= 0;
2867 HOST_WIDE_INT pos
= 0;
2869 rtx inner
= NULL_RTX
;
2871 /* First special-case some codes. */
2875 #ifdef INSN_SCHEDULING
2876 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2878 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2881 return find_split_point (&SUBREG_REG (x
), insn
);
2885 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2886 using LO_SUM and HIGH. */
2887 if (GET_CODE (XEXP (x
, 0)) == CONST
2888 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2891 gen_rtx_LO_SUM (Pmode
,
2892 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2894 return &XEXP (XEXP (x
, 0), 0);
2898 /* If we have a PLUS whose second operand is a constant and the
2899 address is not valid, perhaps will can split it up using
2900 the machine-specific way to split large constants. We use
2901 the first pseudo-reg (one of the virtual regs) as a placeholder;
2902 it will not remain in the result. */
2903 if (GET_CODE (XEXP (x
, 0)) == PLUS
2904 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2905 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2907 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2908 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2911 /* This should have produced two insns, each of which sets our
2912 placeholder. If the source of the second is a valid address,
2913 we can make put both sources together and make a split point
2917 && NEXT_INSN (seq
) != NULL_RTX
2918 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2919 && GET_CODE (seq
) == INSN
2920 && GET_CODE (PATTERN (seq
)) == SET
2921 && SET_DEST (PATTERN (seq
)) == reg
2922 && ! reg_mentioned_p (reg
,
2923 SET_SRC (PATTERN (seq
)))
2924 && GET_CODE (NEXT_INSN (seq
)) == INSN
2925 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2926 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2927 && memory_address_p (GET_MODE (x
),
2928 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2930 rtx src1
= SET_SRC (PATTERN (seq
));
2931 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2933 /* Replace the placeholder in SRC2 with SRC1. If we can
2934 find where in SRC2 it was placed, that can become our
2935 split point and we can replace this address with SRC2.
2936 Just try two obvious places. */
2938 src2
= replace_rtx (src2
, reg
, src1
);
2940 if (XEXP (src2
, 0) == src1
)
2941 split
= &XEXP (src2
, 0);
2942 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2943 && XEXP (XEXP (src2
, 0), 0) == src1
)
2944 split
= &XEXP (XEXP (src2
, 0), 0);
2948 SUBST (XEXP (x
, 0), src2
);
2953 /* If that didn't work, perhaps the first operand is complex and
2954 needs to be computed separately, so make a split point there.
2955 This will occur on machines that just support REG + CONST
2956 and have a constant moved through some previous computation. */
2958 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
2959 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2960 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
2961 return &XEXP (XEXP (x
, 0), 0);
2967 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2968 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2969 we need to put the operand into a register. So split at that
2972 if (SET_DEST (x
) == cc0_rtx
2973 && GET_CODE (SET_SRC (x
)) != COMPARE
2974 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2975 && !OBJECT_P (SET_SRC (x
))
2976 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2977 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
2978 return &SET_SRC (x
);
2981 /* See if we can split SET_SRC as it stands. */
2982 split
= find_split_point (&SET_SRC (x
), insn
);
2983 if (split
&& split
!= &SET_SRC (x
))
2986 /* See if we can split SET_DEST as it stands. */
2987 split
= find_split_point (&SET_DEST (x
), insn
);
2988 if (split
&& split
!= &SET_DEST (x
))
2991 /* See if this is a bitfield assignment with everything constant. If
2992 so, this is an IOR of an AND, so split it into that. */
2993 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2994 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2995 <= HOST_BITS_PER_WIDE_INT
)
2996 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2997 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2998 && GET_CODE (SET_SRC (x
)) == CONST_INT
2999 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3000 + INTVAL (XEXP (SET_DEST (x
), 2)))
3001 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3002 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3004 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3005 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3006 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3007 rtx dest
= XEXP (SET_DEST (x
), 0);
3008 enum machine_mode mode
= GET_MODE (dest
);
3009 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3011 if (BITS_BIG_ENDIAN
)
3012 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3016 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3019 gen_binary (IOR
, mode
,
3020 gen_binary (AND
, mode
, dest
,
3021 gen_int_mode (~(mask
<< pos
),
3023 GEN_INT (src
<< pos
)));
3025 SUBST (SET_DEST (x
), dest
);
3027 split
= find_split_point (&SET_SRC (x
), insn
);
3028 if (split
&& split
!= &SET_SRC (x
))
3032 /* Otherwise, see if this is an operation that we can split into two.
3033 If so, try to split that. */
3034 code
= GET_CODE (SET_SRC (x
));
3039 /* If we are AND'ing with a large constant that is only a single
3040 bit and the result is only being used in a context where we
3041 need to know if it is zero or nonzero, replace it with a bit
3042 extraction. This will avoid the large constant, which might
3043 have taken more than one insn to make. If the constant were
3044 not a valid argument to the AND but took only one insn to make,
3045 this is no worse, but if it took more than one insn, it will
3048 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3049 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3050 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3051 && GET_CODE (SET_DEST (x
)) == REG
3052 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3053 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3054 && XEXP (*split
, 0) == SET_DEST (x
)
3055 && XEXP (*split
, 1) == const0_rtx
)
3057 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3058 XEXP (SET_SRC (x
), 0),
3059 pos
, NULL_RTX
, 1, 1, 0, 0);
3060 if (extraction
!= 0)
3062 SUBST (SET_SRC (x
), extraction
);
3063 return find_split_point (loc
, insn
);
3069 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3070 is known to be on, this can be converted into a NEG of a shift. */
3071 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3072 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3073 && 1 <= (pos
= exact_log2
3074 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3075 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3077 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3081 gen_rtx_LSHIFTRT (mode
,
3082 XEXP (SET_SRC (x
), 0),
3085 split
= find_split_point (&SET_SRC (x
), insn
);
3086 if (split
&& split
!= &SET_SRC (x
))
3092 inner
= XEXP (SET_SRC (x
), 0);
3094 /* We can't optimize if either mode is a partial integer
3095 mode as we don't know how many bits are significant
3097 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3098 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3102 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3108 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3109 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3111 inner
= XEXP (SET_SRC (x
), 0);
3112 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3113 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3115 if (BITS_BIG_ENDIAN
)
3116 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3117 unsignedp
= (code
== ZERO_EXTRACT
);
3125 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3127 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3129 /* For unsigned, we have a choice of a shift followed by an
3130 AND or two shifts. Use two shifts for field sizes where the
3131 constant might be too large. We assume here that we can
3132 always at least get 8-bit constants in an AND insn, which is
3133 true for every current RISC. */
3135 if (unsignedp
&& len
<= 8)
3140 (mode
, gen_lowpart (mode
, inner
),
3142 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3144 split
= find_split_point (&SET_SRC (x
), insn
);
3145 if (split
&& split
!= &SET_SRC (x
))
3152 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3153 gen_rtx_ASHIFT (mode
,
3154 gen_lowpart (mode
, inner
),
3155 GEN_INT (GET_MODE_BITSIZE (mode
)
3157 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3159 split
= find_split_point (&SET_SRC (x
), insn
);
3160 if (split
&& split
!= &SET_SRC (x
))
3165 /* See if this is a simple operation with a constant as the second
3166 operand. It might be that this constant is out of range and hence
3167 could be used as a split point. */
3168 if (BINARY_P (SET_SRC (x
))
3169 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3170 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3171 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3172 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3173 return &XEXP (SET_SRC (x
), 1);
3175 /* Finally, see if this is a simple operation with its first operand
3176 not in a register. The operation might require this operand in a
3177 register, so return it as a split point. We can always do this
3178 because if the first operand were another operation, we would have
3179 already found it as a split point. */
3180 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3181 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3182 return &XEXP (SET_SRC (x
), 0);
3188 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3189 it is better to write this as (not (ior A B)) so we can split it.
3190 Similarly for IOR. */
3191 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3194 gen_rtx_NOT (GET_MODE (x
),
3195 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3197 XEXP (XEXP (x
, 0), 0),
3198 XEXP (XEXP (x
, 1), 0))));
3199 return find_split_point (loc
, insn
);
3202 /* Many RISC machines have a large set of logical insns. If the
3203 second operand is a NOT, put it first so we will try to split the
3204 other operand first. */
3205 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3207 rtx tem
= XEXP (x
, 0);
3208 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3209 SUBST (XEXP (x
, 1), tem
);
3217 /* Otherwise, select our actions depending on our rtx class. */
3218 switch (GET_RTX_CLASS (code
))
3220 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3222 split
= find_split_point (&XEXP (x
, 2), insn
);
3225 /* ... fall through ... */
3227 case RTX_COMM_ARITH
:
3229 case RTX_COMM_COMPARE
:
3230 split
= find_split_point (&XEXP (x
, 1), insn
);
3233 /* ... fall through ... */
3235 /* Some machines have (and (shift ...) ...) insns. If X is not
3236 an AND, but XEXP (X, 0) is, use it as our split point. */
3237 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3238 return &XEXP (x
, 0);
3240 split
= find_split_point (&XEXP (x
, 0), insn
);
3246 /* Otherwise, we don't have a split point. */
3251 /* Throughout X, replace FROM with TO, and return the result.
3252 The result is TO if X is FROM;
3253 otherwise the result is X, but its contents may have been modified.
3254 If they were modified, a record was made in undobuf so that
3255 undo_all will (among other things) return X to its original state.
3257 If the number of changes necessary is too much to record to undo,
3258 the excess changes are not made, so the result is invalid.
3259 The changes already made can still be undone.
3260 undobuf.num_undo is incremented for such changes, so by testing that
3261 the caller can tell whether the result is valid.
3263 `n_occurrences' is incremented each time FROM is replaced.
3265 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3267 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3268 by copying if `n_occurrences' is nonzero. */
3271 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3273 enum rtx_code code
= GET_CODE (x
);
3274 enum machine_mode op0_mode
= VOIDmode
;
3279 /* Two expressions are equal if they are identical copies of a shared
3280 RTX or if they are both registers with the same register number
3283 #define COMBINE_RTX_EQUAL_P(X,Y) \
3285 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3286 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3288 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3291 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3294 /* If X and FROM are the same register but different modes, they will
3295 not have been seen as equal above. However, flow.c will make a
3296 LOG_LINKS entry for that case. If we do nothing, we will try to
3297 rerecognize our original insn and, when it succeeds, we will
3298 delete the feeding insn, which is incorrect.
3300 So force this insn not to match in this (rare) case. */
3301 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3302 && REGNO (x
) == REGNO (from
))
3303 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3305 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3306 of which may contain things that can be combined. */
3307 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3310 /* It is possible to have a subexpression appear twice in the insn.
3311 Suppose that FROM is a register that appears within TO.
3312 Then, after that subexpression has been scanned once by `subst',
3313 the second time it is scanned, TO may be found. If we were
3314 to scan TO here, we would find FROM within it and create a
3315 self-referent rtl structure which is completely wrong. */
3316 if (COMBINE_RTX_EQUAL_P (x
, to
))
3319 /* Parallel asm_operands need special attention because all of the
3320 inputs are shared across the arms. Furthermore, unsharing the
3321 rtl results in recognition failures. Failure to handle this case
3322 specially can result in circular rtl.
3324 Solve this by doing a normal pass across the first entry of the
3325 parallel, and only processing the SET_DESTs of the subsequent
3328 if (code
== PARALLEL
3329 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3330 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3332 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3334 /* If this substitution failed, this whole thing fails. */
3335 if (GET_CODE (new) == CLOBBER
3336 && XEXP (new, 0) == const0_rtx
)
3339 SUBST (XVECEXP (x
, 0, 0), new);
3341 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3343 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3345 if (GET_CODE (dest
) != REG
3346 && GET_CODE (dest
) != CC0
3347 && GET_CODE (dest
) != PC
)
3349 new = subst (dest
, from
, to
, 0, unique_copy
);
3351 /* If this substitution failed, this whole thing fails. */
3352 if (GET_CODE (new) == CLOBBER
3353 && XEXP (new, 0) == const0_rtx
)
3356 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3362 len
= GET_RTX_LENGTH (code
);
3363 fmt
= GET_RTX_FORMAT (code
);
3365 /* We don't need to process a SET_DEST that is a register, CC0,
3366 or PC, so set up to skip this common case. All other cases
3367 where we want to suppress replacing something inside a
3368 SET_SRC are handled via the IN_DEST operand. */
3370 && (GET_CODE (SET_DEST (x
)) == REG
3371 || GET_CODE (SET_DEST (x
)) == CC0
3372 || GET_CODE (SET_DEST (x
)) == PC
))
3375 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3378 op0_mode
= GET_MODE (XEXP (x
, 0));
3380 for (i
= 0; i
< len
; i
++)
3385 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3387 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3389 new = (unique_copy
&& n_occurrences
3390 ? copy_rtx (to
) : to
);
3395 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3398 /* If this substitution failed, this whole thing
3400 if (GET_CODE (new) == CLOBBER
3401 && XEXP (new, 0) == const0_rtx
)
3405 SUBST (XVECEXP (x
, i
, j
), new);
3408 else if (fmt
[i
] == 'e')
3410 /* If this is a register being set, ignore it. */
3413 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3414 || code
== ZERO_EXTRACT
)
3416 && GET_CODE (new) == REG
)
3419 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3421 /* In general, don't install a subreg involving two
3422 modes not tieable. It can worsen register
3423 allocation, and can even make invalid reload
3424 insns, since the reg inside may need to be copied
3425 from in the outside mode, and that may be invalid
3426 if it is an fp reg copied in integer mode.
3428 We allow two exceptions to this: It is valid if
3429 it is inside another SUBREG and the mode of that
3430 SUBREG and the mode of the inside of TO is
3431 tieable and it is valid if X is a SET that copies
3434 if (GET_CODE (to
) == SUBREG
3435 && ! MODES_TIEABLE_P (GET_MODE (to
),
3436 GET_MODE (SUBREG_REG (to
)))
3437 && ! (code
== SUBREG
3438 && MODES_TIEABLE_P (GET_MODE (x
),
3439 GET_MODE (SUBREG_REG (to
))))
3441 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3444 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3446 #ifdef CANNOT_CHANGE_MODE_CLASS
3448 && GET_CODE (to
) == REG
3449 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3450 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3453 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3456 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3460 /* If we are in a SET_DEST, suppress most cases unless we
3461 have gone inside a MEM, in which case we want to
3462 simplify the address. We assume here that things that
3463 are actually part of the destination have their inner
3464 parts in the first expression. This is true for SUBREG,
3465 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3466 things aside from REG and MEM that should appear in a
3468 new = subst (XEXP (x
, i
), from
, to
,
3470 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3471 || code
== ZERO_EXTRACT
))
3473 && i
== 0), unique_copy
);
3475 /* If we found that we will have to reject this combination,
3476 indicate that by returning the CLOBBER ourselves, rather than
3477 an expression containing it. This will speed things up as
3478 well as prevent accidents where two CLOBBERs are considered
3479 to be equal, thus producing an incorrect simplification. */
3481 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3484 if (GET_CODE (x
) == SUBREG
3485 && (GET_CODE (new) == CONST_INT
3486 || GET_CODE (new) == CONST_DOUBLE
))
3488 enum machine_mode mode
= GET_MODE (x
);
3490 x
= simplify_subreg (GET_MODE (x
), new,
3491 GET_MODE (SUBREG_REG (x
)),
3494 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3496 else if (GET_CODE (new) == CONST_INT
3497 && GET_CODE (x
) == ZERO_EXTEND
)
3499 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3500 new, GET_MODE (XEXP (x
, 0)));
3505 SUBST (XEXP (x
, i
), new);
3510 /* Try to simplify X. If the simplification changed the code, it is likely
3511 that further simplification will help, so loop, but limit the number
3512 of repetitions that will be performed. */
3514 for (i
= 0; i
< 4; i
++)
3516 /* If X is sufficiently simple, don't bother trying to do anything
3518 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3519 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3521 if (GET_CODE (x
) == code
)
3524 code
= GET_CODE (x
);
3526 /* We no longer know the original mode of operand 0 since we
3527 have changed the form of X) */
3528 op0_mode
= VOIDmode
;
3534 /* Simplify X, a piece of RTL. We just operate on the expression at the
3535 outer level; call `subst' to simplify recursively. Return the new
3538 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3539 will be the iteration even if an expression with a code different from
3540 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3543 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3546 enum rtx_code code
= GET_CODE (x
);
3547 enum machine_mode mode
= GET_MODE (x
);
3552 /* If this is a commutative operation, put a constant last and a complex
3553 expression first. We don't need to do this for comparisons here. */
3554 if (COMMUTATIVE_ARITH_P (x
)
3555 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3558 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3559 SUBST (XEXP (x
, 1), temp
);
3562 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3563 sign extension of a PLUS with a constant, reverse the order of the sign
3564 extension and the addition. Note that this not the same as the original
3565 code, but overflow is undefined for signed values. Also note that the
3566 PLUS will have been partially moved "inside" the sign-extension, so that
3567 the first operand of X will really look like:
3568 (ashiftrt (plus (ashift A C4) C5) C4).
3570 (plus (ashiftrt (ashift A C4) C2) C4)
3571 and replace the first operand of X with that expression. Later parts
3572 of this function may simplify the expression further.
3574 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3575 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3576 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3578 We do this to simplify address expressions. */
3580 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3581 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3582 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3583 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3584 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3585 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3586 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3587 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3588 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3589 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3590 XEXP (XEXP (x
, 0), 1))) != 0)
3593 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3594 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3595 INTVAL (XEXP (XEXP (x
, 0), 1)));
3597 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3598 INTVAL (XEXP (XEXP (x
, 0), 1)));
3600 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3603 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3604 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3605 things. Check for cases where both arms are testing the same
3608 Don't do anything if all operands are very simple. */
3611 && ((!OBJECT_P (XEXP (x
, 0))
3612 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3613 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3614 || (!OBJECT_P (XEXP (x
, 1))
3615 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3616 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3618 && (!OBJECT_P (XEXP (x
, 0))
3619 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3620 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3622 rtx cond
, true_rtx
, false_rtx
;
3624 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3626 /* If everything is a comparison, what we have is highly unlikely
3627 to be simpler, so don't use it. */
3628 && ! (COMPARISON_P (x
)
3629 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3631 rtx cop1
= const0_rtx
;
3632 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3634 if (cond_code
== NE
&& COMPARISON_P (cond
))
3637 /* Simplify the alternative arms; this may collapse the true and
3638 false arms to store-flag values. Be careful to use copy_rtx
3639 here since true_rtx or false_rtx might share RTL with x as a
3640 result of the if_then_else_cond call above. */
3641 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3642 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3644 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3645 is unlikely to be simpler. */
3646 if (general_operand (true_rtx
, VOIDmode
)
3647 && general_operand (false_rtx
, VOIDmode
))
3649 enum rtx_code reversed
;
3651 /* Restarting if we generate a store-flag expression will cause
3652 us to loop. Just drop through in this case. */
3654 /* If the result values are STORE_FLAG_VALUE and zero, we can
3655 just make the comparison operation. */
3656 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3657 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3658 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3659 && ((reversed
= reversed_comparison_code_parts
3660 (cond_code
, cond
, cop1
, NULL
))
3662 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3664 /* Likewise, we can make the negate of a comparison operation
3665 if the result values are - STORE_FLAG_VALUE and zero. */
3666 else if (GET_CODE (true_rtx
) == CONST_INT
3667 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3668 && false_rtx
== const0_rtx
)
3669 x
= simplify_gen_unary (NEG
, mode
,
3670 gen_binary (cond_code
, mode
, cond
,
3673 else if (GET_CODE (false_rtx
) == CONST_INT
3674 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3675 && true_rtx
== const0_rtx
3676 && ((reversed
= reversed_comparison_code_parts
3677 (cond_code
, cond
, cop1
, NULL
))
3679 x
= simplify_gen_unary (NEG
, mode
,
3680 gen_binary (reversed
, mode
,
3684 return gen_rtx_IF_THEN_ELSE (mode
,
3685 gen_binary (cond_code
, VOIDmode
,
3687 true_rtx
, false_rtx
);
3689 code
= GET_CODE (x
);
3690 op0_mode
= VOIDmode
;
3695 /* Try to fold this expression in case we have constants that weren't
3698 switch (GET_RTX_CLASS (code
))
3701 if (op0_mode
== VOIDmode
)
3702 op0_mode
= GET_MODE (XEXP (x
, 0));
3703 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3706 case RTX_COMM_COMPARE
:
3708 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3709 if (cmp_mode
== VOIDmode
)
3711 cmp_mode
= GET_MODE (XEXP (x
, 1));
3712 if (cmp_mode
== VOIDmode
)
3713 cmp_mode
= op0_mode
;
3715 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3716 XEXP (x
, 0), XEXP (x
, 1));
3719 case RTX_COMM_ARITH
:
3721 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3723 case RTX_BITFIELD_OPS
:
3725 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3726 XEXP (x
, 1), XEXP (x
, 2));
3735 code
= GET_CODE (temp
);
3736 op0_mode
= VOIDmode
;
3737 mode
= GET_MODE (temp
);
3740 /* First see if we can apply the inverse distributive law. */
3741 if (code
== PLUS
|| code
== MINUS
3742 || code
== AND
|| code
== IOR
|| code
== XOR
)
3744 x
= apply_distributive_law (x
);
3745 code
= GET_CODE (x
);
3746 op0_mode
= VOIDmode
;
3749 /* If CODE is an associative operation not otherwise handled, see if we
3750 can associate some operands. This can win if they are constants or
3751 if they are logically related (i.e. (a & b) & a). */
3752 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3753 || code
== AND
|| code
== IOR
|| code
== XOR
3754 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3755 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3756 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3758 if (GET_CODE (XEXP (x
, 0)) == code
)
3760 rtx other
= XEXP (XEXP (x
, 0), 0);
3761 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3762 rtx inner_op1
= XEXP (x
, 1);
3765 /* Make sure we pass the constant operand if any as the second
3766 one if this is a commutative operation. */
3767 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3769 rtx tem
= inner_op0
;
3770 inner_op0
= inner_op1
;
3773 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3774 : code
== DIV
? MULT
3776 mode
, inner_op0
, inner_op1
);
3778 /* For commutative operations, try the other pair if that one
3780 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3782 other
= XEXP (XEXP (x
, 0), 1);
3783 inner
= simplify_binary_operation (code
, mode
,
3784 XEXP (XEXP (x
, 0), 0),
3789 return gen_binary (code
, mode
, other
, inner
);
3793 /* A little bit of algebraic simplification here. */
3797 /* Ensure that our address has any ASHIFTs converted to MULT in case
3798 address-recognizing predicates are called later. */
3799 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3800 SUBST (XEXP (x
, 0), temp
);
3804 if (op0_mode
== VOIDmode
)
3805 op0_mode
= GET_MODE (SUBREG_REG (x
));
3807 /* See if this can be moved to simplify_subreg. */
3808 if (CONSTANT_P (SUBREG_REG (x
))
3809 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3810 /* Don't call gen_lowpart if the inner mode
3811 is VOIDmode and we cannot simplify it, as SUBREG without
3812 inner mode is invalid. */
3813 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3814 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3815 return gen_lowpart (mode
, SUBREG_REG (x
));
3817 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3821 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3827 /* Don't change the mode of the MEM if that would change the meaning
3829 if (GET_CODE (SUBREG_REG (x
)) == MEM
3830 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3831 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3832 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3834 /* Note that we cannot do any narrowing for non-constants since
3835 we might have been counting on using the fact that some bits were
3836 zero. We now do this in the SET. */
3841 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3842 && subreg_lowpart_p (XEXP (x
, 0))
3843 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3844 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3845 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3846 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3848 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3850 x
= gen_rtx_ROTATE (inner_mode
,
3851 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3853 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3854 return gen_lowpart (mode
, x
);
3857 /* Apply De Morgan's laws to reduce number of patterns for machines
3858 with negating logical insns (and-not, nand, etc.). If result has
3859 only one NOT, put it first, since that is how the patterns are
3862 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3864 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3865 enum machine_mode op_mode
;
3867 op_mode
= GET_MODE (in1
);
3868 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3870 op_mode
= GET_MODE (in2
);
3871 if (op_mode
== VOIDmode
)
3873 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3875 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3878 in2
= in1
; in1
= tem
;
3881 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3887 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3888 if (GET_CODE (XEXP (x
, 0)) == XOR
3889 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3890 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3891 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3893 temp
= expand_compound_operation (XEXP (x
, 0));
3895 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3896 replaced by (lshiftrt X C). This will convert
3897 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3899 if (GET_CODE (temp
) == ASHIFTRT
3900 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3901 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3902 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3903 INTVAL (XEXP (temp
, 1)));
3905 /* If X has only a single bit that might be nonzero, say, bit I, convert
3906 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3907 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3908 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3909 or a SUBREG of one since we'd be making the expression more
3910 complex if it was just a register. */
3912 if (GET_CODE (temp
) != REG
3913 && ! (GET_CODE (temp
) == SUBREG
3914 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3915 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3917 rtx temp1
= simplify_shift_const
3918 (NULL_RTX
, ASHIFTRT
, mode
,
3919 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3920 GET_MODE_BITSIZE (mode
) - 1 - i
),
3921 GET_MODE_BITSIZE (mode
) - 1 - i
);
3923 /* If all we did was surround TEMP with the two shifts, we
3924 haven't improved anything, so don't use it. Otherwise,
3925 we are better off with TEMP1. */
3926 if (GET_CODE (temp1
) != ASHIFTRT
3927 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3928 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3934 /* We can't handle truncation to a partial integer mode here
3935 because we don't know the real bitsize of the partial
3937 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3940 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3941 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3942 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3944 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3945 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3947 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3948 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3949 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3950 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3951 return XEXP (XEXP (x
, 0), 0);
3953 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3954 (OP:SI foo:SI) if OP is NEG or ABS. */
3955 if ((GET_CODE (XEXP (x
, 0)) == ABS
3956 || GET_CODE (XEXP (x
, 0)) == NEG
)
3957 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3958 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3959 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3960 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3961 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3963 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3965 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3966 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3967 && subreg_lowpart_p (XEXP (x
, 0)))
3968 return SUBREG_REG (XEXP (x
, 0));
3970 /* If we know that the value is already truncated, we can
3971 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3972 is nonzero for the corresponding modes. But don't do this
3973 for an (LSHIFTRT (MULT ...)) since this will cause problems
3974 with the umulXi3_highpart patterns. */
3975 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3976 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3977 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3978 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3979 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3980 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3981 return gen_lowpart (mode
, XEXP (x
, 0));
3983 /* A truncate of a comparison can be replaced with a subreg if
3984 STORE_FLAG_VALUE permits. This is like the previous test,
3985 but it works even if the comparison is done in a mode larger
3986 than HOST_BITS_PER_WIDE_INT. */
3987 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3988 && COMPARISON_P (XEXP (x
, 0))
3989 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
3990 return gen_lowpart (mode
, XEXP (x
, 0));
3992 /* Similarly, a truncate of a register whose value is a
3993 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3995 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3996 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
3997 && (temp
= get_last_value (XEXP (x
, 0)))
3998 && COMPARISON_P (temp
))
3999 return gen_lowpart (mode
, XEXP (x
, 0));
4003 case FLOAT_TRUNCATE
:
4004 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4005 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4006 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4007 return XEXP (XEXP (x
, 0), 0);
4009 /* (float_truncate:SF (float_truncate:DF foo:XF))
4010 = (float_truncate:SF foo:XF).
4011 This may eliminate double rounding, so it is unsafe.
4013 (float_truncate:SF (float_extend:XF foo:DF))
4014 = (float_truncate:SF foo:DF).
4016 (float_truncate:DF (float_extend:XF foo:SF))
4017 = (float_extend:SF foo:DF). */
4018 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4019 && flag_unsafe_math_optimizations
)
4020 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4021 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4023 > GET_MODE_SIZE (mode
)
4024 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4026 XEXP (XEXP (x
, 0), 0), mode
);
4028 /* (float_truncate (float x)) is (float x) */
4029 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4030 && (flag_unsafe_math_optimizations
4031 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4032 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4033 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4034 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4035 return simplify_gen_unary (FLOAT
, mode
,
4036 XEXP (XEXP (x
, 0), 0),
4037 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4039 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4040 (OP:SF foo:SF) if OP is NEG or ABS. */
4041 if ((GET_CODE (XEXP (x
, 0)) == ABS
4042 || GET_CODE (XEXP (x
, 0)) == NEG
)
4043 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4044 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4045 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4046 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4048 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4049 is (float_truncate:SF x). */
4050 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4051 && subreg_lowpart_p (XEXP (x
, 0))
4052 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4053 return SUBREG_REG (XEXP (x
, 0));
4056 /* (float_extend (float_extend x)) is (float_extend x)
4058 (float_extend (float x)) is (float x) assuming that double
4059 rounding can't happen.
4061 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4062 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4063 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4064 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4065 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4066 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4067 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4068 XEXP (XEXP (x
, 0), 0),
4069 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4074 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4075 using cc0, in which case we want to leave it as a COMPARE
4076 so we can distinguish it from a register-register-copy. */
4077 if (XEXP (x
, 1) == const0_rtx
)
4080 /* x - 0 is the same as x unless x's mode has signed zeros and
4081 allows rounding towards -infinity. Under those conditions,
4083 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4084 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4085 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4091 /* (const (const X)) can become (const X). Do it this way rather than
4092 returning the inner CONST since CONST can be shared with a
4094 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4095 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4100 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4101 can add in an offset. find_split_point will split this address up
4102 again if it doesn't match. */
4103 if (GET_CODE (XEXP (x
, 0)) == HIGH
4104 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4110 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4112 if (GET_CODE (XEXP (x
, 0)) == MULT
4113 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4117 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4118 in2
= XEXP (XEXP (x
, 0), 1);
4119 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4120 gen_binary (MULT
, mode
, in1
, in2
));
4123 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4124 outermost. That's because that's the way indexed addresses are
4125 supposed to appear. This code used to check many more cases, but
4126 they are now checked elsewhere. */
4127 if (GET_CODE (XEXP (x
, 0)) == PLUS
4128 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4129 return gen_binary (PLUS
, mode
,
4130 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4132 XEXP (XEXP (x
, 0), 1));
4134 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4135 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4136 bit-field and can be replaced by either a sign_extend or a
4137 sign_extract. The `and' may be a zero_extend and the two
4138 <c>, -<c> constants may be reversed. */
4139 if (GET_CODE (XEXP (x
, 0)) == XOR
4140 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4141 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4142 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4143 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4144 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4145 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4146 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4147 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4148 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4149 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4150 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4151 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4152 == (unsigned int) i
+ 1))))
4153 return simplify_shift_const
4154 (NULL_RTX
, ASHIFTRT
, mode
,
4155 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4156 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4157 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4158 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4160 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4161 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4162 is 1. This produces better code than the alternative immediately
4164 if (COMPARISON_P (XEXP (x
, 0))
4165 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4166 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4167 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4168 XEXP (XEXP (x
, 0), 0),
4169 XEXP (XEXP (x
, 0), 1))))
4171 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4173 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4174 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4175 the bitsize of the mode - 1. This allows simplification of
4176 "a = (b & 8) == 0;" */
4177 if (XEXP (x
, 1) == constm1_rtx
4178 && GET_CODE (XEXP (x
, 0)) != REG
4179 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4180 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4181 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4182 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4183 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4184 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4185 GET_MODE_BITSIZE (mode
) - 1),
4186 GET_MODE_BITSIZE (mode
) - 1);
4188 /* If we are adding two things that have no bits in common, convert
4189 the addition into an IOR. This will often be further simplified,
4190 for example in cases like ((a & 1) + (a & 2)), which can
4193 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4194 && (nonzero_bits (XEXP (x
, 0), mode
)
4195 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4197 /* Try to simplify the expression further. */
4198 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4199 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4201 /* If we could, great. If not, do not go ahead with the IOR
4202 replacement, since PLUS appears in many special purpose
4203 address arithmetic instructions. */
4204 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4210 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4211 by reversing the comparison code if valid. */
4212 if (STORE_FLAG_VALUE
== 1
4213 && XEXP (x
, 0) == const1_rtx
4214 && COMPARISON_P (XEXP (x
, 1))
4215 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4216 XEXP (XEXP (x
, 1), 0),
4217 XEXP (XEXP (x
, 1), 1))))
4220 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4221 (and <foo> (const_int pow2-1)) */
4222 if (GET_CODE (XEXP (x
, 1)) == AND
4223 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4224 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4225 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4226 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4227 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4229 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4231 if (GET_CODE (XEXP (x
, 1)) == MULT
4232 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4236 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4237 in2
= XEXP (XEXP (x
, 1), 1);
4238 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4242 /* Canonicalize (minus (neg A) (mult B C)) to
4243 (minus (mult (neg B) C) A). */
4244 if (GET_CODE (XEXP (x
, 1)) == MULT
4245 && GET_CODE (XEXP (x
, 0)) == NEG
)
4249 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4250 in2
= XEXP (XEXP (x
, 1), 1);
4251 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4252 XEXP (XEXP (x
, 0), 0));
4255 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4257 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4258 return gen_binary (MINUS
, mode
,
4259 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4260 XEXP (XEXP (x
, 1), 0)),
4261 XEXP (XEXP (x
, 1), 1));
4265 /* If we have (mult (plus A B) C), apply the distributive law and then
4266 the inverse distributive law to see if things simplify. This
4267 occurs mostly in addresses, often when unrolling loops. */
4269 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4271 x
= apply_distributive_law
4272 (gen_binary (PLUS
, mode
,
4273 gen_binary (MULT
, mode
,
4274 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4275 gen_binary (MULT
, mode
,
4276 XEXP (XEXP (x
, 0), 1),
4277 copy_rtx (XEXP (x
, 1)))));
4279 if (GET_CODE (x
) != MULT
)
4282 /* Try simplify a*(b/c) as (a*b)/c. */
4283 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4284 && GET_CODE (XEXP (x
, 0)) == DIV
)
4286 rtx tem
= simplify_binary_operation (MULT
, mode
,
4287 XEXP (XEXP (x
, 0), 0),
4290 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4295 /* If this is a divide by a power of two, treat it as a shift if
4296 its first operand is a shift. */
4297 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4298 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4299 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4300 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4301 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4302 || GET_CODE (XEXP (x
, 0)) == ROTATE
4303 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4304 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4308 case GT
: case GTU
: case GE
: case GEU
:
4309 case LT
: case LTU
: case LE
: case LEU
:
4310 case UNEQ
: case LTGT
:
4311 case UNGT
: case UNGE
:
4312 case UNLT
: case UNLE
:
4313 case UNORDERED
: case ORDERED
:
4314 /* If the first operand is a condition code, we can't do anything
4316 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4317 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4318 && ! CC0_P (XEXP (x
, 0))))
4320 rtx op0
= XEXP (x
, 0);
4321 rtx op1
= XEXP (x
, 1);
4322 enum rtx_code new_code
;
4324 if (GET_CODE (op0
) == COMPARE
)
4325 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4327 /* Simplify our comparison, if possible. */
4328 new_code
= simplify_comparison (code
, &op0
, &op1
);
4330 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4331 if only the low-order bit is possibly nonzero in X (such as when
4332 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4333 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4334 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4337 Remove any ZERO_EXTRACT we made when thinking this was a
4338 comparison. It may now be simpler to use, e.g., an AND. If a
4339 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4340 the call to make_compound_operation in the SET case. */
4342 if (STORE_FLAG_VALUE
== 1
4343 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4344 && op1
== const0_rtx
4345 && mode
== GET_MODE (op0
)
4346 && nonzero_bits (op0
, mode
) == 1)
4347 return gen_lowpart (mode
,
4348 expand_compound_operation (op0
));
4350 else if (STORE_FLAG_VALUE
== 1
4351 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4352 && op1
== const0_rtx
4353 && mode
== GET_MODE (op0
)
4354 && (num_sign_bit_copies (op0
, mode
)
4355 == GET_MODE_BITSIZE (mode
)))
4357 op0
= expand_compound_operation (op0
);
4358 return simplify_gen_unary (NEG
, mode
,
4359 gen_lowpart (mode
, op0
),
4363 else if (STORE_FLAG_VALUE
== 1
4364 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4365 && op1
== const0_rtx
4366 && mode
== GET_MODE (op0
)
4367 && nonzero_bits (op0
, mode
) == 1)
4369 op0
= expand_compound_operation (op0
);
4370 return gen_binary (XOR
, mode
,
4371 gen_lowpart (mode
, op0
),
4375 else if (STORE_FLAG_VALUE
== 1
4376 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4377 && op1
== const0_rtx
4378 && mode
== GET_MODE (op0
)
4379 && (num_sign_bit_copies (op0
, mode
)
4380 == GET_MODE_BITSIZE (mode
)))
4382 op0
= expand_compound_operation (op0
);
4383 return plus_constant (gen_lowpart (mode
, op0
), 1);
4386 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4388 if (STORE_FLAG_VALUE
== -1
4389 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4390 && op1
== const0_rtx
4391 && (num_sign_bit_copies (op0
, mode
)
4392 == GET_MODE_BITSIZE (mode
)))
4393 return gen_lowpart (mode
,
4394 expand_compound_operation (op0
));
4396 else if (STORE_FLAG_VALUE
== -1
4397 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4398 && op1
== const0_rtx
4399 && mode
== GET_MODE (op0
)
4400 && nonzero_bits (op0
, mode
) == 1)
4402 op0
= expand_compound_operation (op0
);
4403 return simplify_gen_unary (NEG
, mode
,
4404 gen_lowpart (mode
, op0
),
4408 else if (STORE_FLAG_VALUE
== -1
4409 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4410 && op1
== const0_rtx
4411 && mode
== GET_MODE (op0
)
4412 && (num_sign_bit_copies (op0
, mode
)
4413 == GET_MODE_BITSIZE (mode
)))
4415 op0
= expand_compound_operation (op0
);
4416 return simplify_gen_unary (NOT
, mode
,
4417 gen_lowpart (mode
, op0
),
4421 /* If X is 0/1, (eq X 0) is X-1. */
4422 else if (STORE_FLAG_VALUE
== -1
4423 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4424 && op1
== const0_rtx
4425 && mode
== GET_MODE (op0
)
4426 && nonzero_bits (op0
, mode
) == 1)
4428 op0
= expand_compound_operation (op0
);
4429 return plus_constant (gen_lowpart (mode
, op0
), -1);
4432 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4433 one bit that might be nonzero, we can convert (ne x 0) to
4434 (ashift x c) where C puts the bit in the sign bit. Remove any
4435 AND with STORE_FLAG_VALUE when we are done, since we are only
4436 going to test the sign bit. */
4437 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4438 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4439 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4440 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4441 && op1
== const0_rtx
4442 && mode
== GET_MODE (op0
)
4443 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4445 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4446 expand_compound_operation (op0
),
4447 GET_MODE_BITSIZE (mode
) - 1 - i
);
4448 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4454 /* If the code changed, return a whole new comparison. */
4455 if (new_code
!= code
)
4456 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4458 /* Otherwise, keep this operation, but maybe change its operands.
4459 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4460 SUBST (XEXP (x
, 0), op0
);
4461 SUBST (XEXP (x
, 1), op1
);
4466 return simplify_if_then_else (x
);
4472 /* If we are processing SET_DEST, we are done. */
4476 return expand_compound_operation (x
);
4479 return simplify_set (x
);
4484 return simplify_logical (x
, last
);
4487 /* (abs (neg <foo>)) -> (abs <foo>) */
4488 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4489 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4491 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4493 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4496 /* If operand is something known to be positive, ignore the ABS. */
4497 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4498 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4499 <= HOST_BITS_PER_WIDE_INT
)
4500 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4501 & ((HOST_WIDE_INT
) 1
4502 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4506 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4507 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4508 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4513 /* (ffs (*_extend <X>)) = (ffs <X>) */
4514 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4515 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4516 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4521 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4522 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4523 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4527 /* (float (sign_extend <X>)) = (float <X>). */
4528 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4529 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4537 /* If this is a shift by a constant amount, simplify it. */
4538 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4539 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4540 INTVAL (XEXP (x
, 1)));
4542 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4544 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4546 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4553 rtx op0
= XEXP (x
, 0);
4554 rtx op1
= XEXP (x
, 1);
4557 if (GET_CODE (op1
) != PARALLEL
)
4559 len
= XVECLEN (op1
, 0);
4561 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4562 && GET_CODE (op0
) == VEC_CONCAT
)
4564 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4566 /* Try to find the element in the VEC_CONCAT. */
4569 if (GET_MODE (op0
) == GET_MODE (x
))
4571 if (GET_CODE (op0
) == VEC_CONCAT
)
4573 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4574 if (op0_size
< offset
)
4575 op0
= XEXP (op0
, 0);
4579 op0
= XEXP (op0
, 1);
4597 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4600 simplify_if_then_else (rtx x
)
4602 enum machine_mode mode
= GET_MODE (x
);
4603 rtx cond
= XEXP (x
, 0);
4604 rtx true_rtx
= XEXP (x
, 1);
4605 rtx false_rtx
= XEXP (x
, 2);
4606 enum rtx_code true_code
= GET_CODE (cond
);
4607 int comparison_p
= COMPARISON_P (cond
);
4610 enum rtx_code false_code
;
4613 /* Simplify storing of the truth value. */
4614 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4615 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4617 /* Also when the truth value has to be reversed. */
4619 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4620 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4624 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4625 in it is being compared against certain values. Get the true and false
4626 comparisons and see if that says anything about the value of each arm. */
4629 && ((false_code
= combine_reversed_comparison_code (cond
))
4631 && GET_CODE (XEXP (cond
, 0)) == REG
)
4634 rtx from
= XEXP (cond
, 0);
4635 rtx true_val
= XEXP (cond
, 1);
4636 rtx false_val
= true_val
;
4639 /* If FALSE_CODE is EQ, swap the codes and arms. */
4641 if (false_code
== EQ
)
4643 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4644 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4647 /* If we are comparing against zero and the expression being tested has
4648 only a single bit that might be nonzero, that is its value when it is
4649 not equal to zero. Similarly if it is known to be -1 or 0. */
4651 if (true_code
== EQ
&& true_val
== const0_rtx
4652 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4653 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4654 else if (true_code
== EQ
&& true_val
== const0_rtx
4655 && (num_sign_bit_copies (from
, GET_MODE (from
))
4656 == GET_MODE_BITSIZE (GET_MODE (from
))))
4657 false_code
= EQ
, false_val
= constm1_rtx
;
4659 /* Now simplify an arm if we know the value of the register in the
4660 branch and it is used in the arm. Be careful due to the potential
4661 of locally-shared RTL. */
4663 if (reg_mentioned_p (from
, true_rtx
))
4664 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4666 pc_rtx
, pc_rtx
, 0, 0);
4667 if (reg_mentioned_p (from
, false_rtx
))
4668 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4670 pc_rtx
, pc_rtx
, 0, 0);
4672 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4673 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4675 true_rtx
= XEXP (x
, 1);
4676 false_rtx
= XEXP (x
, 2);
4677 true_code
= GET_CODE (cond
);
4680 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4681 reversed, do so to avoid needing two sets of patterns for
4682 subtract-and-branch insns. Similarly if we have a constant in the true
4683 arm, the false arm is the same as the first operand of the comparison, or
4684 the false arm is more complicated than the true arm. */
4687 && combine_reversed_comparison_code (cond
) != UNKNOWN
4688 && (true_rtx
== pc_rtx
4689 || (CONSTANT_P (true_rtx
)
4690 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4691 || true_rtx
== const0_rtx
4692 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4693 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4694 && !OBJECT_P (false_rtx
))
4695 || reg_mentioned_p (true_rtx
, false_rtx
)
4696 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4698 true_code
= reversed_comparison_code (cond
, NULL
);
4700 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4703 SUBST (XEXP (x
, 1), false_rtx
);
4704 SUBST (XEXP (x
, 2), true_rtx
);
4706 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4709 /* It is possible that the conditional has been simplified out. */
4710 true_code
= GET_CODE (cond
);
4711 comparison_p
= COMPARISON_P (cond
);
4714 /* If the two arms are identical, we don't need the comparison. */
4716 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4719 /* Convert a == b ? b : a to "a". */
4720 if (true_code
== EQ
&& ! side_effects_p (cond
)
4721 && !HONOR_NANS (mode
)
4722 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4723 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4725 else if (true_code
== NE
&& ! side_effects_p (cond
)
4726 && !HONOR_NANS (mode
)
4727 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4728 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4731 /* Look for cases where we have (abs x) or (neg (abs X)). */
4733 if (GET_MODE_CLASS (mode
) == MODE_INT
4734 && GET_CODE (false_rtx
) == NEG
4735 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4737 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4738 && ! side_effects_p (true_rtx
))
4743 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4747 simplify_gen_unary (NEG
, mode
,
4748 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4754 /* Look for MIN or MAX. */
4756 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4758 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4759 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4760 && ! side_effects_p (cond
))
4765 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4768 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4771 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4774 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4779 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4780 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4781 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4782 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4783 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4784 neither 1 or -1, but it isn't worth checking for. */
4786 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4788 && GET_MODE_CLASS (mode
) == MODE_INT
4789 && ! side_effects_p (x
))
4791 rtx t
= make_compound_operation (true_rtx
, SET
);
4792 rtx f
= make_compound_operation (false_rtx
, SET
);
4793 rtx cond_op0
= XEXP (cond
, 0);
4794 rtx cond_op1
= XEXP (cond
, 1);
4795 enum rtx_code op
= NIL
, extend_op
= NIL
;
4796 enum machine_mode m
= mode
;
4797 rtx z
= 0, c1
= NULL_RTX
;
4799 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4800 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4801 || GET_CODE (t
) == ASHIFT
4802 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4803 && rtx_equal_p (XEXP (t
, 0), f
))
4804 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4806 /* If an identity-zero op is commutative, check whether there
4807 would be a match if we swapped the operands. */
4808 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4809 || GET_CODE (t
) == XOR
)
4810 && rtx_equal_p (XEXP (t
, 1), f
))
4811 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4812 else if (GET_CODE (t
) == SIGN_EXTEND
4813 && (GET_CODE (XEXP (t
, 0)) == PLUS
4814 || GET_CODE (XEXP (t
, 0)) == MINUS
4815 || GET_CODE (XEXP (t
, 0)) == IOR
4816 || GET_CODE (XEXP (t
, 0)) == XOR
4817 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4818 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4819 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4820 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4821 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4822 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4823 && (num_sign_bit_copies (f
, GET_MODE (f
))
4825 (GET_MODE_BITSIZE (mode
)
4826 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4828 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4829 extend_op
= SIGN_EXTEND
;
4830 m
= GET_MODE (XEXP (t
, 0));
4832 else if (GET_CODE (t
) == SIGN_EXTEND
4833 && (GET_CODE (XEXP (t
, 0)) == PLUS
4834 || GET_CODE (XEXP (t
, 0)) == IOR
4835 || GET_CODE (XEXP (t
, 0)) == XOR
)
4836 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4837 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4838 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4839 && (num_sign_bit_copies (f
, GET_MODE (f
))
4841 (GET_MODE_BITSIZE (mode
)
4842 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4844 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4845 extend_op
= SIGN_EXTEND
;
4846 m
= GET_MODE (XEXP (t
, 0));
4848 else if (GET_CODE (t
) == ZERO_EXTEND
4849 && (GET_CODE (XEXP (t
, 0)) == PLUS
4850 || GET_CODE (XEXP (t
, 0)) == MINUS
4851 || GET_CODE (XEXP (t
, 0)) == IOR
4852 || GET_CODE (XEXP (t
, 0)) == XOR
4853 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4854 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4855 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4856 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4857 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4858 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4859 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4860 && ((nonzero_bits (f
, GET_MODE (f
))
4861 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4864 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4865 extend_op
= ZERO_EXTEND
;
4866 m
= GET_MODE (XEXP (t
, 0));
4868 else if (GET_CODE (t
) == ZERO_EXTEND
4869 && (GET_CODE (XEXP (t
, 0)) == PLUS
4870 || GET_CODE (XEXP (t
, 0)) == IOR
4871 || GET_CODE (XEXP (t
, 0)) == XOR
)
4872 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4873 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4874 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4875 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4876 && ((nonzero_bits (f
, GET_MODE (f
))
4877 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4880 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4881 extend_op
= ZERO_EXTEND
;
4882 m
= GET_MODE (XEXP (t
, 0));
4887 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4888 pc_rtx
, pc_rtx
, 0, 0);
4889 temp
= gen_binary (MULT
, m
, temp
,
4890 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4891 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4892 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
4894 if (extend_op
!= NIL
)
4895 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4901 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4902 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4903 negation of a single bit, we can convert this operation to a shift. We
4904 can actually do this more generally, but it doesn't seem worth it. */
4906 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4907 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4908 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4909 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4910 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4911 == GET_MODE_BITSIZE (mode
))
4912 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4914 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4915 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
4917 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4918 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4919 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4920 && GET_MODE (XEXP (cond
, 0)) == mode
4921 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4922 == nonzero_bits (XEXP (cond
, 0), mode
)
4923 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4924 return XEXP (cond
, 0);
4929 /* Simplify X, a SET expression. Return the new expression. */
4932 simplify_set (rtx x
)
4934 rtx src
= SET_SRC (x
);
4935 rtx dest
= SET_DEST (x
);
4936 enum machine_mode mode
4937 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4941 /* (set (pc) (return)) gets written as (return). */
4942 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4945 /* Now that we know for sure which bits of SRC we are using, see if we can
4946 simplify the expression for the object knowing that we only need the
4949 if (GET_MODE_CLASS (mode
) == MODE_INT
4950 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4952 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4953 SUBST (SET_SRC (x
), src
);
4956 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4957 the comparison result and try to simplify it unless we already have used
4958 undobuf.other_insn. */
4959 if ((GET_MODE_CLASS (mode
) == MODE_CC
4960 || GET_CODE (src
) == COMPARE
4962 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4963 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4964 && COMPARISON_P (*cc_use
)
4965 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4967 enum rtx_code old_code
= GET_CODE (*cc_use
);
4968 enum rtx_code new_code
;
4970 int other_changed
= 0;
4971 enum machine_mode compare_mode
= GET_MODE (dest
);
4972 enum machine_mode tmp_mode
;
4974 if (GET_CODE (src
) == COMPARE
)
4975 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4977 op0
= src
, op1
= const0_rtx
;
4979 /* Check whether the comparison is known at compile time. */
4980 if (GET_MODE (op0
) != VOIDmode
)
4981 tmp_mode
= GET_MODE (op0
);
4982 else if (GET_MODE (op1
) != VOIDmode
)
4983 tmp_mode
= GET_MODE (op1
);
4985 tmp_mode
= compare_mode
;
4986 tmp
= simplify_const_relational_operation (old_code
, tmp_mode
,
4988 if (tmp
!= NULL_RTX
)
4990 rtx pat
= PATTERN (other_insn
);
4991 undobuf
.other_insn
= other_insn
;
4992 SUBST (*cc_use
, tmp
);
4994 /* Attempt to simplify CC user. */
4995 if (GET_CODE (pat
) == SET
)
4997 rtx
new = simplify_rtx (SET_SRC (pat
));
4998 if (new != NULL_RTX
)
4999 SUBST (SET_SRC (pat
), new);
5002 /* Convert X into a no-op move. */
5003 SUBST (SET_DEST (x
), pc_rtx
);
5004 SUBST (SET_SRC (x
), pc_rtx
);
5008 /* Simplify our comparison, if possible. */
5009 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5011 #ifdef SELECT_CC_MODE
5012 /* If this machine has CC modes other than CCmode, check to see if we
5013 need to use a different CC mode here. */
5014 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5017 /* If the mode changed, we have to change SET_DEST, the mode in the
5018 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5019 a hard register, just build new versions with the proper mode. If it
5020 is a pseudo, we lose unless it is only time we set the pseudo, in
5021 which case we can safely change its mode. */
5022 if (compare_mode
!= GET_MODE (dest
))
5024 unsigned int regno
= REGNO (dest
);
5025 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5027 if (regno
< FIRST_PSEUDO_REGISTER
5028 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5030 if (regno
>= FIRST_PSEUDO_REGISTER
)
5031 SUBST (regno_reg_rtx
[regno
], new_dest
);
5033 SUBST (SET_DEST (x
), new_dest
);
5034 SUBST (XEXP (*cc_use
, 0), new_dest
);
5041 #endif /* SELECT_CC_MODE */
5043 /* If the code changed, we have to build a new comparison in
5044 undobuf.other_insn. */
5045 if (new_code
!= old_code
)
5047 int other_changed_previously
= other_changed
;
5048 unsigned HOST_WIDE_INT mask
;
5050 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5054 /* If the only change we made was to change an EQ into an NE or
5055 vice versa, OP0 has only one bit that might be nonzero, and OP1
5056 is zero, check if changing the user of the condition code will
5057 produce a valid insn. If it won't, we can keep the original code
5058 in that insn by surrounding our operation with an XOR. */
5060 if (((old_code
== NE
&& new_code
== EQ
)
5061 || (old_code
== EQ
&& new_code
== NE
))
5062 && ! other_changed_previously
&& op1
== const0_rtx
5063 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5064 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5066 rtx pat
= PATTERN (other_insn
), note
= 0;
5068 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5069 && ! check_asm_operands (pat
)))
5071 PUT_CODE (*cc_use
, old_code
);
5074 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5080 undobuf
.other_insn
= other_insn
;
5083 /* If we are now comparing against zero, change our source if
5084 needed. If we do not use cc0, we always have a COMPARE. */
5085 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5087 SUBST (SET_SRC (x
), op0
);
5093 /* Otherwise, if we didn't previously have a COMPARE in the
5094 correct mode, we need one. */
5095 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5097 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5102 /* Otherwise, update the COMPARE if needed. */
5103 SUBST (XEXP (src
, 0), op0
);
5104 SUBST (XEXP (src
, 1), op1
);
5109 /* Get SET_SRC in a form where we have placed back any
5110 compound expressions. Then do the checks below. */
5111 src
= make_compound_operation (src
, SET
);
5112 SUBST (SET_SRC (x
), src
);
5115 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5116 and X being a REG or (subreg (reg)), we may be able to convert this to
5117 (set (subreg:m2 x) (op)).
5119 We can always do this if M1 is narrower than M2 because that means that
5120 we only care about the low bits of the result.
5122 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5123 perform a narrower operation than requested since the high-order bits will
5124 be undefined. On machine where it is defined, this transformation is safe
5125 as long as M1 and M2 have the same number of words. */
5127 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5128 && !OBJECT_P (SUBREG_REG (src
))
5129 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5131 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5132 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5133 #ifndef WORD_REGISTER_OPERATIONS
5134 && (GET_MODE_SIZE (GET_MODE (src
))
5135 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5137 #ifdef CANNOT_CHANGE_MODE_CLASS
5138 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5139 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5140 GET_MODE (SUBREG_REG (src
)),
5143 && (GET_CODE (dest
) == REG
5144 || (GET_CODE (dest
) == SUBREG
5145 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5147 SUBST (SET_DEST (x
),
5148 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5150 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5152 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5156 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5159 && GET_CODE (src
) == SUBREG
5160 && subreg_lowpart_p (src
)
5161 && (GET_MODE_BITSIZE (GET_MODE (src
))
5162 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5164 rtx inner
= SUBREG_REG (src
);
5165 enum machine_mode inner_mode
= GET_MODE (inner
);
5167 /* Here we make sure that we don't have a sign bit on. */
5168 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5169 && (nonzero_bits (inner
, inner_mode
)
5170 < ((unsigned HOST_WIDE_INT
) 1
5171 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5173 SUBST (SET_SRC (x
), inner
);
5179 #ifdef LOAD_EXTEND_OP
5180 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5181 would require a paradoxical subreg. Replace the subreg with a
5182 zero_extend to avoid the reload that would otherwise be required. */
5184 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5185 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5186 && SUBREG_BYTE (src
) == 0
5187 && (GET_MODE_SIZE (GET_MODE (src
))
5188 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5189 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5192 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5193 GET_MODE (src
), SUBREG_REG (src
)));
5199 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5200 are comparing an item known to be 0 or -1 against 0, use a logical
5201 operation instead. Check for one of the arms being an IOR of the other
5202 arm with some value. We compute three terms to be IOR'ed together. In
5203 practice, at most two will be nonzero. Then we do the IOR's. */
5205 if (GET_CODE (dest
) != PC
5206 && GET_CODE (src
) == IF_THEN_ELSE
5207 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5208 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5209 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5210 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5211 #ifdef HAVE_conditional_move
5212 && ! can_conditionally_move_p (GET_MODE (src
))
5214 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5215 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5216 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5217 && ! side_effects_p (src
))
5219 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5220 ? XEXP (src
, 1) : XEXP (src
, 2));
5221 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5222 ? XEXP (src
, 2) : XEXP (src
, 1));
5223 rtx term1
= const0_rtx
, term2
, term3
;
5225 if (GET_CODE (true_rtx
) == IOR
5226 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5227 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5228 else if (GET_CODE (true_rtx
) == IOR
5229 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5230 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5231 else if (GET_CODE (false_rtx
) == IOR
5232 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5233 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5234 else if (GET_CODE (false_rtx
) == IOR
5235 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5236 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5238 term2
= gen_binary (AND
, GET_MODE (src
),
5239 XEXP (XEXP (src
, 0), 0), true_rtx
);
5240 term3
= gen_binary (AND
, GET_MODE (src
),
5241 simplify_gen_unary (NOT
, GET_MODE (src
),
5242 XEXP (XEXP (src
, 0), 0),
5247 gen_binary (IOR
, GET_MODE (src
),
5248 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5254 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5255 whole thing fail. */
5256 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5258 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5261 /* Convert this into a field assignment operation, if possible. */
5262 return make_field_assignment (x
);
5265 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5266 result. LAST is nonzero if this is the last retry. */
5269 simplify_logical (rtx x
, int last
)
5271 enum machine_mode mode
= GET_MODE (x
);
5272 rtx op0
= XEXP (x
, 0);
5273 rtx op1
= XEXP (x
, 1);
5276 switch (GET_CODE (x
))
5279 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5280 insn (and may simplify more). */
5281 if (GET_CODE (op0
) == XOR
5282 && rtx_equal_p (XEXP (op0
, 0), op1
)
5283 && ! side_effects_p (op1
))
5284 x
= gen_binary (AND
, mode
,
5285 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5288 if (GET_CODE (op0
) == XOR
5289 && rtx_equal_p (XEXP (op0
, 1), op1
)
5290 && ! side_effects_p (op1
))
5291 x
= gen_binary (AND
, mode
,
5292 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5295 /* Similarly for (~(A ^ B)) & A. */
5296 if (GET_CODE (op0
) == NOT
5297 && GET_CODE (XEXP (op0
, 0)) == XOR
5298 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5299 && ! side_effects_p (op1
))
5300 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5302 if (GET_CODE (op0
) == NOT
5303 && GET_CODE (XEXP (op0
, 0)) == XOR
5304 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5305 && ! side_effects_p (op1
))
5306 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5308 /* We can call simplify_and_const_int only if we don't lose
5309 any (sign) bits when converting INTVAL (op1) to
5310 "unsigned HOST_WIDE_INT". */
5311 if (GET_CODE (op1
) == CONST_INT
5312 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5313 || INTVAL (op1
) > 0))
5315 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5317 /* If we have (ior (and (X C1) C2)) and the next restart would be
5318 the last, simplify this by making C1 as small as possible
5321 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5322 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5323 && GET_CODE (op1
) == CONST_INT
)
5324 return gen_binary (IOR
, mode
,
5325 gen_binary (AND
, mode
, XEXP (op0
, 0),
5326 GEN_INT (INTVAL (XEXP (op0
, 1))
5327 & ~INTVAL (op1
))), op1
);
5329 if (GET_CODE (x
) != AND
)
5336 /* Convert (A | B) & A to A. */
5337 if (GET_CODE (op0
) == IOR
5338 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5339 || rtx_equal_p (XEXP (op0
, 1), op1
))
5340 && ! side_effects_p (XEXP (op0
, 0))
5341 && ! side_effects_p (XEXP (op0
, 1)))
5344 /* In the following group of tests (and those in case IOR below),
5345 we start with some combination of logical operations and apply
5346 the distributive law followed by the inverse distributive law.
5347 Most of the time, this results in no change. However, if some of
5348 the operands are the same or inverses of each other, simplifications
5351 For example, (and (ior A B) (not B)) can occur as the result of
5352 expanding a bit field assignment. When we apply the distributive
5353 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5354 which then simplifies to (and (A (not B))).
5356 If we have (and (ior A B) C), apply the distributive law and then
5357 the inverse distributive law to see if things simplify. */
5359 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5361 x
= apply_distributive_law
5362 (gen_binary (GET_CODE (op0
), mode
,
5363 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5364 gen_binary (AND
, mode
, XEXP (op0
, 1),
5366 if (GET_CODE (x
) != AND
)
5370 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5371 return apply_distributive_law
5372 (gen_binary (GET_CODE (op1
), mode
,
5373 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5374 gen_binary (AND
, mode
, XEXP (op1
, 1),
5377 /* Similarly, taking advantage of the fact that
5378 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5380 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5381 return apply_distributive_law
5382 (gen_binary (XOR
, mode
,
5383 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5384 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5387 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5388 return apply_distributive_law
5389 (gen_binary (XOR
, mode
,
5390 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5391 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5395 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5396 if (GET_CODE (op1
) == CONST_INT
5397 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5398 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5401 /* Convert (A & B) | A to A. */
5402 if (GET_CODE (op0
) == AND
5403 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5404 || rtx_equal_p (XEXP (op0
, 1), op1
))
5405 && ! side_effects_p (XEXP (op0
, 0))
5406 && ! side_effects_p (XEXP (op0
, 1)))
5409 /* If we have (ior (and A B) C), apply the distributive law and then
5410 the inverse distributive law to see if things simplify. */
5412 if (GET_CODE (op0
) == AND
)
5414 x
= apply_distributive_law
5415 (gen_binary (AND
, mode
,
5416 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5417 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5420 if (GET_CODE (x
) != IOR
)
5424 if (GET_CODE (op1
) == AND
)
5426 x
= apply_distributive_law
5427 (gen_binary (AND
, mode
,
5428 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5429 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5432 if (GET_CODE (x
) != IOR
)
5436 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5437 mode size to (rotate A CX). */
5439 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5440 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5441 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5442 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5443 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5444 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5445 == GET_MODE_BITSIZE (mode
)))
5446 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5447 (GET_CODE (op0
) == ASHIFT
5448 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5450 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5451 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5452 does not affect any of the bits in OP1, it can really be done
5453 as a PLUS and we can associate. We do this by seeing if OP1
5454 can be safely shifted left C bits. */
5455 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5456 && GET_CODE (XEXP (op0
, 0)) == PLUS
5457 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5458 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5459 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5461 int count
= INTVAL (XEXP (op0
, 1));
5462 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5464 if (mask
>> count
== INTVAL (op1
)
5465 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5467 SUBST (XEXP (XEXP (op0
, 0), 1),
5468 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5475 /* If we are XORing two things that have no bits in common,
5476 convert them into an IOR. This helps to detect rotation encoded
5477 using those methods and possibly other simplifications. */
5479 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5480 && (nonzero_bits (op0
, mode
)
5481 & nonzero_bits (op1
, mode
)) == 0)
5482 return (gen_binary (IOR
, mode
, op0
, op1
));
5484 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5485 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5488 int num_negated
= 0;
5490 if (GET_CODE (op0
) == NOT
)
5491 num_negated
++, op0
= XEXP (op0
, 0);
5492 if (GET_CODE (op1
) == NOT
)
5493 num_negated
++, op1
= XEXP (op1
, 0);
5495 if (num_negated
== 2)
5497 SUBST (XEXP (x
, 0), op0
);
5498 SUBST (XEXP (x
, 1), op1
);
5500 else if (num_negated
== 1)
5502 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5506 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5507 correspond to a machine insn or result in further simplifications
5508 if B is a constant. */
5510 if (GET_CODE (op0
) == AND
5511 && rtx_equal_p (XEXP (op0
, 1), op1
)
5512 && ! side_effects_p (op1
))
5513 return gen_binary (AND
, mode
,
5514 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5517 else if (GET_CODE (op0
) == AND
5518 && rtx_equal_p (XEXP (op0
, 0), op1
)
5519 && ! side_effects_p (op1
))
5520 return gen_binary (AND
, mode
,
5521 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5524 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5525 comparison if STORE_FLAG_VALUE is 1. */
5526 if (STORE_FLAG_VALUE
== 1
5527 && op1
== const1_rtx
5528 && COMPARISON_P (op0
)
5529 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5533 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5534 is (lt foo (const_int 0)), so we can perform the above
5535 simplification if STORE_FLAG_VALUE is 1. */
5537 if (STORE_FLAG_VALUE
== 1
5538 && op1
== const1_rtx
5539 && GET_CODE (op0
) == LSHIFTRT
5540 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5541 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5542 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5544 /* (xor (comparison foo bar) (const_int sign-bit))
5545 when STORE_FLAG_VALUE is the sign bit. */
5546 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5547 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5548 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5549 && op1
== const_true_rtx
5550 && COMPARISON_P (op0
)
5551 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5564 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5565 operations" because they can be replaced with two more basic operations.
5566 ZERO_EXTEND is also considered "compound" because it can be replaced with
5567 an AND operation, which is simpler, though only one operation.
5569 The function expand_compound_operation is called with an rtx expression
5570 and will convert it to the appropriate shifts and AND operations,
5571 simplifying at each stage.
5573 The function make_compound_operation is called to convert an expression
5574 consisting of shifts and ANDs into the equivalent compound expression.
5575 It is the inverse of this function, loosely speaking. */
5578 expand_compound_operation (rtx x
)
5580 unsigned HOST_WIDE_INT pos
= 0, len
;
5582 unsigned int modewidth
;
5585 switch (GET_CODE (x
))
5590 /* We can't necessarily use a const_int for a multiword mode;
5591 it depends on implicitly extending the value.
5592 Since we don't know the right way to extend it,
5593 we can't tell whether the implicit way is right.
5595 Even for a mode that is no wider than a const_int,
5596 we can't win, because we need to sign extend one of its bits through
5597 the rest of it, and we don't know which bit. */
5598 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5601 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5602 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5603 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5604 reloaded. If not for that, MEM's would very rarely be safe.
5606 Reject MODEs bigger than a word, because we might not be able
5607 to reference a two-register group starting with an arbitrary register
5608 (and currently gen_lowpart might crash for a SUBREG). */
5610 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5613 /* Reject MODEs that aren't scalar integers because turning vector
5614 or complex modes into shifts causes problems. */
5616 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5619 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5620 /* If the inner object has VOIDmode (the only way this can happen
5621 is if it is an ASM_OPERANDS), we can't do anything since we don't
5622 know how much masking to do. */
5631 /* If the operand is a CLOBBER, just return it. */
5632 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5635 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5636 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5637 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5640 /* Reject MODEs that aren't scalar integers because turning vector
5641 or complex modes into shifts causes problems. */
5643 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5646 len
= INTVAL (XEXP (x
, 1));
5647 pos
= INTVAL (XEXP (x
, 2));
5649 /* If this goes outside the object being extracted, replace the object
5650 with a (use (mem ...)) construct that only combine understands
5651 and is used only for this purpose. */
5652 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5653 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5655 if (BITS_BIG_ENDIAN
)
5656 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5663 /* Convert sign extension to zero extension, if we know that the high
5664 bit is not set, as this is easier to optimize. It will be converted
5665 back to cheaper alternative in make_extraction. */
5666 if (GET_CODE (x
) == SIGN_EXTEND
5667 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5668 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5669 & ~(((unsigned HOST_WIDE_INT
)
5670 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5674 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5675 rtx temp2
= expand_compound_operation (temp
);
5677 /* Make sure this is a profitable operation. */
5678 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5680 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5686 /* We can optimize some special cases of ZERO_EXTEND. */
5687 if (GET_CODE (x
) == ZERO_EXTEND
)
5689 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5690 know that the last value didn't have any inappropriate bits
5692 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5693 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5694 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5695 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5696 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5697 return XEXP (XEXP (x
, 0), 0);
5699 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5700 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5701 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5702 && subreg_lowpart_p (XEXP (x
, 0))
5703 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5704 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5705 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5706 return SUBREG_REG (XEXP (x
, 0));
5708 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5709 is a comparison and STORE_FLAG_VALUE permits. This is like
5710 the first case, but it works even when GET_MODE (x) is larger
5711 than HOST_WIDE_INT. */
5712 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5713 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5714 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5715 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5716 <= HOST_BITS_PER_WIDE_INT
)
5717 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5718 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5719 return XEXP (XEXP (x
, 0), 0);
5721 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5722 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5723 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5724 && subreg_lowpart_p (XEXP (x
, 0))
5725 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5726 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5727 <= HOST_BITS_PER_WIDE_INT
)
5728 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5729 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5730 return SUBREG_REG (XEXP (x
, 0));
5734 /* If we reach here, we want to return a pair of shifts. The inner
5735 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5736 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5737 logical depending on the value of UNSIGNEDP.
5739 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5740 converted into an AND of a shift.
5742 We must check for the case where the left shift would have a negative
5743 count. This can happen in a case like (x >> 31) & 255 on machines
5744 that can't shift by a constant. On those machines, we would first
5745 combine the shift with the AND to produce a variable-position
5746 extraction. Then the constant of 31 would be substituted in to produce
5747 a such a position. */
5749 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5750 if (modewidth
+ len
>= pos
)
5751 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5753 simplify_shift_const (NULL_RTX
, ASHIFT
,
5756 modewidth
- pos
- len
),
5759 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5760 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5761 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5764 ((HOST_WIDE_INT
) 1 << len
) - 1);
5766 /* Any other cases we can't handle. */
5769 /* If we couldn't do this for some reason, return the original
5771 if (GET_CODE (tem
) == CLOBBER
)
5777 /* X is a SET which contains an assignment of one object into
5778 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5779 or certain SUBREGS). If possible, convert it into a series of
5782 We half-heartedly support variable positions, but do not at all
5783 support variable lengths. */
5786 expand_field_assignment (rtx x
)
5789 rtx pos
; /* Always counts from low bit. */
5792 enum machine_mode compute_mode
;
5794 /* Loop until we find something we can't simplify. */
5797 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5798 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5800 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5801 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5802 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5804 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5805 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5807 inner
= XEXP (SET_DEST (x
), 0);
5808 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5809 pos
= XEXP (SET_DEST (x
), 2);
5811 /* If the position is constant and spans the width of INNER,
5812 surround INNER with a USE to indicate this. */
5813 if (GET_CODE (pos
) == CONST_INT
5814 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5815 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5817 if (BITS_BIG_ENDIAN
)
5819 if (GET_CODE (pos
) == CONST_INT
)
5820 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5822 else if (GET_CODE (pos
) == MINUS
5823 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5824 && (INTVAL (XEXP (pos
, 1))
5825 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5826 /* If position is ADJUST - X, new position is X. */
5827 pos
= XEXP (pos
, 0);
5829 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5830 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5836 /* A SUBREG between two modes that occupy the same numbers of words
5837 can be done by moving the SUBREG to the source. */
5838 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5839 /* We need SUBREGs to compute nonzero_bits properly. */
5840 && nonzero_sign_valid
5841 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5842 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5843 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5844 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5846 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5848 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5855 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5856 inner
= SUBREG_REG (inner
);
5858 compute_mode
= GET_MODE (inner
);
5860 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5861 if (! SCALAR_INT_MODE_P (compute_mode
))
5863 enum machine_mode imode
;
5865 /* Don't do anything for vector or complex integral types. */
5866 if (! FLOAT_MODE_P (compute_mode
))
5869 /* Try to find an integral mode to pun with. */
5870 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5871 if (imode
== BLKmode
)
5874 compute_mode
= imode
;
5875 inner
= gen_lowpart (imode
, inner
);
5878 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5879 if (len
< HOST_BITS_PER_WIDE_INT
)
5880 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5884 /* Now compute the equivalent expression. Make a copy of INNER
5885 for the SET_DEST in case it is a MEM into which we will substitute;
5886 we don't want shared RTL in that case. */
5888 (VOIDmode
, copy_rtx (inner
),
5889 gen_binary (IOR
, compute_mode
,
5890 gen_binary (AND
, compute_mode
,
5891 simplify_gen_unary (NOT
, compute_mode
,
5897 gen_binary (ASHIFT
, compute_mode
,
5898 gen_binary (AND
, compute_mode
,
5900 (compute_mode
, SET_SRC (x
)),
5908 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5909 it is an RTX that represents a variable starting position; otherwise,
5910 POS is the (constant) starting bit position (counted from the LSB).
5912 INNER may be a USE. This will occur when we started with a bitfield
5913 that went outside the boundary of the object in memory, which is
5914 allowed on most machines. To isolate this case, we produce a USE
5915 whose mode is wide enough and surround the MEM with it. The only
5916 code that understands the USE is this routine. If it is not removed,
5917 it will cause the resulting insn not to match.
5919 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5922 IN_DEST is nonzero if this is a reference in the destination of a
5923 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5924 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5927 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5928 ZERO_EXTRACT should be built even for bits starting at bit 0.
5930 MODE is the desired mode of the result (if IN_DEST == 0).
5932 The result is an RTX for the extraction or NULL_RTX if the target
5936 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5937 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5938 int in_dest
, int in_compare
)
5940 /* This mode describes the size of the storage area
5941 to fetch the overall value from. Within that, we
5942 ignore the POS lowest bits, etc. */
5943 enum machine_mode is_mode
= GET_MODE (inner
);
5944 enum machine_mode inner_mode
;
5945 enum machine_mode wanted_inner_mode
= byte_mode
;
5946 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5947 enum machine_mode pos_mode
= word_mode
;
5948 enum machine_mode extraction_mode
= word_mode
;
5949 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5952 rtx orig_pos_rtx
= pos_rtx
;
5953 HOST_WIDE_INT orig_pos
;
5955 /* Get some information about INNER and get the innermost object. */
5956 if (GET_CODE (inner
) == USE
)
5957 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5958 /* We don't need to adjust the position because we set up the USE
5959 to pretend that it was a full-word object. */
5960 spans_byte
= 1, inner
= XEXP (inner
, 0);
5961 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5963 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5964 consider just the QI as the memory to extract from.
5965 The subreg adds or removes high bits; its mode is
5966 irrelevant to the meaning of this extraction,
5967 since POS and LEN count from the lsb. */
5968 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5969 is_mode
= GET_MODE (SUBREG_REG (inner
));
5970 inner
= SUBREG_REG (inner
);
5972 else if (GET_CODE (inner
) == ASHIFT
5973 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5974 && pos_rtx
== 0 && pos
== 0
5975 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5977 /* We're extracting the least significant bits of an rtx
5978 (ashift X (const_int C)), where LEN > C. Extract the
5979 least significant (LEN - C) bits of X, giving an rtx
5980 whose mode is MODE, then shift it left C times. */
5981 new = make_extraction (mode
, XEXP (inner
, 0),
5982 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5983 unsignedp
, in_dest
, in_compare
);
5985 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
5988 inner_mode
= GET_MODE (inner
);
5990 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5991 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5993 /* See if this can be done without an extraction. We never can if the
5994 width of the field is not the same as that of some integer mode. For
5995 registers, we can only avoid the extraction if the position is at the
5996 low-order bit and this is either not in the destination or we have the
5997 appropriate STRICT_LOW_PART operation available.
5999 For MEM, we can avoid an extract if the field starts on an appropriate
6000 boundary and we can change the mode of the memory reference. However,
6001 we cannot directly access the MEM if we have a USE and the underlying
6002 MEM is not TMODE. This combination means that MEM was being used in a
6003 context where bits outside its mode were being referenced; that is only
6004 valid in bit-field insns. */
6006 if (tmode
!= BLKmode
6007 && ! (spans_byte
&& inner_mode
!= tmode
)
6008 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6009 && GET_CODE (inner
) != MEM
6011 || (GET_CODE (inner
) == REG
6012 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6013 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6015 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6016 : BITS_PER_UNIT
)) == 0
6017 /* We can't do this if we are widening INNER_MODE (it
6018 may not be aligned, for one thing). */
6019 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6020 && (inner_mode
== tmode
6021 || (! mode_dependent_address_p (XEXP (inner
, 0))
6022 && ! MEM_VOLATILE_P (inner
))))))
6024 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6025 field. If the original and current mode are the same, we need not
6026 adjust the offset. Otherwise, we do if bytes big endian.
6028 If INNER is not a MEM, get a piece consisting of just the field
6029 of interest (in this case POS % BITS_PER_WORD must be 0). */
6031 if (GET_CODE (inner
) == MEM
)
6033 HOST_WIDE_INT offset
;
6035 /* POS counts from lsb, but make OFFSET count in memory order. */
6036 if (BYTES_BIG_ENDIAN
)
6037 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6039 offset
= pos
/ BITS_PER_UNIT
;
6041 new = adjust_address_nv (inner
, tmode
, offset
);
6043 else if (GET_CODE (inner
) == REG
)
6045 if (tmode
!= inner_mode
)
6047 /* We can't call gen_lowpart in a DEST since we
6048 always want a SUBREG (see below) and it would sometimes
6049 return a new hard register. */
6052 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6054 if (WORDS_BIG_ENDIAN
6055 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6056 final_word
= ((GET_MODE_SIZE (inner_mode
)
6057 - GET_MODE_SIZE (tmode
))
6058 / UNITS_PER_WORD
) - final_word
;
6060 final_word
*= UNITS_PER_WORD
;
6061 if (BYTES_BIG_ENDIAN
&&
6062 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6063 final_word
+= (GET_MODE_SIZE (inner_mode
)
6064 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6066 /* Avoid creating invalid subregs, for example when
6067 simplifying (x>>32)&255. */
6068 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6071 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6074 new = gen_lowpart (tmode
, inner
);
6080 new = force_to_mode (inner
, tmode
,
6081 len
>= HOST_BITS_PER_WIDE_INT
6082 ? ~(unsigned HOST_WIDE_INT
) 0
6083 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6086 /* If this extraction is going into the destination of a SET,
6087 make a STRICT_LOW_PART unless we made a MEM. */
6090 return (GET_CODE (new) == MEM
? new
6091 : (GET_CODE (new) != SUBREG
6092 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6093 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6098 if (GET_CODE (new) == CONST_INT
)
6099 return gen_int_mode (INTVAL (new), mode
);
6101 /* If we know that no extraneous bits are set, and that the high
6102 bit is not set, convert the extraction to the cheaper of
6103 sign and zero extension, that are equivalent in these cases. */
6104 if (flag_expensive_optimizations
6105 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6106 && ((nonzero_bits (new, tmode
)
6107 & ~(((unsigned HOST_WIDE_INT
)
6108 GET_MODE_MASK (tmode
))
6112 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6113 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6115 /* Prefer ZERO_EXTENSION, since it gives more information to
6117 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6122 /* Otherwise, sign- or zero-extend unless we already are in the
6125 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6129 /* Unless this is a COMPARE or we have a funny memory reference,
6130 don't do anything with zero-extending field extracts starting at
6131 the low-order bit since they are simple AND operations. */
6132 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6133 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6136 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6137 we would be spanning bytes or if the position is not a constant and the
6138 length is not 1. In all other cases, we would only be going outside
6139 our object in cases when an original shift would have been
6141 if (! spans_byte
&& GET_CODE (inner
) == MEM
6142 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6143 || (pos_rtx
!= 0 && len
!= 1)))
6146 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6147 and the mode for the result. */
6148 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6150 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6151 pos_mode
= mode_for_extraction (EP_insv
, 2);
6152 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6155 if (! in_dest
&& unsignedp
6156 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6158 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6159 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6160 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6163 if (! in_dest
&& ! unsignedp
6164 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6166 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6167 pos_mode
= mode_for_extraction (EP_extv
, 3);
6168 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6171 /* Never narrow an object, since that might not be safe. */
6173 if (mode
!= VOIDmode
6174 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6175 extraction_mode
= mode
;
6177 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6178 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6179 pos_mode
= GET_MODE (pos_rtx
);
6181 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6182 if we have to change the mode of memory and cannot, the desired mode is
6184 if (GET_CODE (inner
) != MEM
)
6185 wanted_inner_mode
= wanted_inner_reg_mode
;
6186 else if (inner_mode
!= wanted_inner_mode
6187 && (mode_dependent_address_p (XEXP (inner
, 0))
6188 || MEM_VOLATILE_P (inner
)))
6189 wanted_inner_mode
= extraction_mode
;
6193 if (BITS_BIG_ENDIAN
)
6195 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6196 BITS_BIG_ENDIAN style. If position is constant, compute new
6197 position. Otherwise, build subtraction.
6198 Note that POS is relative to the mode of the original argument.
6199 If it's a MEM we need to recompute POS relative to that.
6200 However, if we're extracting from (or inserting into) a register,
6201 we want to recompute POS relative to wanted_inner_mode. */
6202 int width
= (GET_CODE (inner
) == MEM
6203 ? GET_MODE_BITSIZE (is_mode
)
6204 : GET_MODE_BITSIZE (wanted_inner_mode
));
6207 pos
= width
- len
- pos
;
6210 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6211 /* POS may be less than 0 now, but we check for that below.
6212 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6215 /* If INNER has a wider mode, make it smaller. If this is a constant
6216 extract, try to adjust the byte to point to the byte containing
6218 if (wanted_inner_mode
!= VOIDmode
6219 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6220 && ((GET_CODE (inner
) == MEM
6221 && (inner_mode
== wanted_inner_mode
6222 || (! mode_dependent_address_p (XEXP (inner
, 0))
6223 && ! MEM_VOLATILE_P (inner
))))))
6227 /* The computations below will be correct if the machine is big
6228 endian in both bits and bytes or little endian in bits and bytes.
6229 If it is mixed, we must adjust. */
6231 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6232 adjust OFFSET to compensate. */
6233 if (BYTES_BIG_ENDIAN
6235 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6236 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6238 /* If this is a constant position, we can move to the desired byte. */
6241 offset
+= pos
/ BITS_PER_UNIT
;
6242 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6245 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6247 && is_mode
!= wanted_inner_mode
)
6248 offset
= (GET_MODE_SIZE (is_mode
)
6249 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6251 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6252 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6255 /* If INNER is not memory, we can always get it into the proper mode. If we
6256 are changing its mode, POS must be a constant and smaller than the size
6258 else if (GET_CODE (inner
) != MEM
)
6260 if (GET_MODE (inner
) != wanted_inner_mode
6262 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6265 inner
= force_to_mode (inner
, wanted_inner_mode
,
6267 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6268 ? ~(unsigned HOST_WIDE_INT
) 0
6269 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6274 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6275 have to zero extend. Otherwise, we can just use a SUBREG. */
6277 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6279 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6281 /* If we know that no extraneous bits are set, and that the high
6282 bit is not set, convert extraction to cheaper one - either
6283 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6285 if (flag_expensive_optimizations
6286 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6287 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6288 & ~(((unsigned HOST_WIDE_INT
)
6289 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6293 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6295 /* Prefer ZERO_EXTENSION, since it gives more information to
6297 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6302 else if (pos_rtx
!= 0
6303 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6304 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6306 /* Make POS_RTX unless we already have it and it is correct. If we don't
6307 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6309 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6310 pos_rtx
= orig_pos_rtx
;
6312 else if (pos_rtx
== 0)
6313 pos_rtx
= GEN_INT (pos
);
6315 /* Make the required operation. See if we can use existing rtx. */
6316 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6317 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6319 new = gen_lowpart (mode
, new);
6324 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6325 with any other operations in X. Return X without that shift if so. */
6328 extract_left_shift (rtx x
, int count
)
6330 enum rtx_code code
= GET_CODE (x
);
6331 enum machine_mode mode
= GET_MODE (x
);
6337 /* This is the shift itself. If it is wide enough, we will return
6338 either the value being shifted if the shift count is equal to
6339 COUNT or a shift for the difference. */
6340 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6341 && INTVAL (XEXP (x
, 1)) >= count
)
6342 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6343 INTVAL (XEXP (x
, 1)) - count
);
6347 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6348 return simplify_gen_unary (code
, mode
, tem
, mode
);
6352 case PLUS
: case IOR
: case XOR
: case AND
:
6353 /* If we can safely shift this constant and we find the inner shift,
6354 make a new operation. */
6355 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6356 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6357 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6358 return gen_binary (code
, mode
, tem
,
6359 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6370 /* Look at the expression rooted at X. Look for expressions
6371 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6372 Form these expressions.
6374 Return the new rtx, usually just X.
6376 Also, for machines like the VAX that don't have logical shift insns,
6377 try to convert logical to arithmetic shift operations in cases where
6378 they are equivalent. This undoes the canonicalizations to logical
6379 shifts done elsewhere.
6381 We try, as much as possible, to re-use rtl expressions to save memory.
6383 IN_CODE says what kind of expression we are processing. Normally, it is
6384 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6385 being kludges), it is MEM. When processing the arguments of a comparison
6386 or a COMPARE against zero, it is COMPARE. */
6389 make_compound_operation (rtx x
, enum rtx_code in_code
)
6391 enum rtx_code code
= GET_CODE (x
);
6392 enum machine_mode mode
= GET_MODE (x
);
6393 int mode_width
= GET_MODE_BITSIZE (mode
);
6395 enum rtx_code next_code
;
6401 /* Select the code to be used in recursive calls. Once we are inside an
6402 address, we stay there. If we have a comparison, set to COMPARE,
6403 but once inside, go back to our default of SET. */
6405 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6406 : ((code
== COMPARE
|| COMPARISON_P (x
))
6407 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6408 : in_code
== COMPARE
? SET
: in_code
);
6410 /* Process depending on the code of this operation. If NEW is set
6411 nonzero, it will be returned. */
6416 /* Convert shifts by constants into multiplications if inside
6418 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6419 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6420 && INTVAL (XEXP (x
, 1)) >= 0)
6422 new = make_compound_operation (XEXP (x
, 0), next_code
);
6423 new = gen_rtx_MULT (mode
, new,
6424 GEN_INT ((HOST_WIDE_INT
) 1
6425 << INTVAL (XEXP (x
, 1))));
6430 /* If the second operand is not a constant, we can't do anything
6432 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6435 /* If the constant is a power of two minus one and the first operand
6436 is a logical right shift, make an extraction. */
6437 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6438 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6440 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6441 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6442 0, in_code
== COMPARE
);
6445 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6446 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6447 && subreg_lowpart_p (XEXP (x
, 0))
6448 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6449 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6451 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6453 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6454 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6455 0, in_code
== COMPARE
);
6457 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6458 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6459 || GET_CODE (XEXP (x
, 0)) == IOR
)
6460 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6461 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6462 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6464 /* Apply the distributive law, and then try to make extractions. */
6465 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6466 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6468 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6470 new = make_compound_operation (new, in_code
);
6473 /* If we are have (and (rotate X C) M) and C is larger than the number
6474 of bits in M, this is an extraction. */
6476 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6477 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6478 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6479 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6481 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6482 new = make_extraction (mode
, new,
6483 (GET_MODE_BITSIZE (mode
)
6484 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6485 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6488 /* On machines without logical shifts, if the operand of the AND is
6489 a logical shift and our mask turns off all the propagated sign
6490 bits, we can replace the logical shift with an arithmetic shift. */
6491 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6492 && !have_insn_for (LSHIFTRT
, mode
)
6493 && have_insn_for (ASHIFTRT
, mode
)
6494 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6495 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6496 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6497 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6499 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6501 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6502 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6504 gen_rtx_ASHIFTRT (mode
,
6505 make_compound_operation
6506 (XEXP (XEXP (x
, 0), 0), next_code
),
6507 XEXP (XEXP (x
, 0), 1)));
6510 /* If the constant is one less than a power of two, this might be
6511 representable by an extraction even if no shift is present.
6512 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6513 we are in a COMPARE. */
6514 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6515 new = make_extraction (mode
,
6516 make_compound_operation (XEXP (x
, 0),
6518 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6520 /* If we are in a comparison and this is an AND with a power of two,
6521 convert this into the appropriate bit extract. */
6522 else if (in_code
== COMPARE
6523 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6524 new = make_extraction (mode
,
6525 make_compound_operation (XEXP (x
, 0),
6527 i
, NULL_RTX
, 1, 1, 0, 1);
6532 /* If the sign bit is known to be zero, replace this with an
6533 arithmetic shift. */
6534 if (have_insn_for (ASHIFTRT
, mode
)
6535 && ! have_insn_for (LSHIFTRT
, mode
)
6536 && mode_width
<= HOST_BITS_PER_WIDE_INT
6537 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6539 new = gen_rtx_ASHIFTRT (mode
,
6540 make_compound_operation (XEXP (x
, 0),
6546 /* ... fall through ... */
6552 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6553 this is a SIGN_EXTRACT. */
6554 if (GET_CODE (rhs
) == CONST_INT
6555 && GET_CODE (lhs
) == ASHIFT
6556 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6557 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6559 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6560 new = make_extraction (mode
, new,
6561 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6562 NULL_RTX
, mode_width
- INTVAL (rhs
),
6563 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6567 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6568 If so, try to merge the shifts into a SIGN_EXTEND. We could
6569 also do this for some cases of SIGN_EXTRACT, but it doesn't
6570 seem worth the effort; the case checked for occurs on Alpha. */
6573 && ! (GET_CODE (lhs
) == SUBREG
6574 && (OBJECT_P (SUBREG_REG (lhs
))))
6575 && GET_CODE (rhs
) == CONST_INT
6576 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6577 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6578 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6579 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6580 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6585 /* Call ourselves recursively on the inner expression. If we are
6586 narrowing the object and it has a different RTL code from
6587 what it originally did, do this SUBREG as a force_to_mode. */
6589 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6590 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6591 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6592 && subreg_lowpart_p (x
))
6594 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6597 /* If we have something other than a SUBREG, we might have
6598 done an expansion, so rerun ourselves. */
6599 if (GET_CODE (newer
) != SUBREG
)
6600 newer
= make_compound_operation (newer
, in_code
);
6605 /* If this is a paradoxical subreg, and the new code is a sign or
6606 zero extension, omit the subreg and widen the extension. If it
6607 is a regular subreg, we can still get rid of the subreg by not
6608 widening so much, or in fact removing the extension entirely. */
6609 if ((GET_CODE (tem
) == SIGN_EXTEND
6610 || GET_CODE (tem
) == ZERO_EXTEND
)
6611 && subreg_lowpart_p (x
))
6613 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6614 || (GET_MODE_SIZE (mode
) >
6615 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6617 if (! SCALAR_INT_MODE_P (mode
))
6619 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6622 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6633 x
= gen_lowpart (mode
, new);
6634 code
= GET_CODE (x
);
6637 /* Now recursively process each operand of this operation. */
6638 fmt
= GET_RTX_FORMAT (code
);
6639 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6642 new = make_compound_operation (XEXP (x
, i
), next_code
);
6643 SUBST (XEXP (x
, i
), new);
6649 /* Given M see if it is a value that would select a field of bits
6650 within an item, but not the entire word. Return -1 if not.
6651 Otherwise, return the starting position of the field, where 0 is the
6654 *PLEN is set to the length of the field. */
6657 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6659 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6660 int pos
= exact_log2 (m
& -m
);
6666 /* Now shift off the low-order zero bits and see if we have a power of
6668 len
= exact_log2 ((m
>> pos
) + 1);
6677 /* See if X can be simplified knowing that we will only refer to it in
6678 MODE and will only refer to those bits that are nonzero in MASK.
6679 If other bits are being computed or if masking operations are done
6680 that select a superset of the bits in MASK, they can sometimes be
6683 Return a possibly simplified expression, but always convert X to
6684 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6686 Also, if REG is nonzero and X is a register equal in value to REG,
6689 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6690 are all off in X. This is used when X will be complemented, by either
6691 NOT, NEG, or XOR. */
6694 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6695 rtx reg
, int just_select
)
6697 enum rtx_code code
= GET_CODE (x
);
6698 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6699 enum machine_mode op_mode
;
6700 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6703 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6704 code below will do the wrong thing since the mode of such an
6705 expression is VOIDmode.
6707 Also do nothing if X is a CLOBBER; this can happen if X was
6708 the return value from a call to gen_lowpart. */
6709 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6712 /* We want to perform the operation is its present mode unless we know
6713 that the operation is valid in MODE, in which case we do the operation
6715 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6716 && have_insn_for (code
, mode
))
6717 ? mode
: GET_MODE (x
));
6719 /* It is not valid to do a right-shift in a narrower mode
6720 than the one it came in with. */
6721 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6722 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6723 op_mode
= GET_MODE (x
);
6725 /* Truncate MASK to fit OP_MODE. */
6727 mask
&= GET_MODE_MASK (op_mode
);
6729 /* When we have an arithmetic operation, or a shift whose count we
6730 do not know, we need to assume that all bits up to the highest-order
6731 bit in MASK will be needed. This is how we form such a mask. */
6732 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6733 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6735 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6738 /* Determine what bits of X are guaranteed to be (non)zero. */
6739 nonzero
= nonzero_bits (x
, mode
);
6741 /* If none of the bits in X are needed, return a zero. */
6742 if (! just_select
&& (nonzero
& mask
) == 0)
6745 /* If X is a CONST_INT, return a new one. Do this here since the
6746 test below will fail. */
6747 if (GET_CODE (x
) == CONST_INT
)
6749 if (SCALAR_INT_MODE_P (mode
))
6750 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6753 x
= GEN_INT (INTVAL (x
) & mask
);
6754 return gen_lowpart_common (mode
, x
);
6758 /* If X is narrower than MODE and we want all the bits in X's mode, just
6759 get X in the proper mode. */
6760 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6761 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6762 return gen_lowpart (mode
, x
);
6764 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6765 MASK are already known to be zero in X, we need not do anything. */
6766 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6772 /* If X is a (clobber (const_int)), return it since we know we are
6773 generating something that won't match. */
6777 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6778 spanned the boundary of the MEM. If we are now masking so it is
6779 within that boundary, we don't need the USE any more. */
6780 if (! BITS_BIG_ENDIAN
6781 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6782 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6789 x
= expand_compound_operation (x
);
6790 if (GET_CODE (x
) != code
)
6791 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6795 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6796 || rtx_equal_p (reg
, get_last_value (x
))))
6801 if (subreg_lowpart_p (x
)
6802 /* We can ignore the effect of this SUBREG if it narrows the mode or
6803 if the constant masks to zero all the bits the mode doesn't
6805 && ((GET_MODE_SIZE (GET_MODE (x
))
6806 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6808 & GET_MODE_MASK (GET_MODE (x
))
6809 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6810 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6814 /* If this is an AND with a constant, convert it into an AND
6815 whose constant is the AND of that constant with MASK. If it
6816 remains an AND of MASK, delete it since it is redundant. */
6818 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6820 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6821 mask
& INTVAL (XEXP (x
, 1)));
6823 /* If X is still an AND, see if it is an AND with a mask that
6824 is just some low-order bits. If so, and it is MASK, we don't
6827 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6828 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6832 /* If it remains an AND, try making another AND with the bits
6833 in the mode mask that aren't in MASK turned on. If the
6834 constant in the AND is wide enough, this might make a
6835 cheaper constant. */
6837 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6838 && GET_MODE_MASK (GET_MODE (x
)) != mask
6839 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6841 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6842 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6843 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6846 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6847 number, sign extend it. */
6848 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6849 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6850 cval
|= (HOST_WIDE_INT
) -1 << width
;
6852 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6853 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6863 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6864 low-order bits (as in an alignment operation) and FOO is already
6865 aligned to that boundary, mask C1 to that boundary as well.
6866 This may eliminate that PLUS and, later, the AND. */
6869 unsigned int width
= GET_MODE_BITSIZE (mode
);
6870 unsigned HOST_WIDE_INT smask
= mask
;
6872 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6873 number, sign extend it. */
6875 if (width
< HOST_BITS_PER_WIDE_INT
6876 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6877 smask
|= (HOST_WIDE_INT
) -1 << width
;
6879 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6880 && exact_log2 (- smask
) >= 0
6881 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6882 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6883 return force_to_mode (plus_constant (XEXP (x
, 0),
6884 (INTVAL (XEXP (x
, 1)) & smask
)),
6885 mode
, smask
, reg
, next_select
);
6888 /* ... fall through ... */
6891 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6892 most significant bit in MASK since carries from those bits will
6893 affect the bits we are interested in. */
6898 /* If X is (minus C Y) where C's least set bit is larger than any bit
6899 in the mask, then we may replace with (neg Y). */
6900 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6901 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6902 & -INTVAL (XEXP (x
, 0))))
6905 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6907 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6910 /* Similarly, if C contains every bit in the fuller_mask, then we may
6911 replace with (not Y). */
6912 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6913 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6914 == INTVAL (XEXP (x
, 0))))
6916 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6917 XEXP (x
, 1), GET_MODE (x
));
6918 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6926 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6927 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6928 operation which may be a bitfield extraction. Ensure that the
6929 constant we form is not wider than the mode of X. */
6931 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6932 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6933 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6934 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6935 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6936 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6937 + floor_log2 (INTVAL (XEXP (x
, 1))))
6938 < GET_MODE_BITSIZE (GET_MODE (x
)))
6939 && (INTVAL (XEXP (x
, 1))
6940 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6942 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6943 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6944 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6945 XEXP (XEXP (x
, 0), 0), temp
);
6946 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6947 XEXP (XEXP (x
, 0), 1));
6948 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6952 /* For most binary operations, just propagate into the operation and
6953 change the mode if we have an operation of that mode. */
6955 op0
= gen_lowpart (op_mode
,
6956 force_to_mode (XEXP (x
, 0), mode
, mask
,
6958 op1
= gen_lowpart (op_mode
,
6959 force_to_mode (XEXP (x
, 1), mode
, mask
,
6962 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6963 x
= gen_binary (code
, op_mode
, op0
, op1
);
6967 /* For left shifts, do the same, but just for the first operand.
6968 However, we cannot do anything with shifts where we cannot
6969 guarantee that the counts are smaller than the size of the mode
6970 because such a count will have a different meaning in a
6973 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6974 && INTVAL (XEXP (x
, 1)) >= 0
6975 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6976 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6977 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6978 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6981 /* If the shift count is a constant and we can do arithmetic in
6982 the mode of the shift, refine which bits we need. Otherwise, use the
6983 conservative form of the mask. */
6984 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6985 && INTVAL (XEXP (x
, 1)) >= 0
6986 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6987 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6988 mask
>>= INTVAL (XEXP (x
, 1));
6992 op0
= gen_lowpart (op_mode
,
6993 force_to_mode (XEXP (x
, 0), op_mode
,
6994 mask
, reg
, next_select
));
6996 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6997 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7001 /* Here we can only do something if the shift count is a constant,
7002 this shift constant is valid for the host, and we can do arithmetic
7005 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7006 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7007 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7009 rtx inner
= XEXP (x
, 0);
7010 unsigned HOST_WIDE_INT inner_mask
;
7012 /* Select the mask of the bits we need for the shift operand. */
7013 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7015 /* We can only change the mode of the shift if we can do arithmetic
7016 in the mode of the shift and INNER_MASK is no wider than the
7017 width of OP_MODE. */
7018 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7019 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7020 op_mode
= GET_MODE (x
);
7022 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7024 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7025 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7028 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7029 shift and AND produces only copies of the sign bit (C2 is one less
7030 than a power of two), we can do this with just a shift. */
7032 if (GET_CODE (x
) == LSHIFTRT
7033 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7034 /* The shift puts one of the sign bit copies in the least significant
7036 && ((INTVAL (XEXP (x
, 1))
7037 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7038 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7039 && exact_log2 (mask
+ 1) >= 0
7040 /* Number of bits left after the shift must be more than the mask
7042 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7043 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7044 /* Must be more sign bit copies than the mask needs. */
7045 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7046 >= exact_log2 (mask
+ 1)))
7047 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7048 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7049 - exact_log2 (mask
+ 1)));
7054 /* If we are just looking for the sign bit, we don't need this shift at
7055 all, even if it has a variable count. */
7056 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7057 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7058 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7059 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7061 /* If this is a shift by a constant, get a mask that contains those bits
7062 that are not copies of the sign bit. We then have two cases: If
7063 MASK only includes those bits, this can be a logical shift, which may
7064 allow simplifications. If MASK is a single-bit field not within
7065 those bits, we are requesting a copy of the sign bit and hence can
7066 shift the sign bit to the appropriate location. */
7068 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7069 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7073 /* If the considered data is wider than HOST_WIDE_INT, we can't
7074 represent a mask for all its bits in a single scalar.
7075 But we only care about the lower bits, so calculate these. */
7077 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7079 nonzero
= ~(HOST_WIDE_INT
) 0;
7081 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7082 is the number of bits a full-width mask would have set.
7083 We need only shift if these are fewer than nonzero can
7084 hold. If not, we must keep all bits set in nonzero. */
7086 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7087 < HOST_BITS_PER_WIDE_INT
)
7088 nonzero
>>= INTVAL (XEXP (x
, 1))
7089 + HOST_BITS_PER_WIDE_INT
7090 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7094 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7095 nonzero
>>= INTVAL (XEXP (x
, 1));
7098 if ((mask
& ~nonzero
) == 0
7099 || (i
= exact_log2 (mask
)) >= 0)
7101 x
= simplify_shift_const
7102 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7103 i
< 0 ? INTVAL (XEXP (x
, 1))
7104 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7106 if (GET_CODE (x
) != ASHIFTRT
)
7107 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7111 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7112 even if the shift count isn't a constant. */
7114 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7118 /* If this is a zero- or sign-extension operation that just affects bits
7119 we don't care about, remove it. Be sure the call above returned
7120 something that is still a shift. */
7122 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7123 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7124 && INTVAL (XEXP (x
, 1)) >= 0
7125 && (INTVAL (XEXP (x
, 1))
7126 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7127 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7128 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7129 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7136 /* If the shift count is constant and we can do computations
7137 in the mode of X, compute where the bits we care about are.
7138 Otherwise, we can't do anything. Don't change the mode of
7139 the shift or propagate MODE into the shift, though. */
7140 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7141 && INTVAL (XEXP (x
, 1)) >= 0)
7143 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7144 GET_MODE (x
), GEN_INT (mask
),
7146 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7148 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7149 INTVAL (temp
), reg
, next_select
));
7154 /* If we just want the low-order bit, the NEG isn't needed since it
7155 won't change the low-order bit. */
7157 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7159 /* We need any bits less significant than the most significant bit in
7160 MASK since carries from those bits will affect the bits we are
7166 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7167 same as the XOR case above. Ensure that the constant we form is not
7168 wider than the mode of X. */
7170 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7171 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7172 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7173 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7174 < GET_MODE_BITSIZE (GET_MODE (x
)))
7175 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7177 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7179 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7180 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7182 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7185 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7186 use the full mask inside the NOT. */
7190 op0
= gen_lowpart (op_mode
,
7191 force_to_mode (XEXP (x
, 0), mode
, mask
,
7193 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7194 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7198 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7199 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7200 which is equal to STORE_FLAG_VALUE. */
7201 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7202 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7203 && (nonzero_bits (XEXP (x
, 0), mode
)
7204 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7205 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7210 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7211 written in a narrower mode. We play it safe and do not do so. */
7214 gen_lowpart (GET_MODE (x
),
7215 force_to_mode (XEXP (x
, 1), mode
,
7216 mask
, reg
, next_select
)));
7218 gen_lowpart (GET_MODE (x
),
7219 force_to_mode (XEXP (x
, 2), mode
,
7220 mask
, reg
, next_select
)));
7227 /* Ensure we return a value of the proper mode. */
7228 return gen_lowpart (mode
, x
);
7231 /* Return nonzero if X is an expression that has one of two values depending on
7232 whether some other value is zero or nonzero. In that case, we return the
7233 value that is being tested, *PTRUE is set to the value if the rtx being
7234 returned has a nonzero value, and *PFALSE is set to the other alternative.
7236 If we return zero, we set *PTRUE and *PFALSE to X. */
7239 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7241 enum machine_mode mode
= GET_MODE (x
);
7242 enum rtx_code code
= GET_CODE (x
);
7243 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7244 unsigned HOST_WIDE_INT nz
;
7246 /* If we are comparing a value against zero, we are done. */
7247 if ((code
== NE
|| code
== EQ
)
7248 && XEXP (x
, 1) == const0_rtx
)
7250 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7251 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7255 /* If this is a unary operation whose operand has one of two values, apply
7256 our opcode to compute those values. */
7257 else if (UNARY_P (x
)
7258 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7260 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7261 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7262 GET_MODE (XEXP (x
, 0)));
7266 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7267 make can't possibly match and would suppress other optimizations. */
7268 else if (code
== COMPARE
)
7271 /* If this is a binary operation, see if either side has only one of two
7272 values. If either one does or if both do and they are conditional on
7273 the same value, compute the new true and false values. */
7274 else if (BINARY_P (x
))
7276 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7277 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7279 if ((cond0
!= 0 || cond1
!= 0)
7280 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7282 /* If if_then_else_cond returned zero, then true/false are the
7283 same rtl. We must copy one of them to prevent invalid rtl
7286 true0
= copy_rtx (true0
);
7287 else if (cond1
== 0)
7288 true1
= copy_rtx (true1
);
7290 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7291 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7292 return cond0
? cond0
: cond1
;
7295 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7296 operands is zero when the other is nonzero, and vice-versa,
7297 and STORE_FLAG_VALUE is 1 or -1. */
7299 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7300 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7302 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7304 rtx op0
= XEXP (XEXP (x
, 0), 1);
7305 rtx op1
= XEXP (XEXP (x
, 1), 1);
7307 cond0
= XEXP (XEXP (x
, 0), 0);
7308 cond1
= XEXP (XEXP (x
, 1), 0);
7310 if (COMPARISON_P (cond0
)
7311 && COMPARISON_P (cond1
)
7312 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7313 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7314 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7315 || ((swap_condition (GET_CODE (cond0
))
7316 == combine_reversed_comparison_code (cond1
))
7317 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7318 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7319 && ! side_effects_p (x
))
7321 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7322 *pfalse
= gen_binary (MULT
, mode
,
7324 ? simplify_gen_unary (NEG
, mode
, op1
,
7332 /* Similarly for MULT, AND and UMIN, except that for these the result
7334 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7335 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7336 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7338 cond0
= XEXP (XEXP (x
, 0), 0);
7339 cond1
= XEXP (XEXP (x
, 1), 0);
7341 if (COMPARISON_P (cond0
)
7342 && COMPARISON_P (cond1
)
7343 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7344 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7345 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7346 || ((swap_condition (GET_CODE (cond0
))
7347 == combine_reversed_comparison_code (cond1
))
7348 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7349 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7350 && ! side_effects_p (x
))
7352 *ptrue
= *pfalse
= const0_rtx
;
7358 else if (code
== IF_THEN_ELSE
)
7360 /* If we have IF_THEN_ELSE already, extract the condition and
7361 canonicalize it if it is NE or EQ. */
7362 cond0
= XEXP (x
, 0);
7363 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7364 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7365 return XEXP (cond0
, 0);
7366 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7368 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7369 return XEXP (cond0
, 0);
7375 /* If X is a SUBREG, we can narrow both the true and false values
7376 if the inner expression, if there is a condition. */
7377 else if (code
== SUBREG
7378 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7381 true0
= simplify_gen_subreg (mode
, true0
,
7382 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7383 false0
= simplify_gen_subreg (mode
, false0
,
7384 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7385 if (true0
&& false0
)
7393 /* If X is a constant, this isn't special and will cause confusions
7394 if we treat it as such. Likewise if it is equivalent to a constant. */
7395 else if (CONSTANT_P (x
)
7396 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7399 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7400 will be least confusing to the rest of the compiler. */
7401 else if (mode
== BImode
)
7403 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7407 /* If X is known to be either 0 or -1, those are the true and
7408 false values when testing X. */
7409 else if (x
== constm1_rtx
|| x
== const0_rtx
7410 || (mode
!= VOIDmode
7411 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7413 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7417 /* Likewise for 0 or a single bit. */
7418 else if (SCALAR_INT_MODE_P (mode
)
7419 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7420 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7422 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7426 /* Otherwise fail; show no condition with true and false values the same. */
7427 *ptrue
= *pfalse
= x
;
7431 /* Return the value of expression X given the fact that condition COND
7432 is known to be true when applied to REG as its first operand and VAL
7433 as its second. X is known to not be shared and so can be modified in
7436 We only handle the simplest cases, and specifically those cases that
7437 arise with IF_THEN_ELSE expressions. */
7440 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7442 enum rtx_code code
= GET_CODE (x
);
7447 if (side_effects_p (x
))
7450 /* If either operand of the condition is a floating point value,
7451 then we have to avoid collapsing an EQ comparison. */
7453 && rtx_equal_p (x
, reg
)
7454 && ! FLOAT_MODE_P (GET_MODE (x
))
7455 && ! FLOAT_MODE_P (GET_MODE (val
)))
7458 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7461 /* If X is (abs REG) and we know something about REG's relationship
7462 with zero, we may be able to simplify this. */
7464 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7467 case GE
: case GT
: case EQ
:
7470 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7472 GET_MODE (XEXP (x
, 0)));
7477 /* The only other cases we handle are MIN, MAX, and comparisons if the
7478 operands are the same as REG and VAL. */
7480 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7482 if (rtx_equal_p (XEXP (x
, 0), val
))
7483 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7485 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7487 if (COMPARISON_P (x
))
7489 if (comparison_dominates_p (cond
, code
))
7490 return const_true_rtx
;
7492 code
= combine_reversed_comparison_code (x
);
7494 && comparison_dominates_p (cond
, code
))
7499 else if (code
== SMAX
|| code
== SMIN
7500 || code
== UMIN
|| code
== UMAX
)
7502 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7504 /* Do not reverse the condition when it is NE or EQ.
7505 This is because we cannot conclude anything about
7506 the value of 'SMAX (x, y)' when x is not equal to y,
7507 but we can when x equals y. */
7508 if ((code
== SMAX
|| code
== UMAX
)
7509 && ! (cond
== EQ
|| cond
== NE
))
7510 cond
= reverse_condition (cond
);
7515 return unsignedp
? x
: XEXP (x
, 1);
7517 return unsignedp
? x
: XEXP (x
, 0);
7519 return unsignedp
? XEXP (x
, 1) : x
;
7521 return unsignedp
? XEXP (x
, 0) : x
;
7528 else if (code
== SUBREG
)
7530 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7531 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7533 if (SUBREG_REG (x
) != r
)
7535 /* We must simplify subreg here, before we lose track of the
7536 original inner_mode. */
7537 new = simplify_subreg (GET_MODE (x
), r
,
7538 inner_mode
, SUBREG_BYTE (x
));
7542 SUBST (SUBREG_REG (x
), r
);
7547 /* We don't have to handle SIGN_EXTEND here, because even in the
7548 case of replacing something with a modeless CONST_INT, a
7549 CONST_INT is already (supposed to be) a valid sign extension for
7550 its narrower mode, which implies it's already properly
7551 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7552 story is different. */
7553 else if (code
== ZERO_EXTEND
)
7555 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7556 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7558 if (XEXP (x
, 0) != r
)
7560 /* We must simplify the zero_extend here, before we lose
7561 track of the original inner_mode. */
7562 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7567 SUBST (XEXP (x
, 0), r
);
7573 fmt
= GET_RTX_FORMAT (code
);
7574 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7577 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7578 else if (fmt
[i
] == 'E')
7579 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7580 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7587 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7588 assignment as a field assignment. */
7591 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7593 if (x
== y
|| rtx_equal_p (x
, y
))
7596 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7599 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7600 Note that all SUBREGs of MEM are paradoxical; otherwise they
7601 would have been rewritten. */
7602 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7603 && GET_CODE (SUBREG_REG (y
)) == MEM
7604 && rtx_equal_p (SUBREG_REG (y
),
7605 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7608 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7609 && GET_CODE (SUBREG_REG (x
)) == MEM
7610 && rtx_equal_p (SUBREG_REG (x
),
7611 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7614 /* We used to see if get_last_value of X and Y were the same but that's
7615 not correct. In one direction, we'll cause the assignment to have
7616 the wrong destination and in the case, we'll import a register into this
7617 insn that might have already have been dead. So fail if none of the
7618 above cases are true. */
7622 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7623 Return that assignment if so.
7625 We only handle the most common cases. */
7628 make_field_assignment (rtx x
)
7630 rtx dest
= SET_DEST (x
);
7631 rtx src
= SET_SRC (x
);
7636 unsigned HOST_WIDE_INT len
;
7638 enum machine_mode mode
;
7640 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7641 a clear of a one-bit field. We will have changed it to
7642 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7645 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7646 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7647 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7648 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7650 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7653 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7657 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7658 && subreg_lowpart_p (XEXP (src
, 0))
7659 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7660 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7661 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7662 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7663 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7664 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7666 assign
= make_extraction (VOIDmode
, dest
, 0,
7667 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7670 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7674 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7676 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7677 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7678 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7680 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7683 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7687 /* The other case we handle is assignments into a constant-position
7688 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7689 a mask that has all one bits except for a group of zero bits and
7690 OTHER is known to have zeros where C1 has ones, this is such an
7691 assignment. Compute the position and length from C1. Shift OTHER
7692 to the appropriate position, force it to the required mode, and
7693 make the extraction. Check for the AND in both operands. */
7695 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7698 rhs
= expand_compound_operation (XEXP (src
, 0));
7699 lhs
= expand_compound_operation (XEXP (src
, 1));
7701 if (GET_CODE (rhs
) == AND
7702 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7703 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7704 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7705 else if (GET_CODE (lhs
) == AND
7706 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7707 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7708 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7712 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7713 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7714 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7715 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7718 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7722 /* The mode to use for the source is the mode of the assignment, or of
7723 what is inside a possible STRICT_LOW_PART. */
7724 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7725 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7727 /* Shift OTHER right POS places and make it the source, restricting it
7728 to the proper length and mode. */
7730 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7731 GET_MODE (src
), other
, pos
),
7733 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7734 ? ~(unsigned HOST_WIDE_INT
) 0
7735 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7738 /* If SRC is masked by an AND that does not make a difference in
7739 the value being stored, strip it. */
7740 if (GET_CODE (assign
) == ZERO_EXTRACT
7741 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7742 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7743 && GET_CODE (src
) == AND
7744 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7745 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7746 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7747 src
= XEXP (src
, 0);
7749 return gen_rtx_SET (VOIDmode
, assign
, src
);
7752 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7756 apply_distributive_law (rtx x
)
7758 enum rtx_code code
= GET_CODE (x
);
7759 enum rtx_code inner_code
;
7760 rtx lhs
, rhs
, other
;
7763 /* Distributivity is not true for floating point as it can change the
7764 value. So we don't do it unless -funsafe-math-optimizations. */
7765 if (FLOAT_MODE_P (GET_MODE (x
))
7766 && ! flag_unsafe_math_optimizations
)
7769 /* The outer operation can only be one of the following: */
7770 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7771 && code
!= PLUS
&& code
!= MINUS
)
7777 /* If either operand is a primitive we can't do anything, so get out
7779 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7782 lhs
= expand_compound_operation (lhs
);
7783 rhs
= expand_compound_operation (rhs
);
7784 inner_code
= GET_CODE (lhs
);
7785 if (inner_code
!= GET_CODE (rhs
))
7788 /* See if the inner and outer operations distribute. */
7795 /* These all distribute except over PLUS. */
7796 if (code
== PLUS
|| code
== MINUS
)
7801 if (code
!= PLUS
&& code
!= MINUS
)
7806 /* This is also a multiply, so it distributes over everything. */
7810 /* Non-paradoxical SUBREGs distributes over all operations, provided
7811 the inner modes and byte offsets are the same, this is an extraction
7812 of a low-order part, we don't convert an fp operation to int or
7813 vice versa, and we would not be converting a single-word
7814 operation into a multi-word operation. The latter test is not
7815 required, but it prevents generating unneeded multi-word operations.
7816 Some of the previous tests are redundant given the latter test, but
7817 are retained because they are required for correctness.
7819 We produce the result slightly differently in this case. */
7821 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7822 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7823 || ! subreg_lowpart_p (lhs
)
7824 || (GET_MODE_CLASS (GET_MODE (lhs
))
7825 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7826 || (GET_MODE_SIZE (GET_MODE (lhs
))
7827 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7828 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7831 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7832 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7833 return gen_lowpart (GET_MODE (x
), tem
);
7839 /* Set LHS and RHS to the inner operands (A and B in the example
7840 above) and set OTHER to the common operand (C in the example).
7841 There is only one way to do this unless the inner operation is
7843 if (COMMUTATIVE_ARITH_P (lhs
)
7844 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7845 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7846 else if (COMMUTATIVE_ARITH_P (lhs
)
7847 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7848 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7849 else if (COMMUTATIVE_ARITH_P (lhs
)
7850 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7851 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7852 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7853 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7857 /* Form the new inner operation, seeing if it simplifies first. */
7858 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7860 /* There is one exception to the general way of distributing:
7861 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7862 if (code
== XOR
&& inner_code
== IOR
)
7865 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7868 /* We may be able to continuing distributing the result, so call
7869 ourselves recursively on the inner operation before forming the
7870 outer operation, which we return. */
7871 return gen_binary (inner_code
, GET_MODE (x
),
7872 apply_distributive_law (tem
), other
);
7875 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7878 Return an equivalent form, if different from X. Otherwise, return X. If
7879 X is zero, we are to always construct the equivalent form. */
7882 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7883 unsigned HOST_WIDE_INT constop
)
7885 unsigned HOST_WIDE_INT nonzero
;
7888 /* Simplify VAROP knowing that we will be only looking at some of the
7891 Note by passing in CONSTOP, we guarantee that the bits not set in
7892 CONSTOP are not significant and will never be examined. We must
7893 ensure that is the case by explicitly masking out those bits
7894 before returning. */
7895 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7897 /* If VAROP is a CLOBBER, we will fail so return it. */
7898 if (GET_CODE (varop
) == CLOBBER
)
7901 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7902 to VAROP and return the new constant. */
7903 if (GET_CODE (varop
) == CONST_INT
)
7904 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7906 /* See what bits may be nonzero in VAROP. Unlike the general case of
7907 a call to nonzero_bits, here we don't care about bits outside
7910 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7912 /* Turn off all bits in the constant that are known to already be zero.
7913 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7914 which is tested below. */
7918 /* If we don't have any bits left, return zero. */
7922 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7923 a power of two, we can replace this with an ASHIFT. */
7924 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7925 && (i
= exact_log2 (constop
)) >= 0)
7926 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7928 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7929 or XOR, then try to apply the distributive law. This may eliminate
7930 operations if either branch can be simplified because of the AND.
7931 It may also make some cases more complex, but those cases probably
7932 won't match a pattern either with or without this. */
7934 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7938 apply_distributive_law
7939 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7940 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7941 XEXP (varop
, 0), constop
),
7942 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7943 XEXP (varop
, 1), constop
))));
7945 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7946 the AND and see if one of the operands simplifies to zero. If so, we
7947 may eliminate it. */
7949 if (GET_CODE (varop
) == PLUS
7950 && exact_log2 (constop
+ 1) >= 0)
7954 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7955 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7956 if (o0
== const0_rtx
)
7958 if (o1
== const0_rtx
)
7962 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7963 if we already had one (just check for the simplest cases). */
7964 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7965 && GET_MODE (XEXP (x
, 0)) == mode
7966 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7967 varop
= XEXP (x
, 0);
7969 varop
= gen_lowpart (mode
, varop
);
7971 /* If we can't make the SUBREG, try to return what we were given. */
7972 if (GET_CODE (varop
) == CLOBBER
)
7973 return x
? x
: varop
;
7975 /* If we are only masking insignificant bits, return VAROP. */
7976 if (constop
== nonzero
)
7980 /* Otherwise, return an AND. */
7981 constop
= trunc_int_for_mode (constop
, mode
);
7982 /* See how much, if any, of X we can use. */
7983 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7984 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7988 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7989 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7990 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7992 SUBST (XEXP (x
, 0), varop
);
7999 #define nonzero_bits_with_known(X, MODE) \
8000 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8002 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8003 It avoids exponential behavior in nonzero_bits1 when X has
8004 identical subexpressions on the first or the second level. */
8006 static unsigned HOST_WIDE_INT
8007 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8008 enum machine_mode known_mode
,
8009 unsigned HOST_WIDE_INT known_ret
)
8011 if (x
== known_x
&& mode
== known_mode
)
8014 /* Try to find identical subexpressions. If found call
8015 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8016 precomputed value for the subexpression as KNOWN_RET. */
8018 if (ARITHMETIC_P (x
))
8020 rtx x0
= XEXP (x
, 0);
8021 rtx x1
= XEXP (x
, 1);
8023 /* Check the first level. */
8025 return nonzero_bits1 (x
, mode
, x0
, mode
,
8026 nonzero_bits_with_known (x0
, mode
));
8028 /* Check the second level. */
8029 if (ARITHMETIC_P (x0
)
8030 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8031 return nonzero_bits1 (x
, mode
, x1
, mode
,
8032 nonzero_bits_with_known (x1
, mode
));
8034 if (ARITHMETIC_P (x1
)
8035 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8036 return nonzero_bits1 (x
, mode
, x0
, mode
,
8037 nonzero_bits_with_known (x0
, mode
));
8040 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8043 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8044 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8045 is less useful. We can't allow both, because that results in exponential
8046 run time recursion. There is a nullstone testcase that triggered
8047 this. This macro avoids accidental uses of num_sign_bit_copies. */
8048 #define cached_num_sign_bit_copies()
8050 /* Given an expression, X, compute which bits in X can be nonzero.
8051 We don't care about bits outside of those defined in MODE.
8053 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8054 a shift, AND, or zero_extract, we can do better. */
8056 static unsigned HOST_WIDE_INT
8057 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8058 enum machine_mode known_mode
,
8059 unsigned HOST_WIDE_INT known_ret
)
8061 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8062 unsigned HOST_WIDE_INT inner_nz
;
8064 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8067 /* For floating-point values, assume all bits are needed. */
8068 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8071 /* If X is wider than MODE, use its mode instead. */
8072 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8074 mode
= GET_MODE (x
);
8075 nonzero
= GET_MODE_MASK (mode
);
8076 mode_width
= GET_MODE_BITSIZE (mode
);
8079 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8080 /* Our only callers in this case look for single bit values. So
8081 just return the mode mask. Those tests will then be false. */
8084 #ifndef WORD_REGISTER_OPERATIONS
8085 /* If MODE is wider than X, but both are a single word for both the host
8086 and target machines, we can compute this from which bits of the
8087 object might be nonzero in its own mode, taking into account the fact
8088 that on many CISC machines, accessing an object in a wider mode
8089 causes the high-order bits to become undefined. So they are
8090 not known to be zero. */
8092 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8093 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8094 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8095 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8097 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8098 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8103 code
= GET_CODE (x
);
8107 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8108 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8109 all the bits above ptr_mode are known to be zero. */
8110 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8112 nonzero
&= GET_MODE_MASK (ptr_mode
);
8115 /* Include declared information about alignment of pointers. */
8116 /* ??? We don't properly preserve REG_POINTER changes across
8117 pointer-to-integer casts, so we can't trust it except for
8118 things that we know must be pointers. See execute/960116-1.c. */
8119 if ((x
== stack_pointer_rtx
8120 || x
== frame_pointer_rtx
8121 || x
== arg_pointer_rtx
)
8122 && REGNO_POINTER_ALIGN (REGNO (x
)))
8124 unsigned HOST_WIDE_INT alignment
8125 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8127 #ifdef PUSH_ROUNDING
8128 /* If PUSH_ROUNDING is defined, it is possible for the
8129 stack to be momentarily aligned only to that amount,
8130 so we pick the least alignment. */
8131 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8132 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8136 nonzero
&= ~(alignment
- 1);
8139 /* If X is a register whose nonzero bits value is current, use it.
8140 Otherwise, if X is a register whose value we can find, use that
8141 value. Otherwise, use the previously-computed global nonzero bits
8142 for this register. */
8144 if (reg_last_set_value
[REGNO (x
)] != 0
8145 && (reg_last_set_mode
[REGNO (x
)] == mode
8146 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8147 && GET_MODE_CLASS (mode
) == MODE_INT
))
8148 && (reg_last_set_label
[REGNO (x
)] == label_tick
8149 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8150 && REG_N_SETS (REGNO (x
)) == 1
8151 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8153 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8154 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8156 tem
= get_last_value (x
);
8160 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8161 /* If X is narrower than MODE and TEM is a non-negative
8162 constant that would appear negative in the mode of X,
8163 sign-extend it for use in reg_nonzero_bits because some
8164 machines (maybe most) will actually do the sign-extension
8165 and this is the conservative approach.
8167 ??? For 2.5, try to tighten up the MD files in this regard
8168 instead of this kludge. */
8170 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8171 && GET_CODE (tem
) == CONST_INT
8173 && 0 != (INTVAL (tem
)
8174 & ((HOST_WIDE_INT
) 1
8175 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8176 tem
= GEN_INT (INTVAL (tem
)
8177 | ((HOST_WIDE_INT
) (-1)
8178 << GET_MODE_BITSIZE (GET_MODE (x
))));
8180 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8182 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8184 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8186 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8187 /* We don't know anything about the upper bits. */
8188 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8189 return nonzero
& mask
;
8195 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8196 /* If X is negative in MODE, sign-extend the value. */
8197 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8198 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8199 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8205 #ifdef LOAD_EXTEND_OP
8206 /* In many, if not most, RISC machines, reading a byte from memory
8207 zeros the rest of the register. Noticing that fact saves a lot
8208 of extra zero-extends. */
8209 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8210 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8215 case UNEQ
: case LTGT
:
8216 case GT
: case GTU
: case UNGT
:
8217 case LT
: case LTU
: case UNLT
:
8218 case GE
: case GEU
: case UNGE
:
8219 case LE
: case LEU
: case UNLE
:
8220 case UNORDERED
: case ORDERED
:
8222 /* If this produces an integer result, we know which bits are set.
8223 Code here used to clear bits outside the mode of X, but that is
8226 if (GET_MODE_CLASS (mode
) == MODE_INT
8227 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8228 nonzero
= STORE_FLAG_VALUE
;
8233 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8234 and num_sign_bit_copies. */
8235 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8236 == GET_MODE_BITSIZE (GET_MODE (x
)))
8240 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8241 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8246 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8247 and num_sign_bit_copies. */
8248 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8249 == GET_MODE_BITSIZE (GET_MODE (x
)))
8255 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8256 & GET_MODE_MASK (mode
));
8260 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8261 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8262 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8266 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8267 Otherwise, show all the bits in the outer mode but not the inner
8269 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8270 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8272 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8274 & (((HOST_WIDE_INT
) 1
8275 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8276 inner_nz
|= (GET_MODE_MASK (mode
)
8277 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8280 nonzero
&= inner_nz
;
8284 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8285 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8289 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8291 unsigned HOST_WIDE_INT nonzero0
=
8292 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8294 /* Don't call nonzero_bits for the second time if it cannot change
8296 if ((nonzero
& nonzero0
) != nonzero
)
8297 nonzero
&= (nonzero0
8298 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8302 case PLUS
: case MINUS
:
8304 case DIV
: case UDIV
:
8305 case MOD
: case UMOD
:
8306 /* We can apply the rules of arithmetic to compute the number of
8307 high- and low-order zero bits of these operations. We start by
8308 computing the width (position of the highest-order nonzero bit)
8309 and the number of low-order zero bits for each value. */
8311 unsigned HOST_WIDE_INT nz0
=
8312 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8313 unsigned HOST_WIDE_INT nz1
=
8314 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8315 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8316 int width0
= floor_log2 (nz0
) + 1;
8317 int width1
= floor_log2 (nz1
) + 1;
8318 int low0
= floor_log2 (nz0
& -nz0
);
8319 int low1
= floor_log2 (nz1
& -nz1
);
8320 HOST_WIDE_INT op0_maybe_minusp
8321 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8322 HOST_WIDE_INT op1_maybe_minusp
8323 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8324 unsigned int result_width
= mode_width
;
8330 result_width
= MAX (width0
, width1
) + 1;
8331 result_low
= MIN (low0
, low1
);
8334 result_low
= MIN (low0
, low1
);
8337 result_width
= width0
+ width1
;
8338 result_low
= low0
+ low1
;
8343 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8344 result_width
= width0
;
8349 result_width
= width0
;
8354 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8355 result_width
= MIN (width0
, width1
);
8356 result_low
= MIN (low0
, low1
);
8361 result_width
= MIN (width0
, width1
);
8362 result_low
= MIN (low0
, low1
);
8368 if (result_width
< mode_width
)
8369 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8372 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8374 #ifdef POINTERS_EXTEND_UNSIGNED
8375 /* If pointers extend unsigned and this is an addition or subtraction
8376 to a pointer in Pmode, all the bits above ptr_mode are known to be
8378 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8379 && (code
== PLUS
|| code
== MINUS
)
8380 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8381 nonzero
&= GET_MODE_MASK (ptr_mode
);
8387 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8388 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8389 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8393 /* If this is a SUBREG formed for a promoted variable that has
8394 been zero-extended, we know that at least the high-order bits
8395 are zero, though others might be too. */
8397 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8398 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8399 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8401 /* If the inner mode is a single word for both the host and target
8402 machines, we can compute this from which bits of the inner
8403 object might be nonzero. */
8404 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8405 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8406 <= HOST_BITS_PER_WIDE_INT
))
8408 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8410 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8411 /* If this is a typical RISC machine, we only have to worry
8412 about the way loads are extended. */
8413 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8415 & (((unsigned HOST_WIDE_INT
) 1
8416 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8418 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8419 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8422 /* On many CISC machines, accessing an object in a wider mode
8423 causes the high-order bits to become undefined. So they are
8424 not known to be zero. */
8425 if (GET_MODE_SIZE (GET_MODE (x
))
8426 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8427 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8428 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8437 /* The nonzero bits are in two classes: any bits within MODE
8438 that aren't in GET_MODE (x) are always significant. The rest of the
8439 nonzero bits are those that are significant in the operand of
8440 the shift when shifted the appropriate number of bits. This
8441 shows that high-order bits are cleared by the right shift and
8442 low-order bits by left shifts. */
8443 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8444 && INTVAL (XEXP (x
, 1)) >= 0
8445 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8447 enum machine_mode inner_mode
= GET_MODE (x
);
8448 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8449 int count
= INTVAL (XEXP (x
, 1));
8450 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8451 unsigned HOST_WIDE_INT op_nonzero
=
8452 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8453 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8454 unsigned HOST_WIDE_INT outer
= 0;
8456 if (mode_width
> width
)
8457 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8459 if (code
== LSHIFTRT
)
8461 else if (code
== ASHIFTRT
)
8465 /* If the sign bit may have been nonzero before the shift, we
8466 need to mark all the places it could have been copied to
8467 by the shift as possibly nonzero. */
8468 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8469 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8471 else if (code
== ASHIFT
)
8474 inner
= ((inner
<< (count
% width
)
8475 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8477 nonzero
&= (outer
| inner
);
8483 /* This is at most the number of bits in the mode. */
8484 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8488 /* If CLZ has a known value at zero, then the nonzero bits are
8489 that value, plus the number of bits in the mode minus one. */
8490 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8491 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8497 /* If CTZ has a known value at zero, then the nonzero bits are
8498 that value, plus the number of bits in the mode minus one. */
8499 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8500 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8510 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8511 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8521 /* See the macro definition above. */
8522 #undef cached_num_sign_bit_copies
8524 #define num_sign_bit_copies_with_known(X, M) \
8525 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8527 /* The function cached_num_sign_bit_copies is a wrapper around
8528 num_sign_bit_copies1. It avoids exponential behavior in
8529 num_sign_bit_copies1 when X has identical subexpressions on the
8530 first or the second level. */
8533 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8534 enum machine_mode known_mode
,
8535 unsigned int known_ret
)
8537 if (x
== known_x
&& mode
== known_mode
)
8540 /* Try to find identical subexpressions. If found call
8541 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8542 the precomputed value for the subexpression as KNOWN_RET. */
8544 if (ARITHMETIC_P (x
))
8546 rtx x0
= XEXP (x
, 0);
8547 rtx x1
= XEXP (x
, 1);
8549 /* Check the first level. */
8552 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8553 num_sign_bit_copies_with_known (x0
, mode
));
8555 /* Check the second level. */
8556 if (ARITHMETIC_P (x0
)
8557 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8559 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8560 num_sign_bit_copies_with_known (x1
, mode
));
8562 if (ARITHMETIC_P (x1
)
8563 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8565 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8566 num_sign_bit_copies_with_known (x0
, mode
));
8569 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8572 /* Return the number of bits at the high-order end of X that are known to
8573 be equal to the sign bit. X will be used in mode MODE; if MODE is
8574 VOIDmode, X will be used in its own mode. The returned value will always
8575 be between 1 and the number of bits in MODE. */
8578 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8579 enum machine_mode known_mode
,
8580 unsigned int known_ret
)
8582 enum rtx_code code
= GET_CODE (x
);
8583 unsigned int bitwidth
;
8584 int num0
, num1
, result
;
8585 unsigned HOST_WIDE_INT nonzero
;
8588 /* If we weren't given a mode, use the mode of X. If the mode is still
8589 VOIDmode, we don't know anything. Likewise if one of the modes is
8592 if (mode
== VOIDmode
)
8593 mode
= GET_MODE (x
);
8595 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8598 bitwidth
= GET_MODE_BITSIZE (mode
);
8600 /* For a smaller object, just ignore the high bits. */
8601 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8603 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8605 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8608 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8610 #ifndef WORD_REGISTER_OPERATIONS
8611 /* If this machine does not do all register operations on the entire
8612 register and MODE is wider than the mode of X, we can say nothing
8613 at all about the high-order bits. */
8616 /* Likewise on machines that do, if the mode of the object is smaller
8617 than a word and loads of that size don't sign extend, we can say
8618 nothing about the high order bits. */
8619 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8620 #ifdef LOAD_EXTEND_OP
8621 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8632 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8633 /* If pointers extend signed and this is a pointer in Pmode, say that
8634 all the bits above ptr_mode are known to be sign bit copies. */
8635 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8637 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8640 if (reg_last_set_value
[REGNO (x
)] != 0
8641 && reg_last_set_mode
[REGNO (x
)] == mode
8642 && (reg_last_set_label
[REGNO (x
)] == label_tick
8643 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8644 && REG_N_SETS (REGNO (x
)) == 1
8645 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8647 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8648 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8650 tem
= get_last_value (x
);
8652 return num_sign_bit_copies_with_known (tem
, mode
);
8654 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8655 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8656 return reg_sign_bit_copies
[REGNO (x
)];
8660 #ifdef LOAD_EXTEND_OP
8661 /* Some RISC machines sign-extend all loads of smaller than a word. */
8662 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8663 return MAX (1, ((int) bitwidth
8664 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8669 /* If the constant is negative, take its 1's complement and remask.
8670 Then see how many zero bits we have. */
8671 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8672 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8673 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8674 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8676 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8679 /* If this is a SUBREG for a promoted object that is sign-extended
8680 and we are looking at it in a wider mode, we know that at least the
8681 high-order bits are known to be sign bit copies. */
8683 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8685 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8686 return MAX ((int) bitwidth
8687 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8691 /* For a smaller object, just ignore the high bits. */
8692 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8694 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8695 return MAX (1, (num0
8696 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8700 #ifdef WORD_REGISTER_OPERATIONS
8701 #ifdef LOAD_EXTEND_OP
8702 /* For paradoxical SUBREGs on machines where all register operations
8703 affect the entire register, just look inside. Note that we are
8704 passing MODE to the recursive call, so the number of sign bit copies
8705 will remain relative to that mode, not the inner mode. */
8707 /* This works only if loads sign extend. Otherwise, if we get a
8708 reload for the inner part, it may be loaded from the stack, and
8709 then we lose all sign bit copies that existed before the store
8712 if ((GET_MODE_SIZE (GET_MODE (x
))
8713 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8714 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8715 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8716 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8722 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8723 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8727 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8728 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8731 /* For a smaller object, just ignore the high bits. */
8732 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8733 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8737 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8739 case ROTATE
: case ROTATERT
:
8740 /* If we are rotating left by a number of bits less than the number
8741 of sign bit copies, we can just subtract that amount from the
8743 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8744 && INTVAL (XEXP (x
, 1)) >= 0
8745 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8747 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8748 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8749 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8754 /* In general, this subtracts one sign bit copy. But if the value
8755 is known to be positive, the number of sign bit copies is the
8756 same as that of the input. Finally, if the input has just one bit
8757 that might be nonzero, all the bits are copies of the sign bit. */
8758 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8759 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8760 return num0
> 1 ? num0
- 1 : 1;
8762 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8767 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8772 case IOR
: case AND
: case XOR
:
8773 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8774 /* Logical operations will preserve the number of sign-bit copies.
8775 MIN and MAX operations always return one of the operands. */
8776 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8777 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8778 return MIN (num0
, num1
);
8780 case PLUS
: case MINUS
:
8781 /* For addition and subtraction, we can have a 1-bit carry. However,
8782 if we are subtracting 1 from a positive number, there will not
8783 be such a carry. Furthermore, if the positive number is known to
8784 be 0 or 1, we know the result is either -1 or 0. */
8786 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8787 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8789 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8790 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8791 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8792 : bitwidth
- floor_log2 (nonzero
) - 1);
8795 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8796 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8797 result
= MAX (1, MIN (num0
, num1
) - 1);
8799 #ifdef POINTERS_EXTEND_UNSIGNED
8800 /* If pointers extend signed and this is an addition or subtraction
8801 to a pointer in Pmode, all the bits above ptr_mode are known to be
8803 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8804 && (code
== PLUS
|| code
== MINUS
)
8805 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8806 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8807 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8813 /* The number of bits of the product is the sum of the number of
8814 bits of both terms. However, unless one of the terms if known
8815 to be positive, we must allow for an additional bit since negating
8816 a negative number can remove one sign bit copy. */
8818 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8819 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8821 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8823 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8824 || (((nonzero_bits (XEXP (x
, 0), mode
)
8825 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8826 && ((nonzero_bits (XEXP (x
, 1), mode
)
8827 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8830 return MAX (1, result
);
8833 /* The result must be <= the first operand. If the first operand
8834 has the high bit set, we know nothing about the number of sign
8836 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8838 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8839 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8842 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8845 /* The result must be <= the second operand. */
8846 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8849 /* Similar to unsigned division, except that we have to worry about
8850 the case where the divisor is negative, in which case we have
8852 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8854 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8855 || (nonzero_bits (XEXP (x
, 1), mode
)
8856 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8862 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8864 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8865 || (nonzero_bits (XEXP (x
, 1), mode
)
8866 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8872 /* Shifts by a constant add to the number of bits equal to the
8874 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8875 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8876 && INTVAL (XEXP (x
, 1)) > 0)
8877 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8882 /* Left shifts destroy copies. */
8883 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8884 || INTVAL (XEXP (x
, 1)) < 0
8885 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8888 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8889 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8892 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8893 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8894 return MIN (num0
, num1
);
8896 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8897 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8898 case GEU
: case GTU
: case LEU
: case LTU
:
8899 case UNORDERED
: case ORDERED
:
8900 /* If the constant is negative, take its 1's complement and remask.
8901 Then see how many zero bits we have. */
8902 nonzero
= STORE_FLAG_VALUE
;
8903 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8904 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8905 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8907 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8914 /* If we haven't been able to figure it out by one of the above rules,
8915 see if some of the high-order bits are known to be zero. If so,
8916 count those bits and return one less than that amount. If we can't
8917 safely compute the mask for this mode, always return BITWIDTH. */
8919 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8922 nonzero
= nonzero_bits (x
, mode
);
8923 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8924 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8927 /* Return the number of "extended" bits there are in X, when interpreted
8928 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8929 unsigned quantities, this is the number of high-order zero bits.
8930 For signed quantities, this is the number of copies of the sign bit
8931 minus 1. In both case, this function returns the number of "spare"
8932 bits. For example, if two quantities for which this function returns
8933 at least 1 are added, the addition is known not to overflow.
8935 This function will always return 0 unless called during combine, which
8936 implies that it must be called from a define_split. */
8939 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8941 if (nonzero_sign_valid
== 0)
8945 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8946 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8947 - floor_log2 (nonzero_bits (x
, mode
)))
8949 : num_sign_bit_copies (x
, mode
) - 1);
8952 /* This function is called from `simplify_shift_const' to merge two
8953 outer operations. Specifically, we have already found that we need
8954 to perform operation *POP0 with constant *PCONST0 at the outermost
8955 position. We would now like to also perform OP1 with constant CONST1
8956 (with *POP0 being done last).
8958 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8959 the resulting operation. *PCOMP_P is set to 1 if we would need to
8960 complement the innermost operand, otherwise it is unchanged.
8962 MODE is the mode in which the operation will be done. No bits outside
8963 the width of this mode matter. It is assumed that the width of this mode
8964 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8966 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8967 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8968 result is simply *PCONST0.
8970 If the resulting operation cannot be expressed as one operation, we
8971 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8974 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8976 enum rtx_code op0
= *pop0
;
8977 HOST_WIDE_INT const0
= *pconst0
;
8979 const0
&= GET_MODE_MASK (mode
);
8980 const1
&= GET_MODE_MASK (mode
);
8982 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8986 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8989 if (op1
== NIL
|| op0
== SET
)
8992 else if (op0
== NIL
)
8993 op0
= op1
, const0
= const1
;
8995 else if (op0
== op1
)
9019 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9020 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9023 /* If the two constants aren't the same, we can't do anything. The
9024 remaining six cases can all be done. */
9025 else if (const0
!= const1
)
9033 /* (a & b) | b == b */
9035 else /* op1 == XOR */
9036 /* (a ^ b) | b == a | b */
9042 /* (a & b) ^ b == (~a) & b */
9043 op0
= AND
, *pcomp_p
= 1;
9044 else /* op1 == IOR */
9045 /* (a | b) ^ b == a & ~b */
9046 op0
= AND
, const0
= ~const0
;
9051 /* (a | b) & b == b */
9053 else /* op1 == XOR */
9054 /* (a ^ b) & b) == (~a) & b */
9061 /* Check for NO-OP cases. */
9062 const0
&= GET_MODE_MASK (mode
);
9064 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9066 else if (const0
== 0 && op0
== AND
)
9068 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9072 /* ??? Slightly redundant with the above mask, but not entirely.
9073 Moving this above means we'd have to sign-extend the mode mask
9074 for the final test. */
9075 const0
= trunc_int_for_mode (const0
, mode
);
9083 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9084 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9085 that we started with.
9087 The shift is normally computed in the widest mode we find in VAROP, as
9088 long as it isn't a different number of words than RESULT_MODE. Exceptions
9089 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9092 simplify_shift_const (rtx x
, enum rtx_code code
,
9093 enum machine_mode result_mode
, rtx varop
,
9096 enum rtx_code orig_code
= code
;
9099 enum machine_mode mode
= result_mode
;
9100 enum machine_mode shift_mode
, tmode
;
9101 unsigned int mode_words
9102 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9103 /* We form (outer_op (code varop count) (outer_const)). */
9104 enum rtx_code outer_op
= NIL
;
9105 HOST_WIDE_INT outer_const
= 0;
9107 int complement_p
= 0;
9110 /* Make sure and truncate the "natural" shift on the way in. We don't
9111 want to do this inside the loop as it makes it more difficult to
9113 if (SHIFT_COUNT_TRUNCATED
)
9114 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9116 /* If we were given an invalid count, don't do anything except exactly
9117 what was requested. */
9119 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9124 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9129 /* Unless one of the branches of the `if' in this loop does a `continue',
9130 we will `break' the loop after the `if'. */
9134 /* If we have an operand of (clobber (const_int 0)), just return that
9136 if (GET_CODE (varop
) == CLOBBER
)
9139 /* If we discovered we had to complement VAROP, leave. Making a NOT
9140 here would cause an infinite loop. */
9144 /* Convert ROTATERT to ROTATE. */
9145 if (code
== ROTATERT
)
9147 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9149 if (VECTOR_MODE_P (result_mode
))
9150 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9152 count
= bitsize
- count
;
9155 /* We need to determine what mode we will do the shift in. If the
9156 shift is a right shift or a ROTATE, we must always do it in the mode
9157 it was originally done in. Otherwise, we can do it in MODE, the
9158 widest mode encountered. */
9160 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9161 ? result_mode
: mode
);
9163 /* Handle cases where the count is greater than the size of the mode
9164 minus 1. For ASHIFT, use the size minus one as the count (this can
9165 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9166 take the count modulo the size. For other shifts, the result is
9169 Since these shifts are being produced by the compiler by combining
9170 multiple operations, each of which are defined, we know what the
9171 result is supposed to be. */
9173 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9175 if (code
== ASHIFTRT
)
9176 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9177 else if (code
== ROTATE
|| code
== ROTATERT
)
9178 count
%= GET_MODE_BITSIZE (shift_mode
);
9181 /* We can't simply return zero because there may be an
9189 /* An arithmetic right shift of a quantity known to be -1 or 0
9191 if (code
== ASHIFTRT
9192 && (num_sign_bit_copies (varop
, shift_mode
)
9193 == GET_MODE_BITSIZE (shift_mode
)))
9199 /* If we are doing an arithmetic right shift and discarding all but
9200 the sign bit copies, this is equivalent to doing a shift by the
9201 bitsize minus one. Convert it into that shift because it will often
9202 allow other simplifications. */
9204 if (code
== ASHIFTRT
9205 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9206 >= GET_MODE_BITSIZE (shift_mode
)))
9207 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9209 /* We simplify the tests below and elsewhere by converting
9210 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9211 `make_compound_operation' will convert it to an ASHIFTRT for
9212 those machines (such as VAX) that don't have an LSHIFTRT. */
9213 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9215 && ((nonzero_bits (varop
, shift_mode
)
9216 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9220 if (code
== LSHIFTRT
9221 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9222 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9225 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9226 && !((nonzero_bits (varop
, shift_mode
) << count
)
9227 & GET_MODE_MASK (shift_mode
)))
9230 switch (GET_CODE (varop
))
9236 new = expand_compound_operation (varop
);
9245 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9246 minus the width of a smaller mode, we can do this with a
9247 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9248 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9249 && ! mode_dependent_address_p (XEXP (varop
, 0))
9250 && ! MEM_VOLATILE_P (varop
)
9251 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9252 MODE_INT
, 1)) != BLKmode
)
9254 new = adjust_address_nv (varop
, tmode
,
9255 BYTES_BIG_ENDIAN
? 0
9256 : count
/ BITS_PER_UNIT
);
9258 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9259 : ZERO_EXTEND
, mode
, new);
9266 /* Similar to the case above, except that we can only do this if
9267 the resulting mode is the same as that of the underlying
9268 MEM and adjust the address depending on the *bits* endianness
9269 because of the way that bit-field extract insns are defined. */
9270 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9271 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9272 MODE_INT
, 1)) != BLKmode
9273 && tmode
== GET_MODE (XEXP (varop
, 0)))
9275 if (BITS_BIG_ENDIAN
)
9276 new = XEXP (varop
, 0);
9279 new = copy_rtx (XEXP (varop
, 0));
9280 SUBST (XEXP (new, 0),
9281 plus_constant (XEXP (new, 0),
9282 count
/ BITS_PER_UNIT
));
9285 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9286 : ZERO_EXTEND
, mode
, new);
9293 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9294 the same number of words as what we've seen so far. Then store
9295 the widest mode in MODE. */
9296 if (subreg_lowpart_p (varop
)
9297 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9298 > GET_MODE_SIZE (GET_MODE (varop
)))
9299 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9300 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9303 varop
= SUBREG_REG (varop
);
9304 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9305 mode
= GET_MODE (varop
);
9311 /* Some machines use MULT instead of ASHIFT because MULT
9312 is cheaper. But it is still better on those machines to
9313 merge two shifts into one. */
9314 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9315 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9318 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9319 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9325 /* Similar, for when divides are cheaper. */
9326 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9327 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9330 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9331 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9337 /* If we are extracting just the sign bit of an arithmetic
9338 right shift, that shift is not needed. However, the sign
9339 bit of a wider mode may be different from what would be
9340 interpreted as the sign bit in a narrower mode, so, if
9341 the result is narrower, don't discard the shift. */
9342 if (code
== LSHIFTRT
9343 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9344 && (GET_MODE_BITSIZE (result_mode
)
9345 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9347 varop
= XEXP (varop
, 0);
9351 /* ... fall through ... */
9356 /* Here we have two nested shifts. The result is usually the
9357 AND of a new shift with a mask. We compute the result below. */
9358 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9359 && INTVAL (XEXP (varop
, 1)) >= 0
9360 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9361 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9362 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9364 enum rtx_code first_code
= GET_CODE (varop
);
9365 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9366 unsigned HOST_WIDE_INT mask
;
9369 /* We have one common special case. We can't do any merging if
9370 the inner code is an ASHIFTRT of a smaller mode. However, if
9371 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9372 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9373 we can convert it to
9374 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9375 This simplifies certain SIGN_EXTEND operations. */
9376 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9377 && count
== (unsigned int)
9378 (GET_MODE_BITSIZE (result_mode
)
9379 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9381 /* C3 has the low-order C1 bits zero. */
9383 mask
= (GET_MODE_MASK (mode
)
9384 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9386 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9387 XEXP (varop
, 0), mask
);
9388 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9390 count
= first_count
;
9395 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9396 than C1 high-order bits equal to the sign bit, we can convert
9397 this to either an ASHIFT or an ASHIFTRT depending on the
9400 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9402 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9403 && GET_MODE (varop
) == shift_mode
9404 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9407 varop
= XEXP (varop
, 0);
9409 signed_count
= count
- first_count
;
9410 if (signed_count
< 0)
9411 count
= -signed_count
, code
= ASHIFT
;
9413 count
= signed_count
;
9418 /* There are some cases we can't do. If CODE is ASHIFTRT,
9419 we can only do this if FIRST_CODE is also ASHIFTRT.
9421 We can't do the case when CODE is ROTATE and FIRST_CODE is
9424 If the mode of this shift is not the mode of the outer shift,
9425 we can't do this if either shift is a right shift or ROTATE.
9427 Finally, we can't do any of these if the mode is too wide
9428 unless the codes are the same.
9430 Handle the case where the shift codes are the same
9433 if (code
== first_code
)
9435 if (GET_MODE (varop
) != result_mode
9436 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9440 count
+= first_count
;
9441 varop
= XEXP (varop
, 0);
9445 if (code
== ASHIFTRT
9446 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9447 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9448 || (GET_MODE (varop
) != result_mode
9449 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9450 || first_code
== ROTATE
9451 || code
== ROTATE
)))
9454 /* To compute the mask to apply after the shift, shift the
9455 nonzero bits of the inner shift the same way the
9456 outer shift will. */
9458 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9461 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9464 /* Give up if we can't compute an outer operation to use. */
9466 || GET_CODE (mask_rtx
) != CONST_INT
9467 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9469 result_mode
, &complement_p
))
9472 /* If the shifts are in the same direction, we add the
9473 counts. Otherwise, we subtract them. */
9474 signed_count
= count
;
9475 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9476 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9477 signed_count
+= first_count
;
9479 signed_count
-= first_count
;
9481 /* If COUNT is positive, the new shift is usually CODE,
9482 except for the two exceptions below, in which case it is
9483 FIRST_CODE. If the count is negative, FIRST_CODE should
9485 if (signed_count
> 0
9486 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9487 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9488 code
= first_code
, count
= signed_count
;
9489 else if (signed_count
< 0)
9490 code
= first_code
, count
= -signed_count
;
9492 count
= signed_count
;
9494 varop
= XEXP (varop
, 0);
9498 /* If we have (A << B << C) for any shift, we can convert this to
9499 (A << C << B). This wins if A is a constant. Only try this if
9500 B is not a constant. */
9502 else if (GET_CODE (varop
) == code
9503 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9505 = simplify_binary_operation (code
, mode
,
9509 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9516 /* Make this fit the case below. */
9517 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9518 GEN_INT (GET_MODE_MASK (mode
)));
9524 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9525 with C the size of VAROP - 1 and the shift is logical if
9526 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9527 we have an (le X 0) operation. If we have an arithmetic shift
9528 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9529 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9531 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9532 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9533 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9534 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9535 && count
== (unsigned int)
9536 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9537 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9540 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9543 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9544 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9549 /* If we have (shift (logical)), move the logical to the outside
9550 to allow it to possibly combine with another logical and the
9551 shift to combine with another shift. This also canonicalizes to
9552 what a ZERO_EXTRACT looks like. Also, some machines have
9553 (and (shift)) insns. */
9555 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9556 /* We can't do this if we have (ashiftrt (xor)) and the
9557 constant has its sign bit set in shift_mode. */
9558 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9559 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9561 && (new = simplify_binary_operation (code
, result_mode
,
9563 GEN_INT (count
))) != 0
9564 && GET_CODE (new) == CONST_INT
9565 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9566 INTVAL (new), result_mode
, &complement_p
))
9568 varop
= XEXP (varop
, 0);
9572 /* If we can't do that, try to simplify the shift in each arm of the
9573 logical expression, make a new logical expression, and apply
9574 the inverse distributive law. This also can't be done
9575 for some (ashiftrt (xor)). */
9576 if (code
!= ASHIFTRT
|| GET_CODE (varop
)!= XOR
9577 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9580 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9581 XEXP (varop
, 0), count
);
9582 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9583 XEXP (varop
, 1), count
);
9585 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9586 varop
= apply_distributive_law (varop
);
9593 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9594 says that the sign bit can be tested, FOO has mode MODE, C is
9595 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9596 that may be nonzero. */
9597 if (code
== LSHIFTRT
9598 && XEXP (varop
, 1) == const0_rtx
9599 && GET_MODE (XEXP (varop
, 0)) == result_mode
9600 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9601 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9602 && ((STORE_FLAG_VALUE
9603 & ((HOST_WIDE_INT
) 1
9604 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9605 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9606 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9607 (HOST_WIDE_INT
) 1, result_mode
,
9610 varop
= XEXP (varop
, 0);
9617 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9618 than the number of bits in the mode is equivalent to A. */
9619 if (code
== LSHIFTRT
9620 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9621 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9623 varop
= XEXP (varop
, 0);
9628 /* NEG commutes with ASHIFT since it is multiplication. Move the
9629 NEG outside to allow shifts to combine. */
9631 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9632 (HOST_WIDE_INT
) 0, result_mode
,
9635 varop
= XEXP (varop
, 0);
9641 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9642 is one less than the number of bits in the mode is
9643 equivalent to (xor A 1). */
9644 if (code
== LSHIFTRT
9645 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9646 && XEXP (varop
, 1) == constm1_rtx
9647 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9648 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9649 (HOST_WIDE_INT
) 1, result_mode
,
9653 varop
= XEXP (varop
, 0);
9657 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9658 that might be nonzero in BAR are those being shifted out and those
9659 bits are known zero in FOO, we can replace the PLUS with FOO.
9660 Similarly in the other operand order. This code occurs when
9661 we are computing the size of a variable-size array. */
9663 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9664 && count
< HOST_BITS_PER_WIDE_INT
9665 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9666 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9667 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9669 varop
= XEXP (varop
, 0);
9672 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9673 && count
< HOST_BITS_PER_WIDE_INT
9674 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9675 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9677 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9678 & nonzero_bits (XEXP (varop
, 1),
9681 varop
= XEXP (varop
, 1);
9685 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9687 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9688 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9690 GEN_INT (count
))) != 0
9691 && GET_CODE (new) == CONST_INT
9692 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9693 INTVAL (new), result_mode
, &complement_p
))
9695 varop
= XEXP (varop
, 0);
9701 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9702 with C the size of VAROP - 1 and the shift is logical if
9703 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9704 we have a (gt X 0) operation. If the shift is arithmetic with
9705 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9706 we have a (neg (gt X 0)) operation. */
9708 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9709 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9710 && count
== (unsigned int)
9711 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9712 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9713 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9714 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9716 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9719 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9722 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9723 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9730 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9731 if the truncate does not affect the value. */
9732 if (code
== LSHIFTRT
9733 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9734 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9735 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9736 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9737 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9739 rtx varop_inner
= XEXP (varop
, 0);
9742 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9743 XEXP (varop_inner
, 0),
9745 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9746 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9759 /* We need to determine what mode to do the shift in. If the shift is
9760 a right shift or ROTATE, we must always do it in the mode it was
9761 originally done in. Otherwise, we can do it in MODE, the widest mode
9762 encountered. The code we care about is that of the shift that will
9763 actually be done, not the shift that was originally requested. */
9765 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9766 ? result_mode
: mode
);
9768 /* We have now finished analyzing the shift. The result should be
9769 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9770 OUTER_OP is non-NIL, it is an operation that needs to be applied
9771 to the result of the shift. OUTER_CONST is the relevant constant,
9772 but we must turn off all bits turned off in the shift.
9774 If we were passed a value for X, see if we can use any pieces of
9775 it. If not, make new rtx. */
9777 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9778 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9779 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9780 const_rtx
= XEXP (x
, 1);
9782 const_rtx
= GEN_INT (count
);
9784 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9785 && GET_MODE (XEXP (x
, 0)) == shift_mode
9786 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9787 varop
= XEXP (x
, 0);
9788 else if (GET_MODE (varop
) != shift_mode
)
9789 varop
= gen_lowpart (shift_mode
, varop
);
9791 /* If we can't make the SUBREG, try to return what we were given. */
9792 if (GET_CODE (varop
) == CLOBBER
)
9793 return x
? x
: varop
;
9795 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9799 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9801 /* If we have an outer operation and we just made a shift, it is
9802 possible that we could have simplified the shift were it not
9803 for the outer operation. So try to do the simplification
9806 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9807 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9808 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9809 INTVAL (XEXP (x
, 1)));
9811 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9812 turn off all the bits that the shift would have turned off. */
9813 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9814 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9815 GET_MODE_MASK (result_mode
) >> orig_count
);
9817 /* Do the remainder of the processing in RESULT_MODE. */
9818 x
= gen_lowpart (result_mode
, x
);
9820 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9823 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9825 if (outer_op
!= NIL
)
9827 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9828 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9830 if (outer_op
== AND
)
9831 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9832 else if (outer_op
== SET
)
9833 /* This means that we have determined that the result is
9834 equivalent to a constant. This should be rare. */
9835 x
= GEN_INT (outer_const
);
9836 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9837 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9839 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9845 /* Like recog, but we receive the address of a pointer to a new pattern.
9846 We try to match the rtx that the pointer points to.
9847 If that fails, we may try to modify or replace the pattern,
9848 storing the replacement into the same pointer object.
9850 Modifications include deletion or addition of CLOBBERs.
9852 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9853 the CLOBBERs are placed.
9855 The value is the final insn code from the pattern ultimately matched,
9859 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9862 int insn_code_number
;
9863 int num_clobbers_to_add
= 0;
9866 rtx old_notes
, old_pat
;
9868 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9869 we use to indicate that something didn't match. If we find such a
9870 thing, force rejection. */
9871 if (GET_CODE (pat
) == PARALLEL
)
9872 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9873 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9874 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9877 old_pat
= PATTERN (insn
);
9878 old_notes
= REG_NOTES (insn
);
9879 PATTERN (insn
) = pat
;
9880 REG_NOTES (insn
) = 0;
9882 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9884 /* If it isn't, there is the possibility that we previously had an insn
9885 that clobbered some register as a side effect, but the combined
9886 insn doesn't need to do that. So try once more without the clobbers
9887 unless this represents an ASM insn. */
9889 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9890 && GET_CODE (pat
) == PARALLEL
)
9894 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9895 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9898 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9902 SUBST_INT (XVECLEN (pat
, 0), pos
);
9905 pat
= XVECEXP (pat
, 0, 0);
9907 PATTERN (insn
) = pat
;
9908 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9910 PATTERN (insn
) = old_pat
;
9911 REG_NOTES (insn
) = old_notes
;
9913 /* Recognize all noop sets, these will be killed by followup pass. */
9914 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9915 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9917 /* If we had any clobbers to add, make a new pattern than contains
9918 them. Then check to make sure that all of them are dead. */
9919 if (num_clobbers_to_add
)
9921 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9922 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9924 + num_clobbers_to_add
)
9925 : num_clobbers_to_add
+ 1));
9927 if (GET_CODE (pat
) == PARALLEL
)
9928 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9929 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9931 XVECEXP (newpat
, 0, 0) = pat
;
9933 add_clobbers (newpat
, insn_code_number
);
9935 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9936 i
< XVECLEN (newpat
, 0); i
++)
9938 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9939 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9941 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9942 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9950 return insn_code_number
;
9953 /* Like gen_lowpart_general but for use by combine. In combine it
9954 is not possible to create any new pseudoregs. However, it is
9955 safe to create invalid memory addresses, because combine will
9956 try to recognize them and all they will do is make the combine
9959 If for some reason this cannot do its job, an rtx
9960 (clobber (const_int 0)) is returned.
9961 An insn containing that will not be recognized. */
9964 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9968 if (GET_MODE (x
) == mode
)
9971 /* Return identity if this is a CONST or symbolic
9974 && (GET_CODE (x
) == CONST
9975 || GET_CODE (x
) == SYMBOL_REF
9976 || GET_CODE (x
) == LABEL_REF
))
9979 /* We can only support MODE being wider than a word if X is a
9980 constant integer or has a mode the same size. */
9982 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9983 && ! ((GET_MODE (x
) == VOIDmode
9984 && (GET_CODE (x
) == CONST_INT
9985 || GET_CODE (x
) == CONST_DOUBLE
))
9986 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9987 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9989 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9990 won't know what to do. So we will strip off the SUBREG here and
9991 process normally. */
9992 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9995 if (GET_MODE (x
) == mode
)
9999 result
= gen_lowpart_common (mode
, x
);
10000 #ifdef CANNOT_CHANGE_MODE_CLASS
10002 && GET_CODE (result
) == SUBREG
10003 && GET_CODE (SUBREG_REG (result
)) == REG
10004 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10005 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10007 + GET_MODE (result
));
10013 if (GET_CODE (x
) == MEM
)
10017 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10019 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10020 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10022 /* If we want to refer to something bigger than the original memref,
10023 generate a paradoxical subreg instead. That will force a reload
10024 of the original memref X. */
10025 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10026 return gen_rtx_SUBREG (mode
, x
, 0);
10028 if (WORDS_BIG_ENDIAN
)
10029 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10030 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10032 if (BYTES_BIG_ENDIAN
)
10034 /* Adjust the address so that the address-after-the-data is
10036 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10037 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10040 return adjust_address_nv (x
, mode
, offset
);
10043 /* If X is a comparison operator, rewrite it in a new mode. This
10044 probably won't match, but may allow further simplifications. */
10045 else if (COMPARISON_P (x
))
10046 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10048 /* If we couldn't simplify X any other way, just enclose it in a
10049 SUBREG. Normally, this SUBREG won't match, but some patterns may
10050 include an explicit SUBREG or we may simplify it further in combine. */
10055 enum machine_mode sub_mode
= GET_MODE (x
);
10057 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10058 if (sub_mode
== VOIDmode
)
10060 sub_mode
= int_mode_for_mode (mode
);
10061 x
= gen_lowpart_common (sub_mode
, x
);
10063 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10065 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10068 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10072 /* These routines make binary and unary operations by first seeing if they
10073 fold; if not, a new expression is allocated. */
10076 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10081 if (GET_CODE (op0
) == CLOBBER
)
10083 else if (GET_CODE (op1
) == CLOBBER
)
10086 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
10087 && swap_commutative_operands_p (op0
, op1
))
10088 tem
= op0
, op0
= op1
, op1
= tem
;
10090 if (GET_RTX_CLASS (code
) == RTX_COMPARE
10091 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
10093 enum machine_mode op_mode
= GET_MODE (op0
);
10095 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10096 just (REL_OP X Y). */
10097 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10099 op1
= XEXP (op0
, 1);
10100 op0
= XEXP (op0
, 0);
10101 op_mode
= GET_MODE (op0
);
10104 if (op_mode
== VOIDmode
)
10105 op_mode
= GET_MODE (op1
);
10106 result
= simplify_relational_operation (code
, mode
, op_mode
, op0
, op1
);
10109 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10114 /* Put complex operands first and constants second. */
10115 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
10116 && swap_commutative_operands_p (op0
, op1
))
10117 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10119 /* If we are turning off bits already known off in OP0, we need not do
10121 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10122 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10123 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10126 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10129 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10130 comparison code that will be tested.
10132 The result is a possibly different comparison code to use. *POP0 and
10133 *POP1 may be updated.
10135 It is possible that we might detect that a comparison is either always
10136 true or always false. However, we do not perform general constant
10137 folding in combine, so this knowledge isn't useful. Such tautologies
10138 should have been detected earlier. Hence we ignore all such cases. */
10140 static enum rtx_code
10141 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10147 enum machine_mode mode
, tmode
;
10149 /* Try a few ways of applying the same transformation to both operands. */
10152 #ifndef WORD_REGISTER_OPERATIONS
10153 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10154 so check specially. */
10155 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10156 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10157 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10158 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10159 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10160 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10161 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10162 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10163 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10164 && XEXP (op0
, 1) == XEXP (op1
, 1)
10165 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10166 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10167 && (INTVAL (XEXP (op0
, 1))
10168 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10169 - (GET_MODE_BITSIZE
10170 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10172 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10173 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10177 /* If both operands are the same constant shift, see if we can ignore the
10178 shift. We can if the shift is a rotate or if the bits shifted out of
10179 this shift are known to be zero for both inputs and if the type of
10180 comparison is compatible with the shift. */
10181 if (GET_CODE (op0
) == GET_CODE (op1
)
10182 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10183 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10184 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10185 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10186 || (GET_CODE (op0
) == ASHIFTRT
10187 && (code
!= GTU
&& code
!= LTU
10188 && code
!= GEU
&& code
!= LEU
)))
10189 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10190 && INTVAL (XEXP (op0
, 1)) >= 0
10191 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10192 && XEXP (op0
, 1) == XEXP (op1
, 1))
10194 enum machine_mode mode
= GET_MODE (op0
);
10195 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10196 int shift_count
= INTVAL (XEXP (op0
, 1));
10198 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10199 mask
&= (mask
>> shift_count
) << shift_count
;
10200 else if (GET_CODE (op0
) == ASHIFT
)
10201 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10203 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10204 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10205 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10210 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10211 SUBREGs are of the same mode, and, in both cases, the AND would
10212 be redundant if the comparison was done in the narrower mode,
10213 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10214 and the operand's possibly nonzero bits are 0xffffff01; in that case
10215 if we only care about QImode, we don't need the AND). This case
10216 occurs if the output mode of an scc insn is not SImode and
10217 STORE_FLAG_VALUE == 1 (e.g., the 386).
10219 Similarly, check for a case where the AND's are ZERO_EXTEND
10220 operations from some narrower mode even though a SUBREG is not
10223 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10224 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10225 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10227 rtx inner_op0
= XEXP (op0
, 0);
10228 rtx inner_op1
= XEXP (op1
, 0);
10229 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10230 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10233 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10234 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10235 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10236 && (GET_MODE (SUBREG_REG (inner_op0
))
10237 == GET_MODE (SUBREG_REG (inner_op1
)))
10238 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10239 <= HOST_BITS_PER_WIDE_INT
)
10240 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10241 GET_MODE (SUBREG_REG (inner_op0
)))))
10242 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10243 GET_MODE (SUBREG_REG (inner_op1
))))))
10245 op0
= SUBREG_REG (inner_op0
);
10246 op1
= SUBREG_REG (inner_op1
);
10248 /* The resulting comparison is always unsigned since we masked
10249 off the original sign bit. */
10250 code
= unsigned_condition (code
);
10256 for (tmode
= GET_CLASS_NARROWEST_MODE
10257 (GET_MODE_CLASS (GET_MODE (op0
)));
10258 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10259 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10261 op0
= gen_lowpart (tmode
, inner_op0
);
10262 op1
= gen_lowpart (tmode
, inner_op1
);
10263 code
= unsigned_condition (code
);
10272 /* If both operands are NOT, we can strip off the outer operation
10273 and adjust the comparison code for swapped operands; similarly for
10274 NEG, except that this must be an equality comparison. */
10275 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10276 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10277 && (code
== EQ
|| code
== NE
)))
10278 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10284 /* If the first operand is a constant, swap the operands and adjust the
10285 comparison code appropriately, but don't do this if the second operand
10286 is already a constant integer. */
10287 if (swap_commutative_operands_p (op0
, op1
))
10289 tem
= op0
, op0
= op1
, op1
= tem
;
10290 code
= swap_condition (code
);
10293 /* We now enter a loop during which we will try to simplify the comparison.
10294 For the most part, we only are concerned with comparisons with zero,
10295 but some things may really be comparisons with zero but not start
10296 out looking that way. */
10298 while (GET_CODE (op1
) == CONST_INT
)
10300 enum machine_mode mode
= GET_MODE (op0
);
10301 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10302 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10303 int equality_comparison_p
;
10304 int sign_bit_comparison_p
;
10305 int unsigned_comparison_p
;
10306 HOST_WIDE_INT const_op
;
10308 /* We only want to handle integral modes. This catches VOIDmode,
10309 CCmode, and the floating-point modes. An exception is that we
10310 can handle VOIDmode if OP0 is a COMPARE or a comparison
10313 if (GET_MODE_CLASS (mode
) != MODE_INT
10314 && ! (mode
== VOIDmode
10315 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10318 /* Get the constant we are comparing against and turn off all bits
10319 not on in our mode. */
10320 const_op
= INTVAL (op1
);
10321 if (mode
!= VOIDmode
)
10322 const_op
= trunc_int_for_mode (const_op
, mode
);
10323 op1
= GEN_INT (const_op
);
10325 /* If we are comparing against a constant power of two and the value
10326 being compared can only have that single bit nonzero (e.g., it was
10327 `and'ed with that bit), we can replace this with a comparison
10330 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10331 || code
== LT
|| code
== LTU
)
10332 && mode_width
<= HOST_BITS_PER_WIDE_INT
10333 && exact_log2 (const_op
) >= 0
10334 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10336 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10337 op1
= const0_rtx
, const_op
= 0;
10340 /* Similarly, if we are comparing a value known to be either -1 or
10341 0 with -1, change it to the opposite comparison against zero. */
10344 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10345 || code
== GEU
|| code
== LTU
)
10346 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10348 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10349 op1
= const0_rtx
, const_op
= 0;
10352 /* Do some canonicalizations based on the comparison code. We prefer
10353 comparisons against zero and then prefer equality comparisons.
10354 If we can reduce the size of a constant, we will do that too. */
10359 /* < C is equivalent to <= (C - 1) */
10363 op1
= GEN_INT (const_op
);
10365 /* ... fall through to LE case below. */
10371 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10375 op1
= GEN_INT (const_op
);
10379 /* If we are doing a <= 0 comparison on a value known to have
10380 a zero sign bit, we can replace this with == 0. */
10381 else if (const_op
== 0
10382 && mode_width
<= HOST_BITS_PER_WIDE_INT
10383 && (nonzero_bits (op0
, mode
)
10384 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10389 /* >= C is equivalent to > (C - 1). */
10393 op1
= GEN_INT (const_op
);
10395 /* ... fall through to GT below. */
10401 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10405 op1
= GEN_INT (const_op
);
10409 /* If we are doing a > 0 comparison on a value known to have
10410 a zero sign bit, we can replace this with != 0. */
10411 else if (const_op
== 0
10412 && mode_width
<= HOST_BITS_PER_WIDE_INT
10413 && (nonzero_bits (op0
, mode
)
10414 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10419 /* < C is equivalent to <= (C - 1). */
10423 op1
= GEN_INT (const_op
);
10425 /* ... fall through ... */
10428 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10429 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10430 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10432 const_op
= 0, op1
= const0_rtx
;
10440 /* unsigned <= 0 is equivalent to == 0 */
10444 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10445 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10446 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10448 const_op
= 0, op1
= const0_rtx
;
10454 /* >= C is equivalent to < (C - 1). */
10458 op1
= GEN_INT (const_op
);
10460 /* ... fall through ... */
10463 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10464 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10465 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10467 const_op
= 0, op1
= const0_rtx
;
10475 /* unsigned > 0 is equivalent to != 0 */
10479 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10480 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10481 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10483 const_op
= 0, op1
= const0_rtx
;
10492 /* Compute some predicates to simplify code below. */
10494 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10495 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10496 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10499 /* If this is a sign bit comparison and we can do arithmetic in
10500 MODE, say that we will only be needing the sign bit of OP0. */
10501 if (sign_bit_comparison_p
10502 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10503 op0
= force_to_mode (op0
, mode
,
10505 << (GET_MODE_BITSIZE (mode
) - 1)),
10508 /* Now try cases based on the opcode of OP0. If none of the cases
10509 does a "continue", we exit this loop immediately after the
10512 switch (GET_CODE (op0
))
10515 /* If we are extracting a single bit from a variable position in
10516 a constant that has only a single bit set and are comparing it
10517 with zero, we can convert this into an equality comparison
10518 between the position and the location of the single bit. */
10519 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10520 have already reduced the shift count modulo the word size. */
10521 if (!SHIFT_COUNT_TRUNCATED
10522 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10523 && XEXP (op0
, 1) == const1_rtx
10524 && equality_comparison_p
&& const_op
== 0
10525 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10527 if (BITS_BIG_ENDIAN
)
10529 enum machine_mode new_mode
10530 = mode_for_extraction (EP_extzv
, 1);
10531 if (new_mode
== MAX_MACHINE_MODE
)
10532 i
= BITS_PER_WORD
- 1 - i
;
10536 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10540 op0
= XEXP (op0
, 2);
10544 /* Result is nonzero iff shift count is equal to I. */
10545 code
= reverse_condition (code
);
10549 /* ... fall through ... */
10552 tem
= expand_compound_operation (op0
);
10561 /* If testing for equality, we can take the NOT of the constant. */
10562 if (equality_comparison_p
10563 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10565 op0
= XEXP (op0
, 0);
10570 /* If just looking at the sign bit, reverse the sense of the
10572 if (sign_bit_comparison_p
)
10574 op0
= XEXP (op0
, 0);
10575 code
= (code
== GE
? LT
: GE
);
10581 /* If testing for equality, we can take the NEG of the constant. */
10582 if (equality_comparison_p
10583 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10585 op0
= XEXP (op0
, 0);
10590 /* The remaining cases only apply to comparisons with zero. */
10594 /* When X is ABS or is known positive,
10595 (neg X) is < 0 if and only if X != 0. */
10597 if (sign_bit_comparison_p
10598 && (GET_CODE (XEXP (op0
, 0)) == ABS
10599 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10600 && (nonzero_bits (XEXP (op0
, 0), mode
)
10601 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10603 op0
= XEXP (op0
, 0);
10604 code
= (code
== LT
? NE
: EQ
);
10608 /* If we have NEG of something whose two high-order bits are the
10609 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10610 if (num_sign_bit_copies (op0
, mode
) >= 2)
10612 op0
= XEXP (op0
, 0);
10613 code
= swap_condition (code
);
10619 /* If we are testing equality and our count is a constant, we
10620 can perform the inverse operation on our RHS. */
10621 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10622 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10623 op1
, XEXP (op0
, 1))) != 0)
10625 op0
= XEXP (op0
, 0);
10630 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10631 a particular bit. Convert it to an AND of a constant of that
10632 bit. This will be converted into a ZERO_EXTRACT. */
10633 if (const_op
== 0 && sign_bit_comparison_p
10634 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10635 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10637 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10640 - INTVAL (XEXP (op0
, 1)))));
10641 code
= (code
== LT
? NE
: EQ
);
10645 /* Fall through. */
10648 /* ABS is ignorable inside an equality comparison with zero. */
10649 if (const_op
== 0 && equality_comparison_p
)
10651 op0
= XEXP (op0
, 0);
10657 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10658 to (compare FOO CONST) if CONST fits in FOO's mode and we
10659 are either testing inequality or have an unsigned comparison
10660 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10661 if (! unsigned_comparison_p
10662 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10663 <= HOST_BITS_PER_WIDE_INT
)
10664 && ((unsigned HOST_WIDE_INT
) const_op
10665 < (((unsigned HOST_WIDE_INT
) 1
10666 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10668 op0
= XEXP (op0
, 0);
10674 /* Check for the case where we are comparing A - C1 with C2,
10675 both constants are smaller than 1/2 the maximum positive
10676 value in MODE, and the comparison is equality or unsigned.
10677 In that case, if A is either zero-extended to MODE or has
10678 sufficient sign bits so that the high-order bit in MODE
10679 is a copy of the sign in the inner mode, we can prove that it is
10680 safe to do the operation in the wider mode. This simplifies
10681 many range checks. */
10683 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10684 && subreg_lowpart_p (op0
)
10685 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10686 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10687 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10688 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10689 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10690 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10691 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10692 GET_MODE (SUBREG_REG (op0
)))
10693 & ~GET_MODE_MASK (mode
))
10694 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10695 GET_MODE (SUBREG_REG (op0
)))
10697 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10698 - GET_MODE_BITSIZE (mode
)))))
10700 op0
= SUBREG_REG (op0
);
10704 /* If the inner mode is narrower and we are extracting the low part,
10705 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10706 if (subreg_lowpart_p (op0
)
10707 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10708 /* Fall through */ ;
10712 /* ... fall through ... */
10715 if ((unsigned_comparison_p
|| equality_comparison_p
)
10716 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10717 <= HOST_BITS_PER_WIDE_INT
)
10718 && ((unsigned HOST_WIDE_INT
) const_op
10719 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10721 op0
= XEXP (op0
, 0);
10727 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10728 this for equality comparisons due to pathological cases involving
10730 if (equality_comparison_p
10731 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10732 op1
, XEXP (op0
, 1))))
10734 op0
= XEXP (op0
, 0);
10739 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10740 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10741 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10743 op0
= XEXP (XEXP (op0
, 0), 0);
10744 code
= (code
== LT
? EQ
: NE
);
10750 /* We used to optimize signed comparisons against zero, but that
10751 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10752 arrive here as equality comparisons, or (GEU, LTU) are
10753 optimized away. No need to special-case them. */
10755 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10756 (eq B (minus A C)), whichever simplifies. We can only do
10757 this for equality comparisons due to pathological cases involving
10759 if (equality_comparison_p
10760 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10761 XEXP (op0
, 1), op1
)))
10763 op0
= XEXP (op0
, 0);
10768 if (equality_comparison_p
10769 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10770 XEXP (op0
, 0), op1
)))
10772 op0
= XEXP (op0
, 1);
10777 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10778 of bits in X minus 1, is one iff X > 0. */
10779 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10780 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10781 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10783 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10785 op0
= XEXP (op0
, 1);
10786 code
= (code
== GE
? LE
: GT
);
10792 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10793 if C is zero or B is a constant. */
10794 if (equality_comparison_p
10795 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10796 XEXP (op0
, 1), op1
)))
10798 op0
= XEXP (op0
, 0);
10805 case UNEQ
: case LTGT
:
10806 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10807 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10808 case UNORDERED
: case ORDERED
:
10809 /* We can't do anything if OP0 is a condition code value, rather
10810 than an actual data value. */
10812 || CC0_P (XEXP (op0
, 0))
10813 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10816 /* Get the two operands being compared. */
10817 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10818 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10820 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10822 /* Check for the cases where we simply want the result of the
10823 earlier test or the opposite of that result. */
10824 if (code
== NE
|| code
== EQ
10825 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10826 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10827 && (STORE_FLAG_VALUE
10828 & (((HOST_WIDE_INT
) 1
10829 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10830 && (code
== LT
|| code
== GE
)))
10832 enum rtx_code new_code
;
10833 if (code
== LT
|| code
== NE
)
10834 new_code
= GET_CODE (op0
);
10836 new_code
= combine_reversed_comparison_code (op0
);
10838 if (new_code
!= UNKNOWN
)
10849 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10851 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10852 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10853 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10855 op0
= XEXP (op0
, 1);
10856 code
= (code
== GE
? GT
: LE
);
10862 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10863 will be converted to a ZERO_EXTRACT later. */
10864 if (const_op
== 0 && equality_comparison_p
10865 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10866 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10868 op0
= simplify_and_const_int
10869 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10871 XEXP (XEXP (op0
, 0), 1)),
10872 (HOST_WIDE_INT
) 1);
10876 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10877 zero and X is a comparison and C1 and C2 describe only bits set
10878 in STORE_FLAG_VALUE, we can compare with X. */
10879 if (const_op
== 0 && equality_comparison_p
10880 && mode_width
<= HOST_BITS_PER_WIDE_INT
10881 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10882 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10883 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10884 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10885 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10887 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10888 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10889 if ((~STORE_FLAG_VALUE
& mask
) == 0
10890 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10891 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10892 && COMPARISON_P (tem
))))
10894 op0
= XEXP (XEXP (op0
, 0), 0);
10899 /* If we are doing an equality comparison of an AND of a bit equal
10900 to the sign bit, replace this with a LT or GE comparison of
10901 the underlying value. */
10902 if (equality_comparison_p
10904 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10905 && mode_width
<= HOST_BITS_PER_WIDE_INT
10906 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10907 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10909 op0
= XEXP (op0
, 0);
10910 code
= (code
== EQ
? GE
: LT
);
10914 /* If this AND operation is really a ZERO_EXTEND from a narrower
10915 mode, the constant fits within that mode, and this is either an
10916 equality or unsigned comparison, try to do this comparison in
10917 the narrower mode. */
10918 if ((equality_comparison_p
|| unsigned_comparison_p
)
10919 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10920 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10921 & GET_MODE_MASK (mode
))
10923 && const_op
>> i
== 0
10924 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10926 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10930 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10931 fits in both M1 and M2 and the SUBREG is either paradoxical
10932 or represents the low part, permute the SUBREG and the AND
10934 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10936 unsigned HOST_WIDE_INT c1
;
10937 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10938 /* Require an integral mode, to avoid creating something like
10940 if (SCALAR_INT_MODE_P (tmode
)
10941 /* It is unsafe to commute the AND into the SUBREG if the
10942 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10943 not defined. As originally written the upper bits
10944 have a defined value due to the AND operation.
10945 However, if we commute the AND inside the SUBREG then
10946 they no longer have defined values and the meaning of
10947 the code has been changed. */
10949 #ifdef WORD_REGISTER_OPERATIONS
10950 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10951 && mode_width
<= BITS_PER_WORD
)
10953 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10954 && subreg_lowpart_p (XEXP (op0
, 0))))
10955 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10956 && mode_width
<= HOST_BITS_PER_WIDE_INT
10957 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10958 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10959 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10961 && c1
!= GET_MODE_MASK (tmode
))
10963 op0
= gen_binary (AND
, tmode
,
10964 SUBREG_REG (XEXP (op0
, 0)),
10965 gen_int_mode (c1
, tmode
));
10966 op0
= gen_lowpart (mode
, op0
);
10971 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10972 if (const_op
== 0 && equality_comparison_p
10973 && XEXP (op0
, 1) == const1_rtx
10974 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10976 op0
= simplify_and_const_int
10977 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10978 code
= (code
== NE
? EQ
: NE
);
10982 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10983 (eq (and (lshiftrt X) 1) 0).
10984 Also handle the case where (not X) is expressed using xor. */
10985 if (const_op
== 0 && equality_comparison_p
10986 && XEXP (op0
, 1) == const1_rtx
10987 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10989 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10990 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10992 if (GET_CODE (shift_op
) == NOT
10993 || (GET_CODE (shift_op
) == XOR
10994 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10995 && GET_CODE (shift_count
) == CONST_INT
10996 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10997 && (INTVAL (XEXP (shift_op
, 1))
10998 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11000 op0
= simplify_and_const_int
11002 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11003 (HOST_WIDE_INT
) 1);
11004 code
= (code
== NE
? EQ
: NE
);
11011 /* If we have (compare (ashift FOO N) (const_int C)) and
11012 the high order N bits of FOO (N+1 if an inequality comparison)
11013 are known to be zero, we can do this by comparing FOO with C
11014 shifted right N bits so long as the low-order N bits of C are
11016 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11017 && INTVAL (XEXP (op0
, 1)) >= 0
11018 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11019 < HOST_BITS_PER_WIDE_INT
)
11021 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11022 && mode_width
<= HOST_BITS_PER_WIDE_INT
11023 && (nonzero_bits (XEXP (op0
, 0), mode
)
11024 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11025 + ! equality_comparison_p
))) == 0)
11027 /* We must perform a logical shift, not an arithmetic one,
11028 as we want the top N bits of C to be zero. */
11029 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11031 temp
>>= INTVAL (XEXP (op0
, 1));
11032 op1
= gen_int_mode (temp
, mode
);
11033 op0
= XEXP (op0
, 0);
11037 /* If we are doing a sign bit comparison, it means we are testing
11038 a particular bit. Convert it to the appropriate AND. */
11039 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11040 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11042 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11045 - INTVAL (XEXP (op0
, 1)))));
11046 code
= (code
== LT
? NE
: EQ
);
11050 /* If this an equality comparison with zero and we are shifting
11051 the low bit to the sign bit, we can convert this to an AND of the
11053 if (const_op
== 0 && equality_comparison_p
11054 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11055 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11058 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11059 (HOST_WIDE_INT
) 1);
11065 /* If this is an equality comparison with zero, we can do this
11066 as a logical shift, which might be much simpler. */
11067 if (equality_comparison_p
&& const_op
== 0
11068 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11070 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11072 INTVAL (XEXP (op0
, 1)));
11076 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11077 do the comparison in a narrower mode. */
11078 if (! unsigned_comparison_p
11079 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11080 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11081 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11082 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11083 MODE_INT
, 1)) != BLKmode
11084 && (((unsigned HOST_WIDE_INT
) const_op
11085 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11086 <= GET_MODE_MASK (tmode
)))
11088 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11092 /* Likewise if OP0 is a PLUS of a sign extension with a
11093 constant, which is usually represented with the PLUS
11094 between the shifts. */
11095 if (! unsigned_comparison_p
11096 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11097 && GET_CODE (XEXP (op0
, 0)) == PLUS
11098 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11099 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11100 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11101 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11102 MODE_INT
, 1)) != BLKmode
11103 && (((unsigned HOST_WIDE_INT
) const_op
11104 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11105 <= GET_MODE_MASK (tmode
)))
11107 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11108 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11109 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11112 op0
= gen_binary (PLUS
, tmode
,
11113 gen_lowpart (tmode
, inner
),
11118 /* ... fall through ... */
11120 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11121 the low order N bits of FOO are known to be zero, we can do this
11122 by comparing FOO with C shifted left N bits so long as no
11123 overflow occurs. */
11124 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11125 && INTVAL (XEXP (op0
, 1)) >= 0
11126 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11127 && mode_width
<= HOST_BITS_PER_WIDE_INT
11128 && (nonzero_bits (XEXP (op0
, 0), mode
)
11129 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11130 && (((unsigned HOST_WIDE_INT
) const_op
11131 + (GET_CODE (op0
) != LSHIFTRT
11132 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11135 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11137 /* If the shift was logical, then we must make the condition
11139 if (GET_CODE (op0
) == LSHIFTRT
)
11140 code
= unsigned_condition (code
);
11142 const_op
<<= INTVAL (XEXP (op0
, 1));
11143 op1
= GEN_INT (const_op
);
11144 op0
= XEXP (op0
, 0);
11148 /* If we are using this shift to extract just the sign bit, we
11149 can replace this with an LT or GE comparison. */
11151 && (equality_comparison_p
|| sign_bit_comparison_p
)
11152 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11153 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11156 op0
= XEXP (op0
, 0);
11157 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11169 /* Now make any compound operations involved in this comparison. Then,
11170 check for an outmost SUBREG on OP0 that is not doing anything or is
11171 paradoxical. The latter transformation must only be performed when
11172 it is known that the "extra" bits will be the same in op0 and op1 or
11173 that they don't matter. There are three cases to consider:
11175 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11176 care bits and we can assume they have any convenient value. So
11177 making the transformation is safe.
11179 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11180 In this case the upper bits of op0 are undefined. We should not make
11181 the simplification in that case as we do not know the contents of
11184 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11185 NIL. In that case we know those bits are zeros or ones. We must
11186 also be sure that they are the same as the upper bits of op1.
11188 We can never remove a SUBREG for a non-equality comparison because
11189 the sign bit is in a different place in the underlying object. */
11191 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11192 op1
= make_compound_operation (op1
, SET
);
11194 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11195 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11196 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11197 && (code
== NE
|| code
== EQ
))
11199 if (GET_MODE_SIZE (GET_MODE (op0
))
11200 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11202 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11204 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11206 op0
= SUBREG_REG (op0
);
11207 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11210 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11211 <= HOST_BITS_PER_WIDE_INT
)
11212 && (nonzero_bits (SUBREG_REG (op0
),
11213 GET_MODE (SUBREG_REG (op0
)))
11214 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11216 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11218 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11219 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11220 op0
= SUBREG_REG (op0
), op1
= tem
;
11224 /* We now do the opposite procedure: Some machines don't have compare
11225 insns in all modes. If OP0's mode is an integer mode smaller than a
11226 word and we can't do a compare in that mode, see if there is a larger
11227 mode for which we can do the compare. There are a number of cases in
11228 which we can use the wider mode. */
11230 mode
= GET_MODE (op0
);
11231 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11232 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11233 && ! have_insn_for (COMPARE
, mode
))
11234 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11236 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11237 tmode
= GET_MODE_WIDER_MODE (tmode
))
11238 if (have_insn_for (COMPARE
, tmode
))
11242 /* If the only nonzero bits in OP0 and OP1 are those in the
11243 narrower mode and this is an equality or unsigned comparison,
11244 we can use the wider mode. Similarly for sign-extended
11245 values, in which case it is true for all comparisons. */
11246 zero_extended
= ((code
== EQ
|| code
== NE
11247 || code
== GEU
|| code
== GTU
11248 || code
== LEU
|| code
== LTU
)
11249 && (nonzero_bits (op0
, tmode
)
11250 & ~GET_MODE_MASK (mode
)) == 0
11251 && ((GET_CODE (op1
) == CONST_INT
11252 || (nonzero_bits (op1
, tmode
)
11253 & ~GET_MODE_MASK (mode
)) == 0)));
11256 || ((num_sign_bit_copies (op0
, tmode
)
11257 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11258 - GET_MODE_BITSIZE (mode
)))
11259 && (num_sign_bit_copies (op1
, tmode
)
11260 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11261 - GET_MODE_BITSIZE (mode
)))))
11263 /* If OP0 is an AND and we don't have an AND in MODE either,
11264 make a new AND in the proper mode. */
11265 if (GET_CODE (op0
) == AND
11266 && !have_insn_for (AND
, mode
))
11267 op0
= gen_binary (AND
, tmode
,
11268 gen_lowpart (tmode
,
11270 gen_lowpart (tmode
,
11273 op0
= gen_lowpart (tmode
, op0
);
11274 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11275 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11276 op1
= gen_lowpart (tmode
, op1
);
11280 /* If this is a test for negative, we can make an explicit
11281 test of the sign bit. */
11283 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11284 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11286 op0
= gen_binary (AND
, tmode
,
11287 gen_lowpart (tmode
, op0
),
11288 GEN_INT ((HOST_WIDE_INT
) 1
11289 << (GET_MODE_BITSIZE (mode
) - 1)));
11290 code
= (code
== LT
) ? NE
: EQ
;
11295 #ifdef CANONICALIZE_COMPARISON
11296 /* If this machine only supports a subset of valid comparisons, see if we
11297 can convert an unsupported one into a supported one. */
11298 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11307 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11308 searching backward. */
11309 static enum rtx_code
11310 combine_reversed_comparison_code (rtx exp
)
11312 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11315 if (code1
!= UNKNOWN
11316 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11318 /* Otherwise try and find where the condition codes were last set and
11320 x
= get_last_value (XEXP (exp
, 0));
11321 if (!x
|| GET_CODE (x
) != COMPARE
)
11323 return reversed_comparison_code_parts (GET_CODE (exp
),
11324 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11327 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11328 Return NULL_RTX in case we fail to do the reversal. */
11330 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11332 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11333 if (reversed_code
== UNKNOWN
)
11336 return gen_binary (reversed_code
, mode
, op0
, op1
);
11339 /* Utility function for following routine. Called when X is part of a value
11340 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11341 for each register mentioned. Similar to mention_regs in cse.c */
11344 update_table_tick (rtx x
)
11346 enum rtx_code code
= GET_CODE (x
);
11347 const char *fmt
= GET_RTX_FORMAT (code
);
11352 unsigned int regno
= REGNO (x
);
11353 unsigned int endregno
11354 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11355 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11358 for (r
= regno
; r
< endregno
; r
++)
11359 reg_last_set_table_tick
[r
] = label_tick
;
11364 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11365 /* Note that we can't have an "E" in values stored; see
11366 get_last_value_validate. */
11369 /* Check for identical subexpressions. If x contains
11370 identical subexpression we only have to traverse one of
11372 if (i
== 0 && ARITHMETIC_P (x
))
11374 /* Note that at this point x1 has already been
11376 rtx x0
= XEXP (x
, 0);
11377 rtx x1
= XEXP (x
, 1);
11379 /* If x0 and x1 are identical then there is no need to
11384 /* If x0 is identical to a subexpression of x1 then while
11385 processing x1, x0 has already been processed. Thus we
11386 are done with x. */
11387 if (ARITHMETIC_P (x1
)
11388 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11391 /* If x1 is identical to a subexpression of x0 then we
11392 still have to process the rest of x0. */
11393 if (ARITHMETIC_P (x0
)
11394 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11396 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11401 update_table_tick (XEXP (x
, i
));
11405 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11406 are saying that the register is clobbered and we no longer know its
11407 value. If INSN is zero, don't update reg_last_set; this is only permitted
11408 with VALUE also zero and is used to invalidate the register. */
11411 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11413 unsigned int regno
= REGNO (reg
);
11414 unsigned int endregno
11415 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11416 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
11419 /* If VALUE contains REG and we have a previous value for REG, substitute
11420 the previous value. */
11421 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11425 /* Set things up so get_last_value is allowed to see anything set up to
11427 subst_low_cuid
= INSN_CUID (insn
);
11428 tem
= get_last_value (reg
);
11430 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11431 it isn't going to be useful and will take a lot of time to process,
11432 so just use the CLOBBER. */
11436 if (ARITHMETIC_P (tem
)
11437 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11438 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11439 tem
= XEXP (tem
, 0);
11441 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11445 /* For each register modified, show we don't know its value, that
11446 we don't know about its bitwise content, that its value has been
11447 updated, and that we don't know the location of the death of the
11449 for (i
= regno
; i
< endregno
; i
++)
11452 reg_last_set
[i
] = insn
;
11454 reg_last_set_value
[i
] = 0;
11455 reg_last_set_mode
[i
] = 0;
11456 reg_last_set_nonzero_bits
[i
] = 0;
11457 reg_last_set_sign_bit_copies
[i
] = 0;
11458 reg_last_death
[i
] = 0;
11461 /* Mark registers that are being referenced in this value. */
11463 update_table_tick (value
);
11465 /* Now update the status of each register being set.
11466 If someone is using this register in this block, set this register
11467 to invalid since we will get confused between the two lives in this
11468 basic block. This makes using this register always invalid. In cse, we
11469 scan the table to invalidate all entries using this register, but this
11470 is too much work for us. */
11472 for (i
= regno
; i
< endregno
; i
++)
11474 reg_last_set_label
[i
] = label_tick
;
11475 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11476 reg_last_set_invalid
[i
] = 1;
11478 reg_last_set_invalid
[i
] = 0;
11481 /* The value being assigned might refer to X (like in "x++;"). In that
11482 case, we must replace it with (clobber (const_int 0)) to prevent
11484 if (value
&& ! get_last_value_validate (&value
, insn
,
11485 reg_last_set_label
[regno
], 0))
11487 value
= copy_rtx (value
);
11488 if (! get_last_value_validate (&value
, insn
,
11489 reg_last_set_label
[regno
], 1))
11493 /* For the main register being modified, update the value, the mode, the
11494 nonzero bits, and the number of sign bit copies. */
11496 reg_last_set_value
[regno
] = value
;
11500 enum machine_mode mode
= GET_MODE (reg
);
11501 subst_low_cuid
= INSN_CUID (insn
);
11502 reg_last_set_mode
[regno
] = mode
;
11503 if (GET_MODE_CLASS (mode
) == MODE_INT
11504 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11505 mode
= nonzero_bits_mode
;
11506 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11507 reg_last_set_sign_bit_copies
[regno
]
11508 = num_sign_bit_copies (value
, GET_MODE (reg
));
11512 /* Called via note_stores from record_dead_and_set_regs to handle one
11513 SET or CLOBBER in an insn. DATA is the instruction in which the
11514 set is occurring. */
11517 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11519 rtx record_dead_insn
= (rtx
) data
;
11521 if (GET_CODE (dest
) == SUBREG
)
11522 dest
= SUBREG_REG (dest
);
11524 if (GET_CODE (dest
) == REG
)
11526 /* If we are setting the whole register, we know its value. Otherwise
11527 show that we don't know the value. We can handle SUBREG in
11529 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11530 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11531 else if (GET_CODE (setter
) == SET
11532 && GET_CODE (SET_DEST (setter
)) == SUBREG
11533 && SUBREG_REG (SET_DEST (setter
)) == dest
11534 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11535 && subreg_lowpart_p (SET_DEST (setter
)))
11536 record_value_for_reg (dest
, record_dead_insn
,
11537 gen_lowpart (GET_MODE (dest
),
11538 SET_SRC (setter
)));
11540 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11542 else if (GET_CODE (dest
) == MEM
11543 /* Ignore pushes, they clobber nothing. */
11544 && ! push_operand (dest
, GET_MODE (dest
)))
11545 mem_last_set
= INSN_CUID (record_dead_insn
);
11548 /* Update the records of when each REG was most recently set or killed
11549 for the things done by INSN. This is the last thing done in processing
11550 INSN in the combiner loop.
11552 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11553 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11554 and also the similar information mem_last_set (which insn most recently
11555 modified memory) and last_call_cuid (which insn was the most recent
11556 subroutine call). */
11559 record_dead_and_set_regs (rtx insn
)
11564 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11566 if (REG_NOTE_KIND (link
) == REG_DEAD
11567 && GET_CODE (XEXP (link
, 0)) == REG
)
11569 unsigned int regno
= REGNO (XEXP (link
, 0));
11570 unsigned int endregno
11571 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11572 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11575 for (i
= regno
; i
< endregno
; i
++)
11576 reg_last_death
[i
] = insn
;
11578 else if (REG_NOTE_KIND (link
) == REG_INC
)
11579 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11582 if (GET_CODE (insn
) == CALL_INSN
)
11584 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11585 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11587 reg_last_set_value
[i
] = 0;
11588 reg_last_set_mode
[i
] = 0;
11589 reg_last_set_nonzero_bits
[i
] = 0;
11590 reg_last_set_sign_bit_copies
[i
] = 0;
11591 reg_last_death
[i
] = 0;
11594 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11596 /* Don't bother recording what this insn does. It might set the
11597 return value register, but we can't combine into a call
11598 pattern anyway, so there's no point trying (and it may cause
11599 a crash, if e.g. we wind up asking for last_set_value of a
11600 SUBREG of the return value register). */
11604 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11607 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11608 register present in the SUBREG, so for each such SUBREG go back and
11609 adjust nonzero and sign bit information of the registers that are
11610 known to have some zero/sign bits set.
11612 This is needed because when combine blows the SUBREGs away, the
11613 information on zero/sign bits is lost and further combines can be
11614 missed because of that. */
11617 record_promoted_value (rtx insn
, rtx subreg
)
11620 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11621 enum machine_mode mode
= GET_MODE (subreg
);
11623 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11626 for (links
= LOG_LINKS (insn
); links
;)
11628 insn
= XEXP (links
, 0);
11629 set
= single_set (insn
);
11631 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11632 || REGNO (SET_DEST (set
)) != regno
11633 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11635 links
= XEXP (links
, 1);
11639 if (reg_last_set
[regno
] == insn
)
11641 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11642 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11645 if (GET_CODE (SET_SRC (set
)) == REG
)
11647 regno
= REGNO (SET_SRC (set
));
11648 links
= LOG_LINKS (insn
);
11655 /* Scan X for promoted SUBREGs. For each one found,
11656 note what it implies to the registers used in it. */
11659 check_promoted_subreg (rtx insn
, rtx x
)
11661 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11662 && GET_CODE (SUBREG_REG (x
)) == REG
)
11663 record_promoted_value (insn
, x
);
11666 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11669 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11673 check_promoted_subreg (insn
, XEXP (x
, i
));
11677 if (XVEC (x
, i
) != 0)
11678 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11679 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11685 /* Utility routine for the following function. Verify that all the registers
11686 mentioned in *LOC are valid when *LOC was part of a value set when
11687 label_tick == TICK. Return 0 if some are not.
11689 If REPLACE is nonzero, replace the invalid reference with
11690 (clobber (const_int 0)) and return 1. This replacement is useful because
11691 we often can get useful information about the form of a value (e.g., if
11692 it was produced by a shift that always produces -1 or 0) even though
11693 we don't know exactly what registers it was produced from. */
11696 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11699 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11700 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11703 if (GET_CODE (x
) == REG
)
11705 unsigned int regno
= REGNO (x
);
11706 unsigned int endregno
11707 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11708 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11711 for (j
= regno
; j
< endregno
; j
++)
11712 if (reg_last_set_invalid
[j
]
11713 /* If this is a pseudo-register that was only set once and not
11714 live at the beginning of the function, it is always valid. */
11715 || (! (regno
>= FIRST_PSEUDO_REGISTER
11716 && REG_N_SETS (regno
) == 1
11717 && (! REGNO_REG_SET_P
11718 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11719 && reg_last_set_label
[j
] > tick
))
11722 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11728 /* If this is a memory reference, make sure that there were
11729 no stores after it that might have clobbered the value. We don't
11730 have alias info, so we assume any store invalidates it. */
11731 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11732 && INSN_CUID (insn
) <= mem_last_set
)
11735 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11739 for (i
= 0; i
< len
; i
++)
11743 /* Check for identical subexpressions. If x contains
11744 identical subexpression we only have to traverse one of
11746 if (i
== 1 && ARITHMETIC_P (x
))
11748 /* Note that at this point x0 has already been checked
11749 and found valid. */
11750 rtx x0
= XEXP (x
, 0);
11751 rtx x1
= XEXP (x
, 1);
11753 /* If x0 and x1 are identical then x is also valid. */
11757 /* If x1 is identical to a subexpression of x0 then
11758 while checking x0, x1 has already been checked. Thus
11759 it is valid and so as x. */
11760 if (ARITHMETIC_P (x0
)
11761 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11764 /* If x0 is identical to a subexpression of x1 then x is
11765 valid iff the rest of x1 is valid. */
11766 if (ARITHMETIC_P (x1
)
11767 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11769 get_last_value_validate (&XEXP (x1
,
11770 x0
== XEXP (x1
, 0) ? 1 : 0),
11771 insn
, tick
, replace
);
11774 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11778 /* Don't bother with these. They shouldn't occur anyway. */
11779 else if (fmt
[i
] == 'E')
11783 /* If we haven't found a reason for it to be invalid, it is valid. */
11787 /* Get the last value assigned to X, if known. Some registers
11788 in the value may be replaced with (clobber (const_int 0)) if their value
11789 is known longer known reliably. */
11792 get_last_value (rtx x
)
11794 unsigned int regno
;
11797 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11798 then convert it to the desired mode. If this is a paradoxical SUBREG,
11799 we cannot predict what values the "extra" bits might have. */
11800 if (GET_CODE (x
) == SUBREG
11801 && subreg_lowpart_p (x
)
11802 && (GET_MODE_SIZE (GET_MODE (x
))
11803 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11804 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11805 return gen_lowpart (GET_MODE (x
), value
);
11807 if (GET_CODE (x
) != REG
)
11811 value
= reg_last_set_value
[regno
];
11813 /* If we don't have a value, or if it isn't for this basic block and
11814 it's either a hard register, set more than once, or it's a live
11815 at the beginning of the function, return 0.
11817 Because if it's not live at the beginning of the function then the reg
11818 is always set before being used (is never used without being set).
11819 And, if it's set only once, and it's always set before use, then all
11820 uses must have the same last value, even if it's not from this basic
11824 || (reg_last_set_label
[regno
] != label_tick
11825 && (regno
< FIRST_PSEUDO_REGISTER
11826 || REG_N_SETS (regno
) != 1
11827 || (REGNO_REG_SET_P
11828 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11831 /* If the value was set in a later insn than the ones we are processing,
11832 we can't use it even if the register was only set once. */
11833 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11836 /* If the value has all its registers valid, return it. */
11837 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11838 reg_last_set_label
[regno
], 0))
11841 /* Otherwise, make a copy and replace any invalid register with
11842 (clobber (const_int 0)). If that fails for some reason, return 0. */
11844 value
= copy_rtx (value
);
11845 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11846 reg_last_set_label
[regno
], 1))
11852 /* Return nonzero if expression X refers to a REG or to memory
11853 that is set in an instruction more recent than FROM_CUID. */
11856 use_crosses_set_p (rtx x
, int from_cuid
)
11860 enum rtx_code code
= GET_CODE (x
);
11864 unsigned int regno
= REGNO (x
);
11865 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11866 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11868 #ifdef PUSH_ROUNDING
11869 /* Don't allow uses of the stack pointer to be moved,
11870 because we don't know whether the move crosses a push insn. */
11871 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11874 for (; regno
< endreg
; regno
++)
11875 if (reg_last_set
[regno
]
11876 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11881 if (code
== MEM
&& mem_last_set
> from_cuid
)
11884 fmt
= GET_RTX_FORMAT (code
);
11886 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11891 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11892 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11895 else if (fmt
[i
] == 'e'
11896 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11902 /* Define three variables used for communication between the following
11905 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11906 static int reg_dead_flag
;
11908 /* Function called via note_stores from reg_dead_at_p.
11910 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11911 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11914 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11916 unsigned int regno
, endregno
;
11918 if (GET_CODE (dest
) != REG
)
11921 regno
= REGNO (dest
);
11922 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11923 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11925 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11926 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11929 /* Return nonzero if REG is known to be dead at INSN.
11931 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11932 referencing REG, it is dead. If we hit a SET referencing REG, it is
11933 live. Otherwise, see if it is live or dead at the start of the basic
11934 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11935 must be assumed to be always live. */
11938 reg_dead_at_p (rtx reg
, rtx insn
)
11943 /* Set variables for reg_dead_at_p_1. */
11944 reg_dead_regno
= REGNO (reg
);
11945 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11946 ? hard_regno_nregs
[reg_dead_regno
]
11952 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11953 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11955 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11956 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11960 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11961 beginning of function. */
11962 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11963 insn
= prev_nonnote_insn (insn
))
11965 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11967 return reg_dead_flag
== 1 ? 1 : 0;
11969 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11973 /* Get the basic block that we were in. */
11975 block
= ENTRY_BLOCK_PTR
->next_bb
;
11978 FOR_EACH_BB (block
)
11979 if (insn
== BB_HEAD (block
))
11982 if (block
== EXIT_BLOCK_PTR
)
11986 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11987 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11993 /* Note hard registers in X that are used. This code is similar to
11994 that in flow.c, but much simpler since we don't care about pseudos. */
11997 mark_used_regs_combine (rtx x
)
11999 RTX_CODE code
= GET_CODE (x
);
12000 unsigned int regno
;
12013 case ADDR_DIFF_VEC
:
12016 /* CC0 must die in the insn after it is set, so we don't need to take
12017 special note of it here. */
12023 /* If we are clobbering a MEM, mark any hard registers inside the
12024 address as used. */
12025 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12026 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12031 /* A hard reg in a wide mode may really be multiple registers.
12032 If so, mark all of them just like the first. */
12033 if (regno
< FIRST_PSEUDO_REGISTER
)
12035 unsigned int endregno
, r
;
12037 /* None of this applies to the stack, frame or arg pointers. */
12038 if (regno
== STACK_POINTER_REGNUM
12039 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12040 || regno
== HARD_FRAME_POINTER_REGNUM
12042 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12043 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12045 || regno
== FRAME_POINTER_REGNUM
)
12048 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12049 for (r
= regno
; r
< endregno
; r
++)
12050 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12056 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12058 rtx testreg
= SET_DEST (x
);
12060 while (GET_CODE (testreg
) == SUBREG
12061 || GET_CODE (testreg
) == ZERO_EXTRACT
12062 || GET_CODE (testreg
) == SIGN_EXTRACT
12063 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12064 testreg
= XEXP (testreg
, 0);
12066 if (GET_CODE (testreg
) == MEM
)
12067 mark_used_regs_combine (XEXP (testreg
, 0));
12069 mark_used_regs_combine (SET_SRC (x
));
12077 /* Recursively scan the operands of this expression. */
12080 const char *fmt
= GET_RTX_FORMAT (code
);
12082 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12085 mark_used_regs_combine (XEXP (x
, i
));
12086 else if (fmt
[i
] == 'E')
12090 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12091 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12097 /* Remove register number REGNO from the dead registers list of INSN.
12099 Return the note used to record the death, if there was one. */
12102 remove_death (unsigned int regno
, rtx insn
)
12104 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12108 REG_N_DEATHS (regno
)--;
12109 remove_note (insn
, note
);
12115 /* For each register (hardware or pseudo) used within expression X, if its
12116 death is in an instruction with cuid between FROM_CUID (inclusive) and
12117 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12118 list headed by PNOTES.
12120 That said, don't move registers killed by maybe_kill_insn.
12122 This is done when X is being merged by combination into TO_INSN. These
12123 notes will then be distributed as needed. */
12126 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12131 enum rtx_code code
= GET_CODE (x
);
12135 unsigned int regno
= REGNO (x
);
12136 rtx where_dead
= reg_last_death
[regno
];
12137 rtx before_dead
, after_dead
;
12139 /* Don't move the register if it gets killed in between from and to. */
12140 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12141 && ! reg_referenced_p (x
, maybe_kill_insn
))
12144 /* WHERE_DEAD could be a USE insn made by combine, so first we
12145 make sure that we have insns with valid INSN_CUID values. */
12146 before_dead
= where_dead
;
12147 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12148 before_dead
= PREV_INSN (before_dead
);
12150 after_dead
= where_dead
;
12151 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12152 after_dead
= NEXT_INSN (after_dead
);
12154 if (before_dead
&& after_dead
12155 && INSN_CUID (before_dead
) >= from_cuid
12156 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12157 || (where_dead
!= after_dead
12158 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12160 rtx note
= remove_death (regno
, where_dead
);
12162 /* It is possible for the call above to return 0. This can occur
12163 when reg_last_death points to I2 or I1 that we combined with.
12164 In that case make a new note.
12166 We must also check for the case where X is a hard register
12167 and NOTE is a death note for a range of hard registers
12168 including X. In that case, we must put REG_DEAD notes for
12169 the remaining registers in place of NOTE. */
12171 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12172 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12173 > GET_MODE_SIZE (GET_MODE (x
))))
12175 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12176 unsigned int deadend
12177 = (deadregno
+ hard_regno_nregs
[deadregno
]
12178 [GET_MODE (XEXP (note
, 0))]);
12179 unsigned int ourend
12180 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12183 for (i
= deadregno
; i
< deadend
; i
++)
12184 if (i
< regno
|| i
>= ourend
)
12185 REG_NOTES (where_dead
)
12186 = gen_rtx_EXPR_LIST (REG_DEAD
,
12188 REG_NOTES (where_dead
));
12191 /* If we didn't find any note, or if we found a REG_DEAD note that
12192 covers only part of the given reg, and we have a multi-reg hard
12193 register, then to be safe we must check for REG_DEAD notes
12194 for each register other than the first. They could have
12195 their own REG_DEAD notes lying around. */
12196 else if ((note
== 0
12198 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12199 < GET_MODE_SIZE (GET_MODE (x
)))))
12200 && regno
< FIRST_PSEUDO_REGISTER
12201 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12203 unsigned int ourend
12204 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12205 unsigned int i
, offset
;
12209 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12213 for (i
= regno
+ offset
; i
< ourend
; i
++)
12214 move_deaths (regno_reg_rtx
[i
],
12215 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12218 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12220 XEXP (note
, 1) = *pnotes
;
12224 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12226 REG_N_DEATHS (regno
)++;
12232 else if (GET_CODE (x
) == SET
)
12234 rtx dest
= SET_DEST (x
);
12236 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12238 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12239 that accesses one word of a multi-word item, some
12240 piece of everything register in the expression is used by
12241 this insn, so remove any old death. */
12242 /* ??? So why do we test for equality of the sizes? */
12244 if (GET_CODE (dest
) == ZERO_EXTRACT
12245 || GET_CODE (dest
) == STRICT_LOW_PART
12246 || (GET_CODE (dest
) == SUBREG
12247 && (((GET_MODE_SIZE (GET_MODE (dest
))
12248 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12249 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12250 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12252 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12256 /* If this is some other SUBREG, we know it replaces the entire
12257 value, so use that as the destination. */
12258 if (GET_CODE (dest
) == SUBREG
)
12259 dest
= SUBREG_REG (dest
);
12261 /* If this is a MEM, adjust deaths of anything used in the address.
12262 For a REG (the only other possibility), the entire value is
12263 being replaced so the old value is not used in this insn. */
12265 if (GET_CODE (dest
) == MEM
)
12266 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12271 else if (GET_CODE (x
) == CLOBBER
)
12274 len
= GET_RTX_LENGTH (code
);
12275 fmt
= GET_RTX_FORMAT (code
);
12277 for (i
= 0; i
< len
; i
++)
12282 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12283 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12286 else if (fmt
[i
] == 'e')
12287 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12291 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12292 pattern of an insn. X must be a REG. */
12295 reg_bitfield_target_p (rtx x
, rtx body
)
12299 if (GET_CODE (body
) == SET
)
12301 rtx dest
= SET_DEST (body
);
12303 unsigned int regno
, tregno
, endregno
, endtregno
;
12305 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12306 target
= XEXP (dest
, 0);
12307 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12308 target
= SUBREG_REG (XEXP (dest
, 0));
12312 if (GET_CODE (target
) == SUBREG
)
12313 target
= SUBREG_REG (target
);
12315 if (GET_CODE (target
) != REG
)
12318 tregno
= REGNO (target
), regno
= REGNO (x
);
12319 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12320 return target
== x
;
12322 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
12323 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12325 return endregno
> tregno
&& regno
< endtregno
;
12328 else if (GET_CODE (body
) == PARALLEL
)
12329 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12330 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12336 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12337 as appropriate. I3 and I2 are the insns resulting from the combination
12338 insns including FROM (I2 may be zero).
12340 Each note in the list is either ignored or placed on some insns, depending
12341 on the type of note. */
12344 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12346 rtx note
, next_note
;
12349 for (note
= notes
; note
; note
= next_note
)
12351 rtx place
= 0, place2
= 0;
12353 /* If this NOTE references a pseudo register, ensure it references
12354 the latest copy of that register. */
12355 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12356 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12357 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12359 next_note
= XEXP (note
, 1);
12360 switch (REG_NOTE_KIND (note
))
12364 /* Doesn't matter much where we put this, as long as it's somewhere.
12365 It is preferable to keep these notes on branches, which is most
12366 likely to be i3. */
12370 case REG_VALUE_PROFILE
:
12371 /* Just get rid of this note, as it is unused later anyway. */
12374 case REG_VTABLE_REF
:
12375 /* ??? Should remain with *a particular* memory load. Given the
12376 nature of vtable data, the last insn seems relatively safe. */
12380 case REG_NON_LOCAL_GOTO
:
12381 if (GET_CODE (i3
) == JUMP_INSN
)
12383 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12389 case REG_EH_REGION
:
12390 /* These notes must remain with the call or trapping instruction. */
12391 if (GET_CODE (i3
) == CALL_INSN
)
12393 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12395 else if (flag_non_call_exceptions
)
12397 if (may_trap_p (i3
))
12399 else if (i2
&& may_trap_p (i2
))
12401 /* ??? Otherwise assume we've combined things such that we
12402 can now prove that the instructions can't trap. Drop the
12403 note in this case. */
12409 case REG_ALWAYS_RETURN
:
12412 /* These notes must remain with the call. It should not be
12413 possible for both I2 and I3 to be a call. */
12414 if (GET_CODE (i3
) == CALL_INSN
)
12416 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12423 /* Any clobbers for i3 may still exist, and so we must process
12424 REG_UNUSED notes from that insn.
12426 Any clobbers from i2 or i1 can only exist if they were added by
12427 recog_for_combine. In that case, recog_for_combine created the
12428 necessary REG_UNUSED notes. Trying to keep any original
12429 REG_UNUSED notes from these insns can cause incorrect output
12430 if it is for the same register as the original i3 dest.
12431 In that case, we will notice that the register is set in i3,
12432 and then add a REG_UNUSED note for the destination of i3, which
12433 is wrong. However, it is possible to have REG_UNUSED notes from
12434 i2 or i1 for register which were both used and clobbered, so
12435 we keep notes from i2 or i1 if they will turn into REG_DEAD
12438 /* If this register is set or clobbered in I3, put the note there
12439 unless there is one already. */
12440 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12442 if (from_insn
!= i3
)
12445 if (! (GET_CODE (XEXP (note
, 0)) == REG
12446 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12447 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12450 /* Otherwise, if this register is used by I3, then this register
12451 now dies here, so we must put a REG_DEAD note here unless there
12453 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12454 && ! (GET_CODE (XEXP (note
, 0)) == REG
12455 ? find_regno_note (i3
, REG_DEAD
,
12456 REGNO (XEXP (note
, 0)))
12457 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12459 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12467 /* These notes say something about results of an insn. We can
12468 only support them if they used to be on I3 in which case they
12469 remain on I3. Otherwise they are ignored.
12471 If the note refers to an expression that is not a constant, we
12472 must also ignore the note since we cannot tell whether the
12473 equivalence is still true. It might be possible to do
12474 slightly better than this (we only have a problem if I2DEST
12475 or I1DEST is present in the expression), but it doesn't
12476 seem worth the trouble. */
12478 if (from_insn
== i3
12479 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12484 case REG_NO_CONFLICT
:
12485 /* These notes say something about how a register is used. They must
12486 be present on any use of the register in I2 or I3. */
12487 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12490 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12500 /* This can show up in several ways -- either directly in the
12501 pattern, or hidden off in the constant pool with (or without?)
12502 a REG_EQUAL note. */
12503 /* ??? Ignore the without-reg_equal-note problem for now. */
12504 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12505 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12506 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12507 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12511 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12512 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12513 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12514 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12522 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12523 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12524 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12526 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12528 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12529 LABEL_NUSES (JUMP_LABEL (place
))--;
12532 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12534 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12536 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12537 LABEL_NUSES (JUMP_LABEL (place2
))--;
12543 /* This note says something about the value of a register prior
12544 to the execution of an insn. It is too much trouble to see
12545 if the note is still correct in all situations. It is better
12546 to simply delete it. */
12550 /* If the insn previously containing this note still exists,
12551 put it back where it was. Otherwise move it to the previous
12552 insn. Adjust the corresponding REG_LIBCALL note. */
12553 if (GET_CODE (from_insn
) != NOTE
)
12557 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12558 place
= prev_real_insn (from_insn
);
12560 XEXP (tem
, 0) = place
;
12561 /* If we're deleting the last remaining instruction of a
12562 libcall sequence, don't add the notes. */
12563 else if (XEXP (note
, 0) == from_insn
)
12569 /* This is handled similarly to REG_RETVAL. */
12570 if (GET_CODE (from_insn
) != NOTE
)
12574 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12575 place
= next_real_insn (from_insn
);
12577 XEXP (tem
, 0) = place
;
12578 /* If we're deleting the last remaining instruction of a
12579 libcall sequence, don't add the notes. */
12580 else if (XEXP (note
, 0) == from_insn
)
12586 /* If the register is used as an input in I3, it dies there.
12587 Similarly for I2, if it is nonzero and adjacent to I3.
12589 If the register is not used as an input in either I3 or I2
12590 and it is not one of the registers we were supposed to eliminate,
12591 there are two possibilities. We might have a non-adjacent I2
12592 or we might have somehow eliminated an additional register
12593 from a computation. For example, we might have had A & B where
12594 we discover that B will always be zero. In this case we will
12595 eliminate the reference to A.
12597 In both cases, we must search to see if we can find a previous
12598 use of A and put the death note there. */
12601 && GET_CODE (from_insn
) == CALL_INSN
12602 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12604 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12606 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12607 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12612 basic_block bb
= this_basic_block
;
12614 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12616 if (! INSN_P (tem
))
12618 if (tem
== BB_HEAD (bb
))
12623 /* If the register is being set at TEM, see if that is all
12624 TEM is doing. If so, delete TEM. Otherwise, make this
12625 into a REG_UNUSED note instead. */
12626 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12628 rtx set
= single_set (tem
);
12629 rtx inner_dest
= 0;
12631 rtx cc0_setter
= NULL_RTX
;
12635 for (inner_dest
= SET_DEST (set
);
12636 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12637 || GET_CODE (inner_dest
) == SUBREG
12638 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12639 inner_dest
= XEXP (inner_dest
, 0))
12642 /* Verify that it was the set, and not a clobber that
12643 modified the register.
12645 CC0 targets must be careful to maintain setter/user
12646 pairs. If we cannot delete the setter due to side
12647 effects, mark the user with an UNUSED note instead
12650 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12651 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12653 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12654 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12655 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12659 /* Move the notes and links of TEM elsewhere.
12660 This might delete other dead insns recursively.
12661 First set the pattern to something that won't use
12663 rtx old_notes
= REG_NOTES (tem
);
12665 PATTERN (tem
) = pc_rtx
;
12666 REG_NOTES (tem
) = NULL
;
12668 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12669 distribute_links (LOG_LINKS (tem
));
12671 PUT_CODE (tem
, NOTE
);
12672 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12673 NOTE_SOURCE_FILE (tem
) = 0;
12676 /* Delete the setter too. */
12679 PATTERN (cc0_setter
) = pc_rtx
;
12680 old_notes
= REG_NOTES (cc0_setter
);
12681 REG_NOTES (cc0_setter
) = NULL
;
12683 distribute_notes (old_notes
, cc0_setter
,
12684 cc0_setter
, NULL_RTX
);
12685 distribute_links (LOG_LINKS (cc0_setter
));
12687 PUT_CODE (cc0_setter
, NOTE
);
12688 NOTE_LINE_NUMBER (cc0_setter
)
12689 = NOTE_INSN_DELETED
;
12690 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12696 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12698 /* If there isn't already a REG_UNUSED note, put one
12699 here. Do not place a REG_DEAD note, even if
12700 the register is also used here; that would not
12701 match the algorithm used in lifetime analysis
12702 and can cause the consistency check in the
12703 scheduler to fail. */
12704 if (! find_regno_note (tem
, REG_UNUSED
,
12705 REGNO (XEXP (note
, 0))))
12710 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12711 || (GET_CODE (tem
) == CALL_INSN
12712 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12716 /* If we are doing a 3->2 combination, and we have a
12717 register which formerly died in i3 and was not used
12718 by i2, which now no longer dies in i3 and is used in
12719 i2 but does not die in i2, and place is between i2
12720 and i3, then we may need to move a link from place to
12722 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12723 && INSN_CUID (place
) > INSN_CUID (i2
)
12725 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12726 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12728 rtx links
= LOG_LINKS (place
);
12729 LOG_LINKS (place
) = 0;
12730 distribute_links (links
);
12735 if (tem
== BB_HEAD (bb
))
12739 /* We haven't found an insn for the death note and it
12740 is still a REG_DEAD note, but we have hit the beginning
12741 of the block. If the existing life info says the reg
12742 was dead, there's nothing left to do. Otherwise, we'll
12743 need to do a global life update after combine. */
12744 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12745 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12746 REGNO (XEXP (note
, 0))))
12747 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12750 /* If the register is set or already dead at PLACE, we needn't do
12751 anything with this note if it is still a REG_DEAD note.
12752 We can here if it is set at all, not if is it totally replace,
12753 which is what `dead_or_set_p' checks, so also check for it being
12756 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12758 unsigned int regno
= REGNO (XEXP (note
, 0));
12760 /* Similarly, if the instruction on which we want to place
12761 the note is a noop, we'll need do a global live update
12762 after we remove them in delete_noop_moves. */
12763 if (noop_move_p (place
))
12764 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12766 if (dead_or_set_p (place
, XEXP (note
, 0))
12767 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12769 /* Unless the register previously died in PLACE, clear
12770 reg_last_death. [I no longer understand why this is
12772 if (reg_last_death
[regno
] != place
)
12773 reg_last_death
[regno
] = 0;
12777 reg_last_death
[regno
] = place
;
12779 /* If this is a death note for a hard reg that is occupying
12780 multiple registers, ensure that we are still using all
12781 parts of the object. If we find a piece of the object
12782 that is unused, we must arrange for an appropriate REG_DEAD
12783 note to be added for it. However, we can't just emit a USE
12784 and tag the note to it, since the register might actually
12785 be dead; so we recourse, and the recursive call then finds
12786 the previous insn that used this register. */
12788 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12789 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12791 unsigned int endregno
12792 = regno
+ hard_regno_nregs
[regno
]
12793 [GET_MODE (XEXP (note
, 0))];
12797 for (i
= regno
; i
< endregno
; i
++)
12798 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12799 && ! find_regno_fusage (place
, USE
, i
))
12800 || dead_or_set_regno_p (place
, i
))
12805 /* Put only REG_DEAD notes for pieces that are
12806 not already dead or set. */
12808 for (i
= regno
; i
< endregno
;
12809 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12811 rtx piece
= regno_reg_rtx
[i
];
12812 basic_block bb
= this_basic_block
;
12814 if (! dead_or_set_p (place
, piece
)
12815 && ! reg_bitfield_target_p (piece
,
12819 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12821 distribute_notes (new_note
, place
, place
,
12824 else if (! refers_to_regno_p (i
, i
+ 1,
12825 PATTERN (place
), 0)
12826 && ! find_regno_fusage (place
, USE
, i
))
12827 for (tem
= PREV_INSN (place
); ;
12828 tem
= PREV_INSN (tem
))
12830 if (! INSN_P (tem
))
12832 if (tem
== BB_HEAD (bb
))
12834 SET_BIT (refresh_blocks
,
12835 this_basic_block
->index
);
12840 if (dead_or_set_p (tem
, piece
)
12841 || reg_bitfield_target_p (piece
,
12845 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12860 /* Any other notes should not be present at this point in the
12867 XEXP (note
, 1) = REG_NOTES (place
);
12868 REG_NOTES (place
) = note
;
12870 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12871 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12872 && GET_CODE (XEXP (note
, 0)) == REG
)
12873 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12877 if ((REG_NOTE_KIND (note
) == REG_DEAD
12878 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12879 && GET_CODE (XEXP (note
, 0)) == REG
)
12880 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12882 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12883 REG_NOTE_KIND (note
),
12885 REG_NOTES (place2
));
12890 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12891 I3, I2, and I1 to new locations. This is also called to add a link
12892 pointing at I3 when I3's destination is changed. */
12895 distribute_links (rtx links
)
12897 rtx link
, next_link
;
12899 for (link
= links
; link
; link
= next_link
)
12905 next_link
= XEXP (link
, 1);
12907 /* If the insn that this link points to is a NOTE or isn't a single
12908 set, ignore it. In the latter case, it isn't clear what we
12909 can do other than ignore the link, since we can't tell which
12910 register it was for. Such links wouldn't be used by combine
12913 It is not possible for the destination of the target of the link to
12914 have been changed by combine. The only potential of this is if we
12915 replace I3, I2, and I1 by I3 and I2. But in that case the
12916 destination of I2 also remains unchanged. */
12918 if (GET_CODE (XEXP (link
, 0)) == NOTE
12919 || (set
= single_set (XEXP (link
, 0))) == 0)
12922 reg
= SET_DEST (set
);
12923 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12924 || GET_CODE (reg
) == SIGN_EXTRACT
12925 || GET_CODE (reg
) == STRICT_LOW_PART
)
12926 reg
= XEXP (reg
, 0);
12928 /* A LOG_LINK is defined as being placed on the first insn that uses
12929 a register and points to the insn that sets the register. Start
12930 searching at the next insn after the target of the link and stop
12931 when we reach a set of the register or the end of the basic block.
12933 Note that this correctly handles the link that used to point from
12934 I3 to I2. Also note that not much searching is typically done here
12935 since most links don't point very far away. */
12937 for (insn
= NEXT_INSN (XEXP (link
, 0));
12938 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12939 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12940 insn
= NEXT_INSN (insn
))
12941 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12943 if (reg_referenced_p (reg
, PATTERN (insn
)))
12947 else if (GET_CODE (insn
) == CALL_INSN
12948 && find_reg_fusage (insn
, USE
, reg
))
12953 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12956 /* If we found a place to put the link, place it there unless there
12957 is already a link to the same insn as LINK at that point. */
12963 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12964 if (XEXP (link2
, 0) == XEXP (link
, 0))
12969 XEXP (link
, 1) = LOG_LINKS (place
);
12970 LOG_LINKS (place
) = link
;
12972 /* Set added_links_insn to the earliest insn we added a
12974 if (added_links_insn
== 0
12975 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12976 added_links_insn
= place
;
12982 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12985 insn_cuid (rtx insn
)
12987 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12988 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12989 insn
= NEXT_INSN (insn
);
12991 if (INSN_UID (insn
) > max_uid_cuid
)
12994 return INSN_CUID (insn
);
12998 dump_combine_stats (FILE *file
)
13002 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13003 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13007 dump_combine_total_stats (FILE *file
)
13011 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13012 total_attempts
, total_merges
, total_extras
, total_successes
);