1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* Number of attempts to combine instructions in this function. */
96 static int combine_attempts
;
98 /* Number of attempts that got as far as substitution in this function. */
100 static int combine_merges
;
102 /* Number of instructions combined with added SETs in this function. */
104 static int combine_extras
;
106 /* Number of instructions combined in this function. */
108 static int combine_successes
;
110 /* Totals over entire compilation. */
112 static int total_attempts
, total_merges
, total_extras
, total_successes
;
115 /* Vector mapping INSN_UIDs to cuids.
116 The cuids are like uids but increase monotonically always.
117 Combine always uses cuids so that it can compare them.
118 But actually renumbering the uids, which we used to do,
119 proves to be a bad idea because it makes it hard to compare
120 the dumps produced by earlier passes with those from later passes. */
122 static int *uid_cuid
;
123 static int max_uid_cuid
;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) \
128 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
130 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
131 BITS_PER_WORD would invoke undefined behavior. Work around it. */
133 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
134 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
136 #define nonzero_bits(X, M) \
137 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
139 #define num_sign_bit_copies(X, M) \
140 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno
;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, te bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
242 static struct reg_stat
*reg_stat
;
244 /* Record the cuid of the last insn that invalidated memory
245 (anything that writes memory, and subroutine calls, but not pushes). */
247 static int mem_last_set
;
249 /* Record the cuid of the last CALL_INSN
250 so we can tell whether a potential combination crosses any calls. */
252 static int last_call_cuid
;
254 /* When `subst' is called, this is the insn that is being modified
255 (by combining in a previous insn). The PATTERN of this insn
256 is still the old pattern partially modified and it should not be
257 looked at, but this may be used to examine the successors of the insn
258 to judge whether a simplification is valid. */
260 static rtx subst_insn
;
262 /* This is the lowest CUID that `subst' is currently dealing with.
263 get_last_value will not return a value if the register was set at or
264 after this CUID. If not for this mechanism, we could get confused if
265 I2 or I1 in try_combine were an insn that used the old value of a register
266 to obtain a new value. In that case, we might erroneously get the
267 new value of the register when we wanted the old one. */
269 static int subst_low_cuid
;
271 /* This contains any hard registers that are used in newpat; reg_dead_at_p
272 must consider all these registers to be always live. */
274 static HARD_REG_SET newpat_used_regs
;
276 /* This is an insn to which a LOG_LINKS entry has been added. If this
277 insn is the earlier than I2 or I3, combine should rescan starting at
280 static rtx added_links_insn
;
282 /* Basic block in which we are performing combines. */
283 static basic_block this_basic_block
;
285 /* A bitmap indicating which blocks had registers go dead at entry.
286 After combine, we'll need to re-do global life analysis with
287 those blocks as starting points. */
288 static sbitmap refresh_blocks
;
290 /* Incremented for each label. */
292 static int label_tick
;
294 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
295 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
297 static enum machine_mode nonzero_bits_mode
;
299 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
300 be safely used. It is zero while computing them and after combine has
301 completed. This former test prevents propagating values based on
302 previously set values, which can be incorrect if a variable is modified
305 static int nonzero_sign_valid
;
308 /* Record one modification to rtl structure
309 to be undone by storing old_contents into *where.
310 is_int is 1 if the contents are an int. */
316 union {rtx r
; int i
;} old_contents
;
317 union {rtx
*r
; int *i
;} where
;
320 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
321 num_undo says how many are currently recorded.
323 other_insn is nonzero if we have modified some other insn in the process
324 of working on subst_insn. It must be verified too. */
333 static struct undobuf undobuf
;
335 /* Number of times the pseudo being substituted for
336 was found and replaced. */
338 static int n_occurrences
;
340 static void do_SUBST (rtx
*, rtx
);
341 static void do_SUBST_INT (int *, int);
342 static void init_reg_last (void);
343 static void setup_incoming_promotions (void);
344 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
345 static int cant_combine_insn_p (rtx
);
346 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
347 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
348 static int contains_muldiv (rtx
);
349 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
350 static void undo_all (void);
351 static void undo_commit (void);
352 static rtx
*find_split_point (rtx
*, rtx
);
353 static rtx
subst (rtx
, rtx
, rtx
, int, int);
354 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
355 static rtx
simplify_if_then_else (rtx
);
356 static rtx
simplify_set (rtx
);
357 static rtx
simplify_logical (rtx
);
358 static rtx
expand_compound_operation (rtx
);
359 static rtx
expand_field_assignment (rtx
);
360 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
361 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
362 static rtx
extract_left_shift (rtx
, int);
363 static rtx
make_compound_operation (rtx
, enum rtx_code
);
364 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
365 unsigned HOST_WIDE_INT
*);
366 static rtx
force_to_mode (rtx
, enum machine_mode
,
367 unsigned HOST_WIDE_INT
, rtx
, int);
368 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
369 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
370 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
371 static rtx
make_field_assignment (rtx
);
372 static rtx
apply_distributive_law (rtx
);
373 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
374 unsigned HOST_WIDE_INT
);
375 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
376 rtx
, enum machine_mode
,
377 unsigned HOST_WIDE_INT
);
378 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
380 unsigned HOST_WIDE_INT
);
381 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
384 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
385 enum machine_mode
, unsigned int);
386 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
387 HOST_WIDE_INT
, enum machine_mode
, int *);
388 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
390 static int recog_for_combine (rtx
*, rtx
, rtx
*);
391 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
392 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
393 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
394 static void update_table_tick (rtx
);
395 static void record_value_for_reg (rtx
, rtx
, rtx
);
396 static void check_promoted_subreg (rtx
, rtx
);
397 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
398 static void record_dead_and_set_regs (rtx
);
399 static int get_last_value_validate (rtx
*, rtx
, int, int);
400 static rtx
get_last_value (rtx
);
401 static int use_crosses_set_p (rtx
, int);
402 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
403 static int reg_dead_at_p (rtx
, rtx
);
404 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
405 static int reg_bitfield_target_p (rtx
, rtx
);
406 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
407 static void distribute_links (rtx
);
408 static void mark_used_regs_combine (rtx
);
409 static int insn_cuid (rtx
);
410 static void record_promoted_value (rtx
, rtx
);
411 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
412 static enum rtx_code
combine_reversed_comparison_code (rtx
);
413 static int unmentioned_reg_p_1 (rtx
*, void *);
414 static bool unmentioned_reg_p (rtx
, rtx
);
416 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
417 insn. The substitution can be undone by undo_all. If INTO is already
418 set to NEWVAL, do not record this change. Because computing NEWVAL might
419 also call SUBST, we have to compute it before we put anything into
423 do_SUBST (rtx
*into
, rtx newval
)
428 if (oldval
== newval
)
431 /* We'd like to catch as many invalid transformations here as
432 possible. Unfortunately, there are way too many mode changes
433 that are perfectly valid, so we'd waste too much effort for
434 little gain doing the checks here. Focus on catching invalid
435 transformations involving integer constants. */
436 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
437 && GET_CODE (newval
) == CONST_INT
)
439 /* Sanity check that we're replacing oldval with a CONST_INT
440 that is a valid sign-extension for the original mode. */
441 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
445 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
446 CONST_INT is not valid, because after the replacement, the
447 original mode would be gone. Unfortunately, we can't tell
448 when do_SUBST is called to replace the operand thereof, so we
449 perform this test on oldval instead, checking whether an
450 invalid replacement took place before we got here. */
451 if ((GET_CODE (oldval
) == SUBREG
452 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
453 || (GET_CODE (oldval
) == ZERO_EXTEND
454 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
459 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
461 buf
= xmalloc (sizeof (struct undo
));
465 buf
->old_contents
.r
= oldval
;
468 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
471 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
473 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
474 for the value of a HOST_WIDE_INT value (including CONST_INT) is
478 do_SUBST_INT (int *into
, int newval
)
483 if (oldval
== newval
)
487 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
489 buf
= xmalloc (sizeof (struct undo
));
493 buf
->old_contents
.i
= oldval
;
496 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
499 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
501 /* Main entry point for combiner. F is the first insn of the function.
502 NREGS is the first unused pseudo-reg number.
504 Return nonzero if the combiner has turned an indirect jump
505 instruction into a direct jump. */
507 combine_instructions (rtx f
, unsigned int nregs
)
514 rtx links
, nextlinks
;
516 int new_direct_jump_p
= 0;
518 combine_attempts
= 0;
521 combine_successes
= 0;
523 combine_max_regno
= nregs
;
525 /* It is not safe to use ordinary gen_lowpart in combine.
526 See comments in gen_lowpart_for_combine. */
527 gen_lowpart
= gen_lowpart_for_combine
;
529 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
531 init_recog_no_volatile ();
533 /* Compute maximum uid value so uid_cuid can be allocated. */
535 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
536 if (INSN_UID (insn
) > i
)
539 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
542 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
544 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
545 problems when, for example, we have j <<= 1 in a loop. */
547 nonzero_sign_valid
= 0;
549 /* Compute the mapping from uids to cuids.
550 Cuids are numbers assigned to insns, like uids,
551 except that cuids increase monotonically through the code.
553 Scan all SETs and see if we can deduce anything about what
554 bits are known to be zero for some registers and how many copies
555 of the sign bit are known to exist for those registers.
557 Also set any known values so that we can use it while searching
558 for what bits are known to be set. */
562 setup_incoming_promotions ();
564 refresh_blocks
= sbitmap_alloc (last_basic_block
);
565 sbitmap_zero (refresh_blocks
);
567 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
569 uid_cuid
[INSN_UID (insn
)] = ++i
;
575 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
577 record_dead_and_set_regs (insn
);
580 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
581 if (REG_NOTE_KIND (links
) == REG_INC
)
582 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
587 if (GET_CODE (insn
) == CODE_LABEL
)
591 nonzero_sign_valid
= 1;
593 /* Now scan all the insns in forward order. */
599 setup_incoming_promotions ();
601 FOR_EACH_BB (this_basic_block
)
603 for (insn
= BB_HEAD (this_basic_block
);
604 insn
!= NEXT_INSN (BB_END (this_basic_block
));
605 insn
= next
? next
: NEXT_INSN (insn
))
609 if (GET_CODE (insn
) == CODE_LABEL
)
612 else if (INSN_P (insn
))
614 /* See if we know about function return values before this
615 insn based upon SUBREG flags. */
616 check_promoted_subreg (insn
, PATTERN (insn
));
618 /* Try this insn with each insn it links back to. */
620 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
621 if ((next
= try_combine (insn
, XEXP (links
, 0),
622 NULL_RTX
, &new_direct_jump_p
)) != 0)
625 /* Try each sequence of three linked insns ending with this one. */
627 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
629 rtx link
= XEXP (links
, 0);
631 /* If the linked insn has been replaced by a note, then there
632 is no point in pursuing this chain any further. */
633 if (GET_CODE (link
) == NOTE
)
636 for (nextlinks
= LOG_LINKS (link
);
638 nextlinks
= XEXP (nextlinks
, 1))
639 if ((next
= try_combine (insn
, link
,
641 &new_direct_jump_p
)) != 0)
646 /* Try to combine a jump insn that uses CC0
647 with a preceding insn that sets CC0, and maybe with its
648 logical predecessor as well.
649 This is how we make decrement-and-branch insns.
650 We need this special code because data flow connections
651 via CC0 do not get entered in LOG_LINKS. */
653 if (GET_CODE (insn
) == JUMP_INSN
654 && (prev
= prev_nonnote_insn (insn
)) != 0
655 && GET_CODE (prev
) == INSN
656 && sets_cc0_p (PATTERN (prev
)))
658 if ((next
= try_combine (insn
, prev
,
659 NULL_RTX
, &new_direct_jump_p
)) != 0)
662 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
663 nextlinks
= XEXP (nextlinks
, 1))
664 if ((next
= try_combine (insn
, prev
,
666 &new_direct_jump_p
)) != 0)
670 /* Do the same for an insn that explicitly references CC0. */
671 if (GET_CODE (insn
) == INSN
672 && (prev
= prev_nonnote_insn (insn
)) != 0
673 && GET_CODE (prev
) == INSN
674 && sets_cc0_p (PATTERN (prev
))
675 && GET_CODE (PATTERN (insn
)) == SET
676 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
678 if ((next
= try_combine (insn
, prev
,
679 NULL_RTX
, &new_direct_jump_p
)) != 0)
682 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
683 nextlinks
= XEXP (nextlinks
, 1))
684 if ((next
= try_combine (insn
, prev
,
686 &new_direct_jump_p
)) != 0)
690 /* Finally, see if any of the insns that this insn links to
691 explicitly references CC0. If so, try this insn, that insn,
692 and its predecessor if it sets CC0. */
693 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
694 if (GET_CODE (XEXP (links
, 0)) == INSN
695 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
696 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
697 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
698 && GET_CODE (prev
) == INSN
699 && sets_cc0_p (PATTERN (prev
))
700 && (next
= try_combine (insn
, XEXP (links
, 0),
701 prev
, &new_direct_jump_p
)) != 0)
705 /* Try combining an insn with two different insns whose results it
707 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
708 for (nextlinks
= XEXP (links
, 1); nextlinks
;
709 nextlinks
= XEXP (nextlinks
, 1))
710 if ((next
= try_combine (insn
, XEXP (links
, 0),
712 &new_direct_jump_p
)) != 0)
715 /* Try this insn with each REG_EQUAL note it links back to. */
716 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
719 rtx temp
= XEXP (links
, 0);
720 if ((set
= single_set (temp
)) != 0
721 && (note
= find_reg_equal_equiv_note (temp
)) != 0
722 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
723 /* Avoid using a register that may already been marked
724 dead by an earlier instruction. */
725 && ! unmentioned_reg_p (XEXP (note
, 0), SET_SRC (set
)))
727 /* Temporarily replace the set's source with the
728 contents of the REG_EQUAL note. The insn will
729 be deleted or recognized by try_combine. */
730 rtx orig
= SET_SRC (set
);
731 SET_SRC (set
) = XEXP (note
, 0);
732 next
= try_combine (insn
, temp
, NULL_RTX
,
736 SET_SRC (set
) = orig
;
740 if (GET_CODE (insn
) != NOTE
)
741 record_dead_and_set_regs (insn
);
750 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
751 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
752 new_direct_jump_p
|= purge_all_dead_edges (0);
753 delete_noop_moves (f
);
755 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
756 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
757 | PROP_KILL_DEAD_CODE
);
760 sbitmap_free (refresh_blocks
);
765 struct undo
*undo
, *next
;
766 for (undo
= undobuf
.frees
; undo
; undo
= next
)
774 total_attempts
+= combine_attempts
;
775 total_merges
+= combine_merges
;
776 total_extras
+= combine_extras
;
777 total_successes
+= combine_successes
;
779 nonzero_sign_valid
= 0;
780 gen_lowpart
= gen_lowpart_general
;
782 /* Make recognizer allow volatile MEMs again. */
785 return new_direct_jump_p
;
788 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
794 for (i
= 0; i
< combine_max_regno
; i
++)
795 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
798 /* Set up any promoted values for incoming argument registers. */
801 setup_incoming_promotions (void)
805 enum machine_mode mode
;
807 rtx first
= get_insns ();
809 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
811 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
812 /* Check whether this register can hold an incoming pointer
813 argument. FUNCTION_ARG_REGNO_P tests outgoing register
814 numbers, so translate if necessary due to register windows. */
815 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
816 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
819 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
822 gen_rtx_CLOBBER (mode
, const0_rtx
)));
827 /* Called via note_stores. If X is a pseudo that is narrower than
828 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
830 If we are setting only a portion of X and we can't figure out what
831 portion, assume all bits will be used since we don't know what will
834 Similarly, set how many bits of X are known to be copies of the sign bit
835 at all locations in the function. This is the smallest number implied
839 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
840 void *data ATTRIBUTE_UNUSED
)
844 if (GET_CODE (x
) == REG
845 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
846 /* If this register is undefined at the start of the file, we can't
847 say what its contents were. */
848 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
849 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
851 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
853 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
854 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
858 /* If this is a complex assignment, see if we can convert it into a
859 simple assignment. */
860 set
= expand_field_assignment (set
);
862 /* If this is a simple assignment, or we have a paradoxical SUBREG,
863 set what we know about X. */
865 if (SET_DEST (set
) == x
866 || (GET_CODE (SET_DEST (set
)) == SUBREG
867 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
868 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
869 && SUBREG_REG (SET_DEST (set
)) == x
))
871 rtx src
= SET_SRC (set
);
873 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
874 /* If X is narrower than a word and SRC is a non-negative
875 constant that would appear negative in the mode of X,
876 sign-extend it for use in reg_stat[].nonzero_bits because some
877 machines (maybe most) will actually do the sign-extension
878 and this is the conservative approach.
880 ??? For 2.5, try to tighten up the MD files in this regard
881 instead of this kludge. */
883 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
884 && GET_CODE (src
) == CONST_INT
886 && 0 != (INTVAL (src
)
888 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
889 src
= GEN_INT (INTVAL (src
)
890 | ((HOST_WIDE_INT
) (-1)
891 << GET_MODE_BITSIZE (GET_MODE (x
))));
894 /* Don't call nonzero_bits if it cannot change anything. */
895 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
896 reg_stat
[REGNO (x
)].nonzero_bits
897 |= nonzero_bits (src
, nonzero_bits_mode
);
898 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
899 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
900 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
901 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
905 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
906 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
911 /* See if INSN can be combined into I3. PRED and SUCC are optionally
912 insns that were previously combined into I3 or that will be combined
913 into the merger of INSN and I3.
915 Return 0 if the combination is not allowed for any reason.
917 If the combination is allowed, *PDEST will be set to the single
918 destination of INSN and *PSRC to the single source, and this function
922 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
923 rtx
*pdest
, rtx
*psrc
)
926 rtx set
= 0, src
, dest
;
931 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
932 && next_active_insn (succ
) == i3
)
933 : next_active_insn (insn
) == i3
);
935 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
936 or a PARALLEL consisting of such a SET and CLOBBERs.
938 If INSN has CLOBBER parallel parts, ignore them for our processing.
939 By definition, these happen during the execution of the insn. When it
940 is merged with another insn, all bets are off. If they are, in fact,
941 needed and aren't also supplied in I3, they may be added by
942 recog_for_combine. Otherwise, it won't match.
944 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
947 Get the source and destination of INSN. If more than one, can't
950 if (GET_CODE (PATTERN (insn
)) == SET
)
951 set
= PATTERN (insn
);
952 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
953 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
955 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
957 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
960 switch (GET_CODE (elt
))
962 /* This is important to combine floating point insns
965 /* Combining an isolated USE doesn't make sense.
966 We depend here on combinable_i3pat to reject them. */
967 /* The code below this loop only verifies that the inputs of
968 the SET in INSN do not change. We call reg_set_between_p
969 to verify that the REG in the USE does not change between
971 If the USE in INSN was for a pseudo register, the matching
972 insn pattern will likely match any register; combining this
973 with any other USE would only be safe if we knew that the
974 used registers have identical values, or if there was
975 something to tell them apart, e.g. different modes. For
976 now, we forgo such complicated tests and simply disallow
977 combining of USES of pseudo registers with any other USE. */
978 if (GET_CODE (XEXP (elt
, 0)) == REG
979 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
981 rtx i3pat
= PATTERN (i3
);
982 int i
= XVECLEN (i3pat
, 0) - 1;
983 unsigned int regno
= REGNO (XEXP (elt
, 0));
987 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
989 if (GET_CODE (i3elt
) == USE
990 && GET_CODE (XEXP (i3elt
, 0)) == REG
991 && (REGNO (XEXP (i3elt
, 0)) == regno
992 ? reg_set_between_p (XEXP (elt
, 0),
993 PREV_INSN (insn
), i3
)
994 : regno
>= FIRST_PSEUDO_REGISTER
))
1001 /* We can ignore CLOBBERs. */
1006 /* Ignore SETs whose result isn't used but not those that
1007 have side-effects. */
1008 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1009 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1010 || INTVAL (XEXP (note
, 0)) <= 0)
1011 && ! side_effects_p (elt
))
1014 /* If we have already found a SET, this is a second one and
1015 so we cannot combine with this insn. */
1023 /* Anything else means we can't combine. */
1029 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1030 so don't do anything with it. */
1031 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1040 set
= expand_field_assignment (set
);
1041 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1043 /* Don't eliminate a store in the stack pointer. */
1044 if (dest
== stack_pointer_rtx
1045 /* Don't combine with an insn that sets a register to itself if it has
1046 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1047 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1048 /* Can't merge an ASM_OPERANDS. */
1049 || GET_CODE (src
) == ASM_OPERANDS
1050 /* Can't merge a function call. */
1051 || GET_CODE (src
) == CALL
1052 /* Don't eliminate a function call argument. */
1053 || (GET_CODE (i3
) == CALL_INSN
1054 && (find_reg_fusage (i3
, USE
, dest
)
1055 || (GET_CODE (dest
) == REG
1056 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1057 && global_regs
[REGNO (dest
)])))
1058 /* Don't substitute into an incremented register. */
1059 || FIND_REG_INC_NOTE (i3
, dest
)
1060 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1062 /* Don't combine the end of a libcall into anything. */
1063 /* ??? This gives worse code, and appears to be unnecessary, since no
1064 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1065 use REG_RETVAL notes for noconflict blocks, but other code here
1066 makes sure that those insns don't disappear. */
1067 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1069 /* Make sure that DEST is not used after SUCC but before I3. */
1070 || (succ
&& ! all_adjacent
1071 && reg_used_between_p (dest
, succ
, i3
))
1072 /* Make sure that the value that is to be substituted for the register
1073 does not use any registers whose values alter in between. However,
1074 If the insns are adjacent, a use can't cross a set even though we
1075 think it might (this can happen for a sequence of insns each setting
1076 the same destination; last_set of that register might point to
1077 a NOTE). If INSN has a REG_EQUIV note, the register is always
1078 equivalent to the memory so the substitution is valid even if there
1079 are intervening stores. Also, don't move a volatile asm or
1080 UNSPEC_VOLATILE across any other insns. */
1082 && (((GET_CODE (src
) != MEM
1083 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1084 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1085 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1086 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1087 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1088 better register allocation by not doing the combine. */
1089 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1090 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1091 /* Don't combine across a CALL_INSN, because that would possibly
1092 change whether the life span of some REGs crosses calls or not,
1093 and it is a pain to update that information.
1094 Exception: if source is a constant, moving it later can't hurt.
1095 Accept that special case, because it helps -fforce-addr a lot. */
1096 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1099 /* DEST must either be a REG or CC0. */
1100 if (GET_CODE (dest
) == REG
)
1102 /* If register alignment is being enforced for multi-word items in all
1103 cases except for parameters, it is possible to have a register copy
1104 insn referencing a hard register that is not allowed to contain the
1105 mode being copied and which would not be valid as an operand of most
1106 insns. Eliminate this problem by not combining with such an insn.
1108 Also, on some machines we don't want to extend the life of a hard
1111 if (GET_CODE (src
) == REG
1112 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1113 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1114 /* Don't extend the life of a hard register unless it is
1115 user variable (if we have few registers) or it can't
1116 fit into the desired register (meaning something special
1118 Also avoid substituting a return register into I3, because
1119 reload can't handle a conflict with constraints of other
1121 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1122 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1125 else if (GET_CODE (dest
) != CC0
)
1128 /* Don't substitute for a register intended as a clobberable operand.
1129 Similarly, don't substitute an expression containing a register that
1130 will be clobbered in I3. */
1131 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1132 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1133 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1134 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1136 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1139 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1140 or not), reject, unless nothing volatile comes between it and I3 */
1142 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1144 /* Make sure succ doesn't contain a volatile reference. */
1145 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1148 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1149 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1153 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1154 to be an explicit register variable, and was chosen for a reason. */
1156 if (GET_CODE (src
) == ASM_OPERANDS
1157 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1160 /* If there are any volatile insns between INSN and I3, reject, because
1161 they might affect machine state. */
1163 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1164 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1167 /* If INSN or I2 contains an autoincrement or autodecrement,
1168 make sure that register is not used between there and I3,
1169 and not already used in I3 either.
1170 Also insist that I3 not be a jump; if it were one
1171 and the incremented register were spilled, we would lose. */
1174 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1175 if (REG_NOTE_KIND (link
) == REG_INC
1176 && (GET_CODE (i3
) == JUMP_INSN
1177 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1178 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1183 /* Don't combine an insn that follows a CC0-setting insn.
1184 An insn that uses CC0 must not be separated from the one that sets it.
1185 We do, however, allow I2 to follow a CC0-setting insn if that insn
1186 is passed as I1; in that case it will be deleted also.
1187 We also allow combining in this case if all the insns are adjacent
1188 because that would leave the two CC0 insns adjacent as well.
1189 It would be more logical to test whether CC0 occurs inside I1 or I2,
1190 but that would be much slower, and this ought to be equivalent. */
1192 p
= prev_nonnote_insn (insn
);
1193 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1198 /* If we get here, we have passed all the tests and the combination is
1207 /* LOC is the location within I3 that contains its pattern or the component
1208 of a PARALLEL of the pattern. We validate that it is valid for combining.
1210 One problem is if I3 modifies its output, as opposed to replacing it
1211 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1212 so would produce an insn that is not equivalent to the original insns.
1216 (set (reg:DI 101) (reg:DI 100))
1217 (set (subreg:SI (reg:DI 101) 0) <foo>)
1219 This is NOT equivalent to:
1221 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1222 (set (reg:DI 101) (reg:DI 100))])
1224 Not only does this modify 100 (in which case it might still be valid
1225 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1227 We can also run into a problem if I2 sets a register that I1
1228 uses and I1 gets directly substituted into I3 (not via I2). In that
1229 case, we would be getting the wrong value of I2DEST into I3, so we
1230 must reject the combination. This case occurs when I2 and I1 both
1231 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1232 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1233 of a SET must prevent combination from occurring.
1235 Before doing the above check, we first try to expand a field assignment
1236 into a set of logical operations.
1238 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1239 we place a register that is both set and used within I3. If more than one
1240 such register is detected, we fail.
1242 Return 1 if the combination is valid, zero otherwise. */
1245 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1246 int i1_not_in_src
, rtx
*pi3dest_killed
)
1250 if (GET_CODE (x
) == SET
)
1253 rtx dest
= SET_DEST (set
);
1254 rtx src
= SET_SRC (set
);
1255 rtx inner_dest
= dest
;
1257 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1258 || GET_CODE (inner_dest
) == SUBREG
1259 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1260 inner_dest
= XEXP (inner_dest
, 0);
1262 /* Check for the case where I3 modifies its output, as discussed
1263 above. We don't want to prevent pseudos from being combined
1264 into the address of a MEM, so only prevent the combination if
1265 i1 or i2 set the same MEM. */
1266 if ((inner_dest
!= dest
&&
1267 (GET_CODE (inner_dest
) != MEM
1268 || rtx_equal_p (i2dest
, inner_dest
)
1269 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1270 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1271 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1273 /* This is the same test done in can_combine_p except we can't test
1274 all_adjacent; we don't have to, since this instruction will stay
1275 in place, thus we are not considering increasing the lifetime of
1278 Also, if this insn sets a function argument, combining it with
1279 something that might need a spill could clobber a previous
1280 function argument; the all_adjacent test in can_combine_p also
1281 checks this; here, we do a more specific test for this case. */
1283 || (GET_CODE (inner_dest
) == REG
1284 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1285 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1286 GET_MODE (inner_dest
))))
1287 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1290 /* If DEST is used in I3, it is being killed in this insn,
1291 so record that for later.
1292 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1293 STACK_POINTER_REGNUM, since these are always considered to be
1294 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1295 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1296 && reg_referenced_p (dest
, PATTERN (i3
))
1297 && REGNO (dest
) != FRAME_POINTER_REGNUM
1298 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1299 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1301 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1302 && (REGNO (dest
) != ARG_POINTER_REGNUM
1303 || ! fixed_regs
[REGNO (dest
)])
1305 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1307 if (*pi3dest_killed
)
1310 *pi3dest_killed
= dest
;
1314 else if (GET_CODE (x
) == PARALLEL
)
1318 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1319 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1320 i1_not_in_src
, pi3dest_killed
))
1327 /* Return 1 if X is an arithmetic expression that contains a multiplication
1328 and division. We don't count multiplications by powers of two here. */
1331 contains_muldiv (rtx x
)
1333 switch (GET_CODE (x
))
1335 case MOD
: case DIV
: case UMOD
: case UDIV
:
1339 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1340 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1343 return contains_muldiv (XEXP (x
, 0))
1344 || contains_muldiv (XEXP (x
, 1));
1347 return contains_muldiv (XEXP (x
, 0));
1353 /* Determine whether INSN can be used in a combination. Return nonzero if
1354 not. This is used in try_combine to detect early some cases where we
1355 can't perform combinations. */
1358 cant_combine_insn_p (rtx insn
)
1363 /* If this isn't really an insn, we can't do anything.
1364 This can occur when flow deletes an insn that it has merged into an
1365 auto-increment address. */
1366 if (! INSN_P (insn
))
1369 /* Never combine loads and stores involving hard regs that are likely
1370 to be spilled. The register allocator can usually handle such
1371 reg-reg moves by tying. If we allow the combiner to make
1372 substitutions of likely-spilled regs, we may abort in reload.
1373 As an exception, we allow combinations involving fixed regs; these are
1374 not available to the register allocator so there's no risk involved. */
1376 set
= single_set (insn
);
1379 src
= SET_SRC (set
);
1380 dest
= SET_DEST (set
);
1381 if (GET_CODE (src
) == SUBREG
)
1382 src
= SUBREG_REG (src
);
1383 if (GET_CODE (dest
) == SUBREG
)
1384 dest
= SUBREG_REG (dest
);
1385 if (REG_P (src
) && REG_P (dest
)
1386 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1387 && ! fixed_regs
[REGNO (src
)]
1388 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1389 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1390 && ! fixed_regs
[REGNO (dest
)]
1391 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1397 /* Adjust INSN after we made a change to its destination.
1399 Changing the destination can invalidate notes that say something about
1400 the results of the insn and a LOG_LINK pointing to the insn. */
1403 adjust_for_new_dest (rtx insn
)
1407 /* For notes, be conservative and simply remove them. */
1408 loc
= ®_NOTES (insn
);
1411 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1412 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1413 *loc
= XEXP (*loc
, 1);
1415 loc
= &XEXP (*loc
, 1);
1418 /* The new insn will have a destination that was previously the destination
1419 of an insn just above it. Call distribute_links to make a LOG_LINK from
1420 the next use of that destination. */
1421 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1424 /* Try to combine the insns I1 and I2 into I3.
1425 Here I1 and I2 appear earlier than I3.
1426 I1 can be zero; then we combine just I2 into I3.
1428 If we are combining three insns and the resulting insn is not recognized,
1429 try splitting it into two insns. If that happens, I2 and I3 are retained
1430 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1433 Return 0 if the combination does not work. Then nothing is changed.
1434 If we did the combination, return the insn at which combine should
1437 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1438 new direct jump instruction. */
1441 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1443 /* New patterns for I3 and I2, respectively. */
1444 rtx newpat
, newi2pat
= 0;
1445 int substed_i2
= 0, substed_i1
= 0;
1446 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1447 int added_sets_1
, added_sets_2
;
1448 /* Total number of SETs to put into I3. */
1450 /* Nonzero if I2's body now appears in I3. */
1452 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1453 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1454 /* Contains I3 if the destination of I3 is used in its source, which means
1455 that the old life of I3 is being killed. If that usage is placed into
1456 I2 and not in I3, a REG_DEAD note must be made. */
1457 rtx i3dest_killed
= 0;
1458 /* SET_DEST and SET_SRC of I2 and I1. */
1459 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1460 /* PATTERN (I2), or a copy of it in certain cases. */
1462 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1463 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1464 int i1_feeds_i3
= 0;
1465 /* Notes that must be added to REG_NOTES in I3 and I2. */
1466 rtx new_i3_notes
, new_i2_notes
;
1467 /* Notes that we substituted I3 into I2 instead of the normal case. */
1468 int i3_subst_into_i2
= 0;
1469 /* Notes that I1, I2 or I3 is a MULT operation. */
1477 /* Exit early if one of the insns involved can't be used for
1479 if (cant_combine_insn_p (i3
)
1480 || cant_combine_insn_p (i2
)
1481 || (i1
&& cant_combine_insn_p (i1
))
1482 /* We also can't do anything if I3 has a
1483 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1486 /* ??? This gives worse code, and appears to be unnecessary, since no
1487 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1488 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1494 undobuf
.other_insn
= 0;
1496 /* Reset the hard register usage information. */
1497 CLEAR_HARD_REG_SET (newpat_used_regs
);
1499 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1500 code below, set I1 to be the earlier of the two insns. */
1501 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1502 temp
= i1
, i1
= i2
, i2
= temp
;
1504 added_links_insn
= 0;
1506 /* First check for one important special-case that the code below will
1507 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1508 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1509 we may be able to replace that destination with the destination of I3.
1510 This occurs in the common code where we compute both a quotient and
1511 remainder into a structure, in which case we want to do the computation
1512 directly into the structure to avoid register-register copies.
1514 Note that this case handles both multiple sets in I2 and also
1515 cases where I2 has a number of CLOBBER or PARALLELs.
1517 We make very conservative checks below and only try to handle the
1518 most common cases of this. For example, we only handle the case
1519 where I2 and I3 are adjacent to avoid making difficult register
1522 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1523 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1524 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1525 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1526 && GET_CODE (PATTERN (i2
)) == PARALLEL
1527 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1528 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1529 below would need to check what is inside (and reg_overlap_mentioned_p
1530 doesn't support those codes anyway). Don't allow those destinations;
1531 the resulting insn isn't likely to be recognized anyway. */
1532 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1533 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1534 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1535 SET_DEST (PATTERN (i3
)))
1536 && next_real_insn (i2
) == i3
)
1538 rtx p2
= PATTERN (i2
);
1540 /* Make sure that the destination of I3,
1541 which we are going to substitute into one output of I2,
1542 is not used within another output of I2. We must avoid making this:
1543 (parallel [(set (mem (reg 69)) ...)
1544 (set (reg 69) ...)])
1545 which is not well-defined as to order of actions.
1546 (Besides, reload can't handle output reloads for this.)
1548 The problem can also happen if the dest of I3 is a memory ref,
1549 if another dest in I2 is an indirect memory ref. */
1550 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1551 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1552 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1553 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1554 SET_DEST (XVECEXP (p2
, 0, i
))))
1557 if (i
== XVECLEN (p2
, 0))
1558 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1559 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1560 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1561 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1566 subst_low_cuid
= INSN_CUID (i2
);
1568 added_sets_2
= added_sets_1
= 0;
1569 i2dest
= SET_SRC (PATTERN (i3
));
1571 /* Replace the dest in I2 with our dest and make the resulting
1572 insn the new pattern for I3. Then skip to where we
1573 validate the pattern. Everything was set up above. */
1574 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1575 SET_DEST (PATTERN (i3
)));
1578 i3_subst_into_i2
= 1;
1579 goto validate_replacement
;
1583 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1584 one of those words to another constant, merge them by making a new
1587 && (temp
= single_set (i2
)) != 0
1588 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1589 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1590 && GET_CODE (SET_DEST (temp
)) == REG
1591 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1592 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1593 && GET_CODE (PATTERN (i3
)) == SET
1594 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1595 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1596 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1597 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1598 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1600 HOST_WIDE_INT lo
, hi
;
1602 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1603 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1606 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1607 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1610 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1612 /* We don't handle the case of the target word being wider
1613 than a host wide int. */
1614 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1617 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1618 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1619 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1621 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1622 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1623 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1625 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1626 >> (HOST_BITS_PER_WIDE_INT
- 1));
1628 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1629 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1630 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1631 (INTVAL (SET_SRC (PATTERN (i3
)))));
1633 hi
= lo
< 0 ? -1 : 0;
1636 /* We don't handle the case of the higher word not fitting
1637 entirely in either hi or lo. */
1642 subst_low_cuid
= INSN_CUID (i2
);
1643 added_sets_2
= added_sets_1
= 0;
1644 i2dest
= SET_DEST (temp
);
1646 SUBST (SET_SRC (temp
),
1647 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1649 newpat
= PATTERN (i2
);
1650 goto validate_replacement
;
1654 /* If we have no I1 and I2 looks like:
1655 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1657 make up a dummy I1 that is
1660 (set (reg:CC X) (compare:CC Y (const_int 0)))
1662 (We can ignore any trailing CLOBBERs.)
1664 This undoes a previous combination and allows us to match a branch-and-
1667 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1668 && XVECLEN (PATTERN (i2
), 0) >= 2
1669 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1670 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1672 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1673 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1674 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1675 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1676 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1677 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1679 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1680 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1685 /* We make I1 with the same INSN_UID as I2. This gives it
1686 the same INSN_CUID for value tracking. Our fake I1 will
1687 never appear in the insn stream so giving it the same INSN_UID
1688 as I2 will not cause a problem. */
1690 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1691 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1692 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1695 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1696 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1697 SET_DEST (PATTERN (i1
)));
1702 /* Verify that I2 and I1 are valid for combining. */
1703 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1704 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1710 /* Record whether I2DEST is used in I2SRC and similarly for the other
1711 cases. Knowing this will help in register status updating below. */
1712 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1713 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1714 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1716 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1718 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1720 /* Ensure that I3's pattern can be the destination of combines. */
1721 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1722 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1729 /* See if any of the insns is a MULT operation. Unless one is, we will
1730 reject a combination that is, since it must be slower. Be conservative
1732 if (GET_CODE (i2src
) == MULT
1733 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1734 || (GET_CODE (PATTERN (i3
)) == SET
1735 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1738 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1739 We used to do this EXCEPT in one case: I3 has a post-inc in an
1740 output operand. However, that exception can give rise to insns like
1742 which is a famous insn on the PDP-11 where the value of r3 used as the
1743 source was model-dependent. Avoid this sort of thing. */
1746 if (!(GET_CODE (PATTERN (i3
)) == SET
1747 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1748 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1749 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1750 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1751 /* It's not the exception. */
1754 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1755 if (REG_NOTE_KIND (link
) == REG_INC
1756 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1758 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1765 /* See if the SETs in I1 or I2 need to be kept around in the merged
1766 instruction: whenever the value set there is still needed past I3.
1767 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1769 For the SET in I1, we have two cases: If I1 and I2 independently
1770 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1771 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1772 in I1 needs to be kept around unless I1DEST dies or is set in either
1773 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1774 I1DEST. If so, we know I1 feeds into I2. */
1776 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1779 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1780 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1782 /* If the set in I2 needs to be kept around, we must make a copy of
1783 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1784 PATTERN (I2), we are only substituting for the original I1DEST, not into
1785 an already-substituted copy. This also prevents making self-referential
1786 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1789 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1790 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1794 i2pat
= copy_rtx (i2pat
);
1798 /* Substitute in the latest insn for the regs set by the earlier ones. */
1800 maxreg
= max_reg_num ();
1804 /* It is possible that the source of I2 or I1 may be performing an
1805 unneeded operation, such as a ZERO_EXTEND of something that is known
1806 to have the high part zero. Handle that case by letting subst look at
1807 the innermost one of them.
1809 Another way to do this would be to have a function that tries to
1810 simplify a single insn instead of merging two or more insns. We don't
1811 do this because of the potential of infinite loops and because
1812 of the potential extra memory required. However, doing it the way
1813 we are is a bit of a kludge and doesn't catch all cases.
1815 But only do this if -fexpensive-optimizations since it slows things down
1816 and doesn't usually win. */
1818 if (flag_expensive_optimizations
)
1820 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1823 subst_low_cuid
= INSN_CUID (i1
);
1824 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1828 subst_low_cuid
= INSN_CUID (i2
);
1829 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1834 /* Many machines that don't use CC0 have insns that can both perform an
1835 arithmetic operation and set the condition code. These operations will
1836 be represented as a PARALLEL with the first element of the vector
1837 being a COMPARE of an arithmetic operation with the constant zero.
1838 The second element of the vector will set some pseudo to the result
1839 of the same arithmetic operation. If we simplify the COMPARE, we won't
1840 match such a pattern and so will generate an extra insn. Here we test
1841 for this case, where both the comparison and the operation result are
1842 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1843 I2SRC. Later we will make the PARALLEL that contains I2. */
1845 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1846 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1847 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1848 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1850 #ifdef SELECT_CC_MODE
1852 enum machine_mode compare_mode
;
1855 newpat
= PATTERN (i3
);
1856 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1860 #ifdef SELECT_CC_MODE
1861 /* See if a COMPARE with the operand we substituted in should be done
1862 with the mode that is currently being used. If not, do the same
1863 processing we do in `subst' for a SET; namely, if the destination
1864 is used only once, try to replace it with a register of the proper
1865 mode and also replace the COMPARE. */
1866 if (undobuf
.other_insn
== 0
1867 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1868 &undobuf
.other_insn
))
1869 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1871 != GET_MODE (SET_DEST (newpat
))))
1873 unsigned int regno
= REGNO (SET_DEST (newpat
));
1874 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1876 if (regno
< FIRST_PSEUDO_REGISTER
1877 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1878 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1880 if (regno
>= FIRST_PSEUDO_REGISTER
)
1881 SUBST (regno_reg_rtx
[regno
], new_dest
);
1883 SUBST (SET_DEST (newpat
), new_dest
);
1884 SUBST (XEXP (*cc_use
, 0), new_dest
);
1885 SUBST (SET_SRC (newpat
),
1886 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1889 undobuf
.other_insn
= 0;
1896 n_occurrences
= 0; /* `subst' counts here */
1898 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1899 need to make a unique copy of I2SRC each time we substitute it
1900 to avoid self-referential rtl. */
1902 subst_low_cuid
= INSN_CUID (i2
);
1903 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1904 ! i1_feeds_i3
&& i1dest_in_i1src
);
1907 /* Record whether i2's body now appears within i3's body. */
1908 i2_is_used
= n_occurrences
;
1911 /* If we already got a failure, don't try to do more. Otherwise,
1912 try to substitute in I1 if we have it. */
1914 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1916 /* Before we can do this substitution, we must redo the test done
1917 above (see detailed comments there) that ensures that I1DEST
1918 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1920 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1928 subst_low_cuid
= INSN_CUID (i1
);
1929 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1933 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1934 to count all the ways that I2SRC and I1SRC can be used. */
1935 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1936 && i2_is_used
+ added_sets_2
> 1)
1937 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1938 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1940 /* Fail if we tried to make a new register (we used to abort, but there's
1941 really no reason to). */
1942 || max_reg_num () != maxreg
1943 /* Fail if we couldn't do something and have a CLOBBER. */
1944 || GET_CODE (newpat
) == CLOBBER
1945 /* Fail if this new pattern is a MULT and we didn't have one before
1946 at the outer level. */
1947 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1954 /* If the actions of the earlier insns must be kept
1955 in addition to substituting them into the latest one,
1956 we must make a new PARALLEL for the latest insn
1957 to hold additional the SETs. */
1959 if (added_sets_1
|| added_sets_2
)
1963 if (GET_CODE (newpat
) == PARALLEL
)
1965 rtvec old
= XVEC (newpat
, 0);
1966 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1967 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1968 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1969 sizeof (old
->elem
[0]) * old
->num_elem
);
1974 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1975 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1976 XVECEXP (newpat
, 0, 0) = old
;
1980 XVECEXP (newpat
, 0, --total_sets
)
1981 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1982 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1986 /* If there is no I1, use I2's body as is. We used to also not do
1987 the subst call below if I2 was substituted into I3,
1988 but that could lose a simplification. */
1990 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1992 /* See comment where i2pat is assigned. */
1993 XVECEXP (newpat
, 0, --total_sets
)
1994 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1998 /* We come here when we are replacing a destination in I2 with the
1999 destination of I3. */
2000 validate_replacement
:
2002 /* Note which hard regs this insn has as inputs. */
2003 mark_used_regs_combine (newpat
);
2005 /* Is the result of combination a valid instruction? */
2006 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2008 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2009 the second SET's destination is a register that is unused and isn't
2010 marked as an instruction that might trap in an EH region. In that case,
2011 we just need the first SET. This can occur when simplifying a divmod
2012 insn. We *must* test for this case here because the code below that
2013 splits two independent SETs doesn't handle this case correctly when it
2014 updates the register status.
2016 It's pointless doing this if we originally had two sets, one from
2017 i3, and one from i2. Combining then splitting the parallel results
2018 in the original i2 again plus an invalid insn (which we delete).
2019 The net effect is only to move instructions around, which makes
2020 debug info less accurate.
2022 Also check the case where the first SET's destination is unused.
2023 That would not cause incorrect code, but does cause an unneeded
2026 if (insn_code_number
< 0
2027 && !(added_sets_2
&& i1
== 0)
2028 && GET_CODE (newpat
) == PARALLEL
2029 && XVECLEN (newpat
, 0) == 2
2030 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2031 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2032 && asm_noperands (newpat
) < 0)
2034 rtx set0
= XVECEXP (newpat
, 0, 0);
2035 rtx set1
= XVECEXP (newpat
, 0, 1);
2038 if (((GET_CODE (SET_DEST (set1
)) == REG
2039 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2040 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2041 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2042 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2043 || INTVAL (XEXP (note
, 0)) <= 0)
2044 && ! side_effects_p (SET_SRC (set1
)))
2047 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2050 else if (((GET_CODE (SET_DEST (set0
)) == REG
2051 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2052 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2053 && find_reg_note (i3
, REG_UNUSED
,
2054 SUBREG_REG (SET_DEST (set0
)))))
2055 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2056 || INTVAL (XEXP (note
, 0)) <= 0)
2057 && ! side_effects_p (SET_SRC (set0
)))
2060 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2062 if (insn_code_number
>= 0)
2064 /* If we will be able to accept this, we have made a
2065 change to the destination of I3. This requires us to
2066 do a few adjustments. */
2068 PATTERN (i3
) = newpat
;
2069 adjust_for_new_dest (i3
);
2074 /* If we were combining three insns and the result is a simple SET
2075 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2076 insns. There are two ways to do this. It can be split using a
2077 machine-specific method (like when you have an addition of a large
2078 constant) or by combine in the function find_split_point. */
2080 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2081 && asm_noperands (newpat
) < 0)
2083 rtx m_split
, *split
;
2084 rtx ni2dest
= i2dest
;
2086 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2087 use I2DEST as a scratch register will help. In the latter case,
2088 convert I2DEST to the mode of the source of NEWPAT if we can. */
2090 m_split
= split_insns (newpat
, i3
);
2092 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2093 inputs of NEWPAT. */
2095 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2096 possible to try that as a scratch reg. This would require adding
2097 more code to make it work though. */
2099 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2101 /* If I2DEST is a hard register or the only use of a pseudo,
2102 we can change its mode. */
2103 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2104 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2105 && GET_CODE (i2dest
) == REG
2106 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2107 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2108 && ! REG_USERVAR_P (i2dest
))))
2109 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2112 m_split
= split_insns (gen_rtx_PARALLEL
2114 gen_rtvec (2, newpat
,
2115 gen_rtx_CLOBBER (VOIDmode
,
2118 /* If the split with the mode-changed register didn't work, try
2119 the original register. */
2120 if (! m_split
&& ni2dest
!= i2dest
)
2123 m_split
= split_insns (gen_rtx_PARALLEL
2125 gen_rtvec (2, newpat
,
2126 gen_rtx_CLOBBER (VOIDmode
,
2132 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2134 m_split
= PATTERN (m_split
);
2135 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2136 if (insn_code_number
>= 0)
2139 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2140 && (next_real_insn (i2
) == i3
2141 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2144 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2145 newi2pat
= PATTERN (m_split
);
2147 i3set
= single_set (NEXT_INSN (m_split
));
2148 i2set
= single_set (m_split
);
2150 /* In case we changed the mode of I2DEST, replace it in the
2151 pseudo-register table here. We can't do it above in case this
2152 code doesn't get executed and we do a split the other way. */
2154 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2155 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2157 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2159 /* If I2 or I3 has multiple SETs, we won't know how to track
2160 register status, so don't use these insns. If I2's destination
2161 is used between I2 and I3, we also can't use these insns. */
2163 if (i2_code_number
>= 0 && i2set
&& i3set
2164 && (next_real_insn (i2
) == i3
2165 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2166 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2168 if (insn_code_number
>= 0)
2171 /* It is possible that both insns now set the destination of I3.
2172 If so, we must show an extra use of it. */
2174 if (insn_code_number
>= 0)
2176 rtx new_i3_dest
= SET_DEST (i3set
);
2177 rtx new_i2_dest
= SET_DEST (i2set
);
2179 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2180 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2181 || GET_CODE (new_i3_dest
) == SUBREG
)
2182 new_i3_dest
= XEXP (new_i3_dest
, 0);
2184 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2185 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2186 || GET_CODE (new_i2_dest
) == SUBREG
)
2187 new_i2_dest
= XEXP (new_i2_dest
, 0);
2189 if (GET_CODE (new_i3_dest
) == REG
2190 && GET_CODE (new_i2_dest
) == REG
2191 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2192 REG_N_SETS (REGNO (new_i2_dest
))++;
2196 /* If we can split it and use I2DEST, go ahead and see if that
2197 helps things be recognized. Verify that none of the registers
2198 are set between I2 and I3. */
2199 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2201 && GET_CODE (i2dest
) == REG
2203 /* We need I2DEST in the proper mode. If it is a hard register
2204 or the only use of a pseudo, we can change its mode. */
2205 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2206 || GET_MODE (*split
) == VOIDmode
2207 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2208 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2209 && ! REG_USERVAR_P (i2dest
)))
2210 && (next_real_insn (i2
) == i3
2211 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2212 /* We can't overwrite I2DEST if its value is still used by
2214 && ! reg_referenced_p (i2dest
, newpat
))
2216 rtx newdest
= i2dest
;
2217 enum rtx_code split_code
= GET_CODE (*split
);
2218 enum machine_mode split_mode
= GET_MODE (*split
);
2220 /* Get NEWDEST as a register in the proper mode. We have already
2221 validated that we can do this. */
2222 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2224 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2226 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2227 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2230 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2231 an ASHIFT. This can occur if it was inside a PLUS and hence
2232 appeared to be a memory address. This is a kludge. */
2233 if (split_code
== MULT
2234 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2235 && INTVAL (XEXP (*split
, 1)) > 0
2236 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2238 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2239 XEXP (*split
, 0), GEN_INT (i
)));
2240 /* Update split_code because we may not have a multiply
2242 split_code
= GET_CODE (*split
);
2245 #ifdef INSN_SCHEDULING
2246 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2247 be written as a ZERO_EXTEND. */
2248 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2250 #ifdef LOAD_EXTEND_OP
2251 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2252 what it really is. */
2253 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2255 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2256 SUBREG_REG (*split
)));
2259 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2260 SUBREG_REG (*split
)));
2264 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2265 SUBST (*split
, newdest
);
2266 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2268 /* If the split point was a MULT and we didn't have one before,
2269 don't use one now. */
2270 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2271 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2275 /* Check for a case where we loaded from memory in a narrow mode and
2276 then sign extended it, but we need both registers. In that case,
2277 we have a PARALLEL with both loads from the same memory location.
2278 We can split this into a load from memory followed by a register-register
2279 copy. This saves at least one insn, more if register allocation can
2282 We cannot do this if the destination of the first assignment is a
2283 condition code register or cc0. We eliminate this case by making sure
2284 the SET_DEST and SET_SRC have the same mode.
2286 We cannot do this if the destination of the second assignment is
2287 a register that we have already assumed is zero-extended. Similarly
2288 for a SUBREG of such a register. */
2290 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2291 && GET_CODE (newpat
) == PARALLEL
2292 && XVECLEN (newpat
, 0) == 2
2293 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2294 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2295 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2296 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2297 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2298 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2299 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2300 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2302 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2303 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2304 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2305 (GET_CODE (temp
) == REG
2306 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2307 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2308 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2309 && (reg_stat
[REGNO (temp
)].nonzero_bits
2310 != GET_MODE_MASK (word_mode
))))
2311 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2312 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2313 (GET_CODE (temp
) == REG
2314 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2315 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2316 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2317 && (reg_stat
[REGNO (temp
)].nonzero_bits
2318 != GET_MODE_MASK (word_mode
)))))
2319 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2320 SET_SRC (XVECEXP (newpat
, 0, 1)))
2321 && ! find_reg_note (i3
, REG_UNUSED
,
2322 SET_DEST (XVECEXP (newpat
, 0, 0))))
2326 newi2pat
= XVECEXP (newpat
, 0, 0);
2327 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2328 newpat
= XVECEXP (newpat
, 0, 1);
2329 SUBST (SET_SRC (newpat
),
2330 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2331 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2333 if (i2_code_number
>= 0)
2334 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2336 if (insn_code_number
>= 0)
2341 /* If we will be able to accept this, we have made a change to the
2342 destination of I3. This requires us to do a few adjustments. */
2343 PATTERN (i3
) = newpat
;
2344 adjust_for_new_dest (i3
);
2346 /* I3 now uses what used to be its destination and which is
2347 now I2's destination. That means we need a LOG_LINK from
2348 I3 to I2. But we used to have one, so we still will.
2350 However, some later insn might be using I2's dest and have
2351 a LOG_LINK pointing at I3. We must remove this link.
2352 The simplest way to remove the link is to point it at I1,
2353 which we know will be a NOTE. */
2355 for (insn
= NEXT_INSN (i3
);
2356 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2357 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2358 insn
= NEXT_INSN (insn
))
2360 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2362 for (link
= LOG_LINKS (insn
); link
;
2363 link
= XEXP (link
, 1))
2364 if (XEXP (link
, 0) == i3
)
2365 XEXP (link
, 0) = i1
;
2373 /* Similarly, check for a case where we have a PARALLEL of two independent
2374 SETs but we started with three insns. In this case, we can do the sets
2375 as two separate insns. This case occurs when some SET allows two
2376 other insns to combine, but the destination of that SET is still live. */
2378 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2379 && GET_CODE (newpat
) == PARALLEL
2380 && XVECLEN (newpat
, 0) == 2
2381 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2382 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2383 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2384 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2387 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2389 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2390 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2391 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2392 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2393 XVECEXP (newpat
, 0, 0))
2394 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2395 XVECEXP (newpat
, 0, 1))
2396 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2397 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2399 /* Normally, it doesn't matter which of the two is done first,
2400 but it does if one references cc0. In that case, it has to
2403 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2405 newi2pat
= XVECEXP (newpat
, 0, 0);
2406 newpat
= XVECEXP (newpat
, 0, 1);
2411 newi2pat
= XVECEXP (newpat
, 0, 1);
2412 newpat
= XVECEXP (newpat
, 0, 0);
2415 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2417 if (i2_code_number
>= 0)
2418 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2421 /* If it still isn't recognized, fail and change things back the way they
2423 if ((insn_code_number
< 0
2424 /* Is the result a reasonable ASM_OPERANDS? */
2425 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2431 /* If we had to change another insn, make sure it is valid also. */
2432 if (undobuf
.other_insn
)
2434 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2435 rtx new_other_notes
;
2438 CLEAR_HARD_REG_SET (newpat_used_regs
);
2440 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2443 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2449 PATTERN (undobuf
.other_insn
) = other_pat
;
2451 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2452 are still valid. Then add any non-duplicate notes added by
2453 recog_for_combine. */
2454 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2456 next
= XEXP (note
, 1);
2458 if (REG_NOTE_KIND (note
) == REG_UNUSED
2459 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2461 if (GET_CODE (XEXP (note
, 0)) == REG
)
2462 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2464 remove_note (undobuf
.other_insn
, note
);
2468 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2469 if (GET_CODE (XEXP (note
, 0)) == REG
)
2470 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2472 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2473 undobuf
.other_insn
, NULL_RTX
);
2476 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2477 they are adjacent to each other or not. */
2479 rtx p
= prev_nonnote_insn (i3
);
2480 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2481 && sets_cc0_p (newi2pat
))
2489 /* We now know that we can do this combination. Merge the insns and
2490 update the status of registers and LOG_LINKS. */
2493 rtx i3notes
, i2notes
, i1notes
= 0;
2494 rtx i3links
, i2links
, i1links
= 0;
2498 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2500 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2501 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2503 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2505 /* Ensure that we do not have something that should not be shared but
2506 occurs multiple times in the new insns. Check this by first
2507 resetting all the `used' flags and then copying anything is shared. */
2509 reset_used_flags (i3notes
);
2510 reset_used_flags (i2notes
);
2511 reset_used_flags (i1notes
);
2512 reset_used_flags (newpat
);
2513 reset_used_flags (newi2pat
);
2514 if (undobuf
.other_insn
)
2515 reset_used_flags (PATTERN (undobuf
.other_insn
));
2517 i3notes
= copy_rtx_if_shared (i3notes
);
2518 i2notes
= copy_rtx_if_shared (i2notes
);
2519 i1notes
= copy_rtx_if_shared (i1notes
);
2520 newpat
= copy_rtx_if_shared (newpat
);
2521 newi2pat
= copy_rtx_if_shared (newi2pat
);
2522 if (undobuf
.other_insn
)
2523 reset_used_flags (PATTERN (undobuf
.other_insn
));
2525 INSN_CODE (i3
) = insn_code_number
;
2526 PATTERN (i3
) = newpat
;
2528 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2530 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2532 reset_used_flags (call_usage
);
2533 call_usage
= copy_rtx (call_usage
);
2536 replace_rtx (call_usage
, i2dest
, i2src
);
2539 replace_rtx (call_usage
, i1dest
, i1src
);
2541 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2544 if (undobuf
.other_insn
)
2545 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2547 /* We had one special case above where I2 had more than one set and
2548 we replaced a destination of one of those sets with the destination
2549 of I3. In that case, we have to update LOG_LINKS of insns later
2550 in this basic block. Note that this (expensive) case is rare.
2552 Also, in this case, we must pretend that all REG_NOTEs for I2
2553 actually came from I3, so that REG_UNUSED notes from I2 will be
2554 properly handled. */
2556 if (i3_subst_into_i2
)
2558 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2559 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2560 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2561 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2562 && ! find_reg_note (i2
, REG_UNUSED
,
2563 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2564 for (temp
= NEXT_INSN (i2
);
2565 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2566 || BB_HEAD (this_basic_block
) != temp
);
2567 temp
= NEXT_INSN (temp
))
2568 if (temp
!= i3
&& INSN_P (temp
))
2569 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2570 if (XEXP (link
, 0) == i2
)
2571 XEXP (link
, 0) = i3
;
2576 while (XEXP (link
, 1))
2577 link
= XEXP (link
, 1);
2578 XEXP (link
, 1) = i2notes
;
2592 INSN_CODE (i2
) = i2_code_number
;
2593 PATTERN (i2
) = newi2pat
;
2597 PUT_CODE (i2
, NOTE
);
2598 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2599 NOTE_SOURCE_FILE (i2
) = 0;
2606 PUT_CODE (i1
, NOTE
);
2607 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2608 NOTE_SOURCE_FILE (i1
) = 0;
2611 /* Get death notes for everything that is now used in either I3 or
2612 I2 and used to die in a previous insn. If we built two new
2613 patterns, move from I1 to I2 then I2 to I3 so that we get the
2614 proper movement on registers that I2 modifies. */
2618 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2619 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2622 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2625 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2627 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2629 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2631 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2633 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2635 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2636 know these are REG_UNUSED and want them to go to the desired insn,
2637 so we always pass it as i3. We have not counted the notes in
2638 reg_n_deaths yet, so we need to do so now. */
2640 if (newi2pat
&& new_i2_notes
)
2642 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2643 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2644 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2646 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2651 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2652 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2653 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2655 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2658 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2659 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2660 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2661 in that case, it might delete I2. Similarly for I2 and I1.
2662 Show an additional death due to the REG_DEAD note we make here. If
2663 we discard it in distribute_notes, we will decrement it again. */
2667 if (GET_CODE (i3dest_killed
) == REG
)
2668 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2670 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2671 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2673 NULL_RTX
, i2
, NULL_RTX
);
2675 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2677 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2680 if (i2dest_in_i2src
)
2682 if (GET_CODE (i2dest
) == REG
)
2683 REG_N_DEATHS (REGNO (i2dest
))++;
2685 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2686 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2687 NULL_RTX
, i2
, NULL_RTX
);
2689 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2690 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2693 if (i1dest_in_i1src
)
2695 if (GET_CODE (i1dest
) == REG
)
2696 REG_N_DEATHS (REGNO (i1dest
))++;
2698 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2699 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2700 NULL_RTX
, i2
, NULL_RTX
);
2702 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2703 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2706 distribute_links (i3links
);
2707 distribute_links (i2links
);
2708 distribute_links (i1links
);
2710 if (GET_CODE (i2dest
) == REG
)
2713 rtx i2_insn
= 0, i2_val
= 0, set
;
2715 /* The insn that used to set this register doesn't exist, and
2716 this life of the register may not exist either. See if one of
2717 I3's links points to an insn that sets I2DEST. If it does,
2718 that is now the last known value for I2DEST. If we don't update
2719 this and I2 set the register to a value that depended on its old
2720 contents, we will get confused. If this insn is used, thing
2721 will be set correctly in combine_instructions. */
2723 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2724 if ((set
= single_set (XEXP (link
, 0))) != 0
2725 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2726 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2728 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2730 /* If the reg formerly set in I2 died only once and that was in I3,
2731 zero its use count so it won't make `reload' do any work. */
2733 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2734 && ! i2dest_in_i2src
)
2736 regno
= REGNO (i2dest
);
2737 REG_N_SETS (regno
)--;
2741 if (i1
&& GET_CODE (i1dest
) == REG
)
2744 rtx i1_insn
= 0, i1_val
= 0, set
;
2746 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2747 if ((set
= single_set (XEXP (link
, 0))) != 0
2748 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2749 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2751 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2753 regno
= REGNO (i1dest
);
2754 if (! added_sets_1
&& ! i1dest_in_i1src
)
2755 REG_N_SETS (regno
)--;
2758 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2759 been made to this insn. The order of
2760 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2761 can affect nonzero_bits of newpat */
2763 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2764 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2766 /* Set new_direct_jump_p if a new return or simple jump instruction
2769 If I3 is now an unconditional jump, ensure that it has a
2770 BARRIER following it since it may have initially been a
2771 conditional jump. It may also be the last nonnote insn. */
2773 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2775 *new_direct_jump_p
= 1;
2776 mark_jump_label (PATTERN (i3
), i3
, 0);
2778 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2779 || GET_CODE (temp
) != BARRIER
)
2780 emit_barrier_after (i3
);
2783 if (undobuf
.other_insn
!= NULL_RTX
2784 && (returnjump_p (undobuf
.other_insn
)
2785 || any_uncondjump_p (undobuf
.other_insn
)))
2787 *new_direct_jump_p
= 1;
2789 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2790 || GET_CODE (temp
) != BARRIER
)
2791 emit_barrier_after (undobuf
.other_insn
);
2794 /* An NOOP jump does not need barrier, but it does need cleaning up
2796 if (GET_CODE (newpat
) == SET
2797 && SET_SRC (newpat
) == pc_rtx
2798 && SET_DEST (newpat
) == pc_rtx
)
2799 *new_direct_jump_p
= 1;
2802 combine_successes
++;
2805 if (added_links_insn
2806 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2807 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2808 return added_links_insn
;
2810 return newi2pat
? i2
: i3
;
2813 /* Undo all the modifications recorded in undobuf. */
2818 struct undo
*undo
, *next
;
2820 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2824 *undo
->where
.i
= undo
->old_contents
.i
;
2826 *undo
->where
.r
= undo
->old_contents
.r
;
2828 undo
->next
= undobuf
.frees
;
2829 undobuf
.frees
= undo
;
2835 /* We've committed to accepting the changes we made. Move all
2836 of the undos to the free list. */
2841 struct undo
*undo
, *next
;
2843 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2846 undo
->next
= undobuf
.frees
;
2847 undobuf
.frees
= undo
;
2853 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2854 where we have an arithmetic expression and return that point. LOC will
2857 try_combine will call this function to see if an insn can be split into
2861 find_split_point (rtx
*loc
, rtx insn
)
2864 enum rtx_code code
= GET_CODE (x
);
2866 unsigned HOST_WIDE_INT len
= 0;
2867 HOST_WIDE_INT pos
= 0;
2869 rtx inner
= NULL_RTX
;
2871 /* First special-case some codes. */
2875 #ifdef INSN_SCHEDULING
2876 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2878 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2881 return find_split_point (&SUBREG_REG (x
), insn
);
2885 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2886 using LO_SUM and HIGH. */
2887 if (GET_CODE (XEXP (x
, 0)) == CONST
2888 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2891 gen_rtx_LO_SUM (Pmode
,
2892 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2894 return &XEXP (XEXP (x
, 0), 0);
2898 /* If we have a PLUS whose second operand is a constant and the
2899 address is not valid, perhaps will can split it up using
2900 the machine-specific way to split large constants. We use
2901 the first pseudo-reg (one of the virtual regs) as a placeholder;
2902 it will not remain in the result. */
2903 if (GET_CODE (XEXP (x
, 0)) == PLUS
2904 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2905 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2907 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2908 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2911 /* This should have produced two insns, each of which sets our
2912 placeholder. If the source of the second is a valid address,
2913 we can make put both sources together and make a split point
2917 && NEXT_INSN (seq
) != NULL_RTX
2918 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2919 && GET_CODE (seq
) == INSN
2920 && GET_CODE (PATTERN (seq
)) == SET
2921 && SET_DEST (PATTERN (seq
)) == reg
2922 && ! reg_mentioned_p (reg
,
2923 SET_SRC (PATTERN (seq
)))
2924 && GET_CODE (NEXT_INSN (seq
)) == INSN
2925 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2926 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2927 && memory_address_p (GET_MODE (x
),
2928 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2930 rtx src1
= SET_SRC (PATTERN (seq
));
2931 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2933 /* Replace the placeholder in SRC2 with SRC1. If we can
2934 find where in SRC2 it was placed, that can become our
2935 split point and we can replace this address with SRC2.
2936 Just try two obvious places. */
2938 src2
= replace_rtx (src2
, reg
, src1
);
2940 if (XEXP (src2
, 0) == src1
)
2941 split
= &XEXP (src2
, 0);
2942 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2943 && XEXP (XEXP (src2
, 0), 0) == src1
)
2944 split
= &XEXP (XEXP (src2
, 0), 0);
2948 SUBST (XEXP (x
, 0), src2
);
2953 /* If that didn't work, perhaps the first operand is complex and
2954 needs to be computed separately, so make a split point there.
2955 This will occur on machines that just support REG + CONST
2956 and have a constant moved through some previous computation. */
2958 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
2959 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2960 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
2961 return &XEXP (XEXP (x
, 0), 0);
2967 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2968 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2969 we need to put the operand into a register. So split at that
2972 if (SET_DEST (x
) == cc0_rtx
2973 && GET_CODE (SET_SRC (x
)) != COMPARE
2974 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2975 && !OBJECT_P (SET_SRC (x
))
2976 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2977 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
2978 return &SET_SRC (x
);
2981 /* See if we can split SET_SRC as it stands. */
2982 split
= find_split_point (&SET_SRC (x
), insn
);
2983 if (split
&& split
!= &SET_SRC (x
))
2986 /* See if we can split SET_DEST as it stands. */
2987 split
= find_split_point (&SET_DEST (x
), insn
);
2988 if (split
&& split
!= &SET_DEST (x
))
2991 /* See if this is a bitfield assignment with everything constant. If
2992 so, this is an IOR of an AND, so split it into that. */
2993 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2994 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2995 <= HOST_BITS_PER_WIDE_INT
)
2996 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2997 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2998 && GET_CODE (SET_SRC (x
)) == CONST_INT
2999 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3000 + INTVAL (XEXP (SET_DEST (x
), 2)))
3001 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3002 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3004 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3005 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3006 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3007 rtx dest
= XEXP (SET_DEST (x
), 0);
3008 enum machine_mode mode
= GET_MODE (dest
);
3009 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3011 if (BITS_BIG_ENDIAN
)
3012 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3016 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3019 gen_binary (IOR
, mode
,
3020 gen_binary (AND
, mode
, dest
,
3021 gen_int_mode (~(mask
<< pos
),
3023 GEN_INT (src
<< pos
)));
3025 SUBST (SET_DEST (x
), dest
);
3027 split
= find_split_point (&SET_SRC (x
), insn
);
3028 if (split
&& split
!= &SET_SRC (x
))
3032 /* Otherwise, see if this is an operation that we can split into two.
3033 If so, try to split that. */
3034 code
= GET_CODE (SET_SRC (x
));
3039 /* If we are AND'ing with a large constant that is only a single
3040 bit and the result is only being used in a context where we
3041 need to know if it is zero or nonzero, replace it with a bit
3042 extraction. This will avoid the large constant, which might
3043 have taken more than one insn to make. If the constant were
3044 not a valid argument to the AND but took only one insn to make,
3045 this is no worse, but if it took more than one insn, it will
3048 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3049 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3050 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3051 && GET_CODE (SET_DEST (x
)) == REG
3052 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3053 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3054 && XEXP (*split
, 0) == SET_DEST (x
)
3055 && XEXP (*split
, 1) == const0_rtx
)
3057 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3058 XEXP (SET_SRC (x
), 0),
3059 pos
, NULL_RTX
, 1, 1, 0, 0);
3060 if (extraction
!= 0)
3062 SUBST (SET_SRC (x
), extraction
);
3063 return find_split_point (loc
, insn
);
3069 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3070 is known to be on, this can be converted into a NEG of a shift. */
3071 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3072 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3073 && 1 <= (pos
= exact_log2
3074 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3075 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3077 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3081 gen_rtx_LSHIFTRT (mode
,
3082 XEXP (SET_SRC (x
), 0),
3085 split
= find_split_point (&SET_SRC (x
), insn
);
3086 if (split
&& split
!= &SET_SRC (x
))
3092 inner
= XEXP (SET_SRC (x
), 0);
3094 /* We can't optimize if either mode is a partial integer
3095 mode as we don't know how many bits are significant
3097 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3098 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3102 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3108 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3109 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3111 inner
= XEXP (SET_SRC (x
), 0);
3112 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3113 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3115 if (BITS_BIG_ENDIAN
)
3116 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3117 unsignedp
= (code
== ZERO_EXTRACT
);
3125 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3127 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3129 /* For unsigned, we have a choice of a shift followed by an
3130 AND or two shifts. Use two shifts for field sizes where the
3131 constant might be too large. We assume here that we can
3132 always at least get 8-bit constants in an AND insn, which is
3133 true for every current RISC. */
3135 if (unsignedp
&& len
<= 8)
3140 (mode
, gen_lowpart (mode
, inner
),
3142 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3144 split
= find_split_point (&SET_SRC (x
), insn
);
3145 if (split
&& split
!= &SET_SRC (x
))
3152 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3153 gen_rtx_ASHIFT (mode
,
3154 gen_lowpart (mode
, inner
),
3155 GEN_INT (GET_MODE_BITSIZE (mode
)
3157 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3159 split
= find_split_point (&SET_SRC (x
), insn
);
3160 if (split
&& split
!= &SET_SRC (x
))
3165 /* See if this is a simple operation with a constant as the second
3166 operand. It might be that this constant is out of range and hence
3167 could be used as a split point. */
3168 if (BINARY_P (SET_SRC (x
))
3169 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3170 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3171 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3172 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3173 return &XEXP (SET_SRC (x
), 1);
3175 /* Finally, see if this is a simple operation with its first operand
3176 not in a register. The operation might require this operand in a
3177 register, so return it as a split point. We can always do this
3178 because if the first operand were another operation, we would have
3179 already found it as a split point. */
3180 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3181 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3182 return &XEXP (SET_SRC (x
), 0);
3188 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3189 it is better to write this as (not (ior A B)) so we can split it.
3190 Similarly for IOR. */
3191 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3194 gen_rtx_NOT (GET_MODE (x
),
3195 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3197 XEXP (XEXP (x
, 0), 0),
3198 XEXP (XEXP (x
, 1), 0))));
3199 return find_split_point (loc
, insn
);
3202 /* Many RISC machines have a large set of logical insns. If the
3203 second operand is a NOT, put it first so we will try to split the
3204 other operand first. */
3205 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3207 rtx tem
= XEXP (x
, 0);
3208 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3209 SUBST (XEXP (x
, 1), tem
);
3217 /* Otherwise, select our actions depending on our rtx class. */
3218 switch (GET_RTX_CLASS (code
))
3220 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3222 split
= find_split_point (&XEXP (x
, 2), insn
);
3225 /* ... fall through ... */
3227 case RTX_COMM_ARITH
:
3229 case RTX_COMM_COMPARE
:
3230 split
= find_split_point (&XEXP (x
, 1), insn
);
3233 /* ... fall through ... */
3235 /* Some machines have (and (shift ...) ...) insns. If X is not
3236 an AND, but XEXP (X, 0) is, use it as our split point. */
3237 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3238 return &XEXP (x
, 0);
3240 split
= find_split_point (&XEXP (x
, 0), insn
);
3246 /* Otherwise, we don't have a split point. */
3251 /* Throughout X, replace FROM with TO, and return the result.
3252 The result is TO if X is FROM;
3253 otherwise the result is X, but its contents may have been modified.
3254 If they were modified, a record was made in undobuf so that
3255 undo_all will (among other things) return X to its original state.
3257 If the number of changes necessary is too much to record to undo,
3258 the excess changes are not made, so the result is invalid.
3259 The changes already made can still be undone.
3260 undobuf.num_undo is incremented for such changes, so by testing that
3261 the caller can tell whether the result is valid.
3263 `n_occurrences' is incremented each time FROM is replaced.
3265 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3267 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3268 by copying if `n_occurrences' is nonzero. */
3271 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3273 enum rtx_code code
= GET_CODE (x
);
3274 enum machine_mode op0_mode
= VOIDmode
;
3279 /* Two expressions are equal if they are identical copies of a shared
3280 RTX or if they are both registers with the same register number
3283 #define COMBINE_RTX_EQUAL_P(X,Y) \
3285 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3286 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3288 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3291 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3294 /* If X and FROM are the same register but different modes, they will
3295 not have been seen as equal above. However, flow.c will make a
3296 LOG_LINKS entry for that case. If we do nothing, we will try to
3297 rerecognize our original insn and, when it succeeds, we will
3298 delete the feeding insn, which is incorrect.
3300 So force this insn not to match in this (rare) case. */
3301 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3302 && REGNO (x
) == REGNO (from
))
3303 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3305 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3306 of which may contain things that can be combined. */
3307 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3310 /* It is possible to have a subexpression appear twice in the insn.
3311 Suppose that FROM is a register that appears within TO.
3312 Then, after that subexpression has been scanned once by `subst',
3313 the second time it is scanned, TO may be found. If we were
3314 to scan TO here, we would find FROM within it and create a
3315 self-referent rtl structure which is completely wrong. */
3316 if (COMBINE_RTX_EQUAL_P (x
, to
))
3319 /* Parallel asm_operands need special attention because all of the
3320 inputs are shared across the arms. Furthermore, unsharing the
3321 rtl results in recognition failures. Failure to handle this case
3322 specially can result in circular rtl.
3324 Solve this by doing a normal pass across the first entry of the
3325 parallel, and only processing the SET_DESTs of the subsequent
3328 if (code
== PARALLEL
3329 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3330 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3332 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3334 /* If this substitution failed, this whole thing fails. */
3335 if (GET_CODE (new) == CLOBBER
3336 && XEXP (new, 0) == const0_rtx
)
3339 SUBST (XVECEXP (x
, 0, 0), new);
3341 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3343 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3345 if (GET_CODE (dest
) != REG
3346 && GET_CODE (dest
) != CC0
3347 && GET_CODE (dest
) != PC
)
3349 new = subst (dest
, from
, to
, 0, unique_copy
);
3351 /* If this substitution failed, this whole thing fails. */
3352 if (GET_CODE (new) == CLOBBER
3353 && XEXP (new, 0) == const0_rtx
)
3356 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3362 len
= GET_RTX_LENGTH (code
);
3363 fmt
= GET_RTX_FORMAT (code
);
3365 /* We don't need to process a SET_DEST that is a register, CC0,
3366 or PC, so set up to skip this common case. All other cases
3367 where we want to suppress replacing something inside a
3368 SET_SRC are handled via the IN_DEST operand. */
3370 && (GET_CODE (SET_DEST (x
)) == REG
3371 || GET_CODE (SET_DEST (x
)) == CC0
3372 || GET_CODE (SET_DEST (x
)) == PC
))
3375 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3378 op0_mode
= GET_MODE (XEXP (x
, 0));
3380 for (i
= 0; i
< len
; i
++)
3385 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3387 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3389 new = (unique_copy
&& n_occurrences
3390 ? copy_rtx (to
) : to
);
3395 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3398 /* If this substitution failed, this whole thing
3400 if (GET_CODE (new) == CLOBBER
3401 && XEXP (new, 0) == const0_rtx
)
3405 SUBST (XVECEXP (x
, i
, j
), new);
3408 else if (fmt
[i
] == 'e')
3410 /* If this is a register being set, ignore it. */
3413 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3414 || code
== ZERO_EXTRACT
)
3416 && GET_CODE (new) == REG
)
3419 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3421 /* In general, don't install a subreg involving two
3422 modes not tieable. It can worsen register
3423 allocation, and can even make invalid reload
3424 insns, since the reg inside may need to be copied
3425 from in the outside mode, and that may be invalid
3426 if it is an fp reg copied in integer mode.
3428 We allow two exceptions to this: It is valid if
3429 it is inside another SUBREG and the mode of that
3430 SUBREG and the mode of the inside of TO is
3431 tieable and it is valid if X is a SET that copies
3434 if (GET_CODE (to
) == SUBREG
3435 && ! MODES_TIEABLE_P (GET_MODE (to
),
3436 GET_MODE (SUBREG_REG (to
)))
3437 && ! (code
== SUBREG
3438 && MODES_TIEABLE_P (GET_MODE (x
),
3439 GET_MODE (SUBREG_REG (to
))))
3441 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3444 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3446 #ifdef CANNOT_CHANGE_MODE_CLASS
3448 && GET_CODE (to
) == REG
3449 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3450 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3453 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3456 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3460 /* If we are in a SET_DEST, suppress most cases unless we
3461 have gone inside a MEM, in which case we want to
3462 simplify the address. We assume here that things that
3463 are actually part of the destination have their inner
3464 parts in the first expression. This is true for SUBREG,
3465 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3466 things aside from REG and MEM that should appear in a
3468 new = subst (XEXP (x
, i
), from
, to
,
3470 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3471 || code
== ZERO_EXTRACT
))
3473 && i
== 0), unique_copy
);
3475 /* If we found that we will have to reject this combination,
3476 indicate that by returning the CLOBBER ourselves, rather than
3477 an expression containing it. This will speed things up as
3478 well as prevent accidents where two CLOBBERs are considered
3479 to be equal, thus producing an incorrect simplification. */
3481 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3484 if (GET_CODE (x
) == SUBREG
3485 && (GET_CODE (new) == CONST_INT
3486 || GET_CODE (new) == CONST_DOUBLE
))
3488 enum machine_mode mode
= GET_MODE (x
);
3490 x
= simplify_subreg (GET_MODE (x
), new,
3491 GET_MODE (SUBREG_REG (x
)),
3494 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3496 else if (GET_CODE (new) == CONST_INT
3497 && GET_CODE (x
) == ZERO_EXTEND
)
3499 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3500 new, GET_MODE (XEXP (x
, 0)));
3505 SUBST (XEXP (x
, i
), new);
3510 /* Try to simplify X. If the simplification changed the code, it is likely
3511 that further simplification will help, so loop, but limit the number
3512 of repetitions that will be performed. */
3514 for (i
= 0; i
< 4; i
++)
3516 /* If X is sufficiently simple, don't bother trying to do anything
3518 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3519 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3521 if (GET_CODE (x
) == code
)
3524 code
= GET_CODE (x
);
3526 /* We no longer know the original mode of operand 0 since we
3527 have changed the form of X) */
3528 op0_mode
= VOIDmode
;
3534 /* Simplify X, a piece of RTL. We just operate on the expression at the
3535 outer level; call `subst' to simplify recursively. Return the new
3538 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3539 if we are inside a SET_DEST. */
3542 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3544 enum rtx_code code
= GET_CODE (x
);
3545 enum machine_mode mode
= GET_MODE (x
);
3550 /* If this is a commutative operation, put a constant last and a complex
3551 expression first. We don't need to do this for comparisons here. */
3552 if (COMMUTATIVE_ARITH_P (x
)
3553 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3556 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3557 SUBST (XEXP (x
, 1), temp
);
3560 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3561 sign extension of a PLUS with a constant, reverse the order of the sign
3562 extension and the addition. Note that this not the same as the original
3563 code, but overflow is undefined for signed values. Also note that the
3564 PLUS will have been partially moved "inside" the sign-extension, so that
3565 the first operand of X will really look like:
3566 (ashiftrt (plus (ashift A C4) C5) C4).
3568 (plus (ashiftrt (ashift A C4) C2) C4)
3569 and replace the first operand of X with that expression. Later parts
3570 of this function may simplify the expression further.
3572 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3573 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3574 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3576 We do this to simplify address expressions. */
3578 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3579 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3580 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3581 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3582 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3583 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3584 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3585 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3586 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3587 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3588 XEXP (XEXP (x
, 0), 1))) != 0)
3591 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3592 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3593 INTVAL (XEXP (XEXP (x
, 0), 1)));
3595 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3596 INTVAL (XEXP (XEXP (x
, 0), 1)));
3598 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3601 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3602 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3603 things. Check for cases where both arms are testing the same
3606 Don't do anything if all operands are very simple. */
3609 && ((!OBJECT_P (XEXP (x
, 0))
3610 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3611 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3612 || (!OBJECT_P (XEXP (x
, 1))
3613 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3614 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3616 && (!OBJECT_P (XEXP (x
, 0))
3617 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3618 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3620 rtx cond
, true_rtx
, false_rtx
;
3622 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3624 /* If everything is a comparison, what we have is highly unlikely
3625 to be simpler, so don't use it. */
3626 && ! (COMPARISON_P (x
)
3627 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3629 rtx cop1
= const0_rtx
;
3630 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3632 if (cond_code
== NE
&& COMPARISON_P (cond
))
3635 /* Simplify the alternative arms; this may collapse the true and
3636 false arms to store-flag values. Be careful to use copy_rtx
3637 here since true_rtx or false_rtx might share RTL with x as a
3638 result of the if_then_else_cond call above. */
3639 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3640 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3642 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3643 is unlikely to be simpler. */
3644 if (general_operand (true_rtx
, VOIDmode
)
3645 && general_operand (false_rtx
, VOIDmode
))
3647 enum rtx_code reversed
;
3649 /* Restarting if we generate a store-flag expression will cause
3650 us to loop. Just drop through in this case. */
3652 /* If the result values are STORE_FLAG_VALUE and zero, we can
3653 just make the comparison operation. */
3654 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3655 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3656 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3657 && ((reversed
= reversed_comparison_code_parts
3658 (cond_code
, cond
, cop1
, NULL
))
3660 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3662 /* Likewise, we can make the negate of a comparison operation
3663 if the result values are - STORE_FLAG_VALUE and zero. */
3664 else if (GET_CODE (true_rtx
) == CONST_INT
3665 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3666 && false_rtx
== const0_rtx
)
3667 x
= simplify_gen_unary (NEG
, mode
,
3668 gen_binary (cond_code
, mode
, cond
,
3671 else if (GET_CODE (false_rtx
) == CONST_INT
3672 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3673 && true_rtx
== const0_rtx
3674 && ((reversed
= reversed_comparison_code_parts
3675 (cond_code
, cond
, cop1
, NULL
))
3677 x
= simplify_gen_unary (NEG
, mode
,
3678 gen_binary (reversed
, mode
,
3682 return gen_rtx_IF_THEN_ELSE (mode
,
3683 gen_binary (cond_code
, VOIDmode
,
3685 true_rtx
, false_rtx
);
3687 code
= GET_CODE (x
);
3688 op0_mode
= VOIDmode
;
3693 /* Try to fold this expression in case we have constants that weren't
3696 switch (GET_RTX_CLASS (code
))
3699 if (op0_mode
== VOIDmode
)
3700 op0_mode
= GET_MODE (XEXP (x
, 0));
3701 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3704 case RTX_COMM_COMPARE
:
3706 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3707 if (cmp_mode
== VOIDmode
)
3709 cmp_mode
= GET_MODE (XEXP (x
, 1));
3710 if (cmp_mode
== VOIDmode
)
3711 cmp_mode
= op0_mode
;
3713 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3714 XEXP (x
, 0), XEXP (x
, 1));
3717 case RTX_COMM_ARITH
:
3719 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3721 case RTX_BITFIELD_OPS
:
3723 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3724 XEXP (x
, 1), XEXP (x
, 2));
3733 code
= GET_CODE (temp
);
3734 op0_mode
= VOIDmode
;
3735 mode
= GET_MODE (temp
);
3738 /* First see if we can apply the inverse distributive law. */
3739 if (code
== PLUS
|| code
== MINUS
3740 || code
== AND
|| code
== IOR
|| code
== XOR
)
3742 x
= apply_distributive_law (x
);
3743 code
= GET_CODE (x
);
3744 op0_mode
= VOIDmode
;
3747 /* If CODE is an associative operation not otherwise handled, see if we
3748 can associate some operands. This can win if they are constants or
3749 if they are logically related (i.e. (a & b) & a). */
3750 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3751 || code
== AND
|| code
== IOR
|| code
== XOR
3752 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3753 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3754 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3756 if (GET_CODE (XEXP (x
, 0)) == code
)
3758 rtx other
= XEXP (XEXP (x
, 0), 0);
3759 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3760 rtx inner_op1
= XEXP (x
, 1);
3763 /* Make sure we pass the constant operand if any as the second
3764 one if this is a commutative operation. */
3765 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3767 rtx tem
= inner_op0
;
3768 inner_op0
= inner_op1
;
3771 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3772 : code
== DIV
? MULT
3774 mode
, inner_op0
, inner_op1
);
3776 /* For commutative operations, try the other pair if that one
3778 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3780 other
= XEXP (XEXP (x
, 0), 1);
3781 inner
= simplify_binary_operation (code
, mode
,
3782 XEXP (XEXP (x
, 0), 0),
3787 return gen_binary (code
, mode
, other
, inner
);
3791 /* A little bit of algebraic simplification here. */
3795 /* Ensure that our address has any ASHIFTs converted to MULT in case
3796 address-recognizing predicates are called later. */
3797 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3798 SUBST (XEXP (x
, 0), temp
);
3802 if (op0_mode
== VOIDmode
)
3803 op0_mode
= GET_MODE (SUBREG_REG (x
));
3805 /* See if this can be moved to simplify_subreg. */
3806 if (CONSTANT_P (SUBREG_REG (x
))
3807 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3808 /* Don't call gen_lowpart if the inner mode
3809 is VOIDmode and we cannot simplify it, as SUBREG without
3810 inner mode is invalid. */
3811 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3812 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3813 return gen_lowpart (mode
, SUBREG_REG (x
));
3815 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3819 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3825 /* Don't change the mode of the MEM if that would change the meaning
3827 if (GET_CODE (SUBREG_REG (x
)) == MEM
3828 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3829 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3830 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3832 /* Note that we cannot do any narrowing for non-constants since
3833 we might have been counting on using the fact that some bits were
3834 zero. We now do this in the SET. */
3839 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3840 && subreg_lowpart_p (XEXP (x
, 0))
3841 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3842 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3843 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3844 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3846 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3848 x
= gen_rtx_ROTATE (inner_mode
,
3849 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3851 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3852 return gen_lowpart (mode
, x
);
3855 /* Apply De Morgan's laws to reduce number of patterns for machines
3856 with negating logical insns (and-not, nand, etc.). If result has
3857 only one NOT, put it first, since that is how the patterns are
3860 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3862 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3863 enum machine_mode op_mode
;
3865 op_mode
= GET_MODE (in1
);
3866 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3868 op_mode
= GET_MODE (in2
);
3869 if (op_mode
== VOIDmode
)
3871 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3873 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3876 in2
= in1
; in1
= tem
;
3879 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3885 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3886 if (GET_CODE (XEXP (x
, 0)) == XOR
3887 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3888 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3889 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3891 temp
= expand_compound_operation (XEXP (x
, 0));
3893 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3894 replaced by (lshiftrt X C). This will convert
3895 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3897 if (GET_CODE (temp
) == ASHIFTRT
3898 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3899 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3900 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3901 INTVAL (XEXP (temp
, 1)));
3903 /* If X has only a single bit that might be nonzero, say, bit I, convert
3904 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3905 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3906 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3907 or a SUBREG of one since we'd be making the expression more
3908 complex if it was just a register. */
3910 if (GET_CODE (temp
) != REG
3911 && ! (GET_CODE (temp
) == SUBREG
3912 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3913 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3915 rtx temp1
= simplify_shift_const
3916 (NULL_RTX
, ASHIFTRT
, mode
,
3917 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3918 GET_MODE_BITSIZE (mode
) - 1 - i
),
3919 GET_MODE_BITSIZE (mode
) - 1 - i
);
3921 /* If all we did was surround TEMP with the two shifts, we
3922 haven't improved anything, so don't use it. Otherwise,
3923 we are better off with TEMP1. */
3924 if (GET_CODE (temp1
) != ASHIFTRT
3925 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3926 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3932 /* We can't handle truncation to a partial integer mode here
3933 because we don't know the real bitsize of the partial
3935 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3938 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3939 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3940 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3942 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3943 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3945 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3946 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3947 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3948 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3949 return XEXP (XEXP (x
, 0), 0);
3951 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3952 (OP:SI foo:SI) if OP is NEG or ABS. */
3953 if ((GET_CODE (XEXP (x
, 0)) == ABS
3954 || GET_CODE (XEXP (x
, 0)) == NEG
)
3955 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3956 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3957 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3958 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3959 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3961 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3963 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3964 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3965 && subreg_lowpart_p (XEXP (x
, 0)))
3966 return SUBREG_REG (XEXP (x
, 0));
3968 /* If we know that the value is already truncated, we can
3969 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3970 is nonzero for the corresponding modes. But don't do this
3971 for an (LSHIFTRT (MULT ...)) since this will cause problems
3972 with the umulXi3_highpart patterns. */
3973 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3974 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3975 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3976 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3977 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3978 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3979 return gen_lowpart (mode
, XEXP (x
, 0));
3981 /* A truncate of a comparison can be replaced with a subreg if
3982 STORE_FLAG_VALUE permits. This is like the previous test,
3983 but it works even if the comparison is done in a mode larger
3984 than HOST_BITS_PER_WIDE_INT. */
3985 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3986 && COMPARISON_P (XEXP (x
, 0))
3987 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
3988 return gen_lowpart (mode
, XEXP (x
, 0));
3990 /* Similarly, a truncate of a register whose value is a
3991 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3993 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3994 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
3995 && (temp
= get_last_value (XEXP (x
, 0)))
3996 && COMPARISON_P (temp
))
3997 return gen_lowpart (mode
, XEXP (x
, 0));
4001 case FLOAT_TRUNCATE
:
4002 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4003 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4004 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4005 return XEXP (XEXP (x
, 0), 0);
4007 /* (float_truncate:SF (float_truncate:DF foo:XF))
4008 = (float_truncate:SF foo:XF).
4009 This may eliminate double rounding, so it is unsafe.
4011 (float_truncate:SF (float_extend:XF foo:DF))
4012 = (float_truncate:SF foo:DF).
4014 (float_truncate:DF (float_extend:XF foo:SF))
4015 = (float_extend:SF foo:DF). */
4016 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4017 && flag_unsafe_math_optimizations
)
4018 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4019 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4021 > GET_MODE_SIZE (mode
)
4022 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4024 XEXP (XEXP (x
, 0), 0), mode
);
4026 /* (float_truncate (float x)) is (float x) */
4027 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4028 && (flag_unsafe_math_optimizations
4029 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4030 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4031 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4032 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4033 return simplify_gen_unary (FLOAT
, mode
,
4034 XEXP (XEXP (x
, 0), 0),
4035 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4037 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4038 (OP:SF foo:SF) if OP is NEG or ABS. */
4039 if ((GET_CODE (XEXP (x
, 0)) == ABS
4040 || GET_CODE (XEXP (x
, 0)) == NEG
)
4041 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4042 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4043 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4044 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4046 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4047 is (float_truncate:SF x). */
4048 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4049 && subreg_lowpart_p (XEXP (x
, 0))
4050 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4051 return SUBREG_REG (XEXP (x
, 0));
4054 /* (float_extend (float_extend x)) is (float_extend x)
4056 (float_extend (float x)) is (float x) assuming that double
4057 rounding can't happen.
4059 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4060 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4061 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4062 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4063 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4064 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4065 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4066 XEXP (XEXP (x
, 0), 0),
4067 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4072 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4073 using cc0, in which case we want to leave it as a COMPARE
4074 so we can distinguish it from a register-register-copy. */
4075 if (XEXP (x
, 1) == const0_rtx
)
4078 /* x - 0 is the same as x unless x's mode has signed zeros and
4079 allows rounding towards -infinity. Under those conditions,
4081 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4082 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4083 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4089 /* (const (const X)) can become (const X). Do it this way rather than
4090 returning the inner CONST since CONST can be shared with a
4092 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4093 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4098 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4099 can add in an offset. find_split_point will split this address up
4100 again if it doesn't match. */
4101 if (GET_CODE (XEXP (x
, 0)) == HIGH
4102 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4108 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4110 if (GET_CODE (XEXP (x
, 0)) == MULT
4111 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4115 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4116 in2
= XEXP (XEXP (x
, 0), 1);
4117 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4118 gen_binary (MULT
, mode
, in1
, in2
));
4121 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4122 outermost. That's because that's the way indexed addresses are
4123 supposed to appear. This code used to check many more cases, but
4124 they are now checked elsewhere. */
4125 if (GET_CODE (XEXP (x
, 0)) == PLUS
4126 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4127 return gen_binary (PLUS
, mode
,
4128 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4130 XEXP (XEXP (x
, 0), 1));
4132 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4133 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4134 bit-field and can be replaced by either a sign_extend or a
4135 sign_extract. The `and' may be a zero_extend and the two
4136 <c>, -<c> constants may be reversed. */
4137 if (GET_CODE (XEXP (x
, 0)) == XOR
4138 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4139 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4140 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4141 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4142 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4143 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4144 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4145 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4146 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4147 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4148 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4149 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4150 == (unsigned int) i
+ 1))))
4151 return simplify_shift_const
4152 (NULL_RTX
, ASHIFTRT
, mode
,
4153 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4154 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4155 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4156 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4158 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4159 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4160 is 1. This produces better code than the alternative immediately
4162 if (COMPARISON_P (XEXP (x
, 0))
4163 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4164 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4165 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4166 XEXP (XEXP (x
, 0), 0),
4167 XEXP (XEXP (x
, 0), 1))))
4169 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4171 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4172 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4173 the bitsize of the mode - 1. This allows simplification of
4174 "a = (b & 8) == 0;" */
4175 if (XEXP (x
, 1) == constm1_rtx
4176 && GET_CODE (XEXP (x
, 0)) != REG
4177 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4178 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4179 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4180 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4181 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4182 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4183 GET_MODE_BITSIZE (mode
) - 1),
4184 GET_MODE_BITSIZE (mode
) - 1);
4186 /* If we are adding two things that have no bits in common, convert
4187 the addition into an IOR. This will often be further simplified,
4188 for example in cases like ((a & 1) + (a & 2)), which can
4191 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4192 && (nonzero_bits (XEXP (x
, 0), mode
)
4193 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4195 /* Try to simplify the expression further. */
4196 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4197 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4199 /* If we could, great. If not, do not go ahead with the IOR
4200 replacement, since PLUS appears in many special purpose
4201 address arithmetic instructions. */
4202 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4208 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4209 by reversing the comparison code if valid. */
4210 if (STORE_FLAG_VALUE
== 1
4211 && XEXP (x
, 0) == const1_rtx
4212 && COMPARISON_P (XEXP (x
, 1))
4213 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4214 XEXP (XEXP (x
, 1), 0),
4215 XEXP (XEXP (x
, 1), 1))))
4218 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4219 (and <foo> (const_int pow2-1)) */
4220 if (GET_CODE (XEXP (x
, 1)) == AND
4221 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4222 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4223 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4224 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4225 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4227 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4229 if (GET_CODE (XEXP (x
, 1)) == MULT
4230 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4234 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4235 in2
= XEXP (XEXP (x
, 1), 1);
4236 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4240 /* Canonicalize (minus (neg A) (mult B C)) to
4241 (minus (mult (neg B) C) A). */
4242 if (GET_CODE (XEXP (x
, 1)) == MULT
4243 && GET_CODE (XEXP (x
, 0)) == NEG
)
4247 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4248 in2
= XEXP (XEXP (x
, 1), 1);
4249 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4250 XEXP (XEXP (x
, 0), 0));
4253 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4255 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4256 return gen_binary (MINUS
, mode
,
4257 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4258 XEXP (XEXP (x
, 1), 0)),
4259 XEXP (XEXP (x
, 1), 1));
4263 /* If we have (mult (plus A B) C), apply the distributive law and then
4264 the inverse distributive law to see if things simplify. This
4265 occurs mostly in addresses, often when unrolling loops. */
4267 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4269 x
= apply_distributive_law
4270 (gen_binary (PLUS
, mode
,
4271 gen_binary (MULT
, mode
,
4272 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4273 gen_binary (MULT
, mode
,
4274 XEXP (XEXP (x
, 0), 1),
4275 copy_rtx (XEXP (x
, 1)))));
4277 if (GET_CODE (x
) != MULT
)
4280 /* Try simplify a*(b/c) as (a*b)/c. */
4281 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4282 && GET_CODE (XEXP (x
, 0)) == DIV
)
4284 rtx tem
= simplify_binary_operation (MULT
, mode
,
4285 XEXP (XEXP (x
, 0), 0),
4288 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4293 /* If this is a divide by a power of two, treat it as a shift if
4294 its first operand is a shift. */
4295 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4296 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4297 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4298 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4299 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4300 || GET_CODE (XEXP (x
, 0)) == ROTATE
4301 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4302 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4306 case GT
: case GTU
: case GE
: case GEU
:
4307 case LT
: case LTU
: case LE
: case LEU
:
4308 case UNEQ
: case LTGT
:
4309 case UNGT
: case UNGE
:
4310 case UNLT
: case UNLE
:
4311 case UNORDERED
: case ORDERED
:
4312 /* If the first operand is a condition code, we can't do anything
4314 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4315 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4316 && ! CC0_P (XEXP (x
, 0))))
4318 rtx op0
= XEXP (x
, 0);
4319 rtx op1
= XEXP (x
, 1);
4320 enum rtx_code new_code
;
4322 if (GET_CODE (op0
) == COMPARE
)
4323 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4325 /* Simplify our comparison, if possible. */
4326 new_code
= simplify_comparison (code
, &op0
, &op1
);
4328 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4329 if only the low-order bit is possibly nonzero in X (such as when
4330 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4331 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4332 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4335 Remove any ZERO_EXTRACT we made when thinking this was a
4336 comparison. It may now be simpler to use, e.g., an AND. If a
4337 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4338 the call to make_compound_operation in the SET case. */
4340 if (STORE_FLAG_VALUE
== 1
4341 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4342 && op1
== const0_rtx
4343 && mode
== GET_MODE (op0
)
4344 && nonzero_bits (op0
, mode
) == 1)
4345 return gen_lowpart (mode
,
4346 expand_compound_operation (op0
));
4348 else if (STORE_FLAG_VALUE
== 1
4349 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4350 && op1
== const0_rtx
4351 && mode
== GET_MODE (op0
)
4352 && (num_sign_bit_copies (op0
, mode
)
4353 == GET_MODE_BITSIZE (mode
)))
4355 op0
= expand_compound_operation (op0
);
4356 return simplify_gen_unary (NEG
, mode
,
4357 gen_lowpart (mode
, op0
),
4361 else if (STORE_FLAG_VALUE
== 1
4362 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4363 && op1
== const0_rtx
4364 && mode
== GET_MODE (op0
)
4365 && nonzero_bits (op0
, mode
) == 1)
4367 op0
= expand_compound_operation (op0
);
4368 return gen_binary (XOR
, mode
,
4369 gen_lowpart (mode
, op0
),
4373 else if (STORE_FLAG_VALUE
== 1
4374 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4375 && op1
== const0_rtx
4376 && mode
== GET_MODE (op0
)
4377 && (num_sign_bit_copies (op0
, mode
)
4378 == GET_MODE_BITSIZE (mode
)))
4380 op0
= expand_compound_operation (op0
);
4381 return plus_constant (gen_lowpart (mode
, op0
), 1);
4384 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4386 if (STORE_FLAG_VALUE
== -1
4387 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4388 && op1
== const0_rtx
4389 && (num_sign_bit_copies (op0
, mode
)
4390 == GET_MODE_BITSIZE (mode
)))
4391 return gen_lowpart (mode
,
4392 expand_compound_operation (op0
));
4394 else if (STORE_FLAG_VALUE
== -1
4395 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4396 && op1
== const0_rtx
4397 && mode
== GET_MODE (op0
)
4398 && nonzero_bits (op0
, mode
) == 1)
4400 op0
= expand_compound_operation (op0
);
4401 return simplify_gen_unary (NEG
, mode
,
4402 gen_lowpart (mode
, op0
),
4406 else if (STORE_FLAG_VALUE
== -1
4407 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4408 && op1
== const0_rtx
4409 && mode
== GET_MODE (op0
)
4410 && (num_sign_bit_copies (op0
, mode
)
4411 == GET_MODE_BITSIZE (mode
)))
4413 op0
= expand_compound_operation (op0
);
4414 return simplify_gen_unary (NOT
, mode
,
4415 gen_lowpart (mode
, op0
),
4419 /* If X is 0/1, (eq X 0) is X-1. */
4420 else if (STORE_FLAG_VALUE
== -1
4421 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4422 && op1
== const0_rtx
4423 && mode
== GET_MODE (op0
)
4424 && nonzero_bits (op0
, mode
) == 1)
4426 op0
= expand_compound_operation (op0
);
4427 return plus_constant (gen_lowpart (mode
, op0
), -1);
4430 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4431 one bit that might be nonzero, we can convert (ne x 0) to
4432 (ashift x c) where C puts the bit in the sign bit. Remove any
4433 AND with STORE_FLAG_VALUE when we are done, since we are only
4434 going to test the sign bit. */
4435 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4436 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4437 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4438 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4439 && op1
== const0_rtx
4440 && mode
== GET_MODE (op0
)
4441 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4443 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4444 expand_compound_operation (op0
),
4445 GET_MODE_BITSIZE (mode
) - 1 - i
);
4446 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4452 /* If the code changed, return a whole new comparison. */
4453 if (new_code
!= code
)
4454 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4456 /* Otherwise, keep this operation, but maybe change its operands.
4457 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4458 SUBST (XEXP (x
, 0), op0
);
4459 SUBST (XEXP (x
, 1), op1
);
4464 return simplify_if_then_else (x
);
4470 /* If we are processing SET_DEST, we are done. */
4474 return expand_compound_operation (x
);
4477 return simplify_set (x
);
4482 return simplify_logical (x
);
4485 /* (abs (neg <foo>)) -> (abs <foo>) */
4486 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4487 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4489 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4491 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4494 /* If operand is something known to be positive, ignore the ABS. */
4495 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4496 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4497 <= HOST_BITS_PER_WIDE_INT
)
4498 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4499 & ((HOST_WIDE_INT
) 1
4500 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4504 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4505 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4506 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4511 /* (ffs (*_extend <X>)) = (ffs <X>) */
4512 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4513 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4514 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4519 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4520 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4521 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4525 /* (float (sign_extend <X>)) = (float <X>). */
4526 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4527 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4535 /* If this is a shift by a constant amount, simplify it. */
4536 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4537 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4538 INTVAL (XEXP (x
, 1)));
4540 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4542 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4544 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4551 rtx op0
= XEXP (x
, 0);
4552 rtx op1
= XEXP (x
, 1);
4555 if (GET_CODE (op1
) != PARALLEL
)
4557 len
= XVECLEN (op1
, 0);
4559 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4560 && GET_CODE (op0
) == VEC_CONCAT
)
4562 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4564 /* Try to find the element in the VEC_CONCAT. */
4567 if (GET_MODE (op0
) == GET_MODE (x
))
4569 if (GET_CODE (op0
) == VEC_CONCAT
)
4571 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4572 if (op0_size
< offset
)
4573 op0
= XEXP (op0
, 0);
4577 op0
= XEXP (op0
, 1);
4595 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4598 simplify_if_then_else (rtx x
)
4600 enum machine_mode mode
= GET_MODE (x
);
4601 rtx cond
= XEXP (x
, 0);
4602 rtx true_rtx
= XEXP (x
, 1);
4603 rtx false_rtx
= XEXP (x
, 2);
4604 enum rtx_code true_code
= GET_CODE (cond
);
4605 int comparison_p
= COMPARISON_P (cond
);
4608 enum rtx_code false_code
;
4611 /* Simplify storing of the truth value. */
4612 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4613 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4615 /* Also when the truth value has to be reversed. */
4617 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4618 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4622 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4623 in it is being compared against certain values. Get the true and false
4624 comparisons and see if that says anything about the value of each arm. */
4627 && ((false_code
= combine_reversed_comparison_code (cond
))
4629 && GET_CODE (XEXP (cond
, 0)) == REG
)
4632 rtx from
= XEXP (cond
, 0);
4633 rtx true_val
= XEXP (cond
, 1);
4634 rtx false_val
= true_val
;
4637 /* If FALSE_CODE is EQ, swap the codes and arms. */
4639 if (false_code
== EQ
)
4641 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4642 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4645 /* If we are comparing against zero and the expression being tested has
4646 only a single bit that might be nonzero, that is its value when it is
4647 not equal to zero. Similarly if it is known to be -1 or 0. */
4649 if (true_code
== EQ
&& true_val
== const0_rtx
4650 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4651 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4652 else if (true_code
== EQ
&& true_val
== const0_rtx
4653 && (num_sign_bit_copies (from
, GET_MODE (from
))
4654 == GET_MODE_BITSIZE (GET_MODE (from
))))
4655 false_code
= EQ
, false_val
= constm1_rtx
;
4657 /* Now simplify an arm if we know the value of the register in the
4658 branch and it is used in the arm. Be careful due to the potential
4659 of locally-shared RTL. */
4661 if (reg_mentioned_p (from
, true_rtx
))
4662 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4664 pc_rtx
, pc_rtx
, 0, 0);
4665 if (reg_mentioned_p (from
, false_rtx
))
4666 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4668 pc_rtx
, pc_rtx
, 0, 0);
4670 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4671 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4673 true_rtx
= XEXP (x
, 1);
4674 false_rtx
= XEXP (x
, 2);
4675 true_code
= GET_CODE (cond
);
4678 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4679 reversed, do so to avoid needing two sets of patterns for
4680 subtract-and-branch insns. Similarly if we have a constant in the true
4681 arm, the false arm is the same as the first operand of the comparison, or
4682 the false arm is more complicated than the true arm. */
4685 && combine_reversed_comparison_code (cond
) != UNKNOWN
4686 && (true_rtx
== pc_rtx
4687 || (CONSTANT_P (true_rtx
)
4688 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4689 || true_rtx
== const0_rtx
4690 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4691 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4692 && !OBJECT_P (false_rtx
))
4693 || reg_mentioned_p (true_rtx
, false_rtx
)
4694 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4696 true_code
= reversed_comparison_code (cond
, NULL
);
4698 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4701 SUBST (XEXP (x
, 1), false_rtx
);
4702 SUBST (XEXP (x
, 2), true_rtx
);
4704 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4707 /* It is possible that the conditional has been simplified out. */
4708 true_code
= GET_CODE (cond
);
4709 comparison_p
= COMPARISON_P (cond
);
4712 /* If the two arms are identical, we don't need the comparison. */
4714 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4717 /* Convert a == b ? b : a to "a". */
4718 if (true_code
== EQ
&& ! side_effects_p (cond
)
4719 && !HONOR_NANS (mode
)
4720 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4721 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4723 else if (true_code
== NE
&& ! side_effects_p (cond
)
4724 && !HONOR_NANS (mode
)
4725 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4726 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4729 /* Look for cases where we have (abs x) or (neg (abs X)). */
4731 if (GET_MODE_CLASS (mode
) == MODE_INT
4732 && GET_CODE (false_rtx
) == NEG
4733 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4735 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4736 && ! side_effects_p (true_rtx
))
4741 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4745 simplify_gen_unary (NEG
, mode
,
4746 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4752 /* Look for MIN or MAX. */
4754 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4756 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4757 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4758 && ! side_effects_p (cond
))
4763 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4766 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4769 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4772 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4777 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4778 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4779 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4780 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4781 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4782 neither 1 or -1, but it isn't worth checking for. */
4784 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4786 && GET_MODE_CLASS (mode
) == MODE_INT
4787 && ! side_effects_p (x
))
4789 rtx t
= make_compound_operation (true_rtx
, SET
);
4790 rtx f
= make_compound_operation (false_rtx
, SET
);
4791 rtx cond_op0
= XEXP (cond
, 0);
4792 rtx cond_op1
= XEXP (cond
, 1);
4793 enum rtx_code op
= NIL
, extend_op
= NIL
;
4794 enum machine_mode m
= mode
;
4795 rtx z
= 0, c1
= NULL_RTX
;
4797 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4798 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4799 || GET_CODE (t
) == ASHIFT
4800 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4801 && rtx_equal_p (XEXP (t
, 0), f
))
4802 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4804 /* If an identity-zero op is commutative, check whether there
4805 would be a match if we swapped the operands. */
4806 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4807 || GET_CODE (t
) == XOR
)
4808 && rtx_equal_p (XEXP (t
, 1), f
))
4809 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4810 else if (GET_CODE (t
) == SIGN_EXTEND
4811 && (GET_CODE (XEXP (t
, 0)) == PLUS
4812 || GET_CODE (XEXP (t
, 0)) == MINUS
4813 || GET_CODE (XEXP (t
, 0)) == IOR
4814 || GET_CODE (XEXP (t
, 0)) == XOR
4815 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4816 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4817 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4818 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4819 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4820 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4821 && (num_sign_bit_copies (f
, GET_MODE (f
))
4823 (GET_MODE_BITSIZE (mode
)
4824 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4826 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4827 extend_op
= SIGN_EXTEND
;
4828 m
= GET_MODE (XEXP (t
, 0));
4830 else if (GET_CODE (t
) == SIGN_EXTEND
4831 && (GET_CODE (XEXP (t
, 0)) == PLUS
4832 || GET_CODE (XEXP (t
, 0)) == IOR
4833 || GET_CODE (XEXP (t
, 0)) == XOR
)
4834 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4835 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4836 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4837 && (num_sign_bit_copies (f
, GET_MODE (f
))
4839 (GET_MODE_BITSIZE (mode
)
4840 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4842 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4843 extend_op
= SIGN_EXTEND
;
4844 m
= GET_MODE (XEXP (t
, 0));
4846 else if (GET_CODE (t
) == ZERO_EXTEND
4847 && (GET_CODE (XEXP (t
, 0)) == PLUS
4848 || GET_CODE (XEXP (t
, 0)) == MINUS
4849 || GET_CODE (XEXP (t
, 0)) == IOR
4850 || GET_CODE (XEXP (t
, 0)) == XOR
4851 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4852 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4853 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4854 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4855 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4856 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4857 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4858 && ((nonzero_bits (f
, GET_MODE (f
))
4859 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4862 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4863 extend_op
= ZERO_EXTEND
;
4864 m
= GET_MODE (XEXP (t
, 0));
4866 else if (GET_CODE (t
) == ZERO_EXTEND
4867 && (GET_CODE (XEXP (t
, 0)) == PLUS
4868 || GET_CODE (XEXP (t
, 0)) == IOR
4869 || GET_CODE (XEXP (t
, 0)) == XOR
)
4870 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4871 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4872 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4873 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4874 && ((nonzero_bits (f
, GET_MODE (f
))
4875 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4878 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4879 extend_op
= ZERO_EXTEND
;
4880 m
= GET_MODE (XEXP (t
, 0));
4885 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4886 pc_rtx
, pc_rtx
, 0, 0);
4887 temp
= gen_binary (MULT
, m
, temp
,
4888 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4889 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4890 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
4892 if (extend_op
!= NIL
)
4893 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4899 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4900 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4901 negation of a single bit, we can convert this operation to a shift. We
4902 can actually do this more generally, but it doesn't seem worth it. */
4904 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4905 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4906 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4907 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4908 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4909 == GET_MODE_BITSIZE (mode
))
4910 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4912 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4913 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
4915 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4916 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4917 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4918 && GET_MODE (XEXP (cond
, 0)) == mode
4919 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4920 == nonzero_bits (XEXP (cond
, 0), mode
)
4921 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4922 return XEXP (cond
, 0);
4927 /* Simplify X, a SET expression. Return the new expression. */
4930 simplify_set (rtx x
)
4932 rtx src
= SET_SRC (x
);
4933 rtx dest
= SET_DEST (x
);
4934 enum machine_mode mode
4935 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4939 /* (set (pc) (return)) gets written as (return). */
4940 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4943 /* Now that we know for sure which bits of SRC we are using, see if we can
4944 simplify the expression for the object knowing that we only need the
4947 if (GET_MODE_CLASS (mode
) == MODE_INT
4948 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4950 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4951 SUBST (SET_SRC (x
), src
);
4954 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4955 the comparison result and try to simplify it unless we already have used
4956 undobuf.other_insn. */
4957 if ((GET_MODE_CLASS (mode
) == MODE_CC
4958 || GET_CODE (src
) == COMPARE
4960 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4961 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4962 && COMPARISON_P (*cc_use
)
4963 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4965 enum rtx_code old_code
= GET_CODE (*cc_use
);
4966 enum rtx_code new_code
;
4968 int other_changed
= 0;
4969 enum machine_mode compare_mode
= GET_MODE (dest
);
4971 if (GET_CODE (src
) == COMPARE
)
4972 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4974 op0
= src
, op1
= const0_rtx
;
4976 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
4979 new_code
= old_code
;
4980 else if (!CONSTANT_P (tmp
))
4982 new_code
= GET_CODE (tmp
);
4983 op0
= XEXP (tmp
, 0);
4984 op1
= XEXP (tmp
, 1);
4988 rtx pat
= PATTERN (other_insn
);
4989 undobuf
.other_insn
= other_insn
;
4990 SUBST (*cc_use
, tmp
);
4992 /* Attempt to simplify CC user. */
4993 if (GET_CODE (pat
) == SET
)
4995 rtx
new = simplify_rtx (SET_SRC (pat
));
4996 if (new != NULL_RTX
)
4997 SUBST (SET_SRC (pat
), new);
5000 /* Convert X into a no-op move. */
5001 SUBST (SET_DEST (x
), pc_rtx
);
5002 SUBST (SET_SRC (x
), pc_rtx
);
5006 /* Simplify our comparison, if possible. */
5007 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5009 #ifdef SELECT_CC_MODE
5010 /* If this machine has CC modes other than CCmode, check to see if we
5011 need to use a different CC mode here. */
5012 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5013 compare_mode
= GET_MODE (op0
);
5015 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5018 /* If the mode changed, we have to change SET_DEST, the mode in the
5019 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5020 a hard register, just build new versions with the proper mode. If it
5021 is a pseudo, we lose unless it is only time we set the pseudo, in
5022 which case we can safely change its mode. */
5023 if (compare_mode
!= GET_MODE (dest
))
5025 unsigned int regno
= REGNO (dest
);
5026 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5028 if (regno
< FIRST_PSEUDO_REGISTER
5029 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5031 if (regno
>= FIRST_PSEUDO_REGISTER
)
5032 SUBST (regno_reg_rtx
[regno
], new_dest
);
5034 SUBST (SET_DEST (x
), new_dest
);
5035 SUBST (XEXP (*cc_use
, 0), new_dest
);
5042 #endif /* SELECT_CC_MODE */
5044 /* If the code changed, we have to build a new comparison in
5045 undobuf.other_insn. */
5046 if (new_code
!= old_code
)
5048 int other_changed_previously
= other_changed
;
5049 unsigned HOST_WIDE_INT mask
;
5051 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5055 /* If the only change we made was to change an EQ into an NE or
5056 vice versa, OP0 has only one bit that might be nonzero, and OP1
5057 is zero, check if changing the user of the condition code will
5058 produce a valid insn. If it won't, we can keep the original code
5059 in that insn by surrounding our operation with an XOR. */
5061 if (((old_code
== NE
&& new_code
== EQ
)
5062 || (old_code
== EQ
&& new_code
== NE
))
5063 && ! other_changed_previously
&& op1
== const0_rtx
5064 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5065 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5067 rtx pat
= PATTERN (other_insn
), note
= 0;
5069 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5070 && ! check_asm_operands (pat
)))
5072 PUT_CODE (*cc_use
, old_code
);
5075 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5081 undobuf
.other_insn
= other_insn
;
5084 /* If we are now comparing against zero, change our source if
5085 needed. If we do not use cc0, we always have a COMPARE. */
5086 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5088 SUBST (SET_SRC (x
), op0
);
5094 /* Otherwise, if we didn't previously have a COMPARE in the
5095 correct mode, we need one. */
5096 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5098 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5103 /* Otherwise, update the COMPARE if needed. */
5104 SUBST (XEXP (src
, 0), op0
);
5105 SUBST (XEXP (src
, 1), op1
);
5110 /* Get SET_SRC in a form where we have placed back any
5111 compound expressions. Then do the checks below. */
5112 src
= make_compound_operation (src
, SET
);
5113 SUBST (SET_SRC (x
), src
);
5116 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5117 and X being a REG or (subreg (reg)), we may be able to convert this to
5118 (set (subreg:m2 x) (op)).
5120 We can always do this if M1 is narrower than M2 because that means that
5121 we only care about the low bits of the result.
5123 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5124 perform a narrower operation than requested since the high-order bits will
5125 be undefined. On machine where it is defined, this transformation is safe
5126 as long as M1 and M2 have the same number of words. */
5128 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5129 && !OBJECT_P (SUBREG_REG (src
))
5130 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5132 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5133 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5134 #ifndef WORD_REGISTER_OPERATIONS
5135 && (GET_MODE_SIZE (GET_MODE (src
))
5136 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5138 #ifdef CANNOT_CHANGE_MODE_CLASS
5139 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5140 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5141 GET_MODE (SUBREG_REG (src
)),
5144 && (GET_CODE (dest
) == REG
5145 || (GET_CODE (dest
) == SUBREG
5146 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5148 SUBST (SET_DEST (x
),
5149 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5151 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5153 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5157 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5160 && GET_CODE (src
) == SUBREG
5161 && subreg_lowpart_p (src
)
5162 && (GET_MODE_BITSIZE (GET_MODE (src
))
5163 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5165 rtx inner
= SUBREG_REG (src
);
5166 enum machine_mode inner_mode
= GET_MODE (inner
);
5168 /* Here we make sure that we don't have a sign bit on. */
5169 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5170 && (nonzero_bits (inner
, inner_mode
)
5171 < ((unsigned HOST_WIDE_INT
) 1
5172 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5174 SUBST (SET_SRC (x
), inner
);
5180 #ifdef LOAD_EXTEND_OP
5181 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5182 would require a paradoxical subreg. Replace the subreg with a
5183 zero_extend to avoid the reload that would otherwise be required. */
5185 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5186 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5187 && SUBREG_BYTE (src
) == 0
5188 && (GET_MODE_SIZE (GET_MODE (src
))
5189 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5190 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5193 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5194 GET_MODE (src
), SUBREG_REG (src
)));
5200 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5201 are comparing an item known to be 0 or -1 against 0, use a logical
5202 operation instead. Check for one of the arms being an IOR of the other
5203 arm with some value. We compute three terms to be IOR'ed together. In
5204 practice, at most two will be nonzero. Then we do the IOR's. */
5206 if (GET_CODE (dest
) != PC
5207 && GET_CODE (src
) == IF_THEN_ELSE
5208 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5209 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5210 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5211 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5212 #ifdef HAVE_conditional_move
5213 && ! can_conditionally_move_p (GET_MODE (src
))
5215 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5216 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5217 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5218 && ! side_effects_p (src
))
5220 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5221 ? XEXP (src
, 1) : XEXP (src
, 2));
5222 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5223 ? XEXP (src
, 2) : XEXP (src
, 1));
5224 rtx term1
= const0_rtx
, term2
, term3
;
5226 if (GET_CODE (true_rtx
) == IOR
5227 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5228 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5229 else if (GET_CODE (true_rtx
) == IOR
5230 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5231 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5232 else if (GET_CODE (false_rtx
) == IOR
5233 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5234 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5235 else if (GET_CODE (false_rtx
) == IOR
5236 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5237 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5239 term2
= gen_binary (AND
, GET_MODE (src
),
5240 XEXP (XEXP (src
, 0), 0), true_rtx
);
5241 term3
= gen_binary (AND
, GET_MODE (src
),
5242 simplify_gen_unary (NOT
, GET_MODE (src
),
5243 XEXP (XEXP (src
, 0), 0),
5248 gen_binary (IOR
, GET_MODE (src
),
5249 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5255 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5256 whole thing fail. */
5257 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5259 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5262 /* Convert this into a field assignment operation, if possible. */
5263 return make_field_assignment (x
);
5266 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5270 simplify_logical (rtx x
)
5272 enum machine_mode mode
= GET_MODE (x
);
5273 rtx op0
= XEXP (x
, 0);
5274 rtx op1
= XEXP (x
, 1);
5277 switch (GET_CODE (x
))
5280 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5281 insn (and may simplify more). */
5282 if (GET_CODE (op0
) == XOR
5283 && rtx_equal_p (XEXP (op0
, 0), op1
)
5284 && ! side_effects_p (op1
))
5285 x
= gen_binary (AND
, mode
,
5286 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5289 if (GET_CODE (op0
) == XOR
5290 && rtx_equal_p (XEXP (op0
, 1), op1
)
5291 && ! side_effects_p (op1
))
5292 x
= gen_binary (AND
, mode
,
5293 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5296 /* Similarly for (~(A ^ B)) & A. */
5297 if (GET_CODE (op0
) == NOT
5298 && GET_CODE (XEXP (op0
, 0)) == XOR
5299 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5300 && ! side_effects_p (op1
))
5301 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5303 if (GET_CODE (op0
) == NOT
5304 && GET_CODE (XEXP (op0
, 0)) == XOR
5305 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5306 && ! side_effects_p (op1
))
5307 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5309 /* We can call simplify_and_const_int only if we don't lose
5310 any (sign) bits when converting INTVAL (op1) to
5311 "unsigned HOST_WIDE_INT". */
5312 if (GET_CODE (op1
) == CONST_INT
5313 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5314 || INTVAL (op1
) > 0))
5316 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5318 /* If we have (ior (and (X C1) C2)) and the next restart would be
5319 the last, simplify this by making C1 as small as possible
5320 and then exit. Only do this if C1 actually changes: for now
5321 this only saves memory but, should this transformation be
5322 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5323 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5324 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5325 && GET_CODE (op1
) == CONST_INT
5326 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5327 return gen_binary (IOR
, mode
,
5328 gen_binary (AND
, mode
, XEXP (op0
, 0),
5329 GEN_INT (INTVAL (XEXP (op0
, 1))
5330 & ~INTVAL (op1
))), op1
);
5332 if (GET_CODE (x
) != AND
)
5339 /* Convert (A | B) & A to A. */
5340 if (GET_CODE (op0
) == IOR
5341 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5342 || rtx_equal_p (XEXP (op0
, 1), op1
))
5343 && ! side_effects_p (XEXP (op0
, 0))
5344 && ! side_effects_p (XEXP (op0
, 1)))
5347 /* In the following group of tests (and those in case IOR below),
5348 we start with some combination of logical operations and apply
5349 the distributive law followed by the inverse distributive law.
5350 Most of the time, this results in no change. However, if some of
5351 the operands are the same or inverses of each other, simplifications
5354 For example, (and (ior A B) (not B)) can occur as the result of
5355 expanding a bit field assignment. When we apply the distributive
5356 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5357 which then simplifies to (and (A (not B))).
5359 If we have (and (ior A B) C), apply the distributive law and then
5360 the inverse distributive law to see if things simplify. */
5362 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5364 x
= apply_distributive_law
5365 (gen_binary (GET_CODE (op0
), mode
,
5366 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5367 gen_binary (AND
, mode
, XEXP (op0
, 1),
5369 if (GET_CODE (x
) != AND
)
5373 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5374 return apply_distributive_law
5375 (gen_binary (GET_CODE (op1
), mode
,
5376 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5377 gen_binary (AND
, mode
, XEXP (op1
, 1),
5380 /* Similarly, taking advantage of the fact that
5381 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5383 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5384 return apply_distributive_law
5385 (gen_binary (XOR
, mode
,
5386 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5387 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5390 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5391 return apply_distributive_law
5392 (gen_binary (XOR
, mode
,
5393 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5394 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5398 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5399 if (GET_CODE (op1
) == CONST_INT
5400 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5401 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5404 /* Convert (A & B) | A to A. */
5405 if (GET_CODE (op0
) == AND
5406 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5407 || rtx_equal_p (XEXP (op0
, 1), op1
))
5408 && ! side_effects_p (XEXP (op0
, 0))
5409 && ! side_effects_p (XEXP (op0
, 1)))
5412 /* If we have (ior (and A B) C), apply the distributive law and then
5413 the inverse distributive law to see if things simplify. */
5415 if (GET_CODE (op0
) == AND
)
5417 x
= apply_distributive_law
5418 (gen_binary (AND
, mode
,
5419 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5420 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5423 if (GET_CODE (x
) != IOR
)
5427 if (GET_CODE (op1
) == AND
)
5429 x
= apply_distributive_law
5430 (gen_binary (AND
, mode
,
5431 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5432 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5435 if (GET_CODE (x
) != IOR
)
5439 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5440 mode size to (rotate A CX). */
5442 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5443 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5444 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5445 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5446 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5447 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5448 == GET_MODE_BITSIZE (mode
)))
5449 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5450 (GET_CODE (op0
) == ASHIFT
5451 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5453 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5454 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5455 does not affect any of the bits in OP1, it can really be done
5456 as a PLUS and we can associate. We do this by seeing if OP1
5457 can be safely shifted left C bits. */
5458 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5459 && GET_CODE (XEXP (op0
, 0)) == PLUS
5460 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5461 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5462 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5464 int count
= INTVAL (XEXP (op0
, 1));
5465 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5467 if (mask
>> count
== INTVAL (op1
)
5468 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5470 SUBST (XEXP (XEXP (op0
, 0), 1),
5471 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5478 /* If we are XORing two things that have no bits in common,
5479 convert them into an IOR. This helps to detect rotation encoded
5480 using those methods and possibly other simplifications. */
5482 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5483 && (nonzero_bits (op0
, mode
)
5484 & nonzero_bits (op1
, mode
)) == 0)
5485 return (gen_binary (IOR
, mode
, op0
, op1
));
5487 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5488 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5491 int num_negated
= 0;
5493 if (GET_CODE (op0
) == NOT
)
5494 num_negated
++, op0
= XEXP (op0
, 0);
5495 if (GET_CODE (op1
) == NOT
)
5496 num_negated
++, op1
= XEXP (op1
, 0);
5498 if (num_negated
== 2)
5500 SUBST (XEXP (x
, 0), op0
);
5501 SUBST (XEXP (x
, 1), op1
);
5503 else if (num_negated
== 1)
5505 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5509 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5510 correspond to a machine insn or result in further simplifications
5511 if B is a constant. */
5513 if (GET_CODE (op0
) == AND
5514 && rtx_equal_p (XEXP (op0
, 1), op1
)
5515 && ! side_effects_p (op1
))
5516 return gen_binary (AND
, mode
,
5517 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5520 else if (GET_CODE (op0
) == AND
5521 && rtx_equal_p (XEXP (op0
, 0), op1
)
5522 && ! side_effects_p (op1
))
5523 return gen_binary (AND
, mode
,
5524 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5527 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5528 comparison if STORE_FLAG_VALUE is 1. */
5529 if (STORE_FLAG_VALUE
== 1
5530 && op1
== const1_rtx
5531 && COMPARISON_P (op0
)
5532 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5536 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5537 is (lt foo (const_int 0)), so we can perform the above
5538 simplification if STORE_FLAG_VALUE is 1. */
5540 if (STORE_FLAG_VALUE
== 1
5541 && op1
== const1_rtx
5542 && GET_CODE (op0
) == LSHIFTRT
5543 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5544 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5545 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5547 /* (xor (comparison foo bar) (const_int sign-bit))
5548 when STORE_FLAG_VALUE is the sign bit. */
5549 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5550 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5551 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5552 && op1
== const_true_rtx
5553 && COMPARISON_P (op0
)
5554 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5567 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5568 operations" because they can be replaced with two more basic operations.
5569 ZERO_EXTEND is also considered "compound" because it can be replaced with
5570 an AND operation, which is simpler, though only one operation.
5572 The function expand_compound_operation is called with an rtx expression
5573 and will convert it to the appropriate shifts and AND operations,
5574 simplifying at each stage.
5576 The function make_compound_operation is called to convert an expression
5577 consisting of shifts and ANDs into the equivalent compound expression.
5578 It is the inverse of this function, loosely speaking. */
5581 expand_compound_operation (rtx x
)
5583 unsigned HOST_WIDE_INT pos
= 0, len
;
5585 unsigned int modewidth
;
5588 switch (GET_CODE (x
))
5593 /* We can't necessarily use a const_int for a multiword mode;
5594 it depends on implicitly extending the value.
5595 Since we don't know the right way to extend it,
5596 we can't tell whether the implicit way is right.
5598 Even for a mode that is no wider than a const_int,
5599 we can't win, because we need to sign extend one of its bits through
5600 the rest of it, and we don't know which bit. */
5601 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5604 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5605 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5606 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5607 reloaded. If not for that, MEM's would very rarely be safe.
5609 Reject MODEs bigger than a word, because we might not be able
5610 to reference a two-register group starting with an arbitrary register
5611 (and currently gen_lowpart might crash for a SUBREG). */
5613 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5616 /* Reject MODEs that aren't scalar integers because turning vector
5617 or complex modes into shifts causes problems. */
5619 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5622 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5623 /* If the inner object has VOIDmode (the only way this can happen
5624 is if it is an ASM_OPERANDS), we can't do anything since we don't
5625 know how much masking to do. */
5634 /* If the operand is a CLOBBER, just return it. */
5635 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5638 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5639 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5640 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5643 /* Reject MODEs that aren't scalar integers because turning vector
5644 or complex modes into shifts causes problems. */
5646 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5649 len
= INTVAL (XEXP (x
, 1));
5650 pos
= INTVAL (XEXP (x
, 2));
5652 /* If this goes outside the object being extracted, replace the object
5653 with a (use (mem ...)) construct that only combine understands
5654 and is used only for this purpose. */
5655 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5656 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5658 if (BITS_BIG_ENDIAN
)
5659 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5666 /* Convert sign extension to zero extension, if we know that the high
5667 bit is not set, as this is easier to optimize. It will be converted
5668 back to cheaper alternative in make_extraction. */
5669 if (GET_CODE (x
) == SIGN_EXTEND
5670 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5671 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5672 & ~(((unsigned HOST_WIDE_INT
)
5673 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5677 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5678 rtx temp2
= expand_compound_operation (temp
);
5680 /* Make sure this is a profitable operation. */
5681 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5683 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5689 /* We can optimize some special cases of ZERO_EXTEND. */
5690 if (GET_CODE (x
) == ZERO_EXTEND
)
5692 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5693 know that the last value didn't have any inappropriate bits
5695 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5696 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5697 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5698 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5699 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5700 return XEXP (XEXP (x
, 0), 0);
5702 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5703 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5704 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5705 && subreg_lowpart_p (XEXP (x
, 0))
5706 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5707 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5708 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5709 return SUBREG_REG (XEXP (x
, 0));
5711 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5712 is a comparison and STORE_FLAG_VALUE permits. This is like
5713 the first case, but it works even when GET_MODE (x) is larger
5714 than HOST_WIDE_INT. */
5715 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5716 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5717 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5719 <= HOST_BITS_PER_WIDE_INT
)
5720 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5721 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5722 return XEXP (XEXP (x
, 0), 0);
5724 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5725 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5726 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5727 && subreg_lowpart_p (XEXP (x
, 0))
5728 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5729 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5730 <= HOST_BITS_PER_WIDE_INT
)
5731 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5732 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5733 return SUBREG_REG (XEXP (x
, 0));
5737 /* If we reach here, we want to return a pair of shifts. The inner
5738 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5739 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5740 logical depending on the value of UNSIGNEDP.
5742 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5743 converted into an AND of a shift.
5745 We must check for the case where the left shift would have a negative
5746 count. This can happen in a case like (x >> 31) & 255 on machines
5747 that can't shift by a constant. On those machines, we would first
5748 combine the shift with the AND to produce a variable-position
5749 extraction. Then the constant of 31 would be substituted in to produce
5750 a such a position. */
5752 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5753 if (modewidth
+ len
>= pos
)
5754 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5756 simplify_shift_const (NULL_RTX
, ASHIFT
,
5759 modewidth
- pos
- len
),
5762 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5763 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5764 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5767 ((HOST_WIDE_INT
) 1 << len
) - 1);
5769 /* Any other cases we can't handle. */
5772 /* If we couldn't do this for some reason, return the original
5774 if (GET_CODE (tem
) == CLOBBER
)
5780 /* X is a SET which contains an assignment of one object into
5781 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5782 or certain SUBREGS). If possible, convert it into a series of
5785 We half-heartedly support variable positions, but do not at all
5786 support variable lengths. */
5789 expand_field_assignment (rtx x
)
5792 rtx pos
; /* Always counts from low bit. */
5795 enum machine_mode compute_mode
;
5797 /* Loop until we find something we can't simplify. */
5800 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5801 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5803 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5804 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5805 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5807 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5808 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5810 inner
= XEXP (SET_DEST (x
), 0);
5811 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5812 pos
= XEXP (SET_DEST (x
), 2);
5814 /* If the position is constant and spans the width of INNER,
5815 surround INNER with a USE to indicate this. */
5816 if (GET_CODE (pos
) == CONST_INT
5817 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5818 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5820 if (BITS_BIG_ENDIAN
)
5822 if (GET_CODE (pos
) == CONST_INT
)
5823 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5825 else if (GET_CODE (pos
) == MINUS
5826 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5827 && (INTVAL (XEXP (pos
, 1))
5828 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5829 /* If position is ADJUST - X, new position is X. */
5830 pos
= XEXP (pos
, 0);
5832 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5833 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5839 /* A SUBREG between two modes that occupy the same numbers of words
5840 can be done by moving the SUBREG to the source. */
5841 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5842 /* We need SUBREGs to compute nonzero_bits properly. */
5843 && nonzero_sign_valid
5844 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5845 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5846 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5847 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5849 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5851 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5858 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5859 inner
= SUBREG_REG (inner
);
5861 compute_mode
= GET_MODE (inner
);
5863 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5864 if (! SCALAR_INT_MODE_P (compute_mode
))
5866 enum machine_mode imode
;
5868 /* Don't do anything for vector or complex integral types. */
5869 if (! FLOAT_MODE_P (compute_mode
))
5872 /* Try to find an integral mode to pun with. */
5873 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5874 if (imode
== BLKmode
)
5877 compute_mode
= imode
;
5878 inner
= gen_lowpart (imode
, inner
);
5881 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5882 if (len
< HOST_BITS_PER_WIDE_INT
)
5883 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5887 /* Now compute the equivalent expression. Make a copy of INNER
5888 for the SET_DEST in case it is a MEM into which we will substitute;
5889 we don't want shared RTL in that case. */
5891 (VOIDmode
, copy_rtx (inner
),
5892 gen_binary (IOR
, compute_mode
,
5893 gen_binary (AND
, compute_mode
,
5894 simplify_gen_unary (NOT
, compute_mode
,
5900 gen_binary (ASHIFT
, compute_mode
,
5901 gen_binary (AND
, compute_mode
,
5903 (compute_mode
, SET_SRC (x
)),
5911 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5912 it is an RTX that represents a variable starting position; otherwise,
5913 POS is the (constant) starting bit position (counted from the LSB).
5915 INNER may be a USE. This will occur when we started with a bitfield
5916 that went outside the boundary of the object in memory, which is
5917 allowed on most machines. To isolate this case, we produce a USE
5918 whose mode is wide enough and surround the MEM with it. The only
5919 code that understands the USE is this routine. If it is not removed,
5920 it will cause the resulting insn not to match.
5922 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5925 IN_DEST is nonzero if this is a reference in the destination of a
5926 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5927 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5930 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5931 ZERO_EXTRACT should be built even for bits starting at bit 0.
5933 MODE is the desired mode of the result (if IN_DEST == 0).
5935 The result is an RTX for the extraction or NULL_RTX if the target
5939 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5940 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5941 int in_dest
, int in_compare
)
5943 /* This mode describes the size of the storage area
5944 to fetch the overall value from. Within that, we
5945 ignore the POS lowest bits, etc. */
5946 enum machine_mode is_mode
= GET_MODE (inner
);
5947 enum machine_mode inner_mode
;
5948 enum machine_mode wanted_inner_mode
= byte_mode
;
5949 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5950 enum machine_mode pos_mode
= word_mode
;
5951 enum machine_mode extraction_mode
= word_mode
;
5952 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5955 rtx orig_pos_rtx
= pos_rtx
;
5956 HOST_WIDE_INT orig_pos
;
5958 /* Get some information about INNER and get the innermost object. */
5959 if (GET_CODE (inner
) == USE
)
5960 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5961 /* We don't need to adjust the position because we set up the USE
5962 to pretend that it was a full-word object. */
5963 spans_byte
= 1, inner
= XEXP (inner
, 0);
5964 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5966 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5967 consider just the QI as the memory to extract from.
5968 The subreg adds or removes high bits; its mode is
5969 irrelevant to the meaning of this extraction,
5970 since POS and LEN count from the lsb. */
5971 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5972 is_mode
= GET_MODE (SUBREG_REG (inner
));
5973 inner
= SUBREG_REG (inner
);
5975 else if (GET_CODE (inner
) == ASHIFT
5976 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5977 && pos_rtx
== 0 && pos
== 0
5978 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5980 /* We're extracting the least significant bits of an rtx
5981 (ashift X (const_int C)), where LEN > C. Extract the
5982 least significant (LEN - C) bits of X, giving an rtx
5983 whose mode is MODE, then shift it left C times. */
5984 new = make_extraction (mode
, XEXP (inner
, 0),
5985 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5986 unsignedp
, in_dest
, in_compare
);
5988 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
5991 inner_mode
= GET_MODE (inner
);
5993 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5994 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5996 /* See if this can be done without an extraction. We never can if the
5997 width of the field is not the same as that of some integer mode. For
5998 registers, we can only avoid the extraction if the position is at the
5999 low-order bit and this is either not in the destination or we have the
6000 appropriate STRICT_LOW_PART operation available.
6002 For MEM, we can avoid an extract if the field starts on an appropriate
6003 boundary and we can change the mode of the memory reference. However,
6004 we cannot directly access the MEM if we have a USE and the underlying
6005 MEM is not TMODE. This combination means that MEM was being used in a
6006 context where bits outside its mode were being referenced; that is only
6007 valid in bit-field insns. */
6009 if (tmode
!= BLKmode
6010 && ! (spans_byte
&& inner_mode
!= tmode
)
6011 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6012 && GET_CODE (inner
) != MEM
6014 || (GET_CODE (inner
) == REG
6015 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6016 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6018 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6019 : BITS_PER_UNIT
)) == 0
6020 /* We can't do this if we are widening INNER_MODE (it
6021 may not be aligned, for one thing). */
6022 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6023 && (inner_mode
== tmode
6024 || (! mode_dependent_address_p (XEXP (inner
, 0))
6025 && ! MEM_VOLATILE_P (inner
))))))
6027 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6028 field. If the original and current mode are the same, we need not
6029 adjust the offset. Otherwise, we do if bytes big endian.
6031 If INNER is not a MEM, get a piece consisting of just the field
6032 of interest (in this case POS % BITS_PER_WORD must be 0). */
6034 if (GET_CODE (inner
) == MEM
)
6036 HOST_WIDE_INT offset
;
6038 /* POS counts from lsb, but make OFFSET count in memory order. */
6039 if (BYTES_BIG_ENDIAN
)
6040 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6042 offset
= pos
/ BITS_PER_UNIT
;
6044 new = adjust_address_nv (inner
, tmode
, offset
);
6046 else if (GET_CODE (inner
) == REG
)
6048 if (tmode
!= inner_mode
)
6050 /* We can't call gen_lowpart in a DEST since we
6051 always want a SUBREG (see below) and it would sometimes
6052 return a new hard register. */
6055 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6057 if (WORDS_BIG_ENDIAN
6058 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6059 final_word
= ((GET_MODE_SIZE (inner_mode
)
6060 - GET_MODE_SIZE (tmode
))
6061 / UNITS_PER_WORD
) - final_word
;
6063 final_word
*= UNITS_PER_WORD
;
6064 if (BYTES_BIG_ENDIAN
&&
6065 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6066 final_word
+= (GET_MODE_SIZE (inner_mode
)
6067 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6069 /* Avoid creating invalid subregs, for example when
6070 simplifying (x>>32)&255. */
6071 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6074 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6077 new = gen_lowpart (tmode
, inner
);
6083 new = force_to_mode (inner
, tmode
,
6084 len
>= HOST_BITS_PER_WIDE_INT
6085 ? ~(unsigned HOST_WIDE_INT
) 0
6086 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6089 /* If this extraction is going into the destination of a SET,
6090 make a STRICT_LOW_PART unless we made a MEM. */
6093 return (GET_CODE (new) == MEM
? new
6094 : (GET_CODE (new) != SUBREG
6095 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6096 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6101 if (GET_CODE (new) == CONST_INT
)
6102 return gen_int_mode (INTVAL (new), mode
);
6104 /* If we know that no extraneous bits are set, and that the high
6105 bit is not set, convert the extraction to the cheaper of
6106 sign and zero extension, that are equivalent in these cases. */
6107 if (flag_expensive_optimizations
6108 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6109 && ((nonzero_bits (new, tmode
)
6110 & ~(((unsigned HOST_WIDE_INT
)
6111 GET_MODE_MASK (tmode
))
6115 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6116 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6118 /* Prefer ZERO_EXTENSION, since it gives more information to
6120 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6125 /* Otherwise, sign- or zero-extend unless we already are in the
6128 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6132 /* Unless this is a COMPARE or we have a funny memory reference,
6133 don't do anything with zero-extending field extracts starting at
6134 the low-order bit since they are simple AND operations. */
6135 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6136 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6139 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6140 we would be spanning bytes or if the position is not a constant and the
6141 length is not 1. In all other cases, we would only be going outside
6142 our object in cases when an original shift would have been
6144 if (! spans_byte
&& GET_CODE (inner
) == MEM
6145 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6146 || (pos_rtx
!= 0 && len
!= 1)))
6149 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6150 and the mode for the result. */
6151 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6153 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6154 pos_mode
= mode_for_extraction (EP_insv
, 2);
6155 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6158 if (! in_dest
&& unsignedp
6159 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6161 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6162 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6163 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6166 if (! in_dest
&& ! unsignedp
6167 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6169 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6170 pos_mode
= mode_for_extraction (EP_extv
, 3);
6171 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6174 /* Never narrow an object, since that might not be safe. */
6176 if (mode
!= VOIDmode
6177 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6178 extraction_mode
= mode
;
6180 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6181 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6182 pos_mode
= GET_MODE (pos_rtx
);
6184 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6185 if we have to change the mode of memory and cannot, the desired mode is
6187 if (GET_CODE (inner
) != MEM
)
6188 wanted_inner_mode
= wanted_inner_reg_mode
;
6189 else if (inner_mode
!= wanted_inner_mode
6190 && (mode_dependent_address_p (XEXP (inner
, 0))
6191 || MEM_VOLATILE_P (inner
)))
6192 wanted_inner_mode
= extraction_mode
;
6196 if (BITS_BIG_ENDIAN
)
6198 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6199 BITS_BIG_ENDIAN style. If position is constant, compute new
6200 position. Otherwise, build subtraction.
6201 Note that POS is relative to the mode of the original argument.
6202 If it's a MEM we need to recompute POS relative to that.
6203 However, if we're extracting from (or inserting into) a register,
6204 we want to recompute POS relative to wanted_inner_mode. */
6205 int width
= (GET_CODE (inner
) == MEM
6206 ? GET_MODE_BITSIZE (is_mode
)
6207 : GET_MODE_BITSIZE (wanted_inner_mode
));
6210 pos
= width
- len
- pos
;
6213 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6214 /* POS may be less than 0 now, but we check for that below.
6215 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6218 /* If INNER has a wider mode, make it smaller. If this is a constant
6219 extract, try to adjust the byte to point to the byte containing
6221 if (wanted_inner_mode
!= VOIDmode
6222 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6223 && ((GET_CODE (inner
) == MEM
6224 && (inner_mode
== wanted_inner_mode
6225 || (! mode_dependent_address_p (XEXP (inner
, 0))
6226 && ! MEM_VOLATILE_P (inner
))))))
6230 /* The computations below will be correct if the machine is big
6231 endian in both bits and bytes or little endian in bits and bytes.
6232 If it is mixed, we must adjust. */
6234 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6235 adjust OFFSET to compensate. */
6236 if (BYTES_BIG_ENDIAN
6238 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6239 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6241 /* If this is a constant position, we can move to the desired byte. */
6244 offset
+= pos
/ BITS_PER_UNIT
;
6245 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6248 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6250 && is_mode
!= wanted_inner_mode
)
6251 offset
= (GET_MODE_SIZE (is_mode
)
6252 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6254 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6255 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6258 /* If INNER is not memory, we can always get it into the proper mode. If we
6259 are changing its mode, POS must be a constant and smaller than the size
6261 else if (GET_CODE (inner
) != MEM
)
6263 if (GET_MODE (inner
) != wanted_inner_mode
6265 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6268 inner
= force_to_mode (inner
, wanted_inner_mode
,
6270 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6271 ? ~(unsigned HOST_WIDE_INT
) 0
6272 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6277 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6278 have to zero extend. Otherwise, we can just use a SUBREG. */
6280 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6282 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6284 /* If we know that no extraneous bits are set, and that the high
6285 bit is not set, convert extraction to cheaper one - either
6286 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6288 if (flag_expensive_optimizations
6289 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6290 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6291 & ~(((unsigned HOST_WIDE_INT
)
6292 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6296 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6298 /* Prefer ZERO_EXTENSION, since it gives more information to
6300 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6305 else if (pos_rtx
!= 0
6306 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6307 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6309 /* Make POS_RTX unless we already have it and it is correct. If we don't
6310 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6312 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6313 pos_rtx
= orig_pos_rtx
;
6315 else if (pos_rtx
== 0)
6316 pos_rtx
= GEN_INT (pos
);
6318 /* Make the required operation. See if we can use existing rtx. */
6319 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6320 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6322 new = gen_lowpart (mode
, new);
6327 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6328 with any other operations in X. Return X without that shift if so. */
6331 extract_left_shift (rtx x
, int count
)
6333 enum rtx_code code
= GET_CODE (x
);
6334 enum machine_mode mode
= GET_MODE (x
);
6340 /* This is the shift itself. If it is wide enough, we will return
6341 either the value being shifted if the shift count is equal to
6342 COUNT or a shift for the difference. */
6343 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6344 && INTVAL (XEXP (x
, 1)) >= count
)
6345 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6346 INTVAL (XEXP (x
, 1)) - count
);
6350 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6351 return simplify_gen_unary (code
, mode
, tem
, mode
);
6355 case PLUS
: case IOR
: case XOR
: case AND
:
6356 /* If we can safely shift this constant and we find the inner shift,
6357 make a new operation. */
6358 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6359 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6360 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6361 return gen_binary (code
, mode
, tem
,
6362 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6373 /* Look at the expression rooted at X. Look for expressions
6374 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6375 Form these expressions.
6377 Return the new rtx, usually just X.
6379 Also, for machines like the VAX that don't have logical shift insns,
6380 try to convert logical to arithmetic shift operations in cases where
6381 they are equivalent. This undoes the canonicalizations to logical
6382 shifts done elsewhere.
6384 We try, as much as possible, to re-use rtl expressions to save memory.
6386 IN_CODE says what kind of expression we are processing. Normally, it is
6387 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6388 being kludges), it is MEM. When processing the arguments of a comparison
6389 or a COMPARE against zero, it is COMPARE. */
6392 make_compound_operation (rtx x
, enum rtx_code in_code
)
6394 enum rtx_code code
= GET_CODE (x
);
6395 enum machine_mode mode
= GET_MODE (x
);
6396 int mode_width
= GET_MODE_BITSIZE (mode
);
6398 enum rtx_code next_code
;
6404 /* Select the code to be used in recursive calls. Once we are inside an
6405 address, we stay there. If we have a comparison, set to COMPARE,
6406 but once inside, go back to our default of SET. */
6408 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6409 : ((code
== COMPARE
|| COMPARISON_P (x
))
6410 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6411 : in_code
== COMPARE
? SET
: in_code
);
6413 /* Process depending on the code of this operation. If NEW is set
6414 nonzero, it will be returned. */
6419 /* Convert shifts by constants into multiplications if inside
6421 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6422 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6423 && INTVAL (XEXP (x
, 1)) >= 0)
6425 new = make_compound_operation (XEXP (x
, 0), next_code
);
6426 new = gen_rtx_MULT (mode
, new,
6427 GEN_INT ((HOST_WIDE_INT
) 1
6428 << INTVAL (XEXP (x
, 1))));
6433 /* If the second operand is not a constant, we can't do anything
6435 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6438 /* If the constant is a power of two minus one and the first operand
6439 is a logical right shift, make an extraction. */
6440 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6441 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6443 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6444 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6445 0, in_code
== COMPARE
);
6448 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6449 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6450 && subreg_lowpart_p (XEXP (x
, 0))
6451 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6452 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6454 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6456 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6457 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6458 0, in_code
== COMPARE
);
6460 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6461 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6462 || GET_CODE (XEXP (x
, 0)) == IOR
)
6463 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6464 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6465 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6467 /* Apply the distributive law, and then try to make extractions. */
6468 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6469 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6471 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6473 new = make_compound_operation (new, in_code
);
6476 /* If we are have (and (rotate X C) M) and C is larger than the number
6477 of bits in M, this is an extraction. */
6479 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6480 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6481 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6482 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6484 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6485 new = make_extraction (mode
, new,
6486 (GET_MODE_BITSIZE (mode
)
6487 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6488 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6491 /* On machines without logical shifts, if the operand of the AND is
6492 a logical shift and our mask turns off all the propagated sign
6493 bits, we can replace the logical shift with an arithmetic shift. */
6494 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6495 && !have_insn_for (LSHIFTRT
, mode
)
6496 && have_insn_for (ASHIFTRT
, mode
)
6497 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6498 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6499 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6500 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6502 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6504 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6505 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6507 gen_rtx_ASHIFTRT (mode
,
6508 make_compound_operation
6509 (XEXP (XEXP (x
, 0), 0), next_code
),
6510 XEXP (XEXP (x
, 0), 1)));
6513 /* If the constant is one less than a power of two, this might be
6514 representable by an extraction even if no shift is present.
6515 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6516 we are in a COMPARE. */
6517 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6518 new = make_extraction (mode
,
6519 make_compound_operation (XEXP (x
, 0),
6521 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6523 /* If we are in a comparison and this is an AND with a power of two,
6524 convert this into the appropriate bit extract. */
6525 else if (in_code
== COMPARE
6526 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6527 new = make_extraction (mode
,
6528 make_compound_operation (XEXP (x
, 0),
6530 i
, NULL_RTX
, 1, 1, 0, 1);
6535 /* If the sign bit is known to be zero, replace this with an
6536 arithmetic shift. */
6537 if (have_insn_for (ASHIFTRT
, mode
)
6538 && ! have_insn_for (LSHIFTRT
, mode
)
6539 && mode_width
<= HOST_BITS_PER_WIDE_INT
6540 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6542 new = gen_rtx_ASHIFTRT (mode
,
6543 make_compound_operation (XEXP (x
, 0),
6549 /* ... fall through ... */
6555 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6556 this is a SIGN_EXTRACT. */
6557 if (GET_CODE (rhs
) == CONST_INT
6558 && GET_CODE (lhs
) == ASHIFT
6559 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6560 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6562 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6563 new = make_extraction (mode
, new,
6564 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6565 NULL_RTX
, mode_width
- INTVAL (rhs
),
6566 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6570 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6571 If so, try to merge the shifts into a SIGN_EXTEND. We could
6572 also do this for some cases of SIGN_EXTRACT, but it doesn't
6573 seem worth the effort; the case checked for occurs on Alpha. */
6576 && ! (GET_CODE (lhs
) == SUBREG
6577 && (OBJECT_P (SUBREG_REG (lhs
))))
6578 && GET_CODE (rhs
) == CONST_INT
6579 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6580 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6581 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6582 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6583 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6588 /* Call ourselves recursively on the inner expression. If we are
6589 narrowing the object and it has a different RTL code from
6590 what it originally did, do this SUBREG as a force_to_mode. */
6592 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6593 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6594 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6595 && subreg_lowpart_p (x
))
6597 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6600 /* If we have something other than a SUBREG, we might have
6601 done an expansion, so rerun ourselves. */
6602 if (GET_CODE (newer
) != SUBREG
)
6603 newer
= make_compound_operation (newer
, in_code
);
6608 /* If this is a paradoxical subreg, and the new code is a sign or
6609 zero extension, omit the subreg and widen the extension. If it
6610 is a regular subreg, we can still get rid of the subreg by not
6611 widening so much, or in fact removing the extension entirely. */
6612 if ((GET_CODE (tem
) == SIGN_EXTEND
6613 || GET_CODE (tem
) == ZERO_EXTEND
)
6614 && subreg_lowpart_p (x
))
6616 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6617 || (GET_MODE_SIZE (mode
) >
6618 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6620 if (! SCALAR_INT_MODE_P (mode
))
6622 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6625 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6636 x
= gen_lowpart (mode
, new);
6637 code
= GET_CODE (x
);
6640 /* Now recursively process each operand of this operation. */
6641 fmt
= GET_RTX_FORMAT (code
);
6642 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6645 new = make_compound_operation (XEXP (x
, i
), next_code
);
6646 SUBST (XEXP (x
, i
), new);
6652 /* Given M see if it is a value that would select a field of bits
6653 within an item, but not the entire word. Return -1 if not.
6654 Otherwise, return the starting position of the field, where 0 is the
6657 *PLEN is set to the length of the field. */
6660 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6662 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6663 int pos
= exact_log2 (m
& -m
);
6669 /* Now shift off the low-order zero bits and see if we have a power of
6671 len
= exact_log2 ((m
>> pos
) + 1);
6680 /* See if X can be simplified knowing that we will only refer to it in
6681 MODE and will only refer to those bits that are nonzero in MASK.
6682 If other bits are being computed or if masking operations are done
6683 that select a superset of the bits in MASK, they can sometimes be
6686 Return a possibly simplified expression, but always convert X to
6687 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6689 Also, if REG is nonzero and X is a register equal in value to REG,
6692 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6693 are all off in X. This is used when X will be complemented, by either
6694 NOT, NEG, or XOR. */
6697 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6698 rtx reg
, int just_select
)
6700 enum rtx_code code
= GET_CODE (x
);
6701 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6702 enum machine_mode op_mode
;
6703 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6706 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6707 code below will do the wrong thing since the mode of such an
6708 expression is VOIDmode.
6710 Also do nothing if X is a CLOBBER; this can happen if X was
6711 the return value from a call to gen_lowpart. */
6712 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6715 /* We want to perform the operation is its present mode unless we know
6716 that the operation is valid in MODE, in which case we do the operation
6718 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6719 && have_insn_for (code
, mode
))
6720 ? mode
: GET_MODE (x
));
6722 /* It is not valid to do a right-shift in a narrower mode
6723 than the one it came in with. */
6724 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6725 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6726 op_mode
= GET_MODE (x
);
6728 /* Truncate MASK to fit OP_MODE. */
6730 mask
&= GET_MODE_MASK (op_mode
);
6732 /* When we have an arithmetic operation, or a shift whose count we
6733 do not know, we need to assume that all bits up to the highest-order
6734 bit in MASK will be needed. This is how we form such a mask. */
6735 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6736 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6738 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6741 /* Determine what bits of X are guaranteed to be (non)zero. */
6742 nonzero
= nonzero_bits (x
, mode
);
6744 /* If none of the bits in X are needed, return a zero. */
6745 if (! just_select
&& (nonzero
& mask
) == 0)
6748 /* If X is a CONST_INT, return a new one. Do this here since the
6749 test below will fail. */
6750 if (GET_CODE (x
) == CONST_INT
)
6752 if (SCALAR_INT_MODE_P (mode
))
6753 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6756 x
= GEN_INT (INTVAL (x
) & mask
);
6757 return gen_lowpart_common (mode
, x
);
6761 /* If X is narrower than MODE and we want all the bits in X's mode, just
6762 get X in the proper mode. */
6763 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6764 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6765 return gen_lowpart (mode
, x
);
6767 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6768 MASK are already known to be zero in X, we need not do anything. */
6769 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6775 /* If X is a (clobber (const_int)), return it since we know we are
6776 generating something that won't match. */
6780 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6781 spanned the boundary of the MEM. If we are now masking so it is
6782 within that boundary, we don't need the USE any more. */
6783 if (! BITS_BIG_ENDIAN
6784 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6785 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6792 x
= expand_compound_operation (x
);
6793 if (GET_CODE (x
) != code
)
6794 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6798 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6799 || rtx_equal_p (reg
, get_last_value (x
))))
6804 if (subreg_lowpart_p (x
)
6805 /* We can ignore the effect of this SUBREG if it narrows the mode or
6806 if the constant masks to zero all the bits the mode doesn't
6808 && ((GET_MODE_SIZE (GET_MODE (x
))
6809 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6811 & GET_MODE_MASK (GET_MODE (x
))
6812 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6813 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6817 /* If this is an AND with a constant, convert it into an AND
6818 whose constant is the AND of that constant with MASK. If it
6819 remains an AND of MASK, delete it since it is redundant. */
6821 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6823 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6824 mask
& INTVAL (XEXP (x
, 1)));
6826 /* If X is still an AND, see if it is an AND with a mask that
6827 is just some low-order bits. If so, and it is MASK, we don't
6830 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6831 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6835 /* If it remains an AND, try making another AND with the bits
6836 in the mode mask that aren't in MASK turned on. If the
6837 constant in the AND is wide enough, this might make a
6838 cheaper constant. */
6840 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6841 && GET_MODE_MASK (GET_MODE (x
)) != mask
6842 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6844 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6845 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6846 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6849 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6850 number, sign extend it. */
6851 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6852 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6853 cval
|= (HOST_WIDE_INT
) -1 << width
;
6855 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6856 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6866 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6867 low-order bits (as in an alignment operation) and FOO is already
6868 aligned to that boundary, mask C1 to that boundary as well.
6869 This may eliminate that PLUS and, later, the AND. */
6872 unsigned int width
= GET_MODE_BITSIZE (mode
);
6873 unsigned HOST_WIDE_INT smask
= mask
;
6875 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6876 number, sign extend it. */
6878 if (width
< HOST_BITS_PER_WIDE_INT
6879 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6880 smask
|= (HOST_WIDE_INT
) -1 << width
;
6882 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6883 && exact_log2 (- smask
) >= 0
6884 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6885 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6886 return force_to_mode (plus_constant (XEXP (x
, 0),
6887 (INTVAL (XEXP (x
, 1)) & smask
)),
6888 mode
, smask
, reg
, next_select
);
6891 /* ... fall through ... */
6894 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6895 most significant bit in MASK since carries from those bits will
6896 affect the bits we are interested in. */
6901 /* If X is (minus C Y) where C's least set bit is larger than any bit
6902 in the mask, then we may replace with (neg Y). */
6903 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6904 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6905 & -INTVAL (XEXP (x
, 0))))
6908 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6910 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6913 /* Similarly, if C contains every bit in the fuller_mask, then we may
6914 replace with (not Y). */
6915 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6916 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6917 == INTVAL (XEXP (x
, 0))))
6919 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6920 XEXP (x
, 1), GET_MODE (x
));
6921 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6929 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6930 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6931 operation which may be a bitfield extraction. Ensure that the
6932 constant we form is not wider than the mode of X. */
6934 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6935 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6936 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6937 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6938 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6939 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6940 + floor_log2 (INTVAL (XEXP (x
, 1))))
6941 < GET_MODE_BITSIZE (GET_MODE (x
)))
6942 && (INTVAL (XEXP (x
, 1))
6943 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6945 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6946 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6947 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6948 XEXP (XEXP (x
, 0), 0), temp
);
6949 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6950 XEXP (XEXP (x
, 0), 1));
6951 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6955 /* For most binary operations, just propagate into the operation and
6956 change the mode if we have an operation of that mode. */
6958 op0
= gen_lowpart (op_mode
,
6959 force_to_mode (XEXP (x
, 0), mode
, mask
,
6961 op1
= gen_lowpart (op_mode
,
6962 force_to_mode (XEXP (x
, 1), mode
, mask
,
6965 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6966 x
= gen_binary (code
, op_mode
, op0
, op1
);
6970 /* For left shifts, do the same, but just for the first operand.
6971 However, we cannot do anything with shifts where we cannot
6972 guarantee that the counts are smaller than the size of the mode
6973 because such a count will have a different meaning in a
6976 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6977 && INTVAL (XEXP (x
, 1)) >= 0
6978 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6979 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6980 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6981 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6984 /* If the shift count is a constant and we can do arithmetic in
6985 the mode of the shift, refine which bits we need. Otherwise, use the
6986 conservative form of the mask. */
6987 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6988 && INTVAL (XEXP (x
, 1)) >= 0
6989 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6990 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6991 mask
>>= INTVAL (XEXP (x
, 1));
6995 op0
= gen_lowpart (op_mode
,
6996 force_to_mode (XEXP (x
, 0), op_mode
,
6997 mask
, reg
, next_select
));
6999 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7000 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7004 /* Here we can only do something if the shift count is a constant,
7005 this shift constant is valid for the host, and we can do arithmetic
7008 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7009 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7010 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7012 rtx inner
= XEXP (x
, 0);
7013 unsigned HOST_WIDE_INT inner_mask
;
7015 /* Select the mask of the bits we need for the shift operand. */
7016 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7018 /* We can only change the mode of the shift if we can do arithmetic
7019 in the mode of the shift and INNER_MASK is no wider than the
7020 width of OP_MODE. */
7021 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7022 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7023 op_mode
= GET_MODE (x
);
7025 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7027 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7028 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7031 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7032 shift and AND produces only copies of the sign bit (C2 is one less
7033 than a power of two), we can do this with just a shift. */
7035 if (GET_CODE (x
) == LSHIFTRT
7036 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7037 /* The shift puts one of the sign bit copies in the least significant
7039 && ((INTVAL (XEXP (x
, 1))
7040 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7041 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7042 && exact_log2 (mask
+ 1) >= 0
7043 /* Number of bits left after the shift must be more than the mask
7045 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7046 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7047 /* Must be more sign bit copies than the mask needs. */
7048 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7049 >= exact_log2 (mask
+ 1)))
7050 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7051 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7052 - exact_log2 (mask
+ 1)));
7057 /* If we are just looking for the sign bit, we don't need this shift at
7058 all, even if it has a variable count. */
7059 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7060 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7061 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7062 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7064 /* If this is a shift by a constant, get a mask that contains those bits
7065 that are not copies of the sign bit. We then have two cases: If
7066 MASK only includes those bits, this can be a logical shift, which may
7067 allow simplifications. If MASK is a single-bit field not within
7068 those bits, we are requesting a copy of the sign bit and hence can
7069 shift the sign bit to the appropriate location. */
7071 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7072 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7076 /* If the considered data is wider than HOST_WIDE_INT, we can't
7077 represent a mask for all its bits in a single scalar.
7078 But we only care about the lower bits, so calculate these. */
7080 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7082 nonzero
= ~(HOST_WIDE_INT
) 0;
7084 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7085 is the number of bits a full-width mask would have set.
7086 We need only shift if these are fewer than nonzero can
7087 hold. If not, we must keep all bits set in nonzero. */
7089 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7090 < HOST_BITS_PER_WIDE_INT
)
7091 nonzero
>>= INTVAL (XEXP (x
, 1))
7092 + HOST_BITS_PER_WIDE_INT
7093 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7097 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7098 nonzero
>>= INTVAL (XEXP (x
, 1));
7101 if ((mask
& ~nonzero
) == 0
7102 || (i
= exact_log2 (mask
)) >= 0)
7104 x
= simplify_shift_const
7105 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7106 i
< 0 ? INTVAL (XEXP (x
, 1))
7107 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7109 if (GET_CODE (x
) != ASHIFTRT
)
7110 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7114 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7115 even if the shift count isn't a constant. */
7117 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7121 /* If this is a zero- or sign-extension operation that just affects bits
7122 we don't care about, remove it. Be sure the call above returned
7123 something that is still a shift. */
7125 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7126 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7127 && INTVAL (XEXP (x
, 1)) >= 0
7128 && (INTVAL (XEXP (x
, 1))
7129 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7130 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7131 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7132 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7139 /* If the shift count is constant and we can do computations
7140 in the mode of X, compute where the bits we care about are.
7141 Otherwise, we can't do anything. Don't change the mode of
7142 the shift or propagate MODE into the shift, though. */
7143 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7144 && INTVAL (XEXP (x
, 1)) >= 0)
7146 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7147 GET_MODE (x
), GEN_INT (mask
),
7149 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7151 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7152 INTVAL (temp
), reg
, next_select
));
7157 /* If we just want the low-order bit, the NEG isn't needed since it
7158 won't change the low-order bit. */
7160 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7162 /* We need any bits less significant than the most significant bit in
7163 MASK since carries from those bits will affect the bits we are
7169 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7170 same as the XOR case above. Ensure that the constant we form is not
7171 wider than the mode of X. */
7173 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7174 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7175 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7176 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7177 < GET_MODE_BITSIZE (GET_MODE (x
)))
7178 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7180 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7182 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7183 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7185 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7188 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7189 use the full mask inside the NOT. */
7193 op0
= gen_lowpart (op_mode
,
7194 force_to_mode (XEXP (x
, 0), mode
, mask
,
7196 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7197 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7201 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7202 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7203 which is equal to STORE_FLAG_VALUE. */
7204 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7205 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7206 && (nonzero_bits (XEXP (x
, 0), mode
)
7207 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7208 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7213 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7214 written in a narrower mode. We play it safe and do not do so. */
7217 gen_lowpart (GET_MODE (x
),
7218 force_to_mode (XEXP (x
, 1), mode
,
7219 mask
, reg
, next_select
)));
7221 gen_lowpart (GET_MODE (x
),
7222 force_to_mode (XEXP (x
, 2), mode
,
7223 mask
, reg
, next_select
)));
7230 /* Ensure we return a value of the proper mode. */
7231 return gen_lowpart (mode
, x
);
7234 /* Return nonzero if X is an expression that has one of two values depending on
7235 whether some other value is zero or nonzero. In that case, we return the
7236 value that is being tested, *PTRUE is set to the value if the rtx being
7237 returned has a nonzero value, and *PFALSE is set to the other alternative.
7239 If we return zero, we set *PTRUE and *PFALSE to X. */
7242 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7244 enum machine_mode mode
= GET_MODE (x
);
7245 enum rtx_code code
= GET_CODE (x
);
7246 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7247 unsigned HOST_WIDE_INT nz
;
7249 /* If we are comparing a value against zero, we are done. */
7250 if ((code
== NE
|| code
== EQ
)
7251 && XEXP (x
, 1) == const0_rtx
)
7253 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7254 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7258 /* If this is a unary operation whose operand has one of two values, apply
7259 our opcode to compute those values. */
7260 else if (UNARY_P (x
)
7261 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7263 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7264 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7265 GET_MODE (XEXP (x
, 0)));
7269 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7270 make can't possibly match and would suppress other optimizations. */
7271 else if (code
== COMPARE
)
7274 /* If this is a binary operation, see if either side has only one of two
7275 values. If either one does or if both do and they are conditional on
7276 the same value, compute the new true and false values. */
7277 else if (BINARY_P (x
))
7279 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7280 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7282 if ((cond0
!= 0 || cond1
!= 0)
7283 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7285 /* If if_then_else_cond returned zero, then true/false are the
7286 same rtl. We must copy one of them to prevent invalid rtl
7289 true0
= copy_rtx (true0
);
7290 else if (cond1
== 0)
7291 true1
= copy_rtx (true1
);
7293 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7294 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7295 return cond0
? cond0
: cond1
;
7298 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7299 operands is zero when the other is nonzero, and vice-versa,
7300 and STORE_FLAG_VALUE is 1 or -1. */
7302 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7303 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7305 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7307 rtx op0
= XEXP (XEXP (x
, 0), 1);
7308 rtx op1
= XEXP (XEXP (x
, 1), 1);
7310 cond0
= XEXP (XEXP (x
, 0), 0);
7311 cond1
= XEXP (XEXP (x
, 1), 0);
7313 if (COMPARISON_P (cond0
)
7314 && COMPARISON_P (cond1
)
7315 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7316 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7317 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7318 || ((swap_condition (GET_CODE (cond0
))
7319 == combine_reversed_comparison_code (cond1
))
7320 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7321 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7322 && ! side_effects_p (x
))
7324 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7325 *pfalse
= gen_binary (MULT
, mode
,
7327 ? simplify_gen_unary (NEG
, mode
, op1
,
7335 /* Similarly for MULT, AND and UMIN, except that for these the result
7337 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7338 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7339 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7341 cond0
= XEXP (XEXP (x
, 0), 0);
7342 cond1
= XEXP (XEXP (x
, 1), 0);
7344 if (COMPARISON_P (cond0
)
7345 && COMPARISON_P (cond1
)
7346 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7347 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7348 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7349 || ((swap_condition (GET_CODE (cond0
))
7350 == combine_reversed_comparison_code (cond1
))
7351 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7352 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7353 && ! side_effects_p (x
))
7355 *ptrue
= *pfalse
= const0_rtx
;
7361 else if (code
== IF_THEN_ELSE
)
7363 /* If we have IF_THEN_ELSE already, extract the condition and
7364 canonicalize it if it is NE or EQ. */
7365 cond0
= XEXP (x
, 0);
7366 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7367 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7368 return XEXP (cond0
, 0);
7369 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7371 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7372 return XEXP (cond0
, 0);
7378 /* If X is a SUBREG, we can narrow both the true and false values
7379 if the inner expression, if there is a condition. */
7380 else if (code
== SUBREG
7381 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7384 true0
= simplify_gen_subreg (mode
, true0
,
7385 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7386 false0
= simplify_gen_subreg (mode
, false0
,
7387 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7388 if (true0
&& false0
)
7396 /* If X is a constant, this isn't special and will cause confusions
7397 if we treat it as such. Likewise if it is equivalent to a constant. */
7398 else if (CONSTANT_P (x
)
7399 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7402 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7403 will be least confusing to the rest of the compiler. */
7404 else if (mode
== BImode
)
7406 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7410 /* If X is known to be either 0 or -1, those are the true and
7411 false values when testing X. */
7412 else if (x
== constm1_rtx
|| x
== const0_rtx
7413 || (mode
!= VOIDmode
7414 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7416 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7420 /* Likewise for 0 or a single bit. */
7421 else if (SCALAR_INT_MODE_P (mode
)
7422 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7423 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7425 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7429 /* Otherwise fail; show no condition with true and false values the same. */
7430 *ptrue
= *pfalse
= x
;
7434 /* Return the value of expression X given the fact that condition COND
7435 is known to be true when applied to REG as its first operand and VAL
7436 as its second. X is known to not be shared and so can be modified in
7439 We only handle the simplest cases, and specifically those cases that
7440 arise with IF_THEN_ELSE expressions. */
7443 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7445 enum rtx_code code
= GET_CODE (x
);
7450 if (side_effects_p (x
))
7453 /* If either operand of the condition is a floating point value,
7454 then we have to avoid collapsing an EQ comparison. */
7456 && rtx_equal_p (x
, reg
)
7457 && ! FLOAT_MODE_P (GET_MODE (x
))
7458 && ! FLOAT_MODE_P (GET_MODE (val
)))
7461 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7464 /* If X is (abs REG) and we know something about REG's relationship
7465 with zero, we may be able to simplify this. */
7467 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7470 case GE
: case GT
: case EQ
:
7473 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7475 GET_MODE (XEXP (x
, 0)));
7480 /* The only other cases we handle are MIN, MAX, and comparisons if the
7481 operands are the same as REG and VAL. */
7483 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7485 if (rtx_equal_p (XEXP (x
, 0), val
))
7486 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7488 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7490 if (COMPARISON_P (x
))
7492 if (comparison_dominates_p (cond
, code
))
7493 return const_true_rtx
;
7495 code
= combine_reversed_comparison_code (x
);
7497 && comparison_dominates_p (cond
, code
))
7502 else if (code
== SMAX
|| code
== SMIN
7503 || code
== UMIN
|| code
== UMAX
)
7505 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7507 /* Do not reverse the condition when it is NE or EQ.
7508 This is because we cannot conclude anything about
7509 the value of 'SMAX (x, y)' when x is not equal to y,
7510 but we can when x equals y. */
7511 if ((code
== SMAX
|| code
== UMAX
)
7512 && ! (cond
== EQ
|| cond
== NE
))
7513 cond
= reverse_condition (cond
);
7518 return unsignedp
? x
: XEXP (x
, 1);
7520 return unsignedp
? x
: XEXP (x
, 0);
7522 return unsignedp
? XEXP (x
, 1) : x
;
7524 return unsignedp
? XEXP (x
, 0) : x
;
7531 else if (code
== SUBREG
)
7533 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7534 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7536 if (SUBREG_REG (x
) != r
)
7538 /* We must simplify subreg here, before we lose track of the
7539 original inner_mode. */
7540 new = simplify_subreg (GET_MODE (x
), r
,
7541 inner_mode
, SUBREG_BYTE (x
));
7545 SUBST (SUBREG_REG (x
), r
);
7550 /* We don't have to handle SIGN_EXTEND here, because even in the
7551 case of replacing something with a modeless CONST_INT, a
7552 CONST_INT is already (supposed to be) a valid sign extension for
7553 its narrower mode, which implies it's already properly
7554 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7555 story is different. */
7556 else if (code
== ZERO_EXTEND
)
7558 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7559 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7561 if (XEXP (x
, 0) != r
)
7563 /* We must simplify the zero_extend here, before we lose
7564 track of the original inner_mode. */
7565 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7570 SUBST (XEXP (x
, 0), r
);
7576 fmt
= GET_RTX_FORMAT (code
);
7577 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7580 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7581 else if (fmt
[i
] == 'E')
7582 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7583 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7590 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7591 assignment as a field assignment. */
7594 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7596 if (x
== y
|| rtx_equal_p (x
, y
))
7599 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7602 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7603 Note that all SUBREGs of MEM are paradoxical; otherwise they
7604 would have been rewritten. */
7605 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7606 && GET_CODE (SUBREG_REG (y
)) == MEM
7607 && rtx_equal_p (SUBREG_REG (y
),
7608 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7611 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7612 && GET_CODE (SUBREG_REG (x
)) == MEM
7613 && rtx_equal_p (SUBREG_REG (x
),
7614 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7617 /* We used to see if get_last_value of X and Y were the same but that's
7618 not correct. In one direction, we'll cause the assignment to have
7619 the wrong destination and in the case, we'll import a register into this
7620 insn that might have already have been dead. So fail if none of the
7621 above cases are true. */
7625 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7626 Return that assignment if so.
7628 We only handle the most common cases. */
7631 make_field_assignment (rtx x
)
7633 rtx dest
= SET_DEST (x
);
7634 rtx src
= SET_SRC (x
);
7639 unsigned HOST_WIDE_INT len
;
7641 enum machine_mode mode
;
7643 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7644 a clear of a one-bit field. We will have changed it to
7645 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7648 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7649 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7650 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7651 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7653 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7656 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7660 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7661 && subreg_lowpart_p (XEXP (src
, 0))
7662 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7663 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7664 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7665 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7666 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7667 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7669 assign
= make_extraction (VOIDmode
, dest
, 0,
7670 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7673 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7677 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7679 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7680 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7681 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7683 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7686 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7690 /* The other case we handle is assignments into a constant-position
7691 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7692 a mask that has all one bits except for a group of zero bits and
7693 OTHER is known to have zeros where C1 has ones, this is such an
7694 assignment. Compute the position and length from C1. Shift OTHER
7695 to the appropriate position, force it to the required mode, and
7696 make the extraction. Check for the AND in both operands. */
7698 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7701 rhs
= expand_compound_operation (XEXP (src
, 0));
7702 lhs
= expand_compound_operation (XEXP (src
, 1));
7704 if (GET_CODE (rhs
) == AND
7705 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7706 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7707 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7708 else if (GET_CODE (lhs
) == AND
7709 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7710 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7711 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7715 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7716 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7717 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7718 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7721 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7725 /* The mode to use for the source is the mode of the assignment, or of
7726 what is inside a possible STRICT_LOW_PART. */
7727 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7728 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7730 /* Shift OTHER right POS places and make it the source, restricting it
7731 to the proper length and mode. */
7733 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7734 GET_MODE (src
), other
, pos
),
7736 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7737 ? ~(unsigned HOST_WIDE_INT
) 0
7738 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7741 /* If SRC is masked by an AND that does not make a difference in
7742 the value being stored, strip it. */
7743 if (GET_CODE (assign
) == ZERO_EXTRACT
7744 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7745 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7746 && GET_CODE (src
) == AND
7747 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7748 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7749 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7750 src
= XEXP (src
, 0);
7752 return gen_rtx_SET (VOIDmode
, assign
, src
);
7755 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7759 apply_distributive_law (rtx x
)
7761 enum rtx_code code
= GET_CODE (x
);
7762 enum rtx_code inner_code
;
7763 rtx lhs
, rhs
, other
;
7766 /* Distributivity is not true for floating point as it can change the
7767 value. So we don't do it unless -funsafe-math-optimizations. */
7768 if (FLOAT_MODE_P (GET_MODE (x
))
7769 && ! flag_unsafe_math_optimizations
)
7772 /* The outer operation can only be one of the following: */
7773 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7774 && code
!= PLUS
&& code
!= MINUS
)
7780 /* If either operand is a primitive we can't do anything, so get out
7782 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7785 lhs
= expand_compound_operation (lhs
);
7786 rhs
= expand_compound_operation (rhs
);
7787 inner_code
= GET_CODE (lhs
);
7788 if (inner_code
!= GET_CODE (rhs
))
7791 /* See if the inner and outer operations distribute. */
7798 /* These all distribute except over PLUS. */
7799 if (code
== PLUS
|| code
== MINUS
)
7804 if (code
!= PLUS
&& code
!= MINUS
)
7809 /* This is also a multiply, so it distributes over everything. */
7813 /* Non-paradoxical SUBREGs distributes over all operations, provided
7814 the inner modes and byte offsets are the same, this is an extraction
7815 of a low-order part, we don't convert an fp operation to int or
7816 vice versa, and we would not be converting a single-word
7817 operation into a multi-word operation. The latter test is not
7818 required, but it prevents generating unneeded multi-word operations.
7819 Some of the previous tests are redundant given the latter test, but
7820 are retained because they are required for correctness.
7822 We produce the result slightly differently in this case. */
7824 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7825 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7826 || ! subreg_lowpart_p (lhs
)
7827 || (GET_MODE_CLASS (GET_MODE (lhs
))
7828 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7829 || (GET_MODE_SIZE (GET_MODE (lhs
))
7830 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7831 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7834 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7835 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7836 return gen_lowpart (GET_MODE (x
), tem
);
7842 /* Set LHS and RHS to the inner operands (A and B in the example
7843 above) and set OTHER to the common operand (C in the example).
7844 There is only one way to do this unless the inner operation is
7846 if (COMMUTATIVE_ARITH_P (lhs
)
7847 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7848 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7849 else if (COMMUTATIVE_ARITH_P (lhs
)
7850 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7851 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7852 else if (COMMUTATIVE_ARITH_P (lhs
)
7853 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7854 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7855 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7856 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7860 /* Form the new inner operation, seeing if it simplifies first. */
7861 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7863 /* There is one exception to the general way of distributing:
7864 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7865 if (code
== XOR
&& inner_code
== IOR
)
7868 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7871 /* We may be able to continuing distributing the result, so call
7872 ourselves recursively on the inner operation before forming the
7873 outer operation, which we return. */
7874 return gen_binary (inner_code
, GET_MODE (x
),
7875 apply_distributive_law (tem
), other
);
7878 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7881 Return an equivalent form, if different from X. Otherwise, return X. If
7882 X is zero, we are to always construct the equivalent form. */
7885 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7886 unsigned HOST_WIDE_INT constop
)
7888 unsigned HOST_WIDE_INT nonzero
;
7891 /* Simplify VAROP knowing that we will be only looking at some of the
7894 Note by passing in CONSTOP, we guarantee that the bits not set in
7895 CONSTOP are not significant and will never be examined. We must
7896 ensure that is the case by explicitly masking out those bits
7897 before returning. */
7898 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7900 /* If VAROP is a CLOBBER, we will fail so return it. */
7901 if (GET_CODE (varop
) == CLOBBER
)
7904 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7905 to VAROP and return the new constant. */
7906 if (GET_CODE (varop
) == CONST_INT
)
7907 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7909 /* See what bits may be nonzero in VAROP. Unlike the general case of
7910 a call to nonzero_bits, here we don't care about bits outside
7913 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7915 /* Turn off all bits in the constant that are known to already be zero.
7916 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7917 which is tested below. */
7921 /* If we don't have any bits left, return zero. */
7925 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7926 a power of two, we can replace this with an ASHIFT. */
7927 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7928 && (i
= exact_log2 (constop
)) >= 0)
7929 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7931 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7932 or XOR, then try to apply the distributive law. This may eliminate
7933 operations if either branch can be simplified because of the AND.
7934 It may also make some cases more complex, but those cases probably
7935 won't match a pattern either with or without this. */
7937 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7941 apply_distributive_law
7942 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7943 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7944 XEXP (varop
, 0), constop
),
7945 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7946 XEXP (varop
, 1), constop
))));
7948 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7949 the AND and see if one of the operands simplifies to zero. If so, we
7950 may eliminate it. */
7952 if (GET_CODE (varop
) == PLUS
7953 && exact_log2 (constop
+ 1) >= 0)
7957 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7958 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7959 if (o0
== const0_rtx
)
7961 if (o1
== const0_rtx
)
7965 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7966 if we already had one (just check for the simplest cases). */
7967 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7968 && GET_MODE (XEXP (x
, 0)) == mode
7969 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7970 varop
= XEXP (x
, 0);
7972 varop
= gen_lowpart (mode
, varop
);
7974 /* If we can't make the SUBREG, try to return what we were given. */
7975 if (GET_CODE (varop
) == CLOBBER
)
7976 return x
? x
: varop
;
7978 /* If we are only masking insignificant bits, return VAROP. */
7979 if (constop
== nonzero
)
7983 /* Otherwise, return an AND. */
7984 constop
= trunc_int_for_mode (constop
, mode
);
7985 /* See how much, if any, of X we can use. */
7986 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7987 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7991 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7992 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7993 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7995 SUBST (XEXP (x
, 0), varop
);
8002 #define nonzero_bits_with_known(X, MODE) \
8003 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8005 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8006 It avoids exponential behavior in nonzero_bits1 when X has
8007 identical subexpressions on the first or the second level. */
8009 static unsigned HOST_WIDE_INT
8010 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8011 enum machine_mode known_mode
,
8012 unsigned HOST_WIDE_INT known_ret
)
8014 if (x
== known_x
&& mode
== known_mode
)
8017 /* Try to find identical subexpressions. If found call
8018 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8019 precomputed value for the subexpression as KNOWN_RET. */
8021 if (ARITHMETIC_P (x
))
8023 rtx x0
= XEXP (x
, 0);
8024 rtx x1
= XEXP (x
, 1);
8026 /* Check the first level. */
8028 return nonzero_bits1 (x
, mode
, x0
, mode
,
8029 nonzero_bits_with_known (x0
, mode
));
8031 /* Check the second level. */
8032 if (ARITHMETIC_P (x0
)
8033 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8034 return nonzero_bits1 (x
, mode
, x1
, mode
,
8035 nonzero_bits_with_known (x1
, mode
));
8037 if (ARITHMETIC_P (x1
)
8038 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8039 return nonzero_bits1 (x
, mode
, x0
, mode
,
8040 nonzero_bits_with_known (x0
, mode
));
8043 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8046 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8047 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8048 is less useful. We can't allow both, because that results in exponential
8049 run time recursion. There is a nullstone testcase that triggered
8050 this. This macro avoids accidental uses of num_sign_bit_copies. */
8051 #define cached_num_sign_bit_copies()
8053 /* Given an expression, X, compute which bits in X can be nonzero.
8054 We don't care about bits outside of those defined in MODE.
8056 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8057 a shift, AND, or zero_extract, we can do better. */
8059 static unsigned HOST_WIDE_INT
8060 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8061 enum machine_mode known_mode
,
8062 unsigned HOST_WIDE_INT known_ret
)
8064 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8065 unsigned HOST_WIDE_INT inner_nz
;
8067 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8070 /* For floating-point values, assume all bits are needed. */
8071 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8074 /* If X is wider than MODE, use its mode instead. */
8075 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8077 mode
= GET_MODE (x
);
8078 nonzero
= GET_MODE_MASK (mode
);
8079 mode_width
= GET_MODE_BITSIZE (mode
);
8082 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8083 /* Our only callers in this case look for single bit values. So
8084 just return the mode mask. Those tests will then be false. */
8087 #ifndef WORD_REGISTER_OPERATIONS
8088 /* If MODE is wider than X, but both are a single word for both the host
8089 and target machines, we can compute this from which bits of the
8090 object might be nonzero in its own mode, taking into account the fact
8091 that on many CISC machines, accessing an object in a wider mode
8092 causes the high-order bits to become undefined. So they are
8093 not known to be zero. */
8095 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8096 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8097 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8098 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8100 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8101 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8106 code
= GET_CODE (x
);
8110 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8111 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8112 all the bits above ptr_mode are known to be zero. */
8113 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8115 nonzero
&= GET_MODE_MASK (ptr_mode
);
8118 /* Include declared information about alignment of pointers. */
8119 /* ??? We don't properly preserve REG_POINTER changes across
8120 pointer-to-integer casts, so we can't trust it except for
8121 things that we know must be pointers. See execute/960116-1.c. */
8122 if ((x
== stack_pointer_rtx
8123 || x
== frame_pointer_rtx
8124 || x
== arg_pointer_rtx
)
8125 && REGNO_POINTER_ALIGN (REGNO (x
)))
8127 unsigned HOST_WIDE_INT alignment
8128 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8130 #ifdef PUSH_ROUNDING
8131 /* If PUSH_ROUNDING is defined, it is possible for the
8132 stack to be momentarily aligned only to that amount,
8133 so we pick the least alignment. */
8134 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8135 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8139 nonzero
&= ~(alignment
- 1);
8142 /* If X is a register whose nonzero bits value is current, use it.
8143 Otherwise, if X is a register whose value we can find, use that
8144 value. Otherwise, use the previously-computed global nonzero bits
8145 for this register. */
8147 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8148 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8149 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8150 && GET_MODE_CLASS (mode
) == MODE_INT
))
8151 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8152 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8153 && REG_N_SETS (REGNO (x
)) == 1
8154 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8156 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8157 return reg_stat
[REGNO (x
)].last_set_nonzero_bits
& nonzero
;
8159 tem
= get_last_value (x
);
8163 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8164 /* If X is narrower than MODE and TEM is a non-negative
8165 constant that would appear negative in the mode of X,
8166 sign-extend it for use in reg_stat[].nonzero_bits because
8167 some machines (maybe most) will actually do the sign-extension
8168 and this is the conservative approach.
8170 ??? For 2.5, try to tighten up the MD files in this regard
8171 instead of this kludge. */
8173 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8174 && GET_CODE (tem
) == CONST_INT
8176 && 0 != (INTVAL (tem
)
8177 & ((HOST_WIDE_INT
) 1
8178 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8179 tem
= GEN_INT (INTVAL (tem
)
8180 | ((HOST_WIDE_INT
) (-1)
8181 << GET_MODE_BITSIZE (GET_MODE (x
))));
8183 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8185 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8187 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8189 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8190 /* We don't know anything about the upper bits. */
8191 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8192 return nonzero
& mask
;
8198 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8199 /* If X is negative in MODE, sign-extend the value. */
8200 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8201 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8202 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8208 #ifdef LOAD_EXTEND_OP
8209 /* In many, if not most, RISC machines, reading a byte from memory
8210 zeros the rest of the register. Noticing that fact saves a lot
8211 of extra zero-extends. */
8212 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8213 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8218 case UNEQ
: case LTGT
:
8219 case GT
: case GTU
: case UNGT
:
8220 case LT
: case LTU
: case UNLT
:
8221 case GE
: case GEU
: case UNGE
:
8222 case LE
: case LEU
: case UNLE
:
8223 case UNORDERED
: case ORDERED
:
8225 /* If this produces an integer result, we know which bits are set.
8226 Code here used to clear bits outside the mode of X, but that is
8229 if (GET_MODE_CLASS (mode
) == MODE_INT
8230 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8231 nonzero
= STORE_FLAG_VALUE
;
8236 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8237 and num_sign_bit_copies. */
8238 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8239 == GET_MODE_BITSIZE (GET_MODE (x
)))
8243 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8244 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8249 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8250 and num_sign_bit_copies. */
8251 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8252 == GET_MODE_BITSIZE (GET_MODE (x
)))
8258 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8259 & GET_MODE_MASK (mode
));
8263 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8264 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8265 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8269 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8270 Otherwise, show all the bits in the outer mode but not the inner
8272 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8273 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8275 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8277 & (((HOST_WIDE_INT
) 1
8278 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8279 inner_nz
|= (GET_MODE_MASK (mode
)
8280 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8283 nonzero
&= inner_nz
;
8287 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8288 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8292 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8294 unsigned HOST_WIDE_INT nonzero0
=
8295 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8297 /* Don't call nonzero_bits for the second time if it cannot change
8299 if ((nonzero
& nonzero0
) != nonzero
)
8300 nonzero
&= (nonzero0
8301 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8305 case PLUS
: case MINUS
:
8307 case DIV
: case UDIV
:
8308 case MOD
: case UMOD
:
8309 /* We can apply the rules of arithmetic to compute the number of
8310 high- and low-order zero bits of these operations. We start by
8311 computing the width (position of the highest-order nonzero bit)
8312 and the number of low-order zero bits for each value. */
8314 unsigned HOST_WIDE_INT nz0
=
8315 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8316 unsigned HOST_WIDE_INT nz1
=
8317 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8318 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8319 int width0
= floor_log2 (nz0
) + 1;
8320 int width1
= floor_log2 (nz1
) + 1;
8321 int low0
= floor_log2 (nz0
& -nz0
);
8322 int low1
= floor_log2 (nz1
& -nz1
);
8323 HOST_WIDE_INT op0_maybe_minusp
8324 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8325 HOST_WIDE_INT op1_maybe_minusp
8326 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8327 unsigned int result_width
= mode_width
;
8333 result_width
= MAX (width0
, width1
) + 1;
8334 result_low
= MIN (low0
, low1
);
8337 result_low
= MIN (low0
, low1
);
8340 result_width
= width0
+ width1
;
8341 result_low
= low0
+ low1
;
8346 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8347 result_width
= width0
;
8352 result_width
= width0
;
8357 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8358 result_width
= MIN (width0
, width1
);
8359 result_low
= MIN (low0
, low1
);
8364 result_width
= MIN (width0
, width1
);
8365 result_low
= MIN (low0
, low1
);
8371 if (result_width
< mode_width
)
8372 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8375 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8377 #ifdef POINTERS_EXTEND_UNSIGNED
8378 /* If pointers extend unsigned and this is an addition or subtraction
8379 to a pointer in Pmode, all the bits above ptr_mode are known to be
8381 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8382 && (code
== PLUS
|| code
== MINUS
)
8383 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8384 nonzero
&= GET_MODE_MASK (ptr_mode
);
8390 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8391 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8392 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8396 /* If this is a SUBREG formed for a promoted variable that has
8397 been zero-extended, we know that at least the high-order bits
8398 are zero, though others might be too. */
8400 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8401 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8402 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8404 /* If the inner mode is a single word for both the host and target
8405 machines, we can compute this from which bits of the inner
8406 object might be nonzero. */
8407 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8408 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8409 <= HOST_BITS_PER_WIDE_INT
))
8411 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8413 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8414 /* If this is a typical RISC machine, we only have to worry
8415 about the way loads are extended. */
8416 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8418 & (((unsigned HOST_WIDE_INT
) 1
8419 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8421 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8422 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8425 /* On many CISC machines, accessing an object in a wider mode
8426 causes the high-order bits to become undefined. So they are
8427 not known to be zero. */
8428 if (GET_MODE_SIZE (GET_MODE (x
))
8429 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8430 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8431 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8440 /* The nonzero bits are in two classes: any bits within MODE
8441 that aren't in GET_MODE (x) are always significant. The rest of the
8442 nonzero bits are those that are significant in the operand of
8443 the shift when shifted the appropriate number of bits. This
8444 shows that high-order bits are cleared by the right shift and
8445 low-order bits by left shifts. */
8446 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8447 && INTVAL (XEXP (x
, 1)) >= 0
8448 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8450 enum machine_mode inner_mode
= GET_MODE (x
);
8451 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8452 int count
= INTVAL (XEXP (x
, 1));
8453 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8454 unsigned HOST_WIDE_INT op_nonzero
=
8455 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8456 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8457 unsigned HOST_WIDE_INT outer
= 0;
8459 if (mode_width
> width
)
8460 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8462 if (code
== LSHIFTRT
)
8464 else if (code
== ASHIFTRT
)
8468 /* If the sign bit may have been nonzero before the shift, we
8469 need to mark all the places it could have been copied to
8470 by the shift as possibly nonzero. */
8471 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8472 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8474 else if (code
== ASHIFT
)
8477 inner
= ((inner
<< (count
% width
)
8478 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8480 nonzero
&= (outer
| inner
);
8486 /* This is at most the number of bits in the mode. */
8487 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8491 /* If CLZ has a known value at zero, then the nonzero bits are
8492 that value, plus the number of bits in the mode minus one. */
8493 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8494 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8500 /* If CTZ has a known value at zero, then the nonzero bits are
8501 that value, plus the number of bits in the mode minus one. */
8502 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8503 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8513 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8514 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8524 /* See the macro definition above. */
8525 #undef cached_num_sign_bit_copies
8527 #define num_sign_bit_copies_with_known(X, M) \
8528 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8530 /* The function cached_num_sign_bit_copies is a wrapper around
8531 num_sign_bit_copies1. It avoids exponential behavior in
8532 num_sign_bit_copies1 when X has identical subexpressions on the
8533 first or the second level. */
8536 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8537 enum machine_mode known_mode
,
8538 unsigned int known_ret
)
8540 if (x
== known_x
&& mode
== known_mode
)
8543 /* Try to find identical subexpressions. If found call
8544 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8545 the precomputed value for the subexpression as KNOWN_RET. */
8547 if (ARITHMETIC_P (x
))
8549 rtx x0
= XEXP (x
, 0);
8550 rtx x1
= XEXP (x
, 1);
8552 /* Check the first level. */
8555 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8556 num_sign_bit_copies_with_known (x0
, mode
));
8558 /* Check the second level. */
8559 if (ARITHMETIC_P (x0
)
8560 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8562 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8563 num_sign_bit_copies_with_known (x1
, mode
));
8565 if (ARITHMETIC_P (x1
)
8566 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8568 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8569 num_sign_bit_copies_with_known (x0
, mode
));
8572 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8575 /* Return the number of bits at the high-order end of X that are known to
8576 be equal to the sign bit. X will be used in mode MODE; if MODE is
8577 VOIDmode, X will be used in its own mode. The returned value will always
8578 be between 1 and the number of bits in MODE. */
8581 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8582 enum machine_mode known_mode
,
8583 unsigned int known_ret
)
8585 enum rtx_code code
= GET_CODE (x
);
8586 unsigned int bitwidth
;
8587 int num0
, num1
, result
;
8588 unsigned HOST_WIDE_INT nonzero
;
8591 /* If we weren't given a mode, use the mode of X. If the mode is still
8592 VOIDmode, we don't know anything. Likewise if one of the modes is
8595 if (mode
== VOIDmode
)
8596 mode
= GET_MODE (x
);
8598 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8601 bitwidth
= GET_MODE_BITSIZE (mode
);
8603 /* For a smaller object, just ignore the high bits. */
8604 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8606 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8608 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8611 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8613 #ifndef WORD_REGISTER_OPERATIONS
8614 /* If this machine does not do all register operations on the entire
8615 register and MODE is wider than the mode of X, we can say nothing
8616 at all about the high-order bits. */
8619 /* Likewise on machines that do, if the mode of the object is smaller
8620 than a word and loads of that size don't sign extend, we can say
8621 nothing about the high order bits. */
8622 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8623 #ifdef LOAD_EXTEND_OP
8624 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8635 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8636 /* If pointers extend signed and this is a pointer in Pmode, say that
8637 all the bits above ptr_mode are known to be sign bit copies. */
8638 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8640 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8643 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8644 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8645 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8646 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8647 && REG_N_SETS (REGNO (x
)) == 1
8648 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8650 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8651 return reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8653 tem
= get_last_value (x
);
8655 return num_sign_bit_copies_with_known (tem
, mode
);
8657 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8658 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8659 return reg_stat
[REGNO (x
)].sign_bit_copies
;
8663 #ifdef LOAD_EXTEND_OP
8664 /* Some RISC machines sign-extend all loads of smaller than a word. */
8665 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8666 return MAX (1, ((int) bitwidth
8667 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8672 /* If the constant is negative, take its 1's complement and remask.
8673 Then see how many zero bits we have. */
8674 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8675 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8676 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8677 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8679 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8682 /* If this is a SUBREG for a promoted object that is sign-extended
8683 and we are looking at it in a wider mode, we know that at least the
8684 high-order bits are known to be sign bit copies. */
8686 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8688 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8689 return MAX ((int) bitwidth
8690 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8694 /* For a smaller object, just ignore the high bits. */
8695 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8697 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8698 return MAX (1, (num0
8699 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8703 #ifdef WORD_REGISTER_OPERATIONS
8704 #ifdef LOAD_EXTEND_OP
8705 /* For paradoxical SUBREGs on machines where all register operations
8706 affect the entire register, just look inside. Note that we are
8707 passing MODE to the recursive call, so the number of sign bit copies
8708 will remain relative to that mode, not the inner mode. */
8710 /* This works only if loads sign extend. Otherwise, if we get a
8711 reload for the inner part, it may be loaded from the stack, and
8712 then we lose all sign bit copies that existed before the store
8715 if ((GET_MODE_SIZE (GET_MODE (x
))
8716 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8717 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8718 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8719 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8725 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8726 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8730 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8731 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8734 /* For a smaller object, just ignore the high bits. */
8735 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8736 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8740 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8742 case ROTATE
: case ROTATERT
:
8743 /* If we are rotating left by a number of bits less than the number
8744 of sign bit copies, we can just subtract that amount from the
8746 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8747 && INTVAL (XEXP (x
, 1)) >= 0
8748 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8750 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8751 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8752 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8757 /* In general, this subtracts one sign bit copy. But if the value
8758 is known to be positive, the number of sign bit copies is the
8759 same as that of the input. Finally, if the input has just one bit
8760 that might be nonzero, all the bits are copies of the sign bit. */
8761 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8762 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8763 return num0
> 1 ? num0
- 1 : 1;
8765 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8770 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8775 case IOR
: case AND
: case XOR
:
8776 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8777 /* Logical operations will preserve the number of sign-bit copies.
8778 MIN and MAX operations always return one of the operands. */
8779 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8780 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8781 return MIN (num0
, num1
);
8783 case PLUS
: case MINUS
:
8784 /* For addition and subtraction, we can have a 1-bit carry. However,
8785 if we are subtracting 1 from a positive number, there will not
8786 be such a carry. Furthermore, if the positive number is known to
8787 be 0 or 1, we know the result is either -1 or 0. */
8789 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8790 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8792 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8793 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8794 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8795 : bitwidth
- floor_log2 (nonzero
) - 1);
8798 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8799 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8800 result
= MAX (1, MIN (num0
, num1
) - 1);
8802 #ifdef POINTERS_EXTEND_UNSIGNED
8803 /* If pointers extend signed and this is an addition or subtraction
8804 to a pointer in Pmode, all the bits above ptr_mode are known to be
8806 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8807 && (code
== PLUS
|| code
== MINUS
)
8808 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8809 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8810 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8816 /* The number of bits of the product is the sum of the number of
8817 bits of both terms. However, unless one of the terms if known
8818 to be positive, we must allow for an additional bit since negating
8819 a negative number can remove one sign bit copy. */
8821 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8822 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8824 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8826 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8827 || (((nonzero_bits (XEXP (x
, 0), mode
)
8828 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8829 && ((nonzero_bits (XEXP (x
, 1), mode
)
8830 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8833 return MAX (1, result
);
8836 /* The result must be <= the first operand. If the first operand
8837 has the high bit set, we know nothing about the number of sign
8839 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8841 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8842 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8845 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8848 /* The result must be <= the second operand. */
8849 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8852 /* Similar to unsigned division, except that we have to worry about
8853 the case where the divisor is negative, in which case we have
8855 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8857 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8858 || (nonzero_bits (XEXP (x
, 1), mode
)
8859 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8865 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8867 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8868 || (nonzero_bits (XEXP (x
, 1), mode
)
8869 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8875 /* Shifts by a constant add to the number of bits equal to the
8877 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8878 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8879 && INTVAL (XEXP (x
, 1)) > 0)
8880 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8885 /* Left shifts destroy copies. */
8886 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8887 || INTVAL (XEXP (x
, 1)) < 0
8888 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8891 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8892 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8895 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8896 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8897 return MIN (num0
, num1
);
8899 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8900 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8901 case GEU
: case GTU
: case LEU
: case LTU
:
8902 case UNORDERED
: case ORDERED
:
8903 /* If the constant is negative, take its 1's complement and remask.
8904 Then see how many zero bits we have. */
8905 nonzero
= STORE_FLAG_VALUE
;
8906 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8907 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8908 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8910 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8917 /* If we haven't been able to figure it out by one of the above rules,
8918 see if some of the high-order bits are known to be zero. If so,
8919 count those bits and return one less than that amount. If we can't
8920 safely compute the mask for this mode, always return BITWIDTH. */
8922 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8925 nonzero
= nonzero_bits (x
, mode
);
8926 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8927 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8930 /* Return the number of "extended" bits there are in X, when interpreted
8931 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8932 unsigned quantities, this is the number of high-order zero bits.
8933 For signed quantities, this is the number of copies of the sign bit
8934 minus 1. In both case, this function returns the number of "spare"
8935 bits. For example, if two quantities for which this function returns
8936 at least 1 are added, the addition is known not to overflow.
8938 This function will always return 0 unless called during combine, which
8939 implies that it must be called from a define_split. */
8942 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8944 if (nonzero_sign_valid
== 0)
8948 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8949 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8950 - floor_log2 (nonzero_bits (x
, mode
)))
8952 : num_sign_bit_copies (x
, mode
) - 1);
8955 /* This function is called from `simplify_shift_const' to merge two
8956 outer operations. Specifically, we have already found that we need
8957 to perform operation *POP0 with constant *PCONST0 at the outermost
8958 position. We would now like to also perform OP1 with constant CONST1
8959 (with *POP0 being done last).
8961 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8962 the resulting operation. *PCOMP_P is set to 1 if we would need to
8963 complement the innermost operand, otherwise it is unchanged.
8965 MODE is the mode in which the operation will be done. No bits outside
8966 the width of this mode matter. It is assumed that the width of this mode
8967 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8969 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8970 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8971 result is simply *PCONST0.
8973 If the resulting operation cannot be expressed as one operation, we
8974 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8977 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8979 enum rtx_code op0
= *pop0
;
8980 HOST_WIDE_INT const0
= *pconst0
;
8982 const0
&= GET_MODE_MASK (mode
);
8983 const1
&= GET_MODE_MASK (mode
);
8985 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8989 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8992 if (op1
== NIL
|| op0
== SET
)
8995 else if (op0
== NIL
)
8996 op0
= op1
, const0
= const1
;
8998 else if (op0
== op1
)
9022 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9023 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9026 /* If the two constants aren't the same, we can't do anything. The
9027 remaining six cases can all be done. */
9028 else if (const0
!= const1
)
9036 /* (a & b) | b == b */
9038 else /* op1 == XOR */
9039 /* (a ^ b) | b == a | b */
9045 /* (a & b) ^ b == (~a) & b */
9046 op0
= AND
, *pcomp_p
= 1;
9047 else /* op1 == IOR */
9048 /* (a | b) ^ b == a & ~b */
9049 op0
= AND
, const0
= ~const0
;
9054 /* (a | b) & b == b */
9056 else /* op1 == XOR */
9057 /* (a ^ b) & b) == (~a) & b */
9064 /* Check for NO-OP cases. */
9065 const0
&= GET_MODE_MASK (mode
);
9067 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9069 else if (const0
== 0 && op0
== AND
)
9071 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9075 /* ??? Slightly redundant with the above mask, but not entirely.
9076 Moving this above means we'd have to sign-extend the mode mask
9077 for the final test. */
9078 const0
= trunc_int_for_mode (const0
, mode
);
9086 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9087 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9088 that we started with.
9090 The shift is normally computed in the widest mode we find in VAROP, as
9091 long as it isn't a different number of words than RESULT_MODE. Exceptions
9092 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9095 simplify_shift_const (rtx x
, enum rtx_code code
,
9096 enum machine_mode result_mode
, rtx varop
,
9099 enum rtx_code orig_code
= code
;
9102 enum machine_mode mode
= result_mode
;
9103 enum machine_mode shift_mode
, tmode
;
9104 unsigned int mode_words
9105 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9106 /* We form (outer_op (code varop count) (outer_const)). */
9107 enum rtx_code outer_op
= NIL
;
9108 HOST_WIDE_INT outer_const
= 0;
9110 int complement_p
= 0;
9113 /* Make sure and truncate the "natural" shift on the way in. We don't
9114 want to do this inside the loop as it makes it more difficult to
9116 if (SHIFT_COUNT_TRUNCATED
)
9117 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9119 /* If we were given an invalid count, don't do anything except exactly
9120 what was requested. */
9122 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9127 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9132 /* Unless one of the branches of the `if' in this loop does a `continue',
9133 we will `break' the loop after the `if'. */
9137 /* If we have an operand of (clobber (const_int 0)), just return that
9139 if (GET_CODE (varop
) == CLOBBER
)
9142 /* If we discovered we had to complement VAROP, leave. Making a NOT
9143 here would cause an infinite loop. */
9147 /* Convert ROTATERT to ROTATE. */
9148 if (code
== ROTATERT
)
9150 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9152 if (VECTOR_MODE_P (result_mode
))
9153 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9155 count
= bitsize
- count
;
9158 /* We need to determine what mode we will do the shift in. If the
9159 shift is a right shift or a ROTATE, we must always do it in the mode
9160 it was originally done in. Otherwise, we can do it in MODE, the
9161 widest mode encountered. */
9163 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9164 ? result_mode
: mode
);
9166 /* Handle cases where the count is greater than the size of the mode
9167 minus 1. For ASHIFT, use the size minus one as the count (this can
9168 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9169 take the count modulo the size. For other shifts, the result is
9172 Since these shifts are being produced by the compiler by combining
9173 multiple operations, each of which are defined, we know what the
9174 result is supposed to be. */
9176 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9178 if (code
== ASHIFTRT
)
9179 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9180 else if (code
== ROTATE
|| code
== ROTATERT
)
9181 count
%= GET_MODE_BITSIZE (shift_mode
);
9184 /* We can't simply return zero because there may be an
9192 /* An arithmetic right shift of a quantity known to be -1 or 0
9194 if (code
== ASHIFTRT
9195 && (num_sign_bit_copies (varop
, shift_mode
)
9196 == GET_MODE_BITSIZE (shift_mode
)))
9202 /* If we are doing an arithmetic right shift and discarding all but
9203 the sign bit copies, this is equivalent to doing a shift by the
9204 bitsize minus one. Convert it into that shift because it will often
9205 allow other simplifications. */
9207 if (code
== ASHIFTRT
9208 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9209 >= GET_MODE_BITSIZE (shift_mode
)))
9210 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9212 /* We simplify the tests below and elsewhere by converting
9213 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9214 `make_compound_operation' will convert it to an ASHIFTRT for
9215 those machines (such as VAX) that don't have an LSHIFTRT. */
9216 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9218 && ((nonzero_bits (varop
, shift_mode
)
9219 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9223 if (code
== LSHIFTRT
9224 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9225 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9228 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9229 && !((nonzero_bits (varop
, shift_mode
) << count
)
9230 & GET_MODE_MASK (shift_mode
)))
9233 switch (GET_CODE (varop
))
9239 new = expand_compound_operation (varop
);
9248 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9249 minus the width of a smaller mode, we can do this with a
9250 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9251 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9252 && ! mode_dependent_address_p (XEXP (varop
, 0))
9253 && ! MEM_VOLATILE_P (varop
)
9254 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9255 MODE_INT
, 1)) != BLKmode
)
9257 new = adjust_address_nv (varop
, tmode
,
9258 BYTES_BIG_ENDIAN
? 0
9259 : count
/ BITS_PER_UNIT
);
9261 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9262 : ZERO_EXTEND
, mode
, new);
9269 /* Similar to the case above, except that we can only do this if
9270 the resulting mode is the same as that of the underlying
9271 MEM and adjust the address depending on the *bits* endianness
9272 because of the way that bit-field extract insns are defined. */
9273 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9274 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9275 MODE_INT
, 1)) != BLKmode
9276 && tmode
== GET_MODE (XEXP (varop
, 0)))
9278 if (BITS_BIG_ENDIAN
)
9279 new = XEXP (varop
, 0);
9282 new = copy_rtx (XEXP (varop
, 0));
9283 SUBST (XEXP (new, 0),
9284 plus_constant (XEXP (new, 0),
9285 count
/ BITS_PER_UNIT
));
9288 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9289 : ZERO_EXTEND
, mode
, new);
9296 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9297 the same number of words as what we've seen so far. Then store
9298 the widest mode in MODE. */
9299 if (subreg_lowpart_p (varop
)
9300 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9301 > GET_MODE_SIZE (GET_MODE (varop
)))
9302 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9303 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9306 varop
= SUBREG_REG (varop
);
9307 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9308 mode
= GET_MODE (varop
);
9314 /* Some machines use MULT instead of ASHIFT because MULT
9315 is cheaper. But it is still better on those machines to
9316 merge two shifts into one. */
9317 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9318 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9321 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9322 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9328 /* Similar, for when divides are cheaper. */
9329 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9330 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9333 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9334 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9340 /* If we are extracting just the sign bit of an arithmetic
9341 right shift, that shift is not needed. However, the sign
9342 bit of a wider mode may be different from what would be
9343 interpreted as the sign bit in a narrower mode, so, if
9344 the result is narrower, don't discard the shift. */
9345 if (code
== LSHIFTRT
9346 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9347 && (GET_MODE_BITSIZE (result_mode
)
9348 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9350 varop
= XEXP (varop
, 0);
9354 /* ... fall through ... */
9359 /* Here we have two nested shifts. The result is usually the
9360 AND of a new shift with a mask. We compute the result below. */
9361 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9362 && INTVAL (XEXP (varop
, 1)) >= 0
9363 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9364 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9365 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9367 enum rtx_code first_code
= GET_CODE (varop
);
9368 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9369 unsigned HOST_WIDE_INT mask
;
9372 /* We have one common special case. We can't do any merging if
9373 the inner code is an ASHIFTRT of a smaller mode. However, if
9374 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9375 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9376 we can convert it to
9377 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9378 This simplifies certain SIGN_EXTEND operations. */
9379 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9380 && count
== (unsigned int)
9381 (GET_MODE_BITSIZE (result_mode
)
9382 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9384 /* C3 has the low-order C1 bits zero. */
9386 mask
= (GET_MODE_MASK (mode
)
9387 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9389 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9390 XEXP (varop
, 0), mask
);
9391 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9393 count
= first_count
;
9398 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9399 than C1 high-order bits equal to the sign bit, we can convert
9400 this to either an ASHIFT or an ASHIFTRT depending on the
9403 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9405 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9406 && GET_MODE (varop
) == shift_mode
9407 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9410 varop
= XEXP (varop
, 0);
9412 signed_count
= count
- first_count
;
9413 if (signed_count
< 0)
9414 count
= -signed_count
, code
= ASHIFT
;
9416 count
= signed_count
;
9421 /* There are some cases we can't do. If CODE is ASHIFTRT,
9422 we can only do this if FIRST_CODE is also ASHIFTRT.
9424 We can't do the case when CODE is ROTATE and FIRST_CODE is
9427 If the mode of this shift is not the mode of the outer shift,
9428 we can't do this if either shift is a right shift or ROTATE.
9430 Finally, we can't do any of these if the mode is too wide
9431 unless the codes are the same.
9433 Handle the case where the shift codes are the same
9436 if (code
== first_code
)
9438 if (GET_MODE (varop
) != result_mode
9439 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9443 count
+= first_count
;
9444 varop
= XEXP (varop
, 0);
9448 if (code
== ASHIFTRT
9449 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9450 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9451 || (GET_MODE (varop
) != result_mode
9452 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9453 || first_code
== ROTATE
9454 || code
== ROTATE
)))
9457 /* To compute the mask to apply after the shift, shift the
9458 nonzero bits of the inner shift the same way the
9459 outer shift will. */
9461 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9464 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9467 /* Give up if we can't compute an outer operation to use. */
9469 || GET_CODE (mask_rtx
) != CONST_INT
9470 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9472 result_mode
, &complement_p
))
9475 /* If the shifts are in the same direction, we add the
9476 counts. Otherwise, we subtract them. */
9477 signed_count
= count
;
9478 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9479 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9480 signed_count
+= first_count
;
9482 signed_count
-= first_count
;
9484 /* If COUNT is positive, the new shift is usually CODE,
9485 except for the two exceptions below, in which case it is
9486 FIRST_CODE. If the count is negative, FIRST_CODE should
9488 if (signed_count
> 0
9489 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9490 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9491 code
= first_code
, count
= signed_count
;
9492 else if (signed_count
< 0)
9493 code
= first_code
, count
= -signed_count
;
9495 count
= signed_count
;
9497 varop
= XEXP (varop
, 0);
9501 /* If we have (A << B << C) for any shift, we can convert this to
9502 (A << C << B). This wins if A is a constant. Only try this if
9503 B is not a constant. */
9505 else if (GET_CODE (varop
) == code
9506 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9508 = simplify_binary_operation (code
, mode
,
9512 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9519 /* Make this fit the case below. */
9520 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9521 GEN_INT (GET_MODE_MASK (mode
)));
9527 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9528 with C the size of VAROP - 1 and the shift is logical if
9529 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9530 we have an (le X 0) operation. If we have an arithmetic shift
9531 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9532 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9534 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9535 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9536 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9537 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9538 && count
== (unsigned int)
9539 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9540 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9543 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9546 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9547 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9552 /* If we have (shift (logical)), move the logical to the outside
9553 to allow it to possibly combine with another logical and the
9554 shift to combine with another shift. This also canonicalizes to
9555 what a ZERO_EXTRACT looks like. Also, some machines have
9556 (and (shift)) insns. */
9558 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9559 /* We can't do this if we have (ashiftrt (xor)) and the
9560 constant has its sign bit set in shift_mode. */
9561 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9562 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9564 && (new = simplify_binary_operation (code
, result_mode
,
9566 GEN_INT (count
))) != 0
9567 && GET_CODE (new) == CONST_INT
9568 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9569 INTVAL (new), result_mode
, &complement_p
))
9571 varop
= XEXP (varop
, 0);
9575 /* If we can't do that, try to simplify the shift in each arm of the
9576 logical expression, make a new logical expression, and apply
9577 the inverse distributive law. This also can't be done
9578 for some (ashiftrt (xor)). */
9579 if (code
!= ASHIFTRT
|| GET_CODE (varop
)!= XOR
9580 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9583 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9584 XEXP (varop
, 0), count
);
9585 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9586 XEXP (varop
, 1), count
);
9588 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9589 varop
= apply_distributive_law (varop
);
9596 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9597 says that the sign bit can be tested, FOO has mode MODE, C is
9598 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9599 that may be nonzero. */
9600 if (code
== LSHIFTRT
9601 && XEXP (varop
, 1) == const0_rtx
9602 && GET_MODE (XEXP (varop
, 0)) == result_mode
9603 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9604 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9605 && ((STORE_FLAG_VALUE
9606 & ((HOST_WIDE_INT
) 1
9607 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9608 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9609 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9610 (HOST_WIDE_INT
) 1, result_mode
,
9613 varop
= XEXP (varop
, 0);
9620 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9621 than the number of bits in the mode is equivalent to A. */
9622 if (code
== LSHIFTRT
9623 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9624 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9626 varop
= XEXP (varop
, 0);
9631 /* NEG commutes with ASHIFT since it is multiplication. Move the
9632 NEG outside to allow shifts to combine. */
9634 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9635 (HOST_WIDE_INT
) 0, result_mode
,
9638 varop
= XEXP (varop
, 0);
9644 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9645 is one less than the number of bits in the mode is
9646 equivalent to (xor A 1). */
9647 if (code
== LSHIFTRT
9648 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9649 && XEXP (varop
, 1) == constm1_rtx
9650 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9651 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9652 (HOST_WIDE_INT
) 1, result_mode
,
9656 varop
= XEXP (varop
, 0);
9660 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9661 that might be nonzero in BAR are those being shifted out and those
9662 bits are known zero in FOO, we can replace the PLUS with FOO.
9663 Similarly in the other operand order. This code occurs when
9664 we are computing the size of a variable-size array. */
9666 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9667 && count
< HOST_BITS_PER_WIDE_INT
9668 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9669 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9670 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9672 varop
= XEXP (varop
, 0);
9675 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9676 && count
< HOST_BITS_PER_WIDE_INT
9677 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9678 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9680 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9681 & nonzero_bits (XEXP (varop
, 1),
9684 varop
= XEXP (varop
, 1);
9688 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9690 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9691 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9693 GEN_INT (count
))) != 0
9694 && GET_CODE (new) == CONST_INT
9695 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9696 INTVAL (new), result_mode
, &complement_p
))
9698 varop
= XEXP (varop
, 0);
9704 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9705 with C the size of VAROP - 1 and the shift is logical if
9706 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9707 we have a (gt X 0) operation. If the shift is arithmetic with
9708 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9709 we have a (neg (gt X 0)) operation. */
9711 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9712 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9713 && count
== (unsigned int)
9714 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9715 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9716 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9717 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9719 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9722 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9725 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9726 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9733 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9734 if the truncate does not affect the value. */
9735 if (code
== LSHIFTRT
9736 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9737 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9738 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9739 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9740 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9742 rtx varop_inner
= XEXP (varop
, 0);
9745 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9746 XEXP (varop_inner
, 0),
9748 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9749 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9762 /* We need to determine what mode to do the shift in. If the shift is
9763 a right shift or ROTATE, we must always do it in the mode it was
9764 originally done in. Otherwise, we can do it in MODE, the widest mode
9765 encountered. The code we care about is that of the shift that will
9766 actually be done, not the shift that was originally requested. */
9768 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9769 ? result_mode
: mode
);
9771 /* We have now finished analyzing the shift. The result should be
9772 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9773 OUTER_OP is non-NIL, it is an operation that needs to be applied
9774 to the result of the shift. OUTER_CONST is the relevant constant,
9775 but we must turn off all bits turned off in the shift.
9777 If we were passed a value for X, see if we can use any pieces of
9778 it. If not, make new rtx. */
9780 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9781 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9782 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9783 const_rtx
= XEXP (x
, 1);
9785 const_rtx
= GEN_INT (count
);
9787 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9788 && GET_MODE (XEXP (x
, 0)) == shift_mode
9789 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9790 varop
= XEXP (x
, 0);
9791 else if (GET_MODE (varop
) != shift_mode
)
9792 varop
= gen_lowpart (shift_mode
, varop
);
9794 /* If we can't make the SUBREG, try to return what we were given. */
9795 if (GET_CODE (varop
) == CLOBBER
)
9796 return x
? x
: varop
;
9798 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9802 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9804 /* If we have an outer operation and we just made a shift, it is
9805 possible that we could have simplified the shift were it not
9806 for the outer operation. So try to do the simplification
9809 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9810 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9811 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9812 INTVAL (XEXP (x
, 1)));
9814 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9815 turn off all the bits that the shift would have turned off. */
9816 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9817 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9818 GET_MODE_MASK (result_mode
) >> orig_count
);
9820 /* Do the remainder of the processing in RESULT_MODE. */
9821 x
= gen_lowpart (result_mode
, x
);
9823 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9826 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9828 if (outer_op
!= NIL
)
9830 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9831 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9833 if (outer_op
== AND
)
9834 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9835 else if (outer_op
== SET
)
9836 /* This means that we have determined that the result is
9837 equivalent to a constant. This should be rare. */
9838 x
= GEN_INT (outer_const
);
9839 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9840 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9842 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9848 /* Like recog, but we receive the address of a pointer to a new pattern.
9849 We try to match the rtx that the pointer points to.
9850 If that fails, we may try to modify or replace the pattern,
9851 storing the replacement into the same pointer object.
9853 Modifications include deletion or addition of CLOBBERs.
9855 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9856 the CLOBBERs are placed.
9858 The value is the final insn code from the pattern ultimately matched,
9862 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9865 int insn_code_number
;
9866 int num_clobbers_to_add
= 0;
9869 rtx old_notes
, old_pat
;
9871 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9872 we use to indicate that something didn't match. If we find such a
9873 thing, force rejection. */
9874 if (GET_CODE (pat
) == PARALLEL
)
9875 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9876 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9877 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9880 old_pat
= PATTERN (insn
);
9881 old_notes
= REG_NOTES (insn
);
9882 PATTERN (insn
) = pat
;
9883 REG_NOTES (insn
) = 0;
9885 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9887 /* If it isn't, there is the possibility that we previously had an insn
9888 that clobbered some register as a side effect, but the combined
9889 insn doesn't need to do that. So try once more without the clobbers
9890 unless this represents an ASM insn. */
9892 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9893 && GET_CODE (pat
) == PARALLEL
)
9897 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9898 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9901 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9905 SUBST_INT (XVECLEN (pat
, 0), pos
);
9908 pat
= XVECEXP (pat
, 0, 0);
9910 PATTERN (insn
) = pat
;
9911 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9913 PATTERN (insn
) = old_pat
;
9914 REG_NOTES (insn
) = old_notes
;
9916 /* Recognize all noop sets, these will be killed by followup pass. */
9917 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9918 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9920 /* If we had any clobbers to add, make a new pattern than contains
9921 them. Then check to make sure that all of them are dead. */
9922 if (num_clobbers_to_add
)
9924 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9925 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9927 + num_clobbers_to_add
)
9928 : num_clobbers_to_add
+ 1));
9930 if (GET_CODE (pat
) == PARALLEL
)
9931 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9932 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9934 XVECEXP (newpat
, 0, 0) = pat
;
9936 add_clobbers (newpat
, insn_code_number
);
9938 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9939 i
< XVECLEN (newpat
, 0); i
++)
9941 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9942 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9944 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9945 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9953 return insn_code_number
;
9956 /* Like gen_lowpart_general but for use by combine. In combine it
9957 is not possible to create any new pseudoregs. However, it is
9958 safe to create invalid memory addresses, because combine will
9959 try to recognize them and all they will do is make the combine
9962 If for some reason this cannot do its job, an rtx
9963 (clobber (const_int 0)) is returned.
9964 An insn containing that will not be recognized. */
9967 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9971 if (GET_MODE (x
) == mode
)
9974 /* Return identity if this is a CONST or symbolic
9977 && (GET_CODE (x
) == CONST
9978 || GET_CODE (x
) == SYMBOL_REF
9979 || GET_CODE (x
) == LABEL_REF
))
9982 /* We can only support MODE being wider than a word if X is a
9983 constant integer or has a mode the same size. */
9985 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9986 && ! ((GET_MODE (x
) == VOIDmode
9987 && (GET_CODE (x
) == CONST_INT
9988 || GET_CODE (x
) == CONST_DOUBLE
))
9989 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9990 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9992 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9993 won't know what to do. So we will strip off the SUBREG here and
9994 process normally. */
9995 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9998 if (GET_MODE (x
) == mode
)
10002 result
= gen_lowpart_common (mode
, x
);
10003 #ifdef CANNOT_CHANGE_MODE_CLASS
10005 && GET_CODE (result
) == SUBREG
10006 && GET_CODE (SUBREG_REG (result
)) == REG
10007 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10008 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10010 + GET_MODE (result
));
10016 if (GET_CODE (x
) == MEM
)
10020 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10022 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10023 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10025 /* If we want to refer to something bigger than the original memref,
10026 generate a paradoxical subreg instead. That will force a reload
10027 of the original memref X. */
10028 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10029 return gen_rtx_SUBREG (mode
, x
, 0);
10031 if (WORDS_BIG_ENDIAN
)
10032 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10033 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10035 if (BYTES_BIG_ENDIAN
)
10037 /* Adjust the address so that the address-after-the-data is
10039 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10040 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10043 return adjust_address_nv (x
, mode
, offset
);
10046 /* If X is a comparison operator, rewrite it in a new mode. This
10047 probably won't match, but may allow further simplifications. */
10048 else if (COMPARISON_P (x
))
10049 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10051 /* If we couldn't simplify X any other way, just enclose it in a
10052 SUBREG. Normally, this SUBREG won't match, but some patterns may
10053 include an explicit SUBREG or we may simplify it further in combine. */
10058 enum machine_mode sub_mode
= GET_MODE (x
);
10060 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10061 if (sub_mode
== VOIDmode
)
10063 sub_mode
= int_mode_for_mode (mode
);
10064 x
= gen_lowpart_common (sub_mode
, x
);
10066 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10068 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10071 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10075 /* These routines make binary and unary operations by first seeing if they
10076 fold; if not, a new expression is allocated. */
10079 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10084 if (GET_CODE (op0
) == CLOBBER
)
10086 else if (GET_CODE (op1
) == CLOBBER
)
10089 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
10090 && swap_commutative_operands_p (op0
, op1
))
10091 tem
= op0
, op0
= op1
, op1
= tem
;
10093 if (GET_RTX_CLASS (code
) == RTX_COMPARE
10094 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
10096 enum machine_mode op_mode
= GET_MODE (op0
);
10098 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10099 just (REL_OP X Y). */
10100 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10102 op1
= XEXP (op0
, 1);
10103 op0
= XEXP (op0
, 0);
10104 op_mode
= GET_MODE (op0
);
10107 if (op_mode
== VOIDmode
)
10108 op_mode
= GET_MODE (op1
);
10109 result
= simplify_relational_operation (code
, mode
, op_mode
, op0
, op1
);
10112 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10117 /* Put complex operands first and constants second. */
10118 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
10119 && swap_commutative_operands_p (op0
, op1
))
10120 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10122 /* If we are turning off bits already known off in OP0, we need not do
10124 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10125 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10126 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10129 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10132 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10133 comparison code that will be tested.
10135 The result is a possibly different comparison code to use. *POP0 and
10136 *POP1 may be updated.
10138 It is possible that we might detect that a comparison is either always
10139 true or always false. However, we do not perform general constant
10140 folding in combine, so this knowledge isn't useful. Such tautologies
10141 should have been detected earlier. Hence we ignore all such cases. */
10143 static enum rtx_code
10144 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10150 enum machine_mode mode
, tmode
;
10152 /* Try a few ways of applying the same transformation to both operands. */
10155 #ifndef WORD_REGISTER_OPERATIONS
10156 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10157 so check specially. */
10158 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10159 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10160 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10161 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10162 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10163 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10164 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10165 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10166 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10167 && XEXP (op0
, 1) == XEXP (op1
, 1)
10168 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10169 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10170 && (INTVAL (XEXP (op0
, 1))
10171 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10172 - (GET_MODE_BITSIZE
10173 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10175 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10176 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10180 /* If both operands are the same constant shift, see if we can ignore the
10181 shift. We can if the shift is a rotate or if the bits shifted out of
10182 this shift are known to be zero for both inputs and if the type of
10183 comparison is compatible with the shift. */
10184 if (GET_CODE (op0
) == GET_CODE (op1
)
10185 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10186 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10187 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10188 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10189 || (GET_CODE (op0
) == ASHIFTRT
10190 && (code
!= GTU
&& code
!= LTU
10191 && code
!= GEU
&& code
!= LEU
)))
10192 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10193 && INTVAL (XEXP (op0
, 1)) >= 0
10194 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10195 && XEXP (op0
, 1) == XEXP (op1
, 1))
10197 enum machine_mode mode
= GET_MODE (op0
);
10198 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10199 int shift_count
= INTVAL (XEXP (op0
, 1));
10201 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10202 mask
&= (mask
>> shift_count
) << shift_count
;
10203 else if (GET_CODE (op0
) == ASHIFT
)
10204 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10206 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10207 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10208 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10213 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10214 SUBREGs are of the same mode, and, in both cases, the AND would
10215 be redundant if the comparison was done in the narrower mode,
10216 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10217 and the operand's possibly nonzero bits are 0xffffff01; in that case
10218 if we only care about QImode, we don't need the AND). This case
10219 occurs if the output mode of an scc insn is not SImode and
10220 STORE_FLAG_VALUE == 1 (e.g., the 386).
10222 Similarly, check for a case where the AND's are ZERO_EXTEND
10223 operations from some narrower mode even though a SUBREG is not
10226 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10227 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10228 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10230 rtx inner_op0
= XEXP (op0
, 0);
10231 rtx inner_op1
= XEXP (op1
, 0);
10232 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10233 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10236 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10237 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10238 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10239 && (GET_MODE (SUBREG_REG (inner_op0
))
10240 == GET_MODE (SUBREG_REG (inner_op1
)))
10241 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10242 <= HOST_BITS_PER_WIDE_INT
)
10243 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10244 GET_MODE (SUBREG_REG (inner_op0
)))))
10245 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10246 GET_MODE (SUBREG_REG (inner_op1
))))))
10248 op0
= SUBREG_REG (inner_op0
);
10249 op1
= SUBREG_REG (inner_op1
);
10251 /* The resulting comparison is always unsigned since we masked
10252 off the original sign bit. */
10253 code
= unsigned_condition (code
);
10259 for (tmode
= GET_CLASS_NARROWEST_MODE
10260 (GET_MODE_CLASS (GET_MODE (op0
)));
10261 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10262 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10264 op0
= gen_lowpart (tmode
, inner_op0
);
10265 op1
= gen_lowpart (tmode
, inner_op1
);
10266 code
= unsigned_condition (code
);
10275 /* If both operands are NOT, we can strip off the outer operation
10276 and adjust the comparison code for swapped operands; similarly for
10277 NEG, except that this must be an equality comparison. */
10278 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10279 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10280 && (code
== EQ
|| code
== NE
)))
10281 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10287 /* If the first operand is a constant, swap the operands and adjust the
10288 comparison code appropriately, but don't do this if the second operand
10289 is already a constant integer. */
10290 if (swap_commutative_operands_p (op0
, op1
))
10292 tem
= op0
, op0
= op1
, op1
= tem
;
10293 code
= swap_condition (code
);
10296 /* We now enter a loop during which we will try to simplify the comparison.
10297 For the most part, we only are concerned with comparisons with zero,
10298 but some things may really be comparisons with zero but not start
10299 out looking that way. */
10301 while (GET_CODE (op1
) == CONST_INT
)
10303 enum machine_mode mode
= GET_MODE (op0
);
10304 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10305 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10306 int equality_comparison_p
;
10307 int sign_bit_comparison_p
;
10308 int unsigned_comparison_p
;
10309 HOST_WIDE_INT const_op
;
10311 /* We only want to handle integral modes. This catches VOIDmode,
10312 CCmode, and the floating-point modes. An exception is that we
10313 can handle VOIDmode if OP0 is a COMPARE or a comparison
10316 if (GET_MODE_CLASS (mode
) != MODE_INT
10317 && ! (mode
== VOIDmode
10318 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10321 /* Get the constant we are comparing against and turn off all bits
10322 not on in our mode. */
10323 const_op
= INTVAL (op1
);
10324 if (mode
!= VOIDmode
)
10325 const_op
= trunc_int_for_mode (const_op
, mode
);
10326 op1
= GEN_INT (const_op
);
10328 /* If we are comparing against a constant power of two and the value
10329 being compared can only have that single bit nonzero (e.g., it was
10330 `and'ed with that bit), we can replace this with a comparison
10333 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10334 || code
== LT
|| code
== LTU
)
10335 && mode_width
<= HOST_BITS_PER_WIDE_INT
10336 && exact_log2 (const_op
) >= 0
10337 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10339 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10340 op1
= const0_rtx
, const_op
= 0;
10343 /* Similarly, if we are comparing a value known to be either -1 or
10344 0 with -1, change it to the opposite comparison against zero. */
10347 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10348 || code
== GEU
|| code
== LTU
)
10349 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10351 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10352 op1
= const0_rtx
, const_op
= 0;
10355 /* Do some canonicalizations based on the comparison code. We prefer
10356 comparisons against zero and then prefer equality comparisons.
10357 If we can reduce the size of a constant, we will do that too. */
10362 /* < C is equivalent to <= (C - 1) */
10366 op1
= GEN_INT (const_op
);
10368 /* ... fall through to LE case below. */
10374 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10378 op1
= GEN_INT (const_op
);
10382 /* If we are doing a <= 0 comparison on a value known to have
10383 a zero sign bit, we can replace this with == 0. */
10384 else if (const_op
== 0
10385 && mode_width
<= HOST_BITS_PER_WIDE_INT
10386 && (nonzero_bits (op0
, mode
)
10387 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10392 /* >= C is equivalent to > (C - 1). */
10396 op1
= GEN_INT (const_op
);
10398 /* ... fall through to GT below. */
10404 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10408 op1
= GEN_INT (const_op
);
10412 /* If we are doing a > 0 comparison on a value known to have
10413 a zero sign bit, we can replace this with != 0. */
10414 else if (const_op
== 0
10415 && mode_width
<= HOST_BITS_PER_WIDE_INT
10416 && (nonzero_bits (op0
, mode
)
10417 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10422 /* < C is equivalent to <= (C - 1). */
10426 op1
= GEN_INT (const_op
);
10428 /* ... fall through ... */
10431 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10432 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10433 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10435 const_op
= 0, op1
= const0_rtx
;
10443 /* unsigned <= 0 is equivalent to == 0 */
10447 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10448 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10449 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10451 const_op
= 0, op1
= const0_rtx
;
10457 /* >= C is equivalent to < (C - 1). */
10461 op1
= GEN_INT (const_op
);
10463 /* ... fall through ... */
10466 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10467 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10468 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10470 const_op
= 0, op1
= const0_rtx
;
10478 /* unsigned > 0 is equivalent to != 0 */
10482 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10483 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10484 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10486 const_op
= 0, op1
= const0_rtx
;
10495 /* Compute some predicates to simplify code below. */
10497 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10498 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10499 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10502 /* If this is a sign bit comparison and we can do arithmetic in
10503 MODE, say that we will only be needing the sign bit of OP0. */
10504 if (sign_bit_comparison_p
10505 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10506 op0
= force_to_mode (op0
, mode
,
10508 << (GET_MODE_BITSIZE (mode
) - 1)),
10511 /* Now try cases based on the opcode of OP0. If none of the cases
10512 does a "continue", we exit this loop immediately after the
10515 switch (GET_CODE (op0
))
10518 /* If we are extracting a single bit from a variable position in
10519 a constant that has only a single bit set and are comparing it
10520 with zero, we can convert this into an equality comparison
10521 between the position and the location of the single bit. */
10522 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10523 have already reduced the shift count modulo the word size. */
10524 if (!SHIFT_COUNT_TRUNCATED
10525 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10526 && XEXP (op0
, 1) == const1_rtx
10527 && equality_comparison_p
&& const_op
== 0
10528 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10530 if (BITS_BIG_ENDIAN
)
10532 enum machine_mode new_mode
10533 = mode_for_extraction (EP_extzv
, 1);
10534 if (new_mode
== MAX_MACHINE_MODE
)
10535 i
= BITS_PER_WORD
- 1 - i
;
10539 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10543 op0
= XEXP (op0
, 2);
10547 /* Result is nonzero iff shift count is equal to I. */
10548 code
= reverse_condition (code
);
10552 /* ... fall through ... */
10555 tem
= expand_compound_operation (op0
);
10564 /* If testing for equality, we can take the NOT of the constant. */
10565 if (equality_comparison_p
10566 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10568 op0
= XEXP (op0
, 0);
10573 /* If just looking at the sign bit, reverse the sense of the
10575 if (sign_bit_comparison_p
)
10577 op0
= XEXP (op0
, 0);
10578 code
= (code
== GE
? LT
: GE
);
10584 /* If testing for equality, we can take the NEG of the constant. */
10585 if (equality_comparison_p
10586 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10588 op0
= XEXP (op0
, 0);
10593 /* The remaining cases only apply to comparisons with zero. */
10597 /* When X is ABS or is known positive,
10598 (neg X) is < 0 if and only if X != 0. */
10600 if (sign_bit_comparison_p
10601 && (GET_CODE (XEXP (op0
, 0)) == ABS
10602 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10603 && (nonzero_bits (XEXP (op0
, 0), mode
)
10604 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10606 op0
= XEXP (op0
, 0);
10607 code
= (code
== LT
? NE
: EQ
);
10611 /* If we have NEG of something whose two high-order bits are the
10612 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10613 if (num_sign_bit_copies (op0
, mode
) >= 2)
10615 op0
= XEXP (op0
, 0);
10616 code
= swap_condition (code
);
10622 /* If we are testing equality and our count is a constant, we
10623 can perform the inverse operation on our RHS. */
10624 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10625 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10626 op1
, XEXP (op0
, 1))) != 0)
10628 op0
= XEXP (op0
, 0);
10633 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10634 a particular bit. Convert it to an AND of a constant of that
10635 bit. This will be converted into a ZERO_EXTRACT. */
10636 if (const_op
== 0 && sign_bit_comparison_p
10637 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10638 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10640 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10643 - INTVAL (XEXP (op0
, 1)))));
10644 code
= (code
== LT
? NE
: EQ
);
10648 /* Fall through. */
10651 /* ABS is ignorable inside an equality comparison with zero. */
10652 if (const_op
== 0 && equality_comparison_p
)
10654 op0
= XEXP (op0
, 0);
10660 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10661 to (compare FOO CONST) if CONST fits in FOO's mode and we
10662 are either testing inequality or have an unsigned comparison
10663 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10664 if (! unsigned_comparison_p
10665 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10666 <= HOST_BITS_PER_WIDE_INT
)
10667 && ((unsigned HOST_WIDE_INT
) const_op
10668 < (((unsigned HOST_WIDE_INT
) 1
10669 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10671 op0
= XEXP (op0
, 0);
10677 /* Check for the case where we are comparing A - C1 with C2,
10678 both constants are smaller than 1/2 the maximum positive
10679 value in MODE, and the comparison is equality or unsigned.
10680 In that case, if A is either zero-extended to MODE or has
10681 sufficient sign bits so that the high-order bit in MODE
10682 is a copy of the sign in the inner mode, we can prove that it is
10683 safe to do the operation in the wider mode. This simplifies
10684 many range checks. */
10686 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10687 && subreg_lowpart_p (op0
)
10688 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10689 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10690 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10691 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10692 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10693 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10694 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10695 GET_MODE (SUBREG_REG (op0
)))
10696 & ~GET_MODE_MASK (mode
))
10697 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10698 GET_MODE (SUBREG_REG (op0
)))
10700 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10701 - GET_MODE_BITSIZE (mode
)))))
10703 op0
= SUBREG_REG (op0
);
10707 /* If the inner mode is narrower and we are extracting the low part,
10708 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10709 if (subreg_lowpart_p (op0
)
10710 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10711 /* Fall through */ ;
10715 /* ... fall through ... */
10718 if ((unsigned_comparison_p
|| equality_comparison_p
)
10719 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10720 <= HOST_BITS_PER_WIDE_INT
)
10721 && ((unsigned HOST_WIDE_INT
) const_op
10722 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10724 op0
= XEXP (op0
, 0);
10730 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10731 this for equality comparisons due to pathological cases involving
10733 if (equality_comparison_p
10734 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10735 op1
, XEXP (op0
, 1))))
10737 op0
= XEXP (op0
, 0);
10742 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10743 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10744 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10746 op0
= XEXP (XEXP (op0
, 0), 0);
10747 code
= (code
== LT
? EQ
: NE
);
10753 /* We used to optimize signed comparisons against zero, but that
10754 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10755 arrive here as equality comparisons, or (GEU, LTU) are
10756 optimized away. No need to special-case them. */
10758 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10759 (eq B (minus A C)), whichever simplifies. We can only do
10760 this for equality comparisons due to pathological cases involving
10762 if (equality_comparison_p
10763 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10764 XEXP (op0
, 1), op1
)))
10766 op0
= XEXP (op0
, 0);
10771 if (equality_comparison_p
10772 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10773 XEXP (op0
, 0), op1
)))
10775 op0
= XEXP (op0
, 1);
10780 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10781 of bits in X minus 1, is one iff X > 0. */
10782 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10783 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10784 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10786 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10788 op0
= XEXP (op0
, 1);
10789 code
= (code
== GE
? LE
: GT
);
10795 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10796 if C is zero or B is a constant. */
10797 if (equality_comparison_p
10798 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10799 XEXP (op0
, 1), op1
)))
10801 op0
= XEXP (op0
, 0);
10808 case UNEQ
: case LTGT
:
10809 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10810 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10811 case UNORDERED
: case ORDERED
:
10812 /* We can't do anything if OP0 is a condition code value, rather
10813 than an actual data value. */
10815 || CC0_P (XEXP (op0
, 0))
10816 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10819 /* Get the two operands being compared. */
10820 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10821 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10823 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10825 /* Check for the cases where we simply want the result of the
10826 earlier test or the opposite of that result. */
10827 if (code
== NE
|| code
== EQ
10828 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10829 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10830 && (STORE_FLAG_VALUE
10831 & (((HOST_WIDE_INT
) 1
10832 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10833 && (code
== LT
|| code
== GE
)))
10835 enum rtx_code new_code
;
10836 if (code
== LT
|| code
== NE
)
10837 new_code
= GET_CODE (op0
);
10839 new_code
= combine_reversed_comparison_code (op0
);
10841 if (new_code
!= UNKNOWN
)
10852 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10854 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10855 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10856 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10858 op0
= XEXP (op0
, 1);
10859 code
= (code
== GE
? GT
: LE
);
10865 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10866 will be converted to a ZERO_EXTRACT later. */
10867 if (const_op
== 0 && equality_comparison_p
10868 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10869 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10871 op0
= simplify_and_const_int
10872 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10874 XEXP (XEXP (op0
, 0), 1)),
10875 (HOST_WIDE_INT
) 1);
10879 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10880 zero and X is a comparison and C1 and C2 describe only bits set
10881 in STORE_FLAG_VALUE, we can compare with X. */
10882 if (const_op
== 0 && equality_comparison_p
10883 && mode_width
<= HOST_BITS_PER_WIDE_INT
10884 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10885 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10886 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10887 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10888 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10890 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10891 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10892 if ((~STORE_FLAG_VALUE
& mask
) == 0
10893 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10894 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10895 && COMPARISON_P (tem
))))
10897 op0
= XEXP (XEXP (op0
, 0), 0);
10902 /* If we are doing an equality comparison of an AND of a bit equal
10903 to the sign bit, replace this with a LT or GE comparison of
10904 the underlying value. */
10905 if (equality_comparison_p
10907 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10908 && mode_width
<= HOST_BITS_PER_WIDE_INT
10909 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10910 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10912 op0
= XEXP (op0
, 0);
10913 code
= (code
== EQ
? GE
: LT
);
10917 /* If this AND operation is really a ZERO_EXTEND from a narrower
10918 mode, the constant fits within that mode, and this is either an
10919 equality or unsigned comparison, try to do this comparison in
10920 the narrower mode. */
10921 if ((equality_comparison_p
|| unsigned_comparison_p
)
10922 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10923 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10924 & GET_MODE_MASK (mode
))
10926 && const_op
>> i
== 0
10927 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10929 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10933 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10934 fits in both M1 and M2 and the SUBREG is either paradoxical
10935 or represents the low part, permute the SUBREG and the AND
10937 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10939 unsigned HOST_WIDE_INT c1
;
10940 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10941 /* Require an integral mode, to avoid creating something like
10943 if (SCALAR_INT_MODE_P (tmode
)
10944 /* It is unsafe to commute the AND into the SUBREG if the
10945 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10946 not defined. As originally written the upper bits
10947 have a defined value due to the AND operation.
10948 However, if we commute the AND inside the SUBREG then
10949 they no longer have defined values and the meaning of
10950 the code has been changed. */
10952 #ifdef WORD_REGISTER_OPERATIONS
10953 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10954 && mode_width
<= BITS_PER_WORD
)
10956 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10957 && subreg_lowpart_p (XEXP (op0
, 0))))
10958 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10959 && mode_width
<= HOST_BITS_PER_WIDE_INT
10960 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10961 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10962 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10964 && c1
!= GET_MODE_MASK (tmode
))
10966 op0
= gen_binary (AND
, tmode
,
10967 SUBREG_REG (XEXP (op0
, 0)),
10968 gen_int_mode (c1
, tmode
));
10969 op0
= gen_lowpart (mode
, op0
);
10974 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10975 if (const_op
== 0 && equality_comparison_p
10976 && XEXP (op0
, 1) == const1_rtx
10977 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10979 op0
= simplify_and_const_int
10980 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10981 code
= (code
== NE
? EQ
: NE
);
10985 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10986 (eq (and (lshiftrt X) 1) 0).
10987 Also handle the case where (not X) is expressed using xor. */
10988 if (const_op
== 0 && equality_comparison_p
10989 && XEXP (op0
, 1) == const1_rtx
10990 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10992 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10993 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10995 if (GET_CODE (shift_op
) == NOT
10996 || (GET_CODE (shift_op
) == XOR
10997 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10998 && GET_CODE (shift_count
) == CONST_INT
10999 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11000 && (INTVAL (XEXP (shift_op
, 1))
11001 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11003 op0
= simplify_and_const_int
11005 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11006 (HOST_WIDE_INT
) 1);
11007 code
= (code
== NE
? EQ
: NE
);
11014 /* If we have (compare (ashift FOO N) (const_int C)) and
11015 the high order N bits of FOO (N+1 if an inequality comparison)
11016 are known to be zero, we can do this by comparing FOO with C
11017 shifted right N bits so long as the low-order N bits of C are
11019 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11020 && INTVAL (XEXP (op0
, 1)) >= 0
11021 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11022 < HOST_BITS_PER_WIDE_INT
)
11024 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11025 && mode_width
<= HOST_BITS_PER_WIDE_INT
11026 && (nonzero_bits (XEXP (op0
, 0), mode
)
11027 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11028 + ! equality_comparison_p
))) == 0)
11030 /* We must perform a logical shift, not an arithmetic one,
11031 as we want the top N bits of C to be zero. */
11032 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11034 temp
>>= INTVAL (XEXP (op0
, 1));
11035 op1
= gen_int_mode (temp
, mode
);
11036 op0
= XEXP (op0
, 0);
11040 /* If we are doing a sign bit comparison, it means we are testing
11041 a particular bit. Convert it to the appropriate AND. */
11042 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11043 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11045 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11048 - INTVAL (XEXP (op0
, 1)))));
11049 code
= (code
== LT
? NE
: EQ
);
11053 /* If this an equality comparison with zero and we are shifting
11054 the low bit to the sign bit, we can convert this to an AND of the
11056 if (const_op
== 0 && equality_comparison_p
11057 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11058 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11061 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11062 (HOST_WIDE_INT
) 1);
11068 /* If this is an equality comparison with zero, we can do this
11069 as a logical shift, which might be much simpler. */
11070 if (equality_comparison_p
&& const_op
== 0
11071 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11073 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11075 INTVAL (XEXP (op0
, 1)));
11079 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11080 do the comparison in a narrower mode. */
11081 if (! unsigned_comparison_p
11082 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11083 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11084 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11085 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11086 MODE_INT
, 1)) != BLKmode
11087 && (((unsigned HOST_WIDE_INT
) const_op
11088 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11089 <= GET_MODE_MASK (tmode
)))
11091 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11095 /* Likewise if OP0 is a PLUS of a sign extension with a
11096 constant, which is usually represented with the PLUS
11097 between the shifts. */
11098 if (! unsigned_comparison_p
11099 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11100 && GET_CODE (XEXP (op0
, 0)) == PLUS
11101 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11102 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11103 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11104 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11105 MODE_INT
, 1)) != BLKmode
11106 && (((unsigned HOST_WIDE_INT
) const_op
11107 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11108 <= GET_MODE_MASK (tmode
)))
11110 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11111 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11112 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11115 op0
= gen_binary (PLUS
, tmode
,
11116 gen_lowpart (tmode
, inner
),
11121 /* ... fall through ... */
11123 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11124 the low order N bits of FOO are known to be zero, we can do this
11125 by comparing FOO with C shifted left N bits so long as no
11126 overflow occurs. */
11127 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11128 && INTVAL (XEXP (op0
, 1)) >= 0
11129 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11130 && mode_width
<= HOST_BITS_PER_WIDE_INT
11131 && (nonzero_bits (XEXP (op0
, 0), mode
)
11132 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11133 && (((unsigned HOST_WIDE_INT
) const_op
11134 + (GET_CODE (op0
) != LSHIFTRT
11135 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11138 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11140 /* If the shift was logical, then we must make the condition
11142 if (GET_CODE (op0
) == LSHIFTRT
)
11143 code
= unsigned_condition (code
);
11145 const_op
<<= INTVAL (XEXP (op0
, 1));
11146 op1
= GEN_INT (const_op
);
11147 op0
= XEXP (op0
, 0);
11151 /* If we are using this shift to extract just the sign bit, we
11152 can replace this with an LT or GE comparison. */
11154 && (equality_comparison_p
|| sign_bit_comparison_p
)
11155 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11156 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11159 op0
= XEXP (op0
, 0);
11160 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11172 /* Now make any compound operations involved in this comparison. Then,
11173 check for an outmost SUBREG on OP0 that is not doing anything or is
11174 paradoxical. The latter transformation must only be performed when
11175 it is known that the "extra" bits will be the same in op0 and op1 or
11176 that they don't matter. There are three cases to consider:
11178 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11179 care bits and we can assume they have any convenient value. So
11180 making the transformation is safe.
11182 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11183 In this case the upper bits of op0 are undefined. We should not make
11184 the simplification in that case as we do not know the contents of
11187 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11188 NIL. In that case we know those bits are zeros or ones. We must
11189 also be sure that they are the same as the upper bits of op1.
11191 We can never remove a SUBREG for a non-equality comparison because
11192 the sign bit is in a different place in the underlying object. */
11194 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11195 op1
= make_compound_operation (op1
, SET
);
11197 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11198 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11199 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11200 && (code
== NE
|| code
== EQ
))
11202 if (GET_MODE_SIZE (GET_MODE (op0
))
11203 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11205 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11207 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11209 op0
= SUBREG_REG (op0
);
11210 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11213 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11214 <= HOST_BITS_PER_WIDE_INT
)
11215 && (nonzero_bits (SUBREG_REG (op0
),
11216 GET_MODE (SUBREG_REG (op0
)))
11217 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11219 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11221 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11222 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11223 op0
= SUBREG_REG (op0
), op1
= tem
;
11227 /* We now do the opposite procedure: Some machines don't have compare
11228 insns in all modes. If OP0's mode is an integer mode smaller than a
11229 word and we can't do a compare in that mode, see if there is a larger
11230 mode for which we can do the compare. There are a number of cases in
11231 which we can use the wider mode. */
11233 mode
= GET_MODE (op0
);
11234 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11235 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11236 && ! have_insn_for (COMPARE
, mode
))
11237 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11239 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11240 tmode
= GET_MODE_WIDER_MODE (tmode
))
11241 if (have_insn_for (COMPARE
, tmode
))
11245 /* If the only nonzero bits in OP0 and OP1 are those in the
11246 narrower mode and this is an equality or unsigned comparison,
11247 we can use the wider mode. Similarly for sign-extended
11248 values, in which case it is true for all comparisons. */
11249 zero_extended
= ((code
== EQ
|| code
== NE
11250 || code
== GEU
|| code
== GTU
11251 || code
== LEU
|| code
== LTU
)
11252 && (nonzero_bits (op0
, tmode
)
11253 & ~GET_MODE_MASK (mode
)) == 0
11254 && ((GET_CODE (op1
) == CONST_INT
11255 || (nonzero_bits (op1
, tmode
)
11256 & ~GET_MODE_MASK (mode
)) == 0)));
11259 || ((num_sign_bit_copies (op0
, tmode
)
11260 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11261 - GET_MODE_BITSIZE (mode
)))
11262 && (num_sign_bit_copies (op1
, tmode
)
11263 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11264 - GET_MODE_BITSIZE (mode
)))))
11266 /* If OP0 is an AND and we don't have an AND in MODE either,
11267 make a new AND in the proper mode. */
11268 if (GET_CODE (op0
) == AND
11269 && !have_insn_for (AND
, mode
))
11270 op0
= gen_binary (AND
, tmode
,
11271 gen_lowpart (tmode
,
11273 gen_lowpart (tmode
,
11276 op0
= gen_lowpart (tmode
, op0
);
11277 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11278 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11279 op1
= gen_lowpart (tmode
, op1
);
11283 /* If this is a test for negative, we can make an explicit
11284 test of the sign bit. */
11286 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11287 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11289 op0
= gen_binary (AND
, tmode
,
11290 gen_lowpart (tmode
, op0
),
11291 GEN_INT ((HOST_WIDE_INT
) 1
11292 << (GET_MODE_BITSIZE (mode
) - 1)));
11293 code
= (code
== LT
) ? NE
: EQ
;
11298 #ifdef CANONICALIZE_COMPARISON
11299 /* If this machine only supports a subset of valid comparisons, see if we
11300 can convert an unsupported one into a supported one. */
11301 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11310 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11311 searching backward. */
11312 static enum rtx_code
11313 combine_reversed_comparison_code (rtx exp
)
11315 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11318 if (code1
!= UNKNOWN
11319 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11321 /* Otherwise try and find where the condition codes were last set and
11323 x
= get_last_value (XEXP (exp
, 0));
11324 if (!x
|| GET_CODE (x
) != COMPARE
)
11326 return reversed_comparison_code_parts (GET_CODE (exp
),
11327 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11330 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11331 Return NULL_RTX in case we fail to do the reversal. */
11333 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11335 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11336 if (reversed_code
== UNKNOWN
)
11339 return gen_binary (reversed_code
, mode
, op0
, op1
);
11342 /* Utility function for following routine. Called when X is part of a value
11343 being stored into last_set_value. Sets last_set_table_tick
11344 for each register mentioned. Similar to mention_regs in cse.c */
11347 update_table_tick (rtx x
)
11349 enum rtx_code code
= GET_CODE (x
);
11350 const char *fmt
= GET_RTX_FORMAT (code
);
11355 unsigned int regno
= REGNO (x
);
11356 unsigned int endregno
11357 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11358 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11361 for (r
= regno
; r
< endregno
; r
++)
11362 reg_stat
[r
].last_set_table_tick
= label_tick
;
11367 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11368 /* Note that we can't have an "E" in values stored; see
11369 get_last_value_validate. */
11372 /* Check for identical subexpressions. If x contains
11373 identical subexpression we only have to traverse one of
11375 if (i
== 0 && ARITHMETIC_P (x
))
11377 /* Note that at this point x1 has already been
11379 rtx x0
= XEXP (x
, 0);
11380 rtx x1
= XEXP (x
, 1);
11382 /* If x0 and x1 are identical then there is no need to
11387 /* If x0 is identical to a subexpression of x1 then while
11388 processing x1, x0 has already been processed. Thus we
11389 are done with x. */
11390 if (ARITHMETIC_P (x1
)
11391 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11394 /* If x1 is identical to a subexpression of x0 then we
11395 still have to process the rest of x0. */
11396 if (ARITHMETIC_P (x0
)
11397 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11399 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11404 update_table_tick (XEXP (x
, i
));
11408 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11409 are saying that the register is clobbered and we no longer know its
11410 value. If INSN is zero, don't update reg_stat[].last_set; this is
11411 only permitted with VALUE also zero and is used to invalidate the
11415 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11417 unsigned int regno
= REGNO (reg
);
11418 unsigned int endregno
11419 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11420 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
11423 /* If VALUE contains REG and we have a previous value for REG, substitute
11424 the previous value. */
11425 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11429 /* Set things up so get_last_value is allowed to see anything set up to
11431 subst_low_cuid
= INSN_CUID (insn
);
11432 tem
= get_last_value (reg
);
11434 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11435 it isn't going to be useful and will take a lot of time to process,
11436 so just use the CLOBBER. */
11440 if (ARITHMETIC_P (tem
)
11441 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11442 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11443 tem
= XEXP (tem
, 0);
11445 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11449 /* For each register modified, show we don't know its value, that
11450 we don't know about its bitwise content, that its value has been
11451 updated, and that we don't know the location of the death of the
11453 for (i
= regno
; i
< endregno
; i
++)
11456 reg_stat
[i
].last_set
= insn
;
11458 reg_stat
[i
].last_set_value
= 0;
11459 reg_stat
[i
].last_set_mode
= 0;
11460 reg_stat
[i
].last_set_nonzero_bits
= 0;
11461 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11462 reg_stat
[i
].last_death
= 0;
11465 /* Mark registers that are being referenced in this value. */
11467 update_table_tick (value
);
11469 /* Now update the status of each register being set.
11470 If someone is using this register in this block, set this register
11471 to invalid since we will get confused between the two lives in this
11472 basic block. This makes using this register always invalid. In cse, we
11473 scan the table to invalidate all entries using this register, but this
11474 is too much work for us. */
11476 for (i
= regno
; i
< endregno
; i
++)
11478 reg_stat
[i
].last_set_label
= label_tick
;
11479 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
11480 reg_stat
[i
].last_set_invalid
= 1;
11482 reg_stat
[i
].last_set_invalid
= 0;
11485 /* The value being assigned might refer to X (like in "x++;"). In that
11486 case, we must replace it with (clobber (const_int 0)) to prevent
11488 if (value
&& ! get_last_value_validate (&value
, insn
,
11489 reg_stat
[regno
].last_set_label
, 0))
11491 value
= copy_rtx (value
);
11492 if (! get_last_value_validate (&value
, insn
,
11493 reg_stat
[regno
].last_set_label
, 1))
11497 /* For the main register being modified, update the value, the mode, the
11498 nonzero bits, and the number of sign bit copies. */
11500 reg_stat
[regno
].last_set_value
= value
;
11504 enum machine_mode mode
= GET_MODE (reg
);
11505 subst_low_cuid
= INSN_CUID (insn
);
11506 reg_stat
[regno
].last_set_mode
= mode
;
11507 if (GET_MODE_CLASS (mode
) == MODE_INT
11508 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11509 mode
= nonzero_bits_mode
;
11510 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11511 reg_stat
[regno
].last_set_sign_bit_copies
11512 = num_sign_bit_copies (value
, GET_MODE (reg
));
11516 /* Called via note_stores from record_dead_and_set_regs to handle one
11517 SET or CLOBBER in an insn. DATA is the instruction in which the
11518 set is occurring. */
11521 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11523 rtx record_dead_insn
= (rtx
) data
;
11525 if (GET_CODE (dest
) == SUBREG
)
11526 dest
= SUBREG_REG (dest
);
11528 if (GET_CODE (dest
) == REG
)
11530 /* If we are setting the whole register, we know its value. Otherwise
11531 show that we don't know the value. We can handle SUBREG in
11533 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11534 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11535 else if (GET_CODE (setter
) == SET
11536 && GET_CODE (SET_DEST (setter
)) == SUBREG
11537 && SUBREG_REG (SET_DEST (setter
)) == dest
11538 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11539 && subreg_lowpart_p (SET_DEST (setter
)))
11540 record_value_for_reg (dest
, record_dead_insn
,
11541 gen_lowpart (GET_MODE (dest
),
11542 SET_SRC (setter
)));
11544 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11546 else if (GET_CODE (dest
) == MEM
11547 /* Ignore pushes, they clobber nothing. */
11548 && ! push_operand (dest
, GET_MODE (dest
)))
11549 mem_last_set
= INSN_CUID (record_dead_insn
);
11552 /* Update the records of when each REG was most recently set or killed
11553 for the things done by INSN. This is the last thing done in processing
11554 INSN in the combiner loop.
11556 We update reg_stat[], in particular fields last_set, last_set_value,
11557 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11558 last_death, and also the similar information mem_last_set (which insn
11559 most recently modified memory) and last_call_cuid (which insn was the
11560 most recent subroutine call). */
11563 record_dead_and_set_regs (rtx insn
)
11568 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11570 if (REG_NOTE_KIND (link
) == REG_DEAD
11571 && GET_CODE (XEXP (link
, 0)) == REG
)
11573 unsigned int regno
= REGNO (XEXP (link
, 0));
11574 unsigned int endregno
11575 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11576 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11579 for (i
= regno
; i
< endregno
; i
++)
11580 reg_stat
[i
].last_death
= insn
;
11582 else if (REG_NOTE_KIND (link
) == REG_INC
)
11583 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11586 if (GET_CODE (insn
) == CALL_INSN
)
11588 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11589 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11591 reg_stat
[i
].last_set_value
= 0;
11592 reg_stat
[i
].last_set_mode
= 0;
11593 reg_stat
[i
].last_set_nonzero_bits
= 0;
11594 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11595 reg_stat
[i
].last_death
= 0;
11598 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11600 /* Don't bother recording what this insn does. It might set the
11601 return value register, but we can't combine into a call
11602 pattern anyway, so there's no point trying (and it may cause
11603 a crash, if e.g. we wind up asking for last_set_value of a
11604 SUBREG of the return value register). */
11608 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11611 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11612 register present in the SUBREG, so for each such SUBREG go back and
11613 adjust nonzero and sign bit information of the registers that are
11614 known to have some zero/sign bits set.
11616 This is needed because when combine blows the SUBREGs away, the
11617 information on zero/sign bits is lost and further combines can be
11618 missed because of that. */
11621 record_promoted_value (rtx insn
, rtx subreg
)
11624 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11625 enum machine_mode mode
= GET_MODE (subreg
);
11627 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11630 for (links
= LOG_LINKS (insn
); links
;)
11632 insn
= XEXP (links
, 0);
11633 set
= single_set (insn
);
11635 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11636 || REGNO (SET_DEST (set
)) != regno
11637 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11639 links
= XEXP (links
, 1);
11643 if (reg_stat
[regno
].last_set
== insn
)
11645 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11646 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11649 if (GET_CODE (SET_SRC (set
)) == REG
)
11651 regno
= REGNO (SET_SRC (set
));
11652 links
= LOG_LINKS (insn
);
11659 /* Scan X for promoted SUBREGs. For each one found,
11660 note what it implies to the registers used in it. */
11663 check_promoted_subreg (rtx insn
, rtx x
)
11665 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11666 && GET_CODE (SUBREG_REG (x
)) == REG
)
11667 record_promoted_value (insn
, x
);
11670 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11673 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11677 check_promoted_subreg (insn
, XEXP (x
, i
));
11681 if (XVEC (x
, i
) != 0)
11682 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11683 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11689 /* Utility routine for the following function. Verify that all the registers
11690 mentioned in *LOC are valid when *LOC was part of a value set when
11691 label_tick == TICK. Return 0 if some are not.
11693 If REPLACE is nonzero, replace the invalid reference with
11694 (clobber (const_int 0)) and return 1. This replacement is useful because
11695 we often can get useful information about the form of a value (e.g., if
11696 it was produced by a shift that always produces -1 or 0) even though
11697 we don't know exactly what registers it was produced from. */
11700 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11703 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11704 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11707 if (GET_CODE (x
) == REG
)
11709 unsigned int regno
= REGNO (x
);
11710 unsigned int endregno
11711 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11712 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11715 for (j
= regno
; j
< endregno
; j
++)
11716 if (reg_stat
[j
].last_set_invalid
11717 /* If this is a pseudo-register that was only set once and not
11718 live at the beginning of the function, it is always valid. */
11719 || (! (regno
>= FIRST_PSEUDO_REGISTER
11720 && REG_N_SETS (regno
) == 1
11721 && (! REGNO_REG_SET_P
11722 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11723 && reg_stat
[j
].last_set_label
> tick
))
11726 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11732 /* If this is a memory reference, make sure that there were
11733 no stores after it that might have clobbered the value. We don't
11734 have alias info, so we assume any store invalidates it. */
11735 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11736 && INSN_CUID (insn
) <= mem_last_set
)
11739 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11743 for (i
= 0; i
< len
; i
++)
11747 /* Check for identical subexpressions. If x contains
11748 identical subexpression we only have to traverse one of
11750 if (i
== 1 && ARITHMETIC_P (x
))
11752 /* Note that at this point x0 has already been checked
11753 and found valid. */
11754 rtx x0
= XEXP (x
, 0);
11755 rtx x1
= XEXP (x
, 1);
11757 /* If x0 and x1 are identical then x is also valid. */
11761 /* If x1 is identical to a subexpression of x0 then
11762 while checking x0, x1 has already been checked. Thus
11763 it is valid and so as x. */
11764 if (ARITHMETIC_P (x0
)
11765 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11768 /* If x0 is identical to a subexpression of x1 then x is
11769 valid iff the rest of x1 is valid. */
11770 if (ARITHMETIC_P (x1
)
11771 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11773 get_last_value_validate (&XEXP (x1
,
11774 x0
== XEXP (x1
, 0) ? 1 : 0),
11775 insn
, tick
, replace
);
11778 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11782 /* Don't bother with these. They shouldn't occur anyway. */
11783 else if (fmt
[i
] == 'E')
11787 /* If we haven't found a reason for it to be invalid, it is valid. */
11791 /* Get the last value assigned to X, if known. Some registers
11792 in the value may be replaced with (clobber (const_int 0)) if their value
11793 is known longer known reliably. */
11796 get_last_value (rtx x
)
11798 unsigned int regno
;
11801 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11802 then convert it to the desired mode. If this is a paradoxical SUBREG,
11803 we cannot predict what values the "extra" bits might have. */
11804 if (GET_CODE (x
) == SUBREG
11805 && subreg_lowpart_p (x
)
11806 && (GET_MODE_SIZE (GET_MODE (x
))
11807 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11808 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11809 return gen_lowpart (GET_MODE (x
), value
);
11811 if (GET_CODE (x
) != REG
)
11815 value
= reg_stat
[regno
].last_set_value
;
11817 /* If we don't have a value, or if it isn't for this basic block and
11818 it's either a hard register, set more than once, or it's a live
11819 at the beginning of the function, return 0.
11821 Because if it's not live at the beginning of the function then the reg
11822 is always set before being used (is never used without being set).
11823 And, if it's set only once, and it's always set before use, then all
11824 uses must have the same last value, even if it's not from this basic
11828 || (reg_stat
[regno
].last_set_label
!= label_tick
11829 && (regno
< FIRST_PSEUDO_REGISTER
11830 || REG_N_SETS (regno
) != 1
11831 || (REGNO_REG_SET_P
11832 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11835 /* If the value was set in a later insn than the ones we are processing,
11836 we can't use it even if the register was only set once. */
11837 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11840 /* If the value has all its registers valid, return it. */
11841 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11842 reg_stat
[regno
].last_set_label
, 0))
11845 /* Otherwise, make a copy and replace any invalid register with
11846 (clobber (const_int 0)). If that fails for some reason, return 0. */
11848 value
= copy_rtx (value
);
11849 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11850 reg_stat
[regno
].last_set_label
, 1))
11856 /* Return nonzero if expression X refers to a REG or to memory
11857 that is set in an instruction more recent than FROM_CUID. */
11860 use_crosses_set_p (rtx x
, int from_cuid
)
11864 enum rtx_code code
= GET_CODE (x
);
11868 unsigned int regno
= REGNO (x
);
11869 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11870 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11872 #ifdef PUSH_ROUNDING
11873 /* Don't allow uses of the stack pointer to be moved,
11874 because we don't know whether the move crosses a push insn. */
11875 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11878 for (; regno
< endreg
; regno
++)
11879 if (reg_stat
[regno
].last_set
11880 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11885 if (code
== MEM
&& mem_last_set
> from_cuid
)
11888 fmt
= GET_RTX_FORMAT (code
);
11890 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11895 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11896 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11899 else if (fmt
[i
] == 'e'
11900 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11906 /* Define three variables used for communication between the following
11909 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11910 static int reg_dead_flag
;
11912 /* Function called via note_stores from reg_dead_at_p.
11914 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11915 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11918 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11920 unsigned int regno
, endregno
;
11922 if (GET_CODE (dest
) != REG
)
11925 regno
= REGNO (dest
);
11926 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11927 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11929 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11930 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11933 /* Return nonzero if REG is known to be dead at INSN.
11935 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11936 referencing REG, it is dead. If we hit a SET referencing REG, it is
11937 live. Otherwise, see if it is live or dead at the start of the basic
11938 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11939 must be assumed to be always live. */
11942 reg_dead_at_p (rtx reg
, rtx insn
)
11947 /* Set variables for reg_dead_at_p_1. */
11948 reg_dead_regno
= REGNO (reg
);
11949 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11950 ? hard_regno_nregs
[reg_dead_regno
]
11956 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11957 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11959 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11960 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11964 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11965 beginning of function. */
11966 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11967 insn
= prev_nonnote_insn (insn
))
11969 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11971 return reg_dead_flag
== 1 ? 1 : 0;
11973 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11977 /* Get the basic block that we were in. */
11979 block
= ENTRY_BLOCK_PTR
->next_bb
;
11982 FOR_EACH_BB (block
)
11983 if (insn
== BB_HEAD (block
))
11986 if (block
== EXIT_BLOCK_PTR
)
11990 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11991 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11997 /* Note hard registers in X that are used. This code is similar to
11998 that in flow.c, but much simpler since we don't care about pseudos. */
12001 mark_used_regs_combine (rtx x
)
12003 RTX_CODE code
= GET_CODE (x
);
12004 unsigned int regno
;
12017 case ADDR_DIFF_VEC
:
12020 /* CC0 must die in the insn after it is set, so we don't need to take
12021 special note of it here. */
12027 /* If we are clobbering a MEM, mark any hard registers inside the
12028 address as used. */
12029 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12030 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12035 /* A hard reg in a wide mode may really be multiple registers.
12036 If so, mark all of them just like the first. */
12037 if (regno
< FIRST_PSEUDO_REGISTER
)
12039 unsigned int endregno
, r
;
12041 /* None of this applies to the stack, frame or arg pointers. */
12042 if (regno
== STACK_POINTER_REGNUM
12043 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12044 || regno
== HARD_FRAME_POINTER_REGNUM
12046 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12047 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12049 || regno
== FRAME_POINTER_REGNUM
)
12052 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12053 for (r
= regno
; r
< endregno
; r
++)
12054 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12060 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12062 rtx testreg
= SET_DEST (x
);
12064 while (GET_CODE (testreg
) == SUBREG
12065 || GET_CODE (testreg
) == ZERO_EXTRACT
12066 || GET_CODE (testreg
) == SIGN_EXTRACT
12067 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12068 testreg
= XEXP (testreg
, 0);
12070 if (GET_CODE (testreg
) == MEM
)
12071 mark_used_regs_combine (XEXP (testreg
, 0));
12073 mark_used_regs_combine (SET_SRC (x
));
12081 /* Recursively scan the operands of this expression. */
12084 const char *fmt
= GET_RTX_FORMAT (code
);
12086 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12089 mark_used_regs_combine (XEXP (x
, i
));
12090 else if (fmt
[i
] == 'E')
12094 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12095 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12101 /* Remove register number REGNO from the dead registers list of INSN.
12103 Return the note used to record the death, if there was one. */
12106 remove_death (unsigned int regno
, rtx insn
)
12108 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12112 REG_N_DEATHS (regno
)--;
12113 remove_note (insn
, note
);
12119 /* For each register (hardware or pseudo) used within expression X, if its
12120 death is in an instruction with cuid between FROM_CUID (inclusive) and
12121 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12122 list headed by PNOTES.
12124 That said, don't move registers killed by maybe_kill_insn.
12126 This is done when X is being merged by combination into TO_INSN. These
12127 notes will then be distributed as needed. */
12130 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12135 enum rtx_code code
= GET_CODE (x
);
12139 unsigned int regno
= REGNO (x
);
12140 rtx where_dead
= reg_stat
[regno
].last_death
;
12141 rtx before_dead
, after_dead
;
12143 /* Don't move the register if it gets killed in between from and to. */
12144 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12145 && ! reg_referenced_p (x
, maybe_kill_insn
))
12148 /* WHERE_DEAD could be a USE insn made by combine, so first we
12149 make sure that we have insns with valid INSN_CUID values. */
12150 before_dead
= where_dead
;
12151 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12152 before_dead
= PREV_INSN (before_dead
);
12154 after_dead
= where_dead
;
12155 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12156 after_dead
= NEXT_INSN (after_dead
);
12158 if (before_dead
&& after_dead
12159 && INSN_CUID (before_dead
) >= from_cuid
12160 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12161 || (where_dead
!= after_dead
12162 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12164 rtx note
= remove_death (regno
, where_dead
);
12166 /* It is possible for the call above to return 0. This can occur
12167 when last_death points to I2 or I1 that we combined with.
12168 In that case make a new note.
12170 We must also check for the case where X is a hard register
12171 and NOTE is a death note for a range of hard registers
12172 including X. In that case, we must put REG_DEAD notes for
12173 the remaining registers in place of NOTE. */
12175 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12176 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12177 > GET_MODE_SIZE (GET_MODE (x
))))
12179 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12180 unsigned int deadend
12181 = (deadregno
+ hard_regno_nregs
[deadregno
]
12182 [GET_MODE (XEXP (note
, 0))]);
12183 unsigned int ourend
12184 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12187 for (i
= deadregno
; i
< deadend
; i
++)
12188 if (i
< regno
|| i
>= ourend
)
12189 REG_NOTES (where_dead
)
12190 = gen_rtx_EXPR_LIST (REG_DEAD
,
12192 REG_NOTES (where_dead
));
12195 /* If we didn't find any note, or if we found a REG_DEAD note that
12196 covers only part of the given reg, and we have a multi-reg hard
12197 register, then to be safe we must check for REG_DEAD notes
12198 for each register other than the first. They could have
12199 their own REG_DEAD notes lying around. */
12200 else if ((note
== 0
12202 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12203 < GET_MODE_SIZE (GET_MODE (x
)))))
12204 && regno
< FIRST_PSEUDO_REGISTER
12205 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12207 unsigned int ourend
12208 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12209 unsigned int i
, offset
;
12213 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12217 for (i
= regno
+ offset
; i
< ourend
; i
++)
12218 move_deaths (regno_reg_rtx
[i
],
12219 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12222 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12224 XEXP (note
, 1) = *pnotes
;
12228 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12230 REG_N_DEATHS (regno
)++;
12236 else if (GET_CODE (x
) == SET
)
12238 rtx dest
= SET_DEST (x
);
12240 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12242 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12243 that accesses one word of a multi-word item, some
12244 piece of everything register in the expression is used by
12245 this insn, so remove any old death. */
12246 /* ??? So why do we test for equality of the sizes? */
12248 if (GET_CODE (dest
) == ZERO_EXTRACT
12249 || GET_CODE (dest
) == STRICT_LOW_PART
12250 || (GET_CODE (dest
) == SUBREG
12251 && (((GET_MODE_SIZE (GET_MODE (dest
))
12252 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12253 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12254 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12256 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12260 /* If this is some other SUBREG, we know it replaces the entire
12261 value, so use that as the destination. */
12262 if (GET_CODE (dest
) == SUBREG
)
12263 dest
= SUBREG_REG (dest
);
12265 /* If this is a MEM, adjust deaths of anything used in the address.
12266 For a REG (the only other possibility), the entire value is
12267 being replaced so the old value is not used in this insn. */
12269 if (GET_CODE (dest
) == MEM
)
12270 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12275 else if (GET_CODE (x
) == CLOBBER
)
12278 len
= GET_RTX_LENGTH (code
);
12279 fmt
= GET_RTX_FORMAT (code
);
12281 for (i
= 0; i
< len
; i
++)
12286 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12287 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12290 else if (fmt
[i
] == 'e')
12291 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12295 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12296 pattern of an insn. X must be a REG. */
12299 reg_bitfield_target_p (rtx x
, rtx body
)
12303 if (GET_CODE (body
) == SET
)
12305 rtx dest
= SET_DEST (body
);
12307 unsigned int regno
, tregno
, endregno
, endtregno
;
12309 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12310 target
= XEXP (dest
, 0);
12311 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12312 target
= SUBREG_REG (XEXP (dest
, 0));
12316 if (GET_CODE (target
) == SUBREG
)
12317 target
= SUBREG_REG (target
);
12319 if (GET_CODE (target
) != REG
)
12322 tregno
= REGNO (target
), regno
= REGNO (x
);
12323 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12324 return target
== x
;
12326 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
12327 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12329 return endregno
> tregno
&& regno
< endtregno
;
12332 else if (GET_CODE (body
) == PARALLEL
)
12333 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12334 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12340 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12341 as appropriate. I3 and I2 are the insns resulting from the combination
12342 insns including FROM (I2 may be zero).
12344 Each note in the list is either ignored or placed on some insns, depending
12345 on the type of note. */
12348 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12350 rtx note
, next_note
;
12353 for (note
= notes
; note
; note
= next_note
)
12355 rtx place
= 0, place2
= 0;
12357 /* If this NOTE references a pseudo register, ensure it references
12358 the latest copy of that register. */
12359 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12360 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12361 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12363 next_note
= XEXP (note
, 1);
12364 switch (REG_NOTE_KIND (note
))
12368 /* Doesn't matter much where we put this, as long as it's somewhere.
12369 It is preferable to keep these notes on branches, which is most
12370 likely to be i3. */
12374 case REG_VALUE_PROFILE
:
12375 /* Just get rid of this note, as it is unused later anyway. */
12378 case REG_VTABLE_REF
:
12379 /* ??? Should remain with *a particular* memory load. Given the
12380 nature of vtable data, the last insn seems relatively safe. */
12384 case REG_NON_LOCAL_GOTO
:
12385 if (GET_CODE (i3
) == JUMP_INSN
)
12387 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12393 case REG_EH_REGION
:
12394 /* These notes must remain with the call or trapping instruction. */
12395 if (GET_CODE (i3
) == CALL_INSN
)
12397 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12399 else if (flag_non_call_exceptions
)
12401 if (may_trap_p (i3
))
12403 else if (i2
&& may_trap_p (i2
))
12405 /* ??? Otherwise assume we've combined things such that we
12406 can now prove that the instructions can't trap. Drop the
12407 note in this case. */
12413 case REG_ALWAYS_RETURN
:
12416 /* These notes must remain with the call. It should not be
12417 possible for both I2 and I3 to be a call. */
12418 if (GET_CODE (i3
) == CALL_INSN
)
12420 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12427 /* Any clobbers for i3 may still exist, and so we must process
12428 REG_UNUSED notes from that insn.
12430 Any clobbers from i2 or i1 can only exist if they were added by
12431 recog_for_combine. In that case, recog_for_combine created the
12432 necessary REG_UNUSED notes. Trying to keep any original
12433 REG_UNUSED notes from these insns can cause incorrect output
12434 if it is for the same register as the original i3 dest.
12435 In that case, we will notice that the register is set in i3,
12436 and then add a REG_UNUSED note for the destination of i3, which
12437 is wrong. However, it is possible to have REG_UNUSED notes from
12438 i2 or i1 for register which were both used and clobbered, so
12439 we keep notes from i2 or i1 if they will turn into REG_DEAD
12442 /* If this register is set or clobbered in I3, put the note there
12443 unless there is one already. */
12444 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12446 if (from_insn
!= i3
)
12449 if (! (GET_CODE (XEXP (note
, 0)) == REG
12450 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12451 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12454 /* Otherwise, if this register is used by I3, then this register
12455 now dies here, so we must put a REG_DEAD note here unless there
12457 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12458 && ! (GET_CODE (XEXP (note
, 0)) == REG
12459 ? find_regno_note (i3
, REG_DEAD
,
12460 REGNO (XEXP (note
, 0)))
12461 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12463 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12471 /* These notes say something about results of an insn. We can
12472 only support them if they used to be on I3 in which case they
12473 remain on I3. Otherwise they are ignored.
12475 If the note refers to an expression that is not a constant, we
12476 must also ignore the note since we cannot tell whether the
12477 equivalence is still true. It might be possible to do
12478 slightly better than this (we only have a problem if I2DEST
12479 or I1DEST is present in the expression), but it doesn't
12480 seem worth the trouble. */
12482 if (from_insn
== i3
12483 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12488 case REG_NO_CONFLICT
:
12489 /* These notes say something about how a register is used. They must
12490 be present on any use of the register in I2 or I3. */
12491 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12494 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12504 /* This can show up in several ways -- either directly in the
12505 pattern, or hidden off in the constant pool with (or without?)
12506 a REG_EQUAL note. */
12507 /* ??? Ignore the without-reg_equal-note problem for now. */
12508 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12509 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12510 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12511 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12515 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12516 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12517 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12518 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12526 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12527 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12528 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12530 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12532 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12533 LABEL_NUSES (JUMP_LABEL (place
))--;
12536 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12538 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12540 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12541 LABEL_NUSES (JUMP_LABEL (place2
))--;
12547 /* This note says something about the value of a register prior
12548 to the execution of an insn. It is too much trouble to see
12549 if the note is still correct in all situations. It is better
12550 to simply delete it. */
12554 /* If the insn previously containing this note still exists,
12555 put it back where it was. Otherwise move it to the previous
12556 insn. Adjust the corresponding REG_LIBCALL note. */
12557 if (GET_CODE (from_insn
) != NOTE
)
12561 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12562 place
= prev_real_insn (from_insn
);
12564 XEXP (tem
, 0) = place
;
12565 /* If we're deleting the last remaining instruction of a
12566 libcall sequence, don't add the notes. */
12567 else if (XEXP (note
, 0) == from_insn
)
12573 /* This is handled similarly to REG_RETVAL. */
12574 if (GET_CODE (from_insn
) != NOTE
)
12578 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12579 place
= next_real_insn (from_insn
);
12581 XEXP (tem
, 0) = place
;
12582 /* If we're deleting the last remaining instruction of a
12583 libcall sequence, don't add the notes. */
12584 else if (XEXP (note
, 0) == from_insn
)
12590 /* If the register is used as an input in I3, it dies there.
12591 Similarly for I2, if it is nonzero and adjacent to I3.
12593 If the register is not used as an input in either I3 or I2
12594 and it is not one of the registers we were supposed to eliminate,
12595 there are two possibilities. We might have a non-adjacent I2
12596 or we might have somehow eliminated an additional register
12597 from a computation. For example, we might have had A & B where
12598 we discover that B will always be zero. In this case we will
12599 eliminate the reference to A.
12601 In both cases, we must search to see if we can find a previous
12602 use of A and put the death note there. */
12605 && GET_CODE (from_insn
) == CALL_INSN
12606 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12608 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12610 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12611 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12616 basic_block bb
= this_basic_block
;
12618 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12620 if (! INSN_P (tem
))
12622 if (tem
== BB_HEAD (bb
))
12627 /* If the register is being set at TEM, see if that is all
12628 TEM is doing. If so, delete TEM. Otherwise, make this
12629 into a REG_UNUSED note instead. */
12630 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12632 rtx set
= single_set (tem
);
12633 rtx inner_dest
= 0;
12635 rtx cc0_setter
= NULL_RTX
;
12639 for (inner_dest
= SET_DEST (set
);
12640 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12641 || GET_CODE (inner_dest
) == SUBREG
12642 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12643 inner_dest
= XEXP (inner_dest
, 0))
12646 /* Verify that it was the set, and not a clobber that
12647 modified the register.
12649 CC0 targets must be careful to maintain setter/user
12650 pairs. If we cannot delete the setter due to side
12651 effects, mark the user with an UNUSED note instead
12654 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12655 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12657 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12658 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12659 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12663 /* Move the notes and links of TEM elsewhere.
12664 This might delete other dead insns recursively.
12665 First set the pattern to something that won't use
12667 rtx old_notes
= REG_NOTES (tem
);
12669 PATTERN (tem
) = pc_rtx
;
12670 REG_NOTES (tem
) = NULL
;
12672 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12673 distribute_links (LOG_LINKS (tem
));
12675 PUT_CODE (tem
, NOTE
);
12676 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12677 NOTE_SOURCE_FILE (tem
) = 0;
12680 /* Delete the setter too. */
12683 PATTERN (cc0_setter
) = pc_rtx
;
12684 old_notes
= REG_NOTES (cc0_setter
);
12685 REG_NOTES (cc0_setter
) = NULL
;
12687 distribute_notes (old_notes
, cc0_setter
,
12688 cc0_setter
, NULL_RTX
);
12689 distribute_links (LOG_LINKS (cc0_setter
));
12691 PUT_CODE (cc0_setter
, NOTE
);
12692 NOTE_LINE_NUMBER (cc0_setter
)
12693 = NOTE_INSN_DELETED
;
12694 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12700 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12702 /* If there isn't already a REG_UNUSED note, put one
12703 here. Do not place a REG_DEAD note, even if
12704 the register is also used here; that would not
12705 match the algorithm used in lifetime analysis
12706 and can cause the consistency check in the
12707 scheduler to fail. */
12708 if (! find_regno_note (tem
, REG_UNUSED
,
12709 REGNO (XEXP (note
, 0))))
12714 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12715 || (GET_CODE (tem
) == CALL_INSN
12716 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12720 /* If we are doing a 3->2 combination, and we have a
12721 register which formerly died in i3 and was not used
12722 by i2, which now no longer dies in i3 and is used in
12723 i2 but does not die in i2, and place is between i2
12724 and i3, then we may need to move a link from place to
12726 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12727 && INSN_CUID (place
) > INSN_CUID (i2
)
12729 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12730 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12732 rtx links
= LOG_LINKS (place
);
12733 LOG_LINKS (place
) = 0;
12734 distribute_links (links
);
12739 if (tem
== BB_HEAD (bb
))
12743 /* We haven't found an insn for the death note and it
12744 is still a REG_DEAD note, but we have hit the beginning
12745 of the block. If the existing life info says the reg
12746 was dead, there's nothing left to do. Otherwise, we'll
12747 need to do a global life update after combine. */
12748 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12749 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12750 REGNO (XEXP (note
, 0))))
12751 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12754 /* If the register is set or already dead at PLACE, we needn't do
12755 anything with this note if it is still a REG_DEAD note.
12756 We can here if it is set at all, not if is it totally replace,
12757 which is what `dead_or_set_p' checks, so also check for it being
12760 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12762 unsigned int regno
= REGNO (XEXP (note
, 0));
12764 /* Similarly, if the instruction on which we want to place
12765 the note is a noop, we'll need do a global live update
12766 after we remove them in delete_noop_moves. */
12767 if (noop_move_p (place
))
12768 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12770 if (dead_or_set_p (place
, XEXP (note
, 0))
12771 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12773 /* Unless the register previously died in PLACE, clear
12774 last_death. [I no longer understand why this is
12776 if (reg_stat
[regno
].last_death
!= place
)
12777 reg_stat
[regno
].last_death
= 0;
12781 reg_stat
[regno
].last_death
= place
;
12783 /* If this is a death note for a hard reg that is occupying
12784 multiple registers, ensure that we are still using all
12785 parts of the object. If we find a piece of the object
12786 that is unused, we must arrange for an appropriate REG_DEAD
12787 note to be added for it. However, we can't just emit a USE
12788 and tag the note to it, since the register might actually
12789 be dead; so we recourse, and the recursive call then finds
12790 the previous insn that used this register. */
12792 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12793 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12795 unsigned int endregno
12796 = regno
+ hard_regno_nregs
[regno
]
12797 [GET_MODE (XEXP (note
, 0))];
12801 for (i
= regno
; i
< endregno
; i
++)
12802 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12803 && ! find_regno_fusage (place
, USE
, i
))
12804 || dead_or_set_regno_p (place
, i
))
12809 /* Put only REG_DEAD notes for pieces that are
12810 not already dead or set. */
12812 for (i
= regno
; i
< endregno
;
12813 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12815 rtx piece
= regno_reg_rtx
[i
];
12816 basic_block bb
= this_basic_block
;
12818 if (! dead_or_set_p (place
, piece
)
12819 && ! reg_bitfield_target_p (piece
,
12823 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12825 distribute_notes (new_note
, place
, place
,
12828 else if (! refers_to_regno_p (i
, i
+ 1,
12829 PATTERN (place
), 0)
12830 && ! find_regno_fusage (place
, USE
, i
))
12831 for (tem
= PREV_INSN (place
); ;
12832 tem
= PREV_INSN (tem
))
12834 if (! INSN_P (tem
))
12836 if (tem
== BB_HEAD (bb
))
12838 SET_BIT (refresh_blocks
,
12839 this_basic_block
->index
);
12844 if (dead_or_set_p (tem
, piece
)
12845 || reg_bitfield_target_p (piece
,
12849 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12864 /* Any other notes should not be present at this point in the
12871 XEXP (note
, 1) = REG_NOTES (place
);
12872 REG_NOTES (place
) = note
;
12874 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12875 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12876 && GET_CODE (XEXP (note
, 0)) == REG
)
12877 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12881 if ((REG_NOTE_KIND (note
) == REG_DEAD
12882 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12883 && GET_CODE (XEXP (note
, 0)) == REG
)
12884 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12886 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12887 REG_NOTE_KIND (note
),
12889 REG_NOTES (place2
));
12894 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12895 I3, I2, and I1 to new locations. This is also called to add a link
12896 pointing at I3 when I3's destination is changed. */
12899 distribute_links (rtx links
)
12901 rtx link
, next_link
;
12903 for (link
= links
; link
; link
= next_link
)
12909 next_link
= XEXP (link
, 1);
12911 /* If the insn that this link points to is a NOTE or isn't a single
12912 set, ignore it. In the latter case, it isn't clear what we
12913 can do other than ignore the link, since we can't tell which
12914 register it was for. Such links wouldn't be used by combine
12917 It is not possible for the destination of the target of the link to
12918 have been changed by combine. The only potential of this is if we
12919 replace I3, I2, and I1 by I3 and I2. But in that case the
12920 destination of I2 also remains unchanged. */
12922 if (GET_CODE (XEXP (link
, 0)) == NOTE
12923 || (set
= single_set (XEXP (link
, 0))) == 0)
12926 reg
= SET_DEST (set
);
12927 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12928 || GET_CODE (reg
) == SIGN_EXTRACT
12929 || GET_CODE (reg
) == STRICT_LOW_PART
)
12930 reg
= XEXP (reg
, 0);
12932 /* A LOG_LINK is defined as being placed on the first insn that uses
12933 a register and points to the insn that sets the register. Start
12934 searching at the next insn after the target of the link and stop
12935 when we reach a set of the register or the end of the basic block.
12937 Note that this correctly handles the link that used to point from
12938 I3 to I2. Also note that not much searching is typically done here
12939 since most links don't point very far away. */
12941 for (insn
= NEXT_INSN (XEXP (link
, 0));
12942 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12943 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12944 insn
= NEXT_INSN (insn
))
12945 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12947 if (reg_referenced_p (reg
, PATTERN (insn
)))
12951 else if (GET_CODE (insn
) == CALL_INSN
12952 && find_reg_fusage (insn
, USE
, reg
))
12957 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12960 /* If we found a place to put the link, place it there unless there
12961 is already a link to the same insn as LINK at that point. */
12967 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12968 if (XEXP (link2
, 0) == XEXP (link
, 0))
12973 XEXP (link
, 1) = LOG_LINKS (place
);
12974 LOG_LINKS (place
) = link
;
12976 /* Set added_links_insn to the earliest insn we added a
12978 if (added_links_insn
== 0
12979 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12980 added_links_insn
= place
;
12986 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12987 Check whether the expression pointer to by LOC is a register or
12988 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12989 Otherwise return zero. */
12992 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12997 && (GET_CODE (x
) == REG
|| GET_CODE (x
) == MEM
)
12998 && ! reg_mentioned_p (x
, (rtx
) expr
))
13003 /* Check for any register or memory mentioned in EQUIV that is not
13004 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13005 of EXPR where some registers may have been replaced by constants. */
13008 unmentioned_reg_p (rtx equiv
, rtx expr
)
13010 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13013 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13016 insn_cuid (rtx insn
)
13018 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13019 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13020 insn
= NEXT_INSN (insn
);
13022 if (INSN_UID (insn
) > max_uid_cuid
)
13025 return INSN_CUID (insn
);
13029 dump_combine_stats (FILE *file
)
13033 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13034 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13038 dump_combine_total_stats (FILE *file
)
13042 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13043 total_attempts
, total_merges
, total_extras
, total_successes
);