1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #ifndef SHIFT_COUNT_TRUNCATED
95 #define SHIFT_COUNT_TRUNCATED 0
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno
;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx
*reg_last_death
;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx
*reg_last_set
;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set
;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid
;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn
;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid
;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs
;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn
;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block
;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST (rtx
*, rtx
);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
346 static int cant_combine_insn_p (rtx
);
347 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
348 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
349 static int contains_muldiv (rtx
);
350 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
351 static void undo_all (void);
352 static void undo_commit (void);
353 static rtx
*find_split_point (rtx
*, rtx
);
354 static rtx
subst (rtx
, rtx
, rtx
, int, int);
355 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
356 static rtx
simplify_if_then_else (rtx
);
357 static rtx
simplify_set (rtx
);
358 static rtx
simplify_logical (rtx
, int);
359 static rtx
expand_compound_operation (rtx
);
360 static rtx
expand_field_assignment (rtx
);
361 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
362 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
363 static rtx
extract_left_shift (rtx
, int);
364 static rtx
make_compound_operation (rtx
, enum rtx_code
);
365 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
366 unsigned HOST_WIDE_INT
*);
367 static rtx
force_to_mode (rtx
, enum machine_mode
,
368 unsigned HOST_WIDE_INT
, rtx
, int);
369 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
370 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
371 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
372 static rtx
make_field_assignment (rtx
);
373 static rtx
apply_distributive_law (rtx
);
374 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
375 unsigned HOST_WIDE_INT
);
376 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
377 rtx
, enum machine_mode
,
378 unsigned HOST_WIDE_INT
);
379 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
381 unsigned HOST_WIDE_INT
);
382 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
385 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
386 enum machine_mode
, unsigned int);
387 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
388 HOST_WIDE_INT
, enum machine_mode
, int *);
389 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
391 static int recog_for_combine (rtx
*, rtx
, rtx
*);
392 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
393 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
394 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
395 static void update_table_tick (rtx
);
396 static void record_value_for_reg (rtx
, rtx
, rtx
);
397 static void check_promoted_subreg (rtx
, rtx
);
398 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
399 static void record_dead_and_set_regs (rtx
);
400 static int get_last_value_validate (rtx
*, rtx
, int, int);
401 static rtx
get_last_value (rtx
);
402 static int use_crosses_set_p (rtx
, int);
403 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
404 static int reg_dead_at_p (rtx
, rtx
);
405 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
406 static int reg_bitfield_target_p (rtx
, rtx
);
407 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
408 static void distribute_links (rtx
);
409 static void mark_used_regs_combine (rtx
);
410 static int insn_cuid (rtx
);
411 static void record_promoted_value (rtx
, rtx
);
412 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
413 static enum rtx_code
combine_reversed_comparison_code (rtx
);
415 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
416 insn. The substitution can be undone by undo_all. If INTO is already
417 set to NEWVAL, do not record this change. Because computing NEWVAL might
418 also call SUBST, we have to compute it before we put anything into
422 do_SUBST (rtx
*into
, rtx newval
)
427 if (oldval
== newval
)
430 /* We'd like to catch as many invalid transformations here as
431 possible. Unfortunately, there are way too many mode changes
432 that are perfectly valid, so we'd waste too much effort for
433 little gain doing the checks here. Focus on catching invalid
434 transformations involving integer constants. */
435 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
436 && GET_CODE (newval
) == CONST_INT
)
438 /* Sanity check that we're replacing oldval with a CONST_INT
439 that is a valid sign-extension for the original mode. */
440 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
444 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
445 CONST_INT is not valid, because after the replacement, the
446 original mode would be gone. Unfortunately, we can't tell
447 when do_SUBST is called to replace the operand thereof, so we
448 perform this test on oldval instead, checking whether an
449 invalid replacement took place before we got here. */
450 if ((GET_CODE (oldval
) == SUBREG
451 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
452 || (GET_CODE (oldval
) == ZERO_EXTEND
453 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
458 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
460 buf
= xmalloc (sizeof (struct undo
));
464 buf
->old_contents
.r
= oldval
;
467 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
470 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
472 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
473 for the value of a HOST_WIDE_INT value (including CONST_INT) is
477 do_SUBST_INT (int *into
, int newval
)
482 if (oldval
== newval
)
486 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
488 buf
= xmalloc (sizeof (struct undo
));
492 buf
->old_contents
.i
= oldval
;
495 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
498 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
500 /* Main entry point for combiner. F is the first insn of the function.
501 NREGS is the first unused pseudo-reg number.
503 Return nonzero if the combiner has turned an indirect jump
504 instruction into a direct jump. */
506 combine_instructions (rtx f
, unsigned int nregs
)
513 rtx links
, nextlinks
;
515 int new_direct_jump_p
= 0;
517 combine_attempts
= 0;
520 combine_successes
= 0;
522 combine_max_regno
= nregs
;
524 /* It is not safe to use ordinary gen_lowpart in combine.
525 See comments in gen_lowpart_for_combine. */
526 gen_lowpart
= gen_lowpart_for_combine
;
528 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
529 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
531 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
532 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
533 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
534 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
535 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
536 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
537 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
538 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
539 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
548 if (INSN_UID (insn
) > i
)
551 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
554 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid
= 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 setup_incoming_promotions ();
576 refresh_blocks
= sbitmap_alloc (last_basic_block
);
577 sbitmap_zero (refresh_blocks
);
579 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
581 uid_cuid
[INSN_UID (insn
)] = ++i
;
587 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
589 record_dead_and_set_regs (insn
);
592 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
593 if (REG_NOTE_KIND (links
) == REG_INC
)
594 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
599 if (GET_CODE (insn
) == CODE_LABEL
)
603 nonzero_sign_valid
= 1;
605 /* Now scan all the insns in forward order. */
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block
)
615 for (insn
= BB_HEAD (this_basic_block
);
616 insn
!= NEXT_INSN (BB_END (this_basic_block
));
617 insn
= next
? next
: NEXT_INSN (insn
))
621 if (GET_CODE (insn
) == CODE_LABEL
)
624 else if (INSN_P (insn
))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn
, PATTERN (insn
));
630 /* Try this insn with each insn it links back to. */
632 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
633 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 NULL_RTX
, &new_direct_jump_p
)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
641 rtx link
= XEXP (links
, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link
) == NOTE
)
648 for (nextlinks
= LOG_LINKS (link
);
650 nextlinks
= XEXP (nextlinks
, 1))
651 if ((next
= try_combine (insn
, link
,
653 &new_direct_jump_p
)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn
) == JUMP_INSN
666 && (prev
= prev_nonnote_insn (insn
)) != 0
667 && GET_CODE (prev
) == INSN
668 && sets_cc0_p (PATTERN (prev
)))
670 if ((next
= try_combine (insn
, prev
,
671 NULL_RTX
, &new_direct_jump_p
)) != 0)
674 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
675 nextlinks
= XEXP (nextlinks
, 1))
676 if ((next
= try_combine (insn
, prev
,
678 &new_direct_jump_p
)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn
) == INSN
684 && (prev
= prev_nonnote_insn (insn
)) != 0
685 && GET_CODE (prev
) == INSN
686 && sets_cc0_p (PATTERN (prev
))
687 && GET_CODE (PATTERN (insn
)) == SET
688 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
690 if ((next
= try_combine (insn
, prev
,
691 NULL_RTX
, &new_direct_jump_p
)) != 0)
694 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
695 nextlinks
= XEXP (nextlinks
, 1))
696 if ((next
= try_combine (insn
, prev
,
698 &new_direct_jump_p
)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
706 if (GET_CODE (XEXP (links
, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
708 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
709 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
710 && GET_CODE (prev
) == INSN
711 && sets_cc0_p (PATTERN (prev
))
712 && (next
= try_combine (insn
, XEXP (links
, 0),
713 prev
, &new_direct_jump_p
)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
720 for (nextlinks
= XEXP (links
, 1); nextlinks
;
721 nextlinks
= XEXP (nextlinks
, 1))
722 if ((next
= try_combine (insn
, XEXP (links
, 0),
724 &new_direct_jump_p
)) != 0)
727 if (GET_CODE (insn
) != NOTE
)
728 record_dead_and_set_regs (insn
);
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
738 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
739 new_direct_jump_p
|= purge_all_dead_edges (0);
740 delete_noop_moves (f
);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
743 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE
);
747 sbitmap_free (refresh_blocks
);
748 free (reg_nonzero_bits
);
749 free (reg_sign_bit_copies
);
750 free (reg_last_death
);
752 free (reg_last_set_value
);
753 free (reg_last_set_table_tick
);
754 free (reg_last_set_label
);
755 free (reg_last_set_invalid
);
756 free (reg_last_set_mode
);
757 free (reg_last_set_nonzero_bits
);
758 free (reg_last_set_sign_bit_copies
);
762 struct undo
*undo
, *next
;
763 for (undo
= undobuf
.frees
; undo
; undo
= next
)
771 total_attempts
+= combine_attempts
;
772 total_merges
+= combine_merges
;
773 total_extras
+= combine_extras
;
774 total_successes
+= combine_successes
;
776 nonzero_sign_valid
= 0;
777 gen_lowpart
= gen_lowpart_general
;
779 /* Make recognizer allow volatile MEMs again. */
782 return new_direct_jump_p
;
785 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
788 init_reg_last_arrays (void)
790 unsigned int nregs
= combine_max_regno
;
792 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
793 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
794 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
795 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
796 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
797 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
798 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
799 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
800 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
803 /* Set up any promoted values for incoming argument registers. */
806 setup_incoming_promotions (void)
810 enum machine_mode mode
;
812 rtx first
= get_insns ();
814 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
816 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
817 /* Check whether this register can hold an incoming pointer
818 argument. FUNCTION_ARG_REGNO_P tests outgoing register
819 numbers, so translate if necessary due to register windows. */
820 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
821 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
824 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
827 gen_rtx_CLOBBER (mode
, const0_rtx
)));
832 /* Called via note_stores. If X is a pseudo that is narrower than
833 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
835 If we are setting only a portion of X and we can't figure out what
836 portion, assume all bits will be used since we don't know what will
839 Similarly, set how many bits of X are known to be copies of the sign bit
840 at all locations in the function. This is the smallest number implied
844 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
845 void *data ATTRIBUTE_UNUSED
)
849 if (GET_CODE (x
) == REG
850 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
851 /* If this register is undefined at the start of the file, we can't
852 say what its contents were. */
853 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
854 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
856 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
858 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
859 reg_sign_bit_copies
[REGNO (x
)] = 1;
863 /* If this is a complex assignment, see if we can convert it into a
864 simple assignment. */
865 set
= expand_field_assignment (set
);
867 /* If this is a simple assignment, or we have a paradoxical SUBREG,
868 set what we know about X. */
870 if (SET_DEST (set
) == x
871 || (GET_CODE (SET_DEST (set
)) == SUBREG
872 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
873 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
874 && SUBREG_REG (SET_DEST (set
)) == x
))
876 rtx src
= SET_SRC (set
);
878 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
879 /* If X is narrower than a word and SRC is a non-negative
880 constant that would appear negative in the mode of X,
881 sign-extend it for use in reg_nonzero_bits because some
882 machines (maybe most) will actually do the sign-extension
883 and this is the conservative approach.
885 ??? For 2.5, try to tighten up the MD files in this regard
886 instead of this kludge. */
888 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
889 && GET_CODE (src
) == CONST_INT
891 && 0 != (INTVAL (src
)
893 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
894 src
= GEN_INT (INTVAL (src
)
895 | ((HOST_WIDE_INT
) (-1)
896 << GET_MODE_BITSIZE (GET_MODE (x
))));
899 /* Don't call nonzero_bits if it cannot change anything. */
900 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
901 reg_nonzero_bits
[REGNO (x
)]
902 |= nonzero_bits (src
, nonzero_bits_mode
);
903 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
904 if (reg_sign_bit_copies
[REGNO (x
)] == 0
905 || reg_sign_bit_copies
[REGNO (x
)] > num
)
906 reg_sign_bit_copies
[REGNO (x
)] = num
;
910 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
911 reg_sign_bit_copies
[REGNO (x
)] = 1;
916 /* See if INSN can be combined into I3. PRED and SUCC are optionally
917 insns that were previously combined into I3 or that will be combined
918 into the merger of INSN and I3.
920 Return 0 if the combination is not allowed for any reason.
922 If the combination is allowed, *PDEST will be set to the single
923 destination of INSN and *PSRC to the single source, and this function
927 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
928 rtx
*pdest
, rtx
*psrc
)
931 rtx set
= 0, src
, dest
;
936 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
937 && next_active_insn (succ
) == i3
)
938 : next_active_insn (insn
) == i3
);
940 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
941 or a PARALLEL consisting of such a SET and CLOBBERs.
943 If INSN has CLOBBER parallel parts, ignore them for our processing.
944 By definition, these happen during the execution of the insn. When it
945 is merged with another insn, all bets are off. If they are, in fact,
946 needed and aren't also supplied in I3, they may be added by
947 recog_for_combine. Otherwise, it won't match.
949 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
952 Get the source and destination of INSN. If more than one, can't
955 if (GET_CODE (PATTERN (insn
)) == SET
)
956 set
= PATTERN (insn
);
957 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
958 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
960 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
962 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
965 switch (GET_CODE (elt
))
967 /* This is important to combine floating point insns
970 /* Combining an isolated USE doesn't make sense.
971 We depend here on combinable_i3pat to reject them. */
972 /* The code below this loop only verifies that the inputs of
973 the SET in INSN do not change. We call reg_set_between_p
974 to verify that the REG in the USE does not change between
976 If the USE in INSN was for a pseudo register, the matching
977 insn pattern will likely match any register; combining this
978 with any other USE would only be safe if we knew that the
979 used registers have identical values, or if there was
980 something to tell them apart, e.g. different modes. For
981 now, we forgo such complicated tests and simply disallow
982 combining of USES of pseudo registers with any other USE. */
983 if (GET_CODE (XEXP (elt
, 0)) == REG
984 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
986 rtx i3pat
= PATTERN (i3
);
987 int i
= XVECLEN (i3pat
, 0) - 1;
988 unsigned int regno
= REGNO (XEXP (elt
, 0));
992 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
994 if (GET_CODE (i3elt
) == USE
995 && GET_CODE (XEXP (i3elt
, 0)) == REG
996 && (REGNO (XEXP (i3elt
, 0)) == regno
997 ? reg_set_between_p (XEXP (elt
, 0),
998 PREV_INSN (insn
), i3
)
999 : regno
>= FIRST_PSEUDO_REGISTER
))
1006 /* We can ignore CLOBBERs. */
1011 /* Ignore SETs whose result isn't used but not those that
1012 have side-effects. */
1013 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1014 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1015 || INTVAL (XEXP (note
, 0)) <= 0)
1016 && ! side_effects_p (elt
))
1019 /* If we have already found a SET, this is a second one and
1020 so we cannot combine with this insn. */
1028 /* Anything else means we can't combine. */
1034 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1035 so don't do anything with it. */
1036 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1045 set
= expand_field_assignment (set
);
1046 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1048 /* Don't eliminate a store in the stack pointer. */
1049 if (dest
== stack_pointer_rtx
1050 /* Don't combine with an insn that sets a register to itself if it has
1051 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1052 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1053 /* Can't merge an ASM_OPERANDS. */
1054 || GET_CODE (src
) == ASM_OPERANDS
1055 /* Can't merge a function call. */
1056 || GET_CODE (src
) == CALL
1057 /* Don't eliminate a function call argument. */
1058 || (GET_CODE (i3
) == CALL_INSN
1059 && (find_reg_fusage (i3
, USE
, dest
)
1060 || (GET_CODE (dest
) == REG
1061 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1062 && global_regs
[REGNO (dest
)])))
1063 /* Don't substitute into an incremented register. */
1064 || FIND_REG_INC_NOTE (i3
, dest
)
1065 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1067 /* Don't combine the end of a libcall into anything. */
1068 /* ??? This gives worse code, and appears to be unnecessary, since no
1069 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1070 use REG_RETVAL notes for noconflict blocks, but other code here
1071 makes sure that those insns don't disappear. */
1072 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1074 /* Make sure that DEST is not used after SUCC but before I3. */
1075 || (succ
&& ! all_adjacent
1076 && reg_used_between_p (dest
, succ
, i3
))
1077 /* Make sure that the value that is to be substituted for the register
1078 does not use any registers whose values alter in between. However,
1079 If the insns are adjacent, a use can't cross a set even though we
1080 think it might (this can happen for a sequence of insns each setting
1081 the same destination; reg_last_set of that register might point to
1082 a NOTE). If INSN has a REG_EQUIV note, the register is always
1083 equivalent to the memory so the substitution is valid even if there
1084 are intervening stores. Also, don't move a volatile asm or
1085 UNSPEC_VOLATILE across any other insns. */
1087 && (((GET_CODE (src
) != MEM
1088 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1089 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1090 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1091 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1092 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1093 better register allocation by not doing the combine. */
1094 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1095 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1096 /* Don't combine across a CALL_INSN, because that would possibly
1097 change whether the life span of some REGs crosses calls or not,
1098 and it is a pain to update that information.
1099 Exception: if source is a constant, moving it later can't hurt.
1100 Accept that special case, because it helps -fforce-addr a lot. */
1101 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1104 /* DEST must either be a REG or CC0. */
1105 if (GET_CODE (dest
) == REG
)
1107 /* If register alignment is being enforced for multi-word items in all
1108 cases except for parameters, it is possible to have a register copy
1109 insn referencing a hard register that is not allowed to contain the
1110 mode being copied and which would not be valid as an operand of most
1111 insns. Eliminate this problem by not combining with such an insn.
1113 Also, on some machines we don't want to extend the life of a hard
1116 if (GET_CODE (src
) == REG
1117 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1118 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1119 /* Don't extend the life of a hard register unless it is
1120 user variable (if we have few registers) or it can't
1121 fit into the desired register (meaning something special
1123 Also avoid substituting a return register into I3, because
1124 reload can't handle a conflict with constraints of other
1126 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1127 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1130 else if (GET_CODE (dest
) != CC0
)
1133 /* Don't substitute for a register intended as a clobberable operand.
1134 Similarly, don't substitute an expression containing a register that
1135 will be clobbered in I3. */
1136 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1137 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1138 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1139 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1141 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1144 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1145 or not), reject, unless nothing volatile comes between it and I3 */
1147 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1149 /* Make sure succ doesn't contain a volatile reference. */
1150 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1153 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1154 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1158 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1159 to be an explicit register variable, and was chosen for a reason. */
1161 if (GET_CODE (src
) == ASM_OPERANDS
1162 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1165 /* If there are any volatile insns between INSN and I3, reject, because
1166 they might affect machine state. */
1168 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1169 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1172 /* If INSN or I2 contains an autoincrement or autodecrement,
1173 make sure that register is not used between there and I3,
1174 and not already used in I3 either.
1175 Also insist that I3 not be a jump; if it were one
1176 and the incremented register were spilled, we would lose. */
1179 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1180 if (REG_NOTE_KIND (link
) == REG_INC
1181 && (GET_CODE (i3
) == JUMP_INSN
1182 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1183 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1188 /* Don't combine an insn that follows a CC0-setting insn.
1189 An insn that uses CC0 must not be separated from the one that sets it.
1190 We do, however, allow I2 to follow a CC0-setting insn if that insn
1191 is passed as I1; in that case it will be deleted also.
1192 We also allow combining in this case if all the insns are adjacent
1193 because that would leave the two CC0 insns adjacent as well.
1194 It would be more logical to test whether CC0 occurs inside I1 or I2,
1195 but that would be much slower, and this ought to be equivalent. */
1197 p
= prev_nonnote_insn (insn
);
1198 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1203 /* If we get here, we have passed all the tests and the combination is
1212 /* LOC is the location within I3 that contains its pattern or the component
1213 of a PARALLEL of the pattern. We validate that it is valid for combining.
1215 One problem is if I3 modifies its output, as opposed to replacing it
1216 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1217 so would produce an insn that is not equivalent to the original insns.
1221 (set (reg:DI 101) (reg:DI 100))
1222 (set (subreg:SI (reg:DI 101) 0) <foo>)
1224 This is NOT equivalent to:
1226 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1227 (set (reg:DI 101) (reg:DI 100))])
1229 Not only does this modify 100 (in which case it might still be valid
1230 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1232 We can also run into a problem if I2 sets a register that I1
1233 uses and I1 gets directly substituted into I3 (not via I2). In that
1234 case, we would be getting the wrong value of I2DEST into I3, so we
1235 must reject the combination. This case occurs when I2 and I1 both
1236 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1237 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1238 of a SET must prevent combination from occurring.
1240 Before doing the above check, we first try to expand a field assignment
1241 into a set of logical operations.
1243 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1244 we place a register that is both set and used within I3. If more than one
1245 such register is detected, we fail.
1247 Return 1 if the combination is valid, zero otherwise. */
1250 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1251 int i1_not_in_src
, rtx
*pi3dest_killed
)
1255 if (GET_CODE (x
) == SET
)
1258 rtx dest
= SET_DEST (set
);
1259 rtx src
= SET_SRC (set
);
1260 rtx inner_dest
= dest
;
1262 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1263 || GET_CODE (inner_dest
) == SUBREG
1264 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1265 inner_dest
= XEXP (inner_dest
, 0);
1267 /* Check for the case where I3 modifies its output, as discussed
1268 above. We don't want to prevent pseudos from being combined
1269 into the address of a MEM, so only prevent the combination if
1270 i1 or i2 set the same MEM. */
1271 if ((inner_dest
!= dest
&&
1272 (GET_CODE (inner_dest
) != MEM
1273 || rtx_equal_p (i2dest
, inner_dest
)
1274 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1275 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1276 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1278 /* This is the same test done in can_combine_p except we can't test
1279 all_adjacent; we don't have to, since this instruction will stay
1280 in place, thus we are not considering increasing the lifetime of
1283 Also, if this insn sets a function argument, combining it with
1284 something that might need a spill could clobber a previous
1285 function argument; the all_adjacent test in can_combine_p also
1286 checks this; here, we do a more specific test for this case. */
1288 || (GET_CODE (inner_dest
) == REG
1289 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1290 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1291 GET_MODE (inner_dest
))))
1292 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1295 /* If DEST is used in I3, it is being killed in this insn,
1296 so record that for later.
1297 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1298 STACK_POINTER_REGNUM, since these are always considered to be
1299 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1300 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1301 && reg_referenced_p (dest
, PATTERN (i3
))
1302 && REGNO (dest
) != FRAME_POINTER_REGNUM
1303 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1304 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1306 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1307 && (REGNO (dest
) != ARG_POINTER_REGNUM
1308 || ! fixed_regs
[REGNO (dest
)])
1310 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1312 if (*pi3dest_killed
)
1315 *pi3dest_killed
= dest
;
1319 else if (GET_CODE (x
) == PARALLEL
)
1323 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1324 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1325 i1_not_in_src
, pi3dest_killed
))
1332 /* Return 1 if X is an arithmetic expression that contains a multiplication
1333 and division. We don't count multiplications by powers of two here. */
1336 contains_muldiv (rtx x
)
1338 switch (GET_CODE (x
))
1340 case MOD
: case DIV
: case UMOD
: case UDIV
:
1344 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1345 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1347 switch (GET_RTX_CLASS (GET_CODE (x
)))
1349 case 'c': case '<': case '2':
1350 return contains_muldiv (XEXP (x
, 0))
1351 || contains_muldiv (XEXP (x
, 1));
1354 return contains_muldiv (XEXP (x
, 0));
1362 /* Determine whether INSN can be used in a combination. Return nonzero if
1363 not. This is used in try_combine to detect early some cases where we
1364 can't perform combinations. */
1367 cant_combine_insn_p (rtx insn
)
1372 /* If this isn't really an insn, we can't do anything.
1373 This can occur when flow deletes an insn that it has merged into an
1374 auto-increment address. */
1375 if (! INSN_P (insn
))
1378 /* Never combine loads and stores involving hard regs that are likely
1379 to be spilled. The register allocator can usually handle such
1380 reg-reg moves by tying. If we allow the combiner to make
1381 substitutions of likely-spilled regs, we may abort in reload.
1382 As an exception, we allow combinations involving fixed regs; these are
1383 not available to the register allocator so there's no risk involved. */
1385 set
= single_set (insn
);
1388 src
= SET_SRC (set
);
1389 dest
= SET_DEST (set
);
1390 if (GET_CODE (src
) == SUBREG
)
1391 src
= SUBREG_REG (src
);
1392 if (GET_CODE (dest
) == SUBREG
)
1393 dest
= SUBREG_REG (dest
);
1394 if (REG_P (src
) && REG_P (dest
)
1395 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1396 && ! fixed_regs
[REGNO (src
)]
1397 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1398 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1399 && ! fixed_regs
[REGNO (dest
)]
1400 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1406 /* Adjust INSN after we made a change to its destination.
1408 Changing the destination can invalidate notes that say something about
1409 the results of the insn and a LOG_LINK pointing to the insn. */
1412 adjust_for_new_dest (rtx insn
)
1416 /* For notes, be conservative and simply remove them. */
1417 loc
= ®_NOTES (insn
);
1420 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1421 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1422 *loc
= XEXP (*loc
, 1);
1424 loc
= &XEXP (*loc
, 1);
1427 /* The new insn will have a destination that was previously the destination
1428 of an insn just above it. Call distribute_links to make a LOG_LINK from
1429 the next use of that destination. */
1430 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1433 /* Try to combine the insns I1 and I2 into I3.
1434 Here I1 and I2 appear earlier than I3.
1435 I1 can be zero; then we combine just I2 into I3.
1437 If we are combining three insns and the resulting insn is not recognized,
1438 try splitting it into two insns. If that happens, I2 and I3 are retained
1439 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1442 Return 0 if the combination does not work. Then nothing is changed.
1443 If we did the combination, return the insn at which combine should
1446 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1447 new direct jump instruction. */
1450 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1452 /* New patterns for I3 and I2, respectively. */
1453 rtx newpat
, newi2pat
= 0;
1454 int substed_i2
= 0, substed_i1
= 0;
1455 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1456 int added_sets_1
, added_sets_2
;
1457 /* Total number of SETs to put into I3. */
1459 /* Nonzero is I2's body now appears in I3. */
1461 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1462 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1463 /* Contains I3 if the destination of I3 is used in its source, which means
1464 that the old life of I3 is being killed. If that usage is placed into
1465 I2 and not in I3, a REG_DEAD note must be made. */
1466 rtx i3dest_killed
= 0;
1467 /* SET_DEST and SET_SRC of I2 and I1. */
1468 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1469 /* PATTERN (I2), or a copy of it in certain cases. */
1471 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1472 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1473 int i1_feeds_i3
= 0;
1474 /* Notes that must be added to REG_NOTES in I3 and I2. */
1475 rtx new_i3_notes
, new_i2_notes
;
1476 /* Notes that we substituted I3 into I2 instead of the normal case. */
1477 int i3_subst_into_i2
= 0;
1478 /* Notes that I1, I2 or I3 is a MULT operation. */
1486 /* Exit early if one of the insns involved can't be used for
1488 if (cant_combine_insn_p (i3
)
1489 || cant_combine_insn_p (i2
)
1490 || (i1
&& cant_combine_insn_p (i1
))
1491 /* We also can't do anything if I3 has a
1492 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1495 /* ??? This gives worse code, and appears to be unnecessary, since no
1496 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1497 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1503 undobuf
.other_insn
= 0;
1505 /* Reset the hard register usage information. */
1506 CLEAR_HARD_REG_SET (newpat_used_regs
);
1508 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1509 code below, set I1 to be the earlier of the two insns. */
1510 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1511 temp
= i1
, i1
= i2
, i2
= temp
;
1513 added_links_insn
= 0;
1515 /* First check for one important special-case that the code below will
1516 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1517 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1518 we may be able to replace that destination with the destination of I3.
1519 This occurs in the common code where we compute both a quotient and
1520 remainder into a structure, in which case we want to do the computation
1521 directly into the structure to avoid register-register copies.
1523 Note that this case handles both multiple sets in I2 and also
1524 cases where I2 has a number of CLOBBER or PARALLELs.
1526 We make very conservative checks below and only try to handle the
1527 most common cases of this. For example, we only handle the case
1528 where I2 and I3 are adjacent to avoid making difficult register
1531 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1532 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1533 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1534 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1535 && GET_CODE (PATTERN (i2
)) == PARALLEL
1536 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1537 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1538 below would need to check what is inside (and reg_overlap_mentioned_p
1539 doesn't support those codes anyway). Don't allow those destinations;
1540 the resulting insn isn't likely to be recognized anyway. */
1541 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1542 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1543 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1544 SET_DEST (PATTERN (i3
)))
1545 && next_real_insn (i2
) == i3
)
1547 rtx p2
= PATTERN (i2
);
1549 /* Make sure that the destination of I3,
1550 which we are going to substitute into one output of I2,
1551 is not used within another output of I2. We must avoid making this:
1552 (parallel [(set (mem (reg 69)) ...)
1553 (set (reg 69) ...)])
1554 which is not well-defined as to order of actions.
1555 (Besides, reload can't handle output reloads for this.)
1557 The problem can also happen if the dest of I3 is a memory ref,
1558 if another dest in I2 is an indirect memory ref. */
1559 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1560 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1561 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1562 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1563 SET_DEST (XVECEXP (p2
, 0, i
))))
1566 if (i
== XVECLEN (p2
, 0))
1567 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1568 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1569 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1570 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1575 subst_low_cuid
= INSN_CUID (i2
);
1577 added_sets_2
= added_sets_1
= 0;
1578 i2dest
= SET_SRC (PATTERN (i3
));
1580 /* Replace the dest in I2 with our dest and make the resulting
1581 insn the new pattern for I3. Then skip to where we
1582 validate the pattern. Everything was set up above. */
1583 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1584 SET_DEST (PATTERN (i3
)));
1587 i3_subst_into_i2
= 1;
1588 goto validate_replacement
;
1592 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1593 one of those words to another constant, merge them by making a new
1596 && (temp
= single_set (i2
)) != 0
1597 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1598 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1599 && GET_CODE (SET_DEST (temp
)) == REG
1600 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1601 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1602 && GET_CODE (PATTERN (i3
)) == SET
1603 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1604 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1605 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1606 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1607 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1609 HOST_WIDE_INT lo
, hi
;
1611 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1612 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1615 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1616 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1619 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1621 /* We don't handle the case of the target word being wider
1622 than a host wide int. */
1623 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1626 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1627 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1628 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1630 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1631 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1632 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1634 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1635 >> (HOST_BITS_PER_WIDE_INT
- 1));
1637 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1638 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1639 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1640 (INTVAL (SET_SRC (PATTERN (i3
)))));
1642 hi
= lo
< 0 ? -1 : 0;
1645 /* We don't handle the case of the higher word not fitting
1646 entirely in either hi or lo. */
1651 subst_low_cuid
= INSN_CUID (i2
);
1652 added_sets_2
= added_sets_1
= 0;
1653 i2dest
= SET_DEST (temp
);
1655 SUBST (SET_SRC (temp
),
1656 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1658 newpat
= PATTERN (i2
);
1659 goto validate_replacement
;
1663 /* If we have no I1 and I2 looks like:
1664 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1666 make up a dummy I1 that is
1669 (set (reg:CC X) (compare:CC Y (const_int 0)))
1671 (We can ignore any trailing CLOBBERs.)
1673 This undoes a previous combination and allows us to match a branch-and-
1676 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1677 && XVECLEN (PATTERN (i2
), 0) >= 2
1678 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1679 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1681 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1682 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1683 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1684 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1685 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1686 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1688 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1689 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1694 /* We make I1 with the same INSN_UID as I2. This gives it
1695 the same INSN_CUID for value tracking. Our fake I1 will
1696 never appear in the insn stream so giving it the same INSN_UID
1697 as I2 will not cause a problem. */
1699 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1700 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1701 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1704 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1705 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1706 SET_DEST (PATTERN (i1
)));
1711 /* Verify that I2 and I1 are valid for combining. */
1712 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1713 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1719 /* Record whether I2DEST is used in I2SRC and similarly for the other
1720 cases. Knowing this will help in register status updating below. */
1721 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1722 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1723 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1725 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1727 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1729 /* Ensure that I3's pattern can be the destination of combines. */
1730 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1731 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1738 /* See if any of the insns is a MULT operation. Unless one is, we will
1739 reject a combination that is, since it must be slower. Be conservative
1741 if (GET_CODE (i2src
) == MULT
1742 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1743 || (GET_CODE (PATTERN (i3
)) == SET
1744 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1747 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1748 We used to do this EXCEPT in one case: I3 has a post-inc in an
1749 output operand. However, that exception can give rise to insns like
1751 which is a famous insn on the PDP-11 where the value of r3 used as the
1752 source was model-dependent. Avoid this sort of thing. */
1755 if (!(GET_CODE (PATTERN (i3
)) == SET
1756 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1757 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1758 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1759 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1760 /* It's not the exception. */
1763 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1764 if (REG_NOTE_KIND (link
) == REG_INC
1765 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1767 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1774 /* See if the SETs in I1 or I2 need to be kept around in the merged
1775 instruction: whenever the value set there is still needed past I3.
1776 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1778 For the SET in I1, we have two cases: If I1 and I2 independently
1779 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1780 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1781 in I1 needs to be kept around unless I1DEST dies or is set in either
1782 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1783 I1DEST. If so, we know I1 feeds into I2. */
1785 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1788 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1789 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1791 /* If the set in I2 needs to be kept around, we must make a copy of
1792 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1793 PATTERN (I2), we are only substituting for the original I1DEST, not into
1794 an already-substituted copy. This also prevents making self-referential
1795 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1798 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1799 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1803 i2pat
= copy_rtx (i2pat
);
1807 /* Substitute in the latest insn for the regs set by the earlier ones. */
1809 maxreg
= max_reg_num ();
1813 /* It is possible that the source of I2 or I1 may be performing an
1814 unneeded operation, such as a ZERO_EXTEND of something that is known
1815 to have the high part zero. Handle that case by letting subst look at
1816 the innermost one of them.
1818 Another way to do this would be to have a function that tries to
1819 simplify a single insn instead of merging two or more insns. We don't
1820 do this because of the potential of infinite loops and because
1821 of the potential extra memory required. However, doing it the way
1822 we are is a bit of a kludge and doesn't catch all cases.
1824 But only do this if -fexpensive-optimizations since it slows things down
1825 and doesn't usually win. */
1827 if (flag_expensive_optimizations
)
1829 /* Pass pc_rtx so no substitutions are done, just simplifications.
1830 The cases that we are interested in here do not involve the few
1831 cases were is_replaced is checked. */
1834 subst_low_cuid
= INSN_CUID (i1
);
1835 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1839 subst_low_cuid
= INSN_CUID (i2
);
1840 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1845 /* Many machines that don't use CC0 have insns that can both perform an
1846 arithmetic operation and set the condition code. These operations will
1847 be represented as a PARALLEL with the first element of the vector
1848 being a COMPARE of an arithmetic operation with the constant zero.
1849 The second element of the vector will set some pseudo to the result
1850 of the same arithmetic operation. If we simplify the COMPARE, we won't
1851 match such a pattern and so will generate an extra insn. Here we test
1852 for this case, where both the comparison and the operation result are
1853 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1854 I2SRC. Later we will make the PARALLEL that contains I2. */
1856 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1857 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1858 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1859 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1861 #ifdef SELECT_CC_MODE
1863 enum machine_mode compare_mode
;
1866 newpat
= PATTERN (i3
);
1867 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1871 #ifdef SELECT_CC_MODE
1872 /* See if a COMPARE with the operand we substituted in should be done
1873 with the mode that is currently being used. If not, do the same
1874 processing we do in `subst' for a SET; namely, if the destination
1875 is used only once, try to replace it with a register of the proper
1876 mode and also replace the COMPARE. */
1877 if (undobuf
.other_insn
== 0
1878 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1879 &undobuf
.other_insn
))
1880 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1882 != GET_MODE (SET_DEST (newpat
))))
1884 unsigned int regno
= REGNO (SET_DEST (newpat
));
1885 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1887 if (regno
< FIRST_PSEUDO_REGISTER
1888 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1889 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1891 if (regno
>= FIRST_PSEUDO_REGISTER
)
1892 SUBST (regno_reg_rtx
[regno
], new_dest
);
1894 SUBST (SET_DEST (newpat
), new_dest
);
1895 SUBST (XEXP (*cc_use
, 0), new_dest
);
1896 SUBST (SET_SRC (newpat
),
1897 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1900 undobuf
.other_insn
= 0;
1907 n_occurrences
= 0; /* `subst' counts here */
1909 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1910 need to make a unique copy of I2SRC each time we substitute it
1911 to avoid self-referential rtl. */
1913 subst_low_cuid
= INSN_CUID (i2
);
1914 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1915 ! i1_feeds_i3
&& i1dest_in_i1src
);
1918 /* Record whether i2's body now appears within i3's body. */
1919 i2_is_used
= n_occurrences
;
1922 /* If we already got a failure, don't try to do more. Otherwise,
1923 try to substitute in I1 if we have it. */
1925 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1927 /* Before we can do this substitution, we must redo the test done
1928 above (see detailed comments there) that ensures that I1DEST
1929 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1931 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1939 subst_low_cuid
= INSN_CUID (i1
);
1940 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1944 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1945 to count all the ways that I2SRC and I1SRC can be used. */
1946 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1947 && i2_is_used
+ added_sets_2
> 1)
1948 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1949 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1951 /* Fail if we tried to make a new register (we used to abort, but there's
1952 really no reason to). */
1953 || max_reg_num () != maxreg
1954 /* Fail if we couldn't do something and have a CLOBBER. */
1955 || GET_CODE (newpat
) == CLOBBER
1956 /* Fail if this new pattern is a MULT and we didn't have one before
1957 at the outer level. */
1958 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1965 /* If the actions of the earlier insns must be kept
1966 in addition to substituting them into the latest one,
1967 we must make a new PARALLEL for the latest insn
1968 to hold additional the SETs. */
1970 if (added_sets_1
|| added_sets_2
)
1974 if (GET_CODE (newpat
) == PARALLEL
)
1976 rtvec old
= XVEC (newpat
, 0);
1977 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1978 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1979 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1980 sizeof (old
->elem
[0]) * old
->num_elem
);
1985 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1986 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1987 XVECEXP (newpat
, 0, 0) = old
;
1991 XVECEXP (newpat
, 0, --total_sets
)
1992 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1993 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1997 /* If there is no I1, use I2's body as is. We used to also not do
1998 the subst call below if I2 was substituted into I3,
1999 but that could lose a simplification. */
2001 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2003 /* See comment where i2pat is assigned. */
2004 XVECEXP (newpat
, 0, --total_sets
)
2005 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2009 /* We come here when we are replacing a destination in I2 with the
2010 destination of I3. */
2011 validate_replacement
:
2013 /* Note which hard regs this insn has as inputs. */
2014 mark_used_regs_combine (newpat
);
2016 /* Is the result of combination a valid instruction? */
2017 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2019 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2020 the second SET's destination is a register that is unused and isn't
2021 marked as an instruction that might trap in an EH region. In that case,
2022 we just need the first SET. This can occur when simplifying a divmod
2023 insn. We *must* test for this case here because the code below that
2024 splits two independent SETs doesn't handle this case correctly when it
2025 updates the register status.
2027 It's pointless doing this if we originally had two sets, one from
2028 i3, and one from i2. Combining then splitting the parallel results
2029 in the original i2 again plus an invalid insn (which we delete).
2030 The net effect is only to move instructions around, which makes
2031 debug info less accurate.
2033 Also check the case where the first SET's destination is unused.
2034 That would not cause incorrect code, but does cause an unneeded
2037 if (insn_code_number
< 0
2038 && !(added_sets_2
&& i1
== 0)
2039 && GET_CODE (newpat
) == PARALLEL
2040 && XVECLEN (newpat
, 0) == 2
2041 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2042 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2043 && asm_noperands (newpat
) < 0)
2045 rtx set0
= XVECEXP (newpat
, 0, 0);
2046 rtx set1
= XVECEXP (newpat
, 0, 1);
2049 if (((GET_CODE (SET_DEST (set1
)) == REG
2050 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2051 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2052 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2053 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2054 || INTVAL (XEXP (note
, 0)) <= 0)
2055 && ! side_effects_p (SET_SRC (set1
)))
2058 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2061 else if (((GET_CODE (SET_DEST (set0
)) == REG
2062 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2063 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2064 && find_reg_note (i3
, REG_UNUSED
,
2065 SUBREG_REG (SET_DEST (set0
)))))
2066 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2067 || INTVAL (XEXP (note
, 0)) <= 0)
2068 && ! side_effects_p (SET_SRC (set0
)))
2071 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2073 if (insn_code_number
>= 0)
2075 /* If we will be able to accept this, we have made a
2076 change to the destination of I3. This requires us to
2077 do a few adjustments. */
2079 PATTERN (i3
) = newpat
;
2080 adjust_for_new_dest (i3
);
2085 /* If we were combining three insns and the result is a simple SET
2086 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2087 insns. There are two ways to do this. It can be split using a
2088 machine-specific method (like when you have an addition of a large
2089 constant) or by combine in the function find_split_point. */
2091 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2092 && asm_noperands (newpat
) < 0)
2094 rtx m_split
, *split
;
2095 rtx ni2dest
= i2dest
;
2097 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2098 use I2DEST as a scratch register will help. In the latter case,
2099 convert I2DEST to the mode of the source of NEWPAT if we can. */
2101 m_split
= split_insns (newpat
, i3
);
2103 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2104 inputs of NEWPAT. */
2106 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2107 possible to try that as a scratch reg. This would require adding
2108 more code to make it work though. */
2110 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2112 /* If I2DEST is a hard register or the only use of a pseudo,
2113 we can change its mode. */
2114 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2115 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2116 && GET_CODE (i2dest
) == REG
2117 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2118 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2119 && ! REG_USERVAR_P (i2dest
))))
2120 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2123 m_split
= split_insns (gen_rtx_PARALLEL
2125 gen_rtvec (2, newpat
,
2126 gen_rtx_CLOBBER (VOIDmode
,
2129 /* If the split with the mode-changed register didn't work, try
2130 the original register. */
2131 if (! m_split
&& ni2dest
!= i2dest
)
2134 m_split
= split_insns (gen_rtx_PARALLEL
2136 gen_rtvec (2, newpat
,
2137 gen_rtx_CLOBBER (VOIDmode
,
2143 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2145 m_split
= PATTERN (m_split
);
2146 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2147 if (insn_code_number
>= 0)
2150 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2151 && (next_real_insn (i2
) == i3
2152 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2155 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2156 newi2pat
= PATTERN (m_split
);
2158 i3set
= single_set (NEXT_INSN (m_split
));
2159 i2set
= single_set (m_split
);
2161 /* In case we changed the mode of I2DEST, replace it in the
2162 pseudo-register table here. We can't do it above in case this
2163 code doesn't get executed and we do a split the other way. */
2165 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2166 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2168 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2170 /* If I2 or I3 has multiple SETs, we won't know how to track
2171 register status, so don't use these insns. If I2's destination
2172 is used between I2 and I3, we also can't use these insns. */
2174 if (i2_code_number
>= 0 && i2set
&& i3set
2175 && (next_real_insn (i2
) == i3
2176 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2177 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2179 if (insn_code_number
>= 0)
2182 /* It is possible that both insns now set the destination of I3.
2183 If so, we must show an extra use of it. */
2185 if (insn_code_number
>= 0)
2187 rtx new_i3_dest
= SET_DEST (i3set
);
2188 rtx new_i2_dest
= SET_DEST (i2set
);
2190 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2191 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2192 || GET_CODE (new_i3_dest
) == SUBREG
)
2193 new_i3_dest
= XEXP (new_i3_dest
, 0);
2195 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2196 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2197 || GET_CODE (new_i2_dest
) == SUBREG
)
2198 new_i2_dest
= XEXP (new_i2_dest
, 0);
2200 if (GET_CODE (new_i3_dest
) == REG
2201 && GET_CODE (new_i2_dest
) == REG
2202 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2203 REG_N_SETS (REGNO (new_i2_dest
))++;
2207 /* If we can split it and use I2DEST, go ahead and see if that
2208 helps things be recognized. Verify that none of the registers
2209 are set between I2 and I3. */
2210 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2212 && GET_CODE (i2dest
) == REG
2214 /* We need I2DEST in the proper mode. If it is a hard register
2215 or the only use of a pseudo, we can change its mode. */
2216 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2217 || GET_MODE (*split
) == VOIDmode
2218 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2219 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2220 && ! REG_USERVAR_P (i2dest
)))
2221 && (next_real_insn (i2
) == i3
2222 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2223 /* We can't overwrite I2DEST if its value is still used by
2225 && ! reg_referenced_p (i2dest
, newpat
))
2227 rtx newdest
= i2dest
;
2228 enum rtx_code split_code
= GET_CODE (*split
);
2229 enum machine_mode split_mode
= GET_MODE (*split
);
2231 /* Get NEWDEST as a register in the proper mode. We have already
2232 validated that we can do this. */
2233 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2235 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2237 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2238 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2241 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2242 an ASHIFT. This can occur if it was inside a PLUS and hence
2243 appeared to be a memory address. This is a kludge. */
2244 if (split_code
== MULT
2245 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2246 && INTVAL (XEXP (*split
, 1)) > 0
2247 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2249 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2250 XEXP (*split
, 0), GEN_INT (i
)));
2251 /* Update split_code because we may not have a multiply
2253 split_code
= GET_CODE (*split
);
2256 #ifdef INSN_SCHEDULING
2257 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2258 be written as a ZERO_EXTEND. */
2259 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2261 #ifdef LOAD_EXTEND_OP
2262 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2263 what it really is. */
2264 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2266 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2267 SUBREG_REG (*split
)));
2270 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2271 SUBREG_REG (*split
)));
2275 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2276 SUBST (*split
, newdest
);
2277 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2279 /* If the split point was a MULT and we didn't have one before,
2280 don't use one now. */
2281 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2282 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2286 /* Check for a case where we loaded from memory in a narrow mode and
2287 then sign extended it, but we need both registers. In that case,
2288 we have a PARALLEL with both loads from the same memory location.
2289 We can split this into a load from memory followed by a register-register
2290 copy. This saves at least one insn, more if register allocation can
2293 We cannot do this if the destination of the first assignment is a
2294 condition code register or cc0. We eliminate this case by making sure
2295 the SET_DEST and SET_SRC have the same mode.
2297 We cannot do this if the destination of the second assignment is
2298 a register that we have already assumed is zero-extended. Similarly
2299 for a SUBREG of such a register. */
2301 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2302 && GET_CODE (newpat
) == PARALLEL
2303 && XVECLEN (newpat
, 0) == 2
2304 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2305 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2306 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2307 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2308 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2309 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2310 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2311 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2313 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2314 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2315 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2316 (GET_CODE (temp
) == REG
2317 && reg_nonzero_bits
[REGNO (temp
)] != 0
2318 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2319 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2320 && (reg_nonzero_bits
[REGNO (temp
)]
2321 != GET_MODE_MASK (word_mode
))))
2322 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2323 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2324 (GET_CODE (temp
) == REG
2325 && reg_nonzero_bits
[REGNO (temp
)] != 0
2326 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2327 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2328 && (reg_nonzero_bits
[REGNO (temp
)]
2329 != GET_MODE_MASK (word_mode
)))))
2330 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2331 SET_SRC (XVECEXP (newpat
, 0, 1)))
2332 && ! find_reg_note (i3
, REG_UNUSED
,
2333 SET_DEST (XVECEXP (newpat
, 0, 0))))
2337 newi2pat
= XVECEXP (newpat
, 0, 0);
2338 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2339 newpat
= XVECEXP (newpat
, 0, 1);
2340 SUBST (SET_SRC (newpat
),
2341 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2342 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2344 if (i2_code_number
>= 0)
2345 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2347 if (insn_code_number
>= 0)
2352 /* If we will be able to accept this, we have made a change to the
2353 destination of I3. This requires us to do a few adjustments. */
2354 PATTERN (i3
) = newpat
;
2355 adjust_for_new_dest (i3
);
2357 /* I3 now uses what used to be its destination and which is
2358 now I2's destination. That means we need a LOG_LINK from
2359 I3 to I2. But we used to have one, so we still will.
2361 However, some later insn might be using I2's dest and have
2362 a LOG_LINK pointing at I3. We must remove this link.
2363 The simplest way to remove the link is to point it at I1,
2364 which we know will be a NOTE. */
2366 for (insn
= NEXT_INSN (i3
);
2367 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2368 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2369 insn
= NEXT_INSN (insn
))
2371 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2373 for (link
= LOG_LINKS (insn
); link
;
2374 link
= XEXP (link
, 1))
2375 if (XEXP (link
, 0) == i3
)
2376 XEXP (link
, 0) = i1
;
2384 /* Similarly, check for a case where we have a PARALLEL of two independent
2385 SETs but we started with three insns. In this case, we can do the sets
2386 as two separate insns. This case occurs when some SET allows two
2387 other insns to combine, but the destination of that SET is still live. */
2389 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2390 && GET_CODE (newpat
) == PARALLEL
2391 && XVECLEN (newpat
, 0) == 2
2392 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2393 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2394 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2395 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2396 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2397 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2398 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2400 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2401 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2402 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2403 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2404 XVECEXP (newpat
, 0, 0))
2405 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2406 XVECEXP (newpat
, 0, 1))
2407 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2408 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2410 /* Normally, it doesn't matter which of the two is done first,
2411 but it does if one references cc0. In that case, it has to
2414 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2416 newi2pat
= XVECEXP (newpat
, 0, 0);
2417 newpat
= XVECEXP (newpat
, 0, 1);
2422 newi2pat
= XVECEXP (newpat
, 0, 1);
2423 newpat
= XVECEXP (newpat
, 0, 0);
2426 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2428 if (i2_code_number
>= 0)
2429 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2432 /* If it still isn't recognized, fail and change things back the way they
2434 if ((insn_code_number
< 0
2435 /* Is the result a reasonable ASM_OPERANDS? */
2436 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2442 /* If we had to change another insn, make sure it is valid also. */
2443 if (undobuf
.other_insn
)
2445 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2446 rtx new_other_notes
;
2449 CLEAR_HARD_REG_SET (newpat_used_regs
);
2451 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2454 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2460 PATTERN (undobuf
.other_insn
) = other_pat
;
2462 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2463 are still valid. Then add any non-duplicate notes added by
2464 recog_for_combine. */
2465 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2467 next
= XEXP (note
, 1);
2469 if (REG_NOTE_KIND (note
) == REG_UNUSED
2470 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2472 if (GET_CODE (XEXP (note
, 0)) == REG
)
2473 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2475 remove_note (undobuf
.other_insn
, note
);
2479 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2480 if (GET_CODE (XEXP (note
, 0)) == REG
)
2481 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2483 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2484 undobuf
.other_insn
, NULL_RTX
);
2487 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2488 they are adjacent to each other or not. */
2490 rtx p
= prev_nonnote_insn (i3
);
2491 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2492 && sets_cc0_p (newi2pat
))
2500 /* We now know that we can do this combination. Merge the insns and
2501 update the status of registers and LOG_LINKS. */
2504 rtx i3notes
, i2notes
, i1notes
= 0;
2505 rtx i3links
, i2links
, i1links
= 0;
2509 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2511 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2512 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2514 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2516 /* Ensure that we do not have something that should not be shared but
2517 occurs multiple times in the new insns. Check this by first
2518 resetting all the `used' flags and then copying anything is shared. */
2520 reset_used_flags (i3notes
);
2521 reset_used_flags (i2notes
);
2522 reset_used_flags (i1notes
);
2523 reset_used_flags (newpat
);
2524 reset_used_flags (newi2pat
);
2525 if (undobuf
.other_insn
)
2526 reset_used_flags (PATTERN (undobuf
.other_insn
));
2528 i3notes
= copy_rtx_if_shared (i3notes
);
2529 i2notes
= copy_rtx_if_shared (i2notes
);
2530 i1notes
= copy_rtx_if_shared (i1notes
);
2531 newpat
= copy_rtx_if_shared (newpat
);
2532 newi2pat
= copy_rtx_if_shared (newi2pat
);
2533 if (undobuf
.other_insn
)
2534 reset_used_flags (PATTERN (undobuf
.other_insn
));
2536 INSN_CODE (i3
) = insn_code_number
;
2537 PATTERN (i3
) = newpat
;
2539 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2541 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2543 reset_used_flags (call_usage
);
2544 call_usage
= copy_rtx (call_usage
);
2547 replace_rtx (call_usage
, i2dest
, i2src
);
2550 replace_rtx (call_usage
, i1dest
, i1src
);
2552 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2555 if (undobuf
.other_insn
)
2556 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2558 /* We had one special case above where I2 had more than one set and
2559 we replaced a destination of one of those sets with the destination
2560 of I3. In that case, we have to update LOG_LINKS of insns later
2561 in this basic block. Note that this (expensive) case is rare.
2563 Also, in this case, we must pretend that all REG_NOTEs for I2
2564 actually came from I3, so that REG_UNUSED notes from I2 will be
2565 properly handled. */
2567 if (i3_subst_into_i2
)
2569 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2570 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2571 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2572 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2573 && ! find_reg_note (i2
, REG_UNUSED
,
2574 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2575 for (temp
= NEXT_INSN (i2
);
2576 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2577 || BB_HEAD (this_basic_block
) != temp
);
2578 temp
= NEXT_INSN (temp
))
2579 if (temp
!= i3
&& INSN_P (temp
))
2580 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2581 if (XEXP (link
, 0) == i2
)
2582 XEXP (link
, 0) = i3
;
2587 while (XEXP (link
, 1))
2588 link
= XEXP (link
, 1);
2589 XEXP (link
, 1) = i2notes
;
2603 INSN_CODE (i2
) = i2_code_number
;
2604 PATTERN (i2
) = newi2pat
;
2608 PUT_CODE (i2
, NOTE
);
2609 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2610 NOTE_SOURCE_FILE (i2
) = 0;
2617 PUT_CODE (i1
, NOTE
);
2618 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2619 NOTE_SOURCE_FILE (i1
) = 0;
2622 /* Get death notes for everything that is now used in either I3 or
2623 I2 and used to die in a previous insn. If we built two new
2624 patterns, move from I1 to I2 then I2 to I3 so that we get the
2625 proper movement on registers that I2 modifies. */
2629 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2630 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2633 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2636 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2638 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2640 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2642 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2644 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2646 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2647 know these are REG_UNUSED and want them to go to the desired insn,
2648 so we always pass it as i3. We have not counted the notes in
2649 reg_n_deaths yet, so we need to do so now. */
2651 if (newi2pat
&& new_i2_notes
)
2653 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2654 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2655 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2657 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2662 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2663 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2664 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2666 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2669 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2670 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2671 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2672 in that case, it might delete I2. Similarly for I2 and I1.
2673 Show an additional death due to the REG_DEAD note we make here. If
2674 we discard it in distribute_notes, we will decrement it again. */
2678 if (GET_CODE (i3dest_killed
) == REG
)
2679 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2681 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2682 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2684 NULL_RTX
, i2
, NULL_RTX
);
2686 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2688 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2691 if (i2dest_in_i2src
)
2693 if (GET_CODE (i2dest
) == REG
)
2694 REG_N_DEATHS (REGNO (i2dest
))++;
2696 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2697 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2698 NULL_RTX
, i2
, NULL_RTX
);
2700 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2701 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2704 if (i1dest_in_i1src
)
2706 if (GET_CODE (i1dest
) == REG
)
2707 REG_N_DEATHS (REGNO (i1dest
))++;
2709 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2710 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2711 NULL_RTX
, i2
, NULL_RTX
);
2713 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2714 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2717 distribute_links (i3links
);
2718 distribute_links (i2links
);
2719 distribute_links (i1links
);
2721 if (GET_CODE (i2dest
) == REG
)
2724 rtx i2_insn
= 0, i2_val
= 0, set
;
2726 /* The insn that used to set this register doesn't exist, and
2727 this life of the register may not exist either. See if one of
2728 I3's links points to an insn that sets I2DEST. If it does,
2729 that is now the last known value for I2DEST. If we don't update
2730 this and I2 set the register to a value that depended on its old
2731 contents, we will get confused. If this insn is used, thing
2732 will be set correctly in combine_instructions. */
2734 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2735 if ((set
= single_set (XEXP (link
, 0))) != 0
2736 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2737 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2739 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2741 /* If the reg formerly set in I2 died only once and that was in I3,
2742 zero its use count so it won't make `reload' do any work. */
2744 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2745 && ! i2dest_in_i2src
)
2747 regno
= REGNO (i2dest
);
2748 REG_N_SETS (regno
)--;
2752 if (i1
&& GET_CODE (i1dest
) == REG
)
2755 rtx i1_insn
= 0, i1_val
= 0, set
;
2757 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2758 if ((set
= single_set (XEXP (link
, 0))) != 0
2759 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2760 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2762 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2764 regno
= REGNO (i1dest
);
2765 if (! added_sets_1
&& ! i1dest_in_i1src
)
2766 REG_N_SETS (regno
)--;
2769 /* Update reg_nonzero_bits et al for any changes that may have been made
2770 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2771 important. Because newi2pat can affect nonzero_bits of newpat */
2773 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2774 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2776 /* Set new_direct_jump_p if a new return or simple jump instruction
2779 If I3 is now an unconditional jump, ensure that it has a
2780 BARRIER following it since it may have initially been a
2781 conditional jump. It may also be the last nonnote insn. */
2783 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2785 *new_direct_jump_p
= 1;
2786 mark_jump_label (PATTERN (i3
), i3
, 0);
2788 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2789 || GET_CODE (temp
) != BARRIER
)
2790 emit_barrier_after (i3
);
2793 if (undobuf
.other_insn
!= NULL_RTX
2794 && (returnjump_p (undobuf
.other_insn
)
2795 || any_uncondjump_p (undobuf
.other_insn
)))
2797 *new_direct_jump_p
= 1;
2799 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2800 || GET_CODE (temp
) != BARRIER
)
2801 emit_barrier_after (undobuf
.other_insn
);
2804 /* An NOOP jump does not need barrier, but it does need cleaning up
2806 if (GET_CODE (newpat
) == SET
2807 && SET_SRC (newpat
) == pc_rtx
2808 && SET_DEST (newpat
) == pc_rtx
)
2809 *new_direct_jump_p
= 1;
2812 combine_successes
++;
2815 if (added_links_insn
2816 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2817 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2818 return added_links_insn
;
2820 return newi2pat
? i2
: i3
;
2823 /* Undo all the modifications recorded in undobuf. */
2828 struct undo
*undo
, *next
;
2830 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2834 *undo
->where
.i
= undo
->old_contents
.i
;
2836 *undo
->where
.r
= undo
->old_contents
.r
;
2838 undo
->next
= undobuf
.frees
;
2839 undobuf
.frees
= undo
;
2845 /* We've committed to accepting the changes we made. Move all
2846 of the undos to the free list. */
2851 struct undo
*undo
, *next
;
2853 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2856 undo
->next
= undobuf
.frees
;
2857 undobuf
.frees
= undo
;
2863 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2864 where we have an arithmetic expression and return that point. LOC will
2867 try_combine will call this function to see if an insn can be split into
2871 find_split_point (rtx
*loc
, rtx insn
)
2874 enum rtx_code code
= GET_CODE (x
);
2876 unsigned HOST_WIDE_INT len
= 0;
2877 HOST_WIDE_INT pos
= 0;
2879 rtx inner
= NULL_RTX
;
2881 /* First special-case some codes. */
2885 #ifdef INSN_SCHEDULING
2886 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2888 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2891 return find_split_point (&SUBREG_REG (x
), insn
);
2895 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2896 using LO_SUM and HIGH. */
2897 if (GET_CODE (XEXP (x
, 0)) == CONST
2898 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2901 gen_rtx_LO_SUM (Pmode
,
2902 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2904 return &XEXP (XEXP (x
, 0), 0);
2908 /* If we have a PLUS whose second operand is a constant and the
2909 address is not valid, perhaps will can split it up using
2910 the machine-specific way to split large constants. We use
2911 the first pseudo-reg (one of the virtual regs) as a placeholder;
2912 it will not remain in the result. */
2913 if (GET_CODE (XEXP (x
, 0)) == PLUS
2914 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2915 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2917 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2918 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2921 /* This should have produced two insns, each of which sets our
2922 placeholder. If the source of the second is a valid address,
2923 we can make put both sources together and make a split point
2927 && NEXT_INSN (seq
) != NULL_RTX
2928 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2929 && GET_CODE (seq
) == INSN
2930 && GET_CODE (PATTERN (seq
)) == SET
2931 && SET_DEST (PATTERN (seq
)) == reg
2932 && ! reg_mentioned_p (reg
,
2933 SET_SRC (PATTERN (seq
)))
2934 && GET_CODE (NEXT_INSN (seq
)) == INSN
2935 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2936 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2937 && memory_address_p (GET_MODE (x
),
2938 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2940 rtx src1
= SET_SRC (PATTERN (seq
));
2941 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2943 /* Replace the placeholder in SRC2 with SRC1. If we can
2944 find where in SRC2 it was placed, that can become our
2945 split point and we can replace this address with SRC2.
2946 Just try two obvious places. */
2948 src2
= replace_rtx (src2
, reg
, src1
);
2950 if (XEXP (src2
, 0) == src1
)
2951 split
= &XEXP (src2
, 0);
2952 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2953 && XEXP (XEXP (src2
, 0), 0) == src1
)
2954 split
= &XEXP (XEXP (src2
, 0), 0);
2958 SUBST (XEXP (x
, 0), src2
);
2963 /* If that didn't work, perhaps the first operand is complex and
2964 needs to be computed separately, so make a split point there.
2965 This will occur on machines that just support REG + CONST
2966 and have a constant moved through some previous computation. */
2968 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2969 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2970 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2972 return &XEXP (XEXP (x
, 0), 0);
2978 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2979 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2980 we need to put the operand into a register. So split at that
2983 if (SET_DEST (x
) == cc0_rtx
2984 && GET_CODE (SET_SRC (x
)) != COMPARE
2985 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2986 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2987 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2988 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2989 return &SET_SRC (x
);
2992 /* See if we can split SET_SRC as it stands. */
2993 split
= find_split_point (&SET_SRC (x
), insn
);
2994 if (split
&& split
!= &SET_SRC (x
))
2997 /* See if we can split SET_DEST as it stands. */
2998 split
= find_split_point (&SET_DEST (x
), insn
);
2999 if (split
&& split
!= &SET_DEST (x
))
3002 /* See if this is a bitfield assignment with everything constant. If
3003 so, this is an IOR of an AND, so split it into that. */
3004 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3005 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3006 <= HOST_BITS_PER_WIDE_INT
)
3007 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3008 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3009 && GET_CODE (SET_SRC (x
)) == CONST_INT
3010 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3011 + INTVAL (XEXP (SET_DEST (x
), 2)))
3012 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3013 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3015 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3016 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3017 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3018 rtx dest
= XEXP (SET_DEST (x
), 0);
3019 enum machine_mode mode
= GET_MODE (dest
);
3020 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3022 if (BITS_BIG_ENDIAN
)
3023 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3027 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3030 gen_binary (IOR
, mode
,
3031 gen_binary (AND
, mode
, dest
,
3032 gen_int_mode (~(mask
<< pos
),
3034 GEN_INT (src
<< pos
)));
3036 SUBST (SET_DEST (x
), dest
);
3038 split
= find_split_point (&SET_SRC (x
), insn
);
3039 if (split
&& split
!= &SET_SRC (x
))
3043 /* Otherwise, see if this is an operation that we can split into two.
3044 If so, try to split that. */
3045 code
= GET_CODE (SET_SRC (x
));
3050 /* If we are AND'ing with a large constant that is only a single
3051 bit and the result is only being used in a context where we
3052 need to know if it is zero or nonzero, replace it with a bit
3053 extraction. This will avoid the large constant, which might
3054 have taken more than one insn to make. If the constant were
3055 not a valid argument to the AND but took only one insn to make,
3056 this is no worse, but if it took more than one insn, it will
3059 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3060 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3061 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3062 && GET_CODE (SET_DEST (x
)) == REG
3063 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3064 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3065 && XEXP (*split
, 0) == SET_DEST (x
)
3066 && XEXP (*split
, 1) == const0_rtx
)
3068 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3069 XEXP (SET_SRC (x
), 0),
3070 pos
, NULL_RTX
, 1, 1, 0, 0);
3071 if (extraction
!= 0)
3073 SUBST (SET_SRC (x
), extraction
);
3074 return find_split_point (loc
, insn
);
3080 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3081 is known to be on, this can be converted into a NEG of a shift. */
3082 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3083 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3084 && 1 <= (pos
= exact_log2
3085 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3086 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3088 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3092 gen_rtx_LSHIFTRT (mode
,
3093 XEXP (SET_SRC (x
), 0),
3096 split
= find_split_point (&SET_SRC (x
), insn
);
3097 if (split
&& split
!= &SET_SRC (x
))
3103 inner
= XEXP (SET_SRC (x
), 0);
3105 /* We can't optimize if either mode is a partial integer
3106 mode as we don't know how many bits are significant
3108 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3109 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3113 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3119 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3120 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3122 inner
= XEXP (SET_SRC (x
), 0);
3123 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3124 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3126 if (BITS_BIG_ENDIAN
)
3127 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3128 unsignedp
= (code
== ZERO_EXTRACT
);
3136 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3138 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3140 /* For unsigned, we have a choice of a shift followed by an
3141 AND or two shifts. Use two shifts for field sizes where the
3142 constant might be too large. We assume here that we can
3143 always at least get 8-bit constants in an AND insn, which is
3144 true for every current RISC. */
3146 if (unsignedp
&& len
<= 8)
3151 (mode
, gen_lowpart (mode
, inner
),
3153 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3155 split
= find_split_point (&SET_SRC (x
), insn
);
3156 if (split
&& split
!= &SET_SRC (x
))
3163 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3164 gen_rtx_ASHIFT (mode
,
3165 gen_lowpart (mode
, inner
),
3166 GEN_INT (GET_MODE_BITSIZE (mode
)
3168 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3170 split
= find_split_point (&SET_SRC (x
), insn
);
3171 if (split
&& split
!= &SET_SRC (x
))
3176 /* See if this is a simple operation with a constant as the second
3177 operand. It might be that this constant is out of range and hence
3178 could be used as a split point. */
3179 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3182 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3183 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3184 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3185 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3187 return &XEXP (SET_SRC (x
), 1);
3189 /* Finally, see if this is a simple operation with its first operand
3190 not in a register. The operation might require this operand in a
3191 register, so return it as a split point. We can always do this
3192 because if the first operand were another operation, we would have
3193 already found it as a split point. */
3194 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3195 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3196 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3197 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3198 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3199 return &XEXP (SET_SRC (x
), 0);
3205 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3206 it is better to write this as (not (ior A B)) so we can split it.
3207 Similarly for IOR. */
3208 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3211 gen_rtx_NOT (GET_MODE (x
),
3212 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3214 XEXP (XEXP (x
, 0), 0),
3215 XEXP (XEXP (x
, 1), 0))));
3216 return find_split_point (loc
, insn
);
3219 /* Many RISC machines have a large set of logical insns. If the
3220 second operand is a NOT, put it first so we will try to split the
3221 other operand first. */
3222 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3224 rtx tem
= XEXP (x
, 0);
3225 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3226 SUBST (XEXP (x
, 1), tem
);
3234 /* Otherwise, select our actions depending on our rtx class. */
3235 switch (GET_RTX_CLASS (code
))
3237 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3239 split
= find_split_point (&XEXP (x
, 2), insn
);
3242 /* ... fall through ... */
3246 split
= find_split_point (&XEXP (x
, 1), insn
);
3249 /* ... fall through ... */
3251 /* Some machines have (and (shift ...) ...) insns. If X is not
3252 an AND, but XEXP (X, 0) is, use it as our split point. */
3253 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3254 return &XEXP (x
, 0);
3256 split
= find_split_point (&XEXP (x
, 0), insn
);
3262 /* Otherwise, we don't have a split point. */
3266 /* Throughout X, replace FROM with TO, and return the result.
3267 The result is TO if X is FROM;
3268 otherwise the result is X, but its contents may have been modified.
3269 If they were modified, a record was made in undobuf so that
3270 undo_all will (among other things) return X to its original state.
3272 If the number of changes necessary is too much to record to undo,
3273 the excess changes are not made, so the result is invalid.
3274 The changes already made can still be undone.
3275 undobuf.num_undo is incremented for such changes, so by testing that
3276 the caller can tell whether the result is valid.
3278 `n_occurrences' is incremented each time FROM is replaced.
3280 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3282 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3283 by copying if `n_occurrences' is nonzero. */
3286 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3288 enum rtx_code code
= GET_CODE (x
);
3289 enum machine_mode op0_mode
= VOIDmode
;
3294 /* Two expressions are equal if they are identical copies of a shared
3295 RTX or if they are both registers with the same register number
3298 #define COMBINE_RTX_EQUAL_P(X,Y) \
3300 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3301 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3303 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3306 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3309 /* If X and FROM are the same register but different modes, they will
3310 not have been seen as equal above. However, flow.c will make a
3311 LOG_LINKS entry for that case. If we do nothing, we will try to
3312 rerecognize our original insn and, when it succeeds, we will
3313 delete the feeding insn, which is incorrect.
3315 So force this insn not to match in this (rare) case. */
3316 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3317 && REGNO (x
) == REGNO (from
))
3318 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3320 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3321 of which may contain things that can be combined. */
3322 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3325 /* It is possible to have a subexpression appear twice in the insn.
3326 Suppose that FROM is a register that appears within TO.
3327 Then, after that subexpression has been scanned once by `subst',
3328 the second time it is scanned, TO may be found. If we were
3329 to scan TO here, we would find FROM within it and create a
3330 self-referent rtl structure which is completely wrong. */
3331 if (COMBINE_RTX_EQUAL_P (x
, to
))
3334 /* Parallel asm_operands need special attention because all of the
3335 inputs are shared across the arms. Furthermore, unsharing the
3336 rtl results in recognition failures. Failure to handle this case
3337 specially can result in circular rtl.
3339 Solve this by doing a normal pass across the first entry of the
3340 parallel, and only processing the SET_DESTs of the subsequent
3343 if (code
== PARALLEL
3344 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3345 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3347 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3349 /* If this substitution failed, this whole thing fails. */
3350 if (GET_CODE (new) == CLOBBER
3351 && XEXP (new, 0) == const0_rtx
)
3354 SUBST (XVECEXP (x
, 0, 0), new);
3356 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3358 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3360 if (GET_CODE (dest
) != REG
3361 && GET_CODE (dest
) != CC0
3362 && GET_CODE (dest
) != PC
)
3364 new = subst (dest
, from
, to
, 0, unique_copy
);
3366 /* If this substitution failed, this whole thing fails. */
3367 if (GET_CODE (new) == CLOBBER
3368 && XEXP (new, 0) == const0_rtx
)
3371 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3377 len
= GET_RTX_LENGTH (code
);
3378 fmt
= GET_RTX_FORMAT (code
);
3380 /* We don't need to process a SET_DEST that is a register, CC0,
3381 or PC, so set up to skip this common case. All other cases
3382 where we want to suppress replacing something inside a
3383 SET_SRC are handled via the IN_DEST operand. */
3385 && (GET_CODE (SET_DEST (x
)) == REG
3386 || GET_CODE (SET_DEST (x
)) == CC0
3387 || GET_CODE (SET_DEST (x
)) == PC
))
3390 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3393 op0_mode
= GET_MODE (XEXP (x
, 0));
3395 for (i
= 0; i
< len
; i
++)
3400 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3402 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3404 new = (unique_copy
&& n_occurrences
3405 ? copy_rtx (to
) : to
);
3410 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3413 /* If this substitution failed, this whole thing
3415 if (GET_CODE (new) == CLOBBER
3416 && XEXP (new, 0) == const0_rtx
)
3420 SUBST (XVECEXP (x
, i
, j
), new);
3423 else if (fmt
[i
] == 'e')
3425 /* If this is a register being set, ignore it. */
3428 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3429 || code
== ZERO_EXTRACT
)
3431 && GET_CODE (new) == REG
)
3434 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3436 /* In general, don't install a subreg involving two
3437 modes not tieable. It can worsen register
3438 allocation, and can even make invalid reload
3439 insns, since the reg inside may need to be copied
3440 from in the outside mode, and that may be invalid
3441 if it is an fp reg copied in integer mode.
3443 We allow two exceptions to this: It is valid if
3444 it is inside another SUBREG and the mode of that
3445 SUBREG and the mode of the inside of TO is
3446 tieable and it is valid if X is a SET that copies
3449 if (GET_CODE (to
) == SUBREG
3450 && ! MODES_TIEABLE_P (GET_MODE (to
),
3451 GET_MODE (SUBREG_REG (to
)))
3452 && ! (code
== SUBREG
3453 && MODES_TIEABLE_P (GET_MODE (x
),
3454 GET_MODE (SUBREG_REG (to
))))
3456 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3459 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3461 #ifdef CANNOT_CHANGE_MODE_CLASS
3463 && GET_CODE (to
) == REG
3464 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3465 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3468 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3471 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3475 /* If we are in a SET_DEST, suppress most cases unless we
3476 have gone inside a MEM, in which case we want to
3477 simplify the address. We assume here that things that
3478 are actually part of the destination have their inner
3479 parts in the first expression. This is true for SUBREG,
3480 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3481 things aside from REG and MEM that should appear in a
3483 new = subst (XEXP (x
, i
), from
, to
,
3485 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3486 || code
== ZERO_EXTRACT
))
3488 && i
== 0), unique_copy
);
3490 /* If we found that we will have to reject this combination,
3491 indicate that by returning the CLOBBER ourselves, rather than
3492 an expression containing it. This will speed things up as
3493 well as prevent accidents where two CLOBBERs are considered
3494 to be equal, thus producing an incorrect simplification. */
3496 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3499 if (GET_CODE (x
) == SUBREG
3500 && (GET_CODE (new) == CONST_INT
3501 || GET_CODE (new) == CONST_DOUBLE
))
3503 enum machine_mode mode
= GET_MODE (x
);
3505 x
= simplify_subreg (GET_MODE (x
), new,
3506 GET_MODE (SUBREG_REG (x
)),
3509 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3511 else if (GET_CODE (new) == CONST_INT
3512 && GET_CODE (x
) == ZERO_EXTEND
)
3514 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3515 new, GET_MODE (XEXP (x
, 0)));
3520 SUBST (XEXP (x
, i
), new);
3525 /* Try to simplify X. If the simplification changed the code, it is likely
3526 that further simplification will help, so loop, but limit the number
3527 of repetitions that will be performed. */
3529 for (i
= 0; i
< 4; i
++)
3531 /* If X is sufficiently simple, don't bother trying to do anything
3533 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3534 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3536 if (GET_CODE (x
) == code
)
3539 code
= GET_CODE (x
);
3541 /* We no longer know the original mode of operand 0 since we
3542 have changed the form of X) */
3543 op0_mode
= VOIDmode
;
3549 /* Simplify X, a piece of RTL. We just operate on the expression at the
3550 outer level; call `subst' to simplify recursively. Return the new
3553 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3554 will be the iteration even if an expression with a code different from
3555 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3558 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3561 enum rtx_code code
= GET_CODE (x
);
3562 enum machine_mode mode
= GET_MODE (x
);
3567 /* If this is a commutative operation, put a constant last and a complex
3568 expression first. We don't need to do this for comparisons here. */
3569 if (GET_RTX_CLASS (code
) == 'c'
3570 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3573 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3574 SUBST (XEXP (x
, 1), temp
);
3577 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3578 sign extension of a PLUS with a constant, reverse the order of the sign
3579 extension and the addition. Note that this not the same as the original
3580 code, but overflow is undefined for signed values. Also note that the
3581 PLUS will have been partially moved "inside" the sign-extension, so that
3582 the first operand of X will really look like:
3583 (ashiftrt (plus (ashift A C4) C5) C4).
3585 (plus (ashiftrt (ashift A C4) C2) C4)
3586 and replace the first operand of X with that expression. Later parts
3587 of this function may simplify the expression further.
3589 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3590 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3591 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3593 We do this to simplify address expressions. */
3595 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3596 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3597 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3598 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3599 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3600 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3601 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3602 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3603 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3604 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3605 XEXP (XEXP (x
, 0), 1))) != 0)
3608 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3609 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3610 INTVAL (XEXP (XEXP (x
, 0), 1)));
3612 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3613 INTVAL (XEXP (XEXP (x
, 0), 1)));
3615 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3618 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3619 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3620 things. Check for cases where both arms are testing the same
3623 Don't do anything if all operands are very simple. */
3625 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3626 || GET_RTX_CLASS (code
) == '<')
3627 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3628 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3629 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3631 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3632 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3633 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3635 || (GET_RTX_CLASS (code
) == '1'
3636 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3637 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3638 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3641 rtx cond
, true_rtx
, false_rtx
;
3643 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3645 /* If everything is a comparison, what we have is highly unlikely
3646 to be simpler, so don't use it. */
3647 && ! (GET_RTX_CLASS (code
) == '<'
3648 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3649 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3651 rtx cop1
= const0_rtx
;
3652 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3654 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3657 /* Simplify the alternative arms; this may collapse the true and
3658 false arms to store-flag values. Be careful to use copy_rtx
3659 here since true_rtx or false_rtx might share RTL with x as a
3660 result of the if_then_else_cond call above. */
3661 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3662 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3664 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3665 is unlikely to be simpler. */
3666 if (general_operand (true_rtx
, VOIDmode
)
3667 && general_operand (false_rtx
, VOIDmode
))
3669 enum rtx_code reversed
;
3671 /* Restarting if we generate a store-flag expression will cause
3672 us to loop. Just drop through in this case. */
3674 /* If the result values are STORE_FLAG_VALUE and zero, we can
3675 just make the comparison operation. */
3676 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3677 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3678 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3679 && ((reversed
= reversed_comparison_code_parts
3680 (cond_code
, cond
, cop1
, NULL
))
3682 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3684 /* Likewise, we can make the negate of a comparison operation
3685 if the result values are - STORE_FLAG_VALUE and zero. */
3686 else if (GET_CODE (true_rtx
) == CONST_INT
3687 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3688 && false_rtx
== const0_rtx
)
3689 x
= simplify_gen_unary (NEG
, mode
,
3690 gen_binary (cond_code
, mode
, cond
,
3693 else if (GET_CODE (false_rtx
) == CONST_INT
3694 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3695 && true_rtx
== const0_rtx
3696 && ((reversed
= reversed_comparison_code_parts
3697 (cond_code
, cond
, cop1
, NULL
))
3699 x
= simplify_gen_unary (NEG
, mode
,
3700 gen_binary (reversed
, mode
,
3704 return gen_rtx_IF_THEN_ELSE (mode
,
3705 gen_binary (cond_code
, VOIDmode
,
3707 true_rtx
, false_rtx
);
3709 code
= GET_CODE (x
);
3710 op0_mode
= VOIDmode
;
3715 /* Try to fold this expression in case we have constants that weren't
3718 switch (GET_RTX_CLASS (code
))
3721 if (op0_mode
== VOIDmode
)
3722 op0_mode
= GET_MODE (XEXP (x
, 0));
3723 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3727 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3728 if (cmp_mode
== VOIDmode
)
3730 cmp_mode
= GET_MODE (XEXP (x
, 1));
3731 if (cmp_mode
== VOIDmode
)
3732 cmp_mode
= op0_mode
;
3734 temp
= simplify_relational_operation (code
, cmp_mode
,
3735 XEXP (x
, 0), XEXP (x
, 1));
3737 #ifdef FLOAT_STORE_FLAG_VALUE
3738 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3740 if (temp
== const0_rtx
)
3741 temp
= CONST0_RTX (mode
);
3743 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3750 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3754 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3755 XEXP (x
, 1), XEXP (x
, 2));
3762 code
= GET_CODE (temp
);
3763 op0_mode
= VOIDmode
;
3764 mode
= GET_MODE (temp
);
3767 /* First see if we can apply the inverse distributive law. */
3768 if (code
== PLUS
|| code
== MINUS
3769 || code
== AND
|| code
== IOR
|| code
== XOR
)
3771 x
= apply_distributive_law (x
);
3772 code
= GET_CODE (x
);
3773 op0_mode
= VOIDmode
;
3776 /* If CODE is an associative operation not otherwise handled, see if we
3777 can associate some operands. This can win if they are constants or
3778 if they are logically related (i.e. (a & b) & a). */
3779 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3780 || code
== AND
|| code
== IOR
|| code
== XOR
3781 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3782 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3783 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3785 if (GET_CODE (XEXP (x
, 0)) == code
)
3787 rtx other
= XEXP (XEXP (x
, 0), 0);
3788 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3789 rtx inner_op1
= XEXP (x
, 1);
3792 /* Make sure we pass the constant operand if any as the second
3793 one if this is a commutative operation. */
3794 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3796 rtx tem
= inner_op0
;
3797 inner_op0
= inner_op1
;
3800 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3801 : code
== DIV
? MULT
3803 mode
, inner_op0
, inner_op1
);
3805 /* For commutative operations, try the other pair if that one
3807 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3809 other
= XEXP (XEXP (x
, 0), 1);
3810 inner
= simplify_binary_operation (code
, mode
,
3811 XEXP (XEXP (x
, 0), 0),
3816 return gen_binary (code
, mode
, other
, inner
);
3820 /* A little bit of algebraic simplification here. */
3824 /* Ensure that our address has any ASHIFTs converted to MULT in case
3825 address-recognizing predicates are called later. */
3826 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3827 SUBST (XEXP (x
, 0), temp
);
3831 if (op0_mode
== VOIDmode
)
3832 op0_mode
= GET_MODE (SUBREG_REG (x
));
3834 /* See if this can be moved to simplify_subreg. */
3835 if (CONSTANT_P (SUBREG_REG (x
))
3836 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3837 /* Don't call gen_lowpart if the inner mode
3838 is VOIDmode and we cannot simplify it, as SUBREG without
3839 inner mode is invalid. */
3840 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3841 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3842 return gen_lowpart (mode
, SUBREG_REG (x
));
3844 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3848 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3854 /* Don't change the mode of the MEM if that would change the meaning
3856 if (GET_CODE (SUBREG_REG (x
)) == MEM
3857 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3858 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3859 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3861 /* Note that we cannot do any narrowing for non-constants since
3862 we might have been counting on using the fact that some bits were
3863 zero. We now do this in the SET. */
3868 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3869 && subreg_lowpart_p (XEXP (x
, 0))
3870 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3871 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3872 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3873 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3875 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3877 x
= gen_rtx_ROTATE (inner_mode
,
3878 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3880 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3881 return gen_lowpart (mode
, x
);
3884 /* Apply De Morgan's laws to reduce number of patterns for machines
3885 with negating logical insns (and-not, nand, etc.). If result has
3886 only one NOT, put it first, since that is how the patterns are
3889 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3891 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3892 enum machine_mode op_mode
;
3894 op_mode
= GET_MODE (in1
);
3895 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3897 op_mode
= GET_MODE (in2
);
3898 if (op_mode
== VOIDmode
)
3900 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3902 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3905 in2
= in1
; in1
= tem
;
3908 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3914 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3915 if (GET_CODE (XEXP (x
, 0)) == XOR
3916 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3917 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3918 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3920 temp
= expand_compound_operation (XEXP (x
, 0));
3922 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3923 replaced by (lshiftrt X C). This will convert
3924 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3926 if (GET_CODE (temp
) == ASHIFTRT
3927 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3928 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3929 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3930 INTVAL (XEXP (temp
, 1)));
3932 /* If X has only a single bit that might be nonzero, say, bit I, convert
3933 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3934 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3935 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3936 or a SUBREG of one since we'd be making the expression more
3937 complex if it was just a register. */
3939 if (GET_CODE (temp
) != REG
3940 && ! (GET_CODE (temp
) == SUBREG
3941 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3942 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3944 rtx temp1
= simplify_shift_const
3945 (NULL_RTX
, ASHIFTRT
, mode
,
3946 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3947 GET_MODE_BITSIZE (mode
) - 1 - i
),
3948 GET_MODE_BITSIZE (mode
) - 1 - i
);
3950 /* If all we did was surround TEMP with the two shifts, we
3951 haven't improved anything, so don't use it. Otherwise,
3952 we are better off with TEMP1. */
3953 if (GET_CODE (temp1
) != ASHIFTRT
3954 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3955 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3961 /* We can't handle truncation to a partial integer mode here
3962 because we don't know the real bitsize of the partial
3964 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3967 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3968 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3969 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3971 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3972 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3974 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3975 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3976 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3977 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3978 return XEXP (XEXP (x
, 0), 0);
3980 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3981 (OP:SI foo:SI) if OP is NEG or ABS. */
3982 if ((GET_CODE (XEXP (x
, 0)) == ABS
3983 || GET_CODE (XEXP (x
, 0)) == NEG
)
3984 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3985 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3986 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3987 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3988 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3990 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3992 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3993 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3994 && subreg_lowpart_p (XEXP (x
, 0)))
3995 return SUBREG_REG (XEXP (x
, 0));
3997 /* If we know that the value is already truncated, we can
3998 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3999 is nonzero for the corresponding modes. But don't do this
4000 for an (LSHIFTRT (MULT ...)) since this will cause problems
4001 with the umulXi3_highpart patterns. */
4002 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4003 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4004 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4005 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4006 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4007 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4008 return gen_lowpart (mode
, XEXP (x
, 0));
4010 /* A truncate of a comparison can be replaced with a subreg if
4011 STORE_FLAG_VALUE permits. This is like the previous test,
4012 but it works even if the comparison is done in a mode larger
4013 than HOST_BITS_PER_WIDE_INT. */
4014 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4015 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4016 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4017 return gen_lowpart (mode
, XEXP (x
, 0));
4019 /* Similarly, a truncate of a register whose value is a
4020 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4022 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4023 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4024 && (temp
= get_last_value (XEXP (x
, 0)))
4025 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4026 return gen_lowpart (mode
, XEXP (x
, 0));
4030 case FLOAT_TRUNCATE
:
4031 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4032 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4033 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4034 return XEXP (XEXP (x
, 0), 0);
4036 /* (float_truncate:SF (float_truncate:DF foo:XF))
4037 = (float_truncate:SF foo:XF).
4038 This may eliminate double rounding, so it is unsafe.
4040 (float_truncate:SF (float_extend:XF foo:DF))
4041 = (float_truncate:SF foo:DF).
4043 (float_truncate:DF (float_extend:XF foo:SF))
4044 = (float_extend:SF foo:DF). */
4045 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4046 && flag_unsafe_math_optimizations
)
4047 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4048 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4050 > GET_MODE_SIZE (mode
)
4051 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4053 XEXP (XEXP (x
, 0), 0), mode
);
4055 /* (float_truncate (float x)) is (float x) */
4056 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4057 && (flag_unsafe_math_optimizations
4058 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4059 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4060 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4061 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4062 return simplify_gen_unary (FLOAT
, mode
,
4063 XEXP (XEXP (x
, 0), 0),
4064 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4066 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4067 (OP:SF foo:SF) if OP is NEG or ABS. */
4068 if ((GET_CODE (XEXP (x
, 0)) == ABS
4069 || GET_CODE (XEXP (x
, 0)) == NEG
)
4070 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4071 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4072 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4073 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4075 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4076 is (float_truncate:SF x). */
4077 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4078 && subreg_lowpart_p (XEXP (x
, 0))
4079 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4080 return SUBREG_REG (XEXP (x
, 0));
4083 /* (float_extend (float_extend x)) is (float_extend x)
4085 (float_extend (float x)) is (float x) assuming that double
4086 rounding can't happen.
4088 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4089 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4090 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4091 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4092 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4093 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4094 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4095 XEXP (XEXP (x
, 0), 0),
4096 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4101 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4102 using cc0, in which case we want to leave it as a COMPARE
4103 so we can distinguish it from a register-register-copy. */
4104 if (XEXP (x
, 1) == const0_rtx
)
4107 /* x - 0 is the same as x unless x's mode has signed zeros and
4108 allows rounding towards -infinity. Under those conditions,
4110 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4111 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4112 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4118 /* (const (const X)) can become (const X). Do it this way rather than
4119 returning the inner CONST since CONST can be shared with a
4121 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4122 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4127 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4128 can add in an offset. find_split_point will split this address up
4129 again if it doesn't match. */
4130 if (GET_CODE (XEXP (x
, 0)) == HIGH
4131 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4137 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4139 if (GET_CODE (XEXP (x
, 0)) == MULT
4140 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4144 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4145 in2
= XEXP (XEXP (x
, 0), 1);
4146 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4147 gen_binary (MULT
, mode
, in1
, in2
));
4150 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4151 outermost. That's because that's the way indexed addresses are
4152 supposed to appear. This code used to check many more cases, but
4153 they are now checked elsewhere. */
4154 if (GET_CODE (XEXP (x
, 0)) == PLUS
4155 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4156 return gen_binary (PLUS
, mode
,
4157 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4159 XEXP (XEXP (x
, 0), 1));
4161 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4162 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4163 bit-field and can be replaced by either a sign_extend or a
4164 sign_extract. The `and' may be a zero_extend and the two
4165 <c>, -<c> constants may be reversed. */
4166 if (GET_CODE (XEXP (x
, 0)) == XOR
4167 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4168 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4169 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4170 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4171 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4172 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4173 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4174 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4175 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4176 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4177 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4178 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4179 == (unsigned int) i
+ 1))))
4180 return simplify_shift_const
4181 (NULL_RTX
, ASHIFTRT
, mode
,
4182 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4183 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4184 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4185 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4187 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4188 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4189 is 1. This produces better code than the alternative immediately
4191 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4192 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4193 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4194 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4195 XEXP (XEXP (x
, 0), 0),
4196 XEXP (XEXP (x
, 0), 1))))
4198 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4200 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4201 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4202 the bitsize of the mode - 1. This allows simplification of
4203 "a = (b & 8) == 0;" */
4204 if (XEXP (x
, 1) == constm1_rtx
4205 && GET_CODE (XEXP (x
, 0)) != REG
4206 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4207 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4208 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4209 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4210 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4211 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4212 GET_MODE_BITSIZE (mode
) - 1),
4213 GET_MODE_BITSIZE (mode
) - 1);
4215 /* If we are adding two things that have no bits in common, convert
4216 the addition into an IOR. This will often be further simplified,
4217 for example in cases like ((a & 1) + (a & 2)), which can
4220 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4221 && (nonzero_bits (XEXP (x
, 0), mode
)
4222 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4224 /* Try to simplify the expression further. */
4225 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4226 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4228 /* If we could, great. If not, do not go ahead with the IOR
4229 replacement, since PLUS appears in many special purpose
4230 address arithmetic instructions. */
4231 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4237 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4238 by reversing the comparison code if valid. */
4239 if (STORE_FLAG_VALUE
== 1
4240 && XEXP (x
, 0) == const1_rtx
4241 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4242 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4243 XEXP (XEXP (x
, 1), 0),
4244 XEXP (XEXP (x
, 1), 1))))
4247 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4248 (and <foo> (const_int pow2-1)) */
4249 if (GET_CODE (XEXP (x
, 1)) == AND
4250 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4251 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4252 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4253 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4254 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4256 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4258 if (GET_CODE (XEXP (x
, 1)) == MULT
4259 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4263 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4264 in2
= XEXP (XEXP (x
, 1), 1);
4265 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4269 /* Canonicalize (minus (neg A) (mult B C)) to
4270 (minus (mult (neg B) C) A). */
4271 if (GET_CODE (XEXP (x
, 1)) == MULT
4272 && GET_CODE (XEXP (x
, 0)) == NEG
)
4276 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4277 in2
= XEXP (XEXP (x
, 1), 1);
4278 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4279 XEXP (XEXP (x
, 0), 0));
4282 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4284 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4285 return gen_binary (MINUS
, mode
,
4286 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4287 XEXP (XEXP (x
, 1), 0)),
4288 XEXP (XEXP (x
, 1), 1));
4292 /* If we have (mult (plus A B) C), apply the distributive law and then
4293 the inverse distributive law to see if things simplify. This
4294 occurs mostly in addresses, often when unrolling loops. */
4296 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4298 x
= apply_distributive_law
4299 (gen_binary (PLUS
, mode
,
4300 gen_binary (MULT
, mode
,
4301 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4302 gen_binary (MULT
, mode
,
4303 XEXP (XEXP (x
, 0), 1),
4304 copy_rtx (XEXP (x
, 1)))));
4306 if (GET_CODE (x
) != MULT
)
4309 /* Try simplify a*(b/c) as (a*b)/c. */
4310 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4311 && GET_CODE (XEXP (x
, 0)) == DIV
)
4313 rtx tem
= simplify_binary_operation (MULT
, mode
,
4314 XEXP (XEXP (x
, 0), 0),
4317 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4322 /* If this is a divide by a power of two, treat it as a shift if
4323 its first operand is a shift. */
4324 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4325 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4326 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4327 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4328 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4329 || GET_CODE (XEXP (x
, 0)) == ROTATE
4330 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4331 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4335 case GT
: case GTU
: case GE
: case GEU
:
4336 case LT
: case LTU
: case LE
: case LEU
:
4337 case UNEQ
: case LTGT
:
4338 case UNGT
: case UNGE
:
4339 case UNLT
: case UNLE
:
4340 case UNORDERED
: case ORDERED
:
4341 /* If the first operand is a condition code, we can't do anything
4343 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4344 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4345 && ! CC0_P (XEXP (x
, 0))))
4347 rtx op0
= XEXP (x
, 0);
4348 rtx op1
= XEXP (x
, 1);
4349 enum rtx_code new_code
;
4351 if (GET_CODE (op0
) == COMPARE
)
4352 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4354 /* Simplify our comparison, if possible. */
4355 new_code
= simplify_comparison (code
, &op0
, &op1
);
4357 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4358 if only the low-order bit is possibly nonzero in X (such as when
4359 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4360 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4361 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4364 Remove any ZERO_EXTRACT we made when thinking this was a
4365 comparison. It may now be simpler to use, e.g., an AND. If a
4366 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4367 the call to make_compound_operation in the SET case. */
4369 if (STORE_FLAG_VALUE
== 1
4370 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4371 && op1
== const0_rtx
4372 && mode
== GET_MODE (op0
)
4373 && nonzero_bits (op0
, mode
) == 1)
4374 return gen_lowpart (mode
,
4375 expand_compound_operation (op0
));
4377 else if (STORE_FLAG_VALUE
== 1
4378 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4379 && op1
== const0_rtx
4380 && mode
== GET_MODE (op0
)
4381 && (num_sign_bit_copies (op0
, mode
)
4382 == GET_MODE_BITSIZE (mode
)))
4384 op0
= expand_compound_operation (op0
);
4385 return simplify_gen_unary (NEG
, mode
,
4386 gen_lowpart (mode
, op0
),
4390 else if (STORE_FLAG_VALUE
== 1
4391 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4392 && op1
== const0_rtx
4393 && mode
== GET_MODE (op0
)
4394 && nonzero_bits (op0
, mode
) == 1)
4396 op0
= expand_compound_operation (op0
);
4397 return gen_binary (XOR
, mode
,
4398 gen_lowpart (mode
, op0
),
4402 else if (STORE_FLAG_VALUE
== 1
4403 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4404 && op1
== const0_rtx
4405 && mode
== GET_MODE (op0
)
4406 && (num_sign_bit_copies (op0
, mode
)
4407 == GET_MODE_BITSIZE (mode
)))
4409 op0
= expand_compound_operation (op0
);
4410 return plus_constant (gen_lowpart (mode
, op0
), 1);
4413 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4415 if (STORE_FLAG_VALUE
== -1
4416 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4417 && op1
== const0_rtx
4418 && (num_sign_bit_copies (op0
, mode
)
4419 == GET_MODE_BITSIZE (mode
)))
4420 return gen_lowpart (mode
,
4421 expand_compound_operation (op0
));
4423 else if (STORE_FLAG_VALUE
== -1
4424 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4425 && op1
== const0_rtx
4426 && mode
== GET_MODE (op0
)
4427 && nonzero_bits (op0
, mode
) == 1)
4429 op0
= expand_compound_operation (op0
);
4430 return simplify_gen_unary (NEG
, mode
,
4431 gen_lowpart (mode
, op0
),
4435 else if (STORE_FLAG_VALUE
== -1
4436 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4437 && op1
== const0_rtx
4438 && mode
== GET_MODE (op0
)
4439 && (num_sign_bit_copies (op0
, mode
)
4440 == GET_MODE_BITSIZE (mode
)))
4442 op0
= expand_compound_operation (op0
);
4443 return simplify_gen_unary (NOT
, mode
,
4444 gen_lowpart (mode
, op0
),
4448 /* If X is 0/1, (eq X 0) is X-1. */
4449 else if (STORE_FLAG_VALUE
== -1
4450 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4451 && op1
== const0_rtx
4452 && mode
== GET_MODE (op0
)
4453 && nonzero_bits (op0
, mode
) == 1)
4455 op0
= expand_compound_operation (op0
);
4456 return plus_constant (gen_lowpart (mode
, op0
), -1);
4459 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4460 one bit that might be nonzero, we can convert (ne x 0) to
4461 (ashift x c) where C puts the bit in the sign bit. Remove any
4462 AND with STORE_FLAG_VALUE when we are done, since we are only
4463 going to test the sign bit. */
4464 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4465 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4466 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4467 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4468 && op1
== const0_rtx
4469 && mode
== GET_MODE (op0
)
4470 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4472 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4473 expand_compound_operation (op0
),
4474 GET_MODE_BITSIZE (mode
) - 1 - i
);
4475 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4481 /* If the code changed, return a whole new comparison. */
4482 if (new_code
!= code
)
4483 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4485 /* Otherwise, keep this operation, but maybe change its operands.
4486 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4487 SUBST (XEXP (x
, 0), op0
);
4488 SUBST (XEXP (x
, 1), op1
);
4493 return simplify_if_then_else (x
);
4499 /* If we are processing SET_DEST, we are done. */
4503 return expand_compound_operation (x
);
4506 return simplify_set (x
);
4511 return simplify_logical (x
, last
);
4514 /* (abs (neg <foo>)) -> (abs <foo>) */
4515 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4516 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4518 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4520 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4523 /* If operand is something known to be positive, ignore the ABS. */
4524 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4525 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4526 <= HOST_BITS_PER_WIDE_INT
)
4527 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4528 & ((HOST_WIDE_INT
) 1
4529 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4533 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4534 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4535 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4540 /* (ffs (*_extend <X>)) = (ffs <X>) */
4541 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4542 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4543 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4548 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4549 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4550 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4554 /* (float (sign_extend <X>)) = (float <X>). */
4555 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4556 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4564 /* If this is a shift by a constant amount, simplify it. */
4565 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4566 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4567 INTVAL (XEXP (x
, 1)));
4569 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4571 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4573 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4580 rtx op0
= XEXP (x
, 0);
4581 rtx op1
= XEXP (x
, 1);
4584 if (GET_CODE (op1
) != PARALLEL
)
4586 len
= XVECLEN (op1
, 0);
4588 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4589 && GET_CODE (op0
) == VEC_CONCAT
)
4591 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4593 /* Try to find the element in the VEC_CONCAT. */
4596 if (GET_MODE (op0
) == GET_MODE (x
))
4598 if (GET_CODE (op0
) == VEC_CONCAT
)
4600 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4601 if (op0_size
< offset
)
4602 op0
= XEXP (op0
, 0);
4606 op0
= XEXP (op0
, 1);
4624 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4627 simplify_if_then_else (rtx x
)
4629 enum machine_mode mode
= GET_MODE (x
);
4630 rtx cond
= XEXP (x
, 0);
4631 rtx true_rtx
= XEXP (x
, 1);
4632 rtx false_rtx
= XEXP (x
, 2);
4633 enum rtx_code true_code
= GET_CODE (cond
);
4634 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4637 enum rtx_code false_code
;
4640 /* Simplify storing of the truth value. */
4641 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4642 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4644 /* Also when the truth value has to be reversed. */
4646 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4647 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4651 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4652 in it is being compared against certain values. Get the true and false
4653 comparisons and see if that says anything about the value of each arm. */
4656 && ((false_code
= combine_reversed_comparison_code (cond
))
4658 && GET_CODE (XEXP (cond
, 0)) == REG
)
4661 rtx from
= XEXP (cond
, 0);
4662 rtx true_val
= XEXP (cond
, 1);
4663 rtx false_val
= true_val
;
4666 /* If FALSE_CODE is EQ, swap the codes and arms. */
4668 if (false_code
== EQ
)
4670 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4671 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4674 /* If we are comparing against zero and the expression being tested has
4675 only a single bit that might be nonzero, that is its value when it is
4676 not equal to zero. Similarly if it is known to be -1 or 0. */
4678 if (true_code
== EQ
&& true_val
== const0_rtx
4679 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4680 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4681 else if (true_code
== EQ
&& true_val
== const0_rtx
4682 && (num_sign_bit_copies (from
, GET_MODE (from
))
4683 == GET_MODE_BITSIZE (GET_MODE (from
))))
4684 false_code
= EQ
, false_val
= constm1_rtx
;
4686 /* Now simplify an arm if we know the value of the register in the
4687 branch and it is used in the arm. Be careful due to the potential
4688 of locally-shared RTL. */
4690 if (reg_mentioned_p (from
, true_rtx
))
4691 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4693 pc_rtx
, pc_rtx
, 0, 0);
4694 if (reg_mentioned_p (from
, false_rtx
))
4695 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4697 pc_rtx
, pc_rtx
, 0, 0);
4699 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4700 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4702 true_rtx
= XEXP (x
, 1);
4703 false_rtx
= XEXP (x
, 2);
4704 true_code
= GET_CODE (cond
);
4707 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4708 reversed, do so to avoid needing two sets of patterns for
4709 subtract-and-branch insns. Similarly if we have a constant in the true
4710 arm, the false arm is the same as the first operand of the comparison, or
4711 the false arm is more complicated than the true arm. */
4714 && combine_reversed_comparison_code (cond
) != UNKNOWN
4715 && (true_rtx
== pc_rtx
4716 || (CONSTANT_P (true_rtx
)
4717 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4718 || true_rtx
== const0_rtx
4719 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4720 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4721 || (GET_CODE (true_rtx
) == SUBREG
4722 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4723 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4724 || reg_mentioned_p (true_rtx
, false_rtx
)
4725 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4727 true_code
= reversed_comparison_code (cond
, NULL
);
4729 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4732 SUBST (XEXP (x
, 1), false_rtx
);
4733 SUBST (XEXP (x
, 2), true_rtx
);
4735 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4738 /* It is possible that the conditional has been simplified out. */
4739 true_code
= GET_CODE (cond
);
4740 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4743 /* If the two arms are identical, we don't need the comparison. */
4745 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4748 /* Convert a == b ? b : a to "a". */
4749 if (true_code
== EQ
&& ! side_effects_p (cond
)
4750 && !HONOR_NANS (mode
)
4751 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4752 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4754 else if (true_code
== NE
&& ! side_effects_p (cond
)
4755 && !HONOR_NANS (mode
)
4756 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4757 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4760 /* Look for cases where we have (abs x) or (neg (abs X)). */
4762 if (GET_MODE_CLASS (mode
) == MODE_INT
4763 && GET_CODE (false_rtx
) == NEG
4764 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4766 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4767 && ! side_effects_p (true_rtx
))
4772 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4776 simplify_gen_unary (NEG
, mode
,
4777 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4783 /* Look for MIN or MAX. */
4785 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4787 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4788 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4789 && ! side_effects_p (cond
))
4794 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4797 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4800 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4803 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4808 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4809 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4810 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4811 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4812 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4813 neither 1 or -1, but it isn't worth checking for. */
4815 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4817 && GET_MODE_CLASS (mode
) == MODE_INT
4818 && ! side_effects_p (x
))
4820 rtx t
= make_compound_operation (true_rtx
, SET
);
4821 rtx f
= make_compound_operation (false_rtx
, SET
);
4822 rtx cond_op0
= XEXP (cond
, 0);
4823 rtx cond_op1
= XEXP (cond
, 1);
4824 enum rtx_code op
= NIL
, extend_op
= NIL
;
4825 enum machine_mode m
= mode
;
4826 rtx z
= 0, c1
= NULL_RTX
;
4828 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4829 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4830 || GET_CODE (t
) == ASHIFT
4831 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4832 && rtx_equal_p (XEXP (t
, 0), f
))
4833 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4835 /* If an identity-zero op is commutative, check whether there
4836 would be a match if we swapped the operands. */
4837 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4838 || GET_CODE (t
) == XOR
)
4839 && rtx_equal_p (XEXP (t
, 1), f
))
4840 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4841 else if (GET_CODE (t
) == SIGN_EXTEND
4842 && (GET_CODE (XEXP (t
, 0)) == PLUS
4843 || GET_CODE (XEXP (t
, 0)) == MINUS
4844 || GET_CODE (XEXP (t
, 0)) == IOR
4845 || GET_CODE (XEXP (t
, 0)) == XOR
4846 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4847 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4848 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4849 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4850 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4851 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4852 && (num_sign_bit_copies (f
, GET_MODE (f
))
4854 (GET_MODE_BITSIZE (mode
)
4855 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4857 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4858 extend_op
= SIGN_EXTEND
;
4859 m
= GET_MODE (XEXP (t
, 0));
4861 else if (GET_CODE (t
) == SIGN_EXTEND
4862 && (GET_CODE (XEXP (t
, 0)) == PLUS
4863 || GET_CODE (XEXP (t
, 0)) == IOR
4864 || GET_CODE (XEXP (t
, 0)) == XOR
)
4865 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4866 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4867 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4868 && (num_sign_bit_copies (f
, GET_MODE (f
))
4870 (GET_MODE_BITSIZE (mode
)
4871 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4873 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4874 extend_op
= SIGN_EXTEND
;
4875 m
= GET_MODE (XEXP (t
, 0));
4877 else if (GET_CODE (t
) == ZERO_EXTEND
4878 && (GET_CODE (XEXP (t
, 0)) == PLUS
4879 || GET_CODE (XEXP (t
, 0)) == MINUS
4880 || GET_CODE (XEXP (t
, 0)) == IOR
4881 || GET_CODE (XEXP (t
, 0)) == XOR
4882 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4883 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4884 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4885 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4886 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4887 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4888 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4889 && ((nonzero_bits (f
, GET_MODE (f
))
4890 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4893 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4894 extend_op
= ZERO_EXTEND
;
4895 m
= GET_MODE (XEXP (t
, 0));
4897 else if (GET_CODE (t
) == ZERO_EXTEND
4898 && (GET_CODE (XEXP (t
, 0)) == PLUS
4899 || GET_CODE (XEXP (t
, 0)) == IOR
4900 || GET_CODE (XEXP (t
, 0)) == XOR
)
4901 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4902 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4903 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4904 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4905 && ((nonzero_bits (f
, GET_MODE (f
))
4906 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4909 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4910 extend_op
= ZERO_EXTEND
;
4911 m
= GET_MODE (XEXP (t
, 0));
4916 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4917 pc_rtx
, pc_rtx
, 0, 0);
4918 temp
= gen_binary (MULT
, m
, temp
,
4919 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4920 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4921 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
4923 if (extend_op
!= NIL
)
4924 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4930 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4931 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4932 negation of a single bit, we can convert this operation to a shift. We
4933 can actually do this more generally, but it doesn't seem worth it. */
4935 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4936 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4937 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4938 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4939 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4940 == GET_MODE_BITSIZE (mode
))
4941 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4943 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4944 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
4946 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4947 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4948 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4949 && GET_MODE (XEXP (cond
, 0)) == mode
4950 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4951 == nonzero_bits (XEXP (cond
, 0), mode
)
4952 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4953 return XEXP (cond
, 0);
4958 /* Simplify X, a SET expression. Return the new expression. */
4961 simplify_set (rtx x
)
4963 rtx src
= SET_SRC (x
);
4964 rtx dest
= SET_DEST (x
);
4965 enum machine_mode mode
4966 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4970 /* (set (pc) (return)) gets written as (return). */
4971 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4974 /* Now that we know for sure which bits of SRC we are using, see if we can
4975 simplify the expression for the object knowing that we only need the
4978 if (GET_MODE_CLASS (mode
) == MODE_INT
4979 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4981 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4982 SUBST (SET_SRC (x
), src
);
4985 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4986 the comparison result and try to simplify it unless we already have used
4987 undobuf.other_insn. */
4988 if ((GET_MODE_CLASS (mode
) == MODE_CC
4989 || GET_CODE (src
) == COMPARE
4991 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4992 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4993 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4994 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4996 enum rtx_code old_code
= GET_CODE (*cc_use
);
4997 enum rtx_code new_code
;
4999 int other_changed
= 0;
5000 enum machine_mode compare_mode
= GET_MODE (dest
);
5001 enum machine_mode tmp_mode
;
5003 if (GET_CODE (src
) == COMPARE
)
5004 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5006 op0
= src
, op1
= const0_rtx
;
5008 /* Check whether the comparison is known at compile time. */
5009 if (GET_MODE (op0
) != VOIDmode
)
5010 tmp_mode
= GET_MODE (op0
);
5011 else if (GET_MODE (op1
) != VOIDmode
)
5012 tmp_mode
= GET_MODE (op1
);
5014 tmp_mode
= compare_mode
;
5015 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5016 if (tmp
!= NULL_RTX
)
5018 rtx pat
= PATTERN (other_insn
);
5019 undobuf
.other_insn
= other_insn
;
5020 SUBST (*cc_use
, tmp
);
5022 /* Attempt to simplify CC user. */
5023 if (GET_CODE (pat
) == SET
)
5025 rtx
new = simplify_rtx (SET_SRC (pat
));
5026 if (new != NULL_RTX
)
5027 SUBST (SET_SRC (pat
), new);
5030 /* Convert X into a no-op move. */
5031 SUBST (SET_DEST (x
), pc_rtx
);
5032 SUBST (SET_SRC (x
), pc_rtx
);
5036 /* Simplify our comparison, if possible. */
5037 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5039 #ifdef SELECT_CC_MODE
5040 /* If this machine has CC modes other than CCmode, check to see if we
5041 need to use a different CC mode here. */
5042 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5045 /* If the mode changed, we have to change SET_DEST, the mode in the
5046 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5047 a hard register, just build new versions with the proper mode. If it
5048 is a pseudo, we lose unless it is only time we set the pseudo, in
5049 which case we can safely change its mode. */
5050 if (compare_mode
!= GET_MODE (dest
))
5052 unsigned int regno
= REGNO (dest
);
5053 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5055 if (regno
< FIRST_PSEUDO_REGISTER
5056 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5058 if (regno
>= FIRST_PSEUDO_REGISTER
)
5059 SUBST (regno_reg_rtx
[regno
], new_dest
);
5061 SUBST (SET_DEST (x
), new_dest
);
5062 SUBST (XEXP (*cc_use
, 0), new_dest
);
5069 #endif /* SELECT_CC_MODE */
5071 /* If the code changed, we have to build a new comparison in
5072 undobuf.other_insn. */
5073 if (new_code
!= old_code
)
5075 int other_changed_previously
= other_changed
;
5076 unsigned HOST_WIDE_INT mask
;
5078 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5082 /* If the only change we made was to change an EQ into an NE or
5083 vice versa, OP0 has only one bit that might be nonzero, and OP1
5084 is zero, check if changing the user of the condition code will
5085 produce a valid insn. If it won't, we can keep the original code
5086 in that insn by surrounding our operation with an XOR. */
5088 if (((old_code
== NE
&& new_code
== EQ
)
5089 || (old_code
== EQ
&& new_code
== NE
))
5090 && ! other_changed_previously
&& op1
== const0_rtx
5091 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5092 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5094 rtx pat
= PATTERN (other_insn
), note
= 0;
5096 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5097 && ! check_asm_operands (pat
)))
5099 PUT_CODE (*cc_use
, old_code
);
5102 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5108 undobuf
.other_insn
= other_insn
;
5111 /* If we are now comparing against zero, change our source if
5112 needed. If we do not use cc0, we always have a COMPARE. */
5113 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5115 SUBST (SET_SRC (x
), op0
);
5121 /* Otherwise, if we didn't previously have a COMPARE in the
5122 correct mode, we need one. */
5123 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5125 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5130 /* Otherwise, update the COMPARE if needed. */
5131 SUBST (XEXP (src
, 0), op0
);
5132 SUBST (XEXP (src
, 1), op1
);
5137 /* Get SET_SRC in a form where we have placed back any
5138 compound expressions. Then do the checks below. */
5139 src
= make_compound_operation (src
, SET
);
5140 SUBST (SET_SRC (x
), src
);
5143 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5144 and X being a REG or (subreg (reg)), we may be able to convert this to
5145 (set (subreg:m2 x) (op)).
5147 We can always do this if M1 is narrower than M2 because that means that
5148 we only care about the low bits of the result.
5150 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5151 perform a narrower operation than requested since the high-order bits will
5152 be undefined. On machine where it is defined, this transformation is safe
5153 as long as M1 and M2 have the same number of words. */
5155 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5156 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5157 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5159 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5160 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5161 #ifndef WORD_REGISTER_OPERATIONS
5162 && (GET_MODE_SIZE (GET_MODE (src
))
5163 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5165 #ifdef CANNOT_CHANGE_MODE_CLASS
5166 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5167 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5168 GET_MODE (SUBREG_REG (src
)),
5171 && (GET_CODE (dest
) == REG
5172 || (GET_CODE (dest
) == SUBREG
5173 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5175 SUBST (SET_DEST (x
),
5176 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5178 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5180 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5184 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5187 && GET_CODE (src
) == SUBREG
5188 && subreg_lowpart_p (src
)
5189 && (GET_MODE_BITSIZE (GET_MODE (src
))
5190 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5192 rtx inner
= SUBREG_REG (src
);
5193 enum machine_mode inner_mode
= GET_MODE (inner
);
5195 /* Here we make sure that we don't have a sign bit on. */
5196 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5197 && (nonzero_bits (inner
, inner_mode
)
5198 < ((unsigned HOST_WIDE_INT
) 1
5199 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5201 SUBST (SET_SRC (x
), inner
);
5207 #ifdef LOAD_EXTEND_OP
5208 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5209 would require a paradoxical subreg. Replace the subreg with a
5210 zero_extend to avoid the reload that would otherwise be required. */
5212 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5213 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5214 && SUBREG_BYTE (src
) == 0
5215 && (GET_MODE_SIZE (GET_MODE (src
))
5216 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5217 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5220 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5221 GET_MODE (src
), SUBREG_REG (src
)));
5227 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5228 are comparing an item known to be 0 or -1 against 0, use a logical
5229 operation instead. Check for one of the arms being an IOR of the other
5230 arm with some value. We compute three terms to be IOR'ed together. In
5231 practice, at most two will be nonzero. Then we do the IOR's. */
5233 if (GET_CODE (dest
) != PC
5234 && GET_CODE (src
) == IF_THEN_ELSE
5235 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5236 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5237 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5238 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5239 #ifdef HAVE_conditional_move
5240 && ! can_conditionally_move_p (GET_MODE (src
))
5242 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5243 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5244 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5245 && ! side_effects_p (src
))
5247 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5248 ? XEXP (src
, 1) : XEXP (src
, 2));
5249 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5250 ? XEXP (src
, 2) : XEXP (src
, 1));
5251 rtx term1
= const0_rtx
, term2
, term3
;
5253 if (GET_CODE (true_rtx
) == IOR
5254 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5255 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5256 else if (GET_CODE (true_rtx
) == IOR
5257 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5258 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5259 else if (GET_CODE (false_rtx
) == IOR
5260 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5261 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5262 else if (GET_CODE (false_rtx
) == IOR
5263 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5264 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5266 term2
= gen_binary (AND
, GET_MODE (src
),
5267 XEXP (XEXP (src
, 0), 0), true_rtx
);
5268 term3
= gen_binary (AND
, GET_MODE (src
),
5269 simplify_gen_unary (NOT
, GET_MODE (src
),
5270 XEXP (XEXP (src
, 0), 0),
5275 gen_binary (IOR
, GET_MODE (src
),
5276 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5282 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5283 whole thing fail. */
5284 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5286 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5289 /* Convert this into a field assignment operation, if possible. */
5290 return make_field_assignment (x
);
5293 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5294 result. LAST is nonzero if this is the last retry. */
5297 simplify_logical (rtx x
, int last
)
5299 enum machine_mode mode
= GET_MODE (x
);
5300 rtx op0
= XEXP (x
, 0);
5301 rtx op1
= XEXP (x
, 1);
5304 switch (GET_CODE (x
))
5307 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5308 insn (and may simplify more). */
5309 if (GET_CODE (op0
) == XOR
5310 && rtx_equal_p (XEXP (op0
, 0), op1
)
5311 && ! side_effects_p (op1
))
5312 x
= gen_binary (AND
, mode
,
5313 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5316 if (GET_CODE (op0
) == XOR
5317 && rtx_equal_p (XEXP (op0
, 1), op1
)
5318 && ! side_effects_p (op1
))
5319 x
= gen_binary (AND
, mode
,
5320 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5323 /* Similarly for (~(A ^ B)) & A. */
5324 if (GET_CODE (op0
) == NOT
5325 && GET_CODE (XEXP (op0
, 0)) == XOR
5326 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5327 && ! side_effects_p (op1
))
5328 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5330 if (GET_CODE (op0
) == NOT
5331 && GET_CODE (XEXP (op0
, 0)) == XOR
5332 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5333 && ! side_effects_p (op1
))
5334 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5336 /* We can call simplify_and_const_int only if we don't lose
5337 any (sign) bits when converting INTVAL (op1) to
5338 "unsigned HOST_WIDE_INT". */
5339 if (GET_CODE (op1
) == CONST_INT
5340 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5341 || INTVAL (op1
) > 0))
5343 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5345 /* If we have (ior (and (X C1) C2)) and the next restart would be
5346 the last, simplify this by making C1 as small as possible
5349 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5350 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5351 && GET_CODE (op1
) == CONST_INT
)
5352 return gen_binary (IOR
, mode
,
5353 gen_binary (AND
, mode
, XEXP (op0
, 0),
5354 GEN_INT (INTVAL (XEXP (op0
, 1))
5355 & ~INTVAL (op1
))), op1
);
5357 if (GET_CODE (x
) != AND
)
5360 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5361 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5362 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5365 /* Convert (A | B) & A to A. */
5366 if (GET_CODE (op0
) == IOR
5367 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5368 || rtx_equal_p (XEXP (op0
, 1), op1
))
5369 && ! side_effects_p (XEXP (op0
, 0))
5370 && ! side_effects_p (XEXP (op0
, 1)))
5373 /* In the following group of tests (and those in case IOR below),
5374 we start with some combination of logical operations and apply
5375 the distributive law followed by the inverse distributive law.
5376 Most of the time, this results in no change. However, if some of
5377 the operands are the same or inverses of each other, simplifications
5380 For example, (and (ior A B) (not B)) can occur as the result of
5381 expanding a bit field assignment. When we apply the distributive
5382 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5383 which then simplifies to (and (A (not B))).
5385 If we have (and (ior A B) C), apply the distributive law and then
5386 the inverse distributive law to see if things simplify. */
5388 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5390 x
= apply_distributive_law
5391 (gen_binary (GET_CODE (op0
), mode
,
5392 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5393 gen_binary (AND
, mode
, XEXP (op0
, 1),
5395 if (GET_CODE (x
) != AND
)
5399 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5400 return apply_distributive_law
5401 (gen_binary (GET_CODE (op1
), mode
,
5402 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5403 gen_binary (AND
, mode
, XEXP (op1
, 1),
5406 /* Similarly, taking advantage of the fact that
5407 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5409 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5410 return apply_distributive_law
5411 (gen_binary (XOR
, mode
,
5412 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5413 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5416 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5417 return apply_distributive_law
5418 (gen_binary (XOR
, mode
,
5419 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5420 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5424 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5425 if (GET_CODE (op1
) == CONST_INT
5426 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5427 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5430 /* Convert (A & B) | A to A. */
5431 if (GET_CODE (op0
) == AND
5432 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5433 || rtx_equal_p (XEXP (op0
, 1), op1
))
5434 && ! side_effects_p (XEXP (op0
, 0))
5435 && ! side_effects_p (XEXP (op0
, 1)))
5438 /* If we have (ior (and A B) C), apply the distributive law and then
5439 the inverse distributive law to see if things simplify. */
5441 if (GET_CODE (op0
) == AND
)
5443 x
= apply_distributive_law
5444 (gen_binary (AND
, mode
,
5445 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5446 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5449 if (GET_CODE (x
) != IOR
)
5453 if (GET_CODE (op1
) == AND
)
5455 x
= apply_distributive_law
5456 (gen_binary (AND
, mode
,
5457 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5458 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5461 if (GET_CODE (x
) != IOR
)
5465 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5466 mode size to (rotate A CX). */
5468 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5469 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5470 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5471 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5472 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5473 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5474 == GET_MODE_BITSIZE (mode
)))
5475 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5476 (GET_CODE (op0
) == ASHIFT
5477 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5479 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5480 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5481 does not affect any of the bits in OP1, it can really be done
5482 as a PLUS and we can associate. We do this by seeing if OP1
5483 can be safely shifted left C bits. */
5484 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5485 && GET_CODE (XEXP (op0
, 0)) == PLUS
5486 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5487 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5488 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5490 int count
= INTVAL (XEXP (op0
, 1));
5491 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5493 if (mask
>> count
== INTVAL (op1
)
5494 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5496 SUBST (XEXP (XEXP (op0
, 0), 1),
5497 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5504 /* If we are XORing two things that have no bits in common,
5505 convert them into an IOR. This helps to detect rotation encoded
5506 using those methods and possibly other simplifications. */
5508 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5509 && (nonzero_bits (op0
, mode
)
5510 & nonzero_bits (op1
, mode
)) == 0)
5511 return (gen_binary (IOR
, mode
, op0
, op1
));
5513 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5514 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5517 int num_negated
= 0;
5519 if (GET_CODE (op0
) == NOT
)
5520 num_negated
++, op0
= XEXP (op0
, 0);
5521 if (GET_CODE (op1
) == NOT
)
5522 num_negated
++, op1
= XEXP (op1
, 0);
5524 if (num_negated
== 2)
5526 SUBST (XEXP (x
, 0), op0
);
5527 SUBST (XEXP (x
, 1), op1
);
5529 else if (num_negated
== 1)
5531 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5535 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5536 correspond to a machine insn or result in further simplifications
5537 if B is a constant. */
5539 if (GET_CODE (op0
) == AND
5540 && rtx_equal_p (XEXP (op0
, 1), op1
)
5541 && ! side_effects_p (op1
))
5542 return gen_binary (AND
, mode
,
5543 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5546 else if (GET_CODE (op0
) == AND
5547 && rtx_equal_p (XEXP (op0
, 0), op1
)
5548 && ! side_effects_p (op1
))
5549 return gen_binary (AND
, mode
,
5550 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5553 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5554 comparison if STORE_FLAG_VALUE is 1. */
5555 if (STORE_FLAG_VALUE
== 1
5556 && op1
== const1_rtx
5557 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5558 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5562 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5563 is (lt foo (const_int 0)), so we can perform the above
5564 simplification if STORE_FLAG_VALUE is 1. */
5566 if (STORE_FLAG_VALUE
== 1
5567 && op1
== const1_rtx
5568 && GET_CODE (op0
) == LSHIFTRT
5569 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5570 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5571 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5573 /* (xor (comparison foo bar) (const_int sign-bit))
5574 when STORE_FLAG_VALUE is the sign bit. */
5575 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5576 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5577 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5578 && op1
== const_true_rtx
5579 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5580 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5593 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5594 operations" because they can be replaced with two more basic operations.
5595 ZERO_EXTEND is also considered "compound" because it can be replaced with
5596 an AND operation, which is simpler, though only one operation.
5598 The function expand_compound_operation is called with an rtx expression
5599 and will convert it to the appropriate shifts and AND operations,
5600 simplifying at each stage.
5602 The function make_compound_operation is called to convert an expression
5603 consisting of shifts and ANDs into the equivalent compound expression.
5604 It is the inverse of this function, loosely speaking. */
5607 expand_compound_operation (rtx x
)
5609 unsigned HOST_WIDE_INT pos
= 0, len
;
5611 unsigned int modewidth
;
5614 switch (GET_CODE (x
))
5619 /* We can't necessarily use a const_int for a multiword mode;
5620 it depends on implicitly extending the value.
5621 Since we don't know the right way to extend it,
5622 we can't tell whether the implicit way is right.
5624 Even for a mode that is no wider than a const_int,
5625 we can't win, because we need to sign extend one of its bits through
5626 the rest of it, and we don't know which bit. */
5627 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5630 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5631 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5632 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5633 reloaded. If not for that, MEM's would very rarely be safe.
5635 Reject MODEs bigger than a word, because we might not be able
5636 to reference a two-register group starting with an arbitrary register
5637 (and currently gen_lowpart might crash for a SUBREG). */
5639 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5642 /* Reject MODEs that aren't scalar integers because turning vector
5643 or complex modes into shifts causes problems. */
5645 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5648 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5649 /* If the inner object has VOIDmode (the only way this can happen
5650 is if it is an ASM_OPERANDS), we can't do anything since we don't
5651 know how much masking to do. */
5660 /* If the operand is a CLOBBER, just return it. */
5661 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5664 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5665 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5666 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5669 /* Reject MODEs that aren't scalar integers because turning vector
5670 or complex modes into shifts causes problems. */
5672 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5675 len
= INTVAL (XEXP (x
, 1));
5676 pos
= INTVAL (XEXP (x
, 2));
5678 /* If this goes outside the object being extracted, replace the object
5679 with a (use (mem ...)) construct that only combine understands
5680 and is used only for this purpose. */
5681 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5682 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5684 if (BITS_BIG_ENDIAN
)
5685 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5692 /* Convert sign extension to zero extension, if we know that the high
5693 bit is not set, as this is easier to optimize. It will be converted
5694 back to cheaper alternative in make_extraction. */
5695 if (GET_CODE (x
) == SIGN_EXTEND
5696 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5697 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5698 & ~(((unsigned HOST_WIDE_INT
)
5699 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5703 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5704 rtx temp2
= expand_compound_operation (temp
);
5706 /* Make sure this is a profitable operation. */
5707 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5709 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5715 /* We can optimize some special cases of ZERO_EXTEND. */
5716 if (GET_CODE (x
) == ZERO_EXTEND
)
5718 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5719 know that the last value didn't have any inappropriate bits
5721 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5722 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5723 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5724 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5725 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5726 return XEXP (XEXP (x
, 0), 0);
5728 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5729 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5730 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5731 && subreg_lowpart_p (XEXP (x
, 0))
5732 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5733 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5734 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5735 return SUBREG_REG (XEXP (x
, 0));
5737 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5738 is a comparison and STORE_FLAG_VALUE permits. This is like
5739 the first case, but it works even when GET_MODE (x) is larger
5740 than HOST_WIDE_INT. */
5741 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5742 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5743 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5744 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5745 <= HOST_BITS_PER_WIDE_INT
)
5746 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5747 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5748 return XEXP (XEXP (x
, 0), 0);
5750 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5751 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5752 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5753 && subreg_lowpart_p (XEXP (x
, 0))
5754 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5755 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5756 <= HOST_BITS_PER_WIDE_INT
)
5757 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5758 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5759 return SUBREG_REG (XEXP (x
, 0));
5763 /* If we reach here, we want to return a pair of shifts. The inner
5764 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5765 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5766 logical depending on the value of UNSIGNEDP.
5768 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5769 converted into an AND of a shift.
5771 We must check for the case where the left shift would have a negative
5772 count. This can happen in a case like (x >> 31) & 255 on machines
5773 that can't shift by a constant. On those machines, we would first
5774 combine the shift with the AND to produce a variable-position
5775 extraction. Then the constant of 31 would be substituted in to produce
5776 a such a position. */
5778 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5779 if (modewidth
+ len
>= pos
)
5780 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5782 simplify_shift_const (NULL_RTX
, ASHIFT
,
5785 modewidth
- pos
- len
),
5788 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5789 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5790 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5793 ((HOST_WIDE_INT
) 1 << len
) - 1);
5795 /* Any other cases we can't handle. */
5798 /* If we couldn't do this for some reason, return the original
5800 if (GET_CODE (tem
) == CLOBBER
)
5806 /* X is a SET which contains an assignment of one object into
5807 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5808 or certain SUBREGS). If possible, convert it into a series of
5811 We half-heartedly support variable positions, but do not at all
5812 support variable lengths. */
5815 expand_field_assignment (rtx x
)
5818 rtx pos
; /* Always counts from low bit. */
5821 enum machine_mode compute_mode
;
5823 /* Loop until we find something we can't simplify. */
5826 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5827 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5829 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5830 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5831 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5833 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5834 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5836 inner
= XEXP (SET_DEST (x
), 0);
5837 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5838 pos
= XEXP (SET_DEST (x
), 2);
5840 /* If the position is constant and spans the width of INNER,
5841 surround INNER with a USE to indicate this. */
5842 if (GET_CODE (pos
) == CONST_INT
5843 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5844 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5846 if (BITS_BIG_ENDIAN
)
5848 if (GET_CODE (pos
) == CONST_INT
)
5849 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5851 else if (GET_CODE (pos
) == MINUS
5852 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5853 && (INTVAL (XEXP (pos
, 1))
5854 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5855 /* If position is ADJUST - X, new position is X. */
5856 pos
= XEXP (pos
, 0);
5858 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5859 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5865 /* A SUBREG between two modes that occupy the same numbers of words
5866 can be done by moving the SUBREG to the source. */
5867 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5868 /* We need SUBREGs to compute nonzero_bits properly. */
5869 && nonzero_sign_valid
5870 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5871 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5872 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5873 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5875 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5877 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5884 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5885 inner
= SUBREG_REG (inner
);
5887 compute_mode
= GET_MODE (inner
);
5889 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5890 if (! SCALAR_INT_MODE_P (compute_mode
))
5892 enum machine_mode imode
;
5894 /* Don't do anything for vector or complex integral types. */
5895 if (! FLOAT_MODE_P (compute_mode
))
5898 /* Try to find an integral mode to pun with. */
5899 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5900 if (imode
== BLKmode
)
5903 compute_mode
= imode
;
5904 inner
= gen_lowpart (imode
, inner
);
5907 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5908 if (len
< HOST_BITS_PER_WIDE_INT
)
5909 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5913 /* Now compute the equivalent expression. Make a copy of INNER
5914 for the SET_DEST in case it is a MEM into which we will substitute;
5915 we don't want shared RTL in that case. */
5917 (VOIDmode
, copy_rtx (inner
),
5918 gen_binary (IOR
, compute_mode
,
5919 gen_binary (AND
, compute_mode
,
5920 simplify_gen_unary (NOT
, compute_mode
,
5926 gen_binary (ASHIFT
, compute_mode
,
5927 gen_binary (AND
, compute_mode
,
5929 (compute_mode
, SET_SRC (x
)),
5937 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5938 it is an RTX that represents a variable starting position; otherwise,
5939 POS is the (constant) starting bit position (counted from the LSB).
5941 INNER may be a USE. This will occur when we started with a bitfield
5942 that went outside the boundary of the object in memory, which is
5943 allowed on most machines. To isolate this case, we produce a USE
5944 whose mode is wide enough and surround the MEM with it. The only
5945 code that understands the USE is this routine. If it is not removed,
5946 it will cause the resulting insn not to match.
5948 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5951 IN_DEST is nonzero if this is a reference in the destination of a
5952 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5953 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5956 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5957 ZERO_EXTRACT should be built even for bits starting at bit 0.
5959 MODE is the desired mode of the result (if IN_DEST == 0).
5961 The result is an RTX for the extraction or NULL_RTX if the target
5965 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5966 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5967 int in_dest
, int in_compare
)
5969 /* This mode describes the size of the storage area
5970 to fetch the overall value from. Within that, we
5971 ignore the POS lowest bits, etc. */
5972 enum machine_mode is_mode
= GET_MODE (inner
);
5973 enum machine_mode inner_mode
;
5974 enum machine_mode wanted_inner_mode
= byte_mode
;
5975 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5976 enum machine_mode pos_mode
= word_mode
;
5977 enum machine_mode extraction_mode
= word_mode
;
5978 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5981 rtx orig_pos_rtx
= pos_rtx
;
5982 HOST_WIDE_INT orig_pos
;
5984 /* Get some information about INNER and get the innermost object. */
5985 if (GET_CODE (inner
) == USE
)
5986 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5987 /* We don't need to adjust the position because we set up the USE
5988 to pretend that it was a full-word object. */
5989 spans_byte
= 1, inner
= XEXP (inner
, 0);
5990 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5992 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5993 consider just the QI as the memory to extract from.
5994 The subreg adds or removes high bits; its mode is
5995 irrelevant to the meaning of this extraction,
5996 since POS and LEN count from the lsb. */
5997 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5998 is_mode
= GET_MODE (SUBREG_REG (inner
));
5999 inner
= SUBREG_REG (inner
);
6001 else if (GET_CODE (inner
) == ASHIFT
6002 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6003 && pos_rtx
== 0 && pos
== 0
6004 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6006 /* We're extracting the least significant bits of an rtx
6007 (ashift X (const_int C)), where LEN > C. Extract the
6008 least significant (LEN - C) bits of X, giving an rtx
6009 whose mode is MODE, then shift it left C times. */
6010 new = make_extraction (mode
, XEXP (inner
, 0),
6011 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6012 unsignedp
, in_dest
, in_compare
);
6014 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6017 inner_mode
= GET_MODE (inner
);
6019 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6020 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6022 /* See if this can be done without an extraction. We never can if the
6023 width of the field is not the same as that of some integer mode. For
6024 registers, we can only avoid the extraction if the position is at the
6025 low-order bit and this is either not in the destination or we have the
6026 appropriate STRICT_LOW_PART operation available.
6028 For MEM, we can avoid an extract if the field starts on an appropriate
6029 boundary and we can change the mode of the memory reference. However,
6030 we cannot directly access the MEM if we have a USE and the underlying
6031 MEM is not TMODE. This combination means that MEM was being used in a
6032 context where bits outside its mode were being referenced; that is only
6033 valid in bit-field insns. */
6035 if (tmode
!= BLKmode
6036 && ! (spans_byte
&& inner_mode
!= tmode
)
6037 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6038 && GET_CODE (inner
) != MEM
6040 || (GET_CODE (inner
) == REG
6041 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6042 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6044 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6045 : BITS_PER_UNIT
)) == 0
6046 /* We can't do this if we are widening INNER_MODE (it
6047 may not be aligned, for one thing). */
6048 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6049 && (inner_mode
== tmode
6050 || (! mode_dependent_address_p (XEXP (inner
, 0))
6051 && ! MEM_VOLATILE_P (inner
))))))
6053 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6054 field. If the original and current mode are the same, we need not
6055 adjust the offset. Otherwise, we do if bytes big endian.
6057 If INNER is not a MEM, get a piece consisting of just the field
6058 of interest (in this case POS % BITS_PER_WORD must be 0). */
6060 if (GET_CODE (inner
) == MEM
)
6062 HOST_WIDE_INT offset
;
6064 /* POS counts from lsb, but make OFFSET count in memory order. */
6065 if (BYTES_BIG_ENDIAN
)
6066 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6068 offset
= pos
/ BITS_PER_UNIT
;
6070 new = adjust_address_nv (inner
, tmode
, offset
);
6072 else if (GET_CODE (inner
) == REG
)
6074 if (tmode
!= inner_mode
)
6076 /* We can't call gen_lowpart in a DEST since we
6077 always want a SUBREG (see below) and it would sometimes
6078 return a new hard register. */
6081 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6083 if (WORDS_BIG_ENDIAN
6084 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6085 final_word
= ((GET_MODE_SIZE (inner_mode
)
6086 - GET_MODE_SIZE (tmode
))
6087 / UNITS_PER_WORD
) - final_word
;
6089 final_word
*= UNITS_PER_WORD
;
6090 if (BYTES_BIG_ENDIAN
&&
6091 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6092 final_word
+= (GET_MODE_SIZE (inner_mode
)
6093 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6095 /* Avoid creating invalid subregs, for example when
6096 simplifying (x>>32)&255. */
6097 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6100 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6103 new = gen_lowpart (tmode
, inner
);
6109 new = force_to_mode (inner
, tmode
,
6110 len
>= HOST_BITS_PER_WIDE_INT
6111 ? ~(unsigned HOST_WIDE_INT
) 0
6112 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6115 /* If this extraction is going into the destination of a SET,
6116 make a STRICT_LOW_PART unless we made a MEM. */
6119 return (GET_CODE (new) == MEM
? new
6120 : (GET_CODE (new) != SUBREG
6121 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6122 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6127 if (GET_CODE (new) == CONST_INT
)
6128 return gen_int_mode (INTVAL (new), mode
);
6130 /* If we know that no extraneous bits are set, and that the high
6131 bit is not set, convert the extraction to the cheaper of
6132 sign and zero extension, that are equivalent in these cases. */
6133 if (flag_expensive_optimizations
6134 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6135 && ((nonzero_bits (new, tmode
)
6136 & ~(((unsigned HOST_WIDE_INT
)
6137 GET_MODE_MASK (tmode
))
6141 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6142 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6144 /* Prefer ZERO_EXTENSION, since it gives more information to
6146 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6151 /* Otherwise, sign- or zero-extend unless we already are in the
6154 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6158 /* Unless this is a COMPARE or we have a funny memory reference,
6159 don't do anything with zero-extending field extracts starting at
6160 the low-order bit since they are simple AND operations. */
6161 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6162 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6165 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6166 we would be spanning bytes or if the position is not a constant and the
6167 length is not 1. In all other cases, we would only be going outside
6168 our object in cases when an original shift would have been
6170 if (! spans_byte
&& GET_CODE (inner
) == MEM
6171 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6172 || (pos_rtx
!= 0 && len
!= 1)))
6175 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6176 and the mode for the result. */
6177 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6179 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6180 pos_mode
= mode_for_extraction (EP_insv
, 2);
6181 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6184 if (! in_dest
&& unsignedp
6185 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6187 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6188 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6189 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6192 if (! in_dest
&& ! unsignedp
6193 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6195 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6196 pos_mode
= mode_for_extraction (EP_extv
, 3);
6197 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6200 /* Never narrow an object, since that might not be safe. */
6202 if (mode
!= VOIDmode
6203 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6204 extraction_mode
= mode
;
6206 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6207 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6208 pos_mode
= GET_MODE (pos_rtx
);
6210 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6211 if we have to change the mode of memory and cannot, the desired mode is
6213 if (GET_CODE (inner
) != MEM
)
6214 wanted_inner_mode
= wanted_inner_reg_mode
;
6215 else if (inner_mode
!= wanted_inner_mode
6216 && (mode_dependent_address_p (XEXP (inner
, 0))
6217 || MEM_VOLATILE_P (inner
)))
6218 wanted_inner_mode
= extraction_mode
;
6222 if (BITS_BIG_ENDIAN
)
6224 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6225 BITS_BIG_ENDIAN style. If position is constant, compute new
6226 position. Otherwise, build subtraction.
6227 Note that POS is relative to the mode of the original argument.
6228 If it's a MEM we need to recompute POS relative to that.
6229 However, if we're extracting from (or inserting into) a register,
6230 we want to recompute POS relative to wanted_inner_mode. */
6231 int width
= (GET_CODE (inner
) == MEM
6232 ? GET_MODE_BITSIZE (is_mode
)
6233 : GET_MODE_BITSIZE (wanted_inner_mode
));
6236 pos
= width
- len
- pos
;
6239 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6240 /* POS may be less than 0 now, but we check for that below.
6241 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6244 /* If INNER has a wider mode, make it smaller. If this is a constant
6245 extract, try to adjust the byte to point to the byte containing
6247 if (wanted_inner_mode
!= VOIDmode
6248 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6249 && ((GET_CODE (inner
) == MEM
6250 && (inner_mode
== wanted_inner_mode
6251 || (! mode_dependent_address_p (XEXP (inner
, 0))
6252 && ! MEM_VOLATILE_P (inner
))))))
6256 /* The computations below will be correct if the machine is big
6257 endian in both bits and bytes or little endian in bits and bytes.
6258 If it is mixed, we must adjust. */
6260 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6261 adjust OFFSET to compensate. */
6262 if (BYTES_BIG_ENDIAN
6264 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6265 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6267 /* If this is a constant position, we can move to the desired byte. */
6270 offset
+= pos
/ BITS_PER_UNIT
;
6271 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6274 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6276 && is_mode
!= wanted_inner_mode
)
6277 offset
= (GET_MODE_SIZE (is_mode
)
6278 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6280 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6281 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6284 /* If INNER is not memory, we can always get it into the proper mode. If we
6285 are changing its mode, POS must be a constant and smaller than the size
6287 else if (GET_CODE (inner
) != MEM
)
6289 if (GET_MODE (inner
) != wanted_inner_mode
6291 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6294 inner
= force_to_mode (inner
, wanted_inner_mode
,
6296 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6297 ? ~(unsigned HOST_WIDE_INT
) 0
6298 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6303 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6304 have to zero extend. Otherwise, we can just use a SUBREG. */
6306 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6308 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6310 /* If we know that no extraneous bits are set, and that the high
6311 bit is not set, convert extraction to cheaper one - either
6312 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6314 if (flag_expensive_optimizations
6315 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6316 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6317 & ~(((unsigned HOST_WIDE_INT
)
6318 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6322 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6324 /* Prefer ZERO_EXTENSION, since it gives more information to
6326 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6331 else if (pos_rtx
!= 0
6332 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6333 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6335 /* Make POS_RTX unless we already have it and it is correct. If we don't
6336 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6338 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6339 pos_rtx
= orig_pos_rtx
;
6341 else if (pos_rtx
== 0)
6342 pos_rtx
= GEN_INT (pos
);
6344 /* Make the required operation. See if we can use existing rtx. */
6345 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6346 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6348 new = gen_lowpart (mode
, new);
6353 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6354 with any other operations in X. Return X without that shift if so. */
6357 extract_left_shift (rtx x
, int count
)
6359 enum rtx_code code
= GET_CODE (x
);
6360 enum machine_mode mode
= GET_MODE (x
);
6366 /* This is the shift itself. If it is wide enough, we will return
6367 either the value being shifted if the shift count is equal to
6368 COUNT or a shift for the difference. */
6369 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6370 && INTVAL (XEXP (x
, 1)) >= count
)
6371 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6372 INTVAL (XEXP (x
, 1)) - count
);
6376 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6377 return simplify_gen_unary (code
, mode
, tem
, mode
);
6381 case PLUS
: case IOR
: case XOR
: case AND
:
6382 /* If we can safely shift this constant and we find the inner shift,
6383 make a new operation. */
6384 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6385 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6386 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6387 return gen_binary (code
, mode
, tem
,
6388 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6399 /* Look at the expression rooted at X. Look for expressions
6400 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6401 Form these expressions.
6403 Return the new rtx, usually just X.
6405 Also, for machines like the VAX that don't have logical shift insns,
6406 try to convert logical to arithmetic shift operations in cases where
6407 they are equivalent. This undoes the canonicalizations to logical
6408 shifts done elsewhere.
6410 We try, as much as possible, to re-use rtl expressions to save memory.
6412 IN_CODE says what kind of expression we are processing. Normally, it is
6413 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6414 being kludges), it is MEM. When processing the arguments of a comparison
6415 or a COMPARE against zero, it is COMPARE. */
6418 make_compound_operation (rtx x
, enum rtx_code in_code
)
6420 enum rtx_code code
= GET_CODE (x
);
6421 enum machine_mode mode
= GET_MODE (x
);
6422 int mode_width
= GET_MODE_BITSIZE (mode
);
6424 enum rtx_code next_code
;
6430 /* Select the code to be used in recursive calls. Once we are inside an
6431 address, we stay there. If we have a comparison, set to COMPARE,
6432 but once inside, go back to our default of SET. */
6434 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6435 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6436 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6437 : in_code
== COMPARE
? SET
: in_code
);
6439 /* Process depending on the code of this operation. If NEW is set
6440 nonzero, it will be returned. */
6445 /* Convert shifts by constants into multiplications if inside
6447 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6448 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6449 && INTVAL (XEXP (x
, 1)) >= 0)
6451 new = make_compound_operation (XEXP (x
, 0), next_code
);
6452 new = gen_rtx_MULT (mode
, new,
6453 GEN_INT ((HOST_WIDE_INT
) 1
6454 << INTVAL (XEXP (x
, 1))));
6459 /* If the second operand is not a constant, we can't do anything
6461 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6464 /* If the constant is a power of two minus one and the first operand
6465 is a logical right shift, make an extraction. */
6466 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6467 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6469 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6470 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6471 0, in_code
== COMPARE
);
6474 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6475 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6476 && subreg_lowpart_p (XEXP (x
, 0))
6477 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6478 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6480 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6482 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6483 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6484 0, in_code
== COMPARE
);
6486 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6487 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6488 || GET_CODE (XEXP (x
, 0)) == IOR
)
6489 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6490 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6491 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6493 /* Apply the distributive law, and then try to make extractions. */
6494 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6495 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6497 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6499 new = make_compound_operation (new, in_code
);
6502 /* If we are have (and (rotate X C) M) and C is larger than the number
6503 of bits in M, this is an extraction. */
6505 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6506 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6507 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6508 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6510 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6511 new = make_extraction (mode
, new,
6512 (GET_MODE_BITSIZE (mode
)
6513 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6514 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6517 /* On machines without logical shifts, if the operand of the AND is
6518 a logical shift and our mask turns off all the propagated sign
6519 bits, we can replace the logical shift with an arithmetic shift. */
6520 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6521 && !have_insn_for (LSHIFTRT
, mode
)
6522 && have_insn_for (ASHIFTRT
, mode
)
6523 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6524 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6525 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6526 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6528 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6530 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6531 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6533 gen_rtx_ASHIFTRT (mode
,
6534 make_compound_operation
6535 (XEXP (XEXP (x
, 0), 0), next_code
),
6536 XEXP (XEXP (x
, 0), 1)));
6539 /* If the constant is one less than a power of two, this might be
6540 representable by an extraction even if no shift is present.
6541 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6542 we are in a COMPARE. */
6543 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6544 new = make_extraction (mode
,
6545 make_compound_operation (XEXP (x
, 0),
6547 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6549 /* If we are in a comparison and this is an AND with a power of two,
6550 convert this into the appropriate bit extract. */
6551 else if (in_code
== COMPARE
6552 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6553 new = make_extraction (mode
,
6554 make_compound_operation (XEXP (x
, 0),
6556 i
, NULL_RTX
, 1, 1, 0, 1);
6561 /* If the sign bit is known to be zero, replace this with an
6562 arithmetic shift. */
6563 if (have_insn_for (ASHIFTRT
, mode
)
6564 && ! have_insn_for (LSHIFTRT
, mode
)
6565 && mode_width
<= HOST_BITS_PER_WIDE_INT
6566 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6568 new = gen_rtx_ASHIFTRT (mode
,
6569 make_compound_operation (XEXP (x
, 0),
6575 /* ... fall through ... */
6581 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6582 this is a SIGN_EXTRACT. */
6583 if (GET_CODE (rhs
) == CONST_INT
6584 && GET_CODE (lhs
) == ASHIFT
6585 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6586 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6588 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6589 new = make_extraction (mode
, new,
6590 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6591 NULL_RTX
, mode_width
- INTVAL (rhs
),
6592 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6596 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6597 If so, try to merge the shifts into a SIGN_EXTEND. We could
6598 also do this for some cases of SIGN_EXTRACT, but it doesn't
6599 seem worth the effort; the case checked for occurs on Alpha. */
6601 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6602 && ! (GET_CODE (lhs
) == SUBREG
6603 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6604 && GET_CODE (rhs
) == CONST_INT
6605 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6606 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6607 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6608 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6609 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6614 /* Call ourselves recursively on the inner expression. If we are
6615 narrowing the object and it has a different RTL code from
6616 what it originally did, do this SUBREG as a force_to_mode. */
6618 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6619 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6620 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6621 && subreg_lowpart_p (x
))
6623 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6626 /* If we have something other than a SUBREG, we might have
6627 done an expansion, so rerun ourselves. */
6628 if (GET_CODE (newer
) != SUBREG
)
6629 newer
= make_compound_operation (newer
, in_code
);
6634 /* If this is a paradoxical subreg, and the new code is a sign or
6635 zero extension, omit the subreg and widen the extension. If it
6636 is a regular subreg, we can still get rid of the subreg by not
6637 widening so much, or in fact removing the extension entirely. */
6638 if ((GET_CODE (tem
) == SIGN_EXTEND
6639 || GET_CODE (tem
) == ZERO_EXTEND
)
6640 && subreg_lowpart_p (x
))
6642 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6643 || (GET_MODE_SIZE (mode
) >
6644 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6646 if (! SCALAR_INT_MODE_P (mode
))
6648 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6651 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6662 x
= gen_lowpart (mode
, new);
6663 code
= GET_CODE (x
);
6666 /* Now recursively process each operand of this operation. */
6667 fmt
= GET_RTX_FORMAT (code
);
6668 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6671 new = make_compound_operation (XEXP (x
, i
), next_code
);
6672 SUBST (XEXP (x
, i
), new);
6678 /* Given M see if it is a value that would select a field of bits
6679 within an item, but not the entire word. Return -1 if not.
6680 Otherwise, return the starting position of the field, where 0 is the
6683 *PLEN is set to the length of the field. */
6686 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6688 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6689 int pos
= exact_log2 (m
& -m
);
6695 /* Now shift off the low-order zero bits and see if we have a power of
6697 len
= exact_log2 ((m
>> pos
) + 1);
6706 /* See if X can be simplified knowing that we will only refer to it in
6707 MODE and will only refer to those bits that are nonzero in MASK.
6708 If other bits are being computed or if masking operations are done
6709 that select a superset of the bits in MASK, they can sometimes be
6712 Return a possibly simplified expression, but always convert X to
6713 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6715 Also, if REG is nonzero and X is a register equal in value to REG,
6718 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6719 are all off in X. This is used when X will be complemented, by either
6720 NOT, NEG, or XOR. */
6723 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6724 rtx reg
, int just_select
)
6726 enum rtx_code code
= GET_CODE (x
);
6727 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6728 enum machine_mode op_mode
;
6729 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6732 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6733 code below will do the wrong thing since the mode of such an
6734 expression is VOIDmode.
6736 Also do nothing if X is a CLOBBER; this can happen if X was
6737 the return value from a call to gen_lowpart. */
6738 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6741 /* We want to perform the operation is its present mode unless we know
6742 that the operation is valid in MODE, in which case we do the operation
6744 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6745 && have_insn_for (code
, mode
))
6746 ? mode
: GET_MODE (x
));
6748 /* It is not valid to do a right-shift in a narrower mode
6749 than the one it came in with. */
6750 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6751 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6752 op_mode
= GET_MODE (x
);
6754 /* Truncate MASK to fit OP_MODE. */
6756 mask
&= GET_MODE_MASK (op_mode
);
6758 /* When we have an arithmetic operation, or a shift whose count we
6759 do not know, we need to assume that all bits up to the highest-order
6760 bit in MASK will be needed. This is how we form such a mask. */
6761 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6762 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6764 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6767 /* Determine what bits of X are guaranteed to be (non)zero. */
6768 nonzero
= nonzero_bits (x
, mode
);
6770 /* If none of the bits in X are needed, return a zero. */
6771 if (! just_select
&& (nonzero
& mask
) == 0)
6774 /* If X is a CONST_INT, return a new one. Do this here since the
6775 test below will fail. */
6776 if (GET_CODE (x
) == CONST_INT
)
6778 if (SCALAR_INT_MODE_P (mode
))
6779 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6782 x
= GEN_INT (INTVAL (x
) & mask
);
6783 return gen_lowpart_common (mode
, x
);
6787 /* If X is narrower than MODE and we want all the bits in X's mode, just
6788 get X in the proper mode. */
6789 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6790 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6791 return gen_lowpart (mode
, x
);
6793 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6794 MASK are already known to be zero in X, we need not do anything. */
6795 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6801 /* If X is a (clobber (const_int)), return it since we know we are
6802 generating something that won't match. */
6806 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6807 spanned the boundary of the MEM. If we are now masking so it is
6808 within that boundary, we don't need the USE any more. */
6809 if (! BITS_BIG_ENDIAN
6810 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6811 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6818 x
= expand_compound_operation (x
);
6819 if (GET_CODE (x
) != code
)
6820 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6824 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6825 || rtx_equal_p (reg
, get_last_value (x
))))
6830 if (subreg_lowpart_p (x
)
6831 /* We can ignore the effect of this SUBREG if it narrows the mode or
6832 if the constant masks to zero all the bits the mode doesn't
6834 && ((GET_MODE_SIZE (GET_MODE (x
))
6835 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6837 & GET_MODE_MASK (GET_MODE (x
))
6838 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6839 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6843 /* If this is an AND with a constant, convert it into an AND
6844 whose constant is the AND of that constant with MASK. If it
6845 remains an AND of MASK, delete it since it is redundant. */
6847 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6849 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6850 mask
& INTVAL (XEXP (x
, 1)));
6852 /* If X is still an AND, see if it is an AND with a mask that
6853 is just some low-order bits. If so, and it is MASK, we don't
6856 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6857 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6861 /* If it remains an AND, try making another AND with the bits
6862 in the mode mask that aren't in MASK turned on. If the
6863 constant in the AND is wide enough, this might make a
6864 cheaper constant. */
6866 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6867 && GET_MODE_MASK (GET_MODE (x
)) != mask
6868 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6870 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6871 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6872 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6875 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6876 number, sign extend it. */
6877 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6878 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6879 cval
|= (HOST_WIDE_INT
) -1 << width
;
6881 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6882 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6892 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6893 low-order bits (as in an alignment operation) and FOO is already
6894 aligned to that boundary, mask C1 to that boundary as well.
6895 This may eliminate that PLUS and, later, the AND. */
6898 unsigned int width
= GET_MODE_BITSIZE (mode
);
6899 unsigned HOST_WIDE_INT smask
= mask
;
6901 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6902 number, sign extend it. */
6904 if (width
< HOST_BITS_PER_WIDE_INT
6905 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6906 smask
|= (HOST_WIDE_INT
) -1 << width
;
6908 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6909 && exact_log2 (- smask
) >= 0
6910 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6911 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6912 return force_to_mode (plus_constant (XEXP (x
, 0),
6913 (INTVAL (XEXP (x
, 1)) & smask
)),
6914 mode
, smask
, reg
, next_select
);
6917 /* ... fall through ... */
6920 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6921 most significant bit in MASK since carries from those bits will
6922 affect the bits we are interested in. */
6927 /* If X is (minus C Y) where C's least set bit is larger than any bit
6928 in the mask, then we may replace with (neg Y). */
6929 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6930 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6931 & -INTVAL (XEXP (x
, 0))))
6934 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6936 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6939 /* Similarly, if C contains every bit in the fuller_mask, then we may
6940 replace with (not Y). */
6941 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6942 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6943 == INTVAL (XEXP (x
, 0))))
6945 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6946 XEXP (x
, 1), GET_MODE (x
));
6947 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6955 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6956 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6957 operation which may be a bitfield extraction. Ensure that the
6958 constant we form is not wider than the mode of X. */
6960 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6961 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6962 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6963 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6964 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6965 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6966 + floor_log2 (INTVAL (XEXP (x
, 1))))
6967 < GET_MODE_BITSIZE (GET_MODE (x
)))
6968 && (INTVAL (XEXP (x
, 1))
6969 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6971 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6972 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6973 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6974 XEXP (XEXP (x
, 0), 0), temp
);
6975 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6976 XEXP (XEXP (x
, 0), 1));
6977 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6981 /* For most binary operations, just propagate into the operation and
6982 change the mode if we have an operation of that mode. */
6984 op0
= gen_lowpart (op_mode
,
6985 force_to_mode (XEXP (x
, 0), mode
, mask
,
6987 op1
= gen_lowpart (op_mode
,
6988 force_to_mode (XEXP (x
, 1), mode
, mask
,
6991 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6992 x
= gen_binary (code
, op_mode
, op0
, op1
);
6996 /* For left shifts, do the same, but just for the first operand.
6997 However, we cannot do anything with shifts where we cannot
6998 guarantee that the counts are smaller than the size of the mode
6999 because such a count will have a different meaning in a
7002 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7003 && INTVAL (XEXP (x
, 1)) >= 0
7004 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7005 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7006 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7007 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7010 /* If the shift count is a constant and we can do arithmetic in
7011 the mode of the shift, refine which bits we need. Otherwise, use the
7012 conservative form of the mask. */
7013 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7014 && INTVAL (XEXP (x
, 1)) >= 0
7015 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7016 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7017 mask
>>= INTVAL (XEXP (x
, 1));
7021 op0
= gen_lowpart (op_mode
,
7022 force_to_mode (XEXP (x
, 0), op_mode
,
7023 mask
, reg
, next_select
));
7025 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7026 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7030 /* Here we can only do something if the shift count is a constant,
7031 this shift constant is valid for the host, and we can do arithmetic
7034 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7035 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7036 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7038 rtx inner
= XEXP (x
, 0);
7039 unsigned HOST_WIDE_INT inner_mask
;
7041 /* Select the mask of the bits we need for the shift operand. */
7042 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7044 /* We can only change the mode of the shift if we can do arithmetic
7045 in the mode of the shift and INNER_MASK is no wider than the
7046 width of OP_MODE. */
7047 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7048 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7049 op_mode
= GET_MODE (x
);
7051 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7053 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7054 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7057 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7058 shift and AND produces only copies of the sign bit (C2 is one less
7059 than a power of two), we can do this with just a shift. */
7061 if (GET_CODE (x
) == LSHIFTRT
7062 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7063 /* The shift puts one of the sign bit copies in the least significant
7065 && ((INTVAL (XEXP (x
, 1))
7066 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7067 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7068 && exact_log2 (mask
+ 1) >= 0
7069 /* Number of bits left after the shift must be more than the mask
7071 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7072 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7073 /* Must be more sign bit copies than the mask needs. */
7074 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7075 >= exact_log2 (mask
+ 1)))
7076 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7077 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7078 - exact_log2 (mask
+ 1)));
7083 /* If we are just looking for the sign bit, we don't need this shift at
7084 all, even if it has a variable count. */
7085 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7086 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7087 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7088 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7090 /* If this is a shift by a constant, get a mask that contains those bits
7091 that are not copies of the sign bit. We then have two cases: If
7092 MASK only includes those bits, this can be a logical shift, which may
7093 allow simplifications. If MASK is a single-bit field not within
7094 those bits, we are requesting a copy of the sign bit and hence can
7095 shift the sign bit to the appropriate location. */
7097 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7098 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7102 /* If the considered data is wider than HOST_WIDE_INT, we can't
7103 represent a mask for all its bits in a single scalar.
7104 But we only care about the lower bits, so calculate these. */
7106 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7108 nonzero
= ~(HOST_WIDE_INT
) 0;
7110 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7111 is the number of bits a full-width mask would have set.
7112 We need only shift if these are fewer than nonzero can
7113 hold. If not, we must keep all bits set in nonzero. */
7115 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7116 < HOST_BITS_PER_WIDE_INT
)
7117 nonzero
>>= INTVAL (XEXP (x
, 1))
7118 + HOST_BITS_PER_WIDE_INT
7119 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7123 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7124 nonzero
>>= INTVAL (XEXP (x
, 1));
7127 if ((mask
& ~nonzero
) == 0
7128 || (i
= exact_log2 (mask
)) >= 0)
7130 x
= simplify_shift_const
7131 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7132 i
< 0 ? INTVAL (XEXP (x
, 1))
7133 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7135 if (GET_CODE (x
) != ASHIFTRT
)
7136 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7140 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7141 even if the shift count isn't a constant. */
7143 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7147 /* If this is a zero- or sign-extension operation that just affects bits
7148 we don't care about, remove it. Be sure the call above returned
7149 something that is still a shift. */
7151 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7152 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7153 && INTVAL (XEXP (x
, 1)) >= 0
7154 && (INTVAL (XEXP (x
, 1))
7155 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7156 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7157 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7158 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7165 /* If the shift count is constant and we can do computations
7166 in the mode of X, compute where the bits we care about are.
7167 Otherwise, we can't do anything. Don't change the mode of
7168 the shift or propagate MODE into the shift, though. */
7169 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7170 && INTVAL (XEXP (x
, 1)) >= 0)
7172 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7173 GET_MODE (x
), GEN_INT (mask
),
7175 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7177 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7178 INTVAL (temp
), reg
, next_select
));
7183 /* If we just want the low-order bit, the NEG isn't needed since it
7184 won't change the low-order bit. */
7186 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7188 /* We need any bits less significant than the most significant bit in
7189 MASK since carries from those bits will affect the bits we are
7195 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7196 same as the XOR case above. Ensure that the constant we form is not
7197 wider than the mode of X. */
7199 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7200 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7201 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7202 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7203 < GET_MODE_BITSIZE (GET_MODE (x
)))
7204 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7206 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7208 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7209 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7211 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7214 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7215 use the full mask inside the NOT. */
7219 op0
= gen_lowpart (op_mode
,
7220 force_to_mode (XEXP (x
, 0), mode
, mask
,
7222 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7223 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7227 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7228 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7229 which is equal to STORE_FLAG_VALUE. */
7230 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7231 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7232 && (nonzero_bits (XEXP (x
, 0), mode
)
7233 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7234 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7239 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7240 written in a narrower mode. We play it safe and do not do so. */
7243 gen_lowpart (GET_MODE (x
),
7244 force_to_mode (XEXP (x
, 1), mode
,
7245 mask
, reg
, next_select
)));
7247 gen_lowpart (GET_MODE (x
),
7248 force_to_mode (XEXP (x
, 2), mode
,
7249 mask
, reg
, next_select
)));
7256 /* Ensure we return a value of the proper mode. */
7257 return gen_lowpart (mode
, x
);
7260 /* Return nonzero if X is an expression that has one of two values depending on
7261 whether some other value is zero or nonzero. In that case, we return the
7262 value that is being tested, *PTRUE is set to the value if the rtx being
7263 returned has a nonzero value, and *PFALSE is set to the other alternative.
7265 If we return zero, we set *PTRUE and *PFALSE to X. */
7268 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7270 enum machine_mode mode
= GET_MODE (x
);
7271 enum rtx_code code
= GET_CODE (x
);
7272 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7273 unsigned HOST_WIDE_INT nz
;
7275 /* If we are comparing a value against zero, we are done. */
7276 if ((code
== NE
|| code
== EQ
)
7277 && XEXP (x
, 1) == const0_rtx
)
7279 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7280 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7284 /* If this is a unary operation whose operand has one of two values, apply
7285 our opcode to compute those values. */
7286 else if (GET_RTX_CLASS (code
) == '1'
7287 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7289 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7290 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7291 GET_MODE (XEXP (x
, 0)));
7295 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7296 make can't possibly match and would suppress other optimizations. */
7297 else if (code
== COMPARE
)
7300 /* If this is a binary operation, see if either side has only one of two
7301 values. If either one does or if both do and they are conditional on
7302 the same value, compute the new true and false values. */
7303 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7304 || GET_RTX_CLASS (code
) == '<')
7306 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7307 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7309 if ((cond0
!= 0 || cond1
!= 0)
7310 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7312 /* If if_then_else_cond returned zero, then true/false are the
7313 same rtl. We must copy one of them to prevent invalid rtl
7316 true0
= copy_rtx (true0
);
7317 else if (cond1
== 0)
7318 true1
= copy_rtx (true1
);
7320 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7321 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7322 return cond0
? cond0
: cond1
;
7325 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7326 operands is zero when the other is nonzero, and vice-versa,
7327 and STORE_FLAG_VALUE is 1 or -1. */
7329 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7330 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7332 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7334 rtx op0
= XEXP (XEXP (x
, 0), 1);
7335 rtx op1
= XEXP (XEXP (x
, 1), 1);
7337 cond0
= XEXP (XEXP (x
, 0), 0);
7338 cond1
= XEXP (XEXP (x
, 1), 0);
7340 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7341 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7342 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7343 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7344 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7345 || ((swap_condition (GET_CODE (cond0
))
7346 == combine_reversed_comparison_code (cond1
))
7347 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7348 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7349 && ! side_effects_p (x
))
7351 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7352 *pfalse
= gen_binary (MULT
, mode
,
7354 ? simplify_gen_unary (NEG
, mode
, op1
,
7362 /* Similarly for MULT, AND and UMIN, except that for these the result
7364 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7365 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7366 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7368 cond0
= XEXP (XEXP (x
, 0), 0);
7369 cond1
= XEXP (XEXP (x
, 1), 0);
7371 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7372 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7373 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7374 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7375 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7376 || ((swap_condition (GET_CODE (cond0
))
7377 == combine_reversed_comparison_code (cond1
))
7378 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7379 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7380 && ! side_effects_p (x
))
7382 *ptrue
= *pfalse
= const0_rtx
;
7388 else if (code
== IF_THEN_ELSE
)
7390 /* If we have IF_THEN_ELSE already, extract the condition and
7391 canonicalize it if it is NE or EQ. */
7392 cond0
= XEXP (x
, 0);
7393 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7394 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7395 return XEXP (cond0
, 0);
7396 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7398 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7399 return XEXP (cond0
, 0);
7405 /* If X is a SUBREG, we can narrow both the true and false values
7406 if the inner expression, if there is a condition. */
7407 else if (code
== SUBREG
7408 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7411 *ptrue
= simplify_gen_subreg (mode
, true0
,
7412 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7413 *pfalse
= simplify_gen_subreg (mode
, false0
,
7414 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7419 /* If X is a constant, this isn't special and will cause confusions
7420 if we treat it as such. Likewise if it is equivalent to a constant. */
7421 else if (CONSTANT_P (x
)
7422 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7425 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7426 will be least confusing to the rest of the compiler. */
7427 else if (mode
== BImode
)
7429 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7433 /* If X is known to be either 0 or -1, those are the true and
7434 false values when testing X. */
7435 else if (x
== constm1_rtx
|| x
== const0_rtx
7436 || (mode
!= VOIDmode
7437 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7439 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7443 /* Likewise for 0 or a single bit. */
7444 else if (SCALAR_INT_MODE_P (mode
)
7445 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7446 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7448 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7452 /* Otherwise fail; show no condition with true and false values the same. */
7453 *ptrue
= *pfalse
= x
;
7457 /* Return the value of expression X given the fact that condition COND
7458 is known to be true when applied to REG as its first operand and VAL
7459 as its second. X is known to not be shared and so can be modified in
7462 We only handle the simplest cases, and specifically those cases that
7463 arise with IF_THEN_ELSE expressions. */
7466 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7468 enum rtx_code code
= GET_CODE (x
);
7473 if (side_effects_p (x
))
7476 /* If either operand of the condition is a floating point value,
7477 then we have to avoid collapsing an EQ comparison. */
7479 && rtx_equal_p (x
, reg
)
7480 && ! FLOAT_MODE_P (GET_MODE (x
))
7481 && ! FLOAT_MODE_P (GET_MODE (val
)))
7484 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7487 /* If X is (abs REG) and we know something about REG's relationship
7488 with zero, we may be able to simplify this. */
7490 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7493 case GE
: case GT
: case EQ
:
7496 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7498 GET_MODE (XEXP (x
, 0)));
7503 /* The only other cases we handle are MIN, MAX, and comparisons if the
7504 operands are the same as REG and VAL. */
7506 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7508 if (rtx_equal_p (XEXP (x
, 0), val
))
7509 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7511 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7513 if (GET_RTX_CLASS (code
) == '<')
7515 if (comparison_dominates_p (cond
, code
))
7516 return const_true_rtx
;
7518 code
= combine_reversed_comparison_code (x
);
7520 && comparison_dominates_p (cond
, code
))
7525 else if (code
== SMAX
|| code
== SMIN
7526 || code
== UMIN
|| code
== UMAX
)
7528 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7530 /* Do not reverse the condition when it is NE or EQ.
7531 This is because we cannot conclude anything about
7532 the value of 'SMAX (x, y)' when x is not equal to y,
7533 but we can when x equals y. */
7534 if ((code
== SMAX
|| code
== UMAX
)
7535 && ! (cond
== EQ
|| cond
== NE
))
7536 cond
= reverse_condition (cond
);
7541 return unsignedp
? x
: XEXP (x
, 1);
7543 return unsignedp
? x
: XEXP (x
, 0);
7545 return unsignedp
? XEXP (x
, 1) : x
;
7547 return unsignedp
? XEXP (x
, 0) : x
;
7554 else if (code
== SUBREG
)
7556 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7557 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7559 if (SUBREG_REG (x
) != r
)
7561 /* We must simplify subreg here, before we lose track of the
7562 original inner_mode. */
7563 new = simplify_subreg (GET_MODE (x
), r
,
7564 inner_mode
, SUBREG_BYTE (x
));
7568 SUBST (SUBREG_REG (x
), r
);
7573 /* We don't have to handle SIGN_EXTEND here, because even in the
7574 case of replacing something with a modeless CONST_INT, a
7575 CONST_INT is already (supposed to be) a valid sign extension for
7576 its narrower mode, which implies it's already properly
7577 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7578 story is different. */
7579 else if (code
== ZERO_EXTEND
)
7581 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7582 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7584 if (XEXP (x
, 0) != r
)
7586 /* We must simplify the zero_extend here, before we lose
7587 track of the original inner_mode. */
7588 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7593 SUBST (XEXP (x
, 0), r
);
7599 fmt
= GET_RTX_FORMAT (code
);
7600 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7603 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7604 else if (fmt
[i
] == 'E')
7605 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7606 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7613 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7614 assignment as a field assignment. */
7617 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7619 if (x
== y
|| rtx_equal_p (x
, y
))
7622 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7625 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7626 Note that all SUBREGs of MEM are paradoxical; otherwise they
7627 would have been rewritten. */
7628 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7629 && GET_CODE (SUBREG_REG (y
)) == MEM
7630 && rtx_equal_p (SUBREG_REG (y
),
7631 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7634 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7635 && GET_CODE (SUBREG_REG (x
)) == MEM
7636 && rtx_equal_p (SUBREG_REG (x
),
7637 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7640 /* We used to see if get_last_value of X and Y were the same but that's
7641 not correct. In one direction, we'll cause the assignment to have
7642 the wrong destination and in the case, we'll import a register into this
7643 insn that might have already have been dead. So fail if none of the
7644 above cases are true. */
7648 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7649 Return that assignment if so.
7651 We only handle the most common cases. */
7654 make_field_assignment (rtx x
)
7656 rtx dest
= SET_DEST (x
);
7657 rtx src
= SET_SRC (x
);
7662 unsigned HOST_WIDE_INT len
;
7664 enum machine_mode mode
;
7666 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7667 a clear of a one-bit field. We will have changed it to
7668 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7671 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7672 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7673 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7674 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7676 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7679 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7683 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7684 && subreg_lowpart_p (XEXP (src
, 0))
7685 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7686 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7687 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7688 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7689 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7690 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7692 assign
= make_extraction (VOIDmode
, dest
, 0,
7693 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7696 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7700 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7702 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7703 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7704 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7706 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7709 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7713 /* The other case we handle is assignments into a constant-position
7714 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7715 a mask that has all one bits except for a group of zero bits and
7716 OTHER is known to have zeros where C1 has ones, this is such an
7717 assignment. Compute the position and length from C1. Shift OTHER
7718 to the appropriate position, force it to the required mode, and
7719 make the extraction. Check for the AND in both operands. */
7721 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7724 rhs
= expand_compound_operation (XEXP (src
, 0));
7725 lhs
= expand_compound_operation (XEXP (src
, 1));
7727 if (GET_CODE (rhs
) == AND
7728 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7729 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7730 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7731 else if (GET_CODE (lhs
) == AND
7732 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7733 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7734 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7738 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7739 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7740 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7741 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7744 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7748 /* The mode to use for the source is the mode of the assignment, or of
7749 what is inside a possible STRICT_LOW_PART. */
7750 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7751 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7753 /* Shift OTHER right POS places and make it the source, restricting it
7754 to the proper length and mode. */
7756 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7757 GET_MODE (src
), other
, pos
),
7759 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7760 ? ~(unsigned HOST_WIDE_INT
) 0
7761 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7764 /* If SRC is masked by an AND that does not make a difference in
7765 the value being stored, strip it. */
7766 if (GET_CODE (assign
) == ZERO_EXTRACT
7767 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7768 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7769 && GET_CODE (src
) == AND
7770 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7771 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7772 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7773 src
= XEXP (src
, 0);
7775 return gen_rtx_SET (VOIDmode
, assign
, src
);
7778 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7782 apply_distributive_law (rtx x
)
7784 enum rtx_code code
= GET_CODE (x
);
7785 enum rtx_code inner_code
;
7786 rtx lhs
, rhs
, other
;
7789 /* Distributivity is not true for floating point as it can change the
7790 value. So we don't do it unless -funsafe-math-optimizations. */
7791 if (FLOAT_MODE_P (GET_MODE (x
))
7792 && ! flag_unsafe_math_optimizations
)
7795 /* The outer operation can only be one of the following: */
7796 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7797 && code
!= PLUS
&& code
!= MINUS
)
7803 /* If either operand is a primitive we can't do anything, so get out
7805 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7806 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7809 lhs
= expand_compound_operation (lhs
);
7810 rhs
= expand_compound_operation (rhs
);
7811 inner_code
= GET_CODE (lhs
);
7812 if (inner_code
!= GET_CODE (rhs
))
7815 /* See if the inner and outer operations distribute. */
7822 /* These all distribute except over PLUS. */
7823 if (code
== PLUS
|| code
== MINUS
)
7828 if (code
!= PLUS
&& code
!= MINUS
)
7833 /* This is also a multiply, so it distributes over everything. */
7837 /* Non-paradoxical SUBREGs distributes over all operations, provided
7838 the inner modes and byte offsets are the same, this is an extraction
7839 of a low-order part, we don't convert an fp operation to int or
7840 vice versa, and we would not be converting a single-word
7841 operation into a multi-word operation. The latter test is not
7842 required, but it prevents generating unneeded multi-word operations.
7843 Some of the previous tests are redundant given the latter test, but
7844 are retained because they are required for correctness.
7846 We produce the result slightly differently in this case. */
7848 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7849 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7850 || ! subreg_lowpart_p (lhs
)
7851 || (GET_MODE_CLASS (GET_MODE (lhs
))
7852 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7853 || (GET_MODE_SIZE (GET_MODE (lhs
))
7854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7855 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7858 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7859 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7860 return gen_lowpart (GET_MODE (x
), tem
);
7866 /* Set LHS and RHS to the inner operands (A and B in the example
7867 above) and set OTHER to the common operand (C in the example).
7868 These is only one way to do this unless the inner operation is
7870 if (GET_RTX_CLASS (inner_code
) == 'c'
7871 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7872 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7873 else if (GET_RTX_CLASS (inner_code
) == 'c'
7874 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7875 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7876 else if (GET_RTX_CLASS (inner_code
) == 'c'
7877 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7878 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7879 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7880 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7884 /* Form the new inner operation, seeing if it simplifies first. */
7885 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7887 /* There is one exception to the general way of distributing:
7888 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7889 if (code
== XOR
&& inner_code
== IOR
)
7892 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7895 /* We may be able to continuing distributing the result, so call
7896 ourselves recursively on the inner operation before forming the
7897 outer operation, which we return. */
7898 return gen_binary (inner_code
, GET_MODE (x
),
7899 apply_distributive_law (tem
), other
);
7902 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7905 Return an equivalent form, if different from X. Otherwise, return X. If
7906 X is zero, we are to always construct the equivalent form. */
7909 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7910 unsigned HOST_WIDE_INT constop
)
7912 unsigned HOST_WIDE_INT nonzero
;
7915 /* Simplify VAROP knowing that we will be only looking at some of the
7918 Note by passing in CONSTOP, we guarantee that the bits not set in
7919 CONSTOP are not significant and will never be examined. We must
7920 ensure that is the case by explicitly masking out those bits
7921 before returning. */
7922 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7924 /* If VAROP is a CLOBBER, we will fail so return it. */
7925 if (GET_CODE (varop
) == CLOBBER
)
7928 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7929 to VAROP and return the new constant. */
7930 if (GET_CODE (varop
) == CONST_INT
)
7931 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7933 /* See what bits may be nonzero in VAROP. Unlike the general case of
7934 a call to nonzero_bits, here we don't care about bits outside
7937 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7939 /* Turn off all bits in the constant that are known to already be zero.
7940 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7941 which is tested below. */
7945 /* If we don't have any bits left, return zero. */
7949 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7950 a power of two, we can replace this with an ASHIFT. */
7951 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7952 && (i
= exact_log2 (constop
)) >= 0)
7953 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7955 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7956 or XOR, then try to apply the distributive law. This may eliminate
7957 operations if either branch can be simplified because of the AND.
7958 It may also make some cases more complex, but those cases probably
7959 won't match a pattern either with or without this. */
7961 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7965 apply_distributive_law
7966 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7967 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7968 XEXP (varop
, 0), constop
),
7969 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7970 XEXP (varop
, 1), constop
))));
7972 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7973 the AND and see if one of the operands simplifies to zero. If so, we
7974 may eliminate it. */
7976 if (GET_CODE (varop
) == PLUS
7977 && exact_log2 (constop
+ 1) >= 0)
7981 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7982 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7983 if (o0
== const0_rtx
)
7985 if (o1
== const0_rtx
)
7989 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7990 if we already had one (just check for the simplest cases). */
7991 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7992 && GET_MODE (XEXP (x
, 0)) == mode
7993 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7994 varop
= XEXP (x
, 0);
7996 varop
= gen_lowpart (mode
, varop
);
7998 /* If we can't make the SUBREG, try to return what we were given. */
7999 if (GET_CODE (varop
) == CLOBBER
)
8000 return x
? x
: varop
;
8002 /* If we are only masking insignificant bits, return VAROP. */
8003 if (constop
== nonzero
)
8007 /* Otherwise, return an AND. */
8008 constop
= trunc_int_for_mode (constop
, mode
);
8009 /* See how much, if any, of X we can use. */
8010 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8011 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8015 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8016 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8017 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8019 SUBST (XEXP (x
, 0), varop
);
8026 #define nonzero_bits_with_known(X, MODE) \
8027 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8029 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8030 It avoids exponential behavior in nonzero_bits1 when X has
8031 identical subexpressions on the first or the second level. */
8033 static unsigned HOST_WIDE_INT
8034 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8035 enum machine_mode known_mode
,
8036 unsigned HOST_WIDE_INT known_ret
)
8038 if (x
== known_x
&& mode
== known_mode
)
8041 /* Try to find identical subexpressions. If found call
8042 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8043 precomputed value for the subexpression as KNOWN_RET. */
8045 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8046 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8048 rtx x0
= XEXP (x
, 0);
8049 rtx x1
= XEXP (x
, 1);
8051 /* Check the first level. */
8053 return nonzero_bits1 (x
, mode
, x0
, mode
,
8054 nonzero_bits_with_known (x0
, mode
));
8056 /* Check the second level. */
8057 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8058 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8059 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8060 return nonzero_bits1 (x
, mode
, x1
, mode
,
8061 nonzero_bits_with_known (x1
, mode
));
8063 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8064 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8065 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8066 return nonzero_bits1 (x
, mode
, x0
, mode
,
8067 nonzero_bits_with_known (x0
, mode
));
8070 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8073 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8074 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8075 is less useful. We can't allow both, because that results in exponential
8076 run time recursion. There is a nullstone testcase that triggered
8077 this. This macro avoids accidental uses of num_sign_bit_copies. */
8078 #define cached_num_sign_bit_copies()
8080 /* Given an expression, X, compute which bits in X can be nonzero.
8081 We don't care about bits outside of those defined in MODE.
8083 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8084 a shift, AND, or zero_extract, we can do better. */
8086 static unsigned HOST_WIDE_INT
8087 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8088 enum machine_mode known_mode
,
8089 unsigned HOST_WIDE_INT known_ret
)
8091 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8092 unsigned HOST_WIDE_INT inner_nz
;
8094 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8097 /* For floating-point values, assume all bits are needed. */
8098 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8101 /* If X is wider than MODE, use its mode instead. */
8102 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8104 mode
= GET_MODE (x
);
8105 nonzero
= GET_MODE_MASK (mode
);
8106 mode_width
= GET_MODE_BITSIZE (mode
);
8109 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8110 /* Our only callers in this case look for single bit values. So
8111 just return the mode mask. Those tests will then be false. */
8114 #ifndef WORD_REGISTER_OPERATIONS
8115 /* If MODE is wider than X, but both are a single word for both the host
8116 and target machines, we can compute this from which bits of the
8117 object might be nonzero in its own mode, taking into account the fact
8118 that on many CISC machines, accessing an object in a wider mode
8119 causes the high-order bits to become undefined. So they are
8120 not known to be zero. */
8122 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8123 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8124 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8125 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8127 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8128 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8133 code
= GET_CODE (x
);
8137 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8138 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8139 all the bits above ptr_mode are known to be zero. */
8140 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8142 nonzero
&= GET_MODE_MASK (ptr_mode
);
8145 /* Include declared information about alignment of pointers. */
8146 /* ??? We don't properly preserve REG_POINTER changes across
8147 pointer-to-integer casts, so we can't trust it except for
8148 things that we know must be pointers. See execute/960116-1.c. */
8149 if ((x
== stack_pointer_rtx
8150 || x
== frame_pointer_rtx
8151 || x
== arg_pointer_rtx
)
8152 && REGNO_POINTER_ALIGN (REGNO (x
)))
8154 unsigned HOST_WIDE_INT alignment
8155 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8157 #ifdef PUSH_ROUNDING
8158 /* If PUSH_ROUNDING is defined, it is possible for the
8159 stack to be momentarily aligned only to that amount,
8160 so we pick the least alignment. */
8161 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8162 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8166 nonzero
&= ~(alignment
- 1);
8169 /* If X is a register whose nonzero bits value is current, use it.
8170 Otherwise, if X is a register whose value we can find, use that
8171 value. Otherwise, use the previously-computed global nonzero bits
8172 for this register. */
8174 if (reg_last_set_value
[REGNO (x
)] != 0
8175 && (reg_last_set_mode
[REGNO (x
)] == mode
8176 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8177 && GET_MODE_CLASS (mode
) == MODE_INT
))
8178 && (reg_last_set_label
[REGNO (x
)] == label_tick
8179 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8180 && REG_N_SETS (REGNO (x
)) == 1
8181 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8183 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8184 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8186 tem
= get_last_value (x
);
8190 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8191 /* If X is narrower than MODE and TEM is a non-negative
8192 constant that would appear negative in the mode of X,
8193 sign-extend it for use in reg_nonzero_bits because some
8194 machines (maybe most) will actually do the sign-extension
8195 and this is the conservative approach.
8197 ??? For 2.5, try to tighten up the MD files in this regard
8198 instead of this kludge. */
8200 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8201 && GET_CODE (tem
) == CONST_INT
8203 && 0 != (INTVAL (tem
)
8204 & ((HOST_WIDE_INT
) 1
8205 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8206 tem
= GEN_INT (INTVAL (tem
)
8207 | ((HOST_WIDE_INT
) (-1)
8208 << GET_MODE_BITSIZE (GET_MODE (x
))));
8210 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8212 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8214 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8216 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8217 /* We don't know anything about the upper bits. */
8218 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8219 return nonzero
& mask
;
8225 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8226 /* If X is negative in MODE, sign-extend the value. */
8227 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8228 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8229 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8235 #ifdef LOAD_EXTEND_OP
8236 /* In many, if not most, RISC machines, reading a byte from memory
8237 zeros the rest of the register. Noticing that fact saves a lot
8238 of extra zero-extends. */
8239 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8240 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8245 case UNEQ
: case LTGT
:
8246 case GT
: case GTU
: case UNGT
:
8247 case LT
: case LTU
: case UNLT
:
8248 case GE
: case GEU
: case UNGE
:
8249 case LE
: case LEU
: case UNLE
:
8250 case UNORDERED
: case ORDERED
:
8252 /* If this produces an integer result, we know which bits are set.
8253 Code here used to clear bits outside the mode of X, but that is
8256 if (GET_MODE_CLASS (mode
) == MODE_INT
8257 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8258 nonzero
= STORE_FLAG_VALUE
;
8263 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8264 and num_sign_bit_copies. */
8265 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8266 == GET_MODE_BITSIZE (GET_MODE (x
)))
8270 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8271 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8276 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8277 and num_sign_bit_copies. */
8278 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8279 == GET_MODE_BITSIZE (GET_MODE (x
)))
8285 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8286 & GET_MODE_MASK (mode
));
8290 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8291 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8292 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8296 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8297 Otherwise, show all the bits in the outer mode but not the inner
8299 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8300 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8302 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8304 & (((HOST_WIDE_INT
) 1
8305 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8306 inner_nz
|= (GET_MODE_MASK (mode
)
8307 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8310 nonzero
&= inner_nz
;
8314 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8315 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8319 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8321 unsigned HOST_WIDE_INT nonzero0
=
8322 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8324 /* Don't call nonzero_bits for the second time if it cannot change
8326 if ((nonzero
& nonzero0
) != nonzero
)
8327 nonzero
&= (nonzero0
8328 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8332 case PLUS
: case MINUS
:
8334 case DIV
: case UDIV
:
8335 case MOD
: case UMOD
:
8336 /* We can apply the rules of arithmetic to compute the number of
8337 high- and low-order zero bits of these operations. We start by
8338 computing the width (position of the highest-order nonzero bit)
8339 and the number of low-order zero bits for each value. */
8341 unsigned HOST_WIDE_INT nz0
=
8342 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8343 unsigned HOST_WIDE_INT nz1
=
8344 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8345 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8346 int width0
= floor_log2 (nz0
) + 1;
8347 int width1
= floor_log2 (nz1
) + 1;
8348 int low0
= floor_log2 (nz0
& -nz0
);
8349 int low1
= floor_log2 (nz1
& -nz1
);
8350 HOST_WIDE_INT op0_maybe_minusp
8351 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8352 HOST_WIDE_INT op1_maybe_minusp
8353 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8354 unsigned int result_width
= mode_width
;
8360 result_width
= MAX (width0
, width1
) + 1;
8361 result_low
= MIN (low0
, low1
);
8364 result_low
= MIN (low0
, low1
);
8367 result_width
= width0
+ width1
;
8368 result_low
= low0
+ low1
;
8373 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8374 result_width
= width0
;
8379 result_width
= width0
;
8384 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8385 result_width
= MIN (width0
, width1
);
8386 result_low
= MIN (low0
, low1
);
8391 result_width
= MIN (width0
, width1
);
8392 result_low
= MIN (low0
, low1
);
8398 if (result_width
< mode_width
)
8399 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8402 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8404 #ifdef POINTERS_EXTEND_UNSIGNED
8405 /* If pointers extend unsigned and this is an addition or subtraction
8406 to a pointer in Pmode, all the bits above ptr_mode are known to be
8408 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8409 && (code
== PLUS
|| code
== MINUS
)
8410 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8411 nonzero
&= GET_MODE_MASK (ptr_mode
);
8417 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8418 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8419 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8423 /* If this is a SUBREG formed for a promoted variable that has
8424 been zero-extended, we know that at least the high-order bits
8425 are zero, though others might be too. */
8427 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8428 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8429 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8431 /* If the inner mode is a single word for both the host and target
8432 machines, we can compute this from which bits of the inner
8433 object might be nonzero. */
8434 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8435 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8436 <= HOST_BITS_PER_WIDE_INT
))
8438 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8440 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8441 /* If this is a typical RISC machine, we only have to worry
8442 about the way loads are extended. */
8443 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8445 & (((unsigned HOST_WIDE_INT
) 1
8446 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8448 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8449 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8452 /* On many CISC machines, accessing an object in a wider mode
8453 causes the high-order bits to become undefined. So they are
8454 not known to be zero. */
8455 if (GET_MODE_SIZE (GET_MODE (x
))
8456 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8457 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8458 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8467 /* The nonzero bits are in two classes: any bits within MODE
8468 that aren't in GET_MODE (x) are always significant. The rest of the
8469 nonzero bits are those that are significant in the operand of
8470 the shift when shifted the appropriate number of bits. This
8471 shows that high-order bits are cleared by the right shift and
8472 low-order bits by left shifts. */
8473 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8474 && INTVAL (XEXP (x
, 1)) >= 0
8475 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8477 enum machine_mode inner_mode
= GET_MODE (x
);
8478 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8479 int count
= INTVAL (XEXP (x
, 1));
8480 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8481 unsigned HOST_WIDE_INT op_nonzero
=
8482 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8483 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8484 unsigned HOST_WIDE_INT outer
= 0;
8486 if (mode_width
> width
)
8487 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8489 if (code
== LSHIFTRT
)
8491 else if (code
== ASHIFTRT
)
8495 /* If the sign bit may have been nonzero before the shift, we
8496 need to mark all the places it could have been copied to
8497 by the shift as possibly nonzero. */
8498 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8499 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8501 else if (code
== ASHIFT
)
8504 inner
= ((inner
<< (count
% width
)
8505 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8507 nonzero
&= (outer
| inner
);
8513 /* This is at most the number of bits in the mode. */
8514 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8518 /* If CLZ has a known value at zero, then the nonzero bits are
8519 that value, plus the number of bits in the mode minus one. */
8520 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8521 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8527 /* If CTZ has a known value at zero, then the nonzero bits are
8528 that value, plus the number of bits in the mode minus one. */
8529 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8530 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8540 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8541 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8551 /* See the macro definition above. */
8552 #undef cached_num_sign_bit_copies
8554 #define num_sign_bit_copies_with_known(X, M) \
8555 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8557 /* The function cached_num_sign_bit_copies is a wrapper around
8558 num_sign_bit_copies1. It avoids exponential behavior in
8559 num_sign_bit_copies1 when X has identical subexpressions on the
8560 first or the second level. */
8563 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8564 enum machine_mode known_mode
,
8565 unsigned int known_ret
)
8567 if (x
== known_x
&& mode
== known_mode
)
8570 /* Try to find identical subexpressions. If found call
8571 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8572 the precomputed value for the subexpression as KNOWN_RET. */
8574 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8575 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8577 rtx x0
= XEXP (x
, 0);
8578 rtx x1
= XEXP (x
, 1);
8580 /* Check the first level. */
8583 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8584 num_sign_bit_copies_with_known (x0
, mode
));
8586 /* Check the second level. */
8587 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8588 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8589 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8591 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8592 num_sign_bit_copies_with_known (x1
, mode
));
8594 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8595 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8596 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8598 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8599 num_sign_bit_copies_with_known (x0
, mode
));
8602 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8605 /* Return the number of bits at the high-order end of X that are known to
8606 be equal to the sign bit. X will be used in mode MODE; if MODE is
8607 VOIDmode, X will be used in its own mode. The returned value will always
8608 be between 1 and the number of bits in MODE. */
8611 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8612 enum machine_mode known_mode
,
8613 unsigned int known_ret
)
8615 enum rtx_code code
= GET_CODE (x
);
8616 unsigned int bitwidth
;
8617 int num0
, num1
, result
;
8618 unsigned HOST_WIDE_INT nonzero
;
8621 /* If we weren't given a mode, use the mode of X. If the mode is still
8622 VOIDmode, we don't know anything. Likewise if one of the modes is
8625 if (mode
== VOIDmode
)
8626 mode
= GET_MODE (x
);
8628 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8631 bitwidth
= GET_MODE_BITSIZE (mode
);
8633 /* For a smaller object, just ignore the high bits. */
8634 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8636 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8638 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8641 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8643 #ifndef WORD_REGISTER_OPERATIONS
8644 /* If this machine does not do all register operations on the entire
8645 register and MODE is wider than the mode of X, we can say nothing
8646 at all about the high-order bits. */
8649 /* Likewise on machines that do, if the mode of the object is smaller
8650 than a word and loads of that size don't sign extend, we can say
8651 nothing about the high order bits. */
8652 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8653 #ifdef LOAD_EXTEND_OP
8654 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8665 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8666 /* If pointers extend signed and this is a pointer in Pmode, say that
8667 all the bits above ptr_mode are known to be sign bit copies. */
8668 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8670 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8673 if (reg_last_set_value
[REGNO (x
)] != 0
8674 && reg_last_set_mode
[REGNO (x
)] == mode
8675 && (reg_last_set_label
[REGNO (x
)] == label_tick
8676 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8677 && REG_N_SETS (REGNO (x
)) == 1
8678 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8680 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8681 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8683 tem
= get_last_value (x
);
8685 return num_sign_bit_copies_with_known (tem
, mode
);
8687 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8688 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8689 return reg_sign_bit_copies
[REGNO (x
)];
8693 #ifdef LOAD_EXTEND_OP
8694 /* Some RISC machines sign-extend all loads of smaller than a word. */
8695 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8696 return MAX (1, ((int) bitwidth
8697 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8702 /* If the constant is negative, take its 1's complement and remask.
8703 Then see how many zero bits we have. */
8704 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8705 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8706 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8707 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8709 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8712 /* If this is a SUBREG for a promoted object that is sign-extended
8713 and we are looking at it in a wider mode, we know that at least the
8714 high-order bits are known to be sign bit copies. */
8716 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8718 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8719 return MAX ((int) bitwidth
8720 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8724 /* For a smaller object, just ignore the high bits. */
8725 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8727 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8728 return MAX (1, (num0
8729 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8733 #ifdef WORD_REGISTER_OPERATIONS
8734 #ifdef LOAD_EXTEND_OP
8735 /* For paradoxical SUBREGs on machines where all register operations
8736 affect the entire register, just look inside. Note that we are
8737 passing MODE to the recursive call, so the number of sign bit copies
8738 will remain relative to that mode, not the inner mode. */
8740 /* This works only if loads sign extend. Otherwise, if we get a
8741 reload for the inner part, it may be loaded from the stack, and
8742 then we lose all sign bit copies that existed before the store
8745 if ((GET_MODE_SIZE (GET_MODE (x
))
8746 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8747 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8748 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8749 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8755 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8756 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8760 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8761 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8764 /* For a smaller object, just ignore the high bits. */
8765 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8766 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8770 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8772 case ROTATE
: case ROTATERT
:
8773 /* If we are rotating left by a number of bits less than the number
8774 of sign bit copies, we can just subtract that amount from the
8776 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8777 && INTVAL (XEXP (x
, 1)) >= 0
8778 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8780 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8781 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8782 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8787 /* In general, this subtracts one sign bit copy. But if the value
8788 is known to be positive, the number of sign bit copies is the
8789 same as that of the input. Finally, if the input has just one bit
8790 that might be nonzero, all the bits are copies of the sign bit. */
8791 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8792 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8793 return num0
> 1 ? num0
- 1 : 1;
8795 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8800 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8805 case IOR
: case AND
: case XOR
:
8806 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8807 /* Logical operations will preserve the number of sign-bit copies.
8808 MIN and MAX operations always return one of the operands. */
8809 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8810 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8811 return MIN (num0
, num1
);
8813 case PLUS
: case MINUS
:
8814 /* For addition and subtraction, we can have a 1-bit carry. However,
8815 if we are subtracting 1 from a positive number, there will not
8816 be such a carry. Furthermore, if the positive number is known to
8817 be 0 or 1, we know the result is either -1 or 0. */
8819 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8820 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8822 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8823 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8824 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8825 : bitwidth
- floor_log2 (nonzero
) - 1);
8828 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8829 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8830 result
= MAX (1, MIN (num0
, num1
) - 1);
8832 #ifdef POINTERS_EXTEND_UNSIGNED
8833 /* If pointers extend signed and this is an addition or subtraction
8834 to a pointer in Pmode, all the bits above ptr_mode are known to be
8836 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8837 && (code
== PLUS
|| code
== MINUS
)
8838 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8839 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8840 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8846 /* The number of bits of the product is the sum of the number of
8847 bits of both terms. However, unless one of the terms if known
8848 to be positive, we must allow for an additional bit since negating
8849 a negative number can remove one sign bit copy. */
8851 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8852 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8854 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8856 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8857 || (((nonzero_bits (XEXP (x
, 0), mode
)
8858 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8859 && ((nonzero_bits (XEXP (x
, 1), mode
)
8860 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8863 return MAX (1, result
);
8866 /* The result must be <= the first operand. If the first operand
8867 has the high bit set, we know nothing about the number of sign
8869 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8871 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8872 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8875 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8878 /* The result must be <= the second operand. */
8879 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8882 /* Similar to unsigned division, except that we have to worry about
8883 the case where the divisor is negative, in which case we have
8885 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8887 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8888 || (nonzero_bits (XEXP (x
, 1), mode
)
8889 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8895 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8897 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8898 || (nonzero_bits (XEXP (x
, 1), mode
)
8899 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8905 /* Shifts by a constant add to the number of bits equal to the
8907 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8908 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8909 && INTVAL (XEXP (x
, 1)) > 0)
8910 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8915 /* Left shifts destroy copies. */
8916 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8917 || INTVAL (XEXP (x
, 1)) < 0
8918 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8921 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8922 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8925 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8926 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8927 return MIN (num0
, num1
);
8929 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8930 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8931 case GEU
: case GTU
: case LEU
: case LTU
:
8932 case UNORDERED
: case ORDERED
:
8933 /* If the constant is negative, take its 1's complement and remask.
8934 Then see how many zero bits we have. */
8935 nonzero
= STORE_FLAG_VALUE
;
8936 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8937 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8938 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8940 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8947 /* If we haven't been able to figure it out by one of the above rules,
8948 see if some of the high-order bits are known to be zero. If so,
8949 count those bits and return one less than that amount. If we can't
8950 safely compute the mask for this mode, always return BITWIDTH. */
8952 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8955 nonzero
= nonzero_bits (x
, mode
);
8956 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8957 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8960 /* Return the number of "extended" bits there are in X, when interpreted
8961 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8962 unsigned quantities, this is the number of high-order zero bits.
8963 For signed quantities, this is the number of copies of the sign bit
8964 minus 1. In both case, this function returns the number of "spare"
8965 bits. For example, if two quantities for which this function returns
8966 at least 1 are added, the addition is known not to overflow.
8968 This function will always return 0 unless called during combine, which
8969 implies that it must be called from a define_split. */
8972 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8974 if (nonzero_sign_valid
== 0)
8978 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8979 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8980 - floor_log2 (nonzero_bits (x
, mode
)))
8982 : num_sign_bit_copies (x
, mode
) - 1);
8985 /* This function is called from `simplify_shift_const' to merge two
8986 outer operations. Specifically, we have already found that we need
8987 to perform operation *POP0 with constant *PCONST0 at the outermost
8988 position. We would now like to also perform OP1 with constant CONST1
8989 (with *POP0 being done last).
8991 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8992 the resulting operation. *PCOMP_P is set to 1 if we would need to
8993 complement the innermost operand, otherwise it is unchanged.
8995 MODE is the mode in which the operation will be done. No bits outside
8996 the width of this mode matter. It is assumed that the width of this mode
8997 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8999 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9000 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9001 result is simply *PCONST0.
9003 If the resulting operation cannot be expressed as one operation, we
9004 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9007 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9009 enum rtx_code op0
= *pop0
;
9010 HOST_WIDE_INT const0
= *pconst0
;
9012 const0
&= GET_MODE_MASK (mode
);
9013 const1
&= GET_MODE_MASK (mode
);
9015 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9019 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9022 if (op1
== NIL
|| op0
== SET
)
9025 else if (op0
== NIL
)
9026 op0
= op1
, const0
= const1
;
9028 else if (op0
== op1
)
9052 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9053 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9056 /* If the two constants aren't the same, we can't do anything. The
9057 remaining six cases can all be done. */
9058 else if (const0
!= const1
)
9066 /* (a & b) | b == b */
9068 else /* op1 == XOR */
9069 /* (a ^ b) | b == a | b */
9075 /* (a & b) ^ b == (~a) & b */
9076 op0
= AND
, *pcomp_p
= 1;
9077 else /* op1 == IOR */
9078 /* (a | b) ^ b == a & ~b */
9079 op0
= AND
, const0
= ~const0
;
9084 /* (a | b) & b == b */
9086 else /* op1 == XOR */
9087 /* (a ^ b) & b) == (~a) & b */
9094 /* Check for NO-OP cases. */
9095 const0
&= GET_MODE_MASK (mode
);
9097 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9099 else if (const0
== 0 && op0
== AND
)
9101 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9105 /* ??? Slightly redundant with the above mask, but not entirely.
9106 Moving this above means we'd have to sign-extend the mode mask
9107 for the final test. */
9108 const0
= trunc_int_for_mode (const0
, mode
);
9116 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9117 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9118 that we started with.
9120 The shift is normally computed in the widest mode we find in VAROP, as
9121 long as it isn't a different number of words than RESULT_MODE. Exceptions
9122 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9125 simplify_shift_const (rtx x
, enum rtx_code code
,
9126 enum machine_mode result_mode
, rtx varop
,
9129 enum rtx_code orig_code
= code
;
9132 enum machine_mode mode
= result_mode
;
9133 enum machine_mode shift_mode
, tmode
;
9134 unsigned int mode_words
9135 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9136 /* We form (outer_op (code varop count) (outer_const)). */
9137 enum rtx_code outer_op
= NIL
;
9138 HOST_WIDE_INT outer_const
= 0;
9140 int complement_p
= 0;
9143 /* Make sure and truncate the "natural" shift on the way in. We don't
9144 want to do this inside the loop as it makes it more difficult to
9146 if (SHIFT_COUNT_TRUNCATED
)
9147 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9149 /* If we were given an invalid count, don't do anything except exactly
9150 what was requested. */
9152 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9157 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9162 /* Unless one of the branches of the `if' in this loop does a `continue',
9163 we will `break' the loop after the `if'. */
9167 /* If we have an operand of (clobber (const_int 0)), just return that
9169 if (GET_CODE (varop
) == CLOBBER
)
9172 /* If we discovered we had to complement VAROP, leave. Making a NOT
9173 here would cause an infinite loop. */
9177 /* Convert ROTATERT to ROTATE. */
9178 if (code
== ROTATERT
)
9180 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9182 if (VECTOR_MODE_P (result_mode
))
9183 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9185 count
= bitsize
- count
;
9188 /* We need to determine what mode we will do the shift in. If the
9189 shift is a right shift or a ROTATE, we must always do it in the mode
9190 it was originally done in. Otherwise, we can do it in MODE, the
9191 widest mode encountered. */
9193 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9194 ? result_mode
: mode
);
9196 /* Handle cases where the count is greater than the size of the mode
9197 minus 1. For ASHIFT, use the size minus one as the count (this can
9198 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9199 take the count modulo the size. For other shifts, the result is
9202 Since these shifts are being produced by the compiler by combining
9203 multiple operations, each of which are defined, we know what the
9204 result is supposed to be. */
9206 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9208 if (code
== ASHIFTRT
)
9209 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9210 else if (code
== ROTATE
|| code
== ROTATERT
)
9211 count
%= GET_MODE_BITSIZE (shift_mode
);
9214 /* We can't simply return zero because there may be an
9222 /* An arithmetic right shift of a quantity known to be -1 or 0
9224 if (code
== ASHIFTRT
9225 && (num_sign_bit_copies (varop
, shift_mode
)
9226 == GET_MODE_BITSIZE (shift_mode
)))
9232 /* If we are doing an arithmetic right shift and discarding all but
9233 the sign bit copies, this is equivalent to doing a shift by the
9234 bitsize minus one. Convert it into that shift because it will often
9235 allow other simplifications. */
9237 if (code
== ASHIFTRT
9238 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9239 >= GET_MODE_BITSIZE (shift_mode
)))
9240 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9242 /* We simplify the tests below and elsewhere by converting
9243 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9244 `make_compound_operation' will convert it to an ASHIFTRT for
9245 those machines (such as VAX) that don't have an LSHIFTRT. */
9246 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9248 && ((nonzero_bits (varop
, shift_mode
)
9249 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9253 if (code
== LSHIFTRT
9254 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9255 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9258 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9259 && !((nonzero_bits (varop
, shift_mode
) << count
)
9260 & GET_MODE_MASK (shift_mode
)))
9263 switch (GET_CODE (varop
))
9269 new = expand_compound_operation (varop
);
9278 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9279 minus the width of a smaller mode, we can do this with a
9280 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9281 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9282 && ! mode_dependent_address_p (XEXP (varop
, 0))
9283 && ! MEM_VOLATILE_P (varop
)
9284 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9285 MODE_INT
, 1)) != BLKmode
)
9287 new = adjust_address_nv (varop
, tmode
,
9288 BYTES_BIG_ENDIAN
? 0
9289 : count
/ BITS_PER_UNIT
);
9291 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9292 : ZERO_EXTEND
, mode
, new);
9299 /* Similar to the case above, except that we can only do this if
9300 the resulting mode is the same as that of the underlying
9301 MEM and adjust the address depending on the *bits* endianness
9302 because of the way that bit-field extract insns are defined. */
9303 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9304 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9305 MODE_INT
, 1)) != BLKmode
9306 && tmode
== GET_MODE (XEXP (varop
, 0)))
9308 if (BITS_BIG_ENDIAN
)
9309 new = XEXP (varop
, 0);
9312 new = copy_rtx (XEXP (varop
, 0));
9313 SUBST (XEXP (new, 0),
9314 plus_constant (XEXP (new, 0),
9315 count
/ BITS_PER_UNIT
));
9318 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9319 : ZERO_EXTEND
, mode
, new);
9326 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9327 the same number of words as what we've seen so far. Then store
9328 the widest mode in MODE. */
9329 if (subreg_lowpart_p (varop
)
9330 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9331 > GET_MODE_SIZE (GET_MODE (varop
)))
9332 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9333 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9336 varop
= SUBREG_REG (varop
);
9337 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9338 mode
= GET_MODE (varop
);
9344 /* Some machines use MULT instead of ASHIFT because MULT
9345 is cheaper. But it is still better on those machines to
9346 merge two shifts into one. */
9347 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9348 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9351 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9352 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9358 /* Similar, for when divides are cheaper. */
9359 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9360 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9363 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9364 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9370 /* If we are extracting just the sign bit of an arithmetic
9371 right shift, that shift is not needed. However, the sign
9372 bit of a wider mode may be different from what would be
9373 interpreted as the sign bit in a narrower mode, so, if
9374 the result is narrower, don't discard the shift. */
9375 if (code
== LSHIFTRT
9376 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9377 && (GET_MODE_BITSIZE (result_mode
)
9378 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9380 varop
= XEXP (varop
, 0);
9384 /* ... fall through ... */
9389 /* Here we have two nested shifts. The result is usually the
9390 AND of a new shift with a mask. We compute the result below. */
9391 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9392 && INTVAL (XEXP (varop
, 1)) >= 0
9393 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9394 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9395 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9397 enum rtx_code first_code
= GET_CODE (varop
);
9398 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9399 unsigned HOST_WIDE_INT mask
;
9402 /* We have one common special case. We can't do any merging if
9403 the inner code is an ASHIFTRT of a smaller mode. However, if
9404 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9405 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9406 we can convert it to
9407 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9408 This simplifies certain SIGN_EXTEND operations. */
9409 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9410 && count
== (unsigned int)
9411 (GET_MODE_BITSIZE (result_mode
)
9412 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9414 /* C3 has the low-order C1 bits zero. */
9416 mask
= (GET_MODE_MASK (mode
)
9417 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9419 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9420 XEXP (varop
, 0), mask
);
9421 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9423 count
= first_count
;
9428 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9429 than C1 high-order bits equal to the sign bit, we can convert
9430 this to either an ASHIFT or an ASHIFTRT depending on the
9433 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9435 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9436 && GET_MODE (varop
) == shift_mode
9437 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9440 varop
= XEXP (varop
, 0);
9442 signed_count
= count
- first_count
;
9443 if (signed_count
< 0)
9444 count
= -signed_count
, code
= ASHIFT
;
9446 count
= signed_count
;
9451 /* There are some cases we can't do. If CODE is ASHIFTRT,
9452 we can only do this if FIRST_CODE is also ASHIFTRT.
9454 We can't do the case when CODE is ROTATE and FIRST_CODE is
9457 If the mode of this shift is not the mode of the outer shift,
9458 we can't do this if either shift is a right shift or ROTATE.
9460 Finally, we can't do any of these if the mode is too wide
9461 unless the codes are the same.
9463 Handle the case where the shift codes are the same
9466 if (code
== first_code
)
9468 if (GET_MODE (varop
) != result_mode
9469 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9473 count
+= first_count
;
9474 varop
= XEXP (varop
, 0);
9478 if (code
== ASHIFTRT
9479 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9480 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9481 || (GET_MODE (varop
) != result_mode
9482 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9483 || first_code
== ROTATE
9484 || code
== ROTATE
)))
9487 /* To compute the mask to apply after the shift, shift the
9488 nonzero bits of the inner shift the same way the
9489 outer shift will. */
9491 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9494 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9497 /* Give up if we can't compute an outer operation to use. */
9499 || GET_CODE (mask_rtx
) != CONST_INT
9500 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9502 result_mode
, &complement_p
))
9505 /* If the shifts are in the same direction, we add the
9506 counts. Otherwise, we subtract them. */
9507 signed_count
= count
;
9508 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9509 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9510 signed_count
+= first_count
;
9512 signed_count
-= first_count
;
9514 /* If COUNT is positive, the new shift is usually CODE,
9515 except for the two exceptions below, in which case it is
9516 FIRST_CODE. If the count is negative, FIRST_CODE should
9518 if (signed_count
> 0
9519 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9520 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9521 code
= first_code
, count
= signed_count
;
9522 else if (signed_count
< 0)
9523 code
= first_code
, count
= -signed_count
;
9525 count
= signed_count
;
9527 varop
= XEXP (varop
, 0);
9531 /* If we have (A << B << C) for any shift, we can convert this to
9532 (A << C << B). This wins if A is a constant. Only try this if
9533 B is not a constant. */
9535 else if (GET_CODE (varop
) == code
9536 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9538 = simplify_binary_operation (code
, mode
,
9542 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9549 /* Make this fit the case below. */
9550 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9551 GEN_INT (GET_MODE_MASK (mode
)));
9557 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9558 with C the size of VAROP - 1 and the shift is logical if
9559 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9560 we have an (le X 0) operation. If we have an arithmetic shift
9561 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9562 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9564 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9565 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9566 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9567 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9568 && count
== (unsigned int)
9569 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9570 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9573 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9576 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9577 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9582 /* If we have (shift (logical)), move the logical to the outside
9583 to allow it to possibly combine with another logical and the
9584 shift to combine with another shift. This also canonicalizes to
9585 what a ZERO_EXTRACT looks like. Also, some machines have
9586 (and (shift)) insns. */
9588 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9589 /* We can't do this if we have (ashiftrt (xor)) and the
9590 constant has its sign bit set in shift_mode. */
9591 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9592 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9594 && (new = simplify_binary_operation (code
, result_mode
,
9596 GEN_INT (count
))) != 0
9597 && GET_CODE (new) == CONST_INT
9598 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9599 INTVAL (new), result_mode
, &complement_p
))
9601 varop
= XEXP (varop
, 0);
9605 /* If we can't do that, try to simplify the shift in each arm of the
9606 logical expression, make a new logical expression, and apply
9607 the inverse distributive law. This also can't be done
9608 for some (ashiftrt (xor)). */
9609 if (code
!= ASHIFTRT
|| GET_CODE (varop
)!= XOR
9610 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9613 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9614 XEXP (varop
, 0), count
);
9615 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9616 XEXP (varop
, 1), count
);
9618 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9619 varop
= apply_distributive_law (varop
);
9626 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9627 says that the sign bit can be tested, FOO has mode MODE, C is
9628 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9629 that may be nonzero. */
9630 if (code
== LSHIFTRT
9631 && XEXP (varop
, 1) == const0_rtx
9632 && GET_MODE (XEXP (varop
, 0)) == result_mode
9633 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9634 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9635 && ((STORE_FLAG_VALUE
9636 & ((HOST_WIDE_INT
) 1
9637 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9638 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9639 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9640 (HOST_WIDE_INT
) 1, result_mode
,
9643 varop
= XEXP (varop
, 0);
9650 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9651 than the number of bits in the mode is equivalent to A. */
9652 if (code
== LSHIFTRT
9653 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9654 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9656 varop
= XEXP (varop
, 0);
9661 /* NEG commutes with ASHIFT since it is multiplication. Move the
9662 NEG outside to allow shifts to combine. */
9664 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9665 (HOST_WIDE_INT
) 0, result_mode
,
9668 varop
= XEXP (varop
, 0);
9674 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9675 is one less than the number of bits in the mode is
9676 equivalent to (xor A 1). */
9677 if (code
== LSHIFTRT
9678 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9679 && XEXP (varop
, 1) == constm1_rtx
9680 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9681 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9682 (HOST_WIDE_INT
) 1, result_mode
,
9686 varop
= XEXP (varop
, 0);
9690 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9691 that might be nonzero in BAR are those being shifted out and those
9692 bits are known zero in FOO, we can replace the PLUS with FOO.
9693 Similarly in the other operand order. This code occurs when
9694 we are computing the size of a variable-size array. */
9696 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9697 && count
< HOST_BITS_PER_WIDE_INT
9698 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9699 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9700 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9702 varop
= XEXP (varop
, 0);
9705 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9706 && count
< HOST_BITS_PER_WIDE_INT
9707 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9708 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9710 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9711 & nonzero_bits (XEXP (varop
, 1),
9714 varop
= XEXP (varop
, 1);
9718 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9720 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9721 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9723 GEN_INT (count
))) != 0
9724 && GET_CODE (new) == CONST_INT
9725 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9726 INTVAL (new), result_mode
, &complement_p
))
9728 varop
= XEXP (varop
, 0);
9734 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9735 with C the size of VAROP - 1 and the shift is logical if
9736 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9737 we have a (gt X 0) operation. If the shift is arithmetic with
9738 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9739 we have a (neg (gt X 0)) operation. */
9741 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9742 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9743 && count
== (unsigned int)
9744 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9745 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9746 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9747 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9749 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9752 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9755 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9756 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9763 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9764 if the truncate does not affect the value. */
9765 if (code
== LSHIFTRT
9766 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9767 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9768 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9769 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9770 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9772 rtx varop_inner
= XEXP (varop
, 0);
9775 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9776 XEXP (varop_inner
, 0),
9778 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9779 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9792 /* We need to determine what mode to do the shift in. If the shift is
9793 a right shift or ROTATE, we must always do it in the mode it was
9794 originally done in. Otherwise, we can do it in MODE, the widest mode
9795 encountered. The code we care about is that of the shift that will
9796 actually be done, not the shift that was originally requested. */
9798 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9799 ? result_mode
: mode
);
9801 /* We have now finished analyzing the shift. The result should be
9802 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9803 OUTER_OP is non-NIL, it is an operation that needs to be applied
9804 to the result of the shift. OUTER_CONST is the relevant constant,
9805 but we must turn off all bits turned off in the shift.
9807 If we were passed a value for X, see if we can use any pieces of
9808 it. If not, make new rtx. */
9810 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9811 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9812 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9813 const_rtx
= XEXP (x
, 1);
9815 const_rtx
= GEN_INT (count
);
9817 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9818 && GET_MODE (XEXP (x
, 0)) == shift_mode
9819 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9820 varop
= XEXP (x
, 0);
9821 else if (GET_MODE (varop
) != shift_mode
)
9822 varop
= gen_lowpart (shift_mode
, varop
);
9824 /* If we can't make the SUBREG, try to return what we were given. */
9825 if (GET_CODE (varop
) == CLOBBER
)
9826 return x
? x
: varop
;
9828 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9832 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9834 /* If we have an outer operation and we just made a shift, it is
9835 possible that we could have simplified the shift were it not
9836 for the outer operation. So try to do the simplification
9839 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9840 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9841 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9842 INTVAL (XEXP (x
, 1)));
9844 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9845 turn off all the bits that the shift would have turned off. */
9846 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9847 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9848 GET_MODE_MASK (result_mode
) >> orig_count
);
9850 /* Do the remainder of the processing in RESULT_MODE. */
9851 x
= gen_lowpart (result_mode
, x
);
9853 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9856 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9858 if (outer_op
!= NIL
)
9860 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9861 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9863 if (outer_op
== AND
)
9864 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9865 else if (outer_op
== SET
)
9866 /* This means that we have determined that the result is
9867 equivalent to a constant. This should be rare. */
9868 x
= GEN_INT (outer_const
);
9869 else if (GET_RTX_CLASS (outer_op
) == '1')
9870 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9872 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9878 /* Like recog, but we receive the address of a pointer to a new pattern.
9879 We try to match the rtx that the pointer points to.
9880 If that fails, we may try to modify or replace the pattern,
9881 storing the replacement into the same pointer object.
9883 Modifications include deletion or addition of CLOBBERs.
9885 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9886 the CLOBBERs are placed.
9888 The value is the final insn code from the pattern ultimately matched,
9892 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9895 int insn_code_number
;
9896 int num_clobbers_to_add
= 0;
9899 rtx old_notes
, old_pat
;
9901 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9902 we use to indicate that something didn't match. If we find such a
9903 thing, force rejection. */
9904 if (GET_CODE (pat
) == PARALLEL
)
9905 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9906 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9907 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9910 old_pat
= PATTERN (insn
);
9911 old_notes
= REG_NOTES (insn
);
9912 PATTERN (insn
) = pat
;
9913 REG_NOTES (insn
) = 0;
9915 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9917 /* If it isn't, there is the possibility that we previously had an insn
9918 that clobbered some register as a side effect, but the combined
9919 insn doesn't need to do that. So try once more without the clobbers
9920 unless this represents an ASM insn. */
9922 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9923 && GET_CODE (pat
) == PARALLEL
)
9927 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9928 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9931 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9935 SUBST_INT (XVECLEN (pat
, 0), pos
);
9938 pat
= XVECEXP (pat
, 0, 0);
9940 PATTERN (insn
) = pat
;
9941 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9943 PATTERN (insn
) = old_pat
;
9944 REG_NOTES (insn
) = old_notes
;
9946 /* Recognize all noop sets, these will be killed by followup pass. */
9947 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9948 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9950 /* If we had any clobbers to add, make a new pattern than contains
9951 them. Then check to make sure that all of them are dead. */
9952 if (num_clobbers_to_add
)
9954 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9955 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9957 + num_clobbers_to_add
)
9958 : num_clobbers_to_add
+ 1));
9960 if (GET_CODE (pat
) == PARALLEL
)
9961 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9962 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9964 XVECEXP (newpat
, 0, 0) = pat
;
9966 add_clobbers (newpat
, insn_code_number
);
9968 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9969 i
< XVECLEN (newpat
, 0); i
++)
9971 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9972 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9974 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9975 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9983 return insn_code_number
;
9986 /* Like gen_lowpart_general but for use by combine. In combine it
9987 is not possible to create any new pseudoregs. However, it is
9988 safe to create invalid memory addresses, because combine will
9989 try to recognize them and all they will do is make the combine
9992 If for some reason this cannot do its job, an rtx
9993 (clobber (const_int 0)) is returned.
9994 An insn containing that will not be recognized. */
9997 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
10001 if (GET_MODE (x
) == mode
)
10004 /* Return identity if this is a CONST or symbolic
10007 && (GET_CODE (x
) == CONST
10008 || GET_CODE (x
) == SYMBOL_REF
10009 || GET_CODE (x
) == LABEL_REF
))
10012 /* We can only support MODE being wider than a word if X is a
10013 constant integer or has a mode the same size. */
10015 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10016 && ! ((GET_MODE (x
) == VOIDmode
10017 && (GET_CODE (x
) == CONST_INT
10018 || GET_CODE (x
) == CONST_DOUBLE
))
10019 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10020 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10022 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10023 won't know what to do. So we will strip off the SUBREG here and
10024 process normally. */
10025 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10027 x
= SUBREG_REG (x
);
10028 if (GET_MODE (x
) == mode
)
10032 result
= gen_lowpart_common (mode
, x
);
10033 #ifdef CANNOT_CHANGE_MODE_CLASS
10035 && GET_CODE (result
) == SUBREG
10036 && GET_CODE (SUBREG_REG (result
)) == REG
10037 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10038 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10040 + GET_MODE (result
));
10046 if (GET_CODE (x
) == MEM
)
10050 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10052 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10053 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10055 /* If we want to refer to something bigger than the original memref,
10056 generate a perverse subreg instead. That will force a reload
10057 of the original memref X. */
10058 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10059 return gen_rtx_SUBREG (mode
, x
, 0);
10061 if (WORDS_BIG_ENDIAN
)
10062 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10063 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10065 if (BYTES_BIG_ENDIAN
)
10067 /* Adjust the address so that the address-after-the-data is
10069 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10070 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10073 return adjust_address_nv (x
, mode
, offset
);
10076 /* If X is a comparison operator, rewrite it in a new mode. This
10077 probably won't match, but may allow further simplifications. */
10078 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10079 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10081 /* If we couldn't simplify X any other way, just enclose it in a
10082 SUBREG. Normally, this SUBREG won't match, but some patterns may
10083 include an explicit SUBREG or we may simplify it further in combine. */
10088 enum machine_mode sub_mode
= GET_MODE (x
);
10090 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10091 if (sub_mode
== VOIDmode
)
10093 sub_mode
= int_mode_for_mode (mode
);
10094 x
= gen_lowpart_common (sub_mode
, x
);
10096 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10098 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10101 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10105 /* These routines make binary and unary operations by first seeing if they
10106 fold; if not, a new expression is allocated. */
10109 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10114 if (GET_CODE (op0
) == CLOBBER
)
10116 else if (GET_CODE (op1
) == CLOBBER
)
10119 if (GET_RTX_CLASS (code
) == 'c'
10120 && swap_commutative_operands_p (op0
, op1
))
10121 tem
= op0
, op0
= op1
, op1
= tem
;
10123 if (GET_RTX_CLASS (code
) == '<')
10125 enum machine_mode op_mode
= GET_MODE (op0
);
10127 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10128 just (REL_OP X Y). */
10129 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10131 op1
= XEXP (op0
, 1);
10132 op0
= XEXP (op0
, 0);
10133 op_mode
= GET_MODE (op0
);
10136 if (op_mode
== VOIDmode
)
10137 op_mode
= GET_MODE (op1
);
10138 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10141 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10146 /* Put complex operands first and constants second. */
10147 if (GET_RTX_CLASS (code
) == 'c'
10148 && swap_commutative_operands_p (op0
, op1
))
10149 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10151 /* If we are turning off bits already known off in OP0, we need not do
10153 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10154 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10155 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10158 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10161 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10162 comparison code that will be tested.
10164 The result is a possibly different comparison code to use. *POP0 and
10165 *POP1 may be updated.
10167 It is possible that we might detect that a comparison is either always
10168 true or always false. However, we do not perform general constant
10169 folding in combine, so this knowledge isn't useful. Such tautologies
10170 should have been detected earlier. Hence we ignore all such cases. */
10172 static enum rtx_code
10173 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10179 enum machine_mode mode
, tmode
;
10181 /* Try a few ways of applying the same transformation to both operands. */
10184 #ifndef WORD_REGISTER_OPERATIONS
10185 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10186 so check specially. */
10187 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10188 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10189 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10190 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10191 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10192 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10193 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10194 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10195 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10196 && XEXP (op0
, 1) == XEXP (op1
, 1)
10197 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10198 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10199 && (INTVAL (XEXP (op0
, 1))
10200 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10201 - (GET_MODE_BITSIZE
10202 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10204 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10205 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10209 /* If both operands are the same constant shift, see if we can ignore the
10210 shift. We can if the shift is a rotate or if the bits shifted out of
10211 this shift are known to be zero for both inputs and if the type of
10212 comparison is compatible with the shift. */
10213 if (GET_CODE (op0
) == GET_CODE (op1
)
10214 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10215 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10216 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10217 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10218 || (GET_CODE (op0
) == ASHIFTRT
10219 && (code
!= GTU
&& code
!= LTU
10220 && code
!= GEU
&& code
!= LEU
)))
10221 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10222 && INTVAL (XEXP (op0
, 1)) >= 0
10223 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10224 && XEXP (op0
, 1) == XEXP (op1
, 1))
10226 enum machine_mode mode
= GET_MODE (op0
);
10227 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10228 int shift_count
= INTVAL (XEXP (op0
, 1));
10230 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10231 mask
&= (mask
>> shift_count
) << shift_count
;
10232 else if (GET_CODE (op0
) == ASHIFT
)
10233 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10235 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10236 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10237 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10242 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10243 SUBREGs are of the same mode, and, in both cases, the AND would
10244 be redundant if the comparison was done in the narrower mode,
10245 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10246 and the operand's possibly nonzero bits are 0xffffff01; in that case
10247 if we only care about QImode, we don't need the AND). This case
10248 occurs if the output mode of an scc insn is not SImode and
10249 STORE_FLAG_VALUE == 1 (e.g., the 386).
10251 Similarly, check for a case where the AND's are ZERO_EXTEND
10252 operations from some narrower mode even though a SUBREG is not
10255 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10256 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10257 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10259 rtx inner_op0
= XEXP (op0
, 0);
10260 rtx inner_op1
= XEXP (op1
, 0);
10261 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10262 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10265 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10266 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10267 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10268 && (GET_MODE (SUBREG_REG (inner_op0
))
10269 == GET_MODE (SUBREG_REG (inner_op1
)))
10270 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10271 <= HOST_BITS_PER_WIDE_INT
)
10272 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10273 GET_MODE (SUBREG_REG (inner_op0
)))))
10274 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10275 GET_MODE (SUBREG_REG (inner_op1
))))))
10277 op0
= SUBREG_REG (inner_op0
);
10278 op1
= SUBREG_REG (inner_op1
);
10280 /* The resulting comparison is always unsigned since we masked
10281 off the original sign bit. */
10282 code
= unsigned_condition (code
);
10288 for (tmode
= GET_CLASS_NARROWEST_MODE
10289 (GET_MODE_CLASS (GET_MODE (op0
)));
10290 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10291 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10293 op0
= gen_lowpart (tmode
, inner_op0
);
10294 op1
= gen_lowpart (tmode
, inner_op1
);
10295 code
= unsigned_condition (code
);
10304 /* If both operands are NOT, we can strip off the outer operation
10305 and adjust the comparison code for swapped operands; similarly for
10306 NEG, except that this must be an equality comparison. */
10307 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10308 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10309 && (code
== EQ
|| code
== NE
)))
10310 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10316 /* If the first operand is a constant, swap the operands and adjust the
10317 comparison code appropriately, but don't do this if the second operand
10318 is already a constant integer. */
10319 if (swap_commutative_operands_p (op0
, op1
))
10321 tem
= op0
, op0
= op1
, op1
= tem
;
10322 code
= swap_condition (code
);
10325 /* We now enter a loop during which we will try to simplify the comparison.
10326 For the most part, we only are concerned with comparisons with zero,
10327 but some things may really be comparisons with zero but not start
10328 out looking that way. */
10330 while (GET_CODE (op1
) == CONST_INT
)
10332 enum machine_mode mode
= GET_MODE (op0
);
10333 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10334 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10335 int equality_comparison_p
;
10336 int sign_bit_comparison_p
;
10337 int unsigned_comparison_p
;
10338 HOST_WIDE_INT const_op
;
10340 /* We only want to handle integral modes. This catches VOIDmode,
10341 CCmode, and the floating-point modes. An exception is that we
10342 can handle VOIDmode if OP0 is a COMPARE or a comparison
10345 if (GET_MODE_CLASS (mode
) != MODE_INT
10346 && ! (mode
== VOIDmode
10347 && (GET_CODE (op0
) == COMPARE
10348 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10351 /* Get the constant we are comparing against and turn off all bits
10352 not on in our mode. */
10353 const_op
= INTVAL (op1
);
10354 if (mode
!= VOIDmode
)
10355 const_op
= trunc_int_for_mode (const_op
, mode
);
10356 op1
= GEN_INT (const_op
);
10358 /* If we are comparing against a constant power of two and the value
10359 being compared can only have that single bit nonzero (e.g., it was
10360 `and'ed with that bit), we can replace this with a comparison
10363 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10364 || code
== LT
|| code
== LTU
)
10365 && mode_width
<= HOST_BITS_PER_WIDE_INT
10366 && exact_log2 (const_op
) >= 0
10367 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10369 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10370 op1
= const0_rtx
, const_op
= 0;
10373 /* Similarly, if we are comparing a value known to be either -1 or
10374 0 with -1, change it to the opposite comparison against zero. */
10377 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10378 || code
== GEU
|| code
== LTU
)
10379 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10381 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10382 op1
= const0_rtx
, const_op
= 0;
10385 /* Do some canonicalizations based on the comparison code. We prefer
10386 comparisons against zero and then prefer equality comparisons.
10387 If we can reduce the size of a constant, we will do that too. */
10392 /* < C is equivalent to <= (C - 1) */
10396 op1
= GEN_INT (const_op
);
10398 /* ... fall through to LE case below. */
10404 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10408 op1
= GEN_INT (const_op
);
10412 /* If we are doing a <= 0 comparison on a value known to have
10413 a zero sign bit, we can replace this with == 0. */
10414 else if (const_op
== 0
10415 && mode_width
<= HOST_BITS_PER_WIDE_INT
10416 && (nonzero_bits (op0
, mode
)
10417 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10422 /* >= C is equivalent to > (C - 1). */
10426 op1
= GEN_INT (const_op
);
10428 /* ... fall through to GT below. */
10434 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10438 op1
= GEN_INT (const_op
);
10442 /* If we are doing a > 0 comparison on a value known to have
10443 a zero sign bit, we can replace this with != 0. */
10444 else if (const_op
== 0
10445 && mode_width
<= HOST_BITS_PER_WIDE_INT
10446 && (nonzero_bits (op0
, mode
)
10447 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10452 /* < C is equivalent to <= (C - 1). */
10456 op1
= GEN_INT (const_op
);
10458 /* ... fall through ... */
10461 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10462 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10463 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10465 const_op
= 0, op1
= const0_rtx
;
10473 /* unsigned <= 0 is equivalent to == 0 */
10477 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10478 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10479 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10481 const_op
= 0, op1
= const0_rtx
;
10487 /* >= C is equivalent to < (C - 1). */
10491 op1
= GEN_INT (const_op
);
10493 /* ... fall through ... */
10496 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10497 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10498 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10500 const_op
= 0, op1
= const0_rtx
;
10508 /* unsigned > 0 is equivalent to != 0 */
10512 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10513 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10514 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10516 const_op
= 0, op1
= const0_rtx
;
10525 /* Compute some predicates to simplify code below. */
10527 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10528 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10529 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10532 /* If this is a sign bit comparison and we can do arithmetic in
10533 MODE, say that we will only be needing the sign bit of OP0. */
10534 if (sign_bit_comparison_p
10535 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10536 op0
= force_to_mode (op0
, mode
,
10538 << (GET_MODE_BITSIZE (mode
) - 1)),
10541 /* Now try cases based on the opcode of OP0. If none of the cases
10542 does a "continue", we exit this loop immediately after the
10545 switch (GET_CODE (op0
))
10548 /* If we are extracting a single bit from a variable position in
10549 a constant that has only a single bit set and are comparing it
10550 with zero, we can convert this into an equality comparison
10551 between the position and the location of the single bit. */
10552 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10553 have already reduced the shift count modulo the word size. */
10554 if (!SHIFT_COUNT_TRUNCATED
10555 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10556 && XEXP (op0
, 1) == const1_rtx
10557 && equality_comparison_p
&& const_op
== 0
10558 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10560 if (BITS_BIG_ENDIAN
)
10562 enum machine_mode new_mode
10563 = mode_for_extraction (EP_extzv
, 1);
10564 if (new_mode
== MAX_MACHINE_MODE
)
10565 i
= BITS_PER_WORD
- 1 - i
;
10569 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10573 op0
= XEXP (op0
, 2);
10577 /* Result is nonzero iff shift count is equal to I. */
10578 code
= reverse_condition (code
);
10582 /* ... fall through ... */
10585 tem
= expand_compound_operation (op0
);
10594 /* If testing for equality, we can take the NOT of the constant. */
10595 if (equality_comparison_p
10596 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10598 op0
= XEXP (op0
, 0);
10603 /* If just looking at the sign bit, reverse the sense of the
10605 if (sign_bit_comparison_p
)
10607 op0
= XEXP (op0
, 0);
10608 code
= (code
== GE
? LT
: GE
);
10614 /* If testing for equality, we can take the NEG of the constant. */
10615 if (equality_comparison_p
10616 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10618 op0
= XEXP (op0
, 0);
10623 /* The remaining cases only apply to comparisons with zero. */
10627 /* When X is ABS or is known positive,
10628 (neg X) is < 0 if and only if X != 0. */
10630 if (sign_bit_comparison_p
10631 && (GET_CODE (XEXP (op0
, 0)) == ABS
10632 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10633 && (nonzero_bits (XEXP (op0
, 0), mode
)
10634 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10636 op0
= XEXP (op0
, 0);
10637 code
= (code
== LT
? NE
: EQ
);
10641 /* If we have NEG of something whose two high-order bits are the
10642 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10643 if (num_sign_bit_copies (op0
, mode
) >= 2)
10645 op0
= XEXP (op0
, 0);
10646 code
= swap_condition (code
);
10652 /* If we are testing equality and our count is a constant, we
10653 can perform the inverse operation on our RHS. */
10654 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10655 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10656 op1
, XEXP (op0
, 1))) != 0)
10658 op0
= XEXP (op0
, 0);
10663 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10664 a particular bit. Convert it to an AND of a constant of that
10665 bit. This will be converted into a ZERO_EXTRACT. */
10666 if (const_op
== 0 && sign_bit_comparison_p
10667 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10668 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10670 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10673 - INTVAL (XEXP (op0
, 1)))));
10674 code
= (code
== LT
? NE
: EQ
);
10678 /* Fall through. */
10681 /* ABS is ignorable inside an equality comparison with zero. */
10682 if (const_op
== 0 && equality_comparison_p
)
10684 op0
= XEXP (op0
, 0);
10690 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10691 to (compare FOO CONST) if CONST fits in FOO's mode and we
10692 are either testing inequality or have an unsigned comparison
10693 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10694 if (! unsigned_comparison_p
10695 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10696 <= HOST_BITS_PER_WIDE_INT
)
10697 && ((unsigned HOST_WIDE_INT
) const_op
10698 < (((unsigned HOST_WIDE_INT
) 1
10699 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10701 op0
= XEXP (op0
, 0);
10707 /* Check for the case where we are comparing A - C1 with C2,
10708 both constants are smaller than 1/2 the maximum positive
10709 value in MODE, and the comparison is equality or unsigned.
10710 In that case, if A is either zero-extended to MODE or has
10711 sufficient sign bits so that the high-order bit in MODE
10712 is a copy of the sign in the inner mode, we can prove that it is
10713 safe to do the operation in the wider mode. This simplifies
10714 many range checks. */
10716 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10717 && subreg_lowpart_p (op0
)
10718 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10719 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10720 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10721 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10722 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10723 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10724 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10725 GET_MODE (SUBREG_REG (op0
)))
10726 & ~GET_MODE_MASK (mode
))
10727 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10728 GET_MODE (SUBREG_REG (op0
)))
10730 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10731 - GET_MODE_BITSIZE (mode
)))))
10733 op0
= SUBREG_REG (op0
);
10737 /* If the inner mode is narrower and we are extracting the low part,
10738 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10739 if (subreg_lowpart_p (op0
)
10740 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10741 /* Fall through */ ;
10745 /* ... fall through ... */
10748 if ((unsigned_comparison_p
|| equality_comparison_p
)
10749 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10750 <= HOST_BITS_PER_WIDE_INT
)
10751 && ((unsigned HOST_WIDE_INT
) const_op
10752 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10754 op0
= XEXP (op0
, 0);
10760 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10761 this for equality comparisons due to pathological cases involving
10763 if (equality_comparison_p
10764 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10765 op1
, XEXP (op0
, 1))))
10767 op0
= XEXP (op0
, 0);
10772 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10773 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10774 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10776 op0
= XEXP (XEXP (op0
, 0), 0);
10777 code
= (code
== LT
? EQ
: NE
);
10783 /* We used to optimize signed comparisons against zero, but that
10784 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10785 arrive here as equality comparisons, or (GEU, LTU) are
10786 optimized away. No need to special-case them. */
10788 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10789 (eq B (minus A C)), whichever simplifies. We can only do
10790 this for equality comparisons due to pathological cases involving
10792 if (equality_comparison_p
10793 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10794 XEXP (op0
, 1), op1
)))
10796 op0
= XEXP (op0
, 0);
10801 if (equality_comparison_p
10802 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10803 XEXP (op0
, 0), op1
)))
10805 op0
= XEXP (op0
, 1);
10810 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10811 of bits in X minus 1, is one iff X > 0. */
10812 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10813 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10814 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10816 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10818 op0
= XEXP (op0
, 1);
10819 code
= (code
== GE
? LE
: GT
);
10825 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10826 if C is zero or B is a constant. */
10827 if (equality_comparison_p
10828 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10829 XEXP (op0
, 1), op1
)))
10831 op0
= XEXP (op0
, 0);
10838 case UNEQ
: case LTGT
:
10839 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10840 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10841 case UNORDERED
: case ORDERED
:
10842 /* We can't do anything if OP0 is a condition code value, rather
10843 than an actual data value. */
10845 || CC0_P (XEXP (op0
, 0))
10846 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10849 /* Get the two operands being compared. */
10850 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10851 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10853 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10855 /* Check for the cases where we simply want the result of the
10856 earlier test or the opposite of that result. */
10857 if (code
== NE
|| code
== EQ
10858 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10859 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10860 && (STORE_FLAG_VALUE
10861 & (((HOST_WIDE_INT
) 1
10862 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10863 && (code
== LT
|| code
== GE
)))
10865 enum rtx_code new_code
;
10866 if (code
== LT
|| code
== NE
)
10867 new_code
= GET_CODE (op0
);
10869 new_code
= combine_reversed_comparison_code (op0
);
10871 if (new_code
!= UNKNOWN
)
10882 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10884 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10885 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10886 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10888 op0
= XEXP (op0
, 1);
10889 code
= (code
== GE
? GT
: LE
);
10895 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10896 will be converted to a ZERO_EXTRACT later. */
10897 if (const_op
== 0 && equality_comparison_p
10898 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10899 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10901 op0
= simplify_and_const_int
10902 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10904 XEXP (XEXP (op0
, 0), 1)),
10905 (HOST_WIDE_INT
) 1);
10909 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10910 zero and X is a comparison and C1 and C2 describe only bits set
10911 in STORE_FLAG_VALUE, we can compare with X. */
10912 if (const_op
== 0 && equality_comparison_p
10913 && mode_width
<= HOST_BITS_PER_WIDE_INT
10914 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10915 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10916 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10917 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10918 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10920 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10921 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10922 if ((~STORE_FLAG_VALUE
& mask
) == 0
10923 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10924 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10925 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10927 op0
= XEXP (XEXP (op0
, 0), 0);
10932 /* If we are doing an equality comparison of an AND of a bit equal
10933 to the sign bit, replace this with a LT or GE comparison of
10934 the underlying value. */
10935 if (equality_comparison_p
10937 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10938 && mode_width
<= HOST_BITS_PER_WIDE_INT
10939 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10940 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10942 op0
= XEXP (op0
, 0);
10943 code
= (code
== EQ
? GE
: LT
);
10947 /* If this AND operation is really a ZERO_EXTEND from a narrower
10948 mode, the constant fits within that mode, and this is either an
10949 equality or unsigned comparison, try to do this comparison in
10950 the narrower mode. */
10951 if ((equality_comparison_p
|| unsigned_comparison_p
)
10952 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10953 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10954 & GET_MODE_MASK (mode
))
10956 && const_op
>> i
== 0
10957 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10959 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10963 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10964 fits in both M1 and M2 and the SUBREG is either paradoxical
10965 or represents the low part, permute the SUBREG and the AND
10967 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10969 unsigned HOST_WIDE_INT c1
;
10970 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10971 /* Require an integral mode, to avoid creating something like
10973 if (SCALAR_INT_MODE_P (tmode
)
10974 /* It is unsafe to commute the AND into the SUBREG if the
10975 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10976 not defined. As originally written the upper bits
10977 have a defined value due to the AND operation.
10978 However, if we commute the AND inside the SUBREG then
10979 they no longer have defined values and the meaning of
10980 the code has been changed. */
10982 #ifdef WORD_REGISTER_OPERATIONS
10983 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10984 && mode_width
<= BITS_PER_WORD
)
10986 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10987 && subreg_lowpart_p (XEXP (op0
, 0))))
10988 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10989 && mode_width
<= HOST_BITS_PER_WIDE_INT
10990 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10991 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10992 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10994 && c1
!= GET_MODE_MASK (tmode
))
10996 op0
= gen_binary (AND
, tmode
,
10997 SUBREG_REG (XEXP (op0
, 0)),
10998 gen_int_mode (c1
, tmode
));
10999 op0
= gen_lowpart (mode
, op0
);
11004 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11005 if (const_op
== 0 && equality_comparison_p
11006 && XEXP (op0
, 1) == const1_rtx
11007 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11009 op0
= simplify_and_const_int
11010 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11011 code
= (code
== NE
? EQ
: NE
);
11015 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11016 (eq (and (lshiftrt X) 1) 0).
11017 Also handle the case where (not X) is expressed using xor. */
11018 if (const_op
== 0 && equality_comparison_p
11019 && XEXP (op0
, 1) == const1_rtx
11020 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11022 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11023 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11025 if (GET_CODE (shift_op
) == NOT
11026 || (GET_CODE (shift_op
) == XOR
11027 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
11028 && GET_CODE (shift_count
) == CONST_INT
11029 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11030 && (INTVAL (XEXP (shift_op
, 1))
11031 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11033 op0
= simplify_and_const_int
11035 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11036 (HOST_WIDE_INT
) 1);
11037 code
= (code
== NE
? EQ
: NE
);
11044 /* If we have (compare (ashift FOO N) (const_int C)) and
11045 the high order N bits of FOO (N+1 if an inequality comparison)
11046 are known to be zero, we can do this by comparing FOO with C
11047 shifted right N bits so long as the low-order N bits of C are
11049 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11050 && INTVAL (XEXP (op0
, 1)) >= 0
11051 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11052 < HOST_BITS_PER_WIDE_INT
)
11054 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11055 && mode_width
<= HOST_BITS_PER_WIDE_INT
11056 && (nonzero_bits (XEXP (op0
, 0), mode
)
11057 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11058 + ! equality_comparison_p
))) == 0)
11060 /* We must perform a logical shift, not an arithmetic one,
11061 as we want the top N bits of C to be zero. */
11062 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11064 temp
>>= INTVAL (XEXP (op0
, 1));
11065 op1
= gen_int_mode (temp
, mode
);
11066 op0
= XEXP (op0
, 0);
11070 /* If we are doing a sign bit comparison, it means we are testing
11071 a particular bit. Convert it to the appropriate AND. */
11072 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11073 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11075 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11078 - INTVAL (XEXP (op0
, 1)))));
11079 code
= (code
== LT
? NE
: EQ
);
11083 /* If this an equality comparison with zero and we are shifting
11084 the low bit to the sign bit, we can convert this to an AND of the
11086 if (const_op
== 0 && equality_comparison_p
11087 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11088 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11091 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11092 (HOST_WIDE_INT
) 1);
11098 /* If this is an equality comparison with zero, we can do this
11099 as a logical shift, which might be much simpler. */
11100 if (equality_comparison_p
&& const_op
== 0
11101 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11103 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11105 INTVAL (XEXP (op0
, 1)));
11109 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11110 do the comparison in a narrower mode. */
11111 if (! unsigned_comparison_p
11112 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11113 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11114 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11115 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11116 MODE_INT
, 1)) != BLKmode
11117 && (((unsigned HOST_WIDE_INT
) const_op
11118 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11119 <= GET_MODE_MASK (tmode
)))
11121 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11125 /* Likewise if OP0 is a PLUS of a sign extension with a
11126 constant, which is usually represented with the PLUS
11127 between the shifts. */
11128 if (! unsigned_comparison_p
11129 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11130 && GET_CODE (XEXP (op0
, 0)) == PLUS
11131 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11132 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11133 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11134 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11135 MODE_INT
, 1)) != BLKmode
11136 && (((unsigned HOST_WIDE_INT
) const_op
11137 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11138 <= GET_MODE_MASK (tmode
)))
11140 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11141 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11142 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11145 op0
= gen_binary (PLUS
, tmode
,
11146 gen_lowpart (tmode
, inner
),
11151 /* ... fall through ... */
11153 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11154 the low order N bits of FOO are known to be zero, we can do this
11155 by comparing FOO with C shifted left N bits so long as no
11156 overflow occurs. */
11157 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11158 && INTVAL (XEXP (op0
, 1)) >= 0
11159 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11160 && mode_width
<= HOST_BITS_PER_WIDE_INT
11161 && (nonzero_bits (XEXP (op0
, 0), mode
)
11162 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11163 && (((unsigned HOST_WIDE_INT
) const_op
11164 + (GET_CODE (op0
) != LSHIFTRT
11165 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11168 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11170 /* If the shift was logical, then we must make the condition
11172 if (GET_CODE (op0
) == LSHIFTRT
)
11173 code
= unsigned_condition (code
);
11175 const_op
<<= INTVAL (XEXP (op0
, 1));
11176 op1
= GEN_INT (const_op
);
11177 op0
= XEXP (op0
, 0);
11181 /* If we are using this shift to extract just the sign bit, we
11182 can replace this with an LT or GE comparison. */
11184 && (equality_comparison_p
|| sign_bit_comparison_p
)
11185 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11186 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11189 op0
= XEXP (op0
, 0);
11190 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11202 /* Now make any compound operations involved in this comparison. Then,
11203 check for an outmost SUBREG on OP0 that is not doing anything or is
11204 paradoxical. The latter transformation must only be performed when
11205 it is known that the "extra" bits will be the same in op0 and op1 or
11206 that they don't matter. There are three cases to consider:
11208 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11209 care bits and we can assume they have any convenient value. So
11210 making the transformation is safe.
11212 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11213 In this case the upper bits of op0 are undefined. We should not make
11214 the simplification in that case as we do not know the contents of
11217 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11218 NIL. In that case we know those bits are zeros or ones. We must
11219 also be sure that they are the same as the upper bits of op1.
11221 We can never remove a SUBREG for a non-equality comparison because
11222 the sign bit is in a different place in the underlying object. */
11224 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11225 op1
= make_compound_operation (op1
, SET
);
11227 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11228 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11229 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11230 && (code
== NE
|| code
== EQ
))
11232 if (GET_MODE_SIZE (GET_MODE (op0
))
11233 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11235 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11237 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11239 op0
= SUBREG_REG (op0
);
11240 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11243 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11244 <= HOST_BITS_PER_WIDE_INT
)
11245 && (nonzero_bits (SUBREG_REG (op0
),
11246 GET_MODE (SUBREG_REG (op0
)))
11247 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11249 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11251 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11252 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11253 op0
= SUBREG_REG (op0
), op1
= tem
;
11257 /* We now do the opposite procedure: Some machines don't have compare
11258 insns in all modes. If OP0's mode is an integer mode smaller than a
11259 word and we can't do a compare in that mode, see if there is a larger
11260 mode for which we can do the compare. There are a number of cases in
11261 which we can use the wider mode. */
11263 mode
= GET_MODE (op0
);
11264 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11265 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11266 && ! have_insn_for (COMPARE
, mode
))
11267 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11269 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11270 tmode
= GET_MODE_WIDER_MODE (tmode
))
11271 if (have_insn_for (COMPARE
, tmode
))
11275 /* If the only nonzero bits in OP0 and OP1 are those in the
11276 narrower mode and this is an equality or unsigned comparison,
11277 we can use the wider mode. Similarly for sign-extended
11278 values, in which case it is true for all comparisons. */
11279 zero_extended
= ((code
== EQ
|| code
== NE
11280 || code
== GEU
|| code
== GTU
11281 || code
== LEU
|| code
== LTU
)
11282 && (nonzero_bits (op0
, tmode
)
11283 & ~GET_MODE_MASK (mode
)) == 0
11284 && ((GET_CODE (op1
) == CONST_INT
11285 || (nonzero_bits (op1
, tmode
)
11286 & ~GET_MODE_MASK (mode
)) == 0)));
11289 || ((num_sign_bit_copies (op0
, tmode
)
11290 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11291 - GET_MODE_BITSIZE (mode
)))
11292 && (num_sign_bit_copies (op1
, tmode
)
11293 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11294 - GET_MODE_BITSIZE (mode
)))))
11296 /* If OP0 is an AND and we don't have an AND in MODE either,
11297 make a new AND in the proper mode. */
11298 if (GET_CODE (op0
) == AND
11299 && !have_insn_for (AND
, mode
))
11300 op0
= gen_binary (AND
, tmode
,
11301 gen_lowpart (tmode
,
11303 gen_lowpart (tmode
,
11306 op0
= gen_lowpart (tmode
, op0
);
11307 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11308 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11309 op1
= gen_lowpart (tmode
, op1
);
11313 /* If this is a test for negative, we can make an explicit
11314 test of the sign bit. */
11316 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11317 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11319 op0
= gen_binary (AND
, tmode
,
11320 gen_lowpart (tmode
, op0
),
11321 GEN_INT ((HOST_WIDE_INT
) 1
11322 << (GET_MODE_BITSIZE (mode
) - 1)));
11323 code
= (code
== LT
) ? NE
: EQ
;
11328 #ifdef CANONICALIZE_COMPARISON
11329 /* If this machine only supports a subset of valid comparisons, see if we
11330 can convert an unsupported one into a supported one. */
11331 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11340 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11341 searching backward. */
11342 static enum rtx_code
11343 combine_reversed_comparison_code (rtx exp
)
11345 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11348 if (code1
!= UNKNOWN
11349 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11351 /* Otherwise try and find where the condition codes were last set and
11353 x
= get_last_value (XEXP (exp
, 0));
11354 if (!x
|| GET_CODE (x
) != COMPARE
)
11356 return reversed_comparison_code_parts (GET_CODE (exp
),
11357 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11360 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11361 Return NULL_RTX in case we fail to do the reversal. */
11363 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11365 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11366 if (reversed_code
== UNKNOWN
)
11369 return gen_binary (reversed_code
, mode
, op0
, op1
);
11372 /* Utility function for following routine. Called when X is part of a value
11373 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11374 for each register mentioned. Similar to mention_regs in cse.c */
11377 update_table_tick (rtx x
)
11379 enum rtx_code code
= GET_CODE (x
);
11380 const char *fmt
= GET_RTX_FORMAT (code
);
11385 unsigned int regno
= REGNO (x
);
11386 unsigned int endregno
11387 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11388 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11391 for (r
= regno
; r
< endregno
; r
++)
11392 reg_last_set_table_tick
[r
] = label_tick
;
11397 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11398 /* Note that we can't have an "E" in values stored; see
11399 get_last_value_validate. */
11402 /* Check for identical subexpressions. If x contains
11403 identical subexpression we only have to traverse one of
11406 && (GET_RTX_CLASS (code
) == '2'
11407 || GET_RTX_CLASS (code
) == 'c'))
11409 /* Note that at this point x1 has already been
11411 rtx x0
= XEXP (x
, 0);
11412 rtx x1
= XEXP (x
, 1);
11414 /* If x0 and x1 are identical then there is no need to
11419 /* If x0 is identical to a subexpression of x1 then while
11420 processing x1, x0 has already been processed. Thus we
11421 are done with x. */
11422 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11423 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11424 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11427 /* If x1 is identical to a subexpression of x0 then we
11428 still have to process the rest of x0. */
11429 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11430 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11431 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11433 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11438 update_table_tick (XEXP (x
, i
));
11442 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11443 are saying that the register is clobbered and we no longer know its
11444 value. If INSN is zero, don't update reg_last_set; this is only permitted
11445 with VALUE also zero and is used to invalidate the register. */
11448 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11450 unsigned int regno
= REGNO (reg
);
11451 unsigned int endregno
11452 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11453 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
11456 /* If VALUE contains REG and we have a previous value for REG, substitute
11457 the previous value. */
11458 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11462 /* Set things up so get_last_value is allowed to see anything set up to
11464 subst_low_cuid
= INSN_CUID (insn
);
11465 tem
= get_last_value (reg
);
11467 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11468 it isn't going to be useful and will take a lot of time to process,
11469 so just use the CLOBBER. */
11473 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11474 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11475 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11476 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11477 tem
= XEXP (tem
, 0);
11479 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11483 /* For each register modified, show we don't know its value, that
11484 we don't know about its bitwise content, that its value has been
11485 updated, and that we don't know the location of the death of the
11487 for (i
= regno
; i
< endregno
; i
++)
11490 reg_last_set
[i
] = insn
;
11492 reg_last_set_value
[i
] = 0;
11493 reg_last_set_mode
[i
] = 0;
11494 reg_last_set_nonzero_bits
[i
] = 0;
11495 reg_last_set_sign_bit_copies
[i
] = 0;
11496 reg_last_death
[i
] = 0;
11499 /* Mark registers that are being referenced in this value. */
11501 update_table_tick (value
);
11503 /* Now update the status of each register being set.
11504 If someone is using this register in this block, set this register
11505 to invalid since we will get confused between the two lives in this
11506 basic block. This makes using this register always invalid. In cse, we
11507 scan the table to invalidate all entries using this register, but this
11508 is too much work for us. */
11510 for (i
= regno
; i
< endregno
; i
++)
11512 reg_last_set_label
[i
] = label_tick
;
11513 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11514 reg_last_set_invalid
[i
] = 1;
11516 reg_last_set_invalid
[i
] = 0;
11519 /* The value being assigned might refer to X (like in "x++;"). In that
11520 case, we must replace it with (clobber (const_int 0)) to prevent
11522 if (value
&& ! get_last_value_validate (&value
, insn
,
11523 reg_last_set_label
[regno
], 0))
11525 value
= copy_rtx (value
);
11526 if (! get_last_value_validate (&value
, insn
,
11527 reg_last_set_label
[regno
], 1))
11531 /* For the main register being modified, update the value, the mode, the
11532 nonzero bits, and the number of sign bit copies. */
11534 reg_last_set_value
[regno
] = value
;
11538 enum machine_mode mode
= GET_MODE (reg
);
11539 subst_low_cuid
= INSN_CUID (insn
);
11540 reg_last_set_mode
[regno
] = mode
;
11541 if (GET_MODE_CLASS (mode
) == MODE_INT
11542 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11543 mode
= nonzero_bits_mode
;
11544 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11545 reg_last_set_sign_bit_copies
[regno
]
11546 = num_sign_bit_copies (value
, GET_MODE (reg
));
11550 /* Called via note_stores from record_dead_and_set_regs to handle one
11551 SET or CLOBBER in an insn. DATA is the instruction in which the
11552 set is occurring. */
11555 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11557 rtx record_dead_insn
= (rtx
) data
;
11559 if (GET_CODE (dest
) == SUBREG
)
11560 dest
= SUBREG_REG (dest
);
11562 if (GET_CODE (dest
) == REG
)
11564 /* If we are setting the whole register, we know its value. Otherwise
11565 show that we don't know the value. We can handle SUBREG in
11567 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11568 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11569 else if (GET_CODE (setter
) == SET
11570 && GET_CODE (SET_DEST (setter
)) == SUBREG
11571 && SUBREG_REG (SET_DEST (setter
)) == dest
11572 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11573 && subreg_lowpart_p (SET_DEST (setter
)))
11574 record_value_for_reg (dest
, record_dead_insn
,
11575 gen_lowpart (GET_MODE (dest
),
11576 SET_SRC (setter
)));
11578 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11580 else if (GET_CODE (dest
) == MEM
11581 /* Ignore pushes, they clobber nothing. */
11582 && ! push_operand (dest
, GET_MODE (dest
)))
11583 mem_last_set
= INSN_CUID (record_dead_insn
);
11586 /* Update the records of when each REG was most recently set or killed
11587 for the things done by INSN. This is the last thing done in processing
11588 INSN in the combiner loop.
11590 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11591 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11592 and also the similar information mem_last_set (which insn most recently
11593 modified memory) and last_call_cuid (which insn was the most recent
11594 subroutine call). */
11597 record_dead_and_set_regs (rtx insn
)
11602 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11604 if (REG_NOTE_KIND (link
) == REG_DEAD
11605 && GET_CODE (XEXP (link
, 0)) == REG
)
11607 unsigned int regno
= REGNO (XEXP (link
, 0));
11608 unsigned int endregno
11609 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11610 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11613 for (i
= regno
; i
< endregno
; i
++)
11614 reg_last_death
[i
] = insn
;
11616 else if (REG_NOTE_KIND (link
) == REG_INC
)
11617 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11620 if (GET_CODE (insn
) == CALL_INSN
)
11622 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11623 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11625 reg_last_set_value
[i
] = 0;
11626 reg_last_set_mode
[i
] = 0;
11627 reg_last_set_nonzero_bits
[i
] = 0;
11628 reg_last_set_sign_bit_copies
[i
] = 0;
11629 reg_last_death
[i
] = 0;
11632 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11634 /* Don't bother recording what this insn does. It might set the
11635 return value register, but we can't combine into a call
11636 pattern anyway, so there's no point trying (and it may cause
11637 a crash, if e.g. we wind up asking for last_set_value of a
11638 SUBREG of the return value register). */
11642 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11645 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11646 register present in the SUBREG, so for each such SUBREG go back and
11647 adjust nonzero and sign bit information of the registers that are
11648 known to have some zero/sign bits set.
11650 This is needed because when combine blows the SUBREGs away, the
11651 information on zero/sign bits is lost and further combines can be
11652 missed because of that. */
11655 record_promoted_value (rtx insn
, rtx subreg
)
11658 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11659 enum machine_mode mode
= GET_MODE (subreg
);
11661 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11664 for (links
= LOG_LINKS (insn
); links
;)
11666 insn
= XEXP (links
, 0);
11667 set
= single_set (insn
);
11669 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11670 || REGNO (SET_DEST (set
)) != regno
11671 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11673 links
= XEXP (links
, 1);
11677 if (reg_last_set
[regno
] == insn
)
11679 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11680 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11683 if (GET_CODE (SET_SRC (set
)) == REG
)
11685 regno
= REGNO (SET_SRC (set
));
11686 links
= LOG_LINKS (insn
);
11693 /* Scan X for promoted SUBREGs. For each one found,
11694 note what it implies to the registers used in it. */
11697 check_promoted_subreg (rtx insn
, rtx x
)
11699 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11700 && GET_CODE (SUBREG_REG (x
)) == REG
)
11701 record_promoted_value (insn
, x
);
11704 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11707 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11711 check_promoted_subreg (insn
, XEXP (x
, i
));
11715 if (XVEC (x
, i
) != 0)
11716 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11717 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11723 /* Utility routine for the following function. Verify that all the registers
11724 mentioned in *LOC are valid when *LOC was part of a value set when
11725 label_tick == TICK. Return 0 if some are not.
11727 If REPLACE is nonzero, replace the invalid reference with
11728 (clobber (const_int 0)) and return 1. This replacement is useful because
11729 we often can get useful information about the form of a value (e.g., if
11730 it was produced by a shift that always produces -1 or 0) even though
11731 we don't know exactly what registers it was produced from. */
11734 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11737 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11738 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11741 if (GET_CODE (x
) == REG
)
11743 unsigned int regno
= REGNO (x
);
11744 unsigned int endregno
11745 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11746 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11749 for (j
= regno
; j
< endregno
; j
++)
11750 if (reg_last_set_invalid
[j
]
11751 /* If this is a pseudo-register that was only set once and not
11752 live at the beginning of the function, it is always valid. */
11753 || (! (regno
>= FIRST_PSEUDO_REGISTER
11754 && REG_N_SETS (regno
) == 1
11755 && (! REGNO_REG_SET_P
11756 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11757 && reg_last_set_label
[j
] > tick
))
11760 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11766 /* If this is a memory reference, make sure that there were
11767 no stores after it that might have clobbered the value. We don't
11768 have alias info, so we assume any store invalidates it. */
11769 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11770 && INSN_CUID (insn
) <= mem_last_set
)
11773 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11777 for (i
= 0; i
< len
; i
++)
11781 /* Check for identical subexpressions. If x contains
11782 identical subexpression we only have to traverse one of
11785 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11786 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11788 /* Note that at this point x0 has already been checked
11789 and found valid. */
11790 rtx x0
= XEXP (x
, 0);
11791 rtx x1
= XEXP (x
, 1);
11793 /* If x0 and x1 are identical then x is also valid. */
11797 /* If x1 is identical to a subexpression of x0 then
11798 while checking x0, x1 has already been checked. Thus
11799 it is valid and so as x. */
11800 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11801 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11802 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11805 /* If x0 is identical to a subexpression of x1 then x is
11806 valid iff the rest of x1 is valid. */
11807 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11808 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11809 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11811 get_last_value_validate (&XEXP (x1
,
11812 x0
== XEXP (x1
, 0) ? 1 : 0),
11813 insn
, tick
, replace
);
11816 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11820 /* Don't bother with these. They shouldn't occur anyway. */
11821 else if (fmt
[i
] == 'E')
11825 /* If we haven't found a reason for it to be invalid, it is valid. */
11829 /* Get the last value assigned to X, if known. Some registers
11830 in the value may be replaced with (clobber (const_int 0)) if their value
11831 is known longer known reliably. */
11834 get_last_value (rtx x
)
11836 unsigned int regno
;
11839 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11840 then convert it to the desired mode. If this is a paradoxical SUBREG,
11841 we cannot predict what values the "extra" bits might have. */
11842 if (GET_CODE (x
) == SUBREG
11843 && subreg_lowpart_p (x
)
11844 && (GET_MODE_SIZE (GET_MODE (x
))
11845 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11846 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11847 return gen_lowpart (GET_MODE (x
), value
);
11849 if (GET_CODE (x
) != REG
)
11853 value
= reg_last_set_value
[regno
];
11855 /* If we don't have a value, or if it isn't for this basic block and
11856 it's either a hard register, set more than once, or it's a live
11857 at the beginning of the function, return 0.
11859 Because if it's not live at the beginning of the function then the reg
11860 is always set before being used (is never used without being set).
11861 And, if it's set only once, and it's always set before use, then all
11862 uses must have the same last value, even if it's not from this basic
11866 || (reg_last_set_label
[regno
] != label_tick
11867 && (regno
< FIRST_PSEUDO_REGISTER
11868 || REG_N_SETS (regno
) != 1
11869 || (REGNO_REG_SET_P
11870 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11873 /* If the value was set in a later insn than the ones we are processing,
11874 we can't use it even if the register was only set once. */
11875 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11878 /* If the value has all its registers valid, return it. */
11879 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11880 reg_last_set_label
[regno
], 0))
11883 /* Otherwise, make a copy and replace any invalid register with
11884 (clobber (const_int 0)). If that fails for some reason, return 0. */
11886 value
= copy_rtx (value
);
11887 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11888 reg_last_set_label
[regno
], 1))
11894 /* Return nonzero if expression X refers to a REG or to memory
11895 that is set in an instruction more recent than FROM_CUID. */
11898 use_crosses_set_p (rtx x
, int from_cuid
)
11902 enum rtx_code code
= GET_CODE (x
);
11906 unsigned int regno
= REGNO (x
);
11907 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11908 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11910 #ifdef PUSH_ROUNDING
11911 /* Don't allow uses of the stack pointer to be moved,
11912 because we don't know whether the move crosses a push insn. */
11913 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11916 for (; regno
< endreg
; regno
++)
11917 if (reg_last_set
[regno
]
11918 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11923 if (code
== MEM
&& mem_last_set
> from_cuid
)
11926 fmt
= GET_RTX_FORMAT (code
);
11928 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11933 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11934 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11937 else if (fmt
[i
] == 'e'
11938 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11944 /* Define three variables used for communication between the following
11947 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11948 static int reg_dead_flag
;
11950 /* Function called via note_stores from reg_dead_at_p.
11952 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11953 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11956 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11958 unsigned int regno
, endregno
;
11960 if (GET_CODE (dest
) != REG
)
11963 regno
= REGNO (dest
);
11964 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11965 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11967 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11968 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11971 /* Return nonzero if REG is known to be dead at INSN.
11973 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11974 referencing REG, it is dead. If we hit a SET referencing REG, it is
11975 live. Otherwise, see if it is live or dead at the start of the basic
11976 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11977 must be assumed to be always live. */
11980 reg_dead_at_p (rtx reg
, rtx insn
)
11985 /* Set variables for reg_dead_at_p_1. */
11986 reg_dead_regno
= REGNO (reg
);
11987 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11988 ? hard_regno_nregs
[reg_dead_regno
]
11994 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11995 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11997 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11998 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12002 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12003 beginning of function. */
12004 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
12005 insn
= prev_nonnote_insn (insn
))
12007 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12009 return reg_dead_flag
== 1 ? 1 : 0;
12011 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12015 /* Get the basic block that we were in. */
12017 block
= ENTRY_BLOCK_PTR
->next_bb
;
12020 FOR_EACH_BB (block
)
12021 if (insn
== BB_HEAD (block
))
12024 if (block
== EXIT_BLOCK_PTR
)
12028 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12029 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12035 /* Note hard registers in X that are used. This code is similar to
12036 that in flow.c, but much simpler since we don't care about pseudos. */
12039 mark_used_regs_combine (rtx x
)
12041 RTX_CODE code
= GET_CODE (x
);
12042 unsigned int regno
;
12055 case ADDR_DIFF_VEC
:
12058 /* CC0 must die in the insn after it is set, so we don't need to take
12059 special note of it here. */
12065 /* If we are clobbering a MEM, mark any hard registers inside the
12066 address as used. */
12067 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12068 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12073 /* A hard reg in a wide mode may really be multiple registers.
12074 If so, mark all of them just like the first. */
12075 if (regno
< FIRST_PSEUDO_REGISTER
)
12077 unsigned int endregno
, r
;
12079 /* None of this applies to the stack, frame or arg pointers. */
12080 if (regno
== STACK_POINTER_REGNUM
12081 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12082 || regno
== HARD_FRAME_POINTER_REGNUM
12084 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12085 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12087 || regno
== FRAME_POINTER_REGNUM
)
12090 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12091 for (r
= regno
; r
< endregno
; r
++)
12092 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12098 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12100 rtx testreg
= SET_DEST (x
);
12102 while (GET_CODE (testreg
) == SUBREG
12103 || GET_CODE (testreg
) == ZERO_EXTRACT
12104 || GET_CODE (testreg
) == SIGN_EXTRACT
12105 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12106 testreg
= XEXP (testreg
, 0);
12108 if (GET_CODE (testreg
) == MEM
)
12109 mark_used_regs_combine (XEXP (testreg
, 0));
12111 mark_used_regs_combine (SET_SRC (x
));
12119 /* Recursively scan the operands of this expression. */
12122 const char *fmt
= GET_RTX_FORMAT (code
);
12124 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12127 mark_used_regs_combine (XEXP (x
, i
));
12128 else if (fmt
[i
] == 'E')
12132 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12133 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12139 /* Remove register number REGNO from the dead registers list of INSN.
12141 Return the note used to record the death, if there was one. */
12144 remove_death (unsigned int regno
, rtx insn
)
12146 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12150 REG_N_DEATHS (regno
)--;
12151 remove_note (insn
, note
);
12157 /* For each register (hardware or pseudo) used within expression X, if its
12158 death is in an instruction with cuid between FROM_CUID (inclusive) and
12159 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12160 list headed by PNOTES.
12162 That said, don't move registers killed by maybe_kill_insn.
12164 This is done when X is being merged by combination into TO_INSN. These
12165 notes will then be distributed as needed. */
12168 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12173 enum rtx_code code
= GET_CODE (x
);
12177 unsigned int regno
= REGNO (x
);
12178 rtx where_dead
= reg_last_death
[regno
];
12179 rtx before_dead
, after_dead
;
12181 /* Don't move the register if it gets killed in between from and to. */
12182 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12183 && ! reg_referenced_p (x
, maybe_kill_insn
))
12186 /* WHERE_DEAD could be a USE insn made by combine, so first we
12187 make sure that we have insns with valid INSN_CUID values. */
12188 before_dead
= where_dead
;
12189 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12190 before_dead
= PREV_INSN (before_dead
);
12192 after_dead
= where_dead
;
12193 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12194 after_dead
= NEXT_INSN (after_dead
);
12196 if (before_dead
&& after_dead
12197 && INSN_CUID (before_dead
) >= from_cuid
12198 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12199 || (where_dead
!= after_dead
12200 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12202 rtx note
= remove_death (regno
, where_dead
);
12204 /* It is possible for the call above to return 0. This can occur
12205 when reg_last_death points to I2 or I1 that we combined with.
12206 In that case make a new note.
12208 We must also check for the case where X is a hard register
12209 and NOTE is a death note for a range of hard registers
12210 including X. In that case, we must put REG_DEAD notes for
12211 the remaining registers in place of NOTE. */
12213 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12214 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12215 > GET_MODE_SIZE (GET_MODE (x
))))
12217 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12218 unsigned int deadend
12219 = (deadregno
+ hard_regno_nregs
[deadregno
]
12220 [GET_MODE (XEXP (note
, 0))]);
12221 unsigned int ourend
12222 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12225 for (i
= deadregno
; i
< deadend
; i
++)
12226 if (i
< regno
|| i
>= ourend
)
12227 REG_NOTES (where_dead
)
12228 = gen_rtx_EXPR_LIST (REG_DEAD
,
12230 REG_NOTES (where_dead
));
12233 /* If we didn't find any note, or if we found a REG_DEAD note that
12234 covers only part of the given reg, and we have a multi-reg hard
12235 register, then to be safe we must check for REG_DEAD notes
12236 for each register other than the first. They could have
12237 their own REG_DEAD notes lying around. */
12238 else if ((note
== 0
12240 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12241 < GET_MODE_SIZE (GET_MODE (x
)))))
12242 && regno
< FIRST_PSEUDO_REGISTER
12243 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12245 unsigned int ourend
12246 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12247 unsigned int i
, offset
;
12251 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12255 for (i
= regno
+ offset
; i
< ourend
; i
++)
12256 move_deaths (regno_reg_rtx
[i
],
12257 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12260 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12262 XEXP (note
, 1) = *pnotes
;
12266 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12268 REG_N_DEATHS (regno
)++;
12274 else if (GET_CODE (x
) == SET
)
12276 rtx dest
= SET_DEST (x
);
12278 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12280 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12281 that accesses one word of a multi-word item, some
12282 piece of everything register in the expression is used by
12283 this insn, so remove any old death. */
12284 /* ??? So why do we test for equality of the sizes? */
12286 if (GET_CODE (dest
) == ZERO_EXTRACT
12287 || GET_CODE (dest
) == STRICT_LOW_PART
12288 || (GET_CODE (dest
) == SUBREG
12289 && (((GET_MODE_SIZE (GET_MODE (dest
))
12290 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12291 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12292 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12294 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12298 /* If this is some other SUBREG, we know it replaces the entire
12299 value, so use that as the destination. */
12300 if (GET_CODE (dest
) == SUBREG
)
12301 dest
= SUBREG_REG (dest
);
12303 /* If this is a MEM, adjust deaths of anything used in the address.
12304 For a REG (the only other possibility), the entire value is
12305 being replaced so the old value is not used in this insn. */
12307 if (GET_CODE (dest
) == MEM
)
12308 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12313 else if (GET_CODE (x
) == CLOBBER
)
12316 len
= GET_RTX_LENGTH (code
);
12317 fmt
= GET_RTX_FORMAT (code
);
12319 for (i
= 0; i
< len
; i
++)
12324 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12325 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12328 else if (fmt
[i
] == 'e')
12329 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12333 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12334 pattern of an insn. X must be a REG. */
12337 reg_bitfield_target_p (rtx x
, rtx body
)
12341 if (GET_CODE (body
) == SET
)
12343 rtx dest
= SET_DEST (body
);
12345 unsigned int regno
, tregno
, endregno
, endtregno
;
12347 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12348 target
= XEXP (dest
, 0);
12349 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12350 target
= SUBREG_REG (XEXP (dest
, 0));
12354 if (GET_CODE (target
) == SUBREG
)
12355 target
= SUBREG_REG (target
);
12357 if (GET_CODE (target
) != REG
)
12360 tregno
= REGNO (target
), regno
= REGNO (x
);
12361 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12362 return target
== x
;
12364 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
12365 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12367 return endregno
> tregno
&& regno
< endtregno
;
12370 else if (GET_CODE (body
) == PARALLEL
)
12371 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12372 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12378 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12379 as appropriate. I3 and I2 are the insns resulting from the combination
12380 insns including FROM (I2 may be zero).
12382 Each note in the list is either ignored or placed on some insns, depending
12383 on the type of note. */
12386 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12388 rtx note
, next_note
;
12391 for (note
= notes
; note
; note
= next_note
)
12393 rtx place
= 0, place2
= 0;
12395 /* If this NOTE references a pseudo register, ensure it references
12396 the latest copy of that register. */
12397 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12398 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12399 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12401 next_note
= XEXP (note
, 1);
12402 switch (REG_NOTE_KIND (note
))
12406 /* Doesn't matter much where we put this, as long as it's somewhere.
12407 It is preferable to keep these notes on branches, which is most
12408 likely to be i3. */
12412 case REG_VALUE_PROFILE
:
12413 /* Just get rid of this note, as it is unused later anyway. */
12416 case REG_VTABLE_REF
:
12417 /* ??? Should remain with *a particular* memory load. Given the
12418 nature of vtable data, the last insn seems relatively safe. */
12422 case REG_NON_LOCAL_GOTO
:
12423 if (GET_CODE (i3
) == JUMP_INSN
)
12425 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12431 case REG_EH_REGION
:
12432 /* These notes must remain with the call or trapping instruction. */
12433 if (GET_CODE (i3
) == CALL_INSN
)
12435 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12437 else if (flag_non_call_exceptions
)
12439 if (may_trap_p (i3
))
12441 else if (i2
&& may_trap_p (i2
))
12443 /* ??? Otherwise assume we've combined things such that we
12444 can now prove that the instructions can't trap. Drop the
12445 note in this case. */
12451 case REG_ALWAYS_RETURN
:
12454 /* These notes must remain with the call. It should not be
12455 possible for both I2 and I3 to be a call. */
12456 if (GET_CODE (i3
) == CALL_INSN
)
12458 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12465 /* Any clobbers for i3 may still exist, and so we must process
12466 REG_UNUSED notes from that insn.
12468 Any clobbers from i2 or i1 can only exist if they were added by
12469 recog_for_combine. In that case, recog_for_combine created the
12470 necessary REG_UNUSED notes. Trying to keep any original
12471 REG_UNUSED notes from these insns can cause incorrect output
12472 if it is for the same register as the original i3 dest.
12473 In that case, we will notice that the register is set in i3,
12474 and then add a REG_UNUSED note for the destination of i3, which
12475 is wrong. However, it is possible to have REG_UNUSED notes from
12476 i2 or i1 for register which were both used and clobbered, so
12477 we keep notes from i2 or i1 if they will turn into REG_DEAD
12480 /* If this register is set or clobbered in I3, put the note there
12481 unless there is one already. */
12482 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12484 if (from_insn
!= i3
)
12487 if (! (GET_CODE (XEXP (note
, 0)) == REG
12488 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12489 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12492 /* Otherwise, if this register is used by I3, then this register
12493 now dies here, so we must put a REG_DEAD note here unless there
12495 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12496 && ! (GET_CODE (XEXP (note
, 0)) == REG
12497 ? find_regno_note (i3
, REG_DEAD
,
12498 REGNO (XEXP (note
, 0)))
12499 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12501 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12509 /* These notes say something about results of an insn. We can
12510 only support them if they used to be on I3 in which case they
12511 remain on I3. Otherwise they are ignored.
12513 If the note refers to an expression that is not a constant, we
12514 must also ignore the note since we cannot tell whether the
12515 equivalence is still true. It might be possible to do
12516 slightly better than this (we only have a problem if I2DEST
12517 or I1DEST is present in the expression), but it doesn't
12518 seem worth the trouble. */
12520 if (from_insn
== i3
12521 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12526 case REG_NO_CONFLICT
:
12527 /* These notes say something about how a register is used. They must
12528 be present on any use of the register in I2 or I3. */
12529 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12532 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12542 /* This can show up in several ways -- either directly in the
12543 pattern, or hidden off in the constant pool with (or without?)
12544 a REG_EQUAL note. */
12545 /* ??? Ignore the without-reg_equal-note problem for now. */
12546 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12547 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12548 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12549 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12553 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12554 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12555 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12556 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12564 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12565 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12566 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12568 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12570 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12571 LABEL_NUSES (JUMP_LABEL (place
))--;
12574 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12576 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12578 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12579 LABEL_NUSES (JUMP_LABEL (place2
))--;
12585 /* This note says something about the value of a register prior
12586 to the execution of an insn. It is too much trouble to see
12587 if the note is still correct in all situations. It is better
12588 to simply delete it. */
12592 /* If the insn previously containing this note still exists,
12593 put it back where it was. Otherwise move it to the previous
12594 insn. Adjust the corresponding REG_LIBCALL note. */
12595 if (GET_CODE (from_insn
) != NOTE
)
12599 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12600 place
= prev_real_insn (from_insn
);
12602 XEXP (tem
, 0) = place
;
12603 /* If we're deleting the last remaining instruction of a
12604 libcall sequence, don't add the notes. */
12605 else if (XEXP (note
, 0) == from_insn
)
12611 /* This is handled similarly to REG_RETVAL. */
12612 if (GET_CODE (from_insn
) != NOTE
)
12616 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12617 place
= next_real_insn (from_insn
);
12619 XEXP (tem
, 0) = place
;
12620 /* If we're deleting the last remaining instruction of a
12621 libcall sequence, don't add the notes. */
12622 else if (XEXP (note
, 0) == from_insn
)
12628 /* If the register is used as an input in I3, it dies there.
12629 Similarly for I2, if it is nonzero and adjacent to I3.
12631 If the register is not used as an input in either I3 or I2
12632 and it is not one of the registers we were supposed to eliminate,
12633 there are two possibilities. We might have a non-adjacent I2
12634 or we might have somehow eliminated an additional register
12635 from a computation. For example, we might have had A & B where
12636 we discover that B will always be zero. In this case we will
12637 eliminate the reference to A.
12639 In both cases, we must search to see if we can find a previous
12640 use of A and put the death note there. */
12643 && GET_CODE (from_insn
) == CALL_INSN
12644 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12646 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12648 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12649 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12654 basic_block bb
= this_basic_block
;
12656 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12658 if (! INSN_P (tem
))
12660 if (tem
== BB_HEAD (bb
))
12665 /* If the register is being set at TEM, see if that is all
12666 TEM is doing. If so, delete TEM. Otherwise, make this
12667 into a REG_UNUSED note instead. */
12668 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12670 rtx set
= single_set (tem
);
12671 rtx inner_dest
= 0;
12673 rtx cc0_setter
= NULL_RTX
;
12677 for (inner_dest
= SET_DEST (set
);
12678 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12679 || GET_CODE (inner_dest
) == SUBREG
12680 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12681 inner_dest
= XEXP (inner_dest
, 0))
12684 /* Verify that it was the set, and not a clobber that
12685 modified the register.
12687 CC0 targets must be careful to maintain setter/user
12688 pairs. If we cannot delete the setter due to side
12689 effects, mark the user with an UNUSED note instead
12692 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12693 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12695 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12696 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12697 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12701 /* Move the notes and links of TEM elsewhere.
12702 This might delete other dead insns recursively.
12703 First set the pattern to something that won't use
12705 rtx old_notes
= REG_NOTES (tem
);
12707 PATTERN (tem
) = pc_rtx
;
12708 REG_NOTES (tem
) = NULL
;
12710 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12711 distribute_links (LOG_LINKS (tem
));
12713 PUT_CODE (tem
, NOTE
);
12714 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12715 NOTE_SOURCE_FILE (tem
) = 0;
12718 /* Delete the setter too. */
12721 PATTERN (cc0_setter
) = pc_rtx
;
12722 old_notes
= REG_NOTES (cc0_setter
);
12723 REG_NOTES (cc0_setter
) = NULL
;
12725 distribute_notes (old_notes
, cc0_setter
,
12726 cc0_setter
, NULL_RTX
);
12727 distribute_links (LOG_LINKS (cc0_setter
));
12729 PUT_CODE (cc0_setter
, NOTE
);
12730 NOTE_LINE_NUMBER (cc0_setter
)
12731 = NOTE_INSN_DELETED
;
12732 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12736 /* If the register is both set and used here, put the
12737 REG_DEAD note here, but place a REG_UNUSED note
12738 here too unless there already is one. */
12739 else if (reg_referenced_p (XEXP (note
, 0),
12744 if (! find_regno_note (tem
, REG_UNUSED
,
12745 REGNO (XEXP (note
, 0))))
12747 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12752 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12754 /* If there isn't already a REG_UNUSED note, put one
12756 if (! find_regno_note (tem
, REG_UNUSED
,
12757 REGNO (XEXP (note
, 0))))
12762 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12763 || (GET_CODE (tem
) == CALL_INSN
12764 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12768 /* If we are doing a 3->2 combination, and we have a
12769 register which formerly died in i3 and was not used
12770 by i2, which now no longer dies in i3 and is used in
12771 i2 but does not die in i2, and place is between i2
12772 and i3, then we may need to move a link from place to
12774 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12775 && INSN_CUID (place
) > INSN_CUID (i2
)
12777 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12778 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12780 rtx links
= LOG_LINKS (place
);
12781 LOG_LINKS (place
) = 0;
12782 distribute_links (links
);
12787 if (tem
== BB_HEAD (bb
))
12791 /* We haven't found an insn for the death note and it
12792 is still a REG_DEAD note, but we have hit the beginning
12793 of the block. If the existing life info says the reg
12794 was dead, there's nothing left to do. Otherwise, we'll
12795 need to do a global life update after combine. */
12796 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12797 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12798 REGNO (XEXP (note
, 0))))
12799 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12802 /* If the register is set or already dead at PLACE, we needn't do
12803 anything with this note if it is still a REG_DEAD note.
12804 We can here if it is set at all, not if is it totally replace,
12805 which is what `dead_or_set_p' checks, so also check for it being
12808 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12810 unsigned int regno
= REGNO (XEXP (note
, 0));
12812 /* Similarly, if the instruction on which we want to place
12813 the note is a noop, we'll need do a global live update
12814 after we remove them in delete_noop_moves. */
12815 if (noop_move_p (place
))
12816 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12818 if (dead_or_set_p (place
, XEXP (note
, 0))
12819 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12821 /* Unless the register previously died in PLACE, clear
12822 reg_last_death. [I no longer understand why this is
12824 if (reg_last_death
[regno
] != place
)
12825 reg_last_death
[regno
] = 0;
12829 reg_last_death
[regno
] = place
;
12831 /* If this is a death note for a hard reg that is occupying
12832 multiple registers, ensure that we are still using all
12833 parts of the object. If we find a piece of the object
12834 that is unused, we must arrange for an appropriate REG_DEAD
12835 note to be added for it. However, we can't just emit a USE
12836 and tag the note to it, since the register might actually
12837 be dead; so we recourse, and the recursive call then finds
12838 the previous insn that used this register. */
12840 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12841 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12843 unsigned int endregno
12844 = regno
+ hard_regno_nregs
[regno
]
12845 [GET_MODE (XEXP (note
, 0))];
12849 for (i
= regno
; i
< endregno
; i
++)
12850 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12851 && ! find_regno_fusage (place
, USE
, i
))
12852 || dead_or_set_regno_p (place
, i
))
12857 /* Put only REG_DEAD notes for pieces that are
12858 not already dead or set. */
12860 for (i
= regno
; i
< endregno
;
12861 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12863 rtx piece
= regno_reg_rtx
[i
];
12864 basic_block bb
= this_basic_block
;
12866 if (! dead_or_set_p (place
, piece
)
12867 && ! reg_bitfield_target_p (piece
,
12871 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12873 distribute_notes (new_note
, place
, place
,
12876 else if (! refers_to_regno_p (i
, i
+ 1,
12877 PATTERN (place
), 0)
12878 && ! find_regno_fusage (place
, USE
, i
))
12879 for (tem
= PREV_INSN (place
); ;
12880 tem
= PREV_INSN (tem
))
12882 if (! INSN_P (tem
))
12884 if (tem
== BB_HEAD (bb
))
12886 SET_BIT (refresh_blocks
,
12887 this_basic_block
->index
);
12892 if (dead_or_set_p (tem
, piece
)
12893 || reg_bitfield_target_p (piece
,
12897 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12912 /* Any other notes should not be present at this point in the
12919 XEXP (note
, 1) = REG_NOTES (place
);
12920 REG_NOTES (place
) = note
;
12922 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12923 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12924 && GET_CODE (XEXP (note
, 0)) == REG
)
12925 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12929 if ((REG_NOTE_KIND (note
) == REG_DEAD
12930 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12931 && GET_CODE (XEXP (note
, 0)) == REG
)
12932 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12934 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12935 REG_NOTE_KIND (note
),
12937 REG_NOTES (place2
));
12942 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12943 I3, I2, and I1 to new locations. This is also called to add a link
12944 pointing at I3 when I3's destination is changed. */
12947 distribute_links (rtx links
)
12949 rtx link
, next_link
;
12951 for (link
= links
; link
; link
= next_link
)
12957 next_link
= XEXP (link
, 1);
12959 /* If the insn that this link points to is a NOTE or isn't a single
12960 set, ignore it. In the latter case, it isn't clear what we
12961 can do other than ignore the link, since we can't tell which
12962 register it was for. Such links wouldn't be used by combine
12965 It is not possible for the destination of the target of the link to
12966 have been changed by combine. The only potential of this is if we
12967 replace I3, I2, and I1 by I3 and I2. But in that case the
12968 destination of I2 also remains unchanged. */
12970 if (GET_CODE (XEXP (link
, 0)) == NOTE
12971 || (set
= single_set (XEXP (link
, 0))) == 0)
12974 reg
= SET_DEST (set
);
12975 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12976 || GET_CODE (reg
) == SIGN_EXTRACT
12977 || GET_CODE (reg
) == STRICT_LOW_PART
)
12978 reg
= XEXP (reg
, 0);
12980 /* A LOG_LINK is defined as being placed on the first insn that uses
12981 a register and points to the insn that sets the register. Start
12982 searching at the next insn after the target of the link and stop
12983 when we reach a set of the register or the end of the basic block.
12985 Note that this correctly handles the link that used to point from
12986 I3 to I2. Also note that not much searching is typically done here
12987 since most links don't point very far away. */
12989 for (insn
= NEXT_INSN (XEXP (link
, 0));
12990 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12991 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12992 insn
= NEXT_INSN (insn
))
12993 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12995 if (reg_referenced_p (reg
, PATTERN (insn
)))
12999 else if (GET_CODE (insn
) == CALL_INSN
13000 && find_reg_fusage (insn
, USE
, reg
))
13005 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13008 /* If we found a place to put the link, place it there unless there
13009 is already a link to the same insn as LINK at that point. */
13015 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13016 if (XEXP (link2
, 0) == XEXP (link
, 0))
13021 XEXP (link
, 1) = LOG_LINKS (place
);
13022 LOG_LINKS (place
) = link
;
13024 /* Set added_links_insn to the earliest insn we added a
13026 if (added_links_insn
== 0
13027 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13028 added_links_insn
= place
;
13034 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13037 insn_cuid (rtx insn
)
13039 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13040 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13041 insn
= NEXT_INSN (insn
);
13043 if (INSN_UID (insn
) > max_uid_cuid
)
13046 return INSN_CUID (insn
);
13050 dump_combine_stats (FILE *file
)
13054 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13055 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13059 dump_combine_total_stats (FILE *file
)
13063 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13064 total_attempts
, total_merges
, total_extras
, total_successes
);