1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #ifndef SHIFT_COUNT_TRUNCATED
95 #define SHIFT_COUNT_TRUNCATED 0
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno
;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx
*reg_last_death
;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx
*reg_last_set
;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set
;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid
;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn
;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid
;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs
;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn
;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block
;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST (rtx
*, rtx
);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
346 static int cant_combine_insn_p (rtx
);
347 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
348 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
349 static int contains_muldiv (rtx
);
350 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
351 static void undo_all (void);
352 static void undo_commit (void);
353 static rtx
*find_split_point (rtx
*, rtx
);
354 static rtx
subst (rtx
, rtx
, rtx
, int, int);
355 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
356 static rtx
simplify_if_then_else (rtx
);
357 static rtx
simplify_set (rtx
);
358 static rtx
simplify_logical (rtx
, int);
359 static rtx
expand_compound_operation (rtx
);
360 static rtx
expand_field_assignment (rtx
);
361 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
362 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
363 static rtx
extract_left_shift (rtx
, int);
364 static rtx
make_compound_operation (rtx
, enum rtx_code
);
365 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
366 unsigned HOST_WIDE_INT
*);
367 static rtx
force_to_mode (rtx
, enum machine_mode
,
368 unsigned HOST_WIDE_INT
, rtx
, int);
369 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
370 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
371 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
372 static rtx
make_field_assignment (rtx
);
373 static rtx
apply_distributive_law (rtx
);
374 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
375 unsigned HOST_WIDE_INT
);
376 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
377 rtx
, enum machine_mode
,
378 unsigned HOST_WIDE_INT
);
379 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
381 unsigned HOST_WIDE_INT
);
382 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
385 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
386 enum machine_mode
, unsigned int);
387 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
388 HOST_WIDE_INT
, enum machine_mode
, int *);
389 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
391 static int recog_for_combine (rtx
*, rtx
, rtx
*);
392 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
393 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
394 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
395 static void update_table_tick (rtx
);
396 static void record_value_for_reg (rtx
, rtx
, rtx
);
397 static void check_promoted_subreg (rtx
, rtx
);
398 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
399 static void record_dead_and_set_regs (rtx
);
400 static int get_last_value_validate (rtx
*, rtx
, int, int);
401 static rtx
get_last_value (rtx
);
402 static int use_crosses_set_p (rtx
, int);
403 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
404 static int reg_dead_at_p (rtx
, rtx
);
405 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
406 static int reg_bitfield_target_p (rtx
, rtx
);
407 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
408 static void distribute_links (rtx
);
409 static void mark_used_regs_combine (rtx
);
410 static int insn_cuid (rtx
);
411 static void record_promoted_value (rtx
, rtx
);
412 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
413 static enum rtx_code
combine_reversed_comparison_code (rtx
);
415 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
416 insn. The substitution can be undone by undo_all. If INTO is already
417 set to NEWVAL, do not record this change. Because computing NEWVAL might
418 also call SUBST, we have to compute it before we put anything into
422 do_SUBST (rtx
*into
, rtx newval
)
427 if (oldval
== newval
)
430 /* We'd like to catch as many invalid transformations here as
431 possible. Unfortunately, there are way too many mode changes
432 that are perfectly valid, so we'd waste too much effort for
433 little gain doing the checks here. Focus on catching invalid
434 transformations involving integer constants. */
435 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
436 && GET_CODE (newval
) == CONST_INT
)
438 /* Sanity check that we're replacing oldval with a CONST_INT
439 that is a valid sign-extension for the original mode. */
440 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
444 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
445 CONST_INT is not valid, because after the replacement, the
446 original mode would be gone. Unfortunately, we can't tell
447 when do_SUBST is called to replace the operand thereof, so we
448 perform this test on oldval instead, checking whether an
449 invalid replacement took place before we got here. */
450 if ((GET_CODE (oldval
) == SUBREG
451 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
452 || (GET_CODE (oldval
) == ZERO_EXTEND
453 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
458 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
460 buf
= xmalloc (sizeof (struct undo
));
464 buf
->old_contents
.r
= oldval
;
467 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
470 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
472 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
473 for the value of a HOST_WIDE_INT value (including CONST_INT) is
477 do_SUBST_INT (int *into
, int newval
)
482 if (oldval
== newval
)
486 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
488 buf
= xmalloc (sizeof (struct undo
));
492 buf
->old_contents
.i
= oldval
;
495 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
498 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
500 /* Main entry point for combiner. F is the first insn of the function.
501 NREGS is the first unused pseudo-reg number.
503 Return nonzero if the combiner has turned an indirect jump
504 instruction into a direct jump. */
506 combine_instructions (rtx f
, unsigned int nregs
)
513 rtx links
, nextlinks
;
515 int new_direct_jump_p
= 0;
517 combine_attempts
= 0;
520 combine_successes
= 0;
522 combine_max_regno
= nregs
;
524 /* It is not safe to use ordinary gen_lowpart in combine.
525 See comments in gen_lowpart_for_combine. */
526 gen_lowpart
= gen_lowpart_for_combine
;
528 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
529 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
531 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
532 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
533 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
534 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
535 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
536 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
537 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
538 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
539 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
548 if (INSN_UID (insn
) > i
)
551 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
554 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid
= 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 setup_incoming_promotions ();
576 refresh_blocks
= sbitmap_alloc (last_basic_block
);
577 sbitmap_zero (refresh_blocks
);
579 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
581 uid_cuid
[INSN_UID (insn
)] = ++i
;
587 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
589 record_dead_and_set_regs (insn
);
592 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
593 if (REG_NOTE_KIND (links
) == REG_INC
)
594 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
599 if (GET_CODE (insn
) == CODE_LABEL
)
603 nonzero_sign_valid
= 1;
605 /* Now scan all the insns in forward order. */
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block
)
615 for (insn
= BB_HEAD (this_basic_block
);
616 insn
!= NEXT_INSN (BB_END (this_basic_block
));
617 insn
= next
? next
: NEXT_INSN (insn
))
621 if (GET_CODE (insn
) == CODE_LABEL
)
624 else if (INSN_P (insn
))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn
, PATTERN (insn
));
630 /* Try this insn with each insn it links back to. */
632 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
633 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 NULL_RTX
, &new_direct_jump_p
)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
641 rtx link
= XEXP (links
, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link
) == NOTE
)
648 for (nextlinks
= LOG_LINKS (link
);
650 nextlinks
= XEXP (nextlinks
, 1))
651 if ((next
= try_combine (insn
, link
,
653 &new_direct_jump_p
)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn
) == JUMP_INSN
666 && (prev
= prev_nonnote_insn (insn
)) != 0
667 && GET_CODE (prev
) == INSN
668 && sets_cc0_p (PATTERN (prev
)))
670 if ((next
= try_combine (insn
, prev
,
671 NULL_RTX
, &new_direct_jump_p
)) != 0)
674 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
675 nextlinks
= XEXP (nextlinks
, 1))
676 if ((next
= try_combine (insn
, prev
,
678 &new_direct_jump_p
)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn
) == INSN
684 && (prev
= prev_nonnote_insn (insn
)) != 0
685 && GET_CODE (prev
) == INSN
686 && sets_cc0_p (PATTERN (prev
))
687 && GET_CODE (PATTERN (insn
)) == SET
688 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
690 if ((next
= try_combine (insn
, prev
,
691 NULL_RTX
, &new_direct_jump_p
)) != 0)
694 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
695 nextlinks
= XEXP (nextlinks
, 1))
696 if ((next
= try_combine (insn
, prev
,
698 &new_direct_jump_p
)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
706 if (GET_CODE (XEXP (links
, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
708 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
709 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
710 && GET_CODE (prev
) == INSN
711 && sets_cc0_p (PATTERN (prev
))
712 && (next
= try_combine (insn
, XEXP (links
, 0),
713 prev
, &new_direct_jump_p
)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
720 for (nextlinks
= XEXP (links
, 1); nextlinks
;
721 nextlinks
= XEXP (nextlinks
, 1))
722 if ((next
= try_combine (insn
, XEXP (links
, 0),
724 &new_direct_jump_p
)) != 0)
727 if (GET_CODE (insn
) != NOTE
)
728 record_dead_and_set_regs (insn
);
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
738 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
739 new_direct_jump_p
|= purge_all_dead_edges (0);
740 delete_noop_moves (f
);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
743 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE
);
747 sbitmap_free (refresh_blocks
);
748 free (reg_nonzero_bits
);
749 free (reg_sign_bit_copies
);
750 free (reg_last_death
);
752 free (reg_last_set_value
);
753 free (reg_last_set_table_tick
);
754 free (reg_last_set_label
);
755 free (reg_last_set_invalid
);
756 free (reg_last_set_mode
);
757 free (reg_last_set_nonzero_bits
);
758 free (reg_last_set_sign_bit_copies
);
762 struct undo
*undo
, *next
;
763 for (undo
= undobuf
.frees
; undo
; undo
= next
)
771 total_attempts
+= combine_attempts
;
772 total_merges
+= combine_merges
;
773 total_extras
+= combine_extras
;
774 total_successes
+= combine_successes
;
776 nonzero_sign_valid
= 0;
777 gen_lowpart
= gen_lowpart_general
;
779 /* Make recognizer allow volatile MEMs again. */
782 return new_direct_jump_p
;
785 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
788 init_reg_last_arrays (void)
790 unsigned int nregs
= combine_max_regno
;
792 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
793 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
794 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
795 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
796 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
797 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
798 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
799 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
800 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
803 /* Set up any promoted values for incoming argument registers. */
806 setup_incoming_promotions (void)
810 enum machine_mode mode
;
812 rtx first
= get_insns ();
814 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
816 #ifndef OUTGOING_REGNO
817 #define OUTGOING_REGNO(N) N
819 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
820 /* Check whether this register can hold an incoming pointer
821 argument. FUNCTION_ARG_REGNO_P tests outgoing register
822 numbers, so translate if necessary due to register windows. */
823 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
824 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
827 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
830 gen_rtx_CLOBBER (mode
, const0_rtx
)));
835 /* Called via note_stores. If X is a pseudo that is narrower than
836 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
838 If we are setting only a portion of X and we can't figure out what
839 portion, assume all bits will be used since we don't know what will
842 Similarly, set how many bits of X are known to be copies of the sign bit
843 at all locations in the function. This is the smallest number implied
847 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
848 void *data ATTRIBUTE_UNUSED
)
852 if (GET_CODE (x
) == REG
853 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
854 /* If this register is undefined at the start of the file, we can't
855 say what its contents were. */
856 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
857 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
859 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
861 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
862 reg_sign_bit_copies
[REGNO (x
)] = 1;
866 /* If this is a complex assignment, see if we can convert it into a
867 simple assignment. */
868 set
= expand_field_assignment (set
);
870 /* If this is a simple assignment, or we have a paradoxical SUBREG,
871 set what we know about X. */
873 if (SET_DEST (set
) == x
874 || (GET_CODE (SET_DEST (set
)) == SUBREG
875 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
876 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
877 && SUBREG_REG (SET_DEST (set
)) == x
))
879 rtx src
= SET_SRC (set
);
881 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
882 /* If X is narrower than a word and SRC is a non-negative
883 constant that would appear negative in the mode of X,
884 sign-extend it for use in reg_nonzero_bits because some
885 machines (maybe most) will actually do the sign-extension
886 and this is the conservative approach.
888 ??? For 2.5, try to tighten up the MD files in this regard
889 instead of this kludge. */
891 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
892 && GET_CODE (src
) == CONST_INT
894 && 0 != (INTVAL (src
)
896 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
897 src
= GEN_INT (INTVAL (src
)
898 | ((HOST_WIDE_INT
) (-1)
899 << GET_MODE_BITSIZE (GET_MODE (x
))));
902 /* Don't call nonzero_bits if it cannot change anything. */
903 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
904 reg_nonzero_bits
[REGNO (x
)]
905 |= nonzero_bits (src
, nonzero_bits_mode
);
906 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
907 if (reg_sign_bit_copies
[REGNO (x
)] == 0
908 || reg_sign_bit_copies
[REGNO (x
)] > num
)
909 reg_sign_bit_copies
[REGNO (x
)] = num
;
913 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
914 reg_sign_bit_copies
[REGNO (x
)] = 1;
919 /* See if INSN can be combined into I3. PRED and SUCC are optionally
920 insns that were previously combined into I3 or that will be combined
921 into the merger of INSN and I3.
923 Return 0 if the combination is not allowed for any reason.
925 If the combination is allowed, *PDEST will be set to the single
926 destination of INSN and *PSRC to the single source, and this function
930 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
931 rtx
*pdest
, rtx
*psrc
)
934 rtx set
= 0, src
, dest
;
939 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
940 && next_active_insn (succ
) == i3
)
941 : next_active_insn (insn
) == i3
);
943 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
944 or a PARALLEL consisting of such a SET and CLOBBERs.
946 If INSN has CLOBBER parallel parts, ignore them for our processing.
947 By definition, these happen during the execution of the insn. When it
948 is merged with another insn, all bets are off. If they are, in fact,
949 needed and aren't also supplied in I3, they may be added by
950 recog_for_combine. Otherwise, it won't match.
952 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
955 Get the source and destination of INSN. If more than one, can't
958 if (GET_CODE (PATTERN (insn
)) == SET
)
959 set
= PATTERN (insn
);
960 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
961 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
963 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
965 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
967 switch (GET_CODE (elt
))
969 /* This is important to combine floating point insns
972 /* Combining an isolated USE doesn't make sense.
973 We depend here on combinable_i3pat to reject them. */
974 /* The code below this loop only verifies that the inputs of
975 the SET in INSN do not change. We call reg_set_between_p
976 to verify that the REG in the USE does not change between
978 If the USE in INSN was for a pseudo register, the matching
979 insn pattern will likely match any register; combining this
980 with any other USE would only be safe if we knew that the
981 used registers have identical values, or if there was
982 something to tell them apart, e.g. different modes. For
983 now, we forgo such complicated tests and simply disallow
984 combining of USES of pseudo registers with any other USE. */
985 if (GET_CODE (XEXP (elt
, 0)) == REG
986 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
988 rtx i3pat
= PATTERN (i3
);
989 int i
= XVECLEN (i3pat
, 0) - 1;
990 unsigned int regno
= REGNO (XEXP (elt
, 0));
994 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
996 if (GET_CODE (i3elt
) == USE
997 && GET_CODE (XEXP (i3elt
, 0)) == REG
998 && (REGNO (XEXP (i3elt
, 0)) == regno
999 ? reg_set_between_p (XEXP (elt
, 0),
1000 PREV_INSN (insn
), i3
)
1001 : regno
>= FIRST_PSEUDO_REGISTER
))
1008 /* We can ignore CLOBBERs. */
1013 /* Ignore SETs whose result isn't used but not those that
1014 have side-effects. */
1015 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1016 && ! side_effects_p (elt
))
1019 /* If we have already found a SET, this is a second one and
1020 so we cannot combine with this insn. */
1028 /* Anything else means we can't combine. */
1034 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1035 so don't do anything with it. */
1036 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1045 set
= expand_field_assignment (set
);
1046 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1048 /* Don't eliminate a store in the stack pointer. */
1049 if (dest
== stack_pointer_rtx
1050 /* Don't combine with an insn that sets a register to itself if it has
1051 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1052 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1053 /* Can't merge an ASM_OPERANDS. */
1054 || GET_CODE (src
) == ASM_OPERANDS
1055 /* Can't merge a function call. */
1056 || GET_CODE (src
) == CALL
1057 /* Don't eliminate a function call argument. */
1058 || (GET_CODE (i3
) == CALL_INSN
1059 && (find_reg_fusage (i3
, USE
, dest
)
1060 || (GET_CODE (dest
) == REG
1061 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1062 && global_regs
[REGNO (dest
)])))
1063 /* Don't substitute into an incremented register. */
1064 || FIND_REG_INC_NOTE (i3
, dest
)
1065 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1067 /* Don't combine the end of a libcall into anything. */
1068 /* ??? This gives worse code, and appears to be unnecessary, since no
1069 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1070 use REG_RETVAL notes for noconflict blocks, but other code here
1071 makes sure that those insns don't disappear. */
1072 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1074 /* Make sure that DEST is not used after SUCC but before I3. */
1075 || (succ
&& ! all_adjacent
1076 && reg_used_between_p (dest
, succ
, i3
))
1077 /* Make sure that the value that is to be substituted for the register
1078 does not use any registers whose values alter in between. However,
1079 If the insns are adjacent, a use can't cross a set even though we
1080 think it might (this can happen for a sequence of insns each setting
1081 the same destination; reg_last_set of that register might point to
1082 a NOTE). If INSN has a REG_EQUIV note, the register is always
1083 equivalent to the memory so the substitution is valid even if there
1084 are intervening stores. Also, don't move a volatile asm or
1085 UNSPEC_VOLATILE across any other insns. */
1087 && (((GET_CODE (src
) != MEM
1088 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1089 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1090 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1091 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1092 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1093 better register allocation by not doing the combine. */
1094 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1095 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1096 /* Don't combine across a CALL_INSN, because that would possibly
1097 change whether the life span of some REGs crosses calls or not,
1098 and it is a pain to update that information.
1099 Exception: if source is a constant, moving it later can't hurt.
1100 Accept that special case, because it helps -fforce-addr a lot. */
1101 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1104 /* DEST must either be a REG or CC0. */
1105 if (GET_CODE (dest
) == REG
)
1107 /* If register alignment is being enforced for multi-word items in all
1108 cases except for parameters, it is possible to have a register copy
1109 insn referencing a hard register that is not allowed to contain the
1110 mode being copied and which would not be valid as an operand of most
1111 insns. Eliminate this problem by not combining with such an insn.
1113 Also, on some machines we don't want to extend the life of a hard
1116 if (GET_CODE (src
) == REG
1117 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1118 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1119 /* Don't extend the life of a hard register unless it is
1120 user variable (if we have few registers) or it can't
1121 fit into the desired register (meaning something special
1123 Also avoid substituting a return register into I3, because
1124 reload can't handle a conflict with constraints of other
1126 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1127 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1130 else if (GET_CODE (dest
) != CC0
)
1133 /* Don't substitute for a register intended as a clobberable operand.
1134 Similarly, don't substitute an expression containing a register that
1135 will be clobbered in I3. */
1136 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1137 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1138 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1139 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1141 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1144 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1145 or not), reject, unless nothing volatile comes between it and I3 */
1147 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1149 /* Make sure succ doesn't contain a volatile reference. */
1150 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1153 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1154 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1158 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1159 to be an explicit register variable, and was chosen for a reason. */
1161 if (GET_CODE (src
) == ASM_OPERANDS
1162 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1165 /* If there are any volatile insns between INSN and I3, reject, because
1166 they might affect machine state. */
1168 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1169 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1172 /* If INSN or I2 contains an autoincrement or autodecrement,
1173 make sure that register is not used between there and I3,
1174 and not already used in I3 either.
1175 Also insist that I3 not be a jump; if it were one
1176 and the incremented register were spilled, we would lose. */
1179 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1180 if (REG_NOTE_KIND (link
) == REG_INC
1181 && (GET_CODE (i3
) == JUMP_INSN
1182 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1183 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1188 /* Don't combine an insn that follows a CC0-setting insn.
1189 An insn that uses CC0 must not be separated from the one that sets it.
1190 We do, however, allow I2 to follow a CC0-setting insn if that insn
1191 is passed as I1; in that case it will be deleted also.
1192 We also allow combining in this case if all the insns are adjacent
1193 because that would leave the two CC0 insns adjacent as well.
1194 It would be more logical to test whether CC0 occurs inside I1 or I2,
1195 but that would be much slower, and this ought to be equivalent. */
1197 p
= prev_nonnote_insn (insn
);
1198 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1203 /* If we get here, we have passed all the tests and the combination is
1212 /* LOC is the location within I3 that contains its pattern or the component
1213 of a PARALLEL of the pattern. We validate that it is valid for combining.
1215 One problem is if I3 modifies its output, as opposed to replacing it
1216 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1217 so would produce an insn that is not equivalent to the original insns.
1221 (set (reg:DI 101) (reg:DI 100))
1222 (set (subreg:SI (reg:DI 101) 0) <foo>)
1224 This is NOT equivalent to:
1226 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1227 (set (reg:DI 101) (reg:DI 100))])
1229 Not only does this modify 100 (in which case it might still be valid
1230 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1232 We can also run into a problem if I2 sets a register that I1
1233 uses and I1 gets directly substituted into I3 (not via I2). In that
1234 case, we would be getting the wrong value of I2DEST into I3, so we
1235 must reject the combination. This case occurs when I2 and I1 both
1236 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1237 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1238 of a SET must prevent combination from occurring.
1240 Before doing the above check, we first try to expand a field assignment
1241 into a set of logical operations.
1243 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1244 we place a register that is both set and used within I3. If more than one
1245 such register is detected, we fail.
1247 Return 1 if the combination is valid, zero otherwise. */
1250 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1251 int i1_not_in_src
, rtx
*pi3dest_killed
)
1255 if (GET_CODE (x
) == SET
)
1258 rtx dest
= SET_DEST (set
);
1259 rtx src
= SET_SRC (set
);
1260 rtx inner_dest
= dest
;
1262 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1263 || GET_CODE (inner_dest
) == SUBREG
1264 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1265 inner_dest
= XEXP (inner_dest
, 0);
1267 /* Check for the case where I3 modifies its output, as discussed
1268 above. We don't want to prevent pseudos from being combined
1269 into the address of a MEM, so only prevent the combination if
1270 i1 or i2 set the same MEM. */
1271 if ((inner_dest
!= dest
&&
1272 (GET_CODE (inner_dest
) != MEM
1273 || rtx_equal_p (i2dest
, inner_dest
)
1274 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1275 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1276 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1278 /* This is the same test done in can_combine_p except we can't test
1279 all_adjacent; we don't have to, since this instruction will stay
1280 in place, thus we are not considering increasing the lifetime of
1283 Also, if this insn sets a function argument, combining it with
1284 something that might need a spill could clobber a previous
1285 function argument; the all_adjacent test in can_combine_p also
1286 checks this; here, we do a more specific test for this case. */
1288 || (GET_CODE (inner_dest
) == REG
1289 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1290 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1291 GET_MODE (inner_dest
))))
1292 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1295 /* If DEST is used in I3, it is being killed in this insn,
1296 so record that for later.
1297 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1298 STACK_POINTER_REGNUM, since these are always considered to be
1299 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1300 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1301 && reg_referenced_p (dest
, PATTERN (i3
))
1302 && REGNO (dest
) != FRAME_POINTER_REGNUM
1303 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1304 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1306 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1307 && (REGNO (dest
) != ARG_POINTER_REGNUM
1308 || ! fixed_regs
[REGNO (dest
)])
1310 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1312 if (*pi3dest_killed
)
1315 *pi3dest_killed
= dest
;
1319 else if (GET_CODE (x
) == PARALLEL
)
1323 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1324 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1325 i1_not_in_src
, pi3dest_killed
))
1332 /* Return 1 if X is an arithmetic expression that contains a multiplication
1333 and division. We don't count multiplications by powers of two here. */
1336 contains_muldiv (rtx x
)
1338 switch (GET_CODE (x
))
1340 case MOD
: case DIV
: case UMOD
: case UDIV
:
1344 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1345 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1347 switch (GET_RTX_CLASS (GET_CODE (x
)))
1349 case 'c': case '<': case '2':
1350 return contains_muldiv (XEXP (x
, 0))
1351 || contains_muldiv (XEXP (x
, 1));
1354 return contains_muldiv (XEXP (x
, 0));
1362 /* Determine whether INSN can be used in a combination. Return nonzero if
1363 not. This is used in try_combine to detect early some cases where we
1364 can't perform combinations. */
1367 cant_combine_insn_p (rtx insn
)
1372 /* If this isn't really an insn, we can't do anything.
1373 This can occur when flow deletes an insn that it has merged into an
1374 auto-increment address. */
1375 if (! INSN_P (insn
))
1378 /* Never combine loads and stores involving hard regs that are likely
1379 to be spilled. The register allocator can usually handle such
1380 reg-reg moves by tying. If we allow the combiner to make
1381 substitutions of likely-spilled regs, we may abort in reload.
1382 As an exception, we allow combinations involving fixed regs; these are
1383 not available to the register allocator so there's no risk involved. */
1385 set
= single_set (insn
);
1388 src
= SET_SRC (set
);
1389 dest
= SET_DEST (set
);
1390 if (GET_CODE (src
) == SUBREG
)
1391 src
= SUBREG_REG (src
);
1392 if (GET_CODE (dest
) == SUBREG
)
1393 dest
= SUBREG_REG (dest
);
1394 if (REG_P (src
) && REG_P (dest
)
1395 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1396 && ! fixed_regs
[REGNO (src
)]
1397 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1398 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1399 && ! fixed_regs
[REGNO (dest
)]
1400 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1406 /* Adjust INSN after we made a change to its destination.
1408 Changing the destination can invalidate notes that say something about
1409 the results of the insn and a LOG_LINK pointing to the insn. */
1412 adjust_for_new_dest (rtx insn
)
1416 /* For notes, be conservative and simply remove them. */
1417 loc
= ®_NOTES (insn
);
1420 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1421 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1422 *loc
= XEXP (*loc
, 1);
1424 loc
= &XEXP (*loc
, 1);
1427 /* The new insn will have a destination that was previously the destination
1428 of an insn just above it. Call distribute_links to make a LOG_LINK from
1429 the next use of that destination. */
1430 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1433 /* Try to combine the insns I1 and I2 into I3.
1434 Here I1 and I2 appear earlier than I3.
1435 I1 can be zero; then we combine just I2 into I3.
1437 If we are combining three insns and the resulting insn is not recognized,
1438 try splitting it into two insns. If that happens, I2 and I3 are retained
1439 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1442 Return 0 if the combination does not work. Then nothing is changed.
1443 If we did the combination, return the insn at which combine should
1446 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1447 new direct jump instruction. */
1450 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1452 /* New patterns for I3 and I2, respectively. */
1453 rtx newpat
, newi2pat
= 0;
1454 int substed_i2
= 0, substed_i1
= 0;
1455 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1456 int added_sets_1
, added_sets_2
;
1457 /* Total number of SETs to put into I3. */
1459 /* Nonzero is I2's body now appears in I3. */
1461 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1462 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1463 /* Contains I3 if the destination of I3 is used in its source, which means
1464 that the old life of I3 is being killed. If that usage is placed into
1465 I2 and not in I3, a REG_DEAD note must be made. */
1466 rtx i3dest_killed
= 0;
1467 /* SET_DEST and SET_SRC of I2 and I1. */
1468 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1469 /* PATTERN (I2), or a copy of it in certain cases. */
1471 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1472 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1473 int i1_feeds_i3
= 0;
1474 /* Notes that must be added to REG_NOTES in I3 and I2. */
1475 rtx new_i3_notes
, new_i2_notes
;
1476 /* Notes that we substituted I3 into I2 instead of the normal case. */
1477 int i3_subst_into_i2
= 0;
1478 /* Notes that I1, I2 or I3 is a MULT operation. */
1486 /* Exit early if one of the insns involved can't be used for
1488 if (cant_combine_insn_p (i3
)
1489 || cant_combine_insn_p (i2
)
1490 || (i1
&& cant_combine_insn_p (i1
))
1491 /* We also can't do anything if I3 has a
1492 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1495 /* ??? This gives worse code, and appears to be unnecessary, since no
1496 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1497 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1503 undobuf
.other_insn
= 0;
1505 /* Reset the hard register usage information. */
1506 CLEAR_HARD_REG_SET (newpat_used_regs
);
1508 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1509 code below, set I1 to be the earlier of the two insns. */
1510 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1511 temp
= i1
, i1
= i2
, i2
= temp
;
1513 added_links_insn
= 0;
1515 /* First check for one important special-case that the code below will
1516 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1517 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1518 we may be able to replace that destination with the destination of I3.
1519 This occurs in the common code where we compute both a quotient and
1520 remainder into a structure, in which case we want to do the computation
1521 directly into the structure to avoid register-register copies.
1523 Note that this case handles both multiple sets in I2 and also
1524 cases where I2 has a number of CLOBBER or PARALLELs.
1526 We make very conservative checks below and only try to handle the
1527 most common cases of this. For example, we only handle the case
1528 where I2 and I3 are adjacent to avoid making difficult register
1531 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1532 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1533 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1534 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1535 && GET_CODE (PATTERN (i2
)) == PARALLEL
1536 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1537 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1538 below would need to check what is inside (and reg_overlap_mentioned_p
1539 doesn't support those codes anyway). Don't allow those destinations;
1540 the resulting insn isn't likely to be recognized anyway. */
1541 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1542 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1543 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1544 SET_DEST (PATTERN (i3
)))
1545 && next_real_insn (i2
) == i3
)
1547 rtx p2
= PATTERN (i2
);
1549 /* Make sure that the destination of I3,
1550 which we are going to substitute into one output of I2,
1551 is not used within another output of I2. We must avoid making this:
1552 (parallel [(set (mem (reg 69)) ...)
1553 (set (reg 69) ...)])
1554 which is not well-defined as to order of actions.
1555 (Besides, reload can't handle output reloads for this.)
1557 The problem can also happen if the dest of I3 is a memory ref,
1558 if another dest in I2 is an indirect memory ref. */
1559 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1560 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1561 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1562 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1563 SET_DEST (XVECEXP (p2
, 0, i
))))
1566 if (i
== XVECLEN (p2
, 0))
1567 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1568 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1569 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1570 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1575 subst_low_cuid
= INSN_CUID (i2
);
1577 added_sets_2
= added_sets_1
= 0;
1578 i2dest
= SET_SRC (PATTERN (i3
));
1580 /* Replace the dest in I2 with our dest and make the resulting
1581 insn the new pattern for I3. Then skip to where we
1582 validate the pattern. Everything was set up above. */
1583 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1584 SET_DEST (PATTERN (i3
)));
1587 i3_subst_into_i2
= 1;
1588 goto validate_replacement
;
1592 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1593 one of those words to another constant, merge them by making a new
1596 && (temp
= single_set (i2
)) != 0
1597 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1598 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1599 && GET_CODE (SET_DEST (temp
)) == REG
1600 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1601 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1602 && GET_CODE (PATTERN (i3
)) == SET
1603 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1604 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1605 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1606 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1607 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1609 HOST_WIDE_INT lo
, hi
;
1611 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1612 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1615 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1616 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1619 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1621 /* We don't handle the case of the target word being wider
1622 than a host wide int. */
1623 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1626 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1627 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1628 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1630 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1631 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1632 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1634 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1635 >> (HOST_BITS_PER_WIDE_INT
- 1));
1637 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1638 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1639 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1640 (INTVAL (SET_SRC (PATTERN (i3
)))));
1642 hi
= lo
< 0 ? -1 : 0;
1645 /* We don't handle the case of the higher word not fitting
1646 entirely in either hi or lo. */
1651 subst_low_cuid
= INSN_CUID (i2
);
1652 added_sets_2
= added_sets_1
= 0;
1653 i2dest
= SET_DEST (temp
);
1655 SUBST (SET_SRC (temp
),
1656 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1658 newpat
= PATTERN (i2
);
1659 goto validate_replacement
;
1663 /* If we have no I1 and I2 looks like:
1664 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1666 make up a dummy I1 that is
1669 (set (reg:CC X) (compare:CC Y (const_int 0)))
1671 (We can ignore any trailing CLOBBERs.)
1673 This undoes a previous combination and allows us to match a branch-and-
1676 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1677 && XVECLEN (PATTERN (i2
), 0) >= 2
1678 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1679 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1681 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1682 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1683 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1684 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1685 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1686 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1688 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1689 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1694 /* We make I1 with the same INSN_UID as I2. This gives it
1695 the same INSN_CUID for value tracking. Our fake I1 will
1696 never appear in the insn stream so giving it the same INSN_UID
1697 as I2 will not cause a problem. */
1699 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1700 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1701 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1704 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1705 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1706 SET_DEST (PATTERN (i1
)));
1711 /* Verify that I2 and I1 are valid for combining. */
1712 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1713 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1719 /* Record whether I2DEST is used in I2SRC and similarly for the other
1720 cases. Knowing this will help in register status updating below. */
1721 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1722 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1723 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1725 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1727 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1729 /* Ensure that I3's pattern can be the destination of combines. */
1730 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1731 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1738 /* See if any of the insns is a MULT operation. Unless one is, we will
1739 reject a combination that is, since it must be slower. Be conservative
1741 if (GET_CODE (i2src
) == MULT
1742 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1743 || (GET_CODE (PATTERN (i3
)) == SET
1744 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1747 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1748 We used to do this EXCEPT in one case: I3 has a post-inc in an
1749 output operand. However, that exception can give rise to insns like
1751 which is a famous insn on the PDP-11 where the value of r3 used as the
1752 source was model-dependent. Avoid this sort of thing. */
1755 if (!(GET_CODE (PATTERN (i3
)) == SET
1756 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1757 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1758 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1759 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1760 /* It's not the exception. */
1763 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1764 if (REG_NOTE_KIND (link
) == REG_INC
1765 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1767 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1774 /* See if the SETs in I1 or I2 need to be kept around in the merged
1775 instruction: whenever the value set there is still needed past I3.
1776 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1778 For the SET in I1, we have two cases: If I1 and I2 independently
1779 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1780 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1781 in I1 needs to be kept around unless I1DEST dies or is set in either
1782 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1783 I1DEST. If so, we know I1 feeds into I2. */
1785 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1788 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1789 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1791 /* If the set in I2 needs to be kept around, we must make a copy of
1792 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1793 PATTERN (I2), we are only substituting for the original I1DEST, not into
1794 an already-substituted copy. This also prevents making self-referential
1795 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1798 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1799 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1803 i2pat
= copy_rtx (i2pat
);
1807 /* Substitute in the latest insn for the regs set by the earlier ones. */
1809 maxreg
= max_reg_num ();
1813 /* It is possible that the source of I2 or I1 may be performing an
1814 unneeded operation, such as a ZERO_EXTEND of something that is known
1815 to have the high part zero. Handle that case by letting subst look at
1816 the innermost one of them.
1818 Another way to do this would be to have a function that tries to
1819 simplify a single insn instead of merging two or more insns. We don't
1820 do this because of the potential of infinite loops and because
1821 of the potential extra memory required. However, doing it the way
1822 we are is a bit of a kludge and doesn't catch all cases.
1824 But only do this if -fexpensive-optimizations since it slows things down
1825 and doesn't usually win. */
1827 if (flag_expensive_optimizations
)
1829 /* Pass pc_rtx so no substitutions are done, just simplifications.
1830 The cases that we are interested in here do not involve the few
1831 cases were is_replaced is checked. */
1834 subst_low_cuid
= INSN_CUID (i1
);
1835 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1839 subst_low_cuid
= INSN_CUID (i2
);
1840 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1845 /* Many machines that don't use CC0 have insns that can both perform an
1846 arithmetic operation and set the condition code. These operations will
1847 be represented as a PARALLEL with the first element of the vector
1848 being a COMPARE of an arithmetic operation with the constant zero.
1849 The second element of the vector will set some pseudo to the result
1850 of the same arithmetic operation. If we simplify the COMPARE, we won't
1851 match such a pattern and so will generate an extra insn. Here we test
1852 for this case, where both the comparison and the operation result are
1853 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1854 I2SRC. Later we will make the PARALLEL that contains I2. */
1856 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1857 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1858 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1859 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1861 #ifdef SELECT_CC_MODE
1863 enum machine_mode compare_mode
;
1866 newpat
= PATTERN (i3
);
1867 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1871 #ifdef SELECT_CC_MODE
1872 /* See if a COMPARE with the operand we substituted in should be done
1873 with the mode that is currently being used. If not, do the same
1874 processing we do in `subst' for a SET; namely, if the destination
1875 is used only once, try to replace it with a register of the proper
1876 mode and also replace the COMPARE. */
1877 if (undobuf
.other_insn
== 0
1878 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1879 &undobuf
.other_insn
))
1880 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1882 != GET_MODE (SET_DEST (newpat
))))
1884 unsigned int regno
= REGNO (SET_DEST (newpat
));
1885 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1887 if (regno
< FIRST_PSEUDO_REGISTER
1888 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1889 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1891 if (regno
>= FIRST_PSEUDO_REGISTER
)
1892 SUBST (regno_reg_rtx
[regno
], new_dest
);
1894 SUBST (SET_DEST (newpat
), new_dest
);
1895 SUBST (XEXP (*cc_use
, 0), new_dest
);
1896 SUBST (SET_SRC (newpat
),
1897 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1900 undobuf
.other_insn
= 0;
1907 n_occurrences
= 0; /* `subst' counts here */
1909 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1910 need to make a unique copy of I2SRC each time we substitute it
1911 to avoid self-referential rtl. */
1913 subst_low_cuid
= INSN_CUID (i2
);
1914 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1915 ! i1_feeds_i3
&& i1dest_in_i1src
);
1918 /* Record whether i2's body now appears within i3's body. */
1919 i2_is_used
= n_occurrences
;
1922 /* If we already got a failure, don't try to do more. Otherwise,
1923 try to substitute in I1 if we have it. */
1925 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1927 /* Before we can do this substitution, we must redo the test done
1928 above (see detailed comments there) that ensures that I1DEST
1929 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1931 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1939 subst_low_cuid
= INSN_CUID (i1
);
1940 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1944 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1945 to count all the ways that I2SRC and I1SRC can be used. */
1946 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1947 && i2_is_used
+ added_sets_2
> 1)
1948 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1949 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1951 /* Fail if we tried to make a new register (we used to abort, but there's
1952 really no reason to). */
1953 || max_reg_num () != maxreg
1954 /* Fail if we couldn't do something and have a CLOBBER. */
1955 || GET_CODE (newpat
) == CLOBBER
1956 /* Fail if this new pattern is a MULT and we didn't have one before
1957 at the outer level. */
1958 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1965 /* If the actions of the earlier insns must be kept
1966 in addition to substituting them into the latest one,
1967 we must make a new PARALLEL for the latest insn
1968 to hold additional the SETs. */
1970 if (added_sets_1
|| added_sets_2
)
1974 if (GET_CODE (newpat
) == PARALLEL
)
1976 rtvec old
= XVEC (newpat
, 0);
1977 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1978 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1979 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1980 sizeof (old
->elem
[0]) * old
->num_elem
);
1985 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1986 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1987 XVECEXP (newpat
, 0, 0) = old
;
1991 XVECEXP (newpat
, 0, --total_sets
)
1992 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1993 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1997 /* If there is no I1, use I2's body as is. We used to also not do
1998 the subst call below if I2 was substituted into I3,
1999 but that could lose a simplification. */
2001 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2003 /* See comment where i2pat is assigned. */
2004 XVECEXP (newpat
, 0, --total_sets
)
2005 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2009 /* We come here when we are replacing a destination in I2 with the
2010 destination of I3. */
2011 validate_replacement
:
2013 /* Note which hard regs this insn has as inputs. */
2014 mark_used_regs_combine (newpat
);
2016 /* Is the result of combination a valid instruction? */
2017 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2019 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2020 the second SET's destination is a register that is unused. In that case,
2021 we just need the first SET. This can occur when simplifying a divmod
2022 insn. We *must* test for this case here because the code below that
2023 splits two independent SETs doesn't handle this case correctly when it
2024 updates the register status. Also check the case where the first
2025 SET's destination is unused. That would not cause incorrect code, but
2026 does cause an unneeded insn to remain. */
2028 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2029 && XVECLEN (newpat
, 0) == 2
2030 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2031 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2032 && asm_noperands (newpat
) < 0)
2034 rtx set0
= XVECEXP (newpat
, 0, 0);
2035 rtx set1
= XVECEXP (newpat
, 0, 1);
2037 if (((GET_CODE (SET_DEST (set1
)) == REG
2038 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2039 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2040 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2041 && ! side_effects_p (SET_SRC (set1
)))
2044 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2047 else if (((GET_CODE (SET_DEST (set0
)) == REG
2048 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2049 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2050 && find_reg_note (i3
, REG_UNUSED
,
2051 SUBREG_REG (SET_DEST (set0
)))))
2052 && ! side_effects_p (SET_SRC (set0
)))
2055 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2057 if (insn_code_number
>= 0)
2059 /* If we will be able to accept this, we have made a
2060 change to the destination of I3. This requires us to
2061 do a few adjustments. */
2063 PATTERN (i3
) = newpat
;
2064 adjust_for_new_dest (i3
);
2069 /* If we were combining three insns and the result is a simple SET
2070 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2071 insns. There are two ways to do this. It can be split using a
2072 machine-specific method (like when you have an addition of a large
2073 constant) or by combine in the function find_split_point. */
2075 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2076 && asm_noperands (newpat
) < 0)
2078 rtx m_split
, *split
;
2079 rtx ni2dest
= i2dest
;
2081 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2082 use I2DEST as a scratch register will help. In the latter case,
2083 convert I2DEST to the mode of the source of NEWPAT if we can. */
2085 m_split
= split_insns (newpat
, i3
);
2087 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2088 inputs of NEWPAT. */
2090 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2091 possible to try that as a scratch reg. This would require adding
2092 more code to make it work though. */
2094 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2096 /* If I2DEST is a hard register or the only use of a pseudo,
2097 we can change its mode. */
2098 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2099 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2100 && GET_CODE (i2dest
) == REG
2101 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2102 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2103 && ! REG_USERVAR_P (i2dest
))))
2104 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2107 m_split
= split_insns (gen_rtx_PARALLEL
2109 gen_rtvec (2, newpat
,
2110 gen_rtx_CLOBBER (VOIDmode
,
2113 /* If the split with the mode-changed register didn't work, try
2114 the original register. */
2115 if (! m_split
&& ni2dest
!= i2dest
)
2118 m_split
= split_insns (gen_rtx_PARALLEL
2120 gen_rtvec (2, newpat
,
2121 gen_rtx_CLOBBER (VOIDmode
,
2127 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2129 m_split
= PATTERN (m_split
);
2130 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2131 if (insn_code_number
>= 0)
2134 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2135 && (next_real_insn (i2
) == i3
2136 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2139 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2140 newi2pat
= PATTERN (m_split
);
2142 i3set
= single_set (NEXT_INSN (m_split
));
2143 i2set
= single_set (m_split
);
2145 /* In case we changed the mode of I2DEST, replace it in the
2146 pseudo-register table here. We can't do it above in case this
2147 code doesn't get executed and we do a split the other way. */
2149 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2150 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2152 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2154 /* If I2 or I3 has multiple SETs, we won't know how to track
2155 register status, so don't use these insns. If I2's destination
2156 is used between I2 and I3, we also can't use these insns. */
2158 if (i2_code_number
>= 0 && i2set
&& i3set
2159 && (next_real_insn (i2
) == i3
2160 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2161 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2163 if (insn_code_number
>= 0)
2166 /* It is possible that both insns now set the destination of I3.
2167 If so, we must show an extra use of it. */
2169 if (insn_code_number
>= 0)
2171 rtx new_i3_dest
= SET_DEST (i3set
);
2172 rtx new_i2_dest
= SET_DEST (i2set
);
2174 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2175 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2176 || GET_CODE (new_i3_dest
) == SUBREG
)
2177 new_i3_dest
= XEXP (new_i3_dest
, 0);
2179 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2180 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2181 || GET_CODE (new_i2_dest
) == SUBREG
)
2182 new_i2_dest
= XEXP (new_i2_dest
, 0);
2184 if (GET_CODE (new_i3_dest
) == REG
2185 && GET_CODE (new_i2_dest
) == REG
2186 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2187 REG_N_SETS (REGNO (new_i2_dest
))++;
2191 /* If we can split it and use I2DEST, go ahead and see if that
2192 helps things be recognized. Verify that none of the registers
2193 are set between I2 and I3. */
2194 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2196 && GET_CODE (i2dest
) == REG
2198 /* We need I2DEST in the proper mode. If it is a hard register
2199 or the only use of a pseudo, we can change its mode. */
2200 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2201 || GET_MODE (*split
) == VOIDmode
2202 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2203 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2204 && ! REG_USERVAR_P (i2dest
)))
2205 && (next_real_insn (i2
) == i3
2206 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2207 /* We can't overwrite I2DEST if its value is still used by
2209 && ! reg_referenced_p (i2dest
, newpat
))
2211 rtx newdest
= i2dest
;
2212 enum rtx_code split_code
= GET_CODE (*split
);
2213 enum machine_mode split_mode
= GET_MODE (*split
);
2215 /* Get NEWDEST as a register in the proper mode. We have already
2216 validated that we can do this. */
2217 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2219 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2221 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2222 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2225 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2226 an ASHIFT. This can occur if it was inside a PLUS and hence
2227 appeared to be a memory address. This is a kludge. */
2228 if (split_code
== MULT
2229 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2230 && INTVAL (XEXP (*split
, 1)) > 0
2231 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2233 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2234 XEXP (*split
, 0), GEN_INT (i
)));
2235 /* Update split_code because we may not have a multiply
2237 split_code
= GET_CODE (*split
);
2240 #ifdef INSN_SCHEDULING
2241 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2242 be written as a ZERO_EXTEND. */
2243 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2245 #ifdef LOAD_EXTEND_OP
2246 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2247 what it really is. */
2248 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2250 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2251 SUBREG_REG (*split
)));
2254 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2255 SUBREG_REG (*split
)));
2259 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2260 SUBST (*split
, newdest
);
2261 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2263 /* If the split point was a MULT and we didn't have one before,
2264 don't use one now. */
2265 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2266 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2270 /* Check for a case where we loaded from memory in a narrow mode and
2271 then sign extended it, but we need both registers. In that case,
2272 we have a PARALLEL with both loads from the same memory location.
2273 We can split this into a load from memory followed by a register-register
2274 copy. This saves at least one insn, more if register allocation can
2277 We cannot do this if the destination of the first assignment is a
2278 condition code register or cc0. We eliminate this case by making sure
2279 the SET_DEST and SET_SRC have the same mode.
2281 We cannot do this if the destination of the second assignment is
2282 a register that we have already assumed is zero-extended. Similarly
2283 for a SUBREG of such a register. */
2285 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2286 && GET_CODE (newpat
) == PARALLEL
2287 && XVECLEN (newpat
, 0) == 2
2288 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2289 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2290 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2291 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2292 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2293 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2294 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2295 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2297 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2298 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2299 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2300 (GET_CODE (temp
) == REG
2301 && reg_nonzero_bits
[REGNO (temp
)] != 0
2302 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2303 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2304 && (reg_nonzero_bits
[REGNO (temp
)]
2305 != GET_MODE_MASK (word_mode
))))
2306 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2307 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2308 (GET_CODE (temp
) == REG
2309 && reg_nonzero_bits
[REGNO (temp
)] != 0
2310 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2311 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2312 && (reg_nonzero_bits
[REGNO (temp
)]
2313 != GET_MODE_MASK (word_mode
)))))
2314 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2315 SET_SRC (XVECEXP (newpat
, 0, 1)))
2316 && ! find_reg_note (i3
, REG_UNUSED
,
2317 SET_DEST (XVECEXP (newpat
, 0, 0))))
2321 newi2pat
= XVECEXP (newpat
, 0, 0);
2322 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2323 newpat
= XVECEXP (newpat
, 0, 1);
2324 SUBST (SET_SRC (newpat
),
2325 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2326 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2328 if (i2_code_number
>= 0)
2329 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2331 if (insn_code_number
>= 0)
2336 /* If we will be able to accept this, we have made a change to the
2337 destination of I3. This requires us to do a few adjustments. */
2338 PATTERN (i3
) = newpat
;
2339 adjust_for_new_dest (i3
);
2341 /* I3 now uses what used to be its destination and which is
2342 now I2's destination. That means we need a LOG_LINK from
2343 I3 to I2. But we used to have one, so we still will.
2345 However, some later insn might be using I2's dest and have
2346 a LOG_LINK pointing at I3. We must remove this link.
2347 The simplest way to remove the link is to point it at I1,
2348 which we know will be a NOTE. */
2350 for (insn
= NEXT_INSN (i3
);
2351 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2352 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2353 insn
= NEXT_INSN (insn
))
2355 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2357 for (link
= LOG_LINKS (insn
); link
;
2358 link
= XEXP (link
, 1))
2359 if (XEXP (link
, 0) == i3
)
2360 XEXP (link
, 0) = i1
;
2368 /* Similarly, check for a case where we have a PARALLEL of two independent
2369 SETs but we started with three insns. In this case, we can do the sets
2370 as two separate insns. This case occurs when some SET allows two
2371 other insns to combine, but the destination of that SET is still live. */
2373 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2374 && GET_CODE (newpat
) == PARALLEL
2375 && XVECLEN (newpat
, 0) == 2
2376 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2379 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2380 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2381 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2382 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2384 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2387 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2388 XVECEXP (newpat
, 0, 0))
2389 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2390 XVECEXP (newpat
, 0, 1))
2391 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2392 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2394 /* Normally, it doesn't matter which of the two is done first,
2395 but it does if one references cc0. In that case, it has to
2398 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2400 newi2pat
= XVECEXP (newpat
, 0, 0);
2401 newpat
= XVECEXP (newpat
, 0, 1);
2406 newi2pat
= XVECEXP (newpat
, 0, 1);
2407 newpat
= XVECEXP (newpat
, 0, 0);
2410 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2412 if (i2_code_number
>= 0)
2413 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2416 /* If it still isn't recognized, fail and change things back the way they
2418 if ((insn_code_number
< 0
2419 /* Is the result a reasonable ASM_OPERANDS? */
2420 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2426 /* If we had to change another insn, make sure it is valid also. */
2427 if (undobuf
.other_insn
)
2429 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2430 rtx new_other_notes
;
2433 CLEAR_HARD_REG_SET (newpat_used_regs
);
2435 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2438 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2444 PATTERN (undobuf
.other_insn
) = other_pat
;
2446 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2447 are still valid. Then add any non-duplicate notes added by
2448 recog_for_combine. */
2449 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2451 next
= XEXP (note
, 1);
2453 if (REG_NOTE_KIND (note
) == REG_UNUSED
2454 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2456 if (GET_CODE (XEXP (note
, 0)) == REG
)
2457 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2459 remove_note (undobuf
.other_insn
, note
);
2463 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2464 if (GET_CODE (XEXP (note
, 0)) == REG
)
2465 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2467 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2468 undobuf
.other_insn
, NULL_RTX
);
2471 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2472 they are adjacent to each other or not. */
2474 rtx p
= prev_nonnote_insn (i3
);
2475 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2476 && sets_cc0_p (newi2pat
))
2484 /* We now know that we can do this combination. Merge the insns and
2485 update the status of registers and LOG_LINKS. */
2488 rtx i3notes
, i2notes
, i1notes
= 0;
2489 rtx i3links
, i2links
, i1links
= 0;
2493 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2495 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2496 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2498 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2500 /* Ensure that we do not have something that should not be shared but
2501 occurs multiple times in the new insns. Check this by first
2502 resetting all the `used' flags and then copying anything is shared. */
2504 reset_used_flags (i3notes
);
2505 reset_used_flags (i2notes
);
2506 reset_used_flags (i1notes
);
2507 reset_used_flags (newpat
);
2508 reset_used_flags (newi2pat
);
2509 if (undobuf
.other_insn
)
2510 reset_used_flags (PATTERN (undobuf
.other_insn
));
2512 i3notes
= copy_rtx_if_shared (i3notes
);
2513 i2notes
= copy_rtx_if_shared (i2notes
);
2514 i1notes
= copy_rtx_if_shared (i1notes
);
2515 newpat
= copy_rtx_if_shared (newpat
);
2516 newi2pat
= copy_rtx_if_shared (newi2pat
);
2517 if (undobuf
.other_insn
)
2518 reset_used_flags (PATTERN (undobuf
.other_insn
));
2520 INSN_CODE (i3
) = insn_code_number
;
2521 PATTERN (i3
) = newpat
;
2523 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2525 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2527 reset_used_flags (call_usage
);
2528 call_usage
= copy_rtx (call_usage
);
2531 replace_rtx (call_usage
, i2dest
, i2src
);
2534 replace_rtx (call_usage
, i1dest
, i1src
);
2536 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2539 if (undobuf
.other_insn
)
2540 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2542 /* We had one special case above where I2 had more than one set and
2543 we replaced a destination of one of those sets with the destination
2544 of I3. In that case, we have to update LOG_LINKS of insns later
2545 in this basic block. Note that this (expensive) case is rare.
2547 Also, in this case, we must pretend that all REG_NOTEs for I2
2548 actually came from I3, so that REG_UNUSED notes from I2 will be
2549 properly handled. */
2551 if (i3_subst_into_i2
)
2553 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2554 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2555 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2556 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2557 && ! find_reg_note (i2
, REG_UNUSED
,
2558 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2559 for (temp
= NEXT_INSN (i2
);
2560 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2561 || BB_HEAD (this_basic_block
) != temp
);
2562 temp
= NEXT_INSN (temp
))
2563 if (temp
!= i3
&& INSN_P (temp
))
2564 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2565 if (XEXP (link
, 0) == i2
)
2566 XEXP (link
, 0) = i3
;
2571 while (XEXP (link
, 1))
2572 link
= XEXP (link
, 1);
2573 XEXP (link
, 1) = i2notes
;
2587 INSN_CODE (i2
) = i2_code_number
;
2588 PATTERN (i2
) = newi2pat
;
2592 PUT_CODE (i2
, NOTE
);
2593 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2594 NOTE_SOURCE_FILE (i2
) = 0;
2601 PUT_CODE (i1
, NOTE
);
2602 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2603 NOTE_SOURCE_FILE (i1
) = 0;
2606 /* Get death notes for everything that is now used in either I3 or
2607 I2 and used to die in a previous insn. If we built two new
2608 patterns, move from I1 to I2 then I2 to I3 so that we get the
2609 proper movement on registers that I2 modifies. */
2613 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2614 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2617 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2620 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2622 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2624 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2626 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2628 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2630 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2631 know these are REG_UNUSED and want them to go to the desired insn,
2632 so we always pass it as i3. We have not counted the notes in
2633 reg_n_deaths yet, so we need to do so now. */
2635 if (newi2pat
&& new_i2_notes
)
2637 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2638 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2639 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2641 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2646 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2647 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2648 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2650 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2653 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2654 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2655 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2656 in that case, it might delete I2. Similarly for I2 and I1.
2657 Show an additional death due to the REG_DEAD note we make here. If
2658 we discard it in distribute_notes, we will decrement it again. */
2662 if (GET_CODE (i3dest_killed
) == REG
)
2663 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2665 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2668 NULL_RTX
, i2
, NULL_RTX
);
2670 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2672 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2675 if (i2dest_in_i2src
)
2677 if (GET_CODE (i2dest
) == REG
)
2678 REG_N_DEATHS (REGNO (i2dest
))++;
2680 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2682 NULL_RTX
, i2
, NULL_RTX
);
2684 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2685 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2688 if (i1dest_in_i1src
)
2690 if (GET_CODE (i1dest
) == REG
)
2691 REG_N_DEATHS (REGNO (i1dest
))++;
2693 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2695 NULL_RTX
, i2
, NULL_RTX
);
2697 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2698 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2701 distribute_links (i3links
);
2702 distribute_links (i2links
);
2703 distribute_links (i1links
);
2705 if (GET_CODE (i2dest
) == REG
)
2708 rtx i2_insn
= 0, i2_val
= 0, set
;
2710 /* The insn that used to set this register doesn't exist, and
2711 this life of the register may not exist either. See if one of
2712 I3's links points to an insn that sets I2DEST. If it does,
2713 that is now the last known value for I2DEST. If we don't update
2714 this and I2 set the register to a value that depended on its old
2715 contents, we will get confused. If this insn is used, thing
2716 will be set correctly in combine_instructions. */
2718 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2719 if ((set
= single_set (XEXP (link
, 0))) != 0
2720 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2721 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2723 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2725 /* If the reg formerly set in I2 died only once and that was in I3,
2726 zero its use count so it won't make `reload' do any work. */
2728 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2729 && ! i2dest_in_i2src
)
2731 regno
= REGNO (i2dest
);
2732 REG_N_SETS (regno
)--;
2736 if (i1
&& GET_CODE (i1dest
) == REG
)
2739 rtx i1_insn
= 0, i1_val
= 0, set
;
2741 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2742 if ((set
= single_set (XEXP (link
, 0))) != 0
2743 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2744 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2746 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2748 regno
= REGNO (i1dest
);
2749 if (! added_sets_1
&& ! i1dest_in_i1src
)
2750 REG_N_SETS (regno
)--;
2753 /* Update reg_nonzero_bits et al for any changes that may have been made
2754 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2755 important. Because newi2pat can affect nonzero_bits of newpat */
2757 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2758 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2760 /* Set new_direct_jump_p if a new return or simple jump instruction
2763 If I3 is now an unconditional jump, ensure that it has a
2764 BARRIER following it since it may have initially been a
2765 conditional jump. It may also be the last nonnote insn. */
2767 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2769 *new_direct_jump_p
= 1;
2770 mark_jump_label (PATTERN (i3
), i3
, 0);
2772 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2773 || GET_CODE (temp
) != BARRIER
)
2774 emit_barrier_after (i3
);
2777 if (undobuf
.other_insn
!= NULL_RTX
2778 && (returnjump_p (undobuf
.other_insn
)
2779 || any_uncondjump_p (undobuf
.other_insn
)))
2781 *new_direct_jump_p
= 1;
2783 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2784 || GET_CODE (temp
) != BARRIER
)
2785 emit_barrier_after (undobuf
.other_insn
);
2788 /* An NOOP jump does not need barrier, but it does need cleaning up
2790 if (GET_CODE (newpat
) == SET
2791 && SET_SRC (newpat
) == pc_rtx
2792 && SET_DEST (newpat
) == pc_rtx
)
2793 *new_direct_jump_p
= 1;
2796 combine_successes
++;
2799 if (added_links_insn
2800 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2801 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2802 return added_links_insn
;
2804 return newi2pat
? i2
: i3
;
2807 /* Undo all the modifications recorded in undobuf. */
2812 struct undo
*undo
, *next
;
2814 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2818 *undo
->where
.i
= undo
->old_contents
.i
;
2820 *undo
->where
.r
= undo
->old_contents
.r
;
2822 undo
->next
= undobuf
.frees
;
2823 undobuf
.frees
= undo
;
2829 /* We've committed to accepting the changes we made. Move all
2830 of the undos to the free list. */
2835 struct undo
*undo
, *next
;
2837 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2840 undo
->next
= undobuf
.frees
;
2841 undobuf
.frees
= undo
;
2847 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2848 where we have an arithmetic expression and return that point. LOC will
2851 try_combine will call this function to see if an insn can be split into
2855 find_split_point (rtx
*loc
, rtx insn
)
2858 enum rtx_code code
= GET_CODE (x
);
2860 unsigned HOST_WIDE_INT len
= 0;
2861 HOST_WIDE_INT pos
= 0;
2863 rtx inner
= NULL_RTX
;
2865 /* First special-case some codes. */
2869 #ifdef INSN_SCHEDULING
2870 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2872 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2875 return find_split_point (&SUBREG_REG (x
), insn
);
2879 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2880 using LO_SUM and HIGH. */
2881 if (GET_CODE (XEXP (x
, 0)) == CONST
2882 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2885 gen_rtx_LO_SUM (Pmode
,
2886 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2888 return &XEXP (XEXP (x
, 0), 0);
2892 /* If we have a PLUS whose second operand is a constant and the
2893 address is not valid, perhaps will can split it up using
2894 the machine-specific way to split large constants. We use
2895 the first pseudo-reg (one of the virtual regs) as a placeholder;
2896 it will not remain in the result. */
2897 if (GET_CODE (XEXP (x
, 0)) == PLUS
2898 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2899 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2901 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2902 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2905 /* This should have produced two insns, each of which sets our
2906 placeholder. If the source of the second is a valid address,
2907 we can make put both sources together and make a split point
2911 && NEXT_INSN (seq
) != NULL_RTX
2912 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2913 && GET_CODE (seq
) == INSN
2914 && GET_CODE (PATTERN (seq
)) == SET
2915 && SET_DEST (PATTERN (seq
)) == reg
2916 && ! reg_mentioned_p (reg
,
2917 SET_SRC (PATTERN (seq
)))
2918 && GET_CODE (NEXT_INSN (seq
)) == INSN
2919 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2920 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2921 && memory_address_p (GET_MODE (x
),
2922 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2924 rtx src1
= SET_SRC (PATTERN (seq
));
2925 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2927 /* Replace the placeholder in SRC2 with SRC1. If we can
2928 find where in SRC2 it was placed, that can become our
2929 split point and we can replace this address with SRC2.
2930 Just try two obvious places. */
2932 src2
= replace_rtx (src2
, reg
, src1
);
2934 if (XEXP (src2
, 0) == src1
)
2935 split
= &XEXP (src2
, 0);
2936 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2937 && XEXP (XEXP (src2
, 0), 0) == src1
)
2938 split
= &XEXP (XEXP (src2
, 0), 0);
2942 SUBST (XEXP (x
, 0), src2
);
2947 /* If that didn't work, perhaps the first operand is complex and
2948 needs to be computed separately, so make a split point there.
2949 This will occur on machines that just support REG + CONST
2950 and have a constant moved through some previous computation. */
2952 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2953 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2954 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2956 return &XEXP (XEXP (x
, 0), 0);
2962 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2963 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2964 we need to put the operand into a register. So split at that
2967 if (SET_DEST (x
) == cc0_rtx
2968 && GET_CODE (SET_SRC (x
)) != COMPARE
2969 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2970 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2971 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2972 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2973 return &SET_SRC (x
);
2976 /* See if we can split SET_SRC as it stands. */
2977 split
= find_split_point (&SET_SRC (x
), insn
);
2978 if (split
&& split
!= &SET_SRC (x
))
2981 /* See if we can split SET_DEST as it stands. */
2982 split
= find_split_point (&SET_DEST (x
), insn
);
2983 if (split
&& split
!= &SET_DEST (x
))
2986 /* See if this is a bitfield assignment with everything constant. If
2987 so, this is an IOR of an AND, so split it into that. */
2988 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2989 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2990 <= HOST_BITS_PER_WIDE_INT
)
2991 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2992 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2993 && GET_CODE (SET_SRC (x
)) == CONST_INT
2994 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2995 + INTVAL (XEXP (SET_DEST (x
), 2)))
2996 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2997 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2999 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3000 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3001 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3002 rtx dest
= XEXP (SET_DEST (x
), 0);
3003 enum machine_mode mode
= GET_MODE (dest
);
3004 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3006 if (BITS_BIG_ENDIAN
)
3007 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3011 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3014 gen_binary (IOR
, mode
,
3015 gen_binary (AND
, mode
, dest
,
3016 gen_int_mode (~(mask
<< pos
),
3018 GEN_INT (src
<< pos
)));
3020 SUBST (SET_DEST (x
), dest
);
3022 split
= find_split_point (&SET_SRC (x
), insn
);
3023 if (split
&& split
!= &SET_SRC (x
))
3027 /* Otherwise, see if this is an operation that we can split into two.
3028 If so, try to split that. */
3029 code
= GET_CODE (SET_SRC (x
));
3034 /* If we are AND'ing with a large constant that is only a single
3035 bit and the result is only being used in a context where we
3036 need to know if it is zero or nonzero, replace it with a bit
3037 extraction. This will avoid the large constant, which might
3038 have taken more than one insn to make. If the constant were
3039 not a valid argument to the AND but took only one insn to make,
3040 this is no worse, but if it took more than one insn, it will
3043 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3044 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3045 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3046 && GET_CODE (SET_DEST (x
)) == REG
3047 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3048 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3049 && XEXP (*split
, 0) == SET_DEST (x
)
3050 && XEXP (*split
, 1) == const0_rtx
)
3052 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3053 XEXP (SET_SRC (x
), 0),
3054 pos
, NULL_RTX
, 1, 1, 0, 0);
3055 if (extraction
!= 0)
3057 SUBST (SET_SRC (x
), extraction
);
3058 return find_split_point (loc
, insn
);
3064 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3065 is known to be on, this can be converted into a NEG of a shift. */
3066 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3067 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3068 && 1 <= (pos
= exact_log2
3069 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3070 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3072 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3076 gen_rtx_LSHIFTRT (mode
,
3077 XEXP (SET_SRC (x
), 0),
3080 split
= find_split_point (&SET_SRC (x
), insn
);
3081 if (split
&& split
!= &SET_SRC (x
))
3087 inner
= XEXP (SET_SRC (x
), 0);
3089 /* We can't optimize if either mode is a partial integer
3090 mode as we don't know how many bits are significant
3092 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3093 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3097 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3103 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3104 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3106 inner
= XEXP (SET_SRC (x
), 0);
3107 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3108 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3110 if (BITS_BIG_ENDIAN
)
3111 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3112 unsignedp
= (code
== ZERO_EXTRACT
);
3120 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3122 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3124 /* For unsigned, we have a choice of a shift followed by an
3125 AND or two shifts. Use two shifts for field sizes where the
3126 constant might be too large. We assume here that we can
3127 always at least get 8-bit constants in an AND insn, which is
3128 true for every current RISC. */
3130 if (unsignedp
&& len
<= 8)
3135 (mode
, gen_lowpart (mode
, inner
),
3137 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3139 split
= find_split_point (&SET_SRC (x
), insn
);
3140 if (split
&& split
!= &SET_SRC (x
))
3147 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3148 gen_rtx_ASHIFT (mode
,
3149 gen_lowpart (mode
, inner
),
3150 GEN_INT (GET_MODE_BITSIZE (mode
)
3152 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3154 split
= find_split_point (&SET_SRC (x
), insn
);
3155 if (split
&& split
!= &SET_SRC (x
))
3160 /* See if this is a simple operation with a constant as the second
3161 operand. It might be that this constant is out of range and hence
3162 could be used as a split point. */
3163 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3165 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3166 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3167 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3168 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3169 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3171 return &XEXP (SET_SRC (x
), 1);
3173 /* Finally, see if this is a simple operation with its first operand
3174 not in a register. The operation might require this operand in a
3175 register, so return it as a split point. We can always do this
3176 because if the first operand were another operation, we would have
3177 already found it as a split point. */
3178 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3179 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3182 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3183 return &XEXP (SET_SRC (x
), 0);
3189 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3190 it is better to write this as (not (ior A B)) so we can split it.
3191 Similarly for IOR. */
3192 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3195 gen_rtx_NOT (GET_MODE (x
),
3196 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3198 XEXP (XEXP (x
, 0), 0),
3199 XEXP (XEXP (x
, 1), 0))));
3200 return find_split_point (loc
, insn
);
3203 /* Many RISC machines have a large set of logical insns. If the
3204 second operand is a NOT, put it first so we will try to split the
3205 other operand first. */
3206 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3208 rtx tem
= XEXP (x
, 0);
3209 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3210 SUBST (XEXP (x
, 1), tem
);
3218 /* Otherwise, select our actions depending on our rtx class. */
3219 switch (GET_RTX_CLASS (code
))
3221 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3223 split
= find_split_point (&XEXP (x
, 2), insn
);
3226 /* ... fall through ... */
3230 split
= find_split_point (&XEXP (x
, 1), insn
);
3233 /* ... fall through ... */
3235 /* Some machines have (and (shift ...) ...) insns. If X is not
3236 an AND, but XEXP (X, 0) is, use it as our split point. */
3237 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3238 return &XEXP (x
, 0);
3240 split
= find_split_point (&XEXP (x
, 0), insn
);
3246 /* Otherwise, we don't have a split point. */
3250 /* Throughout X, replace FROM with TO, and return the result.
3251 The result is TO if X is FROM;
3252 otherwise the result is X, but its contents may have been modified.
3253 If they were modified, a record was made in undobuf so that
3254 undo_all will (among other things) return X to its original state.
3256 If the number of changes necessary is too much to record to undo,
3257 the excess changes are not made, so the result is invalid.
3258 The changes already made can still be undone.
3259 undobuf.num_undo is incremented for such changes, so by testing that
3260 the caller can tell whether the result is valid.
3262 `n_occurrences' is incremented each time FROM is replaced.
3264 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3266 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3267 by copying if `n_occurrences' is nonzero. */
3270 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3272 enum rtx_code code
= GET_CODE (x
);
3273 enum machine_mode op0_mode
= VOIDmode
;
3278 /* Two expressions are equal if they are identical copies of a shared
3279 RTX or if they are both registers with the same register number
3282 #define COMBINE_RTX_EQUAL_P(X,Y) \
3284 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3285 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3287 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3290 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3293 /* If X and FROM are the same register but different modes, they will
3294 not have been seen as equal above. However, flow.c will make a
3295 LOG_LINKS entry for that case. If we do nothing, we will try to
3296 rerecognize our original insn and, when it succeeds, we will
3297 delete the feeding insn, which is incorrect.
3299 So force this insn not to match in this (rare) case. */
3300 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3301 && REGNO (x
) == REGNO (from
))
3302 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3304 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3305 of which may contain things that can be combined. */
3306 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3309 /* It is possible to have a subexpression appear twice in the insn.
3310 Suppose that FROM is a register that appears within TO.
3311 Then, after that subexpression has been scanned once by `subst',
3312 the second time it is scanned, TO may be found. If we were
3313 to scan TO here, we would find FROM within it and create a
3314 self-referent rtl structure which is completely wrong. */
3315 if (COMBINE_RTX_EQUAL_P (x
, to
))
3318 /* Parallel asm_operands need special attention because all of the
3319 inputs are shared across the arms. Furthermore, unsharing the
3320 rtl results in recognition failures. Failure to handle this case
3321 specially can result in circular rtl.
3323 Solve this by doing a normal pass across the first entry of the
3324 parallel, and only processing the SET_DESTs of the subsequent
3327 if (code
== PARALLEL
3328 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3329 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3331 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3333 /* If this substitution failed, this whole thing fails. */
3334 if (GET_CODE (new) == CLOBBER
3335 && XEXP (new, 0) == const0_rtx
)
3338 SUBST (XVECEXP (x
, 0, 0), new);
3340 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3342 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3344 if (GET_CODE (dest
) != REG
3345 && GET_CODE (dest
) != CC0
3346 && GET_CODE (dest
) != PC
)
3348 new = subst (dest
, from
, to
, 0, unique_copy
);
3350 /* If this substitution failed, this whole thing fails. */
3351 if (GET_CODE (new) == CLOBBER
3352 && XEXP (new, 0) == const0_rtx
)
3355 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3361 len
= GET_RTX_LENGTH (code
);
3362 fmt
= GET_RTX_FORMAT (code
);
3364 /* We don't need to process a SET_DEST that is a register, CC0,
3365 or PC, so set up to skip this common case. All other cases
3366 where we want to suppress replacing something inside a
3367 SET_SRC are handled via the IN_DEST operand. */
3369 && (GET_CODE (SET_DEST (x
)) == REG
3370 || GET_CODE (SET_DEST (x
)) == CC0
3371 || GET_CODE (SET_DEST (x
)) == PC
))
3374 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3377 op0_mode
= GET_MODE (XEXP (x
, 0));
3379 for (i
= 0; i
< len
; i
++)
3384 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3386 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3388 new = (unique_copy
&& n_occurrences
3389 ? copy_rtx (to
) : to
);
3394 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3397 /* If this substitution failed, this whole thing
3399 if (GET_CODE (new) == CLOBBER
3400 && XEXP (new, 0) == const0_rtx
)
3404 SUBST (XVECEXP (x
, i
, j
), new);
3407 else if (fmt
[i
] == 'e')
3409 /* If this is a register being set, ignore it. */
3412 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3413 || code
== ZERO_EXTRACT
)
3415 && GET_CODE (new) == REG
)
3418 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3420 /* In general, don't install a subreg involving two
3421 modes not tieable. It can worsen register
3422 allocation, and can even make invalid reload
3423 insns, since the reg inside may need to be copied
3424 from in the outside mode, and that may be invalid
3425 if it is an fp reg copied in integer mode.
3427 We allow two exceptions to this: It is valid if
3428 it is inside another SUBREG and the mode of that
3429 SUBREG and the mode of the inside of TO is
3430 tieable and it is valid if X is a SET that copies
3433 if (GET_CODE (to
) == SUBREG
3434 && ! MODES_TIEABLE_P (GET_MODE (to
),
3435 GET_MODE (SUBREG_REG (to
)))
3436 && ! (code
== SUBREG
3437 && MODES_TIEABLE_P (GET_MODE (x
),
3438 GET_MODE (SUBREG_REG (to
))))
3440 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3443 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3445 #ifdef CANNOT_CHANGE_MODE_CLASS
3447 && GET_CODE (to
) == REG
3448 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3449 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3452 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3455 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3459 /* If we are in a SET_DEST, suppress most cases unless we
3460 have gone inside a MEM, in which case we want to
3461 simplify the address. We assume here that things that
3462 are actually part of the destination have their inner
3463 parts in the first expression. This is true for SUBREG,
3464 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3465 things aside from REG and MEM that should appear in a
3467 new = subst (XEXP (x
, i
), from
, to
,
3469 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3470 || code
== ZERO_EXTRACT
))
3472 && i
== 0), unique_copy
);
3474 /* If we found that we will have to reject this combination,
3475 indicate that by returning the CLOBBER ourselves, rather than
3476 an expression containing it. This will speed things up as
3477 well as prevent accidents where two CLOBBERs are considered
3478 to be equal, thus producing an incorrect simplification. */
3480 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3483 if (GET_CODE (x
) == SUBREG
3484 && (GET_CODE (new) == CONST_INT
3485 || GET_CODE (new) == CONST_DOUBLE
))
3487 enum machine_mode mode
= GET_MODE (x
);
3489 x
= simplify_subreg (GET_MODE (x
), new,
3490 GET_MODE (SUBREG_REG (x
)),
3493 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3495 else if (GET_CODE (new) == CONST_INT
3496 && GET_CODE (x
) == ZERO_EXTEND
)
3498 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3499 new, GET_MODE (XEXP (x
, 0)));
3504 SUBST (XEXP (x
, i
), new);
3509 /* Try to simplify X. If the simplification changed the code, it is likely
3510 that further simplification will help, so loop, but limit the number
3511 of repetitions that will be performed. */
3513 for (i
= 0; i
< 4; i
++)
3515 /* If X is sufficiently simple, don't bother trying to do anything
3517 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3518 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3520 if (GET_CODE (x
) == code
)
3523 code
= GET_CODE (x
);
3525 /* We no longer know the original mode of operand 0 since we
3526 have changed the form of X) */
3527 op0_mode
= VOIDmode
;
3533 /* Simplify X, a piece of RTL. We just operate on the expression at the
3534 outer level; call `subst' to simplify recursively. Return the new
3537 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3538 will be the iteration even if an expression with a code different from
3539 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3542 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3545 enum rtx_code code
= GET_CODE (x
);
3546 enum machine_mode mode
= GET_MODE (x
);
3551 /* If this is a commutative operation, put a constant last and a complex
3552 expression first. We don't need to do this for comparisons here. */
3553 if (GET_RTX_CLASS (code
) == 'c'
3554 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3557 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3558 SUBST (XEXP (x
, 1), temp
);
3561 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3562 sign extension of a PLUS with a constant, reverse the order of the sign
3563 extension and the addition. Note that this not the same as the original
3564 code, but overflow is undefined for signed values. Also note that the
3565 PLUS will have been partially moved "inside" the sign-extension, so that
3566 the first operand of X will really look like:
3567 (ashiftrt (plus (ashift A C4) C5) C4).
3569 (plus (ashiftrt (ashift A C4) C2) C4)
3570 and replace the first operand of X with that expression. Later parts
3571 of this function may simplify the expression further.
3573 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3574 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3575 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3577 We do this to simplify address expressions. */
3579 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3580 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3581 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3582 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3583 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3584 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3585 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3586 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3587 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3588 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3589 XEXP (XEXP (x
, 0), 1))) != 0)
3592 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3593 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3594 INTVAL (XEXP (XEXP (x
, 0), 1)));
3596 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3597 INTVAL (XEXP (XEXP (x
, 0), 1)));
3599 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3602 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3603 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3604 things. Check for cases where both arms are testing the same
3607 Don't do anything if all operands are very simple. */
3609 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3610 || GET_RTX_CLASS (code
) == '<')
3611 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3612 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3613 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3615 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3616 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3617 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3619 || (GET_RTX_CLASS (code
) == '1'
3620 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3621 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3622 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3625 rtx cond
, true_rtx
, false_rtx
;
3627 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3629 /* If everything is a comparison, what we have is highly unlikely
3630 to be simpler, so don't use it. */
3631 && ! (GET_RTX_CLASS (code
) == '<'
3632 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3633 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3635 rtx cop1
= const0_rtx
;
3636 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3638 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3641 /* Simplify the alternative arms; this may collapse the true and
3642 false arms to store-flag values. Be careful to use copy_rtx
3643 here since true_rtx or false_rtx might share RTL with x as a
3644 result of the if_then_else_cond call above. */
3645 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3646 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3648 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3649 is unlikely to be simpler. */
3650 if (general_operand (true_rtx
, VOIDmode
)
3651 && general_operand (false_rtx
, VOIDmode
))
3653 enum rtx_code reversed
;
3655 /* Restarting if we generate a store-flag expression will cause
3656 us to loop. Just drop through in this case. */
3658 /* If the result values are STORE_FLAG_VALUE and zero, we can
3659 just make the comparison operation. */
3660 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3661 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3662 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3663 && ((reversed
= reversed_comparison_code_parts
3664 (cond_code
, cond
, cop1
, NULL
))
3666 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3668 /* Likewise, we can make the negate of a comparison operation
3669 if the result values are - STORE_FLAG_VALUE and zero. */
3670 else if (GET_CODE (true_rtx
) == CONST_INT
3671 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3672 && false_rtx
== const0_rtx
)
3673 x
= simplify_gen_unary (NEG
, mode
,
3674 gen_binary (cond_code
, mode
, cond
,
3677 else if (GET_CODE (false_rtx
) == CONST_INT
3678 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3679 && true_rtx
== const0_rtx
3680 && ((reversed
= reversed_comparison_code_parts
3681 (cond_code
, cond
, cop1
, NULL
))
3683 x
= simplify_gen_unary (NEG
, mode
,
3684 gen_binary (reversed
, mode
,
3688 return gen_rtx_IF_THEN_ELSE (mode
,
3689 gen_binary (cond_code
, VOIDmode
,
3691 true_rtx
, false_rtx
);
3693 code
= GET_CODE (x
);
3694 op0_mode
= VOIDmode
;
3699 /* Try to fold this expression in case we have constants that weren't
3702 switch (GET_RTX_CLASS (code
))
3705 if (op0_mode
== VOIDmode
)
3706 op0_mode
= GET_MODE (XEXP (x
, 0));
3707 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3711 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3712 if (cmp_mode
== VOIDmode
)
3714 cmp_mode
= GET_MODE (XEXP (x
, 1));
3715 if (cmp_mode
== VOIDmode
)
3716 cmp_mode
= op0_mode
;
3718 temp
= simplify_relational_operation (code
, cmp_mode
,
3719 XEXP (x
, 0), XEXP (x
, 1));
3721 #ifdef FLOAT_STORE_FLAG_VALUE
3722 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3724 if (temp
== const0_rtx
)
3725 temp
= CONST0_RTX (mode
);
3727 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3734 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3738 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3739 XEXP (x
, 1), XEXP (x
, 2));
3746 code
= GET_CODE (temp
);
3747 op0_mode
= VOIDmode
;
3748 mode
= GET_MODE (temp
);
3751 /* First see if we can apply the inverse distributive law. */
3752 if (code
== PLUS
|| code
== MINUS
3753 || code
== AND
|| code
== IOR
|| code
== XOR
)
3755 x
= apply_distributive_law (x
);
3756 code
= GET_CODE (x
);
3757 op0_mode
= VOIDmode
;
3760 /* If CODE is an associative operation not otherwise handled, see if we
3761 can associate some operands. This can win if they are constants or
3762 if they are logically related (i.e. (a & b) & a). */
3763 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3764 || code
== AND
|| code
== IOR
|| code
== XOR
3765 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3766 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3767 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3769 if (GET_CODE (XEXP (x
, 0)) == code
)
3771 rtx other
= XEXP (XEXP (x
, 0), 0);
3772 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3773 rtx inner_op1
= XEXP (x
, 1);
3776 /* Make sure we pass the constant operand if any as the second
3777 one if this is a commutative operation. */
3778 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3780 rtx tem
= inner_op0
;
3781 inner_op0
= inner_op1
;
3784 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3785 : code
== DIV
? MULT
3787 mode
, inner_op0
, inner_op1
);
3789 /* For commutative operations, try the other pair if that one
3791 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3793 other
= XEXP (XEXP (x
, 0), 1);
3794 inner
= simplify_binary_operation (code
, mode
,
3795 XEXP (XEXP (x
, 0), 0),
3800 return gen_binary (code
, mode
, other
, inner
);
3804 /* A little bit of algebraic simplification here. */
3808 /* Ensure that our address has any ASHIFTs converted to MULT in case
3809 address-recognizing predicates are called later. */
3810 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3811 SUBST (XEXP (x
, 0), temp
);
3815 if (op0_mode
== VOIDmode
)
3816 op0_mode
= GET_MODE (SUBREG_REG (x
));
3818 /* See if this can be moved to simplify_subreg. */
3819 if (CONSTANT_P (SUBREG_REG (x
))
3820 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3821 /* Don't call gen_lowpart if the inner mode
3822 is VOIDmode and we cannot simplify it, as SUBREG without
3823 inner mode is invalid. */
3824 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3825 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3826 return gen_lowpart (mode
, SUBREG_REG (x
));
3828 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3832 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3838 /* Don't change the mode of the MEM if that would change the meaning
3840 if (GET_CODE (SUBREG_REG (x
)) == MEM
3841 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3842 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3843 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3845 /* Note that we cannot do any narrowing for non-constants since
3846 we might have been counting on using the fact that some bits were
3847 zero. We now do this in the SET. */
3852 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3853 && subreg_lowpart_p (XEXP (x
, 0))
3854 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3855 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3856 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3857 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3859 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3861 x
= gen_rtx_ROTATE (inner_mode
,
3862 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3864 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3865 return gen_lowpart (mode
, x
);
3868 /* Apply De Morgan's laws to reduce number of patterns for machines
3869 with negating logical insns (and-not, nand, etc.). If result has
3870 only one NOT, put it first, since that is how the patterns are
3873 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3875 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3876 enum machine_mode op_mode
;
3878 op_mode
= GET_MODE (in1
);
3879 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3881 op_mode
= GET_MODE (in2
);
3882 if (op_mode
== VOIDmode
)
3884 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3886 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3889 in2
= in1
; in1
= tem
;
3892 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3898 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3899 if (GET_CODE (XEXP (x
, 0)) == XOR
3900 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3901 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3902 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3904 temp
= expand_compound_operation (XEXP (x
, 0));
3906 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3907 replaced by (lshiftrt X C). This will convert
3908 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3910 if (GET_CODE (temp
) == ASHIFTRT
3911 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3912 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3913 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3914 INTVAL (XEXP (temp
, 1)));
3916 /* If X has only a single bit that might be nonzero, say, bit I, convert
3917 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3918 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3919 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3920 or a SUBREG of one since we'd be making the expression more
3921 complex if it was just a register. */
3923 if (GET_CODE (temp
) != REG
3924 && ! (GET_CODE (temp
) == SUBREG
3925 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3926 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3928 rtx temp1
= simplify_shift_const
3929 (NULL_RTX
, ASHIFTRT
, mode
,
3930 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3931 GET_MODE_BITSIZE (mode
) - 1 - i
),
3932 GET_MODE_BITSIZE (mode
) - 1 - i
);
3934 /* If all we did was surround TEMP with the two shifts, we
3935 haven't improved anything, so don't use it. Otherwise,
3936 we are better off with TEMP1. */
3937 if (GET_CODE (temp1
) != ASHIFTRT
3938 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3939 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3945 /* We can't handle truncation to a partial integer mode here
3946 because we don't know the real bitsize of the partial
3948 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3951 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3952 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3953 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3955 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3956 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3958 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3959 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3960 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3961 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3962 return XEXP (XEXP (x
, 0), 0);
3964 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3965 (OP:SI foo:SI) if OP is NEG or ABS. */
3966 if ((GET_CODE (XEXP (x
, 0)) == ABS
3967 || GET_CODE (XEXP (x
, 0)) == NEG
)
3968 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3969 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3970 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3971 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3972 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3974 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3976 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3977 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3978 && subreg_lowpart_p (XEXP (x
, 0)))
3979 return SUBREG_REG (XEXP (x
, 0));
3981 /* If we know that the value is already truncated, we can
3982 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3983 is nonzero for the corresponding modes. But don't do this
3984 for an (LSHIFTRT (MULT ...)) since this will cause problems
3985 with the umulXi3_highpart patterns. */
3986 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3987 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3988 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3989 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3990 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3991 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3992 return gen_lowpart (mode
, XEXP (x
, 0));
3994 /* A truncate of a comparison can be replaced with a subreg if
3995 STORE_FLAG_VALUE permits. This is like the previous test,
3996 but it works even if the comparison is done in a mode larger
3997 than HOST_BITS_PER_WIDE_INT. */
3998 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3999 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4000 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4001 return gen_lowpart (mode
, XEXP (x
, 0));
4003 /* Similarly, a truncate of a register whose value is a
4004 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4006 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4007 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4008 && (temp
= get_last_value (XEXP (x
, 0)))
4009 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4010 return gen_lowpart (mode
, XEXP (x
, 0));
4014 case FLOAT_TRUNCATE
:
4015 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4016 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4017 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4018 return XEXP (XEXP (x
, 0), 0);
4020 /* (float_truncate:SF (float_truncate:DF foo:XF))
4021 = (float_truncate:SF foo:XF).
4022 This may eliminate double rounding, so it is unsafe.
4024 (float_truncate:SF (float_extend:XF foo:DF))
4025 = (float_truncate:SF foo:DF).
4027 (float_truncate:DF (float_extend:XF foo:SF))
4028 = (float_extend:SF foo:DF). */
4029 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4030 && flag_unsafe_math_optimizations
)
4031 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4032 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4034 > GET_MODE_SIZE (mode
)
4035 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4037 XEXP (XEXP (x
, 0), 0), mode
);
4039 /* (float_truncate (float x)) is (float x) */
4040 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4041 && (flag_unsafe_math_optimizations
4042 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4043 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4044 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4045 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4046 return simplify_gen_unary (FLOAT
, mode
,
4047 XEXP (XEXP (x
, 0), 0),
4048 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4050 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4051 (OP:SF foo:SF) if OP is NEG or ABS. */
4052 if ((GET_CODE (XEXP (x
, 0)) == ABS
4053 || GET_CODE (XEXP (x
, 0)) == NEG
)
4054 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4055 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4056 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4057 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4059 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4060 is (float_truncate:SF x). */
4061 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4062 && subreg_lowpart_p (XEXP (x
, 0))
4063 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4064 return SUBREG_REG (XEXP (x
, 0));
4067 /* (float_extend (float_extend x)) is (float_extend x)
4069 (float_extend (float x)) is (float x) assuming that double
4070 rounding can't happen.
4072 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4073 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4074 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4075 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4076 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4077 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4078 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4079 XEXP (XEXP (x
, 0), 0),
4080 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4085 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4086 using cc0, in which case we want to leave it as a COMPARE
4087 so we can distinguish it from a register-register-copy. */
4088 if (XEXP (x
, 1) == const0_rtx
)
4091 /* x - 0 is the same as x unless x's mode has signed zeros and
4092 allows rounding towards -infinity. Under those conditions,
4094 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4095 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4096 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4102 /* (const (const X)) can become (const X). Do it this way rather than
4103 returning the inner CONST since CONST can be shared with a
4105 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4106 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4111 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4112 can add in an offset. find_split_point will split this address up
4113 again if it doesn't match. */
4114 if (GET_CODE (XEXP (x
, 0)) == HIGH
4115 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4121 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4123 if (GET_CODE (XEXP (x
, 0)) == MULT
4124 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4128 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4129 in2
= XEXP (XEXP (x
, 0), 1);
4130 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4131 gen_binary (MULT
, mode
, in1
, in2
));
4134 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4135 outermost. That's because that's the way indexed addresses are
4136 supposed to appear. This code used to check many more cases, but
4137 they are now checked elsewhere. */
4138 if (GET_CODE (XEXP (x
, 0)) == PLUS
4139 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4140 return gen_binary (PLUS
, mode
,
4141 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4143 XEXP (XEXP (x
, 0), 1));
4145 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4146 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4147 bit-field and can be replaced by either a sign_extend or a
4148 sign_extract. The `and' may be a zero_extend and the two
4149 <c>, -<c> constants may be reversed. */
4150 if (GET_CODE (XEXP (x
, 0)) == XOR
4151 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4152 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4153 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4154 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4155 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4156 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4157 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4158 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4159 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4160 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4161 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4162 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4163 == (unsigned int) i
+ 1))))
4164 return simplify_shift_const
4165 (NULL_RTX
, ASHIFTRT
, mode
,
4166 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4167 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4168 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4169 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4171 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4172 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4173 is 1. This produces better code than the alternative immediately
4175 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4176 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4177 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4178 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4179 XEXP (XEXP (x
, 0), 0),
4180 XEXP (XEXP (x
, 0), 1))))
4182 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4184 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4185 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4186 the bitsize of the mode - 1. This allows simplification of
4187 "a = (b & 8) == 0;" */
4188 if (XEXP (x
, 1) == constm1_rtx
4189 && GET_CODE (XEXP (x
, 0)) != REG
4190 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4191 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4192 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4193 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4194 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4195 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4196 GET_MODE_BITSIZE (mode
) - 1),
4197 GET_MODE_BITSIZE (mode
) - 1);
4199 /* If we are adding two things that have no bits in common, convert
4200 the addition into an IOR. This will often be further simplified,
4201 for example in cases like ((a & 1) + (a & 2)), which can
4204 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4205 && (nonzero_bits (XEXP (x
, 0), mode
)
4206 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4208 /* Try to simplify the expression further. */
4209 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4210 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4212 /* If we could, great. If not, do not go ahead with the IOR
4213 replacement, since PLUS appears in many special purpose
4214 address arithmetic instructions. */
4215 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4221 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4222 by reversing the comparison code if valid. */
4223 if (STORE_FLAG_VALUE
== 1
4224 && XEXP (x
, 0) == const1_rtx
4225 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4226 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4227 XEXP (XEXP (x
, 1), 0),
4228 XEXP (XEXP (x
, 1), 1))))
4231 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4232 (and <foo> (const_int pow2-1)) */
4233 if (GET_CODE (XEXP (x
, 1)) == AND
4234 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4235 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4236 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4237 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4238 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4240 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4242 if (GET_CODE (XEXP (x
, 1)) == MULT
4243 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4247 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4248 in2
= XEXP (XEXP (x
, 1), 1);
4249 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4253 /* Canonicalize (minus (neg A) (mult B C)) to
4254 (minus (mult (neg B) C) A). */
4255 if (GET_CODE (XEXP (x
, 1)) == MULT
4256 && GET_CODE (XEXP (x
, 0)) == NEG
)
4260 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4261 in2
= XEXP (XEXP (x
, 1), 1);
4262 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4263 XEXP (XEXP (x
, 0), 0));
4266 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4268 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4269 return gen_binary (MINUS
, mode
,
4270 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4271 XEXP (XEXP (x
, 1), 0)),
4272 XEXP (XEXP (x
, 1), 1));
4276 /* If we have (mult (plus A B) C), apply the distributive law and then
4277 the inverse distributive law to see if things simplify. This
4278 occurs mostly in addresses, often when unrolling loops. */
4280 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4282 x
= apply_distributive_law
4283 (gen_binary (PLUS
, mode
,
4284 gen_binary (MULT
, mode
,
4285 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4286 gen_binary (MULT
, mode
,
4287 XEXP (XEXP (x
, 0), 1),
4288 copy_rtx (XEXP (x
, 1)))));
4290 if (GET_CODE (x
) != MULT
)
4293 /* Try simplify a*(b/c) as (a*b)/c. */
4294 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4295 && GET_CODE (XEXP (x
, 0)) == DIV
)
4297 rtx tem
= simplify_binary_operation (MULT
, mode
,
4298 XEXP (XEXP (x
, 0), 0),
4301 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4306 /* If this is a divide by a power of two, treat it as a shift if
4307 its first operand is a shift. */
4308 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4309 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4310 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4311 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4312 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4313 || GET_CODE (XEXP (x
, 0)) == ROTATE
4314 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4315 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4319 case GT
: case GTU
: case GE
: case GEU
:
4320 case LT
: case LTU
: case LE
: case LEU
:
4321 case UNEQ
: case LTGT
:
4322 case UNGT
: case UNGE
:
4323 case UNLT
: case UNLE
:
4324 case UNORDERED
: case ORDERED
:
4325 /* If the first operand is a condition code, we can't do anything
4327 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4328 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4329 && ! CC0_P (XEXP (x
, 0))))
4331 rtx op0
= XEXP (x
, 0);
4332 rtx op1
= XEXP (x
, 1);
4333 enum rtx_code new_code
;
4335 if (GET_CODE (op0
) == COMPARE
)
4336 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4338 /* Simplify our comparison, if possible. */
4339 new_code
= simplify_comparison (code
, &op0
, &op1
);
4341 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4342 if only the low-order bit is possibly nonzero in X (such as when
4343 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4344 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4345 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4348 Remove any ZERO_EXTRACT we made when thinking this was a
4349 comparison. It may now be simpler to use, e.g., an AND. If a
4350 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4351 the call to make_compound_operation in the SET case. */
4353 if (STORE_FLAG_VALUE
== 1
4354 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4355 && op1
== const0_rtx
4356 && mode
== GET_MODE (op0
)
4357 && nonzero_bits (op0
, mode
) == 1)
4358 return gen_lowpart (mode
,
4359 expand_compound_operation (op0
));
4361 else if (STORE_FLAG_VALUE
== 1
4362 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4363 && op1
== const0_rtx
4364 && mode
== GET_MODE (op0
)
4365 && (num_sign_bit_copies (op0
, mode
)
4366 == GET_MODE_BITSIZE (mode
)))
4368 op0
= expand_compound_operation (op0
);
4369 return simplify_gen_unary (NEG
, mode
,
4370 gen_lowpart (mode
, op0
),
4374 else if (STORE_FLAG_VALUE
== 1
4375 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4376 && op1
== const0_rtx
4377 && mode
== GET_MODE (op0
)
4378 && nonzero_bits (op0
, mode
) == 1)
4380 op0
= expand_compound_operation (op0
);
4381 return gen_binary (XOR
, mode
,
4382 gen_lowpart (mode
, op0
),
4386 else if (STORE_FLAG_VALUE
== 1
4387 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4388 && op1
== const0_rtx
4389 && mode
== GET_MODE (op0
)
4390 && (num_sign_bit_copies (op0
, mode
)
4391 == GET_MODE_BITSIZE (mode
)))
4393 op0
= expand_compound_operation (op0
);
4394 return plus_constant (gen_lowpart (mode
, op0
), 1);
4397 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4399 if (STORE_FLAG_VALUE
== -1
4400 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4401 && op1
== const0_rtx
4402 && (num_sign_bit_copies (op0
, mode
)
4403 == GET_MODE_BITSIZE (mode
)))
4404 return gen_lowpart (mode
,
4405 expand_compound_operation (op0
));
4407 else if (STORE_FLAG_VALUE
== -1
4408 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4409 && op1
== const0_rtx
4410 && mode
== GET_MODE (op0
)
4411 && nonzero_bits (op0
, mode
) == 1)
4413 op0
= expand_compound_operation (op0
);
4414 return simplify_gen_unary (NEG
, mode
,
4415 gen_lowpart (mode
, op0
),
4419 else if (STORE_FLAG_VALUE
== -1
4420 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4421 && op1
== const0_rtx
4422 && mode
== GET_MODE (op0
)
4423 && (num_sign_bit_copies (op0
, mode
)
4424 == GET_MODE_BITSIZE (mode
)))
4426 op0
= expand_compound_operation (op0
);
4427 return simplify_gen_unary (NOT
, mode
,
4428 gen_lowpart (mode
, op0
),
4432 /* If X is 0/1, (eq X 0) is X-1. */
4433 else if (STORE_FLAG_VALUE
== -1
4434 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4435 && op1
== const0_rtx
4436 && mode
== GET_MODE (op0
)
4437 && nonzero_bits (op0
, mode
) == 1)
4439 op0
= expand_compound_operation (op0
);
4440 return plus_constant (gen_lowpart (mode
, op0
), -1);
4443 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4444 one bit that might be nonzero, we can convert (ne x 0) to
4445 (ashift x c) where C puts the bit in the sign bit. Remove any
4446 AND with STORE_FLAG_VALUE when we are done, since we are only
4447 going to test the sign bit. */
4448 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4449 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4450 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4451 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4452 && op1
== const0_rtx
4453 && mode
== GET_MODE (op0
)
4454 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4456 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4457 expand_compound_operation (op0
),
4458 GET_MODE_BITSIZE (mode
) - 1 - i
);
4459 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4465 /* If the code changed, return a whole new comparison. */
4466 if (new_code
!= code
)
4467 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4469 /* Otherwise, keep this operation, but maybe change its operands.
4470 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4471 SUBST (XEXP (x
, 0), op0
);
4472 SUBST (XEXP (x
, 1), op1
);
4477 return simplify_if_then_else (x
);
4483 /* If we are processing SET_DEST, we are done. */
4487 return expand_compound_operation (x
);
4490 return simplify_set (x
);
4495 return simplify_logical (x
, last
);
4498 /* (abs (neg <foo>)) -> (abs <foo>) */
4499 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4500 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4502 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4504 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4507 /* If operand is something known to be positive, ignore the ABS. */
4508 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4509 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4510 <= HOST_BITS_PER_WIDE_INT
)
4511 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4512 & ((HOST_WIDE_INT
) 1
4513 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4517 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4518 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4519 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4524 /* (ffs (*_extend <X>)) = (ffs <X>) */
4525 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4526 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4527 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4532 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4533 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4534 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4538 /* (float (sign_extend <X>)) = (float <X>). */
4539 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4540 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4548 /* If this is a shift by a constant amount, simplify it. */
4549 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4550 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4551 INTVAL (XEXP (x
, 1)));
4553 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4555 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4557 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4564 rtx op0
= XEXP (x
, 0);
4565 rtx op1
= XEXP (x
, 1);
4568 if (GET_CODE (op1
) != PARALLEL
)
4570 len
= XVECLEN (op1
, 0);
4572 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4573 && GET_CODE (op0
) == VEC_CONCAT
)
4575 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4577 /* Try to find the element in the VEC_CONCAT. */
4580 if (GET_MODE (op0
) == GET_MODE (x
))
4582 if (GET_CODE (op0
) == VEC_CONCAT
)
4584 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4585 if (op0_size
< offset
)
4586 op0
= XEXP (op0
, 0);
4590 op0
= XEXP (op0
, 1);
4608 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4611 simplify_if_then_else (rtx x
)
4613 enum machine_mode mode
= GET_MODE (x
);
4614 rtx cond
= XEXP (x
, 0);
4615 rtx true_rtx
= XEXP (x
, 1);
4616 rtx false_rtx
= XEXP (x
, 2);
4617 enum rtx_code true_code
= GET_CODE (cond
);
4618 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4621 enum rtx_code false_code
;
4624 /* Simplify storing of the truth value. */
4625 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4626 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4628 /* Also when the truth value has to be reversed. */
4630 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4631 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4635 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4636 in it is being compared against certain values. Get the true and false
4637 comparisons and see if that says anything about the value of each arm. */
4640 && ((false_code
= combine_reversed_comparison_code (cond
))
4642 && GET_CODE (XEXP (cond
, 0)) == REG
)
4645 rtx from
= XEXP (cond
, 0);
4646 rtx true_val
= XEXP (cond
, 1);
4647 rtx false_val
= true_val
;
4650 /* If FALSE_CODE is EQ, swap the codes and arms. */
4652 if (false_code
== EQ
)
4654 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4655 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4658 /* If we are comparing against zero and the expression being tested has
4659 only a single bit that might be nonzero, that is its value when it is
4660 not equal to zero. Similarly if it is known to be -1 or 0. */
4662 if (true_code
== EQ
&& true_val
== const0_rtx
4663 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4664 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4665 else if (true_code
== EQ
&& true_val
== const0_rtx
4666 && (num_sign_bit_copies (from
, GET_MODE (from
))
4667 == GET_MODE_BITSIZE (GET_MODE (from
))))
4668 false_code
= EQ
, false_val
= constm1_rtx
;
4670 /* Now simplify an arm if we know the value of the register in the
4671 branch and it is used in the arm. Be careful due to the potential
4672 of locally-shared RTL. */
4674 if (reg_mentioned_p (from
, true_rtx
))
4675 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4677 pc_rtx
, pc_rtx
, 0, 0);
4678 if (reg_mentioned_p (from
, false_rtx
))
4679 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4681 pc_rtx
, pc_rtx
, 0, 0);
4683 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4684 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4686 true_rtx
= XEXP (x
, 1);
4687 false_rtx
= XEXP (x
, 2);
4688 true_code
= GET_CODE (cond
);
4691 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4692 reversed, do so to avoid needing two sets of patterns for
4693 subtract-and-branch insns. Similarly if we have a constant in the true
4694 arm, the false arm is the same as the first operand of the comparison, or
4695 the false arm is more complicated than the true arm. */
4698 && combine_reversed_comparison_code (cond
) != UNKNOWN
4699 && (true_rtx
== pc_rtx
4700 || (CONSTANT_P (true_rtx
)
4701 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4702 || true_rtx
== const0_rtx
4703 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4704 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4705 || (GET_CODE (true_rtx
) == SUBREG
4706 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4707 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4708 || reg_mentioned_p (true_rtx
, false_rtx
)
4709 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4711 true_code
= reversed_comparison_code (cond
, NULL
);
4713 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4716 SUBST (XEXP (x
, 1), false_rtx
);
4717 SUBST (XEXP (x
, 2), true_rtx
);
4719 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4722 /* It is possible that the conditional has been simplified out. */
4723 true_code
= GET_CODE (cond
);
4724 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4727 /* If the two arms are identical, we don't need the comparison. */
4729 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4732 /* Convert a == b ? b : a to "a". */
4733 if (true_code
== EQ
&& ! side_effects_p (cond
)
4734 && !HONOR_NANS (mode
)
4735 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4736 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4738 else if (true_code
== NE
&& ! side_effects_p (cond
)
4739 && !HONOR_NANS (mode
)
4740 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4741 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4744 /* Look for cases where we have (abs x) or (neg (abs X)). */
4746 if (GET_MODE_CLASS (mode
) == MODE_INT
4747 && GET_CODE (false_rtx
) == NEG
4748 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4750 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4751 && ! side_effects_p (true_rtx
))
4756 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4760 simplify_gen_unary (NEG
, mode
,
4761 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4767 /* Look for MIN or MAX. */
4769 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4771 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4772 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4773 && ! side_effects_p (cond
))
4778 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4781 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4784 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4787 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4792 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4793 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4794 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4795 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4796 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4797 neither 1 or -1, but it isn't worth checking for. */
4799 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4801 && GET_MODE_CLASS (mode
) == MODE_INT
4802 && ! side_effects_p (x
))
4804 rtx t
= make_compound_operation (true_rtx
, SET
);
4805 rtx f
= make_compound_operation (false_rtx
, SET
);
4806 rtx cond_op0
= XEXP (cond
, 0);
4807 rtx cond_op1
= XEXP (cond
, 1);
4808 enum rtx_code op
= NIL
, extend_op
= NIL
;
4809 enum machine_mode m
= mode
;
4810 rtx z
= 0, c1
= NULL_RTX
;
4812 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4813 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4814 || GET_CODE (t
) == ASHIFT
4815 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4816 && rtx_equal_p (XEXP (t
, 0), f
))
4817 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4819 /* If an identity-zero op is commutative, check whether there
4820 would be a match if we swapped the operands. */
4821 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4822 || GET_CODE (t
) == XOR
)
4823 && rtx_equal_p (XEXP (t
, 1), f
))
4824 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4825 else if (GET_CODE (t
) == SIGN_EXTEND
4826 && (GET_CODE (XEXP (t
, 0)) == PLUS
4827 || GET_CODE (XEXP (t
, 0)) == MINUS
4828 || GET_CODE (XEXP (t
, 0)) == IOR
4829 || GET_CODE (XEXP (t
, 0)) == XOR
4830 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4831 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4832 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4833 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4834 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4835 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4836 && (num_sign_bit_copies (f
, GET_MODE (f
))
4838 (GET_MODE_BITSIZE (mode
)
4839 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4841 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4842 extend_op
= SIGN_EXTEND
;
4843 m
= GET_MODE (XEXP (t
, 0));
4845 else if (GET_CODE (t
) == SIGN_EXTEND
4846 && (GET_CODE (XEXP (t
, 0)) == PLUS
4847 || GET_CODE (XEXP (t
, 0)) == IOR
4848 || GET_CODE (XEXP (t
, 0)) == XOR
)
4849 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4850 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4851 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4852 && (num_sign_bit_copies (f
, GET_MODE (f
))
4854 (GET_MODE_BITSIZE (mode
)
4855 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4857 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4858 extend_op
= SIGN_EXTEND
;
4859 m
= GET_MODE (XEXP (t
, 0));
4861 else if (GET_CODE (t
) == ZERO_EXTEND
4862 && (GET_CODE (XEXP (t
, 0)) == PLUS
4863 || GET_CODE (XEXP (t
, 0)) == MINUS
4864 || GET_CODE (XEXP (t
, 0)) == IOR
4865 || GET_CODE (XEXP (t
, 0)) == XOR
4866 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4867 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4868 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4869 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4870 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4871 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4872 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4873 && ((nonzero_bits (f
, GET_MODE (f
))
4874 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4877 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4878 extend_op
= ZERO_EXTEND
;
4879 m
= GET_MODE (XEXP (t
, 0));
4881 else if (GET_CODE (t
) == ZERO_EXTEND
4882 && (GET_CODE (XEXP (t
, 0)) == PLUS
4883 || GET_CODE (XEXP (t
, 0)) == IOR
4884 || GET_CODE (XEXP (t
, 0)) == XOR
)
4885 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4886 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4887 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4888 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4889 && ((nonzero_bits (f
, GET_MODE (f
))
4890 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4893 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4894 extend_op
= ZERO_EXTEND
;
4895 m
= GET_MODE (XEXP (t
, 0));
4900 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4901 pc_rtx
, pc_rtx
, 0, 0);
4902 temp
= gen_binary (MULT
, m
, temp
,
4903 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4904 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4905 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
4907 if (extend_op
!= NIL
)
4908 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4914 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4915 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4916 negation of a single bit, we can convert this operation to a shift. We
4917 can actually do this more generally, but it doesn't seem worth it. */
4919 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4920 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4921 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4922 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4923 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4924 == GET_MODE_BITSIZE (mode
))
4925 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4927 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4928 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
4930 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4931 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4932 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4933 && GET_MODE (XEXP (cond
, 0)) == mode
4934 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4935 == nonzero_bits (XEXP (cond
, 0), mode
)
4936 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4937 return XEXP (cond
, 0);
4942 /* Simplify X, a SET expression. Return the new expression. */
4945 simplify_set (rtx x
)
4947 rtx src
= SET_SRC (x
);
4948 rtx dest
= SET_DEST (x
);
4949 enum machine_mode mode
4950 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4954 /* (set (pc) (return)) gets written as (return). */
4955 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4958 /* Now that we know for sure which bits of SRC we are using, see if we can
4959 simplify the expression for the object knowing that we only need the
4962 if (GET_MODE_CLASS (mode
) == MODE_INT
4963 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4965 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4966 SUBST (SET_SRC (x
), src
);
4969 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4970 the comparison result and try to simplify it unless we already have used
4971 undobuf.other_insn. */
4972 if ((GET_MODE_CLASS (mode
) == MODE_CC
4973 || GET_CODE (src
) == COMPARE
4975 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4976 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4977 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4978 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4980 enum rtx_code old_code
= GET_CODE (*cc_use
);
4981 enum rtx_code new_code
;
4983 int other_changed
= 0;
4984 enum machine_mode compare_mode
= GET_MODE (dest
);
4985 enum machine_mode tmp_mode
;
4987 if (GET_CODE (src
) == COMPARE
)
4988 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4990 op0
= src
, op1
= const0_rtx
;
4992 /* Check whether the comparison is known at compile time. */
4993 if (GET_MODE (op0
) != VOIDmode
)
4994 tmp_mode
= GET_MODE (op0
);
4995 else if (GET_MODE (op1
) != VOIDmode
)
4996 tmp_mode
= GET_MODE (op1
);
4998 tmp_mode
= compare_mode
;
4999 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5000 if (tmp
!= NULL_RTX
)
5002 rtx pat
= PATTERN (other_insn
);
5003 undobuf
.other_insn
= other_insn
;
5004 SUBST (*cc_use
, tmp
);
5006 /* Attempt to simplify CC user. */
5007 if (GET_CODE (pat
) == SET
)
5009 rtx
new = simplify_rtx (SET_SRC (pat
));
5010 if (new != NULL_RTX
)
5011 SUBST (SET_SRC (pat
), new);
5014 /* Convert X into a no-op move. */
5015 SUBST (SET_DEST (x
), pc_rtx
);
5016 SUBST (SET_SRC (x
), pc_rtx
);
5020 /* Simplify our comparison, if possible. */
5021 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5023 #ifdef SELECT_CC_MODE
5024 /* If this machine has CC modes other than CCmode, check to see if we
5025 need to use a different CC mode here. */
5026 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5029 /* If the mode changed, we have to change SET_DEST, the mode in the
5030 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5031 a hard register, just build new versions with the proper mode. If it
5032 is a pseudo, we lose unless it is only time we set the pseudo, in
5033 which case we can safely change its mode. */
5034 if (compare_mode
!= GET_MODE (dest
))
5036 unsigned int regno
= REGNO (dest
);
5037 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5039 if (regno
< FIRST_PSEUDO_REGISTER
5040 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5042 if (regno
>= FIRST_PSEUDO_REGISTER
)
5043 SUBST (regno_reg_rtx
[regno
], new_dest
);
5045 SUBST (SET_DEST (x
), new_dest
);
5046 SUBST (XEXP (*cc_use
, 0), new_dest
);
5053 #endif /* SELECT_CC_MODE */
5055 /* If the code changed, we have to build a new comparison in
5056 undobuf.other_insn. */
5057 if (new_code
!= old_code
)
5059 int other_changed_previously
= other_changed
;
5060 unsigned HOST_WIDE_INT mask
;
5062 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5066 /* If the only change we made was to change an EQ into an NE or
5067 vice versa, OP0 has only one bit that might be nonzero, and OP1
5068 is zero, check if changing the user of the condition code will
5069 produce a valid insn. If it won't, we can keep the original code
5070 in that insn by surrounding our operation with an XOR. */
5072 if (((old_code
== NE
&& new_code
== EQ
)
5073 || (old_code
== EQ
&& new_code
== NE
))
5074 && ! other_changed_previously
&& op1
== const0_rtx
5075 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5076 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5078 rtx pat
= PATTERN (other_insn
), note
= 0;
5080 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5081 && ! check_asm_operands (pat
)))
5083 PUT_CODE (*cc_use
, old_code
);
5086 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5092 undobuf
.other_insn
= other_insn
;
5095 /* If we are now comparing against zero, change our source if
5096 needed. If we do not use cc0, we always have a COMPARE. */
5097 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5099 SUBST (SET_SRC (x
), op0
);
5105 /* Otherwise, if we didn't previously have a COMPARE in the
5106 correct mode, we need one. */
5107 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5109 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5114 /* Otherwise, update the COMPARE if needed. */
5115 SUBST (XEXP (src
, 0), op0
);
5116 SUBST (XEXP (src
, 1), op1
);
5121 /* Get SET_SRC in a form where we have placed back any
5122 compound expressions. Then do the checks below. */
5123 src
= make_compound_operation (src
, SET
);
5124 SUBST (SET_SRC (x
), src
);
5127 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5128 and X being a REG or (subreg (reg)), we may be able to convert this to
5129 (set (subreg:m2 x) (op)).
5131 We can always do this if M1 is narrower than M2 because that means that
5132 we only care about the low bits of the result.
5134 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5135 perform a narrower operation than requested since the high-order bits will
5136 be undefined. On machine where it is defined, this transformation is safe
5137 as long as M1 and M2 have the same number of words. */
5139 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5140 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5141 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5143 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5144 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5145 #ifndef WORD_REGISTER_OPERATIONS
5146 && (GET_MODE_SIZE (GET_MODE (src
))
5147 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5149 #ifdef CANNOT_CHANGE_MODE_CLASS
5150 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5151 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5152 GET_MODE (SUBREG_REG (src
)),
5155 && (GET_CODE (dest
) == REG
5156 || (GET_CODE (dest
) == SUBREG
5157 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5159 SUBST (SET_DEST (x
),
5160 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5162 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5164 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5168 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5171 && GET_CODE (src
) == SUBREG
5172 && subreg_lowpart_p (src
)
5173 && (GET_MODE_BITSIZE (GET_MODE (src
))
5174 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5176 rtx inner
= SUBREG_REG (src
);
5177 enum machine_mode inner_mode
= GET_MODE (inner
);
5179 /* Here we make sure that we don't have a sign bit on. */
5180 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5181 && (nonzero_bits (inner
, inner_mode
)
5182 < ((unsigned HOST_WIDE_INT
) 1
5183 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5185 SUBST (SET_SRC (x
), inner
);
5191 #ifdef LOAD_EXTEND_OP
5192 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5193 would require a paradoxical subreg. Replace the subreg with a
5194 zero_extend to avoid the reload that would otherwise be required. */
5196 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5197 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5198 && SUBREG_BYTE (src
) == 0
5199 && (GET_MODE_SIZE (GET_MODE (src
))
5200 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5201 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5204 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5205 GET_MODE (src
), SUBREG_REG (src
)));
5211 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5212 are comparing an item known to be 0 or -1 against 0, use a logical
5213 operation instead. Check for one of the arms being an IOR of the other
5214 arm with some value. We compute three terms to be IOR'ed together. In
5215 practice, at most two will be nonzero. Then we do the IOR's. */
5217 if (GET_CODE (dest
) != PC
5218 && GET_CODE (src
) == IF_THEN_ELSE
5219 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5220 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5221 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5222 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5223 #ifdef HAVE_conditional_move
5224 && ! can_conditionally_move_p (GET_MODE (src
))
5226 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5227 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5228 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5229 && ! side_effects_p (src
))
5231 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5232 ? XEXP (src
, 1) : XEXP (src
, 2));
5233 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5234 ? XEXP (src
, 2) : XEXP (src
, 1));
5235 rtx term1
= const0_rtx
, term2
, term3
;
5237 if (GET_CODE (true_rtx
) == IOR
5238 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5239 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5240 else if (GET_CODE (true_rtx
) == IOR
5241 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5242 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5243 else if (GET_CODE (false_rtx
) == IOR
5244 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5245 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5246 else if (GET_CODE (false_rtx
) == IOR
5247 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5248 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5250 term2
= gen_binary (AND
, GET_MODE (src
),
5251 XEXP (XEXP (src
, 0), 0), true_rtx
);
5252 term3
= gen_binary (AND
, GET_MODE (src
),
5253 simplify_gen_unary (NOT
, GET_MODE (src
),
5254 XEXP (XEXP (src
, 0), 0),
5259 gen_binary (IOR
, GET_MODE (src
),
5260 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5266 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5267 whole thing fail. */
5268 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5270 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5273 /* Convert this into a field assignment operation, if possible. */
5274 return make_field_assignment (x
);
5277 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5278 result. LAST is nonzero if this is the last retry. */
5281 simplify_logical (rtx x
, int last
)
5283 enum machine_mode mode
= GET_MODE (x
);
5284 rtx op0
= XEXP (x
, 0);
5285 rtx op1
= XEXP (x
, 1);
5288 switch (GET_CODE (x
))
5291 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5292 insn (and may simplify more). */
5293 if (GET_CODE (op0
) == XOR
5294 && rtx_equal_p (XEXP (op0
, 0), op1
)
5295 && ! side_effects_p (op1
))
5296 x
= gen_binary (AND
, mode
,
5297 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5300 if (GET_CODE (op0
) == XOR
5301 && rtx_equal_p (XEXP (op0
, 1), op1
)
5302 && ! side_effects_p (op1
))
5303 x
= gen_binary (AND
, mode
,
5304 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5307 /* Similarly for (~(A ^ B)) & A. */
5308 if (GET_CODE (op0
) == NOT
5309 && GET_CODE (XEXP (op0
, 0)) == XOR
5310 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5311 && ! side_effects_p (op1
))
5312 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5314 if (GET_CODE (op0
) == NOT
5315 && GET_CODE (XEXP (op0
, 0)) == XOR
5316 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5317 && ! side_effects_p (op1
))
5318 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5320 /* We can call simplify_and_const_int only if we don't lose
5321 any (sign) bits when converting INTVAL (op1) to
5322 "unsigned HOST_WIDE_INT". */
5323 if (GET_CODE (op1
) == CONST_INT
5324 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5325 || INTVAL (op1
) > 0))
5327 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5329 /* If we have (ior (and (X C1) C2)) and the next restart would be
5330 the last, simplify this by making C1 as small as possible
5333 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5334 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5335 && GET_CODE (op1
) == CONST_INT
)
5336 return gen_binary (IOR
, mode
,
5337 gen_binary (AND
, mode
, XEXP (op0
, 0),
5338 GEN_INT (INTVAL (XEXP (op0
, 1))
5339 & ~INTVAL (op1
))), op1
);
5341 if (GET_CODE (x
) != AND
)
5344 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5345 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5346 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5349 /* Convert (A | B) & A to A. */
5350 if (GET_CODE (op0
) == IOR
5351 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5352 || rtx_equal_p (XEXP (op0
, 1), op1
))
5353 && ! side_effects_p (XEXP (op0
, 0))
5354 && ! side_effects_p (XEXP (op0
, 1)))
5357 /* In the following group of tests (and those in case IOR below),
5358 we start with some combination of logical operations and apply
5359 the distributive law followed by the inverse distributive law.
5360 Most of the time, this results in no change. However, if some of
5361 the operands are the same or inverses of each other, simplifications
5364 For example, (and (ior A B) (not B)) can occur as the result of
5365 expanding a bit field assignment. When we apply the distributive
5366 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5367 which then simplifies to (and (A (not B))).
5369 If we have (and (ior A B) C), apply the distributive law and then
5370 the inverse distributive law to see if things simplify. */
5372 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5374 x
= apply_distributive_law
5375 (gen_binary (GET_CODE (op0
), mode
,
5376 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5377 gen_binary (AND
, mode
, XEXP (op0
, 1),
5379 if (GET_CODE (x
) != AND
)
5383 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5384 return apply_distributive_law
5385 (gen_binary (GET_CODE (op1
), mode
,
5386 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5387 gen_binary (AND
, mode
, XEXP (op1
, 1),
5390 /* Similarly, taking advantage of the fact that
5391 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5393 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5394 return apply_distributive_law
5395 (gen_binary (XOR
, mode
,
5396 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5397 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5400 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5401 return apply_distributive_law
5402 (gen_binary (XOR
, mode
,
5403 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5404 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5408 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5409 if (GET_CODE (op1
) == CONST_INT
5410 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5411 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5414 /* Convert (A & B) | A to A. */
5415 if (GET_CODE (op0
) == AND
5416 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5417 || rtx_equal_p (XEXP (op0
, 1), op1
))
5418 && ! side_effects_p (XEXP (op0
, 0))
5419 && ! side_effects_p (XEXP (op0
, 1)))
5422 /* If we have (ior (and A B) C), apply the distributive law and then
5423 the inverse distributive law to see if things simplify. */
5425 if (GET_CODE (op0
) == AND
)
5427 x
= apply_distributive_law
5428 (gen_binary (AND
, mode
,
5429 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5430 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5433 if (GET_CODE (x
) != IOR
)
5437 if (GET_CODE (op1
) == AND
)
5439 x
= apply_distributive_law
5440 (gen_binary (AND
, mode
,
5441 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5442 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5445 if (GET_CODE (x
) != IOR
)
5449 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5450 mode size to (rotate A CX). */
5452 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5453 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5454 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5455 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5456 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5457 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5458 == GET_MODE_BITSIZE (mode
)))
5459 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5460 (GET_CODE (op0
) == ASHIFT
5461 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5463 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5464 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5465 does not affect any of the bits in OP1, it can really be done
5466 as a PLUS and we can associate. We do this by seeing if OP1
5467 can be safely shifted left C bits. */
5468 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5469 && GET_CODE (XEXP (op0
, 0)) == PLUS
5470 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5471 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5472 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5474 int count
= INTVAL (XEXP (op0
, 1));
5475 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5477 if (mask
>> count
== INTVAL (op1
)
5478 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5480 SUBST (XEXP (XEXP (op0
, 0), 1),
5481 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5488 /* If we are XORing two things that have no bits in common,
5489 convert them into an IOR. This helps to detect rotation encoded
5490 using those methods and possibly other simplifications. */
5492 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5493 && (nonzero_bits (op0
, mode
)
5494 & nonzero_bits (op1
, mode
)) == 0)
5495 return (gen_binary (IOR
, mode
, op0
, op1
));
5497 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5498 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5501 int num_negated
= 0;
5503 if (GET_CODE (op0
) == NOT
)
5504 num_negated
++, op0
= XEXP (op0
, 0);
5505 if (GET_CODE (op1
) == NOT
)
5506 num_negated
++, op1
= XEXP (op1
, 0);
5508 if (num_negated
== 2)
5510 SUBST (XEXP (x
, 0), op0
);
5511 SUBST (XEXP (x
, 1), op1
);
5513 else if (num_negated
== 1)
5515 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5519 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5520 correspond to a machine insn or result in further simplifications
5521 if B is a constant. */
5523 if (GET_CODE (op0
) == AND
5524 && rtx_equal_p (XEXP (op0
, 1), op1
)
5525 && ! side_effects_p (op1
))
5526 return gen_binary (AND
, mode
,
5527 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5530 else if (GET_CODE (op0
) == AND
5531 && rtx_equal_p (XEXP (op0
, 0), op1
)
5532 && ! side_effects_p (op1
))
5533 return gen_binary (AND
, mode
,
5534 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5537 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5538 comparison if STORE_FLAG_VALUE is 1. */
5539 if (STORE_FLAG_VALUE
== 1
5540 && op1
== const1_rtx
5541 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5542 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5546 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5547 is (lt foo (const_int 0)), so we can perform the above
5548 simplification if STORE_FLAG_VALUE is 1. */
5550 if (STORE_FLAG_VALUE
== 1
5551 && op1
== const1_rtx
5552 && GET_CODE (op0
) == LSHIFTRT
5553 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5554 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5555 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5557 /* (xor (comparison foo bar) (const_int sign-bit))
5558 when STORE_FLAG_VALUE is the sign bit. */
5559 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5560 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5561 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5562 && op1
== const_true_rtx
5563 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5564 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5577 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5578 operations" because they can be replaced with two more basic operations.
5579 ZERO_EXTEND is also considered "compound" because it can be replaced with
5580 an AND operation, which is simpler, though only one operation.
5582 The function expand_compound_operation is called with an rtx expression
5583 and will convert it to the appropriate shifts and AND operations,
5584 simplifying at each stage.
5586 The function make_compound_operation is called to convert an expression
5587 consisting of shifts and ANDs into the equivalent compound expression.
5588 It is the inverse of this function, loosely speaking. */
5591 expand_compound_operation (rtx x
)
5593 unsigned HOST_WIDE_INT pos
= 0, len
;
5595 unsigned int modewidth
;
5598 switch (GET_CODE (x
))
5603 /* We can't necessarily use a const_int for a multiword mode;
5604 it depends on implicitly extending the value.
5605 Since we don't know the right way to extend it,
5606 we can't tell whether the implicit way is right.
5608 Even for a mode that is no wider than a const_int,
5609 we can't win, because we need to sign extend one of its bits through
5610 the rest of it, and we don't know which bit. */
5611 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5614 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5615 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5616 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5617 reloaded. If not for that, MEM's would very rarely be safe.
5619 Reject MODEs bigger than a word, because we might not be able
5620 to reference a two-register group starting with an arbitrary register
5621 (and currently gen_lowpart might crash for a SUBREG). */
5623 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5626 /* Reject MODEs that aren't scalar integers because turning vector
5627 or complex modes into shifts causes problems. */
5629 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5632 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5633 /* If the inner object has VOIDmode (the only way this can happen
5634 is if it is an ASM_OPERANDS), we can't do anything since we don't
5635 know how much masking to do. */
5644 /* If the operand is a CLOBBER, just return it. */
5645 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5648 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5649 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5650 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5653 /* Reject MODEs that aren't scalar integers because turning vector
5654 or complex modes into shifts causes problems. */
5656 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5659 len
= INTVAL (XEXP (x
, 1));
5660 pos
= INTVAL (XEXP (x
, 2));
5662 /* If this goes outside the object being extracted, replace the object
5663 with a (use (mem ...)) construct that only combine understands
5664 and is used only for this purpose. */
5665 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5666 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5668 if (BITS_BIG_ENDIAN
)
5669 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5676 /* Convert sign extension to zero extension, if we know that the high
5677 bit is not set, as this is easier to optimize. It will be converted
5678 back to cheaper alternative in make_extraction. */
5679 if (GET_CODE (x
) == SIGN_EXTEND
5680 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5681 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5682 & ~(((unsigned HOST_WIDE_INT
)
5683 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5687 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5688 rtx temp2
= expand_compound_operation (temp
);
5690 /* Make sure this is a profitable operation. */
5691 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5693 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5699 /* We can optimize some special cases of ZERO_EXTEND. */
5700 if (GET_CODE (x
) == ZERO_EXTEND
)
5702 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5703 know that the last value didn't have any inappropriate bits
5705 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5706 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5707 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5708 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5709 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5710 return XEXP (XEXP (x
, 0), 0);
5712 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5713 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5714 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5715 && subreg_lowpart_p (XEXP (x
, 0))
5716 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5717 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5718 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5719 return SUBREG_REG (XEXP (x
, 0));
5721 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5722 is a comparison and STORE_FLAG_VALUE permits. This is like
5723 the first case, but it works even when GET_MODE (x) is larger
5724 than HOST_WIDE_INT. */
5725 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5726 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5727 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5728 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5729 <= HOST_BITS_PER_WIDE_INT
)
5730 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5731 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5732 return XEXP (XEXP (x
, 0), 0);
5734 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5735 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5736 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5737 && subreg_lowpart_p (XEXP (x
, 0))
5738 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5739 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5740 <= HOST_BITS_PER_WIDE_INT
)
5741 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5742 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5743 return SUBREG_REG (XEXP (x
, 0));
5747 /* If we reach here, we want to return a pair of shifts. The inner
5748 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5749 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5750 logical depending on the value of UNSIGNEDP.
5752 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5753 converted into an AND of a shift.
5755 We must check for the case where the left shift would have a negative
5756 count. This can happen in a case like (x >> 31) & 255 on machines
5757 that can't shift by a constant. On those machines, we would first
5758 combine the shift with the AND to produce a variable-position
5759 extraction. Then the constant of 31 would be substituted in to produce
5760 a such a position. */
5762 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5763 if (modewidth
+ len
>= pos
)
5764 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5766 simplify_shift_const (NULL_RTX
, ASHIFT
,
5769 modewidth
- pos
- len
),
5772 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5773 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5774 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5777 ((HOST_WIDE_INT
) 1 << len
) - 1);
5779 /* Any other cases we can't handle. */
5782 /* If we couldn't do this for some reason, return the original
5784 if (GET_CODE (tem
) == CLOBBER
)
5790 /* X is a SET which contains an assignment of one object into
5791 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5792 or certain SUBREGS). If possible, convert it into a series of
5795 We half-heartedly support variable positions, but do not at all
5796 support variable lengths. */
5799 expand_field_assignment (rtx x
)
5802 rtx pos
; /* Always counts from low bit. */
5805 enum machine_mode compute_mode
;
5807 /* Loop until we find something we can't simplify. */
5810 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5811 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5813 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5814 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5815 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5817 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5818 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5820 inner
= XEXP (SET_DEST (x
), 0);
5821 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5822 pos
= XEXP (SET_DEST (x
), 2);
5824 /* If the position is constant and spans the width of INNER,
5825 surround INNER with a USE to indicate this. */
5826 if (GET_CODE (pos
) == CONST_INT
5827 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5828 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5830 if (BITS_BIG_ENDIAN
)
5832 if (GET_CODE (pos
) == CONST_INT
)
5833 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5835 else if (GET_CODE (pos
) == MINUS
5836 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5837 && (INTVAL (XEXP (pos
, 1))
5838 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5839 /* If position is ADJUST - X, new position is X. */
5840 pos
= XEXP (pos
, 0);
5842 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5843 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5849 /* A SUBREG between two modes that occupy the same numbers of words
5850 can be done by moving the SUBREG to the source. */
5851 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5852 /* We need SUBREGs to compute nonzero_bits properly. */
5853 && nonzero_sign_valid
5854 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5855 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5856 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5857 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5859 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5861 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5868 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5869 inner
= SUBREG_REG (inner
);
5871 compute_mode
= GET_MODE (inner
);
5873 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5874 if (! SCALAR_INT_MODE_P (compute_mode
))
5876 enum machine_mode imode
;
5878 /* Don't do anything for vector or complex integral types. */
5879 if (! FLOAT_MODE_P (compute_mode
))
5882 /* Try to find an integral mode to pun with. */
5883 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5884 if (imode
== BLKmode
)
5887 compute_mode
= imode
;
5888 inner
= gen_lowpart (imode
, inner
);
5891 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5892 if (len
< HOST_BITS_PER_WIDE_INT
)
5893 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5897 /* Now compute the equivalent expression. Make a copy of INNER
5898 for the SET_DEST in case it is a MEM into which we will substitute;
5899 we don't want shared RTL in that case. */
5901 (VOIDmode
, copy_rtx (inner
),
5902 gen_binary (IOR
, compute_mode
,
5903 gen_binary (AND
, compute_mode
,
5904 simplify_gen_unary (NOT
, compute_mode
,
5910 gen_binary (ASHIFT
, compute_mode
,
5911 gen_binary (AND
, compute_mode
,
5913 (compute_mode
, SET_SRC (x
)),
5921 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5922 it is an RTX that represents a variable starting position; otherwise,
5923 POS is the (constant) starting bit position (counted from the LSB).
5925 INNER may be a USE. This will occur when we started with a bitfield
5926 that went outside the boundary of the object in memory, which is
5927 allowed on most machines. To isolate this case, we produce a USE
5928 whose mode is wide enough and surround the MEM with it. The only
5929 code that understands the USE is this routine. If it is not removed,
5930 it will cause the resulting insn not to match.
5932 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5935 IN_DEST is nonzero if this is a reference in the destination of a
5936 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5937 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5940 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5941 ZERO_EXTRACT should be built even for bits starting at bit 0.
5943 MODE is the desired mode of the result (if IN_DEST == 0).
5945 The result is an RTX for the extraction or NULL_RTX if the target
5949 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5950 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5951 int in_dest
, int in_compare
)
5953 /* This mode describes the size of the storage area
5954 to fetch the overall value from. Within that, we
5955 ignore the POS lowest bits, etc. */
5956 enum machine_mode is_mode
= GET_MODE (inner
);
5957 enum machine_mode inner_mode
;
5958 enum machine_mode wanted_inner_mode
= byte_mode
;
5959 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5960 enum machine_mode pos_mode
= word_mode
;
5961 enum machine_mode extraction_mode
= word_mode
;
5962 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5965 rtx orig_pos_rtx
= pos_rtx
;
5966 HOST_WIDE_INT orig_pos
;
5968 /* Get some information about INNER and get the innermost object. */
5969 if (GET_CODE (inner
) == USE
)
5970 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5971 /* We don't need to adjust the position because we set up the USE
5972 to pretend that it was a full-word object. */
5973 spans_byte
= 1, inner
= XEXP (inner
, 0);
5974 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5976 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5977 consider just the QI as the memory to extract from.
5978 The subreg adds or removes high bits; its mode is
5979 irrelevant to the meaning of this extraction,
5980 since POS and LEN count from the lsb. */
5981 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5982 is_mode
= GET_MODE (SUBREG_REG (inner
));
5983 inner
= SUBREG_REG (inner
);
5985 else if (GET_CODE (inner
) == ASHIFT
5986 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5987 && pos_rtx
== 0 && pos
== 0
5988 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5990 /* We're extracting the least significant bits of an rtx
5991 (ashift X (const_int C)), where LEN > C. Extract the
5992 least significant (LEN - C) bits of X, giving an rtx
5993 whose mode is MODE, then shift it left C times. */
5994 new = make_extraction (mode
, XEXP (inner
, 0),
5995 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5996 unsignedp
, in_dest
, in_compare
);
5998 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6001 inner_mode
= GET_MODE (inner
);
6003 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6004 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6006 /* See if this can be done without an extraction. We never can if the
6007 width of the field is not the same as that of some integer mode. For
6008 registers, we can only avoid the extraction if the position is at the
6009 low-order bit and this is either not in the destination or we have the
6010 appropriate STRICT_LOW_PART operation available.
6012 For MEM, we can avoid an extract if the field starts on an appropriate
6013 boundary and we can change the mode of the memory reference. However,
6014 we cannot directly access the MEM if we have a USE and the underlying
6015 MEM is not TMODE. This combination means that MEM was being used in a
6016 context where bits outside its mode were being referenced; that is only
6017 valid in bit-field insns. */
6019 if (tmode
!= BLKmode
6020 && ! (spans_byte
&& inner_mode
!= tmode
)
6021 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6022 && GET_CODE (inner
) != MEM
6024 || (GET_CODE (inner
) == REG
6025 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6026 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6028 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6029 : BITS_PER_UNIT
)) == 0
6030 /* We can't do this if we are widening INNER_MODE (it
6031 may not be aligned, for one thing). */
6032 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6033 && (inner_mode
== tmode
6034 || (! mode_dependent_address_p (XEXP (inner
, 0))
6035 && ! MEM_VOLATILE_P (inner
))))))
6037 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6038 field. If the original and current mode are the same, we need not
6039 adjust the offset. Otherwise, we do if bytes big endian.
6041 If INNER is not a MEM, get a piece consisting of just the field
6042 of interest (in this case POS % BITS_PER_WORD must be 0). */
6044 if (GET_CODE (inner
) == MEM
)
6046 HOST_WIDE_INT offset
;
6048 /* POS counts from lsb, but make OFFSET count in memory order. */
6049 if (BYTES_BIG_ENDIAN
)
6050 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6052 offset
= pos
/ BITS_PER_UNIT
;
6054 new = adjust_address_nv (inner
, tmode
, offset
);
6056 else if (GET_CODE (inner
) == REG
)
6058 if (tmode
!= inner_mode
)
6060 /* We can't call gen_lowpart in a DEST since we
6061 always want a SUBREG (see below) and it would sometimes
6062 return a new hard register. */
6065 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6067 if (WORDS_BIG_ENDIAN
6068 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6069 final_word
= ((GET_MODE_SIZE (inner_mode
)
6070 - GET_MODE_SIZE (tmode
))
6071 / UNITS_PER_WORD
) - final_word
;
6073 final_word
*= UNITS_PER_WORD
;
6074 if (BYTES_BIG_ENDIAN
&&
6075 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6076 final_word
+= (GET_MODE_SIZE (inner_mode
)
6077 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6079 /* Avoid creating invalid subregs, for example when
6080 simplifying (x>>32)&255. */
6081 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6084 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6087 new = gen_lowpart (tmode
, inner
);
6093 new = force_to_mode (inner
, tmode
,
6094 len
>= HOST_BITS_PER_WIDE_INT
6095 ? ~(unsigned HOST_WIDE_INT
) 0
6096 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6099 /* If this extraction is going into the destination of a SET,
6100 make a STRICT_LOW_PART unless we made a MEM. */
6103 return (GET_CODE (new) == MEM
? new
6104 : (GET_CODE (new) != SUBREG
6105 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6106 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6111 if (GET_CODE (new) == CONST_INT
)
6112 return gen_int_mode (INTVAL (new), mode
);
6114 /* If we know that no extraneous bits are set, and that the high
6115 bit is not set, convert the extraction to the cheaper of
6116 sign and zero extension, that are equivalent in these cases. */
6117 if (flag_expensive_optimizations
6118 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6119 && ((nonzero_bits (new, tmode
)
6120 & ~(((unsigned HOST_WIDE_INT
)
6121 GET_MODE_MASK (tmode
))
6125 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6126 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6128 /* Prefer ZERO_EXTENSION, since it gives more information to
6130 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6135 /* Otherwise, sign- or zero-extend unless we already are in the
6138 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6142 /* Unless this is a COMPARE or we have a funny memory reference,
6143 don't do anything with zero-extending field extracts starting at
6144 the low-order bit since they are simple AND operations. */
6145 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6146 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6149 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6150 we would be spanning bytes or if the position is not a constant and the
6151 length is not 1. In all other cases, we would only be going outside
6152 our object in cases when an original shift would have been
6154 if (! spans_byte
&& GET_CODE (inner
) == MEM
6155 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6156 || (pos_rtx
!= 0 && len
!= 1)))
6159 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6160 and the mode for the result. */
6161 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6163 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6164 pos_mode
= mode_for_extraction (EP_insv
, 2);
6165 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6168 if (! in_dest
&& unsignedp
6169 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6171 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6172 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6173 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6176 if (! in_dest
&& ! unsignedp
6177 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6179 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6180 pos_mode
= mode_for_extraction (EP_extv
, 3);
6181 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6184 /* Never narrow an object, since that might not be safe. */
6186 if (mode
!= VOIDmode
6187 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6188 extraction_mode
= mode
;
6190 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6191 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6192 pos_mode
= GET_MODE (pos_rtx
);
6194 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6195 if we have to change the mode of memory and cannot, the desired mode is
6197 if (GET_CODE (inner
) != MEM
)
6198 wanted_inner_mode
= wanted_inner_reg_mode
;
6199 else if (inner_mode
!= wanted_inner_mode
6200 && (mode_dependent_address_p (XEXP (inner
, 0))
6201 || MEM_VOLATILE_P (inner
)))
6202 wanted_inner_mode
= extraction_mode
;
6206 if (BITS_BIG_ENDIAN
)
6208 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6209 BITS_BIG_ENDIAN style. If position is constant, compute new
6210 position. Otherwise, build subtraction.
6211 Note that POS is relative to the mode of the original argument.
6212 If it's a MEM we need to recompute POS relative to that.
6213 However, if we're extracting from (or inserting into) a register,
6214 we want to recompute POS relative to wanted_inner_mode. */
6215 int width
= (GET_CODE (inner
) == MEM
6216 ? GET_MODE_BITSIZE (is_mode
)
6217 : GET_MODE_BITSIZE (wanted_inner_mode
));
6220 pos
= width
- len
- pos
;
6223 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6224 /* POS may be less than 0 now, but we check for that below.
6225 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6228 /* If INNER has a wider mode, make it smaller. If this is a constant
6229 extract, try to adjust the byte to point to the byte containing
6231 if (wanted_inner_mode
!= VOIDmode
6232 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6233 && ((GET_CODE (inner
) == MEM
6234 && (inner_mode
== wanted_inner_mode
6235 || (! mode_dependent_address_p (XEXP (inner
, 0))
6236 && ! MEM_VOLATILE_P (inner
))))))
6240 /* The computations below will be correct if the machine is big
6241 endian in both bits and bytes or little endian in bits and bytes.
6242 If it is mixed, we must adjust. */
6244 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6245 adjust OFFSET to compensate. */
6246 if (BYTES_BIG_ENDIAN
6248 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6249 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6251 /* If this is a constant position, we can move to the desired byte. */
6254 offset
+= pos
/ BITS_PER_UNIT
;
6255 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6258 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6260 && is_mode
!= wanted_inner_mode
)
6261 offset
= (GET_MODE_SIZE (is_mode
)
6262 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6264 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6265 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6268 /* If INNER is not memory, we can always get it into the proper mode. If we
6269 are changing its mode, POS must be a constant and smaller than the size
6271 else if (GET_CODE (inner
) != MEM
)
6273 if (GET_MODE (inner
) != wanted_inner_mode
6275 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6278 inner
= force_to_mode (inner
, wanted_inner_mode
,
6280 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6281 ? ~(unsigned HOST_WIDE_INT
) 0
6282 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6287 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6288 have to zero extend. Otherwise, we can just use a SUBREG. */
6290 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6292 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6294 /* If we know that no extraneous bits are set, and that the high
6295 bit is not set, convert extraction to cheaper one - either
6296 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6298 if (flag_expensive_optimizations
6299 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6300 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6301 & ~(((unsigned HOST_WIDE_INT
)
6302 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6306 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6308 /* Prefer ZERO_EXTENSION, since it gives more information to
6310 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6315 else if (pos_rtx
!= 0
6316 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6317 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6319 /* Make POS_RTX unless we already have it and it is correct. If we don't
6320 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6322 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6323 pos_rtx
= orig_pos_rtx
;
6325 else if (pos_rtx
== 0)
6326 pos_rtx
= GEN_INT (pos
);
6328 /* Make the required operation. See if we can use existing rtx. */
6329 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6330 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6332 new = gen_lowpart (mode
, new);
6337 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6338 with any other operations in X. Return X without that shift if so. */
6341 extract_left_shift (rtx x
, int count
)
6343 enum rtx_code code
= GET_CODE (x
);
6344 enum machine_mode mode
= GET_MODE (x
);
6350 /* This is the shift itself. If it is wide enough, we will return
6351 either the value being shifted if the shift count is equal to
6352 COUNT or a shift for the difference. */
6353 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6354 && INTVAL (XEXP (x
, 1)) >= count
)
6355 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6356 INTVAL (XEXP (x
, 1)) - count
);
6360 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6361 return simplify_gen_unary (code
, mode
, tem
, mode
);
6365 case PLUS
: case IOR
: case XOR
: case AND
:
6366 /* If we can safely shift this constant and we find the inner shift,
6367 make a new operation. */
6368 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6369 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6370 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6371 return gen_binary (code
, mode
, tem
,
6372 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6383 /* Look at the expression rooted at X. Look for expressions
6384 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6385 Form these expressions.
6387 Return the new rtx, usually just X.
6389 Also, for machines like the VAX that don't have logical shift insns,
6390 try to convert logical to arithmetic shift operations in cases where
6391 they are equivalent. This undoes the canonicalizations to logical
6392 shifts done elsewhere.
6394 We try, as much as possible, to re-use rtl expressions to save memory.
6396 IN_CODE says what kind of expression we are processing. Normally, it is
6397 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6398 being kludges), it is MEM. When processing the arguments of a comparison
6399 or a COMPARE against zero, it is COMPARE. */
6402 make_compound_operation (rtx x
, enum rtx_code in_code
)
6404 enum rtx_code code
= GET_CODE (x
);
6405 enum machine_mode mode
= GET_MODE (x
);
6406 int mode_width
= GET_MODE_BITSIZE (mode
);
6408 enum rtx_code next_code
;
6414 /* Select the code to be used in recursive calls. Once we are inside an
6415 address, we stay there. If we have a comparison, set to COMPARE,
6416 but once inside, go back to our default of SET. */
6418 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6419 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6420 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6421 : in_code
== COMPARE
? SET
: in_code
);
6423 /* Process depending on the code of this operation. If NEW is set
6424 nonzero, it will be returned. */
6429 /* Convert shifts by constants into multiplications if inside
6431 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6432 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6433 && INTVAL (XEXP (x
, 1)) >= 0)
6435 new = make_compound_operation (XEXP (x
, 0), next_code
);
6436 new = gen_rtx_MULT (mode
, new,
6437 GEN_INT ((HOST_WIDE_INT
) 1
6438 << INTVAL (XEXP (x
, 1))));
6443 /* If the second operand is not a constant, we can't do anything
6445 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6448 /* If the constant is a power of two minus one and the first operand
6449 is a logical right shift, make an extraction. */
6450 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6451 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6453 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6454 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6455 0, in_code
== COMPARE
);
6458 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6459 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6460 && subreg_lowpart_p (XEXP (x
, 0))
6461 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6462 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6464 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6466 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6467 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6468 0, in_code
== COMPARE
);
6470 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6471 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6472 || GET_CODE (XEXP (x
, 0)) == IOR
)
6473 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6474 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6475 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6477 /* Apply the distributive law, and then try to make extractions. */
6478 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6479 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6481 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6483 new = make_compound_operation (new, in_code
);
6486 /* If we are have (and (rotate X C) M) and C is larger than the number
6487 of bits in M, this is an extraction. */
6489 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6490 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6491 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6492 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6494 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6495 new = make_extraction (mode
, new,
6496 (GET_MODE_BITSIZE (mode
)
6497 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6498 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6501 /* On machines without logical shifts, if the operand of the AND is
6502 a logical shift and our mask turns off all the propagated sign
6503 bits, we can replace the logical shift with an arithmetic shift. */
6504 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6505 && !have_insn_for (LSHIFTRT
, mode
)
6506 && have_insn_for (ASHIFTRT
, mode
)
6507 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6508 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6509 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6510 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6512 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6514 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6515 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6517 gen_rtx_ASHIFTRT (mode
,
6518 make_compound_operation
6519 (XEXP (XEXP (x
, 0), 0), next_code
),
6520 XEXP (XEXP (x
, 0), 1)));
6523 /* If the constant is one less than a power of two, this might be
6524 representable by an extraction even if no shift is present.
6525 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6526 we are in a COMPARE. */
6527 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6528 new = make_extraction (mode
,
6529 make_compound_operation (XEXP (x
, 0),
6531 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6533 /* If we are in a comparison and this is an AND with a power of two,
6534 convert this into the appropriate bit extract. */
6535 else if (in_code
== COMPARE
6536 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6537 new = make_extraction (mode
,
6538 make_compound_operation (XEXP (x
, 0),
6540 i
, NULL_RTX
, 1, 1, 0, 1);
6545 /* If the sign bit is known to be zero, replace this with an
6546 arithmetic shift. */
6547 if (have_insn_for (ASHIFTRT
, mode
)
6548 && ! have_insn_for (LSHIFTRT
, mode
)
6549 && mode_width
<= HOST_BITS_PER_WIDE_INT
6550 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6552 new = gen_rtx_ASHIFTRT (mode
,
6553 make_compound_operation (XEXP (x
, 0),
6559 /* ... fall through ... */
6565 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6566 this is a SIGN_EXTRACT. */
6567 if (GET_CODE (rhs
) == CONST_INT
6568 && GET_CODE (lhs
) == ASHIFT
6569 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6570 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6572 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6573 new = make_extraction (mode
, new,
6574 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6575 NULL_RTX
, mode_width
- INTVAL (rhs
),
6576 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6580 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6581 If so, try to merge the shifts into a SIGN_EXTEND. We could
6582 also do this for some cases of SIGN_EXTRACT, but it doesn't
6583 seem worth the effort; the case checked for occurs on Alpha. */
6585 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6586 && ! (GET_CODE (lhs
) == SUBREG
6587 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6588 && GET_CODE (rhs
) == CONST_INT
6589 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6590 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6591 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6592 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6593 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6598 /* Call ourselves recursively on the inner expression. If we are
6599 narrowing the object and it has a different RTL code from
6600 what it originally did, do this SUBREG as a force_to_mode. */
6602 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6603 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6604 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6605 && subreg_lowpart_p (x
))
6607 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6610 /* If we have something other than a SUBREG, we might have
6611 done an expansion, so rerun ourselves. */
6612 if (GET_CODE (newer
) != SUBREG
)
6613 newer
= make_compound_operation (newer
, in_code
);
6618 /* If this is a paradoxical subreg, and the new code is a sign or
6619 zero extension, omit the subreg and widen the extension. If it
6620 is a regular subreg, we can still get rid of the subreg by not
6621 widening so much, or in fact removing the extension entirely. */
6622 if ((GET_CODE (tem
) == SIGN_EXTEND
6623 || GET_CODE (tem
) == ZERO_EXTEND
)
6624 && subreg_lowpart_p (x
))
6626 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6627 || (GET_MODE_SIZE (mode
) >
6628 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6630 if (! SCALAR_INT_MODE_P (mode
))
6632 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6635 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6646 x
= gen_lowpart (mode
, new);
6647 code
= GET_CODE (x
);
6650 /* Now recursively process each operand of this operation. */
6651 fmt
= GET_RTX_FORMAT (code
);
6652 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6655 new = make_compound_operation (XEXP (x
, i
), next_code
);
6656 SUBST (XEXP (x
, i
), new);
6662 /* Given M see if it is a value that would select a field of bits
6663 within an item, but not the entire word. Return -1 if not.
6664 Otherwise, return the starting position of the field, where 0 is the
6667 *PLEN is set to the length of the field. */
6670 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6672 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6673 int pos
= exact_log2 (m
& -m
);
6679 /* Now shift off the low-order zero bits and see if we have a power of
6681 len
= exact_log2 ((m
>> pos
) + 1);
6690 /* See if X can be simplified knowing that we will only refer to it in
6691 MODE and will only refer to those bits that are nonzero in MASK.
6692 If other bits are being computed or if masking operations are done
6693 that select a superset of the bits in MASK, they can sometimes be
6696 Return a possibly simplified expression, but always convert X to
6697 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6699 Also, if REG is nonzero and X is a register equal in value to REG,
6702 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6703 are all off in X. This is used when X will be complemented, by either
6704 NOT, NEG, or XOR. */
6707 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6708 rtx reg
, int just_select
)
6710 enum rtx_code code
= GET_CODE (x
);
6711 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6712 enum machine_mode op_mode
;
6713 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6716 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6717 code below will do the wrong thing since the mode of such an
6718 expression is VOIDmode.
6720 Also do nothing if X is a CLOBBER; this can happen if X was
6721 the return value from a call to gen_lowpart. */
6722 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6725 /* We want to perform the operation is its present mode unless we know
6726 that the operation is valid in MODE, in which case we do the operation
6728 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6729 && have_insn_for (code
, mode
))
6730 ? mode
: GET_MODE (x
));
6732 /* It is not valid to do a right-shift in a narrower mode
6733 than the one it came in with. */
6734 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6735 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6736 op_mode
= GET_MODE (x
);
6738 /* Truncate MASK to fit OP_MODE. */
6740 mask
&= GET_MODE_MASK (op_mode
);
6742 /* When we have an arithmetic operation, or a shift whose count we
6743 do not know, we need to assume that all bits up to the highest-order
6744 bit in MASK will be needed. This is how we form such a mask. */
6745 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6746 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6748 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6751 /* Determine what bits of X are guaranteed to be (non)zero. */
6752 nonzero
= nonzero_bits (x
, mode
);
6754 /* If none of the bits in X are needed, return a zero. */
6755 if (! just_select
&& (nonzero
& mask
) == 0)
6758 /* If X is a CONST_INT, return a new one. Do this here since the
6759 test below will fail. */
6760 if (GET_CODE (x
) == CONST_INT
)
6762 if (SCALAR_INT_MODE_P (mode
))
6763 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6766 x
= GEN_INT (INTVAL (x
) & mask
);
6767 return gen_lowpart_common (mode
, x
);
6771 /* If X is narrower than MODE and we want all the bits in X's mode, just
6772 get X in the proper mode. */
6773 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6774 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6775 return gen_lowpart (mode
, x
);
6777 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6778 MASK are already known to be zero in X, we need not do anything. */
6779 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6785 /* If X is a (clobber (const_int)), return it since we know we are
6786 generating something that won't match. */
6790 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6791 spanned the boundary of the MEM. If we are now masking so it is
6792 within that boundary, we don't need the USE any more. */
6793 if (! BITS_BIG_ENDIAN
6794 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6795 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6802 x
= expand_compound_operation (x
);
6803 if (GET_CODE (x
) != code
)
6804 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6808 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6809 || rtx_equal_p (reg
, get_last_value (x
))))
6814 if (subreg_lowpart_p (x
)
6815 /* We can ignore the effect of this SUBREG if it narrows the mode or
6816 if the constant masks to zero all the bits the mode doesn't
6818 && ((GET_MODE_SIZE (GET_MODE (x
))
6819 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6821 & GET_MODE_MASK (GET_MODE (x
))
6822 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6823 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6827 /* If this is an AND with a constant, convert it into an AND
6828 whose constant is the AND of that constant with MASK. If it
6829 remains an AND of MASK, delete it since it is redundant. */
6831 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6833 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6834 mask
& INTVAL (XEXP (x
, 1)));
6836 /* If X is still an AND, see if it is an AND with a mask that
6837 is just some low-order bits. If so, and it is MASK, we don't
6840 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6841 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6845 /* If it remains an AND, try making another AND with the bits
6846 in the mode mask that aren't in MASK turned on. If the
6847 constant in the AND is wide enough, this might make a
6848 cheaper constant. */
6850 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6851 && GET_MODE_MASK (GET_MODE (x
)) != mask
6852 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6854 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6855 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6856 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6859 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6860 number, sign extend it. */
6861 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6862 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6863 cval
|= (HOST_WIDE_INT
) -1 << width
;
6865 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6866 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6876 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6877 low-order bits (as in an alignment operation) and FOO is already
6878 aligned to that boundary, mask C1 to that boundary as well.
6879 This may eliminate that PLUS and, later, the AND. */
6882 unsigned int width
= GET_MODE_BITSIZE (mode
);
6883 unsigned HOST_WIDE_INT smask
= mask
;
6885 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6886 number, sign extend it. */
6888 if (width
< HOST_BITS_PER_WIDE_INT
6889 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6890 smask
|= (HOST_WIDE_INT
) -1 << width
;
6892 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6893 && exact_log2 (- smask
) >= 0
6894 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6895 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6896 return force_to_mode (plus_constant (XEXP (x
, 0),
6897 (INTVAL (XEXP (x
, 1)) & smask
)),
6898 mode
, smask
, reg
, next_select
);
6901 /* ... fall through ... */
6904 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6905 most significant bit in MASK since carries from those bits will
6906 affect the bits we are interested in. */
6911 /* If X is (minus C Y) where C's least set bit is larger than any bit
6912 in the mask, then we may replace with (neg Y). */
6913 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6914 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6915 & -INTVAL (XEXP (x
, 0))))
6918 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6920 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6923 /* Similarly, if C contains every bit in the fuller_mask, then we may
6924 replace with (not Y). */
6925 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6926 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6927 == INTVAL (XEXP (x
, 0))))
6929 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6930 XEXP (x
, 1), GET_MODE (x
));
6931 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6939 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6940 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6941 operation which may be a bitfield extraction. Ensure that the
6942 constant we form is not wider than the mode of X. */
6944 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6945 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6946 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6947 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6948 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6949 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6950 + floor_log2 (INTVAL (XEXP (x
, 1))))
6951 < GET_MODE_BITSIZE (GET_MODE (x
)))
6952 && (INTVAL (XEXP (x
, 1))
6953 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6955 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6956 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6957 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6958 XEXP (XEXP (x
, 0), 0), temp
);
6959 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6960 XEXP (XEXP (x
, 0), 1));
6961 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6965 /* For most binary operations, just propagate into the operation and
6966 change the mode if we have an operation of that mode. */
6968 op0
= gen_lowpart (op_mode
,
6969 force_to_mode (XEXP (x
, 0), mode
, mask
,
6971 op1
= gen_lowpart (op_mode
,
6972 force_to_mode (XEXP (x
, 1), mode
, mask
,
6975 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6976 x
= gen_binary (code
, op_mode
, op0
, op1
);
6980 /* For left shifts, do the same, but just for the first operand.
6981 However, we cannot do anything with shifts where we cannot
6982 guarantee that the counts are smaller than the size of the mode
6983 because such a count will have a different meaning in a
6986 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6987 && INTVAL (XEXP (x
, 1)) >= 0
6988 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6989 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6990 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6991 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6994 /* If the shift count is a constant and we can do arithmetic in
6995 the mode of the shift, refine which bits we need. Otherwise, use the
6996 conservative form of the mask. */
6997 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6998 && INTVAL (XEXP (x
, 1)) >= 0
6999 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7000 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7001 mask
>>= INTVAL (XEXP (x
, 1));
7005 op0
= gen_lowpart (op_mode
,
7006 force_to_mode (XEXP (x
, 0), op_mode
,
7007 mask
, reg
, next_select
));
7009 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7010 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7014 /* Here we can only do something if the shift count is a constant,
7015 this shift constant is valid for the host, and we can do arithmetic
7018 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7019 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7020 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7022 rtx inner
= XEXP (x
, 0);
7023 unsigned HOST_WIDE_INT inner_mask
;
7025 /* Select the mask of the bits we need for the shift operand. */
7026 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7028 /* We can only change the mode of the shift if we can do arithmetic
7029 in the mode of the shift and INNER_MASK is no wider than the
7030 width of OP_MODE. */
7031 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7032 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7033 op_mode
= GET_MODE (x
);
7035 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7037 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7038 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7041 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7042 shift and AND produces only copies of the sign bit (C2 is one less
7043 than a power of two), we can do this with just a shift. */
7045 if (GET_CODE (x
) == LSHIFTRT
7046 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7047 /* The shift puts one of the sign bit copies in the least significant
7049 && ((INTVAL (XEXP (x
, 1))
7050 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7051 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7052 && exact_log2 (mask
+ 1) >= 0
7053 /* Number of bits left after the shift must be more than the mask
7055 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7056 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7057 /* Must be more sign bit copies than the mask needs. */
7058 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7059 >= exact_log2 (mask
+ 1)))
7060 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7061 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7062 - exact_log2 (mask
+ 1)));
7067 /* If we are just looking for the sign bit, we don't need this shift at
7068 all, even if it has a variable count. */
7069 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7070 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7071 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7072 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7074 /* If this is a shift by a constant, get a mask that contains those bits
7075 that are not copies of the sign bit. We then have two cases: If
7076 MASK only includes those bits, this can be a logical shift, which may
7077 allow simplifications. If MASK is a single-bit field not within
7078 those bits, we are requesting a copy of the sign bit and hence can
7079 shift the sign bit to the appropriate location. */
7081 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7082 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7086 /* If the considered data is wider than HOST_WIDE_INT, we can't
7087 represent a mask for all its bits in a single scalar.
7088 But we only care about the lower bits, so calculate these. */
7090 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7092 nonzero
= ~(HOST_WIDE_INT
) 0;
7094 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7095 is the number of bits a full-width mask would have set.
7096 We need only shift if these are fewer than nonzero can
7097 hold. If not, we must keep all bits set in nonzero. */
7099 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7100 < HOST_BITS_PER_WIDE_INT
)
7101 nonzero
>>= INTVAL (XEXP (x
, 1))
7102 + HOST_BITS_PER_WIDE_INT
7103 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7107 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7108 nonzero
>>= INTVAL (XEXP (x
, 1));
7111 if ((mask
& ~nonzero
) == 0
7112 || (i
= exact_log2 (mask
)) >= 0)
7114 x
= simplify_shift_const
7115 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7116 i
< 0 ? INTVAL (XEXP (x
, 1))
7117 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7119 if (GET_CODE (x
) != ASHIFTRT
)
7120 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7124 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7125 even if the shift count isn't a constant. */
7127 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7131 /* If this is a zero- or sign-extension operation that just affects bits
7132 we don't care about, remove it. Be sure the call above returned
7133 something that is still a shift. */
7135 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7136 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7137 && INTVAL (XEXP (x
, 1)) >= 0
7138 && (INTVAL (XEXP (x
, 1))
7139 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7140 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7141 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7142 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7149 /* If the shift count is constant and we can do computations
7150 in the mode of X, compute where the bits we care about are.
7151 Otherwise, we can't do anything. Don't change the mode of
7152 the shift or propagate MODE into the shift, though. */
7153 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7154 && INTVAL (XEXP (x
, 1)) >= 0)
7156 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7157 GET_MODE (x
), GEN_INT (mask
),
7159 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7161 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7162 INTVAL (temp
), reg
, next_select
));
7167 /* If we just want the low-order bit, the NEG isn't needed since it
7168 won't change the low-order bit. */
7170 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7172 /* We need any bits less significant than the most significant bit in
7173 MASK since carries from those bits will affect the bits we are
7179 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7180 same as the XOR case above. Ensure that the constant we form is not
7181 wider than the mode of X. */
7183 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7184 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7185 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7186 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7187 < GET_MODE_BITSIZE (GET_MODE (x
)))
7188 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7190 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7192 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7193 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7195 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7198 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7199 use the full mask inside the NOT. */
7203 op0
= gen_lowpart (op_mode
,
7204 force_to_mode (XEXP (x
, 0), mode
, mask
,
7206 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7207 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7211 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7212 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7213 which is equal to STORE_FLAG_VALUE. */
7214 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7215 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7216 && (nonzero_bits (XEXP (x
, 0), mode
)
7217 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7218 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7223 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7224 written in a narrower mode. We play it safe and do not do so. */
7227 gen_lowpart (GET_MODE (x
),
7228 force_to_mode (XEXP (x
, 1), mode
,
7229 mask
, reg
, next_select
)));
7231 gen_lowpart (GET_MODE (x
),
7232 force_to_mode (XEXP (x
, 2), mode
,
7233 mask
, reg
, next_select
)));
7240 /* Ensure we return a value of the proper mode. */
7241 return gen_lowpart (mode
, x
);
7244 /* Return nonzero if X is an expression that has one of two values depending on
7245 whether some other value is zero or nonzero. In that case, we return the
7246 value that is being tested, *PTRUE is set to the value if the rtx being
7247 returned has a nonzero value, and *PFALSE is set to the other alternative.
7249 If we return zero, we set *PTRUE and *PFALSE to X. */
7252 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7254 enum machine_mode mode
= GET_MODE (x
);
7255 enum rtx_code code
= GET_CODE (x
);
7256 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7257 unsigned HOST_WIDE_INT nz
;
7259 /* If we are comparing a value against zero, we are done. */
7260 if ((code
== NE
|| code
== EQ
)
7261 && XEXP (x
, 1) == const0_rtx
)
7263 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7264 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7268 /* If this is a unary operation whose operand has one of two values, apply
7269 our opcode to compute those values. */
7270 else if (GET_RTX_CLASS (code
) == '1'
7271 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7273 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7274 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7275 GET_MODE (XEXP (x
, 0)));
7279 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7280 make can't possibly match and would suppress other optimizations. */
7281 else if (code
== COMPARE
)
7284 /* If this is a binary operation, see if either side has only one of two
7285 values. If either one does or if both do and they are conditional on
7286 the same value, compute the new true and false values. */
7287 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7288 || GET_RTX_CLASS (code
) == '<')
7290 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7291 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7293 if ((cond0
!= 0 || cond1
!= 0)
7294 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7296 /* If if_then_else_cond returned zero, then true/false are the
7297 same rtl. We must copy one of them to prevent invalid rtl
7300 true0
= copy_rtx (true0
);
7301 else if (cond1
== 0)
7302 true1
= copy_rtx (true1
);
7304 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7305 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7306 return cond0
? cond0
: cond1
;
7309 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7310 operands is zero when the other is nonzero, and vice-versa,
7311 and STORE_FLAG_VALUE is 1 or -1. */
7313 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7314 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7316 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7318 rtx op0
= XEXP (XEXP (x
, 0), 1);
7319 rtx op1
= XEXP (XEXP (x
, 1), 1);
7321 cond0
= XEXP (XEXP (x
, 0), 0);
7322 cond1
= XEXP (XEXP (x
, 1), 0);
7324 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7325 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7326 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7327 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7328 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7329 || ((swap_condition (GET_CODE (cond0
))
7330 == combine_reversed_comparison_code (cond1
))
7331 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7332 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7333 && ! side_effects_p (x
))
7335 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7336 *pfalse
= gen_binary (MULT
, mode
,
7338 ? simplify_gen_unary (NEG
, mode
, op1
,
7346 /* Similarly for MULT, AND and UMIN, except that for these the result
7348 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7349 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7350 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7352 cond0
= XEXP (XEXP (x
, 0), 0);
7353 cond1
= XEXP (XEXP (x
, 1), 0);
7355 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7356 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7357 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7358 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7359 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7360 || ((swap_condition (GET_CODE (cond0
))
7361 == combine_reversed_comparison_code (cond1
))
7362 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7363 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7364 && ! side_effects_p (x
))
7366 *ptrue
= *pfalse
= const0_rtx
;
7372 else if (code
== IF_THEN_ELSE
)
7374 /* If we have IF_THEN_ELSE already, extract the condition and
7375 canonicalize it if it is NE or EQ. */
7376 cond0
= XEXP (x
, 0);
7377 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7378 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7379 return XEXP (cond0
, 0);
7380 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7382 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7383 return XEXP (cond0
, 0);
7389 /* If X is a SUBREG, we can narrow both the true and false values
7390 if the inner expression, if there is a condition. */
7391 else if (code
== SUBREG
7392 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7395 *ptrue
= simplify_gen_subreg (mode
, true0
,
7396 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7397 *pfalse
= simplify_gen_subreg (mode
, false0
,
7398 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7403 /* If X is a constant, this isn't special and will cause confusions
7404 if we treat it as such. Likewise if it is equivalent to a constant. */
7405 else if (CONSTANT_P (x
)
7406 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7409 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7410 will be least confusing to the rest of the compiler. */
7411 else if (mode
== BImode
)
7413 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7417 /* If X is known to be either 0 or -1, those are the true and
7418 false values when testing X. */
7419 else if (x
== constm1_rtx
|| x
== const0_rtx
7420 || (mode
!= VOIDmode
7421 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7423 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7427 /* Likewise for 0 or a single bit. */
7428 else if (SCALAR_INT_MODE_P (mode
)
7429 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7430 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7432 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7436 /* Otherwise fail; show no condition with true and false values the same. */
7437 *ptrue
= *pfalse
= x
;
7441 /* Return the value of expression X given the fact that condition COND
7442 is known to be true when applied to REG as its first operand and VAL
7443 as its second. X is known to not be shared and so can be modified in
7446 We only handle the simplest cases, and specifically those cases that
7447 arise with IF_THEN_ELSE expressions. */
7450 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7452 enum rtx_code code
= GET_CODE (x
);
7457 if (side_effects_p (x
))
7460 /* If either operand of the condition is a floating point value,
7461 then we have to avoid collapsing an EQ comparison. */
7463 && rtx_equal_p (x
, reg
)
7464 && ! FLOAT_MODE_P (GET_MODE (x
))
7465 && ! FLOAT_MODE_P (GET_MODE (val
)))
7468 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7471 /* If X is (abs REG) and we know something about REG's relationship
7472 with zero, we may be able to simplify this. */
7474 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7477 case GE
: case GT
: case EQ
:
7480 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7482 GET_MODE (XEXP (x
, 0)));
7487 /* The only other cases we handle are MIN, MAX, and comparisons if the
7488 operands are the same as REG and VAL. */
7490 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7492 if (rtx_equal_p (XEXP (x
, 0), val
))
7493 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7495 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7497 if (GET_RTX_CLASS (code
) == '<')
7499 if (comparison_dominates_p (cond
, code
))
7500 return const_true_rtx
;
7502 code
= combine_reversed_comparison_code (x
);
7504 && comparison_dominates_p (cond
, code
))
7509 else if (code
== SMAX
|| code
== SMIN
7510 || code
== UMIN
|| code
== UMAX
)
7512 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7514 /* Do not reverse the condition when it is NE or EQ.
7515 This is because we cannot conclude anything about
7516 the value of 'SMAX (x, y)' when x is not equal to y,
7517 but we can when x equals y. */
7518 if ((code
== SMAX
|| code
== UMAX
)
7519 && ! (cond
== EQ
|| cond
== NE
))
7520 cond
= reverse_condition (cond
);
7525 return unsignedp
? x
: XEXP (x
, 1);
7527 return unsignedp
? x
: XEXP (x
, 0);
7529 return unsignedp
? XEXP (x
, 1) : x
;
7531 return unsignedp
? XEXP (x
, 0) : x
;
7538 else if (code
== SUBREG
)
7540 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7541 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7543 if (SUBREG_REG (x
) != r
)
7545 /* We must simplify subreg here, before we lose track of the
7546 original inner_mode. */
7547 new = simplify_subreg (GET_MODE (x
), r
,
7548 inner_mode
, SUBREG_BYTE (x
));
7552 SUBST (SUBREG_REG (x
), r
);
7557 /* We don't have to handle SIGN_EXTEND here, because even in the
7558 case of replacing something with a modeless CONST_INT, a
7559 CONST_INT is already (supposed to be) a valid sign extension for
7560 its narrower mode, which implies it's already properly
7561 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7562 story is different. */
7563 else if (code
== ZERO_EXTEND
)
7565 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7566 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7568 if (XEXP (x
, 0) != r
)
7570 /* We must simplify the zero_extend here, before we lose
7571 track of the original inner_mode. */
7572 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7577 SUBST (XEXP (x
, 0), r
);
7583 fmt
= GET_RTX_FORMAT (code
);
7584 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7587 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7588 else if (fmt
[i
] == 'E')
7589 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7590 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7597 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7598 assignment as a field assignment. */
7601 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7603 if (x
== y
|| rtx_equal_p (x
, y
))
7606 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7609 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7610 Note that all SUBREGs of MEM are paradoxical; otherwise they
7611 would have been rewritten. */
7612 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7613 && GET_CODE (SUBREG_REG (y
)) == MEM
7614 && rtx_equal_p (SUBREG_REG (y
),
7615 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7618 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7619 && GET_CODE (SUBREG_REG (x
)) == MEM
7620 && rtx_equal_p (SUBREG_REG (x
),
7621 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7624 /* We used to see if get_last_value of X and Y were the same but that's
7625 not correct. In one direction, we'll cause the assignment to have
7626 the wrong destination and in the case, we'll import a register into this
7627 insn that might have already have been dead. So fail if none of the
7628 above cases are true. */
7632 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7633 Return that assignment if so.
7635 We only handle the most common cases. */
7638 make_field_assignment (rtx x
)
7640 rtx dest
= SET_DEST (x
);
7641 rtx src
= SET_SRC (x
);
7646 unsigned HOST_WIDE_INT len
;
7648 enum machine_mode mode
;
7650 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7651 a clear of a one-bit field. We will have changed it to
7652 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7655 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7656 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7657 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7658 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7660 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7663 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7667 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7668 && subreg_lowpart_p (XEXP (src
, 0))
7669 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7670 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7671 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7672 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7673 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7674 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7676 assign
= make_extraction (VOIDmode
, dest
, 0,
7677 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7680 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7684 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7686 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7687 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7688 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7690 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7693 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7697 /* The other case we handle is assignments into a constant-position
7698 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7699 a mask that has all one bits except for a group of zero bits and
7700 OTHER is known to have zeros where C1 has ones, this is such an
7701 assignment. Compute the position and length from C1. Shift OTHER
7702 to the appropriate position, force it to the required mode, and
7703 make the extraction. Check for the AND in both operands. */
7705 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7708 rhs
= expand_compound_operation (XEXP (src
, 0));
7709 lhs
= expand_compound_operation (XEXP (src
, 1));
7711 if (GET_CODE (rhs
) == AND
7712 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7713 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7714 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7715 else if (GET_CODE (lhs
) == AND
7716 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7717 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7718 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7722 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7723 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7724 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7725 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7728 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7732 /* The mode to use for the source is the mode of the assignment, or of
7733 what is inside a possible STRICT_LOW_PART. */
7734 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7735 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7737 /* Shift OTHER right POS places and make it the source, restricting it
7738 to the proper length and mode. */
7740 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7741 GET_MODE (src
), other
, pos
),
7743 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7744 ? ~(unsigned HOST_WIDE_INT
) 0
7745 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7748 /* If SRC is masked by an AND that does not make a difference in
7749 the value being stored, strip it. */
7750 if (GET_CODE (assign
) == ZERO_EXTRACT
7751 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7752 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7753 && GET_CODE (src
) == AND
7754 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7755 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7756 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7757 src
= XEXP (src
, 0);
7759 return gen_rtx_SET (VOIDmode
, assign
, src
);
7762 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7766 apply_distributive_law (rtx x
)
7768 enum rtx_code code
= GET_CODE (x
);
7769 enum rtx_code inner_code
;
7770 rtx lhs
, rhs
, other
;
7773 /* Distributivity is not true for floating point as it can change the
7774 value. So we don't do it unless -funsafe-math-optimizations. */
7775 if (FLOAT_MODE_P (GET_MODE (x
))
7776 && ! flag_unsafe_math_optimizations
)
7779 /* The outer operation can only be one of the following: */
7780 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7781 && code
!= PLUS
&& code
!= MINUS
)
7787 /* If either operand is a primitive we can't do anything, so get out
7789 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7790 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7793 lhs
= expand_compound_operation (lhs
);
7794 rhs
= expand_compound_operation (rhs
);
7795 inner_code
= GET_CODE (lhs
);
7796 if (inner_code
!= GET_CODE (rhs
))
7799 /* See if the inner and outer operations distribute. */
7806 /* These all distribute except over PLUS. */
7807 if (code
== PLUS
|| code
== MINUS
)
7812 if (code
!= PLUS
&& code
!= MINUS
)
7817 /* This is also a multiply, so it distributes over everything. */
7821 /* Non-paradoxical SUBREGs distributes over all operations, provided
7822 the inner modes and byte offsets are the same, this is an extraction
7823 of a low-order part, we don't convert an fp operation to int or
7824 vice versa, and we would not be converting a single-word
7825 operation into a multi-word operation. The latter test is not
7826 required, but it prevents generating unneeded multi-word operations.
7827 Some of the previous tests are redundant given the latter test, but
7828 are retained because they are required for correctness.
7830 We produce the result slightly differently in this case. */
7832 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7833 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7834 || ! subreg_lowpart_p (lhs
)
7835 || (GET_MODE_CLASS (GET_MODE (lhs
))
7836 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7837 || (GET_MODE_SIZE (GET_MODE (lhs
))
7838 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7839 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7842 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7843 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7844 return gen_lowpart (GET_MODE (x
), tem
);
7850 /* Set LHS and RHS to the inner operands (A and B in the example
7851 above) and set OTHER to the common operand (C in the example).
7852 These is only one way to do this unless the inner operation is
7854 if (GET_RTX_CLASS (inner_code
) == 'c'
7855 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7856 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7857 else if (GET_RTX_CLASS (inner_code
) == 'c'
7858 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7859 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7860 else if (GET_RTX_CLASS (inner_code
) == 'c'
7861 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7862 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7863 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7864 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7868 /* Form the new inner operation, seeing if it simplifies first. */
7869 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7871 /* There is one exception to the general way of distributing:
7872 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7873 if (code
== XOR
&& inner_code
== IOR
)
7876 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7879 /* We may be able to continuing distributing the result, so call
7880 ourselves recursively on the inner operation before forming the
7881 outer operation, which we return. */
7882 return gen_binary (inner_code
, GET_MODE (x
),
7883 apply_distributive_law (tem
), other
);
7886 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7889 Return an equivalent form, if different from X. Otherwise, return X. If
7890 X is zero, we are to always construct the equivalent form. */
7893 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7894 unsigned HOST_WIDE_INT constop
)
7896 unsigned HOST_WIDE_INT nonzero
;
7899 /* Simplify VAROP knowing that we will be only looking at some of the
7902 Note by passing in CONSTOP, we guarantee that the bits not set in
7903 CONSTOP are not significant and will never be examined. We must
7904 ensure that is the case by explicitly masking out those bits
7905 before returning. */
7906 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7908 /* If VAROP is a CLOBBER, we will fail so return it. */
7909 if (GET_CODE (varop
) == CLOBBER
)
7912 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7913 to VAROP and return the new constant. */
7914 if (GET_CODE (varop
) == CONST_INT
)
7915 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7917 /* See what bits may be nonzero in VAROP. Unlike the general case of
7918 a call to nonzero_bits, here we don't care about bits outside
7921 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7923 /* Turn off all bits in the constant that are known to already be zero.
7924 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7925 which is tested below. */
7929 /* If we don't have any bits left, return zero. */
7933 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7934 a power of two, we can replace this with an ASHIFT. */
7935 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7936 && (i
= exact_log2 (constop
)) >= 0)
7937 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7939 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7940 or XOR, then try to apply the distributive law. This may eliminate
7941 operations if either branch can be simplified because of the AND.
7942 It may also make some cases more complex, but those cases probably
7943 won't match a pattern either with or without this. */
7945 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7949 apply_distributive_law
7950 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7951 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7952 XEXP (varop
, 0), constop
),
7953 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7954 XEXP (varop
, 1), constop
))));
7956 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7957 the AND and see if one of the operands simplifies to zero. If so, we
7958 may eliminate it. */
7960 if (GET_CODE (varop
) == PLUS
7961 && exact_log2 (constop
+ 1) >= 0)
7965 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7966 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7967 if (o0
== const0_rtx
)
7969 if (o1
== const0_rtx
)
7973 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7974 if we already had one (just check for the simplest cases). */
7975 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7976 && GET_MODE (XEXP (x
, 0)) == mode
7977 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7978 varop
= XEXP (x
, 0);
7980 varop
= gen_lowpart (mode
, varop
);
7982 /* If we can't make the SUBREG, try to return what we were given. */
7983 if (GET_CODE (varop
) == CLOBBER
)
7984 return x
? x
: varop
;
7986 /* If we are only masking insignificant bits, return VAROP. */
7987 if (constop
== nonzero
)
7991 /* Otherwise, return an AND. */
7992 constop
= trunc_int_for_mode (constop
, mode
);
7993 /* See how much, if any, of X we can use. */
7994 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7995 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7999 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8000 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8001 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8003 SUBST (XEXP (x
, 0), varop
);
8010 #define nonzero_bits_with_known(X, MODE) \
8011 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8013 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8014 It avoids exponential behavior in nonzero_bits1 when X has
8015 identical subexpressions on the first or the second level. */
8017 static unsigned HOST_WIDE_INT
8018 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8019 enum machine_mode known_mode
,
8020 unsigned HOST_WIDE_INT known_ret
)
8022 if (x
== known_x
&& mode
== known_mode
)
8025 /* Try to find identical subexpressions. If found call
8026 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8027 precomputed value for the subexpression as KNOWN_RET. */
8029 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8030 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8032 rtx x0
= XEXP (x
, 0);
8033 rtx x1
= XEXP (x
, 1);
8035 /* Check the first level. */
8037 return nonzero_bits1 (x
, mode
, x0
, mode
,
8038 nonzero_bits_with_known (x0
, mode
));
8040 /* Check the second level. */
8041 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8042 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8043 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8044 return nonzero_bits1 (x
, mode
, x1
, mode
,
8045 nonzero_bits_with_known (x1
, mode
));
8047 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8048 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8049 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8050 return nonzero_bits1 (x
, mode
, x0
, mode
,
8051 nonzero_bits_with_known (x0
, mode
));
8054 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8057 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8058 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8059 is less useful. We can't allow both, because that results in exponential
8060 run time recursion. There is a nullstone testcase that triggered
8061 this. This macro avoids accidental uses of num_sign_bit_copies. */
8062 #define cached_num_sign_bit_copies()
8064 /* Given an expression, X, compute which bits in X can be nonzero.
8065 We don't care about bits outside of those defined in MODE.
8067 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8068 a shift, AND, or zero_extract, we can do better. */
8070 static unsigned HOST_WIDE_INT
8071 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8072 enum machine_mode known_mode
,
8073 unsigned HOST_WIDE_INT known_ret
)
8075 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8076 unsigned HOST_WIDE_INT inner_nz
;
8078 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8081 /* For floating-point values, assume all bits are needed. */
8082 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8085 /* If X is wider than MODE, use its mode instead. */
8086 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8088 mode
= GET_MODE (x
);
8089 nonzero
= GET_MODE_MASK (mode
);
8090 mode_width
= GET_MODE_BITSIZE (mode
);
8093 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8094 /* Our only callers in this case look for single bit values. So
8095 just return the mode mask. Those tests will then be false. */
8098 #ifndef WORD_REGISTER_OPERATIONS
8099 /* If MODE is wider than X, but both are a single word for both the host
8100 and target machines, we can compute this from which bits of the
8101 object might be nonzero in its own mode, taking into account the fact
8102 that on many CISC machines, accessing an object in a wider mode
8103 causes the high-order bits to become undefined. So they are
8104 not known to be zero. */
8106 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8107 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8108 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8109 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8111 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8112 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8117 code
= GET_CODE (x
);
8121 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8122 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8123 all the bits above ptr_mode are known to be zero. */
8124 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8126 nonzero
&= GET_MODE_MASK (ptr_mode
);
8129 /* Include declared information about alignment of pointers. */
8130 /* ??? We don't properly preserve REG_POINTER changes across
8131 pointer-to-integer casts, so we can't trust it except for
8132 things that we know must be pointers. See execute/960116-1.c. */
8133 if ((x
== stack_pointer_rtx
8134 || x
== frame_pointer_rtx
8135 || x
== arg_pointer_rtx
)
8136 && REGNO_POINTER_ALIGN (REGNO (x
)))
8138 unsigned HOST_WIDE_INT alignment
8139 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8141 #ifdef PUSH_ROUNDING
8142 /* If PUSH_ROUNDING is defined, it is possible for the
8143 stack to be momentarily aligned only to that amount,
8144 so we pick the least alignment. */
8145 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8146 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8150 nonzero
&= ~(alignment
- 1);
8153 /* If X is a register whose nonzero bits value is current, use it.
8154 Otherwise, if X is a register whose value we can find, use that
8155 value. Otherwise, use the previously-computed global nonzero bits
8156 for this register. */
8158 if (reg_last_set_value
[REGNO (x
)] != 0
8159 && (reg_last_set_mode
[REGNO (x
)] == mode
8160 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8161 && GET_MODE_CLASS (mode
) == MODE_INT
))
8162 && (reg_last_set_label
[REGNO (x
)] == label_tick
8163 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8164 && REG_N_SETS (REGNO (x
)) == 1
8165 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8167 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8168 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8170 tem
= get_last_value (x
);
8174 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8175 /* If X is narrower than MODE and TEM is a non-negative
8176 constant that would appear negative in the mode of X,
8177 sign-extend it for use in reg_nonzero_bits because some
8178 machines (maybe most) will actually do the sign-extension
8179 and this is the conservative approach.
8181 ??? For 2.5, try to tighten up the MD files in this regard
8182 instead of this kludge. */
8184 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8185 && GET_CODE (tem
) == CONST_INT
8187 && 0 != (INTVAL (tem
)
8188 & ((HOST_WIDE_INT
) 1
8189 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8190 tem
= GEN_INT (INTVAL (tem
)
8191 | ((HOST_WIDE_INT
) (-1)
8192 << GET_MODE_BITSIZE (GET_MODE (x
))));
8194 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8196 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8198 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8200 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8201 /* We don't know anything about the upper bits. */
8202 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8203 return nonzero
& mask
;
8209 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8210 /* If X is negative in MODE, sign-extend the value. */
8211 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8212 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8213 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8219 #ifdef LOAD_EXTEND_OP
8220 /* In many, if not most, RISC machines, reading a byte from memory
8221 zeros the rest of the register. Noticing that fact saves a lot
8222 of extra zero-extends. */
8223 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8224 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8229 case UNEQ
: case LTGT
:
8230 case GT
: case GTU
: case UNGT
:
8231 case LT
: case LTU
: case UNLT
:
8232 case GE
: case GEU
: case UNGE
:
8233 case LE
: case LEU
: case UNLE
:
8234 case UNORDERED
: case ORDERED
:
8236 /* If this produces an integer result, we know which bits are set.
8237 Code here used to clear bits outside the mode of X, but that is
8240 if (GET_MODE_CLASS (mode
) == MODE_INT
8241 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8242 nonzero
= STORE_FLAG_VALUE
;
8247 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8248 and num_sign_bit_copies. */
8249 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8250 == GET_MODE_BITSIZE (GET_MODE (x
)))
8254 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8255 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8260 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8261 and num_sign_bit_copies. */
8262 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8263 == GET_MODE_BITSIZE (GET_MODE (x
)))
8269 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8270 & GET_MODE_MASK (mode
));
8274 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8275 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8276 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8280 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8281 Otherwise, show all the bits in the outer mode but not the inner
8283 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8284 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8286 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8288 & (((HOST_WIDE_INT
) 1
8289 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8290 inner_nz
|= (GET_MODE_MASK (mode
)
8291 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8294 nonzero
&= inner_nz
;
8298 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8299 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8303 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8305 unsigned HOST_WIDE_INT nonzero0
=
8306 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8308 /* Don't call nonzero_bits for the second time if it cannot change
8310 if ((nonzero
& nonzero0
) != nonzero
)
8311 nonzero
&= (nonzero0
8312 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8316 case PLUS
: case MINUS
:
8318 case DIV
: case UDIV
:
8319 case MOD
: case UMOD
:
8320 /* We can apply the rules of arithmetic to compute the number of
8321 high- and low-order zero bits of these operations. We start by
8322 computing the width (position of the highest-order nonzero bit)
8323 and the number of low-order zero bits for each value. */
8325 unsigned HOST_WIDE_INT nz0
=
8326 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8327 unsigned HOST_WIDE_INT nz1
=
8328 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8329 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8330 int width0
= floor_log2 (nz0
) + 1;
8331 int width1
= floor_log2 (nz1
) + 1;
8332 int low0
= floor_log2 (nz0
& -nz0
);
8333 int low1
= floor_log2 (nz1
& -nz1
);
8334 HOST_WIDE_INT op0_maybe_minusp
8335 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8336 HOST_WIDE_INT op1_maybe_minusp
8337 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8338 unsigned int result_width
= mode_width
;
8344 result_width
= MAX (width0
, width1
) + 1;
8345 result_low
= MIN (low0
, low1
);
8348 result_low
= MIN (low0
, low1
);
8351 result_width
= width0
+ width1
;
8352 result_low
= low0
+ low1
;
8357 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8358 result_width
= width0
;
8363 result_width
= width0
;
8368 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8369 result_width
= MIN (width0
, width1
);
8370 result_low
= MIN (low0
, low1
);
8375 result_width
= MIN (width0
, width1
);
8376 result_low
= MIN (low0
, low1
);
8382 if (result_width
< mode_width
)
8383 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8386 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8388 #ifdef POINTERS_EXTEND_UNSIGNED
8389 /* If pointers extend unsigned and this is an addition or subtraction
8390 to a pointer in Pmode, all the bits above ptr_mode are known to be
8392 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8393 && (code
== PLUS
|| code
== MINUS
)
8394 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8395 nonzero
&= GET_MODE_MASK (ptr_mode
);
8401 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8402 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8403 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8407 /* If this is a SUBREG formed for a promoted variable that has
8408 been zero-extended, we know that at least the high-order bits
8409 are zero, though others might be too. */
8411 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8412 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8413 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8415 /* If the inner mode is a single word for both the host and target
8416 machines, we can compute this from which bits of the inner
8417 object might be nonzero. */
8418 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8419 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8420 <= HOST_BITS_PER_WIDE_INT
))
8422 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8424 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8425 /* If this is a typical RISC machine, we only have to worry
8426 about the way loads are extended. */
8427 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8429 & (((unsigned HOST_WIDE_INT
) 1
8430 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8432 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8433 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8436 /* On many CISC machines, accessing an object in a wider mode
8437 causes the high-order bits to become undefined. So they are
8438 not known to be zero. */
8439 if (GET_MODE_SIZE (GET_MODE (x
))
8440 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8441 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8442 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8451 /* The nonzero bits are in two classes: any bits within MODE
8452 that aren't in GET_MODE (x) are always significant. The rest of the
8453 nonzero bits are those that are significant in the operand of
8454 the shift when shifted the appropriate number of bits. This
8455 shows that high-order bits are cleared by the right shift and
8456 low-order bits by left shifts. */
8457 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8458 && INTVAL (XEXP (x
, 1)) >= 0
8459 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8461 enum machine_mode inner_mode
= GET_MODE (x
);
8462 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8463 int count
= INTVAL (XEXP (x
, 1));
8464 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8465 unsigned HOST_WIDE_INT op_nonzero
=
8466 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8467 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8468 unsigned HOST_WIDE_INT outer
= 0;
8470 if (mode_width
> width
)
8471 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8473 if (code
== LSHIFTRT
)
8475 else if (code
== ASHIFTRT
)
8479 /* If the sign bit may have been nonzero before the shift, we
8480 need to mark all the places it could have been copied to
8481 by the shift as possibly nonzero. */
8482 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8483 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8485 else if (code
== ASHIFT
)
8488 inner
= ((inner
<< (count
% width
)
8489 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8491 nonzero
&= (outer
| inner
);
8497 /* This is at most the number of bits in the mode. */
8498 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8502 /* If CLZ has a known value at zero, then the nonzero bits are
8503 that value, plus the number of bits in the mode minus one. */
8504 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8505 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8511 /* If CTZ has a known value at zero, then the nonzero bits are
8512 that value, plus the number of bits in the mode minus one. */
8513 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8514 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8524 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8525 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8535 /* See the macro definition above. */
8536 #undef cached_num_sign_bit_copies
8538 #define num_sign_bit_copies_with_known(X, M) \
8539 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8541 /* The function cached_num_sign_bit_copies is a wrapper around
8542 num_sign_bit_copies1. It avoids exponential behavior in
8543 num_sign_bit_copies1 when X has identical subexpressions on the
8544 first or the second level. */
8547 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8548 enum machine_mode known_mode
,
8549 unsigned int known_ret
)
8551 if (x
== known_x
&& mode
== known_mode
)
8554 /* Try to find identical subexpressions. If found call
8555 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8556 the precomputed value for the subexpression as KNOWN_RET. */
8558 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8559 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8561 rtx x0
= XEXP (x
, 0);
8562 rtx x1
= XEXP (x
, 1);
8564 /* Check the first level. */
8567 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8568 num_sign_bit_copies_with_known (x0
, mode
));
8570 /* Check the second level. */
8571 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8572 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8573 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8575 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8576 num_sign_bit_copies_with_known (x1
, mode
));
8578 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8579 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8580 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8582 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8583 num_sign_bit_copies_with_known (x0
, mode
));
8586 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8589 /* Return the number of bits at the high-order end of X that are known to
8590 be equal to the sign bit. X will be used in mode MODE; if MODE is
8591 VOIDmode, X will be used in its own mode. The returned value will always
8592 be between 1 and the number of bits in MODE. */
8595 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8596 enum machine_mode known_mode
,
8597 unsigned int known_ret
)
8599 enum rtx_code code
= GET_CODE (x
);
8600 unsigned int bitwidth
;
8601 int num0
, num1
, result
;
8602 unsigned HOST_WIDE_INT nonzero
;
8605 /* If we weren't given a mode, use the mode of X. If the mode is still
8606 VOIDmode, we don't know anything. Likewise if one of the modes is
8609 if (mode
== VOIDmode
)
8610 mode
= GET_MODE (x
);
8612 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8615 bitwidth
= GET_MODE_BITSIZE (mode
);
8617 /* For a smaller object, just ignore the high bits. */
8618 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8620 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8622 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8625 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8627 #ifndef WORD_REGISTER_OPERATIONS
8628 /* If this machine does not do all register operations on the entire
8629 register and MODE is wider than the mode of X, we can say nothing
8630 at all about the high-order bits. */
8633 /* Likewise on machines that do, if the mode of the object is smaller
8634 than a word and loads of that size don't sign extend, we can say
8635 nothing about the high order bits. */
8636 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8637 #ifdef LOAD_EXTEND_OP
8638 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8649 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8650 /* If pointers extend signed and this is a pointer in Pmode, say that
8651 all the bits above ptr_mode are known to be sign bit copies. */
8652 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8654 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8657 if (reg_last_set_value
[REGNO (x
)] != 0
8658 && reg_last_set_mode
[REGNO (x
)] == mode
8659 && (reg_last_set_label
[REGNO (x
)] == label_tick
8660 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8661 && REG_N_SETS (REGNO (x
)) == 1
8662 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8664 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8665 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8667 tem
= get_last_value (x
);
8669 return num_sign_bit_copies_with_known (tem
, mode
);
8671 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8672 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8673 return reg_sign_bit_copies
[REGNO (x
)];
8677 #ifdef LOAD_EXTEND_OP
8678 /* Some RISC machines sign-extend all loads of smaller than a word. */
8679 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8680 return MAX (1, ((int) bitwidth
8681 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8686 /* If the constant is negative, take its 1's complement and remask.
8687 Then see how many zero bits we have. */
8688 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8689 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8690 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8691 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8693 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8696 /* If this is a SUBREG for a promoted object that is sign-extended
8697 and we are looking at it in a wider mode, we know that at least the
8698 high-order bits are known to be sign bit copies. */
8700 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8702 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8703 return MAX ((int) bitwidth
8704 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8708 /* For a smaller object, just ignore the high bits. */
8709 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8711 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8712 return MAX (1, (num0
8713 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8717 #ifdef WORD_REGISTER_OPERATIONS
8718 #ifdef LOAD_EXTEND_OP
8719 /* For paradoxical SUBREGs on machines where all register operations
8720 affect the entire register, just look inside. Note that we are
8721 passing MODE to the recursive call, so the number of sign bit copies
8722 will remain relative to that mode, not the inner mode. */
8724 /* This works only if loads sign extend. Otherwise, if we get a
8725 reload for the inner part, it may be loaded from the stack, and
8726 then we lose all sign bit copies that existed before the store
8729 if ((GET_MODE_SIZE (GET_MODE (x
))
8730 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8731 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8732 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8733 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8739 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8740 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8744 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8745 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8748 /* For a smaller object, just ignore the high bits. */
8749 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8750 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8754 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8756 case ROTATE
: case ROTATERT
:
8757 /* If we are rotating left by a number of bits less than the number
8758 of sign bit copies, we can just subtract that amount from the
8760 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8761 && INTVAL (XEXP (x
, 1)) >= 0
8762 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8764 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8765 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8766 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8771 /* In general, this subtracts one sign bit copy. But if the value
8772 is known to be positive, the number of sign bit copies is the
8773 same as that of the input. Finally, if the input has just one bit
8774 that might be nonzero, all the bits are copies of the sign bit. */
8775 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8776 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8777 return num0
> 1 ? num0
- 1 : 1;
8779 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8784 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8789 case IOR
: case AND
: case XOR
:
8790 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8791 /* Logical operations will preserve the number of sign-bit copies.
8792 MIN and MAX operations always return one of the operands. */
8793 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8794 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8795 return MIN (num0
, num1
);
8797 case PLUS
: case MINUS
:
8798 /* For addition and subtraction, we can have a 1-bit carry. However,
8799 if we are subtracting 1 from a positive number, there will not
8800 be such a carry. Furthermore, if the positive number is known to
8801 be 0 or 1, we know the result is either -1 or 0. */
8803 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8804 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8806 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8807 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8808 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8809 : bitwidth
- floor_log2 (nonzero
) - 1);
8812 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8813 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8814 result
= MAX (1, MIN (num0
, num1
) - 1);
8816 #ifdef POINTERS_EXTEND_UNSIGNED
8817 /* If pointers extend signed and this is an addition or subtraction
8818 to a pointer in Pmode, all the bits above ptr_mode are known to be
8820 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8821 && (code
== PLUS
|| code
== MINUS
)
8822 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8823 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8824 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8830 /* The number of bits of the product is the sum of the number of
8831 bits of both terms. However, unless one of the terms if known
8832 to be positive, we must allow for an additional bit since negating
8833 a negative number can remove one sign bit copy. */
8835 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8836 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8838 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8840 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8841 || (((nonzero_bits (XEXP (x
, 0), mode
)
8842 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8843 && ((nonzero_bits (XEXP (x
, 1), mode
)
8844 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8847 return MAX (1, result
);
8850 /* The result must be <= the first operand. If the first operand
8851 has the high bit set, we know nothing about the number of sign
8853 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8855 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8856 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8859 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8862 /* The result must be <= the second operand. */
8863 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8866 /* Similar to unsigned division, except that we have to worry about
8867 the case where the divisor is negative, in which case we have
8869 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8871 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8872 || (nonzero_bits (XEXP (x
, 1), mode
)
8873 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8879 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8881 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8882 || (nonzero_bits (XEXP (x
, 1), mode
)
8883 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8889 /* Shifts by a constant add to the number of bits equal to the
8891 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8892 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8893 && INTVAL (XEXP (x
, 1)) > 0)
8894 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8899 /* Left shifts destroy copies. */
8900 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8901 || INTVAL (XEXP (x
, 1)) < 0
8902 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8905 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8906 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8909 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8910 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8911 return MIN (num0
, num1
);
8913 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8914 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8915 case GEU
: case GTU
: case LEU
: case LTU
:
8916 case UNORDERED
: case ORDERED
:
8917 /* If the constant is negative, take its 1's complement and remask.
8918 Then see how many zero bits we have. */
8919 nonzero
= STORE_FLAG_VALUE
;
8920 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8921 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8922 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8924 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8931 /* If we haven't been able to figure it out by one of the above rules,
8932 see if some of the high-order bits are known to be zero. If so,
8933 count those bits and return one less than that amount. If we can't
8934 safely compute the mask for this mode, always return BITWIDTH. */
8936 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8939 nonzero
= nonzero_bits (x
, mode
);
8940 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8941 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8944 /* Return the number of "extended" bits there are in X, when interpreted
8945 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8946 unsigned quantities, this is the number of high-order zero bits.
8947 For signed quantities, this is the number of copies of the sign bit
8948 minus 1. In both case, this function returns the number of "spare"
8949 bits. For example, if two quantities for which this function returns
8950 at least 1 are added, the addition is known not to overflow.
8952 This function will always return 0 unless called during combine, which
8953 implies that it must be called from a define_split. */
8956 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8958 if (nonzero_sign_valid
== 0)
8962 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8963 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8964 - floor_log2 (nonzero_bits (x
, mode
)))
8966 : num_sign_bit_copies (x
, mode
) - 1);
8969 /* This function is called from `simplify_shift_const' to merge two
8970 outer operations. Specifically, we have already found that we need
8971 to perform operation *POP0 with constant *PCONST0 at the outermost
8972 position. We would now like to also perform OP1 with constant CONST1
8973 (with *POP0 being done last).
8975 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8976 the resulting operation. *PCOMP_P is set to 1 if we would need to
8977 complement the innermost operand, otherwise it is unchanged.
8979 MODE is the mode in which the operation will be done. No bits outside
8980 the width of this mode matter. It is assumed that the width of this mode
8981 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8983 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8984 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8985 result is simply *PCONST0.
8987 If the resulting operation cannot be expressed as one operation, we
8988 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8991 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8993 enum rtx_code op0
= *pop0
;
8994 HOST_WIDE_INT const0
= *pconst0
;
8996 const0
&= GET_MODE_MASK (mode
);
8997 const1
&= GET_MODE_MASK (mode
);
8999 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9003 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9006 if (op1
== NIL
|| op0
== SET
)
9009 else if (op0
== NIL
)
9010 op0
= op1
, const0
= const1
;
9012 else if (op0
== op1
)
9036 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9037 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9040 /* If the two constants aren't the same, we can't do anything. The
9041 remaining six cases can all be done. */
9042 else if (const0
!= const1
)
9050 /* (a & b) | b == b */
9052 else /* op1 == XOR */
9053 /* (a ^ b) | b == a | b */
9059 /* (a & b) ^ b == (~a) & b */
9060 op0
= AND
, *pcomp_p
= 1;
9061 else /* op1 == IOR */
9062 /* (a | b) ^ b == a & ~b */
9063 op0
= AND
, const0
= ~const0
;
9068 /* (a | b) & b == b */
9070 else /* op1 == XOR */
9071 /* (a ^ b) & b) == (~a) & b */
9078 /* Check for NO-OP cases. */
9079 const0
&= GET_MODE_MASK (mode
);
9081 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9083 else if (const0
== 0 && op0
== AND
)
9085 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9089 /* ??? Slightly redundant with the above mask, but not entirely.
9090 Moving this above means we'd have to sign-extend the mode mask
9091 for the final test. */
9092 const0
= trunc_int_for_mode (const0
, mode
);
9100 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9101 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9102 that we started with.
9104 The shift is normally computed in the widest mode we find in VAROP, as
9105 long as it isn't a different number of words than RESULT_MODE. Exceptions
9106 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9109 simplify_shift_const (rtx x
, enum rtx_code code
,
9110 enum machine_mode result_mode
, rtx varop
,
9113 enum rtx_code orig_code
= code
;
9116 enum machine_mode mode
= result_mode
;
9117 enum machine_mode shift_mode
, tmode
;
9118 unsigned int mode_words
9119 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9120 /* We form (outer_op (code varop count) (outer_const)). */
9121 enum rtx_code outer_op
= NIL
;
9122 HOST_WIDE_INT outer_const
= 0;
9124 int complement_p
= 0;
9127 /* Make sure and truncate the "natural" shift on the way in. We don't
9128 want to do this inside the loop as it makes it more difficult to
9130 if (SHIFT_COUNT_TRUNCATED
)
9131 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9133 /* If we were given an invalid count, don't do anything except exactly
9134 what was requested. */
9136 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9141 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9146 /* Unless one of the branches of the `if' in this loop does a `continue',
9147 we will `break' the loop after the `if'. */
9151 /* If we have an operand of (clobber (const_int 0)), just return that
9153 if (GET_CODE (varop
) == CLOBBER
)
9156 /* If we discovered we had to complement VAROP, leave. Making a NOT
9157 here would cause an infinite loop. */
9161 /* Convert ROTATERT to ROTATE. */
9162 if (code
== ROTATERT
)
9164 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9166 if (VECTOR_MODE_P (result_mode
))
9167 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9169 count
= bitsize
- count
;
9172 /* We need to determine what mode we will do the shift in. If the
9173 shift is a right shift or a ROTATE, we must always do it in the mode
9174 it was originally done in. Otherwise, we can do it in MODE, the
9175 widest mode encountered. */
9177 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9178 ? result_mode
: mode
);
9180 /* Handle cases where the count is greater than the size of the mode
9181 minus 1. For ASHIFT, use the size minus one as the count (this can
9182 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9183 take the count modulo the size. For other shifts, the result is
9186 Since these shifts are being produced by the compiler by combining
9187 multiple operations, each of which are defined, we know what the
9188 result is supposed to be. */
9190 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9192 if (code
== ASHIFTRT
)
9193 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9194 else if (code
== ROTATE
|| code
== ROTATERT
)
9195 count
%= GET_MODE_BITSIZE (shift_mode
);
9198 /* We can't simply return zero because there may be an
9206 /* An arithmetic right shift of a quantity known to be -1 or 0
9208 if (code
== ASHIFTRT
9209 && (num_sign_bit_copies (varop
, shift_mode
)
9210 == GET_MODE_BITSIZE (shift_mode
)))
9216 /* If we are doing an arithmetic right shift and discarding all but
9217 the sign bit copies, this is equivalent to doing a shift by the
9218 bitsize minus one. Convert it into that shift because it will often
9219 allow other simplifications. */
9221 if (code
== ASHIFTRT
9222 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9223 >= GET_MODE_BITSIZE (shift_mode
)))
9224 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9226 /* We simplify the tests below and elsewhere by converting
9227 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9228 `make_compound_operation' will convert it to an ASHIFTRT for
9229 those machines (such as VAX) that don't have an LSHIFTRT. */
9230 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9232 && ((nonzero_bits (varop
, shift_mode
)
9233 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9237 if (code
== LSHIFTRT
9238 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9239 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9242 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9243 && !((nonzero_bits (varop
, shift_mode
) << count
)
9244 & GET_MODE_MASK (shift_mode
)))
9247 switch (GET_CODE (varop
))
9253 new = expand_compound_operation (varop
);
9262 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9263 minus the width of a smaller mode, we can do this with a
9264 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9265 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9266 && ! mode_dependent_address_p (XEXP (varop
, 0))
9267 && ! MEM_VOLATILE_P (varop
)
9268 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9269 MODE_INT
, 1)) != BLKmode
)
9271 new = adjust_address_nv (varop
, tmode
,
9272 BYTES_BIG_ENDIAN
? 0
9273 : count
/ BITS_PER_UNIT
);
9275 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9276 : ZERO_EXTEND
, mode
, new);
9283 /* Similar to the case above, except that we can only do this if
9284 the resulting mode is the same as that of the underlying
9285 MEM and adjust the address depending on the *bits* endianness
9286 because of the way that bit-field extract insns are defined. */
9287 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9288 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9289 MODE_INT
, 1)) != BLKmode
9290 && tmode
== GET_MODE (XEXP (varop
, 0)))
9292 if (BITS_BIG_ENDIAN
)
9293 new = XEXP (varop
, 0);
9296 new = copy_rtx (XEXP (varop
, 0));
9297 SUBST (XEXP (new, 0),
9298 plus_constant (XEXP (new, 0),
9299 count
/ BITS_PER_UNIT
));
9302 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9303 : ZERO_EXTEND
, mode
, new);
9310 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9311 the same number of words as what we've seen so far. Then store
9312 the widest mode in MODE. */
9313 if (subreg_lowpart_p (varop
)
9314 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9315 > GET_MODE_SIZE (GET_MODE (varop
)))
9316 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9317 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9320 varop
= SUBREG_REG (varop
);
9321 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9322 mode
= GET_MODE (varop
);
9328 /* Some machines use MULT instead of ASHIFT because MULT
9329 is cheaper. But it is still better on those machines to
9330 merge two shifts into one. */
9331 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9332 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9335 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9336 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9342 /* Similar, for when divides are cheaper. */
9343 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9344 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9347 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9348 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9354 /* If we are extracting just the sign bit of an arithmetic
9355 right shift, that shift is not needed. However, the sign
9356 bit of a wider mode may be different from what would be
9357 interpreted as the sign bit in a narrower mode, so, if
9358 the result is narrower, don't discard the shift. */
9359 if (code
== LSHIFTRT
9360 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9361 && (GET_MODE_BITSIZE (result_mode
)
9362 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9364 varop
= XEXP (varop
, 0);
9368 /* ... fall through ... */
9373 /* Here we have two nested shifts. The result is usually the
9374 AND of a new shift with a mask. We compute the result below. */
9375 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9376 && INTVAL (XEXP (varop
, 1)) >= 0
9377 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9378 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9379 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9381 enum rtx_code first_code
= GET_CODE (varop
);
9382 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9383 unsigned HOST_WIDE_INT mask
;
9386 /* We have one common special case. We can't do any merging if
9387 the inner code is an ASHIFTRT of a smaller mode. However, if
9388 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9389 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9390 we can convert it to
9391 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9392 This simplifies certain SIGN_EXTEND operations. */
9393 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9394 && count
== (unsigned int)
9395 (GET_MODE_BITSIZE (result_mode
)
9396 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9398 /* C3 has the low-order C1 bits zero. */
9400 mask
= (GET_MODE_MASK (mode
)
9401 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9403 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9404 XEXP (varop
, 0), mask
);
9405 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9407 count
= first_count
;
9412 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9413 than C1 high-order bits equal to the sign bit, we can convert
9414 this to either an ASHIFT or an ASHIFTRT depending on the
9417 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9419 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9420 && GET_MODE (varop
) == shift_mode
9421 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9424 varop
= XEXP (varop
, 0);
9426 signed_count
= count
- first_count
;
9427 if (signed_count
< 0)
9428 count
= -signed_count
, code
= ASHIFT
;
9430 count
= signed_count
;
9435 /* There are some cases we can't do. If CODE is ASHIFTRT,
9436 we can only do this if FIRST_CODE is also ASHIFTRT.
9438 We can't do the case when CODE is ROTATE and FIRST_CODE is
9441 If the mode of this shift is not the mode of the outer shift,
9442 we can't do this if either shift is a right shift or ROTATE.
9444 Finally, we can't do any of these if the mode is too wide
9445 unless the codes are the same.
9447 Handle the case where the shift codes are the same
9450 if (code
== first_code
)
9452 if (GET_MODE (varop
) != result_mode
9453 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9457 count
+= first_count
;
9458 varop
= XEXP (varop
, 0);
9462 if (code
== ASHIFTRT
9463 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9464 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9465 || (GET_MODE (varop
) != result_mode
9466 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9467 || first_code
== ROTATE
9468 || code
== ROTATE
)))
9471 /* To compute the mask to apply after the shift, shift the
9472 nonzero bits of the inner shift the same way the
9473 outer shift will. */
9475 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9478 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9481 /* Give up if we can't compute an outer operation to use. */
9483 || GET_CODE (mask_rtx
) != CONST_INT
9484 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9486 result_mode
, &complement_p
))
9489 /* If the shifts are in the same direction, we add the
9490 counts. Otherwise, we subtract them. */
9491 signed_count
= count
;
9492 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9493 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9494 signed_count
+= first_count
;
9496 signed_count
-= first_count
;
9498 /* If COUNT is positive, the new shift is usually CODE,
9499 except for the two exceptions below, in which case it is
9500 FIRST_CODE. If the count is negative, FIRST_CODE should
9502 if (signed_count
> 0
9503 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9504 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9505 code
= first_code
, count
= signed_count
;
9506 else if (signed_count
< 0)
9507 code
= first_code
, count
= -signed_count
;
9509 count
= signed_count
;
9511 varop
= XEXP (varop
, 0);
9515 /* If we have (A << B << C) for any shift, we can convert this to
9516 (A << C << B). This wins if A is a constant. Only try this if
9517 B is not a constant. */
9519 else if (GET_CODE (varop
) == code
9520 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9522 = simplify_binary_operation (code
, mode
,
9526 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9533 /* Make this fit the case below. */
9534 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9535 GEN_INT (GET_MODE_MASK (mode
)));
9541 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9542 with C the size of VAROP - 1 and the shift is logical if
9543 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9544 we have an (le X 0) operation. If we have an arithmetic shift
9545 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9546 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9548 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9549 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9550 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9551 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9552 && count
== (unsigned int)
9553 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9554 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9557 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9560 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9561 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9566 /* If we have (shift (logical)), move the logical to the outside
9567 to allow it to possibly combine with another logical and the
9568 shift to combine with another shift. This also canonicalizes to
9569 what a ZERO_EXTRACT looks like. Also, some machines have
9570 (and (shift)) insns. */
9572 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9573 /* We can't do this if we have (ashiftrt (xor)) and the
9574 constant has its sign bit set in shift_mode. */
9575 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9576 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9578 && (new = simplify_binary_operation (code
, result_mode
,
9580 GEN_INT (count
))) != 0
9581 && GET_CODE (new) == CONST_INT
9582 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9583 INTVAL (new), result_mode
, &complement_p
))
9585 varop
= XEXP (varop
, 0);
9589 /* If we can't do that, try to simplify the shift in each arm of the
9590 logical expression, make a new logical expression, and apply
9591 the inverse distributive law. This also can't be done
9592 for some (ashiftrt (xor)). */
9593 if (code
!= ASHIFTRT
|| GET_CODE (varop
)!= XOR
9594 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9597 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9598 XEXP (varop
, 0), count
);
9599 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9600 XEXP (varop
, 1), count
);
9602 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9603 varop
= apply_distributive_law (varop
);
9610 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9611 says that the sign bit can be tested, FOO has mode MODE, C is
9612 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9613 that may be nonzero. */
9614 if (code
== LSHIFTRT
9615 && XEXP (varop
, 1) == const0_rtx
9616 && GET_MODE (XEXP (varop
, 0)) == result_mode
9617 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9618 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9619 && ((STORE_FLAG_VALUE
9620 & ((HOST_WIDE_INT
) 1
9621 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9622 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9623 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9624 (HOST_WIDE_INT
) 1, result_mode
,
9627 varop
= XEXP (varop
, 0);
9634 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9635 than the number of bits in the mode is equivalent to A. */
9636 if (code
== LSHIFTRT
9637 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9638 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9640 varop
= XEXP (varop
, 0);
9645 /* NEG commutes with ASHIFT since it is multiplication. Move the
9646 NEG outside to allow shifts to combine. */
9648 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9649 (HOST_WIDE_INT
) 0, result_mode
,
9652 varop
= XEXP (varop
, 0);
9658 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9659 is one less than the number of bits in the mode is
9660 equivalent to (xor A 1). */
9661 if (code
== LSHIFTRT
9662 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9663 && XEXP (varop
, 1) == constm1_rtx
9664 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9665 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9666 (HOST_WIDE_INT
) 1, result_mode
,
9670 varop
= XEXP (varop
, 0);
9674 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9675 that might be nonzero in BAR are those being shifted out and those
9676 bits are known zero in FOO, we can replace the PLUS with FOO.
9677 Similarly in the other operand order. This code occurs when
9678 we are computing the size of a variable-size array. */
9680 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9681 && count
< HOST_BITS_PER_WIDE_INT
9682 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9683 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9684 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9686 varop
= XEXP (varop
, 0);
9689 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9690 && count
< HOST_BITS_PER_WIDE_INT
9691 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9692 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9694 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9695 & nonzero_bits (XEXP (varop
, 1),
9698 varop
= XEXP (varop
, 1);
9702 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9704 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9705 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9707 GEN_INT (count
))) != 0
9708 && GET_CODE (new) == CONST_INT
9709 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9710 INTVAL (new), result_mode
, &complement_p
))
9712 varop
= XEXP (varop
, 0);
9718 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9719 with C the size of VAROP - 1 and the shift is logical if
9720 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9721 we have a (gt X 0) operation. If the shift is arithmetic with
9722 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9723 we have a (neg (gt X 0)) operation. */
9725 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9726 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9727 && count
== (unsigned int)
9728 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9729 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9730 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9731 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9733 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9736 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9739 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9740 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9747 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9748 if the truncate does not affect the value. */
9749 if (code
== LSHIFTRT
9750 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9751 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9752 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9753 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9754 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9756 rtx varop_inner
= XEXP (varop
, 0);
9759 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9760 XEXP (varop_inner
, 0),
9762 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9763 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9776 /* We need to determine what mode to do the shift in. If the shift is
9777 a right shift or ROTATE, we must always do it in the mode it was
9778 originally done in. Otherwise, we can do it in MODE, the widest mode
9779 encountered. The code we care about is that of the shift that will
9780 actually be done, not the shift that was originally requested. */
9782 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9783 ? result_mode
: mode
);
9785 /* We have now finished analyzing the shift. The result should be
9786 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9787 OUTER_OP is non-NIL, it is an operation that needs to be applied
9788 to the result of the shift. OUTER_CONST is the relevant constant,
9789 but we must turn off all bits turned off in the shift.
9791 If we were passed a value for X, see if we can use any pieces of
9792 it. If not, make new rtx. */
9794 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9795 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9796 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9797 const_rtx
= XEXP (x
, 1);
9799 const_rtx
= GEN_INT (count
);
9801 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9802 && GET_MODE (XEXP (x
, 0)) == shift_mode
9803 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9804 varop
= XEXP (x
, 0);
9805 else if (GET_MODE (varop
) != shift_mode
)
9806 varop
= gen_lowpart (shift_mode
, varop
);
9808 /* If we can't make the SUBREG, try to return what we were given. */
9809 if (GET_CODE (varop
) == CLOBBER
)
9810 return x
? x
: varop
;
9812 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9816 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9818 /* If we have an outer operation and we just made a shift, it is
9819 possible that we could have simplified the shift were it not
9820 for the outer operation. So try to do the simplification
9823 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9824 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9825 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9826 INTVAL (XEXP (x
, 1)));
9828 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9829 turn off all the bits that the shift would have turned off. */
9830 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9831 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9832 GET_MODE_MASK (result_mode
) >> orig_count
);
9834 /* Do the remainder of the processing in RESULT_MODE. */
9835 x
= gen_lowpart (result_mode
, x
);
9837 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9840 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9842 if (outer_op
!= NIL
)
9844 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9845 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9847 if (outer_op
== AND
)
9848 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9849 else if (outer_op
== SET
)
9850 /* This means that we have determined that the result is
9851 equivalent to a constant. This should be rare. */
9852 x
= GEN_INT (outer_const
);
9853 else if (GET_RTX_CLASS (outer_op
) == '1')
9854 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9856 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9862 /* Like recog, but we receive the address of a pointer to a new pattern.
9863 We try to match the rtx that the pointer points to.
9864 If that fails, we may try to modify or replace the pattern,
9865 storing the replacement into the same pointer object.
9867 Modifications include deletion or addition of CLOBBERs.
9869 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9870 the CLOBBERs are placed.
9872 The value is the final insn code from the pattern ultimately matched,
9876 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9879 int insn_code_number
;
9880 int num_clobbers_to_add
= 0;
9883 rtx old_notes
, old_pat
;
9885 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9886 we use to indicate that something didn't match. If we find such a
9887 thing, force rejection. */
9888 if (GET_CODE (pat
) == PARALLEL
)
9889 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9890 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9891 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9894 old_pat
= PATTERN (insn
);
9895 old_notes
= REG_NOTES (insn
);
9896 PATTERN (insn
) = pat
;
9897 REG_NOTES (insn
) = 0;
9899 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9901 /* If it isn't, there is the possibility that we previously had an insn
9902 that clobbered some register as a side effect, but the combined
9903 insn doesn't need to do that. So try once more without the clobbers
9904 unless this represents an ASM insn. */
9906 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9907 && GET_CODE (pat
) == PARALLEL
)
9911 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9912 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9915 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9919 SUBST_INT (XVECLEN (pat
, 0), pos
);
9922 pat
= XVECEXP (pat
, 0, 0);
9924 PATTERN (insn
) = pat
;
9925 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9927 PATTERN (insn
) = old_pat
;
9928 REG_NOTES (insn
) = old_notes
;
9930 /* Recognize all noop sets, these will be killed by followup pass. */
9931 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9932 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9934 /* If we had any clobbers to add, make a new pattern than contains
9935 them. Then check to make sure that all of them are dead. */
9936 if (num_clobbers_to_add
)
9938 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9939 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9941 + num_clobbers_to_add
)
9942 : num_clobbers_to_add
+ 1));
9944 if (GET_CODE (pat
) == PARALLEL
)
9945 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9946 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9948 XVECEXP (newpat
, 0, 0) = pat
;
9950 add_clobbers (newpat
, insn_code_number
);
9952 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9953 i
< XVECLEN (newpat
, 0); i
++)
9955 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9956 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9958 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9959 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9967 return insn_code_number
;
9970 /* Like gen_lowpart_general but for use by combine. In combine it
9971 is not possible to create any new pseudoregs. However, it is
9972 safe to create invalid memory addresses, because combine will
9973 try to recognize them and all they will do is make the combine
9976 If for some reason this cannot do its job, an rtx
9977 (clobber (const_int 0)) is returned.
9978 An insn containing that will not be recognized. */
9981 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9985 if (GET_MODE (x
) == mode
)
9988 /* Return identity if this is a CONST or symbolic
9991 && (GET_CODE (x
) == CONST
9992 || GET_CODE (x
) == SYMBOL_REF
9993 || GET_CODE (x
) == LABEL_REF
))
9996 /* We can only support MODE being wider than a word if X is a
9997 constant integer or has a mode the same size. */
9999 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10000 && ! ((GET_MODE (x
) == VOIDmode
10001 && (GET_CODE (x
) == CONST_INT
10002 || GET_CODE (x
) == CONST_DOUBLE
))
10003 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10004 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10006 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10007 won't know what to do. So we will strip off the SUBREG here and
10008 process normally. */
10009 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10011 x
= SUBREG_REG (x
);
10012 if (GET_MODE (x
) == mode
)
10016 result
= gen_lowpart_common (mode
, x
);
10017 #ifdef CANNOT_CHANGE_MODE_CLASS
10019 && GET_CODE (result
) == SUBREG
10020 && GET_CODE (SUBREG_REG (result
)) == REG
10021 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10022 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10024 + GET_MODE (result
));
10030 if (GET_CODE (x
) == MEM
)
10034 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10036 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10037 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10039 /* If we want to refer to something bigger than the original memref,
10040 generate a perverse subreg instead. That will force a reload
10041 of the original memref X. */
10042 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10043 return gen_rtx_SUBREG (mode
, x
, 0);
10045 if (WORDS_BIG_ENDIAN
)
10046 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10047 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10049 if (BYTES_BIG_ENDIAN
)
10051 /* Adjust the address so that the address-after-the-data is
10053 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10054 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10057 return adjust_address_nv (x
, mode
, offset
);
10060 /* If X is a comparison operator, rewrite it in a new mode. This
10061 probably won't match, but may allow further simplifications. */
10062 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10063 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10065 /* If we couldn't simplify X any other way, just enclose it in a
10066 SUBREG. Normally, this SUBREG won't match, but some patterns may
10067 include an explicit SUBREG or we may simplify it further in combine. */
10072 enum machine_mode sub_mode
= GET_MODE (x
);
10074 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10075 if (sub_mode
== VOIDmode
)
10077 sub_mode
= int_mode_for_mode (mode
);
10078 x
= gen_lowpart_common (sub_mode
, x
);
10080 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10082 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10085 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10089 /* These routines make binary and unary operations by first seeing if they
10090 fold; if not, a new expression is allocated. */
10093 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10098 if (GET_CODE (op0
) == CLOBBER
)
10100 else if (GET_CODE (op1
) == CLOBBER
)
10103 if (GET_RTX_CLASS (code
) == 'c'
10104 && swap_commutative_operands_p (op0
, op1
))
10105 tem
= op0
, op0
= op1
, op1
= tem
;
10107 if (GET_RTX_CLASS (code
) == '<')
10109 enum machine_mode op_mode
= GET_MODE (op0
);
10111 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10112 just (REL_OP X Y). */
10113 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10115 op1
= XEXP (op0
, 1);
10116 op0
= XEXP (op0
, 0);
10117 op_mode
= GET_MODE (op0
);
10120 if (op_mode
== VOIDmode
)
10121 op_mode
= GET_MODE (op1
);
10122 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10125 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10130 /* Put complex operands first and constants second. */
10131 if (GET_RTX_CLASS (code
) == 'c'
10132 && swap_commutative_operands_p (op0
, op1
))
10133 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10135 /* If we are turning off bits already known off in OP0, we need not do
10137 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10138 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10139 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10142 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10145 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10146 comparison code that will be tested.
10148 The result is a possibly different comparison code to use. *POP0 and
10149 *POP1 may be updated.
10151 It is possible that we might detect that a comparison is either always
10152 true or always false. However, we do not perform general constant
10153 folding in combine, so this knowledge isn't useful. Such tautologies
10154 should have been detected earlier. Hence we ignore all such cases. */
10156 static enum rtx_code
10157 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10163 enum machine_mode mode
, tmode
;
10165 /* Try a few ways of applying the same transformation to both operands. */
10168 #ifndef WORD_REGISTER_OPERATIONS
10169 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10170 so check specially. */
10171 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10172 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10173 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10174 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10175 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10176 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10177 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10178 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10179 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10180 && XEXP (op0
, 1) == XEXP (op1
, 1)
10181 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10182 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10183 && (INTVAL (XEXP (op0
, 1))
10184 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10185 - (GET_MODE_BITSIZE
10186 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10188 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10189 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10193 /* If both operands are the same constant shift, see if we can ignore the
10194 shift. We can if the shift is a rotate or if the bits shifted out of
10195 this shift are known to be zero for both inputs and if the type of
10196 comparison is compatible with the shift. */
10197 if (GET_CODE (op0
) == GET_CODE (op1
)
10198 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10199 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10200 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10201 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10202 || (GET_CODE (op0
) == ASHIFTRT
10203 && (code
!= GTU
&& code
!= LTU
10204 && code
!= GEU
&& code
!= LEU
)))
10205 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10206 && INTVAL (XEXP (op0
, 1)) >= 0
10207 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10208 && XEXP (op0
, 1) == XEXP (op1
, 1))
10210 enum machine_mode mode
= GET_MODE (op0
);
10211 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10212 int shift_count
= INTVAL (XEXP (op0
, 1));
10214 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10215 mask
&= (mask
>> shift_count
) << shift_count
;
10216 else if (GET_CODE (op0
) == ASHIFT
)
10217 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10219 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10220 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10221 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10226 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10227 SUBREGs are of the same mode, and, in both cases, the AND would
10228 be redundant if the comparison was done in the narrower mode,
10229 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10230 and the operand's possibly nonzero bits are 0xffffff01; in that case
10231 if we only care about QImode, we don't need the AND). This case
10232 occurs if the output mode of an scc insn is not SImode and
10233 STORE_FLAG_VALUE == 1 (e.g., the 386).
10235 Similarly, check for a case where the AND's are ZERO_EXTEND
10236 operations from some narrower mode even though a SUBREG is not
10239 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10240 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10241 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10243 rtx inner_op0
= XEXP (op0
, 0);
10244 rtx inner_op1
= XEXP (op1
, 0);
10245 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10246 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10249 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10250 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10251 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10252 && (GET_MODE (SUBREG_REG (inner_op0
))
10253 == GET_MODE (SUBREG_REG (inner_op1
)))
10254 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10255 <= HOST_BITS_PER_WIDE_INT
)
10256 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10257 GET_MODE (SUBREG_REG (inner_op0
)))))
10258 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10259 GET_MODE (SUBREG_REG (inner_op1
))))))
10261 op0
= SUBREG_REG (inner_op0
);
10262 op1
= SUBREG_REG (inner_op1
);
10264 /* The resulting comparison is always unsigned since we masked
10265 off the original sign bit. */
10266 code
= unsigned_condition (code
);
10272 for (tmode
= GET_CLASS_NARROWEST_MODE
10273 (GET_MODE_CLASS (GET_MODE (op0
)));
10274 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10275 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10277 op0
= gen_lowpart (tmode
, inner_op0
);
10278 op1
= gen_lowpart (tmode
, inner_op1
);
10279 code
= unsigned_condition (code
);
10288 /* If both operands are NOT, we can strip off the outer operation
10289 and adjust the comparison code for swapped operands; similarly for
10290 NEG, except that this must be an equality comparison. */
10291 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10292 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10293 && (code
== EQ
|| code
== NE
)))
10294 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10300 /* If the first operand is a constant, swap the operands and adjust the
10301 comparison code appropriately, but don't do this if the second operand
10302 is already a constant integer. */
10303 if (swap_commutative_operands_p (op0
, op1
))
10305 tem
= op0
, op0
= op1
, op1
= tem
;
10306 code
= swap_condition (code
);
10309 /* We now enter a loop during which we will try to simplify the comparison.
10310 For the most part, we only are concerned with comparisons with zero,
10311 but some things may really be comparisons with zero but not start
10312 out looking that way. */
10314 while (GET_CODE (op1
) == CONST_INT
)
10316 enum machine_mode mode
= GET_MODE (op0
);
10317 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10318 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10319 int equality_comparison_p
;
10320 int sign_bit_comparison_p
;
10321 int unsigned_comparison_p
;
10322 HOST_WIDE_INT const_op
;
10324 /* We only want to handle integral modes. This catches VOIDmode,
10325 CCmode, and the floating-point modes. An exception is that we
10326 can handle VOIDmode if OP0 is a COMPARE or a comparison
10329 if (GET_MODE_CLASS (mode
) != MODE_INT
10330 && ! (mode
== VOIDmode
10331 && (GET_CODE (op0
) == COMPARE
10332 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10335 /* Get the constant we are comparing against and turn off all bits
10336 not on in our mode. */
10337 const_op
= INTVAL (op1
);
10338 if (mode
!= VOIDmode
)
10339 const_op
= trunc_int_for_mode (const_op
, mode
);
10340 op1
= GEN_INT (const_op
);
10342 /* If we are comparing against a constant power of two and the value
10343 being compared can only have that single bit nonzero (e.g., it was
10344 `and'ed with that bit), we can replace this with a comparison
10347 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10348 || code
== LT
|| code
== LTU
)
10349 && mode_width
<= HOST_BITS_PER_WIDE_INT
10350 && exact_log2 (const_op
) >= 0
10351 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10353 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10354 op1
= const0_rtx
, const_op
= 0;
10357 /* Similarly, if we are comparing a value known to be either -1 or
10358 0 with -1, change it to the opposite comparison against zero. */
10361 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10362 || code
== GEU
|| code
== LTU
)
10363 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10365 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10366 op1
= const0_rtx
, const_op
= 0;
10369 /* Do some canonicalizations based on the comparison code. We prefer
10370 comparisons against zero and then prefer equality comparisons.
10371 If we can reduce the size of a constant, we will do that too. */
10376 /* < C is equivalent to <= (C - 1) */
10380 op1
= GEN_INT (const_op
);
10382 /* ... fall through to LE case below. */
10388 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10392 op1
= GEN_INT (const_op
);
10396 /* If we are doing a <= 0 comparison on a value known to have
10397 a zero sign bit, we can replace this with == 0. */
10398 else if (const_op
== 0
10399 && mode_width
<= HOST_BITS_PER_WIDE_INT
10400 && (nonzero_bits (op0
, mode
)
10401 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10406 /* >= C is equivalent to > (C - 1). */
10410 op1
= GEN_INT (const_op
);
10412 /* ... fall through to GT below. */
10418 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10422 op1
= GEN_INT (const_op
);
10426 /* If we are doing a > 0 comparison on a value known to have
10427 a zero sign bit, we can replace this with != 0. */
10428 else if (const_op
== 0
10429 && mode_width
<= HOST_BITS_PER_WIDE_INT
10430 && (nonzero_bits (op0
, mode
)
10431 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10436 /* < C is equivalent to <= (C - 1). */
10440 op1
= GEN_INT (const_op
);
10442 /* ... fall through ... */
10445 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10446 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10447 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10449 const_op
= 0, op1
= const0_rtx
;
10457 /* unsigned <= 0 is equivalent to == 0 */
10461 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10462 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10463 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10465 const_op
= 0, op1
= const0_rtx
;
10471 /* >= C is equivalent to < (C - 1). */
10475 op1
= GEN_INT (const_op
);
10477 /* ... fall through ... */
10480 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10481 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10482 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10484 const_op
= 0, op1
= const0_rtx
;
10492 /* unsigned > 0 is equivalent to != 0 */
10496 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10497 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10498 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10500 const_op
= 0, op1
= const0_rtx
;
10509 /* Compute some predicates to simplify code below. */
10511 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10512 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10513 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10516 /* If this is a sign bit comparison and we can do arithmetic in
10517 MODE, say that we will only be needing the sign bit of OP0. */
10518 if (sign_bit_comparison_p
10519 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10520 op0
= force_to_mode (op0
, mode
,
10522 << (GET_MODE_BITSIZE (mode
) - 1)),
10525 /* Now try cases based on the opcode of OP0. If none of the cases
10526 does a "continue", we exit this loop immediately after the
10529 switch (GET_CODE (op0
))
10532 /* If we are extracting a single bit from a variable position in
10533 a constant that has only a single bit set and are comparing it
10534 with zero, we can convert this into an equality comparison
10535 between the position and the location of the single bit. */
10536 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10537 have already reduced the shift count modulo the word size. */
10538 if (!SHIFT_COUNT_TRUNCATED
10539 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10540 && XEXP (op0
, 1) == const1_rtx
10541 && equality_comparison_p
&& const_op
== 0
10542 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10544 if (BITS_BIG_ENDIAN
)
10546 enum machine_mode new_mode
10547 = mode_for_extraction (EP_extzv
, 1);
10548 if (new_mode
== MAX_MACHINE_MODE
)
10549 i
= BITS_PER_WORD
- 1 - i
;
10553 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10557 op0
= XEXP (op0
, 2);
10561 /* Result is nonzero iff shift count is equal to I. */
10562 code
= reverse_condition (code
);
10566 /* ... fall through ... */
10569 tem
= expand_compound_operation (op0
);
10578 /* If testing for equality, we can take the NOT of the constant. */
10579 if (equality_comparison_p
10580 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10582 op0
= XEXP (op0
, 0);
10587 /* If just looking at the sign bit, reverse the sense of the
10589 if (sign_bit_comparison_p
)
10591 op0
= XEXP (op0
, 0);
10592 code
= (code
== GE
? LT
: GE
);
10598 /* If testing for equality, we can take the NEG of the constant. */
10599 if (equality_comparison_p
10600 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10602 op0
= XEXP (op0
, 0);
10607 /* The remaining cases only apply to comparisons with zero. */
10611 /* When X is ABS or is known positive,
10612 (neg X) is < 0 if and only if X != 0. */
10614 if (sign_bit_comparison_p
10615 && (GET_CODE (XEXP (op0
, 0)) == ABS
10616 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10617 && (nonzero_bits (XEXP (op0
, 0), mode
)
10618 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10620 op0
= XEXP (op0
, 0);
10621 code
= (code
== LT
? NE
: EQ
);
10625 /* If we have NEG of something whose two high-order bits are the
10626 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10627 if (num_sign_bit_copies (op0
, mode
) >= 2)
10629 op0
= XEXP (op0
, 0);
10630 code
= swap_condition (code
);
10636 /* If we are testing equality and our count is a constant, we
10637 can perform the inverse operation on our RHS. */
10638 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10639 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10640 op1
, XEXP (op0
, 1))) != 0)
10642 op0
= XEXP (op0
, 0);
10647 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10648 a particular bit. Convert it to an AND of a constant of that
10649 bit. This will be converted into a ZERO_EXTRACT. */
10650 if (const_op
== 0 && sign_bit_comparison_p
10651 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10652 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10654 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10657 - INTVAL (XEXP (op0
, 1)))));
10658 code
= (code
== LT
? NE
: EQ
);
10662 /* Fall through. */
10665 /* ABS is ignorable inside an equality comparison with zero. */
10666 if (const_op
== 0 && equality_comparison_p
)
10668 op0
= XEXP (op0
, 0);
10674 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10675 to (compare FOO CONST) if CONST fits in FOO's mode and we
10676 are either testing inequality or have an unsigned comparison
10677 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10678 if (! unsigned_comparison_p
10679 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10680 <= HOST_BITS_PER_WIDE_INT
)
10681 && ((unsigned HOST_WIDE_INT
) const_op
10682 < (((unsigned HOST_WIDE_INT
) 1
10683 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10685 op0
= XEXP (op0
, 0);
10691 /* Check for the case where we are comparing A - C1 with C2,
10692 both constants are smaller than 1/2 the maximum positive
10693 value in MODE, and the comparison is equality or unsigned.
10694 In that case, if A is either zero-extended to MODE or has
10695 sufficient sign bits so that the high-order bit in MODE
10696 is a copy of the sign in the inner mode, we can prove that it is
10697 safe to do the operation in the wider mode. This simplifies
10698 many range checks. */
10700 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10701 && subreg_lowpart_p (op0
)
10702 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10703 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10704 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10705 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10706 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10707 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10708 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10709 GET_MODE (SUBREG_REG (op0
)))
10710 & ~GET_MODE_MASK (mode
))
10711 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10712 GET_MODE (SUBREG_REG (op0
)))
10714 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10715 - GET_MODE_BITSIZE (mode
)))))
10717 op0
= SUBREG_REG (op0
);
10721 /* If the inner mode is narrower and we are extracting the low part,
10722 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10723 if (subreg_lowpart_p (op0
)
10724 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10725 /* Fall through */ ;
10729 /* ... fall through ... */
10732 if ((unsigned_comparison_p
|| equality_comparison_p
)
10733 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10734 <= HOST_BITS_PER_WIDE_INT
)
10735 && ((unsigned HOST_WIDE_INT
) const_op
10736 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10738 op0
= XEXP (op0
, 0);
10744 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10745 this for equality comparisons due to pathological cases involving
10747 if (equality_comparison_p
10748 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10749 op1
, XEXP (op0
, 1))))
10751 op0
= XEXP (op0
, 0);
10756 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10757 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10758 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10760 op0
= XEXP (XEXP (op0
, 0), 0);
10761 code
= (code
== LT
? EQ
: NE
);
10767 /* We used to optimize signed comparisons against zero, but that
10768 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10769 arrive here as equality comparisons, or (GEU, LTU) are
10770 optimized away. No need to special-case them. */
10772 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10773 (eq B (minus A C)), whichever simplifies. We can only do
10774 this for equality comparisons due to pathological cases involving
10776 if (equality_comparison_p
10777 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10778 XEXP (op0
, 1), op1
)))
10780 op0
= XEXP (op0
, 0);
10785 if (equality_comparison_p
10786 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10787 XEXP (op0
, 0), op1
)))
10789 op0
= XEXP (op0
, 1);
10794 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10795 of bits in X minus 1, is one iff X > 0. */
10796 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10797 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10798 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10800 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10802 op0
= XEXP (op0
, 1);
10803 code
= (code
== GE
? LE
: GT
);
10809 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10810 if C is zero or B is a constant. */
10811 if (equality_comparison_p
10812 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10813 XEXP (op0
, 1), op1
)))
10815 op0
= XEXP (op0
, 0);
10822 case UNEQ
: case LTGT
:
10823 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10824 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10825 case UNORDERED
: case ORDERED
:
10826 /* We can't do anything if OP0 is a condition code value, rather
10827 than an actual data value. */
10829 || CC0_P (XEXP (op0
, 0))
10830 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10833 /* Get the two operands being compared. */
10834 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10835 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10837 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10839 /* Check for the cases where we simply want the result of the
10840 earlier test or the opposite of that result. */
10841 if (code
== NE
|| code
== EQ
10842 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10843 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10844 && (STORE_FLAG_VALUE
10845 & (((HOST_WIDE_INT
) 1
10846 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10847 && (code
== LT
|| code
== GE
)))
10849 enum rtx_code new_code
;
10850 if (code
== LT
|| code
== NE
)
10851 new_code
= GET_CODE (op0
);
10853 new_code
= combine_reversed_comparison_code (op0
);
10855 if (new_code
!= UNKNOWN
)
10866 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10868 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10869 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10870 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10872 op0
= XEXP (op0
, 1);
10873 code
= (code
== GE
? GT
: LE
);
10879 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10880 will be converted to a ZERO_EXTRACT later. */
10881 if (const_op
== 0 && equality_comparison_p
10882 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10883 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10885 op0
= simplify_and_const_int
10886 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10888 XEXP (XEXP (op0
, 0), 1)),
10889 (HOST_WIDE_INT
) 1);
10893 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10894 zero and X is a comparison and C1 and C2 describe only bits set
10895 in STORE_FLAG_VALUE, we can compare with X. */
10896 if (const_op
== 0 && equality_comparison_p
10897 && mode_width
<= HOST_BITS_PER_WIDE_INT
10898 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10899 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10900 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10901 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10902 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10904 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10905 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10906 if ((~STORE_FLAG_VALUE
& mask
) == 0
10907 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10908 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10909 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10911 op0
= XEXP (XEXP (op0
, 0), 0);
10916 /* If we are doing an equality comparison of an AND of a bit equal
10917 to the sign bit, replace this with a LT or GE comparison of
10918 the underlying value. */
10919 if (equality_comparison_p
10921 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10922 && mode_width
<= HOST_BITS_PER_WIDE_INT
10923 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10924 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10926 op0
= XEXP (op0
, 0);
10927 code
= (code
== EQ
? GE
: LT
);
10931 /* If this AND operation is really a ZERO_EXTEND from a narrower
10932 mode, the constant fits within that mode, and this is either an
10933 equality or unsigned comparison, try to do this comparison in
10934 the narrower mode. */
10935 if ((equality_comparison_p
|| unsigned_comparison_p
)
10936 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10937 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10938 & GET_MODE_MASK (mode
))
10940 && const_op
>> i
== 0
10941 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10943 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10947 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10948 fits in both M1 and M2 and the SUBREG is either paradoxical
10949 or represents the low part, permute the SUBREG and the AND
10951 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10953 unsigned HOST_WIDE_INT c1
;
10954 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10955 /* Require an integral mode, to avoid creating something like
10957 if (SCALAR_INT_MODE_P (tmode
)
10958 /* It is unsafe to commute the AND into the SUBREG if the
10959 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10960 not defined. As originally written the upper bits
10961 have a defined value due to the AND operation.
10962 However, if we commute the AND inside the SUBREG then
10963 they no longer have defined values and the meaning of
10964 the code has been changed. */
10966 #ifdef WORD_REGISTER_OPERATIONS
10967 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10968 && mode_width
<= BITS_PER_WORD
)
10970 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10971 && subreg_lowpart_p (XEXP (op0
, 0))))
10972 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10973 && mode_width
<= HOST_BITS_PER_WIDE_INT
10974 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10975 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10976 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10978 && c1
!= GET_MODE_MASK (tmode
))
10980 op0
= gen_binary (AND
, tmode
,
10981 SUBREG_REG (XEXP (op0
, 0)),
10982 gen_int_mode (c1
, tmode
));
10983 op0
= gen_lowpart (mode
, op0
);
10988 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10989 if (const_op
== 0 && equality_comparison_p
10990 && XEXP (op0
, 1) == const1_rtx
10991 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10993 op0
= simplify_and_const_int
10994 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10995 code
= (code
== NE
? EQ
: NE
);
10999 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11000 (eq (and (lshiftrt X) 1) 0).
11001 Also handle the case where (not X) is expressed using xor. */
11002 if (const_op
== 0 && equality_comparison_p
11003 && XEXP (op0
, 1) == const1_rtx
11004 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11006 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11007 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11009 if (GET_CODE (shift_op
) == NOT
11010 || (GET_CODE (shift_op
) == XOR
11011 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
11012 && GET_CODE (shift_count
) == CONST_INT
11013 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11014 && (INTVAL (XEXP (shift_op
, 1))
11015 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11017 op0
= simplify_and_const_int
11019 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11020 (HOST_WIDE_INT
) 1);
11021 code
= (code
== NE
? EQ
: NE
);
11028 /* If we have (compare (ashift FOO N) (const_int C)) and
11029 the high order N bits of FOO (N+1 if an inequality comparison)
11030 are known to be zero, we can do this by comparing FOO with C
11031 shifted right N bits so long as the low-order N bits of C are
11033 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11034 && INTVAL (XEXP (op0
, 1)) >= 0
11035 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11036 < HOST_BITS_PER_WIDE_INT
)
11038 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11039 && mode_width
<= HOST_BITS_PER_WIDE_INT
11040 && (nonzero_bits (XEXP (op0
, 0), mode
)
11041 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11042 + ! equality_comparison_p
))) == 0)
11044 /* We must perform a logical shift, not an arithmetic one,
11045 as we want the top N bits of C to be zero. */
11046 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11048 temp
>>= INTVAL (XEXP (op0
, 1));
11049 op1
= gen_int_mode (temp
, mode
);
11050 op0
= XEXP (op0
, 0);
11054 /* If we are doing a sign bit comparison, it means we are testing
11055 a particular bit. Convert it to the appropriate AND. */
11056 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11057 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11059 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11062 - INTVAL (XEXP (op0
, 1)))));
11063 code
= (code
== LT
? NE
: EQ
);
11067 /* If this an equality comparison with zero and we are shifting
11068 the low bit to the sign bit, we can convert this to an AND of the
11070 if (const_op
== 0 && equality_comparison_p
11071 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11072 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11075 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11076 (HOST_WIDE_INT
) 1);
11082 /* If this is an equality comparison with zero, we can do this
11083 as a logical shift, which might be much simpler. */
11084 if (equality_comparison_p
&& const_op
== 0
11085 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11087 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11089 INTVAL (XEXP (op0
, 1)));
11093 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11094 do the comparison in a narrower mode. */
11095 if (! unsigned_comparison_p
11096 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11097 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11098 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11099 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11100 MODE_INT
, 1)) != BLKmode
11101 && (((unsigned HOST_WIDE_INT
) const_op
11102 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11103 <= GET_MODE_MASK (tmode
)))
11105 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11109 /* Likewise if OP0 is a PLUS of a sign extension with a
11110 constant, which is usually represented with the PLUS
11111 between the shifts. */
11112 if (! unsigned_comparison_p
11113 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11114 && GET_CODE (XEXP (op0
, 0)) == PLUS
11115 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11116 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11117 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11118 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11119 MODE_INT
, 1)) != BLKmode
11120 && (((unsigned HOST_WIDE_INT
) const_op
11121 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11122 <= GET_MODE_MASK (tmode
)))
11124 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11125 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11126 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11129 op0
= gen_binary (PLUS
, tmode
,
11130 gen_lowpart (tmode
, inner
),
11135 /* ... fall through ... */
11137 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11138 the low order N bits of FOO are known to be zero, we can do this
11139 by comparing FOO with C shifted left N bits so long as no
11140 overflow occurs. */
11141 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11142 && INTVAL (XEXP (op0
, 1)) >= 0
11143 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11144 && mode_width
<= HOST_BITS_PER_WIDE_INT
11145 && (nonzero_bits (XEXP (op0
, 0), mode
)
11146 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11147 && (((unsigned HOST_WIDE_INT
) const_op
11148 + (GET_CODE (op0
) != LSHIFTRT
11149 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11152 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11154 /* If the shift was logical, then we must make the condition
11156 if (GET_CODE (op0
) == LSHIFTRT
)
11157 code
= unsigned_condition (code
);
11159 const_op
<<= INTVAL (XEXP (op0
, 1));
11160 op1
= GEN_INT (const_op
);
11161 op0
= XEXP (op0
, 0);
11165 /* If we are using this shift to extract just the sign bit, we
11166 can replace this with an LT or GE comparison. */
11168 && (equality_comparison_p
|| sign_bit_comparison_p
)
11169 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11170 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11173 op0
= XEXP (op0
, 0);
11174 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11186 /* Now make any compound operations involved in this comparison. Then,
11187 check for an outmost SUBREG on OP0 that is not doing anything or is
11188 paradoxical. The latter transformation must only be performed when
11189 it is known that the "extra" bits will be the same in op0 and op1 or
11190 that they don't matter. There are three cases to consider:
11192 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11193 care bits and we can assume they have any convenient value. So
11194 making the transformation is safe.
11196 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11197 In this case the upper bits of op0 are undefined. We should not make
11198 the simplification in that case as we do not know the contents of
11201 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11202 NIL. In that case we know those bits are zeros or ones. We must
11203 also be sure that they are the same as the upper bits of op1.
11205 We can never remove a SUBREG for a non-equality comparison because
11206 the sign bit is in a different place in the underlying object. */
11208 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11209 op1
= make_compound_operation (op1
, SET
);
11211 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11212 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11213 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11214 && (code
== NE
|| code
== EQ
))
11216 if (GET_MODE_SIZE (GET_MODE (op0
))
11217 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11219 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11221 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11223 op0
= SUBREG_REG (op0
);
11224 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11227 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11228 <= HOST_BITS_PER_WIDE_INT
)
11229 && (nonzero_bits (SUBREG_REG (op0
),
11230 GET_MODE (SUBREG_REG (op0
)))
11231 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11233 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11235 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11236 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11237 op0
= SUBREG_REG (op0
), op1
= tem
;
11241 /* We now do the opposite procedure: Some machines don't have compare
11242 insns in all modes. If OP0's mode is an integer mode smaller than a
11243 word and we can't do a compare in that mode, see if there is a larger
11244 mode for which we can do the compare. There are a number of cases in
11245 which we can use the wider mode. */
11247 mode
= GET_MODE (op0
);
11248 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11249 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11250 && ! have_insn_for (COMPARE
, mode
))
11251 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11253 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11254 tmode
= GET_MODE_WIDER_MODE (tmode
))
11255 if (have_insn_for (COMPARE
, tmode
))
11259 /* If the only nonzero bits in OP0 and OP1 are those in the
11260 narrower mode and this is an equality or unsigned comparison,
11261 we can use the wider mode. Similarly for sign-extended
11262 values, in which case it is true for all comparisons. */
11263 zero_extended
= ((code
== EQ
|| code
== NE
11264 || code
== GEU
|| code
== GTU
11265 || code
== LEU
|| code
== LTU
)
11266 && (nonzero_bits (op0
, tmode
)
11267 & ~GET_MODE_MASK (mode
)) == 0
11268 && ((GET_CODE (op1
) == CONST_INT
11269 || (nonzero_bits (op1
, tmode
)
11270 & ~GET_MODE_MASK (mode
)) == 0)));
11273 || ((num_sign_bit_copies (op0
, tmode
)
11274 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11275 - GET_MODE_BITSIZE (mode
)))
11276 && (num_sign_bit_copies (op1
, tmode
)
11277 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11278 - GET_MODE_BITSIZE (mode
)))))
11280 /* If OP0 is an AND and we don't have an AND in MODE either,
11281 make a new AND in the proper mode. */
11282 if (GET_CODE (op0
) == AND
11283 && !have_insn_for (AND
, mode
))
11284 op0
= gen_binary (AND
, tmode
,
11285 gen_lowpart (tmode
,
11287 gen_lowpart (tmode
,
11290 op0
= gen_lowpart (tmode
, op0
);
11291 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11292 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11293 op1
= gen_lowpart (tmode
, op1
);
11297 /* If this is a test for negative, we can make an explicit
11298 test of the sign bit. */
11300 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11301 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11303 op0
= gen_binary (AND
, tmode
,
11304 gen_lowpart (tmode
, op0
),
11305 GEN_INT ((HOST_WIDE_INT
) 1
11306 << (GET_MODE_BITSIZE (mode
) - 1)));
11307 code
= (code
== LT
) ? NE
: EQ
;
11312 #ifdef CANONICALIZE_COMPARISON
11313 /* If this machine only supports a subset of valid comparisons, see if we
11314 can convert an unsupported one into a supported one. */
11315 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11324 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11325 searching backward. */
11326 static enum rtx_code
11327 combine_reversed_comparison_code (rtx exp
)
11329 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11332 if (code1
!= UNKNOWN
11333 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11335 /* Otherwise try and find where the condition codes were last set and
11337 x
= get_last_value (XEXP (exp
, 0));
11338 if (!x
|| GET_CODE (x
) != COMPARE
)
11340 return reversed_comparison_code_parts (GET_CODE (exp
),
11341 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11344 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11345 Return NULL_RTX in case we fail to do the reversal. */
11347 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11349 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11350 if (reversed_code
== UNKNOWN
)
11353 return gen_binary (reversed_code
, mode
, op0
, op1
);
11356 /* Utility function for following routine. Called when X is part of a value
11357 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11358 for each register mentioned. Similar to mention_regs in cse.c */
11361 update_table_tick (rtx x
)
11363 enum rtx_code code
= GET_CODE (x
);
11364 const char *fmt
= GET_RTX_FORMAT (code
);
11369 unsigned int regno
= REGNO (x
);
11370 unsigned int endregno
11371 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11372 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11375 for (r
= regno
; r
< endregno
; r
++)
11376 reg_last_set_table_tick
[r
] = label_tick
;
11381 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11382 /* Note that we can't have an "E" in values stored; see
11383 get_last_value_validate. */
11386 /* Check for identical subexpressions. If x contains
11387 identical subexpression we only have to traverse one of
11390 && (GET_RTX_CLASS (code
) == '2'
11391 || GET_RTX_CLASS (code
) == 'c'))
11393 /* Note that at this point x1 has already been
11395 rtx x0
= XEXP (x
, 0);
11396 rtx x1
= XEXP (x
, 1);
11398 /* If x0 and x1 are identical then there is no need to
11403 /* If x0 is identical to a subexpression of x1 then while
11404 processing x1, x0 has already been processed. Thus we
11405 are done with x. */
11406 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11407 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11408 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11411 /* If x1 is identical to a subexpression of x0 then we
11412 still have to process the rest of x0. */
11413 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11414 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11415 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11417 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11422 update_table_tick (XEXP (x
, i
));
11426 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11427 are saying that the register is clobbered and we no longer know its
11428 value. If INSN is zero, don't update reg_last_set; this is only permitted
11429 with VALUE also zero and is used to invalidate the register. */
11432 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11434 unsigned int regno
= REGNO (reg
);
11435 unsigned int endregno
11436 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11437 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
11440 /* If VALUE contains REG and we have a previous value for REG, substitute
11441 the previous value. */
11442 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11446 /* Set things up so get_last_value is allowed to see anything set up to
11448 subst_low_cuid
= INSN_CUID (insn
);
11449 tem
= get_last_value (reg
);
11451 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11452 it isn't going to be useful and will take a lot of time to process,
11453 so just use the CLOBBER. */
11457 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11458 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11459 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11460 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11461 tem
= XEXP (tem
, 0);
11463 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11467 /* For each register modified, show we don't know its value, that
11468 we don't know about its bitwise content, that its value has been
11469 updated, and that we don't know the location of the death of the
11471 for (i
= regno
; i
< endregno
; i
++)
11474 reg_last_set
[i
] = insn
;
11476 reg_last_set_value
[i
] = 0;
11477 reg_last_set_mode
[i
] = 0;
11478 reg_last_set_nonzero_bits
[i
] = 0;
11479 reg_last_set_sign_bit_copies
[i
] = 0;
11480 reg_last_death
[i
] = 0;
11483 /* Mark registers that are being referenced in this value. */
11485 update_table_tick (value
);
11487 /* Now update the status of each register being set.
11488 If someone is using this register in this block, set this register
11489 to invalid since we will get confused between the two lives in this
11490 basic block. This makes using this register always invalid. In cse, we
11491 scan the table to invalidate all entries using this register, but this
11492 is too much work for us. */
11494 for (i
= regno
; i
< endregno
; i
++)
11496 reg_last_set_label
[i
] = label_tick
;
11497 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11498 reg_last_set_invalid
[i
] = 1;
11500 reg_last_set_invalid
[i
] = 0;
11503 /* The value being assigned might refer to X (like in "x++;"). In that
11504 case, we must replace it with (clobber (const_int 0)) to prevent
11506 if (value
&& ! get_last_value_validate (&value
, insn
,
11507 reg_last_set_label
[regno
], 0))
11509 value
= copy_rtx (value
);
11510 if (! get_last_value_validate (&value
, insn
,
11511 reg_last_set_label
[regno
], 1))
11515 /* For the main register being modified, update the value, the mode, the
11516 nonzero bits, and the number of sign bit copies. */
11518 reg_last_set_value
[regno
] = value
;
11522 enum machine_mode mode
= GET_MODE (reg
);
11523 subst_low_cuid
= INSN_CUID (insn
);
11524 reg_last_set_mode
[regno
] = mode
;
11525 if (GET_MODE_CLASS (mode
) == MODE_INT
11526 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11527 mode
= nonzero_bits_mode
;
11528 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11529 reg_last_set_sign_bit_copies
[regno
]
11530 = num_sign_bit_copies (value
, GET_MODE (reg
));
11534 /* Called via note_stores from record_dead_and_set_regs to handle one
11535 SET or CLOBBER in an insn. DATA is the instruction in which the
11536 set is occurring. */
11539 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11541 rtx record_dead_insn
= (rtx
) data
;
11543 if (GET_CODE (dest
) == SUBREG
)
11544 dest
= SUBREG_REG (dest
);
11546 if (GET_CODE (dest
) == REG
)
11548 /* If we are setting the whole register, we know its value. Otherwise
11549 show that we don't know the value. We can handle SUBREG in
11551 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11552 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11553 else if (GET_CODE (setter
) == SET
11554 && GET_CODE (SET_DEST (setter
)) == SUBREG
11555 && SUBREG_REG (SET_DEST (setter
)) == dest
11556 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11557 && subreg_lowpart_p (SET_DEST (setter
)))
11558 record_value_for_reg (dest
, record_dead_insn
,
11559 gen_lowpart (GET_MODE (dest
),
11560 SET_SRC (setter
)));
11562 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11564 else if (GET_CODE (dest
) == MEM
11565 /* Ignore pushes, they clobber nothing. */
11566 && ! push_operand (dest
, GET_MODE (dest
)))
11567 mem_last_set
= INSN_CUID (record_dead_insn
);
11570 /* Update the records of when each REG was most recently set or killed
11571 for the things done by INSN. This is the last thing done in processing
11572 INSN in the combiner loop.
11574 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11575 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11576 and also the similar information mem_last_set (which insn most recently
11577 modified memory) and last_call_cuid (which insn was the most recent
11578 subroutine call). */
11581 record_dead_and_set_regs (rtx insn
)
11586 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11588 if (REG_NOTE_KIND (link
) == REG_DEAD
11589 && GET_CODE (XEXP (link
, 0)) == REG
)
11591 unsigned int regno
= REGNO (XEXP (link
, 0));
11592 unsigned int endregno
11593 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11594 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11597 for (i
= regno
; i
< endregno
; i
++)
11598 reg_last_death
[i
] = insn
;
11600 else if (REG_NOTE_KIND (link
) == REG_INC
)
11601 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11604 if (GET_CODE (insn
) == CALL_INSN
)
11606 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11607 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11609 reg_last_set_value
[i
] = 0;
11610 reg_last_set_mode
[i
] = 0;
11611 reg_last_set_nonzero_bits
[i
] = 0;
11612 reg_last_set_sign_bit_copies
[i
] = 0;
11613 reg_last_death
[i
] = 0;
11616 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11618 /* Don't bother recording what this insn does. It might set the
11619 return value register, but we can't combine into a call
11620 pattern anyway, so there's no point trying (and it may cause
11621 a crash, if e.g. we wind up asking for last_set_value of a
11622 SUBREG of the return value register). */
11626 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11629 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11630 register present in the SUBREG, so for each such SUBREG go back and
11631 adjust nonzero and sign bit information of the registers that are
11632 known to have some zero/sign bits set.
11634 This is needed because when combine blows the SUBREGs away, the
11635 information on zero/sign bits is lost and further combines can be
11636 missed because of that. */
11639 record_promoted_value (rtx insn
, rtx subreg
)
11642 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11643 enum machine_mode mode
= GET_MODE (subreg
);
11645 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11648 for (links
= LOG_LINKS (insn
); links
;)
11650 insn
= XEXP (links
, 0);
11651 set
= single_set (insn
);
11653 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11654 || REGNO (SET_DEST (set
)) != regno
11655 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11657 links
= XEXP (links
, 1);
11661 if (reg_last_set
[regno
] == insn
)
11663 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11664 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11667 if (GET_CODE (SET_SRC (set
)) == REG
)
11669 regno
= REGNO (SET_SRC (set
));
11670 links
= LOG_LINKS (insn
);
11677 /* Scan X for promoted SUBREGs. For each one found,
11678 note what it implies to the registers used in it. */
11681 check_promoted_subreg (rtx insn
, rtx x
)
11683 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11684 && GET_CODE (SUBREG_REG (x
)) == REG
)
11685 record_promoted_value (insn
, x
);
11688 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11691 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11695 check_promoted_subreg (insn
, XEXP (x
, i
));
11699 if (XVEC (x
, i
) != 0)
11700 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11701 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11707 /* Utility routine for the following function. Verify that all the registers
11708 mentioned in *LOC are valid when *LOC was part of a value set when
11709 label_tick == TICK. Return 0 if some are not.
11711 If REPLACE is nonzero, replace the invalid reference with
11712 (clobber (const_int 0)) and return 1. This replacement is useful because
11713 we often can get useful information about the form of a value (e.g., if
11714 it was produced by a shift that always produces -1 or 0) even though
11715 we don't know exactly what registers it was produced from. */
11718 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11721 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11722 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11725 if (GET_CODE (x
) == REG
)
11727 unsigned int regno
= REGNO (x
);
11728 unsigned int endregno
11729 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11730 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11733 for (j
= regno
; j
< endregno
; j
++)
11734 if (reg_last_set_invalid
[j
]
11735 /* If this is a pseudo-register that was only set once and not
11736 live at the beginning of the function, it is always valid. */
11737 || (! (regno
>= FIRST_PSEUDO_REGISTER
11738 && REG_N_SETS (regno
) == 1
11739 && (! REGNO_REG_SET_P
11740 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11741 && reg_last_set_label
[j
] > tick
))
11744 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11750 /* If this is a memory reference, make sure that there were
11751 no stores after it that might have clobbered the value. We don't
11752 have alias info, so we assume any store invalidates it. */
11753 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11754 && INSN_CUID (insn
) <= mem_last_set
)
11757 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11761 for (i
= 0; i
< len
; i
++)
11765 /* Check for identical subexpressions. If x contains
11766 identical subexpression we only have to traverse one of
11769 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11770 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11772 /* Note that at this point x0 has already been checked
11773 and found valid. */
11774 rtx x0
= XEXP (x
, 0);
11775 rtx x1
= XEXP (x
, 1);
11777 /* If x0 and x1 are identical then x is also valid. */
11781 /* If x1 is identical to a subexpression of x0 then
11782 while checking x0, x1 has already been checked. Thus
11783 it is valid and so as x. */
11784 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11785 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11786 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11789 /* If x0 is identical to a subexpression of x1 then x is
11790 valid iff the rest of x1 is valid. */
11791 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11792 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11793 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11795 get_last_value_validate (&XEXP (x1
,
11796 x0
== XEXP (x1
, 0) ? 1 : 0),
11797 insn
, tick
, replace
);
11800 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11804 /* Don't bother with these. They shouldn't occur anyway. */
11805 else if (fmt
[i
] == 'E')
11809 /* If we haven't found a reason for it to be invalid, it is valid. */
11813 /* Get the last value assigned to X, if known. Some registers
11814 in the value may be replaced with (clobber (const_int 0)) if their value
11815 is known longer known reliably. */
11818 get_last_value (rtx x
)
11820 unsigned int regno
;
11823 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11824 then convert it to the desired mode. If this is a paradoxical SUBREG,
11825 we cannot predict what values the "extra" bits might have. */
11826 if (GET_CODE (x
) == SUBREG
11827 && subreg_lowpart_p (x
)
11828 && (GET_MODE_SIZE (GET_MODE (x
))
11829 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11830 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11831 return gen_lowpart (GET_MODE (x
), value
);
11833 if (GET_CODE (x
) != REG
)
11837 value
= reg_last_set_value
[regno
];
11839 /* If we don't have a value, or if it isn't for this basic block and
11840 it's either a hard register, set more than once, or it's a live
11841 at the beginning of the function, return 0.
11843 Because if it's not live at the beginning of the function then the reg
11844 is always set before being used (is never used without being set).
11845 And, if it's set only once, and it's always set before use, then all
11846 uses must have the same last value, even if it's not from this basic
11850 || (reg_last_set_label
[regno
] != label_tick
11851 && (regno
< FIRST_PSEUDO_REGISTER
11852 || REG_N_SETS (regno
) != 1
11853 || (REGNO_REG_SET_P
11854 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11857 /* If the value was set in a later insn than the ones we are processing,
11858 we can't use it even if the register was only set once. */
11859 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11862 /* If the value has all its registers valid, return it. */
11863 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11864 reg_last_set_label
[regno
], 0))
11867 /* Otherwise, make a copy and replace any invalid register with
11868 (clobber (const_int 0)). If that fails for some reason, return 0. */
11870 value
= copy_rtx (value
);
11871 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11872 reg_last_set_label
[regno
], 1))
11878 /* Return nonzero if expression X refers to a REG or to memory
11879 that is set in an instruction more recent than FROM_CUID. */
11882 use_crosses_set_p (rtx x
, int from_cuid
)
11886 enum rtx_code code
= GET_CODE (x
);
11890 unsigned int regno
= REGNO (x
);
11891 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11892 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11894 #ifdef PUSH_ROUNDING
11895 /* Don't allow uses of the stack pointer to be moved,
11896 because we don't know whether the move crosses a push insn. */
11897 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11900 for (; regno
< endreg
; regno
++)
11901 if (reg_last_set
[regno
]
11902 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11907 if (code
== MEM
&& mem_last_set
> from_cuid
)
11910 fmt
= GET_RTX_FORMAT (code
);
11912 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11917 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11918 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11921 else if (fmt
[i
] == 'e'
11922 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11928 /* Define three variables used for communication between the following
11931 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11932 static int reg_dead_flag
;
11934 /* Function called via note_stores from reg_dead_at_p.
11936 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11937 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11940 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11942 unsigned int regno
, endregno
;
11944 if (GET_CODE (dest
) != REG
)
11947 regno
= REGNO (dest
);
11948 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11949 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11951 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11952 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11955 /* Return nonzero if REG is known to be dead at INSN.
11957 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11958 referencing REG, it is dead. If we hit a SET referencing REG, it is
11959 live. Otherwise, see if it is live or dead at the start of the basic
11960 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11961 must be assumed to be always live. */
11964 reg_dead_at_p (rtx reg
, rtx insn
)
11969 /* Set variables for reg_dead_at_p_1. */
11970 reg_dead_regno
= REGNO (reg
);
11971 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11972 ? hard_regno_nregs
[reg_dead_regno
]
11978 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11979 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11981 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11982 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11986 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11987 beginning of function. */
11988 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11989 insn
= prev_nonnote_insn (insn
))
11991 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11993 return reg_dead_flag
== 1 ? 1 : 0;
11995 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11999 /* Get the basic block that we were in. */
12001 block
= ENTRY_BLOCK_PTR
->next_bb
;
12004 FOR_EACH_BB (block
)
12005 if (insn
== BB_HEAD (block
))
12008 if (block
== EXIT_BLOCK_PTR
)
12012 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12013 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12019 /* Note hard registers in X that are used. This code is similar to
12020 that in flow.c, but much simpler since we don't care about pseudos. */
12023 mark_used_regs_combine (rtx x
)
12025 RTX_CODE code
= GET_CODE (x
);
12026 unsigned int regno
;
12039 case ADDR_DIFF_VEC
:
12042 /* CC0 must die in the insn after it is set, so we don't need to take
12043 special note of it here. */
12049 /* If we are clobbering a MEM, mark any hard registers inside the
12050 address as used. */
12051 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12052 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12057 /* A hard reg in a wide mode may really be multiple registers.
12058 If so, mark all of them just like the first. */
12059 if (regno
< FIRST_PSEUDO_REGISTER
)
12061 unsigned int endregno
, r
;
12063 /* None of this applies to the stack, frame or arg pointers. */
12064 if (regno
== STACK_POINTER_REGNUM
12065 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12066 || regno
== HARD_FRAME_POINTER_REGNUM
12068 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12069 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12071 || regno
== FRAME_POINTER_REGNUM
)
12074 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12075 for (r
= regno
; r
< endregno
; r
++)
12076 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12082 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12084 rtx testreg
= SET_DEST (x
);
12086 while (GET_CODE (testreg
) == SUBREG
12087 || GET_CODE (testreg
) == ZERO_EXTRACT
12088 || GET_CODE (testreg
) == SIGN_EXTRACT
12089 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12090 testreg
= XEXP (testreg
, 0);
12092 if (GET_CODE (testreg
) == MEM
)
12093 mark_used_regs_combine (XEXP (testreg
, 0));
12095 mark_used_regs_combine (SET_SRC (x
));
12103 /* Recursively scan the operands of this expression. */
12106 const char *fmt
= GET_RTX_FORMAT (code
);
12108 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12111 mark_used_regs_combine (XEXP (x
, i
));
12112 else if (fmt
[i
] == 'E')
12116 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12117 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12123 /* Remove register number REGNO from the dead registers list of INSN.
12125 Return the note used to record the death, if there was one. */
12128 remove_death (unsigned int regno
, rtx insn
)
12130 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12134 REG_N_DEATHS (regno
)--;
12135 remove_note (insn
, note
);
12141 /* For each register (hardware or pseudo) used within expression X, if its
12142 death is in an instruction with cuid between FROM_CUID (inclusive) and
12143 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12144 list headed by PNOTES.
12146 That said, don't move registers killed by maybe_kill_insn.
12148 This is done when X is being merged by combination into TO_INSN. These
12149 notes will then be distributed as needed. */
12152 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12157 enum rtx_code code
= GET_CODE (x
);
12161 unsigned int regno
= REGNO (x
);
12162 rtx where_dead
= reg_last_death
[regno
];
12163 rtx before_dead
, after_dead
;
12165 /* Don't move the register if it gets killed in between from and to. */
12166 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12167 && ! reg_referenced_p (x
, maybe_kill_insn
))
12170 /* WHERE_DEAD could be a USE insn made by combine, so first we
12171 make sure that we have insns with valid INSN_CUID values. */
12172 before_dead
= where_dead
;
12173 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12174 before_dead
= PREV_INSN (before_dead
);
12176 after_dead
= where_dead
;
12177 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12178 after_dead
= NEXT_INSN (after_dead
);
12180 if (before_dead
&& after_dead
12181 && INSN_CUID (before_dead
) >= from_cuid
12182 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12183 || (where_dead
!= after_dead
12184 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12186 rtx note
= remove_death (regno
, where_dead
);
12188 /* It is possible for the call above to return 0. This can occur
12189 when reg_last_death points to I2 or I1 that we combined with.
12190 In that case make a new note.
12192 We must also check for the case where X is a hard register
12193 and NOTE is a death note for a range of hard registers
12194 including X. In that case, we must put REG_DEAD notes for
12195 the remaining registers in place of NOTE. */
12197 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12198 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12199 > GET_MODE_SIZE (GET_MODE (x
))))
12201 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12202 unsigned int deadend
12203 = (deadregno
+ hard_regno_nregs
[deadregno
]
12204 [GET_MODE (XEXP (note
, 0))]);
12205 unsigned int ourend
12206 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12209 for (i
= deadregno
; i
< deadend
; i
++)
12210 if (i
< regno
|| i
>= ourend
)
12211 REG_NOTES (where_dead
)
12212 = gen_rtx_EXPR_LIST (REG_DEAD
,
12214 REG_NOTES (where_dead
));
12217 /* If we didn't find any note, or if we found a REG_DEAD note that
12218 covers only part of the given reg, and we have a multi-reg hard
12219 register, then to be safe we must check for REG_DEAD notes
12220 for each register other than the first. They could have
12221 their own REG_DEAD notes lying around. */
12222 else if ((note
== 0
12224 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12225 < GET_MODE_SIZE (GET_MODE (x
)))))
12226 && regno
< FIRST_PSEUDO_REGISTER
12227 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12229 unsigned int ourend
12230 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12231 unsigned int i
, offset
;
12235 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12239 for (i
= regno
+ offset
; i
< ourend
; i
++)
12240 move_deaths (regno_reg_rtx
[i
],
12241 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12244 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12246 XEXP (note
, 1) = *pnotes
;
12250 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12252 REG_N_DEATHS (regno
)++;
12258 else if (GET_CODE (x
) == SET
)
12260 rtx dest
= SET_DEST (x
);
12262 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12264 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12265 that accesses one word of a multi-word item, some
12266 piece of everything register in the expression is used by
12267 this insn, so remove any old death. */
12268 /* ??? So why do we test for equality of the sizes? */
12270 if (GET_CODE (dest
) == ZERO_EXTRACT
12271 || GET_CODE (dest
) == STRICT_LOW_PART
12272 || (GET_CODE (dest
) == SUBREG
12273 && (((GET_MODE_SIZE (GET_MODE (dest
))
12274 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12275 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12276 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12278 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12282 /* If this is some other SUBREG, we know it replaces the entire
12283 value, so use that as the destination. */
12284 if (GET_CODE (dest
) == SUBREG
)
12285 dest
= SUBREG_REG (dest
);
12287 /* If this is a MEM, adjust deaths of anything used in the address.
12288 For a REG (the only other possibility), the entire value is
12289 being replaced so the old value is not used in this insn. */
12291 if (GET_CODE (dest
) == MEM
)
12292 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12297 else if (GET_CODE (x
) == CLOBBER
)
12300 len
= GET_RTX_LENGTH (code
);
12301 fmt
= GET_RTX_FORMAT (code
);
12303 for (i
= 0; i
< len
; i
++)
12308 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12309 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12312 else if (fmt
[i
] == 'e')
12313 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12317 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12318 pattern of an insn. X must be a REG. */
12321 reg_bitfield_target_p (rtx x
, rtx body
)
12325 if (GET_CODE (body
) == SET
)
12327 rtx dest
= SET_DEST (body
);
12329 unsigned int regno
, tregno
, endregno
, endtregno
;
12331 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12332 target
= XEXP (dest
, 0);
12333 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12334 target
= SUBREG_REG (XEXP (dest
, 0));
12338 if (GET_CODE (target
) == SUBREG
)
12339 target
= SUBREG_REG (target
);
12341 if (GET_CODE (target
) != REG
)
12344 tregno
= REGNO (target
), regno
= REGNO (x
);
12345 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12346 return target
== x
;
12348 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
12349 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
12351 return endregno
> tregno
&& regno
< endtregno
;
12354 else if (GET_CODE (body
) == PARALLEL
)
12355 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12356 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12362 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12363 as appropriate. I3 and I2 are the insns resulting from the combination
12364 insns including FROM (I2 may be zero).
12366 Each note in the list is either ignored or placed on some insns, depending
12367 on the type of note. */
12370 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12372 rtx note
, next_note
;
12375 for (note
= notes
; note
; note
= next_note
)
12377 rtx place
= 0, place2
= 0;
12379 /* If this NOTE references a pseudo register, ensure it references
12380 the latest copy of that register. */
12381 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12382 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12383 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12385 next_note
= XEXP (note
, 1);
12386 switch (REG_NOTE_KIND (note
))
12390 /* Doesn't matter much where we put this, as long as it's somewhere.
12391 It is preferable to keep these notes on branches, which is most
12392 likely to be i3. */
12396 case REG_VALUE_PROFILE
:
12397 /* Just get rid of this note, as it is unused later anyway. */
12400 case REG_VTABLE_REF
:
12401 /* ??? Should remain with *a particular* memory load. Given the
12402 nature of vtable data, the last insn seems relatively safe. */
12406 case REG_NON_LOCAL_GOTO
:
12407 if (GET_CODE (i3
) == JUMP_INSN
)
12409 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12415 case REG_EH_REGION
:
12416 /* These notes must remain with the call or trapping instruction. */
12417 if (GET_CODE (i3
) == CALL_INSN
)
12419 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12421 else if (flag_non_call_exceptions
)
12423 if (may_trap_p (i3
))
12425 else if (i2
&& may_trap_p (i2
))
12427 /* ??? Otherwise assume we've combined things such that we
12428 can now prove that the instructions can't trap. Drop the
12429 note in this case. */
12435 case REG_ALWAYS_RETURN
:
12438 /* These notes must remain with the call. It should not be
12439 possible for both I2 and I3 to be a call. */
12440 if (GET_CODE (i3
) == CALL_INSN
)
12442 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12449 /* Any clobbers for i3 may still exist, and so we must process
12450 REG_UNUSED notes from that insn.
12452 Any clobbers from i2 or i1 can only exist if they were added by
12453 recog_for_combine. In that case, recog_for_combine created the
12454 necessary REG_UNUSED notes. Trying to keep any original
12455 REG_UNUSED notes from these insns can cause incorrect output
12456 if it is for the same register as the original i3 dest.
12457 In that case, we will notice that the register is set in i3,
12458 and then add a REG_UNUSED note for the destination of i3, which
12459 is wrong. However, it is possible to have REG_UNUSED notes from
12460 i2 or i1 for register which were both used and clobbered, so
12461 we keep notes from i2 or i1 if they will turn into REG_DEAD
12464 /* If this register is set or clobbered in I3, put the note there
12465 unless there is one already. */
12466 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12468 if (from_insn
!= i3
)
12471 if (! (GET_CODE (XEXP (note
, 0)) == REG
12472 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12473 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12476 /* Otherwise, if this register is used by I3, then this register
12477 now dies here, so we must put a REG_DEAD note here unless there
12479 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12480 && ! (GET_CODE (XEXP (note
, 0)) == REG
12481 ? find_regno_note (i3
, REG_DEAD
,
12482 REGNO (XEXP (note
, 0)))
12483 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12485 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12493 /* These notes say something about results of an insn. We can
12494 only support them if they used to be on I3 in which case they
12495 remain on I3. Otherwise they are ignored.
12497 If the note refers to an expression that is not a constant, we
12498 must also ignore the note since we cannot tell whether the
12499 equivalence is still true. It might be possible to do
12500 slightly better than this (we only have a problem if I2DEST
12501 or I1DEST is present in the expression), but it doesn't
12502 seem worth the trouble. */
12504 if (from_insn
== i3
12505 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12510 case REG_NO_CONFLICT
:
12511 /* These notes say something about how a register is used. They must
12512 be present on any use of the register in I2 or I3. */
12513 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12516 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12526 /* This can show up in several ways -- either directly in the
12527 pattern, or hidden off in the constant pool with (or without?)
12528 a REG_EQUAL note. */
12529 /* ??? Ignore the without-reg_equal-note problem for now. */
12530 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12531 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12532 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12533 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12537 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12538 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12539 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12540 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12548 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12549 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12550 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12552 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12554 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12555 LABEL_NUSES (JUMP_LABEL (place
))--;
12558 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12560 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12562 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12563 LABEL_NUSES (JUMP_LABEL (place2
))--;
12569 /* This note says something about the value of a register prior
12570 to the execution of an insn. It is too much trouble to see
12571 if the note is still correct in all situations. It is better
12572 to simply delete it. */
12576 /* If the insn previously containing this note still exists,
12577 put it back where it was. Otherwise move it to the previous
12578 insn. Adjust the corresponding REG_LIBCALL note. */
12579 if (GET_CODE (from_insn
) != NOTE
)
12583 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12584 place
= prev_real_insn (from_insn
);
12586 XEXP (tem
, 0) = place
;
12587 /* If we're deleting the last remaining instruction of a
12588 libcall sequence, don't add the notes. */
12589 else if (XEXP (note
, 0) == from_insn
)
12595 /* This is handled similarly to REG_RETVAL. */
12596 if (GET_CODE (from_insn
) != NOTE
)
12600 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12601 place
= next_real_insn (from_insn
);
12603 XEXP (tem
, 0) = place
;
12604 /* If we're deleting the last remaining instruction of a
12605 libcall sequence, don't add the notes. */
12606 else if (XEXP (note
, 0) == from_insn
)
12612 /* If the register is used as an input in I3, it dies there.
12613 Similarly for I2, if it is nonzero and adjacent to I3.
12615 If the register is not used as an input in either I3 or I2
12616 and it is not one of the registers we were supposed to eliminate,
12617 there are two possibilities. We might have a non-adjacent I2
12618 or we might have somehow eliminated an additional register
12619 from a computation. For example, we might have had A & B where
12620 we discover that B will always be zero. In this case we will
12621 eliminate the reference to A.
12623 In both cases, we must search to see if we can find a previous
12624 use of A and put the death note there. */
12627 && GET_CODE (from_insn
) == CALL_INSN
12628 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12630 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12632 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12633 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12638 basic_block bb
= this_basic_block
;
12640 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12642 if (! INSN_P (tem
))
12644 if (tem
== BB_HEAD (bb
))
12649 /* If the register is being set at TEM, see if that is all
12650 TEM is doing. If so, delete TEM. Otherwise, make this
12651 into a REG_UNUSED note instead. */
12652 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12654 rtx set
= single_set (tem
);
12655 rtx inner_dest
= 0;
12657 rtx cc0_setter
= NULL_RTX
;
12661 for (inner_dest
= SET_DEST (set
);
12662 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12663 || GET_CODE (inner_dest
) == SUBREG
12664 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12665 inner_dest
= XEXP (inner_dest
, 0))
12668 /* Verify that it was the set, and not a clobber that
12669 modified the register.
12671 CC0 targets must be careful to maintain setter/user
12672 pairs. If we cannot delete the setter due to side
12673 effects, mark the user with an UNUSED note instead
12676 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12677 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12679 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12680 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12681 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12685 /* Move the notes and links of TEM elsewhere.
12686 This might delete other dead insns recursively.
12687 First set the pattern to something that won't use
12689 rtx old_notes
= REG_NOTES (tem
);
12691 PATTERN (tem
) = pc_rtx
;
12692 REG_NOTES (tem
) = NULL
;
12694 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12695 distribute_links (LOG_LINKS (tem
));
12697 PUT_CODE (tem
, NOTE
);
12698 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12699 NOTE_SOURCE_FILE (tem
) = 0;
12702 /* Delete the setter too. */
12705 PATTERN (cc0_setter
) = pc_rtx
;
12706 old_notes
= REG_NOTES (cc0_setter
);
12707 REG_NOTES (cc0_setter
) = NULL
;
12709 distribute_notes (old_notes
, cc0_setter
,
12710 cc0_setter
, NULL_RTX
);
12711 distribute_links (LOG_LINKS (cc0_setter
));
12713 PUT_CODE (cc0_setter
, NOTE
);
12714 NOTE_LINE_NUMBER (cc0_setter
)
12715 = NOTE_INSN_DELETED
;
12716 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12720 /* If the register is both set and used here, put the
12721 REG_DEAD note here, but place a REG_UNUSED note
12722 here too unless there already is one. */
12723 else if (reg_referenced_p (XEXP (note
, 0),
12728 if (! find_regno_note (tem
, REG_UNUSED
,
12729 REGNO (XEXP (note
, 0))))
12731 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12736 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12738 /* If there isn't already a REG_UNUSED note, put one
12740 if (! find_regno_note (tem
, REG_UNUSED
,
12741 REGNO (XEXP (note
, 0))))
12746 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12747 || (GET_CODE (tem
) == CALL_INSN
12748 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12752 /* If we are doing a 3->2 combination, and we have a
12753 register which formerly died in i3 and was not used
12754 by i2, which now no longer dies in i3 and is used in
12755 i2 but does not die in i2, and place is between i2
12756 and i3, then we may need to move a link from place to
12758 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12759 && INSN_CUID (place
) > INSN_CUID (i2
)
12761 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12762 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12764 rtx links
= LOG_LINKS (place
);
12765 LOG_LINKS (place
) = 0;
12766 distribute_links (links
);
12771 if (tem
== BB_HEAD (bb
))
12775 /* We haven't found an insn for the death note and it
12776 is still a REG_DEAD note, but we have hit the beginning
12777 of the block. If the existing life info says the reg
12778 was dead, there's nothing left to do. Otherwise, we'll
12779 need to do a global life update after combine. */
12780 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12781 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12782 REGNO (XEXP (note
, 0))))
12783 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12786 /* If the register is set or already dead at PLACE, we needn't do
12787 anything with this note if it is still a REG_DEAD note.
12788 We can here if it is set at all, not if is it totally replace,
12789 which is what `dead_or_set_p' checks, so also check for it being
12792 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12794 unsigned int regno
= REGNO (XEXP (note
, 0));
12796 /* Similarly, if the instruction on which we want to place
12797 the note is a noop, we'll need do a global live update
12798 after we remove them in delete_noop_moves. */
12799 if (noop_move_p (place
))
12800 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12802 if (dead_or_set_p (place
, XEXP (note
, 0))
12803 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12805 /* Unless the register previously died in PLACE, clear
12806 reg_last_death. [I no longer understand why this is
12808 if (reg_last_death
[regno
] != place
)
12809 reg_last_death
[regno
] = 0;
12813 reg_last_death
[regno
] = place
;
12815 /* If this is a death note for a hard reg that is occupying
12816 multiple registers, ensure that we are still using all
12817 parts of the object. If we find a piece of the object
12818 that is unused, we must arrange for an appropriate REG_DEAD
12819 note to be added for it. However, we can't just emit a USE
12820 and tag the note to it, since the register might actually
12821 be dead; so we recourse, and the recursive call then finds
12822 the previous insn that used this register. */
12824 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12825 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12827 unsigned int endregno
12828 = regno
+ hard_regno_nregs
[regno
]
12829 [GET_MODE (XEXP (note
, 0))];
12833 for (i
= regno
; i
< endregno
; i
++)
12834 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12835 && ! find_regno_fusage (place
, USE
, i
))
12836 || dead_or_set_regno_p (place
, i
))
12841 /* Put only REG_DEAD notes for pieces that are
12842 not already dead or set. */
12844 for (i
= regno
; i
< endregno
;
12845 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12847 rtx piece
= regno_reg_rtx
[i
];
12848 basic_block bb
= this_basic_block
;
12850 if (! dead_or_set_p (place
, piece
)
12851 && ! reg_bitfield_target_p (piece
,
12855 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12857 distribute_notes (new_note
, place
, place
,
12860 else if (! refers_to_regno_p (i
, i
+ 1,
12861 PATTERN (place
), 0)
12862 && ! find_regno_fusage (place
, USE
, i
))
12863 for (tem
= PREV_INSN (place
); ;
12864 tem
= PREV_INSN (tem
))
12866 if (! INSN_P (tem
))
12868 if (tem
== BB_HEAD (bb
))
12870 SET_BIT (refresh_blocks
,
12871 this_basic_block
->index
);
12876 if (dead_or_set_p (tem
, piece
)
12877 || reg_bitfield_target_p (piece
,
12881 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12896 /* Any other notes should not be present at this point in the
12903 XEXP (note
, 1) = REG_NOTES (place
);
12904 REG_NOTES (place
) = note
;
12906 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12907 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12908 && GET_CODE (XEXP (note
, 0)) == REG
)
12909 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12913 if ((REG_NOTE_KIND (note
) == REG_DEAD
12914 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12915 && GET_CODE (XEXP (note
, 0)) == REG
)
12916 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12918 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12919 REG_NOTE_KIND (note
),
12921 REG_NOTES (place2
));
12926 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12927 I3, I2, and I1 to new locations. This is also called to add a link
12928 pointing at I3 when I3's destination is changed. */
12931 distribute_links (rtx links
)
12933 rtx link
, next_link
;
12935 for (link
= links
; link
; link
= next_link
)
12941 next_link
= XEXP (link
, 1);
12943 /* If the insn that this link points to is a NOTE or isn't a single
12944 set, ignore it. In the latter case, it isn't clear what we
12945 can do other than ignore the link, since we can't tell which
12946 register it was for. Such links wouldn't be used by combine
12949 It is not possible for the destination of the target of the link to
12950 have been changed by combine. The only potential of this is if we
12951 replace I3, I2, and I1 by I3 and I2. But in that case the
12952 destination of I2 also remains unchanged. */
12954 if (GET_CODE (XEXP (link
, 0)) == NOTE
12955 || (set
= single_set (XEXP (link
, 0))) == 0)
12958 reg
= SET_DEST (set
);
12959 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12960 || GET_CODE (reg
) == SIGN_EXTRACT
12961 || GET_CODE (reg
) == STRICT_LOW_PART
)
12962 reg
= XEXP (reg
, 0);
12964 /* A LOG_LINK is defined as being placed on the first insn that uses
12965 a register and points to the insn that sets the register. Start
12966 searching at the next insn after the target of the link and stop
12967 when we reach a set of the register or the end of the basic block.
12969 Note that this correctly handles the link that used to point from
12970 I3 to I2. Also note that not much searching is typically done here
12971 since most links don't point very far away. */
12973 for (insn
= NEXT_INSN (XEXP (link
, 0));
12974 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12975 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12976 insn
= NEXT_INSN (insn
))
12977 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12979 if (reg_referenced_p (reg
, PATTERN (insn
)))
12983 else if (GET_CODE (insn
) == CALL_INSN
12984 && find_reg_fusage (insn
, USE
, reg
))
12989 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12992 /* If we found a place to put the link, place it there unless there
12993 is already a link to the same insn as LINK at that point. */
12999 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13000 if (XEXP (link2
, 0) == XEXP (link
, 0))
13005 XEXP (link
, 1) = LOG_LINKS (place
);
13006 LOG_LINKS (place
) = link
;
13008 /* Set added_links_insn to the earliest insn we added a
13010 if (added_links_insn
== 0
13011 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13012 added_links_insn
= place
;
13018 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13021 insn_cuid (rtx insn
)
13023 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13024 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13025 insn
= NEXT_INSN (insn
);
13027 if (INSN_UID (insn
) > max_uid_cuid
)
13030 return INSN_CUID (insn
);
13034 dump_combine_stats (FILE *file
)
13038 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13039 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13043 dump_combine_total_stats (FILE *file
)
13047 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13048 total_attempts
, total_merges
, total_extras
, total_successes
);