1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* Basic block in which we are performing combines. */
306 static basic_block this_basic_block
;
307 static bool optimize_this_for_speed_p
;
310 /* Length of the currently allocated uid_insn_cost array. */
312 static int max_uid_known
;
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
317 static int *uid_insn_cost
;
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
325 struct insn_link
*next
;
328 static struct insn_link
**uid_log_links
;
331 insn_uid_check (const_rtx insn
)
333 int uid
= INSN_UID (insn
);
334 gcc_checking_assert (uid
<= max_uid_known
);
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
346 static struct obstack insn_link_obstack
;
348 /* Allocate a link. */
350 static inline struct insn_link
*
351 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
354 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
355 sizeof (struct insn_link
));
362 /* Incremented for each basic block. */
364 static int label_tick
;
366 /* Reset to label_tick for each extended basic block in scanning order. */
368 static int label_tick_ebb_start
;
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
373 static machine_mode nonzero_bits_mode
;
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
381 static int nonzero_sign_valid
;
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
387 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
393 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
394 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
407 rtx_insn
*other_insn
;
410 static struct undobuf undobuf
;
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
415 static int n_occurrences
;
417 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
419 unsigned HOST_WIDE_INT
,
420 unsigned HOST_WIDE_INT
*);
421 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
423 unsigned int, unsigned int *);
424 static void do_SUBST (rtx
*, rtx
);
425 static void do_SUBST_INT (int *, int);
426 static void init_reg_last (void);
427 static void setup_incoming_promotions (rtx_insn
*);
428 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
429 static int cant_combine_insn_p (rtx_insn
*);
430 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
431 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
432 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
433 static int contains_muldiv (rtx
);
434 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
436 static void undo_all (void);
437 static void undo_commit (void);
438 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
439 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
440 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
441 static rtx
simplify_if_then_else (rtx
);
442 static rtx
simplify_set (rtx
);
443 static rtx
simplify_logical (rtx
);
444 static rtx
expand_compound_operation (rtx
);
445 static const_rtx
expand_field_assignment (const_rtx
);
446 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
447 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
448 static rtx
extract_left_shift (rtx
, int);
449 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
450 unsigned HOST_WIDE_INT
*);
451 static rtx
canon_reg_for_combine (rtx
, rtx
);
452 static rtx
force_to_mode (rtx
, machine_mode
,
453 unsigned HOST_WIDE_INT
, int);
454 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
455 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
456 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
457 static rtx
make_field_assignment (rtx
);
458 static rtx
apply_distributive_law (rtx
);
459 static rtx
distribute_and_simplify_rtx (rtx
, int);
460 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
461 unsigned HOST_WIDE_INT
);
462 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
463 unsigned HOST_WIDE_INT
);
464 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
465 HOST_WIDE_INT
, machine_mode
, int *);
466 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
467 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
469 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
470 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
471 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
473 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
474 static void update_table_tick (rtx
);
475 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
476 static void check_promoted_subreg (rtx_insn
*, rtx
);
477 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
478 static void record_dead_and_set_regs (rtx_insn
*);
479 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
480 static rtx
get_last_value (const_rtx
);
481 static int use_crosses_set_p (const_rtx
, int);
482 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
483 static int reg_dead_at_p (rtx
, rtx_insn
*);
484 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
485 static int reg_bitfield_target_p (rtx
, rtx
);
486 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
487 static void distribute_links (struct insn_link
*);
488 static void mark_used_regs_combine (rtx
);
489 static void record_promoted_value (rtx_insn
*, rtx
);
490 static bool unmentioned_reg_p (rtx
, rtx
);
491 static void record_truncated_values (rtx
*, void *);
492 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
493 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
514 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
520 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
521 bool op0_preserve_value
)
523 int code_int
= (int)*code
;
524 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
525 *code
= (enum rtx_code
)code_int
;
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
535 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
540 ret
= split_insns (pattern
, insn
);
541 nregs
= max_reg_num ();
542 if (nregs
> reg_stat
.length ())
543 reg_stat
.safe_grow_cleared (nregs
);
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
554 find_single_use_1 (rtx dest
, rtx
*loc
)
557 enum rtx_code code
= GET_CODE (x
);
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
577 if (GET_CODE (SET_DEST (x
)) != CC0
578 && GET_CODE (SET_DEST (x
)) != PC
579 && !REG_P (SET_DEST (x
))
580 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
581 && REG_P (SUBREG_REG (SET_DEST (x
)))
582 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
583 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
584 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
585 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_rtx_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_rtx_costs. */
892 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
895 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
896 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
897 ? new_i2_cost
+ new_i3_cost
: 0;
901 new_cost
= new_i3_cost
;
905 if (undobuf
.other_insn
)
907 int old_other_cost
, new_other_cost
;
909 old_other_cost
= INSN_COST (undobuf
.other_insn
);
910 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
911 if (old_other_cost
> 0 && new_other_cost
> 0)
913 old_cost
+= old_other_cost
;
914 new_cost
+= new_other_cost
;
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
922 int reject
= old_cost
> 0 && new_cost
> old_cost
;
926 fprintf (dump_file
, "%s combination of insns ",
927 reject
? "rejecting" : "allowing");
929 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
930 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
931 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
932 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
934 fprintf (dump_file
, "original costs ");
936 fprintf (dump_file
, "%d + ", i0_cost
);
937 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
938 fprintf (dump_file
, "%d + ", i1_cost
);
939 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
942 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
943 new_i2_cost
, new_i3_cost
, new_cost
);
945 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
951 /* Update the uid_insn_cost array with the replacement costs. */
952 INSN_COST (i2
) = new_i2_cost
;
953 INSN_COST (i3
) = new_i3_cost
;
965 /* Delete any insns that copy a register to itself. */
968 delete_noop_moves (void)
970 rtx_insn
*insn
, *next
;
973 FOR_EACH_BB_FN (bb
, cfun
)
975 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
977 next
= NEXT_INSN (insn
);
978 if (INSN_P (insn
) && noop_move_p (insn
))
981 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
983 delete_insn_and_edges (insn
);
990 /* Return false if we do not want to (or cannot) combine DEF. */
992 can_combine_def_p (df_ref def
)
994 /* Do not consider if it is pre/post modification in MEM. */
995 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
998 unsigned int regno
= DF_REF_REGNO (def
);
1000 /* Do not combine frame pointer adjustments. */
1001 if ((regno
== FRAME_POINTER_REGNUM
1002 && (!reload_completed
|| frame_pointer_needed
))
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 && regno
== HARD_FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1007 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1013 /* Return false if we do not want to (or cannot) combine USE. */
1015 can_combine_use_p (df_ref use
)
1017 /* Do not consider the usage of the stack pointer by function call. */
1018 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1024 /* Fill in log links field for all insns. */
1027 create_log_links (void)
1030 rtx_insn
**next_use
;
1034 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1045 FOR_EACH_BB_FN (bb
, cfun
)
1047 FOR_BB_INSNS_REVERSE (bb
, insn
)
1049 if (!NONDEBUG_INSN_P (insn
))
1052 /* Log links are created only once. */
1053 gcc_assert (!LOG_LINKS (insn
));
1055 FOR_EACH_INSN_DEF (def
, insn
)
1057 unsigned int regno
= DF_REF_REGNO (def
);
1060 if (!next_use
[regno
])
1063 if (!can_combine_def_p (def
))
1066 use_insn
= next_use
[regno
];
1067 next_use
[regno
] = NULL
;
1069 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1079 if (regno
< FIRST_PSEUDO_REGISTER
1080 && asm_noperands (PATTERN (use_insn
)) >= 0)
1083 /* Don't add duplicate links between instructions. */
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, use_insn
)
1086 if (insn
== links
->insn
&& regno
== links
->regno
)
1090 LOG_LINKS (use_insn
)
1091 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1094 FOR_EACH_INSN_USE (use
, insn
)
1095 if (can_combine_use_p (use
))
1096 next_use
[DF_REF_REGNO (use
)] = insn
;
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1111 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1113 struct insn_link
*links
;
1114 FOR_EACH_LOG_LINK (links
, b
)
1115 if (links
->insn
== a
)
1117 if (HAVE_cc0
&& sets_cc0_p (a
))
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1128 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1130 rtx_insn
*insn
, *next
;
1132 struct insn_link
*links
, *nextlinks
;
1134 basic_block last_bb
;
1136 int new_direct_jump_p
= 0;
1138 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1139 first
= NEXT_INSN (first
);
1143 combine_attempts
= 0;
1146 combine_successes
= 0;
1148 rtl_hooks
= combine_rtl_hooks
;
1150 reg_stat
.safe_grow_cleared (nregs
);
1152 init_recog_no_volatile ();
1154 /* Allocate array for insn info. */
1155 max_uid_known
= get_max_uid ();
1156 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1157 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1158 gcc_obstack_init (&insn_link_obstack
);
1160 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1165 nonzero_sign_valid
= 0;
1166 label_tick
= label_tick_ebb_start
= 1;
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1175 setup_incoming_promotions (first
);
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1178 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1180 create_log_links ();
1181 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1183 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1188 if (!single_pred_p (this_basic_block
)
1189 || single_pred (this_basic_block
) != last_bb
)
1190 label_tick_ebb_start
= label_tick
;
1191 last_bb
= this_basic_block
;
1193 FOR_BB_INSNS (this_basic_block
, insn
)
1194 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1198 subst_low_luid
= DF_INSN_LUID (insn
);
1201 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1203 record_dead_and_set_regs (insn
);
1206 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1207 if (REG_NOTE_KIND (links
) == REG_INC
)
1208 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1211 /* Record the current insn_rtx_cost of this instruction. */
1212 if (NONJUMP_INSN_P (insn
))
1213 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1214 optimize_this_for_speed_p
);
1216 fprintf (dump_file
, "insn_cost %d: %d\n",
1217 INSN_UID (insn
), INSN_COST (insn
));
1221 nonzero_sign_valid
= 1;
1223 /* Now scan all the insns in forward order. */
1224 label_tick
= label_tick_ebb_start
= 1;
1226 setup_incoming_promotions (first
);
1227 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1228 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1230 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1232 rtx_insn
*last_combined_insn
= NULL
;
1233 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1238 if (!single_pred_p (this_basic_block
)
1239 || single_pred (this_basic_block
) != last_bb
)
1240 label_tick_ebb_start
= label_tick
;
1241 last_bb
= this_basic_block
;
1243 rtl_profile_for_bb (this_basic_block
);
1244 for (insn
= BB_HEAD (this_basic_block
);
1245 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1246 insn
= next
? next
: NEXT_INSN (insn
))
1249 if (!NONDEBUG_INSN_P (insn
))
1252 while (last_combined_insn
1253 && last_combined_insn
->deleted ())
1254 last_combined_insn
= PREV_INSN (last_combined_insn
);
1255 if (last_combined_insn
== NULL_RTX
1256 || BARRIER_P (last_combined_insn
)
1257 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1258 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1259 last_combined_insn
= insn
;
1261 /* See if we know about function return values before this
1262 insn based upon SUBREG flags. */
1263 check_promoted_subreg (insn
, PATTERN (insn
));
1265 /* See if we can find hardregs and subreg of pseudos in
1266 narrower modes. This could help turning TRUNCATEs
1268 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1270 /* Try this insn with each insn it links back to. */
1272 FOR_EACH_LOG_LINK (links
, insn
)
1273 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1274 NULL
, &new_direct_jump_p
,
1275 last_combined_insn
)) != 0)
1277 statistics_counter_event (cfun
, "two-insn combine", 1);
1281 /* Try each sequence of three linked insns ending with this one. */
1283 if (max_combine
>= 3)
1284 FOR_EACH_LOG_LINK (links
, insn
)
1286 rtx_insn
*link
= links
->insn
;
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 FOR_EACH_LOG_LINK (nextlinks
, link
)
1294 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1295 NULL
, &new_direct_jump_p
,
1296 last_combined_insn
)) != 0)
1298 statistics_counter_event (cfun
, "three-insn combine", 1);
1303 /* Try to combine a jump insn that uses CC0
1304 with a preceding insn that sets CC0, and maybe with its
1305 logical predecessor as well.
1306 This is how we make decrement-and-branch insns.
1307 We need this special code because data flow connections
1308 via CC0 do not get entered in LOG_LINKS. */
1312 && (prev
= prev_nonnote_insn (insn
)) != 0
1313 && NONJUMP_INSN_P (prev
)
1314 && sets_cc0_p (PATTERN (prev
)))
1316 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1318 last_combined_insn
)) != 0)
1321 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1322 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1323 NULL
, &new_direct_jump_p
,
1324 last_combined_insn
)) != 0)
1328 /* Do the same for an insn that explicitly references CC0. */
1329 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1330 && (prev
= prev_nonnote_insn (insn
)) != 0
1331 && NONJUMP_INSN_P (prev
)
1332 && sets_cc0_p (PATTERN (prev
))
1333 && GET_CODE (PATTERN (insn
)) == SET
1334 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1336 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1338 last_combined_insn
)) != 0)
1341 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1342 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1343 NULL
, &new_direct_jump_p
,
1344 last_combined_insn
)) != 0)
1348 /* Finally, see if any of the insns that this insn links to
1349 explicitly references CC0. If so, try this insn, that insn,
1350 and its predecessor if it sets CC0. */
1353 FOR_EACH_LOG_LINK (links
, insn
)
1354 if (NONJUMP_INSN_P (links
->insn
)
1355 && GET_CODE (PATTERN (links
->insn
)) == SET
1356 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1357 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1358 && NONJUMP_INSN_P (prev
)
1359 && sets_cc0_p (PATTERN (prev
))
1360 && (next
= try_combine (insn
, links
->insn
,
1361 prev
, NULL
, &new_direct_jump_p
,
1362 last_combined_insn
)) != 0)
1366 /* Try combining an insn with two different insns whose results it
1368 if (max_combine
>= 3)
1369 FOR_EACH_LOG_LINK (links
, insn
)
1370 for (nextlinks
= links
->next
; nextlinks
;
1371 nextlinks
= nextlinks
->next
)
1372 if ((next
= try_combine (insn
, links
->insn
,
1373 nextlinks
->insn
, NULL
,
1375 last_combined_insn
)) != 0)
1378 statistics_counter_event (cfun
, "three-insn combine", 1);
1382 /* Try four-instruction combinations. */
1383 if (max_combine
>= 4)
1384 FOR_EACH_LOG_LINK (links
, insn
)
1386 struct insn_link
*next1
;
1387 rtx_insn
*link
= links
->insn
;
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1394 FOR_EACH_LOG_LINK (next1
, link
)
1396 rtx_insn
*link1
= next1
->insn
;
1399 /* I0 -> I1 -> I2 -> I3. */
1400 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1401 if ((next
= try_combine (insn
, link
, link1
,
1404 last_combined_insn
)) != 0)
1406 statistics_counter_event (cfun
, "four-insn combine", 1);
1409 /* I0, I1 -> I2, I2 -> I3. */
1410 for (nextlinks
= next1
->next
; nextlinks
;
1411 nextlinks
= nextlinks
->next
)
1412 if ((next
= try_combine (insn
, link
, link1
,
1415 last_combined_insn
)) != 0)
1417 statistics_counter_event (cfun
, "four-insn combine", 1);
1422 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1424 rtx_insn
*link1
= next1
->insn
;
1427 /* I0 -> I2; I1, I2 -> I3. */
1428 FOR_EACH_LOG_LINK (nextlinks
, link
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1437 /* I0 -> I1; I1, I2 -> I3. */
1438 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1439 if ((next
= try_combine (insn
, link
, link1
,
1442 last_combined_insn
)) != 0)
1444 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1451 FOR_EACH_LOG_LINK (links
, insn
)
1454 rtx_insn
*temp
= links
->insn
;
1455 if ((set
= single_set (temp
)) != 0
1456 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1457 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1460 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1461 && (GET_MODE (note
) == VOIDmode
1462 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1463 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1464 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1465 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1466 == GET_MODE (note
))))))
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1471 rtx orig_src
= SET_SRC (set
);
1472 rtx orig_dest
= SET_DEST (set
);
1473 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1474 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1475 SET_SRC (set
) = note
;
1477 i2mod_old_rhs
= copy_rtx (orig_src
);
1478 i2mod_new_rhs
= copy_rtx (note
);
1479 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1481 last_combined_insn
);
1485 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1488 SET_SRC (set
) = orig_src
;
1489 SET_DEST (set
) = orig_dest
;
1494 record_dead_and_set_regs (insn
);
1501 default_rtl_profile ();
1503 new_direct_jump_p
|= purge_all_dead_edges ();
1504 delete_noop_moves ();
1507 obstack_free (&insn_link_obstack
, NULL
);
1508 free (uid_log_links
);
1509 free (uid_insn_cost
);
1510 reg_stat
.release ();
1513 struct undo
*undo
, *next
;
1514 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1522 total_attempts
+= combine_attempts
;
1523 total_merges
+= combine_merges
;
1524 total_extras
+= combine_extras
;
1525 total_successes
+= combine_successes
;
1527 nonzero_sign_valid
= 0;
1528 rtl_hooks
= general_rtl_hooks
;
1530 /* Make recognizer allow volatile MEMs again. */
1533 return new_direct_jump_p
;
1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1539 init_reg_last (void)
1544 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1545 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1548 /* Set up any promoted values for incoming argument registers. */
1551 setup_incoming_promotions (rtx_insn
*first
)
1554 bool strictly_local
= false;
1556 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1557 arg
= DECL_CHAIN (arg
))
1559 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1561 machine_mode mode1
, mode2
, mode3
, mode4
;
1563 /* Only continue if the incoming argument is in a register. */
1567 /* Determine, if possible, whether all call sites of the current
1568 function lie within the current compilation unit. (This does
1569 take into account the exporting of a function via taking its
1570 address, and so forth.) */
1571 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1573 /* The mode and signedness of the argument before any promotions happen
1574 (equal to the mode of the pseudo holding it at that stage). */
1575 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1576 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1578 /* The mode and signedness of the argument after any source language and
1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1580 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1581 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1583 /* The mode and signedness of the argument as it is actually passed,
1584 see assign_parm_setup_reg in function.c. */
1585 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1586 TREE_TYPE (cfun
->decl
), 0);
1588 /* The mode of the register in which the argument is being passed. */
1589 mode4
= GET_MODE (reg
);
1591 /* Eliminate sign extensions in the callee when:
1592 (a) A mode promotion has occurred; */
1595 /* (b) The mode of the register is the same as the mode of
1596 the argument as it is passed; */
1599 /* (c) There's no language level extension; */
1602 /* (c.1) All callers are from the current compilation unit. If that's
1603 the case we don't have to rely on an ABI, we only have to know
1604 what we're generating right now, and we know that we will do the
1605 mode1 to mode2 promotion with the given sign. */
1606 else if (!strictly_local
)
1608 /* (c.2) The combination of the two promotions is useful. This is
1609 true when the signs match, or if the first promotion is unsigned.
1610 In the later case, (sign_extend (zero_extend x)) is the same as
1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1617 /* Record that the value was promoted from mode1 to mode3,
1618 so that any sign extension at the head of the current
1619 function may be eliminated. */
1620 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1621 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1622 record_value_for_reg (reg
, first
, x
);
1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1628 because some machines (maybe most) will actually do the sign-extension and
1629 this is the conservative approach.
1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1635 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1637 if (GET_MODE_PRECISION (mode
) < prec
1638 && CONST_INT_P (src
)
1640 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1641 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1650 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1653 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1654 unsigned HOST_WIDE_INT bits
= 0;
1655 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1656 unsigned int num
= 0;
1659 reg_equal
= XEXP (reg_equal_note
, 0);
1661 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1663 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1665 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1668 /* Don't call nonzero_bits if it cannot change anything. */
1669 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1671 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1672 if (reg_equal
&& bits
)
1673 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1674 rsp
->nonzero_bits
|= bits
;
1677 /* Don't call num_sign_bit_copies if it cannot change anything. */
1678 if (rsp
->sign_bit_copies
!= 1)
1680 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1681 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1683 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1684 if (num
== 0 || numeq
> num
)
1687 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1688 rsp
->sign_bit_copies
= num
;
1692 /* Called via note_stores. If X is a pseudo that is narrower than
1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1695 If we are setting only a portion of X and we can't figure out what
1696 portion, assume all bits will be used since we don't know what will
1699 Similarly, set how many bits of X are known to be copies of the sign bit
1700 at all locations in the function. This is the smallest number implied
1704 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1706 rtx_insn
*insn
= (rtx_insn
*) data
;
1709 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1710 /* If this register is undefined at the start of the file, we can't
1711 say what its contents were. */
1712 && ! REGNO_REG_SET_P
1713 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1714 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1716 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1718 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1720 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1721 rsp
->sign_bit_copies
= 1;
1725 /* If this register is being initialized using itself, and the
1726 register is uninitialized in this basic block, and there are
1727 no LOG_LINKS which set the register, then part of the
1728 register is uninitialized. In that case we can't assume
1729 anything about the number of nonzero bits.
1731 ??? We could do better if we checked this in
1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1733 could avoid making assumptions about the insn which initially
1734 sets the register, while still using the information in other
1735 insns. We would have to be careful to check every insn
1736 involved in the combination. */
1739 && reg_referenced_p (x
, PATTERN (insn
))
1740 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1743 struct insn_link
*link
;
1745 FOR_EACH_LOG_LINK (link
, insn
)
1746 if (dead_or_set_p (link
->insn
, x
))
1750 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1751 rsp
->sign_bit_copies
= 1;
1756 /* If this is a complex assignment, see if we can convert it into a
1757 simple assignment. */
1758 set
= expand_field_assignment (set
);
1760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1761 set what we know about X. */
1763 if (SET_DEST (set
) == x
1764 || (paradoxical_subreg_p (SET_DEST (set
))
1765 && SUBREG_REG (SET_DEST (set
)) == x
))
1766 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1769 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1770 rsp
->sign_bit_copies
= 1;
1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1776 optionally insns that were previously combined into I3 or that will be
1777 combined into the merger of INSN and I3. The order is PRED, PRED2,
1778 INSN, SUCC, SUCC2, I3.
1780 Return 0 if the combination is not allowed for any reason.
1782 If the combination is allowed, *PDEST will be set to the single
1783 destination of INSN and *PSRC to the single source, and this function
1787 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1788 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1789 rtx
*pdest
, rtx
*psrc
)
1796 bool all_adjacent
= true;
1797 int (*is_volatile_p
) (const_rtx
);
1803 if (next_active_insn (succ2
) != i3
)
1804 all_adjacent
= false;
1805 if (next_active_insn (succ
) != succ2
)
1806 all_adjacent
= false;
1808 else if (next_active_insn (succ
) != i3
)
1809 all_adjacent
= false;
1810 if (next_active_insn (insn
) != succ
)
1811 all_adjacent
= false;
1813 else if (next_active_insn (insn
) != i3
)
1814 all_adjacent
= false;
1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1817 or a PARALLEL consisting of such a SET and CLOBBERs.
1819 If INSN has CLOBBER parallel parts, ignore them for our processing.
1820 By definition, these happen during the execution of the insn. When it
1821 is merged with another insn, all bets are off. If they are, in fact,
1822 needed and aren't also supplied in I3, they may be added by
1823 recog_for_combine. Otherwise, it won't match.
1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1828 Get the source and destination of INSN. If more than one, can't
1831 if (GET_CODE (PATTERN (insn
)) == SET
)
1832 set
= PATTERN (insn
);
1833 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1834 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1836 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1838 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1840 switch (GET_CODE (elt
))
1842 /* This is important to combine floating point insns
1843 for the SH4 port. */
1845 /* Combining an isolated USE doesn't make sense.
1846 We depend here on combinable_i3pat to reject them. */
1847 /* The code below this loop only verifies that the inputs of
1848 the SET in INSN do not change. We call reg_set_between_p
1849 to verify that the REG in the USE does not change between
1851 If the USE in INSN was for a pseudo register, the matching
1852 insn pattern will likely match any register; combining this
1853 with any other USE would only be safe if we knew that the
1854 used registers have identical values, or if there was
1855 something to tell them apart, e.g. different modes. For
1856 now, we forgo such complicated tests and simply disallow
1857 combining of USES of pseudo registers with any other USE. */
1858 if (REG_P (XEXP (elt
, 0))
1859 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1861 rtx i3pat
= PATTERN (i3
);
1862 int i
= XVECLEN (i3pat
, 0) - 1;
1863 unsigned int regno
= REGNO (XEXP (elt
, 0));
1867 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1869 if (GET_CODE (i3elt
) == USE
1870 && REG_P (XEXP (i3elt
, 0))
1871 && (REGNO (XEXP (i3elt
, 0)) == regno
1872 ? reg_set_between_p (XEXP (elt
, 0),
1873 PREV_INSN (insn
), i3
)
1874 : regno
>= FIRST_PSEUDO_REGISTER
))
1881 /* We can ignore CLOBBERs. */
1886 /* Ignore SETs whose result isn't used but not those that
1887 have side-effects. */
1888 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1889 && insn_nothrow_p (insn
)
1890 && !side_effects_p (elt
))
1893 /* If we have already found a SET, this is a second one and
1894 so we cannot combine with this insn. */
1902 /* Anything else means we can't combine. */
1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1909 so don't do anything with it. */
1910 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1919 /* The simplification in expand_field_assignment may call back to
1920 get_last_value, so set safe guard here. */
1921 subst_low_luid
= DF_INSN_LUID (insn
);
1923 set
= expand_field_assignment (set
);
1924 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1926 /* Do not eliminate user-specified register if it is in an
1927 asm input because we may break the register asm usage defined
1928 in GCC manual if allow to do so.
1929 Be aware that this may cover more cases than we expect but this
1930 should be harmless. */
1931 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1932 && extract_asm_operands (PATTERN (i3
)))
1935 /* Don't eliminate a store in the stack pointer. */
1936 if (dest
== stack_pointer_rtx
1937 /* Don't combine with an insn that sets a register to itself if it has
1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1939 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1940 /* Can't merge an ASM_OPERANDS. */
1941 || GET_CODE (src
) == ASM_OPERANDS
1942 /* Can't merge a function call. */
1943 || GET_CODE (src
) == CALL
1944 /* Don't eliminate a function call argument. */
1946 && (find_reg_fusage (i3
, USE
, dest
)
1948 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1949 && global_regs
[REGNO (dest
)])))
1950 /* Don't substitute into an incremented register. */
1951 || FIND_REG_INC_NOTE (i3
, dest
)
1952 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1953 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1954 /* Don't substitute into a non-local goto, this confuses CFG. */
1955 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1956 /* Make sure that DEST is not used after SUCC but before I3. */
1959 && (reg_used_between_p (dest
, succ2
, i3
)
1960 || reg_used_between_p (dest
, succ
, succ2
)))
1961 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1962 /* Make sure that the value that is to be substituted for the register
1963 does not use any registers whose values alter in between. However,
1964 If the insns are adjacent, a use can't cross a set even though we
1965 think it might (this can happen for a sequence of insns each setting
1966 the same destination; last_set of that register might point to
1967 a NOTE). If INSN has a REG_EQUIV note, the register is always
1968 equivalent to the memory so the substitution is valid even if there
1969 are intervening stores. Also, don't move a volatile asm or
1970 UNSPEC_VOLATILE across any other insns. */
1973 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1974 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1975 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1976 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1977 /* Don't combine across a CALL_INSN, because that would possibly
1978 change whether the life span of some REGs crosses calls or not,
1979 and it is a pain to update that information.
1980 Exception: if source is a constant, moving it later can't hurt.
1981 Accept that as a special case. */
1982 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1985 /* DEST must either be a REG or CC0. */
1988 /* If register alignment is being enforced for multi-word items in all
1989 cases except for parameters, it is possible to have a register copy
1990 insn referencing a hard register that is not allowed to contain the
1991 mode being copied and which would not be valid as an operand of most
1992 insns. Eliminate this problem by not combining with such an insn.
1994 Also, on some machines we don't want to extend the life of a hard
1998 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1999 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2000 /* Don't extend the life of a hard register unless it is
2001 user variable (if we have few registers) or it can't
2002 fit into the desired register (meaning something special
2004 Also avoid substituting a return register into I3, because
2005 reload can't handle a conflict with constraints of other
2007 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2008 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2011 else if (GET_CODE (dest
) != CC0
)
2015 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2016 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2017 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2019 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2021 /* If the clobber represents an earlyclobber operand, we must not
2022 substitute an expression containing the clobbered register.
2023 As we do not analyze the constraint strings here, we have to
2024 make the conservative assumption. However, if the register is
2025 a fixed hard reg, the clobber cannot represent any operand;
2026 we leave it up to the machine description to either accept or
2027 reject use-and-clobber patterns. */
2029 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2030 || !fixed_regs
[REGNO (reg
)])
2031 if (reg_overlap_mentioned_p (reg
, src
))
2035 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2036 or not), reject, unless nothing volatile comes between it and I3 */
2038 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2040 /* Make sure neither succ nor succ2 contains a volatile reference. */
2041 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2043 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2045 /* We'll check insns between INSN and I3 below. */
2048 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2049 to be an explicit register variable, and was chosen for a reason. */
2051 if (GET_CODE (src
) == ASM_OPERANDS
2052 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2055 /* If INSN contains volatile references (specifically volatile MEMs),
2056 we cannot combine across any other volatile references.
2057 Even if INSN doesn't contain volatile references, any intervening
2058 volatile insn might affect machine state. */
2060 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2064 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2065 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2068 /* If INSN contains an autoincrement or autodecrement, make sure that
2069 register is not used between there and I3, and not already used in
2070 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2071 Also insist that I3 not be a jump; if it were one
2072 and the incremented register were spilled, we would lose. */
2075 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2076 if (REG_NOTE_KIND (link
) == REG_INC
2078 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2079 || (pred
!= NULL_RTX
2080 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2081 || (pred2
!= NULL_RTX
2082 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2083 || (succ
!= NULL_RTX
2084 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2085 || (succ2
!= NULL_RTX
2086 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2087 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2090 /* Don't combine an insn that follows a CC0-setting insn.
2091 An insn that uses CC0 must not be separated from the one that sets it.
2092 We do, however, allow I2 to follow a CC0-setting insn if that insn
2093 is passed as I1; in that case it will be deleted also.
2094 We also allow combining in this case if all the insns are adjacent
2095 because that would leave the two CC0 insns adjacent as well.
2096 It would be more logical to test whether CC0 occurs inside I1 or I2,
2097 but that would be much slower, and this ought to be equivalent. */
2101 p
= prev_nonnote_insn (insn
);
2102 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2107 /* If we get here, we have passed all the tests and the combination is
2116 /* LOC is the location within I3 that contains its pattern or the component
2117 of a PARALLEL of the pattern. We validate that it is valid for combining.
2119 One problem is if I3 modifies its output, as opposed to replacing it
2120 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2121 doing so would produce an insn that is not equivalent to the original insns.
2125 (set (reg:DI 101) (reg:DI 100))
2126 (set (subreg:SI (reg:DI 101) 0) <foo>)
2128 This is NOT equivalent to:
2130 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2131 (set (reg:DI 101) (reg:DI 100))])
2133 Not only does this modify 100 (in which case it might still be valid
2134 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2136 We can also run into a problem if I2 sets a register that I1
2137 uses and I1 gets directly substituted into I3 (not via I2). In that
2138 case, we would be getting the wrong value of I2DEST into I3, so we
2139 must reject the combination. This case occurs when I2 and I1 both
2140 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2141 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2142 of a SET must prevent combination from occurring. The same situation
2143 can occur for I0, in which case I0_NOT_IN_SRC is set.
2145 Before doing the above check, we first try to expand a field assignment
2146 into a set of logical operations.
2148 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2149 we place a register that is both set and used within I3. If more than one
2150 such register is detected, we fail.
2152 Return 1 if the combination is valid, zero otherwise. */
2155 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2156 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2160 if (GET_CODE (x
) == SET
)
2163 rtx dest
= SET_DEST (set
);
2164 rtx src
= SET_SRC (set
);
2165 rtx inner_dest
= dest
;
2168 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2169 || GET_CODE (inner_dest
) == SUBREG
2170 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2171 inner_dest
= XEXP (inner_dest
, 0);
2173 /* Check for the case where I3 modifies its output, as discussed
2174 above. We don't want to prevent pseudos from being combined
2175 into the address of a MEM, so only prevent the combination if
2176 i1 or i2 set the same MEM. */
2177 if ((inner_dest
!= dest
&&
2178 (!MEM_P (inner_dest
)
2179 || rtx_equal_p (i2dest
, inner_dest
)
2180 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2181 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2182 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2183 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2184 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2186 /* This is the same test done in can_combine_p except we can't test
2187 all_adjacent; we don't have to, since this instruction will stay
2188 in place, thus we are not considering increasing the lifetime of
2191 Also, if this insn sets a function argument, combining it with
2192 something that might need a spill could clobber a previous
2193 function argument; the all_adjacent test in can_combine_p also
2194 checks this; here, we do a more specific test for this case. */
2196 || (REG_P (inner_dest
)
2197 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2198 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2199 GET_MODE (inner_dest
))))
2200 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2201 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2204 /* If DEST is used in I3, it is being killed in this insn, so
2205 record that for later. We have to consider paradoxical
2206 subregs here, since they kill the whole register, but we
2207 ignore partial subregs, STRICT_LOW_PART, etc.
2208 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2209 STACK_POINTER_REGNUM, since these are always considered to be
2210 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2212 if (GET_CODE (subdest
) == SUBREG
2213 && (GET_MODE_SIZE (GET_MODE (subdest
))
2214 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2215 subdest
= SUBREG_REG (subdest
);
2218 && reg_referenced_p (subdest
, PATTERN (i3
))
2219 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2220 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2221 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2222 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2223 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2224 || ! fixed_regs
[REGNO (subdest
)]))
2225 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2227 if (*pi3dest_killed
)
2230 *pi3dest_killed
= subdest
;
2234 else if (GET_CODE (x
) == PARALLEL
)
2238 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2239 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2240 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2247 /* Return 1 if X is an arithmetic expression that contains a multiplication
2248 and division. We don't count multiplications by powers of two here. */
2251 contains_muldiv (rtx x
)
2253 switch (GET_CODE (x
))
2255 case MOD
: case DIV
: case UMOD
: case UDIV
:
2259 return ! (CONST_INT_P (XEXP (x
, 1))
2260 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2263 return contains_muldiv (XEXP (x
, 0))
2264 || contains_muldiv (XEXP (x
, 1));
2267 return contains_muldiv (XEXP (x
, 0));
2273 /* Determine whether INSN can be used in a combination. Return nonzero if
2274 not. This is used in try_combine to detect early some cases where we
2275 can't perform combinations. */
2278 cant_combine_insn_p (rtx_insn
*insn
)
2283 /* If this isn't really an insn, we can't do anything.
2284 This can occur when flow deletes an insn that it has merged into an
2285 auto-increment address. */
2286 if (!NONDEBUG_INSN_P (insn
))
2289 /* Never combine loads and stores involving hard regs that are likely
2290 to be spilled. The register allocator can usually handle such
2291 reg-reg moves by tying. If we allow the combiner to make
2292 substitutions of likely-spilled regs, reload might die.
2293 As an exception, we allow combinations involving fixed regs; these are
2294 not available to the register allocator so there's no risk involved. */
2296 set
= single_set (insn
);
2299 src
= SET_SRC (set
);
2300 dest
= SET_DEST (set
);
2301 if (GET_CODE (src
) == SUBREG
)
2302 src
= SUBREG_REG (src
);
2303 if (GET_CODE (dest
) == SUBREG
)
2304 dest
= SUBREG_REG (dest
);
2305 if (REG_P (src
) && REG_P (dest
)
2306 && ((HARD_REGISTER_P (src
)
2307 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2308 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2309 || (HARD_REGISTER_P (dest
)
2310 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2311 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2317 struct likely_spilled_retval_info
2319 unsigned regno
, nregs
;
2323 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2324 hard registers that are known to be written to / clobbered in full. */
2326 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2328 struct likely_spilled_retval_info
*const info
=
2329 (struct likely_spilled_retval_info
*) data
;
2330 unsigned regno
, nregs
;
2333 if (!REG_P (XEXP (set
, 0)))
2336 if (regno
>= info
->regno
+ info
->nregs
)
2338 nregs
= REG_NREGS (x
);
2339 if (regno
+ nregs
<= info
->regno
)
2341 new_mask
= (2U << (nregs
- 1)) - 1;
2342 if (regno
< info
->regno
)
2343 new_mask
>>= info
->regno
- regno
;
2345 new_mask
<<= regno
- info
->regno
;
2346 info
->mask
&= ~new_mask
;
2349 /* Return nonzero iff part of the return value is live during INSN, and
2350 it is likely spilled. This can happen when more than one insn is needed
2351 to copy the return value, e.g. when we consider to combine into the
2352 second copy insn for a complex value. */
2355 likely_spilled_retval_p (rtx_insn
*insn
)
2357 rtx_insn
*use
= BB_END (this_basic_block
);
2360 unsigned regno
, nregs
;
2361 /* We assume here that no machine mode needs more than
2362 32 hard registers when the value overlaps with a register
2363 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2365 struct likely_spilled_retval_info info
;
2367 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2369 reg
= XEXP (PATTERN (use
), 0);
2370 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2372 regno
= REGNO (reg
);
2373 nregs
= REG_NREGS (reg
);
2376 mask
= (2U << (nregs
- 1)) - 1;
2378 /* Disregard parts of the return value that are set later. */
2382 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2384 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2387 /* Check if any of the (probably) live return value registers is
2392 if ((mask
& 1 << nregs
)
2393 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2399 /* Adjust INSN after we made a change to its destination.
2401 Changing the destination can invalidate notes that say something about
2402 the results of the insn and a LOG_LINK pointing to the insn. */
2405 adjust_for_new_dest (rtx_insn
*insn
)
2407 /* For notes, be conservative and simply remove them. */
2408 remove_reg_equal_equiv_notes (insn
);
2410 /* The new insn will have a destination that was previously the destination
2411 of an insn just above it. Call distribute_links to make a LOG_LINK from
2412 the next use of that destination. */
2414 rtx set
= single_set (insn
);
2417 rtx reg
= SET_DEST (set
);
2419 while (GET_CODE (reg
) == ZERO_EXTRACT
2420 || GET_CODE (reg
) == STRICT_LOW_PART
2421 || GET_CODE (reg
) == SUBREG
)
2422 reg
= XEXP (reg
, 0);
2423 gcc_assert (REG_P (reg
));
2425 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2427 df_insn_rescan (insn
);
2430 /* Return TRUE if combine can reuse reg X in mode MODE.
2431 ADDED_SETS is nonzero if the original set is still required. */
2433 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2441 /* Allow hard registers if the new mode is legal, and occupies no more
2442 registers than the old mode. */
2443 if (regno
< FIRST_PSEUDO_REGISTER
)
2444 return (HARD_REGNO_MODE_OK (regno
, mode
)
2445 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2447 /* Or a pseudo that is only used once. */
2448 return (regno
< reg_n_sets_max
2449 && REG_N_SETS (regno
) == 1
2451 && !REG_USERVAR_P (x
));
2455 /* Check whether X, the destination of a set, refers to part of
2456 the register specified by REG. */
2459 reg_subword_p (rtx x
, rtx reg
)
2461 /* Check that reg is an integer mode register. */
2462 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2465 if (GET_CODE (x
) == STRICT_LOW_PART
2466 || GET_CODE (x
) == ZERO_EXTRACT
)
2469 return GET_CODE (x
) == SUBREG
2470 && SUBREG_REG (x
) == reg
2471 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2474 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2475 Note that the INSN should be deleted *after* removing dead edges, so
2476 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2477 but not for a (set (pc) (label_ref FOO)). */
2480 update_cfg_for_uncondjump (rtx_insn
*insn
)
2482 basic_block bb
= BLOCK_FOR_INSN (insn
);
2483 gcc_assert (BB_END (bb
) == insn
);
2485 purge_dead_edges (bb
);
2488 if (EDGE_COUNT (bb
->succs
) == 1)
2492 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2494 /* Remove barriers from the footer if there are any. */
2495 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2496 if (BARRIER_P (insn
))
2498 if (PREV_INSN (insn
))
2499 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2501 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2502 if (NEXT_INSN (insn
))
2503 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2505 else if (LABEL_P (insn
))
2510 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2511 by an arbitrary number of CLOBBERs. */
2513 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2515 if (GET_CODE (pat
) != PARALLEL
)
2518 int len
= XVECLEN (pat
, 0);
2523 for (i
= 0; i
< n
; i
++)
2524 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2525 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2527 for ( ; i
< len
; i
++)
2528 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2529 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2535 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2536 CLOBBERs), can be split into individual SETs in that order, without
2537 changing semantics. */
2539 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2541 if (!insn_nothrow_p (insn
))
2544 rtx pat
= PATTERN (insn
);
2547 for (i
= 0; i
< n
; i
++)
2549 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2552 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2554 for (j
= i
+ 1; j
< n
; j
++)
2555 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2562 /* Try to combine the insns I0, I1 and I2 into I3.
2563 Here I0, I1 and I2 appear earlier than I3.
2564 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2567 If we are combining more than two insns and the resulting insn is not
2568 recognized, try splitting it into two insns. If that happens, I2 and I3
2569 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2570 Otherwise, I0, I1 and I2 are pseudo-deleted.
2572 Return 0 if the combination does not work. Then nothing is changed.
2573 If we did the combination, return the insn at which combine should
2576 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2577 new direct jump instruction.
2579 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2580 been I3 passed to an earlier try_combine within the same basic
2584 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2585 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2587 /* New patterns for I3 and I2, respectively. */
2588 rtx newpat
, newi2pat
= 0;
2589 rtvec newpat_vec_with_clobbers
= 0;
2590 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2591 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2593 int added_sets_0
, added_sets_1
, added_sets_2
;
2594 /* Total number of SETs to put into I3. */
2596 /* Nonzero if I2's or I1's body now appears in I3. */
2597 int i2_is_used
= 0, i1_is_used
= 0;
2598 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2599 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2600 /* Contains I3 if the destination of I3 is used in its source, which means
2601 that the old life of I3 is being killed. If that usage is placed into
2602 I2 and not in I3, a REG_DEAD note must be made. */
2603 rtx i3dest_killed
= 0;
2604 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2605 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2606 /* Copy of SET_SRC of I1 and I0, if needed. */
2607 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2608 /* Set if I2DEST was reused as a scratch register. */
2609 bool i2scratch
= false;
2610 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2611 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2612 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2613 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2614 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2615 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2616 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2617 /* Notes that must be added to REG_NOTES in I3 and I2. */
2618 rtx new_i3_notes
, new_i2_notes
;
2619 /* Notes that we substituted I3 into I2 instead of the normal case. */
2620 int i3_subst_into_i2
= 0;
2621 /* Notes that I1, I2 or I3 is a MULT operation. */
2624 int changed_i3_dest
= 0;
2627 rtx_insn
*temp_insn
;
2629 struct insn_link
*link
;
2631 rtx new_other_notes
;
2634 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2636 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2639 /* Only try four-insn combinations when there's high likelihood of
2640 success. Look for simple insns, such as loads of constants or
2641 binary operations involving a constant. */
2649 if (!flag_expensive_optimizations
)
2652 for (i
= 0; i
< 4; i
++)
2654 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2655 rtx set
= single_set (insn
);
2659 src
= SET_SRC (set
);
2660 if (CONSTANT_P (src
))
2665 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2667 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2668 || GET_CODE (src
) == LSHIFTRT
)
2672 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2673 are likely manipulating its value. Ideally we'll be able to combine
2674 all four insns into a bitfield insertion of some kind.
2676 Note the source in I0 might be inside a sign/zero extension and the
2677 memory modes in I0 and I3 might be different. So extract the address
2678 from the destination of I3 and search for it in the source of I0.
2680 In the event that there's a match but the source/dest do not actually
2681 refer to the same memory, the worst that happens is we try some
2682 combinations that we wouldn't have otherwise. */
2683 if ((set0
= single_set (i0
))
2684 /* Ensure the source of SET0 is a MEM, possibly buried inside
2686 && (GET_CODE (SET_SRC (set0
)) == MEM
2687 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2688 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2689 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2690 && (set3
= single_set (i3
))
2691 /* Ensure the destination of SET3 is a MEM. */
2692 && GET_CODE (SET_DEST (set3
)) == MEM
2693 /* Would it be better to extract the base address for the MEM
2694 in SET3 and look for that? I don't have cases where it matters
2695 but I could envision such cases. */
2696 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2699 if (ngood
< 2 && nshift
< 2)
2703 /* Exit early if one of the insns involved can't be used for
2706 || (i1
&& CALL_P (i1
))
2707 || (i0
&& CALL_P (i0
))
2708 || cant_combine_insn_p (i3
)
2709 || cant_combine_insn_p (i2
)
2710 || (i1
&& cant_combine_insn_p (i1
))
2711 || (i0
&& cant_combine_insn_p (i0
))
2712 || likely_spilled_retval_p (i3
))
2716 undobuf
.other_insn
= 0;
2718 /* Reset the hard register usage information. */
2719 CLEAR_HARD_REG_SET (newpat_used_regs
);
2721 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2724 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2725 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2727 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2728 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2730 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2731 INSN_UID (i2
), INSN_UID (i3
));
2734 /* If multiple insns feed into one of I2 or I3, they can be in any
2735 order. To simplify the code below, reorder them in sequence. */
2736 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2738 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2740 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2743 added_links_insn
= 0;
2745 /* First check for one important special case that the code below will
2746 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2747 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2748 we may be able to replace that destination with the destination of I3.
2749 This occurs in the common code where we compute both a quotient and
2750 remainder into a structure, in which case we want to do the computation
2751 directly into the structure to avoid register-register copies.
2753 Note that this case handles both multiple sets in I2 and also cases
2754 where I2 has a number of CLOBBERs inside the PARALLEL.
2756 We make very conservative checks below and only try to handle the
2757 most common cases of this. For example, we only handle the case
2758 where I2 and I3 are adjacent to avoid making difficult register
2761 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2762 && REG_P (SET_SRC (PATTERN (i3
)))
2763 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2764 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2765 && GET_CODE (PATTERN (i2
)) == PARALLEL
2766 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2767 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2768 below would need to check what is inside (and reg_overlap_mentioned_p
2769 doesn't support those codes anyway). Don't allow those destinations;
2770 the resulting insn isn't likely to be recognized anyway. */
2771 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2772 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2773 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2774 SET_DEST (PATTERN (i3
)))
2775 && next_active_insn (i2
) == i3
)
2777 rtx p2
= PATTERN (i2
);
2779 /* Make sure that the destination of I3,
2780 which we are going to substitute into one output of I2,
2781 is not used within another output of I2. We must avoid making this:
2782 (parallel [(set (mem (reg 69)) ...)
2783 (set (reg 69) ...)])
2784 which is not well-defined as to order of actions.
2785 (Besides, reload can't handle output reloads for this.)
2787 The problem can also happen if the dest of I3 is a memory ref,
2788 if another dest in I2 is an indirect memory ref. */
2789 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2790 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2791 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2792 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2793 SET_DEST (XVECEXP (p2
, 0, i
))))
2796 /* Make sure this PARALLEL is not an asm. We do not allow combining
2797 that usually (see can_combine_p), so do not here either. */
2798 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2799 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2800 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2803 if (i
== XVECLEN (p2
, 0))
2804 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2805 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2806 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2811 subst_low_luid
= DF_INSN_LUID (i2
);
2813 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2814 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2815 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2816 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2818 /* Replace the dest in I2 with our dest and make the resulting
2819 insn the new pattern for I3. Then skip to where we validate
2820 the pattern. Everything was set up above. */
2821 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2823 i3_subst_into_i2
= 1;
2824 goto validate_replacement
;
2828 /* If I2 is setting a pseudo to a constant and I3 is setting some
2829 sub-part of it to another constant, merge them by making a new
2832 && (temp_expr
= single_set (i2
)) != 0
2833 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2834 && GET_CODE (PATTERN (i3
)) == SET
2835 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2836 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2838 rtx dest
= SET_DEST (PATTERN (i3
));
2842 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2844 if (CONST_INT_P (XEXP (dest
, 1))
2845 && CONST_INT_P (XEXP (dest
, 2)))
2847 width
= INTVAL (XEXP (dest
, 1));
2848 offset
= INTVAL (XEXP (dest
, 2));
2849 dest
= XEXP (dest
, 0);
2850 if (BITS_BIG_ENDIAN
)
2851 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2856 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2857 dest
= XEXP (dest
, 0);
2858 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2864 /* If this is the low part, we're done. */
2865 if (subreg_lowpart_p (dest
))
2867 /* Handle the case where inner is twice the size of outer. */
2868 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2869 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2870 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2871 /* Otherwise give up for now. */
2878 rtx inner
= SET_SRC (PATTERN (i3
));
2879 rtx outer
= SET_SRC (temp_expr
);
2882 = wi::insert (rtx_mode_t (outer
, GET_MODE (SET_DEST (temp_expr
))),
2883 rtx_mode_t (inner
, GET_MODE (dest
)),
2888 subst_low_luid
= DF_INSN_LUID (i2
);
2889 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2890 i2dest
= SET_DEST (temp_expr
);
2891 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2893 /* Replace the source in I2 with the new constant and make the
2894 resulting insn the new pattern for I3. Then skip to where we
2895 validate the pattern. Everything was set up above. */
2896 SUBST (SET_SRC (temp_expr
),
2897 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2899 newpat
= PATTERN (i2
);
2901 /* The dest of I3 has been replaced with the dest of I2. */
2902 changed_i3_dest
= 1;
2903 goto validate_replacement
;
2907 /* If we have no I1 and I2 looks like:
2908 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2910 make up a dummy I1 that is
2913 (set (reg:CC X) (compare:CC Y (const_int 0)))
2915 (We can ignore any trailing CLOBBERs.)
2917 This undoes a previous combination and allows us to match a branch-and-
2920 if (!HAVE_cc0
&& i1
== 0
2921 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2922 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2924 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2925 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2926 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2927 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2928 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2929 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2931 /* We make I1 with the same INSN_UID as I2. This gives it
2932 the same DF_INSN_LUID for value tracking. Our fake I1 will
2933 never appear in the insn stream so giving it the same INSN_UID
2934 as I2 will not cause a problem. */
2936 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2937 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2939 INSN_UID (i1
) = INSN_UID (i2
);
2941 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2942 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2943 SET_DEST (PATTERN (i1
)));
2944 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2945 SUBST_LINK (LOG_LINKS (i2
),
2946 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2949 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2950 make those two SETs separate I1 and I2 insns, and make an I0 that is
2952 if (!HAVE_cc0
&& i0
== 0
2953 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2954 && can_split_parallel_of_n_reg_sets (i2
, 2)
2955 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2956 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2958 /* If there is no I1, there is no I0 either. */
2961 /* We make I1 with the same INSN_UID as I2. This gives it
2962 the same DF_INSN_LUID for value tracking. Our fake I1 will
2963 never appear in the insn stream so giving it the same INSN_UID
2964 as I2 will not cause a problem. */
2966 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2967 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2969 INSN_UID (i1
) = INSN_UID (i2
);
2971 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2974 /* Verify that I2 and I1 are valid for combining. */
2975 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2976 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2978 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2985 /* Record whether I2DEST is used in I2SRC and similarly for the other
2986 cases. Knowing this will help in register status updating below. */
2987 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2988 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2989 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2990 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2991 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2992 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2993 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2994 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2995 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2997 /* For the earlier insns, determine which of the subsequent ones they
2999 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3000 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3001 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3002 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3003 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3005 /* Ensure that I3's pattern can be the destination of combines. */
3006 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3007 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3008 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3009 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3016 /* See if any of the insns is a MULT operation. Unless one is, we will
3017 reject a combination that is, since it must be slower. Be conservative
3019 if (GET_CODE (i2src
) == MULT
3020 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3021 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3022 || (GET_CODE (PATTERN (i3
)) == SET
3023 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3026 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3027 We used to do this EXCEPT in one case: I3 has a post-inc in an
3028 output operand. However, that exception can give rise to insns like
3030 which is a famous insn on the PDP-11 where the value of r3 used as the
3031 source was model-dependent. Avoid this sort of thing. */
3034 if (!(GET_CODE (PATTERN (i3
)) == SET
3035 && REG_P (SET_SRC (PATTERN (i3
)))
3036 && MEM_P (SET_DEST (PATTERN (i3
)))
3037 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3038 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3039 /* It's not the exception. */
3044 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3045 if (REG_NOTE_KIND (link
) == REG_INC
3046 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3048 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3055 /* See if the SETs in I1 or I2 need to be kept around in the merged
3056 instruction: whenever the value set there is still needed past I3.
3057 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3059 For the SET in I1, we have two cases: if I1 and I2 independently feed
3060 into I3, the set in I1 needs to be kept around unless I1DEST dies
3061 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3062 in I1 needs to be kept around unless I1DEST dies or is set in either
3063 I2 or I3. The same considerations apply to I0. */
3065 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3068 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3069 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3074 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3075 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3076 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3077 && dead_or_set_p (i2
, i0dest
)));
3081 /* We are about to copy insns for the case where they need to be kept
3082 around. Check that they can be copied in the merged instruction. */
3084 if (targetm
.cannot_copy_insn_p
3085 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3086 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3087 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3093 /* If the set in I2 needs to be kept around, we must make a copy of
3094 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3095 PATTERN (I2), we are only substituting for the original I1DEST, not into
3096 an already-substituted copy. This also prevents making self-referential
3097 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3102 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3103 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3105 i2pat
= copy_rtx (PATTERN (i2
));
3110 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3111 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3113 i1pat
= copy_rtx (PATTERN (i1
));
3118 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3119 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3121 i0pat
= copy_rtx (PATTERN (i0
));
3126 /* Substitute in the latest insn for the regs set by the earlier ones. */
3128 maxreg
= max_reg_num ();
3132 /* Many machines that don't use CC0 have insns that can both perform an
3133 arithmetic operation and set the condition code. These operations will
3134 be represented as a PARALLEL with the first element of the vector
3135 being a COMPARE of an arithmetic operation with the constant zero.
3136 The second element of the vector will set some pseudo to the result
3137 of the same arithmetic operation. If we simplify the COMPARE, we won't
3138 match such a pattern and so will generate an extra insn. Here we test
3139 for this case, where both the comparison and the operation result are
3140 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3141 I2SRC. Later we will make the PARALLEL that contains I2. */
3143 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3144 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3145 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3146 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3149 rtx
*cc_use_loc
= NULL
;
3150 rtx_insn
*cc_use_insn
= NULL
;
3151 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3152 machine_mode compare_mode
, orig_compare_mode
;
3153 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3155 newpat
= PATTERN (i3
);
3156 newpat_dest
= SET_DEST (newpat
);
3157 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3159 if (undobuf
.other_insn
== 0
3160 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3163 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3164 compare_code
= simplify_compare_const (compare_code
,
3165 GET_MODE (i2dest
), op0
, &op1
);
3166 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3169 /* Do the rest only if op1 is const0_rtx, which may be the
3170 result of simplification. */
3171 if (op1
== const0_rtx
)
3173 /* If a single use of the CC is found, prepare to modify it
3174 when SELECT_CC_MODE returns a new CC-class mode, or when
3175 the above simplify_compare_const() returned a new comparison
3176 operator. undobuf.other_insn is assigned the CC use insn
3177 when modifying it. */
3180 #ifdef SELECT_CC_MODE
3181 machine_mode new_mode
3182 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3183 if (new_mode
!= orig_compare_mode
3184 && can_change_dest_mode (SET_DEST (newpat
),
3185 added_sets_2
, new_mode
))
3187 unsigned int regno
= REGNO (newpat_dest
);
3188 compare_mode
= new_mode
;
3189 if (regno
< FIRST_PSEUDO_REGISTER
)
3190 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3193 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3194 newpat_dest
= regno_reg_rtx
[regno
];
3198 /* Cases for modifying the CC-using comparison. */
3199 if (compare_code
!= orig_compare_code
3200 /* ??? Do we need to verify the zero rtx? */
3201 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3203 /* Replace cc_use_loc with entire new RTX. */
3205 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3206 newpat_dest
, const0_rtx
));
3207 undobuf
.other_insn
= cc_use_insn
;
3209 else if (compare_mode
!= orig_compare_mode
)
3211 /* Just replace the CC reg with a new mode. */
3212 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3213 undobuf
.other_insn
= cc_use_insn
;
3217 /* Now we modify the current newpat:
3218 First, SET_DEST(newpat) is updated if the CC mode has been
3219 altered. For targets without SELECT_CC_MODE, this should be
3221 if (compare_mode
!= orig_compare_mode
)
3222 SUBST (SET_DEST (newpat
), newpat_dest
);
3223 /* This is always done to propagate i2src into newpat. */
3224 SUBST (SET_SRC (newpat
),
3225 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3226 /* Create new version of i2pat if needed; the below PARALLEL
3227 creation needs this to work correctly. */
3228 if (! rtx_equal_p (i2src
, op0
))
3229 i2pat
= gen_rtx_SET (i2dest
, op0
);
3234 if (i2_is_used
== 0)
3236 /* It is possible that the source of I2 or I1 may be performing
3237 an unneeded operation, such as a ZERO_EXTEND of something
3238 that is known to have the high part zero. Handle that case
3239 by letting subst look at the inner insns.
3241 Another way to do this would be to have a function that tries
3242 to simplify a single insn instead of merging two or more
3243 insns. We don't do this because of the potential of infinite
3244 loops and because of the potential extra memory required.
3245 However, doing it the way we are is a bit of a kludge and
3246 doesn't catch all cases.
3248 But only do this if -fexpensive-optimizations since it slows
3249 things down and doesn't usually win.
3251 This is not done in the COMPARE case above because the
3252 unmodified I2PAT is used in the PARALLEL and so a pattern
3253 with a modified I2SRC would not match. */
3255 if (flag_expensive_optimizations
)
3257 /* Pass pc_rtx so no substitutions are done, just
3261 subst_low_luid
= DF_INSN_LUID (i1
);
3262 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3265 subst_low_luid
= DF_INSN_LUID (i2
);
3266 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3269 n_occurrences
= 0; /* `subst' counts here */
3270 subst_low_luid
= DF_INSN_LUID (i2
);
3272 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3273 copy of I2SRC each time we substitute it, in order to avoid creating
3274 self-referential RTL when we will be substituting I1SRC for I1DEST
3275 later. Likewise if I0 feeds into I2, either directly or indirectly
3276 through I1, and I0DEST is in I0SRC. */
3277 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3278 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3279 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3280 && i0dest_in_i0src
));
3283 /* Record whether I2's body now appears within I3's body. */
3284 i2_is_used
= n_occurrences
;
3287 /* If we already got a failure, don't try to do more. Otherwise, try to
3288 substitute I1 if we have it. */
3290 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3292 /* Check that an autoincrement side-effect on I1 has not been lost.
3293 This happens if I1DEST is mentioned in I2 and dies there, and
3294 has disappeared from the new pattern. */
3295 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3297 && dead_or_set_p (i2
, i1dest
)
3298 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3299 /* Before we can do this substitution, we must redo the test done
3300 above (see detailed comments there) that ensures I1DEST isn't
3301 mentioned in any SETs in NEWPAT that are field assignments. */
3302 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3310 subst_low_luid
= DF_INSN_LUID (i1
);
3312 /* If the following substitution will modify I1SRC, make a copy of it
3313 for the case where it is substituted for I1DEST in I2PAT later. */
3314 if (added_sets_2
&& i1_feeds_i2_n
)
3315 i1src_copy
= copy_rtx (i1src
);
3317 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3318 copy of I1SRC each time we substitute it, in order to avoid creating
3319 self-referential RTL when we will be substituting I0SRC for I0DEST
3321 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3322 i0_feeds_i1_n
&& i0dest_in_i0src
);
3325 /* Record whether I1's body now appears within I3's body. */
3326 i1_is_used
= n_occurrences
;
3329 /* Likewise for I0 if we have it. */
3331 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3333 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3334 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3335 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3336 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3337 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3344 /* If the following substitution will modify I0SRC, make a copy of it
3345 for the case where it is substituted for I0DEST in I1PAT later. */
3346 if (added_sets_1
&& i0_feeds_i1_n
)
3347 i0src_copy
= copy_rtx (i0src
);
3348 /* And a copy for I0DEST in I2PAT substitution. */
3349 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3350 || (i0_feeds_i2_n
)))
3351 i0src_copy2
= copy_rtx (i0src
);
3354 subst_low_luid
= DF_INSN_LUID (i0
);
3355 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3359 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3360 to count all the ways that I2SRC and I1SRC can be used. */
3361 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3362 && i2_is_used
+ added_sets_2
> 1)
3363 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3364 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3366 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3367 && (n_occurrences
+ added_sets_0
3368 + (added_sets_1
&& i0_feeds_i1_n
)
3369 + (added_sets_2
&& i0_feeds_i2_n
)
3371 /* Fail if we tried to make a new register. */
3372 || max_reg_num () != maxreg
3373 /* Fail if we couldn't do something and have a CLOBBER. */
3374 || GET_CODE (newpat
) == CLOBBER
3375 /* Fail if this new pattern is a MULT and we didn't have one before
3376 at the outer level. */
3377 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3384 /* If the actions of the earlier insns must be kept
3385 in addition to substituting them into the latest one,
3386 we must make a new PARALLEL for the latest insn
3387 to hold additional the SETs. */
3389 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3391 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3394 if (GET_CODE (newpat
) == PARALLEL
)
3396 rtvec old
= XVEC (newpat
, 0);
3397 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3398 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3399 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3400 sizeof (old
->elem
[0]) * old
->num_elem
);
3405 total_sets
= 1 + extra_sets
;
3406 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3407 XVECEXP (newpat
, 0, 0) = old
;
3411 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3417 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3419 XVECEXP (newpat
, 0, --total_sets
) = t
;
3425 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3426 i0_feeds_i1_n
&& i0dest_in_i0src
);
3427 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3428 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3430 XVECEXP (newpat
, 0, --total_sets
) = t
;
3434 validate_replacement
:
3436 /* Note which hard regs this insn has as inputs. */
3437 mark_used_regs_combine (newpat
);
3439 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3440 consider splitting this pattern, we might need these clobbers. */
3441 if (i1
&& GET_CODE (newpat
) == PARALLEL
3442 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3444 int len
= XVECLEN (newpat
, 0);
3446 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3447 for (i
= 0; i
< len
; i
++)
3448 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3451 /* We have recognized nothing yet. */
3452 insn_code_number
= -1;
3454 /* See if this is a PARALLEL of two SETs where one SET's destination is
3455 a register that is unused and this isn't marked as an instruction that
3456 might trap in an EH region. In that case, we just need the other SET.
3457 We prefer this over the PARALLEL.
3459 This can occur when simplifying a divmod insn. We *must* test for this
3460 case here because the code below that splits two independent SETs doesn't
3461 handle this case correctly when it updates the register status.
3463 It's pointless doing this if we originally had two sets, one from
3464 i3, and one from i2. Combining then splitting the parallel results
3465 in the original i2 again plus an invalid insn (which we delete).
3466 The net effect is only to move instructions around, which makes
3467 debug info less accurate. */
3469 if (!(added_sets_2
&& i1
== 0)
3470 && is_parallel_of_n_reg_sets (newpat
, 2)
3471 && asm_noperands (newpat
) < 0)
3473 rtx set0
= XVECEXP (newpat
, 0, 0);
3474 rtx set1
= XVECEXP (newpat
, 0, 1);
3475 rtx oldpat
= newpat
;
3477 if (((REG_P (SET_DEST (set1
))
3478 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3479 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3480 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3481 && insn_nothrow_p (i3
)
3482 && !side_effects_p (SET_SRC (set1
)))
3485 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3488 else if (((REG_P (SET_DEST (set0
))
3489 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3490 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3491 && find_reg_note (i3
, REG_UNUSED
,
3492 SUBREG_REG (SET_DEST (set0
)))))
3493 && insn_nothrow_p (i3
)
3494 && !side_effects_p (SET_SRC (set0
)))
3497 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3499 if (insn_code_number
>= 0)
3500 changed_i3_dest
= 1;
3503 if (insn_code_number
< 0)
3507 /* Is the result of combination a valid instruction? */
3508 if (insn_code_number
< 0)
3509 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3511 /* If we were combining three insns and the result is a simple SET
3512 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3513 insns. There are two ways to do this. It can be split using a
3514 machine-specific method (like when you have an addition of a large
3515 constant) or by combine in the function find_split_point. */
3517 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3518 && asm_noperands (newpat
) < 0)
3520 rtx parallel
, *split
;
3521 rtx_insn
*m_split_insn
;
3523 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3524 use I2DEST as a scratch register will help. In the latter case,
3525 convert I2DEST to the mode of the source of NEWPAT if we can. */
3527 m_split_insn
= combine_split_insns (newpat
, i3
);
3529 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3530 inputs of NEWPAT. */
3532 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3533 possible to try that as a scratch reg. This would require adding
3534 more code to make it work though. */
3536 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3538 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3540 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3541 (temporarily, until we are committed to this instruction
3542 combination) does not work: for example, any call to nonzero_bits
3543 on the register (from a splitter in the MD file, for example)
3544 will get the old information, which is invalid.
3546 Since nowadays we can create registers during combine just fine,
3547 we should just create a new one here, not reuse i2dest. */
3549 /* First try to split using the original register as a
3550 scratch register. */
3551 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3552 gen_rtvec (2, newpat
,
3553 gen_rtx_CLOBBER (VOIDmode
,
3555 m_split_insn
= combine_split_insns (parallel
, i3
);
3557 /* If that didn't work, try changing the mode of I2DEST if
3559 if (m_split_insn
== 0
3560 && new_mode
!= GET_MODE (i2dest
)
3561 && new_mode
!= VOIDmode
3562 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3564 machine_mode old_mode
= GET_MODE (i2dest
);
3567 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3568 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3571 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3572 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3575 parallel
= (gen_rtx_PARALLEL
3577 gen_rtvec (2, newpat
,
3578 gen_rtx_CLOBBER (VOIDmode
,
3580 m_split_insn
= combine_split_insns (parallel
, i3
);
3582 if (m_split_insn
== 0
3583 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3587 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3588 buf
= undobuf
.undos
;
3589 undobuf
.undos
= buf
->next
;
3590 buf
->next
= undobuf
.frees
;
3591 undobuf
.frees
= buf
;
3595 i2scratch
= m_split_insn
!= 0;
3598 /* If recog_for_combine has discarded clobbers, try to use them
3599 again for the split. */
3600 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3602 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3603 m_split_insn
= combine_split_insns (parallel
, i3
);
3606 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3608 rtx m_split_pat
= PATTERN (m_split_insn
);
3609 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3610 if (insn_code_number
>= 0)
3611 newpat
= m_split_pat
;
3613 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3614 && (next_nonnote_nondebug_insn (i2
) == i3
3615 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3618 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3619 newi2pat
= PATTERN (m_split_insn
);
3621 i3set
= single_set (NEXT_INSN (m_split_insn
));
3622 i2set
= single_set (m_split_insn
);
3624 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3626 /* If I2 or I3 has multiple SETs, we won't know how to track
3627 register status, so don't use these insns. If I2's destination
3628 is used between I2 and I3, we also can't use these insns. */
3630 if (i2_code_number
>= 0 && i2set
&& i3set
3631 && (next_nonnote_nondebug_insn (i2
) == i3
3632 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3633 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3635 if (insn_code_number
>= 0)
3638 /* It is possible that both insns now set the destination of I3.
3639 If so, we must show an extra use of it. */
3641 if (insn_code_number
>= 0)
3643 rtx new_i3_dest
= SET_DEST (i3set
);
3644 rtx new_i2_dest
= SET_DEST (i2set
);
3646 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3647 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3648 || GET_CODE (new_i3_dest
) == SUBREG
)
3649 new_i3_dest
= XEXP (new_i3_dest
, 0);
3651 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3652 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3653 || GET_CODE (new_i2_dest
) == SUBREG
)
3654 new_i2_dest
= XEXP (new_i2_dest
, 0);
3656 if (REG_P (new_i3_dest
)
3657 && REG_P (new_i2_dest
)
3658 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3659 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3660 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3664 /* If we can split it and use I2DEST, go ahead and see if that
3665 helps things be recognized. Verify that none of the registers
3666 are set between I2 and I3. */
3667 if (insn_code_number
< 0
3668 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3669 && (!HAVE_cc0
|| REG_P (i2dest
))
3670 /* We need I2DEST in the proper mode. If it is a hard register
3671 or the only use of a pseudo, we can change its mode.
3672 Make sure we don't change a hard register to have a mode that
3673 isn't valid for it, or change the number of registers. */
3674 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3675 || GET_MODE (*split
) == VOIDmode
3676 || can_change_dest_mode (i2dest
, added_sets_2
,
3678 && (next_nonnote_nondebug_insn (i2
) == i3
3679 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3680 /* We can't overwrite I2DEST if its value is still used by
3682 && ! reg_referenced_p (i2dest
, newpat
))
3684 rtx newdest
= i2dest
;
3685 enum rtx_code split_code
= GET_CODE (*split
);
3686 machine_mode split_mode
= GET_MODE (*split
);
3687 bool subst_done
= false;
3688 newi2pat
= NULL_RTX
;
3692 /* *SPLIT may be part of I2SRC, so make sure we have the
3693 original expression around for later debug processing.
3694 We should not need I2SRC any more in other cases. */
3695 if (MAY_HAVE_DEBUG_INSNS
)
3696 i2src
= copy_rtx (i2src
);
3700 /* Get NEWDEST as a register in the proper mode. We have already
3701 validated that we can do this. */
3702 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3704 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3705 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3708 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3709 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3713 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3714 an ASHIFT. This can occur if it was inside a PLUS and hence
3715 appeared to be a memory address. This is a kludge. */
3716 if (split_code
== MULT
3717 && CONST_INT_P (XEXP (*split
, 1))
3718 && INTVAL (XEXP (*split
, 1)) > 0
3719 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3721 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3722 XEXP (*split
, 0), GEN_INT (i
)));
3723 /* Update split_code because we may not have a multiply
3725 split_code
= GET_CODE (*split
);
3728 /* Similarly for (plus (mult FOO (const_int pow2))). */
3729 if (split_code
== PLUS
3730 && GET_CODE (XEXP (*split
, 0)) == MULT
3731 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3732 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3733 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3735 rtx nsplit
= XEXP (*split
, 0);
3736 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3737 XEXP (nsplit
, 0), GEN_INT (i
)));
3738 /* Update split_code because we may not have a multiply
3740 split_code
= GET_CODE (*split
);
3743 #ifdef INSN_SCHEDULING
3744 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3745 be written as a ZERO_EXTEND. */
3746 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3748 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3749 what it really is. */
3750 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3752 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3753 SUBREG_REG (*split
)));
3755 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3756 SUBREG_REG (*split
)));
3760 /* Attempt to split binary operators using arithmetic identities. */
3761 if (BINARY_P (SET_SRC (newpat
))
3762 && split_mode
== GET_MODE (SET_SRC (newpat
))
3763 && ! side_effects_p (SET_SRC (newpat
)))
3765 rtx setsrc
= SET_SRC (newpat
);
3766 machine_mode mode
= GET_MODE (setsrc
);
3767 enum rtx_code code
= GET_CODE (setsrc
);
3768 rtx src_op0
= XEXP (setsrc
, 0);
3769 rtx src_op1
= XEXP (setsrc
, 1);
3771 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3772 if (rtx_equal_p (src_op0
, src_op1
))
3774 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3775 SUBST (XEXP (setsrc
, 0), newdest
);
3776 SUBST (XEXP (setsrc
, 1), newdest
);
3779 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3780 else if ((code
== PLUS
|| code
== MULT
)
3781 && GET_CODE (src_op0
) == code
3782 && GET_CODE (XEXP (src_op0
, 0)) == code
3783 && (INTEGRAL_MODE_P (mode
)
3784 || (FLOAT_MODE_P (mode
)
3785 && flag_unsafe_math_optimizations
)))
3787 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3788 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3789 rtx r
= XEXP (src_op0
, 1);
3792 /* Split both "((X op Y) op X) op Y" and
3793 "((X op Y) op Y) op X" as "T op T" where T is
3795 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3796 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3798 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3799 SUBST (XEXP (setsrc
, 0), newdest
);
3800 SUBST (XEXP (setsrc
, 1), newdest
);
3803 /* Split "((X op X) op Y) op Y)" as "T op T" where
3805 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3807 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3808 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3809 SUBST (XEXP (setsrc
, 0), newdest
);
3810 SUBST (XEXP (setsrc
, 1), newdest
);
3818 newi2pat
= gen_rtx_SET (newdest
, *split
);
3819 SUBST (*split
, newdest
);
3822 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3824 /* recog_for_combine might have added CLOBBERs to newi2pat.
3825 Make sure NEWPAT does not depend on the clobbered regs. */
3826 if (GET_CODE (newi2pat
) == PARALLEL
)
3827 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3828 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3830 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3831 if (reg_overlap_mentioned_p (reg
, newpat
))
3838 /* If the split point was a MULT and we didn't have one before,
3839 don't use one now. */
3840 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3841 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3845 /* Check for a case where we loaded from memory in a narrow mode and
3846 then sign extended it, but we need both registers. In that case,
3847 we have a PARALLEL with both loads from the same memory location.
3848 We can split this into a load from memory followed by a register-register
3849 copy. This saves at least one insn, more if register allocation can
3852 We cannot do this if the destination of the first assignment is a
3853 condition code register or cc0. We eliminate this case by making sure
3854 the SET_DEST and SET_SRC have the same mode.
3856 We cannot do this if the destination of the second assignment is
3857 a register that we have already assumed is zero-extended. Similarly
3858 for a SUBREG of such a register. */
3860 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3861 && GET_CODE (newpat
) == PARALLEL
3862 && XVECLEN (newpat
, 0) == 2
3863 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3864 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3865 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3866 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3867 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3868 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3869 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3870 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3872 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3873 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3874 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3876 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3877 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3878 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3879 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3880 != GET_MODE_MASK (word_mode
))))
3881 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3882 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3884 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3885 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3886 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3887 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3888 != GET_MODE_MASK (word_mode
)))))
3889 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3890 SET_SRC (XVECEXP (newpat
, 0, 1)))
3891 && ! find_reg_note (i3
, REG_UNUSED
,
3892 SET_DEST (XVECEXP (newpat
, 0, 0))))
3896 newi2pat
= XVECEXP (newpat
, 0, 0);
3897 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3898 newpat
= XVECEXP (newpat
, 0, 1);
3899 SUBST (SET_SRC (newpat
),
3900 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3901 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3903 if (i2_code_number
>= 0)
3904 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3906 if (insn_code_number
>= 0)
3910 /* Similarly, check for a case where we have a PARALLEL of two independent
3911 SETs but we started with three insns. In this case, we can do the sets
3912 as two separate insns. This case occurs when some SET allows two
3913 other insns to combine, but the destination of that SET is still live.
3915 Also do this if we started with two insns and (at least) one of the
3916 resulting sets is a noop; this noop will be deleted later. */
3918 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3919 && GET_CODE (newpat
) == PARALLEL
3920 && XVECLEN (newpat
, 0) == 2
3921 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3922 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3923 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3924 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3925 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3926 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3927 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3928 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3929 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3930 XVECEXP (newpat
, 0, 0))
3931 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3932 XVECEXP (newpat
, 0, 1))
3933 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3934 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3936 rtx set0
= XVECEXP (newpat
, 0, 0);
3937 rtx set1
= XVECEXP (newpat
, 0, 1);
3939 /* Normally, it doesn't matter which of the two is done first,
3940 but the one that references cc0 can't be the second, and
3941 one which uses any regs/memory set in between i2 and i3 can't
3942 be first. The PARALLEL might also have been pre-existing in i3,
3943 so we need to make sure that we won't wrongly hoist a SET to i2
3944 that would conflict with a death note present in there. */
3945 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3946 && !(REG_P (SET_DEST (set1
))
3947 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3948 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3949 && find_reg_note (i2
, REG_DEAD
,
3950 SUBREG_REG (SET_DEST (set1
))))
3951 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3952 /* If I3 is a jump, ensure that set0 is a jump so that
3953 we do not create invalid RTL. */
3954 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3960 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3961 && !(REG_P (SET_DEST (set0
))
3962 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3963 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3964 && find_reg_note (i2
, REG_DEAD
,
3965 SUBREG_REG (SET_DEST (set0
))))
3966 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3967 /* If I3 is a jump, ensure that set1 is a jump so that
3968 we do not create invalid RTL. */
3969 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3981 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3983 if (i2_code_number
>= 0)
3985 /* recog_for_combine might have added CLOBBERs to newi2pat.
3986 Make sure NEWPAT does not depend on the clobbered regs. */
3987 if (GET_CODE (newi2pat
) == PARALLEL
)
3989 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3990 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3992 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3993 if (reg_overlap_mentioned_p (reg
, newpat
))
4001 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4005 /* If it still isn't recognized, fail and change things back the way they
4007 if ((insn_code_number
< 0
4008 /* Is the result a reasonable ASM_OPERANDS? */
4009 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4015 /* If we had to change another insn, make sure it is valid also. */
4016 if (undobuf
.other_insn
)
4018 CLEAR_HARD_REG_SET (newpat_used_regs
);
4020 other_pat
= PATTERN (undobuf
.other_insn
);
4021 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4024 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4031 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4032 they are adjacent to each other or not. */
4035 rtx_insn
*p
= prev_nonnote_insn (i3
);
4036 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4037 && sets_cc0_p (newi2pat
))
4044 /* Only allow this combination if insn_rtx_costs reports that the
4045 replacement instructions are cheaper than the originals. */
4046 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4052 if (MAY_HAVE_DEBUG_INSNS
)
4056 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4057 if (undo
->kind
== UNDO_MODE
)
4059 rtx reg
= *undo
->where
.r
;
4060 machine_mode new_mode
= GET_MODE (reg
);
4061 machine_mode old_mode
= undo
->old_contents
.m
;
4063 /* Temporarily revert mode back. */
4064 adjust_reg_mode (reg
, old_mode
);
4066 if (reg
== i2dest
&& i2scratch
)
4068 /* If we used i2dest as a scratch register with a
4069 different mode, substitute it for the original
4070 i2src while its original mode is temporarily
4071 restored, and then clear i2scratch so that we don't
4072 do it again later. */
4073 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4076 /* Put back the new mode. */
4077 adjust_reg_mode (reg
, new_mode
);
4081 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4082 rtx_insn
*first
, *last
;
4087 last
= last_combined_insn
;
4092 last
= undobuf
.other_insn
;
4094 if (DF_INSN_LUID (last
)
4095 < DF_INSN_LUID (last_combined_insn
))
4096 last
= last_combined_insn
;
4099 /* We're dealing with a reg that changed mode but not
4100 meaning, so we want to turn it into a subreg for
4101 the new mode. However, because of REG sharing and
4102 because its mode had already changed, we have to do
4103 it in two steps. First, replace any debug uses of
4104 reg, with its original mode temporarily restored,
4105 with this copy we have created; then, replace the
4106 copy with the SUBREG of the original shared reg,
4107 once again changed to the new mode. */
4108 propagate_for_debug (first
, last
, reg
, tempreg
,
4110 adjust_reg_mode (reg
, new_mode
);
4111 propagate_for_debug (first
, last
, tempreg
,
4112 lowpart_subreg (old_mode
, reg
, new_mode
),
4118 /* If we will be able to accept this, we have made a
4119 change to the destination of I3. This requires us to
4120 do a few adjustments. */
4122 if (changed_i3_dest
)
4124 PATTERN (i3
) = newpat
;
4125 adjust_for_new_dest (i3
);
4128 /* We now know that we can do this combination. Merge the insns and
4129 update the status of registers and LOG_LINKS. */
4131 if (undobuf
.other_insn
)
4135 PATTERN (undobuf
.other_insn
) = other_pat
;
4137 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4138 ensure that they are still valid. Then add any non-duplicate
4139 notes added by recog_for_combine. */
4140 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4142 next
= XEXP (note
, 1);
4144 if ((REG_NOTE_KIND (note
) == REG_DEAD
4145 && !reg_referenced_p (XEXP (note
, 0),
4146 PATTERN (undobuf
.other_insn
)))
4147 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4148 && !reg_set_p (XEXP (note
, 0),
4149 PATTERN (undobuf
.other_insn
))))
4150 remove_note (undobuf
.other_insn
, note
);
4153 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4154 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4161 struct insn_link
*link
;
4164 /* I3 now uses what used to be its destination and which is now
4165 I2's destination. This requires us to do a few adjustments. */
4166 PATTERN (i3
) = newpat
;
4167 adjust_for_new_dest (i3
);
4169 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4172 However, some later insn might be using I2's dest and have
4173 a LOG_LINK pointing at I3. We must remove this link.
4174 The simplest way to remove the link is to point it at I1,
4175 which we know will be a NOTE. */
4177 /* newi2pat is usually a SET here; however, recog_for_combine might
4178 have added some clobbers. */
4179 if (GET_CODE (newi2pat
) == PARALLEL
)
4180 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4182 ni2dest
= SET_DEST (newi2pat
);
4184 for (insn
= NEXT_INSN (i3
);
4185 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4186 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4187 insn
= NEXT_INSN (insn
))
4189 if (NONDEBUG_INSN_P (insn
)
4190 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4192 FOR_EACH_LOG_LINK (link
, insn
)
4193 if (link
->insn
== i3
)
4202 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4203 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4206 /* Compute which registers we expect to eliminate. newi2pat may be setting
4207 either i3dest or i2dest, so we must check it. */
4208 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4209 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4212 /* For i1, we need to compute both local elimination and global
4213 elimination information with respect to newi2pat because i1dest
4214 may be the same as i3dest, in which case newi2pat may be setting
4215 i1dest. Global information is used when distributing REG_DEAD
4216 note for i2 and i3, in which case it does matter if newi2pat sets
4219 Local information is used when distributing REG_DEAD note for i1,
4220 in which case it doesn't matter if newi2pat sets i1dest or not.
4221 See PR62151, if we have four insns combination:
4223 i1: r1 <- i1src (using r0)
4225 i2: r0 <- i2src (using r1)
4226 i3: r3 <- i3src (using r0)
4228 From i1's point of view, r0 is eliminated, no matter if it is set
4229 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4230 should be discarded.
4232 Note local information only affects cases in forms like "I1->I2->I3",
4233 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4234 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4236 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4239 rtx elim_i1
= (local_elim_i1
== 0
4240 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4242 /* Same case as i1. */
4243 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4245 rtx elim_i0
= (local_elim_i0
== 0
4246 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4249 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4251 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4252 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4254 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4256 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4258 /* Ensure that we do not have something that should not be shared but
4259 occurs multiple times in the new insns. Check this by first
4260 resetting all the `used' flags and then copying anything is shared. */
4262 reset_used_flags (i3notes
);
4263 reset_used_flags (i2notes
);
4264 reset_used_flags (i1notes
);
4265 reset_used_flags (i0notes
);
4266 reset_used_flags (newpat
);
4267 reset_used_flags (newi2pat
);
4268 if (undobuf
.other_insn
)
4269 reset_used_flags (PATTERN (undobuf
.other_insn
));
4271 i3notes
= copy_rtx_if_shared (i3notes
);
4272 i2notes
= copy_rtx_if_shared (i2notes
);
4273 i1notes
= copy_rtx_if_shared (i1notes
);
4274 i0notes
= copy_rtx_if_shared (i0notes
);
4275 newpat
= copy_rtx_if_shared (newpat
);
4276 newi2pat
= copy_rtx_if_shared (newi2pat
);
4277 if (undobuf
.other_insn
)
4278 reset_used_flags (PATTERN (undobuf
.other_insn
));
4280 INSN_CODE (i3
) = insn_code_number
;
4281 PATTERN (i3
) = newpat
;
4283 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4285 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4287 reset_used_flags (call_usage
);
4288 call_usage
= copy_rtx (call_usage
);
4292 /* I2SRC must still be meaningful at this point. Some splitting
4293 operations can invalidate I2SRC, but those operations do not
4296 replace_rtx (call_usage
, i2dest
, i2src
);
4300 replace_rtx (call_usage
, i1dest
, i1src
);
4302 replace_rtx (call_usage
, i0dest
, i0src
);
4304 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4307 if (undobuf
.other_insn
)
4308 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4310 /* We had one special case above where I2 had more than one set and
4311 we replaced a destination of one of those sets with the destination
4312 of I3. In that case, we have to update LOG_LINKS of insns later
4313 in this basic block. Note that this (expensive) case is rare.
4315 Also, in this case, we must pretend that all REG_NOTEs for I2
4316 actually came from I3, so that REG_UNUSED notes from I2 will be
4317 properly handled. */
4319 if (i3_subst_into_i2
)
4321 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4322 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4323 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4324 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4325 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4326 && ! find_reg_note (i2
, REG_UNUSED
,
4327 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4328 for (temp_insn
= NEXT_INSN (i2
);
4330 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4331 || BB_HEAD (this_basic_block
) != temp_insn
);
4332 temp_insn
= NEXT_INSN (temp_insn
))
4333 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4334 FOR_EACH_LOG_LINK (link
, temp_insn
)
4335 if (link
->insn
== i2
)
4341 while (XEXP (link
, 1))
4342 link
= XEXP (link
, 1);
4343 XEXP (link
, 1) = i2notes
;
4350 LOG_LINKS (i3
) = NULL
;
4352 LOG_LINKS (i2
) = NULL
;
4357 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4358 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4360 INSN_CODE (i2
) = i2_code_number
;
4361 PATTERN (i2
) = newi2pat
;
4365 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4366 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4368 SET_INSN_DELETED (i2
);
4373 LOG_LINKS (i1
) = NULL
;
4375 if (MAY_HAVE_DEBUG_INSNS
)
4376 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4378 SET_INSN_DELETED (i1
);
4383 LOG_LINKS (i0
) = NULL
;
4385 if (MAY_HAVE_DEBUG_INSNS
)
4386 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4388 SET_INSN_DELETED (i0
);
4391 /* Get death notes for everything that is now used in either I3 or
4392 I2 and used to die in a previous insn. If we built two new
4393 patterns, move from I1 to I2 then I2 to I3 so that we get the
4394 proper movement on registers that I2 modifies. */
4397 from_luid
= DF_INSN_LUID (i0
);
4399 from_luid
= DF_INSN_LUID (i1
);
4401 from_luid
= DF_INSN_LUID (i2
);
4403 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4404 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4406 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4408 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4409 elim_i2
, elim_i1
, elim_i0
);
4411 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4412 elim_i2
, elim_i1
, elim_i0
);
4414 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4415 elim_i2
, local_elim_i1
, local_elim_i0
);
4417 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4418 elim_i2
, elim_i1
, local_elim_i0
);
4420 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4421 elim_i2
, elim_i1
, elim_i0
);
4423 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4424 know these are REG_UNUSED and want them to go to the desired insn,
4425 so we always pass it as i3. */
4427 if (newi2pat
&& new_i2_notes
)
4428 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4432 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4435 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4436 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4437 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4438 in that case, it might delete I2. Similarly for I2 and I1.
4439 Show an additional death due to the REG_DEAD note we make here. If
4440 we discard it in distribute_notes, we will decrement it again. */
4444 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4445 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4446 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4449 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4450 elim_i2
, elim_i1
, elim_i0
);
4453 if (i2dest_in_i2src
)
4455 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4456 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4457 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4458 NULL_RTX
, NULL_RTX
);
4460 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4461 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4464 if (i1dest_in_i1src
)
4466 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4467 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4468 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4469 NULL_RTX
, NULL_RTX
);
4471 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4472 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4475 if (i0dest_in_i0src
)
4477 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4478 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4479 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4480 NULL_RTX
, NULL_RTX
);
4482 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4483 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4486 distribute_links (i3links
);
4487 distribute_links (i2links
);
4488 distribute_links (i1links
);
4489 distribute_links (i0links
);
4493 struct insn_link
*link
;
4494 rtx_insn
*i2_insn
= 0;
4495 rtx i2_val
= 0, set
;
4497 /* The insn that used to set this register doesn't exist, and
4498 this life of the register may not exist either. See if one of
4499 I3's links points to an insn that sets I2DEST. If it does,
4500 that is now the last known value for I2DEST. If we don't update
4501 this and I2 set the register to a value that depended on its old
4502 contents, we will get confused. If this insn is used, thing
4503 will be set correctly in combine_instructions. */
4504 FOR_EACH_LOG_LINK (link
, i3
)
4505 if ((set
= single_set (link
->insn
)) != 0
4506 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4507 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4509 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4511 /* If the reg formerly set in I2 died only once and that was in I3,
4512 zero its use count so it won't make `reload' do any work. */
4514 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4515 && ! i2dest_in_i2src
4516 && REGNO (i2dest
) < reg_n_sets_max
)
4517 INC_REG_N_SETS (REGNO (i2dest
), -1);
4520 if (i1
&& REG_P (i1dest
))
4522 struct insn_link
*link
;
4523 rtx_insn
*i1_insn
= 0;
4524 rtx i1_val
= 0, set
;
4526 FOR_EACH_LOG_LINK (link
, i3
)
4527 if ((set
= single_set (link
->insn
)) != 0
4528 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4529 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4531 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4534 && ! i1dest_in_i1src
4535 && REGNO (i1dest
) < reg_n_sets_max
)
4536 INC_REG_N_SETS (REGNO (i1dest
), -1);
4539 if (i0
&& REG_P (i0dest
))
4541 struct insn_link
*link
;
4542 rtx_insn
*i0_insn
= 0;
4543 rtx i0_val
= 0, set
;
4545 FOR_EACH_LOG_LINK (link
, i3
)
4546 if ((set
= single_set (link
->insn
)) != 0
4547 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4548 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4550 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4553 && ! i0dest_in_i0src
4554 && REGNO (i0dest
) < reg_n_sets_max
)
4555 INC_REG_N_SETS (REGNO (i0dest
), -1);
4558 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4559 been made to this insn. The order is important, because newi2pat
4560 can affect nonzero_bits of newpat. */
4562 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4563 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4566 if (undobuf
.other_insn
!= NULL_RTX
)
4570 fprintf (dump_file
, "modifying other_insn ");
4571 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4573 df_insn_rescan (undobuf
.other_insn
);
4576 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4580 fprintf (dump_file
, "modifying insn i0 ");
4581 dump_insn_slim (dump_file
, i0
);
4583 df_insn_rescan (i0
);
4586 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4590 fprintf (dump_file
, "modifying insn i1 ");
4591 dump_insn_slim (dump_file
, i1
);
4593 df_insn_rescan (i1
);
4596 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4600 fprintf (dump_file
, "modifying insn i2 ");
4601 dump_insn_slim (dump_file
, i2
);
4603 df_insn_rescan (i2
);
4606 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4610 fprintf (dump_file
, "modifying insn i3 ");
4611 dump_insn_slim (dump_file
, i3
);
4613 df_insn_rescan (i3
);
4616 /* Set new_direct_jump_p if a new return or simple jump instruction
4617 has been created. Adjust the CFG accordingly. */
4618 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4620 *new_direct_jump_p
= 1;
4621 mark_jump_label (PATTERN (i3
), i3
, 0);
4622 update_cfg_for_uncondjump (i3
);
4625 if (undobuf
.other_insn
!= NULL_RTX
4626 && (returnjump_p (undobuf
.other_insn
)
4627 || any_uncondjump_p (undobuf
.other_insn
)))
4629 *new_direct_jump_p
= 1;
4630 update_cfg_for_uncondjump (undobuf
.other_insn
);
4633 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4634 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4636 basic_block bb
= BLOCK_FOR_INSN (i3
);
4638 remove_edge (split_block (bb
, i3
));
4639 emit_barrier_after_bb (bb
);
4640 *new_direct_jump_p
= 1;
4643 if (undobuf
.other_insn
4644 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4645 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4647 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4649 remove_edge (split_block (bb
, undobuf
.other_insn
));
4650 emit_barrier_after_bb (bb
);
4651 *new_direct_jump_p
= 1;
4654 /* A noop might also need cleaning up of CFG, if it comes from the
4655 simplification of a jump. */
4657 && GET_CODE (newpat
) == SET
4658 && SET_SRC (newpat
) == pc_rtx
4659 && SET_DEST (newpat
) == pc_rtx
)
4661 *new_direct_jump_p
= 1;
4662 update_cfg_for_uncondjump (i3
);
4665 if (undobuf
.other_insn
!= NULL_RTX
4666 && JUMP_P (undobuf
.other_insn
)
4667 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4668 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4669 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4671 *new_direct_jump_p
= 1;
4672 update_cfg_for_uncondjump (undobuf
.other_insn
);
4675 combine_successes
++;
4678 if (added_links_insn
4679 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4680 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4681 return added_links_insn
;
4683 return newi2pat
? i2
: i3
;
4686 /* Get a marker for undoing to the current state. */
4689 get_undo_marker (void)
4691 return undobuf
.undos
;
4694 /* Undo the modifications up to the marker. */
4697 undo_to_marker (void *marker
)
4699 struct undo
*undo
, *next
;
4701 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4709 *undo
->where
.r
= undo
->old_contents
.r
;
4712 *undo
->where
.i
= undo
->old_contents
.i
;
4715 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4718 *undo
->where
.l
= undo
->old_contents
.l
;
4724 undo
->next
= undobuf
.frees
;
4725 undobuf
.frees
= undo
;
4728 undobuf
.undos
= (struct undo
*) marker
;
4731 /* Undo all the modifications recorded in undobuf. */
4739 /* We've committed to accepting the changes we made. Move all
4740 of the undos to the free list. */
4745 struct undo
*undo
, *next
;
4747 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4750 undo
->next
= undobuf
.frees
;
4751 undobuf
.frees
= undo
;
4756 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4757 where we have an arithmetic expression and return that point. LOC will
4760 try_combine will call this function to see if an insn can be split into
4764 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4767 enum rtx_code code
= GET_CODE (x
);
4769 unsigned HOST_WIDE_INT len
= 0;
4770 HOST_WIDE_INT pos
= 0;
4772 rtx inner
= NULL_RTX
;
4774 /* First special-case some codes. */
4778 #ifdef INSN_SCHEDULING
4779 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4781 if (MEM_P (SUBREG_REG (x
)))
4784 return find_split_point (&SUBREG_REG (x
), insn
, false);
4787 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4788 using LO_SUM and HIGH. */
4789 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4790 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4792 machine_mode address_mode
= get_address_mode (x
);
4795 gen_rtx_LO_SUM (address_mode
,
4796 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4798 return &XEXP (XEXP (x
, 0), 0);
4801 /* If we have a PLUS whose second operand is a constant and the
4802 address is not valid, perhaps will can split it up using
4803 the machine-specific way to split large constants. We use
4804 the first pseudo-reg (one of the virtual regs) as a placeholder;
4805 it will not remain in the result. */
4806 if (GET_CODE (XEXP (x
, 0)) == PLUS
4807 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4808 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4809 MEM_ADDR_SPACE (x
)))
4811 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4812 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4815 /* This should have produced two insns, each of which sets our
4816 placeholder. If the source of the second is a valid address,
4817 we can make put both sources together and make a split point
4821 && NEXT_INSN (seq
) != NULL_RTX
4822 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4823 && NONJUMP_INSN_P (seq
)
4824 && GET_CODE (PATTERN (seq
)) == SET
4825 && SET_DEST (PATTERN (seq
)) == reg
4826 && ! reg_mentioned_p (reg
,
4827 SET_SRC (PATTERN (seq
)))
4828 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4829 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4830 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4831 && memory_address_addr_space_p
4832 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4833 MEM_ADDR_SPACE (x
)))
4835 rtx src1
= SET_SRC (PATTERN (seq
));
4836 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4838 /* Replace the placeholder in SRC2 with SRC1. If we can
4839 find where in SRC2 it was placed, that can become our
4840 split point and we can replace this address with SRC2.
4841 Just try two obvious places. */
4843 src2
= replace_rtx (src2
, reg
, src1
);
4845 if (XEXP (src2
, 0) == src1
)
4846 split
= &XEXP (src2
, 0);
4847 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4848 && XEXP (XEXP (src2
, 0), 0) == src1
)
4849 split
= &XEXP (XEXP (src2
, 0), 0);
4853 SUBST (XEXP (x
, 0), src2
);
4858 /* If that didn't work, perhaps the first operand is complex and
4859 needs to be computed separately, so make a split point there.
4860 This will occur on machines that just support REG + CONST
4861 and have a constant moved through some previous computation. */
4863 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4864 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4865 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4866 return &XEXP (XEXP (x
, 0), 0);
4869 /* If we have a PLUS whose first operand is complex, try computing it
4870 separately by making a split there. */
4871 if (GET_CODE (XEXP (x
, 0)) == PLUS
4872 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4874 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4875 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4876 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4877 return &XEXP (XEXP (x
, 0), 0);
4881 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4882 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4883 we need to put the operand into a register. So split at that
4886 if (SET_DEST (x
) == cc0_rtx
4887 && GET_CODE (SET_SRC (x
)) != COMPARE
4888 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4889 && !OBJECT_P (SET_SRC (x
))
4890 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4891 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4892 return &SET_SRC (x
);
4894 /* See if we can split SET_SRC as it stands. */
4895 split
= find_split_point (&SET_SRC (x
), insn
, true);
4896 if (split
&& split
!= &SET_SRC (x
))
4899 /* See if we can split SET_DEST as it stands. */
4900 split
= find_split_point (&SET_DEST (x
), insn
, false);
4901 if (split
&& split
!= &SET_DEST (x
))
4904 /* See if this is a bitfield assignment with everything constant. If
4905 so, this is an IOR of an AND, so split it into that. */
4906 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4907 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4908 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4909 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4910 && CONST_INT_P (SET_SRC (x
))
4911 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4912 + INTVAL (XEXP (SET_DEST (x
), 2)))
4913 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4914 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4916 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4917 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4918 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4919 rtx dest
= XEXP (SET_DEST (x
), 0);
4920 machine_mode mode
= GET_MODE (dest
);
4921 unsigned HOST_WIDE_INT mask
4922 = (HOST_WIDE_INT_1U
<< len
) - 1;
4925 if (BITS_BIG_ENDIAN
)
4926 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4928 or_mask
= gen_int_mode (src
<< pos
, mode
);
4931 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4934 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4936 simplify_gen_binary (IOR
, mode
,
4937 simplify_gen_binary (AND
, mode
,
4942 SUBST (SET_DEST (x
), dest
);
4944 split
= find_split_point (&SET_SRC (x
), insn
, true);
4945 if (split
&& split
!= &SET_SRC (x
))
4949 /* Otherwise, see if this is an operation that we can split into two.
4950 If so, try to split that. */
4951 code
= GET_CODE (SET_SRC (x
));
4956 /* If we are AND'ing with a large constant that is only a single
4957 bit and the result is only being used in a context where we
4958 need to know if it is zero or nonzero, replace it with a bit
4959 extraction. This will avoid the large constant, which might
4960 have taken more than one insn to make. If the constant were
4961 not a valid argument to the AND but took only one insn to make,
4962 this is no worse, but if it took more than one insn, it will
4965 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4966 && REG_P (XEXP (SET_SRC (x
), 0))
4967 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4968 && REG_P (SET_DEST (x
))
4969 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4970 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4971 && XEXP (*split
, 0) == SET_DEST (x
)
4972 && XEXP (*split
, 1) == const0_rtx
)
4974 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4975 XEXP (SET_SRC (x
), 0),
4976 pos
, NULL_RTX
, 1, 1, 0, 0);
4977 if (extraction
!= 0)
4979 SUBST (SET_SRC (x
), extraction
);
4980 return find_split_point (loc
, insn
, false);
4986 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4987 is known to be on, this can be converted into a NEG of a shift. */
4988 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4989 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4990 && 1 <= (pos
= exact_log2
4991 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4992 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4994 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4998 gen_rtx_LSHIFTRT (mode
,
4999 XEXP (SET_SRC (x
), 0),
5002 split
= find_split_point (&SET_SRC (x
), insn
, true);
5003 if (split
&& split
!= &SET_SRC (x
))
5009 inner
= XEXP (SET_SRC (x
), 0);
5011 /* We can't optimize if either mode is a partial integer
5012 mode as we don't know how many bits are significant
5014 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5015 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5019 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5025 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5026 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5028 inner
= XEXP (SET_SRC (x
), 0);
5029 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5030 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5032 if (BITS_BIG_ENDIAN
)
5033 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5034 unsignedp
= (code
== ZERO_EXTRACT
);
5043 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5045 machine_mode mode
= GET_MODE (SET_SRC (x
));
5047 /* For unsigned, we have a choice of a shift followed by an
5048 AND or two shifts. Use two shifts for field sizes where the
5049 constant might be too large. We assume here that we can
5050 always at least get 8-bit constants in an AND insn, which is
5051 true for every current RISC. */
5053 if (unsignedp
&& len
<= 8)
5055 unsigned HOST_WIDE_INT mask
5056 = (HOST_WIDE_INT_1U
<< len
) - 1;
5060 (mode
, gen_lowpart (mode
, inner
),
5062 gen_int_mode (mask
, mode
)));
5064 split
= find_split_point (&SET_SRC (x
), insn
, true);
5065 if (split
&& split
!= &SET_SRC (x
))
5072 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5073 gen_rtx_ASHIFT (mode
,
5074 gen_lowpart (mode
, inner
),
5075 GEN_INT (GET_MODE_PRECISION (mode
)
5077 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5079 split
= find_split_point (&SET_SRC (x
), insn
, true);
5080 if (split
&& split
!= &SET_SRC (x
))
5085 /* See if this is a simple operation with a constant as the second
5086 operand. It might be that this constant is out of range and hence
5087 could be used as a split point. */
5088 if (BINARY_P (SET_SRC (x
))
5089 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5090 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5091 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5092 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5093 return &XEXP (SET_SRC (x
), 1);
5095 /* Finally, see if this is a simple operation with its first operand
5096 not in a register. The operation might require this operand in a
5097 register, so return it as a split point. We can always do this
5098 because if the first operand were another operation, we would have
5099 already found it as a split point. */
5100 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5101 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5102 return &XEXP (SET_SRC (x
), 0);
5108 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5109 it is better to write this as (not (ior A B)) so we can split it.
5110 Similarly for IOR. */
5111 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5114 gen_rtx_NOT (GET_MODE (x
),
5115 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5117 XEXP (XEXP (x
, 0), 0),
5118 XEXP (XEXP (x
, 1), 0))));
5119 return find_split_point (loc
, insn
, set_src
);
5122 /* Many RISC machines have a large set of logical insns. If the
5123 second operand is a NOT, put it first so we will try to split the
5124 other operand first. */
5125 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5127 rtx tem
= XEXP (x
, 0);
5128 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5129 SUBST (XEXP (x
, 1), tem
);
5135 /* Canonicalization can produce (minus A (mult B C)), where C is a
5136 constant. It may be better to try splitting (plus (mult B -C) A)
5137 instead if this isn't a multiply by a power of two. */
5138 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5139 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5140 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5142 machine_mode mode
= GET_MODE (x
);
5143 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5144 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5145 SUBST (*loc
, gen_rtx_PLUS (mode
,
5147 XEXP (XEXP (x
, 1), 0),
5148 gen_int_mode (other_int
,
5151 return find_split_point (loc
, insn
, set_src
);
5154 /* Split at a multiply-accumulate instruction. However if this is
5155 the SET_SRC, we likely do not have such an instruction and it's
5156 worthless to try this split. */
5158 && (GET_CODE (XEXP (x
, 0)) == MULT
5159 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5160 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5167 /* Otherwise, select our actions depending on our rtx class. */
5168 switch (GET_RTX_CLASS (code
))
5170 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5172 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5177 case RTX_COMM_ARITH
:
5179 case RTX_COMM_COMPARE
:
5180 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5185 /* Some machines have (and (shift ...) ...) insns. If X is not
5186 an AND, but XEXP (X, 0) is, use it as our split point. */
5187 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5188 return &XEXP (x
, 0);
5190 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5196 /* Otherwise, we don't have a split point. */
5201 /* Throughout X, replace FROM with TO, and return the result.
5202 The result is TO if X is FROM;
5203 otherwise the result is X, but its contents may have been modified.
5204 If they were modified, a record was made in undobuf so that
5205 undo_all will (among other things) return X to its original state.
5207 If the number of changes necessary is too much to record to undo,
5208 the excess changes are not made, so the result is invalid.
5209 The changes already made can still be undone.
5210 undobuf.num_undo is incremented for such changes, so by testing that
5211 the caller can tell whether the result is valid.
5213 `n_occurrences' is incremented each time FROM is replaced.
5215 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5217 IN_COND is nonzero if we are at the top level of a condition.
5219 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5220 by copying if `n_occurrences' is nonzero. */
5223 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5225 enum rtx_code code
= GET_CODE (x
);
5226 machine_mode op0_mode
= VOIDmode
;
5231 /* Two expressions are equal if they are identical copies of a shared
5232 RTX or if they are both registers with the same register number
5235 #define COMBINE_RTX_EQUAL_P(X,Y) \
5237 || (REG_P (X) && REG_P (Y) \
5238 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5240 /* Do not substitute into clobbers of regs -- this will never result in
5242 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5245 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5248 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5251 /* If X and FROM are the same register but different modes, they
5252 will not have been seen as equal above. However, the log links code
5253 will make a LOG_LINKS entry for that case. If we do nothing, we
5254 will try to rerecognize our original insn and, when it succeeds,
5255 we will delete the feeding insn, which is incorrect.
5257 So force this insn not to match in this (rare) case. */
5258 if (! in_dest
&& code
== REG
&& REG_P (from
)
5259 && reg_overlap_mentioned_p (x
, from
))
5260 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5262 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5263 of which may contain things that can be combined. */
5264 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5267 /* It is possible to have a subexpression appear twice in the insn.
5268 Suppose that FROM is a register that appears within TO.
5269 Then, after that subexpression has been scanned once by `subst',
5270 the second time it is scanned, TO may be found. If we were
5271 to scan TO here, we would find FROM within it and create a
5272 self-referent rtl structure which is completely wrong. */
5273 if (COMBINE_RTX_EQUAL_P (x
, to
))
5276 /* Parallel asm_operands need special attention because all of the
5277 inputs are shared across the arms. Furthermore, unsharing the
5278 rtl results in recognition failures. Failure to handle this case
5279 specially can result in circular rtl.
5281 Solve this by doing a normal pass across the first entry of the
5282 parallel, and only processing the SET_DESTs of the subsequent
5285 if (code
== PARALLEL
5286 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5287 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5289 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5291 /* If this substitution failed, this whole thing fails. */
5292 if (GET_CODE (new_rtx
) == CLOBBER
5293 && XEXP (new_rtx
, 0) == const0_rtx
)
5296 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5298 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5300 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5303 && GET_CODE (dest
) != CC0
5304 && GET_CODE (dest
) != PC
)
5306 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5308 /* If this substitution failed, this whole thing fails. */
5309 if (GET_CODE (new_rtx
) == CLOBBER
5310 && XEXP (new_rtx
, 0) == const0_rtx
)
5313 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5319 len
= GET_RTX_LENGTH (code
);
5320 fmt
= GET_RTX_FORMAT (code
);
5322 /* We don't need to process a SET_DEST that is a register, CC0,
5323 or PC, so set up to skip this common case. All other cases
5324 where we want to suppress replacing something inside a
5325 SET_SRC are handled via the IN_DEST operand. */
5327 && (REG_P (SET_DEST (x
))
5328 || GET_CODE (SET_DEST (x
)) == CC0
5329 || GET_CODE (SET_DEST (x
)) == PC
))
5332 /* Trying to simplify the operands of a widening MULT is not likely
5333 to create RTL matching a machine insn. */
5335 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5336 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5337 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5338 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5339 && REG_P (XEXP (XEXP (x
, 0), 0))
5340 && REG_P (XEXP (XEXP (x
, 1), 0))
5345 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5348 op0_mode
= GET_MODE (XEXP (x
, 0));
5350 for (i
= 0; i
< len
; i
++)
5355 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5357 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5359 new_rtx
= (unique_copy
&& n_occurrences
5360 ? copy_rtx (to
) : to
);
5365 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5368 /* If this substitution failed, this whole thing
5370 if (GET_CODE (new_rtx
) == CLOBBER
5371 && XEXP (new_rtx
, 0) == const0_rtx
)
5375 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5378 else if (fmt
[i
] == 'e')
5380 /* If this is a register being set, ignore it. */
5381 new_rtx
= XEXP (x
, i
);
5384 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5386 || code
== STRICT_LOW_PART
))
5389 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5391 /* In general, don't install a subreg involving two
5392 modes not tieable. It can worsen register
5393 allocation, and can even make invalid reload
5394 insns, since the reg inside may need to be copied
5395 from in the outside mode, and that may be invalid
5396 if it is an fp reg copied in integer mode.
5398 We allow two exceptions to this: It is valid if
5399 it is inside another SUBREG and the mode of that
5400 SUBREG and the mode of the inside of TO is
5401 tieable and it is valid if X is a SET that copies
5404 if (GET_CODE (to
) == SUBREG
5405 && ! MODES_TIEABLE_P (GET_MODE (to
),
5406 GET_MODE (SUBREG_REG (to
)))
5407 && ! (code
== SUBREG
5408 && MODES_TIEABLE_P (GET_MODE (x
),
5409 GET_MODE (SUBREG_REG (to
))))
5413 && XEXP (x
, 0) == cc0_rtx
))))
5414 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5418 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5419 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5422 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5424 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5428 /* If we are in a SET_DEST, suppress most cases unless we
5429 have gone inside a MEM, in which case we want to
5430 simplify the address. We assume here that things that
5431 are actually part of the destination have their inner
5432 parts in the first expression. This is true for SUBREG,
5433 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5434 things aside from REG and MEM that should appear in a
5436 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5438 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5439 || code
== ZERO_EXTRACT
))
5442 code
== IF_THEN_ELSE
&& i
== 0,
5445 /* If we found that we will have to reject this combination,
5446 indicate that by returning the CLOBBER ourselves, rather than
5447 an expression containing it. This will speed things up as
5448 well as prevent accidents where two CLOBBERs are considered
5449 to be equal, thus producing an incorrect simplification. */
5451 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5454 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5456 machine_mode mode
= GET_MODE (x
);
5458 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5459 GET_MODE (SUBREG_REG (x
)),
5462 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5464 else if (CONST_SCALAR_INT_P (new_rtx
)
5465 && GET_CODE (x
) == ZERO_EXTEND
)
5467 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5468 new_rtx
, GET_MODE (XEXP (x
, 0)));
5472 SUBST (XEXP (x
, i
), new_rtx
);
5477 /* Check if we are loading something from the constant pool via float
5478 extension; in this case we would undo compress_float_constant
5479 optimization and degenerate constant load to an immediate value. */
5480 if (GET_CODE (x
) == FLOAT_EXTEND
5481 && MEM_P (XEXP (x
, 0))
5482 && MEM_READONLY_P (XEXP (x
, 0)))
5484 rtx tmp
= avoid_constant_pool_reference (x
);
5489 /* Try to simplify X. If the simplification changed the code, it is likely
5490 that further simplification will help, so loop, but limit the number
5491 of repetitions that will be performed. */
5493 for (i
= 0; i
< 4; i
++)
5495 /* If X is sufficiently simple, don't bother trying to do anything
5497 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5498 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5500 if (GET_CODE (x
) == code
)
5503 code
= GET_CODE (x
);
5505 /* We no longer know the original mode of operand 0 since we
5506 have changed the form of X) */
5507 op0_mode
= VOIDmode
;
5513 /* If X is a commutative operation whose operands are not in the canonical
5514 order, use substitutions to swap them. */
5517 maybe_swap_commutative_operands (rtx x
)
5519 if (COMMUTATIVE_ARITH_P (x
)
5520 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5522 rtx temp
= XEXP (x
, 0);
5523 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5524 SUBST (XEXP (x
, 1), temp
);
5528 /* Simplify X, a piece of RTL. We just operate on the expression at the
5529 outer level; call `subst' to simplify recursively. Return the new
5532 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5533 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5537 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5540 enum rtx_code code
= GET_CODE (x
);
5541 machine_mode mode
= GET_MODE (x
);
5545 /* If this is a commutative operation, put a constant last and a complex
5546 expression first. We don't need to do this for comparisons here. */
5547 maybe_swap_commutative_operands (x
);
5549 /* Try to fold this expression in case we have constants that weren't
5552 switch (GET_RTX_CLASS (code
))
5555 if (op0_mode
== VOIDmode
)
5556 op0_mode
= GET_MODE (XEXP (x
, 0));
5557 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5560 case RTX_COMM_COMPARE
:
5562 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5563 if (cmp_mode
== VOIDmode
)
5565 cmp_mode
= GET_MODE (XEXP (x
, 1));
5566 if (cmp_mode
== VOIDmode
)
5567 cmp_mode
= op0_mode
;
5569 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5570 XEXP (x
, 0), XEXP (x
, 1));
5573 case RTX_COMM_ARITH
:
5575 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5577 case RTX_BITFIELD_OPS
:
5579 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5580 XEXP (x
, 1), XEXP (x
, 2));
5589 code
= GET_CODE (temp
);
5590 op0_mode
= VOIDmode
;
5591 mode
= GET_MODE (temp
);
5594 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5595 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5596 things. Check for cases where both arms are testing the same
5599 Don't do anything if all operands are very simple. */
5602 && ((!OBJECT_P (XEXP (x
, 0))
5603 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5604 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5605 || (!OBJECT_P (XEXP (x
, 1))
5606 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5607 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5609 && (!OBJECT_P (XEXP (x
, 0))
5610 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5611 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5613 rtx cond
, true_rtx
, false_rtx
;
5615 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5617 /* If everything is a comparison, what we have is highly unlikely
5618 to be simpler, so don't use it. */
5619 && ! (COMPARISON_P (x
)
5620 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5622 rtx cop1
= const0_rtx
;
5623 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5625 if (cond_code
== NE
&& COMPARISON_P (cond
))
5628 /* Simplify the alternative arms; this may collapse the true and
5629 false arms to store-flag values. Be careful to use copy_rtx
5630 here since true_rtx or false_rtx might share RTL with x as a
5631 result of the if_then_else_cond call above. */
5632 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5633 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5635 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5636 is unlikely to be simpler. */
5637 if (general_operand (true_rtx
, VOIDmode
)
5638 && general_operand (false_rtx
, VOIDmode
))
5640 enum rtx_code reversed
;
5642 /* Restarting if we generate a store-flag expression will cause
5643 us to loop. Just drop through in this case. */
5645 /* If the result values are STORE_FLAG_VALUE and zero, we can
5646 just make the comparison operation. */
5647 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5648 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5650 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5651 && ((reversed
= reversed_comparison_code_parts
5652 (cond_code
, cond
, cop1
, NULL
))
5654 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5657 /* Likewise, we can make the negate of a comparison operation
5658 if the result values are - STORE_FLAG_VALUE and zero. */
5659 else if (CONST_INT_P (true_rtx
)
5660 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5661 && false_rtx
== const0_rtx
)
5662 x
= simplify_gen_unary (NEG
, mode
,
5663 simplify_gen_relational (cond_code
,
5667 else if (CONST_INT_P (false_rtx
)
5668 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5669 && true_rtx
== const0_rtx
5670 && ((reversed
= reversed_comparison_code_parts
5671 (cond_code
, cond
, cop1
, NULL
))
5673 x
= simplify_gen_unary (NEG
, mode
,
5674 simplify_gen_relational (reversed
,
5679 return gen_rtx_IF_THEN_ELSE (mode
,
5680 simplify_gen_relational (cond_code
,
5685 true_rtx
, false_rtx
);
5687 code
= GET_CODE (x
);
5688 op0_mode
= VOIDmode
;
5693 /* First see if we can apply the inverse distributive law. */
5694 if (code
== PLUS
|| code
== MINUS
5695 || code
== AND
|| code
== IOR
|| code
== XOR
)
5697 x
= apply_distributive_law (x
);
5698 code
= GET_CODE (x
);
5699 op0_mode
= VOIDmode
;
5702 /* If CODE is an associative operation not otherwise handled, see if we
5703 can associate some operands. This can win if they are constants or
5704 if they are logically related (i.e. (a & b) & a). */
5705 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5706 || code
== AND
|| code
== IOR
|| code
== XOR
5707 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5708 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5709 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5711 if (GET_CODE (XEXP (x
, 0)) == code
)
5713 rtx other
= XEXP (XEXP (x
, 0), 0);
5714 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5715 rtx inner_op1
= XEXP (x
, 1);
5718 /* Make sure we pass the constant operand if any as the second
5719 one if this is a commutative operation. */
5720 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5721 std::swap (inner_op0
, inner_op1
);
5722 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5723 : code
== DIV
? MULT
5725 mode
, inner_op0
, inner_op1
);
5727 /* For commutative operations, try the other pair if that one
5729 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5731 other
= XEXP (XEXP (x
, 0), 1);
5732 inner
= simplify_binary_operation (code
, mode
,
5733 XEXP (XEXP (x
, 0), 0),
5738 return simplify_gen_binary (code
, mode
, other
, inner
);
5742 /* A little bit of algebraic simplification here. */
5746 /* Ensure that our address has any ASHIFTs converted to MULT in case
5747 address-recognizing predicates are called later. */
5748 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5749 SUBST (XEXP (x
, 0), temp
);
5753 if (op0_mode
== VOIDmode
)
5754 op0_mode
= GET_MODE (SUBREG_REG (x
));
5756 /* See if this can be moved to simplify_subreg. */
5757 if (CONSTANT_P (SUBREG_REG (x
))
5758 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5759 /* Don't call gen_lowpart if the inner mode
5760 is VOIDmode and we cannot simplify it, as SUBREG without
5761 inner mode is invalid. */
5762 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5763 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5764 return gen_lowpart (mode
, SUBREG_REG (x
));
5766 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5770 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5775 /* If op is known to have all lower bits zero, the result is zero. */
5777 && SCALAR_INT_MODE_P (mode
)
5778 && SCALAR_INT_MODE_P (op0_mode
)
5779 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5780 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5781 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5782 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5783 & GET_MODE_MASK (mode
)) == 0)
5784 return CONST0_RTX (mode
);
5787 /* Don't change the mode of the MEM if that would change the meaning
5789 if (MEM_P (SUBREG_REG (x
))
5790 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5791 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5792 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5793 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5795 /* Note that we cannot do any narrowing for non-constants since
5796 we might have been counting on using the fact that some bits were
5797 zero. We now do this in the SET. */
5802 temp
= expand_compound_operation (XEXP (x
, 0));
5804 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5805 replaced by (lshiftrt X C). This will convert
5806 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5808 if (GET_CODE (temp
) == ASHIFTRT
5809 && CONST_INT_P (XEXP (temp
, 1))
5810 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5811 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5812 INTVAL (XEXP (temp
, 1)));
5814 /* If X has only a single bit that might be nonzero, say, bit I, convert
5815 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5816 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5817 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5818 or a SUBREG of one since we'd be making the expression more
5819 complex if it was just a register. */
5822 && ! (GET_CODE (temp
) == SUBREG
5823 && REG_P (SUBREG_REG (temp
)))
5824 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5826 rtx temp1
= simplify_shift_const
5827 (NULL_RTX
, ASHIFTRT
, mode
,
5828 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5829 GET_MODE_PRECISION (mode
) - 1 - i
),
5830 GET_MODE_PRECISION (mode
) - 1 - i
);
5832 /* If all we did was surround TEMP with the two shifts, we
5833 haven't improved anything, so don't use it. Otherwise,
5834 we are better off with TEMP1. */
5835 if (GET_CODE (temp1
) != ASHIFTRT
5836 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5837 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5843 /* We can't handle truncation to a partial integer mode here
5844 because we don't know the real bitsize of the partial
5846 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5849 if (HWI_COMPUTABLE_MODE_P (mode
))
5851 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5852 GET_MODE_MASK (mode
), 0));
5854 /* We can truncate a constant value and return it. */
5855 if (CONST_INT_P (XEXP (x
, 0)))
5856 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5858 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5859 whose value is a comparison can be replaced with a subreg if
5860 STORE_FLAG_VALUE permits. */
5861 if (HWI_COMPUTABLE_MODE_P (mode
)
5862 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5863 && (temp
= get_last_value (XEXP (x
, 0)))
5864 && COMPARISON_P (temp
))
5865 return gen_lowpart (mode
, XEXP (x
, 0));
5869 /* (const (const X)) can become (const X). Do it this way rather than
5870 returning the inner CONST since CONST can be shared with a
5872 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5873 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5877 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5878 can add in an offset. find_split_point will split this address up
5879 again if it doesn't match. */
5880 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5881 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5886 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5887 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5888 bit-field and can be replaced by either a sign_extend or a
5889 sign_extract. The `and' may be a zero_extend and the two
5890 <c>, -<c> constants may be reversed. */
5891 if (GET_CODE (XEXP (x
, 0)) == XOR
5892 && CONST_INT_P (XEXP (x
, 1))
5893 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5894 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5895 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5896 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5897 && HWI_COMPUTABLE_MODE_P (mode
)
5898 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5899 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5900 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5901 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
5902 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5903 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5904 == (unsigned int) i
+ 1))))
5905 return simplify_shift_const
5906 (NULL_RTX
, ASHIFTRT
, mode
,
5907 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5908 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5909 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5910 GET_MODE_PRECISION (mode
) - (i
+ 1));
5912 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5913 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5914 the bitsize of the mode - 1. This allows simplification of
5915 "a = (b & 8) == 0;" */
5916 if (XEXP (x
, 1) == constm1_rtx
5917 && !REG_P (XEXP (x
, 0))
5918 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5919 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5920 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5921 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5922 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5923 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5924 GET_MODE_PRECISION (mode
) - 1),
5925 GET_MODE_PRECISION (mode
) - 1);
5927 /* If we are adding two things that have no bits in common, convert
5928 the addition into an IOR. This will often be further simplified,
5929 for example in cases like ((a & 1) + (a & 2)), which can
5932 if (HWI_COMPUTABLE_MODE_P (mode
)
5933 && (nonzero_bits (XEXP (x
, 0), mode
)
5934 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5936 /* Try to simplify the expression further. */
5937 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5938 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5940 /* If we could, great. If not, do not go ahead with the IOR
5941 replacement, since PLUS appears in many special purpose
5942 address arithmetic instructions. */
5943 if (GET_CODE (temp
) != CLOBBER
5944 && (GET_CODE (temp
) != IOR
5945 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5946 || XEXP (temp
, 1) != XEXP (x
, 1))
5947 && (XEXP (temp
, 0) != XEXP (x
, 1)
5948 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5952 /* Canonicalize x + x into x << 1. */
5953 if (GET_MODE_CLASS (mode
) == MODE_INT
5954 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
5955 && !side_effects_p (XEXP (x
, 0)))
5956 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
5961 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5962 (and <foo> (const_int pow2-1)) */
5963 if (GET_CODE (XEXP (x
, 1)) == AND
5964 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5965 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
5966 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5967 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5968 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5972 /* If we have (mult (plus A B) C), apply the distributive law and then
5973 the inverse distributive law to see if things simplify. This
5974 occurs mostly in addresses, often when unrolling loops. */
5976 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5978 rtx result
= distribute_and_simplify_rtx (x
, 0);
5983 /* Try simplify a*(b/c) as (a*b)/c. */
5984 if (FLOAT_MODE_P (mode
) && flag_associative_math
5985 && GET_CODE (XEXP (x
, 0)) == DIV
)
5987 rtx tem
= simplify_binary_operation (MULT
, mode
,
5988 XEXP (XEXP (x
, 0), 0),
5991 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5996 /* If this is a divide by a power of two, treat it as a shift if
5997 its first operand is a shift. */
5998 if (CONST_INT_P (XEXP (x
, 1))
5999 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6000 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6001 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6002 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6003 || GET_CODE (XEXP (x
, 0)) == ROTATE
6004 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6005 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
6009 case GT
: case GTU
: case GE
: case GEU
:
6010 case LT
: case LTU
: case LE
: case LEU
:
6011 case UNEQ
: case LTGT
:
6012 case UNGT
: case UNGE
:
6013 case UNLT
: case UNLE
:
6014 case UNORDERED
: case ORDERED
:
6015 /* If the first operand is a condition code, we can't do anything
6017 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6018 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6019 && ! CC0_P (XEXP (x
, 0))))
6021 rtx op0
= XEXP (x
, 0);
6022 rtx op1
= XEXP (x
, 1);
6023 enum rtx_code new_code
;
6025 if (GET_CODE (op0
) == COMPARE
)
6026 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6028 /* Simplify our comparison, if possible. */
6029 new_code
= simplify_comparison (code
, &op0
, &op1
);
6031 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6032 if only the low-order bit is possibly nonzero in X (such as when
6033 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6034 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6035 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6038 Remove any ZERO_EXTRACT we made when thinking this was a
6039 comparison. It may now be simpler to use, e.g., an AND. If a
6040 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6041 the call to make_compound_operation in the SET case.
6043 Don't apply these optimizations if the caller would
6044 prefer a comparison rather than a value.
6045 E.g., for the condition in an IF_THEN_ELSE most targets need
6046 an explicit comparison. */
6051 else if (STORE_FLAG_VALUE
== 1
6052 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6053 && op1
== const0_rtx
6054 && mode
== GET_MODE (op0
)
6055 && nonzero_bits (op0
, mode
) == 1)
6056 return gen_lowpart (mode
,
6057 expand_compound_operation (op0
));
6059 else if (STORE_FLAG_VALUE
== 1
6060 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6061 && op1
== const0_rtx
6062 && mode
== GET_MODE (op0
)
6063 && (num_sign_bit_copies (op0
, mode
)
6064 == GET_MODE_PRECISION (mode
)))
6066 op0
= expand_compound_operation (op0
);
6067 return simplify_gen_unary (NEG
, mode
,
6068 gen_lowpart (mode
, op0
),
6072 else if (STORE_FLAG_VALUE
== 1
6073 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6074 && op1
== const0_rtx
6075 && mode
== GET_MODE (op0
)
6076 && nonzero_bits (op0
, mode
) == 1)
6078 op0
= expand_compound_operation (op0
);
6079 return simplify_gen_binary (XOR
, mode
,
6080 gen_lowpart (mode
, op0
),
6084 else if (STORE_FLAG_VALUE
== 1
6085 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6086 && op1
== const0_rtx
6087 && mode
== GET_MODE (op0
)
6088 && (num_sign_bit_copies (op0
, mode
)
6089 == GET_MODE_PRECISION (mode
)))
6091 op0
= expand_compound_operation (op0
);
6092 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6095 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6100 else if (STORE_FLAG_VALUE
== -1
6101 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6102 && op1
== const0_rtx
6103 && mode
== GET_MODE (op0
)
6104 && (num_sign_bit_copies (op0
, mode
)
6105 == GET_MODE_PRECISION (mode
)))
6106 return gen_lowpart (mode
,
6107 expand_compound_operation (op0
));
6109 else if (STORE_FLAG_VALUE
== -1
6110 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6111 && op1
== const0_rtx
6112 && mode
== GET_MODE (op0
)
6113 && nonzero_bits (op0
, mode
) == 1)
6115 op0
= expand_compound_operation (op0
);
6116 return simplify_gen_unary (NEG
, mode
,
6117 gen_lowpart (mode
, op0
),
6121 else if (STORE_FLAG_VALUE
== -1
6122 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6123 && op1
== const0_rtx
6124 && mode
== GET_MODE (op0
)
6125 && (num_sign_bit_copies (op0
, mode
)
6126 == GET_MODE_PRECISION (mode
)))
6128 op0
= expand_compound_operation (op0
);
6129 return simplify_gen_unary (NOT
, mode
,
6130 gen_lowpart (mode
, op0
),
6134 /* If X is 0/1, (eq X 0) is X-1. */
6135 else if (STORE_FLAG_VALUE
== -1
6136 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6137 && op1
== const0_rtx
6138 && mode
== GET_MODE (op0
)
6139 && nonzero_bits (op0
, mode
) == 1)
6141 op0
= expand_compound_operation (op0
);
6142 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6145 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6146 one bit that might be nonzero, we can convert (ne x 0) to
6147 (ashift x c) where C puts the bit in the sign bit. Remove any
6148 AND with STORE_FLAG_VALUE when we are done, since we are only
6149 going to test the sign bit. */
6150 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6151 && HWI_COMPUTABLE_MODE_P (mode
)
6152 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6153 && op1
== const0_rtx
6154 && mode
== GET_MODE (op0
)
6155 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6157 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6158 expand_compound_operation (op0
),
6159 GET_MODE_PRECISION (mode
) - 1 - i
);
6160 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6166 /* If the code changed, return a whole new comparison.
6167 We also need to avoid using SUBST in cases where
6168 simplify_comparison has widened a comparison with a CONST_INT,
6169 since in that case the wider CONST_INT may fail the sanity
6170 checks in do_SUBST. */
6171 if (new_code
!= code
6172 || (CONST_INT_P (op1
)
6173 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6174 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6175 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6177 /* Otherwise, keep this operation, but maybe change its operands.
6178 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6179 SUBST (XEXP (x
, 0), op0
);
6180 SUBST (XEXP (x
, 1), op1
);
6185 return simplify_if_then_else (x
);
6191 /* If we are processing SET_DEST, we are done. */
6195 return expand_compound_operation (x
);
6198 return simplify_set (x
);
6202 return simplify_logical (x
);
6209 /* If this is a shift by a constant amount, simplify it. */
6210 if (CONST_INT_P (XEXP (x
, 1)))
6211 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6212 INTVAL (XEXP (x
, 1)));
6214 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6216 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6218 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6230 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6233 simplify_if_then_else (rtx x
)
6235 machine_mode mode
= GET_MODE (x
);
6236 rtx cond
= XEXP (x
, 0);
6237 rtx true_rtx
= XEXP (x
, 1);
6238 rtx false_rtx
= XEXP (x
, 2);
6239 enum rtx_code true_code
= GET_CODE (cond
);
6240 int comparison_p
= COMPARISON_P (cond
);
6243 enum rtx_code false_code
;
6246 /* Simplify storing of the truth value. */
6247 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6248 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6249 XEXP (cond
, 0), XEXP (cond
, 1));
6251 /* Also when the truth value has to be reversed. */
6253 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6254 && (reversed
= reversed_comparison (cond
, mode
)))
6257 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6258 in it is being compared against certain values. Get the true and false
6259 comparisons and see if that says anything about the value of each arm. */
6262 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6264 && REG_P (XEXP (cond
, 0)))
6267 rtx from
= XEXP (cond
, 0);
6268 rtx true_val
= XEXP (cond
, 1);
6269 rtx false_val
= true_val
;
6272 /* If FALSE_CODE is EQ, swap the codes and arms. */
6274 if (false_code
== EQ
)
6276 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6277 std::swap (true_rtx
, false_rtx
);
6280 /* If we are comparing against zero and the expression being tested has
6281 only a single bit that might be nonzero, that is its value when it is
6282 not equal to zero. Similarly if it is known to be -1 or 0. */
6284 if (true_code
== EQ
&& true_val
== const0_rtx
6285 && pow2p_hwi (nzb
= nonzero_bits (from
, GET_MODE (from
))))
6288 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6290 else if (true_code
== EQ
&& true_val
== const0_rtx
6291 && (num_sign_bit_copies (from
, GET_MODE (from
))
6292 == GET_MODE_PRECISION (GET_MODE (from
))))
6295 false_val
= constm1_rtx
;
6298 /* Now simplify an arm if we know the value of the register in the
6299 branch and it is used in the arm. Be careful due to the potential
6300 of locally-shared RTL. */
6302 if (reg_mentioned_p (from
, true_rtx
))
6303 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6305 pc_rtx
, pc_rtx
, 0, 0, 0);
6306 if (reg_mentioned_p (from
, false_rtx
))
6307 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6309 pc_rtx
, pc_rtx
, 0, 0, 0);
6311 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6312 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6314 true_rtx
= XEXP (x
, 1);
6315 false_rtx
= XEXP (x
, 2);
6316 true_code
= GET_CODE (cond
);
6319 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6320 reversed, do so to avoid needing two sets of patterns for
6321 subtract-and-branch insns. Similarly if we have a constant in the true
6322 arm, the false arm is the same as the first operand of the comparison, or
6323 the false arm is more complicated than the true arm. */
6326 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6327 && (true_rtx
== pc_rtx
6328 || (CONSTANT_P (true_rtx
)
6329 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6330 || true_rtx
== const0_rtx
6331 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6332 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6333 && !OBJECT_P (false_rtx
))
6334 || reg_mentioned_p (true_rtx
, false_rtx
)
6335 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6337 true_code
= reversed_comparison_code (cond
, NULL
);
6338 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6339 SUBST (XEXP (x
, 1), false_rtx
);
6340 SUBST (XEXP (x
, 2), true_rtx
);
6342 std::swap (true_rtx
, false_rtx
);
6345 /* It is possible that the conditional has been simplified out. */
6346 true_code
= GET_CODE (cond
);
6347 comparison_p
= COMPARISON_P (cond
);
6350 /* If the two arms are identical, we don't need the comparison. */
6352 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6355 /* Convert a == b ? b : a to "a". */
6356 if (true_code
== EQ
&& ! side_effects_p (cond
)
6357 && !HONOR_NANS (mode
)
6358 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6359 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6361 else if (true_code
== NE
&& ! side_effects_p (cond
)
6362 && !HONOR_NANS (mode
)
6363 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6364 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6367 /* Look for cases where we have (abs x) or (neg (abs X)). */
6369 if (GET_MODE_CLASS (mode
) == MODE_INT
6371 && XEXP (cond
, 1) == const0_rtx
6372 && GET_CODE (false_rtx
) == NEG
6373 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6374 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6375 && ! side_effects_p (true_rtx
))
6380 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6384 simplify_gen_unary (NEG
, mode
,
6385 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6391 /* Look for MIN or MAX. */
6393 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6395 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6396 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6397 && ! side_effects_p (cond
))
6402 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6405 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6408 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6411 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6416 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6417 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6418 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6419 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6420 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6421 neither 1 or -1, but it isn't worth checking for. */
6423 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6425 && GET_MODE_CLASS (mode
) == MODE_INT
6426 && ! side_effects_p (x
))
6428 rtx t
= make_compound_operation (true_rtx
, SET
);
6429 rtx f
= make_compound_operation (false_rtx
, SET
);
6430 rtx cond_op0
= XEXP (cond
, 0);
6431 rtx cond_op1
= XEXP (cond
, 1);
6432 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6433 machine_mode m
= mode
;
6434 rtx z
= 0, c1
= NULL_RTX
;
6436 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6437 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6438 || GET_CODE (t
) == ASHIFT
6439 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6440 && rtx_equal_p (XEXP (t
, 0), f
))
6441 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6443 /* If an identity-zero op is commutative, check whether there
6444 would be a match if we swapped the operands. */
6445 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6446 || GET_CODE (t
) == XOR
)
6447 && rtx_equal_p (XEXP (t
, 1), f
))
6448 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6449 else if (GET_CODE (t
) == SIGN_EXTEND
6450 && (GET_CODE (XEXP (t
, 0)) == PLUS
6451 || GET_CODE (XEXP (t
, 0)) == MINUS
6452 || GET_CODE (XEXP (t
, 0)) == IOR
6453 || GET_CODE (XEXP (t
, 0)) == XOR
6454 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6455 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6456 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6457 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6458 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6459 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6460 && (num_sign_bit_copies (f
, GET_MODE (f
))
6462 (GET_MODE_PRECISION (mode
)
6463 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6465 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6466 extend_op
= SIGN_EXTEND
;
6467 m
= GET_MODE (XEXP (t
, 0));
6469 else if (GET_CODE (t
) == SIGN_EXTEND
6470 && (GET_CODE (XEXP (t
, 0)) == PLUS
6471 || GET_CODE (XEXP (t
, 0)) == IOR
6472 || GET_CODE (XEXP (t
, 0)) == XOR
)
6473 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6474 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6475 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6476 && (num_sign_bit_copies (f
, GET_MODE (f
))
6478 (GET_MODE_PRECISION (mode
)
6479 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6481 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6482 extend_op
= SIGN_EXTEND
;
6483 m
= GET_MODE (XEXP (t
, 0));
6485 else if (GET_CODE (t
) == ZERO_EXTEND
6486 && (GET_CODE (XEXP (t
, 0)) == PLUS
6487 || GET_CODE (XEXP (t
, 0)) == MINUS
6488 || GET_CODE (XEXP (t
, 0)) == IOR
6489 || GET_CODE (XEXP (t
, 0)) == XOR
6490 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6491 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6492 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6493 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6494 && HWI_COMPUTABLE_MODE_P (mode
)
6495 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6496 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6497 && ((nonzero_bits (f
, GET_MODE (f
))
6498 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6501 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6502 extend_op
= ZERO_EXTEND
;
6503 m
= GET_MODE (XEXP (t
, 0));
6505 else if (GET_CODE (t
) == ZERO_EXTEND
6506 && (GET_CODE (XEXP (t
, 0)) == PLUS
6507 || GET_CODE (XEXP (t
, 0)) == IOR
6508 || GET_CODE (XEXP (t
, 0)) == XOR
)
6509 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6510 && HWI_COMPUTABLE_MODE_P (mode
)
6511 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6512 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6513 && ((nonzero_bits (f
, GET_MODE (f
))
6514 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6517 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6518 extend_op
= ZERO_EXTEND
;
6519 m
= GET_MODE (XEXP (t
, 0));
6524 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6525 cond_op0
, cond_op1
),
6526 pc_rtx
, pc_rtx
, 0, 0, 0);
6527 temp
= simplify_gen_binary (MULT
, m
, temp
,
6528 simplify_gen_binary (MULT
, m
, c1
,
6530 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6531 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6533 if (extend_op
!= UNKNOWN
)
6534 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6540 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6541 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6542 negation of a single bit, we can convert this operation to a shift. We
6543 can actually do this more generally, but it doesn't seem worth it. */
6545 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6546 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6547 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6548 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6549 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6550 == GET_MODE_PRECISION (mode
))
6551 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6553 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6554 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6556 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6557 non-zero bit in A is C1. */
6558 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6559 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6560 && INTEGRAL_MODE_P (GET_MODE (XEXP (cond
, 0)))
6561 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6562 == nonzero_bits (XEXP (cond
, 0), GET_MODE (XEXP (cond
, 0)))
6563 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6565 rtx val
= XEXP (cond
, 0);
6566 enum machine_mode val_mode
= GET_MODE (val
);
6567 if (val_mode
== mode
)
6569 else if (GET_MODE_PRECISION (val_mode
) < GET_MODE_PRECISION (mode
))
6570 return simplify_gen_unary (ZERO_EXTEND
, mode
, val
, val_mode
);
6576 /* Simplify X, a SET expression. Return the new expression. */
6579 simplify_set (rtx x
)
6581 rtx src
= SET_SRC (x
);
6582 rtx dest
= SET_DEST (x
);
6584 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6585 rtx_insn
*other_insn
;
6588 /* (set (pc) (return)) gets written as (return). */
6589 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6592 /* Now that we know for sure which bits of SRC we are using, see if we can
6593 simplify the expression for the object knowing that we only need the
6596 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6598 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6599 SUBST (SET_SRC (x
), src
);
6602 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6603 the comparison result and try to simplify it unless we already have used
6604 undobuf.other_insn. */
6605 if ((GET_MODE_CLASS (mode
) == MODE_CC
6606 || GET_CODE (src
) == COMPARE
6608 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6609 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6610 && COMPARISON_P (*cc_use
)
6611 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6613 enum rtx_code old_code
= GET_CODE (*cc_use
);
6614 enum rtx_code new_code
;
6616 int other_changed
= 0;
6617 rtx inner_compare
= NULL_RTX
;
6618 machine_mode compare_mode
= GET_MODE (dest
);
6620 if (GET_CODE (src
) == COMPARE
)
6622 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6623 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6625 inner_compare
= op0
;
6626 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6630 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6632 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6635 new_code
= old_code
;
6636 else if (!CONSTANT_P (tmp
))
6638 new_code
= GET_CODE (tmp
);
6639 op0
= XEXP (tmp
, 0);
6640 op1
= XEXP (tmp
, 1);
6644 rtx pat
= PATTERN (other_insn
);
6645 undobuf
.other_insn
= other_insn
;
6646 SUBST (*cc_use
, tmp
);
6648 /* Attempt to simplify CC user. */
6649 if (GET_CODE (pat
) == SET
)
6651 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6652 if (new_rtx
!= NULL_RTX
)
6653 SUBST (SET_SRC (pat
), new_rtx
);
6656 /* Convert X into a no-op move. */
6657 SUBST (SET_DEST (x
), pc_rtx
);
6658 SUBST (SET_SRC (x
), pc_rtx
);
6662 /* Simplify our comparison, if possible. */
6663 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6665 #ifdef SELECT_CC_MODE
6666 /* If this machine has CC modes other than CCmode, check to see if we
6667 need to use a different CC mode here. */
6668 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6669 compare_mode
= GET_MODE (op0
);
6670 else if (inner_compare
6671 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6672 && new_code
== old_code
6673 && op0
== XEXP (inner_compare
, 0)
6674 && op1
== XEXP (inner_compare
, 1))
6675 compare_mode
= GET_MODE (inner_compare
);
6677 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6679 /* If the mode changed, we have to change SET_DEST, the mode in the
6680 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6681 a hard register, just build new versions with the proper mode. If it
6682 is a pseudo, we lose unless it is only time we set the pseudo, in
6683 which case we can safely change its mode. */
6684 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6686 if (can_change_dest_mode (dest
, 0, compare_mode
))
6688 unsigned int regno
= REGNO (dest
);
6691 if (regno
< FIRST_PSEUDO_REGISTER
)
6692 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6695 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6696 new_dest
= regno_reg_rtx
[regno
];
6699 SUBST (SET_DEST (x
), new_dest
);
6700 SUBST (XEXP (*cc_use
, 0), new_dest
);
6706 #endif /* SELECT_CC_MODE */
6708 /* If the code changed, we have to build a new comparison in
6709 undobuf.other_insn. */
6710 if (new_code
!= old_code
)
6712 int other_changed_previously
= other_changed
;
6713 unsigned HOST_WIDE_INT mask
;
6714 rtx old_cc_use
= *cc_use
;
6716 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6720 /* If the only change we made was to change an EQ into an NE or
6721 vice versa, OP0 has only one bit that might be nonzero, and OP1
6722 is zero, check if changing the user of the condition code will
6723 produce a valid insn. If it won't, we can keep the original code
6724 in that insn by surrounding our operation with an XOR. */
6726 if (((old_code
== NE
&& new_code
== EQ
)
6727 || (old_code
== EQ
&& new_code
== NE
))
6728 && ! other_changed_previously
&& op1
== const0_rtx
6729 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6730 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6732 rtx pat
= PATTERN (other_insn
), note
= 0;
6734 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6735 && ! check_asm_operands (pat
)))
6737 *cc_use
= old_cc_use
;
6740 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6748 undobuf
.other_insn
= other_insn
;
6750 /* Don't generate a compare of a CC with 0, just use that CC. */
6751 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6753 SUBST (SET_SRC (x
), op0
);
6756 /* Otherwise, if we didn't previously have the same COMPARE we
6757 want, create it from scratch. */
6758 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6759 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6761 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6767 /* Get SET_SRC in a form where we have placed back any
6768 compound expressions. Then do the checks below. */
6769 src
= make_compound_operation (src
, SET
);
6770 SUBST (SET_SRC (x
), src
);
6773 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6774 and X being a REG or (subreg (reg)), we may be able to convert this to
6775 (set (subreg:m2 x) (op)).
6777 We can always do this if M1 is narrower than M2 because that means that
6778 we only care about the low bits of the result.
6780 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6781 perform a narrower operation than requested since the high-order bits will
6782 be undefined. On machine where it is defined, this transformation is safe
6783 as long as M1 and M2 have the same number of words. */
6785 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6786 && !OBJECT_P (SUBREG_REG (src
))
6787 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6789 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6790 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6791 && (WORD_REGISTER_OPERATIONS
6792 || (GET_MODE_SIZE (GET_MODE (src
))
6793 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6794 #ifdef CANNOT_CHANGE_MODE_CLASS
6795 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6796 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6797 GET_MODE (SUBREG_REG (src
)),
6801 || (GET_CODE (dest
) == SUBREG
6802 && REG_P (SUBREG_REG (dest
)))))
6804 SUBST (SET_DEST (x
),
6805 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6807 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6809 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6812 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6815 && GET_CODE (src
) == SUBREG
6816 && subreg_lowpart_p (src
)
6817 && (GET_MODE_PRECISION (GET_MODE (src
))
6818 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6820 rtx inner
= SUBREG_REG (src
);
6821 machine_mode inner_mode
= GET_MODE (inner
);
6823 /* Here we make sure that we don't have a sign bit on. */
6824 if (val_signbit_known_clear_p (GET_MODE (src
),
6825 nonzero_bits (inner
, inner_mode
)))
6827 SUBST (SET_SRC (x
), inner
);
6832 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6833 would require a paradoxical subreg. Replace the subreg with a
6834 zero_extend to avoid the reload that would otherwise be required. */
6836 enum rtx_code extend_op
;
6837 if (paradoxical_subreg_p (src
)
6838 && MEM_P (SUBREG_REG (src
))
6839 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6842 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6847 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6848 are comparing an item known to be 0 or -1 against 0, use a logical
6849 operation instead. Check for one of the arms being an IOR of the other
6850 arm with some value. We compute three terms to be IOR'ed together. In
6851 practice, at most two will be nonzero. Then we do the IOR's. */
6853 if (GET_CODE (dest
) != PC
6854 && GET_CODE (src
) == IF_THEN_ELSE
6855 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6856 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6857 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6858 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6859 && (!HAVE_conditional_move
6860 || ! can_conditionally_move_p (GET_MODE (src
)))
6861 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6862 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6863 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6864 && ! side_effects_p (src
))
6866 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6867 ? XEXP (src
, 1) : XEXP (src
, 2));
6868 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6869 ? XEXP (src
, 2) : XEXP (src
, 1));
6870 rtx term1
= const0_rtx
, term2
, term3
;
6872 if (GET_CODE (true_rtx
) == IOR
6873 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6874 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6875 else if (GET_CODE (true_rtx
) == IOR
6876 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6877 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6878 else if (GET_CODE (false_rtx
) == IOR
6879 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6880 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6881 else if (GET_CODE (false_rtx
) == IOR
6882 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6883 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6885 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6886 XEXP (XEXP (src
, 0), 0), true_rtx
);
6887 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6888 simplify_gen_unary (NOT
, GET_MODE (src
),
6889 XEXP (XEXP (src
, 0), 0),
6894 simplify_gen_binary (IOR
, GET_MODE (src
),
6895 simplify_gen_binary (IOR
, GET_MODE (src
),
6902 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6903 whole thing fail. */
6904 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6906 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6909 /* Convert this into a field assignment operation, if possible. */
6910 return make_field_assignment (x
);
6913 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6917 simplify_logical (rtx x
)
6919 machine_mode mode
= GET_MODE (x
);
6920 rtx op0
= XEXP (x
, 0);
6921 rtx op1
= XEXP (x
, 1);
6923 switch (GET_CODE (x
))
6926 /* We can call simplify_and_const_int only if we don't lose
6927 any (sign) bits when converting INTVAL (op1) to
6928 "unsigned HOST_WIDE_INT". */
6929 if (CONST_INT_P (op1
)
6930 && (HWI_COMPUTABLE_MODE_P (mode
)
6931 || INTVAL (op1
) > 0))
6933 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6934 if (GET_CODE (x
) != AND
)
6941 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6942 apply the distributive law and then the inverse distributive
6943 law to see if things simplify. */
6944 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6946 rtx result
= distribute_and_simplify_rtx (x
, 0);
6950 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6952 rtx result
= distribute_and_simplify_rtx (x
, 1);
6959 /* If we have (ior (and A B) C), apply the distributive law and then
6960 the inverse distributive law to see if things simplify. */
6962 if (GET_CODE (op0
) == AND
)
6964 rtx result
= distribute_and_simplify_rtx (x
, 0);
6969 if (GET_CODE (op1
) == AND
)
6971 rtx result
= distribute_and_simplify_rtx (x
, 1);
6984 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6985 operations" because they can be replaced with two more basic operations.
6986 ZERO_EXTEND is also considered "compound" because it can be replaced with
6987 an AND operation, which is simpler, though only one operation.
6989 The function expand_compound_operation is called with an rtx expression
6990 and will convert it to the appropriate shifts and AND operations,
6991 simplifying at each stage.
6993 The function make_compound_operation is called to convert an expression
6994 consisting of shifts and ANDs into the equivalent compound expression.
6995 It is the inverse of this function, loosely speaking. */
6998 expand_compound_operation (rtx x
)
7000 unsigned HOST_WIDE_INT pos
= 0, len
;
7002 unsigned int modewidth
;
7005 switch (GET_CODE (x
))
7011 /* We can't necessarily use a const_int for a multiword mode;
7012 it depends on implicitly extending the value.
7013 Since we don't know the right way to extend it,
7014 we can't tell whether the implicit way is right.
7016 Even for a mode that is no wider than a const_int,
7017 we can't win, because we need to sign extend one of its bits through
7018 the rest of it, and we don't know which bit. */
7019 if (CONST_INT_P (XEXP (x
, 0)))
7022 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7023 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7024 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7025 reloaded. If not for that, MEM's would very rarely be safe.
7027 Reject MODEs bigger than a word, because we might not be able
7028 to reference a two-register group starting with an arbitrary register
7029 (and currently gen_lowpart might crash for a SUBREG). */
7031 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7034 /* Reject MODEs that aren't scalar integers because turning vector
7035 or complex modes into shifts causes problems. */
7037 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7040 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7041 /* If the inner object has VOIDmode (the only way this can happen
7042 is if it is an ASM_OPERANDS), we can't do anything since we don't
7043 know how much masking to do. */
7055 /* If the operand is a CLOBBER, just return it. */
7056 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7059 if (!CONST_INT_P (XEXP (x
, 1))
7060 || !CONST_INT_P (XEXP (x
, 2))
7061 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7064 /* Reject MODEs that aren't scalar integers because turning vector
7065 or complex modes into shifts causes problems. */
7067 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7070 len
= INTVAL (XEXP (x
, 1));
7071 pos
= INTVAL (XEXP (x
, 2));
7073 /* This should stay within the object being extracted, fail otherwise. */
7074 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7077 if (BITS_BIG_ENDIAN
)
7078 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7085 /* Convert sign extension to zero extension, if we know that the high
7086 bit is not set, as this is easier to optimize. It will be converted
7087 back to cheaper alternative in make_extraction. */
7088 if (GET_CODE (x
) == SIGN_EXTEND
7089 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7090 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7091 & ~(((unsigned HOST_WIDE_INT
)
7092 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7096 machine_mode mode
= GET_MODE (x
);
7097 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7098 rtx temp2
= expand_compound_operation (temp
);
7100 /* Make sure this is a profitable operation. */
7101 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7102 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7104 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7105 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7111 /* We can optimize some special cases of ZERO_EXTEND. */
7112 if (GET_CODE (x
) == ZERO_EXTEND
)
7114 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7115 know that the last value didn't have any inappropriate bits
7117 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7118 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7119 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7120 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7121 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7122 return XEXP (XEXP (x
, 0), 0);
7124 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7125 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7126 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7127 && subreg_lowpart_p (XEXP (x
, 0))
7128 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7129 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7130 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7131 return SUBREG_REG (XEXP (x
, 0));
7133 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7134 is a comparison and STORE_FLAG_VALUE permits. This is like
7135 the first case, but it works even when GET_MODE (x) is larger
7136 than HOST_WIDE_INT. */
7137 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7138 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7139 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7140 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7141 <= HOST_BITS_PER_WIDE_INT
)
7142 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7143 return XEXP (XEXP (x
, 0), 0);
7145 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7146 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7147 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7148 && subreg_lowpart_p (XEXP (x
, 0))
7149 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7150 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7151 <= HOST_BITS_PER_WIDE_INT
)
7152 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7153 return SUBREG_REG (XEXP (x
, 0));
7157 /* If we reach here, we want to return a pair of shifts. The inner
7158 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7159 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7160 logical depending on the value of UNSIGNEDP.
7162 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7163 converted into an AND of a shift.
7165 We must check for the case where the left shift would have a negative
7166 count. This can happen in a case like (x >> 31) & 255 on machines
7167 that can't shift by a constant. On those machines, we would first
7168 combine the shift with the AND to produce a variable-position
7169 extraction. Then the constant of 31 would be substituted in
7170 to produce such a position. */
7172 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7173 if (modewidth
>= pos
+ len
)
7175 machine_mode mode
= GET_MODE (x
);
7176 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7177 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7179 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7180 tem
, modewidth
- pos
- len
);
7181 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7182 mode
, tem
, modewidth
- len
);
7184 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7185 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7186 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7189 (HOST_WIDE_INT_1U
<< len
) - 1);
7191 /* Any other cases we can't handle. */
7194 /* If we couldn't do this for some reason, return the original
7196 if (GET_CODE (tem
) == CLOBBER
)
7202 /* X is a SET which contains an assignment of one object into
7203 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7204 or certain SUBREGS). If possible, convert it into a series of
7207 We half-heartedly support variable positions, but do not at all
7208 support variable lengths. */
7211 expand_field_assignment (const_rtx x
)
7214 rtx pos
; /* Always counts from low bit. */
7216 rtx mask
, cleared
, masked
;
7217 machine_mode compute_mode
;
7219 /* Loop until we find something we can't simplify. */
7222 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7223 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7225 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7226 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7227 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7229 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7230 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7232 inner
= XEXP (SET_DEST (x
), 0);
7233 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7234 pos
= XEXP (SET_DEST (x
), 2);
7236 /* A constant position should stay within the width of INNER. */
7237 if (CONST_INT_P (pos
)
7238 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7241 if (BITS_BIG_ENDIAN
)
7243 if (CONST_INT_P (pos
))
7244 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7246 else if (GET_CODE (pos
) == MINUS
7247 && CONST_INT_P (XEXP (pos
, 1))
7248 && (INTVAL (XEXP (pos
, 1))
7249 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7250 /* If position is ADJUST - X, new position is X. */
7251 pos
= XEXP (pos
, 0);
7254 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7255 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7256 gen_int_mode (prec
- len
,
7263 /* A SUBREG between two modes that occupy the same numbers of words
7264 can be done by moving the SUBREG to the source. */
7265 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7266 /* We need SUBREGs to compute nonzero_bits properly. */
7267 && nonzero_sign_valid
7268 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7269 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7270 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7271 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7273 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7275 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7282 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7283 inner
= SUBREG_REG (inner
);
7285 compute_mode
= GET_MODE (inner
);
7287 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7288 if (! SCALAR_INT_MODE_P (compute_mode
))
7292 /* Don't do anything for vector or complex integral types. */
7293 if (! FLOAT_MODE_P (compute_mode
))
7296 /* Try to find an integral mode to pun with. */
7297 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7298 if (imode
== BLKmode
)
7301 compute_mode
= imode
;
7302 inner
= gen_lowpart (imode
, inner
);
7305 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7306 if (len
>= HOST_BITS_PER_WIDE_INT
)
7309 /* Don't try to compute in too wide unsupported modes. */
7310 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7313 /* Now compute the equivalent expression. Make a copy of INNER
7314 for the SET_DEST in case it is a MEM into which we will substitute;
7315 we don't want shared RTL in that case. */
7316 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7318 cleared
= simplify_gen_binary (AND
, compute_mode
,
7319 simplify_gen_unary (NOT
, compute_mode
,
7320 simplify_gen_binary (ASHIFT
,
7325 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7326 simplify_gen_binary (
7328 gen_lowpart (compute_mode
, SET_SRC (x
)),
7332 x
= gen_rtx_SET (copy_rtx (inner
),
7333 simplify_gen_binary (IOR
, compute_mode
,
7340 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7341 it is an RTX that represents the (variable) starting position; otherwise,
7342 POS is the (constant) starting bit position. Both are counted from the LSB.
7344 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7346 IN_DEST is nonzero if this is a reference in the destination of a SET.
7347 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7348 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7351 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7352 ZERO_EXTRACT should be built even for bits starting at bit 0.
7354 MODE is the desired mode of the result (if IN_DEST == 0).
7356 The result is an RTX for the extraction or NULL_RTX if the target
7360 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7361 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7362 int in_dest
, int in_compare
)
7364 /* This mode describes the size of the storage area
7365 to fetch the overall value from. Within that, we
7366 ignore the POS lowest bits, etc. */
7367 machine_mode is_mode
= GET_MODE (inner
);
7368 machine_mode inner_mode
;
7369 machine_mode wanted_inner_mode
;
7370 machine_mode wanted_inner_reg_mode
= word_mode
;
7371 machine_mode pos_mode
= word_mode
;
7372 machine_mode extraction_mode
= word_mode
;
7373 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7375 rtx orig_pos_rtx
= pos_rtx
;
7376 HOST_WIDE_INT orig_pos
;
7378 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7379 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7381 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7383 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7384 consider just the QI as the memory to extract from.
7385 The subreg adds or removes high bits; its mode is
7386 irrelevant to the meaning of this extraction,
7387 since POS and LEN count from the lsb. */
7388 if (MEM_P (SUBREG_REG (inner
)))
7389 is_mode
= GET_MODE (SUBREG_REG (inner
));
7390 inner
= SUBREG_REG (inner
);
7392 else if (GET_CODE (inner
) == ASHIFT
7393 && CONST_INT_P (XEXP (inner
, 1))
7394 && pos_rtx
== 0 && pos
== 0
7395 && len
> UINTVAL (XEXP (inner
, 1)))
7397 /* We're extracting the least significant bits of an rtx
7398 (ashift X (const_int C)), where LEN > C. Extract the
7399 least significant (LEN - C) bits of X, giving an rtx
7400 whose mode is MODE, then shift it left C times. */
7401 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7402 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7403 unsignedp
, in_dest
, in_compare
);
7405 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7407 else if (GET_CODE (inner
) == TRUNCATE
)
7408 inner
= XEXP (inner
, 0);
7410 inner_mode
= GET_MODE (inner
);
7412 /* See if this can be done without an extraction. We never can if the
7413 width of the field is not the same as that of some integer mode. For
7414 registers, we can only avoid the extraction if the position is at the
7415 low-order bit and this is either not in the destination or we have the
7416 appropriate STRICT_LOW_PART operation available.
7418 For MEM, we can avoid an extract if the field starts on an appropriate
7419 boundary and we can change the mode of the memory reference. */
7421 if (tmode
!= BLKmode
7422 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7424 && (pos
== 0 || REG_P (inner
))
7425 && (inner_mode
== tmode
7427 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7428 || reg_truncated_to_mode (tmode
, inner
))
7431 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7432 || (MEM_P (inner
) && pos_rtx
== 0
7434 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7435 : BITS_PER_UNIT
)) == 0
7436 /* We can't do this if we are widening INNER_MODE (it
7437 may not be aligned, for one thing). */
7438 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7439 && (inner_mode
== tmode
7440 || (! mode_dependent_address_p (XEXP (inner
, 0),
7441 MEM_ADDR_SPACE (inner
))
7442 && ! MEM_VOLATILE_P (inner
))))))
7444 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7445 field. If the original and current mode are the same, we need not
7446 adjust the offset. Otherwise, we do if bytes big endian.
7448 If INNER is not a MEM, get a piece consisting of just the field
7449 of interest (in this case POS % BITS_PER_WORD must be 0). */
7453 HOST_WIDE_INT offset
;
7455 /* POS counts from lsb, but make OFFSET count in memory order. */
7456 if (BYTES_BIG_ENDIAN
)
7457 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7459 offset
= pos
/ BITS_PER_UNIT
;
7461 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7463 else if (REG_P (inner
))
7465 if (tmode
!= inner_mode
)
7467 /* We can't call gen_lowpart in a DEST since we
7468 always want a SUBREG (see below) and it would sometimes
7469 return a new hard register. */
7472 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7474 if (WORDS_BIG_ENDIAN
7475 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7476 final_word
= ((GET_MODE_SIZE (inner_mode
)
7477 - GET_MODE_SIZE (tmode
))
7478 / UNITS_PER_WORD
) - final_word
;
7480 final_word
*= UNITS_PER_WORD
;
7481 if (BYTES_BIG_ENDIAN
&&
7482 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7483 final_word
+= (GET_MODE_SIZE (inner_mode
)
7484 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7486 /* Avoid creating invalid subregs, for example when
7487 simplifying (x>>32)&255. */
7488 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7491 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7494 new_rtx
= gen_lowpart (tmode
, inner
);
7500 new_rtx
= force_to_mode (inner
, tmode
,
7501 len
>= HOST_BITS_PER_WIDE_INT
7503 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7505 /* If this extraction is going into the destination of a SET,
7506 make a STRICT_LOW_PART unless we made a MEM. */
7509 return (MEM_P (new_rtx
) ? new_rtx
7510 : (GET_CODE (new_rtx
) != SUBREG
7511 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7512 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7517 if (CONST_SCALAR_INT_P (new_rtx
))
7518 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7519 mode
, new_rtx
, tmode
);
7521 /* If we know that no extraneous bits are set, and that the high
7522 bit is not set, convert the extraction to the cheaper of
7523 sign and zero extension, that are equivalent in these cases. */
7524 if (flag_expensive_optimizations
7525 && (HWI_COMPUTABLE_MODE_P (tmode
)
7526 && ((nonzero_bits (new_rtx
, tmode
)
7527 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7530 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7531 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7533 /* Prefer ZERO_EXTENSION, since it gives more information to
7535 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7536 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7541 /* Otherwise, sign- or zero-extend unless we already are in the
7544 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7548 /* Unless this is a COMPARE or we have a funny memory reference,
7549 don't do anything with zero-extending field extracts starting at
7550 the low-order bit since they are simple AND operations. */
7551 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7552 && ! in_compare
&& unsignedp
)
7555 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7556 if the position is not a constant and the length is not 1. In all
7557 other cases, we would only be going outside our object in cases when
7558 an original shift would have been undefined. */
7560 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7561 || (pos_rtx
!= 0 && len
!= 1)))
7564 enum extraction_pattern pattern
= (in_dest
? EP_insv
7565 : unsignedp
? EP_extzv
: EP_extv
);
7567 /* If INNER is not from memory, we want it to have the mode of a register
7568 extraction pattern's structure operand, or word_mode if there is no
7569 such pattern. The same applies to extraction_mode and pos_mode
7570 and their respective operands.
7572 For memory, assume that the desired extraction_mode and pos_mode
7573 are the same as for a register operation, since at present we don't
7574 have named patterns for aligned memory structures. */
7575 struct extraction_insn insn
;
7576 if (get_best_reg_extraction_insn (&insn
, pattern
,
7577 GET_MODE_BITSIZE (inner_mode
), mode
))
7579 wanted_inner_reg_mode
= insn
.struct_mode
;
7580 pos_mode
= insn
.pos_mode
;
7581 extraction_mode
= insn
.field_mode
;
7584 /* Never narrow an object, since that might not be safe. */
7586 if (mode
!= VOIDmode
7587 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7588 extraction_mode
= mode
;
7591 wanted_inner_mode
= wanted_inner_reg_mode
;
7594 /* Be careful not to go beyond the extracted object and maintain the
7595 natural alignment of the memory. */
7596 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7597 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7598 > GET_MODE_BITSIZE (wanted_inner_mode
))
7600 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7601 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7607 if (BITS_BIG_ENDIAN
)
7609 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7610 BITS_BIG_ENDIAN style. If position is constant, compute new
7611 position. Otherwise, build subtraction.
7612 Note that POS is relative to the mode of the original argument.
7613 If it's a MEM we need to recompute POS relative to that.
7614 However, if we're extracting from (or inserting into) a register,
7615 we want to recompute POS relative to wanted_inner_mode. */
7616 int width
= (MEM_P (inner
)
7617 ? GET_MODE_BITSIZE (is_mode
)
7618 : GET_MODE_BITSIZE (wanted_inner_mode
));
7621 pos
= width
- len
- pos
;
7624 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7625 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7627 /* POS may be less than 0 now, but we check for that below.
7628 Note that it can only be less than 0 if !MEM_P (inner). */
7631 /* If INNER has a wider mode, and this is a constant extraction, try to
7632 make it smaller and adjust the byte to point to the byte containing
7634 if (wanted_inner_mode
!= VOIDmode
7635 && inner_mode
!= wanted_inner_mode
7637 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7639 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7640 && ! MEM_VOLATILE_P (inner
))
7644 /* The computations below will be correct if the machine is big
7645 endian in both bits and bytes or little endian in bits and bytes.
7646 If it is mixed, we must adjust. */
7648 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7649 adjust OFFSET to compensate. */
7650 if (BYTES_BIG_ENDIAN
7651 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7652 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7654 /* We can now move to the desired byte. */
7655 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7656 * GET_MODE_SIZE (wanted_inner_mode
);
7657 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7659 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7660 && is_mode
!= wanted_inner_mode
)
7661 offset
= (GET_MODE_SIZE (is_mode
)
7662 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7664 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7667 /* If INNER is not memory, get it into the proper mode. If we are changing
7668 its mode, POS must be a constant and smaller than the size of the new
7670 else if (!MEM_P (inner
))
7672 /* On the LHS, don't create paradoxical subregs implicitely truncating
7673 the register unless TRULY_NOOP_TRUNCATION. */
7675 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7679 if (GET_MODE (inner
) != wanted_inner_mode
7681 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7687 inner
= force_to_mode (inner
, wanted_inner_mode
,
7689 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7691 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7696 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7697 have to zero extend. Otherwise, we can just use a SUBREG. */
7699 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7701 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7702 GET_MODE (pos_rtx
));
7704 /* If we know that no extraneous bits are set, and that the high
7705 bit is not set, convert extraction to cheaper one - either
7706 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7708 if (flag_expensive_optimizations
7709 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7710 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7711 & ~(((unsigned HOST_WIDE_INT
)
7712 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7716 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7717 GET_MODE (pos_rtx
));
7719 /* Prefer ZERO_EXTENSION, since it gives more information to
7721 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7722 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7728 /* Make POS_RTX unless we already have it and it is correct. If we don't
7729 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7731 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7732 pos_rtx
= orig_pos_rtx
;
7734 else if (pos_rtx
== 0)
7735 pos_rtx
= GEN_INT (pos
);
7737 /* Make the required operation. See if we can use existing rtx. */
7738 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7739 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7741 new_rtx
= gen_lowpart (mode
, new_rtx
);
7746 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7747 with any other operations in X. Return X without that shift if so. */
7750 extract_left_shift (rtx x
, int count
)
7752 enum rtx_code code
= GET_CODE (x
);
7753 machine_mode mode
= GET_MODE (x
);
7759 /* This is the shift itself. If it is wide enough, we will return
7760 either the value being shifted if the shift count is equal to
7761 COUNT or a shift for the difference. */
7762 if (CONST_INT_P (XEXP (x
, 1))
7763 && INTVAL (XEXP (x
, 1)) >= count
)
7764 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7765 INTVAL (XEXP (x
, 1)) - count
);
7769 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7770 return simplify_gen_unary (code
, mode
, tem
, mode
);
7774 case PLUS
: case IOR
: case XOR
: case AND
:
7775 /* If we can safely shift this constant and we find the inner shift,
7776 make a new operation. */
7777 if (CONST_INT_P (XEXP (x
, 1))
7778 && (UINTVAL (XEXP (x
, 1))
7779 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7780 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7782 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7783 return simplify_gen_binary (code
, mode
, tem
,
7784 gen_int_mode (val
, mode
));
7795 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7796 level of the expression and MODE is its mode. IN_CODE is as for
7797 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7798 that should be used when recursing on operands of *X_PTR.
7800 There are two possible actions:
7802 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7803 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7805 - Return a new rtx, which the caller returns directly. */
7808 make_compound_operation_int (machine_mode mode
, rtx
*x_ptr
,
7809 enum rtx_code in_code
,
7810 enum rtx_code
*next_code_ptr
)
7813 enum rtx_code next_code
= *next_code_ptr
;
7814 enum rtx_code code
= GET_CODE (x
);
7815 int mode_width
= GET_MODE_PRECISION (mode
);
7820 bool equality_comparison
= false;
7824 equality_comparison
= true;
7828 /* Process depending on the code of this operation. If NEW is set
7829 nonzero, it will be returned. */
7834 /* Convert shifts by constants into multiplications if inside
7836 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7837 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7838 && INTVAL (XEXP (x
, 1)) >= 0)
7840 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7841 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7843 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7844 if (GET_CODE (new_rtx
) == NEG
)
7846 new_rtx
= XEXP (new_rtx
, 0);
7849 multval
= trunc_int_for_mode (multval
, mode
);
7850 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7857 lhs
= make_compound_operation (lhs
, next_code
);
7858 rhs
= make_compound_operation (rhs
, next_code
);
7859 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
7861 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7863 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7865 else if (GET_CODE (lhs
) == MULT
7866 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7868 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7869 simplify_gen_unary (NEG
, mode
,
7872 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7876 SUBST (XEXP (x
, 0), lhs
);
7877 SUBST (XEXP (x
, 1), rhs
);
7879 maybe_swap_commutative_operands (x
);
7885 lhs
= make_compound_operation (lhs
, next_code
);
7886 rhs
= make_compound_operation (rhs
, next_code
);
7887 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
7889 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7891 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7893 else if (GET_CODE (rhs
) == MULT
7894 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7896 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7897 simplify_gen_unary (NEG
, mode
,
7900 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7904 SUBST (XEXP (x
, 0), lhs
);
7905 SUBST (XEXP (x
, 1), rhs
);
7910 /* If the second operand is not a constant, we can't do anything
7912 if (!CONST_INT_P (XEXP (x
, 1)))
7915 /* If the constant is a power of two minus one and the first operand
7916 is a logical right shift, make an extraction. */
7917 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7918 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7920 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7921 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7922 0, in_code
== COMPARE
);
7925 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7926 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7927 && subreg_lowpart_p (XEXP (x
, 0))
7928 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7929 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7931 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
7932 machine_mode inner_mode
= GET_MODE (inner_x0
);
7933 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
7934 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
7936 i
, 1, 0, in_code
== COMPARE
);
7940 /* If we narrowed the mode when dropping the subreg, then
7941 we must zero-extend to keep the semantics of the AND. */
7942 if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
7944 else if (SCALAR_INT_MODE_P (inner_mode
))
7945 new_rtx
= simplify_gen_unary (ZERO_EXTEND
, mode
,
7946 new_rtx
, inner_mode
);
7951 /* If that didn't give anything, see if the AND simplifies on
7953 if (!new_rtx
&& i
>= 0)
7955 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7956 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
7957 0, in_code
== COMPARE
);
7960 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7961 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7962 || GET_CODE (XEXP (x
, 0)) == IOR
)
7963 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7964 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7965 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7967 /* Apply the distributive law, and then try to make extractions. */
7968 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7969 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7971 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7973 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7976 /* If we are have (and (rotate X C) M) and C is larger than the number
7977 of bits in M, this is an extraction. */
7979 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7980 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7981 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7982 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7984 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7985 new_rtx
= make_extraction (mode
, new_rtx
,
7986 (GET_MODE_PRECISION (mode
)
7987 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7988 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7991 /* On machines without logical shifts, if the operand of the AND is
7992 a logical shift and our mask turns off all the propagated sign
7993 bits, we can replace the logical shift with an arithmetic shift. */
7994 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7995 && !have_insn_for (LSHIFTRT
, mode
)
7996 && have_insn_for (ASHIFTRT
, mode
)
7997 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7998 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7999 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8000 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8002 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8004 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8005 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8007 gen_rtx_ASHIFTRT (mode
,
8008 make_compound_operation
8009 (XEXP (XEXP (x
, 0), 0), next_code
),
8010 XEXP (XEXP (x
, 0), 1)));
8013 /* If the constant is one less than a power of two, this might be
8014 representable by an extraction even if no shift is present.
8015 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8016 we are in a COMPARE. */
8017 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8018 new_rtx
= make_extraction (mode
,
8019 make_compound_operation (XEXP (x
, 0),
8021 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8023 /* If we are in a comparison and this is an AND with a power of two,
8024 convert this into the appropriate bit extract. */
8025 else if (in_code
== COMPARE
8026 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8027 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8028 new_rtx
= make_extraction (mode
,
8029 make_compound_operation (XEXP (x
, 0),
8031 i
, NULL_RTX
, 1, 1, 0, 1);
8033 /* If the one operand is a paradoxical subreg of a register or memory and
8034 the constant (limited to the smaller mode) has only zero bits where
8035 the sub expression has known zero bits, this can be expressed as
8037 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8041 sub
= XEXP (XEXP (x
, 0), 0);
8042 machine_mode sub_mode
= GET_MODE (sub
);
8043 if ((REG_P (sub
) || MEM_P (sub
))
8044 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8046 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8047 unsigned HOST_WIDE_INT mask
;
8049 /* original AND constant with all the known zero bits set */
8050 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8051 if ((mask
& mode_mask
) == mode_mask
)
8053 new_rtx
= make_compound_operation (sub
, next_code
);
8054 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8055 GET_MODE_PRECISION (sub_mode
),
8056 1, 0, in_code
== COMPARE
);
8064 /* If the sign bit is known to be zero, replace this with an
8065 arithmetic shift. */
8066 if (have_insn_for (ASHIFTRT
, mode
)
8067 && ! have_insn_for (LSHIFTRT
, mode
)
8068 && mode_width
<= HOST_BITS_PER_WIDE_INT
8069 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8071 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8072 make_compound_operation (XEXP (x
, 0),
8084 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8085 this is a SIGN_EXTRACT. */
8086 if (CONST_INT_P (rhs
)
8087 && GET_CODE (lhs
) == ASHIFT
8088 && CONST_INT_P (XEXP (lhs
, 1))
8089 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8090 && INTVAL (XEXP (lhs
, 1)) >= 0
8091 && INTVAL (rhs
) < mode_width
)
8093 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8094 new_rtx
= make_extraction (mode
, new_rtx
,
8095 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8096 NULL_RTX
, mode_width
- INTVAL (rhs
),
8097 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8101 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8102 If so, try to merge the shifts into a SIGN_EXTEND. We could
8103 also do this for some cases of SIGN_EXTRACT, but it doesn't
8104 seem worth the effort; the case checked for occurs on Alpha. */
8107 && ! (GET_CODE (lhs
) == SUBREG
8108 && (OBJECT_P (SUBREG_REG (lhs
))))
8109 && CONST_INT_P (rhs
)
8110 && INTVAL (rhs
) >= 0
8111 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8112 && INTVAL (rhs
) < mode_width
8113 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8114 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8115 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8116 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8121 /* Call ourselves recursively on the inner expression. If we are
8122 narrowing the object and it has a different RTL code from
8123 what it originally did, do this SUBREG as a force_to_mode. */
8125 rtx inner
= SUBREG_REG (x
), simplified
;
8126 enum rtx_code subreg_code
= in_code
;
8128 /* If the SUBREG is masking of a logical right shift,
8129 make an extraction. */
8130 if (GET_CODE (inner
) == LSHIFTRT
8131 && CONST_INT_P (XEXP (inner
, 1))
8132 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8133 && (UINTVAL (XEXP (inner
, 1))
8134 < GET_MODE_PRECISION (GET_MODE (inner
)))
8135 && subreg_lowpart_p (x
))
8137 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8138 int width
= GET_MODE_PRECISION (GET_MODE (inner
))
8139 - INTVAL (XEXP (inner
, 1));
8140 if (width
> mode_width
)
8142 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8143 width
, 1, 0, in_code
== COMPARE
);
8147 /* If in_code is COMPARE, it isn't always safe to pass it through
8148 to the recursive make_compound_operation call. */
8149 if (subreg_code
== COMPARE
8150 && (!subreg_lowpart_p (x
)
8151 || GET_CODE (inner
) == SUBREG
8152 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8153 is (const_int 0), rather than
8154 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8155 || (GET_CODE (inner
) == AND
8156 && CONST_INT_P (XEXP (inner
, 1))
8157 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8158 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8159 >= GET_MODE_BITSIZE (mode
))))
8162 tem
= make_compound_operation (inner
, subreg_code
);
8165 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8169 if (GET_CODE (tem
) != GET_CODE (inner
)
8170 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8171 && subreg_lowpart_p (x
))
8174 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8176 /* If we have something other than a SUBREG, we might have
8177 done an expansion, so rerun ourselves. */
8178 if (GET_CODE (newer
) != SUBREG
)
8179 newer
= make_compound_operation (newer
, in_code
);
8181 /* force_to_mode can expand compounds. If it just re-expanded the
8182 compound, use gen_lowpart to convert to the desired mode. */
8183 if (rtx_equal_p (newer
, x
)
8184 /* Likewise if it re-expanded the compound only partially.
8185 This happens for SUBREG of ZERO_EXTRACT if they extract
8186 the same number of bits. */
8187 || (GET_CODE (newer
) == SUBREG
8188 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8189 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8190 && GET_CODE (inner
) == AND
8191 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8192 return gen_lowpart (GET_MODE (x
), tem
);
8207 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8208 *next_code_ptr
= next_code
;
8212 /* Look at the expression rooted at X. Look for expressions
8213 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8214 Form these expressions.
8216 Return the new rtx, usually just X.
8218 Also, for machines like the VAX that don't have logical shift insns,
8219 try to convert logical to arithmetic shift operations in cases where
8220 they are equivalent. This undoes the canonicalizations to logical
8221 shifts done elsewhere.
8223 We try, as much as possible, to re-use rtl expressions to save memory.
8225 IN_CODE says what kind of expression we are processing. Normally, it is
8226 SET. In a memory address it is MEM. When processing the arguments of
8227 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8228 precisely it is an equality comparison against zero. */
8231 make_compound_operation (rtx x
, enum rtx_code in_code
)
8233 enum rtx_code code
= GET_CODE (x
);
8236 enum rtx_code next_code
;
8239 /* Select the code to be used in recursive calls. Once we are inside an
8240 address, we stay there. If we have a comparison, set to COMPARE,
8241 but once inside, go back to our default of SET. */
8243 next_code
= (code
== MEM
? MEM
8244 : ((code
== COMPARE
|| COMPARISON_P (x
))
8245 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8246 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8248 if (SCALAR_INT_MODE_P (GET_MODE (x
)))
8250 rtx new_rtx
= make_compound_operation_int (GET_MODE (x
), &x
,
8251 in_code
, &next_code
);
8254 code
= GET_CODE (x
);
8257 /* Now recursively process each operand of this operation. We need to
8258 handle ZERO_EXTEND specially so that we don't lose track of the
8260 if (code
== ZERO_EXTEND
)
8262 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8263 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8264 new_rtx
, GET_MODE (XEXP (x
, 0)));
8267 SUBST (XEXP (x
, 0), new_rtx
);
8271 fmt
= GET_RTX_FORMAT (code
);
8272 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8275 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8276 SUBST (XEXP (x
, i
), new_rtx
);
8278 else if (fmt
[i
] == 'E')
8279 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8281 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8282 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8285 maybe_swap_commutative_operands (x
);
8289 /* Given M see if it is a value that would select a field of bits
8290 within an item, but not the entire word. Return -1 if not.
8291 Otherwise, return the starting position of the field, where 0 is the
8294 *PLEN is set to the length of the field. */
8297 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8299 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8300 int pos
= m
? ctz_hwi (m
) : -1;
8304 /* Now shift off the low-order zero bits and see if we have a
8305 power of two minus 1. */
8306 len
= exact_log2 ((m
>> pos
) + 1);
8315 /* If X refers to a register that equals REG in value, replace these
8316 references with REG. */
8318 canon_reg_for_combine (rtx x
, rtx reg
)
8325 enum rtx_code code
= GET_CODE (x
);
8326 switch (GET_RTX_CLASS (code
))
8329 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8330 if (op0
!= XEXP (x
, 0))
8331 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8336 case RTX_COMM_ARITH
:
8337 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8338 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8339 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8340 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8344 case RTX_COMM_COMPARE
:
8345 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8346 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8347 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8348 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8349 GET_MODE (op0
), op0
, op1
);
8353 case RTX_BITFIELD_OPS
:
8354 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8355 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8356 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8357 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8358 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8359 GET_MODE (op0
), op0
, op1
, op2
);
8365 if (rtx_equal_p (get_last_value (reg
), x
)
8366 || rtx_equal_p (reg
, get_last_value (x
)))
8375 fmt
= GET_RTX_FORMAT (code
);
8377 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8380 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8381 if (op
!= XEXP (x
, i
))
8391 else if (fmt
[i
] == 'E')
8394 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8396 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8397 if (op
!= XVECEXP (x
, i
, j
))
8404 XVECEXP (x
, i
, j
) = op
;
8415 /* Return X converted to MODE. If the value is already truncated to
8416 MODE we can just return a subreg even though in the general case we
8417 would need an explicit truncation. */
8420 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8422 if (!CONST_INT_P (x
)
8423 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8424 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8425 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8427 /* Bit-cast X into an integer mode. */
8428 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8429 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8430 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8434 return gen_lowpart (mode
, x
);
8437 /* See if X can be simplified knowing that we will only refer to it in
8438 MODE and will only refer to those bits that are nonzero in MASK.
8439 If other bits are being computed or if masking operations are done
8440 that select a superset of the bits in MASK, they can sometimes be
8443 Return a possibly simplified expression, but always convert X to
8444 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8446 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8447 are all off in X. This is used when X will be complemented, by either
8448 NOT, NEG, or XOR. */
8451 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8454 enum rtx_code code
= GET_CODE (x
);
8455 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8456 machine_mode op_mode
;
8457 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8460 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8461 code below will do the wrong thing since the mode of such an
8462 expression is VOIDmode.
8464 Also do nothing if X is a CLOBBER; this can happen if X was
8465 the return value from a call to gen_lowpart. */
8466 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8469 /* We want to perform the operation in its present mode unless we know
8470 that the operation is valid in MODE, in which case we do the operation
8472 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8473 && have_insn_for (code
, mode
))
8474 ? mode
: GET_MODE (x
));
8476 /* It is not valid to do a right-shift in a narrower mode
8477 than the one it came in with. */
8478 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8479 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8480 op_mode
= GET_MODE (x
);
8482 /* Truncate MASK to fit OP_MODE. */
8484 mask
&= GET_MODE_MASK (op_mode
);
8486 /* When we have an arithmetic operation, or a shift whose count we
8487 do not know, we need to assume that all bits up to the highest-order
8488 bit in MASK will be needed. This is how we form such a mask. */
8489 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8490 fuller_mask
= HOST_WIDE_INT_M1U
;
8492 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8495 /* Determine what bits of X are guaranteed to be (non)zero. */
8496 nonzero
= nonzero_bits (x
, mode
);
8498 /* If none of the bits in X are needed, return a zero. */
8499 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8502 /* If X is a CONST_INT, return a new one. Do this here since the
8503 test below will fail. */
8504 if (CONST_INT_P (x
))
8506 if (SCALAR_INT_MODE_P (mode
))
8507 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8510 x
= GEN_INT (INTVAL (x
) & mask
);
8511 return gen_lowpart_common (mode
, x
);
8515 /* If X is narrower than MODE and we want all the bits in X's mode, just
8516 get X in the proper mode. */
8517 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8518 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8519 return gen_lowpart (mode
, x
);
8521 /* We can ignore the effect of a SUBREG if it narrows the mode or
8522 if the constant masks to zero all the bits the mode doesn't have. */
8523 if (GET_CODE (x
) == SUBREG
8524 && subreg_lowpart_p (x
)
8525 && ((GET_MODE_SIZE (GET_MODE (x
))
8526 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8528 & GET_MODE_MASK (GET_MODE (x
))
8529 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8530 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8532 /* The arithmetic simplifications here only work for scalar integer modes. */
8533 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8534 return gen_lowpart_or_truncate (mode
, x
);
8539 /* If X is a (clobber (const_int)), return it since we know we are
8540 generating something that won't match. */
8547 x
= expand_compound_operation (x
);
8548 if (GET_CODE (x
) != code
)
8549 return force_to_mode (x
, mode
, mask
, next_select
);
8553 /* Similarly for a truncate. */
8554 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8557 /* If this is an AND with a constant, convert it into an AND
8558 whose constant is the AND of that constant with MASK. If it
8559 remains an AND of MASK, delete it since it is redundant. */
8561 if (CONST_INT_P (XEXP (x
, 1)))
8563 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8564 mask
& INTVAL (XEXP (x
, 1)));
8566 /* If X is still an AND, see if it is an AND with a mask that
8567 is just some low-order bits. If so, and it is MASK, we don't
8570 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8571 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8575 /* If it remains an AND, try making another AND with the bits
8576 in the mode mask that aren't in MASK turned on. If the
8577 constant in the AND is wide enough, this might make a
8578 cheaper constant. */
8580 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8581 && GET_MODE_MASK (GET_MODE (x
)) != mask
8582 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8584 unsigned HOST_WIDE_INT cval
8585 = UINTVAL (XEXP (x
, 1))
8586 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8589 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8590 gen_int_mode (cval
, GET_MODE (x
)));
8591 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8592 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8602 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8603 low-order bits (as in an alignment operation) and FOO is already
8604 aligned to that boundary, mask C1 to that boundary as well.
8605 This may eliminate that PLUS and, later, the AND. */
8608 unsigned int width
= GET_MODE_PRECISION (mode
);
8609 unsigned HOST_WIDE_INT smask
= mask
;
8611 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8612 number, sign extend it. */
8614 if (width
< HOST_BITS_PER_WIDE_INT
8615 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8616 smask
|= HOST_WIDE_INT_M1U
<< width
;
8618 if (CONST_INT_P (XEXP (x
, 1))
8619 && pow2p_hwi (- smask
)
8620 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8621 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8622 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8623 (INTVAL (XEXP (x
, 1)) & smask
)),
8624 mode
, smask
, next_select
);
8630 /* Substituting into the operands of a widening MULT is not likely to
8631 create RTL matching a machine insn. */
8633 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8634 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8635 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8636 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8637 && REG_P (XEXP (XEXP (x
, 0), 0))
8638 && REG_P (XEXP (XEXP (x
, 1), 0)))
8639 return gen_lowpart_or_truncate (mode
, x
);
8641 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8642 most significant bit in MASK since carries from those bits will
8643 affect the bits we are interested in. */
8648 /* If X is (minus C Y) where C's least set bit is larger than any bit
8649 in the mask, then we may replace with (neg Y). */
8650 if (CONST_INT_P (XEXP (x
, 0))
8651 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8653 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8655 return force_to_mode (x
, mode
, mask
, next_select
);
8658 /* Similarly, if C contains every bit in the fuller_mask, then we may
8659 replace with (not Y). */
8660 if (CONST_INT_P (XEXP (x
, 0))
8661 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8663 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8664 XEXP (x
, 1), GET_MODE (x
));
8665 return force_to_mode (x
, mode
, mask
, next_select
);
8673 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8674 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8675 operation which may be a bitfield extraction. Ensure that the
8676 constant we form is not wider than the mode of X. */
8678 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8679 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8680 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8681 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8682 && CONST_INT_P (XEXP (x
, 1))
8683 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8684 + floor_log2 (INTVAL (XEXP (x
, 1))))
8685 < GET_MODE_PRECISION (GET_MODE (x
)))
8686 && (UINTVAL (XEXP (x
, 1))
8687 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8689 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8690 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8692 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8693 XEXP (XEXP (x
, 0), 0), temp
);
8694 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8695 XEXP (XEXP (x
, 0), 1));
8696 return force_to_mode (x
, mode
, mask
, next_select
);
8700 /* For most binary operations, just propagate into the operation and
8701 change the mode if we have an operation of that mode. */
8703 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8704 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8706 /* If we ended up truncating both operands, truncate the result of the
8707 operation instead. */
8708 if (GET_CODE (op0
) == TRUNCATE
8709 && GET_CODE (op1
) == TRUNCATE
)
8711 op0
= XEXP (op0
, 0);
8712 op1
= XEXP (op1
, 0);
8715 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8716 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8718 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8719 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8723 /* For left shifts, do the same, but just for the first operand.
8724 However, we cannot do anything with shifts where we cannot
8725 guarantee that the counts are smaller than the size of the mode
8726 because such a count will have a different meaning in a
8729 if (! (CONST_INT_P (XEXP (x
, 1))
8730 && INTVAL (XEXP (x
, 1)) >= 0
8731 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8732 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8733 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8734 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8737 /* If the shift count is a constant and we can do arithmetic in
8738 the mode of the shift, refine which bits we need. Otherwise, use the
8739 conservative form of the mask. */
8740 if (CONST_INT_P (XEXP (x
, 1))
8741 && INTVAL (XEXP (x
, 1)) >= 0
8742 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8743 && HWI_COMPUTABLE_MODE_P (op_mode
))
8744 mask
>>= INTVAL (XEXP (x
, 1));
8748 op0
= gen_lowpart_or_truncate (op_mode
,
8749 force_to_mode (XEXP (x
, 0), op_mode
,
8750 mask
, next_select
));
8752 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8753 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8757 /* Here we can only do something if the shift count is a constant,
8758 this shift constant is valid for the host, and we can do arithmetic
8761 if (CONST_INT_P (XEXP (x
, 1))
8762 && INTVAL (XEXP (x
, 1)) >= 0
8763 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8764 && HWI_COMPUTABLE_MODE_P (op_mode
))
8766 rtx inner
= XEXP (x
, 0);
8767 unsigned HOST_WIDE_INT inner_mask
;
8769 /* Select the mask of the bits we need for the shift operand. */
8770 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8772 /* We can only change the mode of the shift if we can do arithmetic
8773 in the mode of the shift and INNER_MASK is no wider than the
8774 width of X's mode. */
8775 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8776 op_mode
= GET_MODE (x
);
8778 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8780 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8781 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8784 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8785 shift and AND produces only copies of the sign bit (C2 is one less
8786 than a power of two), we can do this with just a shift. */
8788 if (GET_CODE (x
) == LSHIFTRT
8789 && CONST_INT_P (XEXP (x
, 1))
8790 /* The shift puts one of the sign bit copies in the least significant
8792 && ((INTVAL (XEXP (x
, 1))
8793 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8794 >= GET_MODE_PRECISION (GET_MODE (x
)))
8795 && pow2p_hwi (mask
+ 1)
8796 /* Number of bits left after the shift must be more than the mask
8798 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8799 <= GET_MODE_PRECISION (GET_MODE (x
)))
8800 /* Must be more sign bit copies than the mask needs. */
8801 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8802 >= exact_log2 (mask
+ 1)))
8803 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8804 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8805 - exact_log2 (mask
+ 1)));
8810 /* If we are just looking for the sign bit, we don't need this shift at
8811 all, even if it has a variable count. */
8812 if (val_signbit_p (GET_MODE (x
), mask
))
8813 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8815 /* If this is a shift by a constant, get a mask that contains those bits
8816 that are not copies of the sign bit. We then have two cases: If
8817 MASK only includes those bits, this can be a logical shift, which may
8818 allow simplifications. If MASK is a single-bit field not within
8819 those bits, we are requesting a copy of the sign bit and hence can
8820 shift the sign bit to the appropriate location. */
8822 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8823 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8827 /* If the considered data is wider than HOST_WIDE_INT, we can't
8828 represent a mask for all its bits in a single scalar.
8829 But we only care about the lower bits, so calculate these. */
8831 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8833 nonzero
= HOST_WIDE_INT_M1U
;
8835 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8836 is the number of bits a full-width mask would have set.
8837 We need only shift if these are fewer than nonzero can
8838 hold. If not, we must keep all bits set in nonzero. */
8840 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8841 < HOST_BITS_PER_WIDE_INT
)
8842 nonzero
>>= INTVAL (XEXP (x
, 1))
8843 + HOST_BITS_PER_WIDE_INT
8844 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8848 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8849 nonzero
>>= INTVAL (XEXP (x
, 1));
8852 if ((mask
& ~nonzero
) == 0)
8854 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8855 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8856 if (GET_CODE (x
) != ASHIFTRT
)
8857 return force_to_mode (x
, mode
, mask
, next_select
);
8860 else if ((i
= exact_log2 (mask
)) >= 0)
8862 x
= simplify_shift_const
8863 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8864 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8866 if (GET_CODE (x
) != ASHIFTRT
)
8867 return force_to_mode (x
, mode
, mask
, next_select
);
8871 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8872 even if the shift count isn't a constant. */
8874 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8875 XEXP (x
, 0), XEXP (x
, 1));
8879 /* If this is a zero- or sign-extension operation that just affects bits
8880 we don't care about, remove it. Be sure the call above returned
8881 something that is still a shift. */
8883 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8884 && CONST_INT_P (XEXP (x
, 1))
8885 && INTVAL (XEXP (x
, 1)) >= 0
8886 && (INTVAL (XEXP (x
, 1))
8887 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8888 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8889 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8890 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8897 /* If the shift count is constant and we can do computations
8898 in the mode of X, compute where the bits we care about are.
8899 Otherwise, we can't do anything. Don't change the mode of
8900 the shift or propagate MODE into the shift, though. */
8901 if (CONST_INT_P (XEXP (x
, 1))
8902 && INTVAL (XEXP (x
, 1)) >= 0)
8904 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8906 gen_int_mode (mask
, GET_MODE (x
)),
8908 if (temp
&& CONST_INT_P (temp
))
8909 x
= simplify_gen_binary (code
, GET_MODE (x
),
8910 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8911 INTVAL (temp
), next_select
),
8917 /* If we just want the low-order bit, the NEG isn't needed since it
8918 won't change the low-order bit. */
8920 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8922 /* We need any bits less significant than the most significant bit in
8923 MASK since carries from those bits will affect the bits we are
8929 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8930 same as the XOR case above. Ensure that the constant we form is not
8931 wider than the mode of X. */
8933 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8934 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8935 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8936 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8937 < GET_MODE_PRECISION (GET_MODE (x
)))
8938 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8940 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8942 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8943 XEXP (XEXP (x
, 0), 0), temp
);
8944 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8945 temp
, XEXP (XEXP (x
, 0), 1));
8947 return force_to_mode (x
, mode
, mask
, next_select
);
8950 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8951 use the full mask inside the NOT. */
8955 op0
= gen_lowpart_or_truncate (op_mode
,
8956 force_to_mode (XEXP (x
, 0), mode
, mask
,
8958 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8959 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8963 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8964 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8965 which is equal to STORE_FLAG_VALUE. */
8966 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8967 && XEXP (x
, 1) == const0_rtx
8968 && GET_MODE (XEXP (x
, 0)) == mode
8969 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
8970 && (nonzero_bits (XEXP (x
, 0), mode
)
8971 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8972 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8977 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8978 written in a narrower mode. We play it safe and do not do so. */
8980 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8981 force_to_mode (XEXP (x
, 1), mode
,
8982 mask
, next_select
));
8983 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8984 force_to_mode (XEXP (x
, 2), mode
,
8985 mask
, next_select
));
8986 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8987 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8988 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8996 /* Ensure we return a value of the proper mode. */
8997 return gen_lowpart_or_truncate (mode
, x
);
9000 /* Return nonzero if X is an expression that has one of two values depending on
9001 whether some other value is zero or nonzero. In that case, we return the
9002 value that is being tested, *PTRUE is set to the value if the rtx being
9003 returned has a nonzero value, and *PFALSE is set to the other alternative.
9005 If we return zero, we set *PTRUE and *PFALSE to X. */
9008 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9010 machine_mode mode
= GET_MODE (x
);
9011 enum rtx_code code
= GET_CODE (x
);
9012 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9013 unsigned HOST_WIDE_INT nz
;
9015 /* If we are comparing a value against zero, we are done. */
9016 if ((code
== NE
|| code
== EQ
)
9017 && XEXP (x
, 1) == const0_rtx
)
9019 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9020 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9024 /* If this is a unary operation whose operand has one of two values, apply
9025 our opcode to compute those values. */
9026 else if (UNARY_P (x
)
9027 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9029 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9030 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9031 GET_MODE (XEXP (x
, 0)));
9035 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9036 make can't possibly match and would suppress other optimizations. */
9037 else if (code
== COMPARE
)
9040 /* If this is a binary operation, see if either side has only one of two
9041 values. If either one does or if both do and they are conditional on
9042 the same value, compute the new true and false values. */
9043 else if (BINARY_P (x
))
9045 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
9046 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
9048 if ((cond0
!= 0 || cond1
!= 0)
9049 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
9051 /* If if_then_else_cond returned zero, then true/false are the
9052 same rtl. We must copy one of them to prevent invalid rtl
9055 true0
= copy_rtx (true0
);
9056 else if (cond1
== 0)
9057 true1
= copy_rtx (true1
);
9059 if (COMPARISON_P (x
))
9061 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9063 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9068 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9069 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9072 return cond0
? cond0
: cond1
;
9075 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9076 operands is zero when the other is nonzero, and vice-versa,
9077 and STORE_FLAG_VALUE is 1 or -1. */
9079 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9080 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9082 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9084 rtx op0
= XEXP (XEXP (x
, 0), 1);
9085 rtx op1
= XEXP (XEXP (x
, 1), 1);
9087 cond0
= XEXP (XEXP (x
, 0), 0);
9088 cond1
= XEXP (XEXP (x
, 1), 0);
9090 if (COMPARISON_P (cond0
)
9091 && COMPARISON_P (cond1
)
9092 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9093 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9094 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9095 || ((swap_condition (GET_CODE (cond0
))
9096 == reversed_comparison_code (cond1
, NULL
))
9097 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9098 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9099 && ! side_effects_p (x
))
9101 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9102 *pfalse
= simplify_gen_binary (MULT
, mode
,
9104 ? simplify_gen_unary (NEG
, mode
,
9112 /* Similarly for MULT, AND and UMIN, except that for these the result
9114 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9115 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9116 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9118 cond0
= XEXP (XEXP (x
, 0), 0);
9119 cond1
= XEXP (XEXP (x
, 1), 0);
9121 if (COMPARISON_P (cond0
)
9122 && COMPARISON_P (cond1
)
9123 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9124 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9125 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9126 || ((swap_condition (GET_CODE (cond0
))
9127 == reversed_comparison_code (cond1
, NULL
))
9128 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9129 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9130 && ! side_effects_p (x
))
9132 *ptrue
= *pfalse
= const0_rtx
;
9138 else if (code
== IF_THEN_ELSE
)
9140 /* If we have IF_THEN_ELSE already, extract the condition and
9141 canonicalize it if it is NE or EQ. */
9142 cond0
= XEXP (x
, 0);
9143 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9144 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9145 return XEXP (cond0
, 0);
9146 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9148 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9149 return XEXP (cond0
, 0);
9155 /* If X is a SUBREG, we can narrow both the true and false values
9156 if the inner expression, if there is a condition. */
9157 else if (code
== SUBREG
9158 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9161 true0
= simplify_gen_subreg (mode
, true0
,
9162 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9163 false0
= simplify_gen_subreg (mode
, false0
,
9164 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9165 if (true0
&& false0
)
9173 /* If X is a constant, this isn't special and will cause confusions
9174 if we treat it as such. Likewise if it is equivalent to a constant. */
9175 else if (CONSTANT_P (x
)
9176 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9179 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9180 will be least confusing to the rest of the compiler. */
9181 else if (mode
== BImode
)
9183 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9187 /* If X is known to be either 0 or -1, those are the true and
9188 false values when testing X. */
9189 else if (x
== constm1_rtx
|| x
== const0_rtx
9190 || (mode
!= VOIDmode
&& mode
!= BLKmode
9191 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9193 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9197 /* Likewise for 0 or a single bit. */
9198 else if (HWI_COMPUTABLE_MODE_P (mode
)
9199 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9201 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9205 /* Otherwise fail; show no condition with true and false values the same. */
9206 *ptrue
= *pfalse
= x
;
9210 /* Return the value of expression X given the fact that condition COND
9211 is known to be true when applied to REG as its first operand and VAL
9212 as its second. X is known to not be shared and so can be modified in
9215 We only handle the simplest cases, and specifically those cases that
9216 arise with IF_THEN_ELSE expressions. */
9219 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9221 enum rtx_code code
= GET_CODE (x
);
9225 if (side_effects_p (x
))
9228 /* If either operand of the condition is a floating point value,
9229 then we have to avoid collapsing an EQ comparison. */
9231 && rtx_equal_p (x
, reg
)
9232 && ! FLOAT_MODE_P (GET_MODE (x
))
9233 && ! FLOAT_MODE_P (GET_MODE (val
)))
9236 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9239 /* If X is (abs REG) and we know something about REG's relationship
9240 with zero, we may be able to simplify this. */
9242 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9245 case GE
: case GT
: case EQ
:
9248 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9250 GET_MODE (XEXP (x
, 0)));
9255 /* The only other cases we handle are MIN, MAX, and comparisons if the
9256 operands are the same as REG and VAL. */
9258 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9260 if (rtx_equal_p (XEXP (x
, 0), val
))
9262 std::swap (val
, reg
);
9263 cond
= swap_condition (cond
);
9266 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9268 if (COMPARISON_P (x
))
9270 if (comparison_dominates_p (cond
, code
))
9271 return const_true_rtx
;
9273 code
= reversed_comparison_code (x
, NULL
);
9275 && comparison_dominates_p (cond
, code
))
9280 else if (code
== SMAX
|| code
== SMIN
9281 || code
== UMIN
|| code
== UMAX
)
9283 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9285 /* Do not reverse the condition when it is NE or EQ.
9286 This is because we cannot conclude anything about
9287 the value of 'SMAX (x, y)' when x is not equal to y,
9288 but we can when x equals y. */
9289 if ((code
== SMAX
|| code
== UMAX
)
9290 && ! (cond
== EQ
|| cond
== NE
))
9291 cond
= reverse_condition (cond
);
9296 return unsignedp
? x
: XEXP (x
, 1);
9298 return unsignedp
? x
: XEXP (x
, 0);
9300 return unsignedp
? XEXP (x
, 1) : x
;
9302 return unsignedp
? XEXP (x
, 0) : x
;
9309 else if (code
== SUBREG
)
9311 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9312 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9314 if (SUBREG_REG (x
) != r
)
9316 /* We must simplify subreg here, before we lose track of the
9317 original inner_mode. */
9318 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9319 inner_mode
, SUBREG_BYTE (x
));
9323 SUBST (SUBREG_REG (x
), r
);
9328 /* We don't have to handle SIGN_EXTEND here, because even in the
9329 case of replacing something with a modeless CONST_INT, a
9330 CONST_INT is already (supposed to be) a valid sign extension for
9331 its narrower mode, which implies it's already properly
9332 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9333 story is different. */
9334 else if (code
== ZERO_EXTEND
)
9336 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9337 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9339 if (XEXP (x
, 0) != r
)
9341 /* We must simplify the zero_extend here, before we lose
9342 track of the original inner_mode. */
9343 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9348 SUBST (XEXP (x
, 0), r
);
9354 fmt
= GET_RTX_FORMAT (code
);
9355 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9358 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9359 else if (fmt
[i
] == 'E')
9360 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9361 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9368 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9369 assignment as a field assignment. */
9372 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9374 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9376 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9378 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9380 /* For big endian, adjust the memory offset. */
9381 if (BYTES_BIG_ENDIAN
)
9382 x
= adjust_address_nv (x
, GET_MODE (y
),
9383 -subreg_lowpart_offset (GET_MODE (x
),
9386 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9389 if (x
== y
|| rtx_equal_p (x
, y
))
9392 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9395 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9396 Note that all SUBREGs of MEM are paradoxical; otherwise they
9397 would have been rewritten. */
9398 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9399 && MEM_P (SUBREG_REG (y
))
9400 && rtx_equal_p (SUBREG_REG (y
),
9401 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9404 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9405 && MEM_P (SUBREG_REG (x
))
9406 && rtx_equal_p (SUBREG_REG (x
),
9407 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9410 /* We used to see if get_last_value of X and Y were the same but that's
9411 not correct. In one direction, we'll cause the assignment to have
9412 the wrong destination and in the case, we'll import a register into this
9413 insn that might have already have been dead. So fail if none of the
9414 above cases are true. */
9418 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9419 Return that assignment if so.
9421 We only handle the most common cases. */
9424 make_field_assignment (rtx x
)
9426 rtx dest
= SET_DEST (x
);
9427 rtx src
= SET_SRC (x
);
9432 unsigned HOST_WIDE_INT len
;
9436 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9437 a clear of a one-bit field. We will have changed it to
9438 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9441 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9442 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9443 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9444 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9446 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9449 return gen_rtx_SET (assign
, const0_rtx
);
9453 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9454 && subreg_lowpart_p (XEXP (src
, 0))
9455 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9456 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9457 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9458 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9459 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9460 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9462 assign
= make_extraction (VOIDmode
, dest
, 0,
9463 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9466 return gen_rtx_SET (assign
, const0_rtx
);
9470 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9472 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9473 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9474 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9476 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9479 return gen_rtx_SET (assign
, const1_rtx
);
9483 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9484 SRC is an AND with all bits of that field set, then we can discard
9486 if (GET_CODE (dest
) == ZERO_EXTRACT
9487 && CONST_INT_P (XEXP (dest
, 1))
9488 && GET_CODE (src
) == AND
9489 && CONST_INT_P (XEXP (src
, 1)))
9491 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9492 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9493 unsigned HOST_WIDE_INT ze_mask
;
9495 if (width
>= HOST_BITS_PER_WIDE_INT
)
9498 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9500 /* Complete overlap. We can remove the source AND. */
9501 if ((and_mask
& ze_mask
) == ze_mask
)
9502 return gen_rtx_SET (dest
, XEXP (src
, 0));
9504 /* Partial overlap. We can reduce the source AND. */
9505 if ((and_mask
& ze_mask
) != and_mask
)
9507 mode
= GET_MODE (src
);
9508 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9509 gen_int_mode (and_mask
& ze_mask
, mode
));
9510 return gen_rtx_SET (dest
, src
);
9514 /* The other case we handle is assignments into a constant-position
9515 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9516 a mask that has all one bits except for a group of zero bits and
9517 OTHER is known to have zeros where C1 has ones, this is such an
9518 assignment. Compute the position and length from C1. Shift OTHER
9519 to the appropriate position, force it to the required mode, and
9520 make the extraction. Check for the AND in both operands. */
9522 /* One or more SUBREGs might obscure the constant-position field
9523 assignment. The first one we are likely to encounter is an outer
9524 narrowing SUBREG, which we can just strip for the purposes of
9525 identifying the constant-field assignment. */
9526 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9527 src
= SUBREG_REG (src
);
9529 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9532 rhs
= expand_compound_operation (XEXP (src
, 0));
9533 lhs
= expand_compound_operation (XEXP (src
, 1));
9535 if (GET_CODE (rhs
) == AND
9536 && CONST_INT_P (XEXP (rhs
, 1))
9537 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9538 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9539 /* The second SUBREG that might get in the way is a paradoxical
9540 SUBREG around the first operand of the AND. We want to
9541 pretend the operand is as wide as the destination here. We
9542 do this by adjusting the MEM to wider mode for the sole
9543 purpose of the call to rtx_equal_for_field_assignment_p. Also
9544 note this trick only works for MEMs. */
9545 else if (GET_CODE (rhs
) == AND
9546 && paradoxical_subreg_p (XEXP (rhs
, 0))
9547 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9548 && CONST_INT_P (XEXP (rhs
, 1))
9549 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9551 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9552 else if (GET_CODE (lhs
) == AND
9553 && CONST_INT_P (XEXP (lhs
, 1))
9554 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9555 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9556 /* The second SUBREG that might get in the way is a paradoxical
9557 SUBREG around the first operand of the AND. We want to
9558 pretend the operand is as wide as the destination here. We
9559 do this by adjusting the MEM to wider mode for the sole
9560 purpose of the call to rtx_equal_for_field_assignment_p. Also
9561 note this trick only works for MEMs. */
9562 else if (GET_CODE (lhs
) == AND
9563 && paradoxical_subreg_p (XEXP (lhs
, 0))
9564 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9565 && CONST_INT_P (XEXP (lhs
, 1))
9566 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9568 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9572 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9573 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9574 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9575 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9578 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9582 /* The mode to use for the source is the mode of the assignment, or of
9583 what is inside a possible STRICT_LOW_PART. */
9584 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9585 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9587 /* Shift OTHER right POS places and make it the source, restricting it
9588 to the proper length and mode. */
9590 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9594 src
= force_to_mode (src
, mode
,
9595 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9597 : (HOST_WIDE_INT_1U
<< len
) - 1,
9600 /* If SRC is masked by an AND that does not make a difference in
9601 the value being stored, strip it. */
9602 if (GET_CODE (assign
) == ZERO_EXTRACT
9603 && CONST_INT_P (XEXP (assign
, 1))
9604 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9605 && GET_CODE (src
) == AND
9606 && CONST_INT_P (XEXP (src
, 1))
9607 && UINTVAL (XEXP (src
, 1))
9608 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9609 src
= XEXP (src
, 0);
9611 return gen_rtx_SET (assign
, src
);
9614 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9618 apply_distributive_law (rtx x
)
9620 enum rtx_code code
= GET_CODE (x
);
9621 enum rtx_code inner_code
;
9622 rtx lhs
, rhs
, other
;
9625 /* Distributivity is not true for floating point as it can change the
9626 value. So we don't do it unless -funsafe-math-optimizations. */
9627 if (FLOAT_MODE_P (GET_MODE (x
))
9628 && ! flag_unsafe_math_optimizations
)
9631 /* The outer operation can only be one of the following: */
9632 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9633 && code
!= PLUS
&& code
!= MINUS
)
9639 /* If either operand is a primitive we can't do anything, so get out
9641 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9644 lhs
= expand_compound_operation (lhs
);
9645 rhs
= expand_compound_operation (rhs
);
9646 inner_code
= GET_CODE (lhs
);
9647 if (inner_code
!= GET_CODE (rhs
))
9650 /* See if the inner and outer operations distribute. */
9657 /* These all distribute except over PLUS. */
9658 if (code
== PLUS
|| code
== MINUS
)
9663 if (code
!= PLUS
&& code
!= MINUS
)
9668 /* This is also a multiply, so it distributes over everything. */
9671 /* This used to handle SUBREG, but this turned out to be counter-
9672 productive, since (subreg (op ...)) usually is not handled by
9673 insn patterns, and this "optimization" therefore transformed
9674 recognizable patterns into unrecognizable ones. Therefore the
9675 SUBREG case was removed from here.
9677 It is possible that distributing SUBREG over arithmetic operations
9678 leads to an intermediate result than can then be optimized further,
9679 e.g. by moving the outer SUBREG to the other side of a SET as done
9680 in simplify_set. This seems to have been the original intent of
9681 handling SUBREGs here.
9683 However, with current GCC this does not appear to actually happen,
9684 at least on major platforms. If some case is found where removing
9685 the SUBREG case here prevents follow-on optimizations, distributing
9686 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9692 /* Set LHS and RHS to the inner operands (A and B in the example
9693 above) and set OTHER to the common operand (C in the example).
9694 There is only one way to do this unless the inner operation is
9696 if (COMMUTATIVE_ARITH_P (lhs
)
9697 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9698 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9699 else if (COMMUTATIVE_ARITH_P (lhs
)
9700 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9701 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9702 else if (COMMUTATIVE_ARITH_P (lhs
)
9703 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9704 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9705 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9706 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9710 /* Form the new inner operation, seeing if it simplifies first. */
9711 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9713 /* There is one exception to the general way of distributing:
9714 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9715 if (code
== XOR
&& inner_code
== IOR
)
9718 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9721 /* We may be able to continuing distributing the result, so call
9722 ourselves recursively on the inner operation before forming the
9723 outer operation, which we return. */
9724 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9725 apply_distributive_law (tem
), other
);
9728 /* See if X is of the form (* (+ A B) C), and if so convert to
9729 (+ (* A C) (* B C)) and try to simplify.
9731 Most of the time, this results in no change. However, if some of
9732 the operands are the same or inverses of each other, simplifications
9735 For example, (and (ior A B) (not B)) can occur as the result of
9736 expanding a bit field assignment. When we apply the distributive
9737 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9738 which then simplifies to (and (A (not B))).
9740 Note that no checks happen on the validity of applying the inverse
9741 distributive law. This is pointless since we can do it in the
9742 few places where this routine is called.
9744 N is the index of the term that is decomposed (the arithmetic operation,
9745 i.e. (+ A B) in the first example above). !N is the index of the term that
9746 is distributed, i.e. of C in the first example above. */
9748 distribute_and_simplify_rtx (rtx x
, int n
)
9751 enum rtx_code outer_code
, inner_code
;
9752 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9754 /* Distributivity is not true for floating point as it can change the
9755 value. So we don't do it unless -funsafe-math-optimizations. */
9756 if (FLOAT_MODE_P (GET_MODE (x
))
9757 && ! flag_unsafe_math_optimizations
)
9760 decomposed
= XEXP (x
, n
);
9761 if (!ARITHMETIC_P (decomposed
))
9764 mode
= GET_MODE (x
);
9765 outer_code
= GET_CODE (x
);
9766 distributed
= XEXP (x
, !n
);
9768 inner_code
= GET_CODE (decomposed
);
9769 inner_op0
= XEXP (decomposed
, 0);
9770 inner_op1
= XEXP (decomposed
, 1);
9772 /* Special case (and (xor B C) (not A)), which is equivalent to
9773 (xor (ior A B) (ior A C)) */
9774 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9776 distributed
= XEXP (distributed
, 0);
9782 /* Distribute the second term. */
9783 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9784 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9788 /* Distribute the first term. */
9789 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9790 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9793 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9795 if (GET_CODE (tmp
) != outer_code
9796 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9797 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9803 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9804 in MODE. Return an equivalent form, if different from (and VAROP
9805 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9808 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9809 unsigned HOST_WIDE_INT constop
)
9811 unsigned HOST_WIDE_INT nonzero
;
9812 unsigned HOST_WIDE_INT orig_constop
;
9817 orig_constop
= constop
;
9818 if (GET_CODE (varop
) == CLOBBER
)
9821 /* Simplify VAROP knowing that we will be only looking at some of the
9824 Note by passing in CONSTOP, we guarantee that the bits not set in
9825 CONSTOP are not significant and will never be examined. We must
9826 ensure that is the case by explicitly masking out those bits
9827 before returning. */
9828 varop
= force_to_mode (varop
, mode
, constop
, 0);
9830 /* If VAROP is a CLOBBER, we will fail so return it. */
9831 if (GET_CODE (varop
) == CLOBBER
)
9834 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9835 to VAROP and return the new constant. */
9836 if (CONST_INT_P (varop
))
9837 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9839 /* See what bits may be nonzero in VAROP. Unlike the general case of
9840 a call to nonzero_bits, here we don't care about bits outside
9843 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9845 /* Turn off all bits in the constant that are known to already be zero.
9846 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9847 which is tested below. */
9851 /* If we don't have any bits left, return zero. */
9855 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9856 a power of two, we can replace this with an ASHIFT. */
9857 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9858 && (i
= exact_log2 (constop
)) >= 0)
9859 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9861 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9862 or XOR, then try to apply the distributive law. This may eliminate
9863 operations if either branch can be simplified because of the AND.
9864 It may also make some cases more complex, but those cases probably
9865 won't match a pattern either with or without this. */
9867 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9871 apply_distributive_law
9872 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9873 simplify_and_const_int (NULL_RTX
,
9877 simplify_and_const_int (NULL_RTX
,
9882 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9883 the AND and see if one of the operands simplifies to zero. If so, we
9884 may eliminate it. */
9886 if (GET_CODE (varop
) == PLUS
9887 && pow2p_hwi (constop
+ 1))
9891 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9892 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9893 if (o0
== const0_rtx
)
9895 if (o1
== const0_rtx
)
9899 /* Make a SUBREG if necessary. If we can't make it, fail. */
9900 varop
= gen_lowpart (mode
, varop
);
9901 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9904 /* If we are only masking insignificant bits, return VAROP. */
9905 if (constop
== nonzero
)
9908 if (varop
== orig_varop
&& constop
== orig_constop
)
9911 /* Otherwise, return an AND. */
9912 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9916 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9919 Return an equivalent form, if different from X. Otherwise, return X. If
9920 X is zero, we are to always construct the equivalent form. */
9923 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9924 unsigned HOST_WIDE_INT constop
)
9926 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9931 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9932 gen_int_mode (constop
, mode
));
9933 if (GET_MODE (x
) != mode
)
9934 x
= gen_lowpart (mode
, x
);
9938 /* Given a REG, X, compute which bits in X can be nonzero.
9939 We don't care about bits outside of those defined in MODE.
9941 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9942 a shift, AND, or zero_extract, we can do better. */
9945 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9946 const_rtx known_x ATTRIBUTE_UNUSED
,
9947 machine_mode known_mode ATTRIBUTE_UNUSED
,
9948 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9949 unsigned HOST_WIDE_INT
*nonzero
)
9954 /* If X is a register whose nonzero bits value is current, use it.
9955 Otherwise, if X is a register whose value we can find, use that
9956 value. Otherwise, use the previously-computed global nonzero bits
9957 for this register. */
9959 rsp
= ®_stat
[REGNO (x
)];
9960 if (rsp
->last_set_value
!= 0
9961 && (rsp
->last_set_mode
== mode
9962 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9963 && GET_MODE_CLASS (mode
) == MODE_INT
))
9964 && ((rsp
->last_set_label
>= label_tick_ebb_start
9965 && rsp
->last_set_label
< label_tick
)
9966 || (rsp
->last_set_label
== label_tick
9967 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9968 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9969 && REGNO (x
) < reg_n_sets_max
9970 && REG_N_SETS (REGNO (x
)) == 1
9972 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9975 /* Note that, even if the precision of last_set_mode is lower than that
9976 of mode, record_value_for_reg invoked nonzero_bits on the register
9977 with nonzero_bits_mode (because last_set_mode is necessarily integral
9978 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
9979 are all valid, hence in mode too since nonzero_bits_mode is defined
9980 to the largest HWI_COMPUTABLE_MODE_P mode. */
9981 *nonzero
&= rsp
->last_set_nonzero_bits
;
9985 tem
= get_last_value (x
);
9988 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
9989 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9990 GET_MODE_PRECISION (mode
));
9995 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9997 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9999 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
10000 /* We don't know anything about the upper bits. */
10001 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
10009 /* Return the number of bits at the high-order end of X that are known to
10010 be equal to the sign bit. X will be used in mode MODE; if MODE is
10011 VOIDmode, X will be used in its own mode. The returned value will always
10012 be between 1 and the number of bits in MODE. */
10015 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
10016 const_rtx known_x ATTRIBUTE_UNUSED
,
10017 machine_mode known_mode
10019 unsigned int known_ret ATTRIBUTE_UNUSED
,
10020 unsigned int *result
)
10023 reg_stat_type
*rsp
;
10025 rsp
= ®_stat
[REGNO (x
)];
10026 if (rsp
->last_set_value
!= 0
10027 && rsp
->last_set_mode
== mode
10028 && ((rsp
->last_set_label
>= label_tick_ebb_start
10029 && rsp
->last_set_label
< label_tick
)
10030 || (rsp
->last_set_label
== label_tick
10031 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10032 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10033 && REGNO (x
) < reg_n_sets_max
10034 && REG_N_SETS (REGNO (x
)) == 1
10035 && !REGNO_REG_SET_P
10036 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10039 *result
= rsp
->last_set_sign_bit_copies
;
10043 tem
= get_last_value (x
);
10047 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10048 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
10049 *result
= rsp
->sign_bit_copies
;
10054 /* Return the number of "extended" bits there are in X, when interpreted
10055 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10056 unsigned quantities, this is the number of high-order zero bits.
10057 For signed quantities, this is the number of copies of the sign bit
10058 minus 1. In both case, this function returns the number of "spare"
10059 bits. For example, if two quantities for which this function returns
10060 at least 1 are added, the addition is known not to overflow.
10062 This function will always return 0 unless called during combine, which
10063 implies that it must be called from a define_split. */
10066 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10068 if (nonzero_sign_valid
== 0)
10072 ? (HWI_COMPUTABLE_MODE_P (mode
)
10073 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
10074 - floor_log2 (nonzero_bits (x
, mode
)))
10076 : num_sign_bit_copies (x
, mode
) - 1);
10079 /* This function is called from `simplify_shift_const' to merge two
10080 outer operations. Specifically, we have already found that we need
10081 to perform operation *POP0 with constant *PCONST0 at the outermost
10082 position. We would now like to also perform OP1 with constant CONST1
10083 (with *POP0 being done last).
10085 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10086 the resulting operation. *PCOMP_P is set to 1 if we would need to
10087 complement the innermost operand, otherwise it is unchanged.
10089 MODE is the mode in which the operation will be done. No bits outside
10090 the width of this mode matter. It is assumed that the width of this mode
10091 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10093 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10094 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10095 result is simply *PCONST0.
10097 If the resulting operation cannot be expressed as one operation, we
10098 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10101 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10103 enum rtx_code op0
= *pop0
;
10104 HOST_WIDE_INT const0
= *pconst0
;
10106 const0
&= GET_MODE_MASK (mode
);
10107 const1
&= GET_MODE_MASK (mode
);
10109 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10113 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10116 if (op1
== UNKNOWN
|| op0
== SET
)
10119 else if (op0
== UNKNOWN
)
10120 op0
= op1
, const0
= const1
;
10122 else if (op0
== op1
)
10146 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10147 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10150 /* If the two constants aren't the same, we can't do anything. The
10151 remaining six cases can all be done. */
10152 else if (const0
!= const1
)
10160 /* (a & b) | b == b */
10162 else /* op1 == XOR */
10163 /* (a ^ b) | b == a | b */
10169 /* (a & b) ^ b == (~a) & b */
10170 op0
= AND
, *pcomp_p
= 1;
10171 else /* op1 == IOR */
10172 /* (a | b) ^ b == a & ~b */
10173 op0
= AND
, const0
= ~const0
;
10178 /* (a | b) & b == b */
10180 else /* op1 == XOR */
10181 /* (a ^ b) & b) == (~a) & b */
10188 /* Check for NO-OP cases. */
10189 const0
&= GET_MODE_MASK (mode
);
10191 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10193 else if (const0
== 0 && op0
== AND
)
10195 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10201 /* ??? Slightly redundant with the above mask, but not entirely.
10202 Moving this above means we'd have to sign-extend the mode mask
10203 for the final test. */
10204 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10205 *pconst0
= trunc_int_for_mode (const0
, mode
);
10210 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10211 the shift in. The original shift operation CODE is performed on OP in
10212 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10213 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10214 result of the shift is subject to operation OUTER_CODE with operand
10217 static machine_mode
10218 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10219 machine_mode orig_mode
, machine_mode mode
,
10220 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10222 if (orig_mode
== mode
)
10224 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10226 /* In general we can't perform in wider mode for right shift and rotate. */
10230 /* We can still widen if the bits brought in from the left are identical
10231 to the sign bit of ORIG_MODE. */
10232 if (num_sign_bit_copies (op
, mode
)
10233 > (unsigned) (GET_MODE_PRECISION (mode
)
10234 - GET_MODE_PRECISION (orig_mode
)))
10239 /* Similarly here but with zero bits. */
10240 if (HWI_COMPUTABLE_MODE_P (mode
)
10241 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10244 /* We can also widen if the bits brought in will be masked off. This
10245 operation is performed in ORIG_MODE. */
10246 if (outer_code
== AND
)
10248 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10251 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10260 gcc_unreachable ();
10267 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10268 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10269 if we cannot simplify it. Otherwise, return a simplified value.
10271 The shift is normally computed in the widest mode we find in VAROP, as
10272 long as it isn't a different number of words than RESULT_MODE. Exceptions
10273 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10276 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10277 rtx varop
, int orig_count
)
10279 enum rtx_code orig_code
= code
;
10280 rtx orig_varop
= varop
;
10282 machine_mode mode
= result_mode
;
10283 machine_mode shift_mode
, tmode
;
10284 unsigned int mode_words
10285 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10286 /* We form (outer_op (code varop count) (outer_const)). */
10287 enum rtx_code outer_op
= UNKNOWN
;
10288 HOST_WIDE_INT outer_const
= 0;
10289 int complement_p
= 0;
10292 /* Make sure and truncate the "natural" shift on the way in. We don't
10293 want to do this inside the loop as it makes it more difficult to
10295 if (SHIFT_COUNT_TRUNCATED
)
10296 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10298 /* If we were given an invalid count, don't do anything except exactly
10299 what was requested. */
10301 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10304 count
= orig_count
;
10306 /* Unless one of the branches of the `if' in this loop does a `continue',
10307 we will `break' the loop after the `if'. */
10311 /* If we have an operand of (clobber (const_int 0)), fail. */
10312 if (GET_CODE (varop
) == CLOBBER
)
10315 /* Convert ROTATERT to ROTATE. */
10316 if (code
== ROTATERT
)
10318 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10320 count
= bitsize
- count
;
10323 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10324 mode
, outer_op
, outer_const
);
10325 machine_mode shift_unit_mode
= GET_MODE_INNER (shift_mode
);
10327 /* Handle cases where the count is greater than the size of the mode
10328 minus 1. For ASHIFT, use the size minus one as the count (this can
10329 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10330 take the count modulo the size. For other shifts, the result is
10333 Since these shifts are being produced by the compiler by combining
10334 multiple operations, each of which are defined, we know what the
10335 result is supposed to be. */
10337 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10339 if (code
== ASHIFTRT
)
10340 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10341 else if (code
== ROTATE
|| code
== ROTATERT
)
10342 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10345 /* We can't simply return zero because there may be an
10347 varop
= const0_rtx
;
10353 /* If we discovered we had to complement VAROP, leave. Making a NOT
10354 here would cause an infinite loop. */
10358 if (shift_mode
== shift_unit_mode
)
10360 /* An arithmetic right shift of a quantity known to be -1 or 0
10362 if (code
== ASHIFTRT
10363 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10364 == GET_MODE_PRECISION (shift_unit_mode
)))
10370 /* If we are doing an arithmetic right shift and discarding all but
10371 the sign bit copies, this is equivalent to doing a shift by the
10372 bitsize minus one. Convert it into that shift because it will
10373 often allow other simplifications. */
10375 if (code
== ASHIFTRT
10376 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10377 >= GET_MODE_PRECISION (shift_unit_mode
)))
10378 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10380 /* We simplify the tests below and elsewhere by converting
10381 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10382 `make_compound_operation' will convert it to an ASHIFTRT for
10383 those machines (such as VAX) that don't have an LSHIFTRT. */
10384 if (code
== ASHIFTRT
10385 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10386 && val_signbit_known_clear_p (shift_unit_mode
,
10387 nonzero_bits (varop
,
10391 if (((code
== LSHIFTRT
10392 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10393 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10395 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10396 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10397 & GET_MODE_MASK (shift_unit_mode
))))
10398 && !side_effects_p (varop
))
10399 varop
= const0_rtx
;
10402 switch (GET_CODE (varop
))
10408 new_rtx
= expand_compound_operation (varop
);
10409 if (new_rtx
!= varop
)
10417 /* The following rules apply only to scalars. */
10418 if (shift_mode
!= shift_unit_mode
)
10421 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10422 minus the width of a smaller mode, we can do this with a
10423 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10424 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10425 && ! mode_dependent_address_p (XEXP (varop
, 0),
10426 MEM_ADDR_SPACE (varop
))
10427 && ! MEM_VOLATILE_P (varop
)
10428 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10429 MODE_INT
, 1)) != BLKmode
)
10431 new_rtx
= adjust_address_nv (varop
, tmode
,
10432 BYTES_BIG_ENDIAN
? 0
10433 : count
/ BITS_PER_UNIT
);
10435 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10436 : ZERO_EXTEND
, mode
, new_rtx
);
10443 /* The following rules apply only to scalars. */
10444 if (shift_mode
!= shift_unit_mode
)
10447 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10448 the same number of words as what we've seen so far. Then store
10449 the widest mode in MODE. */
10450 if (subreg_lowpart_p (varop
)
10451 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10452 > GET_MODE_SIZE (GET_MODE (varop
)))
10453 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10454 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10456 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10457 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10459 varop
= SUBREG_REG (varop
);
10460 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10461 mode
= GET_MODE (varop
);
10467 /* Some machines use MULT instead of ASHIFT because MULT
10468 is cheaper. But it is still better on those machines to
10469 merge two shifts into one. */
10470 if (CONST_INT_P (XEXP (varop
, 1))
10471 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10474 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10476 GEN_INT (exact_log2 (
10477 UINTVAL (XEXP (varop
, 1)))));
10483 /* Similar, for when divides are cheaper. */
10484 if (CONST_INT_P (XEXP (varop
, 1))
10485 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10488 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10490 GEN_INT (exact_log2 (
10491 UINTVAL (XEXP (varop
, 1)))));
10497 /* If we are extracting just the sign bit of an arithmetic
10498 right shift, that shift is not needed. However, the sign
10499 bit of a wider mode may be different from what would be
10500 interpreted as the sign bit in a narrower mode, so, if
10501 the result is narrower, don't discard the shift. */
10502 if (code
== LSHIFTRT
10503 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10504 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10505 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10507 varop
= XEXP (varop
, 0);
10516 /* The following rules apply only to scalars. */
10517 if (shift_mode
!= shift_unit_mode
)
10520 /* Here we have two nested shifts. The result is usually the
10521 AND of a new shift with a mask. We compute the result below. */
10522 if (CONST_INT_P (XEXP (varop
, 1))
10523 && INTVAL (XEXP (varop
, 1)) >= 0
10524 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10525 && HWI_COMPUTABLE_MODE_P (result_mode
)
10526 && HWI_COMPUTABLE_MODE_P (mode
))
10528 enum rtx_code first_code
= GET_CODE (varop
);
10529 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10530 unsigned HOST_WIDE_INT mask
;
10533 /* We have one common special case. We can't do any merging if
10534 the inner code is an ASHIFTRT of a smaller mode. However, if
10535 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10536 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10537 we can convert it to
10538 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10539 This simplifies certain SIGN_EXTEND operations. */
10540 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10541 && count
== (GET_MODE_PRECISION (result_mode
)
10542 - GET_MODE_PRECISION (GET_MODE (varop
))))
10544 /* C3 has the low-order C1 bits zero. */
10546 mask
= GET_MODE_MASK (mode
)
10547 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10549 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10550 XEXP (varop
, 0), mask
);
10551 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10553 count
= first_count
;
10558 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10559 than C1 high-order bits equal to the sign bit, we can convert
10560 this to either an ASHIFT or an ASHIFTRT depending on the
10563 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10565 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10566 && GET_MODE (varop
) == shift_mode
10567 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10570 varop
= XEXP (varop
, 0);
10571 count
-= first_count
;
10581 /* There are some cases we can't do. If CODE is ASHIFTRT,
10582 we can only do this if FIRST_CODE is also ASHIFTRT.
10584 We can't do the case when CODE is ROTATE and FIRST_CODE is
10587 If the mode of this shift is not the mode of the outer shift,
10588 we can't do this if either shift is a right shift or ROTATE.
10590 Finally, we can't do any of these if the mode is too wide
10591 unless the codes are the same.
10593 Handle the case where the shift codes are the same
10596 if (code
== first_code
)
10598 if (GET_MODE (varop
) != result_mode
10599 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10600 || code
== ROTATE
))
10603 count
+= first_count
;
10604 varop
= XEXP (varop
, 0);
10608 if (code
== ASHIFTRT
10609 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10610 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10611 || (GET_MODE (varop
) != result_mode
10612 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10613 || first_code
== ROTATE
10614 || code
== ROTATE
)))
10617 /* To compute the mask to apply after the shift, shift the
10618 nonzero bits of the inner shift the same way the
10619 outer shift will. */
10621 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10625 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10628 /* Give up if we can't compute an outer operation to use. */
10630 || !CONST_INT_P (mask_rtx
)
10631 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10633 result_mode
, &complement_p
))
10636 /* If the shifts are in the same direction, we add the
10637 counts. Otherwise, we subtract them. */
10638 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10639 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10640 count
+= first_count
;
10642 count
-= first_count
;
10644 /* If COUNT is positive, the new shift is usually CODE,
10645 except for the two exceptions below, in which case it is
10646 FIRST_CODE. If the count is negative, FIRST_CODE should
10649 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10650 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10652 else if (count
< 0)
10653 code
= first_code
, count
= -count
;
10655 varop
= XEXP (varop
, 0);
10659 /* If we have (A << B << C) for any shift, we can convert this to
10660 (A << C << B). This wins if A is a constant. Only try this if
10661 B is not a constant. */
10663 else if (GET_CODE (varop
) == code
10664 && CONST_INT_P (XEXP (varop
, 0))
10665 && !CONST_INT_P (XEXP (varop
, 1)))
10667 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10668 sure the result will be masked. See PR70222. */
10669 if (code
== LSHIFTRT
10670 && mode
!= result_mode
10671 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10672 GET_MODE_MASK (result_mode
)
10673 >> orig_count
, result_mode
,
10676 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10677 up outer sign extension (often left and right shift) is
10678 hardly more efficient than the original. See PR70429. */
10679 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10682 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10685 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10692 /* The following rules apply only to scalars. */
10693 if (shift_mode
!= shift_unit_mode
)
10696 /* Make this fit the case below. */
10697 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10703 /* The following rules apply only to scalars. */
10704 if (shift_mode
!= shift_unit_mode
)
10707 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10708 with C the size of VAROP - 1 and the shift is logical if
10709 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10710 we have an (le X 0) operation. If we have an arithmetic shift
10711 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10712 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10714 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10715 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10716 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10717 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10718 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10719 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10722 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10725 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10726 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10731 /* If we have (shift (logical)), move the logical to the outside
10732 to allow it to possibly combine with another logical and the
10733 shift to combine with another shift. This also canonicalizes to
10734 what a ZERO_EXTRACT looks like. Also, some machines have
10735 (and (shift)) insns. */
10737 if (CONST_INT_P (XEXP (varop
, 1))
10738 /* We can't do this if we have (ashiftrt (xor)) and the
10739 constant has its sign bit set in shift_mode with shift_mode
10740 wider than result_mode. */
10741 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10742 && result_mode
!= shift_mode
10743 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10745 && (new_rtx
= simplify_const_binary_operation
10746 (code
, result_mode
,
10747 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10748 GEN_INT (count
))) != 0
10749 && CONST_INT_P (new_rtx
)
10750 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10751 INTVAL (new_rtx
), result_mode
, &complement_p
))
10753 varop
= XEXP (varop
, 0);
10757 /* If we can't do that, try to simplify the shift in each arm of the
10758 logical expression, make a new logical expression, and apply
10759 the inverse distributive law. This also can't be done for
10760 (ashiftrt (xor)) where we've widened the shift and the constant
10761 changes the sign bit. */
10762 if (CONST_INT_P (XEXP (varop
, 1))
10763 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10764 && result_mode
!= shift_mode
10765 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10768 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10769 XEXP (varop
, 0), count
);
10770 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10771 XEXP (varop
, 1), count
);
10773 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10775 varop
= apply_distributive_law (varop
);
10783 /* The following rules apply only to scalars. */
10784 if (shift_mode
!= shift_unit_mode
)
10787 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10788 says that the sign bit can be tested, FOO has mode MODE, C is
10789 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10790 that may be nonzero. */
10791 if (code
== LSHIFTRT
10792 && XEXP (varop
, 1) == const0_rtx
10793 && GET_MODE (XEXP (varop
, 0)) == result_mode
10794 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10795 && HWI_COMPUTABLE_MODE_P (result_mode
)
10796 && STORE_FLAG_VALUE
== -1
10797 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10798 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10801 varop
= XEXP (varop
, 0);
10808 /* The following rules apply only to scalars. */
10809 if (shift_mode
!= shift_unit_mode
)
10812 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10813 than the number of bits in the mode is equivalent to A. */
10814 if (code
== LSHIFTRT
10815 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10816 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10818 varop
= XEXP (varop
, 0);
10823 /* NEG commutes with ASHIFT since it is multiplication. Move the
10824 NEG outside to allow shifts to combine. */
10826 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10829 varop
= XEXP (varop
, 0);
10835 /* The following rules apply only to scalars. */
10836 if (shift_mode
!= shift_unit_mode
)
10839 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10840 is one less than the number of bits in the mode is
10841 equivalent to (xor A 1). */
10842 if (code
== LSHIFTRT
10843 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10844 && XEXP (varop
, 1) == constm1_rtx
10845 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10846 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10850 varop
= XEXP (varop
, 0);
10854 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10855 that might be nonzero in BAR are those being shifted out and those
10856 bits are known zero in FOO, we can replace the PLUS with FOO.
10857 Similarly in the other operand order. This code occurs when
10858 we are computing the size of a variable-size array. */
10860 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10861 && count
< HOST_BITS_PER_WIDE_INT
10862 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10863 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10864 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10866 varop
= XEXP (varop
, 0);
10869 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10870 && count
< HOST_BITS_PER_WIDE_INT
10871 && HWI_COMPUTABLE_MODE_P (result_mode
)
10872 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10874 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10875 & nonzero_bits (XEXP (varop
, 1),
10878 varop
= XEXP (varop
, 1);
10882 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10884 && CONST_INT_P (XEXP (varop
, 1))
10885 && (new_rtx
= simplify_const_binary_operation
10886 (ASHIFT
, result_mode
,
10887 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10888 GEN_INT (count
))) != 0
10889 && CONST_INT_P (new_rtx
)
10890 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10891 INTVAL (new_rtx
), result_mode
, &complement_p
))
10893 varop
= XEXP (varop
, 0);
10897 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10898 signbit', and attempt to change the PLUS to an XOR and move it to
10899 the outer operation as is done above in the AND/IOR/XOR case
10900 leg for shift(logical). See details in logical handling above
10901 for reasoning in doing so. */
10902 if (code
== LSHIFTRT
10903 && CONST_INT_P (XEXP (varop
, 1))
10904 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10905 && (new_rtx
= simplify_const_binary_operation
10906 (code
, result_mode
,
10907 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10908 GEN_INT (count
))) != 0
10909 && CONST_INT_P (new_rtx
)
10910 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10911 INTVAL (new_rtx
), result_mode
, &complement_p
))
10913 varop
= XEXP (varop
, 0);
10920 /* The following rules apply only to scalars. */
10921 if (shift_mode
!= shift_unit_mode
)
10924 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10925 with C the size of VAROP - 1 and the shift is logical if
10926 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10927 we have a (gt X 0) operation. If the shift is arithmetic with
10928 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10929 we have a (neg (gt X 0)) operation. */
10931 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10932 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10933 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10934 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10935 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10936 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10937 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10940 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10943 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10944 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10951 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10952 if the truncate does not affect the value. */
10953 if (code
== LSHIFTRT
10954 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10955 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10956 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10957 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
10958 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
10960 rtx varop_inner
= XEXP (varop
, 0);
10963 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10964 XEXP (varop_inner
, 0),
10966 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10967 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10980 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10981 outer_op
, outer_const
);
10983 /* We have now finished analyzing the shift. The result should be
10984 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10985 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10986 to the result of the shift. OUTER_CONST is the relevant constant,
10987 but we must turn off all bits turned off in the shift. */
10989 if (outer_op
== UNKNOWN
10990 && orig_code
== code
&& orig_count
== count
10991 && varop
== orig_varop
10992 && shift_mode
== GET_MODE (varop
))
10995 /* Make a SUBREG if necessary. If we can't make it, fail. */
10996 varop
= gen_lowpart (shift_mode
, varop
);
10997 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11000 /* If we have an outer operation and we just made a shift, it is
11001 possible that we could have simplified the shift were it not
11002 for the outer operation. So try to do the simplification
11005 if (outer_op
!= UNKNOWN
)
11006 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11011 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11013 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11014 turn off all the bits that the shift would have turned off. */
11015 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11016 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
11017 GET_MODE_MASK (result_mode
) >> orig_count
);
11019 /* Do the remainder of the processing in RESULT_MODE. */
11020 x
= gen_lowpart_or_truncate (result_mode
, x
);
11022 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11025 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11027 if (outer_op
!= UNKNOWN
)
11029 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11030 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
11031 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
11033 if (outer_op
== AND
)
11034 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
11035 else if (outer_op
== SET
)
11037 /* This means that we have determined that the result is
11038 equivalent to a constant. This should be rare. */
11039 if (!side_effects_p (x
))
11040 x
= GEN_INT (outer_const
);
11042 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11043 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
11045 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
11046 GEN_INT (outer_const
));
11052 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11053 The result of the shift is RESULT_MODE. If we cannot simplify it,
11054 return X or, if it is NULL, synthesize the expression with
11055 simplify_gen_binary. Otherwise, return a simplified value.
11057 The shift is normally computed in the widest mode we find in VAROP, as
11058 long as it isn't a different number of words than RESULT_MODE. Exceptions
11059 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11062 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11063 rtx varop
, int count
)
11065 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11070 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11071 if (GET_MODE (x
) != result_mode
)
11072 x
= gen_lowpart (result_mode
, x
);
11077 /* A subroutine of recog_for_combine. See there for arguments and
11081 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11083 rtx pat
= *pnewpat
;
11084 rtx pat_without_clobbers
;
11085 int insn_code_number
;
11086 int num_clobbers_to_add
= 0;
11088 rtx notes
= NULL_RTX
;
11089 rtx old_notes
, old_pat
;
11092 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11093 we use to indicate that something didn't match. If we find such a
11094 thing, force rejection. */
11095 if (GET_CODE (pat
) == PARALLEL
)
11096 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11097 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11098 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11101 old_pat
= PATTERN (insn
);
11102 old_notes
= REG_NOTES (insn
);
11103 PATTERN (insn
) = pat
;
11104 REG_NOTES (insn
) = NULL_RTX
;
11106 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11107 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11109 if (insn_code_number
< 0)
11110 fputs ("Failed to match this instruction:\n", dump_file
);
11112 fputs ("Successfully matched this instruction:\n", dump_file
);
11113 print_rtl_single (dump_file
, pat
);
11116 /* If it isn't, there is the possibility that we previously had an insn
11117 that clobbered some register as a side effect, but the combined
11118 insn doesn't need to do that. So try once more without the clobbers
11119 unless this represents an ASM insn. */
11121 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11122 && GET_CODE (pat
) == PARALLEL
)
11126 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11127 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11130 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11134 SUBST_INT (XVECLEN (pat
, 0), pos
);
11137 pat
= XVECEXP (pat
, 0, 0);
11139 PATTERN (insn
) = pat
;
11140 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11141 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11143 if (insn_code_number
< 0)
11144 fputs ("Failed to match this instruction:\n", dump_file
);
11146 fputs ("Successfully matched this instruction:\n", dump_file
);
11147 print_rtl_single (dump_file
, pat
);
11151 pat_without_clobbers
= pat
;
11153 PATTERN (insn
) = old_pat
;
11154 REG_NOTES (insn
) = old_notes
;
11156 /* Recognize all noop sets, these will be killed by followup pass. */
11157 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11158 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11160 /* If we had any clobbers to add, make a new pattern than contains
11161 them. Then check to make sure that all of them are dead. */
11162 if (num_clobbers_to_add
)
11164 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11165 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11166 ? (XVECLEN (pat
, 0)
11167 + num_clobbers_to_add
)
11168 : num_clobbers_to_add
+ 1));
11170 if (GET_CODE (pat
) == PARALLEL
)
11171 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11172 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11174 XVECEXP (newpat
, 0, 0) = pat
;
11176 add_clobbers (newpat
, insn_code_number
);
11178 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11179 i
< XVECLEN (newpat
, 0); i
++)
11181 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11182 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11184 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11186 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11187 notes
= alloc_reg_note (REG_UNUSED
,
11188 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11194 if (insn_code_number
>= 0
11195 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11197 old_pat
= PATTERN (insn
);
11198 old_notes
= REG_NOTES (insn
);
11199 old_icode
= INSN_CODE (insn
);
11200 PATTERN (insn
) = pat
;
11201 REG_NOTES (insn
) = notes
;
11203 /* Allow targets to reject combined insn. */
11204 if (!targetm
.legitimate_combined_insn (insn
))
11206 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11207 fputs ("Instruction not appropriate for target.",
11210 /* Callers expect recog_for_combine to strip
11211 clobbers from the pattern on failure. */
11212 pat
= pat_without_clobbers
;
11215 insn_code_number
= -1;
11218 PATTERN (insn
) = old_pat
;
11219 REG_NOTES (insn
) = old_notes
;
11220 INSN_CODE (insn
) = old_icode
;
11226 return insn_code_number
;
11229 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11230 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11231 Return whether anything was so changed. */
11234 change_zero_ext (rtx pat
)
11236 bool changed
= false;
11237 rtx
*src
= &SET_SRC (pat
);
11239 subrtx_ptr_iterator::array_type array
;
11240 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11243 machine_mode mode
= GET_MODE (x
);
11246 if (GET_CODE (x
) == ZERO_EXTRACT
11247 && CONST_INT_P (XEXP (x
, 1))
11248 && CONST_INT_P (XEXP (x
, 2))
11249 && GET_MODE (XEXP (x
, 0)) != VOIDmode
11250 && GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
11251 <= GET_MODE_PRECISION (mode
))
11253 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
11255 size
= INTVAL (XEXP (x
, 1));
11257 int start
= INTVAL (XEXP (x
, 2));
11258 if (BITS_BIG_ENDIAN
)
11259 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11262 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11265 if (mode
!= inner_mode
)
11266 x
= gen_lowpart_SUBREG (mode
, x
);
11268 else if (GET_CODE (x
) == ZERO_EXTEND
11269 && SCALAR_INT_MODE_P (mode
)
11270 && GET_CODE (XEXP (x
, 0)) == SUBREG
11271 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11272 && !paradoxical_subreg_p (XEXP (x
, 0))
11273 && subreg_lowpart_p (XEXP (x
, 0)))
11275 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11276 x
= SUBREG_REG (XEXP (x
, 0));
11277 if (GET_MODE (x
) != mode
)
11278 x
= gen_lowpart_SUBREG (mode
, x
);
11280 else if (GET_CODE (x
) == ZERO_EXTEND
11281 && SCALAR_INT_MODE_P (mode
)
11282 && REG_P (XEXP (x
, 0))
11283 && HARD_REGISTER_P (XEXP (x
, 0))
11284 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11286 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11287 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11292 if (!(GET_CODE (x
) == LSHIFTRT
11293 && CONST_INT_P (XEXP (x
, 1))
11294 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11296 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11297 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11305 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11306 maybe_swap_commutative_operands (**iter
);
11308 rtx
*dst
= &SET_DEST (pat
);
11309 if (GET_CODE (*dst
) == ZERO_EXTRACT
11310 && REG_P (XEXP (*dst
, 0))
11311 && CONST_INT_P (XEXP (*dst
, 1))
11312 && CONST_INT_P (XEXP (*dst
, 2)))
11314 rtx reg
= XEXP (*dst
, 0);
11315 int width
= INTVAL (XEXP (*dst
, 1));
11316 int offset
= INTVAL (XEXP (*dst
, 2));
11317 machine_mode mode
= GET_MODE (reg
);
11318 int reg_width
= GET_MODE_PRECISION (mode
);
11319 if (BITS_BIG_ENDIAN
)
11320 offset
= reg_width
- width
- offset
;
11323 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11324 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11325 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11327 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11330 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11331 w
= gen_rtx_IOR (mode
, x
, z
);
11332 SUBST (SET_DEST (pat
), reg
);
11333 SUBST (SET_SRC (pat
), w
);
11341 /* Like recog, but we receive the address of a pointer to a new pattern.
11342 We try to match the rtx that the pointer points to.
11343 If that fails, we may try to modify or replace the pattern,
11344 storing the replacement into the same pointer object.
11346 Modifications include deletion or addition of CLOBBERs. If the
11347 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11348 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11349 (and undo if that fails).
11351 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11352 the CLOBBERs are placed.
11354 The value is the final insn code from the pattern ultimately matched,
11358 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11360 rtx pat
= *pnewpat
;
11361 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11362 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11363 return insn_code_number
;
11365 void *marker
= get_undo_marker ();
11366 bool changed
= false;
11368 if (GET_CODE (pat
) == SET
)
11369 changed
= change_zero_ext (pat
);
11370 else if (GET_CODE (pat
) == PARALLEL
)
11373 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11375 rtx set
= XVECEXP (pat
, 0, i
);
11376 if (GET_CODE (set
) == SET
)
11377 changed
|= change_zero_ext (set
);
11383 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11385 if (insn_code_number
< 0)
11386 undo_to_marker (marker
);
11389 return insn_code_number
;
11392 /* Like gen_lowpart_general but for use by combine. In combine it
11393 is not possible to create any new pseudoregs. However, it is
11394 safe to create invalid memory addresses, because combine will
11395 try to recognize them and all they will do is make the combine
11398 If for some reason this cannot do its job, an rtx
11399 (clobber (const_int 0)) is returned.
11400 An insn containing that will not be recognized. */
11403 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11405 machine_mode imode
= GET_MODE (x
);
11406 unsigned int osize
= GET_MODE_SIZE (omode
);
11407 unsigned int isize
= GET_MODE_SIZE (imode
);
11410 if (omode
== imode
)
11413 /* We can only support MODE being wider than a word if X is a
11414 constant integer or has a mode the same size. */
11415 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11416 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11419 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11420 won't know what to do. So we will strip off the SUBREG here and
11421 process normally. */
11422 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11424 x
= SUBREG_REG (x
);
11426 /* For use in case we fall down into the address adjustments
11427 further below, we need to adjust the known mode and size of
11428 x; imode and isize, since we just adjusted x. */
11429 imode
= GET_MODE (x
);
11431 if (imode
== omode
)
11434 isize
= GET_MODE_SIZE (imode
);
11437 result
= gen_lowpart_common (omode
, x
);
11446 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11448 if (MEM_VOLATILE_P (x
)
11449 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11452 /* If we want to refer to something bigger than the original memref,
11453 generate a paradoxical subreg instead. That will force a reload
11454 of the original memref X. */
11456 return gen_rtx_SUBREG (omode
, x
, 0);
11458 if (WORDS_BIG_ENDIAN
)
11459 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11461 /* Adjust the address so that the address-after-the-data is
11463 if (BYTES_BIG_ENDIAN
)
11464 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11466 return adjust_address_nv (x
, omode
, offset
);
11469 /* If X is a comparison operator, rewrite it in a new mode. This
11470 probably won't match, but may allow further simplifications. */
11471 else if (COMPARISON_P (x
))
11472 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11474 /* If we couldn't simplify X any other way, just enclose it in a
11475 SUBREG. Normally, this SUBREG won't match, but some patterns may
11476 include an explicit SUBREG or we may simplify it further in combine. */
11481 if (imode
== VOIDmode
)
11483 imode
= int_mode_for_mode (omode
);
11484 x
= gen_lowpart_common (imode
, x
);
11488 res
= lowpart_subreg (omode
, x
, imode
);
11494 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11497 /* Try to simplify a comparison between OP0 and a constant OP1,
11498 where CODE is the comparison code that will be tested, into a
11499 (CODE OP0 const0_rtx) form.
11501 The result is a possibly different comparison code to use.
11502 *POP1 may be updated. */
11504 static enum rtx_code
11505 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11506 rtx op0
, rtx
*pop1
)
11508 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11509 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11511 /* Get the constant we are comparing against and turn off all bits
11512 not on in our mode. */
11513 if (mode
!= VOIDmode
)
11514 const_op
= trunc_int_for_mode (const_op
, mode
);
11516 /* If we are comparing against a constant power of two and the value
11517 being compared can only have that single bit nonzero (e.g., it was
11518 `and'ed with that bit), we can replace this with a comparison
11521 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11522 || code
== LT
|| code
== LTU
)
11523 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11524 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11525 && (nonzero_bits (op0
, mode
)
11526 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11528 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11532 /* Similarly, if we are comparing a value known to be either -1 or
11533 0 with -1, change it to the opposite comparison against zero. */
11535 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11536 || code
== GEU
|| code
== LTU
)
11537 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11539 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11543 /* Do some canonicalizations based on the comparison code. We prefer
11544 comparisons against zero and then prefer equality comparisons.
11545 If we can reduce the size of a constant, we will do that too. */
11549 /* < C is equivalent to <= (C - 1) */
11554 /* ... fall through to LE case below. */
11555 gcc_fallthrough ();
11561 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11568 /* If we are doing a <= 0 comparison on a value known to have
11569 a zero sign bit, we can replace this with == 0. */
11570 else if (const_op
== 0
11571 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11572 && (nonzero_bits (op0
, mode
)
11573 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11579 /* >= C is equivalent to > (C - 1). */
11584 /* ... fall through to GT below. */
11585 gcc_fallthrough ();
11591 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11598 /* If we are doing a > 0 comparison on a value known to have
11599 a zero sign bit, we can replace this with != 0. */
11600 else if (const_op
== 0
11601 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11602 && (nonzero_bits (op0
, mode
)
11603 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11609 /* < C is equivalent to <= (C - 1). */
11614 /* ... fall through ... */
11616 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11617 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11618 && (unsigned HOST_WIDE_INT
) const_op
11619 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11629 /* unsigned <= 0 is equivalent to == 0 */
11632 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11633 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11634 && (unsigned HOST_WIDE_INT
) const_op
11635 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11643 /* >= C is equivalent to > (C - 1). */
11648 /* ... fall through ... */
11651 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11652 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11653 && (unsigned HOST_WIDE_INT
) const_op
11654 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11664 /* unsigned > 0 is equivalent to != 0 */
11667 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11668 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11669 && (unsigned HOST_WIDE_INT
) const_op
11670 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11681 *pop1
= GEN_INT (const_op
);
11685 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11686 comparison code that will be tested.
11688 The result is a possibly different comparison code to use. *POP0 and
11689 *POP1 may be updated.
11691 It is possible that we might detect that a comparison is either always
11692 true or always false. However, we do not perform general constant
11693 folding in combine, so this knowledge isn't useful. Such tautologies
11694 should have been detected earlier. Hence we ignore all such cases. */
11696 static enum rtx_code
11697 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11703 machine_mode mode
, tmode
;
11705 /* Try a few ways of applying the same transformation to both operands. */
11708 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11709 so check specially. */
11710 if (!WORD_REGISTER_OPERATIONS
11711 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11712 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11713 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11714 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11715 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11716 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11717 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11718 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11719 && CONST_INT_P (XEXP (op0
, 1))
11720 && XEXP (op0
, 1) == XEXP (op1
, 1)
11721 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11722 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11723 && (INTVAL (XEXP (op0
, 1))
11724 == (GET_MODE_PRECISION (GET_MODE (op0
))
11725 - (GET_MODE_PRECISION
11726 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11728 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11729 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11732 /* If both operands are the same constant shift, see if we can ignore the
11733 shift. We can if the shift is a rotate or if the bits shifted out of
11734 this shift are known to be zero for both inputs and if the type of
11735 comparison is compatible with the shift. */
11736 if (GET_CODE (op0
) == GET_CODE (op1
)
11737 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11738 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11739 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11740 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11741 || (GET_CODE (op0
) == ASHIFTRT
11742 && (code
!= GTU
&& code
!= LTU
11743 && code
!= GEU
&& code
!= LEU
)))
11744 && CONST_INT_P (XEXP (op0
, 1))
11745 && INTVAL (XEXP (op0
, 1)) >= 0
11746 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11747 && XEXP (op0
, 1) == XEXP (op1
, 1))
11749 machine_mode mode
= GET_MODE (op0
);
11750 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11751 int shift_count
= INTVAL (XEXP (op0
, 1));
11753 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11754 mask
&= (mask
>> shift_count
) << shift_count
;
11755 else if (GET_CODE (op0
) == ASHIFT
)
11756 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11758 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11759 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11760 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11765 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11766 SUBREGs are of the same mode, and, in both cases, the AND would
11767 be redundant if the comparison was done in the narrower mode,
11768 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11769 and the operand's possibly nonzero bits are 0xffffff01; in that case
11770 if we only care about QImode, we don't need the AND). This case
11771 occurs if the output mode of an scc insn is not SImode and
11772 STORE_FLAG_VALUE == 1 (e.g., the 386).
11774 Similarly, check for a case where the AND's are ZERO_EXTEND
11775 operations from some narrower mode even though a SUBREG is not
11778 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11779 && CONST_INT_P (XEXP (op0
, 1))
11780 && CONST_INT_P (XEXP (op1
, 1)))
11782 rtx inner_op0
= XEXP (op0
, 0);
11783 rtx inner_op1
= XEXP (op1
, 0);
11784 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11785 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11788 if (paradoxical_subreg_p (inner_op0
)
11789 && GET_CODE (inner_op1
) == SUBREG
11790 && (GET_MODE (SUBREG_REG (inner_op0
))
11791 == GET_MODE (SUBREG_REG (inner_op1
)))
11792 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11793 <= HOST_BITS_PER_WIDE_INT
)
11794 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11795 GET_MODE (SUBREG_REG (inner_op0
)))))
11796 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11797 GET_MODE (SUBREG_REG (inner_op1
))))))
11799 op0
= SUBREG_REG (inner_op0
);
11800 op1
= SUBREG_REG (inner_op1
);
11802 /* The resulting comparison is always unsigned since we masked
11803 off the original sign bit. */
11804 code
= unsigned_condition (code
);
11810 for (tmode
= GET_CLASS_NARROWEST_MODE
11811 (GET_MODE_CLASS (GET_MODE (op0
)));
11812 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11813 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11815 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11816 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11817 code
= unsigned_condition (code
);
11826 /* If both operands are NOT, we can strip off the outer operation
11827 and adjust the comparison code for swapped operands; similarly for
11828 NEG, except that this must be an equality comparison. */
11829 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11830 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11831 && (code
== EQ
|| code
== NE
)))
11832 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11838 /* If the first operand is a constant, swap the operands and adjust the
11839 comparison code appropriately, but don't do this if the second operand
11840 is already a constant integer. */
11841 if (swap_commutative_operands_p (op0
, op1
))
11843 std::swap (op0
, op1
);
11844 code
= swap_condition (code
);
11847 /* We now enter a loop during which we will try to simplify the comparison.
11848 For the most part, we only are concerned with comparisons with zero,
11849 but some things may really be comparisons with zero but not start
11850 out looking that way. */
11852 while (CONST_INT_P (op1
))
11854 machine_mode mode
= GET_MODE (op0
);
11855 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11856 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11857 int equality_comparison_p
;
11858 int sign_bit_comparison_p
;
11859 int unsigned_comparison_p
;
11860 HOST_WIDE_INT const_op
;
11862 /* We only want to handle integral modes. This catches VOIDmode,
11863 CCmode, and the floating-point modes. An exception is that we
11864 can handle VOIDmode if OP0 is a COMPARE or a comparison
11867 if (GET_MODE_CLASS (mode
) != MODE_INT
11868 && ! (mode
== VOIDmode
11869 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11872 /* Try to simplify the compare to constant, possibly changing the
11873 comparison op, and/or changing op1 to zero. */
11874 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11875 const_op
= INTVAL (op1
);
11877 /* Compute some predicates to simplify code below. */
11879 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11880 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11881 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11884 /* If this is a sign bit comparison and we can do arithmetic in
11885 MODE, say that we will only be needing the sign bit of OP0. */
11886 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11887 op0
= force_to_mode (op0
, mode
,
11889 << (GET_MODE_PRECISION (mode
) - 1),
11892 /* Now try cases based on the opcode of OP0. If none of the cases
11893 does a "continue", we exit this loop immediately after the
11896 switch (GET_CODE (op0
))
11899 /* If we are extracting a single bit from a variable position in
11900 a constant that has only a single bit set and are comparing it
11901 with zero, we can convert this into an equality comparison
11902 between the position and the location of the single bit. */
11903 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11904 have already reduced the shift count modulo the word size. */
11905 if (!SHIFT_COUNT_TRUNCATED
11906 && CONST_INT_P (XEXP (op0
, 0))
11907 && XEXP (op0
, 1) == const1_rtx
11908 && equality_comparison_p
&& const_op
== 0
11909 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11911 if (BITS_BIG_ENDIAN
)
11912 i
= BITS_PER_WORD
- 1 - i
;
11914 op0
= XEXP (op0
, 2);
11918 /* Result is nonzero iff shift count is equal to I. */
11919 code
= reverse_condition (code
);
11926 tem
= expand_compound_operation (op0
);
11935 /* If testing for equality, we can take the NOT of the constant. */
11936 if (equality_comparison_p
11937 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11939 op0
= XEXP (op0
, 0);
11944 /* If just looking at the sign bit, reverse the sense of the
11946 if (sign_bit_comparison_p
)
11948 op0
= XEXP (op0
, 0);
11949 code
= (code
== GE
? LT
: GE
);
11955 /* If testing for equality, we can take the NEG of the constant. */
11956 if (equality_comparison_p
11957 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11959 op0
= XEXP (op0
, 0);
11964 /* The remaining cases only apply to comparisons with zero. */
11968 /* When X is ABS or is known positive,
11969 (neg X) is < 0 if and only if X != 0. */
11971 if (sign_bit_comparison_p
11972 && (GET_CODE (XEXP (op0
, 0)) == ABS
11973 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11974 && (nonzero_bits (XEXP (op0
, 0), mode
)
11975 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11978 op0
= XEXP (op0
, 0);
11979 code
= (code
== LT
? NE
: EQ
);
11983 /* If we have NEG of something whose two high-order bits are the
11984 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11985 if (num_sign_bit_copies (op0
, mode
) >= 2)
11987 op0
= XEXP (op0
, 0);
11988 code
= swap_condition (code
);
11994 /* If we are testing equality and our count is a constant, we
11995 can perform the inverse operation on our RHS. */
11996 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11997 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11998 op1
, XEXP (op0
, 1))) != 0)
12000 op0
= XEXP (op0
, 0);
12005 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12006 a particular bit. Convert it to an AND of a constant of that
12007 bit. This will be converted into a ZERO_EXTRACT. */
12008 if (const_op
== 0 && sign_bit_comparison_p
12009 && CONST_INT_P (XEXP (op0
, 1))
12010 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12012 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12015 - INTVAL (XEXP (op0
, 1)))));
12016 code
= (code
== LT
? NE
: EQ
);
12020 /* Fall through. */
12023 /* ABS is ignorable inside an equality comparison with zero. */
12024 if (const_op
== 0 && equality_comparison_p
)
12026 op0
= XEXP (op0
, 0);
12032 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12033 (compare FOO CONST) if CONST fits in FOO's mode and we
12034 are either testing inequality or have an unsigned
12035 comparison with ZERO_EXTEND or a signed comparison with
12036 SIGN_EXTEND. But don't do it if we don't have a compare
12037 insn of the given mode, since we'd have to revert it
12038 later on, and then we wouldn't know whether to sign- or
12040 mode
= GET_MODE (XEXP (op0
, 0));
12041 if (GET_MODE_CLASS (mode
) == MODE_INT
12042 && ! unsigned_comparison_p
12043 && HWI_COMPUTABLE_MODE_P (mode
)
12044 && trunc_int_for_mode (const_op
, mode
) == const_op
12045 && have_insn_for (COMPARE
, mode
))
12047 op0
= XEXP (op0
, 0);
12053 /* Check for the case where we are comparing A - C1 with C2, that is
12055 (subreg:MODE (plus (A) (-C1))) op (C2)
12057 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12058 comparison in the wider mode. One of the following two conditions
12059 must be true in order for this to be valid:
12061 1. The mode extension results in the same bit pattern being added
12062 on both sides and the comparison is equality or unsigned. As
12063 C2 has been truncated to fit in MODE, the pattern can only be
12066 2. The mode extension results in the sign bit being copied on
12069 The difficulty here is that we have predicates for A but not for
12070 (A - C1) so we need to check that C1 is within proper bounds so
12071 as to perturbate A as little as possible. */
12073 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12074 && subreg_lowpart_p (op0
)
12075 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
12076 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12077 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12079 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
12080 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12081 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12084 && (unsigned HOST_WIDE_INT
) c1
12085 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12086 && (equality_comparison_p
|| unsigned_comparison_p
)
12087 /* (A - C1) zero-extends if it is positive and sign-extends
12088 if it is negative, C2 both zero- and sign-extends. */
12089 && ((0 == (nonzero_bits (a
, inner_mode
)
12090 & ~GET_MODE_MASK (mode
))
12092 /* (A - C1) sign-extends if it is positive and 1-extends
12093 if it is negative, C2 both sign- and 1-extends. */
12094 || (num_sign_bit_copies (a
, inner_mode
)
12095 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12098 || ((unsigned HOST_WIDE_INT
) c1
12099 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12100 /* (A - C1) always sign-extends, like C2. */
12101 && num_sign_bit_copies (a
, inner_mode
)
12102 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12103 - (mode_width
- 1))))
12105 op0
= SUBREG_REG (op0
);
12110 /* If the inner mode is narrower and we are extracting the low part,
12111 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12112 if (subreg_lowpart_p (op0
)
12113 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
12115 else if (subreg_lowpart_p (op0
)
12116 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12117 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12118 && (code
== NE
|| code
== EQ
)
12119 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12120 <= HOST_BITS_PER_WIDE_INT
)
12121 && !paradoxical_subreg_p (op0
)
12122 && (nonzero_bits (SUBREG_REG (op0
),
12123 GET_MODE (SUBREG_REG (op0
)))
12124 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12126 /* Remove outer subregs that don't do anything. */
12127 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12129 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12130 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12132 op0
= SUBREG_REG (op0
);
12144 mode
= GET_MODE (XEXP (op0
, 0));
12145 if (GET_MODE_CLASS (mode
) == MODE_INT
12146 && (unsigned_comparison_p
|| equality_comparison_p
)
12147 && HWI_COMPUTABLE_MODE_P (mode
)
12148 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12150 && have_insn_for (COMPARE
, mode
))
12152 op0
= XEXP (op0
, 0);
12158 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12159 this for equality comparisons due to pathological cases involving
12161 if (equality_comparison_p
12162 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12163 op1
, XEXP (op0
, 1))))
12165 op0
= XEXP (op0
, 0);
12170 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12171 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12172 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12174 op0
= XEXP (XEXP (op0
, 0), 0);
12175 code
= (code
== LT
? EQ
: NE
);
12181 /* We used to optimize signed comparisons against zero, but that
12182 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12183 arrive here as equality comparisons, or (GEU, LTU) are
12184 optimized away. No need to special-case them. */
12186 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12187 (eq B (minus A C)), whichever simplifies. We can only do
12188 this for equality comparisons due to pathological cases involving
12190 if (equality_comparison_p
12191 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12192 XEXP (op0
, 1), op1
)))
12194 op0
= XEXP (op0
, 0);
12199 if (equality_comparison_p
12200 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12201 XEXP (op0
, 0), op1
)))
12203 op0
= XEXP (op0
, 1);
12208 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12209 of bits in X minus 1, is one iff X > 0. */
12210 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12211 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12212 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12213 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12215 op0
= XEXP (op0
, 1);
12216 code
= (code
== GE
? LE
: GT
);
12222 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12223 if C is zero or B is a constant. */
12224 if (equality_comparison_p
12225 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12226 XEXP (op0
, 1), op1
)))
12228 op0
= XEXP (op0
, 0);
12235 case UNEQ
: case LTGT
:
12236 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12237 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12238 case UNORDERED
: case ORDERED
:
12239 /* We can't do anything if OP0 is a condition code value, rather
12240 than an actual data value. */
12242 || CC0_P (XEXP (op0
, 0))
12243 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12246 /* Get the two operands being compared. */
12247 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12248 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12250 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12252 /* Check for the cases where we simply want the result of the
12253 earlier test or the opposite of that result. */
12254 if (code
== NE
|| code
== EQ
12255 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12256 && (code
== LT
|| code
== GE
)))
12258 enum rtx_code new_code
;
12259 if (code
== LT
|| code
== NE
)
12260 new_code
= GET_CODE (op0
);
12262 new_code
= reversed_comparison_code (op0
, NULL
);
12264 if (new_code
!= UNKNOWN
)
12275 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12277 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12278 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12279 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12281 op0
= XEXP (op0
, 1);
12282 code
= (code
== GE
? GT
: LE
);
12288 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12289 will be converted to a ZERO_EXTRACT later. */
12290 if (const_op
== 0 && equality_comparison_p
12291 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12292 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12294 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12295 XEXP (XEXP (op0
, 0), 1));
12296 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12300 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12301 zero and X is a comparison and C1 and C2 describe only bits set
12302 in STORE_FLAG_VALUE, we can compare with X. */
12303 if (const_op
== 0 && equality_comparison_p
12304 && mode_width
<= HOST_BITS_PER_WIDE_INT
12305 && CONST_INT_P (XEXP (op0
, 1))
12306 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12307 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12308 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12309 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12311 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12312 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12313 if ((~STORE_FLAG_VALUE
& mask
) == 0
12314 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12315 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12316 && COMPARISON_P (tem
))))
12318 op0
= XEXP (XEXP (op0
, 0), 0);
12323 /* If we are doing an equality comparison of an AND of a bit equal
12324 to the sign bit, replace this with a LT or GE comparison of
12325 the underlying value. */
12326 if (equality_comparison_p
12328 && CONST_INT_P (XEXP (op0
, 1))
12329 && mode_width
<= HOST_BITS_PER_WIDE_INT
12330 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12331 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12333 op0
= XEXP (op0
, 0);
12334 code
= (code
== EQ
? GE
: LT
);
12338 /* If this AND operation is really a ZERO_EXTEND from a narrower
12339 mode, the constant fits within that mode, and this is either an
12340 equality or unsigned comparison, try to do this comparison in
12345 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12346 -> (ne:DI (reg:SI 4) (const_int 0))
12348 unless TRULY_NOOP_TRUNCATION allows it or the register is
12349 known to hold a value of the required mode the
12350 transformation is invalid. */
12351 if ((equality_comparison_p
|| unsigned_comparison_p
)
12352 && CONST_INT_P (XEXP (op0
, 1))
12353 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12354 & GET_MODE_MASK (mode
))
12356 && const_op
>> i
== 0
12357 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12359 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12363 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12364 fits in both M1 and M2 and the SUBREG is either paradoxical
12365 or represents the low part, permute the SUBREG and the AND
12367 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12368 && CONST_INT_P (XEXP (op0
, 1)))
12370 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12371 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12372 /* Require an integral mode, to avoid creating something like
12374 if (SCALAR_INT_MODE_P (tmode
)
12375 /* It is unsafe to commute the AND into the SUBREG if the
12376 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12377 not defined. As originally written the upper bits
12378 have a defined value due to the AND operation.
12379 However, if we commute the AND inside the SUBREG then
12380 they no longer have defined values and the meaning of
12381 the code has been changed.
12382 Also C1 should not change value in the smaller mode,
12383 see PR67028 (a positive C1 can become negative in the
12384 smaller mode, so that the AND does no longer mask the
12386 && ((WORD_REGISTER_OPERATIONS
12387 && mode_width
> GET_MODE_PRECISION (tmode
)
12388 && mode_width
<= BITS_PER_WORD
12389 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12390 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12391 && subreg_lowpart_p (XEXP (op0
, 0))))
12392 && mode_width
<= HOST_BITS_PER_WIDE_INT
12393 && HWI_COMPUTABLE_MODE_P (tmode
)
12394 && (c1
& ~mask
) == 0
12395 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12397 && c1
!= GET_MODE_MASK (tmode
))
12399 op0
= simplify_gen_binary (AND
, tmode
,
12400 SUBREG_REG (XEXP (op0
, 0)),
12401 gen_int_mode (c1
, tmode
));
12402 op0
= gen_lowpart (mode
, op0
);
12407 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12408 if (const_op
== 0 && equality_comparison_p
12409 && XEXP (op0
, 1) == const1_rtx
12410 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12412 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12413 XEXP (XEXP (op0
, 0), 0), 1);
12414 code
= (code
== NE
? EQ
: NE
);
12418 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12419 (eq (and (lshiftrt X) 1) 0).
12420 Also handle the case where (not X) is expressed using xor. */
12421 if (const_op
== 0 && equality_comparison_p
12422 && XEXP (op0
, 1) == const1_rtx
12423 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12425 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12426 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12428 if (GET_CODE (shift_op
) == NOT
12429 || (GET_CODE (shift_op
) == XOR
12430 && CONST_INT_P (XEXP (shift_op
, 1))
12431 && CONST_INT_P (shift_count
)
12432 && HWI_COMPUTABLE_MODE_P (mode
)
12433 && (UINTVAL (XEXP (shift_op
, 1))
12434 == HOST_WIDE_INT_1U
12435 << INTVAL (shift_count
))))
12438 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12439 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12440 code
= (code
== NE
? EQ
: NE
);
12447 /* If we have (compare (ashift FOO N) (const_int C)) and
12448 the high order N bits of FOO (N+1 if an inequality comparison)
12449 are known to be zero, we can do this by comparing FOO with C
12450 shifted right N bits so long as the low-order N bits of C are
12452 if (CONST_INT_P (XEXP (op0
, 1))
12453 && INTVAL (XEXP (op0
, 1)) >= 0
12454 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12455 < HOST_BITS_PER_WIDE_INT
)
12456 && (((unsigned HOST_WIDE_INT
) const_op
12457 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12459 && mode_width
<= HOST_BITS_PER_WIDE_INT
12460 && (nonzero_bits (XEXP (op0
, 0), mode
)
12461 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12462 + ! equality_comparison_p
))) == 0)
12464 /* We must perform a logical shift, not an arithmetic one,
12465 as we want the top N bits of C to be zero. */
12466 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12468 temp
>>= INTVAL (XEXP (op0
, 1));
12469 op1
= gen_int_mode (temp
, mode
);
12470 op0
= XEXP (op0
, 0);
12474 /* If we are doing a sign bit comparison, it means we are testing
12475 a particular bit. Convert it to the appropriate AND. */
12476 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12477 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12479 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12482 - INTVAL (XEXP (op0
, 1)))));
12483 code
= (code
== LT
? NE
: EQ
);
12487 /* If this an equality comparison with zero and we are shifting
12488 the low bit to the sign bit, we can convert this to an AND of the
12490 if (const_op
== 0 && equality_comparison_p
12491 && CONST_INT_P (XEXP (op0
, 1))
12492 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12494 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12500 /* If this is an equality comparison with zero, we can do this
12501 as a logical shift, which might be much simpler. */
12502 if (equality_comparison_p
&& const_op
== 0
12503 && CONST_INT_P (XEXP (op0
, 1)))
12505 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12507 INTVAL (XEXP (op0
, 1)));
12511 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12512 do the comparison in a narrower mode. */
12513 if (! unsigned_comparison_p
12514 && CONST_INT_P (XEXP (op0
, 1))
12515 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12516 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12517 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12518 MODE_INT
, 1)) != BLKmode
12519 && (((unsigned HOST_WIDE_INT
) const_op
12520 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12521 <= GET_MODE_MASK (tmode
)))
12523 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12527 /* Likewise if OP0 is a PLUS of a sign extension with a
12528 constant, which is usually represented with the PLUS
12529 between the shifts. */
12530 if (! unsigned_comparison_p
12531 && CONST_INT_P (XEXP (op0
, 1))
12532 && GET_CODE (XEXP (op0
, 0)) == PLUS
12533 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12534 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12535 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12536 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12537 MODE_INT
, 1)) != BLKmode
12538 && (((unsigned HOST_WIDE_INT
) const_op
12539 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12540 <= GET_MODE_MASK (tmode
)))
12542 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12543 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12544 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12545 add_const
, XEXP (op0
, 1));
12547 op0
= simplify_gen_binary (PLUS
, tmode
,
12548 gen_lowpart (tmode
, inner
),
12555 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12556 the low order N bits of FOO are known to be zero, we can do this
12557 by comparing FOO with C shifted left N bits so long as no
12558 overflow occurs. Even if the low order N bits of FOO aren't known
12559 to be zero, if the comparison is >= or < we can use the same
12560 optimization and for > or <= by setting all the low
12561 order N bits in the comparison constant. */
12562 if (CONST_INT_P (XEXP (op0
, 1))
12563 && INTVAL (XEXP (op0
, 1)) > 0
12564 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12565 && mode_width
<= HOST_BITS_PER_WIDE_INT
12566 && (((unsigned HOST_WIDE_INT
) const_op
12567 + (GET_CODE (op0
) != LSHIFTRT
12568 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12571 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12573 unsigned HOST_WIDE_INT low_bits
12574 = (nonzero_bits (XEXP (op0
, 0), mode
)
12575 & ((HOST_WIDE_INT_1U
12576 << INTVAL (XEXP (op0
, 1))) - 1));
12577 if (low_bits
== 0 || !equality_comparison_p
)
12579 /* If the shift was logical, then we must make the condition
12581 if (GET_CODE (op0
) == LSHIFTRT
)
12582 code
= unsigned_condition (code
);
12584 const_op
= (unsigned HOST_WIDE_INT
) const_op
12585 << INTVAL (XEXP (op0
, 1));
12587 && (code
== GT
|| code
== GTU
12588 || code
== LE
|| code
== LEU
))
12590 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12591 op1
= GEN_INT (const_op
);
12592 op0
= XEXP (op0
, 0);
12597 /* If we are using this shift to extract just the sign bit, we
12598 can replace this with an LT or GE comparison. */
12600 && (equality_comparison_p
|| sign_bit_comparison_p
)
12601 && CONST_INT_P (XEXP (op0
, 1))
12602 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12604 op0
= XEXP (op0
, 0);
12605 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12617 /* Now make any compound operations involved in this comparison. Then,
12618 check for an outmost SUBREG on OP0 that is not doing anything or is
12619 paradoxical. The latter transformation must only be performed when
12620 it is known that the "extra" bits will be the same in op0 and op1 or
12621 that they don't matter. There are three cases to consider:
12623 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12624 care bits and we can assume they have any convenient value. So
12625 making the transformation is safe.
12627 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12628 In this case the upper bits of op0 are undefined. We should not make
12629 the simplification in that case as we do not know the contents of
12632 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12633 In that case we know those bits are zeros or ones. We must also be
12634 sure that they are the same as the upper bits of op1.
12636 We can never remove a SUBREG for a non-equality comparison because
12637 the sign bit is in a different place in the underlying object. */
12639 rtx_code op0_mco_code
= SET
;
12640 if (op1
== const0_rtx
)
12641 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12643 op0
= make_compound_operation (op0
, op0_mco_code
);
12644 op1
= make_compound_operation (op1
, SET
);
12646 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12647 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12648 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12649 && (code
== NE
|| code
== EQ
))
12651 if (paradoxical_subreg_p (op0
))
12653 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12655 if (REG_P (SUBREG_REG (op0
)))
12657 op0
= SUBREG_REG (op0
);
12658 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12661 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12662 <= HOST_BITS_PER_WIDE_INT
)
12663 && (nonzero_bits (SUBREG_REG (op0
),
12664 GET_MODE (SUBREG_REG (op0
)))
12665 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12667 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12669 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12670 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12671 op0
= SUBREG_REG (op0
), op1
= tem
;
12675 /* We now do the opposite procedure: Some machines don't have compare
12676 insns in all modes. If OP0's mode is an integer mode smaller than a
12677 word and we can't do a compare in that mode, see if there is a larger
12678 mode for which we can do the compare. There are a number of cases in
12679 which we can use the wider mode. */
12681 mode
= GET_MODE (op0
);
12682 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12683 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12684 && ! have_insn_for (COMPARE
, mode
))
12685 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12686 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12687 tmode
= GET_MODE_WIDER_MODE (tmode
))
12688 if (have_insn_for (COMPARE
, tmode
))
12692 /* If this is a test for negative, we can make an explicit
12693 test of the sign bit. Test this first so we can use
12694 a paradoxical subreg to extend OP0. */
12696 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12697 && HWI_COMPUTABLE_MODE_P (mode
))
12699 unsigned HOST_WIDE_INT sign
12700 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12701 op0
= simplify_gen_binary (AND
, tmode
,
12702 gen_lowpart (tmode
, op0
),
12703 gen_int_mode (sign
, tmode
));
12704 code
= (code
== LT
) ? NE
: EQ
;
12708 /* If the only nonzero bits in OP0 and OP1 are those in the
12709 narrower mode and this is an equality or unsigned comparison,
12710 we can use the wider mode. Similarly for sign-extended
12711 values, in which case it is true for all comparisons. */
12712 zero_extended
= ((code
== EQ
|| code
== NE
12713 || code
== GEU
|| code
== GTU
12714 || code
== LEU
|| code
== LTU
)
12715 && (nonzero_bits (op0
, tmode
)
12716 & ~GET_MODE_MASK (mode
)) == 0
12717 && ((CONST_INT_P (op1
)
12718 || (nonzero_bits (op1
, tmode
)
12719 & ~GET_MODE_MASK (mode
)) == 0)));
12722 || ((num_sign_bit_copies (op0
, tmode
)
12723 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12724 - GET_MODE_PRECISION (mode
)))
12725 && (num_sign_bit_copies (op1
, tmode
)
12726 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12727 - GET_MODE_PRECISION (mode
)))))
12729 /* If OP0 is an AND and we don't have an AND in MODE either,
12730 make a new AND in the proper mode. */
12731 if (GET_CODE (op0
) == AND
12732 && !have_insn_for (AND
, mode
))
12733 op0
= simplify_gen_binary (AND
, tmode
,
12734 gen_lowpart (tmode
,
12736 gen_lowpart (tmode
,
12742 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12743 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12747 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12748 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12755 /* We may have changed the comparison operands. Re-canonicalize. */
12756 if (swap_commutative_operands_p (op0
, op1
))
12758 std::swap (op0
, op1
);
12759 code
= swap_condition (code
);
12762 /* If this machine only supports a subset of valid comparisons, see if we
12763 can convert an unsupported one into a supported one. */
12764 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12772 /* Utility function for record_value_for_reg. Count number of
12777 enum rtx_code code
= GET_CODE (x
);
12781 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12782 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12784 rtx x0
= XEXP (x
, 0);
12785 rtx x1
= XEXP (x
, 1);
12788 return 1 + 2 * count_rtxs (x0
);
12790 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12791 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12792 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12793 return 2 + 2 * count_rtxs (x0
)
12794 + count_rtxs (x
== XEXP (x1
, 0)
12795 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12797 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12798 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12799 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12800 return 2 + 2 * count_rtxs (x1
)
12801 + count_rtxs (x
== XEXP (x0
, 0)
12802 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12805 fmt
= GET_RTX_FORMAT (code
);
12806 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12808 ret
+= count_rtxs (XEXP (x
, i
));
12809 else if (fmt
[i
] == 'E')
12810 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12811 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12816 /* Utility function for following routine. Called when X is part of a value
12817 being stored into last_set_value. Sets last_set_table_tick
12818 for each register mentioned. Similar to mention_regs in cse.c */
12821 update_table_tick (rtx x
)
12823 enum rtx_code code
= GET_CODE (x
);
12824 const char *fmt
= GET_RTX_FORMAT (code
);
12829 unsigned int regno
= REGNO (x
);
12830 unsigned int endregno
= END_REGNO (x
);
12833 for (r
= regno
; r
< endregno
; r
++)
12835 reg_stat_type
*rsp
= ®_stat
[r
];
12836 rsp
->last_set_table_tick
= label_tick
;
12842 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12845 /* Check for identical subexpressions. If x contains
12846 identical subexpression we only have to traverse one of
12848 if (i
== 0 && ARITHMETIC_P (x
))
12850 /* Note that at this point x1 has already been
12852 rtx x0
= XEXP (x
, 0);
12853 rtx x1
= XEXP (x
, 1);
12855 /* If x0 and x1 are identical then there is no need to
12860 /* If x0 is identical to a subexpression of x1 then while
12861 processing x1, x0 has already been processed. Thus we
12862 are done with x. */
12863 if (ARITHMETIC_P (x1
)
12864 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12867 /* If x1 is identical to a subexpression of x0 then we
12868 still have to process the rest of x0. */
12869 if (ARITHMETIC_P (x0
)
12870 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12872 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12877 update_table_tick (XEXP (x
, i
));
12879 else if (fmt
[i
] == 'E')
12880 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12881 update_table_tick (XVECEXP (x
, i
, j
));
12884 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12885 are saying that the register is clobbered and we no longer know its
12886 value. If INSN is zero, don't update reg_stat[].last_set; this is
12887 only permitted with VALUE also zero and is used to invalidate the
12891 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12893 unsigned int regno
= REGNO (reg
);
12894 unsigned int endregno
= END_REGNO (reg
);
12896 reg_stat_type
*rsp
;
12898 /* If VALUE contains REG and we have a previous value for REG, substitute
12899 the previous value. */
12900 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12904 /* Set things up so get_last_value is allowed to see anything set up to
12906 subst_low_luid
= DF_INSN_LUID (insn
);
12907 tem
= get_last_value (reg
);
12909 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12910 it isn't going to be useful and will take a lot of time to process,
12911 so just use the CLOBBER. */
12915 if (ARITHMETIC_P (tem
)
12916 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12917 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12918 tem
= XEXP (tem
, 0);
12919 else if (count_occurrences (value
, reg
, 1) >= 2)
12921 /* If there are two or more occurrences of REG in VALUE,
12922 prevent the value from growing too much. */
12923 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12924 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12927 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12931 /* For each register modified, show we don't know its value, that
12932 we don't know about its bitwise content, that its value has been
12933 updated, and that we don't know the location of the death of the
12935 for (i
= regno
; i
< endregno
; i
++)
12937 rsp
= ®_stat
[i
];
12940 rsp
->last_set
= insn
;
12942 rsp
->last_set_value
= 0;
12943 rsp
->last_set_mode
= VOIDmode
;
12944 rsp
->last_set_nonzero_bits
= 0;
12945 rsp
->last_set_sign_bit_copies
= 0;
12946 rsp
->last_death
= 0;
12947 rsp
->truncated_to_mode
= VOIDmode
;
12950 /* Mark registers that are being referenced in this value. */
12952 update_table_tick (value
);
12954 /* Now update the status of each register being set.
12955 If someone is using this register in this block, set this register
12956 to invalid since we will get confused between the two lives in this
12957 basic block. This makes using this register always invalid. In cse, we
12958 scan the table to invalidate all entries using this register, but this
12959 is too much work for us. */
12961 for (i
= regno
; i
< endregno
; i
++)
12963 rsp
= ®_stat
[i
];
12964 rsp
->last_set_label
= label_tick
;
12966 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12967 rsp
->last_set_invalid
= 1;
12969 rsp
->last_set_invalid
= 0;
12972 /* The value being assigned might refer to X (like in "x++;"). In that
12973 case, we must replace it with (clobber (const_int 0)) to prevent
12975 rsp
= ®_stat
[regno
];
12976 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12978 value
= copy_rtx (value
);
12979 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12983 /* For the main register being modified, update the value, the mode, the
12984 nonzero bits, and the number of sign bit copies. */
12986 rsp
->last_set_value
= value
;
12990 machine_mode mode
= GET_MODE (reg
);
12991 subst_low_luid
= DF_INSN_LUID (insn
);
12992 rsp
->last_set_mode
= mode
;
12993 if (GET_MODE_CLASS (mode
) == MODE_INT
12994 && HWI_COMPUTABLE_MODE_P (mode
))
12995 mode
= nonzero_bits_mode
;
12996 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12997 rsp
->last_set_sign_bit_copies
12998 = num_sign_bit_copies (value
, GET_MODE (reg
));
13002 /* Called via note_stores from record_dead_and_set_regs to handle one
13003 SET or CLOBBER in an insn. DATA is the instruction in which the
13004 set is occurring. */
13007 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13009 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13011 if (GET_CODE (dest
) == SUBREG
)
13012 dest
= SUBREG_REG (dest
);
13014 if (!record_dead_insn
)
13017 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13023 /* If we are setting the whole register, we know its value. Otherwise
13024 show that we don't know the value. We can handle SUBREG in
13026 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13027 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13028 else if (GET_CODE (setter
) == SET
13029 && GET_CODE (SET_DEST (setter
)) == SUBREG
13030 && SUBREG_REG (SET_DEST (setter
)) == dest
13031 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13032 && subreg_lowpart_p (SET_DEST (setter
)))
13033 record_value_for_reg (dest
, record_dead_insn
,
13034 gen_lowpart (GET_MODE (dest
),
13035 SET_SRC (setter
)));
13037 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13039 else if (MEM_P (dest
)
13040 /* Ignore pushes, they clobber nothing. */
13041 && ! push_operand (dest
, GET_MODE (dest
)))
13042 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13045 /* Update the records of when each REG was most recently set or killed
13046 for the things done by INSN. This is the last thing done in processing
13047 INSN in the combiner loop.
13049 We update reg_stat[], in particular fields last_set, last_set_value,
13050 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13051 last_death, and also the similar information mem_last_set (which insn
13052 most recently modified memory) and last_call_luid (which insn was the
13053 most recent subroutine call). */
13056 record_dead_and_set_regs (rtx_insn
*insn
)
13061 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13063 if (REG_NOTE_KIND (link
) == REG_DEAD
13064 && REG_P (XEXP (link
, 0)))
13066 unsigned int regno
= REGNO (XEXP (link
, 0));
13067 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13069 for (i
= regno
; i
< endregno
; i
++)
13071 reg_stat_type
*rsp
;
13073 rsp
= ®_stat
[i
];
13074 rsp
->last_death
= insn
;
13077 else if (REG_NOTE_KIND (link
) == REG_INC
)
13078 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13083 hard_reg_set_iterator hrsi
;
13084 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13086 reg_stat_type
*rsp
;
13088 rsp
= ®_stat
[i
];
13089 rsp
->last_set_invalid
= 1;
13090 rsp
->last_set
= insn
;
13091 rsp
->last_set_value
= 0;
13092 rsp
->last_set_mode
= VOIDmode
;
13093 rsp
->last_set_nonzero_bits
= 0;
13094 rsp
->last_set_sign_bit_copies
= 0;
13095 rsp
->last_death
= 0;
13096 rsp
->truncated_to_mode
= VOIDmode
;
13099 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13101 /* We can't combine into a call pattern. Remember, though, that
13102 the return value register is set at this LUID. We could
13103 still replace a register with the return value from the
13104 wrong subroutine call! */
13105 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13108 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13111 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13112 register present in the SUBREG, so for each such SUBREG go back and
13113 adjust nonzero and sign bit information of the registers that are
13114 known to have some zero/sign bits set.
13116 This is needed because when combine blows the SUBREGs away, the
13117 information on zero/sign bits is lost and further combines can be
13118 missed because of that. */
13121 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13123 struct insn_link
*links
;
13125 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13126 machine_mode mode
= GET_MODE (subreg
);
13128 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
13131 for (links
= LOG_LINKS (insn
); links
;)
13133 reg_stat_type
*rsp
;
13135 insn
= links
->insn
;
13136 set
= single_set (insn
);
13138 if (! set
|| !REG_P (SET_DEST (set
))
13139 || REGNO (SET_DEST (set
)) != regno
13140 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13142 links
= links
->next
;
13146 rsp
= ®_stat
[regno
];
13147 if (rsp
->last_set
== insn
)
13149 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13150 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13153 if (REG_P (SET_SRC (set
)))
13155 regno
= REGNO (SET_SRC (set
));
13156 links
= LOG_LINKS (insn
);
13163 /* Check if X, a register, is known to contain a value already
13164 truncated to MODE. In this case we can use a subreg to refer to
13165 the truncated value even though in the generic case we would need
13166 an explicit truncation. */
13169 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13171 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13172 machine_mode truncated
= rsp
->truncated_to_mode
;
13175 || rsp
->truncation_label
< label_tick_ebb_start
)
13177 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
13179 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13184 /* If X is a hard reg or a subreg record the mode that the register is
13185 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13186 to turn a truncate into a subreg using this information. Return true
13187 if traversing X is complete. */
13190 record_truncated_value (rtx x
)
13192 machine_mode truncated_mode
;
13193 reg_stat_type
*rsp
;
13195 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13197 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13198 truncated_mode
= GET_MODE (x
);
13200 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
13203 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13206 x
= SUBREG_REG (x
);
13208 /* ??? For hard-regs we now record everything. We might be able to
13209 optimize this using last_set_mode. */
13210 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13211 truncated_mode
= GET_MODE (x
);
13215 rsp
= ®_stat
[REGNO (x
)];
13216 if (rsp
->truncated_to_mode
== 0
13217 || rsp
->truncation_label
< label_tick_ebb_start
13218 || (GET_MODE_SIZE (truncated_mode
)
13219 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13221 rsp
->truncated_to_mode
= truncated_mode
;
13222 rsp
->truncation_label
= label_tick
;
13228 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13229 the modes they are used in. This can help truning TRUNCATEs into
13233 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13235 subrtx_var_iterator::array_type array
;
13236 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13237 if (record_truncated_value (*iter
))
13238 iter
.skip_subrtxes ();
13241 /* Scan X for promoted SUBREGs. For each one found,
13242 note what it implies to the registers used in it. */
13245 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13247 if (GET_CODE (x
) == SUBREG
13248 && SUBREG_PROMOTED_VAR_P (x
)
13249 && REG_P (SUBREG_REG (x
)))
13250 record_promoted_value (insn
, x
);
13253 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13256 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13260 check_promoted_subreg (insn
, XEXP (x
, i
));
13264 if (XVEC (x
, i
) != 0)
13265 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13266 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13272 /* Verify that all the registers and memory references mentioned in *LOC are
13273 still valid. *LOC was part of a value set in INSN when label_tick was
13274 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13275 the invalid references with (clobber (const_int 0)) and return 1. This
13276 replacement is useful because we often can get useful information about
13277 the form of a value (e.g., if it was produced by a shift that always
13278 produces -1 or 0) even though we don't know exactly what registers it
13279 was produced from. */
13282 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13285 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13286 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13291 unsigned int regno
= REGNO (x
);
13292 unsigned int endregno
= END_REGNO (x
);
13295 for (j
= regno
; j
< endregno
; j
++)
13297 reg_stat_type
*rsp
= ®_stat
[j
];
13298 if (rsp
->last_set_invalid
13299 /* If this is a pseudo-register that was only set once and not
13300 live at the beginning of the function, it is always valid. */
13301 || (! (regno
>= FIRST_PSEUDO_REGISTER
13302 && regno
< reg_n_sets_max
13303 && REG_N_SETS (regno
) == 1
13304 && (!REGNO_REG_SET_P
13305 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13307 && rsp
->last_set_label
> tick
))
13310 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13317 /* If this is a memory reference, make sure that there were no stores after
13318 it that might have clobbered the value. We don't have alias info, so we
13319 assume any store invalidates it. Moreover, we only have local UIDs, so
13320 we also assume that there were stores in the intervening basic blocks. */
13321 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13322 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13325 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13329 for (i
= 0; i
< len
; i
++)
13333 /* Check for identical subexpressions. If x contains
13334 identical subexpression we only have to traverse one of
13336 if (i
== 1 && ARITHMETIC_P (x
))
13338 /* Note that at this point x0 has already been checked
13339 and found valid. */
13340 rtx x0
= XEXP (x
, 0);
13341 rtx x1
= XEXP (x
, 1);
13343 /* If x0 and x1 are identical then x is also valid. */
13347 /* If x1 is identical to a subexpression of x0 then
13348 while checking x0, x1 has already been checked. Thus
13349 it is valid and so as x. */
13350 if (ARITHMETIC_P (x0
)
13351 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13354 /* If x0 is identical to a subexpression of x1 then x is
13355 valid iff the rest of x1 is valid. */
13356 if (ARITHMETIC_P (x1
)
13357 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13359 get_last_value_validate (&XEXP (x1
,
13360 x0
== XEXP (x1
, 0) ? 1 : 0),
13361 insn
, tick
, replace
);
13364 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13368 else if (fmt
[i
] == 'E')
13369 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13370 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13371 insn
, tick
, replace
) == 0)
13375 /* If we haven't found a reason for it to be invalid, it is valid. */
13379 /* Get the last value assigned to X, if known. Some registers
13380 in the value may be replaced with (clobber (const_int 0)) if their value
13381 is known longer known reliably. */
13384 get_last_value (const_rtx x
)
13386 unsigned int regno
;
13388 reg_stat_type
*rsp
;
13390 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13391 then convert it to the desired mode. If this is a paradoxical SUBREG,
13392 we cannot predict what values the "extra" bits might have. */
13393 if (GET_CODE (x
) == SUBREG
13394 && subreg_lowpart_p (x
)
13395 && !paradoxical_subreg_p (x
)
13396 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13397 return gen_lowpart (GET_MODE (x
), value
);
13403 rsp
= ®_stat
[regno
];
13404 value
= rsp
->last_set_value
;
13406 /* If we don't have a value, or if it isn't for this basic block and
13407 it's either a hard register, set more than once, or it's a live
13408 at the beginning of the function, return 0.
13410 Because if it's not live at the beginning of the function then the reg
13411 is always set before being used (is never used without being set).
13412 And, if it's set only once, and it's always set before use, then all
13413 uses must have the same last value, even if it's not from this basic
13417 || (rsp
->last_set_label
< label_tick_ebb_start
13418 && (regno
< FIRST_PSEUDO_REGISTER
13419 || regno
>= reg_n_sets_max
13420 || REG_N_SETS (regno
) != 1
13422 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13425 /* If the value was set in a later insn than the ones we are processing,
13426 we can't use it even if the register was only set once. */
13427 if (rsp
->last_set_label
== label_tick
13428 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13431 /* If fewer bits were set than what we are asked for now, we cannot use
13433 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13434 < GET_MODE_PRECISION (GET_MODE (x
)))
13437 /* If the value has all its registers valid, return it. */
13438 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13441 /* Otherwise, make a copy and replace any invalid register with
13442 (clobber (const_int 0)). If that fails for some reason, return 0. */
13444 value
= copy_rtx (value
);
13445 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13451 /* Return nonzero if expression X refers to a REG or to memory
13452 that is set in an instruction more recent than FROM_LUID. */
13455 use_crosses_set_p (const_rtx x
, int from_luid
)
13459 enum rtx_code code
= GET_CODE (x
);
13463 unsigned int regno
= REGNO (x
);
13464 unsigned endreg
= END_REGNO (x
);
13466 #ifdef PUSH_ROUNDING
13467 /* Don't allow uses of the stack pointer to be moved,
13468 because we don't know whether the move crosses a push insn. */
13469 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13472 for (; regno
< endreg
; regno
++)
13474 reg_stat_type
*rsp
= ®_stat
[regno
];
13476 && rsp
->last_set_label
== label_tick
13477 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13483 if (code
== MEM
&& mem_last_set
> from_luid
)
13486 fmt
= GET_RTX_FORMAT (code
);
13488 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13493 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13494 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13497 else if (fmt
[i
] == 'e'
13498 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13504 /* Define three variables used for communication between the following
13507 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13508 static int reg_dead_flag
;
13510 /* Function called via note_stores from reg_dead_at_p.
13512 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13513 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13516 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13518 unsigned int regno
, endregno
;
13523 regno
= REGNO (dest
);
13524 endregno
= END_REGNO (dest
);
13525 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13526 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13529 /* Return nonzero if REG is known to be dead at INSN.
13531 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13532 referencing REG, it is dead. If we hit a SET referencing REG, it is
13533 live. Otherwise, see if it is live or dead at the start of the basic
13534 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13535 must be assumed to be always live. */
13538 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13543 /* Set variables for reg_dead_at_p_1. */
13544 reg_dead_regno
= REGNO (reg
);
13545 reg_dead_endregno
= END_REGNO (reg
);
13549 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13550 we allow the machine description to decide whether use-and-clobber
13551 patterns are OK. */
13552 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13554 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13555 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13559 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13560 beginning of basic block. */
13561 block
= BLOCK_FOR_INSN (insn
);
13566 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13569 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13571 return reg_dead_flag
== 1 ? 1 : 0;
13573 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13577 if (insn
== BB_HEAD (block
))
13580 insn
= PREV_INSN (insn
);
13583 /* Look at live-in sets for the basic block that we were in. */
13584 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13585 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13591 /* Note hard registers in X that are used. */
13594 mark_used_regs_combine (rtx x
)
13596 RTX_CODE code
= GET_CODE (x
);
13597 unsigned int regno
;
13608 case ADDR_DIFF_VEC
:
13610 /* CC0 must die in the insn after it is set, so we don't need to take
13611 special note of it here. */
13616 /* If we are clobbering a MEM, mark any hard registers inside the
13617 address as used. */
13618 if (MEM_P (XEXP (x
, 0)))
13619 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13624 /* A hard reg in a wide mode may really be multiple registers.
13625 If so, mark all of them just like the first. */
13626 if (regno
< FIRST_PSEUDO_REGISTER
)
13628 /* None of this applies to the stack, frame or arg pointers. */
13629 if (regno
== STACK_POINTER_REGNUM
13630 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13631 && regno
== HARD_FRAME_POINTER_REGNUM
)
13632 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13633 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13634 || regno
== FRAME_POINTER_REGNUM
)
13637 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13643 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13645 rtx testreg
= SET_DEST (x
);
13647 while (GET_CODE (testreg
) == SUBREG
13648 || GET_CODE (testreg
) == ZERO_EXTRACT
13649 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13650 testreg
= XEXP (testreg
, 0);
13652 if (MEM_P (testreg
))
13653 mark_used_regs_combine (XEXP (testreg
, 0));
13655 mark_used_regs_combine (SET_SRC (x
));
13663 /* Recursively scan the operands of this expression. */
13666 const char *fmt
= GET_RTX_FORMAT (code
);
13668 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13671 mark_used_regs_combine (XEXP (x
, i
));
13672 else if (fmt
[i
] == 'E')
13676 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13677 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13683 /* Remove register number REGNO from the dead registers list of INSN.
13685 Return the note used to record the death, if there was one. */
13688 remove_death (unsigned int regno
, rtx_insn
*insn
)
13690 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13693 remove_note (insn
, note
);
13698 /* For each register (hardware or pseudo) used within expression X, if its
13699 death is in an instruction with luid between FROM_LUID (inclusive) and
13700 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13701 list headed by PNOTES.
13703 That said, don't move registers killed by maybe_kill_insn.
13705 This is done when X is being merged by combination into TO_INSN. These
13706 notes will then be distributed as needed. */
13709 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13714 enum rtx_code code
= GET_CODE (x
);
13718 unsigned int regno
= REGNO (x
);
13719 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13721 /* Don't move the register if it gets killed in between from and to. */
13722 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13723 && ! reg_referenced_p (x
, maybe_kill_insn
))
13727 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13728 && DF_INSN_LUID (where_dead
) >= from_luid
13729 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13731 rtx note
= remove_death (regno
, where_dead
);
13733 /* It is possible for the call above to return 0. This can occur
13734 when last_death points to I2 or I1 that we combined with.
13735 In that case make a new note.
13737 We must also check for the case where X is a hard register
13738 and NOTE is a death note for a range of hard registers
13739 including X. In that case, we must put REG_DEAD notes for
13740 the remaining registers in place of NOTE. */
13742 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13743 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13744 > GET_MODE_SIZE (GET_MODE (x
))))
13746 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13747 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13748 unsigned int ourend
= END_REGNO (x
);
13751 for (i
= deadregno
; i
< deadend
; i
++)
13752 if (i
< regno
|| i
>= ourend
)
13753 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13756 /* If we didn't find any note, or if we found a REG_DEAD note that
13757 covers only part of the given reg, and we have a multi-reg hard
13758 register, then to be safe we must check for REG_DEAD notes
13759 for each register other than the first. They could have
13760 their own REG_DEAD notes lying around. */
13761 else if ((note
== 0
13763 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13764 < GET_MODE_SIZE (GET_MODE (x
)))))
13765 && regno
< FIRST_PSEUDO_REGISTER
13766 && REG_NREGS (x
) > 1)
13768 unsigned int ourend
= END_REGNO (x
);
13769 unsigned int i
, offset
;
13773 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13777 for (i
= regno
+ offset
; i
< ourend
; i
++)
13778 move_deaths (regno_reg_rtx
[i
],
13779 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13782 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13784 XEXP (note
, 1) = *pnotes
;
13788 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13794 else if (GET_CODE (x
) == SET
)
13796 rtx dest
= SET_DEST (x
);
13798 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13800 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13801 that accesses one word of a multi-word item, some
13802 piece of everything register in the expression is used by
13803 this insn, so remove any old death. */
13804 /* ??? So why do we test for equality of the sizes? */
13806 if (GET_CODE (dest
) == ZERO_EXTRACT
13807 || GET_CODE (dest
) == STRICT_LOW_PART
13808 || (GET_CODE (dest
) == SUBREG
13809 && (((GET_MODE_SIZE (GET_MODE (dest
))
13810 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13811 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13812 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13814 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13818 /* If this is some other SUBREG, we know it replaces the entire
13819 value, so use that as the destination. */
13820 if (GET_CODE (dest
) == SUBREG
)
13821 dest
= SUBREG_REG (dest
);
13823 /* If this is a MEM, adjust deaths of anything used in the address.
13824 For a REG (the only other possibility), the entire value is
13825 being replaced so the old value is not used in this insn. */
13828 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13833 else if (GET_CODE (x
) == CLOBBER
)
13836 len
= GET_RTX_LENGTH (code
);
13837 fmt
= GET_RTX_FORMAT (code
);
13839 for (i
= 0; i
< len
; i
++)
13844 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13845 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13848 else if (fmt
[i
] == 'e')
13849 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13853 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13854 pattern of an insn. X must be a REG. */
13857 reg_bitfield_target_p (rtx x
, rtx body
)
13861 if (GET_CODE (body
) == SET
)
13863 rtx dest
= SET_DEST (body
);
13865 unsigned int regno
, tregno
, endregno
, endtregno
;
13867 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13868 target
= XEXP (dest
, 0);
13869 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13870 target
= SUBREG_REG (XEXP (dest
, 0));
13874 if (GET_CODE (target
) == SUBREG
)
13875 target
= SUBREG_REG (target
);
13877 if (!REG_P (target
))
13880 tregno
= REGNO (target
), regno
= REGNO (x
);
13881 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13882 return target
== x
;
13884 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13885 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13887 return endregno
> tregno
&& regno
< endtregno
;
13890 else if (GET_CODE (body
) == PARALLEL
)
13891 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13892 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13898 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13899 as appropriate. I3 and I2 are the insns resulting from the combination
13900 insns including FROM (I2 may be zero).
13902 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13903 not need REG_DEAD notes because they are being substituted for. This
13904 saves searching in the most common cases.
13906 Each note in the list is either ignored or placed on some insns, depending
13907 on the type of note. */
13910 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13911 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13913 rtx note
, next_note
;
13915 rtx_insn
*tem_insn
;
13917 for (note
= notes
; note
; note
= next_note
)
13919 rtx_insn
*place
= 0, *place2
= 0;
13921 next_note
= XEXP (note
, 1);
13922 switch (REG_NOTE_KIND (note
))
13926 /* Doesn't matter much where we put this, as long as it's somewhere.
13927 It is preferable to keep these notes on branches, which is most
13928 likely to be i3. */
13932 case REG_NON_LOCAL_GOTO
:
13937 gcc_assert (i2
&& JUMP_P (i2
));
13942 case REG_EH_REGION
:
13943 /* These notes must remain with the call or trapping instruction. */
13946 else if (i2
&& CALL_P (i2
))
13950 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13951 if (may_trap_p (i3
))
13953 else if (i2
&& may_trap_p (i2
))
13955 /* ??? Otherwise assume we've combined things such that we
13956 can now prove that the instructions can't trap. Drop the
13957 note in this case. */
13961 case REG_ARGS_SIZE
:
13962 /* ??? How to distribute between i3-i1. Assume i3 contains the
13963 entire adjustment. Assert i3 contains at least some adjust. */
13964 if (!noop_move_p (i3
))
13966 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13967 /* fixup_args_size_notes looks at REG_NORETURN note,
13968 so ensure the note is placed there first. */
13972 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13973 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13977 XEXP (n
, 1) = REG_NOTES (i3
);
13978 REG_NOTES (i3
) = n
;
13982 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13983 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13984 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13985 gcc_assert (old_size
!= args_size
13987 && !ACCUMULATE_OUTGOING_ARGS
13988 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13995 case REG_CALL_DECL
:
13996 /* These notes must remain with the call. It should not be
13997 possible for both I2 and I3 to be a call. */
14002 gcc_assert (i2
&& CALL_P (i2
));
14008 /* Any clobbers for i3 may still exist, and so we must process
14009 REG_UNUSED notes from that insn.
14011 Any clobbers from i2 or i1 can only exist if they were added by
14012 recog_for_combine. In that case, recog_for_combine created the
14013 necessary REG_UNUSED notes. Trying to keep any original
14014 REG_UNUSED notes from these insns can cause incorrect output
14015 if it is for the same register as the original i3 dest.
14016 In that case, we will notice that the register is set in i3,
14017 and then add a REG_UNUSED note for the destination of i3, which
14018 is wrong. However, it is possible to have REG_UNUSED notes from
14019 i2 or i1 for register which were both used and clobbered, so
14020 we keep notes from i2 or i1 if they will turn into REG_DEAD
14023 /* If this register is set or clobbered in I3, put the note there
14024 unless there is one already. */
14025 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14027 if (from_insn
!= i3
)
14030 if (! (REG_P (XEXP (note
, 0))
14031 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14032 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14035 /* Otherwise, if this register is used by I3, then this register
14036 now dies here, so we must put a REG_DEAD note here unless there
14038 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14039 && ! (REG_P (XEXP (note
, 0))
14040 ? find_regno_note (i3
, REG_DEAD
,
14041 REGNO (XEXP (note
, 0)))
14042 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14044 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14052 /* These notes say something about results of an insn. We can
14053 only support them if they used to be on I3 in which case they
14054 remain on I3. Otherwise they are ignored.
14056 If the note refers to an expression that is not a constant, we
14057 must also ignore the note since we cannot tell whether the
14058 equivalence is still true. It might be possible to do
14059 slightly better than this (we only have a problem if I2DEST
14060 or I1DEST is present in the expression), but it doesn't
14061 seem worth the trouble. */
14063 if (from_insn
== i3
14064 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14069 /* These notes say something about how a register is used. They must
14070 be present on any use of the register in I2 or I3. */
14071 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14074 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14083 case REG_LABEL_TARGET
:
14084 case REG_LABEL_OPERAND
:
14085 /* This can show up in several ways -- either directly in the
14086 pattern, or hidden off in the constant pool with (or without?)
14087 a REG_EQUAL note. */
14088 /* ??? Ignore the without-reg_equal-note problem for now. */
14089 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14090 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14091 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14092 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14096 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14097 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14098 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14099 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14107 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14108 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14110 if (place
&& JUMP_P (place
)
14111 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14112 && (JUMP_LABEL (place
) == NULL
14113 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14115 rtx label
= JUMP_LABEL (place
);
14118 JUMP_LABEL (place
) = XEXP (note
, 0);
14119 else if (LABEL_P (label
))
14120 LABEL_NUSES (label
)--;
14123 if (place2
&& JUMP_P (place2
)
14124 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14125 && (JUMP_LABEL (place2
) == NULL
14126 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14128 rtx label
= JUMP_LABEL (place2
);
14131 JUMP_LABEL (place2
) = XEXP (note
, 0);
14132 else if (LABEL_P (label
))
14133 LABEL_NUSES (label
)--;
14139 /* This note says something about the value of a register prior
14140 to the execution of an insn. It is too much trouble to see
14141 if the note is still correct in all situations. It is better
14142 to simply delete it. */
14146 /* If we replaced the right hand side of FROM_INSN with a
14147 REG_EQUAL note, the original use of the dying register
14148 will not have been combined into I3 and I2. In such cases,
14149 FROM_INSN is guaranteed to be the first of the combined
14150 instructions, so we simply need to search back before
14151 FROM_INSN for the previous use or set of this register,
14152 then alter the notes there appropriately.
14154 If the register is used as an input in I3, it dies there.
14155 Similarly for I2, if it is nonzero and adjacent to I3.
14157 If the register is not used as an input in either I3 or I2
14158 and it is not one of the registers we were supposed to eliminate,
14159 there are two possibilities. We might have a non-adjacent I2
14160 or we might have somehow eliminated an additional register
14161 from a computation. For example, we might have had A & B where
14162 we discover that B will always be zero. In this case we will
14163 eliminate the reference to A.
14165 In both cases, we must search to see if we can find a previous
14166 use of A and put the death note there. */
14169 && from_insn
== i2mod
14170 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14171 tem_insn
= from_insn
;
14175 && CALL_P (from_insn
)
14176 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14178 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14180 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14181 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14183 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14185 && reg_overlap_mentioned_p (XEXP (note
, 0),
14187 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14188 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14191 /* If the new I2 sets the same register that is marked dead
14192 in the note, we do not know where to put the note.
14194 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14200 basic_block bb
= this_basic_block
;
14202 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14204 if (!NONDEBUG_INSN_P (tem_insn
))
14206 if (tem_insn
== BB_HEAD (bb
))
14211 /* If the register is being set at TEM_INSN, see if that is all
14212 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14213 into a REG_UNUSED note instead. Don't delete sets to
14214 global register vars. */
14215 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14216 || !global_regs
[REGNO (XEXP (note
, 0))])
14217 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14219 rtx set
= single_set (tem_insn
);
14220 rtx inner_dest
= 0;
14221 rtx_insn
*cc0_setter
= NULL
;
14224 for (inner_dest
= SET_DEST (set
);
14225 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14226 || GET_CODE (inner_dest
) == SUBREG
14227 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14228 inner_dest
= XEXP (inner_dest
, 0))
14231 /* Verify that it was the set, and not a clobber that
14232 modified the register.
14234 CC0 targets must be careful to maintain setter/user
14235 pairs. If we cannot delete the setter due to side
14236 effects, mark the user with an UNUSED note instead
14239 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14240 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14242 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14243 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14244 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14246 /* Move the notes and links of TEM_INSN elsewhere.
14247 This might delete other dead insns recursively.
14248 First set the pattern to something that won't use
14250 rtx old_notes
= REG_NOTES (tem_insn
);
14252 PATTERN (tem_insn
) = pc_rtx
;
14253 REG_NOTES (tem_insn
) = NULL
;
14255 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14256 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14257 distribute_links (LOG_LINKS (tem_insn
));
14259 SET_INSN_DELETED (tem_insn
);
14260 if (tem_insn
== i2
)
14263 /* Delete the setter too. */
14266 PATTERN (cc0_setter
) = pc_rtx
;
14267 old_notes
= REG_NOTES (cc0_setter
);
14268 REG_NOTES (cc0_setter
) = NULL
;
14270 distribute_notes (old_notes
, cc0_setter
,
14272 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14273 distribute_links (LOG_LINKS (cc0_setter
));
14275 SET_INSN_DELETED (cc0_setter
);
14276 if (cc0_setter
== i2
)
14282 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14284 /* If there isn't already a REG_UNUSED note, put one
14285 here. Do not place a REG_DEAD note, even if
14286 the register is also used here; that would not
14287 match the algorithm used in lifetime analysis
14288 and can cause the consistency check in the
14289 scheduler to fail. */
14290 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14291 REGNO (XEXP (note
, 0))))
14296 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14297 || (CALL_P (tem_insn
)
14298 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14302 /* If we are doing a 3->2 combination, and we have a
14303 register which formerly died in i3 and was not used
14304 by i2, which now no longer dies in i3 and is used in
14305 i2 but does not die in i2, and place is between i2
14306 and i3, then we may need to move a link from place to
14308 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14310 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14311 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14313 struct insn_link
*links
= LOG_LINKS (place
);
14314 LOG_LINKS (place
) = NULL
;
14315 distribute_links (links
);
14320 if (tem_insn
== BB_HEAD (bb
))
14326 /* If the register is set or already dead at PLACE, we needn't do
14327 anything with this note if it is still a REG_DEAD note.
14328 We check here if it is set at all, not if is it totally replaced,
14329 which is what `dead_or_set_p' checks, so also check for it being
14332 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14334 unsigned int regno
= REGNO (XEXP (note
, 0));
14335 reg_stat_type
*rsp
= ®_stat
[regno
];
14337 if (dead_or_set_p (place
, XEXP (note
, 0))
14338 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14340 /* Unless the register previously died in PLACE, clear
14341 last_death. [I no longer understand why this is
14343 if (rsp
->last_death
!= place
)
14344 rsp
->last_death
= 0;
14348 rsp
->last_death
= place
;
14350 /* If this is a death note for a hard reg that is occupying
14351 multiple registers, ensure that we are still using all
14352 parts of the object. If we find a piece of the object
14353 that is unused, we must arrange for an appropriate REG_DEAD
14354 note to be added for it. However, we can't just emit a USE
14355 and tag the note to it, since the register might actually
14356 be dead; so we recourse, and the recursive call then finds
14357 the previous insn that used this register. */
14359 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14361 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14362 bool all_used
= true;
14365 for (i
= regno
; i
< endregno
; i
++)
14366 if ((! refers_to_regno_p (i
, PATTERN (place
))
14367 && ! find_regno_fusage (place
, USE
, i
))
14368 || dead_or_set_regno_p (place
, i
))
14376 /* Put only REG_DEAD notes for pieces that are
14377 not already dead or set. */
14379 for (i
= regno
; i
< endregno
;
14380 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14382 rtx piece
= regno_reg_rtx
[i
];
14383 basic_block bb
= this_basic_block
;
14385 if (! dead_or_set_p (place
, piece
)
14386 && ! reg_bitfield_target_p (piece
,
14389 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14392 distribute_notes (new_note
, place
, place
,
14393 NULL
, NULL_RTX
, NULL_RTX
,
14396 else if (! refers_to_regno_p (i
, PATTERN (place
))
14397 && ! find_regno_fusage (place
, USE
, i
))
14398 for (tem_insn
= PREV_INSN (place
); ;
14399 tem_insn
= PREV_INSN (tem_insn
))
14401 if (!NONDEBUG_INSN_P (tem_insn
))
14403 if (tem_insn
== BB_HEAD (bb
))
14407 if (dead_or_set_p (tem_insn
, piece
)
14408 || reg_bitfield_target_p (piece
,
14409 PATTERN (tem_insn
)))
14411 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14424 /* Any other notes should not be present at this point in the
14426 gcc_unreachable ();
14431 XEXP (note
, 1) = REG_NOTES (place
);
14432 REG_NOTES (place
) = note
;
14436 add_shallow_copy_of_reg_note (place2
, note
);
14440 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14441 I3, I2, and I1 to new locations. This is also called to add a link
14442 pointing at I3 when I3's destination is changed. */
14445 distribute_links (struct insn_link
*links
)
14447 struct insn_link
*link
, *next_link
;
14449 for (link
= links
; link
; link
= next_link
)
14451 rtx_insn
*place
= 0;
14455 next_link
= link
->next
;
14457 /* If the insn that this link points to is a NOTE, ignore it. */
14458 if (NOTE_P (link
->insn
))
14462 rtx pat
= PATTERN (link
->insn
);
14463 if (GET_CODE (pat
) == SET
)
14465 else if (GET_CODE (pat
) == PARALLEL
)
14468 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14470 set
= XVECEXP (pat
, 0, i
);
14471 if (GET_CODE (set
) != SET
)
14474 reg
= SET_DEST (set
);
14475 while (GET_CODE (reg
) == ZERO_EXTRACT
14476 || GET_CODE (reg
) == STRICT_LOW_PART
14477 || GET_CODE (reg
) == SUBREG
)
14478 reg
= XEXP (reg
, 0);
14483 if (REGNO (reg
) == link
->regno
)
14486 if (i
== XVECLEN (pat
, 0))
14492 reg
= SET_DEST (set
);
14494 while (GET_CODE (reg
) == ZERO_EXTRACT
14495 || GET_CODE (reg
) == STRICT_LOW_PART
14496 || GET_CODE (reg
) == SUBREG
)
14497 reg
= XEXP (reg
, 0);
14499 /* A LOG_LINK is defined as being placed on the first insn that uses
14500 a register and points to the insn that sets the register. Start
14501 searching at the next insn after the target of the link and stop
14502 when we reach a set of the register or the end of the basic block.
14504 Note that this correctly handles the link that used to point from
14505 I3 to I2. Also note that not much searching is typically done here
14506 since most links don't point very far away. */
14508 for (insn
= NEXT_INSN (link
->insn
);
14509 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14510 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14511 insn
= NEXT_INSN (insn
))
14512 if (DEBUG_INSN_P (insn
))
14514 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14516 if (reg_referenced_p (reg
, PATTERN (insn
)))
14520 else if (CALL_P (insn
)
14521 && find_reg_fusage (insn
, USE
, reg
))
14526 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14529 /* If we found a place to put the link, place it there unless there
14530 is already a link to the same insn as LINK at that point. */
14534 struct insn_link
*link2
;
14536 FOR_EACH_LOG_LINK (link2
, place
)
14537 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14542 link
->next
= LOG_LINKS (place
);
14543 LOG_LINKS (place
) = link
;
14545 /* Set added_links_insn to the earliest insn we added a
14547 if (added_links_insn
== 0
14548 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14549 added_links_insn
= place
;
14555 /* Check for any register or memory mentioned in EQUIV that is not
14556 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14557 of EXPR where some registers may have been replaced by constants. */
14560 unmentioned_reg_p (rtx equiv
, rtx expr
)
14562 subrtx_iterator::array_type array
;
14563 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14565 const_rtx x
= *iter
;
14566 if ((REG_P (x
) || MEM_P (x
))
14567 && !reg_mentioned_p (x
, expr
))
14573 DEBUG_FUNCTION
void
14574 dump_combine_stats (FILE *file
)
14578 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14579 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14583 dump_combine_total_stats (FILE *file
)
14587 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14588 total_attempts
, total_merges
, total_extras
, total_successes
);
14591 /* Try combining insns through substitution. */
14592 static unsigned int
14593 rest_of_handle_combine (void)
14595 int rebuild_jump_labels_after_combine
;
14597 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14598 df_note_add_problem ();
14601 regstat_init_n_sets_and_refs ();
14602 reg_n_sets_max
= max_reg_num ();
14604 rebuild_jump_labels_after_combine
14605 = combine_instructions (get_insns (), max_reg_num ());
14607 /* Combining insns may have turned an indirect jump into a
14608 direct jump. Rebuild the JUMP_LABEL fields of jumping
14610 if (rebuild_jump_labels_after_combine
)
14612 if (dom_info_available_p (CDI_DOMINATORS
))
14613 free_dominance_info (CDI_DOMINATORS
);
14614 timevar_push (TV_JUMP
);
14615 rebuild_jump_labels (get_insns ());
14617 timevar_pop (TV_JUMP
);
14620 regstat_free_n_sets_and_refs ();
14626 const pass_data pass_data_combine
=
14628 RTL_PASS
, /* type */
14629 "combine", /* name */
14630 OPTGROUP_NONE
, /* optinfo_flags */
14631 TV_COMBINE
, /* tv_id */
14632 PROP_cfglayout
, /* properties_required */
14633 0, /* properties_provided */
14634 0, /* properties_destroyed */
14635 0, /* todo_flags_start */
14636 TODO_df_finish
, /* todo_flags_finish */
14639 class pass_combine
: public rtl_opt_pass
14642 pass_combine (gcc::context
*ctxt
)
14643 : rtl_opt_pass (pass_data_combine
, ctxt
)
14646 /* opt_pass methods: */
14647 virtual bool gate (function
*) { return (optimize
> 0); }
14648 virtual unsigned int execute (function
*)
14650 return rest_of_handle_combine ();
14653 }; // class pass_combine
14655 } // anon namespace
14658 make_pass_combine (gcc::context
*ctxt
)
14660 return new pass_combine (ctxt
);