1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* Basic block in which we are performing combines. */
306 static basic_block this_basic_block
;
307 static bool optimize_this_for_speed_p
;
310 /* Length of the currently allocated uid_insn_cost array. */
312 static int max_uid_known
;
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
317 static int *uid_insn_cost
;
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
325 struct insn_link
*next
;
328 static struct insn_link
**uid_log_links
;
331 insn_uid_check (const_rtx insn
)
333 int uid
= INSN_UID (insn
);
334 gcc_checking_assert (uid
<= max_uid_known
);
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
346 static struct obstack insn_link_obstack
;
348 /* Allocate a link. */
350 static inline struct insn_link
*
351 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
354 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
355 sizeof (struct insn_link
));
362 /* Incremented for each basic block. */
364 static int label_tick
;
366 /* Reset to label_tick for each extended basic block in scanning order. */
368 static int label_tick_ebb_start
;
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
373 static machine_mode nonzero_bits_mode
;
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
381 static int nonzero_sign_valid
;
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
387 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
393 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
394 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
407 rtx_insn
*other_insn
;
410 static struct undobuf undobuf
;
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
415 static int n_occurrences
;
417 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
419 unsigned HOST_WIDE_INT
,
420 unsigned HOST_WIDE_INT
*);
421 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
423 unsigned int, unsigned int *);
424 static void do_SUBST (rtx
*, rtx
);
425 static void do_SUBST_INT (int *, int);
426 static void init_reg_last (void);
427 static void setup_incoming_promotions (rtx_insn
*);
428 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
429 static int cant_combine_insn_p (rtx_insn
*);
430 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
431 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
432 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
433 static int contains_muldiv (rtx
);
434 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
436 static void undo_all (void);
437 static void undo_commit (void);
438 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
439 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
440 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
441 static rtx
simplify_if_then_else (rtx
);
442 static rtx
simplify_set (rtx
);
443 static rtx
simplify_logical (rtx
);
444 static rtx
expand_compound_operation (rtx
);
445 static const_rtx
expand_field_assignment (const_rtx
);
446 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
447 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
448 static rtx
extract_left_shift (rtx
, int);
449 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
450 unsigned HOST_WIDE_INT
*);
451 static rtx
canon_reg_for_combine (rtx
, rtx
);
452 static rtx
force_to_mode (rtx
, machine_mode
,
453 unsigned HOST_WIDE_INT
, int);
454 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
455 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
456 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
457 static rtx
make_field_assignment (rtx
);
458 static rtx
apply_distributive_law (rtx
);
459 static rtx
distribute_and_simplify_rtx (rtx
, int);
460 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
461 unsigned HOST_WIDE_INT
);
462 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
463 unsigned HOST_WIDE_INT
);
464 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
465 HOST_WIDE_INT
, machine_mode
, int *);
466 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
467 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
469 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
470 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
471 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
473 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
474 static void update_table_tick (rtx
);
475 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
476 static void check_promoted_subreg (rtx_insn
*, rtx
);
477 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
478 static void record_dead_and_set_regs (rtx_insn
*);
479 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
480 static rtx
get_last_value (const_rtx
);
481 static int use_crosses_set_p (const_rtx
, int);
482 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
483 static int reg_dead_at_p (rtx
, rtx_insn
*);
484 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
485 static int reg_bitfield_target_p (rtx
, rtx
);
486 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
487 static void distribute_links (struct insn_link
*);
488 static void mark_used_regs_combine (rtx
);
489 static void record_promoted_value (rtx_insn
*, rtx
);
490 static bool unmentioned_reg_p (rtx
, rtx
);
491 static void record_truncated_values (rtx
*, void *);
492 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
493 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
514 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
520 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
521 bool op0_preserve_value
)
523 int code_int
= (int)*code
;
524 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
525 *code
= (enum rtx_code
)code_int
;
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
535 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
540 ret
= split_insns (pattern
, insn
);
541 nregs
= max_reg_num ();
542 if (nregs
> reg_stat
.length ())
543 reg_stat
.safe_grow_cleared (nregs
);
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
554 find_single_use_1 (rtx dest
, rtx
*loc
)
557 enum rtx_code code
= GET_CODE (x
);
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
577 if (GET_CODE (SET_DEST (x
)) != CC0
578 && GET_CODE (SET_DEST (x
)) != PC
579 && !REG_P (SET_DEST (x
))
580 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
581 && REG_P (SUBREG_REG (SET_DEST (x
)))
582 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
583 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
584 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
585 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_rtx_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_rtx_costs. */
892 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
895 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
896 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
897 ? new_i2_cost
+ new_i3_cost
: 0;
901 new_cost
= new_i3_cost
;
905 if (undobuf
.other_insn
)
907 int old_other_cost
, new_other_cost
;
909 old_other_cost
= INSN_COST (undobuf
.other_insn
);
910 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
911 if (old_other_cost
> 0 && new_other_cost
> 0)
913 old_cost
+= old_other_cost
;
914 new_cost
+= new_other_cost
;
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
922 int reject
= old_cost
> 0 && new_cost
> old_cost
;
926 fprintf (dump_file
, "%s combination of insns ",
927 reject
? "rejecting" : "allowing");
929 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
930 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
931 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
932 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
934 fprintf (dump_file
, "original costs ");
936 fprintf (dump_file
, "%d + ", i0_cost
);
937 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
938 fprintf (dump_file
, "%d + ", i1_cost
);
939 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
942 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
943 new_i2_cost
, new_i3_cost
, new_cost
);
945 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
951 /* Update the uid_insn_cost array with the replacement costs. */
952 INSN_COST (i2
) = new_i2_cost
;
953 INSN_COST (i3
) = new_i3_cost
;
965 /* Delete any insns that copy a register to itself. */
968 delete_noop_moves (void)
970 rtx_insn
*insn
, *next
;
973 FOR_EACH_BB_FN (bb
, cfun
)
975 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
977 next
= NEXT_INSN (insn
);
978 if (INSN_P (insn
) && noop_move_p (insn
))
981 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
983 delete_insn_and_edges (insn
);
990 /* Return false if we do not want to (or cannot) combine DEF. */
992 can_combine_def_p (df_ref def
)
994 /* Do not consider if it is pre/post modification in MEM. */
995 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
998 unsigned int regno
= DF_REF_REGNO (def
);
1000 /* Do not combine frame pointer adjustments. */
1001 if ((regno
== FRAME_POINTER_REGNUM
1002 && (!reload_completed
|| frame_pointer_needed
))
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 && regno
== HARD_FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1007 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1013 /* Return false if we do not want to (or cannot) combine USE. */
1015 can_combine_use_p (df_ref use
)
1017 /* Do not consider the usage of the stack pointer by function call. */
1018 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1024 /* Fill in log links field for all insns. */
1027 create_log_links (void)
1030 rtx_insn
**next_use
;
1034 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1045 FOR_EACH_BB_FN (bb
, cfun
)
1047 FOR_BB_INSNS_REVERSE (bb
, insn
)
1049 if (!NONDEBUG_INSN_P (insn
))
1052 /* Log links are created only once. */
1053 gcc_assert (!LOG_LINKS (insn
));
1055 FOR_EACH_INSN_DEF (def
, insn
)
1057 unsigned int regno
= DF_REF_REGNO (def
);
1060 if (!next_use
[regno
])
1063 if (!can_combine_def_p (def
))
1066 use_insn
= next_use
[regno
];
1067 next_use
[regno
] = NULL
;
1069 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1079 if (regno
< FIRST_PSEUDO_REGISTER
1080 && asm_noperands (PATTERN (use_insn
)) >= 0)
1083 /* Don't add duplicate links between instructions. */
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, use_insn
)
1086 if (insn
== links
->insn
&& regno
== links
->regno
)
1090 LOG_LINKS (use_insn
)
1091 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1094 FOR_EACH_INSN_USE (use
, insn
)
1095 if (can_combine_use_p (use
))
1096 next_use
[DF_REF_REGNO (use
)] = insn
;
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1111 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1113 struct insn_link
*links
;
1114 FOR_EACH_LOG_LINK (links
, b
)
1115 if (links
->insn
== a
)
1117 if (HAVE_cc0
&& sets_cc0_p (a
))
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1128 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1130 rtx_insn
*insn
, *next
;
1132 struct insn_link
*links
, *nextlinks
;
1134 basic_block last_bb
;
1136 int new_direct_jump_p
= 0;
1138 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1139 first
= NEXT_INSN (first
);
1143 combine_attempts
= 0;
1146 combine_successes
= 0;
1148 rtl_hooks
= combine_rtl_hooks
;
1150 reg_stat
.safe_grow_cleared (nregs
);
1152 init_recog_no_volatile ();
1154 /* Allocate array for insn info. */
1155 max_uid_known
= get_max_uid ();
1156 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1157 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1158 gcc_obstack_init (&insn_link_obstack
);
1160 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1165 nonzero_sign_valid
= 0;
1166 label_tick
= label_tick_ebb_start
= 1;
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1175 setup_incoming_promotions (first
);
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1178 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1180 create_log_links ();
1181 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1183 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1188 if (!single_pred_p (this_basic_block
)
1189 || single_pred (this_basic_block
) != last_bb
)
1190 label_tick_ebb_start
= label_tick
;
1191 last_bb
= this_basic_block
;
1193 FOR_BB_INSNS (this_basic_block
, insn
)
1194 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1198 subst_low_luid
= DF_INSN_LUID (insn
);
1201 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1203 record_dead_and_set_regs (insn
);
1206 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1207 if (REG_NOTE_KIND (links
) == REG_INC
)
1208 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1211 /* Record the current insn_rtx_cost of this instruction. */
1212 if (NONJUMP_INSN_P (insn
))
1213 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1214 optimize_this_for_speed_p
);
1216 fprintf (dump_file
, "insn_cost %d: %d\n",
1217 INSN_UID (insn
), INSN_COST (insn
));
1221 nonzero_sign_valid
= 1;
1223 /* Now scan all the insns in forward order. */
1224 label_tick
= label_tick_ebb_start
= 1;
1226 setup_incoming_promotions (first
);
1227 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1228 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1230 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1232 rtx_insn
*last_combined_insn
= NULL
;
1233 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1238 if (!single_pred_p (this_basic_block
)
1239 || single_pred (this_basic_block
) != last_bb
)
1240 label_tick_ebb_start
= label_tick
;
1241 last_bb
= this_basic_block
;
1243 rtl_profile_for_bb (this_basic_block
);
1244 for (insn
= BB_HEAD (this_basic_block
);
1245 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1246 insn
= next
? next
: NEXT_INSN (insn
))
1249 if (!NONDEBUG_INSN_P (insn
))
1252 while (last_combined_insn
1253 && last_combined_insn
->deleted ())
1254 last_combined_insn
= PREV_INSN (last_combined_insn
);
1255 if (last_combined_insn
== NULL_RTX
1256 || BARRIER_P (last_combined_insn
)
1257 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1258 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1259 last_combined_insn
= insn
;
1261 /* See if we know about function return values before this
1262 insn based upon SUBREG flags. */
1263 check_promoted_subreg (insn
, PATTERN (insn
));
1265 /* See if we can find hardregs and subreg of pseudos in
1266 narrower modes. This could help turning TRUNCATEs
1268 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1270 /* Try this insn with each insn it links back to. */
1272 FOR_EACH_LOG_LINK (links
, insn
)
1273 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1274 NULL
, &new_direct_jump_p
,
1275 last_combined_insn
)) != 0)
1277 statistics_counter_event (cfun
, "two-insn combine", 1);
1281 /* Try each sequence of three linked insns ending with this one. */
1283 if (max_combine
>= 3)
1284 FOR_EACH_LOG_LINK (links
, insn
)
1286 rtx_insn
*link
= links
->insn
;
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 FOR_EACH_LOG_LINK (nextlinks
, link
)
1294 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1295 NULL
, &new_direct_jump_p
,
1296 last_combined_insn
)) != 0)
1298 statistics_counter_event (cfun
, "three-insn combine", 1);
1303 /* Try to combine a jump insn that uses CC0
1304 with a preceding insn that sets CC0, and maybe with its
1305 logical predecessor as well.
1306 This is how we make decrement-and-branch insns.
1307 We need this special code because data flow connections
1308 via CC0 do not get entered in LOG_LINKS. */
1312 && (prev
= prev_nonnote_insn (insn
)) != 0
1313 && NONJUMP_INSN_P (prev
)
1314 && sets_cc0_p (PATTERN (prev
)))
1316 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1318 last_combined_insn
)) != 0)
1321 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1322 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1323 NULL
, &new_direct_jump_p
,
1324 last_combined_insn
)) != 0)
1328 /* Do the same for an insn that explicitly references CC0. */
1329 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1330 && (prev
= prev_nonnote_insn (insn
)) != 0
1331 && NONJUMP_INSN_P (prev
)
1332 && sets_cc0_p (PATTERN (prev
))
1333 && GET_CODE (PATTERN (insn
)) == SET
1334 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1336 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1338 last_combined_insn
)) != 0)
1341 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1342 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1343 NULL
, &new_direct_jump_p
,
1344 last_combined_insn
)) != 0)
1348 /* Finally, see if any of the insns that this insn links to
1349 explicitly references CC0. If so, try this insn, that insn,
1350 and its predecessor if it sets CC0. */
1353 FOR_EACH_LOG_LINK (links
, insn
)
1354 if (NONJUMP_INSN_P (links
->insn
)
1355 && GET_CODE (PATTERN (links
->insn
)) == SET
1356 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1357 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1358 && NONJUMP_INSN_P (prev
)
1359 && sets_cc0_p (PATTERN (prev
))
1360 && (next
= try_combine (insn
, links
->insn
,
1361 prev
, NULL
, &new_direct_jump_p
,
1362 last_combined_insn
)) != 0)
1366 /* Try combining an insn with two different insns whose results it
1368 if (max_combine
>= 3)
1369 FOR_EACH_LOG_LINK (links
, insn
)
1370 for (nextlinks
= links
->next
; nextlinks
;
1371 nextlinks
= nextlinks
->next
)
1372 if ((next
= try_combine (insn
, links
->insn
,
1373 nextlinks
->insn
, NULL
,
1375 last_combined_insn
)) != 0)
1378 statistics_counter_event (cfun
, "three-insn combine", 1);
1382 /* Try four-instruction combinations. */
1383 if (max_combine
>= 4)
1384 FOR_EACH_LOG_LINK (links
, insn
)
1386 struct insn_link
*next1
;
1387 rtx_insn
*link
= links
->insn
;
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1394 FOR_EACH_LOG_LINK (next1
, link
)
1396 rtx_insn
*link1
= next1
->insn
;
1399 /* I0 -> I1 -> I2 -> I3. */
1400 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1401 if ((next
= try_combine (insn
, link
, link1
,
1404 last_combined_insn
)) != 0)
1406 statistics_counter_event (cfun
, "four-insn combine", 1);
1409 /* I0, I1 -> I2, I2 -> I3. */
1410 for (nextlinks
= next1
->next
; nextlinks
;
1411 nextlinks
= nextlinks
->next
)
1412 if ((next
= try_combine (insn
, link
, link1
,
1415 last_combined_insn
)) != 0)
1417 statistics_counter_event (cfun
, "four-insn combine", 1);
1422 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1424 rtx_insn
*link1
= next1
->insn
;
1427 /* I0 -> I2; I1, I2 -> I3. */
1428 FOR_EACH_LOG_LINK (nextlinks
, link
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1437 /* I0 -> I1; I1, I2 -> I3. */
1438 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1439 if ((next
= try_combine (insn
, link
, link1
,
1442 last_combined_insn
)) != 0)
1444 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1451 FOR_EACH_LOG_LINK (links
, insn
)
1454 rtx_insn
*temp
= links
->insn
;
1455 if ((set
= single_set (temp
)) != 0
1456 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1457 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1460 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1461 && (GET_MODE (note
) == VOIDmode
1462 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1463 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1464 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1465 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1466 == GET_MODE (note
))))))
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1471 rtx orig_src
= SET_SRC (set
);
1472 rtx orig_dest
= SET_DEST (set
);
1473 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1474 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1475 SET_SRC (set
) = note
;
1477 i2mod_old_rhs
= copy_rtx (orig_src
);
1478 i2mod_new_rhs
= copy_rtx (note
);
1479 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1481 last_combined_insn
);
1485 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1488 SET_SRC (set
) = orig_src
;
1489 SET_DEST (set
) = orig_dest
;
1494 record_dead_and_set_regs (insn
);
1501 default_rtl_profile ();
1503 new_direct_jump_p
|= purge_all_dead_edges ();
1504 delete_noop_moves ();
1507 obstack_free (&insn_link_obstack
, NULL
);
1508 free (uid_log_links
);
1509 free (uid_insn_cost
);
1510 reg_stat
.release ();
1513 struct undo
*undo
, *next
;
1514 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1522 total_attempts
+= combine_attempts
;
1523 total_merges
+= combine_merges
;
1524 total_extras
+= combine_extras
;
1525 total_successes
+= combine_successes
;
1527 nonzero_sign_valid
= 0;
1528 rtl_hooks
= general_rtl_hooks
;
1530 /* Make recognizer allow volatile MEMs again. */
1533 return new_direct_jump_p
;
1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1539 init_reg_last (void)
1544 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1545 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1548 /* Set up any promoted values for incoming argument registers. */
1551 setup_incoming_promotions (rtx_insn
*first
)
1554 bool strictly_local
= false;
1556 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1557 arg
= DECL_CHAIN (arg
))
1559 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1561 machine_mode mode1
, mode2
, mode3
, mode4
;
1563 /* Only continue if the incoming argument is in a register. */
1567 /* Determine, if possible, whether all call sites of the current
1568 function lie within the current compilation unit. (This does
1569 take into account the exporting of a function via taking its
1570 address, and so forth.) */
1571 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1573 /* The mode and signedness of the argument before any promotions happen
1574 (equal to the mode of the pseudo holding it at that stage). */
1575 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1576 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1578 /* The mode and signedness of the argument after any source language and
1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1580 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1581 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1583 /* The mode and signedness of the argument as it is actually passed,
1584 see assign_parm_setup_reg in function.c. */
1585 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1586 TREE_TYPE (cfun
->decl
), 0);
1588 /* The mode of the register in which the argument is being passed. */
1589 mode4
= GET_MODE (reg
);
1591 /* Eliminate sign extensions in the callee when:
1592 (a) A mode promotion has occurred; */
1595 /* (b) The mode of the register is the same as the mode of
1596 the argument as it is passed; */
1599 /* (c) There's no language level extension; */
1602 /* (c.1) All callers are from the current compilation unit. If that's
1603 the case we don't have to rely on an ABI, we only have to know
1604 what we're generating right now, and we know that we will do the
1605 mode1 to mode2 promotion with the given sign. */
1606 else if (!strictly_local
)
1608 /* (c.2) The combination of the two promotions is useful. This is
1609 true when the signs match, or if the first promotion is unsigned.
1610 In the later case, (sign_extend (zero_extend x)) is the same as
1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1617 /* Record that the value was promoted from mode1 to mode3,
1618 so that any sign extension at the head of the current
1619 function may be eliminated. */
1620 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1621 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1622 record_value_for_reg (reg
, first
, x
);
1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1628 because some machines (maybe most) will actually do the sign-extension and
1629 this is the conservative approach.
1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1635 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1637 if (GET_MODE_PRECISION (mode
) < prec
1638 && CONST_INT_P (src
)
1640 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1641 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1650 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1653 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1654 unsigned HOST_WIDE_INT bits
= 0;
1655 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1656 unsigned int num
= 0;
1659 reg_equal
= XEXP (reg_equal_note
, 0);
1661 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1663 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1665 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1668 /* Don't call nonzero_bits if it cannot change anything. */
1669 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1671 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1672 if (reg_equal
&& bits
)
1673 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1674 rsp
->nonzero_bits
|= bits
;
1677 /* Don't call num_sign_bit_copies if it cannot change anything. */
1678 if (rsp
->sign_bit_copies
!= 1)
1680 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1681 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1683 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1684 if (num
== 0 || numeq
> num
)
1687 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1688 rsp
->sign_bit_copies
= num
;
1692 /* Called via note_stores. If X is a pseudo that is narrower than
1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1695 If we are setting only a portion of X and we can't figure out what
1696 portion, assume all bits will be used since we don't know what will
1699 Similarly, set how many bits of X are known to be copies of the sign bit
1700 at all locations in the function. This is the smallest number implied
1704 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1706 rtx_insn
*insn
= (rtx_insn
*) data
;
1709 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1710 /* If this register is undefined at the start of the file, we can't
1711 say what its contents were. */
1712 && ! REGNO_REG_SET_P
1713 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1714 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1716 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1718 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1720 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1721 rsp
->sign_bit_copies
= 1;
1725 /* If this register is being initialized using itself, and the
1726 register is uninitialized in this basic block, and there are
1727 no LOG_LINKS which set the register, then part of the
1728 register is uninitialized. In that case we can't assume
1729 anything about the number of nonzero bits.
1731 ??? We could do better if we checked this in
1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1733 could avoid making assumptions about the insn which initially
1734 sets the register, while still using the information in other
1735 insns. We would have to be careful to check every insn
1736 involved in the combination. */
1739 && reg_referenced_p (x
, PATTERN (insn
))
1740 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1743 struct insn_link
*link
;
1745 FOR_EACH_LOG_LINK (link
, insn
)
1746 if (dead_or_set_p (link
->insn
, x
))
1750 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1751 rsp
->sign_bit_copies
= 1;
1756 /* If this is a complex assignment, see if we can convert it into a
1757 simple assignment. */
1758 set
= expand_field_assignment (set
);
1760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1761 set what we know about X. */
1763 if (SET_DEST (set
) == x
1764 || (paradoxical_subreg_p (SET_DEST (set
))
1765 && SUBREG_REG (SET_DEST (set
)) == x
))
1766 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1769 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1770 rsp
->sign_bit_copies
= 1;
1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1776 optionally insns that were previously combined into I3 or that will be
1777 combined into the merger of INSN and I3. The order is PRED, PRED2,
1778 INSN, SUCC, SUCC2, I3.
1780 Return 0 if the combination is not allowed for any reason.
1782 If the combination is allowed, *PDEST will be set to the single
1783 destination of INSN and *PSRC to the single source, and this function
1787 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1788 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1789 rtx
*pdest
, rtx
*psrc
)
1796 bool all_adjacent
= true;
1797 int (*is_volatile_p
) (const_rtx
);
1803 if (next_active_insn (succ2
) != i3
)
1804 all_adjacent
= false;
1805 if (next_active_insn (succ
) != succ2
)
1806 all_adjacent
= false;
1808 else if (next_active_insn (succ
) != i3
)
1809 all_adjacent
= false;
1810 if (next_active_insn (insn
) != succ
)
1811 all_adjacent
= false;
1813 else if (next_active_insn (insn
) != i3
)
1814 all_adjacent
= false;
1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1817 or a PARALLEL consisting of such a SET and CLOBBERs.
1819 If INSN has CLOBBER parallel parts, ignore them for our processing.
1820 By definition, these happen during the execution of the insn. When it
1821 is merged with another insn, all bets are off. If they are, in fact,
1822 needed and aren't also supplied in I3, they may be added by
1823 recog_for_combine. Otherwise, it won't match.
1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1828 Get the source and destination of INSN. If more than one, can't
1831 if (GET_CODE (PATTERN (insn
)) == SET
)
1832 set
= PATTERN (insn
);
1833 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1834 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1836 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1838 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1840 switch (GET_CODE (elt
))
1842 /* This is important to combine floating point insns
1843 for the SH4 port. */
1845 /* Combining an isolated USE doesn't make sense.
1846 We depend here on combinable_i3pat to reject them. */
1847 /* The code below this loop only verifies that the inputs of
1848 the SET in INSN do not change. We call reg_set_between_p
1849 to verify that the REG in the USE does not change between
1851 If the USE in INSN was for a pseudo register, the matching
1852 insn pattern will likely match any register; combining this
1853 with any other USE would only be safe if we knew that the
1854 used registers have identical values, or if there was
1855 something to tell them apart, e.g. different modes. For
1856 now, we forgo such complicated tests and simply disallow
1857 combining of USES of pseudo registers with any other USE. */
1858 if (REG_P (XEXP (elt
, 0))
1859 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1861 rtx i3pat
= PATTERN (i3
);
1862 int i
= XVECLEN (i3pat
, 0) - 1;
1863 unsigned int regno
= REGNO (XEXP (elt
, 0));
1867 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1869 if (GET_CODE (i3elt
) == USE
1870 && REG_P (XEXP (i3elt
, 0))
1871 && (REGNO (XEXP (i3elt
, 0)) == regno
1872 ? reg_set_between_p (XEXP (elt
, 0),
1873 PREV_INSN (insn
), i3
)
1874 : regno
>= FIRST_PSEUDO_REGISTER
))
1881 /* We can ignore CLOBBERs. */
1886 /* Ignore SETs whose result isn't used but not those that
1887 have side-effects. */
1888 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1889 && insn_nothrow_p (insn
)
1890 && !side_effects_p (elt
))
1893 /* If we have already found a SET, this is a second one and
1894 so we cannot combine with this insn. */
1902 /* Anything else means we can't combine. */
1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1909 so don't do anything with it. */
1910 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1919 /* The simplification in expand_field_assignment may call back to
1920 get_last_value, so set safe guard here. */
1921 subst_low_luid
= DF_INSN_LUID (insn
);
1923 set
= expand_field_assignment (set
);
1924 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1926 /* Do not eliminate user-specified register if it is in an
1927 asm input because we may break the register asm usage defined
1928 in GCC manual if allow to do so.
1929 Be aware that this may cover more cases than we expect but this
1930 should be harmless. */
1931 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1932 && extract_asm_operands (PATTERN (i3
)))
1935 /* Don't eliminate a store in the stack pointer. */
1936 if (dest
== stack_pointer_rtx
1937 /* Don't combine with an insn that sets a register to itself if it has
1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1939 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1940 /* Can't merge an ASM_OPERANDS. */
1941 || GET_CODE (src
) == ASM_OPERANDS
1942 /* Can't merge a function call. */
1943 || GET_CODE (src
) == CALL
1944 /* Don't eliminate a function call argument. */
1946 && (find_reg_fusage (i3
, USE
, dest
)
1948 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1949 && global_regs
[REGNO (dest
)])))
1950 /* Don't substitute into an incremented register. */
1951 || FIND_REG_INC_NOTE (i3
, dest
)
1952 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1953 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1954 /* Don't substitute into a non-local goto, this confuses CFG. */
1955 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1956 /* Make sure that DEST is not used after INSN but before SUCC, or
1957 between SUCC and SUCC2. */
1958 || (succ
&& reg_used_between_p (dest
, insn
, succ
))
1959 || (succ2
&& reg_used_between_p (dest
, succ
, succ2
))
1960 /* Make sure that DEST is not used after SUCC but before I3. */
1963 && (reg_used_between_p (dest
, succ2
, i3
)
1964 || reg_used_between_p (dest
, succ
, succ2
)))
1965 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1966 /* Make sure that the value that is to be substituted for the register
1967 does not use any registers whose values alter in between. However,
1968 If the insns are adjacent, a use can't cross a set even though we
1969 think it might (this can happen for a sequence of insns each setting
1970 the same destination; last_set of that register might point to
1971 a NOTE). If INSN has a REG_EQUIV note, the register is always
1972 equivalent to the memory so the substitution is valid even if there
1973 are intervening stores. Also, don't move a volatile asm or
1974 UNSPEC_VOLATILE across any other insns. */
1977 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1978 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1979 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1980 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1981 /* Don't combine across a CALL_INSN, because that would possibly
1982 change whether the life span of some REGs crosses calls or not,
1983 and it is a pain to update that information.
1984 Exception: if source is a constant, moving it later can't hurt.
1985 Accept that as a special case. */
1986 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1989 /* DEST must either be a REG or CC0. */
1992 /* If register alignment is being enforced for multi-word items in all
1993 cases except for parameters, it is possible to have a register copy
1994 insn referencing a hard register that is not allowed to contain the
1995 mode being copied and which would not be valid as an operand of most
1996 insns. Eliminate this problem by not combining with such an insn.
1998 Also, on some machines we don't want to extend the life of a hard
2002 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2003 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2004 /* Don't extend the life of a hard register unless it is
2005 user variable (if we have few registers) or it can't
2006 fit into the desired register (meaning something special
2008 Also avoid substituting a return register into I3, because
2009 reload can't handle a conflict with constraints of other
2011 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2012 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2015 else if (GET_CODE (dest
) != CC0
)
2019 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2020 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2021 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2023 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2025 /* If the clobber represents an earlyclobber operand, we must not
2026 substitute an expression containing the clobbered register.
2027 As we do not analyze the constraint strings here, we have to
2028 make the conservative assumption. However, if the register is
2029 a fixed hard reg, the clobber cannot represent any operand;
2030 we leave it up to the machine description to either accept or
2031 reject use-and-clobber patterns. */
2033 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2034 || !fixed_regs
[REGNO (reg
)])
2035 if (reg_overlap_mentioned_p (reg
, src
))
2039 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2040 or not), reject, unless nothing volatile comes between it and I3 */
2042 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2044 /* Make sure neither succ nor succ2 contains a volatile reference. */
2045 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2047 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2049 /* We'll check insns between INSN and I3 below. */
2052 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2053 to be an explicit register variable, and was chosen for a reason. */
2055 if (GET_CODE (src
) == ASM_OPERANDS
2056 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2059 /* If INSN contains volatile references (specifically volatile MEMs),
2060 we cannot combine across any other volatile references.
2061 Even if INSN doesn't contain volatile references, any intervening
2062 volatile insn might affect machine state. */
2064 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2068 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2069 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2072 /* If INSN contains an autoincrement or autodecrement, make sure that
2073 register is not used between there and I3, and not already used in
2074 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2075 Also insist that I3 not be a jump; if it were one
2076 and the incremented register were spilled, we would lose. */
2079 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2080 if (REG_NOTE_KIND (link
) == REG_INC
2082 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2083 || (pred
!= NULL_RTX
2084 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2085 || (pred2
!= NULL_RTX
2086 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2087 || (succ
!= NULL_RTX
2088 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2089 || (succ2
!= NULL_RTX
2090 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2091 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2094 /* Don't combine an insn that follows a CC0-setting insn.
2095 An insn that uses CC0 must not be separated from the one that sets it.
2096 We do, however, allow I2 to follow a CC0-setting insn if that insn
2097 is passed as I1; in that case it will be deleted also.
2098 We also allow combining in this case if all the insns are adjacent
2099 because that would leave the two CC0 insns adjacent as well.
2100 It would be more logical to test whether CC0 occurs inside I1 or I2,
2101 but that would be much slower, and this ought to be equivalent. */
2105 p
= prev_nonnote_insn (insn
);
2106 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2111 /* If we get here, we have passed all the tests and the combination is
2120 /* LOC is the location within I3 that contains its pattern or the component
2121 of a PARALLEL of the pattern. We validate that it is valid for combining.
2123 One problem is if I3 modifies its output, as opposed to replacing it
2124 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2125 doing so would produce an insn that is not equivalent to the original insns.
2129 (set (reg:DI 101) (reg:DI 100))
2130 (set (subreg:SI (reg:DI 101) 0) <foo>)
2132 This is NOT equivalent to:
2134 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2135 (set (reg:DI 101) (reg:DI 100))])
2137 Not only does this modify 100 (in which case it might still be valid
2138 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2140 We can also run into a problem if I2 sets a register that I1
2141 uses and I1 gets directly substituted into I3 (not via I2). In that
2142 case, we would be getting the wrong value of I2DEST into I3, so we
2143 must reject the combination. This case occurs when I2 and I1 both
2144 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2145 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2146 of a SET must prevent combination from occurring. The same situation
2147 can occur for I0, in which case I0_NOT_IN_SRC is set.
2149 Before doing the above check, we first try to expand a field assignment
2150 into a set of logical operations.
2152 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2153 we place a register that is both set and used within I3. If more than one
2154 such register is detected, we fail.
2156 Return 1 if the combination is valid, zero otherwise. */
2159 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2160 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2164 if (GET_CODE (x
) == SET
)
2167 rtx dest
= SET_DEST (set
);
2168 rtx src
= SET_SRC (set
);
2169 rtx inner_dest
= dest
;
2172 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2173 || GET_CODE (inner_dest
) == SUBREG
2174 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2175 inner_dest
= XEXP (inner_dest
, 0);
2177 /* Check for the case where I3 modifies its output, as discussed
2178 above. We don't want to prevent pseudos from being combined
2179 into the address of a MEM, so only prevent the combination if
2180 i1 or i2 set the same MEM. */
2181 if ((inner_dest
!= dest
&&
2182 (!MEM_P (inner_dest
)
2183 || rtx_equal_p (i2dest
, inner_dest
)
2184 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2185 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2186 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2187 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2188 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2190 /* This is the same test done in can_combine_p except we can't test
2191 all_adjacent; we don't have to, since this instruction will stay
2192 in place, thus we are not considering increasing the lifetime of
2195 Also, if this insn sets a function argument, combining it with
2196 something that might need a spill could clobber a previous
2197 function argument; the all_adjacent test in can_combine_p also
2198 checks this; here, we do a more specific test for this case. */
2200 || (REG_P (inner_dest
)
2201 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2202 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2203 GET_MODE (inner_dest
))))
2204 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2205 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2208 /* If DEST is used in I3, it is being killed in this insn, so
2209 record that for later. We have to consider paradoxical
2210 subregs here, since they kill the whole register, but we
2211 ignore partial subregs, STRICT_LOW_PART, etc.
2212 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2213 STACK_POINTER_REGNUM, since these are always considered to be
2214 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2216 if (GET_CODE (subdest
) == SUBREG
2217 && (GET_MODE_SIZE (GET_MODE (subdest
))
2218 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2219 subdest
= SUBREG_REG (subdest
);
2222 && reg_referenced_p (subdest
, PATTERN (i3
))
2223 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2224 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2225 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2226 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2227 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2228 || ! fixed_regs
[REGNO (subdest
)]))
2229 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2231 if (*pi3dest_killed
)
2234 *pi3dest_killed
= subdest
;
2238 else if (GET_CODE (x
) == PARALLEL
)
2242 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2243 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2244 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2251 /* Return 1 if X is an arithmetic expression that contains a multiplication
2252 and division. We don't count multiplications by powers of two here. */
2255 contains_muldiv (rtx x
)
2257 switch (GET_CODE (x
))
2259 case MOD
: case DIV
: case UMOD
: case UDIV
:
2263 return ! (CONST_INT_P (XEXP (x
, 1))
2264 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2267 return contains_muldiv (XEXP (x
, 0))
2268 || contains_muldiv (XEXP (x
, 1));
2271 return contains_muldiv (XEXP (x
, 0));
2277 /* Determine whether INSN can be used in a combination. Return nonzero if
2278 not. This is used in try_combine to detect early some cases where we
2279 can't perform combinations. */
2282 cant_combine_insn_p (rtx_insn
*insn
)
2287 /* If this isn't really an insn, we can't do anything.
2288 This can occur when flow deletes an insn that it has merged into an
2289 auto-increment address. */
2290 if (!NONDEBUG_INSN_P (insn
))
2293 /* Never combine loads and stores involving hard regs that are likely
2294 to be spilled. The register allocator can usually handle such
2295 reg-reg moves by tying. If we allow the combiner to make
2296 substitutions of likely-spilled regs, reload might die.
2297 As an exception, we allow combinations involving fixed regs; these are
2298 not available to the register allocator so there's no risk involved. */
2300 set
= single_set (insn
);
2303 src
= SET_SRC (set
);
2304 dest
= SET_DEST (set
);
2305 if (GET_CODE (src
) == SUBREG
)
2306 src
= SUBREG_REG (src
);
2307 if (GET_CODE (dest
) == SUBREG
)
2308 dest
= SUBREG_REG (dest
);
2309 if (REG_P (src
) && REG_P (dest
)
2310 && ((HARD_REGISTER_P (src
)
2311 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2312 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2313 || (HARD_REGISTER_P (dest
)
2314 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2315 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2321 struct likely_spilled_retval_info
2323 unsigned regno
, nregs
;
2327 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2328 hard registers that are known to be written to / clobbered in full. */
2330 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2332 struct likely_spilled_retval_info
*const info
=
2333 (struct likely_spilled_retval_info
*) data
;
2334 unsigned regno
, nregs
;
2337 if (!REG_P (XEXP (set
, 0)))
2340 if (regno
>= info
->regno
+ info
->nregs
)
2342 nregs
= REG_NREGS (x
);
2343 if (regno
+ nregs
<= info
->regno
)
2345 new_mask
= (2U << (nregs
- 1)) - 1;
2346 if (regno
< info
->regno
)
2347 new_mask
>>= info
->regno
- regno
;
2349 new_mask
<<= regno
- info
->regno
;
2350 info
->mask
&= ~new_mask
;
2353 /* Return nonzero iff part of the return value is live during INSN, and
2354 it is likely spilled. This can happen when more than one insn is needed
2355 to copy the return value, e.g. when we consider to combine into the
2356 second copy insn for a complex value. */
2359 likely_spilled_retval_p (rtx_insn
*insn
)
2361 rtx_insn
*use
= BB_END (this_basic_block
);
2364 unsigned regno
, nregs
;
2365 /* We assume here that no machine mode needs more than
2366 32 hard registers when the value overlaps with a register
2367 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2369 struct likely_spilled_retval_info info
;
2371 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2373 reg
= XEXP (PATTERN (use
), 0);
2374 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2376 regno
= REGNO (reg
);
2377 nregs
= REG_NREGS (reg
);
2380 mask
= (2U << (nregs
- 1)) - 1;
2382 /* Disregard parts of the return value that are set later. */
2386 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2388 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2391 /* Check if any of the (probably) live return value registers is
2396 if ((mask
& 1 << nregs
)
2397 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2403 /* Adjust INSN after we made a change to its destination.
2405 Changing the destination can invalidate notes that say something about
2406 the results of the insn and a LOG_LINK pointing to the insn. */
2409 adjust_for_new_dest (rtx_insn
*insn
)
2411 /* For notes, be conservative and simply remove them. */
2412 remove_reg_equal_equiv_notes (insn
);
2414 /* The new insn will have a destination that was previously the destination
2415 of an insn just above it. Call distribute_links to make a LOG_LINK from
2416 the next use of that destination. */
2418 rtx set
= single_set (insn
);
2421 rtx reg
= SET_DEST (set
);
2423 while (GET_CODE (reg
) == ZERO_EXTRACT
2424 || GET_CODE (reg
) == STRICT_LOW_PART
2425 || GET_CODE (reg
) == SUBREG
)
2426 reg
= XEXP (reg
, 0);
2427 gcc_assert (REG_P (reg
));
2429 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2431 df_insn_rescan (insn
);
2434 /* Return TRUE if combine can reuse reg X in mode MODE.
2435 ADDED_SETS is nonzero if the original set is still required. */
2437 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2445 /* Allow hard registers if the new mode is legal, and occupies no more
2446 registers than the old mode. */
2447 if (regno
< FIRST_PSEUDO_REGISTER
)
2448 return (HARD_REGNO_MODE_OK (regno
, mode
)
2449 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2451 /* Or a pseudo that is only used once. */
2452 return (regno
< reg_n_sets_max
2453 && REG_N_SETS (regno
) == 1
2455 && !REG_USERVAR_P (x
));
2459 /* Check whether X, the destination of a set, refers to part of
2460 the register specified by REG. */
2463 reg_subword_p (rtx x
, rtx reg
)
2465 /* Check that reg is an integer mode register. */
2466 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2469 if (GET_CODE (x
) == STRICT_LOW_PART
2470 || GET_CODE (x
) == ZERO_EXTRACT
)
2473 return GET_CODE (x
) == SUBREG
2474 && SUBREG_REG (x
) == reg
2475 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2478 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2479 Note that the INSN should be deleted *after* removing dead edges, so
2480 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2481 but not for a (set (pc) (label_ref FOO)). */
2484 update_cfg_for_uncondjump (rtx_insn
*insn
)
2486 basic_block bb
= BLOCK_FOR_INSN (insn
);
2487 gcc_assert (BB_END (bb
) == insn
);
2489 purge_dead_edges (bb
);
2492 if (EDGE_COUNT (bb
->succs
) == 1)
2496 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2498 /* Remove barriers from the footer if there are any. */
2499 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2500 if (BARRIER_P (insn
))
2502 if (PREV_INSN (insn
))
2503 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2505 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2506 if (NEXT_INSN (insn
))
2507 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2509 else if (LABEL_P (insn
))
2514 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2515 by an arbitrary number of CLOBBERs. */
2517 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2519 if (GET_CODE (pat
) != PARALLEL
)
2522 int len
= XVECLEN (pat
, 0);
2527 for (i
= 0; i
< n
; i
++)
2528 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2529 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2531 for ( ; i
< len
; i
++)
2532 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2533 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2539 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2540 CLOBBERs), can be split into individual SETs in that order, without
2541 changing semantics. */
2543 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2545 if (!insn_nothrow_p (insn
))
2548 rtx pat
= PATTERN (insn
);
2551 for (i
= 0; i
< n
; i
++)
2553 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2556 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2558 for (j
= i
+ 1; j
< n
; j
++)
2559 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2566 /* Try to combine the insns I0, I1 and I2 into I3.
2567 Here I0, I1 and I2 appear earlier than I3.
2568 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2571 If we are combining more than two insns and the resulting insn is not
2572 recognized, try splitting it into two insns. If that happens, I2 and I3
2573 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2574 Otherwise, I0, I1 and I2 are pseudo-deleted.
2576 Return 0 if the combination does not work. Then nothing is changed.
2577 If we did the combination, return the insn at which combine should
2580 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2581 new direct jump instruction.
2583 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2584 been I3 passed to an earlier try_combine within the same basic
2588 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2589 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2591 /* New patterns for I3 and I2, respectively. */
2592 rtx newpat
, newi2pat
= 0;
2593 rtvec newpat_vec_with_clobbers
= 0;
2594 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2595 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2597 int added_sets_0
, added_sets_1
, added_sets_2
;
2598 /* Total number of SETs to put into I3. */
2600 /* Nonzero if I2's or I1's body now appears in I3. */
2601 int i2_is_used
= 0, i1_is_used
= 0;
2602 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2603 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2604 /* Contains I3 if the destination of I3 is used in its source, which means
2605 that the old life of I3 is being killed. If that usage is placed into
2606 I2 and not in I3, a REG_DEAD note must be made. */
2607 rtx i3dest_killed
= 0;
2608 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2609 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2610 /* Copy of SET_SRC of I1 and I0, if needed. */
2611 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2612 /* Set if I2DEST was reused as a scratch register. */
2613 bool i2scratch
= false;
2614 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2615 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2616 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2617 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2618 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2619 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2620 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2621 /* Notes that must be added to REG_NOTES in I3 and I2. */
2622 rtx new_i3_notes
, new_i2_notes
;
2623 /* Notes that we substituted I3 into I2 instead of the normal case. */
2624 int i3_subst_into_i2
= 0;
2625 /* Notes that I1, I2 or I3 is a MULT operation. */
2628 int changed_i3_dest
= 0;
2631 rtx_insn
*temp_insn
;
2633 struct insn_link
*link
;
2635 rtx new_other_notes
;
2638 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2640 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2643 /* Only try four-insn combinations when there's high likelihood of
2644 success. Look for simple insns, such as loads of constants or
2645 binary operations involving a constant. */
2653 if (!flag_expensive_optimizations
)
2656 for (i
= 0; i
< 4; i
++)
2658 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2659 rtx set
= single_set (insn
);
2663 src
= SET_SRC (set
);
2664 if (CONSTANT_P (src
))
2669 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2671 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2672 || GET_CODE (src
) == LSHIFTRT
)
2676 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2677 are likely manipulating its value. Ideally we'll be able to combine
2678 all four insns into a bitfield insertion of some kind.
2680 Note the source in I0 might be inside a sign/zero extension and the
2681 memory modes in I0 and I3 might be different. So extract the address
2682 from the destination of I3 and search for it in the source of I0.
2684 In the event that there's a match but the source/dest do not actually
2685 refer to the same memory, the worst that happens is we try some
2686 combinations that we wouldn't have otherwise. */
2687 if ((set0
= single_set (i0
))
2688 /* Ensure the source of SET0 is a MEM, possibly buried inside
2690 && (GET_CODE (SET_SRC (set0
)) == MEM
2691 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2692 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2693 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2694 && (set3
= single_set (i3
))
2695 /* Ensure the destination of SET3 is a MEM. */
2696 && GET_CODE (SET_DEST (set3
)) == MEM
2697 /* Would it be better to extract the base address for the MEM
2698 in SET3 and look for that? I don't have cases where it matters
2699 but I could envision such cases. */
2700 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2703 if (ngood
< 2 && nshift
< 2)
2707 /* Exit early if one of the insns involved can't be used for
2710 || (i1
&& CALL_P (i1
))
2711 || (i0
&& CALL_P (i0
))
2712 || cant_combine_insn_p (i3
)
2713 || cant_combine_insn_p (i2
)
2714 || (i1
&& cant_combine_insn_p (i1
))
2715 || (i0
&& cant_combine_insn_p (i0
))
2716 || likely_spilled_retval_p (i3
))
2720 undobuf
.other_insn
= 0;
2722 /* Reset the hard register usage information. */
2723 CLEAR_HARD_REG_SET (newpat_used_regs
);
2725 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2728 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2729 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2731 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2732 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2734 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2735 INSN_UID (i2
), INSN_UID (i3
));
2738 /* If multiple insns feed into one of I2 or I3, they can be in any
2739 order. To simplify the code below, reorder them in sequence. */
2740 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2742 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2744 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2747 added_links_insn
= 0;
2749 /* First check for one important special case that the code below will
2750 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2751 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2752 we may be able to replace that destination with the destination of I3.
2753 This occurs in the common code where we compute both a quotient and
2754 remainder into a structure, in which case we want to do the computation
2755 directly into the structure to avoid register-register copies.
2757 Note that this case handles both multiple sets in I2 and also cases
2758 where I2 has a number of CLOBBERs inside the PARALLEL.
2760 We make very conservative checks below and only try to handle the
2761 most common cases of this. For example, we only handle the case
2762 where I2 and I3 are adjacent to avoid making difficult register
2765 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2766 && REG_P (SET_SRC (PATTERN (i3
)))
2767 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2768 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2769 && GET_CODE (PATTERN (i2
)) == PARALLEL
2770 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2771 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2772 below would need to check what is inside (and reg_overlap_mentioned_p
2773 doesn't support those codes anyway). Don't allow those destinations;
2774 the resulting insn isn't likely to be recognized anyway. */
2775 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2776 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2777 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2778 SET_DEST (PATTERN (i3
)))
2779 && next_active_insn (i2
) == i3
)
2781 rtx p2
= PATTERN (i2
);
2783 /* Make sure that the destination of I3,
2784 which we are going to substitute into one output of I2,
2785 is not used within another output of I2. We must avoid making this:
2786 (parallel [(set (mem (reg 69)) ...)
2787 (set (reg 69) ...)])
2788 which is not well-defined as to order of actions.
2789 (Besides, reload can't handle output reloads for this.)
2791 The problem can also happen if the dest of I3 is a memory ref,
2792 if another dest in I2 is an indirect memory ref.
2794 Neither can this PARALLEL be an asm. We do not allow combining
2795 that usually (see can_combine_p), so do not here either. */
2797 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2799 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2800 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2801 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2802 SET_DEST (XVECEXP (p2
, 0, i
))))
2804 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2805 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2810 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2811 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2812 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2817 subst_low_luid
= DF_INSN_LUID (i2
);
2819 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2820 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2821 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2822 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2824 /* Replace the dest in I2 with our dest and make the resulting
2825 insn the new pattern for I3. Then skip to where we validate
2826 the pattern. Everything was set up above. */
2827 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2829 i3_subst_into_i2
= 1;
2830 goto validate_replacement
;
2834 /* If I2 is setting a pseudo to a constant and I3 is setting some
2835 sub-part of it to another constant, merge them by making a new
2838 && (temp_expr
= single_set (i2
)) != 0
2839 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2840 && GET_CODE (PATTERN (i3
)) == SET
2841 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2842 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2844 rtx dest
= SET_DEST (PATTERN (i3
));
2848 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2850 if (CONST_INT_P (XEXP (dest
, 1))
2851 && CONST_INT_P (XEXP (dest
, 2)))
2853 width
= INTVAL (XEXP (dest
, 1));
2854 offset
= INTVAL (XEXP (dest
, 2));
2855 dest
= XEXP (dest
, 0);
2856 if (BITS_BIG_ENDIAN
)
2857 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2862 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2863 dest
= XEXP (dest
, 0);
2864 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2870 /* If this is the low part, we're done. */
2871 if (subreg_lowpart_p (dest
))
2873 /* Handle the case where inner is twice the size of outer. */
2874 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2875 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2876 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2877 /* Otherwise give up for now. */
2884 rtx inner
= SET_SRC (PATTERN (i3
));
2885 rtx outer
= SET_SRC (temp_expr
);
2888 = wi::insert (rtx_mode_t (outer
, GET_MODE (SET_DEST (temp_expr
))),
2889 rtx_mode_t (inner
, GET_MODE (dest
)),
2894 subst_low_luid
= DF_INSN_LUID (i2
);
2895 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2896 i2dest
= SET_DEST (temp_expr
);
2897 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2899 /* Replace the source in I2 with the new constant and make the
2900 resulting insn the new pattern for I3. Then skip to where we
2901 validate the pattern. Everything was set up above. */
2902 SUBST (SET_SRC (temp_expr
),
2903 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2905 newpat
= PATTERN (i2
);
2907 /* The dest of I3 has been replaced with the dest of I2. */
2908 changed_i3_dest
= 1;
2909 goto validate_replacement
;
2913 /* If we have no I1 and I2 looks like:
2914 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2916 make up a dummy I1 that is
2919 (set (reg:CC X) (compare:CC Y (const_int 0)))
2921 (We can ignore any trailing CLOBBERs.)
2923 This undoes a previous combination and allows us to match a branch-and-
2926 if (!HAVE_cc0
&& i1
== 0
2927 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2928 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2930 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2931 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2932 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2933 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2934 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2935 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2937 /* We make I1 with the same INSN_UID as I2. This gives it
2938 the same DF_INSN_LUID for value tracking. Our fake I1 will
2939 never appear in the insn stream so giving it the same INSN_UID
2940 as I2 will not cause a problem. */
2942 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2943 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2945 INSN_UID (i1
) = INSN_UID (i2
);
2947 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2948 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2949 SET_DEST (PATTERN (i1
)));
2950 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2951 SUBST_LINK (LOG_LINKS (i2
),
2952 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2955 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2956 make those two SETs separate I1 and I2 insns, and make an I0 that is
2958 if (!HAVE_cc0
&& i0
== 0
2959 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2960 && can_split_parallel_of_n_reg_sets (i2
, 2)
2961 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2962 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2964 /* If there is no I1, there is no I0 either. */
2967 /* We make I1 with the same INSN_UID as I2. This gives it
2968 the same DF_INSN_LUID for value tracking. Our fake I1 will
2969 never appear in the insn stream so giving it the same INSN_UID
2970 as I2 will not cause a problem. */
2972 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2973 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2975 INSN_UID (i1
) = INSN_UID (i2
);
2977 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2980 /* Verify that I2 and I1 are valid for combining. */
2981 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2982 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2984 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2991 /* Record whether I2DEST is used in I2SRC and similarly for the other
2992 cases. Knowing this will help in register status updating below. */
2993 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2994 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2995 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2996 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2997 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2998 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2999 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3000 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3001 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3003 /* For the earlier insns, determine which of the subsequent ones they
3005 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3006 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3007 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3008 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3009 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3011 /* Ensure that I3's pattern can be the destination of combines. */
3012 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3013 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3014 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3015 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3022 /* See if any of the insns is a MULT operation. Unless one is, we will
3023 reject a combination that is, since it must be slower. Be conservative
3025 if (GET_CODE (i2src
) == MULT
3026 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3027 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3028 || (GET_CODE (PATTERN (i3
)) == SET
3029 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3032 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3033 We used to do this EXCEPT in one case: I3 has a post-inc in an
3034 output operand. However, that exception can give rise to insns like
3036 which is a famous insn on the PDP-11 where the value of r3 used as the
3037 source was model-dependent. Avoid this sort of thing. */
3040 if (!(GET_CODE (PATTERN (i3
)) == SET
3041 && REG_P (SET_SRC (PATTERN (i3
)))
3042 && MEM_P (SET_DEST (PATTERN (i3
)))
3043 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3044 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3045 /* It's not the exception. */
3050 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3051 if (REG_NOTE_KIND (link
) == REG_INC
3052 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3054 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3061 /* See if the SETs in I1 or I2 need to be kept around in the merged
3062 instruction: whenever the value set there is still needed past I3.
3063 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3065 For the SET in I1, we have two cases: if I1 and I2 independently feed
3066 into I3, the set in I1 needs to be kept around unless I1DEST dies
3067 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3068 in I1 needs to be kept around unless I1DEST dies or is set in either
3069 I2 or I3. The same considerations apply to I0. */
3071 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3074 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3075 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3080 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3081 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3082 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3083 && dead_or_set_p (i2
, i0dest
)));
3087 /* We are about to copy insns for the case where they need to be kept
3088 around. Check that they can be copied in the merged instruction. */
3090 if (targetm
.cannot_copy_insn_p
3091 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3092 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3093 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3099 /* If the set in I2 needs to be kept around, we must make a copy of
3100 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3101 PATTERN (I2), we are only substituting for the original I1DEST, not into
3102 an already-substituted copy. This also prevents making self-referential
3103 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3108 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3109 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3111 i2pat
= copy_rtx (PATTERN (i2
));
3116 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3117 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3119 i1pat
= copy_rtx (PATTERN (i1
));
3124 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3125 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3127 i0pat
= copy_rtx (PATTERN (i0
));
3132 /* Substitute in the latest insn for the regs set by the earlier ones. */
3134 maxreg
= max_reg_num ();
3138 /* Many machines that don't use CC0 have insns that can both perform an
3139 arithmetic operation and set the condition code. These operations will
3140 be represented as a PARALLEL with the first element of the vector
3141 being a COMPARE of an arithmetic operation with the constant zero.
3142 The second element of the vector will set some pseudo to the result
3143 of the same arithmetic operation. If we simplify the COMPARE, we won't
3144 match such a pattern and so will generate an extra insn. Here we test
3145 for this case, where both the comparison and the operation result are
3146 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3147 I2SRC. Later we will make the PARALLEL that contains I2. */
3149 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3150 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3151 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3152 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3155 rtx
*cc_use_loc
= NULL
;
3156 rtx_insn
*cc_use_insn
= NULL
;
3157 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3158 machine_mode compare_mode
, orig_compare_mode
;
3159 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3161 newpat
= PATTERN (i3
);
3162 newpat_dest
= SET_DEST (newpat
);
3163 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3165 if (undobuf
.other_insn
== 0
3166 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3169 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3170 compare_code
= simplify_compare_const (compare_code
,
3171 GET_MODE (i2dest
), op0
, &op1
);
3172 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3175 /* Do the rest only if op1 is const0_rtx, which may be the
3176 result of simplification. */
3177 if (op1
== const0_rtx
)
3179 /* If a single use of the CC is found, prepare to modify it
3180 when SELECT_CC_MODE returns a new CC-class mode, or when
3181 the above simplify_compare_const() returned a new comparison
3182 operator. undobuf.other_insn is assigned the CC use insn
3183 when modifying it. */
3186 #ifdef SELECT_CC_MODE
3187 machine_mode new_mode
3188 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3189 if (new_mode
!= orig_compare_mode
3190 && can_change_dest_mode (SET_DEST (newpat
),
3191 added_sets_2
, new_mode
))
3193 unsigned int regno
= REGNO (newpat_dest
);
3194 compare_mode
= new_mode
;
3195 if (regno
< FIRST_PSEUDO_REGISTER
)
3196 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3199 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3200 newpat_dest
= regno_reg_rtx
[regno
];
3204 /* Cases for modifying the CC-using comparison. */
3205 if (compare_code
!= orig_compare_code
3206 /* ??? Do we need to verify the zero rtx? */
3207 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3209 /* Replace cc_use_loc with entire new RTX. */
3211 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3212 newpat_dest
, const0_rtx
));
3213 undobuf
.other_insn
= cc_use_insn
;
3215 else if (compare_mode
!= orig_compare_mode
)
3217 /* Just replace the CC reg with a new mode. */
3218 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3219 undobuf
.other_insn
= cc_use_insn
;
3223 /* Now we modify the current newpat:
3224 First, SET_DEST(newpat) is updated if the CC mode has been
3225 altered. For targets without SELECT_CC_MODE, this should be
3227 if (compare_mode
!= orig_compare_mode
)
3228 SUBST (SET_DEST (newpat
), newpat_dest
);
3229 /* This is always done to propagate i2src into newpat. */
3230 SUBST (SET_SRC (newpat
),
3231 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3232 /* Create new version of i2pat if needed; the below PARALLEL
3233 creation needs this to work correctly. */
3234 if (! rtx_equal_p (i2src
, op0
))
3235 i2pat
= gen_rtx_SET (i2dest
, op0
);
3240 if (i2_is_used
== 0)
3242 /* It is possible that the source of I2 or I1 may be performing
3243 an unneeded operation, such as a ZERO_EXTEND of something
3244 that is known to have the high part zero. Handle that case
3245 by letting subst look at the inner insns.
3247 Another way to do this would be to have a function that tries
3248 to simplify a single insn instead of merging two or more
3249 insns. We don't do this because of the potential of infinite
3250 loops and because of the potential extra memory required.
3251 However, doing it the way we are is a bit of a kludge and
3252 doesn't catch all cases.
3254 But only do this if -fexpensive-optimizations since it slows
3255 things down and doesn't usually win.
3257 This is not done in the COMPARE case above because the
3258 unmodified I2PAT is used in the PARALLEL and so a pattern
3259 with a modified I2SRC would not match. */
3261 if (flag_expensive_optimizations
)
3263 /* Pass pc_rtx so no substitutions are done, just
3267 subst_low_luid
= DF_INSN_LUID (i1
);
3268 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3271 subst_low_luid
= DF_INSN_LUID (i2
);
3272 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3275 n_occurrences
= 0; /* `subst' counts here */
3276 subst_low_luid
= DF_INSN_LUID (i2
);
3278 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3279 copy of I2SRC each time we substitute it, in order to avoid creating
3280 self-referential RTL when we will be substituting I1SRC for I1DEST
3281 later. Likewise if I0 feeds into I2, either directly or indirectly
3282 through I1, and I0DEST is in I0SRC. */
3283 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3284 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3285 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3286 && i0dest_in_i0src
));
3289 /* Record whether I2's body now appears within I3's body. */
3290 i2_is_used
= n_occurrences
;
3293 /* If we already got a failure, don't try to do more. Otherwise, try to
3294 substitute I1 if we have it. */
3296 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3298 /* Check that an autoincrement side-effect on I1 has not been lost.
3299 This happens if I1DEST is mentioned in I2 and dies there, and
3300 has disappeared from the new pattern. */
3301 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3303 && dead_or_set_p (i2
, i1dest
)
3304 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3305 /* Before we can do this substitution, we must redo the test done
3306 above (see detailed comments there) that ensures I1DEST isn't
3307 mentioned in any SETs in NEWPAT that are field assignments. */
3308 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3316 subst_low_luid
= DF_INSN_LUID (i1
);
3318 /* If the following substitution will modify I1SRC, make a copy of it
3319 for the case where it is substituted for I1DEST in I2PAT later. */
3320 if (added_sets_2
&& i1_feeds_i2_n
)
3321 i1src_copy
= copy_rtx (i1src
);
3323 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3324 copy of I1SRC each time we substitute it, in order to avoid creating
3325 self-referential RTL when we will be substituting I0SRC for I0DEST
3327 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3328 i0_feeds_i1_n
&& i0dest_in_i0src
);
3331 /* Record whether I1's body now appears within I3's body. */
3332 i1_is_used
= n_occurrences
;
3335 /* Likewise for I0 if we have it. */
3337 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3339 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3340 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3341 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3342 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3343 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3350 /* If the following substitution will modify I0SRC, make a copy of it
3351 for the case where it is substituted for I0DEST in I1PAT later. */
3352 if (added_sets_1
&& i0_feeds_i1_n
)
3353 i0src_copy
= copy_rtx (i0src
);
3354 /* And a copy for I0DEST in I2PAT substitution. */
3355 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3356 || (i0_feeds_i2_n
)))
3357 i0src_copy2
= copy_rtx (i0src
);
3360 subst_low_luid
= DF_INSN_LUID (i0
);
3361 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3365 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3366 to count all the ways that I2SRC and I1SRC can be used. */
3367 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3368 && i2_is_used
+ added_sets_2
> 1)
3369 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3370 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3372 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3373 && (n_occurrences
+ added_sets_0
3374 + (added_sets_1
&& i0_feeds_i1_n
)
3375 + (added_sets_2
&& i0_feeds_i2_n
)
3377 /* Fail if we tried to make a new register. */
3378 || max_reg_num () != maxreg
3379 /* Fail if we couldn't do something and have a CLOBBER. */
3380 || GET_CODE (newpat
) == CLOBBER
3381 /* Fail if this new pattern is a MULT and we didn't have one before
3382 at the outer level. */
3383 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3390 /* If the actions of the earlier insns must be kept
3391 in addition to substituting them into the latest one,
3392 we must make a new PARALLEL for the latest insn
3393 to hold additional the SETs. */
3395 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3397 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3400 if (GET_CODE (newpat
) == PARALLEL
)
3402 rtvec old
= XVEC (newpat
, 0);
3403 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3404 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3405 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3406 sizeof (old
->elem
[0]) * old
->num_elem
);
3411 total_sets
= 1 + extra_sets
;
3412 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3413 XVECEXP (newpat
, 0, 0) = old
;
3417 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3423 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3425 XVECEXP (newpat
, 0, --total_sets
) = t
;
3431 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3432 i0_feeds_i1_n
&& i0dest_in_i0src
);
3433 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3434 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3436 XVECEXP (newpat
, 0, --total_sets
) = t
;
3440 validate_replacement
:
3442 /* Note which hard regs this insn has as inputs. */
3443 mark_used_regs_combine (newpat
);
3445 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3446 consider splitting this pattern, we might need these clobbers. */
3447 if (i1
&& GET_CODE (newpat
) == PARALLEL
3448 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3450 int len
= XVECLEN (newpat
, 0);
3452 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3453 for (i
= 0; i
< len
; i
++)
3454 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3457 /* We have recognized nothing yet. */
3458 insn_code_number
= -1;
3460 /* See if this is a PARALLEL of two SETs where one SET's destination is
3461 a register that is unused and this isn't marked as an instruction that
3462 might trap in an EH region. In that case, we just need the other SET.
3463 We prefer this over the PARALLEL.
3465 This can occur when simplifying a divmod insn. We *must* test for this
3466 case here because the code below that splits two independent SETs doesn't
3467 handle this case correctly when it updates the register status.
3469 It's pointless doing this if we originally had two sets, one from
3470 i3, and one from i2. Combining then splitting the parallel results
3471 in the original i2 again plus an invalid insn (which we delete).
3472 The net effect is only to move instructions around, which makes
3473 debug info less accurate. */
3475 if (!(added_sets_2
&& i1
== 0)
3476 && is_parallel_of_n_reg_sets (newpat
, 2)
3477 && asm_noperands (newpat
) < 0)
3479 rtx set0
= XVECEXP (newpat
, 0, 0);
3480 rtx set1
= XVECEXP (newpat
, 0, 1);
3481 rtx oldpat
= newpat
;
3483 if (((REG_P (SET_DEST (set1
))
3484 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3485 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3486 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3487 && insn_nothrow_p (i3
)
3488 && !side_effects_p (SET_SRC (set1
)))
3491 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3494 else if (((REG_P (SET_DEST (set0
))
3495 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3496 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3497 && find_reg_note (i3
, REG_UNUSED
,
3498 SUBREG_REG (SET_DEST (set0
)))))
3499 && insn_nothrow_p (i3
)
3500 && !side_effects_p (SET_SRC (set0
)))
3503 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3505 if (insn_code_number
>= 0)
3506 changed_i3_dest
= 1;
3509 if (insn_code_number
< 0)
3513 /* Is the result of combination a valid instruction? */
3514 if (insn_code_number
< 0)
3515 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3517 /* If we were combining three insns and the result is a simple SET
3518 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3519 insns. There are two ways to do this. It can be split using a
3520 machine-specific method (like when you have an addition of a large
3521 constant) or by combine in the function find_split_point. */
3523 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3524 && asm_noperands (newpat
) < 0)
3526 rtx parallel
, *split
;
3527 rtx_insn
*m_split_insn
;
3529 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3530 use I2DEST as a scratch register will help. In the latter case,
3531 convert I2DEST to the mode of the source of NEWPAT if we can. */
3533 m_split_insn
= combine_split_insns (newpat
, i3
);
3535 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3536 inputs of NEWPAT. */
3538 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3539 possible to try that as a scratch reg. This would require adding
3540 more code to make it work though. */
3542 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3544 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3546 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3547 (temporarily, until we are committed to this instruction
3548 combination) does not work: for example, any call to nonzero_bits
3549 on the register (from a splitter in the MD file, for example)
3550 will get the old information, which is invalid.
3552 Since nowadays we can create registers during combine just fine,
3553 we should just create a new one here, not reuse i2dest. */
3555 /* First try to split using the original register as a
3556 scratch register. */
3557 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3558 gen_rtvec (2, newpat
,
3559 gen_rtx_CLOBBER (VOIDmode
,
3561 m_split_insn
= combine_split_insns (parallel
, i3
);
3563 /* If that didn't work, try changing the mode of I2DEST if
3565 if (m_split_insn
== 0
3566 && new_mode
!= GET_MODE (i2dest
)
3567 && new_mode
!= VOIDmode
3568 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3570 machine_mode old_mode
= GET_MODE (i2dest
);
3573 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3574 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3577 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3578 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3581 parallel
= (gen_rtx_PARALLEL
3583 gen_rtvec (2, newpat
,
3584 gen_rtx_CLOBBER (VOIDmode
,
3586 m_split_insn
= combine_split_insns (parallel
, i3
);
3588 if (m_split_insn
== 0
3589 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3593 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3594 buf
= undobuf
.undos
;
3595 undobuf
.undos
= buf
->next
;
3596 buf
->next
= undobuf
.frees
;
3597 undobuf
.frees
= buf
;
3601 i2scratch
= m_split_insn
!= 0;
3604 /* If recog_for_combine has discarded clobbers, try to use them
3605 again for the split. */
3606 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3608 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3609 m_split_insn
= combine_split_insns (parallel
, i3
);
3612 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3614 rtx m_split_pat
= PATTERN (m_split_insn
);
3615 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3616 if (insn_code_number
>= 0)
3617 newpat
= m_split_pat
;
3619 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3620 && (next_nonnote_nondebug_insn (i2
) == i3
3621 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3624 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3625 newi2pat
= PATTERN (m_split_insn
);
3627 i3set
= single_set (NEXT_INSN (m_split_insn
));
3628 i2set
= single_set (m_split_insn
);
3630 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3632 /* If I2 or I3 has multiple SETs, we won't know how to track
3633 register status, so don't use these insns. If I2's destination
3634 is used between I2 and I3, we also can't use these insns. */
3636 if (i2_code_number
>= 0 && i2set
&& i3set
3637 && (next_nonnote_nondebug_insn (i2
) == i3
3638 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3639 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3641 if (insn_code_number
>= 0)
3644 /* It is possible that both insns now set the destination of I3.
3645 If so, we must show an extra use of it. */
3647 if (insn_code_number
>= 0)
3649 rtx new_i3_dest
= SET_DEST (i3set
);
3650 rtx new_i2_dest
= SET_DEST (i2set
);
3652 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3653 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3654 || GET_CODE (new_i3_dest
) == SUBREG
)
3655 new_i3_dest
= XEXP (new_i3_dest
, 0);
3657 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3658 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3659 || GET_CODE (new_i2_dest
) == SUBREG
)
3660 new_i2_dest
= XEXP (new_i2_dest
, 0);
3662 if (REG_P (new_i3_dest
)
3663 && REG_P (new_i2_dest
)
3664 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3665 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3666 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3670 /* If we can split it and use I2DEST, go ahead and see if that
3671 helps things be recognized. Verify that none of the registers
3672 are set between I2 and I3. */
3673 if (insn_code_number
< 0
3674 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3675 && (!HAVE_cc0
|| REG_P (i2dest
))
3676 /* We need I2DEST in the proper mode. If it is a hard register
3677 or the only use of a pseudo, we can change its mode.
3678 Make sure we don't change a hard register to have a mode that
3679 isn't valid for it, or change the number of registers. */
3680 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3681 || GET_MODE (*split
) == VOIDmode
3682 || can_change_dest_mode (i2dest
, added_sets_2
,
3684 && (next_nonnote_nondebug_insn (i2
) == i3
3685 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3686 /* We can't overwrite I2DEST if its value is still used by
3688 && ! reg_referenced_p (i2dest
, newpat
))
3690 rtx newdest
= i2dest
;
3691 enum rtx_code split_code
= GET_CODE (*split
);
3692 machine_mode split_mode
= GET_MODE (*split
);
3693 bool subst_done
= false;
3694 newi2pat
= NULL_RTX
;
3698 /* *SPLIT may be part of I2SRC, so make sure we have the
3699 original expression around for later debug processing.
3700 We should not need I2SRC any more in other cases. */
3701 if (MAY_HAVE_DEBUG_INSNS
)
3702 i2src
= copy_rtx (i2src
);
3706 /* Get NEWDEST as a register in the proper mode. We have already
3707 validated that we can do this. */
3708 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3710 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3711 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3714 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3715 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3719 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3720 an ASHIFT. This can occur if it was inside a PLUS and hence
3721 appeared to be a memory address. This is a kludge. */
3722 if (split_code
== MULT
3723 && CONST_INT_P (XEXP (*split
, 1))
3724 && INTVAL (XEXP (*split
, 1)) > 0
3725 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3727 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3728 XEXP (*split
, 0), GEN_INT (i
)));
3729 /* Update split_code because we may not have a multiply
3731 split_code
= GET_CODE (*split
);
3734 /* Similarly for (plus (mult FOO (const_int pow2))). */
3735 if (split_code
== PLUS
3736 && GET_CODE (XEXP (*split
, 0)) == MULT
3737 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3738 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3739 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3741 rtx nsplit
= XEXP (*split
, 0);
3742 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3743 XEXP (nsplit
, 0), GEN_INT (i
)));
3744 /* Update split_code because we may not have a multiply
3746 split_code
= GET_CODE (*split
);
3749 #ifdef INSN_SCHEDULING
3750 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3751 be written as a ZERO_EXTEND. */
3752 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3754 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3755 what it really is. */
3756 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3758 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3759 SUBREG_REG (*split
)));
3761 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3762 SUBREG_REG (*split
)));
3766 /* Attempt to split binary operators using arithmetic identities. */
3767 if (BINARY_P (SET_SRC (newpat
))
3768 && split_mode
== GET_MODE (SET_SRC (newpat
))
3769 && ! side_effects_p (SET_SRC (newpat
)))
3771 rtx setsrc
= SET_SRC (newpat
);
3772 machine_mode mode
= GET_MODE (setsrc
);
3773 enum rtx_code code
= GET_CODE (setsrc
);
3774 rtx src_op0
= XEXP (setsrc
, 0);
3775 rtx src_op1
= XEXP (setsrc
, 1);
3777 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3778 if (rtx_equal_p (src_op0
, src_op1
))
3780 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3781 SUBST (XEXP (setsrc
, 0), newdest
);
3782 SUBST (XEXP (setsrc
, 1), newdest
);
3785 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3786 else if ((code
== PLUS
|| code
== MULT
)
3787 && GET_CODE (src_op0
) == code
3788 && GET_CODE (XEXP (src_op0
, 0)) == code
3789 && (INTEGRAL_MODE_P (mode
)
3790 || (FLOAT_MODE_P (mode
)
3791 && flag_unsafe_math_optimizations
)))
3793 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3794 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3795 rtx r
= XEXP (src_op0
, 1);
3798 /* Split both "((X op Y) op X) op Y" and
3799 "((X op Y) op Y) op X" as "T op T" where T is
3801 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3802 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3804 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3805 SUBST (XEXP (setsrc
, 0), newdest
);
3806 SUBST (XEXP (setsrc
, 1), newdest
);
3809 /* Split "((X op X) op Y) op Y)" as "T op T" where
3811 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3813 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3814 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3815 SUBST (XEXP (setsrc
, 0), newdest
);
3816 SUBST (XEXP (setsrc
, 1), newdest
);
3824 newi2pat
= gen_rtx_SET (newdest
, *split
);
3825 SUBST (*split
, newdest
);
3828 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3830 /* recog_for_combine might have added CLOBBERs to newi2pat.
3831 Make sure NEWPAT does not depend on the clobbered regs. */
3832 if (GET_CODE (newi2pat
) == PARALLEL
)
3833 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3834 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3836 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3837 if (reg_overlap_mentioned_p (reg
, newpat
))
3844 /* If the split point was a MULT and we didn't have one before,
3845 don't use one now. */
3846 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3847 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3851 /* Check for a case where we loaded from memory in a narrow mode and
3852 then sign extended it, but we need both registers. In that case,
3853 we have a PARALLEL with both loads from the same memory location.
3854 We can split this into a load from memory followed by a register-register
3855 copy. This saves at least one insn, more if register allocation can
3858 We cannot do this if the destination of the first assignment is a
3859 condition code register or cc0. We eliminate this case by making sure
3860 the SET_DEST and SET_SRC have the same mode.
3862 We cannot do this if the destination of the second assignment is
3863 a register that we have already assumed is zero-extended. Similarly
3864 for a SUBREG of such a register. */
3866 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3867 && GET_CODE (newpat
) == PARALLEL
3868 && XVECLEN (newpat
, 0) == 2
3869 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3870 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3871 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3872 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3873 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3874 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3875 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3876 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3878 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3879 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3880 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3882 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3883 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3884 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3885 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3886 != GET_MODE_MASK (word_mode
))))
3887 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3888 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3890 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3891 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3892 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3893 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3894 != GET_MODE_MASK (word_mode
)))))
3895 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3896 SET_SRC (XVECEXP (newpat
, 0, 1)))
3897 && ! find_reg_note (i3
, REG_UNUSED
,
3898 SET_DEST (XVECEXP (newpat
, 0, 0))))
3902 newi2pat
= XVECEXP (newpat
, 0, 0);
3903 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3904 newpat
= XVECEXP (newpat
, 0, 1);
3905 SUBST (SET_SRC (newpat
),
3906 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3907 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3909 if (i2_code_number
>= 0)
3910 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3912 if (insn_code_number
>= 0)
3916 /* Similarly, check for a case where we have a PARALLEL of two independent
3917 SETs but we started with three insns. In this case, we can do the sets
3918 as two separate insns. This case occurs when some SET allows two
3919 other insns to combine, but the destination of that SET is still live.
3921 Also do this if we started with two insns and (at least) one of the
3922 resulting sets is a noop; this noop will be deleted later. */
3924 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3925 && GET_CODE (newpat
) == PARALLEL
3926 && XVECLEN (newpat
, 0) == 2
3927 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3928 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3929 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3930 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3931 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3932 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3933 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3934 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3935 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3936 XVECEXP (newpat
, 0, 0))
3937 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3938 XVECEXP (newpat
, 0, 1))
3939 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3940 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3942 rtx set0
= XVECEXP (newpat
, 0, 0);
3943 rtx set1
= XVECEXP (newpat
, 0, 1);
3945 /* Normally, it doesn't matter which of the two is done first,
3946 but the one that references cc0 can't be the second, and
3947 one which uses any regs/memory set in between i2 and i3 can't
3948 be first. The PARALLEL might also have been pre-existing in i3,
3949 so we need to make sure that we won't wrongly hoist a SET to i2
3950 that would conflict with a death note present in there. */
3951 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3952 && !(REG_P (SET_DEST (set1
))
3953 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3954 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3955 && find_reg_note (i2
, REG_DEAD
,
3956 SUBREG_REG (SET_DEST (set1
))))
3957 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3958 /* If I3 is a jump, ensure that set0 is a jump so that
3959 we do not create invalid RTL. */
3960 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3966 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3967 && !(REG_P (SET_DEST (set0
))
3968 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3969 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3970 && find_reg_note (i2
, REG_DEAD
,
3971 SUBREG_REG (SET_DEST (set0
))))
3972 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3973 /* If I3 is a jump, ensure that set1 is a jump so that
3974 we do not create invalid RTL. */
3975 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3987 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3989 if (i2_code_number
>= 0)
3991 /* recog_for_combine might have added CLOBBERs to newi2pat.
3992 Make sure NEWPAT does not depend on the clobbered regs. */
3993 if (GET_CODE (newi2pat
) == PARALLEL
)
3995 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3996 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3998 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3999 if (reg_overlap_mentioned_p (reg
, newpat
))
4007 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4011 /* If it still isn't recognized, fail and change things back the way they
4013 if ((insn_code_number
< 0
4014 /* Is the result a reasonable ASM_OPERANDS? */
4015 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4021 /* If we had to change another insn, make sure it is valid also. */
4022 if (undobuf
.other_insn
)
4024 CLEAR_HARD_REG_SET (newpat_used_regs
);
4026 other_pat
= PATTERN (undobuf
.other_insn
);
4027 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4030 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4037 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4038 they are adjacent to each other or not. */
4041 rtx_insn
*p
= prev_nonnote_insn (i3
);
4042 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4043 && sets_cc0_p (newi2pat
))
4050 /* Only allow this combination if insn_rtx_costs reports that the
4051 replacement instructions are cheaper than the originals. */
4052 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4058 if (MAY_HAVE_DEBUG_INSNS
)
4062 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4063 if (undo
->kind
== UNDO_MODE
)
4065 rtx reg
= *undo
->where
.r
;
4066 machine_mode new_mode
= GET_MODE (reg
);
4067 machine_mode old_mode
= undo
->old_contents
.m
;
4069 /* Temporarily revert mode back. */
4070 adjust_reg_mode (reg
, old_mode
);
4072 if (reg
== i2dest
&& i2scratch
)
4074 /* If we used i2dest as a scratch register with a
4075 different mode, substitute it for the original
4076 i2src while its original mode is temporarily
4077 restored, and then clear i2scratch so that we don't
4078 do it again later. */
4079 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4082 /* Put back the new mode. */
4083 adjust_reg_mode (reg
, new_mode
);
4087 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4088 rtx_insn
*first
, *last
;
4093 last
= last_combined_insn
;
4098 last
= undobuf
.other_insn
;
4100 if (DF_INSN_LUID (last
)
4101 < DF_INSN_LUID (last_combined_insn
))
4102 last
= last_combined_insn
;
4105 /* We're dealing with a reg that changed mode but not
4106 meaning, so we want to turn it into a subreg for
4107 the new mode. However, because of REG sharing and
4108 because its mode had already changed, we have to do
4109 it in two steps. First, replace any debug uses of
4110 reg, with its original mode temporarily restored,
4111 with this copy we have created; then, replace the
4112 copy with the SUBREG of the original shared reg,
4113 once again changed to the new mode. */
4114 propagate_for_debug (first
, last
, reg
, tempreg
,
4116 adjust_reg_mode (reg
, new_mode
);
4117 propagate_for_debug (first
, last
, tempreg
,
4118 lowpart_subreg (old_mode
, reg
, new_mode
),
4124 /* If we will be able to accept this, we have made a
4125 change to the destination of I3. This requires us to
4126 do a few adjustments. */
4128 if (changed_i3_dest
)
4130 PATTERN (i3
) = newpat
;
4131 adjust_for_new_dest (i3
);
4134 /* We now know that we can do this combination. Merge the insns and
4135 update the status of registers and LOG_LINKS. */
4137 if (undobuf
.other_insn
)
4141 PATTERN (undobuf
.other_insn
) = other_pat
;
4143 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4144 ensure that they are still valid. Then add any non-duplicate
4145 notes added by recog_for_combine. */
4146 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4148 next
= XEXP (note
, 1);
4150 if ((REG_NOTE_KIND (note
) == REG_DEAD
4151 && !reg_referenced_p (XEXP (note
, 0),
4152 PATTERN (undobuf
.other_insn
)))
4153 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4154 && !reg_set_p (XEXP (note
, 0),
4155 PATTERN (undobuf
.other_insn
)))
4156 /* Simply drop equal note since it may be no longer valid
4157 for other_insn. It may be possible to record that CC
4158 register is changed and only discard those notes, but
4159 in practice it's unnecessary complication and doesn't
4160 give any meaningful improvement.
4163 || REG_NOTE_KIND (note
) == REG_EQUAL
4164 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4165 remove_note (undobuf
.other_insn
, note
);
4168 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4169 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4176 struct insn_link
*link
;
4179 /* I3 now uses what used to be its destination and which is now
4180 I2's destination. This requires us to do a few adjustments. */
4181 PATTERN (i3
) = newpat
;
4182 adjust_for_new_dest (i3
);
4184 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4187 However, some later insn might be using I2's dest and have
4188 a LOG_LINK pointing at I3. We must remove this link.
4189 The simplest way to remove the link is to point it at I1,
4190 which we know will be a NOTE. */
4192 /* newi2pat is usually a SET here; however, recog_for_combine might
4193 have added some clobbers. */
4194 if (GET_CODE (newi2pat
) == PARALLEL
)
4195 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4197 ni2dest
= SET_DEST (newi2pat
);
4199 for (insn
= NEXT_INSN (i3
);
4200 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4201 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4202 insn
= NEXT_INSN (insn
))
4204 if (NONDEBUG_INSN_P (insn
)
4205 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4207 FOR_EACH_LOG_LINK (link
, insn
)
4208 if (link
->insn
== i3
)
4217 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4218 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4221 /* Compute which registers we expect to eliminate. newi2pat may be setting
4222 either i3dest or i2dest, so we must check it. */
4223 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4224 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4227 /* For i1, we need to compute both local elimination and global
4228 elimination information with respect to newi2pat because i1dest
4229 may be the same as i3dest, in which case newi2pat may be setting
4230 i1dest. Global information is used when distributing REG_DEAD
4231 note for i2 and i3, in which case it does matter if newi2pat sets
4234 Local information is used when distributing REG_DEAD note for i1,
4235 in which case it doesn't matter if newi2pat sets i1dest or not.
4236 See PR62151, if we have four insns combination:
4238 i1: r1 <- i1src (using r0)
4240 i2: r0 <- i2src (using r1)
4241 i3: r3 <- i3src (using r0)
4243 From i1's point of view, r0 is eliminated, no matter if it is set
4244 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4245 should be discarded.
4247 Note local information only affects cases in forms like "I1->I2->I3",
4248 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4249 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4251 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4254 rtx elim_i1
= (local_elim_i1
== 0
4255 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4257 /* Same case as i1. */
4258 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4260 rtx elim_i0
= (local_elim_i0
== 0
4261 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4264 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4266 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4267 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4269 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4271 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4273 /* Ensure that we do not have something that should not be shared but
4274 occurs multiple times in the new insns. Check this by first
4275 resetting all the `used' flags and then copying anything is shared. */
4277 reset_used_flags (i3notes
);
4278 reset_used_flags (i2notes
);
4279 reset_used_flags (i1notes
);
4280 reset_used_flags (i0notes
);
4281 reset_used_flags (newpat
);
4282 reset_used_flags (newi2pat
);
4283 if (undobuf
.other_insn
)
4284 reset_used_flags (PATTERN (undobuf
.other_insn
));
4286 i3notes
= copy_rtx_if_shared (i3notes
);
4287 i2notes
= copy_rtx_if_shared (i2notes
);
4288 i1notes
= copy_rtx_if_shared (i1notes
);
4289 i0notes
= copy_rtx_if_shared (i0notes
);
4290 newpat
= copy_rtx_if_shared (newpat
);
4291 newi2pat
= copy_rtx_if_shared (newi2pat
);
4292 if (undobuf
.other_insn
)
4293 reset_used_flags (PATTERN (undobuf
.other_insn
));
4295 INSN_CODE (i3
) = insn_code_number
;
4296 PATTERN (i3
) = newpat
;
4298 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4300 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4301 link
= XEXP (link
, 1))
4305 /* I2SRC must still be meaningful at this point. Some
4306 splitting operations can invalidate I2SRC, but those
4307 operations do not apply to calls. */
4309 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4313 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4316 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4321 if (undobuf
.other_insn
)
4322 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4324 /* We had one special case above where I2 had more than one set and
4325 we replaced a destination of one of those sets with the destination
4326 of I3. In that case, we have to update LOG_LINKS of insns later
4327 in this basic block. Note that this (expensive) case is rare.
4329 Also, in this case, we must pretend that all REG_NOTEs for I2
4330 actually came from I3, so that REG_UNUSED notes from I2 will be
4331 properly handled. */
4333 if (i3_subst_into_i2
)
4335 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4336 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4337 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4338 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4339 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4340 && ! find_reg_note (i2
, REG_UNUSED
,
4341 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4342 for (temp_insn
= NEXT_INSN (i2
);
4344 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4345 || BB_HEAD (this_basic_block
) != temp_insn
);
4346 temp_insn
= NEXT_INSN (temp_insn
))
4347 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4348 FOR_EACH_LOG_LINK (link
, temp_insn
)
4349 if (link
->insn
== i2
)
4355 while (XEXP (link
, 1))
4356 link
= XEXP (link
, 1);
4357 XEXP (link
, 1) = i2notes
;
4364 LOG_LINKS (i3
) = NULL
;
4366 LOG_LINKS (i2
) = NULL
;
4371 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4372 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4374 INSN_CODE (i2
) = i2_code_number
;
4375 PATTERN (i2
) = newi2pat
;
4379 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4380 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4382 SET_INSN_DELETED (i2
);
4387 LOG_LINKS (i1
) = NULL
;
4389 if (MAY_HAVE_DEBUG_INSNS
)
4390 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4392 SET_INSN_DELETED (i1
);
4397 LOG_LINKS (i0
) = NULL
;
4399 if (MAY_HAVE_DEBUG_INSNS
)
4400 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4402 SET_INSN_DELETED (i0
);
4405 /* Get death notes for everything that is now used in either I3 or
4406 I2 and used to die in a previous insn. If we built two new
4407 patterns, move from I1 to I2 then I2 to I3 so that we get the
4408 proper movement on registers that I2 modifies. */
4411 from_luid
= DF_INSN_LUID (i0
);
4413 from_luid
= DF_INSN_LUID (i1
);
4415 from_luid
= DF_INSN_LUID (i2
);
4417 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4418 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4420 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4422 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4423 elim_i2
, elim_i1
, elim_i0
);
4425 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4426 elim_i2
, elim_i1
, elim_i0
);
4428 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4429 elim_i2
, local_elim_i1
, local_elim_i0
);
4431 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4432 elim_i2
, elim_i1
, local_elim_i0
);
4434 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4435 elim_i2
, elim_i1
, elim_i0
);
4437 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4438 know these are REG_UNUSED and want them to go to the desired insn,
4439 so we always pass it as i3. */
4441 if (newi2pat
&& new_i2_notes
)
4442 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4446 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4449 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4450 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4451 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4452 in that case, it might delete I2. Similarly for I2 and I1.
4453 Show an additional death due to the REG_DEAD note we make here. If
4454 we discard it in distribute_notes, we will decrement it again. */
4458 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4459 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4460 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4463 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4464 elim_i2
, elim_i1
, elim_i0
);
4467 if (i2dest_in_i2src
)
4469 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4470 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4471 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4472 NULL_RTX
, NULL_RTX
);
4474 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4475 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4478 if (i1dest_in_i1src
)
4480 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4481 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4482 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4483 NULL_RTX
, NULL_RTX
);
4485 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4486 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4489 if (i0dest_in_i0src
)
4491 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4492 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4493 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4494 NULL_RTX
, NULL_RTX
);
4496 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4497 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4500 distribute_links (i3links
);
4501 distribute_links (i2links
);
4502 distribute_links (i1links
);
4503 distribute_links (i0links
);
4507 struct insn_link
*link
;
4508 rtx_insn
*i2_insn
= 0;
4509 rtx i2_val
= 0, set
;
4511 /* The insn that used to set this register doesn't exist, and
4512 this life of the register may not exist either. See if one of
4513 I3's links points to an insn that sets I2DEST. If it does,
4514 that is now the last known value for I2DEST. If we don't update
4515 this and I2 set the register to a value that depended on its old
4516 contents, we will get confused. If this insn is used, thing
4517 will be set correctly in combine_instructions. */
4518 FOR_EACH_LOG_LINK (link
, i3
)
4519 if ((set
= single_set (link
->insn
)) != 0
4520 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4521 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4523 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4525 /* If the reg formerly set in I2 died only once and that was in I3,
4526 zero its use count so it won't make `reload' do any work. */
4528 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4529 && ! i2dest_in_i2src
4530 && REGNO (i2dest
) < reg_n_sets_max
)
4531 INC_REG_N_SETS (REGNO (i2dest
), -1);
4534 if (i1
&& REG_P (i1dest
))
4536 struct insn_link
*link
;
4537 rtx_insn
*i1_insn
= 0;
4538 rtx i1_val
= 0, set
;
4540 FOR_EACH_LOG_LINK (link
, i3
)
4541 if ((set
= single_set (link
->insn
)) != 0
4542 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4543 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4545 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4548 && ! i1dest_in_i1src
4549 && REGNO (i1dest
) < reg_n_sets_max
)
4550 INC_REG_N_SETS (REGNO (i1dest
), -1);
4553 if (i0
&& REG_P (i0dest
))
4555 struct insn_link
*link
;
4556 rtx_insn
*i0_insn
= 0;
4557 rtx i0_val
= 0, set
;
4559 FOR_EACH_LOG_LINK (link
, i3
)
4560 if ((set
= single_set (link
->insn
)) != 0
4561 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4562 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4564 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4567 && ! i0dest_in_i0src
4568 && REGNO (i0dest
) < reg_n_sets_max
)
4569 INC_REG_N_SETS (REGNO (i0dest
), -1);
4572 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4573 been made to this insn. The order is important, because newi2pat
4574 can affect nonzero_bits of newpat. */
4576 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4577 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4580 if (undobuf
.other_insn
!= NULL_RTX
)
4584 fprintf (dump_file
, "modifying other_insn ");
4585 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4587 df_insn_rescan (undobuf
.other_insn
);
4590 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4594 fprintf (dump_file
, "modifying insn i0 ");
4595 dump_insn_slim (dump_file
, i0
);
4597 df_insn_rescan (i0
);
4600 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4604 fprintf (dump_file
, "modifying insn i1 ");
4605 dump_insn_slim (dump_file
, i1
);
4607 df_insn_rescan (i1
);
4610 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4614 fprintf (dump_file
, "modifying insn i2 ");
4615 dump_insn_slim (dump_file
, i2
);
4617 df_insn_rescan (i2
);
4620 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4624 fprintf (dump_file
, "modifying insn i3 ");
4625 dump_insn_slim (dump_file
, i3
);
4627 df_insn_rescan (i3
);
4630 /* Set new_direct_jump_p if a new return or simple jump instruction
4631 has been created. Adjust the CFG accordingly. */
4632 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4634 *new_direct_jump_p
= 1;
4635 mark_jump_label (PATTERN (i3
), i3
, 0);
4636 update_cfg_for_uncondjump (i3
);
4639 if (undobuf
.other_insn
!= NULL_RTX
4640 && (returnjump_p (undobuf
.other_insn
)
4641 || any_uncondjump_p (undobuf
.other_insn
)))
4643 *new_direct_jump_p
= 1;
4644 update_cfg_for_uncondjump (undobuf
.other_insn
);
4647 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4648 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4650 basic_block bb
= BLOCK_FOR_INSN (i3
);
4652 remove_edge (split_block (bb
, i3
));
4653 emit_barrier_after_bb (bb
);
4654 *new_direct_jump_p
= 1;
4657 if (undobuf
.other_insn
4658 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4659 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4661 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4663 remove_edge (split_block (bb
, undobuf
.other_insn
));
4664 emit_barrier_after_bb (bb
);
4665 *new_direct_jump_p
= 1;
4668 /* A noop might also need cleaning up of CFG, if it comes from the
4669 simplification of a jump. */
4671 && GET_CODE (newpat
) == SET
4672 && SET_SRC (newpat
) == pc_rtx
4673 && SET_DEST (newpat
) == pc_rtx
)
4675 *new_direct_jump_p
= 1;
4676 update_cfg_for_uncondjump (i3
);
4679 if (undobuf
.other_insn
!= NULL_RTX
4680 && JUMP_P (undobuf
.other_insn
)
4681 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4682 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4683 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4685 *new_direct_jump_p
= 1;
4686 update_cfg_for_uncondjump (undobuf
.other_insn
);
4689 combine_successes
++;
4692 if (added_links_insn
4693 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4694 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4695 return added_links_insn
;
4697 return newi2pat
? i2
: i3
;
4700 /* Get a marker for undoing to the current state. */
4703 get_undo_marker (void)
4705 return undobuf
.undos
;
4708 /* Undo the modifications up to the marker. */
4711 undo_to_marker (void *marker
)
4713 struct undo
*undo
, *next
;
4715 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4723 *undo
->where
.r
= undo
->old_contents
.r
;
4726 *undo
->where
.i
= undo
->old_contents
.i
;
4729 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4732 *undo
->where
.l
= undo
->old_contents
.l
;
4738 undo
->next
= undobuf
.frees
;
4739 undobuf
.frees
= undo
;
4742 undobuf
.undos
= (struct undo
*) marker
;
4745 /* Undo all the modifications recorded in undobuf. */
4753 /* We've committed to accepting the changes we made. Move all
4754 of the undos to the free list. */
4759 struct undo
*undo
, *next
;
4761 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4764 undo
->next
= undobuf
.frees
;
4765 undobuf
.frees
= undo
;
4770 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4771 where we have an arithmetic expression and return that point. LOC will
4774 try_combine will call this function to see if an insn can be split into
4778 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4781 enum rtx_code code
= GET_CODE (x
);
4783 unsigned HOST_WIDE_INT len
= 0;
4784 HOST_WIDE_INT pos
= 0;
4786 rtx inner
= NULL_RTX
;
4788 /* First special-case some codes. */
4792 #ifdef INSN_SCHEDULING
4793 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4795 if (MEM_P (SUBREG_REG (x
)))
4798 return find_split_point (&SUBREG_REG (x
), insn
, false);
4801 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4802 using LO_SUM and HIGH. */
4803 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4804 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4806 machine_mode address_mode
= get_address_mode (x
);
4809 gen_rtx_LO_SUM (address_mode
,
4810 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4812 return &XEXP (XEXP (x
, 0), 0);
4815 /* If we have a PLUS whose second operand is a constant and the
4816 address is not valid, perhaps will can split it up using
4817 the machine-specific way to split large constants. We use
4818 the first pseudo-reg (one of the virtual regs) as a placeholder;
4819 it will not remain in the result. */
4820 if (GET_CODE (XEXP (x
, 0)) == PLUS
4821 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4822 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4823 MEM_ADDR_SPACE (x
)))
4825 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4826 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4829 /* This should have produced two insns, each of which sets our
4830 placeholder. If the source of the second is a valid address,
4831 we can make put both sources together and make a split point
4835 && NEXT_INSN (seq
) != NULL_RTX
4836 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4837 && NONJUMP_INSN_P (seq
)
4838 && GET_CODE (PATTERN (seq
)) == SET
4839 && SET_DEST (PATTERN (seq
)) == reg
4840 && ! reg_mentioned_p (reg
,
4841 SET_SRC (PATTERN (seq
)))
4842 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4843 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4844 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4845 && memory_address_addr_space_p
4846 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4847 MEM_ADDR_SPACE (x
)))
4849 rtx src1
= SET_SRC (PATTERN (seq
));
4850 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4852 /* Replace the placeholder in SRC2 with SRC1. If we can
4853 find where in SRC2 it was placed, that can become our
4854 split point and we can replace this address with SRC2.
4855 Just try two obvious places. */
4857 src2
= replace_rtx (src2
, reg
, src1
);
4859 if (XEXP (src2
, 0) == src1
)
4860 split
= &XEXP (src2
, 0);
4861 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4862 && XEXP (XEXP (src2
, 0), 0) == src1
)
4863 split
= &XEXP (XEXP (src2
, 0), 0);
4867 SUBST (XEXP (x
, 0), src2
);
4872 /* If that didn't work, perhaps the first operand is complex and
4873 needs to be computed separately, so make a split point there.
4874 This will occur on machines that just support REG + CONST
4875 and have a constant moved through some previous computation. */
4877 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4878 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4879 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4880 return &XEXP (XEXP (x
, 0), 0);
4883 /* If we have a PLUS whose first operand is complex, try computing it
4884 separately by making a split there. */
4885 if (GET_CODE (XEXP (x
, 0)) == PLUS
4886 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4888 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4889 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4890 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4891 return &XEXP (XEXP (x
, 0), 0);
4895 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4896 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4897 we need to put the operand into a register. So split at that
4900 if (SET_DEST (x
) == cc0_rtx
4901 && GET_CODE (SET_SRC (x
)) != COMPARE
4902 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4903 && !OBJECT_P (SET_SRC (x
))
4904 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4905 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4906 return &SET_SRC (x
);
4908 /* See if we can split SET_SRC as it stands. */
4909 split
= find_split_point (&SET_SRC (x
), insn
, true);
4910 if (split
&& split
!= &SET_SRC (x
))
4913 /* See if we can split SET_DEST as it stands. */
4914 split
= find_split_point (&SET_DEST (x
), insn
, false);
4915 if (split
&& split
!= &SET_DEST (x
))
4918 /* See if this is a bitfield assignment with everything constant. If
4919 so, this is an IOR of an AND, so split it into that. */
4920 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4921 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4922 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4923 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4924 && CONST_INT_P (SET_SRC (x
))
4925 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4926 + INTVAL (XEXP (SET_DEST (x
), 2)))
4927 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4928 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4930 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4931 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4932 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4933 rtx dest
= XEXP (SET_DEST (x
), 0);
4934 machine_mode mode
= GET_MODE (dest
);
4935 unsigned HOST_WIDE_INT mask
4936 = (HOST_WIDE_INT_1U
<< len
) - 1;
4939 if (BITS_BIG_ENDIAN
)
4940 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4942 or_mask
= gen_int_mode (src
<< pos
, mode
);
4945 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4948 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4950 simplify_gen_binary (IOR
, mode
,
4951 simplify_gen_binary (AND
, mode
,
4956 SUBST (SET_DEST (x
), dest
);
4958 split
= find_split_point (&SET_SRC (x
), insn
, true);
4959 if (split
&& split
!= &SET_SRC (x
))
4963 /* Otherwise, see if this is an operation that we can split into two.
4964 If so, try to split that. */
4965 code
= GET_CODE (SET_SRC (x
));
4970 /* If we are AND'ing with a large constant that is only a single
4971 bit and the result is only being used in a context where we
4972 need to know if it is zero or nonzero, replace it with a bit
4973 extraction. This will avoid the large constant, which might
4974 have taken more than one insn to make. If the constant were
4975 not a valid argument to the AND but took only one insn to make,
4976 this is no worse, but if it took more than one insn, it will
4979 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4980 && REG_P (XEXP (SET_SRC (x
), 0))
4981 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4982 && REG_P (SET_DEST (x
))
4983 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4984 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4985 && XEXP (*split
, 0) == SET_DEST (x
)
4986 && XEXP (*split
, 1) == const0_rtx
)
4988 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4989 XEXP (SET_SRC (x
), 0),
4990 pos
, NULL_RTX
, 1, 1, 0, 0);
4991 if (extraction
!= 0)
4993 SUBST (SET_SRC (x
), extraction
);
4994 return find_split_point (loc
, insn
, false);
5000 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5001 is known to be on, this can be converted into a NEG of a shift. */
5002 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5003 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5004 && 1 <= (pos
= exact_log2
5005 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5006 GET_MODE (XEXP (SET_SRC (x
), 0))))))
5008 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5012 gen_rtx_LSHIFTRT (mode
,
5013 XEXP (SET_SRC (x
), 0),
5016 split
= find_split_point (&SET_SRC (x
), insn
, true);
5017 if (split
&& split
!= &SET_SRC (x
))
5023 inner
= XEXP (SET_SRC (x
), 0);
5025 /* We can't optimize if either mode is a partial integer
5026 mode as we don't know how many bits are significant
5028 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5029 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5033 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5039 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5040 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5042 inner
= XEXP (SET_SRC (x
), 0);
5043 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5044 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5046 if (BITS_BIG_ENDIAN
)
5047 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5048 unsignedp
= (code
== ZERO_EXTRACT
);
5057 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5059 machine_mode mode
= GET_MODE (SET_SRC (x
));
5061 /* For unsigned, we have a choice of a shift followed by an
5062 AND or two shifts. Use two shifts for field sizes where the
5063 constant might be too large. We assume here that we can
5064 always at least get 8-bit constants in an AND insn, which is
5065 true for every current RISC. */
5067 if (unsignedp
&& len
<= 8)
5069 unsigned HOST_WIDE_INT mask
5070 = (HOST_WIDE_INT_1U
<< len
) - 1;
5074 (mode
, gen_lowpart (mode
, inner
),
5076 gen_int_mode (mask
, mode
)));
5078 split
= find_split_point (&SET_SRC (x
), insn
, true);
5079 if (split
&& split
!= &SET_SRC (x
))
5086 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5087 gen_rtx_ASHIFT (mode
,
5088 gen_lowpart (mode
, inner
),
5089 GEN_INT (GET_MODE_PRECISION (mode
)
5091 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5093 split
= find_split_point (&SET_SRC (x
), insn
, true);
5094 if (split
&& split
!= &SET_SRC (x
))
5099 /* See if this is a simple operation with a constant as the second
5100 operand. It might be that this constant is out of range and hence
5101 could be used as a split point. */
5102 if (BINARY_P (SET_SRC (x
))
5103 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5104 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5105 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5106 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5107 return &XEXP (SET_SRC (x
), 1);
5109 /* Finally, see if this is a simple operation with its first operand
5110 not in a register. The operation might require this operand in a
5111 register, so return it as a split point. We can always do this
5112 because if the first operand were another operation, we would have
5113 already found it as a split point. */
5114 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5115 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5116 return &XEXP (SET_SRC (x
), 0);
5122 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5123 it is better to write this as (not (ior A B)) so we can split it.
5124 Similarly for IOR. */
5125 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5128 gen_rtx_NOT (GET_MODE (x
),
5129 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5131 XEXP (XEXP (x
, 0), 0),
5132 XEXP (XEXP (x
, 1), 0))));
5133 return find_split_point (loc
, insn
, set_src
);
5136 /* Many RISC machines have a large set of logical insns. If the
5137 second operand is a NOT, put it first so we will try to split the
5138 other operand first. */
5139 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5141 rtx tem
= XEXP (x
, 0);
5142 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5143 SUBST (XEXP (x
, 1), tem
);
5149 /* Canonicalization can produce (minus A (mult B C)), where C is a
5150 constant. It may be better to try splitting (plus (mult B -C) A)
5151 instead if this isn't a multiply by a power of two. */
5152 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5153 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5154 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5156 machine_mode mode
= GET_MODE (x
);
5157 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5158 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5159 SUBST (*loc
, gen_rtx_PLUS (mode
,
5161 XEXP (XEXP (x
, 1), 0),
5162 gen_int_mode (other_int
,
5165 return find_split_point (loc
, insn
, set_src
);
5168 /* Split at a multiply-accumulate instruction. However if this is
5169 the SET_SRC, we likely do not have such an instruction and it's
5170 worthless to try this split. */
5172 && (GET_CODE (XEXP (x
, 0)) == MULT
5173 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5174 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5181 /* Otherwise, select our actions depending on our rtx class. */
5182 switch (GET_RTX_CLASS (code
))
5184 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5186 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5191 case RTX_COMM_ARITH
:
5193 case RTX_COMM_COMPARE
:
5194 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5199 /* Some machines have (and (shift ...) ...) insns. If X is not
5200 an AND, but XEXP (X, 0) is, use it as our split point. */
5201 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5202 return &XEXP (x
, 0);
5204 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5210 /* Otherwise, we don't have a split point. */
5215 /* Throughout X, replace FROM with TO, and return the result.
5216 The result is TO if X is FROM;
5217 otherwise the result is X, but its contents may have been modified.
5218 If they were modified, a record was made in undobuf so that
5219 undo_all will (among other things) return X to its original state.
5221 If the number of changes necessary is too much to record to undo,
5222 the excess changes are not made, so the result is invalid.
5223 The changes already made can still be undone.
5224 undobuf.num_undo is incremented for such changes, so by testing that
5225 the caller can tell whether the result is valid.
5227 `n_occurrences' is incremented each time FROM is replaced.
5229 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5231 IN_COND is nonzero if we are at the top level of a condition.
5233 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5234 by copying if `n_occurrences' is nonzero. */
5237 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5239 enum rtx_code code
= GET_CODE (x
);
5240 machine_mode op0_mode
= VOIDmode
;
5245 /* Two expressions are equal if they are identical copies of a shared
5246 RTX or if they are both registers with the same register number
5249 #define COMBINE_RTX_EQUAL_P(X,Y) \
5251 || (REG_P (X) && REG_P (Y) \
5252 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5254 /* Do not substitute into clobbers of regs -- this will never result in
5256 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5259 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5262 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5265 /* If X and FROM are the same register but different modes, they
5266 will not have been seen as equal above. However, the log links code
5267 will make a LOG_LINKS entry for that case. If we do nothing, we
5268 will try to rerecognize our original insn and, when it succeeds,
5269 we will delete the feeding insn, which is incorrect.
5271 So force this insn not to match in this (rare) case. */
5272 if (! in_dest
&& code
== REG
&& REG_P (from
)
5273 && reg_overlap_mentioned_p (x
, from
))
5274 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5276 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5277 of which may contain things that can be combined. */
5278 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5281 /* It is possible to have a subexpression appear twice in the insn.
5282 Suppose that FROM is a register that appears within TO.
5283 Then, after that subexpression has been scanned once by `subst',
5284 the second time it is scanned, TO may be found. If we were
5285 to scan TO here, we would find FROM within it and create a
5286 self-referent rtl structure which is completely wrong. */
5287 if (COMBINE_RTX_EQUAL_P (x
, to
))
5290 /* Parallel asm_operands need special attention because all of the
5291 inputs are shared across the arms. Furthermore, unsharing the
5292 rtl results in recognition failures. Failure to handle this case
5293 specially can result in circular rtl.
5295 Solve this by doing a normal pass across the first entry of the
5296 parallel, and only processing the SET_DESTs of the subsequent
5299 if (code
== PARALLEL
5300 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5301 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5303 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5305 /* If this substitution failed, this whole thing fails. */
5306 if (GET_CODE (new_rtx
) == CLOBBER
5307 && XEXP (new_rtx
, 0) == const0_rtx
)
5310 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5312 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5314 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5317 && GET_CODE (dest
) != CC0
5318 && GET_CODE (dest
) != PC
)
5320 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5322 /* If this substitution failed, this whole thing fails. */
5323 if (GET_CODE (new_rtx
) == CLOBBER
5324 && XEXP (new_rtx
, 0) == const0_rtx
)
5327 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5333 len
= GET_RTX_LENGTH (code
);
5334 fmt
= GET_RTX_FORMAT (code
);
5336 /* We don't need to process a SET_DEST that is a register, CC0,
5337 or PC, so set up to skip this common case. All other cases
5338 where we want to suppress replacing something inside a
5339 SET_SRC are handled via the IN_DEST operand. */
5341 && (REG_P (SET_DEST (x
))
5342 || GET_CODE (SET_DEST (x
)) == CC0
5343 || GET_CODE (SET_DEST (x
)) == PC
))
5346 /* Trying to simplify the operands of a widening MULT is not likely
5347 to create RTL matching a machine insn. */
5349 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5350 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5351 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5352 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5353 && REG_P (XEXP (XEXP (x
, 0), 0))
5354 && REG_P (XEXP (XEXP (x
, 1), 0))
5359 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5362 op0_mode
= GET_MODE (XEXP (x
, 0));
5364 for (i
= 0; i
< len
; i
++)
5369 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5371 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5373 new_rtx
= (unique_copy
&& n_occurrences
5374 ? copy_rtx (to
) : to
);
5379 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5382 /* If this substitution failed, this whole thing
5384 if (GET_CODE (new_rtx
) == CLOBBER
5385 && XEXP (new_rtx
, 0) == const0_rtx
)
5389 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5392 else if (fmt
[i
] == 'e')
5394 /* If this is a register being set, ignore it. */
5395 new_rtx
= XEXP (x
, i
);
5398 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5400 || code
== STRICT_LOW_PART
))
5403 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5405 /* In general, don't install a subreg involving two
5406 modes not tieable. It can worsen register
5407 allocation, and can even make invalid reload
5408 insns, since the reg inside may need to be copied
5409 from in the outside mode, and that may be invalid
5410 if it is an fp reg copied in integer mode.
5412 We allow two exceptions to this: It is valid if
5413 it is inside another SUBREG and the mode of that
5414 SUBREG and the mode of the inside of TO is
5415 tieable and it is valid if X is a SET that copies
5418 if (GET_CODE (to
) == SUBREG
5419 && ! MODES_TIEABLE_P (GET_MODE (to
),
5420 GET_MODE (SUBREG_REG (to
)))
5421 && ! (code
== SUBREG
5422 && MODES_TIEABLE_P (GET_MODE (x
),
5423 GET_MODE (SUBREG_REG (to
))))
5427 && XEXP (x
, 0) == cc0_rtx
))))
5428 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5432 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5433 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5436 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5438 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5442 /* If we are in a SET_DEST, suppress most cases unless we
5443 have gone inside a MEM, in which case we want to
5444 simplify the address. We assume here that things that
5445 are actually part of the destination have their inner
5446 parts in the first expression. This is true for SUBREG,
5447 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5448 things aside from REG and MEM that should appear in a
5450 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5452 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5453 || code
== ZERO_EXTRACT
))
5456 code
== IF_THEN_ELSE
&& i
== 0,
5459 /* If we found that we will have to reject this combination,
5460 indicate that by returning the CLOBBER ourselves, rather than
5461 an expression containing it. This will speed things up as
5462 well as prevent accidents where two CLOBBERs are considered
5463 to be equal, thus producing an incorrect simplification. */
5465 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5468 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5470 machine_mode mode
= GET_MODE (x
);
5472 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5473 GET_MODE (SUBREG_REG (x
)),
5476 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5478 else if (CONST_SCALAR_INT_P (new_rtx
)
5479 && GET_CODE (x
) == ZERO_EXTEND
)
5481 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5482 new_rtx
, GET_MODE (XEXP (x
, 0)));
5486 SUBST (XEXP (x
, i
), new_rtx
);
5491 /* Check if we are loading something from the constant pool via float
5492 extension; in this case we would undo compress_float_constant
5493 optimization and degenerate constant load to an immediate value. */
5494 if (GET_CODE (x
) == FLOAT_EXTEND
5495 && MEM_P (XEXP (x
, 0))
5496 && MEM_READONLY_P (XEXP (x
, 0)))
5498 rtx tmp
= avoid_constant_pool_reference (x
);
5503 /* Try to simplify X. If the simplification changed the code, it is likely
5504 that further simplification will help, so loop, but limit the number
5505 of repetitions that will be performed. */
5507 for (i
= 0; i
< 4; i
++)
5509 /* If X is sufficiently simple, don't bother trying to do anything
5511 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5512 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5514 if (GET_CODE (x
) == code
)
5517 code
= GET_CODE (x
);
5519 /* We no longer know the original mode of operand 0 since we
5520 have changed the form of X) */
5521 op0_mode
= VOIDmode
;
5527 /* If X is a commutative operation whose operands are not in the canonical
5528 order, use substitutions to swap them. */
5531 maybe_swap_commutative_operands (rtx x
)
5533 if (COMMUTATIVE_ARITH_P (x
)
5534 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5536 rtx temp
= XEXP (x
, 0);
5537 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5538 SUBST (XEXP (x
, 1), temp
);
5542 /* Simplify X, a piece of RTL. We just operate on the expression at the
5543 outer level; call `subst' to simplify recursively. Return the new
5546 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5547 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5551 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5554 enum rtx_code code
= GET_CODE (x
);
5555 machine_mode mode
= GET_MODE (x
);
5559 /* If this is a commutative operation, put a constant last and a complex
5560 expression first. We don't need to do this for comparisons here. */
5561 maybe_swap_commutative_operands (x
);
5563 /* Try to fold this expression in case we have constants that weren't
5566 switch (GET_RTX_CLASS (code
))
5569 if (op0_mode
== VOIDmode
)
5570 op0_mode
= GET_MODE (XEXP (x
, 0));
5571 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5574 case RTX_COMM_COMPARE
:
5576 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5577 if (cmp_mode
== VOIDmode
)
5579 cmp_mode
= GET_MODE (XEXP (x
, 1));
5580 if (cmp_mode
== VOIDmode
)
5581 cmp_mode
= op0_mode
;
5583 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5584 XEXP (x
, 0), XEXP (x
, 1));
5587 case RTX_COMM_ARITH
:
5589 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5591 case RTX_BITFIELD_OPS
:
5593 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5594 XEXP (x
, 1), XEXP (x
, 2));
5603 code
= GET_CODE (temp
);
5604 op0_mode
= VOIDmode
;
5605 mode
= GET_MODE (temp
);
5608 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5609 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5610 things. Check for cases where both arms are testing the same
5613 Don't do anything if all operands are very simple. */
5616 && ((!OBJECT_P (XEXP (x
, 0))
5617 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5618 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5619 || (!OBJECT_P (XEXP (x
, 1))
5620 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5621 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5623 && (!OBJECT_P (XEXP (x
, 0))
5624 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5625 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5627 rtx cond
, true_rtx
, false_rtx
;
5629 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5631 /* If everything is a comparison, what we have is highly unlikely
5632 to be simpler, so don't use it. */
5633 && ! (COMPARISON_P (x
)
5634 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5636 rtx cop1
= const0_rtx
;
5637 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5639 if (cond_code
== NE
&& COMPARISON_P (cond
))
5642 /* Simplify the alternative arms; this may collapse the true and
5643 false arms to store-flag values. Be careful to use copy_rtx
5644 here since true_rtx or false_rtx might share RTL with x as a
5645 result of the if_then_else_cond call above. */
5646 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5647 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5649 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5650 is unlikely to be simpler. */
5651 if (general_operand (true_rtx
, VOIDmode
)
5652 && general_operand (false_rtx
, VOIDmode
))
5654 enum rtx_code reversed
;
5656 /* Restarting if we generate a store-flag expression will cause
5657 us to loop. Just drop through in this case. */
5659 /* If the result values are STORE_FLAG_VALUE and zero, we can
5660 just make the comparison operation. */
5661 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5662 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5664 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5665 && ((reversed
= reversed_comparison_code_parts
5666 (cond_code
, cond
, cop1
, NULL
))
5668 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5671 /* Likewise, we can make the negate of a comparison operation
5672 if the result values are - STORE_FLAG_VALUE and zero. */
5673 else if (CONST_INT_P (true_rtx
)
5674 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5675 && false_rtx
== const0_rtx
)
5676 x
= simplify_gen_unary (NEG
, mode
,
5677 simplify_gen_relational (cond_code
,
5681 else if (CONST_INT_P (false_rtx
)
5682 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5683 && true_rtx
== const0_rtx
5684 && ((reversed
= reversed_comparison_code_parts
5685 (cond_code
, cond
, cop1
, NULL
))
5687 x
= simplify_gen_unary (NEG
, mode
,
5688 simplify_gen_relational (reversed
,
5693 return gen_rtx_IF_THEN_ELSE (mode
,
5694 simplify_gen_relational (cond_code
,
5699 true_rtx
, false_rtx
);
5701 code
= GET_CODE (x
);
5702 op0_mode
= VOIDmode
;
5707 /* First see if we can apply the inverse distributive law. */
5708 if (code
== PLUS
|| code
== MINUS
5709 || code
== AND
|| code
== IOR
|| code
== XOR
)
5711 x
= apply_distributive_law (x
);
5712 code
= GET_CODE (x
);
5713 op0_mode
= VOIDmode
;
5716 /* If CODE is an associative operation not otherwise handled, see if we
5717 can associate some operands. This can win if they are constants or
5718 if they are logically related (i.e. (a & b) & a). */
5719 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5720 || code
== AND
|| code
== IOR
|| code
== XOR
5721 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5722 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5723 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5725 if (GET_CODE (XEXP (x
, 0)) == code
)
5727 rtx other
= XEXP (XEXP (x
, 0), 0);
5728 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5729 rtx inner_op1
= XEXP (x
, 1);
5732 /* Make sure we pass the constant operand if any as the second
5733 one if this is a commutative operation. */
5734 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5735 std::swap (inner_op0
, inner_op1
);
5736 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5737 : code
== DIV
? MULT
5739 mode
, inner_op0
, inner_op1
);
5741 /* For commutative operations, try the other pair if that one
5743 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5745 other
= XEXP (XEXP (x
, 0), 1);
5746 inner
= simplify_binary_operation (code
, mode
,
5747 XEXP (XEXP (x
, 0), 0),
5752 return simplify_gen_binary (code
, mode
, other
, inner
);
5756 /* A little bit of algebraic simplification here. */
5760 /* Ensure that our address has any ASHIFTs converted to MULT in case
5761 address-recognizing predicates are called later. */
5762 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5763 SUBST (XEXP (x
, 0), temp
);
5767 if (op0_mode
== VOIDmode
)
5768 op0_mode
= GET_MODE (SUBREG_REG (x
));
5770 /* See if this can be moved to simplify_subreg. */
5771 if (CONSTANT_P (SUBREG_REG (x
))
5772 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5773 /* Don't call gen_lowpart if the inner mode
5774 is VOIDmode and we cannot simplify it, as SUBREG without
5775 inner mode is invalid. */
5776 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5777 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5778 return gen_lowpart (mode
, SUBREG_REG (x
));
5780 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5784 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5789 /* If op is known to have all lower bits zero, the result is zero. */
5791 && SCALAR_INT_MODE_P (mode
)
5792 && SCALAR_INT_MODE_P (op0_mode
)
5793 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5794 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5795 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5796 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5797 & GET_MODE_MASK (mode
)) == 0)
5798 return CONST0_RTX (mode
);
5801 /* Don't change the mode of the MEM if that would change the meaning
5803 if (MEM_P (SUBREG_REG (x
))
5804 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5805 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5806 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5807 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5809 /* Note that we cannot do any narrowing for non-constants since
5810 we might have been counting on using the fact that some bits were
5811 zero. We now do this in the SET. */
5816 temp
= expand_compound_operation (XEXP (x
, 0));
5818 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5819 replaced by (lshiftrt X C). This will convert
5820 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5822 if (GET_CODE (temp
) == ASHIFTRT
5823 && CONST_INT_P (XEXP (temp
, 1))
5824 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5825 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5826 INTVAL (XEXP (temp
, 1)));
5828 /* If X has only a single bit that might be nonzero, say, bit I, convert
5829 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5830 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5831 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5832 or a SUBREG of one since we'd be making the expression more
5833 complex if it was just a register. */
5836 && ! (GET_CODE (temp
) == SUBREG
5837 && REG_P (SUBREG_REG (temp
)))
5838 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5840 rtx temp1
= simplify_shift_const
5841 (NULL_RTX
, ASHIFTRT
, mode
,
5842 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5843 GET_MODE_PRECISION (mode
) - 1 - i
),
5844 GET_MODE_PRECISION (mode
) - 1 - i
);
5846 /* If all we did was surround TEMP with the two shifts, we
5847 haven't improved anything, so don't use it. Otherwise,
5848 we are better off with TEMP1. */
5849 if (GET_CODE (temp1
) != ASHIFTRT
5850 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5851 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5857 /* We can't handle truncation to a partial integer mode here
5858 because we don't know the real bitsize of the partial
5860 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5863 if (HWI_COMPUTABLE_MODE_P (mode
))
5865 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5866 GET_MODE_MASK (mode
), 0));
5868 /* We can truncate a constant value and return it. */
5869 if (CONST_INT_P (XEXP (x
, 0)))
5870 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5872 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5873 whose value is a comparison can be replaced with a subreg if
5874 STORE_FLAG_VALUE permits. */
5875 if (HWI_COMPUTABLE_MODE_P (mode
)
5876 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5877 && (temp
= get_last_value (XEXP (x
, 0)))
5878 && COMPARISON_P (temp
))
5879 return gen_lowpart (mode
, XEXP (x
, 0));
5883 /* (const (const X)) can become (const X). Do it this way rather than
5884 returning the inner CONST since CONST can be shared with a
5886 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5887 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5891 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5892 can add in an offset. find_split_point will split this address up
5893 again if it doesn't match. */
5894 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5895 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5900 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5901 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5902 bit-field and can be replaced by either a sign_extend or a
5903 sign_extract. The `and' may be a zero_extend and the two
5904 <c>, -<c> constants may be reversed. */
5905 if (GET_CODE (XEXP (x
, 0)) == XOR
5906 && CONST_INT_P (XEXP (x
, 1))
5907 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5908 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5909 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5910 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5911 && HWI_COMPUTABLE_MODE_P (mode
)
5912 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5913 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5914 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5915 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
5916 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5917 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5918 == (unsigned int) i
+ 1))))
5919 return simplify_shift_const
5920 (NULL_RTX
, ASHIFTRT
, mode
,
5921 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5922 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5923 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5924 GET_MODE_PRECISION (mode
) - (i
+ 1));
5926 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5927 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5928 the bitsize of the mode - 1. This allows simplification of
5929 "a = (b & 8) == 0;" */
5930 if (XEXP (x
, 1) == constm1_rtx
5931 && !REG_P (XEXP (x
, 0))
5932 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5933 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5934 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5935 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5936 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5937 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5938 GET_MODE_PRECISION (mode
) - 1),
5939 GET_MODE_PRECISION (mode
) - 1);
5941 /* If we are adding two things that have no bits in common, convert
5942 the addition into an IOR. This will often be further simplified,
5943 for example in cases like ((a & 1) + (a & 2)), which can
5946 if (HWI_COMPUTABLE_MODE_P (mode
)
5947 && (nonzero_bits (XEXP (x
, 0), mode
)
5948 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5950 /* Try to simplify the expression further. */
5951 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5952 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5954 /* If we could, great. If not, do not go ahead with the IOR
5955 replacement, since PLUS appears in many special purpose
5956 address arithmetic instructions. */
5957 if (GET_CODE (temp
) != CLOBBER
5958 && (GET_CODE (temp
) != IOR
5959 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5960 || XEXP (temp
, 1) != XEXP (x
, 1))
5961 && (XEXP (temp
, 0) != XEXP (x
, 1)
5962 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5966 /* Canonicalize x + x into x << 1. */
5967 if (GET_MODE_CLASS (mode
) == MODE_INT
5968 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
5969 && !side_effects_p (XEXP (x
, 0)))
5970 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
5975 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5976 (and <foo> (const_int pow2-1)) */
5977 if (GET_CODE (XEXP (x
, 1)) == AND
5978 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5979 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
5980 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5981 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5982 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5986 /* If we have (mult (plus A B) C), apply the distributive law and then
5987 the inverse distributive law to see if things simplify. This
5988 occurs mostly in addresses, often when unrolling loops. */
5990 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5992 rtx result
= distribute_and_simplify_rtx (x
, 0);
5997 /* Try simplify a*(b/c) as (a*b)/c. */
5998 if (FLOAT_MODE_P (mode
) && flag_associative_math
5999 && GET_CODE (XEXP (x
, 0)) == DIV
)
6001 rtx tem
= simplify_binary_operation (MULT
, mode
,
6002 XEXP (XEXP (x
, 0), 0),
6005 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6010 /* If this is a divide by a power of two, treat it as a shift if
6011 its first operand is a shift. */
6012 if (CONST_INT_P (XEXP (x
, 1))
6013 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6014 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6015 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6016 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6017 || GET_CODE (XEXP (x
, 0)) == ROTATE
6018 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6019 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
6023 case GT
: case GTU
: case GE
: case GEU
:
6024 case LT
: case LTU
: case LE
: case LEU
:
6025 case UNEQ
: case LTGT
:
6026 case UNGT
: case UNGE
:
6027 case UNLT
: case UNLE
:
6028 case UNORDERED
: case ORDERED
:
6029 /* If the first operand is a condition code, we can't do anything
6031 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6032 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6033 && ! CC0_P (XEXP (x
, 0))))
6035 rtx op0
= XEXP (x
, 0);
6036 rtx op1
= XEXP (x
, 1);
6037 enum rtx_code new_code
;
6039 if (GET_CODE (op0
) == COMPARE
)
6040 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6042 /* Simplify our comparison, if possible. */
6043 new_code
= simplify_comparison (code
, &op0
, &op1
);
6045 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6046 if only the low-order bit is possibly nonzero in X (such as when
6047 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6048 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6049 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6052 Remove any ZERO_EXTRACT we made when thinking this was a
6053 comparison. It may now be simpler to use, e.g., an AND. If a
6054 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6055 the call to make_compound_operation in the SET case.
6057 Don't apply these optimizations if the caller would
6058 prefer a comparison rather than a value.
6059 E.g., for the condition in an IF_THEN_ELSE most targets need
6060 an explicit comparison. */
6065 else if (STORE_FLAG_VALUE
== 1
6066 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6067 && op1
== const0_rtx
6068 && mode
== GET_MODE (op0
)
6069 && nonzero_bits (op0
, mode
) == 1)
6070 return gen_lowpart (mode
,
6071 expand_compound_operation (op0
));
6073 else if (STORE_FLAG_VALUE
== 1
6074 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6075 && op1
== const0_rtx
6076 && mode
== GET_MODE (op0
)
6077 && (num_sign_bit_copies (op0
, mode
)
6078 == GET_MODE_PRECISION (mode
)))
6080 op0
= expand_compound_operation (op0
);
6081 return simplify_gen_unary (NEG
, mode
,
6082 gen_lowpart (mode
, op0
),
6086 else if (STORE_FLAG_VALUE
== 1
6087 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6088 && op1
== const0_rtx
6089 && mode
== GET_MODE (op0
)
6090 && nonzero_bits (op0
, mode
) == 1)
6092 op0
= expand_compound_operation (op0
);
6093 return simplify_gen_binary (XOR
, mode
,
6094 gen_lowpart (mode
, op0
),
6098 else if (STORE_FLAG_VALUE
== 1
6099 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6100 && op1
== const0_rtx
6101 && mode
== GET_MODE (op0
)
6102 && (num_sign_bit_copies (op0
, mode
)
6103 == GET_MODE_PRECISION (mode
)))
6105 op0
= expand_compound_operation (op0
);
6106 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6109 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6114 else if (STORE_FLAG_VALUE
== -1
6115 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6116 && op1
== const0_rtx
6117 && mode
== GET_MODE (op0
)
6118 && (num_sign_bit_copies (op0
, mode
)
6119 == GET_MODE_PRECISION (mode
)))
6120 return gen_lowpart (mode
,
6121 expand_compound_operation (op0
));
6123 else if (STORE_FLAG_VALUE
== -1
6124 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6125 && op1
== const0_rtx
6126 && mode
== GET_MODE (op0
)
6127 && nonzero_bits (op0
, mode
) == 1)
6129 op0
= expand_compound_operation (op0
);
6130 return simplify_gen_unary (NEG
, mode
,
6131 gen_lowpart (mode
, op0
),
6135 else if (STORE_FLAG_VALUE
== -1
6136 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6137 && op1
== const0_rtx
6138 && mode
== GET_MODE (op0
)
6139 && (num_sign_bit_copies (op0
, mode
)
6140 == GET_MODE_PRECISION (mode
)))
6142 op0
= expand_compound_operation (op0
);
6143 return simplify_gen_unary (NOT
, mode
,
6144 gen_lowpart (mode
, op0
),
6148 /* If X is 0/1, (eq X 0) is X-1. */
6149 else if (STORE_FLAG_VALUE
== -1
6150 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6151 && op1
== const0_rtx
6152 && mode
== GET_MODE (op0
)
6153 && nonzero_bits (op0
, mode
) == 1)
6155 op0
= expand_compound_operation (op0
);
6156 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6159 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6160 one bit that might be nonzero, we can convert (ne x 0) to
6161 (ashift x c) where C puts the bit in the sign bit. Remove any
6162 AND with STORE_FLAG_VALUE when we are done, since we are only
6163 going to test the sign bit. */
6164 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6165 && HWI_COMPUTABLE_MODE_P (mode
)
6166 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6167 && op1
== const0_rtx
6168 && mode
== GET_MODE (op0
)
6169 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6171 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6172 expand_compound_operation (op0
),
6173 GET_MODE_PRECISION (mode
) - 1 - i
);
6174 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6180 /* If the code changed, return a whole new comparison.
6181 We also need to avoid using SUBST in cases where
6182 simplify_comparison has widened a comparison with a CONST_INT,
6183 since in that case the wider CONST_INT may fail the sanity
6184 checks in do_SUBST. */
6185 if (new_code
!= code
6186 || (CONST_INT_P (op1
)
6187 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6188 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6189 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6191 /* Otherwise, keep this operation, but maybe change its operands.
6192 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6193 SUBST (XEXP (x
, 0), op0
);
6194 SUBST (XEXP (x
, 1), op1
);
6199 return simplify_if_then_else (x
);
6205 /* If we are processing SET_DEST, we are done. */
6209 return expand_compound_operation (x
);
6212 return simplify_set (x
);
6216 return simplify_logical (x
);
6223 /* If this is a shift by a constant amount, simplify it. */
6224 if (CONST_INT_P (XEXP (x
, 1)))
6225 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6226 INTVAL (XEXP (x
, 1)));
6228 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6230 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6232 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6244 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6247 simplify_if_then_else (rtx x
)
6249 machine_mode mode
= GET_MODE (x
);
6250 rtx cond
= XEXP (x
, 0);
6251 rtx true_rtx
= XEXP (x
, 1);
6252 rtx false_rtx
= XEXP (x
, 2);
6253 enum rtx_code true_code
= GET_CODE (cond
);
6254 int comparison_p
= COMPARISON_P (cond
);
6257 enum rtx_code false_code
;
6260 /* Simplify storing of the truth value. */
6261 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6262 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6263 XEXP (cond
, 0), XEXP (cond
, 1));
6265 /* Also when the truth value has to be reversed. */
6267 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6268 && (reversed
= reversed_comparison (cond
, mode
)))
6271 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6272 in it is being compared against certain values. Get the true and false
6273 comparisons and see if that says anything about the value of each arm. */
6276 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6278 && REG_P (XEXP (cond
, 0)))
6281 rtx from
= XEXP (cond
, 0);
6282 rtx true_val
= XEXP (cond
, 1);
6283 rtx false_val
= true_val
;
6286 /* If FALSE_CODE is EQ, swap the codes and arms. */
6288 if (false_code
== EQ
)
6290 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6291 std::swap (true_rtx
, false_rtx
);
6294 /* If we are comparing against zero and the expression being tested has
6295 only a single bit that might be nonzero, that is its value when it is
6296 not equal to zero. Similarly if it is known to be -1 or 0. */
6298 if (true_code
== EQ
&& true_val
== const0_rtx
6299 && pow2p_hwi (nzb
= nonzero_bits (from
, GET_MODE (from
))))
6302 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6304 else if (true_code
== EQ
&& true_val
== const0_rtx
6305 && (num_sign_bit_copies (from
, GET_MODE (from
))
6306 == GET_MODE_PRECISION (GET_MODE (from
))))
6309 false_val
= constm1_rtx
;
6312 /* Now simplify an arm if we know the value of the register in the
6313 branch and it is used in the arm. Be careful due to the potential
6314 of locally-shared RTL. */
6316 if (reg_mentioned_p (from
, true_rtx
))
6317 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6319 pc_rtx
, pc_rtx
, 0, 0, 0);
6320 if (reg_mentioned_p (from
, false_rtx
))
6321 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6323 pc_rtx
, pc_rtx
, 0, 0, 0);
6325 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6326 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6328 true_rtx
= XEXP (x
, 1);
6329 false_rtx
= XEXP (x
, 2);
6330 true_code
= GET_CODE (cond
);
6333 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6334 reversed, do so to avoid needing two sets of patterns for
6335 subtract-and-branch insns. Similarly if we have a constant in the true
6336 arm, the false arm is the same as the first operand of the comparison, or
6337 the false arm is more complicated than the true arm. */
6340 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6341 && (true_rtx
== pc_rtx
6342 || (CONSTANT_P (true_rtx
)
6343 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6344 || true_rtx
== const0_rtx
6345 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6346 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6347 && !OBJECT_P (false_rtx
))
6348 || reg_mentioned_p (true_rtx
, false_rtx
)
6349 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6351 true_code
= reversed_comparison_code (cond
, NULL
);
6352 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6353 SUBST (XEXP (x
, 1), false_rtx
);
6354 SUBST (XEXP (x
, 2), true_rtx
);
6356 std::swap (true_rtx
, false_rtx
);
6359 /* It is possible that the conditional has been simplified out. */
6360 true_code
= GET_CODE (cond
);
6361 comparison_p
= COMPARISON_P (cond
);
6364 /* If the two arms are identical, we don't need the comparison. */
6366 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6369 /* Convert a == b ? b : a to "a". */
6370 if (true_code
== EQ
&& ! side_effects_p (cond
)
6371 && !HONOR_NANS (mode
)
6372 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6373 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6375 else if (true_code
== NE
&& ! side_effects_p (cond
)
6376 && !HONOR_NANS (mode
)
6377 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6378 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6381 /* Look for cases where we have (abs x) or (neg (abs X)). */
6383 if (GET_MODE_CLASS (mode
) == MODE_INT
6385 && XEXP (cond
, 1) == const0_rtx
6386 && GET_CODE (false_rtx
) == NEG
6387 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6388 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6389 && ! side_effects_p (true_rtx
))
6394 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6398 simplify_gen_unary (NEG
, mode
,
6399 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6405 /* Look for MIN or MAX. */
6407 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6409 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6410 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6411 && ! side_effects_p (cond
))
6416 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6419 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6422 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6425 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6430 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6431 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6432 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6433 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6434 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6435 neither 1 or -1, but it isn't worth checking for. */
6437 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6439 && GET_MODE_CLASS (mode
) == MODE_INT
6440 && ! side_effects_p (x
))
6442 rtx t
= make_compound_operation (true_rtx
, SET
);
6443 rtx f
= make_compound_operation (false_rtx
, SET
);
6444 rtx cond_op0
= XEXP (cond
, 0);
6445 rtx cond_op1
= XEXP (cond
, 1);
6446 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6447 machine_mode m
= mode
;
6448 rtx z
= 0, c1
= NULL_RTX
;
6450 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6451 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6452 || GET_CODE (t
) == ASHIFT
6453 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6454 && rtx_equal_p (XEXP (t
, 0), f
))
6455 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6457 /* If an identity-zero op is commutative, check whether there
6458 would be a match if we swapped the operands. */
6459 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6460 || GET_CODE (t
) == XOR
)
6461 && rtx_equal_p (XEXP (t
, 1), f
))
6462 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6463 else if (GET_CODE (t
) == SIGN_EXTEND
6464 && (GET_CODE (XEXP (t
, 0)) == PLUS
6465 || GET_CODE (XEXP (t
, 0)) == MINUS
6466 || GET_CODE (XEXP (t
, 0)) == IOR
6467 || GET_CODE (XEXP (t
, 0)) == XOR
6468 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6469 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6470 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6471 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6472 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6473 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6474 && (num_sign_bit_copies (f
, GET_MODE (f
))
6476 (GET_MODE_PRECISION (mode
)
6477 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6479 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6480 extend_op
= SIGN_EXTEND
;
6481 m
= GET_MODE (XEXP (t
, 0));
6483 else if (GET_CODE (t
) == SIGN_EXTEND
6484 && (GET_CODE (XEXP (t
, 0)) == PLUS
6485 || GET_CODE (XEXP (t
, 0)) == IOR
6486 || GET_CODE (XEXP (t
, 0)) == XOR
)
6487 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6488 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6489 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6490 && (num_sign_bit_copies (f
, GET_MODE (f
))
6492 (GET_MODE_PRECISION (mode
)
6493 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6495 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6496 extend_op
= SIGN_EXTEND
;
6497 m
= GET_MODE (XEXP (t
, 0));
6499 else if (GET_CODE (t
) == ZERO_EXTEND
6500 && (GET_CODE (XEXP (t
, 0)) == PLUS
6501 || GET_CODE (XEXP (t
, 0)) == MINUS
6502 || GET_CODE (XEXP (t
, 0)) == IOR
6503 || GET_CODE (XEXP (t
, 0)) == XOR
6504 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6505 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6506 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6507 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6508 && HWI_COMPUTABLE_MODE_P (mode
)
6509 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6510 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6511 && ((nonzero_bits (f
, GET_MODE (f
))
6512 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6515 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6516 extend_op
= ZERO_EXTEND
;
6517 m
= GET_MODE (XEXP (t
, 0));
6519 else if (GET_CODE (t
) == ZERO_EXTEND
6520 && (GET_CODE (XEXP (t
, 0)) == PLUS
6521 || GET_CODE (XEXP (t
, 0)) == IOR
6522 || GET_CODE (XEXP (t
, 0)) == XOR
)
6523 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6524 && HWI_COMPUTABLE_MODE_P (mode
)
6525 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6526 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6527 && ((nonzero_bits (f
, GET_MODE (f
))
6528 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6531 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6532 extend_op
= ZERO_EXTEND
;
6533 m
= GET_MODE (XEXP (t
, 0));
6538 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6539 cond_op0
, cond_op1
),
6540 pc_rtx
, pc_rtx
, 0, 0, 0);
6541 temp
= simplify_gen_binary (MULT
, m
, temp
,
6542 simplify_gen_binary (MULT
, m
, c1
,
6544 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6545 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6547 if (extend_op
!= UNKNOWN
)
6548 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6554 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6555 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6556 negation of a single bit, we can convert this operation to a shift. We
6557 can actually do this more generally, but it doesn't seem worth it. */
6559 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6560 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6561 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6562 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6563 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6564 == GET_MODE_PRECISION (mode
))
6565 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6567 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6568 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6570 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6571 non-zero bit in A is C1. */
6572 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6573 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6574 && INTEGRAL_MODE_P (GET_MODE (XEXP (cond
, 0)))
6575 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6576 == nonzero_bits (XEXP (cond
, 0), GET_MODE (XEXP (cond
, 0)))
6577 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6579 rtx val
= XEXP (cond
, 0);
6580 enum machine_mode val_mode
= GET_MODE (val
);
6581 if (val_mode
== mode
)
6583 else if (GET_MODE_PRECISION (val_mode
) < GET_MODE_PRECISION (mode
))
6584 return simplify_gen_unary (ZERO_EXTEND
, mode
, val
, val_mode
);
6590 /* Simplify X, a SET expression. Return the new expression. */
6593 simplify_set (rtx x
)
6595 rtx src
= SET_SRC (x
);
6596 rtx dest
= SET_DEST (x
);
6598 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6599 rtx_insn
*other_insn
;
6602 /* (set (pc) (return)) gets written as (return). */
6603 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6606 /* Now that we know for sure which bits of SRC we are using, see if we can
6607 simplify the expression for the object knowing that we only need the
6610 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6612 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6613 SUBST (SET_SRC (x
), src
);
6616 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6617 the comparison result and try to simplify it unless we already have used
6618 undobuf.other_insn. */
6619 if ((GET_MODE_CLASS (mode
) == MODE_CC
6620 || GET_CODE (src
) == COMPARE
6622 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6623 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6624 && COMPARISON_P (*cc_use
)
6625 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6627 enum rtx_code old_code
= GET_CODE (*cc_use
);
6628 enum rtx_code new_code
;
6630 int other_changed
= 0;
6631 rtx inner_compare
= NULL_RTX
;
6632 machine_mode compare_mode
= GET_MODE (dest
);
6634 if (GET_CODE (src
) == COMPARE
)
6636 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6637 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6639 inner_compare
= op0
;
6640 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6644 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6646 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6649 new_code
= old_code
;
6650 else if (!CONSTANT_P (tmp
))
6652 new_code
= GET_CODE (tmp
);
6653 op0
= XEXP (tmp
, 0);
6654 op1
= XEXP (tmp
, 1);
6658 rtx pat
= PATTERN (other_insn
);
6659 undobuf
.other_insn
= other_insn
;
6660 SUBST (*cc_use
, tmp
);
6662 /* Attempt to simplify CC user. */
6663 if (GET_CODE (pat
) == SET
)
6665 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6666 if (new_rtx
!= NULL_RTX
)
6667 SUBST (SET_SRC (pat
), new_rtx
);
6670 /* Convert X into a no-op move. */
6671 SUBST (SET_DEST (x
), pc_rtx
);
6672 SUBST (SET_SRC (x
), pc_rtx
);
6676 /* Simplify our comparison, if possible. */
6677 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6679 #ifdef SELECT_CC_MODE
6680 /* If this machine has CC modes other than CCmode, check to see if we
6681 need to use a different CC mode here. */
6682 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6683 compare_mode
= GET_MODE (op0
);
6684 else if (inner_compare
6685 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6686 && new_code
== old_code
6687 && op0
== XEXP (inner_compare
, 0)
6688 && op1
== XEXP (inner_compare
, 1))
6689 compare_mode
= GET_MODE (inner_compare
);
6691 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6693 /* If the mode changed, we have to change SET_DEST, the mode in the
6694 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6695 a hard register, just build new versions with the proper mode. If it
6696 is a pseudo, we lose unless it is only time we set the pseudo, in
6697 which case we can safely change its mode. */
6698 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6700 if (can_change_dest_mode (dest
, 0, compare_mode
))
6702 unsigned int regno
= REGNO (dest
);
6705 if (regno
< FIRST_PSEUDO_REGISTER
)
6706 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6709 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6710 new_dest
= regno_reg_rtx
[regno
];
6713 SUBST (SET_DEST (x
), new_dest
);
6714 SUBST (XEXP (*cc_use
, 0), new_dest
);
6720 #endif /* SELECT_CC_MODE */
6722 /* If the code changed, we have to build a new comparison in
6723 undobuf.other_insn. */
6724 if (new_code
!= old_code
)
6726 int other_changed_previously
= other_changed
;
6727 unsigned HOST_WIDE_INT mask
;
6728 rtx old_cc_use
= *cc_use
;
6730 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6734 /* If the only change we made was to change an EQ into an NE or
6735 vice versa, OP0 has only one bit that might be nonzero, and OP1
6736 is zero, check if changing the user of the condition code will
6737 produce a valid insn. If it won't, we can keep the original code
6738 in that insn by surrounding our operation with an XOR. */
6740 if (((old_code
== NE
&& new_code
== EQ
)
6741 || (old_code
== EQ
&& new_code
== NE
))
6742 && ! other_changed_previously
&& op1
== const0_rtx
6743 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6744 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6746 rtx pat
= PATTERN (other_insn
), note
= 0;
6748 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6749 && ! check_asm_operands (pat
)))
6751 *cc_use
= old_cc_use
;
6754 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6762 undobuf
.other_insn
= other_insn
;
6764 /* Don't generate a compare of a CC with 0, just use that CC. */
6765 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6767 SUBST (SET_SRC (x
), op0
);
6770 /* Otherwise, if we didn't previously have the same COMPARE we
6771 want, create it from scratch. */
6772 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6773 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6775 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6781 /* Get SET_SRC in a form where we have placed back any
6782 compound expressions. Then do the checks below. */
6783 src
= make_compound_operation (src
, SET
);
6784 SUBST (SET_SRC (x
), src
);
6787 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6788 and X being a REG or (subreg (reg)), we may be able to convert this to
6789 (set (subreg:m2 x) (op)).
6791 We can always do this if M1 is narrower than M2 because that means that
6792 we only care about the low bits of the result.
6794 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6795 perform a narrower operation than requested since the high-order bits will
6796 be undefined. On machine where it is defined, this transformation is safe
6797 as long as M1 and M2 have the same number of words. */
6799 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6800 && !OBJECT_P (SUBREG_REG (src
))
6801 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6803 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6804 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6805 && (WORD_REGISTER_OPERATIONS
6806 || (GET_MODE_SIZE (GET_MODE (src
))
6807 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6808 #ifdef CANNOT_CHANGE_MODE_CLASS
6809 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6810 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6811 GET_MODE (SUBREG_REG (src
)),
6815 || (GET_CODE (dest
) == SUBREG
6816 && REG_P (SUBREG_REG (dest
)))))
6818 SUBST (SET_DEST (x
),
6819 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6821 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6823 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6826 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6829 && GET_CODE (src
) == SUBREG
6830 && subreg_lowpart_p (src
)
6831 && (GET_MODE_PRECISION (GET_MODE (src
))
6832 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6834 rtx inner
= SUBREG_REG (src
);
6835 machine_mode inner_mode
= GET_MODE (inner
);
6837 /* Here we make sure that we don't have a sign bit on. */
6838 if (val_signbit_known_clear_p (GET_MODE (src
),
6839 nonzero_bits (inner
, inner_mode
)))
6841 SUBST (SET_SRC (x
), inner
);
6846 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6847 would require a paradoxical subreg. Replace the subreg with a
6848 zero_extend to avoid the reload that would otherwise be required. */
6850 enum rtx_code extend_op
;
6851 if (paradoxical_subreg_p (src
)
6852 && MEM_P (SUBREG_REG (src
))
6853 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6856 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6861 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6862 are comparing an item known to be 0 or -1 against 0, use a logical
6863 operation instead. Check for one of the arms being an IOR of the other
6864 arm with some value. We compute three terms to be IOR'ed together. In
6865 practice, at most two will be nonzero. Then we do the IOR's. */
6867 if (GET_CODE (dest
) != PC
6868 && GET_CODE (src
) == IF_THEN_ELSE
6869 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6870 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6871 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6872 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6873 && (!HAVE_conditional_move
6874 || ! can_conditionally_move_p (GET_MODE (src
)))
6875 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6876 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6877 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6878 && ! side_effects_p (src
))
6880 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6881 ? XEXP (src
, 1) : XEXP (src
, 2));
6882 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6883 ? XEXP (src
, 2) : XEXP (src
, 1));
6884 rtx term1
= const0_rtx
, term2
, term3
;
6886 if (GET_CODE (true_rtx
) == IOR
6887 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6888 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6889 else if (GET_CODE (true_rtx
) == IOR
6890 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6891 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6892 else if (GET_CODE (false_rtx
) == IOR
6893 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6894 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6895 else if (GET_CODE (false_rtx
) == IOR
6896 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6897 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6899 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6900 XEXP (XEXP (src
, 0), 0), true_rtx
);
6901 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6902 simplify_gen_unary (NOT
, GET_MODE (src
),
6903 XEXP (XEXP (src
, 0), 0),
6908 simplify_gen_binary (IOR
, GET_MODE (src
),
6909 simplify_gen_binary (IOR
, GET_MODE (src
),
6916 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6917 whole thing fail. */
6918 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6920 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6923 /* Convert this into a field assignment operation, if possible. */
6924 return make_field_assignment (x
);
6927 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6931 simplify_logical (rtx x
)
6933 machine_mode mode
= GET_MODE (x
);
6934 rtx op0
= XEXP (x
, 0);
6935 rtx op1
= XEXP (x
, 1);
6937 switch (GET_CODE (x
))
6940 /* We can call simplify_and_const_int only if we don't lose
6941 any (sign) bits when converting INTVAL (op1) to
6942 "unsigned HOST_WIDE_INT". */
6943 if (CONST_INT_P (op1
)
6944 && (HWI_COMPUTABLE_MODE_P (mode
)
6945 || INTVAL (op1
) > 0))
6947 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6948 if (GET_CODE (x
) != AND
)
6955 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6956 apply the distributive law and then the inverse distributive
6957 law to see if things simplify. */
6958 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6960 rtx result
= distribute_and_simplify_rtx (x
, 0);
6964 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6966 rtx result
= distribute_and_simplify_rtx (x
, 1);
6973 /* If we have (ior (and A B) C), apply the distributive law and then
6974 the inverse distributive law to see if things simplify. */
6976 if (GET_CODE (op0
) == AND
)
6978 rtx result
= distribute_and_simplify_rtx (x
, 0);
6983 if (GET_CODE (op1
) == AND
)
6985 rtx result
= distribute_and_simplify_rtx (x
, 1);
6998 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6999 operations" because they can be replaced with two more basic operations.
7000 ZERO_EXTEND is also considered "compound" because it can be replaced with
7001 an AND operation, which is simpler, though only one operation.
7003 The function expand_compound_operation is called with an rtx expression
7004 and will convert it to the appropriate shifts and AND operations,
7005 simplifying at each stage.
7007 The function make_compound_operation is called to convert an expression
7008 consisting of shifts and ANDs into the equivalent compound expression.
7009 It is the inverse of this function, loosely speaking. */
7012 expand_compound_operation (rtx x
)
7014 unsigned HOST_WIDE_INT pos
= 0, len
;
7016 unsigned int modewidth
;
7019 switch (GET_CODE (x
))
7025 /* We can't necessarily use a const_int for a multiword mode;
7026 it depends on implicitly extending the value.
7027 Since we don't know the right way to extend it,
7028 we can't tell whether the implicit way is right.
7030 Even for a mode that is no wider than a const_int,
7031 we can't win, because we need to sign extend one of its bits through
7032 the rest of it, and we don't know which bit. */
7033 if (CONST_INT_P (XEXP (x
, 0)))
7036 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7037 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7038 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7039 reloaded. If not for that, MEM's would very rarely be safe.
7041 Reject MODEs bigger than a word, because we might not be able
7042 to reference a two-register group starting with an arbitrary register
7043 (and currently gen_lowpart might crash for a SUBREG). */
7045 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7048 /* Reject MODEs that aren't scalar integers because turning vector
7049 or complex modes into shifts causes problems. */
7051 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7054 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7055 /* If the inner object has VOIDmode (the only way this can happen
7056 is if it is an ASM_OPERANDS), we can't do anything since we don't
7057 know how much masking to do. */
7069 /* If the operand is a CLOBBER, just return it. */
7070 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7073 if (!CONST_INT_P (XEXP (x
, 1))
7074 || !CONST_INT_P (XEXP (x
, 2))
7075 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7078 /* Reject MODEs that aren't scalar integers because turning vector
7079 or complex modes into shifts causes problems. */
7081 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7084 len
= INTVAL (XEXP (x
, 1));
7085 pos
= INTVAL (XEXP (x
, 2));
7087 /* This should stay within the object being extracted, fail otherwise. */
7088 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7091 if (BITS_BIG_ENDIAN
)
7092 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7099 /* Convert sign extension to zero extension, if we know that the high
7100 bit is not set, as this is easier to optimize. It will be converted
7101 back to cheaper alternative in make_extraction. */
7102 if (GET_CODE (x
) == SIGN_EXTEND
7103 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7104 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7105 & ~(((unsigned HOST_WIDE_INT
)
7106 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7110 machine_mode mode
= GET_MODE (x
);
7111 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7112 rtx temp2
= expand_compound_operation (temp
);
7114 /* Make sure this is a profitable operation. */
7115 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7116 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7118 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7119 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7125 /* We can optimize some special cases of ZERO_EXTEND. */
7126 if (GET_CODE (x
) == ZERO_EXTEND
)
7128 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7129 know that the last value didn't have any inappropriate bits
7131 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7132 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7133 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7134 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7135 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7136 return XEXP (XEXP (x
, 0), 0);
7138 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7139 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7140 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7141 && subreg_lowpart_p (XEXP (x
, 0))
7142 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7143 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7144 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7145 return SUBREG_REG (XEXP (x
, 0));
7147 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7148 is a comparison and STORE_FLAG_VALUE permits. This is like
7149 the first case, but it works even when GET_MODE (x) is larger
7150 than HOST_WIDE_INT. */
7151 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7152 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7153 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7154 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7155 <= HOST_BITS_PER_WIDE_INT
)
7156 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7157 return XEXP (XEXP (x
, 0), 0);
7159 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7160 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7161 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7162 && subreg_lowpart_p (XEXP (x
, 0))
7163 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7164 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7165 <= HOST_BITS_PER_WIDE_INT
)
7166 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7167 return SUBREG_REG (XEXP (x
, 0));
7171 /* If we reach here, we want to return a pair of shifts. The inner
7172 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7173 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7174 logical depending on the value of UNSIGNEDP.
7176 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7177 converted into an AND of a shift.
7179 We must check for the case where the left shift would have a negative
7180 count. This can happen in a case like (x >> 31) & 255 on machines
7181 that can't shift by a constant. On those machines, we would first
7182 combine the shift with the AND to produce a variable-position
7183 extraction. Then the constant of 31 would be substituted in
7184 to produce such a position. */
7186 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7187 if (modewidth
>= pos
+ len
)
7189 machine_mode mode
= GET_MODE (x
);
7190 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7191 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7193 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7194 tem
, modewidth
- pos
- len
);
7195 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7196 mode
, tem
, modewidth
- len
);
7198 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7199 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7200 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7203 (HOST_WIDE_INT_1U
<< len
) - 1);
7205 /* Any other cases we can't handle. */
7208 /* If we couldn't do this for some reason, return the original
7210 if (GET_CODE (tem
) == CLOBBER
)
7216 /* X is a SET which contains an assignment of one object into
7217 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7218 or certain SUBREGS). If possible, convert it into a series of
7221 We half-heartedly support variable positions, but do not at all
7222 support variable lengths. */
7225 expand_field_assignment (const_rtx x
)
7228 rtx pos
; /* Always counts from low bit. */
7230 rtx mask
, cleared
, masked
;
7231 machine_mode compute_mode
;
7233 /* Loop until we find something we can't simplify. */
7236 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7237 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7239 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7240 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7241 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7243 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7244 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7246 inner
= XEXP (SET_DEST (x
), 0);
7247 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7248 pos
= XEXP (SET_DEST (x
), 2);
7250 /* A constant position should stay within the width of INNER. */
7251 if (CONST_INT_P (pos
)
7252 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7255 if (BITS_BIG_ENDIAN
)
7257 if (CONST_INT_P (pos
))
7258 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7260 else if (GET_CODE (pos
) == MINUS
7261 && CONST_INT_P (XEXP (pos
, 1))
7262 && (INTVAL (XEXP (pos
, 1))
7263 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7264 /* If position is ADJUST - X, new position is X. */
7265 pos
= XEXP (pos
, 0);
7268 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7269 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7270 gen_int_mode (prec
- len
,
7277 /* A SUBREG between two modes that occupy the same numbers of words
7278 can be done by moving the SUBREG to the source. */
7279 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7280 /* We need SUBREGs to compute nonzero_bits properly. */
7281 && nonzero_sign_valid
7282 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7283 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7284 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7285 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7287 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7289 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7296 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7297 inner
= SUBREG_REG (inner
);
7299 compute_mode
= GET_MODE (inner
);
7301 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7302 if (! SCALAR_INT_MODE_P (compute_mode
))
7306 /* Don't do anything for vector or complex integral types. */
7307 if (! FLOAT_MODE_P (compute_mode
))
7310 /* Try to find an integral mode to pun with. */
7311 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7312 if (imode
== BLKmode
)
7315 compute_mode
= imode
;
7316 inner
= gen_lowpart (imode
, inner
);
7319 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7320 if (len
>= HOST_BITS_PER_WIDE_INT
)
7323 /* Don't try to compute in too wide unsupported modes. */
7324 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7327 /* Now compute the equivalent expression. Make a copy of INNER
7328 for the SET_DEST in case it is a MEM into which we will substitute;
7329 we don't want shared RTL in that case. */
7330 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7332 cleared
= simplify_gen_binary (AND
, compute_mode
,
7333 simplify_gen_unary (NOT
, compute_mode
,
7334 simplify_gen_binary (ASHIFT
,
7339 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7340 simplify_gen_binary (
7342 gen_lowpart (compute_mode
, SET_SRC (x
)),
7346 x
= gen_rtx_SET (copy_rtx (inner
),
7347 simplify_gen_binary (IOR
, compute_mode
,
7354 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7355 it is an RTX that represents the (variable) starting position; otherwise,
7356 POS is the (constant) starting bit position. Both are counted from the LSB.
7358 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7360 IN_DEST is nonzero if this is a reference in the destination of a SET.
7361 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7362 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7365 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7366 ZERO_EXTRACT should be built even for bits starting at bit 0.
7368 MODE is the desired mode of the result (if IN_DEST == 0).
7370 The result is an RTX for the extraction or NULL_RTX if the target
7374 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7375 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7376 int in_dest
, int in_compare
)
7378 /* This mode describes the size of the storage area
7379 to fetch the overall value from. Within that, we
7380 ignore the POS lowest bits, etc. */
7381 machine_mode is_mode
= GET_MODE (inner
);
7382 machine_mode inner_mode
;
7383 machine_mode wanted_inner_mode
;
7384 machine_mode wanted_inner_reg_mode
= word_mode
;
7385 machine_mode pos_mode
= word_mode
;
7386 machine_mode extraction_mode
= word_mode
;
7387 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7389 rtx orig_pos_rtx
= pos_rtx
;
7390 HOST_WIDE_INT orig_pos
;
7392 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7393 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7395 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7397 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7398 consider just the QI as the memory to extract from.
7399 The subreg adds or removes high bits; its mode is
7400 irrelevant to the meaning of this extraction,
7401 since POS and LEN count from the lsb. */
7402 if (MEM_P (SUBREG_REG (inner
)))
7403 is_mode
= GET_MODE (SUBREG_REG (inner
));
7404 inner
= SUBREG_REG (inner
);
7406 else if (GET_CODE (inner
) == ASHIFT
7407 && CONST_INT_P (XEXP (inner
, 1))
7408 && pos_rtx
== 0 && pos
== 0
7409 && len
> UINTVAL (XEXP (inner
, 1)))
7411 /* We're extracting the least significant bits of an rtx
7412 (ashift X (const_int C)), where LEN > C. Extract the
7413 least significant (LEN - C) bits of X, giving an rtx
7414 whose mode is MODE, then shift it left C times. */
7415 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7416 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7417 unsignedp
, in_dest
, in_compare
);
7419 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7421 else if (GET_CODE (inner
) == TRUNCATE
)
7422 inner
= XEXP (inner
, 0);
7424 inner_mode
= GET_MODE (inner
);
7426 /* See if this can be done without an extraction. We never can if the
7427 width of the field is not the same as that of some integer mode. For
7428 registers, we can only avoid the extraction if the position is at the
7429 low-order bit and this is either not in the destination or we have the
7430 appropriate STRICT_LOW_PART operation available.
7432 For MEM, we can avoid an extract if the field starts on an appropriate
7433 boundary and we can change the mode of the memory reference. */
7435 if (tmode
!= BLKmode
7436 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7438 && (pos
== 0 || REG_P (inner
))
7439 && (inner_mode
== tmode
7441 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7442 || reg_truncated_to_mode (tmode
, inner
))
7445 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7446 || (MEM_P (inner
) && pos_rtx
== 0
7448 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7449 : BITS_PER_UNIT
)) == 0
7450 /* We can't do this if we are widening INNER_MODE (it
7451 may not be aligned, for one thing). */
7452 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7453 && (inner_mode
== tmode
7454 || (! mode_dependent_address_p (XEXP (inner
, 0),
7455 MEM_ADDR_SPACE (inner
))
7456 && ! MEM_VOLATILE_P (inner
))))))
7458 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7459 field. If the original and current mode are the same, we need not
7460 adjust the offset. Otherwise, we do if bytes big endian.
7462 If INNER is not a MEM, get a piece consisting of just the field
7463 of interest (in this case POS % BITS_PER_WORD must be 0). */
7467 HOST_WIDE_INT offset
;
7469 /* POS counts from lsb, but make OFFSET count in memory order. */
7470 if (BYTES_BIG_ENDIAN
)
7471 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7473 offset
= pos
/ BITS_PER_UNIT
;
7475 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7477 else if (REG_P (inner
))
7479 if (tmode
!= inner_mode
)
7481 /* We can't call gen_lowpart in a DEST since we
7482 always want a SUBREG (see below) and it would sometimes
7483 return a new hard register. */
7486 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7488 if (WORDS_BIG_ENDIAN
7489 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7490 final_word
= ((GET_MODE_SIZE (inner_mode
)
7491 - GET_MODE_SIZE (tmode
))
7492 / UNITS_PER_WORD
) - final_word
;
7494 final_word
*= UNITS_PER_WORD
;
7495 if (BYTES_BIG_ENDIAN
&&
7496 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7497 final_word
+= (GET_MODE_SIZE (inner_mode
)
7498 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7500 /* Avoid creating invalid subregs, for example when
7501 simplifying (x>>32)&255. */
7502 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7505 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7508 new_rtx
= gen_lowpart (tmode
, inner
);
7514 new_rtx
= force_to_mode (inner
, tmode
,
7515 len
>= HOST_BITS_PER_WIDE_INT
7517 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7519 /* If this extraction is going into the destination of a SET,
7520 make a STRICT_LOW_PART unless we made a MEM. */
7523 return (MEM_P (new_rtx
) ? new_rtx
7524 : (GET_CODE (new_rtx
) != SUBREG
7525 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7526 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7531 if (CONST_SCALAR_INT_P (new_rtx
))
7532 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7533 mode
, new_rtx
, tmode
);
7535 /* If we know that no extraneous bits are set, and that the high
7536 bit is not set, convert the extraction to the cheaper of
7537 sign and zero extension, that are equivalent in these cases. */
7538 if (flag_expensive_optimizations
7539 && (HWI_COMPUTABLE_MODE_P (tmode
)
7540 && ((nonzero_bits (new_rtx
, tmode
)
7541 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7544 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7545 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7547 /* Prefer ZERO_EXTENSION, since it gives more information to
7549 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7550 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7555 /* Otherwise, sign- or zero-extend unless we already are in the
7558 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7562 /* Unless this is a COMPARE or we have a funny memory reference,
7563 don't do anything with zero-extending field extracts starting at
7564 the low-order bit since they are simple AND operations. */
7565 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7566 && ! in_compare
&& unsignedp
)
7569 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7570 if the position is not a constant and the length is not 1. In all
7571 other cases, we would only be going outside our object in cases when
7572 an original shift would have been undefined. */
7574 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7575 || (pos_rtx
!= 0 && len
!= 1)))
7578 enum extraction_pattern pattern
= (in_dest
? EP_insv
7579 : unsignedp
? EP_extzv
: EP_extv
);
7581 /* If INNER is not from memory, we want it to have the mode of a register
7582 extraction pattern's structure operand, or word_mode if there is no
7583 such pattern. The same applies to extraction_mode and pos_mode
7584 and their respective operands.
7586 For memory, assume that the desired extraction_mode and pos_mode
7587 are the same as for a register operation, since at present we don't
7588 have named patterns for aligned memory structures. */
7589 struct extraction_insn insn
;
7590 if (get_best_reg_extraction_insn (&insn
, pattern
,
7591 GET_MODE_BITSIZE (inner_mode
), mode
))
7593 wanted_inner_reg_mode
= insn
.struct_mode
;
7594 pos_mode
= insn
.pos_mode
;
7595 extraction_mode
= insn
.field_mode
;
7598 /* Never narrow an object, since that might not be safe. */
7600 if (mode
!= VOIDmode
7601 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7602 extraction_mode
= mode
;
7605 wanted_inner_mode
= wanted_inner_reg_mode
;
7608 /* Be careful not to go beyond the extracted object and maintain the
7609 natural alignment of the memory. */
7610 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7611 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7612 > GET_MODE_BITSIZE (wanted_inner_mode
))
7614 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7615 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7621 if (BITS_BIG_ENDIAN
)
7623 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7624 BITS_BIG_ENDIAN style. If position is constant, compute new
7625 position. Otherwise, build subtraction.
7626 Note that POS is relative to the mode of the original argument.
7627 If it's a MEM we need to recompute POS relative to that.
7628 However, if we're extracting from (or inserting into) a register,
7629 we want to recompute POS relative to wanted_inner_mode. */
7630 int width
= (MEM_P (inner
)
7631 ? GET_MODE_BITSIZE (is_mode
)
7632 : GET_MODE_BITSIZE (wanted_inner_mode
));
7635 pos
= width
- len
- pos
;
7638 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7639 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7641 /* POS may be less than 0 now, but we check for that below.
7642 Note that it can only be less than 0 if !MEM_P (inner). */
7645 /* If INNER has a wider mode, and this is a constant extraction, try to
7646 make it smaller and adjust the byte to point to the byte containing
7648 if (wanted_inner_mode
!= VOIDmode
7649 && inner_mode
!= wanted_inner_mode
7651 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7653 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7654 && ! MEM_VOLATILE_P (inner
))
7658 /* The computations below will be correct if the machine is big
7659 endian in both bits and bytes or little endian in bits and bytes.
7660 If it is mixed, we must adjust. */
7662 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7663 adjust OFFSET to compensate. */
7664 if (BYTES_BIG_ENDIAN
7665 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7666 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7668 /* We can now move to the desired byte. */
7669 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7670 * GET_MODE_SIZE (wanted_inner_mode
);
7671 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7673 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7674 && is_mode
!= wanted_inner_mode
)
7675 offset
= (GET_MODE_SIZE (is_mode
)
7676 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7678 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7681 /* If INNER is not memory, get it into the proper mode. If we are changing
7682 its mode, POS must be a constant and smaller than the size of the new
7684 else if (!MEM_P (inner
))
7686 /* On the LHS, don't create paradoxical subregs implicitely truncating
7687 the register unless TRULY_NOOP_TRUNCATION. */
7689 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7693 if (GET_MODE (inner
) != wanted_inner_mode
7695 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7701 inner
= force_to_mode (inner
, wanted_inner_mode
,
7703 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7705 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7710 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7711 have to zero extend. Otherwise, we can just use a SUBREG. */
7713 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7715 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7716 GET_MODE (pos_rtx
));
7718 /* If we know that no extraneous bits are set, and that the high
7719 bit is not set, convert extraction to cheaper one - either
7720 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7722 if (flag_expensive_optimizations
7723 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7724 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7725 & ~(((unsigned HOST_WIDE_INT
)
7726 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7730 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7731 GET_MODE (pos_rtx
));
7733 /* Prefer ZERO_EXTENSION, since it gives more information to
7735 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7736 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7742 /* Make POS_RTX unless we already have it and it is correct. If we don't
7743 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7745 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7746 pos_rtx
= orig_pos_rtx
;
7748 else if (pos_rtx
== 0)
7749 pos_rtx
= GEN_INT (pos
);
7751 /* Make the required operation. See if we can use existing rtx. */
7752 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7753 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7755 new_rtx
= gen_lowpart (mode
, new_rtx
);
7760 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7761 with any other operations in X. Return X without that shift if so. */
7764 extract_left_shift (rtx x
, int count
)
7766 enum rtx_code code
= GET_CODE (x
);
7767 machine_mode mode
= GET_MODE (x
);
7773 /* This is the shift itself. If it is wide enough, we will return
7774 either the value being shifted if the shift count is equal to
7775 COUNT or a shift for the difference. */
7776 if (CONST_INT_P (XEXP (x
, 1))
7777 && INTVAL (XEXP (x
, 1)) >= count
)
7778 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7779 INTVAL (XEXP (x
, 1)) - count
);
7783 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7784 return simplify_gen_unary (code
, mode
, tem
, mode
);
7788 case PLUS
: case IOR
: case XOR
: case AND
:
7789 /* If we can safely shift this constant and we find the inner shift,
7790 make a new operation. */
7791 if (CONST_INT_P (XEXP (x
, 1))
7792 && (UINTVAL (XEXP (x
, 1))
7793 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7794 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7796 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7797 return simplify_gen_binary (code
, mode
, tem
,
7798 gen_int_mode (val
, mode
));
7809 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7810 level of the expression and MODE is its mode. IN_CODE is as for
7811 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7812 that should be used when recursing on operands of *X_PTR.
7814 There are two possible actions:
7816 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7817 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7819 - Return a new rtx, which the caller returns directly. */
7822 make_compound_operation_int (machine_mode mode
, rtx
*x_ptr
,
7823 enum rtx_code in_code
,
7824 enum rtx_code
*next_code_ptr
)
7827 enum rtx_code next_code
= *next_code_ptr
;
7828 enum rtx_code code
= GET_CODE (x
);
7829 int mode_width
= GET_MODE_PRECISION (mode
);
7834 bool equality_comparison
= false;
7838 equality_comparison
= true;
7842 /* Process depending on the code of this operation. If NEW is set
7843 nonzero, it will be returned. */
7848 /* Convert shifts by constants into multiplications if inside
7850 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7851 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7852 && INTVAL (XEXP (x
, 1)) >= 0)
7854 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7855 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7857 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7858 if (GET_CODE (new_rtx
) == NEG
)
7860 new_rtx
= XEXP (new_rtx
, 0);
7863 multval
= trunc_int_for_mode (multval
, mode
);
7864 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7871 lhs
= make_compound_operation (lhs
, next_code
);
7872 rhs
= make_compound_operation (rhs
, next_code
);
7873 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
7875 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7877 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7879 else if (GET_CODE (lhs
) == MULT
7880 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7882 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7883 simplify_gen_unary (NEG
, mode
,
7886 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7890 SUBST (XEXP (x
, 0), lhs
);
7891 SUBST (XEXP (x
, 1), rhs
);
7893 maybe_swap_commutative_operands (x
);
7899 lhs
= make_compound_operation (lhs
, next_code
);
7900 rhs
= make_compound_operation (rhs
, next_code
);
7901 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
7903 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7905 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7907 else if (GET_CODE (rhs
) == MULT
7908 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7910 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7911 simplify_gen_unary (NEG
, mode
,
7914 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7918 SUBST (XEXP (x
, 0), lhs
);
7919 SUBST (XEXP (x
, 1), rhs
);
7924 /* If the second operand is not a constant, we can't do anything
7926 if (!CONST_INT_P (XEXP (x
, 1)))
7929 /* If the constant is a power of two minus one and the first operand
7930 is a logical right shift, make an extraction. */
7931 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7932 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7934 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7935 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7936 0, in_code
== COMPARE
);
7939 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7940 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7941 && subreg_lowpart_p (XEXP (x
, 0))
7942 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7943 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7945 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
7946 machine_mode inner_mode
= GET_MODE (inner_x0
);
7947 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
7948 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
7950 i
, 1, 0, in_code
== COMPARE
);
7954 /* If we narrowed the mode when dropping the subreg, then
7955 we must zero-extend to keep the semantics of the AND. */
7956 if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
7958 else if (SCALAR_INT_MODE_P (inner_mode
))
7959 new_rtx
= simplify_gen_unary (ZERO_EXTEND
, mode
,
7960 new_rtx
, inner_mode
);
7965 /* If that didn't give anything, see if the AND simplifies on
7967 if (!new_rtx
&& i
>= 0)
7969 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7970 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
7971 0, in_code
== COMPARE
);
7974 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7975 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7976 || GET_CODE (XEXP (x
, 0)) == IOR
)
7977 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7978 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7979 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7981 /* Apply the distributive law, and then try to make extractions. */
7982 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7983 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7985 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7987 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7990 /* If we are have (and (rotate X C) M) and C is larger than the number
7991 of bits in M, this is an extraction. */
7993 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7994 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7995 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7996 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7998 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7999 new_rtx
= make_extraction (mode
, new_rtx
,
8000 (GET_MODE_PRECISION (mode
)
8001 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8002 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8005 /* On machines without logical shifts, if the operand of the AND is
8006 a logical shift and our mask turns off all the propagated sign
8007 bits, we can replace the logical shift with an arithmetic shift. */
8008 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8009 && !have_insn_for (LSHIFTRT
, mode
)
8010 && have_insn_for (ASHIFTRT
, mode
)
8011 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8012 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8013 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8014 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8016 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8018 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8019 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8021 gen_rtx_ASHIFTRT (mode
,
8022 make_compound_operation
8023 (XEXP (XEXP (x
, 0), 0), next_code
),
8024 XEXP (XEXP (x
, 0), 1)));
8027 /* If the constant is one less than a power of two, this might be
8028 representable by an extraction even if no shift is present.
8029 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8030 we are in a COMPARE. */
8031 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8032 new_rtx
= make_extraction (mode
,
8033 make_compound_operation (XEXP (x
, 0),
8035 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8037 /* If we are in a comparison and this is an AND with a power of two,
8038 convert this into the appropriate bit extract. */
8039 else if (in_code
== COMPARE
8040 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8041 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8042 new_rtx
= make_extraction (mode
,
8043 make_compound_operation (XEXP (x
, 0),
8045 i
, NULL_RTX
, 1, 1, 0, 1);
8047 /* If the one operand is a paradoxical subreg of a register or memory and
8048 the constant (limited to the smaller mode) has only zero bits where
8049 the sub expression has known zero bits, this can be expressed as
8051 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8055 sub
= XEXP (XEXP (x
, 0), 0);
8056 machine_mode sub_mode
= GET_MODE (sub
);
8057 if ((REG_P (sub
) || MEM_P (sub
))
8058 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8060 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8061 unsigned HOST_WIDE_INT mask
;
8063 /* original AND constant with all the known zero bits set */
8064 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8065 if ((mask
& mode_mask
) == mode_mask
)
8067 new_rtx
= make_compound_operation (sub
, next_code
);
8068 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8069 GET_MODE_PRECISION (sub_mode
),
8070 1, 0, in_code
== COMPARE
);
8078 /* If the sign bit is known to be zero, replace this with an
8079 arithmetic shift. */
8080 if (have_insn_for (ASHIFTRT
, mode
)
8081 && ! have_insn_for (LSHIFTRT
, mode
)
8082 && mode_width
<= HOST_BITS_PER_WIDE_INT
8083 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8085 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8086 make_compound_operation (XEXP (x
, 0),
8098 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8099 this is a SIGN_EXTRACT. */
8100 if (CONST_INT_P (rhs
)
8101 && GET_CODE (lhs
) == ASHIFT
8102 && CONST_INT_P (XEXP (lhs
, 1))
8103 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8104 && INTVAL (XEXP (lhs
, 1)) >= 0
8105 && INTVAL (rhs
) < mode_width
)
8107 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8108 new_rtx
= make_extraction (mode
, new_rtx
,
8109 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8110 NULL_RTX
, mode_width
- INTVAL (rhs
),
8111 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8115 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8116 If so, try to merge the shifts into a SIGN_EXTEND. We could
8117 also do this for some cases of SIGN_EXTRACT, but it doesn't
8118 seem worth the effort; the case checked for occurs on Alpha. */
8121 && ! (GET_CODE (lhs
) == SUBREG
8122 && (OBJECT_P (SUBREG_REG (lhs
))))
8123 && CONST_INT_P (rhs
)
8124 && INTVAL (rhs
) >= 0
8125 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8126 && INTVAL (rhs
) < mode_width
8127 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8128 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8129 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8130 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8135 /* Call ourselves recursively on the inner expression. If we are
8136 narrowing the object and it has a different RTL code from
8137 what it originally did, do this SUBREG as a force_to_mode. */
8139 rtx inner
= SUBREG_REG (x
), simplified
;
8140 enum rtx_code subreg_code
= in_code
;
8142 /* If the SUBREG is masking of a logical right shift,
8143 make an extraction. */
8144 if (GET_CODE (inner
) == LSHIFTRT
8145 && CONST_INT_P (XEXP (inner
, 1))
8146 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8147 && (UINTVAL (XEXP (inner
, 1))
8148 < GET_MODE_PRECISION (GET_MODE (inner
)))
8149 && subreg_lowpart_p (x
))
8151 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8152 int width
= GET_MODE_PRECISION (GET_MODE (inner
))
8153 - INTVAL (XEXP (inner
, 1));
8154 if (width
> mode_width
)
8156 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8157 width
, 1, 0, in_code
== COMPARE
);
8161 /* If in_code is COMPARE, it isn't always safe to pass it through
8162 to the recursive make_compound_operation call. */
8163 if (subreg_code
== COMPARE
8164 && (!subreg_lowpart_p (x
)
8165 || GET_CODE (inner
) == SUBREG
8166 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8167 is (const_int 0), rather than
8168 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8169 || (GET_CODE (inner
) == AND
8170 && CONST_INT_P (XEXP (inner
, 1))
8171 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8172 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8173 >= GET_MODE_BITSIZE (mode
))))
8176 tem
= make_compound_operation (inner
, subreg_code
);
8179 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8183 if (GET_CODE (tem
) != GET_CODE (inner
)
8184 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8185 && subreg_lowpart_p (x
))
8188 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8190 /* If we have something other than a SUBREG, we might have
8191 done an expansion, so rerun ourselves. */
8192 if (GET_CODE (newer
) != SUBREG
)
8193 newer
= make_compound_operation (newer
, in_code
);
8195 /* force_to_mode can expand compounds. If it just re-expanded the
8196 compound, use gen_lowpart to convert to the desired mode. */
8197 if (rtx_equal_p (newer
, x
)
8198 /* Likewise if it re-expanded the compound only partially.
8199 This happens for SUBREG of ZERO_EXTRACT if they extract
8200 the same number of bits. */
8201 || (GET_CODE (newer
) == SUBREG
8202 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8203 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8204 && GET_CODE (inner
) == AND
8205 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8206 return gen_lowpart (GET_MODE (x
), tem
);
8221 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8222 *next_code_ptr
= next_code
;
8226 /* Look at the expression rooted at X. Look for expressions
8227 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8228 Form these expressions.
8230 Return the new rtx, usually just X.
8232 Also, for machines like the VAX that don't have logical shift insns,
8233 try to convert logical to arithmetic shift operations in cases where
8234 they are equivalent. This undoes the canonicalizations to logical
8235 shifts done elsewhere.
8237 We try, as much as possible, to re-use rtl expressions to save memory.
8239 IN_CODE says what kind of expression we are processing. Normally, it is
8240 SET. In a memory address it is MEM. When processing the arguments of
8241 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8242 precisely it is an equality comparison against zero. */
8245 make_compound_operation (rtx x
, enum rtx_code in_code
)
8247 enum rtx_code code
= GET_CODE (x
);
8250 enum rtx_code next_code
;
8253 /* Select the code to be used in recursive calls. Once we are inside an
8254 address, we stay there. If we have a comparison, set to COMPARE,
8255 but once inside, go back to our default of SET. */
8257 next_code
= (code
== MEM
? MEM
8258 : ((code
== COMPARE
|| COMPARISON_P (x
))
8259 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8260 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8262 if (SCALAR_INT_MODE_P (GET_MODE (x
)))
8264 rtx new_rtx
= make_compound_operation_int (GET_MODE (x
), &x
,
8265 in_code
, &next_code
);
8268 code
= GET_CODE (x
);
8271 /* Now recursively process each operand of this operation. We need to
8272 handle ZERO_EXTEND specially so that we don't lose track of the
8274 if (code
== ZERO_EXTEND
)
8276 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8277 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8278 new_rtx
, GET_MODE (XEXP (x
, 0)));
8281 SUBST (XEXP (x
, 0), new_rtx
);
8285 fmt
= GET_RTX_FORMAT (code
);
8286 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8289 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8290 SUBST (XEXP (x
, i
), new_rtx
);
8292 else if (fmt
[i
] == 'E')
8293 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8295 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8296 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8299 maybe_swap_commutative_operands (x
);
8303 /* Given M see if it is a value that would select a field of bits
8304 within an item, but not the entire word. Return -1 if not.
8305 Otherwise, return the starting position of the field, where 0 is the
8308 *PLEN is set to the length of the field. */
8311 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8313 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8314 int pos
= m
? ctz_hwi (m
) : -1;
8318 /* Now shift off the low-order zero bits and see if we have a
8319 power of two minus 1. */
8320 len
= exact_log2 ((m
>> pos
) + 1);
8329 /* If X refers to a register that equals REG in value, replace these
8330 references with REG. */
8332 canon_reg_for_combine (rtx x
, rtx reg
)
8339 enum rtx_code code
= GET_CODE (x
);
8340 switch (GET_RTX_CLASS (code
))
8343 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8344 if (op0
!= XEXP (x
, 0))
8345 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8350 case RTX_COMM_ARITH
:
8351 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8352 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8353 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8354 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8358 case RTX_COMM_COMPARE
:
8359 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8360 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8361 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8362 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8363 GET_MODE (op0
), op0
, op1
);
8367 case RTX_BITFIELD_OPS
:
8368 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8369 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8370 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8371 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8372 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8373 GET_MODE (op0
), op0
, op1
, op2
);
8379 if (rtx_equal_p (get_last_value (reg
), x
)
8380 || rtx_equal_p (reg
, get_last_value (x
)))
8389 fmt
= GET_RTX_FORMAT (code
);
8391 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8394 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8395 if (op
!= XEXP (x
, i
))
8405 else if (fmt
[i
] == 'E')
8408 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8410 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8411 if (op
!= XVECEXP (x
, i
, j
))
8418 XVECEXP (x
, i
, j
) = op
;
8429 /* Return X converted to MODE. If the value is already truncated to
8430 MODE we can just return a subreg even though in the general case we
8431 would need an explicit truncation. */
8434 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8436 if (!CONST_INT_P (x
)
8437 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8438 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8439 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8441 /* Bit-cast X into an integer mode. */
8442 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8443 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8444 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8448 return gen_lowpart (mode
, x
);
8451 /* See if X can be simplified knowing that we will only refer to it in
8452 MODE and will only refer to those bits that are nonzero in MASK.
8453 If other bits are being computed or if masking operations are done
8454 that select a superset of the bits in MASK, they can sometimes be
8457 Return a possibly simplified expression, but always convert X to
8458 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8460 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8461 are all off in X. This is used when X will be complemented, by either
8462 NOT, NEG, or XOR. */
8465 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8468 enum rtx_code code
= GET_CODE (x
);
8469 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8470 machine_mode op_mode
;
8471 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8474 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8475 code below will do the wrong thing since the mode of such an
8476 expression is VOIDmode.
8478 Also do nothing if X is a CLOBBER; this can happen if X was
8479 the return value from a call to gen_lowpart. */
8480 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8483 /* We want to perform the operation in its present mode unless we know
8484 that the operation is valid in MODE, in which case we do the operation
8486 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8487 && have_insn_for (code
, mode
))
8488 ? mode
: GET_MODE (x
));
8490 /* It is not valid to do a right-shift in a narrower mode
8491 than the one it came in with. */
8492 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8493 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8494 op_mode
= GET_MODE (x
);
8496 /* Truncate MASK to fit OP_MODE. */
8498 mask
&= GET_MODE_MASK (op_mode
);
8500 /* When we have an arithmetic operation, or a shift whose count we
8501 do not know, we need to assume that all bits up to the highest-order
8502 bit in MASK will be needed. This is how we form such a mask. */
8503 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8504 fuller_mask
= HOST_WIDE_INT_M1U
;
8506 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8509 /* Determine what bits of X are guaranteed to be (non)zero. */
8510 nonzero
= nonzero_bits (x
, mode
);
8512 /* If none of the bits in X are needed, return a zero. */
8513 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8516 /* If X is a CONST_INT, return a new one. Do this here since the
8517 test below will fail. */
8518 if (CONST_INT_P (x
))
8520 if (SCALAR_INT_MODE_P (mode
))
8521 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8524 x
= GEN_INT (INTVAL (x
) & mask
);
8525 return gen_lowpart_common (mode
, x
);
8529 /* If X is narrower than MODE and we want all the bits in X's mode, just
8530 get X in the proper mode. */
8531 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8532 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8533 return gen_lowpart (mode
, x
);
8535 /* We can ignore the effect of a SUBREG if it narrows the mode or
8536 if the constant masks to zero all the bits the mode doesn't have. */
8537 if (GET_CODE (x
) == SUBREG
8538 && subreg_lowpart_p (x
)
8539 && ((GET_MODE_SIZE (GET_MODE (x
))
8540 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8542 & GET_MODE_MASK (GET_MODE (x
))
8543 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8544 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8546 /* The arithmetic simplifications here only work for scalar integer modes. */
8547 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8548 return gen_lowpart_or_truncate (mode
, x
);
8553 /* If X is a (clobber (const_int)), return it since we know we are
8554 generating something that won't match. */
8561 x
= expand_compound_operation (x
);
8562 if (GET_CODE (x
) != code
)
8563 return force_to_mode (x
, mode
, mask
, next_select
);
8567 /* Similarly for a truncate. */
8568 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8571 /* If this is an AND with a constant, convert it into an AND
8572 whose constant is the AND of that constant with MASK. If it
8573 remains an AND of MASK, delete it since it is redundant. */
8575 if (CONST_INT_P (XEXP (x
, 1)))
8577 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8578 mask
& INTVAL (XEXP (x
, 1)));
8580 /* If X is still an AND, see if it is an AND with a mask that
8581 is just some low-order bits. If so, and it is MASK, we don't
8584 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8585 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8589 /* If it remains an AND, try making another AND with the bits
8590 in the mode mask that aren't in MASK turned on. If the
8591 constant in the AND is wide enough, this might make a
8592 cheaper constant. */
8594 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8595 && GET_MODE_MASK (GET_MODE (x
)) != mask
8596 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8598 unsigned HOST_WIDE_INT cval
8599 = UINTVAL (XEXP (x
, 1))
8600 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8603 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8604 gen_int_mode (cval
, GET_MODE (x
)));
8605 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8606 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8616 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8617 low-order bits (as in an alignment operation) and FOO is already
8618 aligned to that boundary, mask C1 to that boundary as well.
8619 This may eliminate that PLUS and, later, the AND. */
8622 unsigned int width
= GET_MODE_PRECISION (mode
);
8623 unsigned HOST_WIDE_INT smask
= mask
;
8625 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8626 number, sign extend it. */
8628 if (width
< HOST_BITS_PER_WIDE_INT
8629 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8630 smask
|= HOST_WIDE_INT_M1U
<< width
;
8632 if (CONST_INT_P (XEXP (x
, 1))
8633 && pow2p_hwi (- smask
)
8634 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8635 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8636 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8637 (INTVAL (XEXP (x
, 1)) & smask
)),
8638 mode
, smask
, next_select
);
8644 /* Substituting into the operands of a widening MULT is not likely to
8645 create RTL matching a machine insn. */
8647 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8648 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8649 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8650 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8651 && REG_P (XEXP (XEXP (x
, 0), 0))
8652 && REG_P (XEXP (XEXP (x
, 1), 0)))
8653 return gen_lowpart_or_truncate (mode
, x
);
8655 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8656 most significant bit in MASK since carries from those bits will
8657 affect the bits we are interested in. */
8662 /* If X is (minus C Y) where C's least set bit is larger than any bit
8663 in the mask, then we may replace with (neg Y). */
8664 if (CONST_INT_P (XEXP (x
, 0))
8665 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8667 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8669 return force_to_mode (x
, mode
, mask
, next_select
);
8672 /* Similarly, if C contains every bit in the fuller_mask, then we may
8673 replace with (not Y). */
8674 if (CONST_INT_P (XEXP (x
, 0))
8675 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8677 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8678 XEXP (x
, 1), GET_MODE (x
));
8679 return force_to_mode (x
, mode
, mask
, next_select
);
8687 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8688 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8689 operation which may be a bitfield extraction. Ensure that the
8690 constant we form is not wider than the mode of X. */
8692 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8693 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8694 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8695 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8696 && CONST_INT_P (XEXP (x
, 1))
8697 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8698 + floor_log2 (INTVAL (XEXP (x
, 1))))
8699 < GET_MODE_PRECISION (GET_MODE (x
)))
8700 && (UINTVAL (XEXP (x
, 1))
8701 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8703 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8704 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8706 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8707 XEXP (XEXP (x
, 0), 0), temp
);
8708 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8709 XEXP (XEXP (x
, 0), 1));
8710 return force_to_mode (x
, mode
, mask
, next_select
);
8714 /* For most binary operations, just propagate into the operation and
8715 change the mode if we have an operation of that mode. */
8717 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8718 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8720 /* If we ended up truncating both operands, truncate the result of the
8721 operation instead. */
8722 if (GET_CODE (op0
) == TRUNCATE
8723 && GET_CODE (op1
) == TRUNCATE
)
8725 op0
= XEXP (op0
, 0);
8726 op1
= XEXP (op1
, 0);
8729 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8730 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8732 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8733 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8737 /* For left shifts, do the same, but just for the first operand.
8738 However, we cannot do anything with shifts where we cannot
8739 guarantee that the counts are smaller than the size of the mode
8740 because such a count will have a different meaning in a
8743 if (! (CONST_INT_P (XEXP (x
, 1))
8744 && INTVAL (XEXP (x
, 1)) >= 0
8745 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8746 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8747 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8748 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8751 /* If the shift count is a constant and we can do arithmetic in
8752 the mode of the shift, refine which bits we need. Otherwise, use the
8753 conservative form of the mask. */
8754 if (CONST_INT_P (XEXP (x
, 1))
8755 && INTVAL (XEXP (x
, 1)) >= 0
8756 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8757 && HWI_COMPUTABLE_MODE_P (op_mode
))
8758 mask
>>= INTVAL (XEXP (x
, 1));
8762 op0
= gen_lowpart_or_truncate (op_mode
,
8763 force_to_mode (XEXP (x
, 0), op_mode
,
8764 mask
, next_select
));
8766 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8767 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8771 /* Here we can only do something if the shift count is a constant,
8772 this shift constant is valid for the host, and we can do arithmetic
8775 if (CONST_INT_P (XEXP (x
, 1))
8776 && INTVAL (XEXP (x
, 1)) >= 0
8777 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8778 && HWI_COMPUTABLE_MODE_P (op_mode
))
8780 rtx inner
= XEXP (x
, 0);
8781 unsigned HOST_WIDE_INT inner_mask
;
8783 /* Select the mask of the bits we need for the shift operand. */
8784 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8786 /* We can only change the mode of the shift if we can do arithmetic
8787 in the mode of the shift and INNER_MASK is no wider than the
8788 width of X's mode. */
8789 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8790 op_mode
= GET_MODE (x
);
8792 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8794 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8795 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8798 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8799 shift and AND produces only copies of the sign bit (C2 is one less
8800 than a power of two), we can do this with just a shift. */
8802 if (GET_CODE (x
) == LSHIFTRT
8803 && CONST_INT_P (XEXP (x
, 1))
8804 /* The shift puts one of the sign bit copies in the least significant
8806 && ((INTVAL (XEXP (x
, 1))
8807 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8808 >= GET_MODE_PRECISION (GET_MODE (x
)))
8809 && pow2p_hwi (mask
+ 1)
8810 /* Number of bits left after the shift must be more than the mask
8812 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8813 <= GET_MODE_PRECISION (GET_MODE (x
)))
8814 /* Must be more sign bit copies than the mask needs. */
8815 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8816 >= exact_log2 (mask
+ 1)))
8817 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8818 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8819 - exact_log2 (mask
+ 1)));
8824 /* If we are just looking for the sign bit, we don't need this shift at
8825 all, even if it has a variable count. */
8826 if (val_signbit_p (GET_MODE (x
), mask
))
8827 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8829 /* If this is a shift by a constant, get a mask that contains those bits
8830 that are not copies of the sign bit. We then have two cases: If
8831 MASK only includes those bits, this can be a logical shift, which may
8832 allow simplifications. If MASK is a single-bit field not within
8833 those bits, we are requesting a copy of the sign bit and hence can
8834 shift the sign bit to the appropriate location. */
8836 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8837 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8841 /* If the considered data is wider than HOST_WIDE_INT, we can't
8842 represent a mask for all its bits in a single scalar.
8843 But we only care about the lower bits, so calculate these. */
8845 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8847 nonzero
= HOST_WIDE_INT_M1U
;
8849 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8850 is the number of bits a full-width mask would have set.
8851 We need only shift if these are fewer than nonzero can
8852 hold. If not, we must keep all bits set in nonzero. */
8854 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8855 < HOST_BITS_PER_WIDE_INT
)
8856 nonzero
>>= INTVAL (XEXP (x
, 1))
8857 + HOST_BITS_PER_WIDE_INT
8858 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8862 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8863 nonzero
>>= INTVAL (XEXP (x
, 1));
8866 if ((mask
& ~nonzero
) == 0)
8868 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8869 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8870 if (GET_CODE (x
) != ASHIFTRT
)
8871 return force_to_mode (x
, mode
, mask
, next_select
);
8874 else if ((i
= exact_log2 (mask
)) >= 0)
8876 x
= simplify_shift_const
8877 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8878 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8880 if (GET_CODE (x
) != ASHIFTRT
)
8881 return force_to_mode (x
, mode
, mask
, next_select
);
8885 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8886 even if the shift count isn't a constant. */
8888 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8889 XEXP (x
, 0), XEXP (x
, 1));
8893 /* If this is a zero- or sign-extension operation that just affects bits
8894 we don't care about, remove it. Be sure the call above returned
8895 something that is still a shift. */
8897 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8898 && CONST_INT_P (XEXP (x
, 1))
8899 && INTVAL (XEXP (x
, 1)) >= 0
8900 && (INTVAL (XEXP (x
, 1))
8901 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8902 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8903 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8904 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8911 /* If the shift count is constant and we can do computations
8912 in the mode of X, compute where the bits we care about are.
8913 Otherwise, we can't do anything. Don't change the mode of
8914 the shift or propagate MODE into the shift, though. */
8915 if (CONST_INT_P (XEXP (x
, 1))
8916 && INTVAL (XEXP (x
, 1)) >= 0)
8918 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8920 gen_int_mode (mask
, GET_MODE (x
)),
8922 if (temp
&& CONST_INT_P (temp
))
8923 x
= simplify_gen_binary (code
, GET_MODE (x
),
8924 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8925 INTVAL (temp
), next_select
),
8931 /* If we just want the low-order bit, the NEG isn't needed since it
8932 won't change the low-order bit. */
8934 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8936 /* We need any bits less significant than the most significant bit in
8937 MASK since carries from those bits will affect the bits we are
8943 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8944 same as the XOR case above. Ensure that the constant we form is not
8945 wider than the mode of X. */
8947 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8948 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8949 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8950 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8951 < GET_MODE_PRECISION (GET_MODE (x
)))
8952 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8954 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8956 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8957 XEXP (XEXP (x
, 0), 0), temp
);
8958 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8959 temp
, XEXP (XEXP (x
, 0), 1));
8961 return force_to_mode (x
, mode
, mask
, next_select
);
8964 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8965 use the full mask inside the NOT. */
8969 op0
= gen_lowpart_or_truncate (op_mode
,
8970 force_to_mode (XEXP (x
, 0), mode
, mask
,
8972 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8973 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8977 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8978 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8979 which is equal to STORE_FLAG_VALUE. */
8980 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8981 && XEXP (x
, 1) == const0_rtx
8982 && GET_MODE (XEXP (x
, 0)) == mode
8983 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
8984 && (nonzero_bits (XEXP (x
, 0), mode
)
8985 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8986 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8991 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8992 written in a narrower mode. We play it safe and do not do so. */
8994 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8995 force_to_mode (XEXP (x
, 1), mode
,
8996 mask
, next_select
));
8997 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8998 force_to_mode (XEXP (x
, 2), mode
,
8999 mask
, next_select
));
9000 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9001 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
9002 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9010 /* Ensure we return a value of the proper mode. */
9011 return gen_lowpart_or_truncate (mode
, x
);
9014 /* Return nonzero if X is an expression that has one of two values depending on
9015 whether some other value is zero or nonzero. In that case, we return the
9016 value that is being tested, *PTRUE is set to the value if the rtx being
9017 returned has a nonzero value, and *PFALSE is set to the other alternative.
9019 If we return zero, we set *PTRUE and *PFALSE to X. */
9022 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9024 machine_mode mode
= GET_MODE (x
);
9025 enum rtx_code code
= GET_CODE (x
);
9026 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9027 unsigned HOST_WIDE_INT nz
;
9029 /* If we are comparing a value against zero, we are done. */
9030 if ((code
== NE
|| code
== EQ
)
9031 && XEXP (x
, 1) == const0_rtx
)
9033 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9034 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9038 /* If this is a unary operation whose operand has one of two values, apply
9039 our opcode to compute those values. */
9040 else if (UNARY_P (x
)
9041 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9043 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9044 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9045 GET_MODE (XEXP (x
, 0)));
9049 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9050 make can't possibly match and would suppress other optimizations. */
9051 else if (code
== COMPARE
)
9054 /* If this is a binary operation, see if either side has only one of two
9055 values. If either one does or if both do and they are conditional on
9056 the same value, compute the new true and false values. */
9057 else if (BINARY_P (x
))
9059 rtx op0
= XEXP (x
, 0);
9060 rtx op1
= XEXP (x
, 1);
9061 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9062 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9064 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9065 && (REG_P (op0
) || REG_P (op1
)))
9067 /* Try to enable a simplification by undoing work done by
9068 if_then_else_cond if it converted a REG into something more
9073 true0
= false0
= op0
;
9078 true1
= false1
= op1
;
9082 if ((cond0
!= 0 || cond1
!= 0)
9083 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9085 /* If if_then_else_cond returned zero, then true/false are the
9086 same rtl. We must copy one of them to prevent invalid rtl
9089 true0
= copy_rtx (true0
);
9090 else if (cond1
== 0)
9091 true1
= copy_rtx (true1
);
9093 if (COMPARISON_P (x
))
9095 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9097 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9102 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9103 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9106 return cond0
? cond0
: cond1
;
9109 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9110 operands is zero when the other is nonzero, and vice-versa,
9111 and STORE_FLAG_VALUE is 1 or -1. */
9113 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9114 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9116 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9118 rtx op0
= XEXP (XEXP (x
, 0), 1);
9119 rtx op1
= XEXP (XEXP (x
, 1), 1);
9121 cond0
= XEXP (XEXP (x
, 0), 0);
9122 cond1
= XEXP (XEXP (x
, 1), 0);
9124 if (COMPARISON_P (cond0
)
9125 && COMPARISON_P (cond1
)
9126 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9127 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9128 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9129 || ((swap_condition (GET_CODE (cond0
))
9130 == reversed_comparison_code (cond1
, NULL
))
9131 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9132 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9133 && ! side_effects_p (x
))
9135 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9136 *pfalse
= simplify_gen_binary (MULT
, mode
,
9138 ? simplify_gen_unary (NEG
, mode
,
9146 /* Similarly for MULT, AND and UMIN, except that for these the result
9148 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9149 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9150 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9152 cond0
= XEXP (XEXP (x
, 0), 0);
9153 cond1
= XEXP (XEXP (x
, 1), 0);
9155 if (COMPARISON_P (cond0
)
9156 && COMPARISON_P (cond1
)
9157 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9158 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9159 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9160 || ((swap_condition (GET_CODE (cond0
))
9161 == reversed_comparison_code (cond1
, NULL
))
9162 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9163 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9164 && ! side_effects_p (x
))
9166 *ptrue
= *pfalse
= const0_rtx
;
9172 else if (code
== IF_THEN_ELSE
)
9174 /* If we have IF_THEN_ELSE already, extract the condition and
9175 canonicalize it if it is NE or EQ. */
9176 cond0
= XEXP (x
, 0);
9177 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9178 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9179 return XEXP (cond0
, 0);
9180 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9182 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9183 return XEXP (cond0
, 0);
9189 /* If X is a SUBREG, we can narrow both the true and false values
9190 if the inner expression, if there is a condition. */
9191 else if (code
== SUBREG
9192 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9195 true0
= simplify_gen_subreg (mode
, true0
,
9196 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9197 false0
= simplify_gen_subreg (mode
, false0
,
9198 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9199 if (true0
&& false0
)
9207 /* If X is a constant, this isn't special and will cause confusions
9208 if we treat it as such. Likewise if it is equivalent to a constant. */
9209 else if (CONSTANT_P (x
)
9210 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9213 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9214 will be least confusing to the rest of the compiler. */
9215 else if (mode
== BImode
)
9217 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9221 /* If X is known to be either 0 or -1, those are the true and
9222 false values when testing X. */
9223 else if (x
== constm1_rtx
|| x
== const0_rtx
9224 || (mode
!= VOIDmode
&& mode
!= BLKmode
9225 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9227 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9231 /* Likewise for 0 or a single bit. */
9232 else if (HWI_COMPUTABLE_MODE_P (mode
)
9233 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9235 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9239 /* Otherwise fail; show no condition with true and false values the same. */
9240 *ptrue
= *pfalse
= x
;
9244 /* Return the value of expression X given the fact that condition COND
9245 is known to be true when applied to REG as its first operand and VAL
9246 as its second. X is known to not be shared and so can be modified in
9249 We only handle the simplest cases, and specifically those cases that
9250 arise with IF_THEN_ELSE expressions. */
9253 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9255 enum rtx_code code
= GET_CODE (x
);
9259 if (side_effects_p (x
))
9262 /* If either operand of the condition is a floating point value,
9263 then we have to avoid collapsing an EQ comparison. */
9265 && rtx_equal_p (x
, reg
)
9266 && ! FLOAT_MODE_P (GET_MODE (x
))
9267 && ! FLOAT_MODE_P (GET_MODE (val
)))
9270 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9273 /* If X is (abs REG) and we know something about REG's relationship
9274 with zero, we may be able to simplify this. */
9276 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9279 case GE
: case GT
: case EQ
:
9282 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9284 GET_MODE (XEXP (x
, 0)));
9289 /* The only other cases we handle are MIN, MAX, and comparisons if the
9290 operands are the same as REG and VAL. */
9292 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9294 if (rtx_equal_p (XEXP (x
, 0), val
))
9296 std::swap (val
, reg
);
9297 cond
= swap_condition (cond
);
9300 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9302 if (COMPARISON_P (x
))
9304 if (comparison_dominates_p (cond
, code
))
9305 return const_true_rtx
;
9307 code
= reversed_comparison_code (x
, NULL
);
9309 && comparison_dominates_p (cond
, code
))
9314 else if (code
== SMAX
|| code
== SMIN
9315 || code
== UMIN
|| code
== UMAX
)
9317 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9319 /* Do not reverse the condition when it is NE or EQ.
9320 This is because we cannot conclude anything about
9321 the value of 'SMAX (x, y)' when x is not equal to y,
9322 but we can when x equals y. */
9323 if ((code
== SMAX
|| code
== UMAX
)
9324 && ! (cond
== EQ
|| cond
== NE
))
9325 cond
= reverse_condition (cond
);
9330 return unsignedp
? x
: XEXP (x
, 1);
9332 return unsignedp
? x
: XEXP (x
, 0);
9334 return unsignedp
? XEXP (x
, 1) : x
;
9336 return unsignedp
? XEXP (x
, 0) : x
;
9343 else if (code
== SUBREG
)
9345 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9346 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9348 if (SUBREG_REG (x
) != r
)
9350 /* We must simplify subreg here, before we lose track of the
9351 original inner_mode. */
9352 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9353 inner_mode
, SUBREG_BYTE (x
));
9357 SUBST (SUBREG_REG (x
), r
);
9362 /* We don't have to handle SIGN_EXTEND here, because even in the
9363 case of replacing something with a modeless CONST_INT, a
9364 CONST_INT is already (supposed to be) a valid sign extension for
9365 its narrower mode, which implies it's already properly
9366 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9367 story is different. */
9368 else if (code
== ZERO_EXTEND
)
9370 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9371 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9373 if (XEXP (x
, 0) != r
)
9375 /* We must simplify the zero_extend here, before we lose
9376 track of the original inner_mode. */
9377 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9382 SUBST (XEXP (x
, 0), r
);
9388 fmt
= GET_RTX_FORMAT (code
);
9389 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9392 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9393 else if (fmt
[i
] == 'E')
9394 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9395 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9402 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9403 assignment as a field assignment. */
9406 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9408 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9410 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9412 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9414 /* For big endian, adjust the memory offset. */
9415 if (BYTES_BIG_ENDIAN
)
9416 x
= adjust_address_nv (x
, GET_MODE (y
),
9417 -subreg_lowpart_offset (GET_MODE (x
),
9420 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9423 if (x
== y
|| rtx_equal_p (x
, y
))
9426 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9429 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9430 Note that all SUBREGs of MEM are paradoxical; otherwise they
9431 would have been rewritten. */
9432 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9433 && MEM_P (SUBREG_REG (y
))
9434 && rtx_equal_p (SUBREG_REG (y
),
9435 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9438 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9439 && MEM_P (SUBREG_REG (x
))
9440 && rtx_equal_p (SUBREG_REG (x
),
9441 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9444 /* We used to see if get_last_value of X and Y were the same but that's
9445 not correct. In one direction, we'll cause the assignment to have
9446 the wrong destination and in the case, we'll import a register into this
9447 insn that might have already have been dead. So fail if none of the
9448 above cases are true. */
9452 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9453 Return that assignment if so.
9455 We only handle the most common cases. */
9458 make_field_assignment (rtx x
)
9460 rtx dest
= SET_DEST (x
);
9461 rtx src
= SET_SRC (x
);
9466 unsigned HOST_WIDE_INT len
;
9470 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9471 a clear of a one-bit field. We will have changed it to
9472 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9475 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9476 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9477 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9478 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9480 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9483 return gen_rtx_SET (assign
, const0_rtx
);
9487 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9488 && subreg_lowpart_p (XEXP (src
, 0))
9489 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9490 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9491 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9492 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9493 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9494 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9496 assign
= make_extraction (VOIDmode
, dest
, 0,
9497 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9500 return gen_rtx_SET (assign
, const0_rtx
);
9504 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9506 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9507 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9508 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9510 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9513 return gen_rtx_SET (assign
, const1_rtx
);
9517 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9518 SRC is an AND with all bits of that field set, then we can discard
9520 if (GET_CODE (dest
) == ZERO_EXTRACT
9521 && CONST_INT_P (XEXP (dest
, 1))
9522 && GET_CODE (src
) == AND
9523 && CONST_INT_P (XEXP (src
, 1)))
9525 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9526 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9527 unsigned HOST_WIDE_INT ze_mask
;
9529 if (width
>= HOST_BITS_PER_WIDE_INT
)
9532 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9534 /* Complete overlap. We can remove the source AND. */
9535 if ((and_mask
& ze_mask
) == ze_mask
)
9536 return gen_rtx_SET (dest
, XEXP (src
, 0));
9538 /* Partial overlap. We can reduce the source AND. */
9539 if ((and_mask
& ze_mask
) != and_mask
)
9541 mode
= GET_MODE (src
);
9542 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9543 gen_int_mode (and_mask
& ze_mask
, mode
));
9544 return gen_rtx_SET (dest
, src
);
9548 /* The other case we handle is assignments into a constant-position
9549 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9550 a mask that has all one bits except for a group of zero bits and
9551 OTHER is known to have zeros where C1 has ones, this is such an
9552 assignment. Compute the position and length from C1. Shift OTHER
9553 to the appropriate position, force it to the required mode, and
9554 make the extraction. Check for the AND in both operands. */
9556 /* One or more SUBREGs might obscure the constant-position field
9557 assignment. The first one we are likely to encounter is an outer
9558 narrowing SUBREG, which we can just strip for the purposes of
9559 identifying the constant-field assignment. */
9560 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9561 src
= SUBREG_REG (src
);
9563 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9566 rhs
= expand_compound_operation (XEXP (src
, 0));
9567 lhs
= expand_compound_operation (XEXP (src
, 1));
9569 if (GET_CODE (rhs
) == AND
9570 && CONST_INT_P (XEXP (rhs
, 1))
9571 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9572 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9573 /* The second SUBREG that might get in the way is a paradoxical
9574 SUBREG around the first operand of the AND. We want to
9575 pretend the operand is as wide as the destination here. We
9576 do this by adjusting the MEM to wider mode for the sole
9577 purpose of the call to rtx_equal_for_field_assignment_p. Also
9578 note this trick only works for MEMs. */
9579 else if (GET_CODE (rhs
) == AND
9580 && paradoxical_subreg_p (XEXP (rhs
, 0))
9581 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9582 && CONST_INT_P (XEXP (rhs
, 1))
9583 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9585 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9586 else if (GET_CODE (lhs
) == AND
9587 && CONST_INT_P (XEXP (lhs
, 1))
9588 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9589 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9590 /* The second SUBREG that might get in the way is a paradoxical
9591 SUBREG around the first operand of the AND. We want to
9592 pretend the operand is as wide as the destination here. We
9593 do this by adjusting the MEM to wider mode for the sole
9594 purpose of the call to rtx_equal_for_field_assignment_p. Also
9595 note this trick only works for MEMs. */
9596 else if (GET_CODE (lhs
) == AND
9597 && paradoxical_subreg_p (XEXP (lhs
, 0))
9598 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9599 && CONST_INT_P (XEXP (lhs
, 1))
9600 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9602 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9606 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9607 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9608 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9609 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9612 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9616 /* The mode to use for the source is the mode of the assignment, or of
9617 what is inside a possible STRICT_LOW_PART. */
9618 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9619 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9621 /* Shift OTHER right POS places and make it the source, restricting it
9622 to the proper length and mode. */
9624 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9628 src
= force_to_mode (src
, mode
,
9629 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9631 : (HOST_WIDE_INT_1U
<< len
) - 1,
9634 /* If SRC is masked by an AND that does not make a difference in
9635 the value being stored, strip it. */
9636 if (GET_CODE (assign
) == ZERO_EXTRACT
9637 && CONST_INT_P (XEXP (assign
, 1))
9638 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9639 && GET_CODE (src
) == AND
9640 && CONST_INT_P (XEXP (src
, 1))
9641 && UINTVAL (XEXP (src
, 1))
9642 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9643 src
= XEXP (src
, 0);
9645 return gen_rtx_SET (assign
, src
);
9648 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9652 apply_distributive_law (rtx x
)
9654 enum rtx_code code
= GET_CODE (x
);
9655 enum rtx_code inner_code
;
9656 rtx lhs
, rhs
, other
;
9659 /* Distributivity is not true for floating point as it can change the
9660 value. So we don't do it unless -funsafe-math-optimizations. */
9661 if (FLOAT_MODE_P (GET_MODE (x
))
9662 && ! flag_unsafe_math_optimizations
)
9665 /* The outer operation can only be one of the following: */
9666 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9667 && code
!= PLUS
&& code
!= MINUS
)
9673 /* If either operand is a primitive we can't do anything, so get out
9675 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9678 lhs
= expand_compound_operation (lhs
);
9679 rhs
= expand_compound_operation (rhs
);
9680 inner_code
= GET_CODE (lhs
);
9681 if (inner_code
!= GET_CODE (rhs
))
9684 /* See if the inner and outer operations distribute. */
9691 /* These all distribute except over PLUS. */
9692 if (code
== PLUS
|| code
== MINUS
)
9697 if (code
!= PLUS
&& code
!= MINUS
)
9702 /* This is also a multiply, so it distributes over everything. */
9705 /* This used to handle SUBREG, but this turned out to be counter-
9706 productive, since (subreg (op ...)) usually is not handled by
9707 insn patterns, and this "optimization" therefore transformed
9708 recognizable patterns into unrecognizable ones. Therefore the
9709 SUBREG case was removed from here.
9711 It is possible that distributing SUBREG over arithmetic operations
9712 leads to an intermediate result than can then be optimized further,
9713 e.g. by moving the outer SUBREG to the other side of a SET as done
9714 in simplify_set. This seems to have been the original intent of
9715 handling SUBREGs here.
9717 However, with current GCC this does not appear to actually happen,
9718 at least on major platforms. If some case is found where removing
9719 the SUBREG case here prevents follow-on optimizations, distributing
9720 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9726 /* Set LHS and RHS to the inner operands (A and B in the example
9727 above) and set OTHER to the common operand (C in the example).
9728 There is only one way to do this unless the inner operation is
9730 if (COMMUTATIVE_ARITH_P (lhs
)
9731 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9732 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9733 else if (COMMUTATIVE_ARITH_P (lhs
)
9734 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9735 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9736 else if (COMMUTATIVE_ARITH_P (lhs
)
9737 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9738 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9739 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9740 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9744 /* Form the new inner operation, seeing if it simplifies first. */
9745 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9747 /* There is one exception to the general way of distributing:
9748 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9749 if (code
== XOR
&& inner_code
== IOR
)
9752 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9755 /* We may be able to continuing distributing the result, so call
9756 ourselves recursively on the inner operation before forming the
9757 outer operation, which we return. */
9758 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9759 apply_distributive_law (tem
), other
);
9762 /* See if X is of the form (* (+ A B) C), and if so convert to
9763 (+ (* A C) (* B C)) and try to simplify.
9765 Most of the time, this results in no change. However, if some of
9766 the operands are the same or inverses of each other, simplifications
9769 For example, (and (ior A B) (not B)) can occur as the result of
9770 expanding a bit field assignment. When we apply the distributive
9771 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9772 which then simplifies to (and (A (not B))).
9774 Note that no checks happen on the validity of applying the inverse
9775 distributive law. This is pointless since we can do it in the
9776 few places where this routine is called.
9778 N is the index of the term that is decomposed (the arithmetic operation,
9779 i.e. (+ A B) in the first example above). !N is the index of the term that
9780 is distributed, i.e. of C in the first example above. */
9782 distribute_and_simplify_rtx (rtx x
, int n
)
9785 enum rtx_code outer_code
, inner_code
;
9786 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9788 /* Distributivity is not true for floating point as it can change the
9789 value. So we don't do it unless -funsafe-math-optimizations. */
9790 if (FLOAT_MODE_P (GET_MODE (x
))
9791 && ! flag_unsafe_math_optimizations
)
9794 decomposed
= XEXP (x
, n
);
9795 if (!ARITHMETIC_P (decomposed
))
9798 mode
= GET_MODE (x
);
9799 outer_code
= GET_CODE (x
);
9800 distributed
= XEXP (x
, !n
);
9802 inner_code
= GET_CODE (decomposed
);
9803 inner_op0
= XEXP (decomposed
, 0);
9804 inner_op1
= XEXP (decomposed
, 1);
9806 /* Special case (and (xor B C) (not A)), which is equivalent to
9807 (xor (ior A B) (ior A C)) */
9808 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9810 distributed
= XEXP (distributed
, 0);
9816 /* Distribute the second term. */
9817 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9818 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9822 /* Distribute the first term. */
9823 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9824 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9827 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9829 if (GET_CODE (tmp
) != outer_code
9830 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9831 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9837 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9838 in MODE. Return an equivalent form, if different from (and VAROP
9839 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9842 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9843 unsigned HOST_WIDE_INT constop
)
9845 unsigned HOST_WIDE_INT nonzero
;
9846 unsigned HOST_WIDE_INT orig_constop
;
9851 orig_constop
= constop
;
9852 if (GET_CODE (varop
) == CLOBBER
)
9855 /* Simplify VAROP knowing that we will be only looking at some of the
9858 Note by passing in CONSTOP, we guarantee that the bits not set in
9859 CONSTOP are not significant and will never be examined. We must
9860 ensure that is the case by explicitly masking out those bits
9861 before returning. */
9862 varop
= force_to_mode (varop
, mode
, constop
, 0);
9864 /* If VAROP is a CLOBBER, we will fail so return it. */
9865 if (GET_CODE (varop
) == CLOBBER
)
9868 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9869 to VAROP and return the new constant. */
9870 if (CONST_INT_P (varop
))
9871 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9873 /* See what bits may be nonzero in VAROP. Unlike the general case of
9874 a call to nonzero_bits, here we don't care about bits outside
9877 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9879 /* Turn off all bits in the constant that are known to already be zero.
9880 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9881 which is tested below. */
9885 /* If we don't have any bits left, return zero. */
9889 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9890 a power of two, we can replace this with an ASHIFT. */
9891 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9892 && (i
= exact_log2 (constop
)) >= 0)
9893 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9895 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9896 or XOR, then try to apply the distributive law. This may eliminate
9897 operations if either branch can be simplified because of the AND.
9898 It may also make some cases more complex, but those cases probably
9899 won't match a pattern either with or without this. */
9901 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9905 apply_distributive_law
9906 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9907 simplify_and_const_int (NULL_RTX
,
9911 simplify_and_const_int (NULL_RTX
,
9916 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9917 the AND and see if one of the operands simplifies to zero. If so, we
9918 may eliminate it. */
9920 if (GET_CODE (varop
) == PLUS
9921 && pow2p_hwi (constop
+ 1))
9925 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9926 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9927 if (o0
== const0_rtx
)
9929 if (o1
== const0_rtx
)
9933 /* Make a SUBREG if necessary. If we can't make it, fail. */
9934 varop
= gen_lowpart (mode
, varop
);
9935 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9938 /* If we are only masking insignificant bits, return VAROP. */
9939 if (constop
== nonzero
)
9942 if (varop
== orig_varop
&& constop
== orig_constop
)
9945 /* Otherwise, return an AND. */
9946 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9950 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9953 Return an equivalent form, if different from X. Otherwise, return X. If
9954 X is zero, we are to always construct the equivalent form. */
9957 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9958 unsigned HOST_WIDE_INT constop
)
9960 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9965 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9966 gen_int_mode (constop
, mode
));
9967 if (GET_MODE (x
) != mode
)
9968 x
= gen_lowpart (mode
, x
);
9972 /* Given a REG, X, compute which bits in X can be nonzero.
9973 We don't care about bits outside of those defined in MODE.
9975 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9976 a shift, AND, or zero_extract, we can do better. */
9979 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9980 const_rtx known_x ATTRIBUTE_UNUSED
,
9981 machine_mode known_mode ATTRIBUTE_UNUSED
,
9982 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9983 unsigned HOST_WIDE_INT
*nonzero
)
9988 /* If X is a register whose nonzero bits value is current, use it.
9989 Otherwise, if X is a register whose value we can find, use that
9990 value. Otherwise, use the previously-computed global nonzero bits
9991 for this register. */
9993 rsp
= ®_stat
[REGNO (x
)];
9994 if (rsp
->last_set_value
!= 0
9995 && (rsp
->last_set_mode
== mode
9996 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9997 && GET_MODE_CLASS (mode
) == MODE_INT
))
9998 && ((rsp
->last_set_label
>= label_tick_ebb_start
9999 && rsp
->last_set_label
< label_tick
)
10000 || (rsp
->last_set_label
== label_tick
10001 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10002 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10003 && REGNO (x
) < reg_n_sets_max
10004 && REG_N_SETS (REGNO (x
)) == 1
10005 && !REGNO_REG_SET_P
10006 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10009 /* Note that, even if the precision of last_set_mode is lower than that
10010 of mode, record_value_for_reg invoked nonzero_bits on the register
10011 with nonzero_bits_mode (because last_set_mode is necessarily integral
10012 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10013 are all valid, hence in mode too since nonzero_bits_mode is defined
10014 to the largest HWI_COMPUTABLE_MODE_P mode. */
10015 *nonzero
&= rsp
->last_set_nonzero_bits
;
10019 tem
= get_last_value (x
);
10022 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10023 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
10024 GET_MODE_PRECISION (mode
));
10029 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10031 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10033 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
10034 /* We don't know anything about the upper bits. */
10035 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
10043 /* Return the number of bits at the high-order end of X that are known to
10044 be equal to the sign bit. X will be used in mode MODE; if MODE is
10045 VOIDmode, X will be used in its own mode. The returned value will always
10046 be between 1 and the number of bits in MODE. */
10049 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
10050 const_rtx known_x ATTRIBUTE_UNUSED
,
10051 machine_mode known_mode
10053 unsigned int known_ret ATTRIBUTE_UNUSED
,
10054 unsigned int *result
)
10057 reg_stat_type
*rsp
;
10059 rsp
= ®_stat
[REGNO (x
)];
10060 if (rsp
->last_set_value
!= 0
10061 && rsp
->last_set_mode
== mode
10062 && ((rsp
->last_set_label
>= label_tick_ebb_start
10063 && rsp
->last_set_label
< label_tick
)
10064 || (rsp
->last_set_label
== label_tick
10065 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10066 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10067 && REGNO (x
) < reg_n_sets_max
10068 && REG_N_SETS (REGNO (x
)) == 1
10069 && !REGNO_REG_SET_P
10070 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10073 *result
= rsp
->last_set_sign_bit_copies
;
10077 tem
= get_last_value (x
);
10081 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10082 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
10083 *result
= rsp
->sign_bit_copies
;
10088 /* Return the number of "extended" bits there are in X, when interpreted
10089 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10090 unsigned quantities, this is the number of high-order zero bits.
10091 For signed quantities, this is the number of copies of the sign bit
10092 minus 1. In both case, this function returns the number of "spare"
10093 bits. For example, if two quantities for which this function returns
10094 at least 1 are added, the addition is known not to overflow.
10096 This function will always return 0 unless called during combine, which
10097 implies that it must be called from a define_split. */
10100 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10102 if (nonzero_sign_valid
== 0)
10106 ? (HWI_COMPUTABLE_MODE_P (mode
)
10107 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
10108 - floor_log2 (nonzero_bits (x
, mode
)))
10110 : num_sign_bit_copies (x
, mode
) - 1);
10113 /* This function is called from `simplify_shift_const' to merge two
10114 outer operations. Specifically, we have already found that we need
10115 to perform operation *POP0 with constant *PCONST0 at the outermost
10116 position. We would now like to also perform OP1 with constant CONST1
10117 (with *POP0 being done last).
10119 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10120 the resulting operation. *PCOMP_P is set to 1 if we would need to
10121 complement the innermost operand, otherwise it is unchanged.
10123 MODE is the mode in which the operation will be done. No bits outside
10124 the width of this mode matter. It is assumed that the width of this mode
10125 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10127 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10128 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10129 result is simply *PCONST0.
10131 If the resulting operation cannot be expressed as one operation, we
10132 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10135 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10137 enum rtx_code op0
= *pop0
;
10138 HOST_WIDE_INT const0
= *pconst0
;
10140 const0
&= GET_MODE_MASK (mode
);
10141 const1
&= GET_MODE_MASK (mode
);
10143 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10147 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10150 if (op1
== UNKNOWN
|| op0
== SET
)
10153 else if (op0
== UNKNOWN
)
10154 op0
= op1
, const0
= const1
;
10156 else if (op0
== op1
)
10180 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10181 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10184 /* If the two constants aren't the same, we can't do anything. The
10185 remaining six cases can all be done. */
10186 else if (const0
!= const1
)
10194 /* (a & b) | b == b */
10196 else /* op1 == XOR */
10197 /* (a ^ b) | b == a | b */
10203 /* (a & b) ^ b == (~a) & b */
10204 op0
= AND
, *pcomp_p
= 1;
10205 else /* op1 == IOR */
10206 /* (a | b) ^ b == a & ~b */
10207 op0
= AND
, const0
= ~const0
;
10212 /* (a | b) & b == b */
10214 else /* op1 == XOR */
10215 /* (a ^ b) & b) == (~a) & b */
10222 /* Check for NO-OP cases. */
10223 const0
&= GET_MODE_MASK (mode
);
10225 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10227 else if (const0
== 0 && op0
== AND
)
10229 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10235 /* ??? Slightly redundant with the above mask, but not entirely.
10236 Moving this above means we'd have to sign-extend the mode mask
10237 for the final test. */
10238 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10239 *pconst0
= trunc_int_for_mode (const0
, mode
);
10244 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10245 the shift in. The original shift operation CODE is performed on OP in
10246 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10247 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10248 result of the shift is subject to operation OUTER_CODE with operand
10251 static machine_mode
10252 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10253 machine_mode orig_mode
, machine_mode mode
,
10254 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10256 if (orig_mode
== mode
)
10258 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10260 /* In general we can't perform in wider mode for right shift and rotate. */
10264 /* We can still widen if the bits brought in from the left are identical
10265 to the sign bit of ORIG_MODE. */
10266 if (num_sign_bit_copies (op
, mode
)
10267 > (unsigned) (GET_MODE_PRECISION (mode
)
10268 - GET_MODE_PRECISION (orig_mode
)))
10273 /* Similarly here but with zero bits. */
10274 if (HWI_COMPUTABLE_MODE_P (mode
)
10275 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10278 /* We can also widen if the bits brought in will be masked off. This
10279 operation is performed in ORIG_MODE. */
10280 if (outer_code
== AND
)
10282 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10285 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10294 gcc_unreachable ();
10301 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10302 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10303 if we cannot simplify it. Otherwise, return a simplified value.
10305 The shift is normally computed in the widest mode we find in VAROP, as
10306 long as it isn't a different number of words than RESULT_MODE. Exceptions
10307 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10310 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10311 rtx varop
, int orig_count
)
10313 enum rtx_code orig_code
= code
;
10314 rtx orig_varop
= varop
;
10316 machine_mode mode
= result_mode
;
10317 machine_mode shift_mode
, tmode
;
10318 unsigned int mode_words
10319 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10320 /* We form (outer_op (code varop count) (outer_const)). */
10321 enum rtx_code outer_op
= UNKNOWN
;
10322 HOST_WIDE_INT outer_const
= 0;
10323 int complement_p
= 0;
10326 /* Make sure and truncate the "natural" shift on the way in. We don't
10327 want to do this inside the loop as it makes it more difficult to
10329 if (SHIFT_COUNT_TRUNCATED
)
10330 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10332 /* If we were given an invalid count, don't do anything except exactly
10333 what was requested. */
10335 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10338 count
= orig_count
;
10340 /* Unless one of the branches of the `if' in this loop does a `continue',
10341 we will `break' the loop after the `if'. */
10345 /* If we have an operand of (clobber (const_int 0)), fail. */
10346 if (GET_CODE (varop
) == CLOBBER
)
10349 /* Convert ROTATERT to ROTATE. */
10350 if (code
== ROTATERT
)
10352 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10354 count
= bitsize
- count
;
10357 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10358 mode
, outer_op
, outer_const
);
10359 machine_mode shift_unit_mode
= GET_MODE_INNER (shift_mode
);
10361 /* Handle cases where the count is greater than the size of the mode
10362 minus 1. For ASHIFT, use the size minus one as the count (this can
10363 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10364 take the count modulo the size. For other shifts, the result is
10367 Since these shifts are being produced by the compiler by combining
10368 multiple operations, each of which are defined, we know what the
10369 result is supposed to be. */
10371 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10373 if (code
== ASHIFTRT
)
10374 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10375 else if (code
== ROTATE
|| code
== ROTATERT
)
10376 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10379 /* We can't simply return zero because there may be an
10381 varop
= const0_rtx
;
10387 /* If we discovered we had to complement VAROP, leave. Making a NOT
10388 here would cause an infinite loop. */
10392 if (shift_mode
== shift_unit_mode
)
10394 /* An arithmetic right shift of a quantity known to be -1 or 0
10396 if (code
== ASHIFTRT
10397 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10398 == GET_MODE_PRECISION (shift_unit_mode
)))
10404 /* If we are doing an arithmetic right shift and discarding all but
10405 the sign bit copies, this is equivalent to doing a shift by the
10406 bitsize minus one. Convert it into that shift because it will
10407 often allow other simplifications. */
10409 if (code
== ASHIFTRT
10410 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10411 >= GET_MODE_PRECISION (shift_unit_mode
)))
10412 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10414 /* We simplify the tests below and elsewhere by converting
10415 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10416 `make_compound_operation' will convert it to an ASHIFTRT for
10417 those machines (such as VAX) that don't have an LSHIFTRT. */
10418 if (code
== ASHIFTRT
10419 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10420 && val_signbit_known_clear_p (shift_unit_mode
,
10421 nonzero_bits (varop
,
10425 if (((code
== LSHIFTRT
10426 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10427 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10429 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10430 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10431 & GET_MODE_MASK (shift_unit_mode
))))
10432 && !side_effects_p (varop
))
10433 varop
= const0_rtx
;
10436 switch (GET_CODE (varop
))
10442 new_rtx
= expand_compound_operation (varop
);
10443 if (new_rtx
!= varop
)
10451 /* The following rules apply only to scalars. */
10452 if (shift_mode
!= shift_unit_mode
)
10455 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10456 minus the width of a smaller mode, we can do this with a
10457 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10458 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10459 && ! mode_dependent_address_p (XEXP (varop
, 0),
10460 MEM_ADDR_SPACE (varop
))
10461 && ! MEM_VOLATILE_P (varop
)
10462 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10463 MODE_INT
, 1)) != BLKmode
)
10465 new_rtx
= adjust_address_nv (varop
, tmode
,
10466 BYTES_BIG_ENDIAN
? 0
10467 : count
/ BITS_PER_UNIT
);
10469 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10470 : ZERO_EXTEND
, mode
, new_rtx
);
10477 /* The following rules apply only to scalars. */
10478 if (shift_mode
!= shift_unit_mode
)
10481 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10482 the same number of words as what we've seen so far. Then store
10483 the widest mode in MODE. */
10484 if (subreg_lowpart_p (varop
)
10485 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10486 > GET_MODE_SIZE (GET_MODE (varop
)))
10487 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10488 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10490 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10491 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10493 varop
= SUBREG_REG (varop
);
10494 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10495 mode
= GET_MODE (varop
);
10501 /* Some machines use MULT instead of ASHIFT because MULT
10502 is cheaper. But it is still better on those machines to
10503 merge two shifts into one. */
10504 if (CONST_INT_P (XEXP (varop
, 1))
10505 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10508 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10510 GEN_INT (exact_log2 (
10511 UINTVAL (XEXP (varop
, 1)))));
10517 /* Similar, for when divides are cheaper. */
10518 if (CONST_INT_P (XEXP (varop
, 1))
10519 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10522 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10524 GEN_INT (exact_log2 (
10525 UINTVAL (XEXP (varop
, 1)))));
10531 /* If we are extracting just the sign bit of an arithmetic
10532 right shift, that shift is not needed. However, the sign
10533 bit of a wider mode may be different from what would be
10534 interpreted as the sign bit in a narrower mode, so, if
10535 the result is narrower, don't discard the shift. */
10536 if (code
== LSHIFTRT
10537 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10538 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10539 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10541 varop
= XEXP (varop
, 0);
10550 /* The following rules apply only to scalars. */
10551 if (shift_mode
!= shift_unit_mode
)
10554 /* Here we have two nested shifts. The result is usually the
10555 AND of a new shift with a mask. We compute the result below. */
10556 if (CONST_INT_P (XEXP (varop
, 1))
10557 && INTVAL (XEXP (varop
, 1)) >= 0
10558 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10559 && HWI_COMPUTABLE_MODE_P (result_mode
)
10560 && HWI_COMPUTABLE_MODE_P (mode
))
10562 enum rtx_code first_code
= GET_CODE (varop
);
10563 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10564 unsigned HOST_WIDE_INT mask
;
10567 /* We have one common special case. We can't do any merging if
10568 the inner code is an ASHIFTRT of a smaller mode. However, if
10569 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10570 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10571 we can convert it to
10572 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10573 This simplifies certain SIGN_EXTEND operations. */
10574 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10575 && count
== (GET_MODE_PRECISION (result_mode
)
10576 - GET_MODE_PRECISION (GET_MODE (varop
))))
10578 /* C3 has the low-order C1 bits zero. */
10580 mask
= GET_MODE_MASK (mode
)
10581 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10583 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10584 XEXP (varop
, 0), mask
);
10585 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10587 count
= first_count
;
10592 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10593 than C1 high-order bits equal to the sign bit, we can convert
10594 this to either an ASHIFT or an ASHIFTRT depending on the
10597 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10599 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10600 && GET_MODE (varop
) == shift_mode
10601 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10604 varop
= XEXP (varop
, 0);
10605 count
-= first_count
;
10615 /* There are some cases we can't do. If CODE is ASHIFTRT,
10616 we can only do this if FIRST_CODE is also ASHIFTRT.
10618 We can't do the case when CODE is ROTATE and FIRST_CODE is
10621 If the mode of this shift is not the mode of the outer shift,
10622 we can't do this if either shift is a right shift or ROTATE.
10624 Finally, we can't do any of these if the mode is too wide
10625 unless the codes are the same.
10627 Handle the case where the shift codes are the same
10630 if (code
== first_code
)
10632 if (GET_MODE (varop
) != result_mode
10633 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10634 || code
== ROTATE
))
10637 count
+= first_count
;
10638 varop
= XEXP (varop
, 0);
10642 if (code
== ASHIFTRT
10643 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10644 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10645 || (GET_MODE (varop
) != result_mode
10646 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10647 || first_code
== ROTATE
10648 || code
== ROTATE
)))
10651 /* To compute the mask to apply after the shift, shift the
10652 nonzero bits of the inner shift the same way the
10653 outer shift will. */
10655 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10659 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10662 /* Give up if we can't compute an outer operation to use. */
10664 || !CONST_INT_P (mask_rtx
)
10665 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10667 result_mode
, &complement_p
))
10670 /* If the shifts are in the same direction, we add the
10671 counts. Otherwise, we subtract them. */
10672 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10673 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10674 count
+= first_count
;
10676 count
-= first_count
;
10678 /* If COUNT is positive, the new shift is usually CODE,
10679 except for the two exceptions below, in which case it is
10680 FIRST_CODE. If the count is negative, FIRST_CODE should
10683 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10684 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10686 else if (count
< 0)
10687 code
= first_code
, count
= -count
;
10689 varop
= XEXP (varop
, 0);
10693 /* If we have (A << B << C) for any shift, we can convert this to
10694 (A << C << B). This wins if A is a constant. Only try this if
10695 B is not a constant. */
10697 else if (GET_CODE (varop
) == code
10698 && CONST_INT_P (XEXP (varop
, 0))
10699 && !CONST_INT_P (XEXP (varop
, 1)))
10701 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10702 sure the result will be masked. See PR70222. */
10703 if (code
== LSHIFTRT
10704 && mode
!= result_mode
10705 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10706 GET_MODE_MASK (result_mode
)
10707 >> orig_count
, result_mode
,
10710 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10711 up outer sign extension (often left and right shift) is
10712 hardly more efficient than the original. See PR70429. */
10713 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10716 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10719 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10726 /* The following rules apply only to scalars. */
10727 if (shift_mode
!= shift_unit_mode
)
10730 /* Make this fit the case below. */
10731 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10737 /* The following rules apply only to scalars. */
10738 if (shift_mode
!= shift_unit_mode
)
10741 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10742 with C the size of VAROP - 1 and the shift is logical if
10743 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10744 we have an (le X 0) operation. If we have an arithmetic shift
10745 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10746 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10748 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10749 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10750 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10751 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10752 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10753 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10756 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10759 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10760 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10765 /* If we have (shift (logical)), move the logical to the outside
10766 to allow it to possibly combine with another logical and the
10767 shift to combine with another shift. This also canonicalizes to
10768 what a ZERO_EXTRACT looks like. Also, some machines have
10769 (and (shift)) insns. */
10771 if (CONST_INT_P (XEXP (varop
, 1))
10772 /* We can't do this if we have (ashiftrt (xor)) and the
10773 constant has its sign bit set in shift_mode with shift_mode
10774 wider than result_mode. */
10775 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10776 && result_mode
!= shift_mode
10777 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10779 && (new_rtx
= simplify_const_binary_operation
10780 (code
, result_mode
,
10781 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10782 GEN_INT (count
))) != 0
10783 && CONST_INT_P (new_rtx
)
10784 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10785 INTVAL (new_rtx
), result_mode
, &complement_p
))
10787 varop
= XEXP (varop
, 0);
10791 /* If we can't do that, try to simplify the shift in each arm of the
10792 logical expression, make a new logical expression, and apply
10793 the inverse distributive law. This also can't be done for
10794 (ashiftrt (xor)) where we've widened the shift and the constant
10795 changes the sign bit. */
10796 if (CONST_INT_P (XEXP (varop
, 1))
10797 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10798 && result_mode
!= shift_mode
10799 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10802 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10803 XEXP (varop
, 0), count
);
10804 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10805 XEXP (varop
, 1), count
);
10807 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10809 varop
= apply_distributive_law (varop
);
10817 /* The following rules apply only to scalars. */
10818 if (shift_mode
!= shift_unit_mode
)
10821 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10822 says that the sign bit can be tested, FOO has mode MODE, C is
10823 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10824 that may be nonzero. */
10825 if (code
== LSHIFTRT
10826 && XEXP (varop
, 1) == const0_rtx
10827 && GET_MODE (XEXP (varop
, 0)) == result_mode
10828 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10829 && HWI_COMPUTABLE_MODE_P (result_mode
)
10830 && STORE_FLAG_VALUE
== -1
10831 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10832 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10835 varop
= XEXP (varop
, 0);
10842 /* The following rules apply only to scalars. */
10843 if (shift_mode
!= shift_unit_mode
)
10846 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10847 than the number of bits in the mode is equivalent to A. */
10848 if (code
== LSHIFTRT
10849 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10850 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10852 varop
= XEXP (varop
, 0);
10857 /* NEG commutes with ASHIFT since it is multiplication. Move the
10858 NEG outside to allow shifts to combine. */
10860 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10863 varop
= XEXP (varop
, 0);
10869 /* The following rules apply only to scalars. */
10870 if (shift_mode
!= shift_unit_mode
)
10873 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10874 is one less than the number of bits in the mode is
10875 equivalent to (xor A 1). */
10876 if (code
== LSHIFTRT
10877 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10878 && XEXP (varop
, 1) == constm1_rtx
10879 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10880 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10884 varop
= XEXP (varop
, 0);
10888 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10889 that might be nonzero in BAR are those being shifted out and those
10890 bits are known zero in FOO, we can replace the PLUS with FOO.
10891 Similarly in the other operand order. This code occurs when
10892 we are computing the size of a variable-size array. */
10894 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10895 && count
< HOST_BITS_PER_WIDE_INT
10896 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10897 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10898 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10900 varop
= XEXP (varop
, 0);
10903 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10904 && count
< HOST_BITS_PER_WIDE_INT
10905 && HWI_COMPUTABLE_MODE_P (result_mode
)
10906 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10908 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10909 & nonzero_bits (XEXP (varop
, 1),
10912 varop
= XEXP (varop
, 1);
10916 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10918 && CONST_INT_P (XEXP (varop
, 1))
10919 && (new_rtx
= simplify_const_binary_operation
10920 (ASHIFT
, result_mode
,
10921 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10922 GEN_INT (count
))) != 0
10923 && CONST_INT_P (new_rtx
)
10924 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10925 INTVAL (new_rtx
), result_mode
, &complement_p
))
10927 varop
= XEXP (varop
, 0);
10931 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10932 signbit', and attempt to change the PLUS to an XOR and move it to
10933 the outer operation as is done above in the AND/IOR/XOR case
10934 leg for shift(logical). See details in logical handling above
10935 for reasoning in doing so. */
10936 if (code
== LSHIFTRT
10937 && CONST_INT_P (XEXP (varop
, 1))
10938 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10939 && (new_rtx
= simplify_const_binary_operation
10940 (code
, result_mode
,
10941 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10942 GEN_INT (count
))) != 0
10943 && CONST_INT_P (new_rtx
)
10944 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10945 INTVAL (new_rtx
), result_mode
, &complement_p
))
10947 varop
= XEXP (varop
, 0);
10954 /* The following rules apply only to scalars. */
10955 if (shift_mode
!= shift_unit_mode
)
10958 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10959 with C the size of VAROP - 1 and the shift is logical if
10960 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10961 we have a (gt X 0) operation. If the shift is arithmetic with
10962 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10963 we have a (neg (gt X 0)) operation. */
10965 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10966 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10967 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10968 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10969 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10970 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10971 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10974 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10977 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10978 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10985 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10986 if the truncate does not affect the value. */
10987 if (code
== LSHIFTRT
10988 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10989 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10990 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10991 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
10992 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
10994 rtx varop_inner
= XEXP (varop
, 0);
10997 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10998 XEXP (varop_inner
, 0),
11000 (count
+ INTVAL (XEXP (varop_inner
, 1))));
11001 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11014 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
11015 outer_op
, outer_const
);
11017 /* We have now finished analyzing the shift. The result should be
11018 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11019 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11020 to the result of the shift. OUTER_CONST is the relevant constant,
11021 but we must turn off all bits turned off in the shift. */
11023 if (outer_op
== UNKNOWN
11024 && orig_code
== code
&& orig_count
== count
11025 && varop
== orig_varop
11026 && shift_mode
== GET_MODE (varop
))
11029 /* Make a SUBREG if necessary. If we can't make it, fail. */
11030 varop
= gen_lowpart (shift_mode
, varop
);
11031 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11034 /* If we have an outer operation and we just made a shift, it is
11035 possible that we could have simplified the shift were it not
11036 for the outer operation. So try to do the simplification
11039 if (outer_op
!= UNKNOWN
)
11040 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11045 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11047 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11048 turn off all the bits that the shift would have turned off. */
11049 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11050 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
11051 GET_MODE_MASK (result_mode
) >> orig_count
);
11053 /* Do the remainder of the processing in RESULT_MODE. */
11054 x
= gen_lowpart_or_truncate (result_mode
, x
);
11056 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11059 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11061 if (outer_op
!= UNKNOWN
)
11063 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11064 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
11065 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
11067 if (outer_op
== AND
)
11068 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
11069 else if (outer_op
== SET
)
11071 /* This means that we have determined that the result is
11072 equivalent to a constant. This should be rare. */
11073 if (!side_effects_p (x
))
11074 x
= GEN_INT (outer_const
);
11076 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11077 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
11079 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
11080 GEN_INT (outer_const
));
11086 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11087 The result of the shift is RESULT_MODE. If we cannot simplify it,
11088 return X or, if it is NULL, synthesize the expression with
11089 simplify_gen_binary. Otherwise, return a simplified value.
11091 The shift is normally computed in the widest mode we find in VAROP, as
11092 long as it isn't a different number of words than RESULT_MODE. Exceptions
11093 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11096 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11097 rtx varop
, int count
)
11099 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11104 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11105 if (GET_MODE (x
) != result_mode
)
11106 x
= gen_lowpart (result_mode
, x
);
11111 /* A subroutine of recog_for_combine. See there for arguments and
11115 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11117 rtx pat
= *pnewpat
;
11118 rtx pat_without_clobbers
;
11119 int insn_code_number
;
11120 int num_clobbers_to_add
= 0;
11122 rtx notes
= NULL_RTX
;
11123 rtx old_notes
, old_pat
;
11126 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11127 we use to indicate that something didn't match. If we find such a
11128 thing, force rejection. */
11129 if (GET_CODE (pat
) == PARALLEL
)
11130 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11131 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11132 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11135 old_pat
= PATTERN (insn
);
11136 old_notes
= REG_NOTES (insn
);
11137 PATTERN (insn
) = pat
;
11138 REG_NOTES (insn
) = NULL_RTX
;
11140 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11141 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11143 if (insn_code_number
< 0)
11144 fputs ("Failed to match this instruction:\n", dump_file
);
11146 fputs ("Successfully matched this instruction:\n", dump_file
);
11147 print_rtl_single (dump_file
, pat
);
11150 /* If it isn't, there is the possibility that we previously had an insn
11151 that clobbered some register as a side effect, but the combined
11152 insn doesn't need to do that. So try once more without the clobbers
11153 unless this represents an ASM insn. */
11155 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11156 && GET_CODE (pat
) == PARALLEL
)
11160 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11161 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11164 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11168 SUBST_INT (XVECLEN (pat
, 0), pos
);
11171 pat
= XVECEXP (pat
, 0, 0);
11173 PATTERN (insn
) = pat
;
11174 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11175 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11177 if (insn_code_number
< 0)
11178 fputs ("Failed to match this instruction:\n", dump_file
);
11180 fputs ("Successfully matched this instruction:\n", dump_file
);
11181 print_rtl_single (dump_file
, pat
);
11185 pat_without_clobbers
= pat
;
11187 PATTERN (insn
) = old_pat
;
11188 REG_NOTES (insn
) = old_notes
;
11190 /* Recognize all noop sets, these will be killed by followup pass. */
11191 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11192 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11194 /* If we had any clobbers to add, make a new pattern than contains
11195 them. Then check to make sure that all of them are dead. */
11196 if (num_clobbers_to_add
)
11198 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11199 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11200 ? (XVECLEN (pat
, 0)
11201 + num_clobbers_to_add
)
11202 : num_clobbers_to_add
+ 1));
11204 if (GET_CODE (pat
) == PARALLEL
)
11205 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11206 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11208 XVECEXP (newpat
, 0, 0) = pat
;
11210 add_clobbers (newpat
, insn_code_number
);
11212 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11213 i
< XVECLEN (newpat
, 0); i
++)
11215 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11216 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11218 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11220 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11221 notes
= alloc_reg_note (REG_UNUSED
,
11222 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11228 if (insn_code_number
>= 0
11229 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11231 old_pat
= PATTERN (insn
);
11232 old_notes
= REG_NOTES (insn
);
11233 old_icode
= INSN_CODE (insn
);
11234 PATTERN (insn
) = pat
;
11235 REG_NOTES (insn
) = notes
;
11236 INSN_CODE (insn
) = insn_code_number
;
11238 /* Allow targets to reject combined insn. */
11239 if (!targetm
.legitimate_combined_insn (insn
))
11241 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11242 fputs ("Instruction not appropriate for target.",
11245 /* Callers expect recog_for_combine to strip
11246 clobbers from the pattern on failure. */
11247 pat
= pat_without_clobbers
;
11250 insn_code_number
= -1;
11253 PATTERN (insn
) = old_pat
;
11254 REG_NOTES (insn
) = old_notes
;
11255 INSN_CODE (insn
) = old_icode
;
11261 return insn_code_number
;
11264 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11265 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11266 Return whether anything was so changed. */
11269 change_zero_ext (rtx pat
)
11271 bool changed
= false;
11272 rtx
*src
= &SET_SRC (pat
);
11274 subrtx_ptr_iterator::array_type array
;
11275 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11278 machine_mode mode
= GET_MODE (x
);
11281 if (GET_CODE (x
) == ZERO_EXTRACT
11282 && CONST_INT_P (XEXP (x
, 1))
11283 && CONST_INT_P (XEXP (x
, 2))
11284 && GET_MODE (XEXP (x
, 0)) != VOIDmode
11285 && GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
11286 <= GET_MODE_PRECISION (mode
))
11288 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
11290 size
= INTVAL (XEXP (x
, 1));
11292 int start
= INTVAL (XEXP (x
, 2));
11293 if (BITS_BIG_ENDIAN
)
11294 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11297 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11300 if (mode
!= inner_mode
)
11301 x
= gen_lowpart_SUBREG (mode
, x
);
11303 else if (GET_CODE (x
) == ZERO_EXTEND
11304 && SCALAR_INT_MODE_P (mode
)
11305 && GET_CODE (XEXP (x
, 0)) == SUBREG
11306 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11307 && !paradoxical_subreg_p (XEXP (x
, 0))
11308 && subreg_lowpart_p (XEXP (x
, 0)))
11310 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11311 x
= SUBREG_REG (XEXP (x
, 0));
11312 if (GET_MODE (x
) != mode
)
11313 x
= gen_lowpart_SUBREG (mode
, x
);
11315 else if (GET_CODE (x
) == ZERO_EXTEND
11316 && SCALAR_INT_MODE_P (mode
)
11317 && REG_P (XEXP (x
, 0))
11318 && HARD_REGISTER_P (XEXP (x
, 0))
11319 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11321 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11322 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11327 if (!(GET_CODE (x
) == LSHIFTRT
11328 && CONST_INT_P (XEXP (x
, 1))
11329 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11331 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11332 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11340 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11341 maybe_swap_commutative_operands (**iter
);
11343 rtx
*dst
= &SET_DEST (pat
);
11344 if (GET_CODE (*dst
) == ZERO_EXTRACT
11345 && REG_P (XEXP (*dst
, 0))
11346 && CONST_INT_P (XEXP (*dst
, 1))
11347 && CONST_INT_P (XEXP (*dst
, 2)))
11349 rtx reg
= XEXP (*dst
, 0);
11350 int width
= INTVAL (XEXP (*dst
, 1));
11351 int offset
= INTVAL (XEXP (*dst
, 2));
11352 machine_mode mode
= GET_MODE (reg
);
11353 int reg_width
= GET_MODE_PRECISION (mode
);
11354 if (BITS_BIG_ENDIAN
)
11355 offset
= reg_width
- width
- offset
;
11358 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11359 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11360 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11362 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11365 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11366 w
= gen_rtx_IOR (mode
, x
, z
);
11367 SUBST (SET_DEST (pat
), reg
);
11368 SUBST (SET_SRC (pat
), w
);
11376 /* Like recog, but we receive the address of a pointer to a new pattern.
11377 We try to match the rtx that the pointer points to.
11378 If that fails, we may try to modify or replace the pattern,
11379 storing the replacement into the same pointer object.
11381 Modifications include deletion or addition of CLOBBERs. If the
11382 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11383 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11384 (and undo if that fails).
11386 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11387 the CLOBBERs are placed.
11389 The value is the final insn code from the pattern ultimately matched,
11393 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11395 rtx pat
= *pnewpat
;
11396 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11397 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11398 return insn_code_number
;
11400 void *marker
= get_undo_marker ();
11401 bool changed
= false;
11403 if (GET_CODE (pat
) == SET
)
11404 changed
= change_zero_ext (pat
);
11405 else if (GET_CODE (pat
) == PARALLEL
)
11408 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11410 rtx set
= XVECEXP (pat
, 0, i
);
11411 if (GET_CODE (set
) == SET
)
11412 changed
|= change_zero_ext (set
);
11418 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11420 if (insn_code_number
< 0)
11421 undo_to_marker (marker
);
11424 return insn_code_number
;
11427 /* Like gen_lowpart_general but for use by combine. In combine it
11428 is not possible to create any new pseudoregs. However, it is
11429 safe to create invalid memory addresses, because combine will
11430 try to recognize them and all they will do is make the combine
11433 If for some reason this cannot do its job, an rtx
11434 (clobber (const_int 0)) is returned.
11435 An insn containing that will not be recognized. */
11438 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11440 machine_mode imode
= GET_MODE (x
);
11441 unsigned int osize
= GET_MODE_SIZE (omode
);
11442 unsigned int isize
= GET_MODE_SIZE (imode
);
11445 if (omode
== imode
)
11448 /* We can only support MODE being wider than a word if X is a
11449 constant integer or has a mode the same size. */
11450 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11451 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11454 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11455 won't know what to do. So we will strip off the SUBREG here and
11456 process normally. */
11457 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11459 x
= SUBREG_REG (x
);
11461 /* For use in case we fall down into the address adjustments
11462 further below, we need to adjust the known mode and size of
11463 x; imode and isize, since we just adjusted x. */
11464 imode
= GET_MODE (x
);
11466 if (imode
== omode
)
11469 isize
= GET_MODE_SIZE (imode
);
11472 result
= gen_lowpart_common (omode
, x
);
11481 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11483 if (MEM_VOLATILE_P (x
)
11484 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11487 /* If we want to refer to something bigger than the original memref,
11488 generate a paradoxical subreg instead. That will force a reload
11489 of the original memref X. */
11491 return gen_rtx_SUBREG (omode
, x
, 0);
11493 if (WORDS_BIG_ENDIAN
)
11494 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11496 /* Adjust the address so that the address-after-the-data is
11498 if (BYTES_BIG_ENDIAN
)
11499 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11501 return adjust_address_nv (x
, omode
, offset
);
11504 /* If X is a comparison operator, rewrite it in a new mode. This
11505 probably won't match, but may allow further simplifications. */
11506 else if (COMPARISON_P (x
))
11507 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11509 /* If we couldn't simplify X any other way, just enclose it in a
11510 SUBREG. Normally, this SUBREG won't match, but some patterns may
11511 include an explicit SUBREG or we may simplify it further in combine. */
11516 if (imode
== VOIDmode
)
11518 imode
= int_mode_for_mode (omode
);
11519 x
= gen_lowpart_common (imode
, x
);
11523 res
= lowpart_subreg (omode
, x
, imode
);
11529 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11532 /* Try to simplify a comparison between OP0 and a constant OP1,
11533 where CODE is the comparison code that will be tested, into a
11534 (CODE OP0 const0_rtx) form.
11536 The result is a possibly different comparison code to use.
11537 *POP1 may be updated. */
11539 static enum rtx_code
11540 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11541 rtx op0
, rtx
*pop1
)
11543 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11544 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11546 /* Get the constant we are comparing against and turn off all bits
11547 not on in our mode. */
11548 if (mode
!= VOIDmode
)
11549 const_op
= trunc_int_for_mode (const_op
, mode
);
11551 /* If we are comparing against a constant power of two and the value
11552 being compared can only have that single bit nonzero (e.g., it was
11553 `and'ed with that bit), we can replace this with a comparison
11556 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11557 || code
== LT
|| code
== LTU
)
11558 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11559 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11560 && (nonzero_bits (op0
, mode
)
11561 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11563 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11567 /* Similarly, if we are comparing a value known to be either -1 or
11568 0 with -1, change it to the opposite comparison against zero. */
11570 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11571 || code
== GEU
|| code
== LTU
)
11572 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11574 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11578 /* Do some canonicalizations based on the comparison code. We prefer
11579 comparisons against zero and then prefer equality comparisons.
11580 If we can reduce the size of a constant, we will do that too. */
11584 /* < C is equivalent to <= (C - 1) */
11589 /* ... fall through to LE case below. */
11590 gcc_fallthrough ();
11596 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11603 /* If we are doing a <= 0 comparison on a value known to have
11604 a zero sign bit, we can replace this with == 0. */
11605 else if (const_op
== 0
11606 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11607 && (nonzero_bits (op0
, mode
)
11608 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11614 /* >= C is equivalent to > (C - 1). */
11619 /* ... fall through to GT below. */
11620 gcc_fallthrough ();
11626 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11633 /* If we are doing a > 0 comparison on a value known to have
11634 a zero sign bit, we can replace this with != 0. */
11635 else if (const_op
== 0
11636 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11637 && (nonzero_bits (op0
, mode
)
11638 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11644 /* < C is equivalent to <= (C - 1). */
11649 /* ... fall through ... */
11651 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11652 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11653 && (unsigned HOST_WIDE_INT
) const_op
11654 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11664 /* unsigned <= 0 is equivalent to == 0 */
11667 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11668 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11669 && (unsigned HOST_WIDE_INT
) const_op
11670 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11678 /* >= C is equivalent to > (C - 1). */
11683 /* ... fall through ... */
11686 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11687 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11688 && (unsigned HOST_WIDE_INT
) const_op
11689 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11699 /* unsigned > 0 is equivalent to != 0 */
11702 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11703 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11704 && (unsigned HOST_WIDE_INT
) const_op
11705 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11716 *pop1
= GEN_INT (const_op
);
11720 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11721 comparison code that will be tested.
11723 The result is a possibly different comparison code to use. *POP0 and
11724 *POP1 may be updated.
11726 It is possible that we might detect that a comparison is either always
11727 true or always false. However, we do not perform general constant
11728 folding in combine, so this knowledge isn't useful. Such tautologies
11729 should have been detected earlier. Hence we ignore all such cases. */
11731 static enum rtx_code
11732 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11738 machine_mode mode
, tmode
;
11740 /* Try a few ways of applying the same transformation to both operands. */
11743 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11744 so check specially. */
11745 if (!WORD_REGISTER_OPERATIONS
11746 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11747 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11748 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11749 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11750 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11751 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11752 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11753 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11754 && CONST_INT_P (XEXP (op0
, 1))
11755 && XEXP (op0
, 1) == XEXP (op1
, 1)
11756 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11757 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11758 && (INTVAL (XEXP (op0
, 1))
11759 == (GET_MODE_PRECISION (GET_MODE (op0
))
11760 - (GET_MODE_PRECISION
11761 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11763 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11764 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11767 /* If both operands are the same constant shift, see if we can ignore the
11768 shift. We can if the shift is a rotate or if the bits shifted out of
11769 this shift are known to be zero for both inputs and if the type of
11770 comparison is compatible with the shift. */
11771 if (GET_CODE (op0
) == GET_CODE (op1
)
11772 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11773 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11774 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11775 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11776 || (GET_CODE (op0
) == ASHIFTRT
11777 && (code
!= GTU
&& code
!= LTU
11778 && code
!= GEU
&& code
!= LEU
)))
11779 && CONST_INT_P (XEXP (op0
, 1))
11780 && INTVAL (XEXP (op0
, 1)) >= 0
11781 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11782 && XEXP (op0
, 1) == XEXP (op1
, 1))
11784 machine_mode mode
= GET_MODE (op0
);
11785 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11786 int shift_count
= INTVAL (XEXP (op0
, 1));
11788 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11789 mask
&= (mask
>> shift_count
) << shift_count
;
11790 else if (GET_CODE (op0
) == ASHIFT
)
11791 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11793 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11794 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11795 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11800 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11801 SUBREGs are of the same mode, and, in both cases, the AND would
11802 be redundant if the comparison was done in the narrower mode,
11803 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11804 and the operand's possibly nonzero bits are 0xffffff01; in that case
11805 if we only care about QImode, we don't need the AND). This case
11806 occurs if the output mode of an scc insn is not SImode and
11807 STORE_FLAG_VALUE == 1 (e.g., the 386).
11809 Similarly, check for a case where the AND's are ZERO_EXTEND
11810 operations from some narrower mode even though a SUBREG is not
11813 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11814 && CONST_INT_P (XEXP (op0
, 1))
11815 && CONST_INT_P (XEXP (op1
, 1)))
11817 rtx inner_op0
= XEXP (op0
, 0);
11818 rtx inner_op1
= XEXP (op1
, 0);
11819 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11820 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11823 if (paradoxical_subreg_p (inner_op0
)
11824 && GET_CODE (inner_op1
) == SUBREG
11825 && (GET_MODE (SUBREG_REG (inner_op0
))
11826 == GET_MODE (SUBREG_REG (inner_op1
)))
11827 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11828 <= HOST_BITS_PER_WIDE_INT
)
11829 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11830 GET_MODE (SUBREG_REG (inner_op0
)))))
11831 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11832 GET_MODE (SUBREG_REG (inner_op1
))))))
11834 op0
= SUBREG_REG (inner_op0
);
11835 op1
= SUBREG_REG (inner_op1
);
11837 /* The resulting comparison is always unsigned since we masked
11838 off the original sign bit. */
11839 code
= unsigned_condition (code
);
11845 for (tmode
= GET_CLASS_NARROWEST_MODE
11846 (GET_MODE_CLASS (GET_MODE (op0
)));
11847 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11848 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11850 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11851 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11852 code
= unsigned_condition (code
);
11861 /* If both operands are NOT, we can strip off the outer operation
11862 and adjust the comparison code for swapped operands; similarly for
11863 NEG, except that this must be an equality comparison. */
11864 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11865 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11866 && (code
== EQ
|| code
== NE
)))
11867 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11873 /* If the first operand is a constant, swap the operands and adjust the
11874 comparison code appropriately, but don't do this if the second operand
11875 is already a constant integer. */
11876 if (swap_commutative_operands_p (op0
, op1
))
11878 std::swap (op0
, op1
);
11879 code
= swap_condition (code
);
11882 /* We now enter a loop during which we will try to simplify the comparison.
11883 For the most part, we only are concerned with comparisons with zero,
11884 but some things may really be comparisons with zero but not start
11885 out looking that way. */
11887 while (CONST_INT_P (op1
))
11889 machine_mode mode
= GET_MODE (op0
);
11890 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11891 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11892 int equality_comparison_p
;
11893 int sign_bit_comparison_p
;
11894 int unsigned_comparison_p
;
11895 HOST_WIDE_INT const_op
;
11897 /* We only want to handle integral modes. This catches VOIDmode,
11898 CCmode, and the floating-point modes. An exception is that we
11899 can handle VOIDmode if OP0 is a COMPARE or a comparison
11902 if (GET_MODE_CLASS (mode
) != MODE_INT
11903 && ! (mode
== VOIDmode
11904 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11907 /* Try to simplify the compare to constant, possibly changing the
11908 comparison op, and/or changing op1 to zero. */
11909 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11910 const_op
= INTVAL (op1
);
11912 /* Compute some predicates to simplify code below. */
11914 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11915 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11916 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11919 /* If this is a sign bit comparison and we can do arithmetic in
11920 MODE, say that we will only be needing the sign bit of OP0. */
11921 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11922 op0
= force_to_mode (op0
, mode
,
11924 << (GET_MODE_PRECISION (mode
) - 1),
11927 /* Now try cases based on the opcode of OP0. If none of the cases
11928 does a "continue", we exit this loop immediately after the
11931 switch (GET_CODE (op0
))
11934 /* If we are extracting a single bit from a variable position in
11935 a constant that has only a single bit set and are comparing it
11936 with zero, we can convert this into an equality comparison
11937 between the position and the location of the single bit. */
11938 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11939 have already reduced the shift count modulo the word size. */
11940 if (!SHIFT_COUNT_TRUNCATED
11941 && CONST_INT_P (XEXP (op0
, 0))
11942 && XEXP (op0
, 1) == const1_rtx
11943 && equality_comparison_p
&& const_op
== 0
11944 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11946 if (BITS_BIG_ENDIAN
)
11947 i
= BITS_PER_WORD
- 1 - i
;
11949 op0
= XEXP (op0
, 2);
11953 /* Result is nonzero iff shift count is equal to I. */
11954 code
= reverse_condition (code
);
11961 tem
= expand_compound_operation (op0
);
11970 /* If testing for equality, we can take the NOT of the constant. */
11971 if (equality_comparison_p
11972 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11974 op0
= XEXP (op0
, 0);
11979 /* If just looking at the sign bit, reverse the sense of the
11981 if (sign_bit_comparison_p
)
11983 op0
= XEXP (op0
, 0);
11984 code
= (code
== GE
? LT
: GE
);
11990 /* If testing for equality, we can take the NEG of the constant. */
11991 if (equality_comparison_p
11992 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11994 op0
= XEXP (op0
, 0);
11999 /* The remaining cases only apply to comparisons with zero. */
12003 /* When X is ABS or is known positive,
12004 (neg X) is < 0 if and only if X != 0. */
12006 if (sign_bit_comparison_p
12007 && (GET_CODE (XEXP (op0
, 0)) == ABS
12008 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12009 && (nonzero_bits (XEXP (op0
, 0), mode
)
12010 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12013 op0
= XEXP (op0
, 0);
12014 code
= (code
== LT
? NE
: EQ
);
12018 /* If we have NEG of something whose two high-order bits are the
12019 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12020 if (num_sign_bit_copies (op0
, mode
) >= 2)
12022 op0
= XEXP (op0
, 0);
12023 code
= swap_condition (code
);
12029 /* If we are testing equality and our count is a constant, we
12030 can perform the inverse operation on our RHS. */
12031 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12032 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12033 op1
, XEXP (op0
, 1))) != 0)
12035 op0
= XEXP (op0
, 0);
12040 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12041 a particular bit. Convert it to an AND of a constant of that
12042 bit. This will be converted into a ZERO_EXTRACT. */
12043 if (const_op
== 0 && sign_bit_comparison_p
12044 && CONST_INT_P (XEXP (op0
, 1))
12045 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12047 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12050 - INTVAL (XEXP (op0
, 1)))));
12051 code
= (code
== LT
? NE
: EQ
);
12055 /* Fall through. */
12058 /* ABS is ignorable inside an equality comparison with zero. */
12059 if (const_op
== 0 && equality_comparison_p
)
12061 op0
= XEXP (op0
, 0);
12067 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12068 (compare FOO CONST) if CONST fits in FOO's mode and we
12069 are either testing inequality or have an unsigned
12070 comparison with ZERO_EXTEND or a signed comparison with
12071 SIGN_EXTEND. But don't do it if we don't have a compare
12072 insn of the given mode, since we'd have to revert it
12073 later on, and then we wouldn't know whether to sign- or
12075 mode
= GET_MODE (XEXP (op0
, 0));
12076 if (GET_MODE_CLASS (mode
) == MODE_INT
12077 && ! unsigned_comparison_p
12078 && HWI_COMPUTABLE_MODE_P (mode
)
12079 && trunc_int_for_mode (const_op
, mode
) == const_op
12080 && have_insn_for (COMPARE
, mode
))
12082 op0
= XEXP (op0
, 0);
12088 /* Check for the case where we are comparing A - C1 with C2, that is
12090 (subreg:MODE (plus (A) (-C1))) op (C2)
12092 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12093 comparison in the wider mode. One of the following two conditions
12094 must be true in order for this to be valid:
12096 1. The mode extension results in the same bit pattern being added
12097 on both sides and the comparison is equality or unsigned. As
12098 C2 has been truncated to fit in MODE, the pattern can only be
12101 2. The mode extension results in the sign bit being copied on
12104 The difficulty here is that we have predicates for A but not for
12105 (A - C1) so we need to check that C1 is within proper bounds so
12106 as to perturbate A as little as possible. */
12108 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12109 && subreg_lowpart_p (op0
)
12110 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
12111 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12112 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12114 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
12115 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12116 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12119 && (unsigned HOST_WIDE_INT
) c1
12120 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12121 && (equality_comparison_p
|| unsigned_comparison_p
)
12122 /* (A - C1) zero-extends if it is positive and sign-extends
12123 if it is negative, C2 both zero- and sign-extends. */
12124 && ((0 == (nonzero_bits (a
, inner_mode
)
12125 & ~GET_MODE_MASK (mode
))
12127 /* (A - C1) sign-extends if it is positive and 1-extends
12128 if it is negative, C2 both sign- and 1-extends. */
12129 || (num_sign_bit_copies (a
, inner_mode
)
12130 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12133 || ((unsigned HOST_WIDE_INT
) c1
12134 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12135 /* (A - C1) always sign-extends, like C2. */
12136 && num_sign_bit_copies (a
, inner_mode
)
12137 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12138 - (mode_width
- 1))))
12140 op0
= SUBREG_REG (op0
);
12145 /* If the inner mode is narrower and we are extracting the low part,
12146 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12147 if (subreg_lowpart_p (op0
)
12148 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
12150 else if (subreg_lowpart_p (op0
)
12151 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12152 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12153 && (code
== NE
|| code
== EQ
)
12154 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12155 <= HOST_BITS_PER_WIDE_INT
)
12156 && !paradoxical_subreg_p (op0
)
12157 && (nonzero_bits (SUBREG_REG (op0
),
12158 GET_MODE (SUBREG_REG (op0
)))
12159 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12161 /* Remove outer subregs that don't do anything. */
12162 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12164 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12165 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12167 op0
= SUBREG_REG (op0
);
12179 mode
= GET_MODE (XEXP (op0
, 0));
12180 if (GET_MODE_CLASS (mode
) == MODE_INT
12181 && (unsigned_comparison_p
|| equality_comparison_p
)
12182 && HWI_COMPUTABLE_MODE_P (mode
)
12183 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12185 && have_insn_for (COMPARE
, mode
))
12187 op0
= XEXP (op0
, 0);
12193 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12194 this for equality comparisons due to pathological cases involving
12196 if (equality_comparison_p
12197 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12198 op1
, XEXP (op0
, 1))))
12200 op0
= XEXP (op0
, 0);
12205 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12206 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12207 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12209 op0
= XEXP (XEXP (op0
, 0), 0);
12210 code
= (code
== LT
? EQ
: NE
);
12216 /* We used to optimize signed comparisons against zero, but that
12217 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12218 arrive here as equality comparisons, or (GEU, LTU) are
12219 optimized away. No need to special-case them. */
12221 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12222 (eq B (minus A C)), whichever simplifies. We can only do
12223 this for equality comparisons due to pathological cases involving
12225 if (equality_comparison_p
12226 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12227 XEXP (op0
, 1), op1
)))
12229 op0
= XEXP (op0
, 0);
12234 if (equality_comparison_p
12235 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12236 XEXP (op0
, 0), op1
)))
12238 op0
= XEXP (op0
, 1);
12243 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12244 of bits in X minus 1, is one iff X > 0. */
12245 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12246 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12247 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12248 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12250 op0
= XEXP (op0
, 1);
12251 code
= (code
== GE
? LE
: GT
);
12257 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12258 if C is zero or B is a constant. */
12259 if (equality_comparison_p
12260 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12261 XEXP (op0
, 1), op1
)))
12263 op0
= XEXP (op0
, 0);
12270 case UNEQ
: case LTGT
:
12271 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12272 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12273 case UNORDERED
: case ORDERED
:
12274 /* We can't do anything if OP0 is a condition code value, rather
12275 than an actual data value. */
12277 || CC0_P (XEXP (op0
, 0))
12278 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12281 /* Get the two operands being compared. */
12282 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12283 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12285 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12287 /* Check for the cases where we simply want the result of the
12288 earlier test or the opposite of that result. */
12289 if (code
== NE
|| code
== EQ
12290 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12291 && (code
== LT
|| code
== GE
)))
12293 enum rtx_code new_code
;
12294 if (code
== LT
|| code
== NE
)
12295 new_code
= GET_CODE (op0
);
12297 new_code
= reversed_comparison_code (op0
, NULL
);
12299 if (new_code
!= UNKNOWN
)
12310 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12312 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12313 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12314 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12316 op0
= XEXP (op0
, 1);
12317 code
= (code
== GE
? GT
: LE
);
12323 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12324 will be converted to a ZERO_EXTRACT later. */
12325 if (const_op
== 0 && equality_comparison_p
12326 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12327 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12329 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12330 XEXP (XEXP (op0
, 0), 1));
12331 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12335 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12336 zero and X is a comparison and C1 and C2 describe only bits set
12337 in STORE_FLAG_VALUE, we can compare with X. */
12338 if (const_op
== 0 && equality_comparison_p
12339 && mode_width
<= HOST_BITS_PER_WIDE_INT
12340 && CONST_INT_P (XEXP (op0
, 1))
12341 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12342 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12343 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12344 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12346 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12347 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12348 if ((~STORE_FLAG_VALUE
& mask
) == 0
12349 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12350 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12351 && COMPARISON_P (tem
))))
12353 op0
= XEXP (XEXP (op0
, 0), 0);
12358 /* If we are doing an equality comparison of an AND of a bit equal
12359 to the sign bit, replace this with a LT or GE comparison of
12360 the underlying value. */
12361 if (equality_comparison_p
12363 && CONST_INT_P (XEXP (op0
, 1))
12364 && mode_width
<= HOST_BITS_PER_WIDE_INT
12365 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12366 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12368 op0
= XEXP (op0
, 0);
12369 code
= (code
== EQ
? GE
: LT
);
12373 /* If this AND operation is really a ZERO_EXTEND from a narrower
12374 mode, the constant fits within that mode, and this is either an
12375 equality or unsigned comparison, try to do this comparison in
12380 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12381 -> (ne:DI (reg:SI 4) (const_int 0))
12383 unless TRULY_NOOP_TRUNCATION allows it or the register is
12384 known to hold a value of the required mode the
12385 transformation is invalid. */
12386 if ((equality_comparison_p
|| unsigned_comparison_p
)
12387 && CONST_INT_P (XEXP (op0
, 1))
12388 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12389 & GET_MODE_MASK (mode
))
12391 && const_op
>> i
== 0
12392 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12394 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12398 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12399 fits in both M1 and M2 and the SUBREG is either paradoxical
12400 or represents the low part, permute the SUBREG and the AND
12402 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12403 && CONST_INT_P (XEXP (op0
, 1)))
12405 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12406 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12407 /* Require an integral mode, to avoid creating something like
12409 if (SCALAR_INT_MODE_P (tmode
)
12410 /* It is unsafe to commute the AND into the SUBREG if the
12411 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12412 not defined. As originally written the upper bits
12413 have a defined value due to the AND operation.
12414 However, if we commute the AND inside the SUBREG then
12415 they no longer have defined values and the meaning of
12416 the code has been changed.
12417 Also C1 should not change value in the smaller mode,
12418 see PR67028 (a positive C1 can become negative in the
12419 smaller mode, so that the AND does no longer mask the
12421 && ((WORD_REGISTER_OPERATIONS
12422 && mode_width
> GET_MODE_PRECISION (tmode
)
12423 && mode_width
<= BITS_PER_WORD
12424 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12425 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12426 && subreg_lowpart_p (XEXP (op0
, 0))))
12427 && mode_width
<= HOST_BITS_PER_WIDE_INT
12428 && HWI_COMPUTABLE_MODE_P (tmode
)
12429 && (c1
& ~mask
) == 0
12430 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12432 && c1
!= GET_MODE_MASK (tmode
))
12434 op0
= simplify_gen_binary (AND
, tmode
,
12435 SUBREG_REG (XEXP (op0
, 0)),
12436 gen_int_mode (c1
, tmode
));
12437 op0
= gen_lowpart (mode
, op0
);
12442 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12443 if (const_op
== 0 && equality_comparison_p
12444 && XEXP (op0
, 1) == const1_rtx
12445 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12447 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12448 XEXP (XEXP (op0
, 0), 0), 1);
12449 code
= (code
== NE
? EQ
: NE
);
12453 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12454 (eq (and (lshiftrt X) 1) 0).
12455 Also handle the case where (not X) is expressed using xor. */
12456 if (const_op
== 0 && equality_comparison_p
12457 && XEXP (op0
, 1) == const1_rtx
12458 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12460 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12461 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12463 if (GET_CODE (shift_op
) == NOT
12464 || (GET_CODE (shift_op
) == XOR
12465 && CONST_INT_P (XEXP (shift_op
, 1))
12466 && CONST_INT_P (shift_count
)
12467 && HWI_COMPUTABLE_MODE_P (mode
)
12468 && (UINTVAL (XEXP (shift_op
, 1))
12469 == HOST_WIDE_INT_1U
12470 << INTVAL (shift_count
))))
12473 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12474 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12475 code
= (code
== NE
? EQ
: NE
);
12482 /* If we have (compare (ashift FOO N) (const_int C)) and
12483 the high order N bits of FOO (N+1 if an inequality comparison)
12484 are known to be zero, we can do this by comparing FOO with C
12485 shifted right N bits so long as the low-order N bits of C are
12487 if (CONST_INT_P (XEXP (op0
, 1))
12488 && INTVAL (XEXP (op0
, 1)) >= 0
12489 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12490 < HOST_BITS_PER_WIDE_INT
)
12491 && (((unsigned HOST_WIDE_INT
) const_op
12492 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12494 && mode_width
<= HOST_BITS_PER_WIDE_INT
12495 && (nonzero_bits (XEXP (op0
, 0), mode
)
12496 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12497 + ! equality_comparison_p
))) == 0)
12499 /* We must perform a logical shift, not an arithmetic one,
12500 as we want the top N bits of C to be zero. */
12501 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12503 temp
>>= INTVAL (XEXP (op0
, 1));
12504 op1
= gen_int_mode (temp
, mode
);
12505 op0
= XEXP (op0
, 0);
12509 /* If we are doing a sign bit comparison, it means we are testing
12510 a particular bit. Convert it to the appropriate AND. */
12511 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12512 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12514 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12517 - INTVAL (XEXP (op0
, 1)))));
12518 code
= (code
== LT
? NE
: EQ
);
12522 /* If this an equality comparison with zero and we are shifting
12523 the low bit to the sign bit, we can convert this to an AND of the
12525 if (const_op
== 0 && equality_comparison_p
12526 && CONST_INT_P (XEXP (op0
, 1))
12527 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12529 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12535 /* If this is an equality comparison with zero, we can do this
12536 as a logical shift, which might be much simpler. */
12537 if (equality_comparison_p
&& const_op
== 0
12538 && CONST_INT_P (XEXP (op0
, 1)))
12540 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12542 INTVAL (XEXP (op0
, 1)));
12546 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12547 do the comparison in a narrower mode. */
12548 if (! unsigned_comparison_p
12549 && CONST_INT_P (XEXP (op0
, 1))
12550 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12551 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12552 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12553 MODE_INT
, 1)) != BLKmode
12554 && (((unsigned HOST_WIDE_INT
) const_op
12555 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12556 <= GET_MODE_MASK (tmode
)))
12558 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12562 /* Likewise if OP0 is a PLUS of a sign extension with a
12563 constant, which is usually represented with the PLUS
12564 between the shifts. */
12565 if (! unsigned_comparison_p
12566 && CONST_INT_P (XEXP (op0
, 1))
12567 && GET_CODE (XEXP (op0
, 0)) == PLUS
12568 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12569 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12570 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12571 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12572 MODE_INT
, 1)) != BLKmode
12573 && (((unsigned HOST_WIDE_INT
) const_op
12574 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12575 <= GET_MODE_MASK (tmode
)))
12577 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12578 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12579 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12580 add_const
, XEXP (op0
, 1));
12582 op0
= simplify_gen_binary (PLUS
, tmode
,
12583 gen_lowpart (tmode
, inner
),
12590 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12591 the low order N bits of FOO are known to be zero, we can do this
12592 by comparing FOO with C shifted left N bits so long as no
12593 overflow occurs. Even if the low order N bits of FOO aren't known
12594 to be zero, if the comparison is >= or < we can use the same
12595 optimization and for > or <= by setting all the low
12596 order N bits in the comparison constant. */
12597 if (CONST_INT_P (XEXP (op0
, 1))
12598 && INTVAL (XEXP (op0
, 1)) > 0
12599 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12600 && mode_width
<= HOST_BITS_PER_WIDE_INT
12601 && (((unsigned HOST_WIDE_INT
) const_op
12602 + (GET_CODE (op0
) != LSHIFTRT
12603 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12606 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12608 unsigned HOST_WIDE_INT low_bits
12609 = (nonzero_bits (XEXP (op0
, 0), mode
)
12610 & ((HOST_WIDE_INT_1U
12611 << INTVAL (XEXP (op0
, 1))) - 1));
12612 if (low_bits
== 0 || !equality_comparison_p
)
12614 /* If the shift was logical, then we must make the condition
12616 if (GET_CODE (op0
) == LSHIFTRT
)
12617 code
= unsigned_condition (code
);
12619 const_op
= (unsigned HOST_WIDE_INT
) const_op
12620 << INTVAL (XEXP (op0
, 1));
12622 && (code
== GT
|| code
== GTU
12623 || code
== LE
|| code
== LEU
))
12625 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12626 op1
= GEN_INT (const_op
);
12627 op0
= XEXP (op0
, 0);
12632 /* If we are using this shift to extract just the sign bit, we
12633 can replace this with an LT or GE comparison. */
12635 && (equality_comparison_p
|| sign_bit_comparison_p
)
12636 && CONST_INT_P (XEXP (op0
, 1))
12637 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12639 op0
= XEXP (op0
, 0);
12640 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12652 /* Now make any compound operations involved in this comparison. Then,
12653 check for an outmost SUBREG on OP0 that is not doing anything or is
12654 paradoxical. The latter transformation must only be performed when
12655 it is known that the "extra" bits will be the same in op0 and op1 or
12656 that they don't matter. There are three cases to consider:
12658 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12659 care bits and we can assume they have any convenient value. So
12660 making the transformation is safe.
12662 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12663 In this case the upper bits of op0 are undefined. We should not make
12664 the simplification in that case as we do not know the contents of
12667 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12668 In that case we know those bits are zeros or ones. We must also be
12669 sure that they are the same as the upper bits of op1.
12671 We can never remove a SUBREG for a non-equality comparison because
12672 the sign bit is in a different place in the underlying object. */
12674 rtx_code op0_mco_code
= SET
;
12675 if (op1
== const0_rtx
)
12676 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12678 op0
= make_compound_operation (op0
, op0_mco_code
);
12679 op1
= make_compound_operation (op1
, SET
);
12681 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12682 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12683 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12684 && (code
== NE
|| code
== EQ
))
12686 if (paradoxical_subreg_p (op0
))
12688 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12690 if (REG_P (SUBREG_REG (op0
)))
12692 op0
= SUBREG_REG (op0
);
12693 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12696 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12697 <= HOST_BITS_PER_WIDE_INT
)
12698 && (nonzero_bits (SUBREG_REG (op0
),
12699 GET_MODE (SUBREG_REG (op0
)))
12700 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12702 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12704 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12705 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12706 op0
= SUBREG_REG (op0
), op1
= tem
;
12710 /* We now do the opposite procedure: Some machines don't have compare
12711 insns in all modes. If OP0's mode is an integer mode smaller than a
12712 word and we can't do a compare in that mode, see if there is a larger
12713 mode for which we can do the compare. There are a number of cases in
12714 which we can use the wider mode. */
12716 mode
= GET_MODE (op0
);
12717 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12718 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12719 && ! have_insn_for (COMPARE
, mode
))
12720 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12721 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12722 tmode
= GET_MODE_WIDER_MODE (tmode
))
12723 if (have_insn_for (COMPARE
, tmode
))
12727 /* If this is a test for negative, we can make an explicit
12728 test of the sign bit. Test this first so we can use
12729 a paradoxical subreg to extend OP0. */
12731 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12732 && HWI_COMPUTABLE_MODE_P (mode
))
12734 unsigned HOST_WIDE_INT sign
12735 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12736 op0
= simplify_gen_binary (AND
, tmode
,
12737 gen_lowpart (tmode
, op0
),
12738 gen_int_mode (sign
, tmode
));
12739 code
= (code
== LT
) ? NE
: EQ
;
12743 /* If the only nonzero bits in OP0 and OP1 are those in the
12744 narrower mode and this is an equality or unsigned comparison,
12745 we can use the wider mode. Similarly for sign-extended
12746 values, in which case it is true for all comparisons. */
12747 zero_extended
= ((code
== EQ
|| code
== NE
12748 || code
== GEU
|| code
== GTU
12749 || code
== LEU
|| code
== LTU
)
12750 && (nonzero_bits (op0
, tmode
)
12751 & ~GET_MODE_MASK (mode
)) == 0
12752 && ((CONST_INT_P (op1
)
12753 || (nonzero_bits (op1
, tmode
)
12754 & ~GET_MODE_MASK (mode
)) == 0)));
12757 || ((num_sign_bit_copies (op0
, tmode
)
12758 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12759 - GET_MODE_PRECISION (mode
)))
12760 && (num_sign_bit_copies (op1
, tmode
)
12761 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12762 - GET_MODE_PRECISION (mode
)))))
12764 /* If OP0 is an AND and we don't have an AND in MODE either,
12765 make a new AND in the proper mode. */
12766 if (GET_CODE (op0
) == AND
12767 && !have_insn_for (AND
, mode
))
12768 op0
= simplify_gen_binary (AND
, tmode
,
12769 gen_lowpart (tmode
,
12771 gen_lowpart (tmode
,
12777 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12778 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12782 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12783 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12790 /* We may have changed the comparison operands. Re-canonicalize. */
12791 if (swap_commutative_operands_p (op0
, op1
))
12793 std::swap (op0
, op1
);
12794 code
= swap_condition (code
);
12797 /* If this machine only supports a subset of valid comparisons, see if we
12798 can convert an unsupported one into a supported one. */
12799 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12807 /* Utility function for record_value_for_reg. Count number of
12812 enum rtx_code code
= GET_CODE (x
);
12816 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12817 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12819 rtx x0
= XEXP (x
, 0);
12820 rtx x1
= XEXP (x
, 1);
12823 return 1 + 2 * count_rtxs (x0
);
12825 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12826 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12827 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12828 return 2 + 2 * count_rtxs (x0
)
12829 + count_rtxs (x
== XEXP (x1
, 0)
12830 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12832 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12833 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12834 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12835 return 2 + 2 * count_rtxs (x1
)
12836 + count_rtxs (x
== XEXP (x0
, 0)
12837 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12840 fmt
= GET_RTX_FORMAT (code
);
12841 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12843 ret
+= count_rtxs (XEXP (x
, i
));
12844 else if (fmt
[i
] == 'E')
12845 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12846 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12851 /* Utility function for following routine. Called when X is part of a value
12852 being stored into last_set_value. Sets last_set_table_tick
12853 for each register mentioned. Similar to mention_regs in cse.c */
12856 update_table_tick (rtx x
)
12858 enum rtx_code code
= GET_CODE (x
);
12859 const char *fmt
= GET_RTX_FORMAT (code
);
12864 unsigned int regno
= REGNO (x
);
12865 unsigned int endregno
= END_REGNO (x
);
12868 for (r
= regno
; r
< endregno
; r
++)
12870 reg_stat_type
*rsp
= ®_stat
[r
];
12871 rsp
->last_set_table_tick
= label_tick
;
12877 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12880 /* Check for identical subexpressions. If x contains
12881 identical subexpression we only have to traverse one of
12883 if (i
== 0 && ARITHMETIC_P (x
))
12885 /* Note that at this point x1 has already been
12887 rtx x0
= XEXP (x
, 0);
12888 rtx x1
= XEXP (x
, 1);
12890 /* If x0 and x1 are identical then there is no need to
12895 /* If x0 is identical to a subexpression of x1 then while
12896 processing x1, x0 has already been processed. Thus we
12897 are done with x. */
12898 if (ARITHMETIC_P (x1
)
12899 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12902 /* If x1 is identical to a subexpression of x0 then we
12903 still have to process the rest of x0. */
12904 if (ARITHMETIC_P (x0
)
12905 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12907 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12912 update_table_tick (XEXP (x
, i
));
12914 else if (fmt
[i
] == 'E')
12915 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12916 update_table_tick (XVECEXP (x
, i
, j
));
12919 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12920 are saying that the register is clobbered and we no longer know its
12921 value. If INSN is zero, don't update reg_stat[].last_set; this is
12922 only permitted with VALUE also zero and is used to invalidate the
12926 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12928 unsigned int regno
= REGNO (reg
);
12929 unsigned int endregno
= END_REGNO (reg
);
12931 reg_stat_type
*rsp
;
12933 /* If VALUE contains REG and we have a previous value for REG, substitute
12934 the previous value. */
12935 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12939 /* Set things up so get_last_value is allowed to see anything set up to
12941 subst_low_luid
= DF_INSN_LUID (insn
);
12942 tem
= get_last_value (reg
);
12944 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12945 it isn't going to be useful and will take a lot of time to process,
12946 so just use the CLOBBER. */
12950 if (ARITHMETIC_P (tem
)
12951 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12952 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12953 tem
= XEXP (tem
, 0);
12954 else if (count_occurrences (value
, reg
, 1) >= 2)
12956 /* If there are two or more occurrences of REG in VALUE,
12957 prevent the value from growing too much. */
12958 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12959 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12962 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12966 /* For each register modified, show we don't know its value, that
12967 we don't know about its bitwise content, that its value has been
12968 updated, and that we don't know the location of the death of the
12970 for (i
= regno
; i
< endregno
; i
++)
12972 rsp
= ®_stat
[i
];
12975 rsp
->last_set
= insn
;
12977 rsp
->last_set_value
= 0;
12978 rsp
->last_set_mode
= VOIDmode
;
12979 rsp
->last_set_nonzero_bits
= 0;
12980 rsp
->last_set_sign_bit_copies
= 0;
12981 rsp
->last_death
= 0;
12982 rsp
->truncated_to_mode
= VOIDmode
;
12985 /* Mark registers that are being referenced in this value. */
12987 update_table_tick (value
);
12989 /* Now update the status of each register being set.
12990 If someone is using this register in this block, set this register
12991 to invalid since we will get confused between the two lives in this
12992 basic block. This makes using this register always invalid. In cse, we
12993 scan the table to invalidate all entries using this register, but this
12994 is too much work for us. */
12996 for (i
= regno
; i
< endregno
; i
++)
12998 rsp
= ®_stat
[i
];
12999 rsp
->last_set_label
= label_tick
;
13001 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13002 rsp
->last_set_invalid
= 1;
13004 rsp
->last_set_invalid
= 0;
13007 /* The value being assigned might refer to X (like in "x++;"). In that
13008 case, we must replace it with (clobber (const_int 0)) to prevent
13010 rsp
= ®_stat
[regno
];
13011 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13013 value
= copy_rtx (value
);
13014 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13018 /* For the main register being modified, update the value, the mode, the
13019 nonzero bits, and the number of sign bit copies. */
13021 rsp
->last_set_value
= value
;
13025 machine_mode mode
= GET_MODE (reg
);
13026 subst_low_luid
= DF_INSN_LUID (insn
);
13027 rsp
->last_set_mode
= mode
;
13028 if (GET_MODE_CLASS (mode
) == MODE_INT
13029 && HWI_COMPUTABLE_MODE_P (mode
))
13030 mode
= nonzero_bits_mode
;
13031 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13032 rsp
->last_set_sign_bit_copies
13033 = num_sign_bit_copies (value
, GET_MODE (reg
));
13037 /* Called via note_stores from record_dead_and_set_regs to handle one
13038 SET or CLOBBER in an insn. DATA is the instruction in which the
13039 set is occurring. */
13042 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13044 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13046 if (GET_CODE (dest
) == SUBREG
)
13047 dest
= SUBREG_REG (dest
);
13049 if (!record_dead_insn
)
13052 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13058 /* If we are setting the whole register, we know its value. Otherwise
13059 show that we don't know the value. We can handle SUBREG in
13061 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13062 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13063 else if (GET_CODE (setter
) == SET
13064 && GET_CODE (SET_DEST (setter
)) == SUBREG
13065 && SUBREG_REG (SET_DEST (setter
)) == dest
13066 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13067 && subreg_lowpart_p (SET_DEST (setter
)))
13068 record_value_for_reg (dest
, record_dead_insn
,
13069 gen_lowpart (GET_MODE (dest
),
13070 SET_SRC (setter
)));
13072 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13074 else if (MEM_P (dest
)
13075 /* Ignore pushes, they clobber nothing. */
13076 && ! push_operand (dest
, GET_MODE (dest
)))
13077 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13080 /* Update the records of when each REG was most recently set or killed
13081 for the things done by INSN. This is the last thing done in processing
13082 INSN in the combiner loop.
13084 We update reg_stat[], in particular fields last_set, last_set_value,
13085 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13086 last_death, and also the similar information mem_last_set (which insn
13087 most recently modified memory) and last_call_luid (which insn was the
13088 most recent subroutine call). */
13091 record_dead_and_set_regs (rtx_insn
*insn
)
13096 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13098 if (REG_NOTE_KIND (link
) == REG_DEAD
13099 && REG_P (XEXP (link
, 0)))
13101 unsigned int regno
= REGNO (XEXP (link
, 0));
13102 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13104 for (i
= regno
; i
< endregno
; i
++)
13106 reg_stat_type
*rsp
;
13108 rsp
= ®_stat
[i
];
13109 rsp
->last_death
= insn
;
13112 else if (REG_NOTE_KIND (link
) == REG_INC
)
13113 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13118 hard_reg_set_iterator hrsi
;
13119 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13121 reg_stat_type
*rsp
;
13123 rsp
= ®_stat
[i
];
13124 rsp
->last_set_invalid
= 1;
13125 rsp
->last_set
= insn
;
13126 rsp
->last_set_value
= 0;
13127 rsp
->last_set_mode
= VOIDmode
;
13128 rsp
->last_set_nonzero_bits
= 0;
13129 rsp
->last_set_sign_bit_copies
= 0;
13130 rsp
->last_death
= 0;
13131 rsp
->truncated_to_mode
= VOIDmode
;
13134 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13136 /* We can't combine into a call pattern. Remember, though, that
13137 the return value register is set at this LUID. We could
13138 still replace a register with the return value from the
13139 wrong subroutine call! */
13140 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13143 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13146 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13147 register present in the SUBREG, so for each such SUBREG go back and
13148 adjust nonzero and sign bit information of the registers that are
13149 known to have some zero/sign bits set.
13151 This is needed because when combine blows the SUBREGs away, the
13152 information on zero/sign bits is lost and further combines can be
13153 missed because of that. */
13156 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13158 struct insn_link
*links
;
13160 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13161 machine_mode mode
= GET_MODE (subreg
);
13163 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
13166 for (links
= LOG_LINKS (insn
); links
;)
13168 reg_stat_type
*rsp
;
13170 insn
= links
->insn
;
13171 set
= single_set (insn
);
13173 if (! set
|| !REG_P (SET_DEST (set
))
13174 || REGNO (SET_DEST (set
)) != regno
13175 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13177 links
= links
->next
;
13181 rsp
= ®_stat
[regno
];
13182 if (rsp
->last_set
== insn
)
13184 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13185 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13188 if (REG_P (SET_SRC (set
)))
13190 regno
= REGNO (SET_SRC (set
));
13191 links
= LOG_LINKS (insn
);
13198 /* Check if X, a register, is known to contain a value already
13199 truncated to MODE. In this case we can use a subreg to refer to
13200 the truncated value even though in the generic case we would need
13201 an explicit truncation. */
13204 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13206 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13207 machine_mode truncated
= rsp
->truncated_to_mode
;
13210 || rsp
->truncation_label
< label_tick_ebb_start
)
13212 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
13214 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13219 /* If X is a hard reg or a subreg record the mode that the register is
13220 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13221 to turn a truncate into a subreg using this information. Return true
13222 if traversing X is complete. */
13225 record_truncated_value (rtx x
)
13227 machine_mode truncated_mode
;
13228 reg_stat_type
*rsp
;
13230 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13232 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13233 truncated_mode
= GET_MODE (x
);
13235 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
13238 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13241 x
= SUBREG_REG (x
);
13243 /* ??? For hard-regs we now record everything. We might be able to
13244 optimize this using last_set_mode. */
13245 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13246 truncated_mode
= GET_MODE (x
);
13250 rsp
= ®_stat
[REGNO (x
)];
13251 if (rsp
->truncated_to_mode
== 0
13252 || rsp
->truncation_label
< label_tick_ebb_start
13253 || (GET_MODE_SIZE (truncated_mode
)
13254 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13256 rsp
->truncated_to_mode
= truncated_mode
;
13257 rsp
->truncation_label
= label_tick
;
13263 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13264 the modes they are used in. This can help truning TRUNCATEs into
13268 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13270 subrtx_var_iterator::array_type array
;
13271 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13272 if (record_truncated_value (*iter
))
13273 iter
.skip_subrtxes ();
13276 /* Scan X for promoted SUBREGs. For each one found,
13277 note what it implies to the registers used in it. */
13280 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13282 if (GET_CODE (x
) == SUBREG
13283 && SUBREG_PROMOTED_VAR_P (x
)
13284 && REG_P (SUBREG_REG (x
)))
13285 record_promoted_value (insn
, x
);
13288 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13291 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13295 check_promoted_subreg (insn
, XEXP (x
, i
));
13299 if (XVEC (x
, i
) != 0)
13300 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13301 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13307 /* Verify that all the registers and memory references mentioned in *LOC are
13308 still valid. *LOC was part of a value set in INSN when label_tick was
13309 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13310 the invalid references with (clobber (const_int 0)) and return 1. This
13311 replacement is useful because we often can get useful information about
13312 the form of a value (e.g., if it was produced by a shift that always
13313 produces -1 or 0) even though we don't know exactly what registers it
13314 was produced from. */
13317 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13320 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13321 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13326 unsigned int regno
= REGNO (x
);
13327 unsigned int endregno
= END_REGNO (x
);
13330 for (j
= regno
; j
< endregno
; j
++)
13332 reg_stat_type
*rsp
= ®_stat
[j
];
13333 if (rsp
->last_set_invalid
13334 /* If this is a pseudo-register that was only set once and not
13335 live at the beginning of the function, it is always valid. */
13336 || (! (regno
>= FIRST_PSEUDO_REGISTER
13337 && regno
< reg_n_sets_max
13338 && REG_N_SETS (regno
) == 1
13339 && (!REGNO_REG_SET_P
13340 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13342 && rsp
->last_set_label
> tick
))
13345 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13352 /* If this is a memory reference, make sure that there were no stores after
13353 it that might have clobbered the value. We don't have alias info, so we
13354 assume any store invalidates it. Moreover, we only have local UIDs, so
13355 we also assume that there were stores in the intervening basic blocks. */
13356 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13357 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13360 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13364 for (i
= 0; i
< len
; i
++)
13368 /* Check for identical subexpressions. If x contains
13369 identical subexpression we only have to traverse one of
13371 if (i
== 1 && ARITHMETIC_P (x
))
13373 /* Note that at this point x0 has already been checked
13374 and found valid. */
13375 rtx x0
= XEXP (x
, 0);
13376 rtx x1
= XEXP (x
, 1);
13378 /* If x0 and x1 are identical then x is also valid. */
13382 /* If x1 is identical to a subexpression of x0 then
13383 while checking x0, x1 has already been checked. Thus
13384 it is valid and so as x. */
13385 if (ARITHMETIC_P (x0
)
13386 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13389 /* If x0 is identical to a subexpression of x1 then x is
13390 valid iff the rest of x1 is valid. */
13391 if (ARITHMETIC_P (x1
)
13392 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13394 get_last_value_validate (&XEXP (x1
,
13395 x0
== XEXP (x1
, 0) ? 1 : 0),
13396 insn
, tick
, replace
);
13399 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13403 else if (fmt
[i
] == 'E')
13404 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13405 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13406 insn
, tick
, replace
) == 0)
13410 /* If we haven't found a reason for it to be invalid, it is valid. */
13414 /* Get the last value assigned to X, if known. Some registers
13415 in the value may be replaced with (clobber (const_int 0)) if their value
13416 is known longer known reliably. */
13419 get_last_value (const_rtx x
)
13421 unsigned int regno
;
13423 reg_stat_type
*rsp
;
13425 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13426 then convert it to the desired mode. If this is a paradoxical SUBREG,
13427 we cannot predict what values the "extra" bits might have. */
13428 if (GET_CODE (x
) == SUBREG
13429 && subreg_lowpart_p (x
)
13430 && !paradoxical_subreg_p (x
)
13431 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13432 return gen_lowpart (GET_MODE (x
), value
);
13438 rsp
= ®_stat
[regno
];
13439 value
= rsp
->last_set_value
;
13441 /* If we don't have a value, or if it isn't for this basic block and
13442 it's either a hard register, set more than once, or it's a live
13443 at the beginning of the function, return 0.
13445 Because if it's not live at the beginning of the function then the reg
13446 is always set before being used (is never used without being set).
13447 And, if it's set only once, and it's always set before use, then all
13448 uses must have the same last value, even if it's not from this basic
13452 || (rsp
->last_set_label
< label_tick_ebb_start
13453 && (regno
< FIRST_PSEUDO_REGISTER
13454 || regno
>= reg_n_sets_max
13455 || REG_N_SETS (regno
) != 1
13457 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13460 /* If the value was set in a later insn than the ones we are processing,
13461 we can't use it even if the register was only set once. */
13462 if (rsp
->last_set_label
== label_tick
13463 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13466 /* If fewer bits were set than what we are asked for now, we cannot use
13468 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13469 < GET_MODE_PRECISION (GET_MODE (x
)))
13472 /* If the value has all its registers valid, return it. */
13473 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13476 /* Otherwise, make a copy and replace any invalid register with
13477 (clobber (const_int 0)). If that fails for some reason, return 0. */
13479 value
= copy_rtx (value
);
13480 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13486 /* Return nonzero if expression X refers to a REG or to memory
13487 that is set in an instruction more recent than FROM_LUID. */
13490 use_crosses_set_p (const_rtx x
, int from_luid
)
13494 enum rtx_code code
= GET_CODE (x
);
13498 unsigned int regno
= REGNO (x
);
13499 unsigned endreg
= END_REGNO (x
);
13501 #ifdef PUSH_ROUNDING
13502 /* Don't allow uses of the stack pointer to be moved,
13503 because we don't know whether the move crosses a push insn. */
13504 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13507 for (; regno
< endreg
; regno
++)
13509 reg_stat_type
*rsp
= ®_stat
[regno
];
13511 && rsp
->last_set_label
== label_tick
13512 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13518 if (code
== MEM
&& mem_last_set
> from_luid
)
13521 fmt
= GET_RTX_FORMAT (code
);
13523 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13528 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13529 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13532 else if (fmt
[i
] == 'e'
13533 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13539 /* Define three variables used for communication between the following
13542 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13543 static int reg_dead_flag
;
13545 /* Function called via note_stores from reg_dead_at_p.
13547 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13548 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13551 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13553 unsigned int regno
, endregno
;
13558 regno
= REGNO (dest
);
13559 endregno
= END_REGNO (dest
);
13560 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13561 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13564 /* Return nonzero if REG is known to be dead at INSN.
13566 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13567 referencing REG, it is dead. If we hit a SET referencing REG, it is
13568 live. Otherwise, see if it is live or dead at the start of the basic
13569 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13570 must be assumed to be always live. */
13573 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13578 /* Set variables for reg_dead_at_p_1. */
13579 reg_dead_regno
= REGNO (reg
);
13580 reg_dead_endregno
= END_REGNO (reg
);
13584 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13585 we allow the machine description to decide whether use-and-clobber
13586 patterns are OK. */
13587 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13589 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13590 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13594 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13595 beginning of basic block. */
13596 block
= BLOCK_FOR_INSN (insn
);
13601 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13604 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13606 return reg_dead_flag
== 1 ? 1 : 0;
13608 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13612 if (insn
== BB_HEAD (block
))
13615 insn
= PREV_INSN (insn
);
13618 /* Look at live-in sets for the basic block that we were in. */
13619 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13620 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13626 /* Note hard registers in X that are used. */
13629 mark_used_regs_combine (rtx x
)
13631 RTX_CODE code
= GET_CODE (x
);
13632 unsigned int regno
;
13643 case ADDR_DIFF_VEC
:
13645 /* CC0 must die in the insn after it is set, so we don't need to take
13646 special note of it here. */
13651 /* If we are clobbering a MEM, mark any hard registers inside the
13652 address as used. */
13653 if (MEM_P (XEXP (x
, 0)))
13654 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13659 /* A hard reg in a wide mode may really be multiple registers.
13660 If so, mark all of them just like the first. */
13661 if (regno
< FIRST_PSEUDO_REGISTER
)
13663 /* None of this applies to the stack, frame or arg pointers. */
13664 if (regno
== STACK_POINTER_REGNUM
13665 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13666 && regno
== HARD_FRAME_POINTER_REGNUM
)
13667 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13668 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13669 || regno
== FRAME_POINTER_REGNUM
)
13672 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13678 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13680 rtx testreg
= SET_DEST (x
);
13682 while (GET_CODE (testreg
) == SUBREG
13683 || GET_CODE (testreg
) == ZERO_EXTRACT
13684 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13685 testreg
= XEXP (testreg
, 0);
13687 if (MEM_P (testreg
))
13688 mark_used_regs_combine (XEXP (testreg
, 0));
13690 mark_used_regs_combine (SET_SRC (x
));
13698 /* Recursively scan the operands of this expression. */
13701 const char *fmt
= GET_RTX_FORMAT (code
);
13703 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13706 mark_used_regs_combine (XEXP (x
, i
));
13707 else if (fmt
[i
] == 'E')
13711 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13712 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13718 /* Remove register number REGNO from the dead registers list of INSN.
13720 Return the note used to record the death, if there was one. */
13723 remove_death (unsigned int regno
, rtx_insn
*insn
)
13725 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13728 remove_note (insn
, note
);
13733 /* For each register (hardware or pseudo) used within expression X, if its
13734 death is in an instruction with luid between FROM_LUID (inclusive) and
13735 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13736 list headed by PNOTES.
13738 That said, don't move registers killed by maybe_kill_insn.
13740 This is done when X is being merged by combination into TO_INSN. These
13741 notes will then be distributed as needed. */
13744 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13749 enum rtx_code code
= GET_CODE (x
);
13753 unsigned int regno
= REGNO (x
);
13754 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13756 /* Don't move the register if it gets killed in between from and to. */
13757 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13758 && ! reg_referenced_p (x
, maybe_kill_insn
))
13762 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13763 && DF_INSN_LUID (where_dead
) >= from_luid
13764 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13766 rtx note
= remove_death (regno
, where_dead
);
13768 /* It is possible for the call above to return 0. This can occur
13769 when last_death points to I2 or I1 that we combined with.
13770 In that case make a new note.
13772 We must also check for the case where X is a hard register
13773 and NOTE is a death note for a range of hard registers
13774 including X. In that case, we must put REG_DEAD notes for
13775 the remaining registers in place of NOTE. */
13777 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13778 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13779 > GET_MODE_SIZE (GET_MODE (x
))))
13781 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13782 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13783 unsigned int ourend
= END_REGNO (x
);
13786 for (i
= deadregno
; i
< deadend
; i
++)
13787 if (i
< regno
|| i
>= ourend
)
13788 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13791 /* If we didn't find any note, or if we found a REG_DEAD note that
13792 covers only part of the given reg, and we have a multi-reg hard
13793 register, then to be safe we must check for REG_DEAD notes
13794 for each register other than the first. They could have
13795 their own REG_DEAD notes lying around. */
13796 else if ((note
== 0
13798 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13799 < GET_MODE_SIZE (GET_MODE (x
)))))
13800 && regno
< FIRST_PSEUDO_REGISTER
13801 && REG_NREGS (x
) > 1)
13803 unsigned int ourend
= END_REGNO (x
);
13804 unsigned int i
, offset
;
13808 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13812 for (i
= regno
+ offset
; i
< ourend
; i
++)
13813 move_deaths (regno_reg_rtx
[i
],
13814 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13817 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13819 XEXP (note
, 1) = *pnotes
;
13823 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13829 else if (GET_CODE (x
) == SET
)
13831 rtx dest
= SET_DEST (x
);
13833 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13835 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13836 that accesses one word of a multi-word item, some
13837 piece of everything register in the expression is used by
13838 this insn, so remove any old death. */
13839 /* ??? So why do we test for equality of the sizes? */
13841 if (GET_CODE (dest
) == ZERO_EXTRACT
13842 || GET_CODE (dest
) == STRICT_LOW_PART
13843 || (GET_CODE (dest
) == SUBREG
13844 && (((GET_MODE_SIZE (GET_MODE (dest
))
13845 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13846 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13847 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13849 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13853 /* If this is some other SUBREG, we know it replaces the entire
13854 value, so use that as the destination. */
13855 if (GET_CODE (dest
) == SUBREG
)
13856 dest
= SUBREG_REG (dest
);
13858 /* If this is a MEM, adjust deaths of anything used in the address.
13859 For a REG (the only other possibility), the entire value is
13860 being replaced so the old value is not used in this insn. */
13863 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13868 else if (GET_CODE (x
) == CLOBBER
)
13871 len
= GET_RTX_LENGTH (code
);
13872 fmt
= GET_RTX_FORMAT (code
);
13874 for (i
= 0; i
< len
; i
++)
13879 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13880 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13883 else if (fmt
[i
] == 'e')
13884 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13888 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13889 pattern of an insn. X must be a REG. */
13892 reg_bitfield_target_p (rtx x
, rtx body
)
13896 if (GET_CODE (body
) == SET
)
13898 rtx dest
= SET_DEST (body
);
13900 unsigned int regno
, tregno
, endregno
, endtregno
;
13902 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13903 target
= XEXP (dest
, 0);
13904 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13905 target
= SUBREG_REG (XEXP (dest
, 0));
13909 if (GET_CODE (target
) == SUBREG
)
13910 target
= SUBREG_REG (target
);
13912 if (!REG_P (target
))
13915 tregno
= REGNO (target
), regno
= REGNO (x
);
13916 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13917 return target
== x
;
13919 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13920 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13922 return endregno
> tregno
&& regno
< endtregno
;
13925 else if (GET_CODE (body
) == PARALLEL
)
13926 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13927 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13933 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13934 as appropriate. I3 and I2 are the insns resulting from the combination
13935 insns including FROM (I2 may be zero).
13937 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13938 not need REG_DEAD notes because they are being substituted for. This
13939 saves searching in the most common cases.
13941 Each note in the list is either ignored or placed on some insns, depending
13942 on the type of note. */
13945 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13946 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13948 rtx note
, next_note
;
13950 rtx_insn
*tem_insn
;
13952 for (note
= notes
; note
; note
= next_note
)
13954 rtx_insn
*place
= 0, *place2
= 0;
13956 next_note
= XEXP (note
, 1);
13957 switch (REG_NOTE_KIND (note
))
13961 /* Doesn't matter much where we put this, as long as it's somewhere.
13962 It is preferable to keep these notes on branches, which is most
13963 likely to be i3. */
13967 case REG_NON_LOCAL_GOTO
:
13972 gcc_assert (i2
&& JUMP_P (i2
));
13977 case REG_EH_REGION
:
13978 /* These notes must remain with the call or trapping instruction. */
13981 else if (i2
&& CALL_P (i2
))
13985 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13986 if (may_trap_p (i3
))
13988 else if (i2
&& may_trap_p (i2
))
13990 /* ??? Otherwise assume we've combined things such that we
13991 can now prove that the instructions can't trap. Drop the
13992 note in this case. */
13996 case REG_ARGS_SIZE
:
13997 /* ??? How to distribute between i3-i1. Assume i3 contains the
13998 entire adjustment. Assert i3 contains at least some adjust. */
13999 if (!noop_move_p (i3
))
14001 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
14002 /* fixup_args_size_notes looks at REG_NORETURN note,
14003 so ensure the note is placed there first. */
14007 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14008 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14012 XEXP (n
, 1) = REG_NOTES (i3
);
14013 REG_NOTES (i3
) = n
;
14017 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14018 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14019 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14020 gcc_assert (old_size
!= args_size
14022 && !ACCUMULATE_OUTGOING_ARGS
14023 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14030 case REG_CALL_DECL
:
14031 /* These notes must remain with the call. It should not be
14032 possible for both I2 and I3 to be a call. */
14037 gcc_assert (i2
&& CALL_P (i2
));
14043 /* Any clobbers for i3 may still exist, and so we must process
14044 REG_UNUSED notes from that insn.
14046 Any clobbers from i2 or i1 can only exist if they were added by
14047 recog_for_combine. In that case, recog_for_combine created the
14048 necessary REG_UNUSED notes. Trying to keep any original
14049 REG_UNUSED notes from these insns can cause incorrect output
14050 if it is for the same register as the original i3 dest.
14051 In that case, we will notice that the register is set in i3,
14052 and then add a REG_UNUSED note for the destination of i3, which
14053 is wrong. However, it is possible to have REG_UNUSED notes from
14054 i2 or i1 for register which were both used and clobbered, so
14055 we keep notes from i2 or i1 if they will turn into REG_DEAD
14058 /* If this register is set or clobbered in I3, put the note there
14059 unless there is one already. */
14060 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14062 if (from_insn
!= i3
)
14065 if (! (REG_P (XEXP (note
, 0))
14066 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14067 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14070 /* Otherwise, if this register is used by I3, then this register
14071 now dies here, so we must put a REG_DEAD note here unless there
14073 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14074 && ! (REG_P (XEXP (note
, 0))
14075 ? find_regno_note (i3
, REG_DEAD
,
14076 REGNO (XEXP (note
, 0)))
14077 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14079 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14087 /* These notes say something about results of an insn. We can
14088 only support them if they used to be on I3 in which case they
14089 remain on I3. Otherwise they are ignored.
14091 If the note refers to an expression that is not a constant, we
14092 must also ignore the note since we cannot tell whether the
14093 equivalence is still true. It might be possible to do
14094 slightly better than this (we only have a problem if I2DEST
14095 or I1DEST is present in the expression), but it doesn't
14096 seem worth the trouble. */
14098 if (from_insn
== i3
14099 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14104 /* These notes say something about how a register is used. They must
14105 be present on any use of the register in I2 or I3. */
14106 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14109 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14118 case REG_LABEL_TARGET
:
14119 case REG_LABEL_OPERAND
:
14120 /* This can show up in several ways -- either directly in the
14121 pattern, or hidden off in the constant pool with (or without?)
14122 a REG_EQUAL note. */
14123 /* ??? Ignore the without-reg_equal-note problem for now. */
14124 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14125 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14126 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14127 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14131 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14132 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14133 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14134 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14142 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14143 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14145 if (place
&& JUMP_P (place
)
14146 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14147 && (JUMP_LABEL (place
) == NULL
14148 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14150 rtx label
= JUMP_LABEL (place
);
14153 JUMP_LABEL (place
) = XEXP (note
, 0);
14154 else if (LABEL_P (label
))
14155 LABEL_NUSES (label
)--;
14158 if (place2
&& JUMP_P (place2
)
14159 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14160 && (JUMP_LABEL (place2
) == NULL
14161 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14163 rtx label
= JUMP_LABEL (place2
);
14166 JUMP_LABEL (place2
) = XEXP (note
, 0);
14167 else if (LABEL_P (label
))
14168 LABEL_NUSES (label
)--;
14174 /* This note says something about the value of a register prior
14175 to the execution of an insn. It is too much trouble to see
14176 if the note is still correct in all situations. It is better
14177 to simply delete it. */
14181 /* If we replaced the right hand side of FROM_INSN with a
14182 REG_EQUAL note, the original use of the dying register
14183 will not have been combined into I3 and I2. In such cases,
14184 FROM_INSN is guaranteed to be the first of the combined
14185 instructions, so we simply need to search back before
14186 FROM_INSN for the previous use or set of this register,
14187 then alter the notes there appropriately.
14189 If the register is used as an input in I3, it dies there.
14190 Similarly for I2, if it is nonzero and adjacent to I3.
14192 If the register is not used as an input in either I3 or I2
14193 and it is not one of the registers we were supposed to eliminate,
14194 there are two possibilities. We might have a non-adjacent I2
14195 or we might have somehow eliminated an additional register
14196 from a computation. For example, we might have had A & B where
14197 we discover that B will always be zero. In this case we will
14198 eliminate the reference to A.
14200 In both cases, we must search to see if we can find a previous
14201 use of A and put the death note there. */
14204 && from_insn
== i2mod
14205 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14206 tem_insn
= from_insn
;
14210 && CALL_P (from_insn
)
14211 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14213 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14215 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14216 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14218 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14220 && reg_overlap_mentioned_p (XEXP (note
, 0),
14222 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14223 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14226 /* If the new I2 sets the same register that is marked dead
14227 in the note, we do not know where to put the note.
14229 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14235 basic_block bb
= this_basic_block
;
14237 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14239 if (!NONDEBUG_INSN_P (tem_insn
))
14241 if (tem_insn
== BB_HEAD (bb
))
14246 /* If the register is being set at TEM_INSN, see if that is all
14247 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14248 into a REG_UNUSED note instead. Don't delete sets to
14249 global register vars. */
14250 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14251 || !global_regs
[REGNO (XEXP (note
, 0))])
14252 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14254 rtx set
= single_set (tem_insn
);
14255 rtx inner_dest
= 0;
14256 rtx_insn
*cc0_setter
= NULL
;
14259 for (inner_dest
= SET_DEST (set
);
14260 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14261 || GET_CODE (inner_dest
) == SUBREG
14262 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14263 inner_dest
= XEXP (inner_dest
, 0))
14266 /* Verify that it was the set, and not a clobber that
14267 modified the register.
14269 CC0 targets must be careful to maintain setter/user
14270 pairs. If we cannot delete the setter due to side
14271 effects, mark the user with an UNUSED note instead
14274 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14275 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14277 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14278 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14279 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14281 /* Move the notes and links of TEM_INSN elsewhere.
14282 This might delete other dead insns recursively.
14283 First set the pattern to something that won't use
14285 rtx old_notes
= REG_NOTES (tem_insn
);
14287 PATTERN (tem_insn
) = pc_rtx
;
14288 REG_NOTES (tem_insn
) = NULL
;
14290 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14291 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14292 distribute_links (LOG_LINKS (tem_insn
));
14294 unsigned int regno
= REGNO (XEXP (note
, 0));
14295 reg_stat_type
*rsp
= ®_stat
[regno
];
14296 if (rsp
->last_set
== tem_insn
)
14297 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14299 SET_INSN_DELETED (tem_insn
);
14300 if (tem_insn
== i2
)
14303 /* Delete the setter too. */
14306 PATTERN (cc0_setter
) = pc_rtx
;
14307 old_notes
= REG_NOTES (cc0_setter
);
14308 REG_NOTES (cc0_setter
) = NULL
;
14310 distribute_notes (old_notes
, cc0_setter
,
14312 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14313 distribute_links (LOG_LINKS (cc0_setter
));
14315 SET_INSN_DELETED (cc0_setter
);
14316 if (cc0_setter
== i2
)
14322 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14324 /* If there isn't already a REG_UNUSED note, put one
14325 here. Do not place a REG_DEAD note, even if
14326 the register is also used here; that would not
14327 match the algorithm used in lifetime analysis
14328 and can cause the consistency check in the
14329 scheduler to fail. */
14330 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14331 REGNO (XEXP (note
, 0))))
14336 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14337 || (CALL_P (tem_insn
)
14338 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14342 /* If we are doing a 3->2 combination, and we have a
14343 register which formerly died in i3 and was not used
14344 by i2, which now no longer dies in i3 and is used in
14345 i2 but does not die in i2, and place is between i2
14346 and i3, then we may need to move a link from place to
14348 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14350 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14351 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14353 struct insn_link
*links
= LOG_LINKS (place
);
14354 LOG_LINKS (place
) = NULL
;
14355 distribute_links (links
);
14360 if (tem_insn
== BB_HEAD (bb
))
14366 /* If the register is set or already dead at PLACE, we needn't do
14367 anything with this note if it is still a REG_DEAD note.
14368 We check here if it is set at all, not if is it totally replaced,
14369 which is what `dead_or_set_p' checks, so also check for it being
14372 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14374 unsigned int regno
= REGNO (XEXP (note
, 0));
14375 reg_stat_type
*rsp
= ®_stat
[regno
];
14377 if (dead_or_set_p (place
, XEXP (note
, 0))
14378 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14380 /* Unless the register previously died in PLACE, clear
14381 last_death. [I no longer understand why this is
14383 if (rsp
->last_death
!= place
)
14384 rsp
->last_death
= 0;
14388 rsp
->last_death
= place
;
14390 /* If this is a death note for a hard reg that is occupying
14391 multiple registers, ensure that we are still using all
14392 parts of the object. If we find a piece of the object
14393 that is unused, we must arrange for an appropriate REG_DEAD
14394 note to be added for it. However, we can't just emit a USE
14395 and tag the note to it, since the register might actually
14396 be dead; so we recourse, and the recursive call then finds
14397 the previous insn that used this register. */
14399 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14401 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14402 bool all_used
= true;
14405 for (i
= regno
; i
< endregno
; i
++)
14406 if ((! refers_to_regno_p (i
, PATTERN (place
))
14407 && ! find_regno_fusage (place
, USE
, i
))
14408 || dead_or_set_regno_p (place
, i
))
14416 /* Put only REG_DEAD notes for pieces that are
14417 not already dead or set. */
14419 for (i
= regno
; i
< endregno
;
14420 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14422 rtx piece
= regno_reg_rtx
[i
];
14423 basic_block bb
= this_basic_block
;
14425 if (! dead_or_set_p (place
, piece
)
14426 && ! reg_bitfield_target_p (piece
,
14429 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14432 distribute_notes (new_note
, place
, place
,
14433 NULL
, NULL_RTX
, NULL_RTX
,
14436 else if (! refers_to_regno_p (i
, PATTERN (place
))
14437 && ! find_regno_fusage (place
, USE
, i
))
14438 for (tem_insn
= PREV_INSN (place
); ;
14439 tem_insn
= PREV_INSN (tem_insn
))
14441 if (!NONDEBUG_INSN_P (tem_insn
))
14443 if (tem_insn
== BB_HEAD (bb
))
14447 if (dead_or_set_p (tem_insn
, piece
)
14448 || reg_bitfield_target_p (piece
,
14449 PATTERN (tem_insn
)))
14451 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14464 /* Any other notes should not be present at this point in the
14466 gcc_unreachable ();
14471 XEXP (note
, 1) = REG_NOTES (place
);
14472 REG_NOTES (place
) = note
;
14476 add_shallow_copy_of_reg_note (place2
, note
);
14480 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14481 I3, I2, and I1 to new locations. This is also called to add a link
14482 pointing at I3 when I3's destination is changed. */
14485 distribute_links (struct insn_link
*links
)
14487 struct insn_link
*link
, *next_link
;
14489 for (link
= links
; link
; link
= next_link
)
14491 rtx_insn
*place
= 0;
14495 next_link
= link
->next
;
14497 /* If the insn that this link points to is a NOTE, ignore it. */
14498 if (NOTE_P (link
->insn
))
14502 rtx pat
= PATTERN (link
->insn
);
14503 if (GET_CODE (pat
) == SET
)
14505 else if (GET_CODE (pat
) == PARALLEL
)
14508 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14510 set
= XVECEXP (pat
, 0, i
);
14511 if (GET_CODE (set
) != SET
)
14514 reg
= SET_DEST (set
);
14515 while (GET_CODE (reg
) == ZERO_EXTRACT
14516 || GET_CODE (reg
) == STRICT_LOW_PART
14517 || GET_CODE (reg
) == SUBREG
)
14518 reg
= XEXP (reg
, 0);
14523 if (REGNO (reg
) == link
->regno
)
14526 if (i
== XVECLEN (pat
, 0))
14532 reg
= SET_DEST (set
);
14534 while (GET_CODE (reg
) == ZERO_EXTRACT
14535 || GET_CODE (reg
) == STRICT_LOW_PART
14536 || GET_CODE (reg
) == SUBREG
)
14537 reg
= XEXP (reg
, 0);
14539 /* A LOG_LINK is defined as being placed on the first insn that uses
14540 a register and points to the insn that sets the register. Start
14541 searching at the next insn after the target of the link and stop
14542 when we reach a set of the register or the end of the basic block.
14544 Note that this correctly handles the link that used to point from
14545 I3 to I2. Also note that not much searching is typically done here
14546 since most links don't point very far away. */
14548 for (insn
= NEXT_INSN (link
->insn
);
14549 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14550 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14551 insn
= NEXT_INSN (insn
))
14552 if (DEBUG_INSN_P (insn
))
14554 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14556 if (reg_referenced_p (reg
, PATTERN (insn
)))
14560 else if (CALL_P (insn
)
14561 && find_reg_fusage (insn
, USE
, reg
))
14566 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14569 /* If we found a place to put the link, place it there unless there
14570 is already a link to the same insn as LINK at that point. */
14574 struct insn_link
*link2
;
14576 FOR_EACH_LOG_LINK (link2
, place
)
14577 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14582 link
->next
= LOG_LINKS (place
);
14583 LOG_LINKS (place
) = link
;
14585 /* Set added_links_insn to the earliest insn we added a
14587 if (added_links_insn
== 0
14588 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14589 added_links_insn
= place
;
14595 /* Check for any register or memory mentioned in EQUIV that is not
14596 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14597 of EXPR where some registers may have been replaced by constants. */
14600 unmentioned_reg_p (rtx equiv
, rtx expr
)
14602 subrtx_iterator::array_type array
;
14603 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14605 const_rtx x
= *iter
;
14606 if ((REG_P (x
) || MEM_P (x
))
14607 && !reg_mentioned_p (x
, expr
))
14613 DEBUG_FUNCTION
void
14614 dump_combine_stats (FILE *file
)
14618 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14619 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14623 dump_combine_total_stats (FILE *file
)
14627 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14628 total_attempts
, total_merges
, total_extras
, total_successes
);
14631 /* Try combining insns through substitution. */
14632 static unsigned int
14633 rest_of_handle_combine (void)
14635 int rebuild_jump_labels_after_combine
;
14637 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14638 df_note_add_problem ();
14641 regstat_init_n_sets_and_refs ();
14642 reg_n_sets_max
= max_reg_num ();
14644 rebuild_jump_labels_after_combine
14645 = combine_instructions (get_insns (), max_reg_num ());
14647 /* Combining insns may have turned an indirect jump into a
14648 direct jump. Rebuild the JUMP_LABEL fields of jumping
14650 if (rebuild_jump_labels_after_combine
)
14652 if (dom_info_available_p (CDI_DOMINATORS
))
14653 free_dominance_info (CDI_DOMINATORS
);
14654 timevar_push (TV_JUMP
);
14655 rebuild_jump_labels (get_insns ());
14657 timevar_pop (TV_JUMP
);
14660 regstat_free_n_sets_and_refs ();
14666 const pass_data pass_data_combine
=
14668 RTL_PASS
, /* type */
14669 "combine", /* name */
14670 OPTGROUP_NONE
, /* optinfo_flags */
14671 TV_COMBINE
, /* tv_id */
14672 PROP_cfglayout
, /* properties_required */
14673 0, /* properties_provided */
14674 0, /* properties_destroyed */
14675 0, /* todo_flags_start */
14676 TODO_df_finish
, /* todo_flags_finish */
14679 class pass_combine
: public rtl_opt_pass
14682 pass_combine (gcc::context
*ctxt
)
14683 : rtl_opt_pass (pass_data_combine
, ctxt
)
14686 /* opt_pass methods: */
14687 virtual bool gate (function
*) { return (optimize
> 0); }
14688 virtual unsigned int execute (function
*)
14690 return rest_of_handle_combine ();
14693 }; // class pass_combine
14695 } // anon namespace
14698 make_pass_combine (gcc::context
*ctxt
)
14700 return new pass_combine (ctxt
);