1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* Basic block in which we are performing combines. */
306 static basic_block this_basic_block
;
307 static bool optimize_this_for_speed_p
;
310 /* Length of the currently allocated uid_insn_cost array. */
312 static int max_uid_known
;
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
317 static int *uid_insn_cost
;
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
325 struct insn_link
*next
;
328 static struct insn_link
**uid_log_links
;
330 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
331 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
333 #define FOR_EACH_LOG_LINK(L, INSN) \
334 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
336 /* Links for LOG_LINKS are allocated from this obstack. */
338 static struct obstack insn_link_obstack
;
340 /* Allocate a link. */
342 static inline struct insn_link
*
343 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
346 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
347 sizeof (struct insn_link
));
354 /* Incremented for each basic block. */
356 static int label_tick
;
358 /* Reset to label_tick for each extended basic block in scanning order. */
360 static int label_tick_ebb_start
;
362 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
363 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
365 static machine_mode nonzero_bits_mode
;
367 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
368 be safely used. It is zero while computing them and after combine has
369 completed. This former test prevents propagating values based on
370 previously set values, which can be incorrect if a variable is modified
373 static int nonzero_sign_valid
;
376 /* Record one modification to rtl structure
377 to be undone by storing old_contents into *where. */
379 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
385 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
386 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
389 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
390 num_undo says how many are currently recorded.
392 other_insn is nonzero if we have modified some other insn in the process
393 of working on subst_insn. It must be verified too. */
399 rtx_insn
*other_insn
;
402 static struct undobuf undobuf
;
404 /* Number of times the pseudo being substituted for
405 was found and replaced. */
407 static int n_occurrences
;
409 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
411 unsigned HOST_WIDE_INT
,
412 unsigned HOST_WIDE_INT
*);
413 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
415 unsigned int, unsigned int *);
416 static void do_SUBST (rtx
*, rtx
);
417 static void do_SUBST_INT (int *, int);
418 static void init_reg_last (void);
419 static void setup_incoming_promotions (rtx_insn
*);
420 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
421 static int cant_combine_insn_p (rtx_insn
*);
422 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
423 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
424 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
425 static int contains_muldiv (rtx
);
426 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
428 static void undo_all (void);
429 static void undo_commit (void);
430 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
431 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
432 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
433 static rtx
simplify_if_then_else (rtx
);
434 static rtx
simplify_set (rtx
);
435 static rtx
simplify_logical (rtx
);
436 static rtx
expand_compound_operation (rtx
);
437 static const_rtx
expand_field_assignment (const_rtx
);
438 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
439 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
440 static rtx
extract_left_shift (rtx
, int);
441 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
442 unsigned HOST_WIDE_INT
*);
443 static rtx
canon_reg_for_combine (rtx
, rtx
);
444 static rtx
force_to_mode (rtx
, machine_mode
,
445 unsigned HOST_WIDE_INT
, int);
446 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
447 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
448 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
449 static rtx
make_field_assignment (rtx
);
450 static rtx
apply_distributive_law (rtx
);
451 static rtx
distribute_and_simplify_rtx (rtx
, int);
452 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
453 unsigned HOST_WIDE_INT
);
454 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
455 unsigned HOST_WIDE_INT
);
456 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
457 HOST_WIDE_INT
, machine_mode
, int *);
458 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
459 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
461 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
462 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
463 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
465 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
466 static void update_table_tick (rtx
);
467 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
468 static void check_promoted_subreg (rtx_insn
*, rtx
);
469 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
470 static void record_dead_and_set_regs (rtx_insn
*);
471 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
472 static rtx
get_last_value (const_rtx
);
473 static int use_crosses_set_p (const_rtx
, int);
474 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
475 static int reg_dead_at_p (rtx
, rtx_insn
*);
476 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
477 static int reg_bitfield_target_p (rtx
, rtx
);
478 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
479 static void distribute_links (struct insn_link
*);
480 static void mark_used_regs_combine (rtx
);
481 static void record_promoted_value (rtx_insn
*, rtx
);
482 static bool unmentioned_reg_p (rtx
, rtx
);
483 static void record_truncated_values (rtx
*, void *);
484 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
485 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
488 /* It is not safe to use ordinary gen_lowpart in combine.
489 See comments in gen_lowpart_for_combine. */
490 #undef RTL_HOOKS_GEN_LOWPART
491 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
493 /* Our implementation of gen_lowpart never emits a new pseudo. */
494 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
495 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
497 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
498 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
500 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
501 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
503 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
504 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
506 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
509 /* Convenience wrapper for the canonicalize_comparison target hook.
510 Target hooks cannot use enum rtx_code. */
512 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
513 bool op0_preserve_value
)
515 int code_int
= (int)*code
;
516 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
517 *code
= (enum rtx_code
)code_int
;
520 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
521 PATTERN can not be split. Otherwise, it returns an insn sequence.
522 This is a wrapper around split_insns which ensures that the
523 reg_stat vector is made larger if the splitter creates a new
527 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
532 ret
= split_insns (pattern
, insn
);
533 nregs
= max_reg_num ();
534 if (nregs
> reg_stat
.length ())
535 reg_stat
.safe_grow_cleared (nregs
);
539 /* This is used by find_single_use to locate an rtx in LOC that
540 contains exactly one use of DEST, which is typically either a REG
541 or CC0. It returns a pointer to the innermost rtx expression
542 containing DEST. Appearances of DEST that are being used to
543 totally replace it are not counted. */
546 find_single_use_1 (rtx dest
, rtx
*loc
)
549 enum rtx_code code
= GET_CODE (x
);
565 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
566 of a REG that occupies all of the REG, the insn uses DEST if
567 it is mentioned in the destination or the source. Otherwise, we
568 need just check the source. */
569 if (GET_CODE (SET_DEST (x
)) != CC0
570 && GET_CODE (SET_DEST (x
)) != PC
571 && !REG_P (SET_DEST (x
))
572 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
573 && REG_P (SUBREG_REG (SET_DEST (x
)))
574 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
575 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
576 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
577 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
580 return find_single_use_1 (dest
, &SET_SRC (x
));
584 return find_single_use_1 (dest
, &XEXP (x
, 0));
590 /* If it wasn't one of the common cases above, check each expression and
591 vector of this code. Look for a unique usage of DEST. */
593 fmt
= GET_RTX_FORMAT (code
);
594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
598 if (dest
== XEXP (x
, i
)
599 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
600 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
603 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
606 result
= this_result
;
607 else if (this_result
)
608 /* Duplicate usage. */
611 else if (fmt
[i
] == 'E')
615 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
617 if (XVECEXP (x
, i
, j
) == dest
619 && REG_P (XVECEXP (x
, i
, j
))
620 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
623 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
626 result
= this_result
;
627 else if (this_result
)
637 /* See if DEST, produced in INSN, is used only a single time in the
638 sequel. If so, return a pointer to the innermost rtx expression in which
641 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
643 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
644 care about REG_DEAD notes or LOG_LINKS.
646 Otherwise, we find the single use by finding an insn that has a
647 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
648 only referenced once in that insn, we know that it must be the first
649 and last insn referencing DEST. */
652 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
657 struct insn_link
*link
;
661 next
= NEXT_INSN (insn
);
663 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
666 result
= find_single_use_1 (dest
, &PATTERN (next
));
675 bb
= BLOCK_FOR_INSN (insn
);
676 for (next
= NEXT_INSN (insn
);
677 next
&& BLOCK_FOR_INSN (next
) == bb
;
678 next
= NEXT_INSN (next
))
679 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
681 FOR_EACH_LOG_LINK (link
, next
)
682 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
687 result
= find_single_use_1 (dest
, &PATTERN (next
));
697 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
698 insn. The substitution can be undone by undo_all. If INTO is already
699 set to NEWVAL, do not record this change. Because computing NEWVAL might
700 also call SUBST, we have to compute it before we put anything into
704 do_SUBST (rtx
*into
, rtx newval
)
709 if (oldval
== newval
)
712 /* We'd like to catch as many invalid transformations here as
713 possible. Unfortunately, there are way too many mode changes
714 that are perfectly valid, so we'd waste too much effort for
715 little gain doing the checks here. Focus on catching invalid
716 transformations involving integer constants. */
717 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
718 && CONST_INT_P (newval
))
720 /* Sanity check that we're replacing oldval with a CONST_INT
721 that is a valid sign-extension for the original mode. */
722 gcc_assert (INTVAL (newval
)
723 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
725 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
726 CONST_INT is not valid, because after the replacement, the
727 original mode would be gone. Unfortunately, we can't tell
728 when do_SUBST is called to replace the operand thereof, so we
729 perform this test on oldval instead, checking whether an
730 invalid replacement took place before we got here. */
731 gcc_assert (!(GET_CODE (oldval
) == SUBREG
732 && CONST_INT_P (SUBREG_REG (oldval
))));
733 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
734 && CONST_INT_P (XEXP (oldval
, 0))));
738 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
740 buf
= XNEW (struct undo
);
742 buf
->kind
= UNDO_RTX
;
744 buf
->old_contents
.r
= oldval
;
747 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
750 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
752 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
753 for the value of a HOST_WIDE_INT value (including CONST_INT) is
757 do_SUBST_INT (int *into
, int newval
)
762 if (oldval
== newval
)
766 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
768 buf
= XNEW (struct undo
);
770 buf
->kind
= UNDO_INT
;
772 buf
->old_contents
.i
= oldval
;
775 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
778 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
780 /* Similar to SUBST, but just substitute the mode. This is used when
781 changing the mode of a pseudo-register, so that any other
782 references to the entry in the regno_reg_rtx array will change as
786 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
789 machine_mode oldval
= GET_MODE (*into
);
791 if (oldval
== newval
)
795 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
797 buf
= XNEW (struct undo
);
799 buf
->kind
= UNDO_MODE
;
801 buf
->old_contents
.m
= oldval
;
802 adjust_reg_mode (*into
, newval
);
804 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
807 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
809 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
812 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
815 struct insn_link
* oldval
= *into
;
817 if (oldval
== newval
)
821 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
823 buf
= XNEW (struct undo
);
825 buf
->kind
= UNDO_LINKS
;
827 buf
->old_contents
.l
= oldval
;
830 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
833 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
835 /* Subroutine of try_combine. Determine whether the replacement patterns
836 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
837 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
838 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
839 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
840 of all the instructions can be estimated and the replacements are more
841 expensive than the original sequence. */
844 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
845 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
847 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
848 int new_i2_cost
, new_i3_cost
;
849 int old_cost
, new_cost
;
851 /* Lookup the original insn_rtx_costs. */
852 i2_cost
= INSN_COST (i2
);
853 i3_cost
= INSN_COST (i3
);
857 i1_cost
= INSN_COST (i1
);
860 i0_cost
= INSN_COST (i0
);
861 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
862 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
866 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
867 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
873 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
874 i1_cost
= i0_cost
= 0;
877 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
879 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
883 /* Calculate the replacement insn_rtx_costs. */
884 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
887 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
888 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
889 ? new_i2_cost
+ new_i3_cost
: 0;
893 new_cost
= new_i3_cost
;
897 if (undobuf
.other_insn
)
899 int old_other_cost
, new_other_cost
;
901 old_other_cost
= INSN_COST (undobuf
.other_insn
);
902 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
903 if (old_other_cost
> 0 && new_other_cost
> 0)
905 old_cost
+= old_other_cost
;
906 new_cost
+= new_other_cost
;
912 /* Disallow this combination if both new_cost and old_cost are greater than
913 zero, and new_cost is greater than old cost. */
914 int reject
= old_cost
> 0 && new_cost
> old_cost
;
918 fprintf (dump_file
, "%s combination of insns ",
919 reject
? "rejecting" : "allowing");
921 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
922 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
923 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
924 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
926 fprintf (dump_file
, "original costs ");
928 fprintf (dump_file
, "%d + ", i0_cost
);
929 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
930 fprintf (dump_file
, "%d + ", i1_cost
);
931 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
934 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
935 new_i2_cost
, new_i3_cost
, new_cost
);
937 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
943 /* Update the uid_insn_cost array with the replacement costs. */
944 INSN_COST (i2
) = new_i2_cost
;
945 INSN_COST (i3
) = new_i3_cost
;
957 /* Delete any insns that copy a register to itself. */
960 delete_noop_moves (void)
962 rtx_insn
*insn
, *next
;
965 FOR_EACH_BB_FN (bb
, cfun
)
967 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
969 next
= NEXT_INSN (insn
);
970 if (INSN_P (insn
) && noop_move_p (insn
))
973 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
975 delete_insn_and_edges (insn
);
982 /* Return false if we do not want to (or cannot) combine DEF. */
984 can_combine_def_p (df_ref def
)
986 /* Do not consider if it is pre/post modification in MEM. */
987 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
990 unsigned int regno
= DF_REF_REGNO (def
);
992 /* Do not combine frame pointer adjustments. */
993 if ((regno
== FRAME_POINTER_REGNUM
994 && (!reload_completed
|| frame_pointer_needed
))
995 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
996 && regno
== HARD_FRAME_POINTER_REGNUM
997 && (!reload_completed
|| frame_pointer_needed
))
998 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
999 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1005 /* Return false if we do not want to (or cannot) combine USE. */
1007 can_combine_use_p (df_ref use
)
1009 /* Do not consider the usage of the stack pointer by function call. */
1010 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1016 /* Fill in log links field for all insns. */
1019 create_log_links (void)
1022 rtx_insn
**next_use
;
1026 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1028 /* Pass through each block from the end, recording the uses of each
1029 register and establishing log links when def is encountered.
1030 Note that we do not clear next_use array in order to save time,
1031 so we have to test whether the use is in the same basic block as def.
1033 There are a few cases below when we do not consider the definition or
1034 usage -- these are taken from original flow.c did. Don't ask me why it is
1035 done this way; I don't know and if it works, I don't want to know. */
1037 FOR_EACH_BB_FN (bb
, cfun
)
1039 FOR_BB_INSNS_REVERSE (bb
, insn
)
1041 if (!NONDEBUG_INSN_P (insn
))
1044 /* Log links are created only once. */
1045 gcc_assert (!LOG_LINKS (insn
));
1047 FOR_EACH_INSN_DEF (def
, insn
)
1049 unsigned int regno
= DF_REF_REGNO (def
);
1052 if (!next_use
[regno
])
1055 if (!can_combine_def_p (def
))
1058 use_insn
= next_use
[regno
];
1059 next_use
[regno
] = NULL
;
1061 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1066 We don't build a LOG_LINK for hard registers contained
1067 in ASM_OPERANDs. If these registers get replaced,
1068 we might wind up changing the semantics of the insn,
1069 even if reload can make what appear to be valid
1070 assignments later. */
1071 if (regno
< FIRST_PSEUDO_REGISTER
1072 && asm_noperands (PATTERN (use_insn
)) >= 0)
1075 /* Don't add duplicate links between instructions. */
1076 struct insn_link
*links
;
1077 FOR_EACH_LOG_LINK (links
, use_insn
)
1078 if (insn
== links
->insn
&& regno
== links
->regno
)
1082 LOG_LINKS (use_insn
)
1083 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1086 FOR_EACH_INSN_USE (use
, insn
)
1087 if (can_combine_use_p (use
))
1088 next_use
[DF_REF_REGNO (use
)] = insn
;
1095 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1096 true if we found a LOG_LINK that proves that A feeds B. This only works
1097 if there are no instructions between A and B which could have a link
1098 depending on A, since in that case we would not record a link for B.
1099 We also check the implicit dependency created by a cc0 setter/user
1103 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1105 struct insn_link
*links
;
1106 FOR_EACH_LOG_LINK (links
, b
)
1107 if (links
->insn
== a
)
1109 if (HAVE_cc0
&& sets_cc0_p (a
))
1114 /* Main entry point for combiner. F is the first insn of the function.
1115 NREGS is the first unused pseudo-reg number.
1117 Return nonzero if the combiner has turned an indirect jump
1118 instruction into a direct jump. */
1120 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1122 rtx_insn
*insn
, *next
;
1124 struct insn_link
*links
, *nextlinks
;
1126 basic_block last_bb
;
1128 int new_direct_jump_p
= 0;
1130 for (first
= f
; first
&& !INSN_P (first
); )
1131 first
= NEXT_INSN (first
);
1135 combine_attempts
= 0;
1138 combine_successes
= 0;
1140 rtl_hooks
= combine_rtl_hooks
;
1142 reg_stat
.safe_grow_cleared (nregs
);
1144 init_recog_no_volatile ();
1146 /* Allocate array for insn info. */
1147 max_uid_known
= get_max_uid ();
1148 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1149 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1150 gcc_obstack_init (&insn_link_obstack
);
1152 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1154 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1155 problems when, for example, we have j <<= 1 in a loop. */
1157 nonzero_sign_valid
= 0;
1158 label_tick
= label_tick_ebb_start
= 1;
1160 /* Scan all SETs and see if we can deduce anything about what
1161 bits are known to be zero for some registers and how many copies
1162 of the sign bit are known to exist for those registers.
1164 Also set any known values so that we can use it while searching
1165 for what bits are known to be set. */
1167 setup_incoming_promotions (first
);
1168 /* Allow the entry block and the first block to fall into the same EBB.
1169 Conceptually the incoming promotions are assigned to the entry block. */
1170 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1172 create_log_links ();
1173 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1175 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1180 if (!single_pred_p (this_basic_block
)
1181 || single_pred (this_basic_block
) != last_bb
)
1182 label_tick_ebb_start
= label_tick
;
1183 last_bb
= this_basic_block
;
1185 FOR_BB_INSNS (this_basic_block
, insn
)
1186 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1190 subst_low_luid
= DF_INSN_LUID (insn
);
1193 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1195 record_dead_and_set_regs (insn
);
1198 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1199 if (REG_NOTE_KIND (links
) == REG_INC
)
1200 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1203 /* Record the current insn_rtx_cost of this instruction. */
1204 if (NONJUMP_INSN_P (insn
))
1205 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1206 optimize_this_for_speed_p
);
1208 fprintf (dump_file
, "insn_cost %d: %d\n",
1209 INSN_UID (insn
), INSN_COST (insn
));
1213 nonzero_sign_valid
= 1;
1215 /* Now scan all the insns in forward order. */
1216 label_tick
= label_tick_ebb_start
= 1;
1218 setup_incoming_promotions (first
);
1219 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1220 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1222 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1224 rtx_insn
*last_combined_insn
= NULL
;
1225 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1230 if (!single_pred_p (this_basic_block
)
1231 || single_pred (this_basic_block
) != last_bb
)
1232 label_tick_ebb_start
= label_tick
;
1233 last_bb
= this_basic_block
;
1235 rtl_profile_for_bb (this_basic_block
);
1236 for (insn
= BB_HEAD (this_basic_block
);
1237 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1238 insn
= next
? next
: NEXT_INSN (insn
))
1241 if (!NONDEBUG_INSN_P (insn
))
1244 while (last_combined_insn
1245 && last_combined_insn
->deleted ())
1246 last_combined_insn
= PREV_INSN (last_combined_insn
);
1247 if (last_combined_insn
== NULL_RTX
1248 || BARRIER_P (last_combined_insn
)
1249 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1250 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1251 last_combined_insn
= insn
;
1253 /* See if we know about function return values before this
1254 insn based upon SUBREG flags. */
1255 check_promoted_subreg (insn
, PATTERN (insn
));
1257 /* See if we can find hardregs and subreg of pseudos in
1258 narrower modes. This could help turning TRUNCATEs
1260 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1262 /* Try this insn with each insn it links back to. */
1264 FOR_EACH_LOG_LINK (links
, insn
)
1265 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1266 NULL
, &new_direct_jump_p
,
1267 last_combined_insn
)) != 0)
1269 statistics_counter_event (cfun
, "two-insn combine", 1);
1273 /* Try each sequence of three linked insns ending with this one. */
1275 if (max_combine
>= 3)
1276 FOR_EACH_LOG_LINK (links
, insn
)
1278 rtx_insn
*link
= links
->insn
;
1280 /* If the linked insn has been replaced by a note, then there
1281 is no point in pursuing this chain any further. */
1285 FOR_EACH_LOG_LINK (nextlinks
, link
)
1286 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1287 NULL
, &new_direct_jump_p
,
1288 last_combined_insn
)) != 0)
1290 statistics_counter_event (cfun
, "three-insn combine", 1);
1295 /* Try to combine a jump insn that uses CC0
1296 with a preceding insn that sets CC0, and maybe with its
1297 logical predecessor as well.
1298 This is how we make decrement-and-branch insns.
1299 We need this special code because data flow connections
1300 via CC0 do not get entered in LOG_LINKS. */
1304 && (prev
= prev_nonnote_insn (insn
)) != 0
1305 && NONJUMP_INSN_P (prev
)
1306 && sets_cc0_p (PATTERN (prev
)))
1308 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1310 last_combined_insn
)) != 0)
1313 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1314 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1315 NULL
, &new_direct_jump_p
,
1316 last_combined_insn
)) != 0)
1320 /* Do the same for an insn that explicitly references CC0. */
1321 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1322 && (prev
= prev_nonnote_insn (insn
)) != 0
1323 && NONJUMP_INSN_P (prev
)
1324 && sets_cc0_p (PATTERN (prev
))
1325 && GET_CODE (PATTERN (insn
)) == SET
1326 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1328 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1330 last_combined_insn
)) != 0)
1333 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1334 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1335 NULL
, &new_direct_jump_p
,
1336 last_combined_insn
)) != 0)
1340 /* Finally, see if any of the insns that this insn links to
1341 explicitly references CC0. If so, try this insn, that insn,
1342 and its predecessor if it sets CC0. */
1345 FOR_EACH_LOG_LINK (links
, insn
)
1346 if (NONJUMP_INSN_P (links
->insn
)
1347 && GET_CODE (PATTERN (links
->insn
)) == SET
1348 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1349 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1350 && NONJUMP_INSN_P (prev
)
1351 && sets_cc0_p (PATTERN (prev
))
1352 && (next
= try_combine (insn
, links
->insn
,
1353 prev
, NULL
, &new_direct_jump_p
,
1354 last_combined_insn
)) != 0)
1358 /* Try combining an insn with two different insns whose results it
1360 if (max_combine
>= 3)
1361 FOR_EACH_LOG_LINK (links
, insn
)
1362 for (nextlinks
= links
->next
; nextlinks
;
1363 nextlinks
= nextlinks
->next
)
1364 if ((next
= try_combine (insn
, links
->insn
,
1365 nextlinks
->insn
, NULL
,
1367 last_combined_insn
)) != 0)
1370 statistics_counter_event (cfun
, "three-insn combine", 1);
1374 /* Try four-instruction combinations. */
1375 if (max_combine
>= 4)
1376 FOR_EACH_LOG_LINK (links
, insn
)
1378 struct insn_link
*next1
;
1379 rtx_insn
*link
= links
->insn
;
1381 /* If the linked insn has been replaced by a note, then there
1382 is no point in pursuing this chain any further. */
1386 FOR_EACH_LOG_LINK (next1
, link
)
1388 rtx_insn
*link1
= next1
->insn
;
1391 /* I0 -> I1 -> I2 -> I3. */
1392 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1393 if ((next
= try_combine (insn
, link
, link1
,
1396 last_combined_insn
)) != 0)
1398 statistics_counter_event (cfun
, "four-insn combine", 1);
1401 /* I0, I1 -> I2, I2 -> I3. */
1402 for (nextlinks
= next1
->next
; nextlinks
;
1403 nextlinks
= nextlinks
->next
)
1404 if ((next
= try_combine (insn
, link
, link1
,
1407 last_combined_insn
)) != 0)
1409 statistics_counter_event (cfun
, "four-insn combine", 1);
1414 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1416 rtx_insn
*link1
= next1
->insn
;
1419 /* I0 -> I2; I1, I2 -> I3. */
1420 FOR_EACH_LOG_LINK (nextlinks
, link
)
1421 if ((next
= try_combine (insn
, link
, link1
,
1424 last_combined_insn
)) != 0)
1426 statistics_counter_event (cfun
, "four-insn combine", 1);
1429 /* I0 -> I1; I1, I2 -> I3. */
1430 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1431 if ((next
= try_combine (insn
, link
, link1
,
1434 last_combined_insn
)) != 0)
1436 statistics_counter_event (cfun
, "four-insn combine", 1);
1442 /* Try this insn with each REG_EQUAL note it links back to. */
1443 FOR_EACH_LOG_LINK (links
, insn
)
1446 rtx_insn
*temp
= links
->insn
;
1447 if ((set
= single_set (temp
)) != 0
1448 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1449 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1450 /* Avoid using a register that may already been marked
1451 dead by an earlier instruction. */
1452 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1453 && (GET_MODE (note
) == VOIDmode
1454 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1455 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1456 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1457 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1458 == GET_MODE (note
))))))
1460 /* Temporarily replace the set's source with the
1461 contents of the REG_EQUAL note. The insn will
1462 be deleted or recognized by try_combine. */
1463 rtx orig_src
= SET_SRC (set
);
1464 rtx orig_dest
= SET_DEST (set
);
1465 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1466 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1467 SET_SRC (set
) = note
;
1469 i2mod_old_rhs
= copy_rtx (orig_src
);
1470 i2mod_new_rhs
= copy_rtx (note
);
1471 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1473 last_combined_insn
);
1477 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1480 SET_SRC (set
) = orig_src
;
1481 SET_DEST (set
) = orig_dest
;
1486 record_dead_and_set_regs (insn
);
1493 default_rtl_profile ();
1495 new_direct_jump_p
|= purge_all_dead_edges ();
1496 delete_noop_moves ();
1499 obstack_free (&insn_link_obstack
, NULL
);
1500 free (uid_log_links
);
1501 free (uid_insn_cost
);
1502 reg_stat
.release ();
1505 struct undo
*undo
, *next
;
1506 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1514 total_attempts
+= combine_attempts
;
1515 total_merges
+= combine_merges
;
1516 total_extras
+= combine_extras
;
1517 total_successes
+= combine_successes
;
1519 nonzero_sign_valid
= 0;
1520 rtl_hooks
= general_rtl_hooks
;
1522 /* Make recognizer allow volatile MEMs again. */
1525 return new_direct_jump_p
;
1528 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1531 init_reg_last (void)
1536 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1537 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1540 /* Set up any promoted values for incoming argument registers. */
1543 setup_incoming_promotions (rtx_insn
*first
)
1546 bool strictly_local
= false;
1548 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1549 arg
= DECL_CHAIN (arg
))
1551 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1553 machine_mode mode1
, mode2
, mode3
, mode4
;
1555 /* Only continue if the incoming argument is in a register. */
1559 /* Determine, if possible, whether all call sites of the current
1560 function lie within the current compilation unit. (This does
1561 take into account the exporting of a function via taking its
1562 address, and so forth.) */
1563 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1565 /* The mode and signedness of the argument before any promotions happen
1566 (equal to the mode of the pseudo holding it at that stage). */
1567 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1568 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1570 /* The mode and signedness of the argument after any source language and
1571 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1572 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1573 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1575 /* The mode and signedness of the argument as it is actually passed,
1576 see assign_parm_setup_reg in function.c. */
1577 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1578 TREE_TYPE (cfun
->decl
), 0);
1580 /* The mode of the register in which the argument is being passed. */
1581 mode4
= GET_MODE (reg
);
1583 /* Eliminate sign extensions in the callee when:
1584 (a) A mode promotion has occurred; */
1587 /* (b) The mode of the register is the same as the mode of
1588 the argument as it is passed; */
1591 /* (c) There's no language level extension; */
1594 /* (c.1) All callers are from the current compilation unit. If that's
1595 the case we don't have to rely on an ABI, we only have to know
1596 what we're generating right now, and we know that we will do the
1597 mode1 to mode2 promotion with the given sign. */
1598 else if (!strictly_local
)
1600 /* (c.2) The combination of the two promotions is useful. This is
1601 true when the signs match, or if the first promotion is unsigned.
1602 In the later case, (sign_extend (zero_extend x)) is the same as
1603 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1609 /* Record that the value was promoted from mode1 to mode3,
1610 so that any sign extension at the head of the current
1611 function may be eliminated. */
1612 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1613 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1614 record_value_for_reg (reg
, first
, x
);
1618 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1619 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1620 because some machines (maybe most) will actually do the sign-extension and
1621 this is the conservative approach.
1623 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1627 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1629 if (GET_MODE_PRECISION (mode
) < prec
1630 && CONST_INT_P (src
)
1632 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1633 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1638 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1642 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1645 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1646 unsigned HOST_WIDE_INT bits
= 0;
1647 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1648 unsigned int num
= 0;
1651 reg_equal
= XEXP (reg_equal_note
, 0);
1653 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1655 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1657 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1660 /* Don't call nonzero_bits if it cannot change anything. */
1661 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1663 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1664 if (reg_equal
&& bits
)
1665 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1666 rsp
->nonzero_bits
|= bits
;
1669 /* Don't call num_sign_bit_copies if it cannot change anything. */
1670 if (rsp
->sign_bit_copies
!= 1)
1672 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1673 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1675 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1676 if (num
== 0 || numeq
> num
)
1679 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1680 rsp
->sign_bit_copies
= num
;
1684 /* Called via note_stores. If X is a pseudo that is narrower than
1685 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1687 If we are setting only a portion of X and we can't figure out what
1688 portion, assume all bits will be used since we don't know what will
1691 Similarly, set how many bits of X are known to be copies of the sign bit
1692 at all locations in the function. This is the smallest number implied
1696 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1698 rtx_insn
*insn
= (rtx_insn
*) data
;
1701 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1702 /* If this register is undefined at the start of the file, we can't
1703 say what its contents were. */
1704 && ! REGNO_REG_SET_P
1705 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1706 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1708 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1710 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1712 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1713 rsp
->sign_bit_copies
= 1;
1717 /* If this register is being initialized using itself, and the
1718 register is uninitialized in this basic block, and there are
1719 no LOG_LINKS which set the register, then part of the
1720 register is uninitialized. In that case we can't assume
1721 anything about the number of nonzero bits.
1723 ??? We could do better if we checked this in
1724 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1725 could avoid making assumptions about the insn which initially
1726 sets the register, while still using the information in other
1727 insns. We would have to be careful to check every insn
1728 involved in the combination. */
1731 && reg_referenced_p (x
, PATTERN (insn
))
1732 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1735 struct insn_link
*link
;
1737 FOR_EACH_LOG_LINK (link
, insn
)
1738 if (dead_or_set_p (link
->insn
, x
))
1742 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1743 rsp
->sign_bit_copies
= 1;
1748 /* If this is a complex assignment, see if we can convert it into a
1749 simple assignment. */
1750 set
= expand_field_assignment (set
);
1752 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1753 set what we know about X. */
1755 if (SET_DEST (set
) == x
1756 || (paradoxical_subreg_p (SET_DEST (set
))
1757 && SUBREG_REG (SET_DEST (set
)) == x
))
1758 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1761 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1762 rsp
->sign_bit_copies
= 1;
1767 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1768 optionally insns that were previously combined into I3 or that will be
1769 combined into the merger of INSN and I3. The order is PRED, PRED2,
1770 INSN, SUCC, SUCC2, I3.
1772 Return 0 if the combination is not allowed for any reason.
1774 If the combination is allowed, *PDEST will be set to the single
1775 destination of INSN and *PSRC to the single source, and this function
1779 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1780 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1781 rtx
*pdest
, rtx
*psrc
)
1788 bool all_adjacent
= true;
1789 int (*is_volatile_p
) (const_rtx
);
1795 if (next_active_insn (succ2
) != i3
)
1796 all_adjacent
= false;
1797 if (next_active_insn (succ
) != succ2
)
1798 all_adjacent
= false;
1800 else if (next_active_insn (succ
) != i3
)
1801 all_adjacent
= false;
1802 if (next_active_insn (insn
) != succ
)
1803 all_adjacent
= false;
1805 else if (next_active_insn (insn
) != i3
)
1806 all_adjacent
= false;
1808 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1809 or a PARALLEL consisting of such a SET and CLOBBERs.
1811 If INSN has CLOBBER parallel parts, ignore them for our processing.
1812 By definition, these happen during the execution of the insn. When it
1813 is merged with another insn, all bets are off. If they are, in fact,
1814 needed and aren't also supplied in I3, they may be added by
1815 recog_for_combine. Otherwise, it won't match.
1817 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1820 Get the source and destination of INSN. If more than one, can't
1823 if (GET_CODE (PATTERN (insn
)) == SET
)
1824 set
= PATTERN (insn
);
1825 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1826 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1828 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1830 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1832 switch (GET_CODE (elt
))
1834 /* This is important to combine floating point insns
1835 for the SH4 port. */
1837 /* Combining an isolated USE doesn't make sense.
1838 We depend here on combinable_i3pat to reject them. */
1839 /* The code below this loop only verifies that the inputs of
1840 the SET in INSN do not change. We call reg_set_between_p
1841 to verify that the REG in the USE does not change between
1843 If the USE in INSN was for a pseudo register, the matching
1844 insn pattern will likely match any register; combining this
1845 with any other USE would only be safe if we knew that the
1846 used registers have identical values, or if there was
1847 something to tell them apart, e.g. different modes. For
1848 now, we forgo such complicated tests and simply disallow
1849 combining of USES of pseudo registers with any other USE. */
1850 if (REG_P (XEXP (elt
, 0))
1851 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1853 rtx i3pat
= PATTERN (i3
);
1854 int i
= XVECLEN (i3pat
, 0) - 1;
1855 unsigned int regno
= REGNO (XEXP (elt
, 0));
1859 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1861 if (GET_CODE (i3elt
) == USE
1862 && REG_P (XEXP (i3elt
, 0))
1863 && (REGNO (XEXP (i3elt
, 0)) == regno
1864 ? reg_set_between_p (XEXP (elt
, 0),
1865 PREV_INSN (insn
), i3
)
1866 : regno
>= FIRST_PSEUDO_REGISTER
))
1873 /* We can ignore CLOBBERs. */
1878 /* Ignore SETs whose result isn't used but not those that
1879 have side-effects. */
1880 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1881 && insn_nothrow_p (insn
)
1882 && !side_effects_p (elt
))
1885 /* If we have already found a SET, this is a second one and
1886 so we cannot combine with this insn. */
1894 /* Anything else means we can't combine. */
1900 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1901 so don't do anything with it. */
1902 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1911 /* The simplification in expand_field_assignment may call back to
1912 get_last_value, so set safe guard here. */
1913 subst_low_luid
= DF_INSN_LUID (insn
);
1915 set
= expand_field_assignment (set
);
1916 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1918 /* Do not eliminate user-specified register if it is in an
1919 asm input because we may break the register asm usage defined
1920 in GCC manual if allow to do so.
1921 Be aware that this may cover more cases than we expect but this
1922 should be harmless. */
1923 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1924 && extract_asm_operands (PATTERN (i3
)))
1927 /* Don't eliminate a store in the stack pointer. */
1928 if (dest
== stack_pointer_rtx
1929 /* Don't combine with an insn that sets a register to itself if it has
1930 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1931 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1932 /* Can't merge an ASM_OPERANDS. */
1933 || GET_CODE (src
) == ASM_OPERANDS
1934 /* Can't merge a function call. */
1935 || GET_CODE (src
) == CALL
1936 /* Don't eliminate a function call argument. */
1938 && (find_reg_fusage (i3
, USE
, dest
)
1940 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1941 && global_regs
[REGNO (dest
)])))
1942 /* Don't substitute into an incremented register. */
1943 || FIND_REG_INC_NOTE (i3
, dest
)
1944 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1945 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1946 /* Don't substitute into a non-local goto, this confuses CFG. */
1947 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1948 /* Make sure that DEST is not used after SUCC but before I3. */
1951 && (reg_used_between_p (dest
, succ2
, i3
)
1952 || reg_used_between_p (dest
, succ
, succ2
)))
1953 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1954 /* Make sure that the value that is to be substituted for the register
1955 does not use any registers whose values alter in between. However,
1956 If the insns are adjacent, a use can't cross a set even though we
1957 think it might (this can happen for a sequence of insns each setting
1958 the same destination; last_set of that register might point to
1959 a NOTE). If INSN has a REG_EQUIV note, the register is always
1960 equivalent to the memory so the substitution is valid even if there
1961 are intervening stores. Also, don't move a volatile asm or
1962 UNSPEC_VOLATILE across any other insns. */
1965 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1966 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1967 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1968 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1969 /* Don't combine across a CALL_INSN, because that would possibly
1970 change whether the life span of some REGs crosses calls or not,
1971 and it is a pain to update that information.
1972 Exception: if source is a constant, moving it later can't hurt.
1973 Accept that as a special case. */
1974 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1977 /* DEST must either be a REG or CC0. */
1980 /* If register alignment is being enforced for multi-word items in all
1981 cases except for parameters, it is possible to have a register copy
1982 insn referencing a hard register that is not allowed to contain the
1983 mode being copied and which would not be valid as an operand of most
1984 insns. Eliminate this problem by not combining with such an insn.
1986 Also, on some machines we don't want to extend the life of a hard
1990 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1991 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1992 /* Don't extend the life of a hard register unless it is
1993 user variable (if we have few registers) or it can't
1994 fit into the desired register (meaning something special
1996 Also avoid substituting a return register into I3, because
1997 reload can't handle a conflict with constraints of other
1999 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2000 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2003 else if (GET_CODE (dest
) != CC0
)
2007 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2008 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2009 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2011 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2013 /* If the clobber represents an earlyclobber operand, we must not
2014 substitute an expression containing the clobbered register.
2015 As we do not analyze the constraint strings here, we have to
2016 make the conservative assumption. However, if the register is
2017 a fixed hard reg, the clobber cannot represent any operand;
2018 we leave it up to the machine description to either accept or
2019 reject use-and-clobber patterns. */
2021 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2022 || !fixed_regs
[REGNO (reg
)])
2023 if (reg_overlap_mentioned_p (reg
, src
))
2027 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2028 or not), reject, unless nothing volatile comes between it and I3 */
2030 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2032 /* Make sure neither succ nor succ2 contains a volatile reference. */
2033 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2035 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2037 /* We'll check insns between INSN and I3 below. */
2040 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2041 to be an explicit register variable, and was chosen for a reason. */
2043 if (GET_CODE (src
) == ASM_OPERANDS
2044 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2047 /* If INSN contains volatile references (specifically volatile MEMs),
2048 we cannot combine across any other volatile references.
2049 Even if INSN doesn't contain volatile references, any intervening
2050 volatile insn might affect machine state. */
2052 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2056 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2057 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2060 /* If INSN contains an autoincrement or autodecrement, make sure that
2061 register is not used between there and I3, and not already used in
2062 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2063 Also insist that I3 not be a jump; if it were one
2064 and the incremented register were spilled, we would lose. */
2067 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2068 if (REG_NOTE_KIND (link
) == REG_INC
2070 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2071 || (pred
!= NULL_RTX
2072 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2073 || (pred2
!= NULL_RTX
2074 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2075 || (succ
!= NULL_RTX
2076 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2077 || (succ2
!= NULL_RTX
2078 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2079 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2082 /* Don't combine an insn that follows a CC0-setting insn.
2083 An insn that uses CC0 must not be separated from the one that sets it.
2084 We do, however, allow I2 to follow a CC0-setting insn if that insn
2085 is passed as I1; in that case it will be deleted also.
2086 We also allow combining in this case if all the insns are adjacent
2087 because that would leave the two CC0 insns adjacent as well.
2088 It would be more logical to test whether CC0 occurs inside I1 or I2,
2089 but that would be much slower, and this ought to be equivalent. */
2093 p
= prev_nonnote_insn (insn
);
2094 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2099 /* If we get here, we have passed all the tests and the combination is
2108 /* LOC is the location within I3 that contains its pattern or the component
2109 of a PARALLEL of the pattern. We validate that it is valid for combining.
2111 One problem is if I3 modifies its output, as opposed to replacing it
2112 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2113 doing so would produce an insn that is not equivalent to the original insns.
2117 (set (reg:DI 101) (reg:DI 100))
2118 (set (subreg:SI (reg:DI 101) 0) <foo>)
2120 This is NOT equivalent to:
2122 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2123 (set (reg:DI 101) (reg:DI 100))])
2125 Not only does this modify 100 (in which case it might still be valid
2126 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2128 We can also run into a problem if I2 sets a register that I1
2129 uses and I1 gets directly substituted into I3 (not via I2). In that
2130 case, we would be getting the wrong value of I2DEST into I3, so we
2131 must reject the combination. This case occurs when I2 and I1 both
2132 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2133 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2134 of a SET must prevent combination from occurring. The same situation
2135 can occur for I0, in which case I0_NOT_IN_SRC is set.
2137 Before doing the above check, we first try to expand a field assignment
2138 into a set of logical operations.
2140 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2141 we place a register that is both set and used within I3. If more than one
2142 such register is detected, we fail.
2144 Return 1 if the combination is valid, zero otherwise. */
2147 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2148 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2152 if (GET_CODE (x
) == SET
)
2155 rtx dest
= SET_DEST (set
);
2156 rtx src
= SET_SRC (set
);
2157 rtx inner_dest
= dest
;
2160 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2161 || GET_CODE (inner_dest
) == SUBREG
2162 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2163 inner_dest
= XEXP (inner_dest
, 0);
2165 /* Check for the case where I3 modifies its output, as discussed
2166 above. We don't want to prevent pseudos from being combined
2167 into the address of a MEM, so only prevent the combination if
2168 i1 or i2 set the same MEM. */
2169 if ((inner_dest
!= dest
&&
2170 (!MEM_P (inner_dest
)
2171 || rtx_equal_p (i2dest
, inner_dest
)
2172 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2173 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2174 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2175 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2176 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2178 /* This is the same test done in can_combine_p except we can't test
2179 all_adjacent; we don't have to, since this instruction will stay
2180 in place, thus we are not considering increasing the lifetime of
2183 Also, if this insn sets a function argument, combining it with
2184 something that might need a spill could clobber a previous
2185 function argument; the all_adjacent test in can_combine_p also
2186 checks this; here, we do a more specific test for this case. */
2188 || (REG_P (inner_dest
)
2189 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2190 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2191 GET_MODE (inner_dest
))))
2192 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2193 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2196 /* If DEST is used in I3, it is being killed in this insn, so
2197 record that for later. We have to consider paradoxical
2198 subregs here, since they kill the whole register, but we
2199 ignore partial subregs, STRICT_LOW_PART, etc.
2200 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2201 STACK_POINTER_REGNUM, since these are always considered to be
2202 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2204 if (GET_CODE (subdest
) == SUBREG
2205 && (GET_MODE_SIZE (GET_MODE (subdest
))
2206 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2207 subdest
= SUBREG_REG (subdest
);
2210 && reg_referenced_p (subdest
, PATTERN (i3
))
2211 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2212 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2213 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2214 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2215 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2216 || ! fixed_regs
[REGNO (subdest
)]))
2217 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2219 if (*pi3dest_killed
)
2222 *pi3dest_killed
= subdest
;
2226 else if (GET_CODE (x
) == PARALLEL
)
2230 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2231 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2232 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2239 /* Return 1 if X is an arithmetic expression that contains a multiplication
2240 and division. We don't count multiplications by powers of two here. */
2243 contains_muldiv (rtx x
)
2245 switch (GET_CODE (x
))
2247 case MOD
: case DIV
: case UMOD
: case UDIV
:
2251 return ! (CONST_INT_P (XEXP (x
, 1))
2252 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2255 return contains_muldiv (XEXP (x
, 0))
2256 || contains_muldiv (XEXP (x
, 1));
2259 return contains_muldiv (XEXP (x
, 0));
2265 /* Determine whether INSN can be used in a combination. Return nonzero if
2266 not. This is used in try_combine to detect early some cases where we
2267 can't perform combinations. */
2270 cant_combine_insn_p (rtx_insn
*insn
)
2275 /* If this isn't really an insn, we can't do anything.
2276 This can occur when flow deletes an insn that it has merged into an
2277 auto-increment address. */
2278 if (! INSN_P (insn
))
2281 /* Never combine loads and stores involving hard regs that are likely
2282 to be spilled. The register allocator can usually handle such
2283 reg-reg moves by tying. If we allow the combiner to make
2284 substitutions of likely-spilled regs, reload might die.
2285 As an exception, we allow combinations involving fixed regs; these are
2286 not available to the register allocator so there's no risk involved. */
2288 set
= single_set (insn
);
2291 src
= SET_SRC (set
);
2292 dest
= SET_DEST (set
);
2293 if (GET_CODE (src
) == SUBREG
)
2294 src
= SUBREG_REG (src
);
2295 if (GET_CODE (dest
) == SUBREG
)
2296 dest
= SUBREG_REG (dest
);
2297 if (REG_P (src
) && REG_P (dest
)
2298 && ((HARD_REGISTER_P (src
)
2299 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2300 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2301 || (HARD_REGISTER_P (dest
)
2302 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2303 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2309 struct likely_spilled_retval_info
2311 unsigned regno
, nregs
;
2315 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2316 hard registers that are known to be written to / clobbered in full. */
2318 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2320 struct likely_spilled_retval_info
*const info
=
2321 (struct likely_spilled_retval_info
*) data
;
2322 unsigned regno
, nregs
;
2325 if (!REG_P (XEXP (set
, 0)))
2328 if (regno
>= info
->regno
+ info
->nregs
)
2330 nregs
= REG_NREGS (x
);
2331 if (regno
+ nregs
<= info
->regno
)
2333 new_mask
= (2U << (nregs
- 1)) - 1;
2334 if (regno
< info
->regno
)
2335 new_mask
>>= info
->regno
- regno
;
2337 new_mask
<<= regno
- info
->regno
;
2338 info
->mask
&= ~new_mask
;
2341 /* Return nonzero iff part of the return value is live during INSN, and
2342 it is likely spilled. This can happen when more than one insn is needed
2343 to copy the return value, e.g. when we consider to combine into the
2344 second copy insn for a complex value. */
2347 likely_spilled_retval_p (rtx_insn
*insn
)
2349 rtx_insn
*use
= BB_END (this_basic_block
);
2352 unsigned regno
, nregs
;
2353 /* We assume here that no machine mode needs more than
2354 32 hard registers when the value overlaps with a register
2355 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2357 struct likely_spilled_retval_info info
;
2359 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2361 reg
= XEXP (PATTERN (use
), 0);
2362 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2364 regno
= REGNO (reg
);
2365 nregs
= REG_NREGS (reg
);
2368 mask
= (2U << (nregs
- 1)) - 1;
2370 /* Disregard parts of the return value that are set later. */
2374 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2376 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2379 /* Check if any of the (probably) live return value registers is
2384 if ((mask
& 1 << nregs
)
2385 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2391 /* Adjust INSN after we made a change to its destination.
2393 Changing the destination can invalidate notes that say something about
2394 the results of the insn and a LOG_LINK pointing to the insn. */
2397 adjust_for_new_dest (rtx_insn
*insn
)
2399 /* For notes, be conservative and simply remove them. */
2400 remove_reg_equal_equiv_notes (insn
);
2402 /* The new insn will have a destination that was previously the destination
2403 of an insn just above it. Call distribute_links to make a LOG_LINK from
2404 the next use of that destination. */
2406 rtx set
= single_set (insn
);
2409 rtx reg
= SET_DEST (set
);
2411 while (GET_CODE (reg
) == ZERO_EXTRACT
2412 || GET_CODE (reg
) == STRICT_LOW_PART
2413 || GET_CODE (reg
) == SUBREG
)
2414 reg
= XEXP (reg
, 0);
2415 gcc_assert (REG_P (reg
));
2417 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2419 df_insn_rescan (insn
);
2422 /* Return TRUE if combine can reuse reg X in mode MODE.
2423 ADDED_SETS is nonzero if the original set is still required. */
2425 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2433 /* Allow hard registers if the new mode is legal, and occupies no more
2434 registers than the old mode. */
2435 if (regno
< FIRST_PSEUDO_REGISTER
)
2436 return (HARD_REGNO_MODE_OK (regno
, mode
)
2437 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2439 /* Or a pseudo that is only used once. */
2440 return (regno
< reg_n_sets_max
2441 && REG_N_SETS (regno
) == 1
2443 && !REG_USERVAR_P (x
));
2447 /* Check whether X, the destination of a set, refers to part of
2448 the register specified by REG. */
2451 reg_subword_p (rtx x
, rtx reg
)
2453 /* Check that reg is an integer mode register. */
2454 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2457 if (GET_CODE (x
) == STRICT_LOW_PART
2458 || GET_CODE (x
) == ZERO_EXTRACT
)
2461 return GET_CODE (x
) == SUBREG
2462 && SUBREG_REG (x
) == reg
2463 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2466 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2467 Note that the INSN should be deleted *after* removing dead edges, so
2468 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2469 but not for a (set (pc) (label_ref FOO)). */
2472 update_cfg_for_uncondjump (rtx_insn
*insn
)
2474 basic_block bb
= BLOCK_FOR_INSN (insn
);
2475 gcc_assert (BB_END (bb
) == insn
);
2477 purge_dead_edges (bb
);
2480 if (EDGE_COUNT (bb
->succs
) == 1)
2484 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2486 /* Remove barriers from the footer if there are any. */
2487 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2488 if (BARRIER_P (insn
))
2490 if (PREV_INSN (insn
))
2491 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2493 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2494 if (NEXT_INSN (insn
))
2495 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2497 else if (LABEL_P (insn
))
2502 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2503 by an arbitrary number of CLOBBERs. */
2505 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2507 if (GET_CODE (pat
) != PARALLEL
)
2510 int len
= XVECLEN (pat
, 0);
2515 for (i
= 0; i
< n
; i
++)
2516 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2517 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2519 for ( ; i
< len
; i
++)
2520 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2521 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2527 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2528 CLOBBERs), can be split into individual SETs in that order, without
2529 changing semantics. */
2531 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2533 if (!insn_nothrow_p (insn
))
2536 rtx pat
= PATTERN (insn
);
2539 for (i
= 0; i
< n
; i
++)
2541 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2544 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2546 for (j
= i
+ 1; j
< n
; j
++)
2547 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2554 /* Try to combine the insns I0, I1 and I2 into I3.
2555 Here I0, I1 and I2 appear earlier than I3.
2556 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2559 If we are combining more than two insns and the resulting insn is not
2560 recognized, try splitting it into two insns. If that happens, I2 and I3
2561 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2562 Otherwise, I0, I1 and I2 are pseudo-deleted.
2564 Return 0 if the combination does not work. Then nothing is changed.
2565 If we did the combination, return the insn at which combine should
2568 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2569 new direct jump instruction.
2571 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2572 been I3 passed to an earlier try_combine within the same basic
2576 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2577 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2579 /* New patterns for I3 and I2, respectively. */
2580 rtx newpat
, newi2pat
= 0;
2581 rtvec newpat_vec_with_clobbers
= 0;
2582 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2583 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2585 int added_sets_0
, added_sets_1
, added_sets_2
;
2586 /* Total number of SETs to put into I3. */
2588 /* Nonzero if I2's or I1's body now appears in I3. */
2589 int i2_is_used
= 0, i1_is_used
= 0;
2590 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2591 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2592 /* Contains I3 if the destination of I3 is used in its source, which means
2593 that the old life of I3 is being killed. If that usage is placed into
2594 I2 and not in I3, a REG_DEAD note must be made. */
2595 rtx i3dest_killed
= 0;
2596 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2597 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2598 /* Copy of SET_SRC of I1 and I0, if needed. */
2599 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2600 /* Set if I2DEST was reused as a scratch register. */
2601 bool i2scratch
= false;
2602 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2603 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2604 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2605 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2606 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2607 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2608 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2609 /* Notes that must be added to REG_NOTES in I3 and I2. */
2610 rtx new_i3_notes
, new_i2_notes
;
2611 /* Notes that we substituted I3 into I2 instead of the normal case. */
2612 int i3_subst_into_i2
= 0;
2613 /* Notes that I1, I2 or I3 is a MULT operation. */
2616 int changed_i3_dest
= 0;
2619 rtx_insn
*temp_insn
;
2621 struct insn_link
*link
;
2623 rtx new_other_notes
;
2626 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2628 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2631 /* Only try four-insn combinations when there's high likelihood of
2632 success. Look for simple insns, such as loads of constants or
2633 binary operations involving a constant. */
2641 if (!flag_expensive_optimizations
)
2644 for (i
= 0; i
< 4; i
++)
2646 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2647 rtx set
= single_set (insn
);
2651 src
= SET_SRC (set
);
2652 if (CONSTANT_P (src
))
2657 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2659 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2660 || GET_CODE (src
) == LSHIFTRT
)
2664 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2665 are likely manipulating its value. Ideally we'll be able to combine
2666 all four insns into a bitfield insertion of some kind.
2668 Note the source in I0 might be inside a sign/zero extension and the
2669 memory modes in I0 and I3 might be different. So extract the address
2670 from the destination of I3 and search for it in the source of I0.
2672 In the event that there's a match but the source/dest do not actually
2673 refer to the same memory, the worst that happens is we try some
2674 combinations that we wouldn't have otherwise. */
2675 if ((set0
= single_set (i0
))
2676 /* Ensure the source of SET0 is a MEM, possibly buried inside
2678 && (GET_CODE (SET_SRC (set0
)) == MEM
2679 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2680 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2681 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2682 && (set3
= single_set (i3
))
2683 /* Ensure the destination of SET3 is a MEM. */
2684 && GET_CODE (SET_DEST (set3
)) == MEM
2685 /* Would it be better to extract the base address for the MEM
2686 in SET3 and look for that? I don't have cases where it matters
2687 but I could envision such cases. */
2688 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2691 if (ngood
< 2 && nshift
< 2)
2695 /* Exit early if one of the insns involved can't be used for
2698 || (i1
&& CALL_P (i1
))
2699 || (i0
&& CALL_P (i0
))
2700 || cant_combine_insn_p (i3
)
2701 || cant_combine_insn_p (i2
)
2702 || (i1
&& cant_combine_insn_p (i1
))
2703 || (i0
&& cant_combine_insn_p (i0
))
2704 || likely_spilled_retval_p (i3
))
2708 undobuf
.other_insn
= 0;
2710 /* Reset the hard register usage information. */
2711 CLEAR_HARD_REG_SET (newpat_used_regs
);
2713 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2716 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2717 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2719 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2720 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2722 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2723 INSN_UID (i2
), INSN_UID (i3
));
2726 /* If multiple insns feed into one of I2 or I3, they can be in any
2727 order. To simplify the code below, reorder them in sequence. */
2728 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2730 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2732 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2735 added_links_insn
= 0;
2737 /* First check for one important special case that the code below will
2738 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2739 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2740 we may be able to replace that destination with the destination of I3.
2741 This occurs in the common code where we compute both a quotient and
2742 remainder into a structure, in which case we want to do the computation
2743 directly into the structure to avoid register-register copies.
2745 Note that this case handles both multiple sets in I2 and also cases
2746 where I2 has a number of CLOBBERs inside the PARALLEL.
2748 We make very conservative checks below and only try to handle the
2749 most common cases of this. For example, we only handle the case
2750 where I2 and I3 are adjacent to avoid making difficult register
2753 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2754 && REG_P (SET_SRC (PATTERN (i3
)))
2755 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2756 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2757 && GET_CODE (PATTERN (i2
)) == PARALLEL
2758 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2759 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2760 below would need to check what is inside (and reg_overlap_mentioned_p
2761 doesn't support those codes anyway). Don't allow those destinations;
2762 the resulting insn isn't likely to be recognized anyway. */
2763 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2764 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2765 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2766 SET_DEST (PATTERN (i3
)))
2767 && next_active_insn (i2
) == i3
)
2769 rtx p2
= PATTERN (i2
);
2771 /* Make sure that the destination of I3,
2772 which we are going to substitute into one output of I2,
2773 is not used within another output of I2. We must avoid making this:
2774 (parallel [(set (mem (reg 69)) ...)
2775 (set (reg 69) ...)])
2776 which is not well-defined as to order of actions.
2777 (Besides, reload can't handle output reloads for this.)
2779 The problem can also happen if the dest of I3 is a memory ref,
2780 if another dest in I2 is an indirect memory ref. */
2781 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2782 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2783 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2784 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2785 SET_DEST (XVECEXP (p2
, 0, i
))))
2788 /* Make sure this PARALLEL is not an asm. We do not allow combining
2789 that usually (see can_combine_p), so do not here either. */
2790 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2791 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2792 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2795 if (i
== XVECLEN (p2
, 0))
2796 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2797 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2798 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2803 subst_low_luid
= DF_INSN_LUID (i2
);
2805 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2806 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2807 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2808 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2810 /* Replace the dest in I2 with our dest and make the resulting
2811 insn the new pattern for I3. Then skip to where we validate
2812 the pattern. Everything was set up above. */
2813 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2815 i3_subst_into_i2
= 1;
2816 goto validate_replacement
;
2820 /* If I2 is setting a pseudo to a constant and I3 is setting some
2821 sub-part of it to another constant, merge them by making a new
2824 && (temp_expr
= single_set (i2
)) != 0
2825 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2826 && GET_CODE (PATTERN (i3
)) == SET
2827 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2828 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2830 rtx dest
= SET_DEST (PATTERN (i3
));
2834 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2836 if (CONST_INT_P (XEXP (dest
, 1))
2837 && CONST_INT_P (XEXP (dest
, 2)))
2839 width
= INTVAL (XEXP (dest
, 1));
2840 offset
= INTVAL (XEXP (dest
, 2));
2841 dest
= XEXP (dest
, 0);
2842 if (BITS_BIG_ENDIAN
)
2843 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2848 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2849 dest
= XEXP (dest
, 0);
2850 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2856 /* If this is the low part, we're done. */
2857 if (subreg_lowpart_p (dest
))
2859 /* Handle the case where inner is twice the size of outer. */
2860 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2861 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2862 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2863 /* Otherwise give up for now. */
2870 rtx inner
= SET_SRC (PATTERN (i3
));
2871 rtx outer
= SET_SRC (temp_expr
);
2874 = wi::insert (rtx_mode_t (outer
, GET_MODE (SET_DEST (temp_expr
))),
2875 rtx_mode_t (inner
, GET_MODE (dest
)),
2880 subst_low_luid
= DF_INSN_LUID (i2
);
2881 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2882 i2dest
= SET_DEST (temp_expr
);
2883 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2885 /* Replace the source in I2 with the new constant and make the
2886 resulting insn the new pattern for I3. Then skip to where we
2887 validate the pattern. Everything was set up above. */
2888 SUBST (SET_SRC (temp_expr
),
2889 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2891 newpat
= PATTERN (i2
);
2893 /* The dest of I3 has been replaced with the dest of I2. */
2894 changed_i3_dest
= 1;
2895 goto validate_replacement
;
2899 /* If we have no I1 and I2 looks like:
2900 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2902 make up a dummy I1 that is
2905 (set (reg:CC X) (compare:CC Y (const_int 0)))
2907 (We can ignore any trailing CLOBBERs.)
2909 This undoes a previous combination and allows us to match a branch-and-
2912 if (!HAVE_cc0
&& i1
== 0
2913 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2914 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2916 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2917 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2918 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2919 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2920 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2921 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2923 /* We make I1 with the same INSN_UID as I2. This gives it
2924 the same DF_INSN_LUID for value tracking. Our fake I1 will
2925 never appear in the insn stream so giving it the same INSN_UID
2926 as I2 will not cause a problem. */
2928 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2929 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2931 INSN_UID (i1
) = INSN_UID (i2
);
2933 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2934 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2935 SET_DEST (PATTERN (i1
)));
2936 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2937 SUBST_LINK (LOG_LINKS (i2
),
2938 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2941 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2942 make those two SETs separate I1 and I2 insns, and make an I0 that is
2944 if (!HAVE_cc0
&& i0
== 0
2945 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2946 && can_split_parallel_of_n_reg_sets (i2
, 2)
2947 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2948 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2950 /* If there is no I1, there is no I0 either. */
2953 /* We make I1 with the same INSN_UID as I2. This gives it
2954 the same DF_INSN_LUID for value tracking. Our fake I1 will
2955 never appear in the insn stream so giving it the same INSN_UID
2956 as I2 will not cause a problem. */
2958 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2959 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2961 INSN_UID (i1
) = INSN_UID (i2
);
2963 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2966 /* Verify that I2 and I1 are valid for combining. */
2967 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2968 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2970 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2977 /* Record whether I2DEST is used in I2SRC and similarly for the other
2978 cases. Knowing this will help in register status updating below. */
2979 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2980 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2981 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2982 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2983 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2984 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2985 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2986 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2987 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2989 /* For the earlier insns, determine which of the subsequent ones they
2991 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2992 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2993 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2994 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2995 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2997 /* Ensure that I3's pattern can be the destination of combines. */
2998 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2999 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3000 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3001 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3008 /* See if any of the insns is a MULT operation. Unless one is, we will
3009 reject a combination that is, since it must be slower. Be conservative
3011 if (GET_CODE (i2src
) == MULT
3012 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3013 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3014 || (GET_CODE (PATTERN (i3
)) == SET
3015 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3018 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3019 We used to do this EXCEPT in one case: I3 has a post-inc in an
3020 output operand. However, that exception can give rise to insns like
3022 which is a famous insn on the PDP-11 where the value of r3 used as the
3023 source was model-dependent. Avoid this sort of thing. */
3026 if (!(GET_CODE (PATTERN (i3
)) == SET
3027 && REG_P (SET_SRC (PATTERN (i3
)))
3028 && MEM_P (SET_DEST (PATTERN (i3
)))
3029 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3030 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3031 /* It's not the exception. */
3036 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3037 if (REG_NOTE_KIND (link
) == REG_INC
3038 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3040 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3047 /* See if the SETs in I1 or I2 need to be kept around in the merged
3048 instruction: whenever the value set there is still needed past I3.
3049 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3051 For the SET in I1, we have two cases: if I1 and I2 independently feed
3052 into I3, the set in I1 needs to be kept around unless I1DEST dies
3053 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3054 in I1 needs to be kept around unless I1DEST dies or is set in either
3055 I2 or I3. The same considerations apply to I0. */
3057 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3060 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3061 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3066 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3067 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3068 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3069 && dead_or_set_p (i2
, i0dest
)));
3073 /* We are about to copy insns for the case where they need to be kept
3074 around. Check that they can be copied in the merged instruction. */
3076 if (targetm
.cannot_copy_insn_p
3077 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3078 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3079 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3085 /* If the set in I2 needs to be kept around, we must make a copy of
3086 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3087 PATTERN (I2), we are only substituting for the original I1DEST, not into
3088 an already-substituted copy. This also prevents making self-referential
3089 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3094 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3095 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3097 i2pat
= copy_rtx (PATTERN (i2
));
3102 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3103 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3105 i1pat
= copy_rtx (PATTERN (i1
));
3110 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3111 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3113 i0pat
= copy_rtx (PATTERN (i0
));
3118 /* Substitute in the latest insn for the regs set by the earlier ones. */
3120 maxreg
= max_reg_num ();
3124 /* Many machines that don't use CC0 have insns that can both perform an
3125 arithmetic operation and set the condition code. These operations will
3126 be represented as a PARALLEL with the first element of the vector
3127 being a COMPARE of an arithmetic operation with the constant zero.
3128 The second element of the vector will set some pseudo to the result
3129 of the same arithmetic operation. If we simplify the COMPARE, we won't
3130 match such a pattern and so will generate an extra insn. Here we test
3131 for this case, where both the comparison and the operation result are
3132 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3133 I2SRC. Later we will make the PARALLEL that contains I2. */
3135 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3136 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3137 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3138 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3141 rtx
*cc_use_loc
= NULL
;
3142 rtx_insn
*cc_use_insn
= NULL
;
3143 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3144 machine_mode compare_mode
, orig_compare_mode
;
3145 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3147 newpat
= PATTERN (i3
);
3148 newpat_dest
= SET_DEST (newpat
);
3149 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3151 if (undobuf
.other_insn
== 0
3152 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3155 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3156 compare_code
= simplify_compare_const (compare_code
,
3157 GET_MODE (i2dest
), op0
, &op1
);
3158 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3161 /* Do the rest only if op1 is const0_rtx, which may be the
3162 result of simplification. */
3163 if (op1
== const0_rtx
)
3165 /* If a single use of the CC is found, prepare to modify it
3166 when SELECT_CC_MODE returns a new CC-class mode, or when
3167 the above simplify_compare_const() returned a new comparison
3168 operator. undobuf.other_insn is assigned the CC use insn
3169 when modifying it. */
3172 #ifdef SELECT_CC_MODE
3173 machine_mode new_mode
3174 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3175 if (new_mode
!= orig_compare_mode
3176 && can_change_dest_mode (SET_DEST (newpat
),
3177 added_sets_2
, new_mode
))
3179 unsigned int regno
= REGNO (newpat_dest
);
3180 compare_mode
= new_mode
;
3181 if (regno
< FIRST_PSEUDO_REGISTER
)
3182 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3185 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3186 newpat_dest
= regno_reg_rtx
[regno
];
3190 /* Cases for modifying the CC-using comparison. */
3191 if (compare_code
!= orig_compare_code
3192 /* ??? Do we need to verify the zero rtx? */
3193 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3195 /* Replace cc_use_loc with entire new RTX. */
3197 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3198 newpat_dest
, const0_rtx
));
3199 undobuf
.other_insn
= cc_use_insn
;
3201 else if (compare_mode
!= orig_compare_mode
)
3203 /* Just replace the CC reg with a new mode. */
3204 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3205 undobuf
.other_insn
= cc_use_insn
;
3209 /* Now we modify the current newpat:
3210 First, SET_DEST(newpat) is updated if the CC mode has been
3211 altered. For targets without SELECT_CC_MODE, this should be
3213 if (compare_mode
!= orig_compare_mode
)
3214 SUBST (SET_DEST (newpat
), newpat_dest
);
3215 /* This is always done to propagate i2src into newpat. */
3216 SUBST (SET_SRC (newpat
),
3217 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3218 /* Create new version of i2pat if needed; the below PARALLEL
3219 creation needs this to work correctly. */
3220 if (! rtx_equal_p (i2src
, op0
))
3221 i2pat
= gen_rtx_SET (i2dest
, op0
);
3226 if (i2_is_used
== 0)
3228 /* It is possible that the source of I2 or I1 may be performing
3229 an unneeded operation, such as a ZERO_EXTEND of something
3230 that is known to have the high part zero. Handle that case
3231 by letting subst look at the inner insns.
3233 Another way to do this would be to have a function that tries
3234 to simplify a single insn instead of merging two or more
3235 insns. We don't do this because of the potential of infinite
3236 loops and because of the potential extra memory required.
3237 However, doing it the way we are is a bit of a kludge and
3238 doesn't catch all cases.
3240 But only do this if -fexpensive-optimizations since it slows
3241 things down and doesn't usually win.
3243 This is not done in the COMPARE case above because the
3244 unmodified I2PAT is used in the PARALLEL and so a pattern
3245 with a modified I2SRC would not match. */
3247 if (flag_expensive_optimizations
)
3249 /* Pass pc_rtx so no substitutions are done, just
3253 subst_low_luid
= DF_INSN_LUID (i1
);
3254 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3257 subst_low_luid
= DF_INSN_LUID (i2
);
3258 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3261 n_occurrences
= 0; /* `subst' counts here */
3262 subst_low_luid
= DF_INSN_LUID (i2
);
3264 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3265 copy of I2SRC each time we substitute it, in order to avoid creating
3266 self-referential RTL when we will be substituting I1SRC for I1DEST
3267 later. Likewise if I0 feeds into I2, either directly or indirectly
3268 through I1, and I0DEST is in I0SRC. */
3269 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3270 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3271 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3272 && i0dest_in_i0src
));
3275 /* Record whether I2's body now appears within I3's body. */
3276 i2_is_used
= n_occurrences
;
3279 /* If we already got a failure, don't try to do more. Otherwise, try to
3280 substitute I1 if we have it. */
3282 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3284 /* Check that an autoincrement side-effect on I1 has not been lost.
3285 This happens if I1DEST is mentioned in I2 and dies there, and
3286 has disappeared from the new pattern. */
3287 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3289 && dead_or_set_p (i2
, i1dest
)
3290 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3291 /* Before we can do this substitution, we must redo the test done
3292 above (see detailed comments there) that ensures I1DEST isn't
3293 mentioned in any SETs in NEWPAT that are field assignments. */
3294 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3302 subst_low_luid
= DF_INSN_LUID (i1
);
3304 /* If the following substitution will modify I1SRC, make a copy of it
3305 for the case where it is substituted for I1DEST in I2PAT later. */
3306 if (added_sets_2
&& i1_feeds_i2_n
)
3307 i1src_copy
= copy_rtx (i1src
);
3309 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3310 copy of I1SRC each time we substitute it, in order to avoid creating
3311 self-referential RTL when we will be substituting I0SRC for I0DEST
3313 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3314 i0_feeds_i1_n
&& i0dest_in_i0src
);
3317 /* Record whether I1's body now appears within I3's body. */
3318 i1_is_used
= n_occurrences
;
3321 /* Likewise for I0 if we have it. */
3323 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3325 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3326 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3327 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3328 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3329 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3336 /* If the following substitution will modify I0SRC, make a copy of it
3337 for the case where it is substituted for I0DEST in I1PAT later. */
3338 if (added_sets_1
&& i0_feeds_i1_n
)
3339 i0src_copy
= copy_rtx (i0src
);
3340 /* And a copy for I0DEST in I2PAT substitution. */
3341 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3342 || (i0_feeds_i2_n
)))
3343 i0src_copy2
= copy_rtx (i0src
);
3346 subst_low_luid
= DF_INSN_LUID (i0
);
3347 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3351 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3352 to count all the ways that I2SRC and I1SRC can be used. */
3353 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3354 && i2_is_used
+ added_sets_2
> 1)
3355 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3356 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3358 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3359 && (n_occurrences
+ added_sets_0
3360 + (added_sets_1
&& i0_feeds_i1_n
)
3361 + (added_sets_2
&& i0_feeds_i2_n
)
3363 /* Fail if we tried to make a new register. */
3364 || max_reg_num () != maxreg
3365 /* Fail if we couldn't do something and have a CLOBBER. */
3366 || GET_CODE (newpat
) == CLOBBER
3367 /* Fail if this new pattern is a MULT and we didn't have one before
3368 at the outer level. */
3369 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3376 /* If the actions of the earlier insns must be kept
3377 in addition to substituting them into the latest one,
3378 we must make a new PARALLEL for the latest insn
3379 to hold additional the SETs. */
3381 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3383 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3386 if (GET_CODE (newpat
) == PARALLEL
)
3388 rtvec old
= XVEC (newpat
, 0);
3389 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3390 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3391 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3392 sizeof (old
->elem
[0]) * old
->num_elem
);
3397 total_sets
= 1 + extra_sets
;
3398 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3399 XVECEXP (newpat
, 0, 0) = old
;
3403 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3409 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3411 XVECEXP (newpat
, 0, --total_sets
) = t
;
3417 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3418 i0_feeds_i1_n
&& i0dest_in_i0src
);
3419 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3420 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3422 XVECEXP (newpat
, 0, --total_sets
) = t
;
3426 validate_replacement
:
3428 /* Note which hard regs this insn has as inputs. */
3429 mark_used_regs_combine (newpat
);
3431 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3432 consider splitting this pattern, we might need these clobbers. */
3433 if (i1
&& GET_CODE (newpat
) == PARALLEL
3434 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3436 int len
= XVECLEN (newpat
, 0);
3438 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3439 for (i
= 0; i
< len
; i
++)
3440 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3443 /* We have recognized nothing yet. */
3444 insn_code_number
= -1;
3446 /* See if this is a PARALLEL of two SETs where one SET's destination is
3447 a register that is unused and this isn't marked as an instruction that
3448 might trap in an EH region. In that case, we just need the other SET.
3449 We prefer this over the PARALLEL.
3451 This can occur when simplifying a divmod insn. We *must* test for this
3452 case here because the code below that splits two independent SETs doesn't
3453 handle this case correctly when it updates the register status.
3455 It's pointless doing this if we originally had two sets, one from
3456 i3, and one from i2. Combining then splitting the parallel results
3457 in the original i2 again plus an invalid insn (which we delete).
3458 The net effect is only to move instructions around, which makes
3459 debug info less accurate. */
3461 if (!(added_sets_2
&& i1
== 0)
3462 && is_parallel_of_n_reg_sets (newpat
, 2)
3463 && asm_noperands (newpat
) < 0)
3465 rtx set0
= XVECEXP (newpat
, 0, 0);
3466 rtx set1
= XVECEXP (newpat
, 0, 1);
3467 rtx oldpat
= newpat
;
3469 if (((REG_P (SET_DEST (set1
))
3470 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3471 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3472 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3473 && insn_nothrow_p (i3
)
3474 && !side_effects_p (SET_SRC (set1
)))
3477 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3480 else if (((REG_P (SET_DEST (set0
))
3481 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3482 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3483 && find_reg_note (i3
, REG_UNUSED
,
3484 SUBREG_REG (SET_DEST (set0
)))))
3485 && insn_nothrow_p (i3
)
3486 && !side_effects_p (SET_SRC (set0
)))
3489 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3491 if (insn_code_number
>= 0)
3492 changed_i3_dest
= 1;
3495 if (insn_code_number
< 0)
3499 /* Is the result of combination a valid instruction? */
3500 if (insn_code_number
< 0)
3501 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3503 /* If we were combining three insns and the result is a simple SET
3504 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3505 insns. There are two ways to do this. It can be split using a
3506 machine-specific method (like when you have an addition of a large
3507 constant) or by combine in the function find_split_point. */
3509 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3510 && asm_noperands (newpat
) < 0)
3512 rtx parallel
, *split
;
3513 rtx_insn
*m_split_insn
;
3515 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3516 use I2DEST as a scratch register will help. In the latter case,
3517 convert I2DEST to the mode of the source of NEWPAT if we can. */
3519 m_split_insn
= combine_split_insns (newpat
, i3
);
3521 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3522 inputs of NEWPAT. */
3524 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3525 possible to try that as a scratch reg. This would require adding
3526 more code to make it work though. */
3528 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3530 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3532 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3533 (temporarily, until we are committed to this instruction
3534 combination) does not work: for example, any call to nonzero_bits
3535 on the register (from a splitter in the MD file, for example)
3536 will get the old information, which is invalid.
3538 Since nowadays we can create registers during combine just fine,
3539 we should just create a new one here, not reuse i2dest. */
3541 /* First try to split using the original register as a
3542 scratch register. */
3543 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3544 gen_rtvec (2, newpat
,
3545 gen_rtx_CLOBBER (VOIDmode
,
3547 m_split_insn
= combine_split_insns (parallel
, i3
);
3549 /* If that didn't work, try changing the mode of I2DEST if
3551 if (m_split_insn
== 0
3552 && new_mode
!= GET_MODE (i2dest
)
3553 && new_mode
!= VOIDmode
3554 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3556 machine_mode old_mode
= GET_MODE (i2dest
);
3559 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3560 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3563 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3564 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3567 parallel
= (gen_rtx_PARALLEL
3569 gen_rtvec (2, newpat
,
3570 gen_rtx_CLOBBER (VOIDmode
,
3572 m_split_insn
= combine_split_insns (parallel
, i3
);
3574 if (m_split_insn
== 0
3575 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3579 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3580 buf
= undobuf
.undos
;
3581 undobuf
.undos
= buf
->next
;
3582 buf
->next
= undobuf
.frees
;
3583 undobuf
.frees
= buf
;
3587 i2scratch
= m_split_insn
!= 0;
3590 /* If recog_for_combine has discarded clobbers, try to use them
3591 again for the split. */
3592 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3594 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3595 m_split_insn
= combine_split_insns (parallel
, i3
);
3598 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3600 rtx m_split_pat
= PATTERN (m_split_insn
);
3601 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3602 if (insn_code_number
>= 0)
3603 newpat
= m_split_pat
;
3605 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3606 && (next_nonnote_nondebug_insn (i2
) == i3
3607 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3610 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3611 newi2pat
= PATTERN (m_split_insn
);
3613 i3set
= single_set (NEXT_INSN (m_split_insn
));
3614 i2set
= single_set (m_split_insn
);
3616 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3618 /* If I2 or I3 has multiple SETs, we won't know how to track
3619 register status, so don't use these insns. If I2's destination
3620 is used between I2 and I3, we also can't use these insns. */
3622 if (i2_code_number
>= 0 && i2set
&& i3set
3623 && (next_nonnote_nondebug_insn (i2
) == i3
3624 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3625 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3627 if (insn_code_number
>= 0)
3630 /* It is possible that both insns now set the destination of I3.
3631 If so, we must show an extra use of it. */
3633 if (insn_code_number
>= 0)
3635 rtx new_i3_dest
= SET_DEST (i3set
);
3636 rtx new_i2_dest
= SET_DEST (i2set
);
3638 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3639 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3640 || GET_CODE (new_i3_dest
) == SUBREG
)
3641 new_i3_dest
= XEXP (new_i3_dest
, 0);
3643 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3644 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3645 || GET_CODE (new_i2_dest
) == SUBREG
)
3646 new_i2_dest
= XEXP (new_i2_dest
, 0);
3648 if (REG_P (new_i3_dest
)
3649 && REG_P (new_i2_dest
)
3650 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3651 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3652 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3656 /* If we can split it and use I2DEST, go ahead and see if that
3657 helps things be recognized. Verify that none of the registers
3658 are set between I2 and I3. */
3659 if (insn_code_number
< 0
3660 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3661 && (!HAVE_cc0
|| REG_P (i2dest
))
3662 /* We need I2DEST in the proper mode. If it is a hard register
3663 or the only use of a pseudo, we can change its mode.
3664 Make sure we don't change a hard register to have a mode that
3665 isn't valid for it, or change the number of registers. */
3666 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3667 || GET_MODE (*split
) == VOIDmode
3668 || can_change_dest_mode (i2dest
, added_sets_2
,
3670 && (next_nonnote_nondebug_insn (i2
) == i3
3671 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3672 /* We can't overwrite I2DEST if its value is still used by
3674 && ! reg_referenced_p (i2dest
, newpat
))
3676 rtx newdest
= i2dest
;
3677 enum rtx_code split_code
= GET_CODE (*split
);
3678 machine_mode split_mode
= GET_MODE (*split
);
3679 bool subst_done
= false;
3680 newi2pat
= NULL_RTX
;
3684 /* *SPLIT may be part of I2SRC, so make sure we have the
3685 original expression around for later debug processing.
3686 We should not need I2SRC any more in other cases. */
3687 if (MAY_HAVE_DEBUG_INSNS
)
3688 i2src
= copy_rtx (i2src
);
3692 /* Get NEWDEST as a register in the proper mode. We have already
3693 validated that we can do this. */
3694 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3696 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3697 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3700 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3701 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3705 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3706 an ASHIFT. This can occur if it was inside a PLUS and hence
3707 appeared to be a memory address. This is a kludge. */
3708 if (split_code
== MULT
3709 && CONST_INT_P (XEXP (*split
, 1))
3710 && INTVAL (XEXP (*split
, 1)) > 0
3711 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3713 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3714 XEXP (*split
, 0), GEN_INT (i
)));
3715 /* Update split_code because we may not have a multiply
3717 split_code
= GET_CODE (*split
);
3720 /* Similarly for (plus (mult FOO (const_int pow2))). */
3721 if (split_code
== PLUS
3722 && GET_CODE (XEXP (*split
, 0)) == MULT
3723 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3724 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3725 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3727 rtx nsplit
= XEXP (*split
, 0);
3728 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3729 XEXP (nsplit
, 0), GEN_INT (i
)));
3730 /* Update split_code because we may not have a multiply
3732 split_code
= GET_CODE (*split
);
3735 #ifdef INSN_SCHEDULING
3736 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3737 be written as a ZERO_EXTEND. */
3738 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3740 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3741 what it really is. */
3742 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3744 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3745 SUBREG_REG (*split
)));
3747 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3748 SUBREG_REG (*split
)));
3752 /* Attempt to split binary operators using arithmetic identities. */
3753 if (BINARY_P (SET_SRC (newpat
))
3754 && split_mode
== GET_MODE (SET_SRC (newpat
))
3755 && ! side_effects_p (SET_SRC (newpat
)))
3757 rtx setsrc
= SET_SRC (newpat
);
3758 machine_mode mode
= GET_MODE (setsrc
);
3759 enum rtx_code code
= GET_CODE (setsrc
);
3760 rtx src_op0
= XEXP (setsrc
, 0);
3761 rtx src_op1
= XEXP (setsrc
, 1);
3763 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3764 if (rtx_equal_p (src_op0
, src_op1
))
3766 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3767 SUBST (XEXP (setsrc
, 0), newdest
);
3768 SUBST (XEXP (setsrc
, 1), newdest
);
3771 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3772 else if ((code
== PLUS
|| code
== MULT
)
3773 && GET_CODE (src_op0
) == code
3774 && GET_CODE (XEXP (src_op0
, 0)) == code
3775 && (INTEGRAL_MODE_P (mode
)
3776 || (FLOAT_MODE_P (mode
)
3777 && flag_unsafe_math_optimizations
)))
3779 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3780 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3781 rtx r
= XEXP (src_op0
, 1);
3784 /* Split both "((X op Y) op X) op Y" and
3785 "((X op Y) op Y) op X" as "T op T" where T is
3787 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3788 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3790 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3791 SUBST (XEXP (setsrc
, 0), newdest
);
3792 SUBST (XEXP (setsrc
, 1), newdest
);
3795 /* Split "((X op X) op Y) op Y)" as "T op T" where
3797 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3799 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3800 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3801 SUBST (XEXP (setsrc
, 0), newdest
);
3802 SUBST (XEXP (setsrc
, 1), newdest
);
3810 newi2pat
= gen_rtx_SET (newdest
, *split
);
3811 SUBST (*split
, newdest
);
3814 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3816 /* recog_for_combine might have added CLOBBERs to newi2pat.
3817 Make sure NEWPAT does not depend on the clobbered regs. */
3818 if (GET_CODE (newi2pat
) == PARALLEL
)
3819 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3820 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3822 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3823 if (reg_overlap_mentioned_p (reg
, newpat
))
3830 /* If the split point was a MULT and we didn't have one before,
3831 don't use one now. */
3832 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3833 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3837 /* Check for a case where we loaded from memory in a narrow mode and
3838 then sign extended it, but we need both registers. In that case,
3839 we have a PARALLEL with both loads from the same memory location.
3840 We can split this into a load from memory followed by a register-register
3841 copy. This saves at least one insn, more if register allocation can
3844 We cannot do this if the destination of the first assignment is a
3845 condition code register or cc0. We eliminate this case by making sure
3846 the SET_DEST and SET_SRC have the same mode.
3848 We cannot do this if the destination of the second assignment is
3849 a register that we have already assumed is zero-extended. Similarly
3850 for a SUBREG of such a register. */
3852 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3853 && GET_CODE (newpat
) == PARALLEL
3854 && XVECLEN (newpat
, 0) == 2
3855 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3856 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3857 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3858 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3859 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3860 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3861 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3862 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3864 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3865 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3866 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3868 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3869 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3870 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3871 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3872 != GET_MODE_MASK (word_mode
))))
3873 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3874 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3876 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3877 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3878 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3879 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3880 != GET_MODE_MASK (word_mode
)))))
3881 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3882 SET_SRC (XVECEXP (newpat
, 0, 1)))
3883 && ! find_reg_note (i3
, REG_UNUSED
,
3884 SET_DEST (XVECEXP (newpat
, 0, 0))))
3888 newi2pat
= XVECEXP (newpat
, 0, 0);
3889 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3890 newpat
= XVECEXP (newpat
, 0, 1);
3891 SUBST (SET_SRC (newpat
),
3892 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3893 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3895 if (i2_code_number
>= 0)
3896 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3898 if (insn_code_number
>= 0)
3902 /* Similarly, check for a case where we have a PARALLEL of two independent
3903 SETs but we started with three insns. In this case, we can do the sets
3904 as two separate insns. This case occurs when some SET allows two
3905 other insns to combine, but the destination of that SET is still live.
3907 Also do this if we started with two insns and (at least) one of the
3908 resulting sets is a noop; this noop will be deleted later. */
3910 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3911 && GET_CODE (newpat
) == PARALLEL
3912 && XVECLEN (newpat
, 0) == 2
3913 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3914 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3915 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3916 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3917 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3918 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3919 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3920 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3921 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3922 XVECEXP (newpat
, 0, 0))
3923 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3924 XVECEXP (newpat
, 0, 1))
3925 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3926 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3928 rtx set0
= XVECEXP (newpat
, 0, 0);
3929 rtx set1
= XVECEXP (newpat
, 0, 1);
3931 /* Normally, it doesn't matter which of the two is done first,
3932 but the one that references cc0 can't be the second, and
3933 one which uses any regs/memory set in between i2 and i3 can't
3934 be first. The PARALLEL might also have been pre-existing in i3,
3935 so we need to make sure that we won't wrongly hoist a SET to i2
3936 that would conflict with a death note present in there. */
3937 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3938 && !(REG_P (SET_DEST (set1
))
3939 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3940 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3941 && find_reg_note (i2
, REG_DEAD
,
3942 SUBREG_REG (SET_DEST (set1
))))
3943 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3944 /* If I3 is a jump, ensure that set0 is a jump so that
3945 we do not create invalid RTL. */
3946 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3952 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3953 && !(REG_P (SET_DEST (set0
))
3954 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3955 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3956 && find_reg_note (i2
, REG_DEAD
,
3957 SUBREG_REG (SET_DEST (set0
))))
3958 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3959 /* If I3 is a jump, ensure that set1 is a jump so that
3960 we do not create invalid RTL. */
3961 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3973 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3975 if (i2_code_number
>= 0)
3977 /* recog_for_combine might have added CLOBBERs to newi2pat.
3978 Make sure NEWPAT does not depend on the clobbered regs. */
3979 if (GET_CODE (newi2pat
) == PARALLEL
)
3981 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3982 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3984 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3985 if (reg_overlap_mentioned_p (reg
, newpat
))
3993 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3997 /* If it still isn't recognized, fail and change things back the way they
3999 if ((insn_code_number
< 0
4000 /* Is the result a reasonable ASM_OPERANDS? */
4001 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4007 /* If we had to change another insn, make sure it is valid also. */
4008 if (undobuf
.other_insn
)
4010 CLEAR_HARD_REG_SET (newpat_used_regs
);
4012 other_pat
= PATTERN (undobuf
.other_insn
);
4013 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4016 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4023 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4024 they are adjacent to each other or not. */
4027 rtx_insn
*p
= prev_nonnote_insn (i3
);
4028 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4029 && sets_cc0_p (newi2pat
))
4036 /* Only allow this combination if insn_rtx_costs reports that the
4037 replacement instructions are cheaper than the originals. */
4038 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4044 if (MAY_HAVE_DEBUG_INSNS
)
4048 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4049 if (undo
->kind
== UNDO_MODE
)
4051 rtx reg
= *undo
->where
.r
;
4052 machine_mode new_mode
= GET_MODE (reg
);
4053 machine_mode old_mode
= undo
->old_contents
.m
;
4055 /* Temporarily revert mode back. */
4056 adjust_reg_mode (reg
, old_mode
);
4058 if (reg
== i2dest
&& i2scratch
)
4060 /* If we used i2dest as a scratch register with a
4061 different mode, substitute it for the original
4062 i2src while its original mode is temporarily
4063 restored, and then clear i2scratch so that we don't
4064 do it again later. */
4065 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4068 /* Put back the new mode. */
4069 adjust_reg_mode (reg
, new_mode
);
4073 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4074 rtx_insn
*first
, *last
;
4079 last
= last_combined_insn
;
4084 last
= undobuf
.other_insn
;
4086 if (DF_INSN_LUID (last
)
4087 < DF_INSN_LUID (last_combined_insn
))
4088 last
= last_combined_insn
;
4091 /* We're dealing with a reg that changed mode but not
4092 meaning, so we want to turn it into a subreg for
4093 the new mode. However, because of REG sharing and
4094 because its mode had already changed, we have to do
4095 it in two steps. First, replace any debug uses of
4096 reg, with its original mode temporarily restored,
4097 with this copy we have created; then, replace the
4098 copy with the SUBREG of the original shared reg,
4099 once again changed to the new mode. */
4100 propagate_for_debug (first
, last
, reg
, tempreg
,
4102 adjust_reg_mode (reg
, new_mode
);
4103 propagate_for_debug (first
, last
, tempreg
,
4104 lowpart_subreg (old_mode
, reg
, new_mode
),
4110 /* If we will be able to accept this, we have made a
4111 change to the destination of I3. This requires us to
4112 do a few adjustments. */
4114 if (changed_i3_dest
)
4116 PATTERN (i3
) = newpat
;
4117 adjust_for_new_dest (i3
);
4120 /* We now know that we can do this combination. Merge the insns and
4121 update the status of registers and LOG_LINKS. */
4123 if (undobuf
.other_insn
)
4127 PATTERN (undobuf
.other_insn
) = other_pat
;
4129 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4130 ensure that they are still valid. Then add any non-duplicate
4131 notes added by recog_for_combine. */
4132 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4134 next
= XEXP (note
, 1);
4136 if ((REG_NOTE_KIND (note
) == REG_DEAD
4137 && !reg_referenced_p (XEXP (note
, 0),
4138 PATTERN (undobuf
.other_insn
)))
4139 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4140 && !reg_set_p (XEXP (note
, 0),
4141 PATTERN (undobuf
.other_insn
))))
4142 remove_note (undobuf
.other_insn
, note
);
4145 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4146 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4153 struct insn_link
*link
;
4156 /* I3 now uses what used to be its destination and which is now
4157 I2's destination. This requires us to do a few adjustments. */
4158 PATTERN (i3
) = newpat
;
4159 adjust_for_new_dest (i3
);
4161 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4164 However, some later insn might be using I2's dest and have
4165 a LOG_LINK pointing at I3. We must remove this link.
4166 The simplest way to remove the link is to point it at I1,
4167 which we know will be a NOTE. */
4169 /* newi2pat is usually a SET here; however, recog_for_combine might
4170 have added some clobbers. */
4171 if (GET_CODE (newi2pat
) == PARALLEL
)
4172 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4174 ni2dest
= SET_DEST (newi2pat
);
4176 for (insn
= NEXT_INSN (i3
);
4177 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4178 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4179 insn
= NEXT_INSN (insn
))
4181 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4183 FOR_EACH_LOG_LINK (link
, insn
)
4184 if (link
->insn
== i3
)
4193 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4194 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4197 /* Compute which registers we expect to eliminate. newi2pat may be setting
4198 either i3dest or i2dest, so we must check it. */
4199 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4200 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4203 /* For i1, we need to compute both local elimination and global
4204 elimination information with respect to newi2pat because i1dest
4205 may be the same as i3dest, in which case newi2pat may be setting
4206 i1dest. Global information is used when distributing REG_DEAD
4207 note for i2 and i3, in which case it does matter if newi2pat sets
4210 Local information is used when distributing REG_DEAD note for i1,
4211 in which case it doesn't matter if newi2pat sets i1dest or not.
4212 See PR62151, if we have four insns combination:
4214 i1: r1 <- i1src (using r0)
4216 i2: r0 <- i2src (using r1)
4217 i3: r3 <- i3src (using r0)
4219 From i1's point of view, r0 is eliminated, no matter if it is set
4220 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4221 should be discarded.
4223 Note local information only affects cases in forms like "I1->I2->I3",
4224 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4225 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4227 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4230 rtx elim_i1
= (local_elim_i1
== 0
4231 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4233 /* Same case as i1. */
4234 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4236 rtx elim_i0
= (local_elim_i0
== 0
4237 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4240 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4242 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4243 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4245 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4247 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4249 /* Ensure that we do not have something that should not be shared but
4250 occurs multiple times in the new insns. Check this by first
4251 resetting all the `used' flags and then copying anything is shared. */
4253 reset_used_flags (i3notes
);
4254 reset_used_flags (i2notes
);
4255 reset_used_flags (i1notes
);
4256 reset_used_flags (i0notes
);
4257 reset_used_flags (newpat
);
4258 reset_used_flags (newi2pat
);
4259 if (undobuf
.other_insn
)
4260 reset_used_flags (PATTERN (undobuf
.other_insn
));
4262 i3notes
= copy_rtx_if_shared (i3notes
);
4263 i2notes
= copy_rtx_if_shared (i2notes
);
4264 i1notes
= copy_rtx_if_shared (i1notes
);
4265 i0notes
= copy_rtx_if_shared (i0notes
);
4266 newpat
= copy_rtx_if_shared (newpat
);
4267 newi2pat
= copy_rtx_if_shared (newi2pat
);
4268 if (undobuf
.other_insn
)
4269 reset_used_flags (PATTERN (undobuf
.other_insn
));
4271 INSN_CODE (i3
) = insn_code_number
;
4272 PATTERN (i3
) = newpat
;
4274 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4276 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4278 reset_used_flags (call_usage
);
4279 call_usage
= copy_rtx (call_usage
);
4283 /* I2SRC must still be meaningful at this point. Some splitting
4284 operations can invalidate I2SRC, but those operations do not
4287 replace_rtx (call_usage
, i2dest
, i2src
);
4291 replace_rtx (call_usage
, i1dest
, i1src
);
4293 replace_rtx (call_usage
, i0dest
, i0src
);
4295 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4298 if (undobuf
.other_insn
)
4299 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4301 /* We had one special case above where I2 had more than one set and
4302 we replaced a destination of one of those sets with the destination
4303 of I3. In that case, we have to update LOG_LINKS of insns later
4304 in this basic block. Note that this (expensive) case is rare.
4306 Also, in this case, we must pretend that all REG_NOTEs for I2
4307 actually came from I3, so that REG_UNUSED notes from I2 will be
4308 properly handled. */
4310 if (i3_subst_into_i2
)
4312 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4313 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4314 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4315 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4316 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4317 && ! find_reg_note (i2
, REG_UNUSED
,
4318 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4319 for (temp_insn
= NEXT_INSN (i2
);
4321 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4322 || BB_HEAD (this_basic_block
) != temp_insn
);
4323 temp_insn
= NEXT_INSN (temp_insn
))
4324 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4325 FOR_EACH_LOG_LINK (link
, temp_insn
)
4326 if (link
->insn
== i2
)
4332 while (XEXP (link
, 1))
4333 link
= XEXP (link
, 1);
4334 XEXP (link
, 1) = i2notes
;
4341 LOG_LINKS (i3
) = NULL
;
4343 LOG_LINKS (i2
) = NULL
;
4348 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4349 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4351 INSN_CODE (i2
) = i2_code_number
;
4352 PATTERN (i2
) = newi2pat
;
4356 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4357 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4359 SET_INSN_DELETED (i2
);
4364 LOG_LINKS (i1
) = NULL
;
4366 if (MAY_HAVE_DEBUG_INSNS
)
4367 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4369 SET_INSN_DELETED (i1
);
4374 LOG_LINKS (i0
) = NULL
;
4376 if (MAY_HAVE_DEBUG_INSNS
)
4377 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4379 SET_INSN_DELETED (i0
);
4382 /* Get death notes for everything that is now used in either I3 or
4383 I2 and used to die in a previous insn. If we built two new
4384 patterns, move from I1 to I2 then I2 to I3 so that we get the
4385 proper movement on registers that I2 modifies. */
4388 from_luid
= DF_INSN_LUID (i0
);
4390 from_luid
= DF_INSN_LUID (i1
);
4392 from_luid
= DF_INSN_LUID (i2
);
4394 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4395 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4397 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4399 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4400 elim_i2
, elim_i1
, elim_i0
);
4402 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4403 elim_i2
, elim_i1
, elim_i0
);
4405 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4406 elim_i2
, local_elim_i1
, local_elim_i0
);
4408 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4409 elim_i2
, elim_i1
, local_elim_i0
);
4411 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4412 elim_i2
, elim_i1
, elim_i0
);
4414 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4415 know these are REG_UNUSED and want them to go to the desired insn,
4416 so we always pass it as i3. */
4418 if (newi2pat
&& new_i2_notes
)
4419 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4423 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4426 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4427 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4428 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4429 in that case, it might delete I2. Similarly for I2 and I1.
4430 Show an additional death due to the REG_DEAD note we make here. If
4431 we discard it in distribute_notes, we will decrement it again. */
4435 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4436 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4437 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4440 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4441 elim_i2
, elim_i1
, elim_i0
);
4444 if (i2dest_in_i2src
)
4446 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4447 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4448 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4449 NULL_RTX
, NULL_RTX
);
4451 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4452 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4455 if (i1dest_in_i1src
)
4457 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4458 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4459 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4460 NULL_RTX
, NULL_RTX
);
4462 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4463 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4466 if (i0dest_in_i0src
)
4468 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4469 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4470 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4471 NULL_RTX
, NULL_RTX
);
4473 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4474 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4477 distribute_links (i3links
);
4478 distribute_links (i2links
);
4479 distribute_links (i1links
);
4480 distribute_links (i0links
);
4484 struct insn_link
*link
;
4485 rtx_insn
*i2_insn
= 0;
4486 rtx i2_val
= 0, set
;
4488 /* The insn that used to set this register doesn't exist, and
4489 this life of the register may not exist either. See if one of
4490 I3's links points to an insn that sets I2DEST. If it does,
4491 that is now the last known value for I2DEST. If we don't update
4492 this and I2 set the register to a value that depended on its old
4493 contents, we will get confused. If this insn is used, thing
4494 will be set correctly in combine_instructions. */
4495 FOR_EACH_LOG_LINK (link
, i3
)
4496 if ((set
= single_set (link
->insn
)) != 0
4497 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4498 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4500 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4502 /* If the reg formerly set in I2 died only once and that was in I3,
4503 zero its use count so it won't make `reload' do any work. */
4505 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4506 && ! i2dest_in_i2src
4507 && REGNO (i2dest
) < reg_n_sets_max
)
4508 INC_REG_N_SETS (REGNO (i2dest
), -1);
4511 if (i1
&& REG_P (i1dest
))
4513 struct insn_link
*link
;
4514 rtx_insn
*i1_insn
= 0;
4515 rtx i1_val
= 0, set
;
4517 FOR_EACH_LOG_LINK (link
, i3
)
4518 if ((set
= single_set (link
->insn
)) != 0
4519 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4520 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4522 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4525 && ! i1dest_in_i1src
4526 && REGNO (i1dest
) < reg_n_sets_max
)
4527 INC_REG_N_SETS (REGNO (i1dest
), -1);
4530 if (i0
&& REG_P (i0dest
))
4532 struct insn_link
*link
;
4533 rtx_insn
*i0_insn
= 0;
4534 rtx i0_val
= 0, set
;
4536 FOR_EACH_LOG_LINK (link
, i3
)
4537 if ((set
= single_set (link
->insn
)) != 0
4538 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4539 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4541 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4544 && ! i0dest_in_i0src
4545 && REGNO (i0dest
) < reg_n_sets_max
)
4546 INC_REG_N_SETS (REGNO (i0dest
), -1);
4549 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4550 been made to this insn. The order is important, because newi2pat
4551 can affect nonzero_bits of newpat. */
4553 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4554 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4557 if (undobuf
.other_insn
!= NULL_RTX
)
4561 fprintf (dump_file
, "modifying other_insn ");
4562 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4564 df_insn_rescan (undobuf
.other_insn
);
4567 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4571 fprintf (dump_file
, "modifying insn i0 ");
4572 dump_insn_slim (dump_file
, i0
);
4574 df_insn_rescan (i0
);
4577 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4581 fprintf (dump_file
, "modifying insn i1 ");
4582 dump_insn_slim (dump_file
, i1
);
4584 df_insn_rescan (i1
);
4587 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4591 fprintf (dump_file
, "modifying insn i2 ");
4592 dump_insn_slim (dump_file
, i2
);
4594 df_insn_rescan (i2
);
4597 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4601 fprintf (dump_file
, "modifying insn i3 ");
4602 dump_insn_slim (dump_file
, i3
);
4604 df_insn_rescan (i3
);
4607 /* Set new_direct_jump_p if a new return or simple jump instruction
4608 has been created. Adjust the CFG accordingly. */
4609 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4611 *new_direct_jump_p
= 1;
4612 mark_jump_label (PATTERN (i3
), i3
, 0);
4613 update_cfg_for_uncondjump (i3
);
4616 if (undobuf
.other_insn
!= NULL_RTX
4617 && (returnjump_p (undobuf
.other_insn
)
4618 || any_uncondjump_p (undobuf
.other_insn
)))
4620 *new_direct_jump_p
= 1;
4621 update_cfg_for_uncondjump (undobuf
.other_insn
);
4624 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4625 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4627 basic_block bb
= BLOCK_FOR_INSN (i3
);
4629 remove_edge (split_block (bb
, i3
));
4630 emit_barrier_after_bb (bb
);
4631 *new_direct_jump_p
= 1;
4634 if (undobuf
.other_insn
4635 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4636 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4638 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4640 remove_edge (split_block (bb
, undobuf
.other_insn
));
4641 emit_barrier_after_bb (bb
);
4642 *new_direct_jump_p
= 1;
4645 /* A noop might also need cleaning up of CFG, if it comes from the
4646 simplification of a jump. */
4648 && GET_CODE (newpat
) == SET
4649 && SET_SRC (newpat
) == pc_rtx
4650 && SET_DEST (newpat
) == pc_rtx
)
4652 *new_direct_jump_p
= 1;
4653 update_cfg_for_uncondjump (i3
);
4656 if (undobuf
.other_insn
!= NULL_RTX
4657 && JUMP_P (undobuf
.other_insn
)
4658 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4659 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4660 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4662 *new_direct_jump_p
= 1;
4663 update_cfg_for_uncondjump (undobuf
.other_insn
);
4666 combine_successes
++;
4669 if (added_links_insn
4670 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4671 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4672 return added_links_insn
;
4674 return newi2pat
? i2
: i3
;
4677 /* Get a marker for undoing to the current state. */
4680 get_undo_marker (void)
4682 return undobuf
.undos
;
4685 /* Undo the modifications up to the marker. */
4688 undo_to_marker (void *marker
)
4690 struct undo
*undo
, *next
;
4692 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4700 *undo
->where
.r
= undo
->old_contents
.r
;
4703 *undo
->where
.i
= undo
->old_contents
.i
;
4706 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4709 *undo
->where
.l
= undo
->old_contents
.l
;
4715 undo
->next
= undobuf
.frees
;
4716 undobuf
.frees
= undo
;
4719 undobuf
.undos
= (struct undo
*) marker
;
4722 /* Undo all the modifications recorded in undobuf. */
4730 /* We've committed to accepting the changes we made. Move all
4731 of the undos to the free list. */
4736 struct undo
*undo
, *next
;
4738 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4741 undo
->next
= undobuf
.frees
;
4742 undobuf
.frees
= undo
;
4747 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4748 where we have an arithmetic expression and return that point. LOC will
4751 try_combine will call this function to see if an insn can be split into
4755 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4758 enum rtx_code code
= GET_CODE (x
);
4760 unsigned HOST_WIDE_INT len
= 0;
4761 HOST_WIDE_INT pos
= 0;
4763 rtx inner
= NULL_RTX
;
4765 /* First special-case some codes. */
4769 #ifdef INSN_SCHEDULING
4770 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4772 if (MEM_P (SUBREG_REG (x
)))
4775 return find_split_point (&SUBREG_REG (x
), insn
, false);
4778 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4779 using LO_SUM and HIGH. */
4780 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4781 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4783 machine_mode address_mode
= get_address_mode (x
);
4786 gen_rtx_LO_SUM (address_mode
,
4787 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4789 return &XEXP (XEXP (x
, 0), 0);
4792 /* If we have a PLUS whose second operand is a constant and the
4793 address is not valid, perhaps will can split it up using
4794 the machine-specific way to split large constants. We use
4795 the first pseudo-reg (one of the virtual regs) as a placeholder;
4796 it will not remain in the result. */
4797 if (GET_CODE (XEXP (x
, 0)) == PLUS
4798 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4799 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4800 MEM_ADDR_SPACE (x
)))
4802 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4803 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4806 /* This should have produced two insns, each of which sets our
4807 placeholder. If the source of the second is a valid address,
4808 we can make put both sources together and make a split point
4812 && NEXT_INSN (seq
) != NULL_RTX
4813 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4814 && NONJUMP_INSN_P (seq
)
4815 && GET_CODE (PATTERN (seq
)) == SET
4816 && SET_DEST (PATTERN (seq
)) == reg
4817 && ! reg_mentioned_p (reg
,
4818 SET_SRC (PATTERN (seq
)))
4819 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4820 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4821 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4822 && memory_address_addr_space_p
4823 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4824 MEM_ADDR_SPACE (x
)))
4826 rtx src1
= SET_SRC (PATTERN (seq
));
4827 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4829 /* Replace the placeholder in SRC2 with SRC1. If we can
4830 find where in SRC2 it was placed, that can become our
4831 split point and we can replace this address with SRC2.
4832 Just try two obvious places. */
4834 src2
= replace_rtx (src2
, reg
, src1
);
4836 if (XEXP (src2
, 0) == src1
)
4837 split
= &XEXP (src2
, 0);
4838 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4839 && XEXP (XEXP (src2
, 0), 0) == src1
)
4840 split
= &XEXP (XEXP (src2
, 0), 0);
4844 SUBST (XEXP (x
, 0), src2
);
4849 /* If that didn't work, perhaps the first operand is complex and
4850 needs to be computed separately, so make a split point there.
4851 This will occur on machines that just support REG + CONST
4852 and have a constant moved through some previous computation. */
4854 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4855 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4856 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4857 return &XEXP (XEXP (x
, 0), 0);
4860 /* If we have a PLUS whose first operand is complex, try computing it
4861 separately by making a split there. */
4862 if (GET_CODE (XEXP (x
, 0)) == PLUS
4863 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4865 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4866 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4867 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4868 return &XEXP (XEXP (x
, 0), 0);
4872 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4873 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4874 we need to put the operand into a register. So split at that
4877 if (SET_DEST (x
) == cc0_rtx
4878 && GET_CODE (SET_SRC (x
)) != COMPARE
4879 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4880 && !OBJECT_P (SET_SRC (x
))
4881 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4882 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4883 return &SET_SRC (x
);
4885 /* See if we can split SET_SRC as it stands. */
4886 split
= find_split_point (&SET_SRC (x
), insn
, true);
4887 if (split
&& split
!= &SET_SRC (x
))
4890 /* See if we can split SET_DEST as it stands. */
4891 split
= find_split_point (&SET_DEST (x
), insn
, false);
4892 if (split
&& split
!= &SET_DEST (x
))
4895 /* See if this is a bitfield assignment with everything constant. If
4896 so, this is an IOR of an AND, so split it into that. */
4897 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4898 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4899 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4900 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4901 && CONST_INT_P (SET_SRC (x
))
4902 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4903 + INTVAL (XEXP (SET_DEST (x
), 2)))
4904 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4905 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4907 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4908 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4909 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4910 rtx dest
= XEXP (SET_DEST (x
), 0);
4911 machine_mode mode
= GET_MODE (dest
);
4912 unsigned HOST_WIDE_INT mask
4913 = (HOST_WIDE_INT_1U
<< len
) - 1;
4916 if (BITS_BIG_ENDIAN
)
4917 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4919 or_mask
= gen_int_mode (src
<< pos
, mode
);
4922 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4925 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4927 simplify_gen_binary (IOR
, mode
,
4928 simplify_gen_binary (AND
, mode
,
4933 SUBST (SET_DEST (x
), dest
);
4935 split
= find_split_point (&SET_SRC (x
), insn
, true);
4936 if (split
&& split
!= &SET_SRC (x
))
4940 /* Otherwise, see if this is an operation that we can split into two.
4941 If so, try to split that. */
4942 code
= GET_CODE (SET_SRC (x
));
4947 /* If we are AND'ing with a large constant that is only a single
4948 bit and the result is only being used in a context where we
4949 need to know if it is zero or nonzero, replace it with a bit
4950 extraction. This will avoid the large constant, which might
4951 have taken more than one insn to make. If the constant were
4952 not a valid argument to the AND but took only one insn to make,
4953 this is no worse, but if it took more than one insn, it will
4956 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4957 && REG_P (XEXP (SET_SRC (x
), 0))
4958 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4959 && REG_P (SET_DEST (x
))
4960 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4961 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4962 && XEXP (*split
, 0) == SET_DEST (x
)
4963 && XEXP (*split
, 1) == const0_rtx
)
4965 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4966 XEXP (SET_SRC (x
), 0),
4967 pos
, NULL_RTX
, 1, 1, 0, 0);
4968 if (extraction
!= 0)
4970 SUBST (SET_SRC (x
), extraction
);
4971 return find_split_point (loc
, insn
, false);
4977 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4978 is known to be on, this can be converted into a NEG of a shift. */
4979 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4980 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4981 && 1 <= (pos
= exact_log2
4982 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4983 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4985 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4989 gen_rtx_LSHIFTRT (mode
,
4990 XEXP (SET_SRC (x
), 0),
4993 split
= find_split_point (&SET_SRC (x
), insn
, true);
4994 if (split
&& split
!= &SET_SRC (x
))
5000 inner
= XEXP (SET_SRC (x
), 0);
5002 /* We can't optimize if either mode is a partial integer
5003 mode as we don't know how many bits are significant
5005 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5006 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5010 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5016 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5017 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5019 inner
= XEXP (SET_SRC (x
), 0);
5020 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5021 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5023 if (BITS_BIG_ENDIAN
)
5024 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5025 unsignedp
= (code
== ZERO_EXTRACT
);
5034 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5036 machine_mode mode
= GET_MODE (SET_SRC (x
));
5038 /* For unsigned, we have a choice of a shift followed by an
5039 AND or two shifts. Use two shifts for field sizes where the
5040 constant might be too large. We assume here that we can
5041 always at least get 8-bit constants in an AND insn, which is
5042 true for every current RISC. */
5044 if (unsignedp
&& len
<= 8)
5046 unsigned HOST_WIDE_INT mask
5047 = (HOST_WIDE_INT_1U
<< len
) - 1;
5051 (mode
, gen_lowpart (mode
, inner
),
5053 gen_int_mode (mask
, mode
)));
5055 split
= find_split_point (&SET_SRC (x
), insn
, true);
5056 if (split
&& split
!= &SET_SRC (x
))
5063 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5064 gen_rtx_ASHIFT (mode
,
5065 gen_lowpart (mode
, inner
),
5066 GEN_INT (GET_MODE_PRECISION (mode
)
5068 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5070 split
= find_split_point (&SET_SRC (x
), insn
, true);
5071 if (split
&& split
!= &SET_SRC (x
))
5076 /* See if this is a simple operation with a constant as the second
5077 operand. It might be that this constant is out of range and hence
5078 could be used as a split point. */
5079 if (BINARY_P (SET_SRC (x
))
5080 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5081 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5082 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5083 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5084 return &XEXP (SET_SRC (x
), 1);
5086 /* Finally, see if this is a simple operation with its first operand
5087 not in a register. The operation might require this operand in a
5088 register, so return it as a split point. We can always do this
5089 because if the first operand were another operation, we would have
5090 already found it as a split point. */
5091 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5092 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5093 return &XEXP (SET_SRC (x
), 0);
5099 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5100 it is better to write this as (not (ior A B)) so we can split it.
5101 Similarly for IOR. */
5102 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5105 gen_rtx_NOT (GET_MODE (x
),
5106 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5108 XEXP (XEXP (x
, 0), 0),
5109 XEXP (XEXP (x
, 1), 0))));
5110 return find_split_point (loc
, insn
, set_src
);
5113 /* Many RISC machines have a large set of logical insns. If the
5114 second operand is a NOT, put it first so we will try to split the
5115 other operand first. */
5116 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5118 rtx tem
= XEXP (x
, 0);
5119 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5120 SUBST (XEXP (x
, 1), tem
);
5126 /* Canonicalization can produce (minus A (mult B C)), where C is a
5127 constant. It may be better to try splitting (plus (mult B -C) A)
5128 instead if this isn't a multiply by a power of two. */
5129 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5130 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5131 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5133 machine_mode mode
= GET_MODE (x
);
5134 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5135 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5136 SUBST (*loc
, gen_rtx_PLUS (mode
,
5138 XEXP (XEXP (x
, 1), 0),
5139 gen_int_mode (other_int
,
5142 return find_split_point (loc
, insn
, set_src
);
5145 /* Split at a multiply-accumulate instruction. However if this is
5146 the SET_SRC, we likely do not have such an instruction and it's
5147 worthless to try this split. */
5149 && (GET_CODE (XEXP (x
, 0)) == MULT
5150 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5151 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5158 /* Otherwise, select our actions depending on our rtx class. */
5159 switch (GET_RTX_CLASS (code
))
5161 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5163 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5168 case RTX_COMM_ARITH
:
5170 case RTX_COMM_COMPARE
:
5171 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5176 /* Some machines have (and (shift ...) ...) insns. If X is not
5177 an AND, but XEXP (X, 0) is, use it as our split point. */
5178 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5179 return &XEXP (x
, 0);
5181 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5187 /* Otherwise, we don't have a split point. */
5192 /* Throughout X, replace FROM with TO, and return the result.
5193 The result is TO if X is FROM;
5194 otherwise the result is X, but its contents may have been modified.
5195 If they were modified, a record was made in undobuf so that
5196 undo_all will (among other things) return X to its original state.
5198 If the number of changes necessary is too much to record to undo,
5199 the excess changes are not made, so the result is invalid.
5200 The changes already made can still be undone.
5201 undobuf.num_undo is incremented for such changes, so by testing that
5202 the caller can tell whether the result is valid.
5204 `n_occurrences' is incremented each time FROM is replaced.
5206 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5208 IN_COND is nonzero if we are at the top level of a condition.
5210 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5211 by copying if `n_occurrences' is nonzero. */
5214 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5216 enum rtx_code code
= GET_CODE (x
);
5217 machine_mode op0_mode
= VOIDmode
;
5222 /* Two expressions are equal if they are identical copies of a shared
5223 RTX or if they are both registers with the same register number
5226 #define COMBINE_RTX_EQUAL_P(X,Y) \
5228 || (REG_P (X) && REG_P (Y) \
5229 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5231 /* Do not substitute into clobbers of regs -- this will never result in
5233 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5236 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5239 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5242 /* If X and FROM are the same register but different modes, they
5243 will not have been seen as equal above. However, the log links code
5244 will make a LOG_LINKS entry for that case. If we do nothing, we
5245 will try to rerecognize our original insn and, when it succeeds,
5246 we will delete the feeding insn, which is incorrect.
5248 So force this insn not to match in this (rare) case. */
5249 if (! in_dest
&& code
== REG
&& REG_P (from
)
5250 && reg_overlap_mentioned_p (x
, from
))
5251 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5253 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5254 of which may contain things that can be combined. */
5255 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5258 /* It is possible to have a subexpression appear twice in the insn.
5259 Suppose that FROM is a register that appears within TO.
5260 Then, after that subexpression has been scanned once by `subst',
5261 the second time it is scanned, TO may be found. If we were
5262 to scan TO here, we would find FROM within it and create a
5263 self-referent rtl structure which is completely wrong. */
5264 if (COMBINE_RTX_EQUAL_P (x
, to
))
5267 /* Parallel asm_operands need special attention because all of the
5268 inputs are shared across the arms. Furthermore, unsharing the
5269 rtl results in recognition failures. Failure to handle this case
5270 specially can result in circular rtl.
5272 Solve this by doing a normal pass across the first entry of the
5273 parallel, and only processing the SET_DESTs of the subsequent
5276 if (code
== PARALLEL
5277 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5278 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5280 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5282 /* If this substitution failed, this whole thing fails. */
5283 if (GET_CODE (new_rtx
) == CLOBBER
5284 && XEXP (new_rtx
, 0) == const0_rtx
)
5287 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5289 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5291 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5294 && GET_CODE (dest
) != CC0
5295 && GET_CODE (dest
) != PC
)
5297 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5299 /* If this substitution failed, this whole thing fails. */
5300 if (GET_CODE (new_rtx
) == CLOBBER
5301 && XEXP (new_rtx
, 0) == const0_rtx
)
5304 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5310 len
= GET_RTX_LENGTH (code
);
5311 fmt
= GET_RTX_FORMAT (code
);
5313 /* We don't need to process a SET_DEST that is a register, CC0,
5314 or PC, so set up to skip this common case. All other cases
5315 where we want to suppress replacing something inside a
5316 SET_SRC are handled via the IN_DEST operand. */
5318 && (REG_P (SET_DEST (x
))
5319 || GET_CODE (SET_DEST (x
)) == CC0
5320 || GET_CODE (SET_DEST (x
)) == PC
))
5323 /* Trying to simplify the operands of a widening MULT is not likely
5324 to create RTL matching a machine insn. */
5326 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5327 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5328 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5329 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5330 && REG_P (XEXP (XEXP (x
, 0), 0))
5331 && REG_P (XEXP (XEXP (x
, 1), 0))
5336 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5339 op0_mode
= GET_MODE (XEXP (x
, 0));
5341 for (i
= 0; i
< len
; i
++)
5346 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5348 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5350 new_rtx
= (unique_copy
&& n_occurrences
5351 ? copy_rtx (to
) : to
);
5356 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5359 /* If this substitution failed, this whole thing
5361 if (GET_CODE (new_rtx
) == CLOBBER
5362 && XEXP (new_rtx
, 0) == const0_rtx
)
5366 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5369 else if (fmt
[i
] == 'e')
5371 /* If this is a register being set, ignore it. */
5372 new_rtx
= XEXP (x
, i
);
5375 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5377 || code
== STRICT_LOW_PART
))
5380 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5382 /* In general, don't install a subreg involving two
5383 modes not tieable. It can worsen register
5384 allocation, and can even make invalid reload
5385 insns, since the reg inside may need to be copied
5386 from in the outside mode, and that may be invalid
5387 if it is an fp reg copied in integer mode.
5389 We allow two exceptions to this: It is valid if
5390 it is inside another SUBREG and the mode of that
5391 SUBREG and the mode of the inside of TO is
5392 tieable and it is valid if X is a SET that copies
5395 if (GET_CODE (to
) == SUBREG
5396 && ! MODES_TIEABLE_P (GET_MODE (to
),
5397 GET_MODE (SUBREG_REG (to
)))
5398 && ! (code
== SUBREG
5399 && MODES_TIEABLE_P (GET_MODE (x
),
5400 GET_MODE (SUBREG_REG (to
))))
5404 && XEXP (x
, 0) == cc0_rtx
))))
5405 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5409 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5410 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5413 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5415 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5419 /* If we are in a SET_DEST, suppress most cases unless we
5420 have gone inside a MEM, in which case we want to
5421 simplify the address. We assume here that things that
5422 are actually part of the destination have their inner
5423 parts in the first expression. This is true for SUBREG,
5424 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5425 things aside from REG and MEM that should appear in a
5427 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5429 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5430 || code
== ZERO_EXTRACT
))
5433 code
== IF_THEN_ELSE
&& i
== 0,
5436 /* If we found that we will have to reject this combination,
5437 indicate that by returning the CLOBBER ourselves, rather than
5438 an expression containing it. This will speed things up as
5439 well as prevent accidents where two CLOBBERs are considered
5440 to be equal, thus producing an incorrect simplification. */
5442 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5445 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5447 machine_mode mode
= GET_MODE (x
);
5449 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5450 GET_MODE (SUBREG_REG (x
)),
5453 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5455 else if (CONST_SCALAR_INT_P (new_rtx
)
5456 && GET_CODE (x
) == ZERO_EXTEND
)
5458 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5459 new_rtx
, GET_MODE (XEXP (x
, 0)));
5463 SUBST (XEXP (x
, i
), new_rtx
);
5468 /* Check if we are loading something from the constant pool via float
5469 extension; in this case we would undo compress_float_constant
5470 optimization and degenerate constant load to an immediate value. */
5471 if (GET_CODE (x
) == FLOAT_EXTEND
5472 && MEM_P (XEXP (x
, 0))
5473 && MEM_READONLY_P (XEXP (x
, 0)))
5475 rtx tmp
= avoid_constant_pool_reference (x
);
5480 /* Try to simplify X. If the simplification changed the code, it is likely
5481 that further simplification will help, so loop, but limit the number
5482 of repetitions that will be performed. */
5484 for (i
= 0; i
< 4; i
++)
5486 /* If X is sufficiently simple, don't bother trying to do anything
5488 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5489 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5491 if (GET_CODE (x
) == code
)
5494 code
= GET_CODE (x
);
5496 /* We no longer know the original mode of operand 0 since we
5497 have changed the form of X) */
5498 op0_mode
= VOIDmode
;
5504 /* If X is a commutative operation whose operands are not in the canonical
5505 order, use substitutions to swap them. */
5508 maybe_swap_commutative_operands (rtx x
)
5510 if (COMMUTATIVE_ARITH_P (x
)
5511 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5513 rtx temp
= XEXP (x
, 0);
5514 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5515 SUBST (XEXP (x
, 1), temp
);
5519 /* Simplify X, a piece of RTL. We just operate on the expression at the
5520 outer level; call `subst' to simplify recursively. Return the new
5523 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5524 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5528 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5531 enum rtx_code code
= GET_CODE (x
);
5532 machine_mode mode
= GET_MODE (x
);
5536 /* If this is a commutative operation, put a constant last and a complex
5537 expression first. We don't need to do this for comparisons here. */
5538 maybe_swap_commutative_operands (x
);
5540 /* Try to fold this expression in case we have constants that weren't
5543 switch (GET_RTX_CLASS (code
))
5546 if (op0_mode
== VOIDmode
)
5547 op0_mode
= GET_MODE (XEXP (x
, 0));
5548 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5551 case RTX_COMM_COMPARE
:
5553 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5554 if (cmp_mode
== VOIDmode
)
5556 cmp_mode
= GET_MODE (XEXP (x
, 1));
5557 if (cmp_mode
== VOIDmode
)
5558 cmp_mode
= op0_mode
;
5560 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5561 XEXP (x
, 0), XEXP (x
, 1));
5564 case RTX_COMM_ARITH
:
5566 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5568 case RTX_BITFIELD_OPS
:
5570 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5571 XEXP (x
, 1), XEXP (x
, 2));
5580 code
= GET_CODE (temp
);
5581 op0_mode
= VOIDmode
;
5582 mode
= GET_MODE (temp
);
5585 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5586 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5587 things. Check for cases where both arms are testing the same
5590 Don't do anything if all operands are very simple. */
5593 && ((!OBJECT_P (XEXP (x
, 0))
5594 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5595 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5596 || (!OBJECT_P (XEXP (x
, 1))
5597 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5598 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5600 && (!OBJECT_P (XEXP (x
, 0))
5601 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5602 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5604 rtx cond
, true_rtx
, false_rtx
;
5606 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5608 /* If everything is a comparison, what we have is highly unlikely
5609 to be simpler, so don't use it. */
5610 && ! (COMPARISON_P (x
)
5611 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5613 rtx cop1
= const0_rtx
;
5614 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5616 if (cond_code
== NE
&& COMPARISON_P (cond
))
5619 /* Simplify the alternative arms; this may collapse the true and
5620 false arms to store-flag values. Be careful to use copy_rtx
5621 here since true_rtx or false_rtx might share RTL with x as a
5622 result of the if_then_else_cond call above. */
5623 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5624 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5626 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5627 is unlikely to be simpler. */
5628 if (general_operand (true_rtx
, VOIDmode
)
5629 && general_operand (false_rtx
, VOIDmode
))
5631 enum rtx_code reversed
;
5633 /* Restarting if we generate a store-flag expression will cause
5634 us to loop. Just drop through in this case. */
5636 /* If the result values are STORE_FLAG_VALUE and zero, we can
5637 just make the comparison operation. */
5638 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5639 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5641 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5642 && ((reversed
= reversed_comparison_code_parts
5643 (cond_code
, cond
, cop1
, NULL
))
5645 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5648 /* Likewise, we can make the negate of a comparison operation
5649 if the result values are - STORE_FLAG_VALUE and zero. */
5650 else if (CONST_INT_P (true_rtx
)
5651 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5652 && false_rtx
== const0_rtx
)
5653 x
= simplify_gen_unary (NEG
, mode
,
5654 simplify_gen_relational (cond_code
,
5658 else if (CONST_INT_P (false_rtx
)
5659 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5660 && true_rtx
== const0_rtx
5661 && ((reversed
= reversed_comparison_code_parts
5662 (cond_code
, cond
, cop1
, NULL
))
5664 x
= simplify_gen_unary (NEG
, mode
,
5665 simplify_gen_relational (reversed
,
5670 return gen_rtx_IF_THEN_ELSE (mode
,
5671 simplify_gen_relational (cond_code
,
5676 true_rtx
, false_rtx
);
5678 code
= GET_CODE (x
);
5679 op0_mode
= VOIDmode
;
5684 /* First see if we can apply the inverse distributive law. */
5685 if (code
== PLUS
|| code
== MINUS
5686 || code
== AND
|| code
== IOR
|| code
== XOR
)
5688 x
= apply_distributive_law (x
);
5689 code
= GET_CODE (x
);
5690 op0_mode
= VOIDmode
;
5693 /* If CODE is an associative operation not otherwise handled, see if we
5694 can associate some operands. This can win if they are constants or
5695 if they are logically related (i.e. (a & b) & a). */
5696 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5697 || code
== AND
|| code
== IOR
|| code
== XOR
5698 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5699 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5700 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5702 if (GET_CODE (XEXP (x
, 0)) == code
)
5704 rtx other
= XEXP (XEXP (x
, 0), 0);
5705 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5706 rtx inner_op1
= XEXP (x
, 1);
5709 /* Make sure we pass the constant operand if any as the second
5710 one if this is a commutative operation. */
5711 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5712 std::swap (inner_op0
, inner_op1
);
5713 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5714 : code
== DIV
? MULT
5716 mode
, inner_op0
, inner_op1
);
5718 /* For commutative operations, try the other pair if that one
5720 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5722 other
= XEXP (XEXP (x
, 0), 1);
5723 inner
= simplify_binary_operation (code
, mode
,
5724 XEXP (XEXP (x
, 0), 0),
5729 return simplify_gen_binary (code
, mode
, other
, inner
);
5733 /* A little bit of algebraic simplification here. */
5737 /* Ensure that our address has any ASHIFTs converted to MULT in case
5738 address-recognizing predicates are called later. */
5739 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5740 SUBST (XEXP (x
, 0), temp
);
5744 if (op0_mode
== VOIDmode
)
5745 op0_mode
= GET_MODE (SUBREG_REG (x
));
5747 /* See if this can be moved to simplify_subreg. */
5748 if (CONSTANT_P (SUBREG_REG (x
))
5749 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5750 /* Don't call gen_lowpart if the inner mode
5751 is VOIDmode and we cannot simplify it, as SUBREG without
5752 inner mode is invalid. */
5753 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5754 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5755 return gen_lowpart (mode
, SUBREG_REG (x
));
5757 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5761 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5766 /* If op is known to have all lower bits zero, the result is zero. */
5768 && SCALAR_INT_MODE_P (mode
)
5769 && SCALAR_INT_MODE_P (op0_mode
)
5770 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5771 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5772 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5773 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5774 & GET_MODE_MASK (mode
)) == 0)
5775 return CONST0_RTX (mode
);
5778 /* Don't change the mode of the MEM if that would change the meaning
5780 if (MEM_P (SUBREG_REG (x
))
5781 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5782 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5783 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5784 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5786 /* Note that we cannot do any narrowing for non-constants since
5787 we might have been counting on using the fact that some bits were
5788 zero. We now do this in the SET. */
5793 temp
= expand_compound_operation (XEXP (x
, 0));
5795 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5796 replaced by (lshiftrt X C). This will convert
5797 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5799 if (GET_CODE (temp
) == ASHIFTRT
5800 && CONST_INT_P (XEXP (temp
, 1))
5801 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5802 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5803 INTVAL (XEXP (temp
, 1)));
5805 /* If X has only a single bit that might be nonzero, say, bit I, convert
5806 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5807 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5808 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5809 or a SUBREG of one since we'd be making the expression more
5810 complex if it was just a register. */
5813 && ! (GET_CODE (temp
) == SUBREG
5814 && REG_P (SUBREG_REG (temp
)))
5815 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5817 rtx temp1
= simplify_shift_const
5818 (NULL_RTX
, ASHIFTRT
, mode
,
5819 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5820 GET_MODE_PRECISION (mode
) - 1 - i
),
5821 GET_MODE_PRECISION (mode
) - 1 - i
);
5823 /* If all we did was surround TEMP with the two shifts, we
5824 haven't improved anything, so don't use it. Otherwise,
5825 we are better off with TEMP1. */
5826 if (GET_CODE (temp1
) != ASHIFTRT
5827 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5828 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5834 /* We can't handle truncation to a partial integer mode here
5835 because we don't know the real bitsize of the partial
5837 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5840 if (HWI_COMPUTABLE_MODE_P (mode
))
5842 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5843 GET_MODE_MASK (mode
), 0));
5845 /* We can truncate a constant value and return it. */
5846 if (CONST_INT_P (XEXP (x
, 0)))
5847 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5849 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5850 whose value is a comparison can be replaced with a subreg if
5851 STORE_FLAG_VALUE permits. */
5852 if (HWI_COMPUTABLE_MODE_P (mode
)
5853 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5854 && (temp
= get_last_value (XEXP (x
, 0)))
5855 && COMPARISON_P (temp
))
5856 return gen_lowpart (mode
, XEXP (x
, 0));
5860 /* (const (const X)) can become (const X). Do it this way rather than
5861 returning the inner CONST since CONST can be shared with a
5863 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5864 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5868 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5869 can add in an offset. find_split_point will split this address up
5870 again if it doesn't match. */
5871 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5872 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5877 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5878 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5879 bit-field and can be replaced by either a sign_extend or a
5880 sign_extract. The `and' may be a zero_extend and the two
5881 <c>, -<c> constants may be reversed. */
5882 if (GET_CODE (XEXP (x
, 0)) == XOR
5883 && CONST_INT_P (XEXP (x
, 1))
5884 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5885 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5886 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5887 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5888 && HWI_COMPUTABLE_MODE_P (mode
)
5889 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5890 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5891 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5892 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
5893 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5894 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5895 == (unsigned int) i
+ 1))))
5896 return simplify_shift_const
5897 (NULL_RTX
, ASHIFTRT
, mode
,
5898 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5899 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5900 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5901 GET_MODE_PRECISION (mode
) - (i
+ 1));
5903 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5904 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5905 the bitsize of the mode - 1. This allows simplification of
5906 "a = (b & 8) == 0;" */
5907 if (XEXP (x
, 1) == constm1_rtx
5908 && !REG_P (XEXP (x
, 0))
5909 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5910 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5911 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5912 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5913 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5914 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5915 GET_MODE_PRECISION (mode
) - 1),
5916 GET_MODE_PRECISION (mode
) - 1);
5918 /* If we are adding two things that have no bits in common, convert
5919 the addition into an IOR. This will often be further simplified,
5920 for example in cases like ((a & 1) + (a & 2)), which can
5923 if (HWI_COMPUTABLE_MODE_P (mode
)
5924 && (nonzero_bits (XEXP (x
, 0), mode
)
5925 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5927 /* Try to simplify the expression further. */
5928 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5929 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5931 /* If we could, great. If not, do not go ahead with the IOR
5932 replacement, since PLUS appears in many special purpose
5933 address arithmetic instructions. */
5934 if (GET_CODE (temp
) != CLOBBER
5935 && (GET_CODE (temp
) != IOR
5936 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5937 || XEXP (temp
, 1) != XEXP (x
, 1))
5938 && (XEXP (temp
, 0) != XEXP (x
, 1)
5939 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5943 /* Canonicalize x + x into x << 1. */
5944 if (GET_MODE_CLASS (mode
) == MODE_INT
5945 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
5946 && !side_effects_p (XEXP (x
, 0)))
5947 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
5952 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5953 (and <foo> (const_int pow2-1)) */
5954 if (GET_CODE (XEXP (x
, 1)) == AND
5955 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5956 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
5957 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5958 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5959 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5963 /* If we have (mult (plus A B) C), apply the distributive law and then
5964 the inverse distributive law to see if things simplify. This
5965 occurs mostly in addresses, often when unrolling loops. */
5967 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5969 rtx result
= distribute_and_simplify_rtx (x
, 0);
5974 /* Try simplify a*(b/c) as (a*b)/c. */
5975 if (FLOAT_MODE_P (mode
) && flag_associative_math
5976 && GET_CODE (XEXP (x
, 0)) == DIV
)
5978 rtx tem
= simplify_binary_operation (MULT
, mode
,
5979 XEXP (XEXP (x
, 0), 0),
5982 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5987 /* If this is a divide by a power of two, treat it as a shift if
5988 its first operand is a shift. */
5989 if (CONST_INT_P (XEXP (x
, 1))
5990 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5991 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5992 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5993 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5994 || GET_CODE (XEXP (x
, 0)) == ROTATE
5995 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5996 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
6000 case GT
: case GTU
: case GE
: case GEU
:
6001 case LT
: case LTU
: case LE
: case LEU
:
6002 case UNEQ
: case LTGT
:
6003 case UNGT
: case UNGE
:
6004 case UNLT
: case UNLE
:
6005 case UNORDERED
: case ORDERED
:
6006 /* If the first operand is a condition code, we can't do anything
6008 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6009 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6010 && ! CC0_P (XEXP (x
, 0))))
6012 rtx op0
= XEXP (x
, 0);
6013 rtx op1
= XEXP (x
, 1);
6014 enum rtx_code new_code
;
6016 if (GET_CODE (op0
) == COMPARE
)
6017 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6019 /* Simplify our comparison, if possible. */
6020 new_code
= simplify_comparison (code
, &op0
, &op1
);
6022 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6023 if only the low-order bit is possibly nonzero in X (such as when
6024 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6025 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6026 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6029 Remove any ZERO_EXTRACT we made when thinking this was a
6030 comparison. It may now be simpler to use, e.g., an AND. If a
6031 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6032 the call to make_compound_operation in the SET case.
6034 Don't apply these optimizations if the caller would
6035 prefer a comparison rather than a value.
6036 E.g., for the condition in an IF_THEN_ELSE most targets need
6037 an explicit comparison. */
6042 else if (STORE_FLAG_VALUE
== 1
6043 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6044 && op1
== const0_rtx
6045 && mode
== GET_MODE (op0
)
6046 && nonzero_bits (op0
, mode
) == 1)
6047 return gen_lowpart (mode
,
6048 expand_compound_operation (op0
));
6050 else if (STORE_FLAG_VALUE
== 1
6051 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6052 && op1
== const0_rtx
6053 && mode
== GET_MODE (op0
)
6054 && (num_sign_bit_copies (op0
, mode
)
6055 == GET_MODE_PRECISION (mode
)))
6057 op0
= expand_compound_operation (op0
);
6058 return simplify_gen_unary (NEG
, mode
,
6059 gen_lowpart (mode
, op0
),
6063 else if (STORE_FLAG_VALUE
== 1
6064 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6065 && op1
== const0_rtx
6066 && mode
== GET_MODE (op0
)
6067 && nonzero_bits (op0
, mode
) == 1)
6069 op0
= expand_compound_operation (op0
);
6070 return simplify_gen_binary (XOR
, mode
,
6071 gen_lowpart (mode
, op0
),
6075 else if (STORE_FLAG_VALUE
== 1
6076 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6077 && op1
== const0_rtx
6078 && mode
== GET_MODE (op0
)
6079 && (num_sign_bit_copies (op0
, mode
)
6080 == GET_MODE_PRECISION (mode
)))
6082 op0
= expand_compound_operation (op0
);
6083 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6086 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6091 else if (STORE_FLAG_VALUE
== -1
6092 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6093 && op1
== const0_rtx
6094 && mode
== GET_MODE (op0
)
6095 && (num_sign_bit_copies (op0
, mode
)
6096 == GET_MODE_PRECISION (mode
)))
6097 return gen_lowpart (mode
,
6098 expand_compound_operation (op0
));
6100 else if (STORE_FLAG_VALUE
== -1
6101 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6102 && op1
== const0_rtx
6103 && mode
== GET_MODE (op0
)
6104 && nonzero_bits (op0
, mode
) == 1)
6106 op0
= expand_compound_operation (op0
);
6107 return simplify_gen_unary (NEG
, mode
,
6108 gen_lowpart (mode
, op0
),
6112 else if (STORE_FLAG_VALUE
== -1
6113 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6114 && op1
== const0_rtx
6115 && mode
== GET_MODE (op0
)
6116 && (num_sign_bit_copies (op0
, mode
)
6117 == GET_MODE_PRECISION (mode
)))
6119 op0
= expand_compound_operation (op0
);
6120 return simplify_gen_unary (NOT
, mode
,
6121 gen_lowpart (mode
, op0
),
6125 /* If X is 0/1, (eq X 0) is X-1. */
6126 else if (STORE_FLAG_VALUE
== -1
6127 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6128 && op1
== const0_rtx
6129 && mode
== GET_MODE (op0
)
6130 && nonzero_bits (op0
, mode
) == 1)
6132 op0
= expand_compound_operation (op0
);
6133 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6136 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6137 one bit that might be nonzero, we can convert (ne x 0) to
6138 (ashift x c) where C puts the bit in the sign bit. Remove any
6139 AND with STORE_FLAG_VALUE when we are done, since we are only
6140 going to test the sign bit. */
6141 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6142 && HWI_COMPUTABLE_MODE_P (mode
)
6143 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6144 && op1
== const0_rtx
6145 && mode
== GET_MODE (op0
)
6146 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6148 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6149 expand_compound_operation (op0
),
6150 GET_MODE_PRECISION (mode
) - 1 - i
);
6151 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6157 /* If the code changed, return a whole new comparison.
6158 We also need to avoid using SUBST in cases where
6159 simplify_comparison has widened a comparison with a CONST_INT,
6160 since in that case the wider CONST_INT may fail the sanity
6161 checks in do_SUBST. */
6162 if (new_code
!= code
6163 || (CONST_INT_P (op1
)
6164 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6165 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6166 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6168 /* Otherwise, keep this operation, but maybe change its operands.
6169 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6170 SUBST (XEXP (x
, 0), op0
);
6171 SUBST (XEXP (x
, 1), op1
);
6176 return simplify_if_then_else (x
);
6182 /* If we are processing SET_DEST, we are done. */
6186 return expand_compound_operation (x
);
6189 return simplify_set (x
);
6193 return simplify_logical (x
);
6200 /* If this is a shift by a constant amount, simplify it. */
6201 if (CONST_INT_P (XEXP (x
, 1)))
6202 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6203 INTVAL (XEXP (x
, 1)));
6205 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6207 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6209 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6221 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6224 simplify_if_then_else (rtx x
)
6226 machine_mode mode
= GET_MODE (x
);
6227 rtx cond
= XEXP (x
, 0);
6228 rtx true_rtx
= XEXP (x
, 1);
6229 rtx false_rtx
= XEXP (x
, 2);
6230 enum rtx_code true_code
= GET_CODE (cond
);
6231 int comparison_p
= COMPARISON_P (cond
);
6234 enum rtx_code false_code
;
6237 /* Simplify storing of the truth value. */
6238 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6239 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6240 XEXP (cond
, 0), XEXP (cond
, 1));
6242 /* Also when the truth value has to be reversed. */
6244 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6245 && (reversed
= reversed_comparison (cond
, mode
)))
6248 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6249 in it is being compared against certain values. Get the true and false
6250 comparisons and see if that says anything about the value of each arm. */
6253 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6255 && REG_P (XEXP (cond
, 0)))
6258 rtx from
= XEXP (cond
, 0);
6259 rtx true_val
= XEXP (cond
, 1);
6260 rtx false_val
= true_val
;
6263 /* If FALSE_CODE is EQ, swap the codes and arms. */
6265 if (false_code
== EQ
)
6267 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6268 std::swap (true_rtx
, false_rtx
);
6271 /* If we are comparing against zero and the expression being tested has
6272 only a single bit that might be nonzero, that is its value when it is
6273 not equal to zero. Similarly if it is known to be -1 or 0. */
6275 if (true_code
== EQ
&& true_val
== const0_rtx
6276 && pow2p_hwi (nzb
= nonzero_bits (from
, GET_MODE (from
))))
6279 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6281 else if (true_code
== EQ
&& true_val
== const0_rtx
6282 && (num_sign_bit_copies (from
, GET_MODE (from
))
6283 == GET_MODE_PRECISION (GET_MODE (from
))))
6286 false_val
= constm1_rtx
;
6289 /* Now simplify an arm if we know the value of the register in the
6290 branch and it is used in the arm. Be careful due to the potential
6291 of locally-shared RTL. */
6293 if (reg_mentioned_p (from
, true_rtx
))
6294 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6296 pc_rtx
, pc_rtx
, 0, 0, 0);
6297 if (reg_mentioned_p (from
, false_rtx
))
6298 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6300 pc_rtx
, pc_rtx
, 0, 0, 0);
6302 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6303 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6305 true_rtx
= XEXP (x
, 1);
6306 false_rtx
= XEXP (x
, 2);
6307 true_code
= GET_CODE (cond
);
6310 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6311 reversed, do so to avoid needing two sets of patterns for
6312 subtract-and-branch insns. Similarly if we have a constant in the true
6313 arm, the false arm is the same as the first operand of the comparison, or
6314 the false arm is more complicated than the true arm. */
6317 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6318 && (true_rtx
== pc_rtx
6319 || (CONSTANT_P (true_rtx
)
6320 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6321 || true_rtx
== const0_rtx
6322 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6323 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6324 && !OBJECT_P (false_rtx
))
6325 || reg_mentioned_p (true_rtx
, false_rtx
)
6326 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6328 true_code
= reversed_comparison_code (cond
, NULL
);
6329 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6330 SUBST (XEXP (x
, 1), false_rtx
);
6331 SUBST (XEXP (x
, 2), true_rtx
);
6333 std::swap (true_rtx
, false_rtx
);
6336 /* It is possible that the conditional has been simplified out. */
6337 true_code
= GET_CODE (cond
);
6338 comparison_p
= COMPARISON_P (cond
);
6341 /* If the two arms are identical, we don't need the comparison. */
6343 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6346 /* Convert a == b ? b : a to "a". */
6347 if (true_code
== EQ
&& ! side_effects_p (cond
)
6348 && !HONOR_NANS (mode
)
6349 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6350 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6352 else if (true_code
== NE
&& ! side_effects_p (cond
)
6353 && !HONOR_NANS (mode
)
6354 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6355 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6358 /* Look for cases where we have (abs x) or (neg (abs X)). */
6360 if (GET_MODE_CLASS (mode
) == MODE_INT
6362 && XEXP (cond
, 1) == const0_rtx
6363 && GET_CODE (false_rtx
) == NEG
6364 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6365 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6366 && ! side_effects_p (true_rtx
))
6371 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6375 simplify_gen_unary (NEG
, mode
,
6376 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6382 /* Look for MIN or MAX. */
6384 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6386 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6387 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6388 && ! side_effects_p (cond
))
6393 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6396 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6399 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6402 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6407 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6408 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6409 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6410 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6411 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6412 neither 1 or -1, but it isn't worth checking for. */
6414 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6416 && GET_MODE_CLASS (mode
) == MODE_INT
6417 && ! side_effects_p (x
))
6419 rtx t
= make_compound_operation (true_rtx
, SET
);
6420 rtx f
= make_compound_operation (false_rtx
, SET
);
6421 rtx cond_op0
= XEXP (cond
, 0);
6422 rtx cond_op1
= XEXP (cond
, 1);
6423 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6424 machine_mode m
= mode
;
6425 rtx z
= 0, c1
= NULL_RTX
;
6427 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6428 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6429 || GET_CODE (t
) == ASHIFT
6430 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6431 && rtx_equal_p (XEXP (t
, 0), f
))
6432 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6434 /* If an identity-zero op is commutative, check whether there
6435 would be a match if we swapped the operands. */
6436 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6437 || GET_CODE (t
) == XOR
)
6438 && rtx_equal_p (XEXP (t
, 1), f
))
6439 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6440 else if (GET_CODE (t
) == SIGN_EXTEND
6441 && (GET_CODE (XEXP (t
, 0)) == PLUS
6442 || GET_CODE (XEXP (t
, 0)) == MINUS
6443 || GET_CODE (XEXP (t
, 0)) == IOR
6444 || GET_CODE (XEXP (t
, 0)) == XOR
6445 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6446 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6447 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6448 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6449 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6450 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6451 && (num_sign_bit_copies (f
, GET_MODE (f
))
6453 (GET_MODE_PRECISION (mode
)
6454 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6456 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6457 extend_op
= SIGN_EXTEND
;
6458 m
= GET_MODE (XEXP (t
, 0));
6460 else if (GET_CODE (t
) == SIGN_EXTEND
6461 && (GET_CODE (XEXP (t
, 0)) == PLUS
6462 || GET_CODE (XEXP (t
, 0)) == IOR
6463 || GET_CODE (XEXP (t
, 0)) == XOR
)
6464 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6465 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6466 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6467 && (num_sign_bit_copies (f
, GET_MODE (f
))
6469 (GET_MODE_PRECISION (mode
)
6470 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6472 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6473 extend_op
= SIGN_EXTEND
;
6474 m
= GET_MODE (XEXP (t
, 0));
6476 else if (GET_CODE (t
) == ZERO_EXTEND
6477 && (GET_CODE (XEXP (t
, 0)) == PLUS
6478 || GET_CODE (XEXP (t
, 0)) == MINUS
6479 || GET_CODE (XEXP (t
, 0)) == IOR
6480 || GET_CODE (XEXP (t
, 0)) == XOR
6481 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6482 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6483 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6484 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6485 && HWI_COMPUTABLE_MODE_P (mode
)
6486 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6487 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6488 && ((nonzero_bits (f
, GET_MODE (f
))
6489 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6492 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6493 extend_op
= ZERO_EXTEND
;
6494 m
= GET_MODE (XEXP (t
, 0));
6496 else if (GET_CODE (t
) == ZERO_EXTEND
6497 && (GET_CODE (XEXP (t
, 0)) == PLUS
6498 || GET_CODE (XEXP (t
, 0)) == IOR
6499 || GET_CODE (XEXP (t
, 0)) == XOR
)
6500 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6501 && HWI_COMPUTABLE_MODE_P (mode
)
6502 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6503 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6504 && ((nonzero_bits (f
, GET_MODE (f
))
6505 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6508 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6509 extend_op
= ZERO_EXTEND
;
6510 m
= GET_MODE (XEXP (t
, 0));
6515 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6516 cond_op0
, cond_op1
),
6517 pc_rtx
, pc_rtx
, 0, 0, 0);
6518 temp
= simplify_gen_binary (MULT
, m
, temp
,
6519 simplify_gen_binary (MULT
, m
, c1
,
6521 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6522 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6524 if (extend_op
!= UNKNOWN
)
6525 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6531 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6532 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6533 negation of a single bit, we can convert this operation to a shift. We
6534 can actually do this more generally, but it doesn't seem worth it. */
6536 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6537 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6538 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6539 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6540 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6541 == GET_MODE_PRECISION (mode
))
6542 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6544 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6545 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6547 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6548 non-zero bit in A is C1. */
6549 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6550 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6551 && INTEGRAL_MODE_P (GET_MODE (XEXP (cond
, 0)))
6552 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6553 == nonzero_bits (XEXP (cond
, 0), GET_MODE (XEXP (cond
, 0)))
6554 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6556 rtx val
= XEXP (cond
, 0);
6557 enum machine_mode val_mode
= GET_MODE (val
);
6558 if (val_mode
== mode
)
6560 else if (GET_MODE_PRECISION (val_mode
) < GET_MODE_PRECISION (mode
))
6561 return simplify_gen_unary (ZERO_EXTEND
, mode
, val
, val_mode
);
6567 /* Simplify X, a SET expression. Return the new expression. */
6570 simplify_set (rtx x
)
6572 rtx src
= SET_SRC (x
);
6573 rtx dest
= SET_DEST (x
);
6575 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6576 rtx_insn
*other_insn
;
6579 /* (set (pc) (return)) gets written as (return). */
6580 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6583 /* Now that we know for sure which bits of SRC we are using, see if we can
6584 simplify the expression for the object knowing that we only need the
6587 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6589 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6590 SUBST (SET_SRC (x
), src
);
6593 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6594 the comparison result and try to simplify it unless we already have used
6595 undobuf.other_insn. */
6596 if ((GET_MODE_CLASS (mode
) == MODE_CC
6597 || GET_CODE (src
) == COMPARE
6599 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6600 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6601 && COMPARISON_P (*cc_use
)
6602 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6604 enum rtx_code old_code
= GET_CODE (*cc_use
);
6605 enum rtx_code new_code
;
6607 int other_changed
= 0;
6608 rtx inner_compare
= NULL_RTX
;
6609 machine_mode compare_mode
= GET_MODE (dest
);
6611 if (GET_CODE (src
) == COMPARE
)
6613 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6614 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6616 inner_compare
= op0
;
6617 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6621 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6623 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6626 new_code
= old_code
;
6627 else if (!CONSTANT_P (tmp
))
6629 new_code
= GET_CODE (tmp
);
6630 op0
= XEXP (tmp
, 0);
6631 op1
= XEXP (tmp
, 1);
6635 rtx pat
= PATTERN (other_insn
);
6636 undobuf
.other_insn
= other_insn
;
6637 SUBST (*cc_use
, tmp
);
6639 /* Attempt to simplify CC user. */
6640 if (GET_CODE (pat
) == SET
)
6642 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6643 if (new_rtx
!= NULL_RTX
)
6644 SUBST (SET_SRC (pat
), new_rtx
);
6647 /* Convert X into a no-op move. */
6648 SUBST (SET_DEST (x
), pc_rtx
);
6649 SUBST (SET_SRC (x
), pc_rtx
);
6653 /* Simplify our comparison, if possible. */
6654 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6656 #ifdef SELECT_CC_MODE
6657 /* If this machine has CC modes other than CCmode, check to see if we
6658 need to use a different CC mode here. */
6659 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6660 compare_mode
= GET_MODE (op0
);
6661 else if (inner_compare
6662 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6663 && new_code
== old_code
6664 && op0
== XEXP (inner_compare
, 0)
6665 && op1
== XEXP (inner_compare
, 1))
6666 compare_mode
= GET_MODE (inner_compare
);
6668 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6670 /* If the mode changed, we have to change SET_DEST, the mode in the
6671 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6672 a hard register, just build new versions with the proper mode. If it
6673 is a pseudo, we lose unless it is only time we set the pseudo, in
6674 which case we can safely change its mode. */
6675 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6677 if (can_change_dest_mode (dest
, 0, compare_mode
))
6679 unsigned int regno
= REGNO (dest
);
6682 if (regno
< FIRST_PSEUDO_REGISTER
)
6683 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6686 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6687 new_dest
= regno_reg_rtx
[regno
];
6690 SUBST (SET_DEST (x
), new_dest
);
6691 SUBST (XEXP (*cc_use
, 0), new_dest
);
6697 #endif /* SELECT_CC_MODE */
6699 /* If the code changed, we have to build a new comparison in
6700 undobuf.other_insn. */
6701 if (new_code
!= old_code
)
6703 int other_changed_previously
= other_changed
;
6704 unsigned HOST_WIDE_INT mask
;
6705 rtx old_cc_use
= *cc_use
;
6707 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6711 /* If the only change we made was to change an EQ into an NE or
6712 vice versa, OP0 has only one bit that might be nonzero, and OP1
6713 is zero, check if changing the user of the condition code will
6714 produce a valid insn. If it won't, we can keep the original code
6715 in that insn by surrounding our operation with an XOR. */
6717 if (((old_code
== NE
&& new_code
== EQ
)
6718 || (old_code
== EQ
&& new_code
== NE
))
6719 && ! other_changed_previously
&& op1
== const0_rtx
6720 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6721 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6723 rtx pat
= PATTERN (other_insn
), note
= 0;
6725 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6726 && ! check_asm_operands (pat
)))
6728 *cc_use
= old_cc_use
;
6731 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6739 undobuf
.other_insn
= other_insn
;
6741 /* Don't generate a compare of a CC with 0, just use that CC. */
6742 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6744 SUBST (SET_SRC (x
), op0
);
6747 /* Otherwise, if we didn't previously have the same COMPARE we
6748 want, create it from scratch. */
6749 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6750 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6752 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6758 /* Get SET_SRC in a form where we have placed back any
6759 compound expressions. Then do the checks below. */
6760 src
= make_compound_operation (src
, SET
);
6761 SUBST (SET_SRC (x
), src
);
6764 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6765 and X being a REG or (subreg (reg)), we may be able to convert this to
6766 (set (subreg:m2 x) (op)).
6768 We can always do this if M1 is narrower than M2 because that means that
6769 we only care about the low bits of the result.
6771 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6772 perform a narrower operation than requested since the high-order bits will
6773 be undefined. On machine where it is defined, this transformation is safe
6774 as long as M1 and M2 have the same number of words. */
6776 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6777 && !OBJECT_P (SUBREG_REG (src
))
6778 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6780 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6781 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6782 && (WORD_REGISTER_OPERATIONS
6783 || (GET_MODE_SIZE (GET_MODE (src
))
6784 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6785 #ifdef CANNOT_CHANGE_MODE_CLASS
6786 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6787 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6788 GET_MODE (SUBREG_REG (src
)),
6792 || (GET_CODE (dest
) == SUBREG
6793 && REG_P (SUBREG_REG (dest
)))))
6795 SUBST (SET_DEST (x
),
6796 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6798 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6800 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6803 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6806 && GET_CODE (src
) == SUBREG
6807 && subreg_lowpart_p (src
)
6808 && (GET_MODE_PRECISION (GET_MODE (src
))
6809 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6811 rtx inner
= SUBREG_REG (src
);
6812 machine_mode inner_mode
= GET_MODE (inner
);
6814 /* Here we make sure that we don't have a sign bit on. */
6815 if (val_signbit_known_clear_p (GET_MODE (src
),
6816 nonzero_bits (inner
, inner_mode
)))
6818 SUBST (SET_SRC (x
), inner
);
6823 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6824 would require a paradoxical subreg. Replace the subreg with a
6825 zero_extend to avoid the reload that would otherwise be required. */
6827 enum rtx_code extend_op
;
6828 if (paradoxical_subreg_p (src
)
6829 && MEM_P (SUBREG_REG (src
))
6830 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6833 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6838 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6839 are comparing an item known to be 0 or -1 against 0, use a logical
6840 operation instead. Check for one of the arms being an IOR of the other
6841 arm with some value. We compute three terms to be IOR'ed together. In
6842 practice, at most two will be nonzero. Then we do the IOR's. */
6844 if (GET_CODE (dest
) != PC
6845 && GET_CODE (src
) == IF_THEN_ELSE
6846 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6847 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6848 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6849 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6850 && (!HAVE_conditional_move
6851 || ! can_conditionally_move_p (GET_MODE (src
)))
6852 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6853 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6854 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6855 && ! side_effects_p (src
))
6857 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6858 ? XEXP (src
, 1) : XEXP (src
, 2));
6859 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6860 ? XEXP (src
, 2) : XEXP (src
, 1));
6861 rtx term1
= const0_rtx
, term2
, term3
;
6863 if (GET_CODE (true_rtx
) == IOR
6864 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6865 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6866 else if (GET_CODE (true_rtx
) == IOR
6867 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6868 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6869 else if (GET_CODE (false_rtx
) == IOR
6870 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6871 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6872 else if (GET_CODE (false_rtx
) == IOR
6873 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6874 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6876 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6877 XEXP (XEXP (src
, 0), 0), true_rtx
);
6878 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6879 simplify_gen_unary (NOT
, GET_MODE (src
),
6880 XEXP (XEXP (src
, 0), 0),
6885 simplify_gen_binary (IOR
, GET_MODE (src
),
6886 simplify_gen_binary (IOR
, GET_MODE (src
),
6893 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6894 whole thing fail. */
6895 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6897 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6900 /* Convert this into a field assignment operation, if possible. */
6901 return make_field_assignment (x
);
6904 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6908 simplify_logical (rtx x
)
6910 machine_mode mode
= GET_MODE (x
);
6911 rtx op0
= XEXP (x
, 0);
6912 rtx op1
= XEXP (x
, 1);
6914 switch (GET_CODE (x
))
6917 /* We can call simplify_and_const_int only if we don't lose
6918 any (sign) bits when converting INTVAL (op1) to
6919 "unsigned HOST_WIDE_INT". */
6920 if (CONST_INT_P (op1
)
6921 && (HWI_COMPUTABLE_MODE_P (mode
)
6922 || INTVAL (op1
) > 0))
6924 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6925 if (GET_CODE (x
) != AND
)
6932 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6933 apply the distributive law and then the inverse distributive
6934 law to see if things simplify. */
6935 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6937 rtx result
= distribute_and_simplify_rtx (x
, 0);
6941 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6943 rtx result
= distribute_and_simplify_rtx (x
, 1);
6950 /* If we have (ior (and A B) C), apply the distributive law and then
6951 the inverse distributive law to see if things simplify. */
6953 if (GET_CODE (op0
) == AND
)
6955 rtx result
= distribute_and_simplify_rtx (x
, 0);
6960 if (GET_CODE (op1
) == AND
)
6962 rtx result
= distribute_and_simplify_rtx (x
, 1);
6975 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6976 operations" because they can be replaced with two more basic operations.
6977 ZERO_EXTEND is also considered "compound" because it can be replaced with
6978 an AND operation, which is simpler, though only one operation.
6980 The function expand_compound_operation is called with an rtx expression
6981 and will convert it to the appropriate shifts and AND operations,
6982 simplifying at each stage.
6984 The function make_compound_operation is called to convert an expression
6985 consisting of shifts and ANDs into the equivalent compound expression.
6986 It is the inverse of this function, loosely speaking. */
6989 expand_compound_operation (rtx x
)
6991 unsigned HOST_WIDE_INT pos
= 0, len
;
6993 unsigned int modewidth
;
6996 switch (GET_CODE (x
))
7002 /* We can't necessarily use a const_int for a multiword mode;
7003 it depends on implicitly extending the value.
7004 Since we don't know the right way to extend it,
7005 we can't tell whether the implicit way is right.
7007 Even for a mode that is no wider than a const_int,
7008 we can't win, because we need to sign extend one of its bits through
7009 the rest of it, and we don't know which bit. */
7010 if (CONST_INT_P (XEXP (x
, 0)))
7013 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7014 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7015 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7016 reloaded. If not for that, MEM's would very rarely be safe.
7018 Reject MODEs bigger than a word, because we might not be able
7019 to reference a two-register group starting with an arbitrary register
7020 (and currently gen_lowpart might crash for a SUBREG). */
7022 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7025 /* Reject MODEs that aren't scalar integers because turning vector
7026 or complex modes into shifts causes problems. */
7028 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7031 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7032 /* If the inner object has VOIDmode (the only way this can happen
7033 is if it is an ASM_OPERANDS), we can't do anything since we don't
7034 know how much masking to do. */
7046 /* If the operand is a CLOBBER, just return it. */
7047 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7050 if (!CONST_INT_P (XEXP (x
, 1))
7051 || !CONST_INT_P (XEXP (x
, 2))
7052 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7055 /* Reject MODEs that aren't scalar integers because turning vector
7056 or complex modes into shifts causes problems. */
7058 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7061 len
= INTVAL (XEXP (x
, 1));
7062 pos
= INTVAL (XEXP (x
, 2));
7064 /* This should stay within the object being extracted, fail otherwise. */
7065 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7068 if (BITS_BIG_ENDIAN
)
7069 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7076 /* Convert sign extension to zero extension, if we know that the high
7077 bit is not set, as this is easier to optimize. It will be converted
7078 back to cheaper alternative in make_extraction. */
7079 if (GET_CODE (x
) == SIGN_EXTEND
7080 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7081 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7082 & ~(((unsigned HOST_WIDE_INT
)
7083 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7087 machine_mode mode
= GET_MODE (x
);
7088 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7089 rtx temp2
= expand_compound_operation (temp
);
7091 /* Make sure this is a profitable operation. */
7092 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7093 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7095 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7096 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7102 /* We can optimize some special cases of ZERO_EXTEND. */
7103 if (GET_CODE (x
) == ZERO_EXTEND
)
7105 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7106 know that the last value didn't have any inappropriate bits
7108 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7109 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7110 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7111 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7112 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7113 return XEXP (XEXP (x
, 0), 0);
7115 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7116 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7117 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7118 && subreg_lowpart_p (XEXP (x
, 0))
7119 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7120 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7121 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7122 return SUBREG_REG (XEXP (x
, 0));
7124 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7125 is a comparison and STORE_FLAG_VALUE permits. This is like
7126 the first case, but it works even when GET_MODE (x) is larger
7127 than HOST_WIDE_INT. */
7128 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7129 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7130 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7131 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7132 <= HOST_BITS_PER_WIDE_INT
)
7133 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7134 return XEXP (XEXP (x
, 0), 0);
7136 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7137 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7138 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7139 && subreg_lowpart_p (XEXP (x
, 0))
7140 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7141 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7142 <= HOST_BITS_PER_WIDE_INT
)
7143 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7144 return SUBREG_REG (XEXP (x
, 0));
7148 /* If we reach here, we want to return a pair of shifts. The inner
7149 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7150 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7151 logical depending on the value of UNSIGNEDP.
7153 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7154 converted into an AND of a shift.
7156 We must check for the case where the left shift would have a negative
7157 count. This can happen in a case like (x >> 31) & 255 on machines
7158 that can't shift by a constant. On those machines, we would first
7159 combine the shift with the AND to produce a variable-position
7160 extraction. Then the constant of 31 would be substituted in
7161 to produce such a position. */
7163 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7164 if (modewidth
>= pos
+ len
)
7166 machine_mode mode
= GET_MODE (x
);
7167 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7168 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7170 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7171 tem
, modewidth
- pos
- len
);
7172 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7173 mode
, tem
, modewidth
- len
);
7175 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7176 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7177 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7180 (HOST_WIDE_INT_1U
<< len
) - 1);
7182 /* Any other cases we can't handle. */
7185 /* If we couldn't do this for some reason, return the original
7187 if (GET_CODE (tem
) == CLOBBER
)
7193 /* X is a SET which contains an assignment of one object into
7194 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7195 or certain SUBREGS). If possible, convert it into a series of
7198 We half-heartedly support variable positions, but do not at all
7199 support variable lengths. */
7202 expand_field_assignment (const_rtx x
)
7205 rtx pos
; /* Always counts from low bit. */
7207 rtx mask
, cleared
, masked
;
7208 machine_mode compute_mode
;
7210 /* Loop until we find something we can't simplify. */
7213 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7214 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7216 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7217 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7218 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7220 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7221 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7223 inner
= XEXP (SET_DEST (x
), 0);
7224 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7225 pos
= XEXP (SET_DEST (x
), 2);
7227 /* A constant position should stay within the width of INNER. */
7228 if (CONST_INT_P (pos
)
7229 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7232 if (BITS_BIG_ENDIAN
)
7234 if (CONST_INT_P (pos
))
7235 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7237 else if (GET_CODE (pos
) == MINUS
7238 && CONST_INT_P (XEXP (pos
, 1))
7239 && (INTVAL (XEXP (pos
, 1))
7240 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7241 /* If position is ADJUST - X, new position is X. */
7242 pos
= XEXP (pos
, 0);
7245 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7246 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7247 gen_int_mode (prec
- len
,
7254 /* A SUBREG between two modes that occupy the same numbers of words
7255 can be done by moving the SUBREG to the source. */
7256 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7257 /* We need SUBREGs to compute nonzero_bits properly. */
7258 && nonzero_sign_valid
7259 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7260 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7261 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7262 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7264 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7266 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7273 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7274 inner
= SUBREG_REG (inner
);
7276 compute_mode
= GET_MODE (inner
);
7278 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7279 if (! SCALAR_INT_MODE_P (compute_mode
))
7283 /* Don't do anything for vector or complex integral types. */
7284 if (! FLOAT_MODE_P (compute_mode
))
7287 /* Try to find an integral mode to pun with. */
7288 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7289 if (imode
== BLKmode
)
7292 compute_mode
= imode
;
7293 inner
= gen_lowpart (imode
, inner
);
7296 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7297 if (len
>= HOST_BITS_PER_WIDE_INT
)
7300 /* Don't try to compute in too wide unsupported modes. */
7301 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7304 /* Now compute the equivalent expression. Make a copy of INNER
7305 for the SET_DEST in case it is a MEM into which we will substitute;
7306 we don't want shared RTL in that case. */
7307 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7309 cleared
= simplify_gen_binary (AND
, compute_mode
,
7310 simplify_gen_unary (NOT
, compute_mode
,
7311 simplify_gen_binary (ASHIFT
,
7316 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7317 simplify_gen_binary (
7319 gen_lowpart (compute_mode
, SET_SRC (x
)),
7323 x
= gen_rtx_SET (copy_rtx (inner
),
7324 simplify_gen_binary (IOR
, compute_mode
,
7331 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7332 it is an RTX that represents the (variable) starting position; otherwise,
7333 POS is the (constant) starting bit position. Both are counted from the LSB.
7335 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7337 IN_DEST is nonzero if this is a reference in the destination of a SET.
7338 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7339 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7342 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7343 ZERO_EXTRACT should be built even for bits starting at bit 0.
7345 MODE is the desired mode of the result (if IN_DEST == 0).
7347 The result is an RTX for the extraction or NULL_RTX if the target
7351 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7352 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7353 int in_dest
, int in_compare
)
7355 /* This mode describes the size of the storage area
7356 to fetch the overall value from. Within that, we
7357 ignore the POS lowest bits, etc. */
7358 machine_mode is_mode
= GET_MODE (inner
);
7359 machine_mode inner_mode
;
7360 machine_mode wanted_inner_mode
;
7361 machine_mode wanted_inner_reg_mode
= word_mode
;
7362 machine_mode pos_mode
= word_mode
;
7363 machine_mode extraction_mode
= word_mode
;
7364 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7366 rtx orig_pos_rtx
= pos_rtx
;
7367 HOST_WIDE_INT orig_pos
;
7369 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7370 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7372 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7374 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7375 consider just the QI as the memory to extract from.
7376 The subreg adds or removes high bits; its mode is
7377 irrelevant to the meaning of this extraction,
7378 since POS and LEN count from the lsb. */
7379 if (MEM_P (SUBREG_REG (inner
)))
7380 is_mode
= GET_MODE (SUBREG_REG (inner
));
7381 inner
= SUBREG_REG (inner
);
7383 else if (GET_CODE (inner
) == ASHIFT
7384 && CONST_INT_P (XEXP (inner
, 1))
7385 && pos_rtx
== 0 && pos
== 0
7386 && len
> UINTVAL (XEXP (inner
, 1)))
7388 /* We're extracting the least significant bits of an rtx
7389 (ashift X (const_int C)), where LEN > C. Extract the
7390 least significant (LEN - C) bits of X, giving an rtx
7391 whose mode is MODE, then shift it left C times. */
7392 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7393 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7394 unsignedp
, in_dest
, in_compare
);
7396 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7398 else if (GET_CODE (inner
) == TRUNCATE
)
7399 inner
= XEXP (inner
, 0);
7401 inner_mode
= GET_MODE (inner
);
7403 /* See if this can be done without an extraction. We never can if the
7404 width of the field is not the same as that of some integer mode. For
7405 registers, we can only avoid the extraction if the position is at the
7406 low-order bit and this is either not in the destination or we have the
7407 appropriate STRICT_LOW_PART operation available.
7409 For MEM, we can avoid an extract if the field starts on an appropriate
7410 boundary and we can change the mode of the memory reference. */
7412 if (tmode
!= BLKmode
7413 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7415 && (pos
== 0 || REG_P (inner
))
7416 && (inner_mode
== tmode
7418 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7419 || reg_truncated_to_mode (tmode
, inner
))
7422 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7423 || (MEM_P (inner
) && pos_rtx
== 0
7425 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7426 : BITS_PER_UNIT
)) == 0
7427 /* We can't do this if we are widening INNER_MODE (it
7428 may not be aligned, for one thing). */
7429 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7430 && (inner_mode
== tmode
7431 || (! mode_dependent_address_p (XEXP (inner
, 0),
7432 MEM_ADDR_SPACE (inner
))
7433 && ! MEM_VOLATILE_P (inner
))))))
7435 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7436 field. If the original and current mode are the same, we need not
7437 adjust the offset. Otherwise, we do if bytes big endian.
7439 If INNER is not a MEM, get a piece consisting of just the field
7440 of interest (in this case POS % BITS_PER_WORD must be 0). */
7444 HOST_WIDE_INT offset
;
7446 /* POS counts from lsb, but make OFFSET count in memory order. */
7447 if (BYTES_BIG_ENDIAN
)
7448 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7450 offset
= pos
/ BITS_PER_UNIT
;
7452 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7454 else if (REG_P (inner
))
7456 if (tmode
!= inner_mode
)
7458 /* We can't call gen_lowpart in a DEST since we
7459 always want a SUBREG (see below) and it would sometimes
7460 return a new hard register. */
7463 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7465 if (WORDS_BIG_ENDIAN
7466 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7467 final_word
= ((GET_MODE_SIZE (inner_mode
)
7468 - GET_MODE_SIZE (tmode
))
7469 / UNITS_PER_WORD
) - final_word
;
7471 final_word
*= UNITS_PER_WORD
;
7472 if (BYTES_BIG_ENDIAN
&&
7473 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7474 final_word
+= (GET_MODE_SIZE (inner_mode
)
7475 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7477 /* Avoid creating invalid subregs, for example when
7478 simplifying (x>>32)&255. */
7479 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7482 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7485 new_rtx
= gen_lowpart (tmode
, inner
);
7491 new_rtx
= force_to_mode (inner
, tmode
,
7492 len
>= HOST_BITS_PER_WIDE_INT
7494 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7496 /* If this extraction is going into the destination of a SET,
7497 make a STRICT_LOW_PART unless we made a MEM. */
7500 return (MEM_P (new_rtx
) ? new_rtx
7501 : (GET_CODE (new_rtx
) != SUBREG
7502 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7503 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7508 if (CONST_SCALAR_INT_P (new_rtx
))
7509 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7510 mode
, new_rtx
, tmode
);
7512 /* If we know that no extraneous bits are set, and that the high
7513 bit is not set, convert the extraction to the cheaper of
7514 sign and zero extension, that are equivalent in these cases. */
7515 if (flag_expensive_optimizations
7516 && (HWI_COMPUTABLE_MODE_P (tmode
)
7517 && ((nonzero_bits (new_rtx
, tmode
)
7518 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7521 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7522 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7524 /* Prefer ZERO_EXTENSION, since it gives more information to
7526 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7527 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7532 /* Otherwise, sign- or zero-extend unless we already are in the
7535 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7539 /* Unless this is a COMPARE or we have a funny memory reference,
7540 don't do anything with zero-extending field extracts starting at
7541 the low-order bit since they are simple AND operations. */
7542 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7543 && ! in_compare
&& unsignedp
)
7546 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7547 if the position is not a constant and the length is not 1. In all
7548 other cases, we would only be going outside our object in cases when
7549 an original shift would have been undefined. */
7551 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7552 || (pos_rtx
!= 0 && len
!= 1)))
7555 enum extraction_pattern pattern
= (in_dest
? EP_insv
7556 : unsignedp
? EP_extzv
: EP_extv
);
7558 /* If INNER is not from memory, we want it to have the mode of a register
7559 extraction pattern's structure operand, or word_mode if there is no
7560 such pattern. The same applies to extraction_mode and pos_mode
7561 and their respective operands.
7563 For memory, assume that the desired extraction_mode and pos_mode
7564 are the same as for a register operation, since at present we don't
7565 have named patterns for aligned memory structures. */
7566 struct extraction_insn insn
;
7567 if (get_best_reg_extraction_insn (&insn
, pattern
,
7568 GET_MODE_BITSIZE (inner_mode
), mode
))
7570 wanted_inner_reg_mode
= insn
.struct_mode
;
7571 pos_mode
= insn
.pos_mode
;
7572 extraction_mode
= insn
.field_mode
;
7575 /* Never narrow an object, since that might not be safe. */
7577 if (mode
!= VOIDmode
7578 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7579 extraction_mode
= mode
;
7582 wanted_inner_mode
= wanted_inner_reg_mode
;
7585 /* Be careful not to go beyond the extracted object and maintain the
7586 natural alignment of the memory. */
7587 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7588 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7589 > GET_MODE_BITSIZE (wanted_inner_mode
))
7591 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7592 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7598 if (BITS_BIG_ENDIAN
)
7600 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7601 BITS_BIG_ENDIAN style. If position is constant, compute new
7602 position. Otherwise, build subtraction.
7603 Note that POS is relative to the mode of the original argument.
7604 If it's a MEM we need to recompute POS relative to that.
7605 However, if we're extracting from (or inserting into) a register,
7606 we want to recompute POS relative to wanted_inner_mode. */
7607 int width
= (MEM_P (inner
)
7608 ? GET_MODE_BITSIZE (is_mode
)
7609 : GET_MODE_BITSIZE (wanted_inner_mode
));
7612 pos
= width
- len
- pos
;
7615 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7616 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7618 /* POS may be less than 0 now, but we check for that below.
7619 Note that it can only be less than 0 if !MEM_P (inner). */
7622 /* If INNER has a wider mode, and this is a constant extraction, try to
7623 make it smaller and adjust the byte to point to the byte containing
7625 if (wanted_inner_mode
!= VOIDmode
7626 && inner_mode
!= wanted_inner_mode
7628 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7630 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7631 && ! MEM_VOLATILE_P (inner
))
7635 /* The computations below will be correct if the machine is big
7636 endian in both bits and bytes or little endian in bits and bytes.
7637 If it is mixed, we must adjust. */
7639 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7640 adjust OFFSET to compensate. */
7641 if (BYTES_BIG_ENDIAN
7642 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7643 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7645 /* We can now move to the desired byte. */
7646 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7647 * GET_MODE_SIZE (wanted_inner_mode
);
7648 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7650 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7651 && is_mode
!= wanted_inner_mode
)
7652 offset
= (GET_MODE_SIZE (is_mode
)
7653 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7655 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7658 /* If INNER is not memory, get it into the proper mode. If we are changing
7659 its mode, POS must be a constant and smaller than the size of the new
7661 else if (!MEM_P (inner
))
7663 /* On the LHS, don't create paradoxical subregs implicitely truncating
7664 the register unless TRULY_NOOP_TRUNCATION. */
7666 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7670 if (GET_MODE (inner
) != wanted_inner_mode
7672 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7678 inner
= force_to_mode (inner
, wanted_inner_mode
,
7680 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7682 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7687 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7688 have to zero extend. Otherwise, we can just use a SUBREG. */
7690 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7692 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7693 GET_MODE (pos_rtx
));
7695 /* If we know that no extraneous bits are set, and that the high
7696 bit is not set, convert extraction to cheaper one - either
7697 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7699 if (flag_expensive_optimizations
7700 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7701 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7702 & ~(((unsigned HOST_WIDE_INT
)
7703 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7707 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7708 GET_MODE (pos_rtx
));
7710 /* Prefer ZERO_EXTENSION, since it gives more information to
7712 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7713 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7719 /* Make POS_RTX unless we already have it and it is correct. If we don't
7720 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7722 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7723 pos_rtx
= orig_pos_rtx
;
7725 else if (pos_rtx
== 0)
7726 pos_rtx
= GEN_INT (pos
);
7728 /* Make the required operation. See if we can use existing rtx. */
7729 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7730 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7732 new_rtx
= gen_lowpart (mode
, new_rtx
);
7737 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7738 with any other operations in X. Return X without that shift if so. */
7741 extract_left_shift (rtx x
, int count
)
7743 enum rtx_code code
= GET_CODE (x
);
7744 machine_mode mode
= GET_MODE (x
);
7750 /* This is the shift itself. If it is wide enough, we will return
7751 either the value being shifted if the shift count is equal to
7752 COUNT or a shift for the difference. */
7753 if (CONST_INT_P (XEXP (x
, 1))
7754 && INTVAL (XEXP (x
, 1)) >= count
)
7755 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7756 INTVAL (XEXP (x
, 1)) - count
);
7760 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7761 return simplify_gen_unary (code
, mode
, tem
, mode
);
7765 case PLUS
: case IOR
: case XOR
: case AND
:
7766 /* If we can safely shift this constant and we find the inner shift,
7767 make a new operation. */
7768 if (CONST_INT_P (XEXP (x
, 1))
7769 && (UINTVAL (XEXP (x
, 1))
7770 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7771 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7773 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7774 return simplify_gen_binary (code
, mode
, tem
,
7775 gen_int_mode (val
, mode
));
7786 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7787 level of the expression and MODE is its mode. IN_CODE is as for
7788 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7789 that should be used when recursing on operands of *X_PTR.
7791 There are two possible actions:
7793 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7794 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7796 - Return a new rtx, which the caller returns directly. */
7799 make_compound_operation_int (machine_mode mode
, rtx
*x_ptr
,
7800 enum rtx_code in_code
,
7801 enum rtx_code
*next_code_ptr
)
7804 enum rtx_code next_code
= *next_code_ptr
;
7805 enum rtx_code code
= GET_CODE (x
);
7806 int mode_width
= GET_MODE_PRECISION (mode
);
7811 bool equality_comparison
= false;
7815 equality_comparison
= true;
7819 /* Process depending on the code of this operation. If NEW is set
7820 nonzero, it will be returned. */
7825 /* Convert shifts by constants into multiplications if inside
7827 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7828 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7829 && INTVAL (XEXP (x
, 1)) >= 0)
7831 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7832 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7834 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7835 if (GET_CODE (new_rtx
) == NEG
)
7837 new_rtx
= XEXP (new_rtx
, 0);
7840 multval
= trunc_int_for_mode (multval
, mode
);
7841 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7848 lhs
= make_compound_operation (lhs
, next_code
);
7849 rhs
= make_compound_operation (rhs
, next_code
);
7850 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
7852 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7854 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7856 else if (GET_CODE (lhs
) == MULT
7857 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7859 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7860 simplify_gen_unary (NEG
, mode
,
7863 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7867 SUBST (XEXP (x
, 0), lhs
);
7868 SUBST (XEXP (x
, 1), rhs
);
7870 maybe_swap_commutative_operands (x
);
7876 lhs
= make_compound_operation (lhs
, next_code
);
7877 rhs
= make_compound_operation (rhs
, next_code
);
7878 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
7880 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7882 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7884 else if (GET_CODE (rhs
) == MULT
7885 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7887 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7888 simplify_gen_unary (NEG
, mode
,
7891 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7895 SUBST (XEXP (x
, 0), lhs
);
7896 SUBST (XEXP (x
, 1), rhs
);
7901 /* If the second operand is not a constant, we can't do anything
7903 if (!CONST_INT_P (XEXP (x
, 1)))
7906 /* If the constant is a power of two minus one and the first operand
7907 is a logical right shift, make an extraction. */
7908 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7909 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7911 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7912 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7913 0, in_code
== COMPARE
);
7916 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7917 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7918 && subreg_lowpart_p (XEXP (x
, 0))
7919 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7920 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7922 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
7923 machine_mode inner_mode
= GET_MODE (inner_x0
);
7924 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
7925 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
7927 i
, 1, 0, in_code
== COMPARE
);
7931 /* If we narrowed the mode when dropping the subreg, then
7932 we must zero-extend to keep the semantics of the AND. */
7933 if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
7935 else if (SCALAR_INT_MODE_P (inner_mode
))
7936 new_rtx
= simplify_gen_unary (ZERO_EXTEND
, mode
,
7937 new_rtx
, inner_mode
);
7942 /* If that didn't give anything, see if the AND simplifies on
7944 if (!new_rtx
&& i
>= 0)
7946 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7947 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
7948 0, in_code
== COMPARE
);
7951 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7952 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7953 || GET_CODE (XEXP (x
, 0)) == IOR
)
7954 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7955 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7956 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7958 /* Apply the distributive law, and then try to make extractions. */
7959 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7960 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7962 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7964 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7967 /* If we are have (and (rotate X C) M) and C is larger than the number
7968 of bits in M, this is an extraction. */
7970 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7971 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7972 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7973 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7975 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7976 new_rtx
= make_extraction (mode
, new_rtx
,
7977 (GET_MODE_PRECISION (mode
)
7978 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7979 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7982 /* On machines without logical shifts, if the operand of the AND is
7983 a logical shift and our mask turns off all the propagated sign
7984 bits, we can replace the logical shift with an arithmetic shift. */
7985 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7986 && !have_insn_for (LSHIFTRT
, mode
)
7987 && have_insn_for (ASHIFTRT
, mode
)
7988 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7989 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7990 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7991 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7993 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7995 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7996 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7998 gen_rtx_ASHIFTRT (mode
,
7999 make_compound_operation
8000 (XEXP (XEXP (x
, 0), 0), next_code
),
8001 XEXP (XEXP (x
, 0), 1)));
8004 /* If the constant is one less than a power of two, this might be
8005 representable by an extraction even if no shift is present.
8006 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8007 we are in a COMPARE. */
8008 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8009 new_rtx
= make_extraction (mode
,
8010 make_compound_operation (XEXP (x
, 0),
8012 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8014 /* If we are in a comparison and this is an AND with a power of two,
8015 convert this into the appropriate bit extract. */
8016 else if (in_code
== COMPARE
8017 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8018 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8019 new_rtx
= make_extraction (mode
,
8020 make_compound_operation (XEXP (x
, 0),
8022 i
, NULL_RTX
, 1, 1, 0, 1);
8024 /* If the one operand is a paradoxical subreg of a register or memory and
8025 the constant (limited to the smaller mode) has only zero bits where
8026 the sub expression has known zero bits, this can be expressed as
8028 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8032 sub
= XEXP (XEXP (x
, 0), 0);
8033 machine_mode sub_mode
= GET_MODE (sub
);
8034 if ((REG_P (sub
) || MEM_P (sub
))
8035 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8037 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8038 unsigned HOST_WIDE_INT mask
;
8040 /* original AND constant with all the known zero bits set */
8041 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8042 if ((mask
& mode_mask
) == mode_mask
)
8044 new_rtx
= make_compound_operation (sub
, next_code
);
8045 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8046 GET_MODE_PRECISION (sub_mode
),
8047 1, 0, in_code
== COMPARE
);
8055 /* If the sign bit is known to be zero, replace this with an
8056 arithmetic shift. */
8057 if (have_insn_for (ASHIFTRT
, mode
)
8058 && ! have_insn_for (LSHIFTRT
, mode
)
8059 && mode_width
<= HOST_BITS_PER_WIDE_INT
8060 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8062 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8063 make_compound_operation (XEXP (x
, 0),
8075 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8076 this is a SIGN_EXTRACT. */
8077 if (CONST_INT_P (rhs
)
8078 && GET_CODE (lhs
) == ASHIFT
8079 && CONST_INT_P (XEXP (lhs
, 1))
8080 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8081 && INTVAL (XEXP (lhs
, 1)) >= 0
8082 && INTVAL (rhs
) < mode_width
)
8084 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8085 new_rtx
= make_extraction (mode
, new_rtx
,
8086 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8087 NULL_RTX
, mode_width
- INTVAL (rhs
),
8088 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8092 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8093 If so, try to merge the shifts into a SIGN_EXTEND. We could
8094 also do this for some cases of SIGN_EXTRACT, but it doesn't
8095 seem worth the effort; the case checked for occurs on Alpha. */
8098 && ! (GET_CODE (lhs
) == SUBREG
8099 && (OBJECT_P (SUBREG_REG (lhs
))))
8100 && CONST_INT_P (rhs
)
8101 && INTVAL (rhs
) >= 0
8102 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8103 && INTVAL (rhs
) < mode_width
8104 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8105 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8106 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8107 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8112 /* Call ourselves recursively on the inner expression. If we are
8113 narrowing the object and it has a different RTL code from
8114 what it originally did, do this SUBREG as a force_to_mode. */
8116 rtx inner
= SUBREG_REG (x
), simplified
;
8117 enum rtx_code subreg_code
= in_code
;
8119 /* If the SUBREG is masking of a logical right shift,
8120 make an extraction. */
8121 if (GET_CODE (inner
) == LSHIFTRT
8122 && CONST_INT_P (XEXP (inner
, 1))
8123 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8124 && (UINTVAL (XEXP (inner
, 1))
8125 < GET_MODE_PRECISION (GET_MODE (inner
)))
8126 && subreg_lowpart_p (x
))
8128 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8129 int width
= GET_MODE_PRECISION (GET_MODE (inner
))
8130 - INTVAL (XEXP (inner
, 1));
8131 if (width
> mode_width
)
8133 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8134 width
, 1, 0, in_code
== COMPARE
);
8138 /* If in_code is COMPARE, it isn't always safe to pass it through
8139 to the recursive make_compound_operation call. */
8140 if (subreg_code
== COMPARE
8141 && (!subreg_lowpart_p (x
)
8142 || GET_CODE (inner
) == SUBREG
8143 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8144 is (const_int 0), rather than
8145 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8146 || (GET_CODE (inner
) == AND
8147 && CONST_INT_P (XEXP (inner
, 1))
8148 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8149 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8150 >= GET_MODE_BITSIZE (mode
))))
8153 tem
= make_compound_operation (inner
, subreg_code
);
8156 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8160 if (GET_CODE (tem
) != GET_CODE (inner
)
8161 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8162 && subreg_lowpart_p (x
))
8165 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8167 /* If we have something other than a SUBREG, we might have
8168 done an expansion, so rerun ourselves. */
8169 if (GET_CODE (newer
) != SUBREG
)
8170 newer
= make_compound_operation (newer
, in_code
);
8172 /* force_to_mode can expand compounds. If it just re-expanded the
8173 compound, use gen_lowpart to convert to the desired mode. */
8174 if (rtx_equal_p (newer
, x
)
8175 /* Likewise if it re-expanded the compound only partially.
8176 This happens for SUBREG of ZERO_EXTRACT if they extract
8177 the same number of bits. */
8178 || (GET_CODE (newer
) == SUBREG
8179 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8180 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8181 && GET_CODE (inner
) == AND
8182 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8183 return gen_lowpart (GET_MODE (x
), tem
);
8198 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8199 *next_code_ptr
= next_code
;
8203 /* Look at the expression rooted at X. Look for expressions
8204 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8205 Form these expressions.
8207 Return the new rtx, usually just X.
8209 Also, for machines like the VAX that don't have logical shift insns,
8210 try to convert logical to arithmetic shift operations in cases where
8211 they are equivalent. This undoes the canonicalizations to logical
8212 shifts done elsewhere.
8214 We try, as much as possible, to re-use rtl expressions to save memory.
8216 IN_CODE says what kind of expression we are processing. Normally, it is
8217 SET. In a memory address it is MEM. When processing the arguments of
8218 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8219 precisely it is an equality comparison against zero. */
8222 make_compound_operation (rtx x
, enum rtx_code in_code
)
8224 enum rtx_code code
= GET_CODE (x
);
8227 enum rtx_code next_code
;
8230 /* Select the code to be used in recursive calls. Once we are inside an
8231 address, we stay there. If we have a comparison, set to COMPARE,
8232 but once inside, go back to our default of SET. */
8234 next_code
= (code
== MEM
? MEM
8235 : ((code
== COMPARE
|| COMPARISON_P (x
))
8236 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8237 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8239 if (SCALAR_INT_MODE_P (GET_MODE (x
)))
8241 rtx new_rtx
= make_compound_operation_int (GET_MODE (x
), &x
,
8242 in_code
, &next_code
);
8245 code
= GET_CODE (x
);
8248 /* Now recursively process each operand of this operation. We need to
8249 handle ZERO_EXTEND specially so that we don't lose track of the
8251 if (code
== ZERO_EXTEND
)
8253 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8254 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8255 new_rtx
, GET_MODE (XEXP (x
, 0)));
8258 SUBST (XEXP (x
, 0), new_rtx
);
8262 fmt
= GET_RTX_FORMAT (code
);
8263 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8266 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8267 SUBST (XEXP (x
, i
), new_rtx
);
8269 else if (fmt
[i
] == 'E')
8270 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8272 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8273 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8276 maybe_swap_commutative_operands (x
);
8280 /* Given M see if it is a value that would select a field of bits
8281 within an item, but not the entire word. Return -1 if not.
8282 Otherwise, return the starting position of the field, where 0 is the
8285 *PLEN is set to the length of the field. */
8288 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8290 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8291 int pos
= m
? ctz_hwi (m
) : -1;
8295 /* Now shift off the low-order zero bits and see if we have a
8296 power of two minus 1. */
8297 len
= exact_log2 ((m
>> pos
) + 1);
8306 /* If X refers to a register that equals REG in value, replace these
8307 references with REG. */
8309 canon_reg_for_combine (rtx x
, rtx reg
)
8316 enum rtx_code code
= GET_CODE (x
);
8317 switch (GET_RTX_CLASS (code
))
8320 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8321 if (op0
!= XEXP (x
, 0))
8322 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8327 case RTX_COMM_ARITH
:
8328 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8329 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8330 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8331 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8335 case RTX_COMM_COMPARE
:
8336 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8337 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8338 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8339 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8340 GET_MODE (op0
), op0
, op1
);
8344 case RTX_BITFIELD_OPS
:
8345 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8346 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8347 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8348 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8349 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8350 GET_MODE (op0
), op0
, op1
, op2
);
8356 if (rtx_equal_p (get_last_value (reg
), x
)
8357 || rtx_equal_p (reg
, get_last_value (x
)))
8366 fmt
= GET_RTX_FORMAT (code
);
8368 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8371 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8372 if (op
!= XEXP (x
, i
))
8382 else if (fmt
[i
] == 'E')
8385 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8387 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8388 if (op
!= XVECEXP (x
, i
, j
))
8395 XVECEXP (x
, i
, j
) = op
;
8406 /* Return X converted to MODE. If the value is already truncated to
8407 MODE we can just return a subreg even though in the general case we
8408 would need an explicit truncation. */
8411 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8413 if (!CONST_INT_P (x
)
8414 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8415 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8416 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8418 /* Bit-cast X into an integer mode. */
8419 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8420 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8421 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8425 return gen_lowpart (mode
, x
);
8428 /* See if X can be simplified knowing that we will only refer to it in
8429 MODE and will only refer to those bits that are nonzero in MASK.
8430 If other bits are being computed or if masking operations are done
8431 that select a superset of the bits in MASK, they can sometimes be
8434 Return a possibly simplified expression, but always convert X to
8435 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8437 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8438 are all off in X. This is used when X will be complemented, by either
8439 NOT, NEG, or XOR. */
8442 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8445 enum rtx_code code
= GET_CODE (x
);
8446 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8447 machine_mode op_mode
;
8448 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8451 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8452 code below will do the wrong thing since the mode of such an
8453 expression is VOIDmode.
8455 Also do nothing if X is a CLOBBER; this can happen if X was
8456 the return value from a call to gen_lowpart. */
8457 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8460 /* We want to perform the operation in its present mode unless we know
8461 that the operation is valid in MODE, in which case we do the operation
8463 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8464 && have_insn_for (code
, mode
))
8465 ? mode
: GET_MODE (x
));
8467 /* It is not valid to do a right-shift in a narrower mode
8468 than the one it came in with. */
8469 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8470 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8471 op_mode
= GET_MODE (x
);
8473 /* Truncate MASK to fit OP_MODE. */
8475 mask
&= GET_MODE_MASK (op_mode
);
8477 /* When we have an arithmetic operation, or a shift whose count we
8478 do not know, we need to assume that all bits up to the highest-order
8479 bit in MASK will be needed. This is how we form such a mask. */
8480 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8481 fuller_mask
= HOST_WIDE_INT_M1U
;
8483 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8486 /* Determine what bits of X are guaranteed to be (non)zero. */
8487 nonzero
= nonzero_bits (x
, mode
);
8489 /* If none of the bits in X are needed, return a zero. */
8490 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8493 /* If X is a CONST_INT, return a new one. Do this here since the
8494 test below will fail. */
8495 if (CONST_INT_P (x
))
8497 if (SCALAR_INT_MODE_P (mode
))
8498 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8501 x
= GEN_INT (INTVAL (x
) & mask
);
8502 return gen_lowpart_common (mode
, x
);
8506 /* If X is narrower than MODE and we want all the bits in X's mode, just
8507 get X in the proper mode. */
8508 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8509 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8510 return gen_lowpart (mode
, x
);
8512 /* We can ignore the effect of a SUBREG if it narrows the mode or
8513 if the constant masks to zero all the bits the mode doesn't have. */
8514 if (GET_CODE (x
) == SUBREG
8515 && subreg_lowpart_p (x
)
8516 && ((GET_MODE_SIZE (GET_MODE (x
))
8517 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8519 & GET_MODE_MASK (GET_MODE (x
))
8520 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8521 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8523 /* The arithmetic simplifications here only work for scalar integer modes. */
8524 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8525 return gen_lowpart_or_truncate (mode
, x
);
8530 /* If X is a (clobber (const_int)), return it since we know we are
8531 generating something that won't match. */
8538 x
= expand_compound_operation (x
);
8539 if (GET_CODE (x
) != code
)
8540 return force_to_mode (x
, mode
, mask
, next_select
);
8544 /* Similarly for a truncate. */
8545 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8548 /* If this is an AND with a constant, convert it into an AND
8549 whose constant is the AND of that constant with MASK. If it
8550 remains an AND of MASK, delete it since it is redundant. */
8552 if (CONST_INT_P (XEXP (x
, 1)))
8554 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8555 mask
& INTVAL (XEXP (x
, 1)));
8557 /* If X is still an AND, see if it is an AND with a mask that
8558 is just some low-order bits. If so, and it is MASK, we don't
8561 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8562 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8566 /* If it remains an AND, try making another AND with the bits
8567 in the mode mask that aren't in MASK turned on. If the
8568 constant in the AND is wide enough, this might make a
8569 cheaper constant. */
8571 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8572 && GET_MODE_MASK (GET_MODE (x
)) != mask
8573 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8575 unsigned HOST_WIDE_INT cval
8576 = UINTVAL (XEXP (x
, 1))
8577 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8580 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8581 gen_int_mode (cval
, GET_MODE (x
)));
8582 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8583 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8593 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8594 low-order bits (as in an alignment operation) and FOO is already
8595 aligned to that boundary, mask C1 to that boundary as well.
8596 This may eliminate that PLUS and, later, the AND. */
8599 unsigned int width
= GET_MODE_PRECISION (mode
);
8600 unsigned HOST_WIDE_INT smask
= mask
;
8602 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8603 number, sign extend it. */
8605 if (width
< HOST_BITS_PER_WIDE_INT
8606 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8607 smask
|= HOST_WIDE_INT_M1U
<< width
;
8609 if (CONST_INT_P (XEXP (x
, 1))
8610 && pow2p_hwi (- smask
)
8611 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8612 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8613 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8614 (INTVAL (XEXP (x
, 1)) & smask
)),
8615 mode
, smask
, next_select
);
8621 /* Substituting into the operands of a widening MULT is not likely to
8622 create RTL matching a machine insn. */
8624 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8625 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8626 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8627 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8628 && REG_P (XEXP (XEXP (x
, 0), 0))
8629 && REG_P (XEXP (XEXP (x
, 1), 0)))
8630 return gen_lowpart_or_truncate (mode
, x
);
8632 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8633 most significant bit in MASK since carries from those bits will
8634 affect the bits we are interested in. */
8639 /* If X is (minus C Y) where C's least set bit is larger than any bit
8640 in the mask, then we may replace with (neg Y). */
8641 if (CONST_INT_P (XEXP (x
, 0))
8642 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8644 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8646 return force_to_mode (x
, mode
, mask
, next_select
);
8649 /* Similarly, if C contains every bit in the fuller_mask, then we may
8650 replace with (not Y). */
8651 if (CONST_INT_P (XEXP (x
, 0))
8652 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8654 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8655 XEXP (x
, 1), GET_MODE (x
));
8656 return force_to_mode (x
, mode
, mask
, next_select
);
8664 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8665 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8666 operation which may be a bitfield extraction. Ensure that the
8667 constant we form is not wider than the mode of X. */
8669 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8670 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8671 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8672 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8673 && CONST_INT_P (XEXP (x
, 1))
8674 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8675 + floor_log2 (INTVAL (XEXP (x
, 1))))
8676 < GET_MODE_PRECISION (GET_MODE (x
)))
8677 && (UINTVAL (XEXP (x
, 1))
8678 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8680 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8681 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8683 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8684 XEXP (XEXP (x
, 0), 0), temp
);
8685 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8686 XEXP (XEXP (x
, 0), 1));
8687 return force_to_mode (x
, mode
, mask
, next_select
);
8691 /* For most binary operations, just propagate into the operation and
8692 change the mode if we have an operation of that mode. */
8694 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8695 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8697 /* If we ended up truncating both operands, truncate the result of the
8698 operation instead. */
8699 if (GET_CODE (op0
) == TRUNCATE
8700 && GET_CODE (op1
) == TRUNCATE
)
8702 op0
= XEXP (op0
, 0);
8703 op1
= XEXP (op1
, 0);
8706 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8707 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8709 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8710 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8714 /* For left shifts, do the same, but just for the first operand.
8715 However, we cannot do anything with shifts where we cannot
8716 guarantee that the counts are smaller than the size of the mode
8717 because such a count will have a different meaning in a
8720 if (! (CONST_INT_P (XEXP (x
, 1))
8721 && INTVAL (XEXP (x
, 1)) >= 0
8722 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8723 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8724 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8725 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8728 /* If the shift count is a constant and we can do arithmetic in
8729 the mode of the shift, refine which bits we need. Otherwise, use the
8730 conservative form of the mask. */
8731 if (CONST_INT_P (XEXP (x
, 1))
8732 && INTVAL (XEXP (x
, 1)) >= 0
8733 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8734 && HWI_COMPUTABLE_MODE_P (op_mode
))
8735 mask
>>= INTVAL (XEXP (x
, 1));
8739 op0
= gen_lowpart_or_truncate (op_mode
,
8740 force_to_mode (XEXP (x
, 0), op_mode
,
8741 mask
, next_select
));
8743 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8744 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8748 /* Here we can only do something if the shift count is a constant,
8749 this shift constant is valid for the host, and we can do arithmetic
8752 if (CONST_INT_P (XEXP (x
, 1))
8753 && INTVAL (XEXP (x
, 1)) >= 0
8754 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8755 && HWI_COMPUTABLE_MODE_P (op_mode
))
8757 rtx inner
= XEXP (x
, 0);
8758 unsigned HOST_WIDE_INT inner_mask
;
8760 /* Select the mask of the bits we need for the shift operand. */
8761 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8763 /* We can only change the mode of the shift if we can do arithmetic
8764 in the mode of the shift and INNER_MASK is no wider than the
8765 width of X's mode. */
8766 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8767 op_mode
= GET_MODE (x
);
8769 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8771 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8772 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8775 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8776 shift and AND produces only copies of the sign bit (C2 is one less
8777 than a power of two), we can do this with just a shift. */
8779 if (GET_CODE (x
) == LSHIFTRT
8780 && CONST_INT_P (XEXP (x
, 1))
8781 /* The shift puts one of the sign bit copies in the least significant
8783 && ((INTVAL (XEXP (x
, 1))
8784 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8785 >= GET_MODE_PRECISION (GET_MODE (x
)))
8786 && pow2p_hwi (mask
+ 1)
8787 /* Number of bits left after the shift must be more than the mask
8789 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8790 <= GET_MODE_PRECISION (GET_MODE (x
)))
8791 /* Must be more sign bit copies than the mask needs. */
8792 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8793 >= exact_log2 (mask
+ 1)))
8794 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8795 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8796 - exact_log2 (mask
+ 1)));
8801 /* If we are just looking for the sign bit, we don't need this shift at
8802 all, even if it has a variable count. */
8803 if (val_signbit_p (GET_MODE (x
), mask
))
8804 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8806 /* If this is a shift by a constant, get a mask that contains those bits
8807 that are not copies of the sign bit. We then have two cases: If
8808 MASK only includes those bits, this can be a logical shift, which may
8809 allow simplifications. If MASK is a single-bit field not within
8810 those bits, we are requesting a copy of the sign bit and hence can
8811 shift the sign bit to the appropriate location. */
8813 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8814 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8818 /* If the considered data is wider than HOST_WIDE_INT, we can't
8819 represent a mask for all its bits in a single scalar.
8820 But we only care about the lower bits, so calculate these. */
8822 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8824 nonzero
= HOST_WIDE_INT_M1U
;
8826 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8827 is the number of bits a full-width mask would have set.
8828 We need only shift if these are fewer than nonzero can
8829 hold. If not, we must keep all bits set in nonzero. */
8831 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8832 < HOST_BITS_PER_WIDE_INT
)
8833 nonzero
>>= INTVAL (XEXP (x
, 1))
8834 + HOST_BITS_PER_WIDE_INT
8835 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8839 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8840 nonzero
>>= INTVAL (XEXP (x
, 1));
8843 if ((mask
& ~nonzero
) == 0)
8845 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8846 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8847 if (GET_CODE (x
) != ASHIFTRT
)
8848 return force_to_mode (x
, mode
, mask
, next_select
);
8851 else if ((i
= exact_log2 (mask
)) >= 0)
8853 x
= simplify_shift_const
8854 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8855 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8857 if (GET_CODE (x
) != ASHIFTRT
)
8858 return force_to_mode (x
, mode
, mask
, next_select
);
8862 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8863 even if the shift count isn't a constant. */
8865 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8866 XEXP (x
, 0), XEXP (x
, 1));
8870 /* If this is a zero- or sign-extension operation that just affects bits
8871 we don't care about, remove it. Be sure the call above returned
8872 something that is still a shift. */
8874 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8875 && CONST_INT_P (XEXP (x
, 1))
8876 && INTVAL (XEXP (x
, 1)) >= 0
8877 && (INTVAL (XEXP (x
, 1))
8878 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8879 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8880 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8881 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8888 /* If the shift count is constant and we can do computations
8889 in the mode of X, compute where the bits we care about are.
8890 Otherwise, we can't do anything. Don't change the mode of
8891 the shift or propagate MODE into the shift, though. */
8892 if (CONST_INT_P (XEXP (x
, 1))
8893 && INTVAL (XEXP (x
, 1)) >= 0)
8895 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8897 gen_int_mode (mask
, GET_MODE (x
)),
8899 if (temp
&& CONST_INT_P (temp
))
8900 x
= simplify_gen_binary (code
, GET_MODE (x
),
8901 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8902 INTVAL (temp
), next_select
),
8908 /* If we just want the low-order bit, the NEG isn't needed since it
8909 won't change the low-order bit. */
8911 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8913 /* We need any bits less significant than the most significant bit in
8914 MASK since carries from those bits will affect the bits we are
8920 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8921 same as the XOR case above. Ensure that the constant we form is not
8922 wider than the mode of X. */
8924 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8925 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8926 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8927 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8928 < GET_MODE_PRECISION (GET_MODE (x
)))
8929 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8931 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8933 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8934 XEXP (XEXP (x
, 0), 0), temp
);
8935 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8936 temp
, XEXP (XEXP (x
, 0), 1));
8938 return force_to_mode (x
, mode
, mask
, next_select
);
8941 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8942 use the full mask inside the NOT. */
8946 op0
= gen_lowpart_or_truncate (op_mode
,
8947 force_to_mode (XEXP (x
, 0), mode
, mask
,
8949 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8950 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8954 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8955 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8956 which is equal to STORE_FLAG_VALUE. */
8957 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8958 && XEXP (x
, 1) == const0_rtx
8959 && GET_MODE (XEXP (x
, 0)) == mode
8960 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
8961 && (nonzero_bits (XEXP (x
, 0), mode
)
8962 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8963 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8968 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8969 written in a narrower mode. We play it safe and do not do so. */
8971 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8972 force_to_mode (XEXP (x
, 1), mode
,
8973 mask
, next_select
));
8974 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8975 force_to_mode (XEXP (x
, 2), mode
,
8976 mask
, next_select
));
8977 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8978 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8979 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8987 /* Ensure we return a value of the proper mode. */
8988 return gen_lowpart_or_truncate (mode
, x
);
8991 /* Return nonzero if X is an expression that has one of two values depending on
8992 whether some other value is zero or nonzero. In that case, we return the
8993 value that is being tested, *PTRUE is set to the value if the rtx being
8994 returned has a nonzero value, and *PFALSE is set to the other alternative.
8996 If we return zero, we set *PTRUE and *PFALSE to X. */
8999 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9001 machine_mode mode
= GET_MODE (x
);
9002 enum rtx_code code
= GET_CODE (x
);
9003 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9004 unsigned HOST_WIDE_INT nz
;
9006 /* If we are comparing a value against zero, we are done. */
9007 if ((code
== NE
|| code
== EQ
)
9008 && XEXP (x
, 1) == const0_rtx
)
9010 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9011 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9015 /* If this is a unary operation whose operand has one of two values, apply
9016 our opcode to compute those values. */
9017 else if (UNARY_P (x
)
9018 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9020 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9021 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9022 GET_MODE (XEXP (x
, 0)));
9026 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9027 make can't possibly match and would suppress other optimizations. */
9028 else if (code
== COMPARE
)
9031 /* If this is a binary operation, see if either side has only one of two
9032 values. If either one does or if both do and they are conditional on
9033 the same value, compute the new true and false values. */
9034 else if (BINARY_P (x
))
9036 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
9037 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
9039 if ((cond0
!= 0 || cond1
!= 0)
9040 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
9042 /* If if_then_else_cond returned zero, then true/false are the
9043 same rtl. We must copy one of them to prevent invalid rtl
9046 true0
= copy_rtx (true0
);
9047 else if (cond1
== 0)
9048 true1
= copy_rtx (true1
);
9050 if (COMPARISON_P (x
))
9052 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9054 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9059 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9060 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9063 return cond0
? cond0
: cond1
;
9066 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9067 operands is zero when the other is nonzero, and vice-versa,
9068 and STORE_FLAG_VALUE is 1 or -1. */
9070 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9071 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9073 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9075 rtx op0
= XEXP (XEXP (x
, 0), 1);
9076 rtx op1
= XEXP (XEXP (x
, 1), 1);
9078 cond0
= XEXP (XEXP (x
, 0), 0);
9079 cond1
= XEXP (XEXP (x
, 1), 0);
9081 if (COMPARISON_P (cond0
)
9082 && COMPARISON_P (cond1
)
9083 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9084 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9085 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9086 || ((swap_condition (GET_CODE (cond0
))
9087 == reversed_comparison_code (cond1
, NULL
))
9088 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9089 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9090 && ! side_effects_p (x
))
9092 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9093 *pfalse
= simplify_gen_binary (MULT
, mode
,
9095 ? simplify_gen_unary (NEG
, mode
,
9103 /* Similarly for MULT, AND and UMIN, except that for these the result
9105 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9106 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9107 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9109 cond0
= XEXP (XEXP (x
, 0), 0);
9110 cond1
= XEXP (XEXP (x
, 1), 0);
9112 if (COMPARISON_P (cond0
)
9113 && COMPARISON_P (cond1
)
9114 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9115 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9116 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9117 || ((swap_condition (GET_CODE (cond0
))
9118 == reversed_comparison_code (cond1
, NULL
))
9119 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9120 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9121 && ! side_effects_p (x
))
9123 *ptrue
= *pfalse
= const0_rtx
;
9129 else if (code
== IF_THEN_ELSE
)
9131 /* If we have IF_THEN_ELSE already, extract the condition and
9132 canonicalize it if it is NE or EQ. */
9133 cond0
= XEXP (x
, 0);
9134 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9135 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9136 return XEXP (cond0
, 0);
9137 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9139 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9140 return XEXP (cond0
, 0);
9146 /* If X is a SUBREG, we can narrow both the true and false values
9147 if the inner expression, if there is a condition. */
9148 else if (code
== SUBREG
9149 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9152 true0
= simplify_gen_subreg (mode
, true0
,
9153 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9154 false0
= simplify_gen_subreg (mode
, false0
,
9155 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9156 if (true0
&& false0
)
9164 /* If X is a constant, this isn't special and will cause confusions
9165 if we treat it as such. Likewise if it is equivalent to a constant. */
9166 else if (CONSTANT_P (x
)
9167 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9170 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9171 will be least confusing to the rest of the compiler. */
9172 else if (mode
== BImode
)
9174 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9178 /* If X is known to be either 0 or -1, those are the true and
9179 false values when testing X. */
9180 else if (x
== constm1_rtx
|| x
== const0_rtx
9181 || (mode
!= VOIDmode
&& mode
!= BLKmode
9182 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9184 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9188 /* Likewise for 0 or a single bit. */
9189 else if (HWI_COMPUTABLE_MODE_P (mode
)
9190 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9192 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9196 /* Otherwise fail; show no condition with true and false values the same. */
9197 *ptrue
= *pfalse
= x
;
9201 /* Return the value of expression X given the fact that condition COND
9202 is known to be true when applied to REG as its first operand and VAL
9203 as its second. X is known to not be shared and so can be modified in
9206 We only handle the simplest cases, and specifically those cases that
9207 arise with IF_THEN_ELSE expressions. */
9210 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9212 enum rtx_code code
= GET_CODE (x
);
9216 if (side_effects_p (x
))
9219 /* If either operand of the condition is a floating point value,
9220 then we have to avoid collapsing an EQ comparison. */
9222 && rtx_equal_p (x
, reg
)
9223 && ! FLOAT_MODE_P (GET_MODE (x
))
9224 && ! FLOAT_MODE_P (GET_MODE (val
)))
9227 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9230 /* If X is (abs REG) and we know something about REG's relationship
9231 with zero, we may be able to simplify this. */
9233 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9236 case GE
: case GT
: case EQ
:
9239 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9241 GET_MODE (XEXP (x
, 0)));
9246 /* The only other cases we handle are MIN, MAX, and comparisons if the
9247 operands are the same as REG and VAL. */
9249 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9251 if (rtx_equal_p (XEXP (x
, 0), val
))
9253 std::swap (val
, reg
);
9254 cond
= swap_condition (cond
);
9257 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9259 if (COMPARISON_P (x
))
9261 if (comparison_dominates_p (cond
, code
))
9262 return const_true_rtx
;
9264 code
= reversed_comparison_code (x
, NULL
);
9266 && comparison_dominates_p (cond
, code
))
9271 else if (code
== SMAX
|| code
== SMIN
9272 || code
== UMIN
|| code
== UMAX
)
9274 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9276 /* Do not reverse the condition when it is NE or EQ.
9277 This is because we cannot conclude anything about
9278 the value of 'SMAX (x, y)' when x is not equal to y,
9279 but we can when x equals y. */
9280 if ((code
== SMAX
|| code
== UMAX
)
9281 && ! (cond
== EQ
|| cond
== NE
))
9282 cond
= reverse_condition (cond
);
9287 return unsignedp
? x
: XEXP (x
, 1);
9289 return unsignedp
? x
: XEXP (x
, 0);
9291 return unsignedp
? XEXP (x
, 1) : x
;
9293 return unsignedp
? XEXP (x
, 0) : x
;
9300 else if (code
== SUBREG
)
9302 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9303 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9305 if (SUBREG_REG (x
) != r
)
9307 /* We must simplify subreg here, before we lose track of the
9308 original inner_mode. */
9309 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9310 inner_mode
, SUBREG_BYTE (x
));
9314 SUBST (SUBREG_REG (x
), r
);
9319 /* We don't have to handle SIGN_EXTEND here, because even in the
9320 case of replacing something with a modeless CONST_INT, a
9321 CONST_INT is already (supposed to be) a valid sign extension for
9322 its narrower mode, which implies it's already properly
9323 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9324 story is different. */
9325 else if (code
== ZERO_EXTEND
)
9327 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9328 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9330 if (XEXP (x
, 0) != r
)
9332 /* We must simplify the zero_extend here, before we lose
9333 track of the original inner_mode. */
9334 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9339 SUBST (XEXP (x
, 0), r
);
9345 fmt
= GET_RTX_FORMAT (code
);
9346 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9349 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9350 else if (fmt
[i
] == 'E')
9351 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9352 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9359 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9360 assignment as a field assignment. */
9363 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9365 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9367 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9369 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9371 /* For big endian, adjust the memory offset. */
9372 if (BYTES_BIG_ENDIAN
)
9373 x
= adjust_address_nv (x
, GET_MODE (y
),
9374 -subreg_lowpart_offset (GET_MODE (x
),
9377 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9380 if (x
== y
|| rtx_equal_p (x
, y
))
9383 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9386 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9387 Note that all SUBREGs of MEM are paradoxical; otherwise they
9388 would have been rewritten. */
9389 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9390 && MEM_P (SUBREG_REG (y
))
9391 && rtx_equal_p (SUBREG_REG (y
),
9392 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9395 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9396 && MEM_P (SUBREG_REG (x
))
9397 && rtx_equal_p (SUBREG_REG (x
),
9398 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9401 /* We used to see if get_last_value of X and Y were the same but that's
9402 not correct. In one direction, we'll cause the assignment to have
9403 the wrong destination and in the case, we'll import a register into this
9404 insn that might have already have been dead. So fail if none of the
9405 above cases are true. */
9409 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9410 Return that assignment if so.
9412 We only handle the most common cases. */
9415 make_field_assignment (rtx x
)
9417 rtx dest
= SET_DEST (x
);
9418 rtx src
= SET_SRC (x
);
9423 unsigned HOST_WIDE_INT len
;
9427 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9428 a clear of a one-bit field. We will have changed it to
9429 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9432 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9433 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9434 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9435 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9437 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9440 return gen_rtx_SET (assign
, const0_rtx
);
9444 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9445 && subreg_lowpart_p (XEXP (src
, 0))
9446 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9447 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9448 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9449 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9450 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9451 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9453 assign
= make_extraction (VOIDmode
, dest
, 0,
9454 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9457 return gen_rtx_SET (assign
, const0_rtx
);
9461 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9463 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9464 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9465 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9467 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9470 return gen_rtx_SET (assign
, const1_rtx
);
9474 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9475 SRC is an AND with all bits of that field set, then we can discard
9477 if (GET_CODE (dest
) == ZERO_EXTRACT
9478 && CONST_INT_P (XEXP (dest
, 1))
9479 && GET_CODE (src
) == AND
9480 && CONST_INT_P (XEXP (src
, 1)))
9482 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9483 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9484 unsigned HOST_WIDE_INT ze_mask
;
9486 if (width
>= HOST_BITS_PER_WIDE_INT
)
9489 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9491 /* Complete overlap. We can remove the source AND. */
9492 if ((and_mask
& ze_mask
) == ze_mask
)
9493 return gen_rtx_SET (dest
, XEXP (src
, 0));
9495 /* Partial overlap. We can reduce the source AND. */
9496 if ((and_mask
& ze_mask
) != and_mask
)
9498 mode
= GET_MODE (src
);
9499 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9500 gen_int_mode (and_mask
& ze_mask
, mode
));
9501 return gen_rtx_SET (dest
, src
);
9505 /* The other case we handle is assignments into a constant-position
9506 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9507 a mask that has all one bits except for a group of zero bits and
9508 OTHER is known to have zeros where C1 has ones, this is such an
9509 assignment. Compute the position and length from C1. Shift OTHER
9510 to the appropriate position, force it to the required mode, and
9511 make the extraction. Check for the AND in both operands. */
9513 /* One or more SUBREGs might obscure the constant-position field
9514 assignment. The first one we are likely to encounter is an outer
9515 narrowing SUBREG, which we can just strip for the purposes of
9516 identifying the constant-field assignment. */
9517 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9518 src
= SUBREG_REG (src
);
9520 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9523 rhs
= expand_compound_operation (XEXP (src
, 0));
9524 lhs
= expand_compound_operation (XEXP (src
, 1));
9526 if (GET_CODE (rhs
) == AND
9527 && CONST_INT_P (XEXP (rhs
, 1))
9528 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9529 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9530 /* The second SUBREG that might get in the way is a paradoxical
9531 SUBREG around the first operand of the AND. We want to
9532 pretend the operand is as wide as the destination here. We
9533 do this by adjusting the MEM to wider mode for the sole
9534 purpose of the call to rtx_equal_for_field_assignment_p. Also
9535 note this trick only works for MEMs. */
9536 else if (GET_CODE (rhs
) == AND
9537 && paradoxical_subreg_p (XEXP (rhs
, 0))
9538 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9539 && CONST_INT_P (XEXP (rhs
, 1))
9540 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9542 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9543 else if (GET_CODE (lhs
) == AND
9544 && CONST_INT_P (XEXP (lhs
, 1))
9545 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9546 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9547 /* The second SUBREG that might get in the way is a paradoxical
9548 SUBREG around the first operand of the AND. We want to
9549 pretend the operand is as wide as the destination here. We
9550 do this by adjusting the MEM to wider mode for the sole
9551 purpose of the call to rtx_equal_for_field_assignment_p. Also
9552 note this trick only works for MEMs. */
9553 else if (GET_CODE (lhs
) == AND
9554 && paradoxical_subreg_p (XEXP (lhs
, 0))
9555 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9556 && CONST_INT_P (XEXP (lhs
, 1))
9557 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9559 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9563 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9564 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9565 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9566 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9569 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9573 /* The mode to use for the source is the mode of the assignment, or of
9574 what is inside a possible STRICT_LOW_PART. */
9575 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9576 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9578 /* Shift OTHER right POS places and make it the source, restricting it
9579 to the proper length and mode. */
9581 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9585 src
= force_to_mode (src
, mode
,
9586 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9588 : (HOST_WIDE_INT_1U
<< len
) - 1,
9591 /* If SRC is masked by an AND that does not make a difference in
9592 the value being stored, strip it. */
9593 if (GET_CODE (assign
) == ZERO_EXTRACT
9594 && CONST_INT_P (XEXP (assign
, 1))
9595 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9596 && GET_CODE (src
) == AND
9597 && CONST_INT_P (XEXP (src
, 1))
9598 && UINTVAL (XEXP (src
, 1))
9599 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9600 src
= XEXP (src
, 0);
9602 return gen_rtx_SET (assign
, src
);
9605 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9609 apply_distributive_law (rtx x
)
9611 enum rtx_code code
= GET_CODE (x
);
9612 enum rtx_code inner_code
;
9613 rtx lhs
, rhs
, other
;
9616 /* Distributivity is not true for floating point as it can change the
9617 value. So we don't do it unless -funsafe-math-optimizations. */
9618 if (FLOAT_MODE_P (GET_MODE (x
))
9619 && ! flag_unsafe_math_optimizations
)
9622 /* The outer operation can only be one of the following: */
9623 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9624 && code
!= PLUS
&& code
!= MINUS
)
9630 /* If either operand is a primitive we can't do anything, so get out
9632 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9635 lhs
= expand_compound_operation (lhs
);
9636 rhs
= expand_compound_operation (rhs
);
9637 inner_code
= GET_CODE (lhs
);
9638 if (inner_code
!= GET_CODE (rhs
))
9641 /* See if the inner and outer operations distribute. */
9648 /* These all distribute except over PLUS. */
9649 if (code
== PLUS
|| code
== MINUS
)
9654 if (code
!= PLUS
&& code
!= MINUS
)
9659 /* This is also a multiply, so it distributes over everything. */
9662 /* This used to handle SUBREG, but this turned out to be counter-
9663 productive, since (subreg (op ...)) usually is not handled by
9664 insn patterns, and this "optimization" therefore transformed
9665 recognizable patterns into unrecognizable ones. Therefore the
9666 SUBREG case was removed from here.
9668 It is possible that distributing SUBREG over arithmetic operations
9669 leads to an intermediate result than can then be optimized further,
9670 e.g. by moving the outer SUBREG to the other side of a SET as done
9671 in simplify_set. This seems to have been the original intent of
9672 handling SUBREGs here.
9674 However, with current GCC this does not appear to actually happen,
9675 at least on major platforms. If some case is found where removing
9676 the SUBREG case here prevents follow-on optimizations, distributing
9677 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9683 /* Set LHS and RHS to the inner operands (A and B in the example
9684 above) and set OTHER to the common operand (C in the example).
9685 There is only one way to do this unless the inner operation is
9687 if (COMMUTATIVE_ARITH_P (lhs
)
9688 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9689 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9690 else if (COMMUTATIVE_ARITH_P (lhs
)
9691 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9692 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9693 else if (COMMUTATIVE_ARITH_P (lhs
)
9694 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9695 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9696 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9697 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9701 /* Form the new inner operation, seeing if it simplifies first. */
9702 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9704 /* There is one exception to the general way of distributing:
9705 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9706 if (code
== XOR
&& inner_code
== IOR
)
9709 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9712 /* We may be able to continuing distributing the result, so call
9713 ourselves recursively on the inner operation before forming the
9714 outer operation, which we return. */
9715 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9716 apply_distributive_law (tem
), other
);
9719 /* See if X is of the form (* (+ A B) C), and if so convert to
9720 (+ (* A C) (* B C)) and try to simplify.
9722 Most of the time, this results in no change. However, if some of
9723 the operands are the same or inverses of each other, simplifications
9726 For example, (and (ior A B) (not B)) can occur as the result of
9727 expanding a bit field assignment. When we apply the distributive
9728 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9729 which then simplifies to (and (A (not B))).
9731 Note that no checks happen on the validity of applying the inverse
9732 distributive law. This is pointless since we can do it in the
9733 few places where this routine is called.
9735 N is the index of the term that is decomposed (the arithmetic operation,
9736 i.e. (+ A B) in the first example above). !N is the index of the term that
9737 is distributed, i.e. of C in the first example above. */
9739 distribute_and_simplify_rtx (rtx x
, int n
)
9742 enum rtx_code outer_code
, inner_code
;
9743 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9745 /* Distributivity is not true for floating point as it can change the
9746 value. So we don't do it unless -funsafe-math-optimizations. */
9747 if (FLOAT_MODE_P (GET_MODE (x
))
9748 && ! flag_unsafe_math_optimizations
)
9751 decomposed
= XEXP (x
, n
);
9752 if (!ARITHMETIC_P (decomposed
))
9755 mode
= GET_MODE (x
);
9756 outer_code
= GET_CODE (x
);
9757 distributed
= XEXP (x
, !n
);
9759 inner_code
= GET_CODE (decomposed
);
9760 inner_op0
= XEXP (decomposed
, 0);
9761 inner_op1
= XEXP (decomposed
, 1);
9763 /* Special case (and (xor B C) (not A)), which is equivalent to
9764 (xor (ior A B) (ior A C)) */
9765 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9767 distributed
= XEXP (distributed
, 0);
9773 /* Distribute the second term. */
9774 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9775 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9779 /* Distribute the first term. */
9780 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9781 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9784 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9786 if (GET_CODE (tmp
) != outer_code
9787 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9788 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9794 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9795 in MODE. Return an equivalent form, if different from (and VAROP
9796 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9799 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9800 unsigned HOST_WIDE_INT constop
)
9802 unsigned HOST_WIDE_INT nonzero
;
9803 unsigned HOST_WIDE_INT orig_constop
;
9808 orig_constop
= constop
;
9809 if (GET_CODE (varop
) == CLOBBER
)
9812 /* Simplify VAROP knowing that we will be only looking at some of the
9815 Note by passing in CONSTOP, we guarantee that the bits not set in
9816 CONSTOP are not significant and will never be examined. We must
9817 ensure that is the case by explicitly masking out those bits
9818 before returning. */
9819 varop
= force_to_mode (varop
, mode
, constop
, 0);
9821 /* If VAROP is a CLOBBER, we will fail so return it. */
9822 if (GET_CODE (varop
) == CLOBBER
)
9825 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9826 to VAROP and return the new constant. */
9827 if (CONST_INT_P (varop
))
9828 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9830 /* See what bits may be nonzero in VAROP. Unlike the general case of
9831 a call to nonzero_bits, here we don't care about bits outside
9834 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9836 /* Turn off all bits in the constant that are known to already be zero.
9837 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9838 which is tested below. */
9842 /* If we don't have any bits left, return zero. */
9846 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9847 a power of two, we can replace this with an ASHIFT. */
9848 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9849 && (i
= exact_log2 (constop
)) >= 0)
9850 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9852 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9853 or XOR, then try to apply the distributive law. This may eliminate
9854 operations if either branch can be simplified because of the AND.
9855 It may also make some cases more complex, but those cases probably
9856 won't match a pattern either with or without this. */
9858 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9862 apply_distributive_law
9863 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9864 simplify_and_const_int (NULL_RTX
,
9868 simplify_and_const_int (NULL_RTX
,
9873 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9874 the AND and see if one of the operands simplifies to zero. If so, we
9875 may eliminate it. */
9877 if (GET_CODE (varop
) == PLUS
9878 && pow2p_hwi (constop
+ 1))
9882 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9883 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9884 if (o0
== const0_rtx
)
9886 if (o1
== const0_rtx
)
9890 /* Make a SUBREG if necessary. If we can't make it, fail. */
9891 varop
= gen_lowpart (mode
, varop
);
9892 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9895 /* If we are only masking insignificant bits, return VAROP. */
9896 if (constop
== nonzero
)
9899 if (varop
== orig_varop
&& constop
== orig_constop
)
9902 /* Otherwise, return an AND. */
9903 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9907 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9910 Return an equivalent form, if different from X. Otherwise, return X. If
9911 X is zero, we are to always construct the equivalent form. */
9914 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9915 unsigned HOST_WIDE_INT constop
)
9917 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9922 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9923 gen_int_mode (constop
, mode
));
9924 if (GET_MODE (x
) != mode
)
9925 x
= gen_lowpart (mode
, x
);
9929 /* Given a REG, X, compute which bits in X can be nonzero.
9930 We don't care about bits outside of those defined in MODE.
9932 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9933 a shift, AND, or zero_extract, we can do better. */
9936 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9937 const_rtx known_x ATTRIBUTE_UNUSED
,
9938 machine_mode known_mode ATTRIBUTE_UNUSED
,
9939 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9940 unsigned HOST_WIDE_INT
*nonzero
)
9945 /* If X is a register whose nonzero bits value is current, use it.
9946 Otherwise, if X is a register whose value we can find, use that
9947 value. Otherwise, use the previously-computed global nonzero bits
9948 for this register. */
9950 rsp
= ®_stat
[REGNO (x
)];
9951 if (rsp
->last_set_value
!= 0
9952 && (rsp
->last_set_mode
== mode
9953 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9954 && GET_MODE_CLASS (mode
) == MODE_INT
))
9955 && ((rsp
->last_set_label
>= label_tick_ebb_start
9956 && rsp
->last_set_label
< label_tick
)
9957 || (rsp
->last_set_label
== label_tick
9958 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9959 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9960 && REGNO (x
) < reg_n_sets_max
9961 && REG_N_SETS (REGNO (x
)) == 1
9963 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9966 /* Note that, even if the precision of last_set_mode is lower than that
9967 of mode, record_value_for_reg invoked nonzero_bits on the register
9968 with nonzero_bits_mode (because last_set_mode is necessarily integral
9969 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
9970 are all valid, hence in mode too since nonzero_bits_mode is defined
9971 to the largest HWI_COMPUTABLE_MODE_P mode. */
9972 *nonzero
&= rsp
->last_set_nonzero_bits
;
9976 tem
= get_last_value (x
);
9979 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
9980 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9981 GET_MODE_PRECISION (mode
));
9986 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9988 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9990 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9991 /* We don't know anything about the upper bits. */
9992 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
10000 /* Return the number of bits at the high-order end of X that are known to
10001 be equal to the sign bit. X will be used in mode MODE; if MODE is
10002 VOIDmode, X will be used in its own mode. The returned value will always
10003 be between 1 and the number of bits in MODE. */
10006 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
10007 const_rtx known_x ATTRIBUTE_UNUSED
,
10008 machine_mode known_mode
10010 unsigned int known_ret ATTRIBUTE_UNUSED
,
10011 unsigned int *result
)
10014 reg_stat_type
*rsp
;
10016 rsp
= ®_stat
[REGNO (x
)];
10017 if (rsp
->last_set_value
!= 0
10018 && rsp
->last_set_mode
== mode
10019 && ((rsp
->last_set_label
>= label_tick_ebb_start
10020 && rsp
->last_set_label
< label_tick
)
10021 || (rsp
->last_set_label
== label_tick
10022 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10023 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10024 && REGNO (x
) < reg_n_sets_max
10025 && REG_N_SETS (REGNO (x
)) == 1
10026 && !REGNO_REG_SET_P
10027 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10030 *result
= rsp
->last_set_sign_bit_copies
;
10034 tem
= get_last_value (x
);
10038 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10039 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
10040 *result
= rsp
->sign_bit_copies
;
10045 /* Return the number of "extended" bits there are in X, when interpreted
10046 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10047 unsigned quantities, this is the number of high-order zero bits.
10048 For signed quantities, this is the number of copies of the sign bit
10049 minus 1. In both case, this function returns the number of "spare"
10050 bits. For example, if two quantities for which this function returns
10051 at least 1 are added, the addition is known not to overflow.
10053 This function will always return 0 unless called during combine, which
10054 implies that it must be called from a define_split. */
10057 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10059 if (nonzero_sign_valid
== 0)
10063 ? (HWI_COMPUTABLE_MODE_P (mode
)
10064 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
10065 - floor_log2 (nonzero_bits (x
, mode
)))
10067 : num_sign_bit_copies (x
, mode
) - 1);
10070 /* This function is called from `simplify_shift_const' to merge two
10071 outer operations. Specifically, we have already found that we need
10072 to perform operation *POP0 with constant *PCONST0 at the outermost
10073 position. We would now like to also perform OP1 with constant CONST1
10074 (with *POP0 being done last).
10076 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10077 the resulting operation. *PCOMP_P is set to 1 if we would need to
10078 complement the innermost operand, otherwise it is unchanged.
10080 MODE is the mode in which the operation will be done. No bits outside
10081 the width of this mode matter. It is assumed that the width of this mode
10082 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10084 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10085 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10086 result is simply *PCONST0.
10088 If the resulting operation cannot be expressed as one operation, we
10089 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10092 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10094 enum rtx_code op0
= *pop0
;
10095 HOST_WIDE_INT const0
= *pconst0
;
10097 const0
&= GET_MODE_MASK (mode
);
10098 const1
&= GET_MODE_MASK (mode
);
10100 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10104 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10107 if (op1
== UNKNOWN
|| op0
== SET
)
10110 else if (op0
== UNKNOWN
)
10111 op0
= op1
, const0
= const1
;
10113 else if (op0
== op1
)
10137 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10138 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10141 /* If the two constants aren't the same, we can't do anything. The
10142 remaining six cases can all be done. */
10143 else if (const0
!= const1
)
10151 /* (a & b) | b == b */
10153 else /* op1 == XOR */
10154 /* (a ^ b) | b == a | b */
10160 /* (a & b) ^ b == (~a) & b */
10161 op0
= AND
, *pcomp_p
= 1;
10162 else /* op1 == IOR */
10163 /* (a | b) ^ b == a & ~b */
10164 op0
= AND
, const0
= ~const0
;
10169 /* (a | b) & b == b */
10171 else /* op1 == XOR */
10172 /* (a ^ b) & b) == (~a) & b */
10179 /* Check for NO-OP cases. */
10180 const0
&= GET_MODE_MASK (mode
);
10182 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10184 else if (const0
== 0 && op0
== AND
)
10186 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10192 /* ??? Slightly redundant with the above mask, but not entirely.
10193 Moving this above means we'd have to sign-extend the mode mask
10194 for the final test. */
10195 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10196 *pconst0
= trunc_int_for_mode (const0
, mode
);
10201 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10202 the shift in. The original shift operation CODE is performed on OP in
10203 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10204 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10205 result of the shift is subject to operation OUTER_CODE with operand
10208 static machine_mode
10209 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10210 machine_mode orig_mode
, machine_mode mode
,
10211 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10213 if (orig_mode
== mode
)
10215 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10217 /* In general we can't perform in wider mode for right shift and rotate. */
10221 /* We can still widen if the bits brought in from the left are identical
10222 to the sign bit of ORIG_MODE. */
10223 if (num_sign_bit_copies (op
, mode
)
10224 > (unsigned) (GET_MODE_PRECISION (mode
)
10225 - GET_MODE_PRECISION (orig_mode
)))
10230 /* Similarly here but with zero bits. */
10231 if (HWI_COMPUTABLE_MODE_P (mode
)
10232 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10235 /* We can also widen if the bits brought in will be masked off. This
10236 operation is performed in ORIG_MODE. */
10237 if (outer_code
== AND
)
10239 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10242 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10251 gcc_unreachable ();
10258 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10259 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10260 if we cannot simplify it. Otherwise, return a simplified value.
10262 The shift is normally computed in the widest mode we find in VAROP, as
10263 long as it isn't a different number of words than RESULT_MODE. Exceptions
10264 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10267 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10268 rtx varop
, int orig_count
)
10270 enum rtx_code orig_code
= code
;
10271 rtx orig_varop
= varop
;
10273 machine_mode mode
= result_mode
;
10274 machine_mode shift_mode
, tmode
;
10275 unsigned int mode_words
10276 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10277 /* We form (outer_op (code varop count) (outer_const)). */
10278 enum rtx_code outer_op
= UNKNOWN
;
10279 HOST_WIDE_INT outer_const
= 0;
10280 int complement_p
= 0;
10283 /* Make sure and truncate the "natural" shift on the way in. We don't
10284 want to do this inside the loop as it makes it more difficult to
10286 if (SHIFT_COUNT_TRUNCATED
)
10287 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10289 /* If we were given an invalid count, don't do anything except exactly
10290 what was requested. */
10292 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10295 count
= orig_count
;
10297 /* Unless one of the branches of the `if' in this loop does a `continue',
10298 we will `break' the loop after the `if'. */
10302 /* If we have an operand of (clobber (const_int 0)), fail. */
10303 if (GET_CODE (varop
) == CLOBBER
)
10306 /* Convert ROTATERT to ROTATE. */
10307 if (code
== ROTATERT
)
10309 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10311 count
= bitsize
- count
;
10314 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10315 mode
, outer_op
, outer_const
);
10316 machine_mode shift_unit_mode
= GET_MODE_INNER (shift_mode
);
10318 /* Handle cases where the count is greater than the size of the mode
10319 minus 1. For ASHIFT, use the size minus one as the count (this can
10320 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10321 take the count modulo the size. For other shifts, the result is
10324 Since these shifts are being produced by the compiler by combining
10325 multiple operations, each of which are defined, we know what the
10326 result is supposed to be. */
10328 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10330 if (code
== ASHIFTRT
)
10331 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10332 else if (code
== ROTATE
|| code
== ROTATERT
)
10333 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10336 /* We can't simply return zero because there may be an
10338 varop
= const0_rtx
;
10344 /* If we discovered we had to complement VAROP, leave. Making a NOT
10345 here would cause an infinite loop. */
10349 if (shift_mode
== shift_unit_mode
)
10351 /* An arithmetic right shift of a quantity known to be -1 or 0
10353 if (code
== ASHIFTRT
10354 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10355 == GET_MODE_PRECISION (shift_unit_mode
)))
10361 /* If we are doing an arithmetic right shift and discarding all but
10362 the sign bit copies, this is equivalent to doing a shift by the
10363 bitsize minus one. Convert it into that shift because it will
10364 often allow other simplifications. */
10366 if (code
== ASHIFTRT
10367 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10368 >= GET_MODE_PRECISION (shift_unit_mode
)))
10369 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10371 /* We simplify the tests below and elsewhere by converting
10372 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10373 `make_compound_operation' will convert it to an ASHIFTRT for
10374 those machines (such as VAX) that don't have an LSHIFTRT. */
10375 if (code
== ASHIFTRT
10376 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10377 && val_signbit_known_clear_p (shift_unit_mode
,
10378 nonzero_bits (varop
,
10382 if (((code
== LSHIFTRT
10383 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10384 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10386 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10387 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10388 & GET_MODE_MASK (shift_unit_mode
))))
10389 && !side_effects_p (varop
))
10390 varop
= const0_rtx
;
10393 switch (GET_CODE (varop
))
10399 new_rtx
= expand_compound_operation (varop
);
10400 if (new_rtx
!= varop
)
10408 /* The following rules apply only to scalars. */
10409 if (shift_mode
!= shift_unit_mode
)
10412 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10413 minus the width of a smaller mode, we can do this with a
10414 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10415 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10416 && ! mode_dependent_address_p (XEXP (varop
, 0),
10417 MEM_ADDR_SPACE (varop
))
10418 && ! MEM_VOLATILE_P (varop
)
10419 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10420 MODE_INT
, 1)) != BLKmode
)
10422 new_rtx
= adjust_address_nv (varop
, tmode
,
10423 BYTES_BIG_ENDIAN
? 0
10424 : count
/ BITS_PER_UNIT
);
10426 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10427 : ZERO_EXTEND
, mode
, new_rtx
);
10434 /* The following rules apply only to scalars. */
10435 if (shift_mode
!= shift_unit_mode
)
10438 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10439 the same number of words as what we've seen so far. Then store
10440 the widest mode in MODE. */
10441 if (subreg_lowpart_p (varop
)
10442 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10443 > GET_MODE_SIZE (GET_MODE (varop
)))
10444 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10445 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10447 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10448 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10450 varop
= SUBREG_REG (varop
);
10451 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10452 mode
= GET_MODE (varop
);
10458 /* Some machines use MULT instead of ASHIFT because MULT
10459 is cheaper. But it is still better on those machines to
10460 merge two shifts into one. */
10461 if (CONST_INT_P (XEXP (varop
, 1))
10462 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10465 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10467 GEN_INT (exact_log2 (
10468 UINTVAL (XEXP (varop
, 1)))));
10474 /* Similar, for when divides are cheaper. */
10475 if (CONST_INT_P (XEXP (varop
, 1))
10476 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10479 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10481 GEN_INT (exact_log2 (
10482 UINTVAL (XEXP (varop
, 1)))));
10488 /* If we are extracting just the sign bit of an arithmetic
10489 right shift, that shift is not needed. However, the sign
10490 bit of a wider mode may be different from what would be
10491 interpreted as the sign bit in a narrower mode, so, if
10492 the result is narrower, don't discard the shift. */
10493 if (code
== LSHIFTRT
10494 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10495 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10496 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10498 varop
= XEXP (varop
, 0);
10507 /* The following rules apply only to scalars. */
10508 if (shift_mode
!= shift_unit_mode
)
10511 /* Here we have two nested shifts. The result is usually the
10512 AND of a new shift with a mask. We compute the result below. */
10513 if (CONST_INT_P (XEXP (varop
, 1))
10514 && INTVAL (XEXP (varop
, 1)) >= 0
10515 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10516 && HWI_COMPUTABLE_MODE_P (result_mode
)
10517 && HWI_COMPUTABLE_MODE_P (mode
))
10519 enum rtx_code first_code
= GET_CODE (varop
);
10520 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10521 unsigned HOST_WIDE_INT mask
;
10524 /* We have one common special case. We can't do any merging if
10525 the inner code is an ASHIFTRT of a smaller mode. However, if
10526 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10527 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10528 we can convert it to
10529 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10530 This simplifies certain SIGN_EXTEND operations. */
10531 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10532 && count
== (GET_MODE_PRECISION (result_mode
)
10533 - GET_MODE_PRECISION (GET_MODE (varop
))))
10535 /* C3 has the low-order C1 bits zero. */
10537 mask
= GET_MODE_MASK (mode
)
10538 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10540 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10541 XEXP (varop
, 0), mask
);
10542 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10544 count
= first_count
;
10549 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10550 than C1 high-order bits equal to the sign bit, we can convert
10551 this to either an ASHIFT or an ASHIFTRT depending on the
10554 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10556 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10557 && GET_MODE (varop
) == shift_mode
10558 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10561 varop
= XEXP (varop
, 0);
10562 count
-= first_count
;
10572 /* There are some cases we can't do. If CODE is ASHIFTRT,
10573 we can only do this if FIRST_CODE is also ASHIFTRT.
10575 We can't do the case when CODE is ROTATE and FIRST_CODE is
10578 If the mode of this shift is not the mode of the outer shift,
10579 we can't do this if either shift is a right shift or ROTATE.
10581 Finally, we can't do any of these if the mode is too wide
10582 unless the codes are the same.
10584 Handle the case where the shift codes are the same
10587 if (code
== first_code
)
10589 if (GET_MODE (varop
) != result_mode
10590 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10591 || code
== ROTATE
))
10594 count
+= first_count
;
10595 varop
= XEXP (varop
, 0);
10599 if (code
== ASHIFTRT
10600 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10601 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10602 || (GET_MODE (varop
) != result_mode
10603 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10604 || first_code
== ROTATE
10605 || code
== ROTATE
)))
10608 /* To compute the mask to apply after the shift, shift the
10609 nonzero bits of the inner shift the same way the
10610 outer shift will. */
10612 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10616 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10619 /* Give up if we can't compute an outer operation to use. */
10621 || !CONST_INT_P (mask_rtx
)
10622 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10624 result_mode
, &complement_p
))
10627 /* If the shifts are in the same direction, we add the
10628 counts. Otherwise, we subtract them. */
10629 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10630 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10631 count
+= first_count
;
10633 count
-= first_count
;
10635 /* If COUNT is positive, the new shift is usually CODE,
10636 except for the two exceptions below, in which case it is
10637 FIRST_CODE. If the count is negative, FIRST_CODE should
10640 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10641 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10643 else if (count
< 0)
10644 code
= first_code
, count
= -count
;
10646 varop
= XEXP (varop
, 0);
10650 /* If we have (A << B << C) for any shift, we can convert this to
10651 (A << C << B). This wins if A is a constant. Only try this if
10652 B is not a constant. */
10654 else if (GET_CODE (varop
) == code
10655 && CONST_INT_P (XEXP (varop
, 0))
10656 && !CONST_INT_P (XEXP (varop
, 1)))
10658 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10659 sure the result will be masked. See PR70222. */
10660 if (code
== LSHIFTRT
10661 && mode
!= result_mode
10662 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10663 GET_MODE_MASK (result_mode
)
10664 >> orig_count
, result_mode
,
10667 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10668 up outer sign extension (often left and right shift) is
10669 hardly more efficient than the original. See PR70429. */
10670 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10673 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10676 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10683 /* The following rules apply only to scalars. */
10684 if (shift_mode
!= shift_unit_mode
)
10687 /* Make this fit the case below. */
10688 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10694 /* The following rules apply only to scalars. */
10695 if (shift_mode
!= shift_unit_mode
)
10698 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10699 with C the size of VAROP - 1 and the shift is logical if
10700 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10701 we have an (le X 0) operation. If we have an arithmetic shift
10702 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10703 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10705 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10706 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10707 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10708 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10709 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10710 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10713 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10716 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10717 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10722 /* If we have (shift (logical)), move the logical to the outside
10723 to allow it to possibly combine with another logical and the
10724 shift to combine with another shift. This also canonicalizes to
10725 what a ZERO_EXTRACT looks like. Also, some machines have
10726 (and (shift)) insns. */
10728 if (CONST_INT_P (XEXP (varop
, 1))
10729 /* We can't do this if we have (ashiftrt (xor)) and the
10730 constant has its sign bit set in shift_mode with shift_mode
10731 wider than result_mode. */
10732 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10733 && result_mode
!= shift_mode
10734 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10736 && (new_rtx
= simplify_const_binary_operation
10737 (code
, result_mode
,
10738 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10739 GEN_INT (count
))) != 0
10740 && CONST_INT_P (new_rtx
)
10741 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10742 INTVAL (new_rtx
), result_mode
, &complement_p
))
10744 varop
= XEXP (varop
, 0);
10748 /* If we can't do that, try to simplify the shift in each arm of the
10749 logical expression, make a new logical expression, and apply
10750 the inverse distributive law. This also can't be done for
10751 (ashiftrt (xor)) where we've widened the shift and the constant
10752 changes the sign bit. */
10753 if (CONST_INT_P (XEXP (varop
, 1))
10754 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10755 && result_mode
!= shift_mode
10756 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10759 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10760 XEXP (varop
, 0), count
);
10761 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10762 XEXP (varop
, 1), count
);
10764 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10766 varop
= apply_distributive_law (varop
);
10774 /* The following rules apply only to scalars. */
10775 if (shift_mode
!= shift_unit_mode
)
10778 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10779 says that the sign bit can be tested, FOO has mode MODE, C is
10780 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10781 that may be nonzero. */
10782 if (code
== LSHIFTRT
10783 && XEXP (varop
, 1) == const0_rtx
10784 && GET_MODE (XEXP (varop
, 0)) == result_mode
10785 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10786 && HWI_COMPUTABLE_MODE_P (result_mode
)
10787 && STORE_FLAG_VALUE
== -1
10788 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10789 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10792 varop
= XEXP (varop
, 0);
10799 /* The following rules apply only to scalars. */
10800 if (shift_mode
!= shift_unit_mode
)
10803 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10804 than the number of bits in the mode is equivalent to A. */
10805 if (code
== LSHIFTRT
10806 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10807 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10809 varop
= XEXP (varop
, 0);
10814 /* NEG commutes with ASHIFT since it is multiplication. Move the
10815 NEG outside to allow shifts to combine. */
10817 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10820 varop
= XEXP (varop
, 0);
10826 /* The following rules apply only to scalars. */
10827 if (shift_mode
!= shift_unit_mode
)
10830 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10831 is one less than the number of bits in the mode is
10832 equivalent to (xor A 1). */
10833 if (code
== LSHIFTRT
10834 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10835 && XEXP (varop
, 1) == constm1_rtx
10836 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10837 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10841 varop
= XEXP (varop
, 0);
10845 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10846 that might be nonzero in BAR are those being shifted out and those
10847 bits are known zero in FOO, we can replace the PLUS with FOO.
10848 Similarly in the other operand order. This code occurs when
10849 we are computing the size of a variable-size array. */
10851 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10852 && count
< HOST_BITS_PER_WIDE_INT
10853 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10854 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10855 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10857 varop
= XEXP (varop
, 0);
10860 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10861 && count
< HOST_BITS_PER_WIDE_INT
10862 && HWI_COMPUTABLE_MODE_P (result_mode
)
10863 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10865 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10866 & nonzero_bits (XEXP (varop
, 1),
10869 varop
= XEXP (varop
, 1);
10873 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10875 && CONST_INT_P (XEXP (varop
, 1))
10876 && (new_rtx
= simplify_const_binary_operation
10877 (ASHIFT
, result_mode
,
10878 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10879 GEN_INT (count
))) != 0
10880 && CONST_INT_P (new_rtx
)
10881 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10882 INTVAL (new_rtx
), result_mode
, &complement_p
))
10884 varop
= XEXP (varop
, 0);
10888 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10889 signbit', and attempt to change the PLUS to an XOR and move it to
10890 the outer operation as is done above in the AND/IOR/XOR case
10891 leg for shift(logical). See details in logical handling above
10892 for reasoning in doing so. */
10893 if (code
== LSHIFTRT
10894 && CONST_INT_P (XEXP (varop
, 1))
10895 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10896 && (new_rtx
= simplify_const_binary_operation
10897 (code
, result_mode
,
10898 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10899 GEN_INT (count
))) != 0
10900 && CONST_INT_P (new_rtx
)
10901 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10902 INTVAL (new_rtx
), result_mode
, &complement_p
))
10904 varop
= XEXP (varop
, 0);
10911 /* The following rules apply only to scalars. */
10912 if (shift_mode
!= shift_unit_mode
)
10915 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10916 with C the size of VAROP - 1 and the shift is logical if
10917 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10918 we have a (gt X 0) operation. If the shift is arithmetic with
10919 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10920 we have a (neg (gt X 0)) operation. */
10922 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10923 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10924 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10925 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10926 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10927 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10928 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10931 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10934 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10935 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10942 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10943 if the truncate does not affect the value. */
10944 if (code
== LSHIFTRT
10945 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10946 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10947 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10948 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
10949 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
10951 rtx varop_inner
= XEXP (varop
, 0);
10954 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10955 XEXP (varop_inner
, 0),
10957 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10958 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10971 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10972 outer_op
, outer_const
);
10974 /* We have now finished analyzing the shift. The result should be
10975 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10976 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10977 to the result of the shift. OUTER_CONST is the relevant constant,
10978 but we must turn off all bits turned off in the shift. */
10980 if (outer_op
== UNKNOWN
10981 && orig_code
== code
&& orig_count
== count
10982 && varop
== orig_varop
10983 && shift_mode
== GET_MODE (varop
))
10986 /* Make a SUBREG if necessary. If we can't make it, fail. */
10987 varop
= gen_lowpart (shift_mode
, varop
);
10988 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10991 /* If we have an outer operation and we just made a shift, it is
10992 possible that we could have simplified the shift were it not
10993 for the outer operation. So try to do the simplification
10996 if (outer_op
!= UNKNOWN
)
10997 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11002 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11004 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11005 turn off all the bits that the shift would have turned off. */
11006 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11007 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
11008 GET_MODE_MASK (result_mode
) >> orig_count
);
11010 /* Do the remainder of the processing in RESULT_MODE. */
11011 x
= gen_lowpart_or_truncate (result_mode
, x
);
11013 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11016 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11018 if (outer_op
!= UNKNOWN
)
11020 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11021 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
11022 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
11024 if (outer_op
== AND
)
11025 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
11026 else if (outer_op
== SET
)
11028 /* This means that we have determined that the result is
11029 equivalent to a constant. This should be rare. */
11030 if (!side_effects_p (x
))
11031 x
= GEN_INT (outer_const
);
11033 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11034 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
11036 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
11037 GEN_INT (outer_const
));
11043 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11044 The result of the shift is RESULT_MODE. If we cannot simplify it,
11045 return X or, if it is NULL, synthesize the expression with
11046 simplify_gen_binary. Otherwise, return a simplified value.
11048 The shift is normally computed in the widest mode we find in VAROP, as
11049 long as it isn't a different number of words than RESULT_MODE. Exceptions
11050 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11053 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11054 rtx varop
, int count
)
11056 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11061 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11062 if (GET_MODE (x
) != result_mode
)
11063 x
= gen_lowpart (result_mode
, x
);
11068 /* A subroutine of recog_for_combine. See there for arguments and
11072 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11074 rtx pat
= *pnewpat
;
11075 rtx pat_without_clobbers
;
11076 int insn_code_number
;
11077 int num_clobbers_to_add
= 0;
11079 rtx notes
= NULL_RTX
;
11080 rtx old_notes
, old_pat
;
11083 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11084 we use to indicate that something didn't match. If we find such a
11085 thing, force rejection. */
11086 if (GET_CODE (pat
) == PARALLEL
)
11087 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11088 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11089 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11092 old_pat
= PATTERN (insn
);
11093 old_notes
= REG_NOTES (insn
);
11094 PATTERN (insn
) = pat
;
11095 REG_NOTES (insn
) = NULL_RTX
;
11097 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11098 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11100 if (insn_code_number
< 0)
11101 fputs ("Failed to match this instruction:\n", dump_file
);
11103 fputs ("Successfully matched this instruction:\n", dump_file
);
11104 print_rtl_single (dump_file
, pat
);
11107 /* If it isn't, there is the possibility that we previously had an insn
11108 that clobbered some register as a side effect, but the combined
11109 insn doesn't need to do that. So try once more without the clobbers
11110 unless this represents an ASM insn. */
11112 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11113 && GET_CODE (pat
) == PARALLEL
)
11117 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11118 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11121 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11125 SUBST_INT (XVECLEN (pat
, 0), pos
);
11128 pat
= XVECEXP (pat
, 0, 0);
11130 PATTERN (insn
) = pat
;
11131 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11132 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11134 if (insn_code_number
< 0)
11135 fputs ("Failed to match this instruction:\n", dump_file
);
11137 fputs ("Successfully matched this instruction:\n", dump_file
);
11138 print_rtl_single (dump_file
, pat
);
11142 pat_without_clobbers
= pat
;
11144 PATTERN (insn
) = old_pat
;
11145 REG_NOTES (insn
) = old_notes
;
11147 /* Recognize all noop sets, these will be killed by followup pass. */
11148 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11149 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11151 /* If we had any clobbers to add, make a new pattern than contains
11152 them. Then check to make sure that all of them are dead. */
11153 if (num_clobbers_to_add
)
11155 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11156 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11157 ? (XVECLEN (pat
, 0)
11158 + num_clobbers_to_add
)
11159 : num_clobbers_to_add
+ 1));
11161 if (GET_CODE (pat
) == PARALLEL
)
11162 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11163 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11165 XVECEXP (newpat
, 0, 0) = pat
;
11167 add_clobbers (newpat
, insn_code_number
);
11169 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11170 i
< XVECLEN (newpat
, 0); i
++)
11172 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11173 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11175 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11177 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11178 notes
= alloc_reg_note (REG_UNUSED
,
11179 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11185 if (insn_code_number
>= 0
11186 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11188 old_pat
= PATTERN (insn
);
11189 old_notes
= REG_NOTES (insn
);
11190 old_icode
= INSN_CODE (insn
);
11191 PATTERN (insn
) = pat
;
11192 REG_NOTES (insn
) = notes
;
11194 /* Allow targets to reject combined insn. */
11195 if (!targetm
.legitimate_combined_insn (insn
))
11197 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11198 fputs ("Instruction not appropriate for target.",
11201 /* Callers expect recog_for_combine to strip
11202 clobbers from the pattern on failure. */
11203 pat
= pat_without_clobbers
;
11206 insn_code_number
= -1;
11209 PATTERN (insn
) = old_pat
;
11210 REG_NOTES (insn
) = old_notes
;
11211 INSN_CODE (insn
) = old_icode
;
11217 return insn_code_number
;
11220 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11221 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11222 Return whether anything was so changed. */
11225 change_zero_ext (rtx pat
)
11227 bool changed
= false;
11228 rtx
*src
= &SET_SRC (pat
);
11230 subrtx_ptr_iterator::array_type array
;
11231 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11234 machine_mode mode
= GET_MODE (x
);
11237 if (GET_CODE (x
) == ZERO_EXTRACT
11238 && CONST_INT_P (XEXP (x
, 1))
11239 && CONST_INT_P (XEXP (x
, 2))
11240 && GET_MODE (XEXP (x
, 0)) != VOIDmode
11241 && GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
11242 <= GET_MODE_PRECISION (mode
))
11244 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
11246 size
= INTVAL (XEXP (x
, 1));
11248 int start
= INTVAL (XEXP (x
, 2));
11249 if (BITS_BIG_ENDIAN
)
11250 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11253 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11256 if (mode
!= inner_mode
)
11257 x
= gen_lowpart_SUBREG (mode
, x
);
11259 else if (GET_CODE (x
) == ZERO_EXTEND
11260 && SCALAR_INT_MODE_P (mode
)
11261 && GET_CODE (XEXP (x
, 0)) == SUBREG
11262 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11263 && !paradoxical_subreg_p (XEXP (x
, 0))
11264 && subreg_lowpart_p (XEXP (x
, 0)))
11266 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11267 x
= SUBREG_REG (XEXP (x
, 0));
11268 if (GET_MODE (x
) != mode
)
11269 x
= gen_lowpart_SUBREG (mode
, x
);
11271 else if (GET_CODE (x
) == ZERO_EXTEND
11272 && SCALAR_INT_MODE_P (mode
)
11273 && REG_P (XEXP (x
, 0))
11274 && HARD_REGISTER_P (XEXP (x
, 0))
11275 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11277 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11278 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11283 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11284 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11291 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11292 maybe_swap_commutative_operands (**iter
);
11294 rtx
*dst
= &SET_DEST (pat
);
11295 if (GET_CODE (*dst
) == ZERO_EXTRACT
11296 && REG_P (XEXP (*dst
, 0))
11297 && CONST_INT_P (XEXP (*dst
, 1))
11298 && CONST_INT_P (XEXP (*dst
, 2)))
11300 rtx reg
= XEXP (*dst
, 0);
11301 int width
= INTVAL (XEXP (*dst
, 1));
11302 int offset
= INTVAL (XEXP (*dst
, 2));
11303 machine_mode mode
= GET_MODE (reg
);
11304 int reg_width
= GET_MODE_PRECISION (mode
);
11305 if (BITS_BIG_ENDIAN
)
11306 offset
= reg_width
- width
- offset
;
11309 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11310 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11311 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11313 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11316 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11317 w
= gen_rtx_IOR (mode
, x
, z
);
11318 SUBST (SET_DEST (pat
), reg
);
11319 SUBST (SET_SRC (pat
), w
);
11327 /* Like recog, but we receive the address of a pointer to a new pattern.
11328 We try to match the rtx that the pointer points to.
11329 If that fails, we may try to modify or replace the pattern,
11330 storing the replacement into the same pointer object.
11332 Modifications include deletion or addition of CLOBBERs. If the
11333 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11334 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11335 (and undo if that fails).
11337 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11338 the CLOBBERs are placed.
11340 The value is the final insn code from the pattern ultimately matched,
11344 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11346 rtx pat
= *pnewpat
;
11347 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11348 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11349 return insn_code_number
;
11351 void *marker
= get_undo_marker ();
11352 bool changed
= false;
11354 if (GET_CODE (pat
) == SET
)
11355 changed
= change_zero_ext (pat
);
11356 else if (GET_CODE (pat
) == PARALLEL
)
11359 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11361 rtx set
= XVECEXP (pat
, 0, i
);
11362 if (GET_CODE (set
) == SET
)
11363 changed
|= change_zero_ext (set
);
11369 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11371 if (insn_code_number
< 0)
11372 undo_to_marker (marker
);
11375 return insn_code_number
;
11378 /* Like gen_lowpart_general but for use by combine. In combine it
11379 is not possible to create any new pseudoregs. However, it is
11380 safe to create invalid memory addresses, because combine will
11381 try to recognize them and all they will do is make the combine
11384 If for some reason this cannot do its job, an rtx
11385 (clobber (const_int 0)) is returned.
11386 An insn containing that will not be recognized. */
11389 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11391 machine_mode imode
= GET_MODE (x
);
11392 unsigned int osize
= GET_MODE_SIZE (omode
);
11393 unsigned int isize
= GET_MODE_SIZE (imode
);
11396 if (omode
== imode
)
11399 /* We can only support MODE being wider than a word if X is a
11400 constant integer or has a mode the same size. */
11401 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11402 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11405 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11406 won't know what to do. So we will strip off the SUBREG here and
11407 process normally. */
11408 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11410 x
= SUBREG_REG (x
);
11412 /* For use in case we fall down into the address adjustments
11413 further below, we need to adjust the known mode and size of
11414 x; imode and isize, since we just adjusted x. */
11415 imode
= GET_MODE (x
);
11417 if (imode
== omode
)
11420 isize
= GET_MODE_SIZE (imode
);
11423 result
= gen_lowpart_common (omode
, x
);
11432 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11434 if (MEM_VOLATILE_P (x
)
11435 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11438 /* If we want to refer to something bigger than the original memref,
11439 generate a paradoxical subreg instead. That will force a reload
11440 of the original memref X. */
11442 return gen_rtx_SUBREG (omode
, x
, 0);
11444 if (WORDS_BIG_ENDIAN
)
11445 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11447 /* Adjust the address so that the address-after-the-data is
11449 if (BYTES_BIG_ENDIAN
)
11450 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11452 return adjust_address_nv (x
, omode
, offset
);
11455 /* If X is a comparison operator, rewrite it in a new mode. This
11456 probably won't match, but may allow further simplifications. */
11457 else if (COMPARISON_P (x
))
11458 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11460 /* If we couldn't simplify X any other way, just enclose it in a
11461 SUBREG. Normally, this SUBREG won't match, but some patterns may
11462 include an explicit SUBREG or we may simplify it further in combine. */
11467 if (imode
== VOIDmode
)
11469 imode
= int_mode_for_mode (omode
);
11470 x
= gen_lowpart_common (imode
, x
);
11474 res
= lowpart_subreg (omode
, x
, imode
);
11480 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11483 /* Try to simplify a comparison between OP0 and a constant OP1,
11484 where CODE is the comparison code that will be tested, into a
11485 (CODE OP0 const0_rtx) form.
11487 The result is a possibly different comparison code to use.
11488 *POP1 may be updated. */
11490 static enum rtx_code
11491 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11492 rtx op0
, rtx
*pop1
)
11494 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11495 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11497 /* Get the constant we are comparing against and turn off all bits
11498 not on in our mode. */
11499 if (mode
!= VOIDmode
)
11500 const_op
= trunc_int_for_mode (const_op
, mode
);
11502 /* If we are comparing against a constant power of two and the value
11503 being compared can only have that single bit nonzero (e.g., it was
11504 `and'ed with that bit), we can replace this with a comparison
11507 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11508 || code
== LT
|| code
== LTU
)
11509 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11510 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11511 && (nonzero_bits (op0
, mode
)
11512 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11514 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11518 /* Similarly, if we are comparing a value known to be either -1 or
11519 0 with -1, change it to the opposite comparison against zero. */
11521 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11522 || code
== GEU
|| code
== LTU
)
11523 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11525 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11529 /* Do some canonicalizations based on the comparison code. We prefer
11530 comparisons against zero and then prefer equality comparisons.
11531 If we can reduce the size of a constant, we will do that too. */
11535 /* < C is equivalent to <= (C - 1) */
11540 /* ... fall through to LE case below. */
11541 gcc_fallthrough ();
11547 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11554 /* If we are doing a <= 0 comparison on a value known to have
11555 a zero sign bit, we can replace this with == 0. */
11556 else if (const_op
== 0
11557 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11558 && (nonzero_bits (op0
, mode
)
11559 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11565 /* >= C is equivalent to > (C - 1). */
11570 /* ... fall through to GT below. */
11571 gcc_fallthrough ();
11577 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11584 /* If we are doing a > 0 comparison on a value known to have
11585 a zero sign bit, we can replace this with != 0. */
11586 else if (const_op
== 0
11587 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11588 && (nonzero_bits (op0
, mode
)
11589 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11595 /* < C is equivalent to <= (C - 1). */
11600 /* ... fall through ... */
11602 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11603 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11604 && (unsigned HOST_WIDE_INT
) const_op
11605 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11615 /* unsigned <= 0 is equivalent to == 0 */
11618 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11619 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11620 && (unsigned HOST_WIDE_INT
) const_op
11621 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11629 /* >= C is equivalent to > (C - 1). */
11634 /* ... fall through ... */
11637 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11638 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11639 && (unsigned HOST_WIDE_INT
) const_op
11640 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11650 /* unsigned > 0 is equivalent to != 0 */
11653 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11654 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11655 && (unsigned HOST_WIDE_INT
) const_op
11656 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11667 *pop1
= GEN_INT (const_op
);
11671 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11672 comparison code that will be tested.
11674 The result is a possibly different comparison code to use. *POP0 and
11675 *POP1 may be updated.
11677 It is possible that we might detect that a comparison is either always
11678 true or always false. However, we do not perform general constant
11679 folding in combine, so this knowledge isn't useful. Such tautologies
11680 should have been detected earlier. Hence we ignore all such cases. */
11682 static enum rtx_code
11683 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11689 machine_mode mode
, tmode
;
11691 /* Try a few ways of applying the same transformation to both operands. */
11694 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11695 so check specially. */
11696 if (!WORD_REGISTER_OPERATIONS
11697 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11698 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11699 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11700 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11701 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11702 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11703 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11704 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11705 && CONST_INT_P (XEXP (op0
, 1))
11706 && XEXP (op0
, 1) == XEXP (op1
, 1)
11707 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11708 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11709 && (INTVAL (XEXP (op0
, 1))
11710 == (GET_MODE_PRECISION (GET_MODE (op0
))
11711 - (GET_MODE_PRECISION
11712 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11714 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11715 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11718 /* If both operands are the same constant shift, see if we can ignore the
11719 shift. We can if the shift is a rotate or if the bits shifted out of
11720 this shift are known to be zero for both inputs and if the type of
11721 comparison is compatible with the shift. */
11722 if (GET_CODE (op0
) == GET_CODE (op1
)
11723 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11724 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11725 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11726 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11727 || (GET_CODE (op0
) == ASHIFTRT
11728 && (code
!= GTU
&& code
!= LTU
11729 && code
!= GEU
&& code
!= LEU
)))
11730 && CONST_INT_P (XEXP (op0
, 1))
11731 && INTVAL (XEXP (op0
, 1)) >= 0
11732 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11733 && XEXP (op0
, 1) == XEXP (op1
, 1))
11735 machine_mode mode
= GET_MODE (op0
);
11736 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11737 int shift_count
= INTVAL (XEXP (op0
, 1));
11739 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11740 mask
&= (mask
>> shift_count
) << shift_count
;
11741 else if (GET_CODE (op0
) == ASHIFT
)
11742 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11744 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11745 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11746 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11751 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11752 SUBREGs are of the same mode, and, in both cases, the AND would
11753 be redundant if the comparison was done in the narrower mode,
11754 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11755 and the operand's possibly nonzero bits are 0xffffff01; in that case
11756 if we only care about QImode, we don't need the AND). This case
11757 occurs if the output mode of an scc insn is not SImode and
11758 STORE_FLAG_VALUE == 1 (e.g., the 386).
11760 Similarly, check for a case where the AND's are ZERO_EXTEND
11761 operations from some narrower mode even though a SUBREG is not
11764 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11765 && CONST_INT_P (XEXP (op0
, 1))
11766 && CONST_INT_P (XEXP (op1
, 1)))
11768 rtx inner_op0
= XEXP (op0
, 0);
11769 rtx inner_op1
= XEXP (op1
, 0);
11770 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11771 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11774 if (paradoxical_subreg_p (inner_op0
)
11775 && GET_CODE (inner_op1
) == SUBREG
11776 && (GET_MODE (SUBREG_REG (inner_op0
))
11777 == GET_MODE (SUBREG_REG (inner_op1
)))
11778 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11779 <= HOST_BITS_PER_WIDE_INT
)
11780 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11781 GET_MODE (SUBREG_REG (inner_op0
)))))
11782 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11783 GET_MODE (SUBREG_REG (inner_op1
))))))
11785 op0
= SUBREG_REG (inner_op0
);
11786 op1
= SUBREG_REG (inner_op1
);
11788 /* The resulting comparison is always unsigned since we masked
11789 off the original sign bit. */
11790 code
= unsigned_condition (code
);
11796 for (tmode
= GET_CLASS_NARROWEST_MODE
11797 (GET_MODE_CLASS (GET_MODE (op0
)));
11798 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11799 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11801 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11802 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11803 code
= unsigned_condition (code
);
11812 /* If both operands are NOT, we can strip off the outer operation
11813 and adjust the comparison code for swapped operands; similarly for
11814 NEG, except that this must be an equality comparison. */
11815 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11816 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11817 && (code
== EQ
|| code
== NE
)))
11818 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11824 /* If the first operand is a constant, swap the operands and adjust the
11825 comparison code appropriately, but don't do this if the second operand
11826 is already a constant integer. */
11827 if (swap_commutative_operands_p (op0
, op1
))
11829 std::swap (op0
, op1
);
11830 code
= swap_condition (code
);
11833 /* We now enter a loop during which we will try to simplify the comparison.
11834 For the most part, we only are concerned with comparisons with zero,
11835 but some things may really be comparisons with zero but not start
11836 out looking that way. */
11838 while (CONST_INT_P (op1
))
11840 machine_mode mode
= GET_MODE (op0
);
11841 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11842 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11843 int equality_comparison_p
;
11844 int sign_bit_comparison_p
;
11845 int unsigned_comparison_p
;
11846 HOST_WIDE_INT const_op
;
11848 /* We only want to handle integral modes. This catches VOIDmode,
11849 CCmode, and the floating-point modes. An exception is that we
11850 can handle VOIDmode if OP0 is a COMPARE or a comparison
11853 if (GET_MODE_CLASS (mode
) != MODE_INT
11854 && ! (mode
== VOIDmode
11855 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11858 /* Try to simplify the compare to constant, possibly changing the
11859 comparison op, and/or changing op1 to zero. */
11860 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11861 const_op
= INTVAL (op1
);
11863 /* Compute some predicates to simplify code below. */
11865 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11866 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11867 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11870 /* If this is a sign bit comparison and we can do arithmetic in
11871 MODE, say that we will only be needing the sign bit of OP0. */
11872 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11873 op0
= force_to_mode (op0
, mode
,
11875 << (GET_MODE_PRECISION (mode
) - 1),
11878 /* Now try cases based on the opcode of OP0. If none of the cases
11879 does a "continue", we exit this loop immediately after the
11882 switch (GET_CODE (op0
))
11885 /* If we are extracting a single bit from a variable position in
11886 a constant that has only a single bit set and are comparing it
11887 with zero, we can convert this into an equality comparison
11888 between the position and the location of the single bit. */
11889 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11890 have already reduced the shift count modulo the word size. */
11891 if (!SHIFT_COUNT_TRUNCATED
11892 && CONST_INT_P (XEXP (op0
, 0))
11893 && XEXP (op0
, 1) == const1_rtx
11894 && equality_comparison_p
&& const_op
== 0
11895 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11897 if (BITS_BIG_ENDIAN
)
11898 i
= BITS_PER_WORD
- 1 - i
;
11900 op0
= XEXP (op0
, 2);
11904 /* Result is nonzero iff shift count is equal to I. */
11905 code
= reverse_condition (code
);
11912 tem
= expand_compound_operation (op0
);
11921 /* If testing for equality, we can take the NOT of the constant. */
11922 if (equality_comparison_p
11923 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11925 op0
= XEXP (op0
, 0);
11930 /* If just looking at the sign bit, reverse the sense of the
11932 if (sign_bit_comparison_p
)
11934 op0
= XEXP (op0
, 0);
11935 code
= (code
== GE
? LT
: GE
);
11941 /* If testing for equality, we can take the NEG of the constant. */
11942 if (equality_comparison_p
11943 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11945 op0
= XEXP (op0
, 0);
11950 /* The remaining cases only apply to comparisons with zero. */
11954 /* When X is ABS or is known positive,
11955 (neg X) is < 0 if and only if X != 0. */
11957 if (sign_bit_comparison_p
11958 && (GET_CODE (XEXP (op0
, 0)) == ABS
11959 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11960 && (nonzero_bits (XEXP (op0
, 0), mode
)
11961 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11964 op0
= XEXP (op0
, 0);
11965 code
= (code
== LT
? NE
: EQ
);
11969 /* If we have NEG of something whose two high-order bits are the
11970 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11971 if (num_sign_bit_copies (op0
, mode
) >= 2)
11973 op0
= XEXP (op0
, 0);
11974 code
= swap_condition (code
);
11980 /* If we are testing equality and our count is a constant, we
11981 can perform the inverse operation on our RHS. */
11982 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11983 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11984 op1
, XEXP (op0
, 1))) != 0)
11986 op0
= XEXP (op0
, 0);
11991 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11992 a particular bit. Convert it to an AND of a constant of that
11993 bit. This will be converted into a ZERO_EXTRACT. */
11994 if (const_op
== 0 && sign_bit_comparison_p
11995 && CONST_INT_P (XEXP (op0
, 1))
11996 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11998 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12001 - INTVAL (XEXP (op0
, 1)))));
12002 code
= (code
== LT
? NE
: EQ
);
12006 /* Fall through. */
12009 /* ABS is ignorable inside an equality comparison with zero. */
12010 if (const_op
== 0 && equality_comparison_p
)
12012 op0
= XEXP (op0
, 0);
12018 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12019 (compare FOO CONST) if CONST fits in FOO's mode and we
12020 are either testing inequality or have an unsigned
12021 comparison with ZERO_EXTEND or a signed comparison with
12022 SIGN_EXTEND. But don't do it if we don't have a compare
12023 insn of the given mode, since we'd have to revert it
12024 later on, and then we wouldn't know whether to sign- or
12026 mode
= GET_MODE (XEXP (op0
, 0));
12027 if (GET_MODE_CLASS (mode
) == MODE_INT
12028 && ! unsigned_comparison_p
12029 && HWI_COMPUTABLE_MODE_P (mode
)
12030 && trunc_int_for_mode (const_op
, mode
) == const_op
12031 && have_insn_for (COMPARE
, mode
))
12033 op0
= XEXP (op0
, 0);
12039 /* Check for the case where we are comparing A - C1 with C2, that is
12041 (subreg:MODE (plus (A) (-C1))) op (C2)
12043 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12044 comparison in the wider mode. One of the following two conditions
12045 must be true in order for this to be valid:
12047 1. The mode extension results in the same bit pattern being added
12048 on both sides and the comparison is equality or unsigned. As
12049 C2 has been truncated to fit in MODE, the pattern can only be
12052 2. The mode extension results in the sign bit being copied on
12055 The difficulty here is that we have predicates for A but not for
12056 (A - C1) so we need to check that C1 is within proper bounds so
12057 as to perturbate A as little as possible. */
12059 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12060 && subreg_lowpart_p (op0
)
12061 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
12062 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12063 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12065 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
12066 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12067 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12070 && (unsigned HOST_WIDE_INT
) c1
12071 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12072 && (equality_comparison_p
|| unsigned_comparison_p
)
12073 /* (A - C1) zero-extends if it is positive and sign-extends
12074 if it is negative, C2 both zero- and sign-extends. */
12075 && ((0 == (nonzero_bits (a
, inner_mode
)
12076 & ~GET_MODE_MASK (mode
))
12078 /* (A - C1) sign-extends if it is positive and 1-extends
12079 if it is negative, C2 both sign- and 1-extends. */
12080 || (num_sign_bit_copies (a
, inner_mode
)
12081 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12084 || ((unsigned HOST_WIDE_INT
) c1
12085 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12086 /* (A - C1) always sign-extends, like C2. */
12087 && num_sign_bit_copies (a
, inner_mode
)
12088 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12089 - (mode_width
- 1))))
12091 op0
= SUBREG_REG (op0
);
12096 /* If the inner mode is narrower and we are extracting the low part,
12097 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12098 if (subreg_lowpart_p (op0
)
12099 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
12101 else if (subreg_lowpart_p (op0
)
12102 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12103 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12104 && (code
== NE
|| code
== EQ
)
12105 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12106 <= HOST_BITS_PER_WIDE_INT
)
12107 && !paradoxical_subreg_p (op0
)
12108 && (nonzero_bits (SUBREG_REG (op0
),
12109 GET_MODE (SUBREG_REG (op0
)))
12110 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12112 /* Remove outer subregs that don't do anything. */
12113 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12115 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12116 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12118 op0
= SUBREG_REG (op0
);
12130 mode
= GET_MODE (XEXP (op0
, 0));
12131 if (GET_MODE_CLASS (mode
) == MODE_INT
12132 && (unsigned_comparison_p
|| equality_comparison_p
)
12133 && HWI_COMPUTABLE_MODE_P (mode
)
12134 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12136 && have_insn_for (COMPARE
, mode
))
12138 op0
= XEXP (op0
, 0);
12144 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12145 this for equality comparisons due to pathological cases involving
12147 if (equality_comparison_p
12148 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12149 op1
, XEXP (op0
, 1))))
12151 op0
= XEXP (op0
, 0);
12156 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12157 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12158 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12160 op0
= XEXP (XEXP (op0
, 0), 0);
12161 code
= (code
== LT
? EQ
: NE
);
12167 /* We used to optimize signed comparisons against zero, but that
12168 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12169 arrive here as equality comparisons, or (GEU, LTU) are
12170 optimized away. No need to special-case them. */
12172 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12173 (eq B (minus A C)), whichever simplifies. We can only do
12174 this for equality comparisons due to pathological cases involving
12176 if (equality_comparison_p
12177 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12178 XEXP (op0
, 1), op1
)))
12180 op0
= XEXP (op0
, 0);
12185 if (equality_comparison_p
12186 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12187 XEXP (op0
, 0), op1
)))
12189 op0
= XEXP (op0
, 1);
12194 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12195 of bits in X minus 1, is one iff X > 0. */
12196 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12197 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12198 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12199 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12201 op0
= XEXP (op0
, 1);
12202 code
= (code
== GE
? LE
: GT
);
12208 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12209 if C is zero or B is a constant. */
12210 if (equality_comparison_p
12211 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12212 XEXP (op0
, 1), op1
)))
12214 op0
= XEXP (op0
, 0);
12221 case UNEQ
: case LTGT
:
12222 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12223 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12224 case UNORDERED
: case ORDERED
:
12225 /* We can't do anything if OP0 is a condition code value, rather
12226 than an actual data value. */
12228 || CC0_P (XEXP (op0
, 0))
12229 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12232 /* Get the two operands being compared. */
12233 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12234 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12236 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12238 /* Check for the cases where we simply want the result of the
12239 earlier test or the opposite of that result. */
12240 if (code
== NE
|| code
== EQ
12241 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12242 && (code
== LT
|| code
== GE
)))
12244 enum rtx_code new_code
;
12245 if (code
== LT
|| code
== NE
)
12246 new_code
= GET_CODE (op0
);
12248 new_code
= reversed_comparison_code (op0
, NULL
);
12250 if (new_code
!= UNKNOWN
)
12261 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12263 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12264 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12265 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12267 op0
= XEXP (op0
, 1);
12268 code
= (code
== GE
? GT
: LE
);
12274 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12275 will be converted to a ZERO_EXTRACT later. */
12276 if (const_op
== 0 && equality_comparison_p
12277 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12278 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12280 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12281 XEXP (XEXP (op0
, 0), 1));
12282 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12286 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12287 zero and X is a comparison and C1 and C2 describe only bits set
12288 in STORE_FLAG_VALUE, we can compare with X. */
12289 if (const_op
== 0 && equality_comparison_p
12290 && mode_width
<= HOST_BITS_PER_WIDE_INT
12291 && CONST_INT_P (XEXP (op0
, 1))
12292 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12293 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12294 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12295 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12297 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12298 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12299 if ((~STORE_FLAG_VALUE
& mask
) == 0
12300 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12301 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12302 && COMPARISON_P (tem
))))
12304 op0
= XEXP (XEXP (op0
, 0), 0);
12309 /* If we are doing an equality comparison of an AND of a bit equal
12310 to the sign bit, replace this with a LT or GE comparison of
12311 the underlying value. */
12312 if (equality_comparison_p
12314 && CONST_INT_P (XEXP (op0
, 1))
12315 && mode_width
<= HOST_BITS_PER_WIDE_INT
12316 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12317 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12319 op0
= XEXP (op0
, 0);
12320 code
= (code
== EQ
? GE
: LT
);
12324 /* If this AND operation is really a ZERO_EXTEND from a narrower
12325 mode, the constant fits within that mode, and this is either an
12326 equality or unsigned comparison, try to do this comparison in
12331 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12332 -> (ne:DI (reg:SI 4) (const_int 0))
12334 unless TRULY_NOOP_TRUNCATION allows it or the register is
12335 known to hold a value of the required mode the
12336 transformation is invalid. */
12337 if ((equality_comparison_p
|| unsigned_comparison_p
)
12338 && CONST_INT_P (XEXP (op0
, 1))
12339 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12340 & GET_MODE_MASK (mode
))
12342 && const_op
>> i
== 0
12343 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12345 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12349 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12350 fits in both M1 and M2 and the SUBREG is either paradoxical
12351 or represents the low part, permute the SUBREG and the AND
12353 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12354 && CONST_INT_P (XEXP (op0
, 1)))
12356 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12357 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12358 /* Require an integral mode, to avoid creating something like
12360 if (SCALAR_INT_MODE_P (tmode
)
12361 /* It is unsafe to commute the AND into the SUBREG if the
12362 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12363 not defined. As originally written the upper bits
12364 have a defined value due to the AND operation.
12365 However, if we commute the AND inside the SUBREG then
12366 they no longer have defined values and the meaning of
12367 the code has been changed.
12368 Also C1 should not change value in the smaller mode,
12369 see PR67028 (a positive C1 can become negative in the
12370 smaller mode, so that the AND does no longer mask the
12372 && ((WORD_REGISTER_OPERATIONS
12373 && mode_width
> GET_MODE_PRECISION (tmode
)
12374 && mode_width
<= BITS_PER_WORD
12375 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12376 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12377 && subreg_lowpart_p (XEXP (op0
, 0))))
12378 && mode_width
<= HOST_BITS_PER_WIDE_INT
12379 && HWI_COMPUTABLE_MODE_P (tmode
)
12380 && (c1
& ~mask
) == 0
12381 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12383 && c1
!= GET_MODE_MASK (tmode
))
12385 op0
= simplify_gen_binary (AND
, tmode
,
12386 SUBREG_REG (XEXP (op0
, 0)),
12387 gen_int_mode (c1
, tmode
));
12388 op0
= gen_lowpart (mode
, op0
);
12393 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12394 if (const_op
== 0 && equality_comparison_p
12395 && XEXP (op0
, 1) == const1_rtx
12396 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12398 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12399 XEXP (XEXP (op0
, 0), 0), 1);
12400 code
= (code
== NE
? EQ
: NE
);
12404 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12405 (eq (and (lshiftrt X) 1) 0).
12406 Also handle the case where (not X) is expressed using xor. */
12407 if (const_op
== 0 && equality_comparison_p
12408 && XEXP (op0
, 1) == const1_rtx
12409 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12411 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12412 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12414 if (GET_CODE (shift_op
) == NOT
12415 || (GET_CODE (shift_op
) == XOR
12416 && CONST_INT_P (XEXP (shift_op
, 1))
12417 && CONST_INT_P (shift_count
)
12418 && HWI_COMPUTABLE_MODE_P (mode
)
12419 && (UINTVAL (XEXP (shift_op
, 1))
12420 == HOST_WIDE_INT_1U
12421 << INTVAL (shift_count
))))
12424 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12425 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12426 code
= (code
== NE
? EQ
: NE
);
12433 /* If we have (compare (ashift FOO N) (const_int C)) and
12434 the high order N bits of FOO (N+1 if an inequality comparison)
12435 are known to be zero, we can do this by comparing FOO with C
12436 shifted right N bits so long as the low-order N bits of C are
12438 if (CONST_INT_P (XEXP (op0
, 1))
12439 && INTVAL (XEXP (op0
, 1)) >= 0
12440 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12441 < HOST_BITS_PER_WIDE_INT
)
12442 && (((unsigned HOST_WIDE_INT
) const_op
12443 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12445 && mode_width
<= HOST_BITS_PER_WIDE_INT
12446 && (nonzero_bits (XEXP (op0
, 0), mode
)
12447 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12448 + ! equality_comparison_p
))) == 0)
12450 /* We must perform a logical shift, not an arithmetic one,
12451 as we want the top N bits of C to be zero. */
12452 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12454 temp
>>= INTVAL (XEXP (op0
, 1));
12455 op1
= gen_int_mode (temp
, mode
);
12456 op0
= XEXP (op0
, 0);
12460 /* If we are doing a sign bit comparison, it means we are testing
12461 a particular bit. Convert it to the appropriate AND. */
12462 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12463 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12465 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12468 - INTVAL (XEXP (op0
, 1)))));
12469 code
= (code
== LT
? NE
: EQ
);
12473 /* If this an equality comparison with zero and we are shifting
12474 the low bit to the sign bit, we can convert this to an AND of the
12476 if (const_op
== 0 && equality_comparison_p
12477 && CONST_INT_P (XEXP (op0
, 1))
12478 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12480 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12486 /* If this is an equality comparison with zero, we can do this
12487 as a logical shift, which might be much simpler. */
12488 if (equality_comparison_p
&& const_op
== 0
12489 && CONST_INT_P (XEXP (op0
, 1)))
12491 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12493 INTVAL (XEXP (op0
, 1)));
12497 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12498 do the comparison in a narrower mode. */
12499 if (! unsigned_comparison_p
12500 && CONST_INT_P (XEXP (op0
, 1))
12501 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12502 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12503 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12504 MODE_INT
, 1)) != BLKmode
12505 && (((unsigned HOST_WIDE_INT
) const_op
12506 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12507 <= GET_MODE_MASK (tmode
)))
12509 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12513 /* Likewise if OP0 is a PLUS of a sign extension with a
12514 constant, which is usually represented with the PLUS
12515 between the shifts. */
12516 if (! unsigned_comparison_p
12517 && CONST_INT_P (XEXP (op0
, 1))
12518 && GET_CODE (XEXP (op0
, 0)) == PLUS
12519 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12520 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12521 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12522 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12523 MODE_INT
, 1)) != BLKmode
12524 && (((unsigned HOST_WIDE_INT
) const_op
12525 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12526 <= GET_MODE_MASK (tmode
)))
12528 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12529 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12530 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12531 add_const
, XEXP (op0
, 1));
12533 op0
= simplify_gen_binary (PLUS
, tmode
,
12534 gen_lowpart (tmode
, inner
),
12541 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12542 the low order N bits of FOO are known to be zero, we can do this
12543 by comparing FOO with C shifted left N bits so long as no
12544 overflow occurs. Even if the low order N bits of FOO aren't known
12545 to be zero, if the comparison is >= or < we can use the same
12546 optimization and for > or <= by setting all the low
12547 order N bits in the comparison constant. */
12548 if (CONST_INT_P (XEXP (op0
, 1))
12549 && INTVAL (XEXP (op0
, 1)) > 0
12550 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12551 && mode_width
<= HOST_BITS_PER_WIDE_INT
12552 && (((unsigned HOST_WIDE_INT
) const_op
12553 + (GET_CODE (op0
) != LSHIFTRT
12554 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12557 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12559 unsigned HOST_WIDE_INT low_bits
12560 = (nonzero_bits (XEXP (op0
, 0), mode
)
12561 & ((HOST_WIDE_INT_1U
12562 << INTVAL (XEXP (op0
, 1))) - 1));
12563 if (low_bits
== 0 || !equality_comparison_p
)
12565 /* If the shift was logical, then we must make the condition
12567 if (GET_CODE (op0
) == LSHIFTRT
)
12568 code
= unsigned_condition (code
);
12570 const_op
= (unsigned HOST_WIDE_INT
) const_op
12571 << INTVAL (XEXP (op0
, 1));
12573 && (code
== GT
|| code
== GTU
12574 || code
== LE
|| code
== LEU
))
12576 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12577 op1
= GEN_INT (const_op
);
12578 op0
= XEXP (op0
, 0);
12583 /* If we are using this shift to extract just the sign bit, we
12584 can replace this with an LT or GE comparison. */
12586 && (equality_comparison_p
|| sign_bit_comparison_p
)
12587 && CONST_INT_P (XEXP (op0
, 1))
12588 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12590 op0
= XEXP (op0
, 0);
12591 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12603 /* Now make any compound operations involved in this comparison. Then,
12604 check for an outmost SUBREG on OP0 that is not doing anything or is
12605 paradoxical. The latter transformation must only be performed when
12606 it is known that the "extra" bits will be the same in op0 and op1 or
12607 that they don't matter. There are three cases to consider:
12609 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12610 care bits and we can assume they have any convenient value. So
12611 making the transformation is safe.
12613 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12614 In this case the upper bits of op0 are undefined. We should not make
12615 the simplification in that case as we do not know the contents of
12618 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12619 In that case we know those bits are zeros or ones. We must also be
12620 sure that they are the same as the upper bits of op1.
12622 We can never remove a SUBREG for a non-equality comparison because
12623 the sign bit is in a different place in the underlying object. */
12625 rtx_code op0_mco_code
= SET
;
12626 if (op1
== const0_rtx
)
12627 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12629 op0
= make_compound_operation (op0
, op0_mco_code
);
12630 op1
= make_compound_operation (op1
, SET
);
12632 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12633 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12634 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12635 && (code
== NE
|| code
== EQ
))
12637 if (paradoxical_subreg_p (op0
))
12639 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12641 if (REG_P (SUBREG_REG (op0
)))
12643 op0
= SUBREG_REG (op0
);
12644 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12647 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12648 <= HOST_BITS_PER_WIDE_INT
)
12649 && (nonzero_bits (SUBREG_REG (op0
),
12650 GET_MODE (SUBREG_REG (op0
)))
12651 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12653 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12655 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12656 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12657 op0
= SUBREG_REG (op0
), op1
= tem
;
12661 /* We now do the opposite procedure: Some machines don't have compare
12662 insns in all modes. If OP0's mode is an integer mode smaller than a
12663 word and we can't do a compare in that mode, see if there is a larger
12664 mode for which we can do the compare. There are a number of cases in
12665 which we can use the wider mode. */
12667 mode
= GET_MODE (op0
);
12668 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12669 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12670 && ! have_insn_for (COMPARE
, mode
))
12671 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12672 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12673 tmode
= GET_MODE_WIDER_MODE (tmode
))
12674 if (have_insn_for (COMPARE
, tmode
))
12678 /* If this is a test for negative, we can make an explicit
12679 test of the sign bit. Test this first so we can use
12680 a paradoxical subreg to extend OP0. */
12682 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12683 && HWI_COMPUTABLE_MODE_P (mode
))
12685 unsigned HOST_WIDE_INT sign
12686 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12687 op0
= simplify_gen_binary (AND
, tmode
,
12688 gen_lowpart (tmode
, op0
),
12689 gen_int_mode (sign
, tmode
));
12690 code
= (code
== LT
) ? NE
: EQ
;
12694 /* If the only nonzero bits in OP0 and OP1 are those in the
12695 narrower mode and this is an equality or unsigned comparison,
12696 we can use the wider mode. Similarly for sign-extended
12697 values, in which case it is true for all comparisons. */
12698 zero_extended
= ((code
== EQ
|| code
== NE
12699 || code
== GEU
|| code
== GTU
12700 || code
== LEU
|| code
== LTU
)
12701 && (nonzero_bits (op0
, tmode
)
12702 & ~GET_MODE_MASK (mode
)) == 0
12703 && ((CONST_INT_P (op1
)
12704 || (nonzero_bits (op1
, tmode
)
12705 & ~GET_MODE_MASK (mode
)) == 0)));
12708 || ((num_sign_bit_copies (op0
, tmode
)
12709 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12710 - GET_MODE_PRECISION (mode
)))
12711 && (num_sign_bit_copies (op1
, tmode
)
12712 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12713 - GET_MODE_PRECISION (mode
)))))
12715 /* If OP0 is an AND and we don't have an AND in MODE either,
12716 make a new AND in the proper mode. */
12717 if (GET_CODE (op0
) == AND
12718 && !have_insn_for (AND
, mode
))
12719 op0
= simplify_gen_binary (AND
, tmode
,
12720 gen_lowpart (tmode
,
12722 gen_lowpart (tmode
,
12728 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12729 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12733 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12734 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12741 /* We may have changed the comparison operands. Re-canonicalize. */
12742 if (swap_commutative_operands_p (op0
, op1
))
12744 std::swap (op0
, op1
);
12745 code
= swap_condition (code
);
12748 /* If this machine only supports a subset of valid comparisons, see if we
12749 can convert an unsupported one into a supported one. */
12750 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12758 /* Utility function for record_value_for_reg. Count number of
12763 enum rtx_code code
= GET_CODE (x
);
12767 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12768 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12770 rtx x0
= XEXP (x
, 0);
12771 rtx x1
= XEXP (x
, 1);
12774 return 1 + 2 * count_rtxs (x0
);
12776 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12777 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12778 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12779 return 2 + 2 * count_rtxs (x0
)
12780 + count_rtxs (x
== XEXP (x1
, 0)
12781 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12783 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12784 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12785 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12786 return 2 + 2 * count_rtxs (x1
)
12787 + count_rtxs (x
== XEXP (x0
, 0)
12788 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12791 fmt
= GET_RTX_FORMAT (code
);
12792 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12794 ret
+= count_rtxs (XEXP (x
, i
));
12795 else if (fmt
[i
] == 'E')
12796 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12797 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12802 /* Utility function for following routine. Called when X is part of a value
12803 being stored into last_set_value. Sets last_set_table_tick
12804 for each register mentioned. Similar to mention_regs in cse.c */
12807 update_table_tick (rtx x
)
12809 enum rtx_code code
= GET_CODE (x
);
12810 const char *fmt
= GET_RTX_FORMAT (code
);
12815 unsigned int regno
= REGNO (x
);
12816 unsigned int endregno
= END_REGNO (x
);
12819 for (r
= regno
; r
< endregno
; r
++)
12821 reg_stat_type
*rsp
= ®_stat
[r
];
12822 rsp
->last_set_table_tick
= label_tick
;
12828 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12831 /* Check for identical subexpressions. If x contains
12832 identical subexpression we only have to traverse one of
12834 if (i
== 0 && ARITHMETIC_P (x
))
12836 /* Note that at this point x1 has already been
12838 rtx x0
= XEXP (x
, 0);
12839 rtx x1
= XEXP (x
, 1);
12841 /* If x0 and x1 are identical then there is no need to
12846 /* If x0 is identical to a subexpression of x1 then while
12847 processing x1, x0 has already been processed. Thus we
12848 are done with x. */
12849 if (ARITHMETIC_P (x1
)
12850 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12853 /* If x1 is identical to a subexpression of x0 then we
12854 still have to process the rest of x0. */
12855 if (ARITHMETIC_P (x0
)
12856 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12858 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12863 update_table_tick (XEXP (x
, i
));
12865 else if (fmt
[i
] == 'E')
12866 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12867 update_table_tick (XVECEXP (x
, i
, j
));
12870 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12871 are saying that the register is clobbered and we no longer know its
12872 value. If INSN is zero, don't update reg_stat[].last_set; this is
12873 only permitted with VALUE also zero and is used to invalidate the
12877 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12879 unsigned int regno
= REGNO (reg
);
12880 unsigned int endregno
= END_REGNO (reg
);
12882 reg_stat_type
*rsp
;
12884 /* If VALUE contains REG and we have a previous value for REG, substitute
12885 the previous value. */
12886 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12890 /* Set things up so get_last_value is allowed to see anything set up to
12892 subst_low_luid
= DF_INSN_LUID (insn
);
12893 tem
= get_last_value (reg
);
12895 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12896 it isn't going to be useful and will take a lot of time to process,
12897 so just use the CLOBBER. */
12901 if (ARITHMETIC_P (tem
)
12902 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12903 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12904 tem
= XEXP (tem
, 0);
12905 else if (count_occurrences (value
, reg
, 1) >= 2)
12907 /* If there are two or more occurrences of REG in VALUE,
12908 prevent the value from growing too much. */
12909 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12910 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12913 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12917 /* For each register modified, show we don't know its value, that
12918 we don't know about its bitwise content, that its value has been
12919 updated, and that we don't know the location of the death of the
12921 for (i
= regno
; i
< endregno
; i
++)
12923 rsp
= ®_stat
[i
];
12926 rsp
->last_set
= insn
;
12928 rsp
->last_set_value
= 0;
12929 rsp
->last_set_mode
= VOIDmode
;
12930 rsp
->last_set_nonzero_bits
= 0;
12931 rsp
->last_set_sign_bit_copies
= 0;
12932 rsp
->last_death
= 0;
12933 rsp
->truncated_to_mode
= VOIDmode
;
12936 /* Mark registers that are being referenced in this value. */
12938 update_table_tick (value
);
12940 /* Now update the status of each register being set.
12941 If someone is using this register in this block, set this register
12942 to invalid since we will get confused between the two lives in this
12943 basic block. This makes using this register always invalid. In cse, we
12944 scan the table to invalidate all entries using this register, but this
12945 is too much work for us. */
12947 for (i
= regno
; i
< endregno
; i
++)
12949 rsp
= ®_stat
[i
];
12950 rsp
->last_set_label
= label_tick
;
12952 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12953 rsp
->last_set_invalid
= 1;
12955 rsp
->last_set_invalid
= 0;
12958 /* The value being assigned might refer to X (like in "x++;"). In that
12959 case, we must replace it with (clobber (const_int 0)) to prevent
12961 rsp
= ®_stat
[regno
];
12962 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12964 value
= copy_rtx (value
);
12965 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12969 /* For the main register being modified, update the value, the mode, the
12970 nonzero bits, and the number of sign bit copies. */
12972 rsp
->last_set_value
= value
;
12976 machine_mode mode
= GET_MODE (reg
);
12977 subst_low_luid
= DF_INSN_LUID (insn
);
12978 rsp
->last_set_mode
= mode
;
12979 if (GET_MODE_CLASS (mode
) == MODE_INT
12980 && HWI_COMPUTABLE_MODE_P (mode
))
12981 mode
= nonzero_bits_mode
;
12982 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12983 rsp
->last_set_sign_bit_copies
12984 = num_sign_bit_copies (value
, GET_MODE (reg
));
12988 /* Called via note_stores from record_dead_and_set_regs to handle one
12989 SET or CLOBBER in an insn. DATA is the instruction in which the
12990 set is occurring. */
12993 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12995 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12997 if (GET_CODE (dest
) == SUBREG
)
12998 dest
= SUBREG_REG (dest
);
13000 if (!record_dead_insn
)
13003 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13009 /* If we are setting the whole register, we know its value. Otherwise
13010 show that we don't know the value. We can handle SUBREG in
13012 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13013 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13014 else if (GET_CODE (setter
) == SET
13015 && GET_CODE (SET_DEST (setter
)) == SUBREG
13016 && SUBREG_REG (SET_DEST (setter
)) == dest
13017 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13018 && subreg_lowpart_p (SET_DEST (setter
)))
13019 record_value_for_reg (dest
, record_dead_insn
,
13020 gen_lowpart (GET_MODE (dest
),
13021 SET_SRC (setter
)));
13023 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13025 else if (MEM_P (dest
)
13026 /* Ignore pushes, they clobber nothing. */
13027 && ! push_operand (dest
, GET_MODE (dest
)))
13028 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13031 /* Update the records of when each REG was most recently set or killed
13032 for the things done by INSN. This is the last thing done in processing
13033 INSN in the combiner loop.
13035 We update reg_stat[], in particular fields last_set, last_set_value,
13036 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13037 last_death, and also the similar information mem_last_set (which insn
13038 most recently modified memory) and last_call_luid (which insn was the
13039 most recent subroutine call). */
13042 record_dead_and_set_regs (rtx_insn
*insn
)
13047 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13049 if (REG_NOTE_KIND (link
) == REG_DEAD
13050 && REG_P (XEXP (link
, 0)))
13052 unsigned int regno
= REGNO (XEXP (link
, 0));
13053 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13055 for (i
= regno
; i
< endregno
; i
++)
13057 reg_stat_type
*rsp
;
13059 rsp
= ®_stat
[i
];
13060 rsp
->last_death
= insn
;
13063 else if (REG_NOTE_KIND (link
) == REG_INC
)
13064 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13069 hard_reg_set_iterator hrsi
;
13070 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13072 reg_stat_type
*rsp
;
13074 rsp
= ®_stat
[i
];
13075 rsp
->last_set_invalid
= 1;
13076 rsp
->last_set
= insn
;
13077 rsp
->last_set_value
= 0;
13078 rsp
->last_set_mode
= VOIDmode
;
13079 rsp
->last_set_nonzero_bits
= 0;
13080 rsp
->last_set_sign_bit_copies
= 0;
13081 rsp
->last_death
= 0;
13082 rsp
->truncated_to_mode
= VOIDmode
;
13085 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13087 /* We can't combine into a call pattern. Remember, though, that
13088 the return value register is set at this LUID. We could
13089 still replace a register with the return value from the
13090 wrong subroutine call! */
13091 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13094 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13097 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13098 register present in the SUBREG, so for each such SUBREG go back and
13099 adjust nonzero and sign bit information of the registers that are
13100 known to have some zero/sign bits set.
13102 This is needed because when combine blows the SUBREGs away, the
13103 information on zero/sign bits is lost and further combines can be
13104 missed because of that. */
13107 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13109 struct insn_link
*links
;
13111 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13112 machine_mode mode
= GET_MODE (subreg
);
13114 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
13117 for (links
= LOG_LINKS (insn
); links
;)
13119 reg_stat_type
*rsp
;
13121 insn
= links
->insn
;
13122 set
= single_set (insn
);
13124 if (! set
|| !REG_P (SET_DEST (set
))
13125 || REGNO (SET_DEST (set
)) != regno
13126 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13128 links
= links
->next
;
13132 rsp
= ®_stat
[regno
];
13133 if (rsp
->last_set
== insn
)
13135 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13136 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13139 if (REG_P (SET_SRC (set
)))
13141 regno
= REGNO (SET_SRC (set
));
13142 links
= LOG_LINKS (insn
);
13149 /* Check if X, a register, is known to contain a value already
13150 truncated to MODE. In this case we can use a subreg to refer to
13151 the truncated value even though in the generic case we would need
13152 an explicit truncation. */
13155 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13157 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13158 machine_mode truncated
= rsp
->truncated_to_mode
;
13161 || rsp
->truncation_label
< label_tick_ebb_start
)
13163 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
13165 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13170 /* If X is a hard reg or a subreg record the mode that the register is
13171 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13172 to turn a truncate into a subreg using this information. Return true
13173 if traversing X is complete. */
13176 record_truncated_value (rtx x
)
13178 machine_mode truncated_mode
;
13179 reg_stat_type
*rsp
;
13181 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13183 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13184 truncated_mode
= GET_MODE (x
);
13186 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
13189 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13192 x
= SUBREG_REG (x
);
13194 /* ??? For hard-regs we now record everything. We might be able to
13195 optimize this using last_set_mode. */
13196 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13197 truncated_mode
= GET_MODE (x
);
13201 rsp
= ®_stat
[REGNO (x
)];
13202 if (rsp
->truncated_to_mode
== 0
13203 || rsp
->truncation_label
< label_tick_ebb_start
13204 || (GET_MODE_SIZE (truncated_mode
)
13205 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13207 rsp
->truncated_to_mode
= truncated_mode
;
13208 rsp
->truncation_label
= label_tick
;
13214 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13215 the modes they are used in. This can help truning TRUNCATEs into
13219 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13221 subrtx_var_iterator::array_type array
;
13222 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13223 if (record_truncated_value (*iter
))
13224 iter
.skip_subrtxes ();
13227 /* Scan X for promoted SUBREGs. For each one found,
13228 note what it implies to the registers used in it. */
13231 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13233 if (GET_CODE (x
) == SUBREG
13234 && SUBREG_PROMOTED_VAR_P (x
)
13235 && REG_P (SUBREG_REG (x
)))
13236 record_promoted_value (insn
, x
);
13239 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13242 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13246 check_promoted_subreg (insn
, XEXP (x
, i
));
13250 if (XVEC (x
, i
) != 0)
13251 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13252 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13258 /* Verify that all the registers and memory references mentioned in *LOC are
13259 still valid. *LOC was part of a value set in INSN when label_tick was
13260 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13261 the invalid references with (clobber (const_int 0)) and return 1. This
13262 replacement is useful because we often can get useful information about
13263 the form of a value (e.g., if it was produced by a shift that always
13264 produces -1 or 0) even though we don't know exactly what registers it
13265 was produced from. */
13268 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13271 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13272 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13277 unsigned int regno
= REGNO (x
);
13278 unsigned int endregno
= END_REGNO (x
);
13281 for (j
= regno
; j
< endregno
; j
++)
13283 reg_stat_type
*rsp
= ®_stat
[j
];
13284 if (rsp
->last_set_invalid
13285 /* If this is a pseudo-register that was only set once and not
13286 live at the beginning of the function, it is always valid. */
13287 || (! (regno
>= FIRST_PSEUDO_REGISTER
13288 && regno
< reg_n_sets_max
13289 && REG_N_SETS (regno
) == 1
13290 && (!REGNO_REG_SET_P
13291 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13293 && rsp
->last_set_label
> tick
))
13296 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13303 /* If this is a memory reference, make sure that there were no stores after
13304 it that might have clobbered the value. We don't have alias info, so we
13305 assume any store invalidates it. Moreover, we only have local UIDs, so
13306 we also assume that there were stores in the intervening basic blocks. */
13307 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13308 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13311 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13315 for (i
= 0; i
< len
; i
++)
13319 /* Check for identical subexpressions. If x contains
13320 identical subexpression we only have to traverse one of
13322 if (i
== 1 && ARITHMETIC_P (x
))
13324 /* Note that at this point x0 has already been checked
13325 and found valid. */
13326 rtx x0
= XEXP (x
, 0);
13327 rtx x1
= XEXP (x
, 1);
13329 /* If x0 and x1 are identical then x is also valid. */
13333 /* If x1 is identical to a subexpression of x0 then
13334 while checking x0, x1 has already been checked. Thus
13335 it is valid and so as x. */
13336 if (ARITHMETIC_P (x0
)
13337 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13340 /* If x0 is identical to a subexpression of x1 then x is
13341 valid iff the rest of x1 is valid. */
13342 if (ARITHMETIC_P (x1
)
13343 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13345 get_last_value_validate (&XEXP (x1
,
13346 x0
== XEXP (x1
, 0) ? 1 : 0),
13347 insn
, tick
, replace
);
13350 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13354 else if (fmt
[i
] == 'E')
13355 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13356 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13357 insn
, tick
, replace
) == 0)
13361 /* If we haven't found a reason for it to be invalid, it is valid. */
13365 /* Get the last value assigned to X, if known. Some registers
13366 in the value may be replaced with (clobber (const_int 0)) if their value
13367 is known longer known reliably. */
13370 get_last_value (const_rtx x
)
13372 unsigned int regno
;
13374 reg_stat_type
*rsp
;
13376 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13377 then convert it to the desired mode. If this is a paradoxical SUBREG,
13378 we cannot predict what values the "extra" bits might have. */
13379 if (GET_CODE (x
) == SUBREG
13380 && subreg_lowpart_p (x
)
13381 && !paradoxical_subreg_p (x
)
13382 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13383 return gen_lowpart (GET_MODE (x
), value
);
13389 rsp
= ®_stat
[regno
];
13390 value
= rsp
->last_set_value
;
13392 /* If we don't have a value, or if it isn't for this basic block and
13393 it's either a hard register, set more than once, or it's a live
13394 at the beginning of the function, return 0.
13396 Because if it's not live at the beginning of the function then the reg
13397 is always set before being used (is never used without being set).
13398 And, if it's set only once, and it's always set before use, then all
13399 uses must have the same last value, even if it's not from this basic
13403 || (rsp
->last_set_label
< label_tick_ebb_start
13404 && (regno
< FIRST_PSEUDO_REGISTER
13405 || regno
>= reg_n_sets_max
13406 || REG_N_SETS (regno
) != 1
13408 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13411 /* If the value was set in a later insn than the ones we are processing,
13412 we can't use it even if the register was only set once. */
13413 if (rsp
->last_set_label
== label_tick
13414 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13417 /* If fewer bits were set than what we are asked for now, we cannot use
13419 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13420 < GET_MODE_PRECISION (GET_MODE (x
)))
13423 /* If the value has all its registers valid, return it. */
13424 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13427 /* Otherwise, make a copy and replace any invalid register with
13428 (clobber (const_int 0)). If that fails for some reason, return 0. */
13430 value
= copy_rtx (value
);
13431 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13437 /* Return nonzero if expression X refers to a REG or to memory
13438 that is set in an instruction more recent than FROM_LUID. */
13441 use_crosses_set_p (const_rtx x
, int from_luid
)
13445 enum rtx_code code
= GET_CODE (x
);
13449 unsigned int regno
= REGNO (x
);
13450 unsigned endreg
= END_REGNO (x
);
13452 #ifdef PUSH_ROUNDING
13453 /* Don't allow uses of the stack pointer to be moved,
13454 because we don't know whether the move crosses a push insn. */
13455 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13458 for (; regno
< endreg
; regno
++)
13460 reg_stat_type
*rsp
= ®_stat
[regno
];
13462 && rsp
->last_set_label
== label_tick
13463 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13469 if (code
== MEM
&& mem_last_set
> from_luid
)
13472 fmt
= GET_RTX_FORMAT (code
);
13474 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13479 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13480 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13483 else if (fmt
[i
] == 'e'
13484 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13490 /* Define three variables used for communication between the following
13493 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13494 static int reg_dead_flag
;
13496 /* Function called via note_stores from reg_dead_at_p.
13498 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13499 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13502 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13504 unsigned int regno
, endregno
;
13509 regno
= REGNO (dest
);
13510 endregno
= END_REGNO (dest
);
13511 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13512 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13515 /* Return nonzero if REG is known to be dead at INSN.
13517 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13518 referencing REG, it is dead. If we hit a SET referencing REG, it is
13519 live. Otherwise, see if it is live or dead at the start of the basic
13520 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13521 must be assumed to be always live. */
13524 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13529 /* Set variables for reg_dead_at_p_1. */
13530 reg_dead_regno
= REGNO (reg
);
13531 reg_dead_endregno
= END_REGNO (reg
);
13535 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13536 we allow the machine description to decide whether use-and-clobber
13537 patterns are OK. */
13538 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13540 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13541 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13545 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13546 beginning of basic block. */
13547 block
= BLOCK_FOR_INSN (insn
);
13552 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13555 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13557 return reg_dead_flag
== 1 ? 1 : 0;
13559 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13563 if (insn
== BB_HEAD (block
))
13566 insn
= PREV_INSN (insn
);
13569 /* Look at live-in sets for the basic block that we were in. */
13570 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13571 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13577 /* Note hard registers in X that are used. */
13580 mark_used_regs_combine (rtx x
)
13582 RTX_CODE code
= GET_CODE (x
);
13583 unsigned int regno
;
13594 case ADDR_DIFF_VEC
:
13596 /* CC0 must die in the insn after it is set, so we don't need to take
13597 special note of it here. */
13602 /* If we are clobbering a MEM, mark any hard registers inside the
13603 address as used. */
13604 if (MEM_P (XEXP (x
, 0)))
13605 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13610 /* A hard reg in a wide mode may really be multiple registers.
13611 If so, mark all of them just like the first. */
13612 if (regno
< FIRST_PSEUDO_REGISTER
)
13614 /* None of this applies to the stack, frame or arg pointers. */
13615 if (regno
== STACK_POINTER_REGNUM
13616 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13617 && regno
== HARD_FRAME_POINTER_REGNUM
)
13618 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13619 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13620 || regno
== FRAME_POINTER_REGNUM
)
13623 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13629 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13631 rtx testreg
= SET_DEST (x
);
13633 while (GET_CODE (testreg
) == SUBREG
13634 || GET_CODE (testreg
) == ZERO_EXTRACT
13635 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13636 testreg
= XEXP (testreg
, 0);
13638 if (MEM_P (testreg
))
13639 mark_used_regs_combine (XEXP (testreg
, 0));
13641 mark_used_regs_combine (SET_SRC (x
));
13649 /* Recursively scan the operands of this expression. */
13652 const char *fmt
= GET_RTX_FORMAT (code
);
13654 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13657 mark_used_regs_combine (XEXP (x
, i
));
13658 else if (fmt
[i
] == 'E')
13662 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13663 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13669 /* Remove register number REGNO from the dead registers list of INSN.
13671 Return the note used to record the death, if there was one. */
13674 remove_death (unsigned int regno
, rtx_insn
*insn
)
13676 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13679 remove_note (insn
, note
);
13684 /* For each register (hardware or pseudo) used within expression X, if its
13685 death is in an instruction with luid between FROM_LUID (inclusive) and
13686 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13687 list headed by PNOTES.
13689 That said, don't move registers killed by maybe_kill_insn.
13691 This is done when X is being merged by combination into TO_INSN. These
13692 notes will then be distributed as needed. */
13695 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13700 enum rtx_code code
= GET_CODE (x
);
13704 unsigned int regno
= REGNO (x
);
13705 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13707 /* Don't move the register if it gets killed in between from and to. */
13708 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13709 && ! reg_referenced_p (x
, maybe_kill_insn
))
13713 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13714 && DF_INSN_LUID (where_dead
) >= from_luid
13715 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13717 rtx note
= remove_death (regno
, where_dead
);
13719 /* It is possible for the call above to return 0. This can occur
13720 when last_death points to I2 or I1 that we combined with.
13721 In that case make a new note.
13723 We must also check for the case where X is a hard register
13724 and NOTE is a death note for a range of hard registers
13725 including X. In that case, we must put REG_DEAD notes for
13726 the remaining registers in place of NOTE. */
13728 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13729 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13730 > GET_MODE_SIZE (GET_MODE (x
))))
13732 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13733 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13734 unsigned int ourend
= END_REGNO (x
);
13737 for (i
= deadregno
; i
< deadend
; i
++)
13738 if (i
< regno
|| i
>= ourend
)
13739 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13742 /* If we didn't find any note, or if we found a REG_DEAD note that
13743 covers only part of the given reg, and we have a multi-reg hard
13744 register, then to be safe we must check for REG_DEAD notes
13745 for each register other than the first. They could have
13746 their own REG_DEAD notes lying around. */
13747 else if ((note
== 0
13749 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13750 < GET_MODE_SIZE (GET_MODE (x
)))))
13751 && regno
< FIRST_PSEUDO_REGISTER
13752 && REG_NREGS (x
) > 1)
13754 unsigned int ourend
= END_REGNO (x
);
13755 unsigned int i
, offset
;
13759 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13763 for (i
= regno
+ offset
; i
< ourend
; i
++)
13764 move_deaths (regno_reg_rtx
[i
],
13765 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13768 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13770 XEXP (note
, 1) = *pnotes
;
13774 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13780 else if (GET_CODE (x
) == SET
)
13782 rtx dest
= SET_DEST (x
);
13784 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13786 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13787 that accesses one word of a multi-word item, some
13788 piece of everything register in the expression is used by
13789 this insn, so remove any old death. */
13790 /* ??? So why do we test for equality of the sizes? */
13792 if (GET_CODE (dest
) == ZERO_EXTRACT
13793 || GET_CODE (dest
) == STRICT_LOW_PART
13794 || (GET_CODE (dest
) == SUBREG
13795 && (((GET_MODE_SIZE (GET_MODE (dest
))
13796 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13797 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13798 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13800 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13804 /* If this is some other SUBREG, we know it replaces the entire
13805 value, so use that as the destination. */
13806 if (GET_CODE (dest
) == SUBREG
)
13807 dest
= SUBREG_REG (dest
);
13809 /* If this is a MEM, adjust deaths of anything used in the address.
13810 For a REG (the only other possibility), the entire value is
13811 being replaced so the old value is not used in this insn. */
13814 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13819 else if (GET_CODE (x
) == CLOBBER
)
13822 len
= GET_RTX_LENGTH (code
);
13823 fmt
= GET_RTX_FORMAT (code
);
13825 for (i
= 0; i
< len
; i
++)
13830 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13831 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13834 else if (fmt
[i
] == 'e')
13835 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13839 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13840 pattern of an insn. X must be a REG. */
13843 reg_bitfield_target_p (rtx x
, rtx body
)
13847 if (GET_CODE (body
) == SET
)
13849 rtx dest
= SET_DEST (body
);
13851 unsigned int regno
, tregno
, endregno
, endtregno
;
13853 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13854 target
= XEXP (dest
, 0);
13855 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13856 target
= SUBREG_REG (XEXP (dest
, 0));
13860 if (GET_CODE (target
) == SUBREG
)
13861 target
= SUBREG_REG (target
);
13863 if (!REG_P (target
))
13866 tregno
= REGNO (target
), regno
= REGNO (x
);
13867 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13868 return target
== x
;
13870 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13871 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13873 return endregno
> tregno
&& regno
< endtregno
;
13876 else if (GET_CODE (body
) == PARALLEL
)
13877 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13878 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13884 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13885 as appropriate. I3 and I2 are the insns resulting from the combination
13886 insns including FROM (I2 may be zero).
13888 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13889 not need REG_DEAD notes because they are being substituted for. This
13890 saves searching in the most common cases.
13892 Each note in the list is either ignored or placed on some insns, depending
13893 on the type of note. */
13896 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13897 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13899 rtx note
, next_note
;
13901 rtx_insn
*tem_insn
;
13903 for (note
= notes
; note
; note
= next_note
)
13905 rtx_insn
*place
= 0, *place2
= 0;
13907 next_note
= XEXP (note
, 1);
13908 switch (REG_NOTE_KIND (note
))
13912 /* Doesn't matter much where we put this, as long as it's somewhere.
13913 It is preferable to keep these notes on branches, which is most
13914 likely to be i3. */
13918 case REG_NON_LOCAL_GOTO
:
13923 gcc_assert (i2
&& JUMP_P (i2
));
13928 case REG_EH_REGION
:
13929 /* These notes must remain with the call or trapping instruction. */
13932 else if (i2
&& CALL_P (i2
))
13936 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13937 if (may_trap_p (i3
))
13939 else if (i2
&& may_trap_p (i2
))
13941 /* ??? Otherwise assume we've combined things such that we
13942 can now prove that the instructions can't trap. Drop the
13943 note in this case. */
13947 case REG_ARGS_SIZE
:
13948 /* ??? How to distribute between i3-i1. Assume i3 contains the
13949 entire adjustment. Assert i3 contains at least some adjust. */
13950 if (!noop_move_p (i3
))
13952 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13953 /* fixup_args_size_notes looks at REG_NORETURN note,
13954 so ensure the note is placed there first. */
13958 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13959 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13963 XEXP (n
, 1) = REG_NOTES (i3
);
13964 REG_NOTES (i3
) = n
;
13968 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13969 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13970 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13971 gcc_assert (old_size
!= args_size
13973 && !ACCUMULATE_OUTGOING_ARGS
13974 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13981 case REG_CALL_DECL
:
13982 /* These notes must remain with the call. It should not be
13983 possible for both I2 and I3 to be a call. */
13988 gcc_assert (i2
&& CALL_P (i2
));
13994 /* Any clobbers for i3 may still exist, and so we must process
13995 REG_UNUSED notes from that insn.
13997 Any clobbers from i2 or i1 can only exist if they were added by
13998 recog_for_combine. In that case, recog_for_combine created the
13999 necessary REG_UNUSED notes. Trying to keep any original
14000 REG_UNUSED notes from these insns can cause incorrect output
14001 if it is for the same register as the original i3 dest.
14002 In that case, we will notice that the register is set in i3,
14003 and then add a REG_UNUSED note for the destination of i3, which
14004 is wrong. However, it is possible to have REG_UNUSED notes from
14005 i2 or i1 for register which were both used and clobbered, so
14006 we keep notes from i2 or i1 if they will turn into REG_DEAD
14009 /* If this register is set or clobbered in I3, put the note there
14010 unless there is one already. */
14011 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14013 if (from_insn
!= i3
)
14016 if (! (REG_P (XEXP (note
, 0))
14017 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14018 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14021 /* Otherwise, if this register is used by I3, then this register
14022 now dies here, so we must put a REG_DEAD note here unless there
14024 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14025 && ! (REG_P (XEXP (note
, 0))
14026 ? find_regno_note (i3
, REG_DEAD
,
14027 REGNO (XEXP (note
, 0)))
14028 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14030 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14038 /* These notes say something about results of an insn. We can
14039 only support them if they used to be on I3 in which case they
14040 remain on I3. Otherwise they are ignored.
14042 If the note refers to an expression that is not a constant, we
14043 must also ignore the note since we cannot tell whether the
14044 equivalence is still true. It might be possible to do
14045 slightly better than this (we only have a problem if I2DEST
14046 or I1DEST is present in the expression), but it doesn't
14047 seem worth the trouble. */
14049 if (from_insn
== i3
14050 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14055 /* These notes say something about how a register is used. They must
14056 be present on any use of the register in I2 or I3. */
14057 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14060 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14069 case REG_LABEL_TARGET
:
14070 case REG_LABEL_OPERAND
:
14071 /* This can show up in several ways -- either directly in the
14072 pattern, or hidden off in the constant pool with (or without?)
14073 a REG_EQUAL note. */
14074 /* ??? Ignore the without-reg_equal-note problem for now. */
14075 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14076 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14077 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14078 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14082 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14083 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14084 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14085 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14093 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14094 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14096 if (place
&& JUMP_P (place
)
14097 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14098 && (JUMP_LABEL (place
) == NULL
14099 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14101 rtx label
= JUMP_LABEL (place
);
14104 JUMP_LABEL (place
) = XEXP (note
, 0);
14105 else if (LABEL_P (label
))
14106 LABEL_NUSES (label
)--;
14109 if (place2
&& JUMP_P (place2
)
14110 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14111 && (JUMP_LABEL (place2
) == NULL
14112 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14114 rtx label
= JUMP_LABEL (place2
);
14117 JUMP_LABEL (place2
) = XEXP (note
, 0);
14118 else if (LABEL_P (label
))
14119 LABEL_NUSES (label
)--;
14125 /* This note says something about the value of a register prior
14126 to the execution of an insn. It is too much trouble to see
14127 if the note is still correct in all situations. It is better
14128 to simply delete it. */
14132 /* If we replaced the right hand side of FROM_INSN with a
14133 REG_EQUAL note, the original use of the dying register
14134 will not have been combined into I3 and I2. In such cases,
14135 FROM_INSN is guaranteed to be the first of the combined
14136 instructions, so we simply need to search back before
14137 FROM_INSN for the previous use or set of this register,
14138 then alter the notes there appropriately.
14140 If the register is used as an input in I3, it dies there.
14141 Similarly for I2, if it is nonzero and adjacent to I3.
14143 If the register is not used as an input in either I3 or I2
14144 and it is not one of the registers we were supposed to eliminate,
14145 there are two possibilities. We might have a non-adjacent I2
14146 or we might have somehow eliminated an additional register
14147 from a computation. For example, we might have had A & B where
14148 we discover that B will always be zero. In this case we will
14149 eliminate the reference to A.
14151 In both cases, we must search to see if we can find a previous
14152 use of A and put the death note there. */
14155 && from_insn
== i2mod
14156 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14157 tem_insn
= from_insn
;
14161 && CALL_P (from_insn
)
14162 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14164 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14166 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14167 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14169 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14171 && reg_overlap_mentioned_p (XEXP (note
, 0),
14173 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14174 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14177 /* If the new I2 sets the same register that is marked dead
14178 in the note, we do not know where to put the note.
14180 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14186 basic_block bb
= this_basic_block
;
14188 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14190 if (!NONDEBUG_INSN_P (tem_insn
))
14192 if (tem_insn
== BB_HEAD (bb
))
14197 /* If the register is being set at TEM_INSN, see if that is all
14198 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14199 into a REG_UNUSED note instead. Don't delete sets to
14200 global register vars. */
14201 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14202 || !global_regs
[REGNO (XEXP (note
, 0))])
14203 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14205 rtx set
= single_set (tem_insn
);
14206 rtx inner_dest
= 0;
14207 rtx_insn
*cc0_setter
= NULL
;
14210 for (inner_dest
= SET_DEST (set
);
14211 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14212 || GET_CODE (inner_dest
) == SUBREG
14213 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14214 inner_dest
= XEXP (inner_dest
, 0))
14217 /* Verify that it was the set, and not a clobber that
14218 modified the register.
14220 CC0 targets must be careful to maintain setter/user
14221 pairs. If we cannot delete the setter due to side
14222 effects, mark the user with an UNUSED note instead
14225 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14226 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14228 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14229 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14230 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14232 /* Move the notes and links of TEM_INSN elsewhere.
14233 This might delete other dead insns recursively.
14234 First set the pattern to something that won't use
14236 rtx old_notes
= REG_NOTES (tem_insn
);
14238 PATTERN (tem_insn
) = pc_rtx
;
14239 REG_NOTES (tem_insn
) = NULL
;
14241 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14242 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14243 distribute_links (LOG_LINKS (tem_insn
));
14245 SET_INSN_DELETED (tem_insn
);
14246 if (tem_insn
== i2
)
14249 /* Delete the setter too. */
14252 PATTERN (cc0_setter
) = pc_rtx
;
14253 old_notes
= REG_NOTES (cc0_setter
);
14254 REG_NOTES (cc0_setter
) = NULL
;
14256 distribute_notes (old_notes
, cc0_setter
,
14258 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14259 distribute_links (LOG_LINKS (cc0_setter
));
14261 SET_INSN_DELETED (cc0_setter
);
14262 if (cc0_setter
== i2
)
14268 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14270 /* If there isn't already a REG_UNUSED note, put one
14271 here. Do not place a REG_DEAD note, even if
14272 the register is also used here; that would not
14273 match the algorithm used in lifetime analysis
14274 and can cause the consistency check in the
14275 scheduler to fail. */
14276 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14277 REGNO (XEXP (note
, 0))))
14282 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14283 || (CALL_P (tem_insn
)
14284 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14288 /* If we are doing a 3->2 combination, and we have a
14289 register which formerly died in i3 and was not used
14290 by i2, which now no longer dies in i3 and is used in
14291 i2 but does not die in i2, and place is between i2
14292 and i3, then we may need to move a link from place to
14294 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14296 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14297 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14299 struct insn_link
*links
= LOG_LINKS (place
);
14300 LOG_LINKS (place
) = NULL
;
14301 distribute_links (links
);
14306 if (tem_insn
== BB_HEAD (bb
))
14312 /* If the register is set or already dead at PLACE, we needn't do
14313 anything with this note if it is still a REG_DEAD note.
14314 We check here if it is set at all, not if is it totally replaced,
14315 which is what `dead_or_set_p' checks, so also check for it being
14318 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14320 unsigned int regno
= REGNO (XEXP (note
, 0));
14321 reg_stat_type
*rsp
= ®_stat
[regno
];
14323 if (dead_or_set_p (place
, XEXP (note
, 0))
14324 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14326 /* Unless the register previously died in PLACE, clear
14327 last_death. [I no longer understand why this is
14329 if (rsp
->last_death
!= place
)
14330 rsp
->last_death
= 0;
14334 rsp
->last_death
= place
;
14336 /* If this is a death note for a hard reg that is occupying
14337 multiple registers, ensure that we are still using all
14338 parts of the object. If we find a piece of the object
14339 that is unused, we must arrange for an appropriate REG_DEAD
14340 note to be added for it. However, we can't just emit a USE
14341 and tag the note to it, since the register might actually
14342 be dead; so we recourse, and the recursive call then finds
14343 the previous insn that used this register. */
14345 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14347 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14348 bool all_used
= true;
14351 for (i
= regno
; i
< endregno
; i
++)
14352 if ((! refers_to_regno_p (i
, PATTERN (place
))
14353 && ! find_regno_fusage (place
, USE
, i
))
14354 || dead_or_set_regno_p (place
, i
))
14362 /* Put only REG_DEAD notes for pieces that are
14363 not already dead or set. */
14365 for (i
= regno
; i
< endregno
;
14366 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14368 rtx piece
= regno_reg_rtx
[i
];
14369 basic_block bb
= this_basic_block
;
14371 if (! dead_or_set_p (place
, piece
)
14372 && ! reg_bitfield_target_p (piece
,
14375 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14378 distribute_notes (new_note
, place
, place
,
14379 NULL
, NULL_RTX
, NULL_RTX
,
14382 else if (! refers_to_regno_p (i
, PATTERN (place
))
14383 && ! find_regno_fusage (place
, USE
, i
))
14384 for (tem_insn
= PREV_INSN (place
); ;
14385 tem_insn
= PREV_INSN (tem_insn
))
14387 if (!NONDEBUG_INSN_P (tem_insn
))
14389 if (tem_insn
== BB_HEAD (bb
))
14393 if (dead_or_set_p (tem_insn
, piece
)
14394 || reg_bitfield_target_p (piece
,
14395 PATTERN (tem_insn
)))
14397 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14410 /* Any other notes should not be present at this point in the
14412 gcc_unreachable ();
14417 XEXP (note
, 1) = REG_NOTES (place
);
14418 REG_NOTES (place
) = note
;
14422 add_shallow_copy_of_reg_note (place2
, note
);
14426 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14427 I3, I2, and I1 to new locations. This is also called to add a link
14428 pointing at I3 when I3's destination is changed. */
14431 distribute_links (struct insn_link
*links
)
14433 struct insn_link
*link
, *next_link
;
14435 for (link
= links
; link
; link
= next_link
)
14437 rtx_insn
*place
= 0;
14441 next_link
= link
->next
;
14443 /* If the insn that this link points to is a NOTE, ignore it. */
14444 if (NOTE_P (link
->insn
))
14448 rtx pat
= PATTERN (link
->insn
);
14449 if (GET_CODE (pat
) == SET
)
14451 else if (GET_CODE (pat
) == PARALLEL
)
14454 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14456 set
= XVECEXP (pat
, 0, i
);
14457 if (GET_CODE (set
) != SET
)
14460 reg
= SET_DEST (set
);
14461 while (GET_CODE (reg
) == ZERO_EXTRACT
14462 || GET_CODE (reg
) == STRICT_LOW_PART
14463 || GET_CODE (reg
) == SUBREG
)
14464 reg
= XEXP (reg
, 0);
14469 if (REGNO (reg
) == link
->regno
)
14472 if (i
== XVECLEN (pat
, 0))
14478 reg
= SET_DEST (set
);
14480 while (GET_CODE (reg
) == ZERO_EXTRACT
14481 || GET_CODE (reg
) == STRICT_LOW_PART
14482 || GET_CODE (reg
) == SUBREG
)
14483 reg
= XEXP (reg
, 0);
14485 /* A LOG_LINK is defined as being placed on the first insn that uses
14486 a register and points to the insn that sets the register. Start
14487 searching at the next insn after the target of the link and stop
14488 when we reach a set of the register or the end of the basic block.
14490 Note that this correctly handles the link that used to point from
14491 I3 to I2. Also note that not much searching is typically done here
14492 since most links don't point very far away. */
14494 for (insn
= NEXT_INSN (link
->insn
);
14495 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14496 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14497 insn
= NEXT_INSN (insn
))
14498 if (DEBUG_INSN_P (insn
))
14500 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14502 if (reg_referenced_p (reg
, PATTERN (insn
)))
14506 else if (CALL_P (insn
)
14507 && find_reg_fusage (insn
, USE
, reg
))
14512 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14515 /* If we found a place to put the link, place it there unless there
14516 is already a link to the same insn as LINK at that point. */
14520 struct insn_link
*link2
;
14522 FOR_EACH_LOG_LINK (link2
, place
)
14523 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14528 link
->next
= LOG_LINKS (place
);
14529 LOG_LINKS (place
) = link
;
14531 /* Set added_links_insn to the earliest insn we added a
14533 if (added_links_insn
== 0
14534 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14535 added_links_insn
= place
;
14541 /* Check for any register or memory mentioned in EQUIV that is not
14542 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14543 of EXPR where some registers may have been replaced by constants. */
14546 unmentioned_reg_p (rtx equiv
, rtx expr
)
14548 subrtx_iterator::array_type array
;
14549 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14551 const_rtx x
= *iter
;
14552 if ((REG_P (x
) || MEM_P (x
))
14553 && !reg_mentioned_p (x
, expr
))
14559 DEBUG_FUNCTION
void
14560 dump_combine_stats (FILE *file
)
14564 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14565 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14569 dump_combine_total_stats (FILE *file
)
14573 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14574 total_attempts
, total_merges
, total_extras
, total_successes
);
14577 /* Try combining insns through substitution. */
14578 static unsigned int
14579 rest_of_handle_combine (void)
14581 int rebuild_jump_labels_after_combine
;
14583 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14584 df_note_add_problem ();
14587 regstat_init_n_sets_and_refs ();
14588 reg_n_sets_max
= max_reg_num ();
14590 rebuild_jump_labels_after_combine
14591 = combine_instructions (get_insns (), max_reg_num ());
14593 /* Combining insns may have turned an indirect jump into a
14594 direct jump. Rebuild the JUMP_LABEL fields of jumping
14596 if (rebuild_jump_labels_after_combine
)
14598 if (dom_info_available_p (CDI_DOMINATORS
))
14599 free_dominance_info (CDI_DOMINATORS
);
14600 timevar_push (TV_JUMP
);
14601 rebuild_jump_labels (get_insns ());
14603 timevar_pop (TV_JUMP
);
14606 regstat_free_n_sets_and_refs ();
14612 const pass_data pass_data_combine
=
14614 RTL_PASS
, /* type */
14615 "combine", /* name */
14616 OPTGROUP_NONE
, /* optinfo_flags */
14617 TV_COMBINE
, /* tv_id */
14618 PROP_cfglayout
, /* properties_required */
14619 0, /* properties_provided */
14620 0, /* properties_destroyed */
14621 0, /* todo_flags_start */
14622 TODO_df_finish
, /* todo_flags_finish */
14625 class pass_combine
: public rtl_opt_pass
14628 pass_combine (gcc::context
*ctxt
)
14629 : rtl_opt_pass (pass_data_combine
, ctxt
)
14632 /* opt_pass methods: */
14633 virtual bool gate (function
*) { return (optimize
> 0); }
14634 virtual unsigned int execute (function
*)
14636 return rest_of_handle_combine ();
14639 }; // class pass_combine
14641 } // anon namespace
14644 make_pass_combine (gcc::context
*ctxt
)
14646 return new pass_combine (ctxt
);