1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
93 #include "rtlhooks-def.h"
95 /* Number of attempts to combine instructions in this function. */
97 static int combine_attempts
;
99 /* Number of attempts that got as far as substitution in this function. */
101 static int combine_merges
;
103 /* Number of instructions combined with added SETs in this function. */
105 static int combine_extras
;
107 /* Number of instructions combined in this function. */
109 static int combine_successes
;
111 /* Totals over entire compilation. */
113 static int total_attempts
, total_merges
, total_extras
, total_successes
;
116 /* Vector mapping INSN_UIDs to cuids.
117 The cuids are like uids but increase monotonically always.
118 Combine always uses cuids so that it can compare them.
119 But actually renumbering the uids, which we used to do,
120 proves to be a bad idea because it makes it hard to compare
121 the dumps produced by earlier passes with those from later passes. */
123 static int *uid_cuid
;
124 static int max_uid_cuid
;
126 /* Get the cuid of an insn. */
128 #define INSN_CUID(INSN) \
129 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
131 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
132 BITS_PER_WORD would invoke undefined behavior. Work around it. */
134 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
135 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
137 /* Maximum register number, which is the size of the tables below. */
139 static unsigned int combine_max_regno
;
142 /* Record last point of death of (hard or pseudo) register n. */
145 /* Record last point of modification of (hard or pseudo) register n. */
148 /* The next group of fields allows the recording of the last value assigned
149 to (hard or pseudo) register n. We use this information to see if an
150 operation being processed is redundant given a prior operation performed
151 on the register. For example, an `and' with a constant is redundant if
152 all the zero bits are already known to be turned off.
154 We use an approach similar to that used by cse, but change it in the
157 (1) We do not want to reinitialize at each label.
158 (2) It is useful, but not critical, to know the actual value assigned
159 to a register. Often just its form is helpful.
161 Therefore, we maintain the following fields:
163 last_set_value the last value assigned
164 last_set_label records the value of label_tick when the
165 register was assigned
166 last_set_table_tick records the value of label_tick when a
167 value using the register is assigned
168 last_set_invalid set to nonzero when it is not valid
169 to use the value of this register in some
172 To understand the usage of these tables, it is important to understand
173 the distinction between the value in last_set_value being valid and
174 the register being validly contained in some other expression in the
177 (The next two parameters are out of date).
179 reg_stat[i].last_set_value is valid if it is nonzero, and either
180 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
182 Register I may validly appear in any expression returned for the value
183 of another register if reg_n_sets[i] is 1. It may also appear in the
184 value for register J if reg_stat[j].last_set_invalid is zero, or
185 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
187 If an expression is found in the table containing a register which may
188 not validly appear in an expression, the register is replaced by
189 something that won't match, (clobber (const_int 0)). */
191 /* Record last value assigned to (hard or pseudo) register n. */
195 /* Record the value of label_tick when an expression involving register n
196 is placed in last_set_value. */
198 int last_set_table_tick
;
200 /* Record the value of label_tick when the value for register n is placed in
205 /* These fields are maintained in parallel with last_set_value and are
206 used to store the mode in which the register was last set, te bits
207 that were known to be zero when it was last set, and the number of
208 sign bits copies it was known to have when it was last set. */
210 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
211 char last_set_sign_bit_copies
;
212 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
214 /* Set nonzero if references to register n in expressions should not be
215 used. last_set_invalid is set nonzero when this register is being
216 assigned to and last_set_table_tick == label_tick. */
218 char last_set_invalid
;
220 /* Some registers that are set more than once and used in more than one
221 basic block are nevertheless always set in similar ways. For example,
222 a QImode register may be loaded from memory in two places on a machine
223 where byte loads zero extend.
225 We record in the following fields if a register has some leading bits
226 that are always equal to the sign bit, and what we know about the
227 nonzero bits of a register, specifically which bits are known to be
230 If an entry is zero, it means that we don't know anything special. */
232 unsigned char sign_bit_copies
;
234 unsigned HOST_WIDE_INT nonzero_bits
;
237 static struct reg_stat
*reg_stat
;
239 /* Record the cuid of the last insn that invalidated memory
240 (anything that writes memory, and subroutine calls, but not pushes). */
242 static int mem_last_set
;
244 /* Record the cuid of the last CALL_INSN
245 so we can tell whether a potential combination crosses any calls. */
247 static int last_call_cuid
;
249 /* When `subst' is called, this is the insn that is being modified
250 (by combining in a previous insn). The PATTERN of this insn
251 is still the old pattern partially modified and it should not be
252 looked at, but this may be used to examine the successors of the insn
253 to judge whether a simplification is valid. */
255 static rtx subst_insn
;
257 /* This is the lowest CUID that `subst' is currently dealing with.
258 get_last_value will not return a value if the register was set at or
259 after this CUID. If not for this mechanism, we could get confused if
260 I2 or I1 in try_combine were an insn that used the old value of a register
261 to obtain a new value. In that case, we might erroneously get the
262 new value of the register when we wanted the old one. */
264 static int subst_low_cuid
;
266 /* This contains any hard registers that are used in newpat; reg_dead_at_p
267 must consider all these registers to be always live. */
269 static HARD_REG_SET newpat_used_regs
;
271 /* This is an insn to which a LOG_LINKS entry has been added. If this
272 insn is the earlier than I2 or I3, combine should rescan starting at
275 static rtx added_links_insn
;
277 /* Basic block in which we are performing combines. */
278 static basic_block this_basic_block
;
280 /* A bitmap indicating which blocks had registers go dead at entry.
281 After combine, we'll need to re-do global life analysis with
282 those blocks as starting points. */
283 static sbitmap refresh_blocks
;
285 /* Incremented for each label. */
287 static int label_tick
;
289 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
290 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
292 static enum machine_mode nonzero_bits_mode
;
294 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
295 be safely used. It is zero while computing them and after combine has
296 completed. This former test prevents propagating values based on
297 previously set values, which can be incorrect if a variable is modified
300 static int nonzero_sign_valid
;
303 /* Record one modification to rtl structure
304 to be undone by storing old_contents into *where.
305 is_int is 1 if the contents are an int. */
311 union {rtx r
; int i
;} old_contents
;
312 union {rtx
*r
; int *i
;} where
;
315 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
316 num_undo says how many are currently recorded.
318 other_insn is nonzero if we have modified some other insn in the process
319 of working on subst_insn. It must be verified too. */
328 static struct undobuf undobuf
;
330 /* Number of times the pseudo being substituted for
331 was found and replaced. */
333 static int n_occurrences
;
335 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
337 unsigned HOST_WIDE_INT
,
338 unsigned HOST_WIDE_INT
*);
339 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
341 unsigned int, unsigned int *);
342 static void do_SUBST (rtx
*, rtx
);
343 static void do_SUBST_INT (int *, int);
344 static void init_reg_last (void);
345 static void setup_incoming_promotions (void);
346 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
347 static int cant_combine_insn_p (rtx
);
348 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
349 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
350 static int contains_muldiv (rtx
);
351 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
352 static void undo_all (void);
353 static void undo_commit (void);
354 static rtx
*find_split_point (rtx
*, rtx
);
355 static rtx
subst (rtx
, rtx
, rtx
, int, int);
356 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
357 static rtx
simplify_if_then_else (rtx
);
358 static rtx
simplify_set (rtx
);
359 static rtx
simplify_logical (rtx
);
360 static rtx
expand_compound_operation (rtx
);
361 static rtx
expand_field_assignment (rtx
);
362 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
363 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
364 static rtx
extract_left_shift (rtx
, int);
365 static rtx
make_compound_operation (rtx
, enum rtx_code
);
366 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
367 unsigned HOST_WIDE_INT
*);
368 static rtx
force_to_mode (rtx
, enum machine_mode
,
369 unsigned HOST_WIDE_INT
, rtx
, int);
370 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
371 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
372 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
373 static rtx
make_field_assignment (rtx
);
374 static rtx
apply_distributive_law (rtx
);
375 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
376 unsigned HOST_WIDE_INT
);
377 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
378 HOST_WIDE_INT
, enum machine_mode
, int *);
379 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
381 static int recog_for_combine (rtx
*, rtx
, rtx
*);
382 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
383 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
384 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
385 static void update_table_tick (rtx
);
386 static void record_value_for_reg (rtx
, rtx
, rtx
);
387 static void check_promoted_subreg (rtx
, rtx
);
388 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
389 static void record_dead_and_set_regs (rtx
);
390 static int get_last_value_validate (rtx
*, rtx
, int, int);
391 static rtx
get_last_value (rtx
);
392 static int use_crosses_set_p (rtx
, int);
393 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
394 static int reg_dead_at_p (rtx
, rtx
);
395 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
396 static int reg_bitfield_target_p (rtx
, rtx
);
397 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
398 static void distribute_links (rtx
);
399 static void mark_used_regs_combine (rtx
);
400 static int insn_cuid (rtx
);
401 static void record_promoted_value (rtx
, rtx
);
402 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
403 static enum rtx_code
combine_reversed_comparison_code (rtx
);
404 static int unmentioned_reg_p_1 (rtx
*, void *);
405 static bool unmentioned_reg_p (rtx
, rtx
);
408 /* It is not safe to use ordinary gen_lowpart in combine.
409 See comments in gen_lowpart_for_combine. */
410 #undef RTL_HOOKS_GEN_LOWPART
411 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
413 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
414 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
416 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
417 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
419 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
422 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
423 insn. The substitution can be undone by undo_all. If INTO is already
424 set to NEWVAL, do not record this change. Because computing NEWVAL might
425 also call SUBST, we have to compute it before we put anything into
429 do_SUBST (rtx
*into
, rtx newval
)
434 if (oldval
== newval
)
437 /* We'd like to catch as many invalid transformations here as
438 possible. Unfortunately, there are way too many mode changes
439 that are perfectly valid, so we'd waste too much effort for
440 little gain doing the checks here. Focus on catching invalid
441 transformations involving integer constants. */
442 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
443 && GET_CODE (newval
) == CONST_INT
)
445 /* Sanity check that we're replacing oldval with a CONST_INT
446 that is a valid sign-extension for the original mode. */
447 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
451 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
452 CONST_INT is not valid, because after the replacement, the
453 original mode would be gone. Unfortunately, we can't tell
454 when do_SUBST is called to replace the operand thereof, so we
455 perform this test on oldval instead, checking whether an
456 invalid replacement took place before we got here. */
457 if ((GET_CODE (oldval
) == SUBREG
458 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
459 || (GET_CODE (oldval
) == ZERO_EXTEND
460 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
465 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
467 buf
= xmalloc (sizeof (struct undo
));
471 buf
->old_contents
.r
= oldval
;
474 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
477 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
479 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
480 for the value of a HOST_WIDE_INT value (including CONST_INT) is
484 do_SUBST_INT (int *into
, int newval
)
489 if (oldval
== newval
)
493 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
495 buf
= xmalloc (sizeof (struct undo
));
499 buf
->old_contents
.i
= oldval
;
502 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
505 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
507 /* Main entry point for combiner. F is the first insn of the function.
508 NREGS is the first unused pseudo-reg number.
510 Return nonzero if the combiner has turned an indirect jump
511 instruction into a direct jump. */
513 combine_instructions (rtx f
, unsigned int nregs
)
520 rtx links
, nextlinks
;
522 int new_direct_jump_p
= 0;
524 combine_attempts
= 0;
527 combine_successes
= 0;
529 combine_max_regno
= nregs
;
531 rtl_hooks
= combine_rtl_hooks
;
533 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
535 init_recog_no_volatile ();
537 /* Compute maximum uid value so uid_cuid can be allocated. */
539 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
540 if (INSN_UID (insn
) > i
)
543 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
546 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
548 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
549 problems when, for example, we have j <<= 1 in a loop. */
551 nonzero_sign_valid
= 0;
553 /* Compute the mapping from uids to cuids.
554 Cuids are numbers assigned to insns, like uids,
555 except that cuids increase monotonically through the code.
557 Scan all SETs and see if we can deduce anything about what
558 bits are known to be zero for some registers and how many copies
559 of the sign bit are known to exist for those registers.
561 Also set any known values so that we can use it while searching
562 for what bits are known to be set. */
566 setup_incoming_promotions ();
568 refresh_blocks
= sbitmap_alloc (last_basic_block
);
569 sbitmap_zero (refresh_blocks
);
571 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
573 uid_cuid
[INSN_UID (insn
)] = ++i
;
579 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
581 record_dead_and_set_regs (insn
);
584 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
585 if (REG_NOTE_KIND (links
) == REG_INC
)
586 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
591 if (GET_CODE (insn
) == CODE_LABEL
)
595 nonzero_sign_valid
= 1;
597 /* Now scan all the insns in forward order. */
603 setup_incoming_promotions ();
605 FOR_EACH_BB (this_basic_block
)
607 for (insn
= BB_HEAD (this_basic_block
);
608 insn
!= NEXT_INSN (BB_END (this_basic_block
));
609 insn
= next
? next
: NEXT_INSN (insn
))
613 if (GET_CODE (insn
) == CODE_LABEL
)
616 else if (INSN_P (insn
))
618 /* See if we know about function return values before this
619 insn based upon SUBREG flags. */
620 check_promoted_subreg (insn
, PATTERN (insn
));
622 /* Try this insn with each insn it links back to. */
624 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
625 if ((next
= try_combine (insn
, XEXP (links
, 0),
626 NULL_RTX
, &new_direct_jump_p
)) != 0)
629 /* Try each sequence of three linked insns ending with this one. */
631 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
633 rtx link
= XEXP (links
, 0);
635 /* If the linked insn has been replaced by a note, then there
636 is no point in pursuing this chain any further. */
637 if (GET_CODE (link
) == NOTE
)
640 for (nextlinks
= LOG_LINKS (link
);
642 nextlinks
= XEXP (nextlinks
, 1))
643 if ((next
= try_combine (insn
, link
,
645 &new_direct_jump_p
)) != 0)
650 /* Try to combine a jump insn that uses CC0
651 with a preceding insn that sets CC0, and maybe with its
652 logical predecessor as well.
653 This is how we make decrement-and-branch insns.
654 We need this special code because data flow connections
655 via CC0 do not get entered in LOG_LINKS. */
657 if (GET_CODE (insn
) == JUMP_INSN
658 && (prev
= prev_nonnote_insn (insn
)) != 0
659 && GET_CODE (prev
) == INSN
660 && sets_cc0_p (PATTERN (prev
)))
662 if ((next
= try_combine (insn
, prev
,
663 NULL_RTX
, &new_direct_jump_p
)) != 0)
666 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
667 nextlinks
= XEXP (nextlinks
, 1))
668 if ((next
= try_combine (insn
, prev
,
670 &new_direct_jump_p
)) != 0)
674 /* Do the same for an insn that explicitly references CC0. */
675 if (GET_CODE (insn
) == INSN
676 && (prev
= prev_nonnote_insn (insn
)) != 0
677 && GET_CODE (prev
) == INSN
678 && sets_cc0_p (PATTERN (prev
))
679 && GET_CODE (PATTERN (insn
)) == SET
680 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
682 if ((next
= try_combine (insn
, prev
,
683 NULL_RTX
, &new_direct_jump_p
)) != 0)
686 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
687 nextlinks
= XEXP (nextlinks
, 1))
688 if ((next
= try_combine (insn
, prev
,
690 &new_direct_jump_p
)) != 0)
694 /* Finally, see if any of the insns that this insn links to
695 explicitly references CC0. If so, try this insn, that insn,
696 and its predecessor if it sets CC0. */
697 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
698 if (GET_CODE (XEXP (links
, 0)) == INSN
699 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
700 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
701 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
702 && GET_CODE (prev
) == INSN
703 && sets_cc0_p (PATTERN (prev
))
704 && (next
= try_combine (insn
, XEXP (links
, 0),
705 prev
, &new_direct_jump_p
)) != 0)
709 /* Try combining an insn with two different insns whose results it
711 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
712 for (nextlinks
= XEXP (links
, 1); nextlinks
;
713 nextlinks
= XEXP (nextlinks
, 1))
714 if ((next
= try_combine (insn
, XEXP (links
, 0),
716 &new_direct_jump_p
)) != 0)
719 /* Try this insn with each REG_EQUAL note it links back to. */
720 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
723 rtx temp
= XEXP (links
, 0);
724 if ((set
= single_set (temp
)) != 0
725 && (note
= find_reg_equal_equiv_note (temp
)) != 0
726 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
727 /* Avoid using a register that may already been marked
728 dead by an earlier instruction. */
729 && ! unmentioned_reg_p (XEXP (note
, 0), SET_SRC (set
)))
731 /* Temporarily replace the set's source with the
732 contents of the REG_EQUAL note. The insn will
733 be deleted or recognized by try_combine. */
734 rtx orig
= SET_SRC (set
);
735 SET_SRC (set
) = XEXP (note
, 0);
736 next
= try_combine (insn
, temp
, NULL_RTX
,
740 SET_SRC (set
) = orig
;
744 if (GET_CODE (insn
) != NOTE
)
745 record_dead_and_set_regs (insn
);
754 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
755 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
756 new_direct_jump_p
|= purge_all_dead_edges (0);
757 delete_noop_moves ();
759 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
760 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
761 | PROP_KILL_DEAD_CODE
);
764 sbitmap_free (refresh_blocks
);
769 struct undo
*undo
, *next
;
770 for (undo
= undobuf
.frees
; undo
; undo
= next
)
778 total_attempts
+= combine_attempts
;
779 total_merges
+= combine_merges
;
780 total_extras
+= combine_extras
;
781 total_successes
+= combine_successes
;
783 nonzero_sign_valid
= 0;
784 rtl_hooks
= general_rtl_hooks
;
786 /* Make recognizer allow volatile MEMs again. */
789 return new_direct_jump_p
;
792 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
798 for (i
= 0; i
< combine_max_regno
; i
++)
799 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
802 /* Set up any promoted values for incoming argument registers. */
805 setup_incoming_promotions (void)
809 enum machine_mode mode
;
811 rtx first
= get_insns ();
813 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
815 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
816 /* Check whether this register can hold an incoming pointer
817 argument. FUNCTION_ARG_REGNO_P tests outgoing register
818 numbers, so translate if necessary due to register windows. */
819 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
820 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
823 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
826 gen_rtx_CLOBBER (mode
, const0_rtx
)));
831 /* Called via note_stores. If X is a pseudo that is narrower than
832 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
834 If we are setting only a portion of X and we can't figure out what
835 portion, assume all bits will be used since we don't know what will
838 Similarly, set how many bits of X are known to be copies of the sign bit
839 at all locations in the function. This is the smallest number implied
843 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
844 void *data ATTRIBUTE_UNUSED
)
848 if (GET_CODE (x
) == REG
849 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
850 /* If this register is undefined at the start of the file, we can't
851 say what its contents were. */
852 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
853 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
855 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
857 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
858 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
862 /* If this is a complex assignment, see if we can convert it into a
863 simple assignment. */
864 set
= expand_field_assignment (set
);
866 /* If this is a simple assignment, or we have a paradoxical SUBREG,
867 set what we know about X. */
869 if (SET_DEST (set
) == x
870 || (GET_CODE (SET_DEST (set
)) == SUBREG
871 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
872 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
873 && SUBREG_REG (SET_DEST (set
)) == x
))
875 rtx src
= SET_SRC (set
);
877 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
878 /* If X is narrower than a word and SRC is a non-negative
879 constant that would appear negative in the mode of X,
880 sign-extend it for use in reg_stat[].nonzero_bits because some
881 machines (maybe most) will actually do the sign-extension
882 and this is the conservative approach.
884 ??? For 2.5, try to tighten up the MD files in this regard
885 instead of this kludge. */
887 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
888 && GET_CODE (src
) == CONST_INT
890 && 0 != (INTVAL (src
)
892 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
893 src
= GEN_INT (INTVAL (src
)
894 | ((HOST_WIDE_INT
) (-1)
895 << GET_MODE_BITSIZE (GET_MODE (x
))));
898 /* Don't call nonzero_bits if it cannot change anything. */
899 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
900 reg_stat
[REGNO (x
)].nonzero_bits
901 |= nonzero_bits (src
, nonzero_bits_mode
);
902 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
903 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
904 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
905 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
909 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
910 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
915 /* See if INSN can be combined into I3. PRED and SUCC are optionally
916 insns that were previously combined into I3 or that will be combined
917 into the merger of INSN and I3.
919 Return 0 if the combination is not allowed for any reason.
921 If the combination is allowed, *PDEST will be set to the single
922 destination of INSN and *PSRC to the single source, and this function
926 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
927 rtx
*pdest
, rtx
*psrc
)
930 rtx set
= 0, src
, dest
;
935 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
936 && next_active_insn (succ
) == i3
)
937 : next_active_insn (insn
) == i3
);
939 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
940 or a PARALLEL consisting of such a SET and CLOBBERs.
942 If INSN has CLOBBER parallel parts, ignore them for our processing.
943 By definition, these happen during the execution of the insn. When it
944 is merged with another insn, all bets are off. If they are, in fact,
945 needed and aren't also supplied in I3, they may be added by
946 recog_for_combine. Otherwise, it won't match.
948 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
951 Get the source and destination of INSN. If more than one, can't
954 if (GET_CODE (PATTERN (insn
)) == SET
)
955 set
= PATTERN (insn
);
956 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
957 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
959 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
961 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
964 switch (GET_CODE (elt
))
966 /* This is important to combine floating point insns
969 /* Combining an isolated USE doesn't make sense.
970 We depend here on combinable_i3pat to reject them. */
971 /* The code below this loop only verifies that the inputs of
972 the SET in INSN do not change. We call reg_set_between_p
973 to verify that the REG in the USE does not change between
975 If the USE in INSN was for a pseudo register, the matching
976 insn pattern will likely match any register; combining this
977 with any other USE would only be safe if we knew that the
978 used registers have identical values, or if there was
979 something to tell them apart, e.g. different modes. For
980 now, we forgo such complicated tests and simply disallow
981 combining of USES of pseudo registers with any other USE. */
982 if (GET_CODE (XEXP (elt
, 0)) == REG
983 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
985 rtx i3pat
= PATTERN (i3
);
986 int i
= XVECLEN (i3pat
, 0) - 1;
987 unsigned int regno
= REGNO (XEXP (elt
, 0));
991 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
993 if (GET_CODE (i3elt
) == USE
994 && GET_CODE (XEXP (i3elt
, 0)) == REG
995 && (REGNO (XEXP (i3elt
, 0)) == regno
996 ? reg_set_between_p (XEXP (elt
, 0),
997 PREV_INSN (insn
), i3
)
998 : regno
>= FIRST_PSEUDO_REGISTER
))
1005 /* We can ignore CLOBBERs. */
1010 /* Ignore SETs whose result isn't used but not those that
1011 have side-effects. */
1012 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1013 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1014 || INTVAL (XEXP (note
, 0)) <= 0)
1015 && ! side_effects_p (elt
))
1018 /* If we have already found a SET, this is a second one and
1019 so we cannot combine with this insn. */
1027 /* Anything else means we can't combine. */
1033 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1034 so don't do anything with it. */
1035 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1044 set
= expand_field_assignment (set
);
1045 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1047 /* Don't eliminate a store in the stack pointer. */
1048 if (dest
== stack_pointer_rtx
1049 /* Don't combine with an insn that sets a register to itself if it has
1050 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1051 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1052 /* Can't merge an ASM_OPERANDS. */
1053 || GET_CODE (src
) == ASM_OPERANDS
1054 /* Can't merge a function call. */
1055 || GET_CODE (src
) == CALL
1056 /* Don't eliminate a function call argument. */
1057 || (GET_CODE (i3
) == CALL_INSN
1058 && (find_reg_fusage (i3
, USE
, dest
)
1059 || (GET_CODE (dest
) == REG
1060 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1061 && global_regs
[REGNO (dest
)])))
1062 /* Don't substitute into an incremented register. */
1063 || FIND_REG_INC_NOTE (i3
, dest
)
1064 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1066 /* Don't combine the end of a libcall into anything. */
1067 /* ??? This gives worse code, and appears to be unnecessary, since no
1068 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1069 use REG_RETVAL notes for noconflict blocks, but other code here
1070 makes sure that those insns don't disappear. */
1071 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1073 /* Make sure that DEST is not used after SUCC but before I3. */
1074 || (succ
&& ! all_adjacent
1075 && reg_used_between_p (dest
, succ
, i3
))
1076 /* Make sure that the value that is to be substituted for the register
1077 does not use any registers whose values alter in between. However,
1078 If the insns are adjacent, a use can't cross a set even though we
1079 think it might (this can happen for a sequence of insns each setting
1080 the same destination; last_set of that register might point to
1081 a NOTE). If INSN has a REG_EQUIV note, the register is always
1082 equivalent to the memory so the substitution is valid even if there
1083 are intervening stores. Also, don't move a volatile asm or
1084 UNSPEC_VOLATILE across any other insns. */
1086 && (((GET_CODE (src
) != MEM
1087 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1088 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1089 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1090 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1091 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1092 better register allocation by not doing the combine. */
1093 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1094 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1095 /* Don't combine across a CALL_INSN, because that would possibly
1096 change whether the life span of some REGs crosses calls or not,
1097 and it is a pain to update that information.
1098 Exception: if source is a constant, moving it later can't hurt.
1099 Accept that special case, because it helps -fforce-addr a lot. */
1100 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1103 /* DEST must either be a REG or CC0. */
1104 if (GET_CODE (dest
) == REG
)
1106 /* If register alignment is being enforced for multi-word items in all
1107 cases except for parameters, it is possible to have a register copy
1108 insn referencing a hard register that is not allowed to contain the
1109 mode being copied and which would not be valid as an operand of most
1110 insns. Eliminate this problem by not combining with such an insn.
1112 Also, on some machines we don't want to extend the life of a hard
1115 if (GET_CODE (src
) == REG
1116 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1117 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1118 /* Don't extend the life of a hard register unless it is
1119 user variable (if we have few registers) or it can't
1120 fit into the desired register (meaning something special
1122 Also avoid substituting a return register into I3, because
1123 reload can't handle a conflict with constraints of other
1125 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1126 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1129 else if (GET_CODE (dest
) != CC0
)
1132 /* Don't substitute for a register intended as a clobberable operand.
1133 Similarly, don't substitute an expression containing a register that
1134 will be clobbered in I3. */
1135 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1136 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1137 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1138 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1140 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1143 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1144 or not), reject, unless nothing volatile comes between it and I3 */
1146 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1148 /* Make sure succ doesn't contain a volatile reference. */
1149 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1152 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1153 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1157 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1158 to be an explicit register variable, and was chosen for a reason. */
1160 if (GET_CODE (src
) == ASM_OPERANDS
1161 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1164 /* If there are any volatile insns between INSN and I3, reject, because
1165 they might affect machine state. */
1167 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1168 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1171 /* If INSN or I2 contains an autoincrement or autodecrement,
1172 make sure that register is not used between there and I3,
1173 and not already used in I3 either.
1174 Also insist that I3 not be a jump; if it were one
1175 and the incremented register were spilled, we would lose. */
1178 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1179 if (REG_NOTE_KIND (link
) == REG_INC
1180 && (GET_CODE (i3
) == JUMP_INSN
1181 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1182 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1187 /* Don't combine an insn that follows a CC0-setting insn.
1188 An insn that uses CC0 must not be separated from the one that sets it.
1189 We do, however, allow I2 to follow a CC0-setting insn if that insn
1190 is passed as I1; in that case it will be deleted also.
1191 We also allow combining in this case if all the insns are adjacent
1192 because that would leave the two CC0 insns adjacent as well.
1193 It would be more logical to test whether CC0 occurs inside I1 or I2,
1194 but that would be much slower, and this ought to be equivalent. */
1196 p
= prev_nonnote_insn (insn
);
1197 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1202 /* If we get here, we have passed all the tests and the combination is
1211 /* LOC is the location within I3 that contains its pattern or the component
1212 of a PARALLEL of the pattern. We validate that it is valid for combining.
1214 One problem is if I3 modifies its output, as opposed to replacing it
1215 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1216 so would produce an insn that is not equivalent to the original insns.
1220 (set (reg:DI 101) (reg:DI 100))
1221 (set (subreg:SI (reg:DI 101) 0) <foo>)
1223 This is NOT equivalent to:
1225 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1226 (set (reg:DI 101) (reg:DI 100))])
1228 Not only does this modify 100 (in which case it might still be valid
1229 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1231 We can also run into a problem if I2 sets a register that I1
1232 uses and I1 gets directly substituted into I3 (not via I2). In that
1233 case, we would be getting the wrong value of I2DEST into I3, so we
1234 must reject the combination. This case occurs when I2 and I1 both
1235 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1236 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1237 of a SET must prevent combination from occurring.
1239 Before doing the above check, we first try to expand a field assignment
1240 into a set of logical operations.
1242 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1243 we place a register that is both set and used within I3. If more than one
1244 such register is detected, we fail.
1246 Return 1 if the combination is valid, zero otherwise. */
1249 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1250 int i1_not_in_src
, rtx
*pi3dest_killed
)
1254 if (GET_CODE (x
) == SET
)
1257 rtx dest
= SET_DEST (set
);
1258 rtx src
= SET_SRC (set
);
1259 rtx inner_dest
= dest
;
1261 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1262 || GET_CODE (inner_dest
) == SUBREG
1263 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1264 inner_dest
= XEXP (inner_dest
, 0);
1266 /* Check for the case where I3 modifies its output, as discussed
1267 above. We don't want to prevent pseudos from being combined
1268 into the address of a MEM, so only prevent the combination if
1269 i1 or i2 set the same MEM. */
1270 if ((inner_dest
!= dest
&&
1271 (GET_CODE (inner_dest
) != MEM
1272 || rtx_equal_p (i2dest
, inner_dest
)
1273 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1274 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1275 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1277 /* This is the same test done in can_combine_p except we can't test
1278 all_adjacent; we don't have to, since this instruction will stay
1279 in place, thus we are not considering increasing the lifetime of
1282 Also, if this insn sets a function argument, combining it with
1283 something that might need a spill could clobber a previous
1284 function argument; the all_adjacent test in can_combine_p also
1285 checks this; here, we do a more specific test for this case. */
1287 || (GET_CODE (inner_dest
) == REG
1288 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1289 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1290 GET_MODE (inner_dest
))))
1291 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1294 /* If DEST is used in I3, it is being killed in this insn,
1295 so record that for later.
1296 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1297 STACK_POINTER_REGNUM, since these are always considered to be
1298 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1299 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1300 && reg_referenced_p (dest
, PATTERN (i3
))
1301 && REGNO (dest
) != FRAME_POINTER_REGNUM
1302 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1303 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1305 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1306 && (REGNO (dest
) != ARG_POINTER_REGNUM
1307 || ! fixed_regs
[REGNO (dest
)])
1309 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1311 if (*pi3dest_killed
)
1314 *pi3dest_killed
= dest
;
1318 else if (GET_CODE (x
) == PARALLEL
)
1322 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1323 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1324 i1_not_in_src
, pi3dest_killed
))
1331 /* Return 1 if X is an arithmetic expression that contains a multiplication
1332 and division. We don't count multiplications by powers of two here. */
1335 contains_muldiv (rtx x
)
1337 switch (GET_CODE (x
))
1339 case MOD
: case DIV
: case UMOD
: case UDIV
:
1343 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1344 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1347 return contains_muldiv (XEXP (x
, 0))
1348 || contains_muldiv (XEXP (x
, 1));
1351 return contains_muldiv (XEXP (x
, 0));
1357 /* Determine whether INSN can be used in a combination. Return nonzero if
1358 not. This is used in try_combine to detect early some cases where we
1359 can't perform combinations. */
1362 cant_combine_insn_p (rtx insn
)
1367 /* If this isn't really an insn, we can't do anything.
1368 This can occur when flow deletes an insn that it has merged into an
1369 auto-increment address. */
1370 if (! INSN_P (insn
))
1373 /* Never combine loads and stores involving hard regs that are likely
1374 to be spilled. The register allocator can usually handle such
1375 reg-reg moves by tying. If we allow the combiner to make
1376 substitutions of likely-spilled regs, we may abort in reload.
1377 As an exception, we allow combinations involving fixed regs; these are
1378 not available to the register allocator so there's no risk involved. */
1380 set
= single_set (insn
);
1383 src
= SET_SRC (set
);
1384 dest
= SET_DEST (set
);
1385 if (GET_CODE (src
) == SUBREG
)
1386 src
= SUBREG_REG (src
);
1387 if (GET_CODE (dest
) == SUBREG
)
1388 dest
= SUBREG_REG (dest
);
1389 if (REG_P (src
) && REG_P (dest
)
1390 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1391 && ! fixed_regs
[REGNO (src
)]
1392 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1393 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1394 && ! fixed_regs
[REGNO (dest
)]
1395 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1401 /* Adjust INSN after we made a change to its destination.
1403 Changing the destination can invalidate notes that say something about
1404 the results of the insn and a LOG_LINK pointing to the insn. */
1407 adjust_for_new_dest (rtx insn
)
1411 /* For notes, be conservative and simply remove them. */
1412 loc
= ®_NOTES (insn
);
1415 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1416 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1417 *loc
= XEXP (*loc
, 1);
1419 loc
= &XEXP (*loc
, 1);
1422 /* The new insn will have a destination that was previously the destination
1423 of an insn just above it. Call distribute_links to make a LOG_LINK from
1424 the next use of that destination. */
1425 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1428 /* Try to combine the insns I1 and I2 into I3.
1429 Here I1 and I2 appear earlier than I3.
1430 I1 can be zero; then we combine just I2 into I3.
1432 If we are combining three insns and the resulting insn is not recognized,
1433 try splitting it into two insns. If that happens, I2 and I3 are retained
1434 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1437 Return 0 if the combination does not work. Then nothing is changed.
1438 If we did the combination, return the insn at which combine should
1441 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1442 new direct jump instruction. */
1445 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1447 /* New patterns for I3 and I2, respectively. */
1448 rtx newpat
, newi2pat
= 0;
1449 int substed_i2
= 0, substed_i1
= 0;
1450 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1451 int added_sets_1
, added_sets_2
;
1452 /* Total number of SETs to put into I3. */
1454 /* Nonzero if I2's body now appears in I3. */
1456 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1457 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1458 /* Contains I3 if the destination of I3 is used in its source, which means
1459 that the old life of I3 is being killed. If that usage is placed into
1460 I2 and not in I3, a REG_DEAD note must be made. */
1461 rtx i3dest_killed
= 0;
1462 /* SET_DEST and SET_SRC of I2 and I1. */
1463 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1464 /* PATTERN (I2), or a copy of it in certain cases. */
1466 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1467 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1468 int i1_feeds_i3
= 0;
1469 /* Notes that must be added to REG_NOTES in I3 and I2. */
1470 rtx new_i3_notes
, new_i2_notes
;
1471 /* Notes that we substituted I3 into I2 instead of the normal case. */
1472 int i3_subst_into_i2
= 0;
1473 /* Notes that I1, I2 or I3 is a MULT operation. */
1481 /* Exit early if one of the insns involved can't be used for
1483 if (cant_combine_insn_p (i3
)
1484 || cant_combine_insn_p (i2
)
1485 || (i1
&& cant_combine_insn_p (i1
))
1486 /* We also can't do anything if I3 has a
1487 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1490 /* ??? This gives worse code, and appears to be unnecessary, since no
1491 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1492 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1498 undobuf
.other_insn
= 0;
1500 /* Reset the hard register usage information. */
1501 CLEAR_HARD_REG_SET (newpat_used_regs
);
1503 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1504 code below, set I1 to be the earlier of the two insns. */
1505 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1506 temp
= i1
, i1
= i2
, i2
= temp
;
1508 added_links_insn
= 0;
1510 /* First check for one important special-case that the code below will
1511 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1512 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1513 we may be able to replace that destination with the destination of I3.
1514 This occurs in the common code where we compute both a quotient and
1515 remainder into a structure, in which case we want to do the computation
1516 directly into the structure to avoid register-register copies.
1518 Note that this case handles both multiple sets in I2 and also
1519 cases where I2 has a number of CLOBBER or PARALLELs.
1521 We make very conservative checks below and only try to handle the
1522 most common cases of this. For example, we only handle the case
1523 where I2 and I3 are adjacent to avoid making difficult register
1526 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1527 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1528 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1529 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1530 && GET_CODE (PATTERN (i2
)) == PARALLEL
1531 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1532 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1533 below would need to check what is inside (and reg_overlap_mentioned_p
1534 doesn't support those codes anyway). Don't allow those destinations;
1535 the resulting insn isn't likely to be recognized anyway. */
1536 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1537 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1538 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1539 SET_DEST (PATTERN (i3
)))
1540 && next_real_insn (i2
) == i3
)
1542 rtx p2
= PATTERN (i2
);
1544 /* Make sure that the destination of I3,
1545 which we are going to substitute into one output of I2,
1546 is not used within another output of I2. We must avoid making this:
1547 (parallel [(set (mem (reg 69)) ...)
1548 (set (reg 69) ...)])
1549 which is not well-defined as to order of actions.
1550 (Besides, reload can't handle output reloads for this.)
1552 The problem can also happen if the dest of I3 is a memory ref,
1553 if another dest in I2 is an indirect memory ref. */
1554 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1555 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1556 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1557 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1558 SET_DEST (XVECEXP (p2
, 0, i
))))
1561 if (i
== XVECLEN (p2
, 0))
1562 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1563 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1564 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1565 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1570 subst_low_cuid
= INSN_CUID (i2
);
1572 added_sets_2
= added_sets_1
= 0;
1573 i2dest
= SET_SRC (PATTERN (i3
));
1575 /* Replace the dest in I2 with our dest and make the resulting
1576 insn the new pattern for I3. Then skip to where we
1577 validate the pattern. Everything was set up above. */
1578 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1579 SET_DEST (PATTERN (i3
)));
1582 i3_subst_into_i2
= 1;
1583 goto validate_replacement
;
1587 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1588 one of those words to another constant, merge them by making a new
1591 && (temp
= single_set (i2
)) != 0
1592 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1593 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1594 && GET_CODE (SET_DEST (temp
)) == REG
1595 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1596 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1597 && GET_CODE (PATTERN (i3
)) == SET
1598 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1599 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1600 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1601 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1602 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1604 HOST_WIDE_INT lo
, hi
;
1606 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1607 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1610 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1611 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1614 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1616 /* We don't handle the case of the target word being wider
1617 than a host wide int. */
1618 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1621 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1622 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1623 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1625 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1626 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1627 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1629 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1630 >> (HOST_BITS_PER_WIDE_INT
- 1));
1632 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1633 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1634 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1635 (INTVAL (SET_SRC (PATTERN (i3
)))));
1637 hi
= lo
< 0 ? -1 : 0;
1640 /* We don't handle the case of the higher word not fitting
1641 entirely in either hi or lo. */
1646 subst_low_cuid
= INSN_CUID (i2
);
1647 added_sets_2
= added_sets_1
= 0;
1648 i2dest
= SET_DEST (temp
);
1650 SUBST (SET_SRC (temp
),
1651 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1653 newpat
= PATTERN (i2
);
1654 goto validate_replacement
;
1658 /* If we have no I1 and I2 looks like:
1659 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1661 make up a dummy I1 that is
1664 (set (reg:CC X) (compare:CC Y (const_int 0)))
1666 (We can ignore any trailing CLOBBERs.)
1668 This undoes a previous combination and allows us to match a branch-and-
1671 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1672 && XVECLEN (PATTERN (i2
), 0) >= 2
1673 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1674 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1676 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1677 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1678 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1679 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1680 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1681 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1683 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1684 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1689 /* We make I1 with the same INSN_UID as I2. This gives it
1690 the same INSN_CUID for value tracking. Our fake I1 will
1691 never appear in the insn stream so giving it the same INSN_UID
1692 as I2 will not cause a problem. */
1694 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1695 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1696 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1699 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1700 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1701 SET_DEST (PATTERN (i1
)));
1706 /* Verify that I2 and I1 are valid for combining. */
1707 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1708 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1714 /* Record whether I2DEST is used in I2SRC and similarly for the other
1715 cases. Knowing this will help in register status updating below. */
1716 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1717 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1718 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1720 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1722 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1724 /* Ensure that I3's pattern can be the destination of combines. */
1725 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1726 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1733 /* See if any of the insns is a MULT operation. Unless one is, we will
1734 reject a combination that is, since it must be slower. Be conservative
1736 if (GET_CODE (i2src
) == MULT
1737 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1738 || (GET_CODE (PATTERN (i3
)) == SET
1739 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1742 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1743 We used to do this EXCEPT in one case: I3 has a post-inc in an
1744 output operand. However, that exception can give rise to insns like
1746 which is a famous insn on the PDP-11 where the value of r3 used as the
1747 source was model-dependent. Avoid this sort of thing. */
1750 if (!(GET_CODE (PATTERN (i3
)) == SET
1751 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1752 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1753 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1754 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1755 /* It's not the exception. */
1758 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1759 if (REG_NOTE_KIND (link
) == REG_INC
1760 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1762 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1769 /* See if the SETs in I1 or I2 need to be kept around in the merged
1770 instruction: whenever the value set there is still needed past I3.
1771 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1773 For the SET in I1, we have two cases: If I1 and I2 independently
1774 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1775 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1776 in I1 needs to be kept around unless I1DEST dies or is set in either
1777 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1778 I1DEST. If so, we know I1 feeds into I2. */
1780 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1783 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1784 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1786 /* If the set in I2 needs to be kept around, we must make a copy of
1787 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1788 PATTERN (I2), we are only substituting for the original I1DEST, not into
1789 an already-substituted copy. This also prevents making self-referential
1790 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1793 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1794 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1798 i2pat
= copy_rtx (i2pat
);
1802 /* Substitute in the latest insn for the regs set by the earlier ones. */
1804 maxreg
= max_reg_num ();
1808 /* It is possible that the source of I2 or I1 may be performing an
1809 unneeded operation, such as a ZERO_EXTEND of something that is known
1810 to have the high part zero. Handle that case by letting subst look at
1811 the innermost one of them.
1813 Another way to do this would be to have a function that tries to
1814 simplify a single insn instead of merging two or more insns. We don't
1815 do this because of the potential of infinite loops and because
1816 of the potential extra memory required. However, doing it the way
1817 we are is a bit of a kludge and doesn't catch all cases.
1819 But only do this if -fexpensive-optimizations since it slows things down
1820 and doesn't usually win. */
1822 if (flag_expensive_optimizations
)
1824 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1827 subst_low_cuid
= INSN_CUID (i1
);
1828 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1832 subst_low_cuid
= INSN_CUID (i2
);
1833 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1838 /* Many machines that don't use CC0 have insns that can both perform an
1839 arithmetic operation and set the condition code. These operations will
1840 be represented as a PARALLEL with the first element of the vector
1841 being a COMPARE of an arithmetic operation with the constant zero.
1842 The second element of the vector will set some pseudo to the result
1843 of the same arithmetic operation. If we simplify the COMPARE, we won't
1844 match such a pattern and so will generate an extra insn. Here we test
1845 for this case, where both the comparison and the operation result are
1846 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1847 I2SRC. Later we will make the PARALLEL that contains I2. */
1849 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1850 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1851 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1852 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1854 #ifdef SELECT_CC_MODE
1856 enum machine_mode compare_mode
;
1859 newpat
= PATTERN (i3
);
1860 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1864 #ifdef SELECT_CC_MODE
1865 /* See if a COMPARE with the operand we substituted in should be done
1866 with the mode that is currently being used. If not, do the same
1867 processing we do in `subst' for a SET; namely, if the destination
1868 is used only once, try to replace it with a register of the proper
1869 mode and also replace the COMPARE. */
1870 if (undobuf
.other_insn
== 0
1871 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1872 &undobuf
.other_insn
))
1873 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1875 != GET_MODE (SET_DEST (newpat
))))
1877 unsigned int regno
= REGNO (SET_DEST (newpat
));
1878 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1880 if (regno
< FIRST_PSEUDO_REGISTER
1881 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1882 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1884 if (regno
>= FIRST_PSEUDO_REGISTER
)
1885 SUBST (regno_reg_rtx
[regno
], new_dest
);
1887 SUBST (SET_DEST (newpat
), new_dest
);
1888 SUBST (XEXP (*cc_use
, 0), new_dest
);
1889 SUBST (SET_SRC (newpat
),
1890 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1893 undobuf
.other_insn
= 0;
1900 n_occurrences
= 0; /* `subst' counts here */
1902 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1903 need to make a unique copy of I2SRC each time we substitute it
1904 to avoid self-referential rtl. */
1906 subst_low_cuid
= INSN_CUID (i2
);
1907 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1908 ! i1_feeds_i3
&& i1dest_in_i1src
);
1911 /* Record whether i2's body now appears within i3's body. */
1912 i2_is_used
= n_occurrences
;
1915 /* If we already got a failure, don't try to do more. Otherwise,
1916 try to substitute in I1 if we have it. */
1918 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1920 /* Before we can do this substitution, we must redo the test done
1921 above (see detailed comments there) that ensures that I1DEST
1922 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1924 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1932 subst_low_cuid
= INSN_CUID (i1
);
1933 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1937 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1938 to count all the ways that I2SRC and I1SRC can be used. */
1939 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1940 && i2_is_used
+ added_sets_2
> 1)
1941 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1942 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1944 /* Fail if we tried to make a new register (we used to abort, but there's
1945 really no reason to). */
1946 || max_reg_num () != maxreg
1947 /* Fail if we couldn't do something and have a CLOBBER. */
1948 || GET_CODE (newpat
) == CLOBBER
1949 /* Fail if this new pattern is a MULT and we didn't have one before
1950 at the outer level. */
1951 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1958 /* If the actions of the earlier insns must be kept
1959 in addition to substituting them into the latest one,
1960 we must make a new PARALLEL for the latest insn
1961 to hold additional the SETs. */
1963 if (added_sets_1
|| added_sets_2
)
1967 if (GET_CODE (newpat
) == PARALLEL
)
1969 rtvec old
= XVEC (newpat
, 0);
1970 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1971 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1972 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1973 sizeof (old
->elem
[0]) * old
->num_elem
);
1978 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1979 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1980 XVECEXP (newpat
, 0, 0) = old
;
1984 XVECEXP (newpat
, 0, --total_sets
)
1985 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1986 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1990 /* If there is no I1, use I2's body as is. We used to also not do
1991 the subst call below if I2 was substituted into I3,
1992 but that could lose a simplification. */
1994 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1996 /* See comment where i2pat is assigned. */
1997 XVECEXP (newpat
, 0, --total_sets
)
1998 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2002 /* We come here when we are replacing a destination in I2 with the
2003 destination of I3. */
2004 validate_replacement
:
2006 /* Note which hard regs this insn has as inputs. */
2007 mark_used_regs_combine (newpat
);
2009 /* Is the result of combination a valid instruction? */
2010 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2012 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2013 the second SET's destination is a register that is unused and isn't
2014 marked as an instruction that might trap in an EH region. In that case,
2015 we just need the first SET. This can occur when simplifying a divmod
2016 insn. We *must* test for this case here because the code below that
2017 splits two independent SETs doesn't handle this case correctly when it
2018 updates the register status.
2020 It's pointless doing this if we originally had two sets, one from
2021 i3, and one from i2. Combining then splitting the parallel results
2022 in the original i2 again plus an invalid insn (which we delete).
2023 The net effect is only to move instructions around, which makes
2024 debug info less accurate.
2026 Also check the case where the first SET's destination is unused.
2027 That would not cause incorrect code, but does cause an unneeded
2030 if (insn_code_number
< 0
2031 && !(added_sets_2
&& i1
== 0)
2032 && GET_CODE (newpat
) == PARALLEL
2033 && XVECLEN (newpat
, 0) == 2
2034 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2035 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2036 && asm_noperands (newpat
) < 0)
2038 rtx set0
= XVECEXP (newpat
, 0, 0);
2039 rtx set1
= XVECEXP (newpat
, 0, 1);
2042 if (((GET_CODE (SET_DEST (set1
)) == REG
2043 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2044 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2045 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2046 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2047 || INTVAL (XEXP (note
, 0)) <= 0)
2048 && ! side_effects_p (SET_SRC (set1
)))
2051 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2054 else if (((GET_CODE (SET_DEST (set0
)) == REG
2055 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2056 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2057 && find_reg_note (i3
, REG_UNUSED
,
2058 SUBREG_REG (SET_DEST (set0
)))))
2059 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2060 || INTVAL (XEXP (note
, 0)) <= 0)
2061 && ! side_effects_p (SET_SRC (set0
)))
2064 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2066 if (insn_code_number
>= 0)
2068 /* If we will be able to accept this, we have made a
2069 change to the destination of I3. This requires us to
2070 do a few adjustments. */
2072 PATTERN (i3
) = newpat
;
2073 adjust_for_new_dest (i3
);
2078 /* If we were combining three insns and the result is a simple SET
2079 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2080 insns. There are two ways to do this. It can be split using a
2081 machine-specific method (like when you have an addition of a large
2082 constant) or by combine in the function find_split_point. */
2084 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2085 && asm_noperands (newpat
) < 0)
2087 rtx m_split
, *split
;
2088 rtx ni2dest
= i2dest
;
2090 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2091 use I2DEST as a scratch register will help. In the latter case,
2092 convert I2DEST to the mode of the source of NEWPAT if we can. */
2094 m_split
= split_insns (newpat
, i3
);
2096 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2097 inputs of NEWPAT. */
2099 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2100 possible to try that as a scratch reg. This would require adding
2101 more code to make it work though. */
2103 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2105 /* If I2DEST is a hard register or the only use of a pseudo,
2106 we can change its mode. */
2107 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2108 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2109 && GET_CODE (i2dest
) == REG
2110 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2111 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2112 && ! REG_USERVAR_P (i2dest
))))
2113 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2116 m_split
= split_insns (gen_rtx_PARALLEL
2118 gen_rtvec (2, newpat
,
2119 gen_rtx_CLOBBER (VOIDmode
,
2122 /* If the split with the mode-changed register didn't work, try
2123 the original register. */
2124 if (! m_split
&& ni2dest
!= i2dest
)
2127 m_split
= split_insns (gen_rtx_PARALLEL
2129 gen_rtvec (2, newpat
,
2130 gen_rtx_CLOBBER (VOIDmode
,
2136 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2138 m_split
= PATTERN (m_split
);
2139 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2140 if (insn_code_number
>= 0)
2143 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2144 && (next_real_insn (i2
) == i3
2145 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2148 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2149 newi2pat
= PATTERN (m_split
);
2151 i3set
= single_set (NEXT_INSN (m_split
));
2152 i2set
= single_set (m_split
);
2154 /* In case we changed the mode of I2DEST, replace it in the
2155 pseudo-register table here. We can't do it above in case this
2156 code doesn't get executed and we do a split the other way. */
2158 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2159 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2161 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2163 /* If I2 or I3 has multiple SETs, we won't know how to track
2164 register status, so don't use these insns. If I2's destination
2165 is used between I2 and I3, we also can't use these insns. */
2167 if (i2_code_number
>= 0 && i2set
&& i3set
2168 && (next_real_insn (i2
) == i3
2169 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2170 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2172 if (insn_code_number
>= 0)
2175 /* It is possible that both insns now set the destination of I3.
2176 If so, we must show an extra use of it. */
2178 if (insn_code_number
>= 0)
2180 rtx new_i3_dest
= SET_DEST (i3set
);
2181 rtx new_i2_dest
= SET_DEST (i2set
);
2183 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2184 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2185 || GET_CODE (new_i3_dest
) == SUBREG
)
2186 new_i3_dest
= XEXP (new_i3_dest
, 0);
2188 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2189 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2190 || GET_CODE (new_i2_dest
) == SUBREG
)
2191 new_i2_dest
= XEXP (new_i2_dest
, 0);
2193 if (GET_CODE (new_i3_dest
) == REG
2194 && GET_CODE (new_i2_dest
) == REG
2195 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2196 REG_N_SETS (REGNO (new_i2_dest
))++;
2200 /* If we can split it and use I2DEST, go ahead and see if that
2201 helps things be recognized. Verify that none of the registers
2202 are set between I2 and I3. */
2203 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2205 && GET_CODE (i2dest
) == REG
2207 /* We need I2DEST in the proper mode. If it is a hard register
2208 or the only use of a pseudo, we can change its mode. */
2209 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2210 || GET_MODE (*split
) == VOIDmode
2211 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2212 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2213 && ! REG_USERVAR_P (i2dest
)))
2214 && (next_real_insn (i2
) == i3
2215 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2216 /* We can't overwrite I2DEST if its value is still used by
2218 && ! reg_referenced_p (i2dest
, newpat
))
2220 rtx newdest
= i2dest
;
2221 enum rtx_code split_code
= GET_CODE (*split
);
2222 enum machine_mode split_mode
= GET_MODE (*split
);
2224 /* Get NEWDEST as a register in the proper mode. We have already
2225 validated that we can do this. */
2226 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2228 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2230 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2231 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2234 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2235 an ASHIFT. This can occur if it was inside a PLUS and hence
2236 appeared to be a memory address. This is a kludge. */
2237 if (split_code
== MULT
2238 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2239 && INTVAL (XEXP (*split
, 1)) > 0
2240 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2242 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2243 XEXP (*split
, 0), GEN_INT (i
)));
2244 /* Update split_code because we may not have a multiply
2246 split_code
= GET_CODE (*split
);
2249 #ifdef INSN_SCHEDULING
2250 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2251 be written as a ZERO_EXTEND. */
2252 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2254 #ifdef LOAD_EXTEND_OP
2255 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2256 what it really is. */
2257 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2259 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2260 SUBREG_REG (*split
)));
2263 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2264 SUBREG_REG (*split
)));
2268 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2269 SUBST (*split
, newdest
);
2270 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2272 /* If the split point was a MULT and we didn't have one before,
2273 don't use one now. */
2274 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2275 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2279 /* Check for a case where we loaded from memory in a narrow mode and
2280 then sign extended it, but we need both registers. In that case,
2281 we have a PARALLEL with both loads from the same memory location.
2282 We can split this into a load from memory followed by a register-register
2283 copy. This saves at least one insn, more if register allocation can
2286 We cannot do this if the destination of the first assignment is a
2287 condition code register or cc0. We eliminate this case by making sure
2288 the SET_DEST and SET_SRC have the same mode.
2290 We cannot do this if the destination of the second assignment is
2291 a register that we have already assumed is zero-extended. Similarly
2292 for a SUBREG of such a register. */
2294 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2295 && GET_CODE (newpat
) == PARALLEL
2296 && XVECLEN (newpat
, 0) == 2
2297 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2298 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2299 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2300 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2301 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2302 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2303 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2304 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2306 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2307 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2308 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2309 (GET_CODE (temp
) == REG
2310 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2311 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2312 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2313 && (reg_stat
[REGNO (temp
)].nonzero_bits
2314 != GET_MODE_MASK (word_mode
))))
2315 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2316 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2317 (GET_CODE (temp
) == REG
2318 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2319 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2320 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2321 && (reg_stat
[REGNO (temp
)].nonzero_bits
2322 != GET_MODE_MASK (word_mode
)))))
2323 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2324 SET_SRC (XVECEXP (newpat
, 0, 1)))
2325 && ! find_reg_note (i3
, REG_UNUSED
,
2326 SET_DEST (XVECEXP (newpat
, 0, 0))))
2330 newi2pat
= XVECEXP (newpat
, 0, 0);
2331 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2332 newpat
= XVECEXP (newpat
, 0, 1);
2333 SUBST (SET_SRC (newpat
),
2334 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2335 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2337 if (i2_code_number
>= 0)
2338 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2340 if (insn_code_number
>= 0)
2345 /* If we will be able to accept this, we have made a change to the
2346 destination of I3. This requires us to do a few adjustments. */
2347 PATTERN (i3
) = newpat
;
2348 adjust_for_new_dest (i3
);
2350 /* I3 now uses what used to be its destination and which is
2351 now I2's destination. That means we need a LOG_LINK from
2352 I3 to I2. But we used to have one, so we still will.
2354 However, some later insn might be using I2's dest and have
2355 a LOG_LINK pointing at I3. We must remove this link.
2356 The simplest way to remove the link is to point it at I1,
2357 which we know will be a NOTE. */
2359 for (insn
= NEXT_INSN (i3
);
2360 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2361 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2362 insn
= NEXT_INSN (insn
))
2364 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2366 for (link
= LOG_LINKS (insn
); link
;
2367 link
= XEXP (link
, 1))
2368 if (XEXP (link
, 0) == i3
)
2369 XEXP (link
, 0) = i1
;
2377 /* Similarly, check for a case where we have a PARALLEL of two independent
2378 SETs but we started with three insns. In this case, we can do the sets
2379 as two separate insns. This case occurs when some SET allows two
2380 other insns to combine, but the destination of that SET is still live. */
2382 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2383 && GET_CODE (newpat
) == PARALLEL
2384 && XVECLEN (newpat
, 0) == 2
2385 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2387 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2388 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2389 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2390 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2391 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2393 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2394 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2395 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2396 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2397 XVECEXP (newpat
, 0, 0))
2398 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2399 XVECEXP (newpat
, 0, 1))
2400 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2401 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2403 /* Normally, it doesn't matter which of the two is done first,
2404 but it does if one references cc0. In that case, it has to
2407 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2409 newi2pat
= XVECEXP (newpat
, 0, 0);
2410 newpat
= XVECEXP (newpat
, 0, 1);
2415 newi2pat
= XVECEXP (newpat
, 0, 1);
2416 newpat
= XVECEXP (newpat
, 0, 0);
2419 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2421 if (i2_code_number
>= 0)
2422 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2425 /* If it still isn't recognized, fail and change things back the way they
2427 if ((insn_code_number
< 0
2428 /* Is the result a reasonable ASM_OPERANDS? */
2429 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2435 /* If we had to change another insn, make sure it is valid also. */
2436 if (undobuf
.other_insn
)
2438 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2439 rtx new_other_notes
;
2442 CLEAR_HARD_REG_SET (newpat_used_regs
);
2444 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2447 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2453 PATTERN (undobuf
.other_insn
) = other_pat
;
2455 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2456 are still valid. Then add any non-duplicate notes added by
2457 recog_for_combine. */
2458 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2460 next
= XEXP (note
, 1);
2462 if (REG_NOTE_KIND (note
) == REG_UNUSED
2463 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2465 if (GET_CODE (XEXP (note
, 0)) == REG
)
2466 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2468 remove_note (undobuf
.other_insn
, note
);
2472 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2473 if (GET_CODE (XEXP (note
, 0)) == REG
)
2474 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2476 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2477 undobuf
.other_insn
, NULL_RTX
);
2480 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2481 they are adjacent to each other or not. */
2483 rtx p
= prev_nonnote_insn (i3
);
2484 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2485 && sets_cc0_p (newi2pat
))
2493 /* We now know that we can do this combination. Merge the insns and
2494 update the status of registers and LOG_LINKS. */
2497 rtx i3notes
, i2notes
, i1notes
= 0;
2498 rtx i3links
, i2links
, i1links
= 0;
2502 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2504 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2505 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2507 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2509 /* Ensure that we do not have something that should not be shared but
2510 occurs multiple times in the new insns. Check this by first
2511 resetting all the `used' flags and then copying anything is shared. */
2513 reset_used_flags (i3notes
);
2514 reset_used_flags (i2notes
);
2515 reset_used_flags (i1notes
);
2516 reset_used_flags (newpat
);
2517 reset_used_flags (newi2pat
);
2518 if (undobuf
.other_insn
)
2519 reset_used_flags (PATTERN (undobuf
.other_insn
));
2521 i3notes
= copy_rtx_if_shared (i3notes
);
2522 i2notes
= copy_rtx_if_shared (i2notes
);
2523 i1notes
= copy_rtx_if_shared (i1notes
);
2524 newpat
= copy_rtx_if_shared (newpat
);
2525 newi2pat
= copy_rtx_if_shared (newi2pat
);
2526 if (undobuf
.other_insn
)
2527 reset_used_flags (PATTERN (undobuf
.other_insn
));
2529 INSN_CODE (i3
) = insn_code_number
;
2530 PATTERN (i3
) = newpat
;
2532 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2534 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2536 reset_used_flags (call_usage
);
2537 call_usage
= copy_rtx (call_usage
);
2540 replace_rtx (call_usage
, i2dest
, i2src
);
2543 replace_rtx (call_usage
, i1dest
, i1src
);
2545 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2548 if (undobuf
.other_insn
)
2549 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2551 /* We had one special case above where I2 had more than one set and
2552 we replaced a destination of one of those sets with the destination
2553 of I3. In that case, we have to update LOG_LINKS of insns later
2554 in this basic block. Note that this (expensive) case is rare.
2556 Also, in this case, we must pretend that all REG_NOTEs for I2
2557 actually came from I3, so that REG_UNUSED notes from I2 will be
2558 properly handled. */
2560 if (i3_subst_into_i2
)
2562 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2563 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2564 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2565 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2566 && ! find_reg_note (i2
, REG_UNUSED
,
2567 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2568 for (temp
= NEXT_INSN (i2
);
2569 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2570 || BB_HEAD (this_basic_block
) != temp
);
2571 temp
= NEXT_INSN (temp
))
2572 if (temp
!= i3
&& INSN_P (temp
))
2573 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2574 if (XEXP (link
, 0) == i2
)
2575 XEXP (link
, 0) = i3
;
2580 while (XEXP (link
, 1))
2581 link
= XEXP (link
, 1);
2582 XEXP (link
, 1) = i2notes
;
2596 INSN_CODE (i2
) = i2_code_number
;
2597 PATTERN (i2
) = newi2pat
;
2601 PUT_CODE (i2
, NOTE
);
2602 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2603 NOTE_SOURCE_FILE (i2
) = 0;
2610 PUT_CODE (i1
, NOTE
);
2611 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2612 NOTE_SOURCE_FILE (i1
) = 0;
2615 /* Get death notes for everything that is now used in either I3 or
2616 I2 and used to die in a previous insn. If we built two new
2617 patterns, move from I1 to I2 then I2 to I3 so that we get the
2618 proper movement on registers that I2 modifies. */
2622 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2623 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2626 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2629 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2631 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2633 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2635 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2637 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2639 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2640 know these are REG_UNUSED and want them to go to the desired insn,
2641 so we always pass it as i3. We have not counted the notes in
2642 reg_n_deaths yet, so we need to do so now. */
2644 if (newi2pat
&& new_i2_notes
)
2646 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2647 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2648 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2650 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2655 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2656 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2657 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2659 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2662 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2663 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2664 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2665 in that case, it might delete I2. Similarly for I2 and I1.
2666 Show an additional death due to the REG_DEAD note we make here. If
2667 we discard it in distribute_notes, we will decrement it again. */
2671 if (GET_CODE (i3dest_killed
) == REG
)
2672 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2674 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2675 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2677 NULL_RTX
, i2
, NULL_RTX
);
2679 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2681 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2684 if (i2dest_in_i2src
)
2686 if (GET_CODE (i2dest
) == REG
)
2687 REG_N_DEATHS (REGNO (i2dest
))++;
2689 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2690 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2691 NULL_RTX
, i2
, NULL_RTX
);
2693 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2694 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2697 if (i1dest_in_i1src
)
2699 if (GET_CODE (i1dest
) == REG
)
2700 REG_N_DEATHS (REGNO (i1dest
))++;
2702 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2703 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2704 NULL_RTX
, i2
, NULL_RTX
);
2706 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2707 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2710 distribute_links (i3links
);
2711 distribute_links (i2links
);
2712 distribute_links (i1links
);
2714 if (GET_CODE (i2dest
) == REG
)
2717 rtx i2_insn
= 0, i2_val
= 0, set
;
2719 /* The insn that used to set this register doesn't exist, and
2720 this life of the register may not exist either. See if one of
2721 I3's links points to an insn that sets I2DEST. If it does,
2722 that is now the last known value for I2DEST. If we don't update
2723 this and I2 set the register to a value that depended on its old
2724 contents, we will get confused. If this insn is used, thing
2725 will be set correctly in combine_instructions. */
2727 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2728 if ((set
= single_set (XEXP (link
, 0))) != 0
2729 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2730 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2732 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2734 /* If the reg formerly set in I2 died only once and that was in I3,
2735 zero its use count so it won't make `reload' do any work. */
2737 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2738 && ! i2dest_in_i2src
)
2740 regno
= REGNO (i2dest
);
2741 REG_N_SETS (regno
)--;
2745 if (i1
&& GET_CODE (i1dest
) == REG
)
2748 rtx i1_insn
= 0, i1_val
= 0, set
;
2750 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2751 if ((set
= single_set (XEXP (link
, 0))) != 0
2752 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2753 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2755 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2757 regno
= REGNO (i1dest
);
2758 if (! added_sets_1
&& ! i1dest_in_i1src
)
2759 REG_N_SETS (regno
)--;
2762 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2763 been made to this insn. The order of
2764 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2765 can affect nonzero_bits of newpat */
2767 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2768 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2770 /* Set new_direct_jump_p if a new return or simple jump instruction
2773 If I3 is now an unconditional jump, ensure that it has a
2774 BARRIER following it since it may have initially been a
2775 conditional jump. It may also be the last nonnote insn. */
2777 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2779 *new_direct_jump_p
= 1;
2780 mark_jump_label (PATTERN (i3
), i3
, 0);
2782 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2783 || GET_CODE (temp
) != BARRIER
)
2784 emit_barrier_after (i3
);
2787 if (undobuf
.other_insn
!= NULL_RTX
2788 && (returnjump_p (undobuf
.other_insn
)
2789 || any_uncondjump_p (undobuf
.other_insn
)))
2791 *new_direct_jump_p
= 1;
2793 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2794 || GET_CODE (temp
) != BARRIER
)
2795 emit_barrier_after (undobuf
.other_insn
);
2798 /* An NOOP jump does not need barrier, but it does need cleaning up
2800 if (GET_CODE (newpat
) == SET
2801 && SET_SRC (newpat
) == pc_rtx
2802 && SET_DEST (newpat
) == pc_rtx
)
2803 *new_direct_jump_p
= 1;
2806 combine_successes
++;
2809 if (added_links_insn
2810 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2811 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2812 return added_links_insn
;
2814 return newi2pat
? i2
: i3
;
2817 /* Undo all the modifications recorded in undobuf. */
2822 struct undo
*undo
, *next
;
2824 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2828 *undo
->where
.i
= undo
->old_contents
.i
;
2830 *undo
->where
.r
= undo
->old_contents
.r
;
2832 undo
->next
= undobuf
.frees
;
2833 undobuf
.frees
= undo
;
2839 /* We've committed to accepting the changes we made. Move all
2840 of the undos to the free list. */
2845 struct undo
*undo
, *next
;
2847 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2850 undo
->next
= undobuf
.frees
;
2851 undobuf
.frees
= undo
;
2857 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2858 where we have an arithmetic expression and return that point. LOC will
2861 try_combine will call this function to see if an insn can be split into
2865 find_split_point (rtx
*loc
, rtx insn
)
2868 enum rtx_code code
= GET_CODE (x
);
2870 unsigned HOST_WIDE_INT len
= 0;
2871 HOST_WIDE_INT pos
= 0;
2873 rtx inner
= NULL_RTX
;
2875 /* First special-case some codes. */
2879 #ifdef INSN_SCHEDULING
2880 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2882 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2885 return find_split_point (&SUBREG_REG (x
), insn
);
2889 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2890 using LO_SUM and HIGH. */
2891 if (GET_CODE (XEXP (x
, 0)) == CONST
2892 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2895 gen_rtx_LO_SUM (Pmode
,
2896 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2898 return &XEXP (XEXP (x
, 0), 0);
2902 /* If we have a PLUS whose second operand is a constant and the
2903 address is not valid, perhaps will can split it up using
2904 the machine-specific way to split large constants. We use
2905 the first pseudo-reg (one of the virtual regs) as a placeholder;
2906 it will not remain in the result. */
2907 if (GET_CODE (XEXP (x
, 0)) == PLUS
2908 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2909 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2911 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2912 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2915 /* This should have produced two insns, each of which sets our
2916 placeholder. If the source of the second is a valid address,
2917 we can make put both sources together and make a split point
2921 && NEXT_INSN (seq
) != NULL_RTX
2922 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2923 && GET_CODE (seq
) == INSN
2924 && GET_CODE (PATTERN (seq
)) == SET
2925 && SET_DEST (PATTERN (seq
)) == reg
2926 && ! reg_mentioned_p (reg
,
2927 SET_SRC (PATTERN (seq
)))
2928 && GET_CODE (NEXT_INSN (seq
)) == INSN
2929 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2930 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2931 && memory_address_p (GET_MODE (x
),
2932 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2934 rtx src1
= SET_SRC (PATTERN (seq
));
2935 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2937 /* Replace the placeholder in SRC2 with SRC1. If we can
2938 find where in SRC2 it was placed, that can become our
2939 split point and we can replace this address with SRC2.
2940 Just try two obvious places. */
2942 src2
= replace_rtx (src2
, reg
, src1
);
2944 if (XEXP (src2
, 0) == src1
)
2945 split
= &XEXP (src2
, 0);
2946 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2947 && XEXP (XEXP (src2
, 0), 0) == src1
)
2948 split
= &XEXP (XEXP (src2
, 0), 0);
2952 SUBST (XEXP (x
, 0), src2
);
2957 /* If that didn't work, perhaps the first operand is complex and
2958 needs to be computed separately, so make a split point there.
2959 This will occur on machines that just support REG + CONST
2960 and have a constant moved through some previous computation. */
2962 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
2963 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2964 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
2965 return &XEXP (XEXP (x
, 0), 0);
2971 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2972 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2973 we need to put the operand into a register. So split at that
2976 if (SET_DEST (x
) == cc0_rtx
2977 && GET_CODE (SET_SRC (x
)) != COMPARE
2978 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2979 && !OBJECT_P (SET_SRC (x
))
2980 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2981 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
2982 return &SET_SRC (x
);
2985 /* See if we can split SET_SRC as it stands. */
2986 split
= find_split_point (&SET_SRC (x
), insn
);
2987 if (split
&& split
!= &SET_SRC (x
))
2990 /* See if we can split SET_DEST as it stands. */
2991 split
= find_split_point (&SET_DEST (x
), insn
);
2992 if (split
&& split
!= &SET_DEST (x
))
2995 /* See if this is a bitfield assignment with everything constant. If
2996 so, this is an IOR of an AND, so split it into that. */
2997 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2998 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2999 <= HOST_BITS_PER_WIDE_INT
)
3000 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3001 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3002 && GET_CODE (SET_SRC (x
)) == CONST_INT
3003 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3004 + INTVAL (XEXP (SET_DEST (x
), 2)))
3005 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3006 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3008 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3009 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3010 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3011 rtx dest
= XEXP (SET_DEST (x
), 0);
3012 enum machine_mode mode
= GET_MODE (dest
);
3013 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3015 if (BITS_BIG_ENDIAN
)
3016 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3020 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3023 gen_binary (IOR
, mode
,
3024 gen_binary (AND
, mode
, dest
,
3025 gen_int_mode (~(mask
<< pos
),
3027 GEN_INT (src
<< pos
)));
3029 SUBST (SET_DEST (x
), dest
);
3031 split
= find_split_point (&SET_SRC (x
), insn
);
3032 if (split
&& split
!= &SET_SRC (x
))
3036 /* Otherwise, see if this is an operation that we can split into two.
3037 If so, try to split that. */
3038 code
= GET_CODE (SET_SRC (x
));
3043 /* If we are AND'ing with a large constant that is only a single
3044 bit and the result is only being used in a context where we
3045 need to know if it is zero or nonzero, replace it with a bit
3046 extraction. This will avoid the large constant, which might
3047 have taken more than one insn to make. If the constant were
3048 not a valid argument to the AND but took only one insn to make,
3049 this is no worse, but if it took more than one insn, it will
3052 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3053 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3054 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3055 && GET_CODE (SET_DEST (x
)) == REG
3056 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3057 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3058 && XEXP (*split
, 0) == SET_DEST (x
)
3059 && XEXP (*split
, 1) == const0_rtx
)
3061 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3062 XEXP (SET_SRC (x
), 0),
3063 pos
, NULL_RTX
, 1, 1, 0, 0);
3064 if (extraction
!= 0)
3066 SUBST (SET_SRC (x
), extraction
);
3067 return find_split_point (loc
, insn
);
3073 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3074 is known to be on, this can be converted into a NEG of a shift. */
3075 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3076 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3077 && 1 <= (pos
= exact_log2
3078 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3079 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3081 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3085 gen_rtx_LSHIFTRT (mode
,
3086 XEXP (SET_SRC (x
), 0),
3089 split
= find_split_point (&SET_SRC (x
), insn
);
3090 if (split
&& split
!= &SET_SRC (x
))
3096 inner
= XEXP (SET_SRC (x
), 0);
3098 /* We can't optimize if either mode is a partial integer
3099 mode as we don't know how many bits are significant
3101 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3102 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3106 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3112 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3113 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3115 inner
= XEXP (SET_SRC (x
), 0);
3116 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3117 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3119 if (BITS_BIG_ENDIAN
)
3120 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3121 unsignedp
= (code
== ZERO_EXTRACT
);
3129 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3131 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3133 /* For unsigned, we have a choice of a shift followed by an
3134 AND or two shifts. Use two shifts for field sizes where the
3135 constant might be too large. We assume here that we can
3136 always at least get 8-bit constants in an AND insn, which is
3137 true for every current RISC. */
3139 if (unsignedp
&& len
<= 8)
3144 (mode
, gen_lowpart (mode
, inner
),
3146 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3148 split
= find_split_point (&SET_SRC (x
), insn
);
3149 if (split
&& split
!= &SET_SRC (x
))
3156 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3157 gen_rtx_ASHIFT (mode
,
3158 gen_lowpart (mode
, inner
),
3159 GEN_INT (GET_MODE_BITSIZE (mode
)
3161 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3163 split
= find_split_point (&SET_SRC (x
), insn
);
3164 if (split
&& split
!= &SET_SRC (x
))
3169 /* See if this is a simple operation with a constant as the second
3170 operand. It might be that this constant is out of range and hence
3171 could be used as a split point. */
3172 if (BINARY_P (SET_SRC (x
))
3173 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3174 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3175 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3176 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3177 return &XEXP (SET_SRC (x
), 1);
3179 /* Finally, see if this is a simple operation with its first operand
3180 not in a register. The operation might require this operand in a
3181 register, so return it as a split point. We can always do this
3182 because if the first operand were another operation, we would have
3183 already found it as a split point. */
3184 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3185 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3186 return &XEXP (SET_SRC (x
), 0);
3192 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3193 it is better to write this as (not (ior A B)) so we can split it.
3194 Similarly for IOR. */
3195 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3198 gen_rtx_NOT (GET_MODE (x
),
3199 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3201 XEXP (XEXP (x
, 0), 0),
3202 XEXP (XEXP (x
, 1), 0))));
3203 return find_split_point (loc
, insn
);
3206 /* Many RISC machines have a large set of logical insns. If the
3207 second operand is a NOT, put it first so we will try to split the
3208 other operand first. */
3209 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3211 rtx tem
= XEXP (x
, 0);
3212 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3213 SUBST (XEXP (x
, 1), tem
);
3221 /* Otherwise, select our actions depending on our rtx class. */
3222 switch (GET_RTX_CLASS (code
))
3224 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3226 split
= find_split_point (&XEXP (x
, 2), insn
);
3229 /* ... fall through ... */
3231 case RTX_COMM_ARITH
:
3233 case RTX_COMM_COMPARE
:
3234 split
= find_split_point (&XEXP (x
, 1), insn
);
3237 /* ... fall through ... */
3239 /* Some machines have (and (shift ...) ...) insns. If X is not
3240 an AND, but XEXP (X, 0) is, use it as our split point. */
3241 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3242 return &XEXP (x
, 0);
3244 split
= find_split_point (&XEXP (x
, 0), insn
);
3250 /* Otherwise, we don't have a split point. */
3255 /* Throughout X, replace FROM with TO, and return the result.
3256 The result is TO if X is FROM;
3257 otherwise the result is X, but its contents may have been modified.
3258 If they were modified, a record was made in undobuf so that
3259 undo_all will (among other things) return X to its original state.
3261 If the number of changes necessary is too much to record to undo,
3262 the excess changes are not made, so the result is invalid.
3263 The changes already made can still be undone.
3264 undobuf.num_undo is incremented for such changes, so by testing that
3265 the caller can tell whether the result is valid.
3267 `n_occurrences' is incremented each time FROM is replaced.
3269 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3271 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3272 by copying if `n_occurrences' is nonzero. */
3275 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3277 enum rtx_code code
= GET_CODE (x
);
3278 enum machine_mode op0_mode
= VOIDmode
;
3283 /* Two expressions are equal if they are identical copies of a shared
3284 RTX or if they are both registers with the same register number
3287 #define COMBINE_RTX_EQUAL_P(X,Y) \
3289 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3290 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3292 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3295 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3298 /* If X and FROM are the same register but different modes, they will
3299 not have been seen as equal above. However, flow.c will make a
3300 LOG_LINKS entry for that case. If we do nothing, we will try to
3301 rerecognize our original insn and, when it succeeds, we will
3302 delete the feeding insn, which is incorrect.
3304 So force this insn not to match in this (rare) case. */
3305 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3306 && REGNO (x
) == REGNO (from
))
3307 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3309 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3310 of which may contain things that can be combined. */
3311 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3314 /* It is possible to have a subexpression appear twice in the insn.
3315 Suppose that FROM is a register that appears within TO.
3316 Then, after that subexpression has been scanned once by `subst',
3317 the second time it is scanned, TO may be found. If we were
3318 to scan TO here, we would find FROM within it and create a
3319 self-referent rtl structure which is completely wrong. */
3320 if (COMBINE_RTX_EQUAL_P (x
, to
))
3323 /* Parallel asm_operands need special attention because all of the
3324 inputs are shared across the arms. Furthermore, unsharing the
3325 rtl results in recognition failures. Failure to handle this case
3326 specially can result in circular rtl.
3328 Solve this by doing a normal pass across the first entry of the
3329 parallel, and only processing the SET_DESTs of the subsequent
3332 if (code
== PARALLEL
3333 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3334 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3336 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3338 /* If this substitution failed, this whole thing fails. */
3339 if (GET_CODE (new) == CLOBBER
3340 && XEXP (new, 0) == const0_rtx
)
3343 SUBST (XVECEXP (x
, 0, 0), new);
3345 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3347 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3349 if (GET_CODE (dest
) != REG
3350 && GET_CODE (dest
) != CC0
3351 && GET_CODE (dest
) != PC
)
3353 new = subst (dest
, from
, to
, 0, unique_copy
);
3355 /* If this substitution failed, this whole thing fails. */
3356 if (GET_CODE (new) == CLOBBER
3357 && XEXP (new, 0) == const0_rtx
)
3360 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3366 len
= GET_RTX_LENGTH (code
);
3367 fmt
= GET_RTX_FORMAT (code
);
3369 /* We don't need to process a SET_DEST that is a register, CC0,
3370 or PC, so set up to skip this common case. All other cases
3371 where we want to suppress replacing something inside a
3372 SET_SRC are handled via the IN_DEST operand. */
3374 && (GET_CODE (SET_DEST (x
)) == REG
3375 || GET_CODE (SET_DEST (x
)) == CC0
3376 || GET_CODE (SET_DEST (x
)) == PC
))
3379 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3382 op0_mode
= GET_MODE (XEXP (x
, 0));
3384 for (i
= 0; i
< len
; i
++)
3389 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3391 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3393 new = (unique_copy
&& n_occurrences
3394 ? copy_rtx (to
) : to
);
3399 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3402 /* If this substitution failed, this whole thing
3404 if (GET_CODE (new) == CLOBBER
3405 && XEXP (new, 0) == const0_rtx
)
3409 SUBST (XVECEXP (x
, i
, j
), new);
3412 else if (fmt
[i
] == 'e')
3414 /* If this is a register being set, ignore it. */
3417 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3418 || code
== ZERO_EXTRACT
)
3420 && GET_CODE (new) == REG
)
3423 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3425 /* In general, don't install a subreg involving two
3426 modes not tieable. It can worsen register
3427 allocation, and can even make invalid reload
3428 insns, since the reg inside may need to be copied
3429 from in the outside mode, and that may be invalid
3430 if it is an fp reg copied in integer mode.
3432 We allow two exceptions to this: It is valid if
3433 it is inside another SUBREG and the mode of that
3434 SUBREG and the mode of the inside of TO is
3435 tieable and it is valid if X is a SET that copies
3438 if (GET_CODE (to
) == SUBREG
3439 && ! MODES_TIEABLE_P (GET_MODE (to
),
3440 GET_MODE (SUBREG_REG (to
)))
3441 && ! (code
== SUBREG
3442 && MODES_TIEABLE_P (GET_MODE (x
),
3443 GET_MODE (SUBREG_REG (to
))))
3445 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3448 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3450 #ifdef CANNOT_CHANGE_MODE_CLASS
3452 && GET_CODE (to
) == REG
3453 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3454 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3457 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3460 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3464 /* If we are in a SET_DEST, suppress most cases unless we
3465 have gone inside a MEM, in which case we want to
3466 simplify the address. We assume here that things that
3467 are actually part of the destination have their inner
3468 parts in the first expression. This is true for SUBREG,
3469 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3470 things aside from REG and MEM that should appear in a
3472 new = subst (XEXP (x
, i
), from
, to
,
3474 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3475 || code
== ZERO_EXTRACT
))
3477 && i
== 0), unique_copy
);
3479 /* If we found that we will have to reject this combination,
3480 indicate that by returning the CLOBBER ourselves, rather than
3481 an expression containing it. This will speed things up as
3482 well as prevent accidents where two CLOBBERs are considered
3483 to be equal, thus producing an incorrect simplification. */
3485 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3488 if (GET_CODE (x
) == SUBREG
3489 && (GET_CODE (new) == CONST_INT
3490 || GET_CODE (new) == CONST_DOUBLE
))
3492 enum machine_mode mode
= GET_MODE (x
);
3494 x
= simplify_subreg (GET_MODE (x
), new,
3495 GET_MODE (SUBREG_REG (x
)),
3498 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3500 else if (GET_CODE (new) == CONST_INT
3501 && GET_CODE (x
) == ZERO_EXTEND
)
3503 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3504 new, GET_MODE (XEXP (x
, 0)));
3509 SUBST (XEXP (x
, i
), new);
3514 /* Try to simplify X. If the simplification changed the code, it is likely
3515 that further simplification will help, so loop, but limit the number
3516 of repetitions that will be performed. */
3518 for (i
= 0; i
< 4; i
++)
3520 /* If X is sufficiently simple, don't bother trying to do anything
3522 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3523 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3525 if (GET_CODE (x
) == code
)
3528 code
= GET_CODE (x
);
3530 /* We no longer know the original mode of operand 0 since we
3531 have changed the form of X) */
3532 op0_mode
= VOIDmode
;
3538 /* Simplify X, a piece of RTL. We just operate on the expression at the
3539 outer level; call `subst' to simplify recursively. Return the new
3542 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3543 if we are inside a SET_DEST. */
3546 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3548 enum rtx_code code
= GET_CODE (x
);
3549 enum machine_mode mode
= GET_MODE (x
);
3554 /* If this is a commutative operation, put a constant last and a complex
3555 expression first. We don't need to do this for comparisons here. */
3556 if (COMMUTATIVE_ARITH_P (x
)
3557 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3560 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3561 SUBST (XEXP (x
, 1), temp
);
3564 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3565 sign extension of a PLUS with a constant, reverse the order of the sign
3566 extension and the addition. Note that this not the same as the original
3567 code, but overflow is undefined for signed values. Also note that the
3568 PLUS will have been partially moved "inside" the sign-extension, so that
3569 the first operand of X will really look like:
3570 (ashiftrt (plus (ashift A C4) C5) C4).
3572 (plus (ashiftrt (ashift A C4) C2) C4)
3573 and replace the first operand of X with that expression. Later parts
3574 of this function may simplify the expression further.
3576 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3577 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3578 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3580 We do this to simplify address expressions. */
3582 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3583 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3584 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3585 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3586 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3587 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3588 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3589 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3590 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3591 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3592 XEXP (XEXP (x
, 0), 1))) != 0)
3595 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3596 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3597 INTVAL (XEXP (XEXP (x
, 0), 1)));
3599 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3600 INTVAL (XEXP (XEXP (x
, 0), 1)));
3602 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3605 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3606 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3607 things. Check for cases where both arms are testing the same
3610 Don't do anything if all operands are very simple. */
3613 && ((!OBJECT_P (XEXP (x
, 0))
3614 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3615 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3616 || (!OBJECT_P (XEXP (x
, 1))
3617 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3618 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3620 && (!OBJECT_P (XEXP (x
, 0))
3621 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3622 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3624 rtx cond
, true_rtx
, false_rtx
;
3626 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3628 /* If everything is a comparison, what we have is highly unlikely
3629 to be simpler, so don't use it. */
3630 && ! (COMPARISON_P (x
)
3631 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3633 rtx cop1
= const0_rtx
;
3634 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3636 if (cond_code
== NE
&& COMPARISON_P (cond
))
3639 /* Simplify the alternative arms; this may collapse the true and
3640 false arms to store-flag values. Be careful to use copy_rtx
3641 here since true_rtx or false_rtx might share RTL with x as a
3642 result of the if_then_else_cond call above. */
3643 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3644 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3646 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3647 is unlikely to be simpler. */
3648 if (general_operand (true_rtx
, VOIDmode
)
3649 && general_operand (false_rtx
, VOIDmode
))
3651 enum rtx_code reversed
;
3653 /* Restarting if we generate a store-flag expression will cause
3654 us to loop. Just drop through in this case. */
3656 /* If the result values are STORE_FLAG_VALUE and zero, we can
3657 just make the comparison operation. */
3658 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3659 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3660 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3661 && ((reversed
= reversed_comparison_code_parts
3662 (cond_code
, cond
, cop1
, NULL
))
3664 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3666 /* Likewise, we can make the negate of a comparison operation
3667 if the result values are - STORE_FLAG_VALUE and zero. */
3668 else if (GET_CODE (true_rtx
) == CONST_INT
3669 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3670 && false_rtx
== const0_rtx
)
3671 x
= simplify_gen_unary (NEG
, mode
,
3672 gen_binary (cond_code
, mode
, cond
,
3675 else if (GET_CODE (false_rtx
) == CONST_INT
3676 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3677 && true_rtx
== const0_rtx
3678 && ((reversed
= reversed_comparison_code_parts
3679 (cond_code
, cond
, cop1
, NULL
))
3681 x
= simplify_gen_unary (NEG
, mode
,
3682 gen_binary (reversed
, mode
,
3686 return gen_rtx_IF_THEN_ELSE (mode
,
3687 gen_binary (cond_code
, VOIDmode
,
3689 true_rtx
, false_rtx
);
3691 code
= GET_CODE (x
);
3692 op0_mode
= VOIDmode
;
3697 /* Try to fold this expression in case we have constants that weren't
3700 switch (GET_RTX_CLASS (code
))
3703 if (op0_mode
== VOIDmode
)
3704 op0_mode
= GET_MODE (XEXP (x
, 0));
3705 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3708 case RTX_COMM_COMPARE
:
3710 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3711 if (cmp_mode
== VOIDmode
)
3713 cmp_mode
= GET_MODE (XEXP (x
, 1));
3714 if (cmp_mode
== VOIDmode
)
3715 cmp_mode
= op0_mode
;
3717 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3718 XEXP (x
, 0), XEXP (x
, 1));
3721 case RTX_COMM_ARITH
:
3723 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3725 case RTX_BITFIELD_OPS
:
3727 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3728 XEXP (x
, 1), XEXP (x
, 2));
3737 code
= GET_CODE (temp
);
3738 op0_mode
= VOIDmode
;
3739 mode
= GET_MODE (temp
);
3742 /* First see if we can apply the inverse distributive law. */
3743 if (code
== PLUS
|| code
== MINUS
3744 || code
== AND
|| code
== IOR
|| code
== XOR
)
3746 x
= apply_distributive_law (x
);
3747 code
= GET_CODE (x
);
3748 op0_mode
= VOIDmode
;
3751 /* If CODE is an associative operation not otherwise handled, see if we
3752 can associate some operands. This can win if they are constants or
3753 if they are logically related (i.e. (a & b) & a). */
3754 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3755 || code
== AND
|| code
== IOR
|| code
== XOR
3756 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3757 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3758 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3760 if (GET_CODE (XEXP (x
, 0)) == code
)
3762 rtx other
= XEXP (XEXP (x
, 0), 0);
3763 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3764 rtx inner_op1
= XEXP (x
, 1);
3767 /* Make sure we pass the constant operand if any as the second
3768 one if this is a commutative operation. */
3769 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3771 rtx tem
= inner_op0
;
3772 inner_op0
= inner_op1
;
3775 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3776 : code
== DIV
? MULT
3778 mode
, inner_op0
, inner_op1
);
3780 /* For commutative operations, try the other pair if that one
3782 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3784 other
= XEXP (XEXP (x
, 0), 1);
3785 inner
= simplify_binary_operation (code
, mode
,
3786 XEXP (XEXP (x
, 0), 0),
3791 return gen_binary (code
, mode
, other
, inner
);
3795 /* A little bit of algebraic simplification here. */
3799 /* Ensure that our address has any ASHIFTs converted to MULT in case
3800 address-recognizing predicates are called later. */
3801 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3802 SUBST (XEXP (x
, 0), temp
);
3806 if (op0_mode
== VOIDmode
)
3807 op0_mode
= GET_MODE (SUBREG_REG (x
));
3809 /* See if this can be moved to simplify_subreg. */
3810 if (CONSTANT_P (SUBREG_REG (x
))
3811 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3812 /* Don't call gen_lowpart if the inner mode
3813 is VOIDmode and we cannot simplify it, as SUBREG without
3814 inner mode is invalid. */
3815 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3816 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3817 return gen_lowpart (mode
, SUBREG_REG (x
));
3819 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3823 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3829 /* Don't change the mode of the MEM if that would change the meaning
3831 if (GET_CODE (SUBREG_REG (x
)) == MEM
3832 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3833 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3834 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3836 /* Note that we cannot do any narrowing for non-constants since
3837 we might have been counting on using the fact that some bits were
3838 zero. We now do this in the SET. */
3843 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3844 && subreg_lowpart_p (XEXP (x
, 0))
3845 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3846 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3847 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3848 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3850 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3852 x
= gen_rtx_ROTATE (inner_mode
,
3853 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3855 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3856 return gen_lowpart (mode
, x
);
3859 /* Apply De Morgan's laws to reduce number of patterns for machines
3860 with negating logical insns (and-not, nand, etc.). If result has
3861 only one NOT, put it first, since that is how the patterns are
3864 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3866 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3867 enum machine_mode op_mode
;
3869 op_mode
= GET_MODE (in1
);
3870 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3872 op_mode
= GET_MODE (in2
);
3873 if (op_mode
== VOIDmode
)
3875 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3877 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3880 in2
= in1
; in1
= tem
;
3883 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3889 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3890 if (GET_CODE (XEXP (x
, 0)) == XOR
3891 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3892 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3893 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3895 temp
= expand_compound_operation (XEXP (x
, 0));
3897 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3898 replaced by (lshiftrt X C). This will convert
3899 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3901 if (GET_CODE (temp
) == ASHIFTRT
3902 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3903 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3904 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3905 INTVAL (XEXP (temp
, 1)));
3907 /* If X has only a single bit that might be nonzero, say, bit I, convert
3908 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3909 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3910 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3911 or a SUBREG of one since we'd be making the expression more
3912 complex if it was just a register. */
3914 if (GET_CODE (temp
) != REG
3915 && ! (GET_CODE (temp
) == SUBREG
3916 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3917 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3919 rtx temp1
= simplify_shift_const
3920 (NULL_RTX
, ASHIFTRT
, mode
,
3921 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3922 GET_MODE_BITSIZE (mode
) - 1 - i
),
3923 GET_MODE_BITSIZE (mode
) - 1 - i
);
3925 /* If all we did was surround TEMP with the two shifts, we
3926 haven't improved anything, so don't use it. Otherwise,
3927 we are better off with TEMP1. */
3928 if (GET_CODE (temp1
) != ASHIFTRT
3929 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3930 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3936 /* We can't handle truncation to a partial integer mode here
3937 because we don't know the real bitsize of the partial
3939 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3942 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3943 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3944 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3946 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3947 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3949 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3950 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3951 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3952 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3953 return XEXP (XEXP (x
, 0), 0);
3955 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3956 (OP:SI foo:SI) if OP is NEG or ABS. */
3957 if ((GET_CODE (XEXP (x
, 0)) == ABS
3958 || GET_CODE (XEXP (x
, 0)) == NEG
)
3959 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3960 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3961 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3962 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3963 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3965 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3967 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3968 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3969 && subreg_lowpart_p (XEXP (x
, 0)))
3970 return SUBREG_REG (XEXP (x
, 0));
3972 /* If we know that the value is already truncated, we can
3973 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3974 is nonzero for the corresponding modes. But don't do this
3975 for an (LSHIFTRT (MULT ...)) since this will cause problems
3976 with the umulXi3_highpart patterns. */
3977 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3978 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3979 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3980 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3981 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3982 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3983 return gen_lowpart (mode
, XEXP (x
, 0));
3985 /* A truncate of a comparison can be replaced with a subreg if
3986 STORE_FLAG_VALUE permits. This is like the previous test,
3987 but it works even if the comparison is done in a mode larger
3988 than HOST_BITS_PER_WIDE_INT. */
3989 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3990 && COMPARISON_P (XEXP (x
, 0))
3991 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
3992 return gen_lowpart (mode
, XEXP (x
, 0));
3994 /* Similarly, a truncate of a register whose value is a
3995 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3997 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3998 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
3999 && (temp
= get_last_value (XEXP (x
, 0)))
4000 && COMPARISON_P (temp
))
4001 return gen_lowpart (mode
, XEXP (x
, 0));
4005 case FLOAT_TRUNCATE
:
4006 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4007 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4008 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4009 return XEXP (XEXP (x
, 0), 0);
4011 /* (float_truncate:SF (float_truncate:DF foo:XF))
4012 = (float_truncate:SF foo:XF).
4013 This may eliminate double rounding, so it is unsafe.
4015 (float_truncate:SF (float_extend:XF foo:DF))
4016 = (float_truncate:SF foo:DF).
4018 (float_truncate:DF (float_extend:XF foo:SF))
4019 = (float_extend:SF foo:DF). */
4020 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4021 && flag_unsafe_math_optimizations
)
4022 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4023 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4025 > GET_MODE_SIZE (mode
)
4026 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4028 XEXP (XEXP (x
, 0), 0), mode
);
4030 /* (float_truncate (float x)) is (float x) */
4031 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4032 && (flag_unsafe_math_optimizations
4033 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4034 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4035 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4036 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4037 return simplify_gen_unary (FLOAT
, mode
,
4038 XEXP (XEXP (x
, 0), 0),
4039 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4041 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4042 (OP:SF foo:SF) if OP is NEG or ABS. */
4043 if ((GET_CODE (XEXP (x
, 0)) == ABS
4044 || GET_CODE (XEXP (x
, 0)) == NEG
)
4045 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4046 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4047 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4048 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4050 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4051 is (float_truncate:SF x). */
4052 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4053 && subreg_lowpart_p (XEXP (x
, 0))
4054 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4055 return SUBREG_REG (XEXP (x
, 0));
4058 /* (float_extend (float_extend x)) is (float_extend x)
4060 (float_extend (float x)) is (float x) assuming that double
4061 rounding can't happen.
4063 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4064 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4065 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4066 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4067 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4068 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4069 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4070 XEXP (XEXP (x
, 0), 0),
4071 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4076 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4077 using cc0, in which case we want to leave it as a COMPARE
4078 so we can distinguish it from a register-register-copy. */
4079 if (XEXP (x
, 1) == const0_rtx
)
4082 /* x - 0 is the same as x unless x's mode has signed zeros and
4083 allows rounding towards -infinity. Under those conditions,
4085 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4086 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4087 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4093 /* (const (const X)) can become (const X). Do it this way rather than
4094 returning the inner CONST since CONST can be shared with a
4096 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4097 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4102 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4103 can add in an offset. find_split_point will split this address up
4104 again if it doesn't match. */
4105 if (GET_CODE (XEXP (x
, 0)) == HIGH
4106 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4112 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4114 if (GET_CODE (XEXP (x
, 0)) == MULT
4115 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4119 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4120 in2
= XEXP (XEXP (x
, 0), 1);
4121 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4122 gen_binary (MULT
, mode
, in1
, in2
));
4125 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4126 outermost. That's because that's the way indexed addresses are
4127 supposed to appear. This code used to check many more cases, but
4128 they are now checked elsewhere. */
4129 if (GET_CODE (XEXP (x
, 0)) == PLUS
4130 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4131 return gen_binary (PLUS
, mode
,
4132 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4134 XEXP (XEXP (x
, 0), 1));
4136 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4137 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4138 bit-field and can be replaced by either a sign_extend or a
4139 sign_extract. The `and' may be a zero_extend and the two
4140 <c>, -<c> constants may be reversed. */
4141 if (GET_CODE (XEXP (x
, 0)) == XOR
4142 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4143 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4144 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4145 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4146 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4147 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4148 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4149 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4150 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4151 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4152 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4153 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4154 == (unsigned int) i
+ 1))))
4155 return simplify_shift_const
4156 (NULL_RTX
, ASHIFTRT
, mode
,
4157 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4158 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4159 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4160 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4162 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4163 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4164 is 1. This produces better code than the alternative immediately
4166 if (COMPARISON_P (XEXP (x
, 0))
4167 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4168 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4169 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4170 XEXP (XEXP (x
, 0), 0),
4171 XEXP (XEXP (x
, 0), 1))))
4173 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4175 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4176 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4177 the bitsize of the mode - 1. This allows simplification of
4178 "a = (b & 8) == 0;" */
4179 if (XEXP (x
, 1) == constm1_rtx
4180 && GET_CODE (XEXP (x
, 0)) != REG
4181 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4182 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4183 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4184 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4185 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4186 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4187 GET_MODE_BITSIZE (mode
) - 1),
4188 GET_MODE_BITSIZE (mode
) - 1);
4190 /* If we are adding two things that have no bits in common, convert
4191 the addition into an IOR. This will often be further simplified,
4192 for example in cases like ((a & 1) + (a & 2)), which can
4195 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4196 && (nonzero_bits (XEXP (x
, 0), mode
)
4197 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4199 /* Try to simplify the expression further. */
4200 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4201 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4203 /* If we could, great. If not, do not go ahead with the IOR
4204 replacement, since PLUS appears in many special purpose
4205 address arithmetic instructions. */
4206 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4212 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4213 by reversing the comparison code if valid. */
4214 if (STORE_FLAG_VALUE
== 1
4215 && XEXP (x
, 0) == const1_rtx
4216 && COMPARISON_P (XEXP (x
, 1))
4217 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4218 XEXP (XEXP (x
, 1), 0),
4219 XEXP (XEXP (x
, 1), 1))))
4222 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4223 (and <foo> (const_int pow2-1)) */
4224 if (GET_CODE (XEXP (x
, 1)) == AND
4225 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4226 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4227 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4228 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4229 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4231 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4233 if (GET_CODE (XEXP (x
, 1)) == MULT
4234 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4238 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4239 in2
= XEXP (XEXP (x
, 1), 1);
4240 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4244 /* Canonicalize (minus (neg A) (mult B C)) to
4245 (minus (mult (neg B) C) A). */
4246 if (GET_CODE (XEXP (x
, 1)) == MULT
4247 && GET_CODE (XEXP (x
, 0)) == NEG
)
4251 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4252 in2
= XEXP (XEXP (x
, 1), 1);
4253 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4254 XEXP (XEXP (x
, 0), 0));
4257 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4259 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4260 return gen_binary (MINUS
, mode
,
4261 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4262 XEXP (XEXP (x
, 1), 0)),
4263 XEXP (XEXP (x
, 1), 1));
4267 /* If we have (mult (plus A B) C), apply the distributive law and then
4268 the inverse distributive law to see if things simplify. This
4269 occurs mostly in addresses, often when unrolling loops. */
4271 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4273 x
= apply_distributive_law
4274 (gen_binary (PLUS
, mode
,
4275 gen_binary (MULT
, mode
,
4276 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4277 gen_binary (MULT
, mode
,
4278 XEXP (XEXP (x
, 0), 1),
4279 copy_rtx (XEXP (x
, 1)))));
4281 if (GET_CODE (x
) != MULT
)
4284 /* Try simplify a*(b/c) as (a*b)/c. */
4285 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4286 && GET_CODE (XEXP (x
, 0)) == DIV
)
4288 rtx tem
= simplify_binary_operation (MULT
, mode
,
4289 XEXP (XEXP (x
, 0), 0),
4292 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4297 /* If this is a divide by a power of two, treat it as a shift if
4298 its first operand is a shift. */
4299 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4300 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4301 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4302 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4303 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4304 || GET_CODE (XEXP (x
, 0)) == ROTATE
4305 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4306 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4310 case GT
: case GTU
: case GE
: case GEU
:
4311 case LT
: case LTU
: case LE
: case LEU
:
4312 case UNEQ
: case LTGT
:
4313 case UNGT
: case UNGE
:
4314 case UNLT
: case UNLE
:
4315 case UNORDERED
: case ORDERED
:
4316 /* If the first operand is a condition code, we can't do anything
4318 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4319 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4320 && ! CC0_P (XEXP (x
, 0))))
4322 rtx op0
= XEXP (x
, 0);
4323 rtx op1
= XEXP (x
, 1);
4324 enum rtx_code new_code
;
4326 if (GET_CODE (op0
) == COMPARE
)
4327 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4329 /* Simplify our comparison, if possible. */
4330 new_code
= simplify_comparison (code
, &op0
, &op1
);
4332 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4333 if only the low-order bit is possibly nonzero in X (such as when
4334 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4335 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4336 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4339 Remove any ZERO_EXTRACT we made when thinking this was a
4340 comparison. It may now be simpler to use, e.g., an AND. If a
4341 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4342 the call to make_compound_operation in the SET case. */
4344 if (STORE_FLAG_VALUE
== 1
4345 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4346 && op1
== const0_rtx
4347 && mode
== GET_MODE (op0
)
4348 && nonzero_bits (op0
, mode
) == 1)
4349 return gen_lowpart (mode
,
4350 expand_compound_operation (op0
));
4352 else if (STORE_FLAG_VALUE
== 1
4353 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4354 && op1
== const0_rtx
4355 && mode
== GET_MODE (op0
)
4356 && (num_sign_bit_copies (op0
, mode
)
4357 == GET_MODE_BITSIZE (mode
)))
4359 op0
= expand_compound_operation (op0
);
4360 return simplify_gen_unary (NEG
, mode
,
4361 gen_lowpart (mode
, op0
),
4365 else if (STORE_FLAG_VALUE
== 1
4366 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4367 && op1
== const0_rtx
4368 && mode
== GET_MODE (op0
)
4369 && nonzero_bits (op0
, mode
) == 1)
4371 op0
= expand_compound_operation (op0
);
4372 return gen_binary (XOR
, mode
,
4373 gen_lowpart (mode
, op0
),
4377 else if (STORE_FLAG_VALUE
== 1
4378 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4379 && op1
== const0_rtx
4380 && mode
== GET_MODE (op0
)
4381 && (num_sign_bit_copies (op0
, mode
)
4382 == GET_MODE_BITSIZE (mode
)))
4384 op0
= expand_compound_operation (op0
);
4385 return plus_constant (gen_lowpart (mode
, op0
), 1);
4388 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4390 if (STORE_FLAG_VALUE
== -1
4391 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4392 && op1
== const0_rtx
4393 && (num_sign_bit_copies (op0
, mode
)
4394 == GET_MODE_BITSIZE (mode
)))
4395 return gen_lowpart (mode
,
4396 expand_compound_operation (op0
));
4398 else if (STORE_FLAG_VALUE
== -1
4399 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4400 && op1
== const0_rtx
4401 && mode
== GET_MODE (op0
)
4402 && nonzero_bits (op0
, mode
) == 1)
4404 op0
= expand_compound_operation (op0
);
4405 return simplify_gen_unary (NEG
, mode
,
4406 gen_lowpart (mode
, op0
),
4410 else if (STORE_FLAG_VALUE
== -1
4411 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4412 && op1
== const0_rtx
4413 && mode
== GET_MODE (op0
)
4414 && (num_sign_bit_copies (op0
, mode
)
4415 == GET_MODE_BITSIZE (mode
)))
4417 op0
= expand_compound_operation (op0
);
4418 return simplify_gen_unary (NOT
, mode
,
4419 gen_lowpart (mode
, op0
),
4423 /* If X is 0/1, (eq X 0) is X-1. */
4424 else if (STORE_FLAG_VALUE
== -1
4425 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4426 && op1
== const0_rtx
4427 && mode
== GET_MODE (op0
)
4428 && nonzero_bits (op0
, mode
) == 1)
4430 op0
= expand_compound_operation (op0
);
4431 return plus_constant (gen_lowpart (mode
, op0
), -1);
4434 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4435 one bit that might be nonzero, we can convert (ne x 0) to
4436 (ashift x c) where C puts the bit in the sign bit. Remove any
4437 AND with STORE_FLAG_VALUE when we are done, since we are only
4438 going to test the sign bit. */
4439 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4440 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4441 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4442 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4443 && op1
== const0_rtx
4444 && mode
== GET_MODE (op0
)
4445 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4447 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4448 expand_compound_operation (op0
),
4449 GET_MODE_BITSIZE (mode
) - 1 - i
);
4450 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4456 /* If the code changed, return a whole new comparison. */
4457 if (new_code
!= code
)
4458 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4460 /* Otherwise, keep this operation, but maybe change its operands.
4461 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4462 SUBST (XEXP (x
, 0), op0
);
4463 SUBST (XEXP (x
, 1), op1
);
4468 return simplify_if_then_else (x
);
4474 /* If we are processing SET_DEST, we are done. */
4478 return expand_compound_operation (x
);
4481 return simplify_set (x
);
4486 return simplify_logical (x
);
4489 /* (abs (neg <foo>)) -> (abs <foo>) */
4490 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4491 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4493 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4495 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4498 /* If operand is something known to be positive, ignore the ABS. */
4499 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4500 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4501 <= HOST_BITS_PER_WIDE_INT
)
4502 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4503 & ((HOST_WIDE_INT
) 1
4504 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4508 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4509 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4510 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4515 /* (ffs (*_extend <X>)) = (ffs <X>) */
4516 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4517 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4518 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4523 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4524 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4525 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4529 /* (float (sign_extend <X>)) = (float <X>). */
4530 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4531 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4539 /* If this is a shift by a constant amount, simplify it. */
4540 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4541 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4542 INTVAL (XEXP (x
, 1)));
4544 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4546 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4548 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4555 rtx op0
= XEXP (x
, 0);
4556 rtx op1
= XEXP (x
, 1);
4559 if (GET_CODE (op1
) != PARALLEL
)
4561 len
= XVECLEN (op1
, 0);
4563 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4564 && GET_CODE (op0
) == VEC_CONCAT
)
4566 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4568 /* Try to find the element in the VEC_CONCAT. */
4571 if (GET_MODE (op0
) == GET_MODE (x
))
4573 if (GET_CODE (op0
) == VEC_CONCAT
)
4575 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4576 if (op0_size
< offset
)
4577 op0
= XEXP (op0
, 0);
4581 op0
= XEXP (op0
, 1);
4599 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4602 simplify_if_then_else (rtx x
)
4604 enum machine_mode mode
= GET_MODE (x
);
4605 rtx cond
= XEXP (x
, 0);
4606 rtx true_rtx
= XEXP (x
, 1);
4607 rtx false_rtx
= XEXP (x
, 2);
4608 enum rtx_code true_code
= GET_CODE (cond
);
4609 int comparison_p
= COMPARISON_P (cond
);
4612 enum rtx_code false_code
;
4615 /* Simplify storing of the truth value. */
4616 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4617 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4619 /* Also when the truth value has to be reversed. */
4621 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4622 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4626 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4627 in it is being compared against certain values. Get the true and false
4628 comparisons and see if that says anything about the value of each arm. */
4631 && ((false_code
= combine_reversed_comparison_code (cond
))
4633 && GET_CODE (XEXP (cond
, 0)) == REG
)
4636 rtx from
= XEXP (cond
, 0);
4637 rtx true_val
= XEXP (cond
, 1);
4638 rtx false_val
= true_val
;
4641 /* If FALSE_CODE is EQ, swap the codes and arms. */
4643 if (false_code
== EQ
)
4645 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4646 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4649 /* If we are comparing against zero and the expression being tested has
4650 only a single bit that might be nonzero, that is its value when it is
4651 not equal to zero. Similarly if it is known to be -1 or 0. */
4653 if (true_code
== EQ
&& true_val
== const0_rtx
4654 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4655 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4656 else if (true_code
== EQ
&& true_val
== const0_rtx
4657 && (num_sign_bit_copies (from
, GET_MODE (from
))
4658 == GET_MODE_BITSIZE (GET_MODE (from
))))
4659 false_code
= EQ
, false_val
= constm1_rtx
;
4661 /* Now simplify an arm if we know the value of the register in the
4662 branch and it is used in the arm. Be careful due to the potential
4663 of locally-shared RTL. */
4665 if (reg_mentioned_p (from
, true_rtx
))
4666 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4668 pc_rtx
, pc_rtx
, 0, 0);
4669 if (reg_mentioned_p (from
, false_rtx
))
4670 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4672 pc_rtx
, pc_rtx
, 0, 0);
4674 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4675 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4677 true_rtx
= XEXP (x
, 1);
4678 false_rtx
= XEXP (x
, 2);
4679 true_code
= GET_CODE (cond
);
4682 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4683 reversed, do so to avoid needing two sets of patterns for
4684 subtract-and-branch insns. Similarly if we have a constant in the true
4685 arm, the false arm is the same as the first operand of the comparison, or
4686 the false arm is more complicated than the true arm. */
4689 && combine_reversed_comparison_code (cond
) != UNKNOWN
4690 && (true_rtx
== pc_rtx
4691 || (CONSTANT_P (true_rtx
)
4692 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4693 || true_rtx
== const0_rtx
4694 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4695 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4696 && !OBJECT_P (false_rtx
))
4697 || reg_mentioned_p (true_rtx
, false_rtx
)
4698 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4700 true_code
= reversed_comparison_code (cond
, NULL
);
4702 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4705 SUBST (XEXP (x
, 1), false_rtx
);
4706 SUBST (XEXP (x
, 2), true_rtx
);
4708 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4711 /* It is possible that the conditional has been simplified out. */
4712 true_code
= GET_CODE (cond
);
4713 comparison_p
= COMPARISON_P (cond
);
4716 /* If the two arms are identical, we don't need the comparison. */
4718 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4721 /* Convert a == b ? b : a to "a". */
4722 if (true_code
== EQ
&& ! side_effects_p (cond
)
4723 && !HONOR_NANS (mode
)
4724 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4725 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4727 else if (true_code
== NE
&& ! side_effects_p (cond
)
4728 && !HONOR_NANS (mode
)
4729 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4730 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4733 /* Look for cases where we have (abs x) or (neg (abs X)). */
4735 if (GET_MODE_CLASS (mode
) == MODE_INT
4736 && GET_CODE (false_rtx
) == NEG
4737 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4739 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4740 && ! side_effects_p (true_rtx
))
4745 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4749 simplify_gen_unary (NEG
, mode
,
4750 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4756 /* Look for MIN or MAX. */
4758 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4760 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4761 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4762 && ! side_effects_p (cond
))
4767 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4770 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4773 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4776 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4781 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4782 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4783 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4784 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4785 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4786 neither 1 or -1, but it isn't worth checking for. */
4788 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4790 && GET_MODE_CLASS (mode
) == MODE_INT
4791 && ! side_effects_p (x
))
4793 rtx t
= make_compound_operation (true_rtx
, SET
);
4794 rtx f
= make_compound_operation (false_rtx
, SET
);
4795 rtx cond_op0
= XEXP (cond
, 0);
4796 rtx cond_op1
= XEXP (cond
, 1);
4797 enum rtx_code op
= NIL
, extend_op
= NIL
;
4798 enum machine_mode m
= mode
;
4799 rtx z
= 0, c1
= NULL_RTX
;
4801 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4802 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4803 || GET_CODE (t
) == ASHIFT
4804 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4805 && rtx_equal_p (XEXP (t
, 0), f
))
4806 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4808 /* If an identity-zero op is commutative, check whether there
4809 would be a match if we swapped the operands. */
4810 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4811 || GET_CODE (t
) == XOR
)
4812 && rtx_equal_p (XEXP (t
, 1), f
))
4813 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4814 else if (GET_CODE (t
) == SIGN_EXTEND
4815 && (GET_CODE (XEXP (t
, 0)) == PLUS
4816 || GET_CODE (XEXP (t
, 0)) == MINUS
4817 || GET_CODE (XEXP (t
, 0)) == IOR
4818 || GET_CODE (XEXP (t
, 0)) == XOR
4819 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4820 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4821 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4822 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4823 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4824 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4825 && (num_sign_bit_copies (f
, GET_MODE (f
))
4827 (GET_MODE_BITSIZE (mode
)
4828 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4830 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4831 extend_op
= SIGN_EXTEND
;
4832 m
= GET_MODE (XEXP (t
, 0));
4834 else if (GET_CODE (t
) == SIGN_EXTEND
4835 && (GET_CODE (XEXP (t
, 0)) == PLUS
4836 || GET_CODE (XEXP (t
, 0)) == IOR
4837 || GET_CODE (XEXP (t
, 0)) == XOR
)
4838 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4839 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4840 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4841 && (num_sign_bit_copies (f
, GET_MODE (f
))
4843 (GET_MODE_BITSIZE (mode
)
4844 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4846 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4847 extend_op
= SIGN_EXTEND
;
4848 m
= GET_MODE (XEXP (t
, 0));
4850 else if (GET_CODE (t
) == ZERO_EXTEND
4851 && (GET_CODE (XEXP (t
, 0)) == PLUS
4852 || GET_CODE (XEXP (t
, 0)) == MINUS
4853 || GET_CODE (XEXP (t
, 0)) == IOR
4854 || GET_CODE (XEXP (t
, 0)) == XOR
4855 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4856 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4857 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4858 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4859 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4860 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4861 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4862 && ((nonzero_bits (f
, GET_MODE (f
))
4863 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4866 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4867 extend_op
= ZERO_EXTEND
;
4868 m
= GET_MODE (XEXP (t
, 0));
4870 else if (GET_CODE (t
) == ZERO_EXTEND
4871 && (GET_CODE (XEXP (t
, 0)) == PLUS
4872 || GET_CODE (XEXP (t
, 0)) == IOR
4873 || GET_CODE (XEXP (t
, 0)) == XOR
)
4874 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4875 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4876 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4877 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4878 && ((nonzero_bits (f
, GET_MODE (f
))
4879 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4882 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4883 extend_op
= ZERO_EXTEND
;
4884 m
= GET_MODE (XEXP (t
, 0));
4889 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4890 pc_rtx
, pc_rtx
, 0, 0);
4891 temp
= gen_binary (MULT
, m
, temp
,
4892 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4893 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4894 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
4896 if (extend_op
!= NIL
)
4897 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4903 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4904 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4905 negation of a single bit, we can convert this operation to a shift. We
4906 can actually do this more generally, but it doesn't seem worth it. */
4908 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4909 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4910 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4911 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4912 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4913 == GET_MODE_BITSIZE (mode
))
4914 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4916 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4917 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
4919 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4920 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4921 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4922 && GET_MODE (XEXP (cond
, 0)) == mode
4923 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4924 == nonzero_bits (XEXP (cond
, 0), mode
)
4925 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4926 return XEXP (cond
, 0);
4931 /* Simplify X, a SET expression. Return the new expression. */
4934 simplify_set (rtx x
)
4936 rtx src
= SET_SRC (x
);
4937 rtx dest
= SET_DEST (x
);
4938 enum machine_mode mode
4939 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4943 /* (set (pc) (return)) gets written as (return). */
4944 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4947 /* Now that we know for sure which bits of SRC we are using, see if we can
4948 simplify the expression for the object knowing that we only need the
4951 if (GET_MODE_CLASS (mode
) == MODE_INT
4952 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4954 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4955 SUBST (SET_SRC (x
), src
);
4958 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4959 the comparison result and try to simplify it unless we already have used
4960 undobuf.other_insn. */
4961 if ((GET_MODE_CLASS (mode
) == MODE_CC
4962 || GET_CODE (src
) == COMPARE
4964 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4965 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4966 && COMPARISON_P (*cc_use
)
4967 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4969 enum rtx_code old_code
= GET_CODE (*cc_use
);
4970 enum rtx_code new_code
;
4972 int other_changed
= 0;
4973 enum machine_mode compare_mode
= GET_MODE (dest
);
4975 if (GET_CODE (src
) == COMPARE
)
4976 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4978 op0
= src
, op1
= const0_rtx
;
4980 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
4983 new_code
= old_code
;
4984 else if (!CONSTANT_P (tmp
))
4986 new_code
= GET_CODE (tmp
);
4987 op0
= XEXP (tmp
, 0);
4988 op1
= XEXP (tmp
, 1);
4992 rtx pat
= PATTERN (other_insn
);
4993 undobuf
.other_insn
= other_insn
;
4994 SUBST (*cc_use
, tmp
);
4996 /* Attempt to simplify CC user. */
4997 if (GET_CODE (pat
) == SET
)
4999 rtx
new = simplify_rtx (SET_SRC (pat
));
5000 if (new != NULL_RTX
)
5001 SUBST (SET_SRC (pat
), new);
5004 /* Convert X into a no-op move. */
5005 SUBST (SET_DEST (x
), pc_rtx
);
5006 SUBST (SET_SRC (x
), pc_rtx
);
5010 /* Simplify our comparison, if possible. */
5011 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5013 #ifdef SELECT_CC_MODE
5014 /* If this machine has CC modes other than CCmode, check to see if we
5015 need to use a different CC mode here. */
5016 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5017 compare_mode
= GET_MODE (op0
);
5019 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5022 /* If the mode changed, we have to change SET_DEST, the mode in the
5023 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5024 a hard register, just build new versions with the proper mode. If it
5025 is a pseudo, we lose unless it is only time we set the pseudo, in
5026 which case we can safely change its mode. */
5027 if (compare_mode
!= GET_MODE (dest
))
5029 unsigned int regno
= REGNO (dest
);
5030 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5032 if (regno
< FIRST_PSEUDO_REGISTER
5033 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5035 if (regno
>= FIRST_PSEUDO_REGISTER
)
5036 SUBST (regno_reg_rtx
[regno
], new_dest
);
5038 SUBST (SET_DEST (x
), new_dest
);
5039 SUBST (XEXP (*cc_use
, 0), new_dest
);
5046 #endif /* SELECT_CC_MODE */
5048 /* If the code changed, we have to build a new comparison in
5049 undobuf.other_insn. */
5050 if (new_code
!= old_code
)
5052 int other_changed_previously
= other_changed
;
5053 unsigned HOST_WIDE_INT mask
;
5055 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5059 /* If the only change we made was to change an EQ into an NE or
5060 vice versa, OP0 has only one bit that might be nonzero, and OP1
5061 is zero, check if changing the user of the condition code will
5062 produce a valid insn. If it won't, we can keep the original code
5063 in that insn by surrounding our operation with an XOR. */
5065 if (((old_code
== NE
&& new_code
== EQ
)
5066 || (old_code
== EQ
&& new_code
== NE
))
5067 && ! other_changed_previously
&& op1
== const0_rtx
5068 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5069 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5071 rtx pat
= PATTERN (other_insn
), note
= 0;
5073 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5074 && ! check_asm_operands (pat
)))
5076 PUT_CODE (*cc_use
, old_code
);
5079 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5085 undobuf
.other_insn
= other_insn
;
5088 /* If we are now comparing against zero, change our source if
5089 needed. If we do not use cc0, we always have a COMPARE. */
5090 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5092 SUBST (SET_SRC (x
), op0
);
5098 /* Otherwise, if we didn't previously have a COMPARE in the
5099 correct mode, we need one. */
5100 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5102 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5107 /* Otherwise, update the COMPARE if needed. */
5108 SUBST (XEXP (src
, 0), op0
);
5109 SUBST (XEXP (src
, 1), op1
);
5114 /* Get SET_SRC in a form where we have placed back any
5115 compound expressions. Then do the checks below. */
5116 src
= make_compound_operation (src
, SET
);
5117 SUBST (SET_SRC (x
), src
);
5120 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5121 and X being a REG or (subreg (reg)), we may be able to convert this to
5122 (set (subreg:m2 x) (op)).
5124 We can always do this if M1 is narrower than M2 because that means that
5125 we only care about the low bits of the result.
5127 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5128 perform a narrower operation than requested since the high-order bits will
5129 be undefined. On machine where it is defined, this transformation is safe
5130 as long as M1 and M2 have the same number of words. */
5132 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5133 && !OBJECT_P (SUBREG_REG (src
))
5134 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5136 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5137 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5138 #ifndef WORD_REGISTER_OPERATIONS
5139 && (GET_MODE_SIZE (GET_MODE (src
))
5140 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5142 #ifdef CANNOT_CHANGE_MODE_CLASS
5143 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5144 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5145 GET_MODE (SUBREG_REG (src
)),
5148 && (GET_CODE (dest
) == REG
5149 || (GET_CODE (dest
) == SUBREG
5150 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5152 SUBST (SET_DEST (x
),
5153 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5155 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5157 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5161 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5164 && GET_CODE (src
) == SUBREG
5165 && subreg_lowpart_p (src
)
5166 && (GET_MODE_BITSIZE (GET_MODE (src
))
5167 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5169 rtx inner
= SUBREG_REG (src
);
5170 enum machine_mode inner_mode
= GET_MODE (inner
);
5172 /* Here we make sure that we don't have a sign bit on. */
5173 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5174 && (nonzero_bits (inner
, inner_mode
)
5175 < ((unsigned HOST_WIDE_INT
) 1
5176 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5178 SUBST (SET_SRC (x
), inner
);
5184 #ifdef LOAD_EXTEND_OP
5185 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5186 would require a paradoxical subreg. Replace the subreg with a
5187 zero_extend to avoid the reload that would otherwise be required. */
5189 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5190 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5191 && SUBREG_BYTE (src
) == 0
5192 && (GET_MODE_SIZE (GET_MODE (src
))
5193 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5194 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5197 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5198 GET_MODE (src
), SUBREG_REG (src
)));
5204 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5205 are comparing an item known to be 0 or -1 against 0, use a logical
5206 operation instead. Check for one of the arms being an IOR of the other
5207 arm with some value. We compute three terms to be IOR'ed together. In
5208 practice, at most two will be nonzero. Then we do the IOR's. */
5210 if (GET_CODE (dest
) != PC
5211 && GET_CODE (src
) == IF_THEN_ELSE
5212 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5213 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5214 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5215 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5216 #ifdef HAVE_conditional_move
5217 && ! can_conditionally_move_p (GET_MODE (src
))
5219 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5220 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5221 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5222 && ! side_effects_p (src
))
5224 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5225 ? XEXP (src
, 1) : XEXP (src
, 2));
5226 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5227 ? XEXP (src
, 2) : XEXP (src
, 1));
5228 rtx term1
= const0_rtx
, term2
, term3
;
5230 if (GET_CODE (true_rtx
) == IOR
5231 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5232 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5233 else if (GET_CODE (true_rtx
) == IOR
5234 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5235 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5236 else if (GET_CODE (false_rtx
) == IOR
5237 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5238 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5239 else if (GET_CODE (false_rtx
) == IOR
5240 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5241 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5243 term2
= gen_binary (AND
, GET_MODE (src
),
5244 XEXP (XEXP (src
, 0), 0), true_rtx
);
5245 term3
= gen_binary (AND
, GET_MODE (src
),
5246 simplify_gen_unary (NOT
, GET_MODE (src
),
5247 XEXP (XEXP (src
, 0), 0),
5252 gen_binary (IOR
, GET_MODE (src
),
5253 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5259 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5260 whole thing fail. */
5261 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5263 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5266 /* Convert this into a field assignment operation, if possible. */
5267 return make_field_assignment (x
);
5270 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5274 simplify_logical (rtx x
)
5276 enum machine_mode mode
= GET_MODE (x
);
5277 rtx op0
= XEXP (x
, 0);
5278 rtx op1
= XEXP (x
, 1);
5281 switch (GET_CODE (x
))
5284 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5285 insn (and may simplify more). */
5286 if (GET_CODE (op0
) == XOR
5287 && rtx_equal_p (XEXP (op0
, 0), op1
)
5288 && ! side_effects_p (op1
))
5289 x
= gen_binary (AND
, mode
,
5290 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5293 if (GET_CODE (op0
) == XOR
5294 && rtx_equal_p (XEXP (op0
, 1), op1
)
5295 && ! side_effects_p (op1
))
5296 x
= gen_binary (AND
, mode
,
5297 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5300 /* Similarly for (~(A ^ B)) & A. */
5301 if (GET_CODE (op0
) == NOT
5302 && GET_CODE (XEXP (op0
, 0)) == XOR
5303 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5304 && ! side_effects_p (op1
))
5305 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5307 if (GET_CODE (op0
) == NOT
5308 && GET_CODE (XEXP (op0
, 0)) == XOR
5309 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5310 && ! side_effects_p (op1
))
5311 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5313 /* We can call simplify_and_const_int only if we don't lose
5314 any (sign) bits when converting INTVAL (op1) to
5315 "unsigned HOST_WIDE_INT". */
5316 if (GET_CODE (op1
) == CONST_INT
5317 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5318 || INTVAL (op1
) > 0))
5320 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5322 /* If we have (ior (and (X C1) C2)) and the next restart would be
5323 the last, simplify this by making C1 as small as possible
5324 and then exit. Only do this if C1 actually changes: for now
5325 this only saves memory but, should this transformation be
5326 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5327 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5328 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5329 && GET_CODE (op1
) == CONST_INT
5330 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5331 return gen_binary (IOR
, mode
,
5332 gen_binary (AND
, mode
, XEXP (op0
, 0),
5333 GEN_INT (INTVAL (XEXP (op0
, 1))
5334 & ~INTVAL (op1
))), op1
);
5336 if (GET_CODE (x
) != AND
)
5343 /* Convert (A | B) & A to A. */
5344 if (GET_CODE (op0
) == IOR
5345 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5346 || rtx_equal_p (XEXP (op0
, 1), op1
))
5347 && ! side_effects_p (XEXP (op0
, 0))
5348 && ! side_effects_p (XEXP (op0
, 1)))
5351 /* In the following group of tests (and those in case IOR below),
5352 we start with some combination of logical operations and apply
5353 the distributive law followed by the inverse distributive law.
5354 Most of the time, this results in no change. However, if some of
5355 the operands are the same or inverses of each other, simplifications
5358 For example, (and (ior A B) (not B)) can occur as the result of
5359 expanding a bit field assignment. When we apply the distributive
5360 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5361 which then simplifies to (and (A (not B))).
5363 If we have (and (ior A B) C), apply the distributive law and then
5364 the inverse distributive law to see if things simplify. */
5366 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5368 x
= apply_distributive_law
5369 (gen_binary (GET_CODE (op0
), mode
,
5370 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5371 gen_binary (AND
, mode
, XEXP (op0
, 1),
5373 if (GET_CODE (x
) != AND
)
5377 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5378 return apply_distributive_law
5379 (gen_binary (GET_CODE (op1
), mode
,
5380 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5381 gen_binary (AND
, mode
, XEXP (op1
, 1),
5384 /* Similarly, taking advantage of the fact that
5385 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5387 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5388 return apply_distributive_law
5389 (gen_binary (XOR
, mode
,
5390 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5391 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5394 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5395 return apply_distributive_law
5396 (gen_binary (XOR
, mode
,
5397 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5398 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5402 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5403 if (GET_CODE (op1
) == CONST_INT
5404 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5405 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5408 /* Convert (A & B) | A to A. */
5409 if (GET_CODE (op0
) == AND
5410 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5411 || rtx_equal_p (XEXP (op0
, 1), op1
))
5412 && ! side_effects_p (XEXP (op0
, 0))
5413 && ! side_effects_p (XEXP (op0
, 1)))
5416 /* If we have (ior (and A B) C), apply the distributive law and then
5417 the inverse distributive law to see if things simplify. */
5419 if (GET_CODE (op0
) == AND
)
5421 x
= apply_distributive_law
5422 (gen_binary (AND
, mode
,
5423 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5424 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5427 if (GET_CODE (x
) != IOR
)
5431 if (GET_CODE (op1
) == AND
)
5433 x
= apply_distributive_law
5434 (gen_binary (AND
, mode
,
5435 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5436 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5439 if (GET_CODE (x
) != IOR
)
5443 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5444 mode size to (rotate A CX). */
5446 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5447 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5448 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5449 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5450 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5451 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5452 == GET_MODE_BITSIZE (mode
)))
5453 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5454 (GET_CODE (op0
) == ASHIFT
5455 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5457 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5458 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5459 does not affect any of the bits in OP1, it can really be done
5460 as a PLUS and we can associate. We do this by seeing if OP1
5461 can be safely shifted left C bits. */
5462 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5463 && GET_CODE (XEXP (op0
, 0)) == PLUS
5464 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5465 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5466 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5468 int count
= INTVAL (XEXP (op0
, 1));
5469 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5471 if (mask
>> count
== INTVAL (op1
)
5472 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5474 SUBST (XEXP (XEXP (op0
, 0), 1),
5475 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5482 /* If we are XORing two things that have no bits in common,
5483 convert them into an IOR. This helps to detect rotation encoded
5484 using those methods and possibly other simplifications. */
5486 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5487 && (nonzero_bits (op0
, mode
)
5488 & nonzero_bits (op1
, mode
)) == 0)
5489 return (gen_binary (IOR
, mode
, op0
, op1
));
5491 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5492 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5495 int num_negated
= 0;
5497 if (GET_CODE (op0
) == NOT
)
5498 num_negated
++, op0
= XEXP (op0
, 0);
5499 if (GET_CODE (op1
) == NOT
)
5500 num_negated
++, op1
= XEXP (op1
, 0);
5502 if (num_negated
== 2)
5504 SUBST (XEXP (x
, 0), op0
);
5505 SUBST (XEXP (x
, 1), op1
);
5507 else if (num_negated
== 1)
5509 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5513 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5514 correspond to a machine insn or result in further simplifications
5515 if B is a constant. */
5517 if (GET_CODE (op0
) == AND
5518 && rtx_equal_p (XEXP (op0
, 1), op1
)
5519 && ! side_effects_p (op1
))
5520 return gen_binary (AND
, mode
,
5521 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5524 else if (GET_CODE (op0
) == AND
5525 && rtx_equal_p (XEXP (op0
, 0), op1
)
5526 && ! side_effects_p (op1
))
5527 return gen_binary (AND
, mode
,
5528 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5531 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5532 comparison if STORE_FLAG_VALUE is 1. */
5533 if (STORE_FLAG_VALUE
== 1
5534 && op1
== const1_rtx
5535 && COMPARISON_P (op0
)
5536 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5540 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5541 is (lt foo (const_int 0)), so we can perform the above
5542 simplification if STORE_FLAG_VALUE is 1. */
5544 if (STORE_FLAG_VALUE
== 1
5545 && op1
== const1_rtx
5546 && GET_CODE (op0
) == LSHIFTRT
5547 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5548 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5549 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5551 /* (xor (comparison foo bar) (const_int sign-bit))
5552 when STORE_FLAG_VALUE is the sign bit. */
5553 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5554 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5555 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5556 && op1
== const_true_rtx
5557 && COMPARISON_P (op0
)
5558 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5571 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5572 operations" because they can be replaced with two more basic operations.
5573 ZERO_EXTEND is also considered "compound" because it can be replaced with
5574 an AND operation, which is simpler, though only one operation.
5576 The function expand_compound_operation is called with an rtx expression
5577 and will convert it to the appropriate shifts and AND operations,
5578 simplifying at each stage.
5580 The function make_compound_operation is called to convert an expression
5581 consisting of shifts and ANDs into the equivalent compound expression.
5582 It is the inverse of this function, loosely speaking. */
5585 expand_compound_operation (rtx x
)
5587 unsigned HOST_WIDE_INT pos
= 0, len
;
5589 unsigned int modewidth
;
5592 switch (GET_CODE (x
))
5597 /* We can't necessarily use a const_int for a multiword mode;
5598 it depends on implicitly extending the value.
5599 Since we don't know the right way to extend it,
5600 we can't tell whether the implicit way is right.
5602 Even for a mode that is no wider than a const_int,
5603 we can't win, because we need to sign extend one of its bits through
5604 the rest of it, and we don't know which bit. */
5605 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5608 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5609 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5610 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5611 reloaded. If not for that, MEM's would very rarely be safe.
5613 Reject MODEs bigger than a word, because we might not be able
5614 to reference a two-register group starting with an arbitrary register
5615 (and currently gen_lowpart might crash for a SUBREG). */
5617 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5620 /* Reject MODEs that aren't scalar integers because turning vector
5621 or complex modes into shifts causes problems. */
5623 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5626 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5627 /* If the inner object has VOIDmode (the only way this can happen
5628 is if it is an ASM_OPERANDS), we can't do anything since we don't
5629 know how much masking to do. */
5638 /* If the operand is a CLOBBER, just return it. */
5639 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5642 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5643 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5644 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5647 /* Reject MODEs that aren't scalar integers because turning vector
5648 or complex modes into shifts causes problems. */
5650 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5653 len
= INTVAL (XEXP (x
, 1));
5654 pos
= INTVAL (XEXP (x
, 2));
5656 /* If this goes outside the object being extracted, replace the object
5657 with a (use (mem ...)) construct that only combine understands
5658 and is used only for this purpose. */
5659 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5660 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5662 if (BITS_BIG_ENDIAN
)
5663 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5670 /* Convert sign extension to zero extension, if we know that the high
5671 bit is not set, as this is easier to optimize. It will be converted
5672 back to cheaper alternative in make_extraction. */
5673 if (GET_CODE (x
) == SIGN_EXTEND
5674 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5675 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5676 & ~(((unsigned HOST_WIDE_INT
)
5677 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5681 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5682 rtx temp2
= expand_compound_operation (temp
);
5684 /* Make sure this is a profitable operation. */
5685 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5687 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5693 /* We can optimize some special cases of ZERO_EXTEND. */
5694 if (GET_CODE (x
) == ZERO_EXTEND
)
5696 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5697 know that the last value didn't have any inappropriate bits
5699 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5700 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5701 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5702 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5703 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5704 return XEXP (XEXP (x
, 0), 0);
5706 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5707 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5708 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5709 && subreg_lowpart_p (XEXP (x
, 0))
5710 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5711 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5712 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5713 return SUBREG_REG (XEXP (x
, 0));
5715 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5716 is a comparison and STORE_FLAG_VALUE permits. This is like
5717 the first case, but it works even when GET_MODE (x) is larger
5718 than HOST_WIDE_INT. */
5719 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5720 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5721 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5722 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5723 <= HOST_BITS_PER_WIDE_INT
)
5724 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5725 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5726 return XEXP (XEXP (x
, 0), 0);
5728 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5729 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5730 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5731 && subreg_lowpart_p (XEXP (x
, 0))
5732 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5733 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5734 <= HOST_BITS_PER_WIDE_INT
)
5735 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5736 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5737 return SUBREG_REG (XEXP (x
, 0));
5741 /* If we reach here, we want to return a pair of shifts. The inner
5742 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5743 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5744 logical depending on the value of UNSIGNEDP.
5746 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5747 converted into an AND of a shift.
5749 We must check for the case where the left shift would have a negative
5750 count. This can happen in a case like (x >> 31) & 255 on machines
5751 that can't shift by a constant. On those machines, we would first
5752 combine the shift with the AND to produce a variable-position
5753 extraction. Then the constant of 31 would be substituted in to produce
5754 a such a position. */
5756 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5757 if (modewidth
+ len
>= pos
)
5758 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5760 simplify_shift_const (NULL_RTX
, ASHIFT
,
5763 modewidth
- pos
- len
),
5766 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5767 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5768 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5771 ((HOST_WIDE_INT
) 1 << len
) - 1);
5773 /* Any other cases we can't handle. */
5776 /* If we couldn't do this for some reason, return the original
5778 if (GET_CODE (tem
) == CLOBBER
)
5784 /* X is a SET which contains an assignment of one object into
5785 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5786 or certain SUBREGS). If possible, convert it into a series of
5789 We half-heartedly support variable positions, but do not at all
5790 support variable lengths. */
5793 expand_field_assignment (rtx x
)
5796 rtx pos
; /* Always counts from low bit. */
5799 enum machine_mode compute_mode
;
5801 /* Loop until we find something we can't simplify. */
5804 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5805 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5807 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5808 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5809 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5811 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5812 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5814 inner
= XEXP (SET_DEST (x
), 0);
5815 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5816 pos
= XEXP (SET_DEST (x
), 2);
5818 /* If the position is constant and spans the width of INNER,
5819 surround INNER with a USE to indicate this. */
5820 if (GET_CODE (pos
) == CONST_INT
5821 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5822 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5824 if (BITS_BIG_ENDIAN
)
5826 if (GET_CODE (pos
) == CONST_INT
)
5827 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5829 else if (GET_CODE (pos
) == MINUS
5830 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5831 && (INTVAL (XEXP (pos
, 1))
5832 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5833 /* If position is ADJUST - X, new position is X. */
5834 pos
= XEXP (pos
, 0);
5836 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5837 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5843 /* A SUBREG between two modes that occupy the same numbers of words
5844 can be done by moving the SUBREG to the source. */
5845 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5846 /* We need SUBREGs to compute nonzero_bits properly. */
5847 && nonzero_sign_valid
5848 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5849 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5850 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5851 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5853 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5855 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5862 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5863 inner
= SUBREG_REG (inner
);
5865 compute_mode
= GET_MODE (inner
);
5867 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5868 if (! SCALAR_INT_MODE_P (compute_mode
))
5870 enum machine_mode imode
;
5872 /* Don't do anything for vector or complex integral types. */
5873 if (! FLOAT_MODE_P (compute_mode
))
5876 /* Try to find an integral mode to pun with. */
5877 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5878 if (imode
== BLKmode
)
5881 compute_mode
= imode
;
5882 inner
= gen_lowpart (imode
, inner
);
5885 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5886 if (len
< HOST_BITS_PER_WIDE_INT
)
5887 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5891 /* Now compute the equivalent expression. Make a copy of INNER
5892 for the SET_DEST in case it is a MEM into which we will substitute;
5893 we don't want shared RTL in that case. */
5895 (VOIDmode
, copy_rtx (inner
),
5896 gen_binary (IOR
, compute_mode
,
5897 gen_binary (AND
, compute_mode
,
5898 simplify_gen_unary (NOT
, compute_mode
,
5904 gen_binary (ASHIFT
, compute_mode
,
5905 gen_binary (AND
, compute_mode
,
5907 (compute_mode
, SET_SRC (x
)),
5915 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5916 it is an RTX that represents a variable starting position; otherwise,
5917 POS is the (constant) starting bit position (counted from the LSB).
5919 INNER may be a USE. This will occur when we started with a bitfield
5920 that went outside the boundary of the object in memory, which is
5921 allowed on most machines. To isolate this case, we produce a USE
5922 whose mode is wide enough and surround the MEM with it. The only
5923 code that understands the USE is this routine. If it is not removed,
5924 it will cause the resulting insn not to match.
5926 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5929 IN_DEST is nonzero if this is a reference in the destination of a
5930 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5931 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5934 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5935 ZERO_EXTRACT should be built even for bits starting at bit 0.
5937 MODE is the desired mode of the result (if IN_DEST == 0).
5939 The result is an RTX for the extraction or NULL_RTX if the target
5943 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5944 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5945 int in_dest
, int in_compare
)
5947 /* This mode describes the size of the storage area
5948 to fetch the overall value from. Within that, we
5949 ignore the POS lowest bits, etc. */
5950 enum machine_mode is_mode
= GET_MODE (inner
);
5951 enum machine_mode inner_mode
;
5952 enum machine_mode wanted_inner_mode
= byte_mode
;
5953 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5954 enum machine_mode pos_mode
= word_mode
;
5955 enum machine_mode extraction_mode
= word_mode
;
5956 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5959 rtx orig_pos_rtx
= pos_rtx
;
5960 HOST_WIDE_INT orig_pos
;
5962 /* Get some information about INNER and get the innermost object. */
5963 if (GET_CODE (inner
) == USE
)
5964 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5965 /* We don't need to adjust the position because we set up the USE
5966 to pretend that it was a full-word object. */
5967 spans_byte
= 1, inner
= XEXP (inner
, 0);
5968 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5970 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5971 consider just the QI as the memory to extract from.
5972 The subreg adds or removes high bits; its mode is
5973 irrelevant to the meaning of this extraction,
5974 since POS and LEN count from the lsb. */
5975 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5976 is_mode
= GET_MODE (SUBREG_REG (inner
));
5977 inner
= SUBREG_REG (inner
);
5979 else if (GET_CODE (inner
) == ASHIFT
5980 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5981 && pos_rtx
== 0 && pos
== 0
5982 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5984 /* We're extracting the least significant bits of an rtx
5985 (ashift X (const_int C)), where LEN > C. Extract the
5986 least significant (LEN - C) bits of X, giving an rtx
5987 whose mode is MODE, then shift it left C times. */
5988 new = make_extraction (mode
, XEXP (inner
, 0),
5989 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5990 unsignedp
, in_dest
, in_compare
);
5992 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
5995 inner_mode
= GET_MODE (inner
);
5997 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5998 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6000 /* See if this can be done without an extraction. We never can if the
6001 width of the field is not the same as that of some integer mode. For
6002 registers, we can only avoid the extraction if the position is at the
6003 low-order bit and this is either not in the destination or we have the
6004 appropriate STRICT_LOW_PART operation available.
6006 For MEM, we can avoid an extract if the field starts on an appropriate
6007 boundary and we can change the mode of the memory reference. However,
6008 we cannot directly access the MEM if we have a USE and the underlying
6009 MEM is not TMODE. This combination means that MEM was being used in a
6010 context where bits outside its mode were being referenced; that is only
6011 valid in bit-field insns. */
6013 if (tmode
!= BLKmode
6014 && ! (spans_byte
&& inner_mode
!= tmode
)
6015 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6016 && GET_CODE (inner
) != MEM
6018 || (GET_CODE (inner
) == REG
6019 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6020 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6022 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6023 : BITS_PER_UNIT
)) == 0
6024 /* We can't do this if we are widening INNER_MODE (it
6025 may not be aligned, for one thing). */
6026 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6027 && (inner_mode
== tmode
6028 || (! mode_dependent_address_p (XEXP (inner
, 0))
6029 && ! MEM_VOLATILE_P (inner
))))))
6031 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6032 field. If the original and current mode are the same, we need not
6033 adjust the offset. Otherwise, we do if bytes big endian.
6035 If INNER is not a MEM, get a piece consisting of just the field
6036 of interest (in this case POS % BITS_PER_WORD must be 0). */
6038 if (GET_CODE (inner
) == MEM
)
6040 HOST_WIDE_INT offset
;
6042 /* POS counts from lsb, but make OFFSET count in memory order. */
6043 if (BYTES_BIG_ENDIAN
)
6044 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6046 offset
= pos
/ BITS_PER_UNIT
;
6048 new = adjust_address_nv (inner
, tmode
, offset
);
6050 else if (GET_CODE (inner
) == REG
)
6052 if (tmode
!= inner_mode
)
6054 /* We can't call gen_lowpart in a DEST since we
6055 always want a SUBREG (see below) and it would sometimes
6056 return a new hard register. */
6059 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6061 if (WORDS_BIG_ENDIAN
6062 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6063 final_word
= ((GET_MODE_SIZE (inner_mode
)
6064 - GET_MODE_SIZE (tmode
))
6065 / UNITS_PER_WORD
) - final_word
;
6067 final_word
*= UNITS_PER_WORD
;
6068 if (BYTES_BIG_ENDIAN
&&
6069 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6070 final_word
+= (GET_MODE_SIZE (inner_mode
)
6071 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6073 /* Avoid creating invalid subregs, for example when
6074 simplifying (x>>32)&255. */
6075 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6078 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6081 new = gen_lowpart (tmode
, inner
);
6087 new = force_to_mode (inner
, tmode
,
6088 len
>= HOST_BITS_PER_WIDE_INT
6089 ? ~(unsigned HOST_WIDE_INT
) 0
6090 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6093 /* If this extraction is going into the destination of a SET,
6094 make a STRICT_LOW_PART unless we made a MEM. */
6097 return (GET_CODE (new) == MEM
? new
6098 : (GET_CODE (new) != SUBREG
6099 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6100 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6105 if (GET_CODE (new) == CONST_INT
)
6106 return gen_int_mode (INTVAL (new), mode
);
6108 /* If we know that no extraneous bits are set, and that the high
6109 bit is not set, convert the extraction to the cheaper of
6110 sign and zero extension, that are equivalent in these cases. */
6111 if (flag_expensive_optimizations
6112 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6113 && ((nonzero_bits (new, tmode
)
6114 & ~(((unsigned HOST_WIDE_INT
)
6115 GET_MODE_MASK (tmode
))
6119 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6120 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6122 /* Prefer ZERO_EXTENSION, since it gives more information to
6124 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6129 /* Otherwise, sign- or zero-extend unless we already are in the
6132 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6136 /* Unless this is a COMPARE or we have a funny memory reference,
6137 don't do anything with zero-extending field extracts starting at
6138 the low-order bit since they are simple AND operations. */
6139 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6140 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6143 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6144 we would be spanning bytes or if the position is not a constant and the
6145 length is not 1. In all other cases, we would only be going outside
6146 our object in cases when an original shift would have been
6148 if (! spans_byte
&& GET_CODE (inner
) == MEM
6149 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6150 || (pos_rtx
!= 0 && len
!= 1)))
6153 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6154 and the mode for the result. */
6155 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6157 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6158 pos_mode
= mode_for_extraction (EP_insv
, 2);
6159 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6162 if (! in_dest
&& unsignedp
6163 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6165 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6166 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6167 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6170 if (! in_dest
&& ! unsignedp
6171 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6173 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6174 pos_mode
= mode_for_extraction (EP_extv
, 3);
6175 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6178 /* Never narrow an object, since that might not be safe. */
6180 if (mode
!= VOIDmode
6181 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6182 extraction_mode
= mode
;
6184 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6185 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6186 pos_mode
= GET_MODE (pos_rtx
);
6188 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6189 if we have to change the mode of memory and cannot, the desired mode is
6191 if (GET_CODE (inner
) != MEM
)
6192 wanted_inner_mode
= wanted_inner_reg_mode
;
6193 else if (inner_mode
!= wanted_inner_mode
6194 && (mode_dependent_address_p (XEXP (inner
, 0))
6195 || MEM_VOLATILE_P (inner
)))
6196 wanted_inner_mode
= extraction_mode
;
6200 if (BITS_BIG_ENDIAN
)
6202 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6203 BITS_BIG_ENDIAN style. If position is constant, compute new
6204 position. Otherwise, build subtraction.
6205 Note that POS is relative to the mode of the original argument.
6206 If it's a MEM we need to recompute POS relative to that.
6207 However, if we're extracting from (or inserting into) a register,
6208 we want to recompute POS relative to wanted_inner_mode. */
6209 int width
= (GET_CODE (inner
) == MEM
6210 ? GET_MODE_BITSIZE (is_mode
)
6211 : GET_MODE_BITSIZE (wanted_inner_mode
));
6214 pos
= width
- len
- pos
;
6217 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6218 /* POS may be less than 0 now, but we check for that below.
6219 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6222 /* If INNER has a wider mode, make it smaller. If this is a constant
6223 extract, try to adjust the byte to point to the byte containing
6225 if (wanted_inner_mode
!= VOIDmode
6226 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6227 && ((GET_CODE (inner
) == MEM
6228 && (inner_mode
== wanted_inner_mode
6229 || (! mode_dependent_address_p (XEXP (inner
, 0))
6230 && ! MEM_VOLATILE_P (inner
))))))
6234 /* The computations below will be correct if the machine is big
6235 endian in both bits and bytes or little endian in bits and bytes.
6236 If it is mixed, we must adjust. */
6238 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6239 adjust OFFSET to compensate. */
6240 if (BYTES_BIG_ENDIAN
6242 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6243 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6245 /* If this is a constant position, we can move to the desired byte. */
6248 offset
+= pos
/ BITS_PER_UNIT
;
6249 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6252 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6254 && is_mode
!= wanted_inner_mode
)
6255 offset
= (GET_MODE_SIZE (is_mode
)
6256 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6258 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6259 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6262 /* If INNER is not memory, we can always get it into the proper mode. If we
6263 are changing its mode, POS must be a constant and smaller than the size
6265 else if (GET_CODE (inner
) != MEM
)
6267 if (GET_MODE (inner
) != wanted_inner_mode
6269 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6272 inner
= force_to_mode (inner
, wanted_inner_mode
,
6274 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6275 ? ~(unsigned HOST_WIDE_INT
) 0
6276 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6281 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6282 have to zero extend. Otherwise, we can just use a SUBREG. */
6284 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6286 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6288 /* If we know that no extraneous bits are set, and that the high
6289 bit is not set, convert extraction to cheaper one - either
6290 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6292 if (flag_expensive_optimizations
6293 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6294 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6295 & ~(((unsigned HOST_WIDE_INT
)
6296 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6300 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6302 /* Prefer ZERO_EXTENSION, since it gives more information to
6304 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6309 else if (pos_rtx
!= 0
6310 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6311 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6313 /* Make POS_RTX unless we already have it and it is correct. If we don't
6314 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6316 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6317 pos_rtx
= orig_pos_rtx
;
6319 else if (pos_rtx
== 0)
6320 pos_rtx
= GEN_INT (pos
);
6322 /* Make the required operation. See if we can use existing rtx. */
6323 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6324 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6326 new = gen_lowpart (mode
, new);
6331 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6332 with any other operations in X. Return X without that shift if so. */
6335 extract_left_shift (rtx x
, int count
)
6337 enum rtx_code code
= GET_CODE (x
);
6338 enum machine_mode mode
= GET_MODE (x
);
6344 /* This is the shift itself. If it is wide enough, we will return
6345 either the value being shifted if the shift count is equal to
6346 COUNT or a shift for the difference. */
6347 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6348 && INTVAL (XEXP (x
, 1)) >= count
)
6349 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6350 INTVAL (XEXP (x
, 1)) - count
);
6354 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6355 return simplify_gen_unary (code
, mode
, tem
, mode
);
6359 case PLUS
: case IOR
: case XOR
: case AND
:
6360 /* If we can safely shift this constant and we find the inner shift,
6361 make a new operation. */
6362 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6363 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6364 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6365 return gen_binary (code
, mode
, tem
,
6366 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6377 /* Look at the expression rooted at X. Look for expressions
6378 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6379 Form these expressions.
6381 Return the new rtx, usually just X.
6383 Also, for machines like the VAX that don't have logical shift insns,
6384 try to convert logical to arithmetic shift operations in cases where
6385 they are equivalent. This undoes the canonicalizations to logical
6386 shifts done elsewhere.
6388 We try, as much as possible, to re-use rtl expressions to save memory.
6390 IN_CODE says what kind of expression we are processing. Normally, it is
6391 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6392 being kludges), it is MEM. When processing the arguments of a comparison
6393 or a COMPARE against zero, it is COMPARE. */
6396 make_compound_operation (rtx x
, enum rtx_code in_code
)
6398 enum rtx_code code
= GET_CODE (x
);
6399 enum machine_mode mode
= GET_MODE (x
);
6400 int mode_width
= GET_MODE_BITSIZE (mode
);
6402 enum rtx_code next_code
;
6408 /* Select the code to be used in recursive calls. Once we are inside an
6409 address, we stay there. If we have a comparison, set to COMPARE,
6410 but once inside, go back to our default of SET. */
6412 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6413 : ((code
== COMPARE
|| COMPARISON_P (x
))
6414 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6415 : in_code
== COMPARE
? SET
: in_code
);
6417 /* Process depending on the code of this operation. If NEW is set
6418 nonzero, it will be returned. */
6423 /* Convert shifts by constants into multiplications if inside
6425 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6426 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6427 && INTVAL (XEXP (x
, 1)) >= 0)
6429 new = make_compound_operation (XEXP (x
, 0), next_code
);
6430 new = gen_rtx_MULT (mode
, new,
6431 GEN_INT ((HOST_WIDE_INT
) 1
6432 << INTVAL (XEXP (x
, 1))));
6437 /* If the second operand is not a constant, we can't do anything
6439 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6442 /* If the constant is a power of two minus one and the first operand
6443 is a logical right shift, make an extraction. */
6444 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6445 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6447 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6448 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6449 0, in_code
== COMPARE
);
6452 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6453 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6454 && subreg_lowpart_p (XEXP (x
, 0))
6455 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6456 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6458 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6460 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6461 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6462 0, in_code
== COMPARE
);
6464 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6465 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6466 || GET_CODE (XEXP (x
, 0)) == IOR
)
6467 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6468 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6469 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6471 /* Apply the distributive law, and then try to make extractions. */
6472 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6473 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6475 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6477 new = make_compound_operation (new, in_code
);
6480 /* If we are have (and (rotate X C) M) and C is larger than the number
6481 of bits in M, this is an extraction. */
6483 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6484 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6485 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6486 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6488 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6489 new = make_extraction (mode
, new,
6490 (GET_MODE_BITSIZE (mode
)
6491 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6492 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6495 /* On machines without logical shifts, if the operand of the AND is
6496 a logical shift and our mask turns off all the propagated sign
6497 bits, we can replace the logical shift with an arithmetic shift. */
6498 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6499 && !have_insn_for (LSHIFTRT
, mode
)
6500 && have_insn_for (ASHIFTRT
, mode
)
6501 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6502 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6503 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6504 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6506 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6508 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6509 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6511 gen_rtx_ASHIFTRT (mode
,
6512 make_compound_operation
6513 (XEXP (XEXP (x
, 0), 0), next_code
),
6514 XEXP (XEXP (x
, 0), 1)));
6517 /* If the constant is one less than a power of two, this might be
6518 representable by an extraction even if no shift is present.
6519 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6520 we are in a COMPARE. */
6521 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6522 new = make_extraction (mode
,
6523 make_compound_operation (XEXP (x
, 0),
6525 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6527 /* If we are in a comparison and this is an AND with a power of two,
6528 convert this into the appropriate bit extract. */
6529 else if (in_code
== COMPARE
6530 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6531 new = make_extraction (mode
,
6532 make_compound_operation (XEXP (x
, 0),
6534 i
, NULL_RTX
, 1, 1, 0, 1);
6539 /* If the sign bit is known to be zero, replace this with an
6540 arithmetic shift. */
6541 if (have_insn_for (ASHIFTRT
, mode
)
6542 && ! have_insn_for (LSHIFTRT
, mode
)
6543 && mode_width
<= HOST_BITS_PER_WIDE_INT
6544 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6546 new = gen_rtx_ASHIFTRT (mode
,
6547 make_compound_operation (XEXP (x
, 0),
6553 /* ... fall through ... */
6559 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6560 this is a SIGN_EXTRACT. */
6561 if (GET_CODE (rhs
) == CONST_INT
6562 && GET_CODE (lhs
) == ASHIFT
6563 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6564 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6566 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6567 new = make_extraction (mode
, new,
6568 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6569 NULL_RTX
, mode_width
- INTVAL (rhs
),
6570 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6574 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6575 If so, try to merge the shifts into a SIGN_EXTEND. We could
6576 also do this for some cases of SIGN_EXTRACT, but it doesn't
6577 seem worth the effort; the case checked for occurs on Alpha. */
6580 && ! (GET_CODE (lhs
) == SUBREG
6581 && (OBJECT_P (SUBREG_REG (lhs
))))
6582 && GET_CODE (rhs
) == CONST_INT
6583 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6584 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6585 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6586 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6587 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6592 /* Call ourselves recursively on the inner expression. If we are
6593 narrowing the object and it has a different RTL code from
6594 what it originally did, do this SUBREG as a force_to_mode. */
6596 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6597 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6598 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6599 && subreg_lowpart_p (x
))
6601 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6604 /* If we have something other than a SUBREG, we might have
6605 done an expansion, so rerun ourselves. */
6606 if (GET_CODE (newer
) != SUBREG
)
6607 newer
= make_compound_operation (newer
, in_code
);
6612 /* If this is a paradoxical subreg, and the new code is a sign or
6613 zero extension, omit the subreg and widen the extension. If it
6614 is a regular subreg, we can still get rid of the subreg by not
6615 widening so much, or in fact removing the extension entirely. */
6616 if ((GET_CODE (tem
) == SIGN_EXTEND
6617 || GET_CODE (tem
) == ZERO_EXTEND
)
6618 && subreg_lowpart_p (x
))
6620 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6621 || (GET_MODE_SIZE (mode
) >
6622 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6624 if (! SCALAR_INT_MODE_P (mode
))
6626 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6629 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6640 x
= gen_lowpart (mode
, new);
6641 code
= GET_CODE (x
);
6644 /* Now recursively process each operand of this operation. */
6645 fmt
= GET_RTX_FORMAT (code
);
6646 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6649 new = make_compound_operation (XEXP (x
, i
), next_code
);
6650 SUBST (XEXP (x
, i
), new);
6656 /* Given M see if it is a value that would select a field of bits
6657 within an item, but not the entire word. Return -1 if not.
6658 Otherwise, return the starting position of the field, where 0 is the
6661 *PLEN is set to the length of the field. */
6664 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6666 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6667 int pos
= exact_log2 (m
& -m
);
6671 /* Now shift off the low-order zero bits and see if we have a
6672 power of two minus 1. */
6673 len
= exact_log2 ((m
>> pos
) + 1);
6682 /* See if X can be simplified knowing that we will only refer to it in
6683 MODE and will only refer to those bits that are nonzero in MASK.
6684 If other bits are being computed or if masking operations are done
6685 that select a superset of the bits in MASK, they can sometimes be
6688 Return a possibly simplified expression, but always convert X to
6689 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6691 Also, if REG is nonzero and X is a register equal in value to REG,
6694 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6695 are all off in X. This is used when X will be complemented, by either
6696 NOT, NEG, or XOR. */
6699 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6700 rtx reg
, int just_select
)
6702 enum rtx_code code
= GET_CODE (x
);
6703 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6704 enum machine_mode op_mode
;
6705 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6708 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6709 code below will do the wrong thing since the mode of such an
6710 expression is VOIDmode.
6712 Also do nothing if X is a CLOBBER; this can happen if X was
6713 the return value from a call to gen_lowpart. */
6714 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6717 /* We want to perform the operation is its present mode unless we know
6718 that the operation is valid in MODE, in which case we do the operation
6720 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6721 && have_insn_for (code
, mode
))
6722 ? mode
: GET_MODE (x
));
6724 /* It is not valid to do a right-shift in a narrower mode
6725 than the one it came in with. */
6726 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6727 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6728 op_mode
= GET_MODE (x
);
6730 /* Truncate MASK to fit OP_MODE. */
6732 mask
&= GET_MODE_MASK (op_mode
);
6734 /* When we have an arithmetic operation, or a shift whose count we
6735 do not know, we need to assume that all bits up to the highest-order
6736 bit in MASK will be needed. This is how we form such a mask. */
6737 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6738 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6740 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6743 /* Determine what bits of X are guaranteed to be (non)zero. */
6744 nonzero
= nonzero_bits (x
, mode
);
6746 /* If none of the bits in X are needed, return a zero. */
6747 if (! just_select
&& (nonzero
& mask
) == 0)
6750 /* If X is a CONST_INT, return a new one. Do this here since the
6751 test below will fail. */
6752 if (GET_CODE (x
) == CONST_INT
)
6754 if (SCALAR_INT_MODE_P (mode
))
6755 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6758 x
= GEN_INT (INTVAL (x
) & mask
);
6759 return gen_lowpart_common (mode
, x
);
6763 /* If X is narrower than MODE and we want all the bits in X's mode, just
6764 get X in the proper mode. */
6765 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6766 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6767 return gen_lowpart (mode
, x
);
6769 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6770 MASK are already known to be zero in X, we need not do anything. */
6771 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6777 /* If X is a (clobber (const_int)), return it since we know we are
6778 generating something that won't match. */
6782 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6783 spanned the boundary of the MEM. If we are now masking so it is
6784 within that boundary, we don't need the USE any more. */
6785 if (! BITS_BIG_ENDIAN
6786 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6787 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6794 x
= expand_compound_operation (x
);
6795 if (GET_CODE (x
) != code
)
6796 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6800 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6801 || rtx_equal_p (reg
, get_last_value (x
))))
6806 if (subreg_lowpart_p (x
)
6807 /* We can ignore the effect of this SUBREG if it narrows the mode or
6808 if the constant masks to zero all the bits the mode doesn't
6810 && ((GET_MODE_SIZE (GET_MODE (x
))
6811 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6813 & GET_MODE_MASK (GET_MODE (x
))
6814 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6815 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6819 /* If this is an AND with a constant, convert it into an AND
6820 whose constant is the AND of that constant with MASK. If it
6821 remains an AND of MASK, delete it since it is redundant. */
6823 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6825 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6826 mask
& INTVAL (XEXP (x
, 1)));
6828 /* If X is still an AND, see if it is an AND with a mask that
6829 is just some low-order bits. If so, and it is MASK, we don't
6832 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6833 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6837 /* If it remains an AND, try making another AND with the bits
6838 in the mode mask that aren't in MASK turned on. If the
6839 constant in the AND is wide enough, this might make a
6840 cheaper constant. */
6842 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6843 && GET_MODE_MASK (GET_MODE (x
)) != mask
6844 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6846 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6847 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6848 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6851 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6852 number, sign extend it. */
6853 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6854 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6855 cval
|= (HOST_WIDE_INT
) -1 << width
;
6857 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6858 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6868 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6869 low-order bits (as in an alignment operation) and FOO is already
6870 aligned to that boundary, mask C1 to that boundary as well.
6871 This may eliminate that PLUS and, later, the AND. */
6874 unsigned int width
= GET_MODE_BITSIZE (mode
);
6875 unsigned HOST_WIDE_INT smask
= mask
;
6877 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6878 number, sign extend it. */
6880 if (width
< HOST_BITS_PER_WIDE_INT
6881 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6882 smask
|= (HOST_WIDE_INT
) -1 << width
;
6884 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6885 && exact_log2 (- smask
) >= 0
6886 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6887 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6888 return force_to_mode (plus_constant (XEXP (x
, 0),
6889 (INTVAL (XEXP (x
, 1)) & smask
)),
6890 mode
, smask
, reg
, next_select
);
6893 /* ... fall through ... */
6896 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6897 most significant bit in MASK since carries from those bits will
6898 affect the bits we are interested in. */
6903 /* If X is (minus C Y) where C's least set bit is larger than any bit
6904 in the mask, then we may replace with (neg Y). */
6905 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6906 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6907 & -INTVAL (XEXP (x
, 0))))
6910 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6912 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6915 /* Similarly, if C contains every bit in the fuller_mask, then we may
6916 replace with (not Y). */
6917 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6918 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6919 == INTVAL (XEXP (x
, 0))))
6921 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6922 XEXP (x
, 1), GET_MODE (x
));
6923 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6931 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6932 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6933 operation which may be a bitfield extraction. Ensure that the
6934 constant we form is not wider than the mode of X. */
6936 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6937 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6938 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6939 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6940 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6941 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6942 + floor_log2 (INTVAL (XEXP (x
, 1))))
6943 < GET_MODE_BITSIZE (GET_MODE (x
)))
6944 && (INTVAL (XEXP (x
, 1))
6945 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6947 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6948 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6949 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6950 XEXP (XEXP (x
, 0), 0), temp
);
6951 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6952 XEXP (XEXP (x
, 0), 1));
6953 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6957 /* For most binary operations, just propagate into the operation and
6958 change the mode if we have an operation of that mode. */
6960 op0
= gen_lowpart (op_mode
,
6961 force_to_mode (XEXP (x
, 0), mode
, mask
,
6963 op1
= gen_lowpart (op_mode
,
6964 force_to_mode (XEXP (x
, 1), mode
, mask
,
6967 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6968 x
= gen_binary (code
, op_mode
, op0
, op1
);
6972 /* For left shifts, do the same, but just for the first operand.
6973 However, we cannot do anything with shifts where we cannot
6974 guarantee that the counts are smaller than the size of the mode
6975 because such a count will have a different meaning in a
6978 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6979 && INTVAL (XEXP (x
, 1)) >= 0
6980 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6981 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6982 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6983 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6986 /* If the shift count is a constant and we can do arithmetic in
6987 the mode of the shift, refine which bits we need. Otherwise, use the
6988 conservative form of the mask. */
6989 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6990 && INTVAL (XEXP (x
, 1)) >= 0
6991 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6992 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6993 mask
>>= INTVAL (XEXP (x
, 1));
6997 op0
= gen_lowpart (op_mode
,
6998 force_to_mode (XEXP (x
, 0), op_mode
,
6999 mask
, reg
, next_select
));
7001 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7002 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7006 /* Here we can only do something if the shift count is a constant,
7007 this shift constant is valid for the host, and we can do arithmetic
7010 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7011 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7012 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7014 rtx inner
= XEXP (x
, 0);
7015 unsigned HOST_WIDE_INT inner_mask
;
7017 /* Select the mask of the bits we need for the shift operand. */
7018 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7020 /* We can only change the mode of the shift if we can do arithmetic
7021 in the mode of the shift and INNER_MASK is no wider than the
7022 width of OP_MODE. */
7023 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7024 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7025 op_mode
= GET_MODE (x
);
7027 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7029 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7030 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7033 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7034 shift and AND produces only copies of the sign bit (C2 is one less
7035 than a power of two), we can do this with just a shift. */
7037 if (GET_CODE (x
) == LSHIFTRT
7038 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7039 /* The shift puts one of the sign bit copies in the least significant
7041 && ((INTVAL (XEXP (x
, 1))
7042 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7043 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7044 && exact_log2 (mask
+ 1) >= 0
7045 /* Number of bits left after the shift must be more than the mask
7047 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7048 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7049 /* Must be more sign bit copies than the mask needs. */
7050 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7051 >= exact_log2 (mask
+ 1)))
7052 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7053 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7054 - exact_log2 (mask
+ 1)));
7059 /* If we are just looking for the sign bit, we don't need this shift at
7060 all, even if it has a variable count. */
7061 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7062 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7063 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7064 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7066 /* If this is a shift by a constant, get a mask that contains those bits
7067 that are not copies of the sign bit. We then have two cases: If
7068 MASK only includes those bits, this can be a logical shift, which may
7069 allow simplifications. If MASK is a single-bit field not within
7070 those bits, we are requesting a copy of the sign bit and hence can
7071 shift the sign bit to the appropriate location. */
7073 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7074 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7078 /* If the considered data is wider than HOST_WIDE_INT, we can't
7079 represent a mask for all its bits in a single scalar.
7080 But we only care about the lower bits, so calculate these. */
7082 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7084 nonzero
= ~(HOST_WIDE_INT
) 0;
7086 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7087 is the number of bits a full-width mask would have set.
7088 We need only shift if these are fewer than nonzero can
7089 hold. If not, we must keep all bits set in nonzero. */
7091 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7092 < HOST_BITS_PER_WIDE_INT
)
7093 nonzero
>>= INTVAL (XEXP (x
, 1))
7094 + HOST_BITS_PER_WIDE_INT
7095 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7099 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7100 nonzero
>>= INTVAL (XEXP (x
, 1));
7103 if ((mask
& ~nonzero
) == 0
7104 || (i
= exact_log2 (mask
)) >= 0)
7106 x
= simplify_shift_const
7107 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7108 i
< 0 ? INTVAL (XEXP (x
, 1))
7109 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7111 if (GET_CODE (x
) != ASHIFTRT
)
7112 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7116 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7117 even if the shift count isn't a constant. */
7119 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7123 /* If this is a zero- or sign-extension operation that just affects bits
7124 we don't care about, remove it. Be sure the call above returned
7125 something that is still a shift. */
7127 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7128 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7129 && INTVAL (XEXP (x
, 1)) >= 0
7130 && (INTVAL (XEXP (x
, 1))
7131 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7132 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7133 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7134 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7141 /* If the shift count is constant and we can do computations
7142 in the mode of X, compute where the bits we care about are.
7143 Otherwise, we can't do anything. Don't change the mode of
7144 the shift or propagate MODE into the shift, though. */
7145 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7146 && INTVAL (XEXP (x
, 1)) >= 0)
7148 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7149 GET_MODE (x
), GEN_INT (mask
),
7151 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7153 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7154 INTVAL (temp
), reg
, next_select
));
7159 /* If we just want the low-order bit, the NEG isn't needed since it
7160 won't change the low-order bit. */
7162 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7164 /* We need any bits less significant than the most significant bit in
7165 MASK since carries from those bits will affect the bits we are
7171 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7172 same as the XOR case above. Ensure that the constant we form is not
7173 wider than the mode of X. */
7175 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7176 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7177 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7178 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7179 < GET_MODE_BITSIZE (GET_MODE (x
)))
7180 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7182 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7184 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7185 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7187 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7190 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7191 use the full mask inside the NOT. */
7195 op0
= gen_lowpart (op_mode
,
7196 force_to_mode (XEXP (x
, 0), mode
, mask
,
7198 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7199 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7203 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7204 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7205 which is equal to STORE_FLAG_VALUE. */
7206 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7207 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7208 && (nonzero_bits (XEXP (x
, 0), mode
)
7209 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7210 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7215 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7216 written in a narrower mode. We play it safe and do not do so. */
7219 gen_lowpart (GET_MODE (x
),
7220 force_to_mode (XEXP (x
, 1), mode
,
7221 mask
, reg
, next_select
)));
7223 gen_lowpart (GET_MODE (x
),
7224 force_to_mode (XEXP (x
, 2), mode
,
7225 mask
, reg
, next_select
)));
7232 /* Ensure we return a value of the proper mode. */
7233 return gen_lowpart (mode
, x
);
7236 /* Return nonzero if X is an expression that has one of two values depending on
7237 whether some other value is zero or nonzero. In that case, we return the
7238 value that is being tested, *PTRUE is set to the value if the rtx being
7239 returned has a nonzero value, and *PFALSE is set to the other alternative.
7241 If we return zero, we set *PTRUE and *PFALSE to X. */
7244 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7246 enum machine_mode mode
= GET_MODE (x
);
7247 enum rtx_code code
= GET_CODE (x
);
7248 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7249 unsigned HOST_WIDE_INT nz
;
7251 /* If we are comparing a value against zero, we are done. */
7252 if ((code
== NE
|| code
== EQ
)
7253 && XEXP (x
, 1) == const0_rtx
)
7255 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7256 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7260 /* If this is a unary operation whose operand has one of two values, apply
7261 our opcode to compute those values. */
7262 else if (UNARY_P (x
)
7263 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7265 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7266 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7267 GET_MODE (XEXP (x
, 0)));
7271 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7272 make can't possibly match and would suppress other optimizations. */
7273 else if (code
== COMPARE
)
7276 /* If this is a binary operation, see if either side has only one of two
7277 values. If either one does or if both do and they are conditional on
7278 the same value, compute the new true and false values. */
7279 else if (BINARY_P (x
))
7281 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7282 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7284 if ((cond0
!= 0 || cond1
!= 0)
7285 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7287 /* If if_then_else_cond returned zero, then true/false are the
7288 same rtl. We must copy one of them to prevent invalid rtl
7291 true0
= copy_rtx (true0
);
7292 else if (cond1
== 0)
7293 true1
= copy_rtx (true1
);
7295 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7296 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7297 return cond0
? cond0
: cond1
;
7300 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7301 operands is zero when the other is nonzero, and vice-versa,
7302 and STORE_FLAG_VALUE is 1 or -1. */
7304 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7305 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7307 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7309 rtx op0
= XEXP (XEXP (x
, 0), 1);
7310 rtx op1
= XEXP (XEXP (x
, 1), 1);
7312 cond0
= XEXP (XEXP (x
, 0), 0);
7313 cond1
= XEXP (XEXP (x
, 1), 0);
7315 if (COMPARISON_P (cond0
)
7316 && COMPARISON_P (cond1
)
7317 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7318 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7319 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7320 || ((swap_condition (GET_CODE (cond0
))
7321 == combine_reversed_comparison_code (cond1
))
7322 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7323 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7324 && ! side_effects_p (x
))
7326 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7327 *pfalse
= gen_binary (MULT
, mode
,
7329 ? simplify_gen_unary (NEG
, mode
, op1
,
7337 /* Similarly for MULT, AND and UMIN, except that for these the result
7339 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7340 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7341 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7343 cond0
= XEXP (XEXP (x
, 0), 0);
7344 cond1
= XEXP (XEXP (x
, 1), 0);
7346 if (COMPARISON_P (cond0
)
7347 && COMPARISON_P (cond1
)
7348 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7349 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7350 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7351 || ((swap_condition (GET_CODE (cond0
))
7352 == combine_reversed_comparison_code (cond1
))
7353 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7354 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7355 && ! side_effects_p (x
))
7357 *ptrue
= *pfalse
= const0_rtx
;
7363 else if (code
== IF_THEN_ELSE
)
7365 /* If we have IF_THEN_ELSE already, extract the condition and
7366 canonicalize it if it is NE or EQ. */
7367 cond0
= XEXP (x
, 0);
7368 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7369 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7370 return XEXP (cond0
, 0);
7371 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7373 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7374 return XEXP (cond0
, 0);
7380 /* If X is a SUBREG, we can narrow both the true and false values
7381 if the inner expression, if there is a condition. */
7382 else if (code
== SUBREG
7383 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7386 true0
= simplify_gen_subreg (mode
, true0
,
7387 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7388 false0
= simplify_gen_subreg (mode
, false0
,
7389 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7390 if (true0
&& false0
)
7398 /* If X is a constant, this isn't special and will cause confusions
7399 if we treat it as such. Likewise if it is equivalent to a constant. */
7400 else if (CONSTANT_P (x
)
7401 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7404 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7405 will be least confusing to the rest of the compiler. */
7406 else if (mode
== BImode
)
7408 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7412 /* If X is known to be either 0 or -1, those are the true and
7413 false values when testing X. */
7414 else if (x
== constm1_rtx
|| x
== const0_rtx
7415 || (mode
!= VOIDmode
7416 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7418 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7422 /* Likewise for 0 or a single bit. */
7423 else if (SCALAR_INT_MODE_P (mode
)
7424 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7425 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7427 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7431 /* Otherwise fail; show no condition with true and false values the same. */
7432 *ptrue
= *pfalse
= x
;
7436 /* Return the value of expression X given the fact that condition COND
7437 is known to be true when applied to REG as its first operand and VAL
7438 as its second. X is known to not be shared and so can be modified in
7441 We only handle the simplest cases, and specifically those cases that
7442 arise with IF_THEN_ELSE expressions. */
7445 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7447 enum rtx_code code
= GET_CODE (x
);
7452 if (side_effects_p (x
))
7455 /* If either operand of the condition is a floating point value,
7456 then we have to avoid collapsing an EQ comparison. */
7458 && rtx_equal_p (x
, reg
)
7459 && ! FLOAT_MODE_P (GET_MODE (x
))
7460 && ! FLOAT_MODE_P (GET_MODE (val
)))
7463 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7466 /* If X is (abs REG) and we know something about REG's relationship
7467 with zero, we may be able to simplify this. */
7469 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7472 case GE
: case GT
: case EQ
:
7475 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7477 GET_MODE (XEXP (x
, 0)));
7482 /* The only other cases we handle are MIN, MAX, and comparisons if the
7483 operands are the same as REG and VAL. */
7485 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7487 if (rtx_equal_p (XEXP (x
, 0), val
))
7488 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7490 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7492 if (COMPARISON_P (x
))
7494 if (comparison_dominates_p (cond
, code
))
7495 return const_true_rtx
;
7497 code
= combine_reversed_comparison_code (x
);
7499 && comparison_dominates_p (cond
, code
))
7504 else if (code
== SMAX
|| code
== SMIN
7505 || code
== UMIN
|| code
== UMAX
)
7507 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7509 /* Do not reverse the condition when it is NE or EQ.
7510 This is because we cannot conclude anything about
7511 the value of 'SMAX (x, y)' when x is not equal to y,
7512 but we can when x equals y. */
7513 if ((code
== SMAX
|| code
== UMAX
)
7514 && ! (cond
== EQ
|| cond
== NE
))
7515 cond
= reverse_condition (cond
);
7520 return unsignedp
? x
: XEXP (x
, 1);
7522 return unsignedp
? x
: XEXP (x
, 0);
7524 return unsignedp
? XEXP (x
, 1) : x
;
7526 return unsignedp
? XEXP (x
, 0) : x
;
7533 else if (code
== SUBREG
)
7535 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7536 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7538 if (SUBREG_REG (x
) != r
)
7540 /* We must simplify subreg here, before we lose track of the
7541 original inner_mode. */
7542 new = simplify_subreg (GET_MODE (x
), r
,
7543 inner_mode
, SUBREG_BYTE (x
));
7547 SUBST (SUBREG_REG (x
), r
);
7552 /* We don't have to handle SIGN_EXTEND here, because even in the
7553 case of replacing something with a modeless CONST_INT, a
7554 CONST_INT is already (supposed to be) a valid sign extension for
7555 its narrower mode, which implies it's already properly
7556 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7557 story is different. */
7558 else if (code
== ZERO_EXTEND
)
7560 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7561 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7563 if (XEXP (x
, 0) != r
)
7565 /* We must simplify the zero_extend here, before we lose
7566 track of the original inner_mode. */
7567 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7572 SUBST (XEXP (x
, 0), r
);
7578 fmt
= GET_RTX_FORMAT (code
);
7579 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7582 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7583 else if (fmt
[i
] == 'E')
7584 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7585 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7592 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7593 assignment as a field assignment. */
7596 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7598 if (x
== y
|| rtx_equal_p (x
, y
))
7601 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7604 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7605 Note that all SUBREGs of MEM are paradoxical; otherwise they
7606 would have been rewritten. */
7607 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7608 && GET_CODE (SUBREG_REG (y
)) == MEM
7609 && rtx_equal_p (SUBREG_REG (y
),
7610 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7613 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7614 && GET_CODE (SUBREG_REG (x
)) == MEM
7615 && rtx_equal_p (SUBREG_REG (x
),
7616 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7619 /* We used to see if get_last_value of X and Y were the same but that's
7620 not correct. In one direction, we'll cause the assignment to have
7621 the wrong destination and in the case, we'll import a register into this
7622 insn that might have already have been dead. So fail if none of the
7623 above cases are true. */
7627 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7628 Return that assignment if so.
7630 We only handle the most common cases. */
7633 make_field_assignment (rtx x
)
7635 rtx dest
= SET_DEST (x
);
7636 rtx src
= SET_SRC (x
);
7641 unsigned HOST_WIDE_INT len
;
7643 enum machine_mode mode
;
7645 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7646 a clear of a one-bit field. We will have changed it to
7647 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7650 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7651 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7652 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7653 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7655 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7658 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7662 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7663 && subreg_lowpart_p (XEXP (src
, 0))
7664 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7665 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7666 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7667 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7668 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7669 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7671 assign
= make_extraction (VOIDmode
, dest
, 0,
7672 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7675 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7679 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7681 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7682 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7683 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7685 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7688 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7692 /* The other case we handle is assignments into a constant-position
7693 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7694 a mask that has all one bits except for a group of zero bits and
7695 OTHER is known to have zeros where C1 has ones, this is such an
7696 assignment. Compute the position and length from C1. Shift OTHER
7697 to the appropriate position, force it to the required mode, and
7698 make the extraction. Check for the AND in both operands. */
7700 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7703 rhs
= expand_compound_operation (XEXP (src
, 0));
7704 lhs
= expand_compound_operation (XEXP (src
, 1));
7706 if (GET_CODE (rhs
) == AND
7707 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7708 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7709 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7710 else if (GET_CODE (lhs
) == AND
7711 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7712 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7713 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7717 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7718 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7719 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7720 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7723 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7727 /* The mode to use for the source is the mode of the assignment, or of
7728 what is inside a possible STRICT_LOW_PART. */
7729 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7730 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7732 /* Shift OTHER right POS places and make it the source, restricting it
7733 to the proper length and mode. */
7735 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7736 GET_MODE (src
), other
, pos
),
7738 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7739 ? ~(unsigned HOST_WIDE_INT
) 0
7740 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7743 /* If SRC is masked by an AND that does not make a difference in
7744 the value being stored, strip it. */
7745 if (GET_CODE (assign
) == ZERO_EXTRACT
7746 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7747 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7748 && GET_CODE (src
) == AND
7749 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7750 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7751 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7752 src
= XEXP (src
, 0);
7754 return gen_rtx_SET (VOIDmode
, assign
, src
);
7757 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7761 apply_distributive_law (rtx x
)
7763 enum rtx_code code
= GET_CODE (x
);
7764 enum rtx_code inner_code
;
7765 rtx lhs
, rhs
, other
;
7768 /* Distributivity is not true for floating point as it can change the
7769 value. So we don't do it unless -funsafe-math-optimizations. */
7770 if (FLOAT_MODE_P (GET_MODE (x
))
7771 && ! flag_unsafe_math_optimizations
)
7774 /* The outer operation can only be one of the following: */
7775 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7776 && code
!= PLUS
&& code
!= MINUS
)
7782 /* If either operand is a primitive we can't do anything, so get out
7784 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7787 lhs
= expand_compound_operation (lhs
);
7788 rhs
= expand_compound_operation (rhs
);
7789 inner_code
= GET_CODE (lhs
);
7790 if (inner_code
!= GET_CODE (rhs
))
7793 /* See if the inner and outer operations distribute. */
7800 /* These all distribute except over PLUS. */
7801 if (code
== PLUS
|| code
== MINUS
)
7806 if (code
!= PLUS
&& code
!= MINUS
)
7811 /* This is also a multiply, so it distributes over everything. */
7815 /* Non-paradoxical SUBREGs distributes over all operations, provided
7816 the inner modes and byte offsets are the same, this is an extraction
7817 of a low-order part, we don't convert an fp operation to int or
7818 vice versa, and we would not be converting a single-word
7819 operation into a multi-word operation. The latter test is not
7820 required, but it prevents generating unneeded multi-word operations.
7821 Some of the previous tests are redundant given the latter test, but
7822 are retained because they are required for correctness.
7824 We produce the result slightly differently in this case. */
7826 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7827 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7828 || ! subreg_lowpart_p (lhs
)
7829 || (GET_MODE_CLASS (GET_MODE (lhs
))
7830 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7831 || (GET_MODE_SIZE (GET_MODE (lhs
))
7832 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7833 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7836 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7837 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7838 return gen_lowpart (GET_MODE (x
), tem
);
7844 /* Set LHS and RHS to the inner operands (A and B in the example
7845 above) and set OTHER to the common operand (C in the example).
7846 There is only one way to do this unless the inner operation is
7848 if (COMMUTATIVE_ARITH_P (lhs
)
7849 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7850 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7851 else if (COMMUTATIVE_ARITH_P (lhs
)
7852 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7853 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7854 else if (COMMUTATIVE_ARITH_P (lhs
)
7855 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7856 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7857 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7858 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7862 /* Form the new inner operation, seeing if it simplifies first. */
7863 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7865 /* There is one exception to the general way of distributing:
7866 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7867 if (code
== XOR
&& inner_code
== IOR
)
7870 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7873 /* We may be able to continuing distributing the result, so call
7874 ourselves recursively on the inner operation before forming the
7875 outer operation, which we return. */
7876 return gen_binary (inner_code
, GET_MODE (x
),
7877 apply_distributive_law (tem
), other
);
7880 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7883 Return an equivalent form, if different from X. Otherwise, return X. If
7884 X is zero, we are to always construct the equivalent form. */
7887 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7888 unsigned HOST_WIDE_INT constop
)
7890 unsigned HOST_WIDE_INT nonzero
;
7893 /* Simplify VAROP knowing that we will be only looking at some of the
7896 Note by passing in CONSTOP, we guarantee that the bits not set in
7897 CONSTOP are not significant and will never be examined. We must
7898 ensure that is the case by explicitly masking out those bits
7899 before returning. */
7900 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7902 /* If VAROP is a CLOBBER, we will fail so return it. */
7903 if (GET_CODE (varop
) == CLOBBER
)
7906 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7907 to VAROP and return the new constant. */
7908 if (GET_CODE (varop
) == CONST_INT
)
7909 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7911 /* See what bits may be nonzero in VAROP. Unlike the general case of
7912 a call to nonzero_bits, here we don't care about bits outside
7915 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7917 /* Turn off all bits in the constant that are known to already be zero.
7918 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7919 which is tested below. */
7923 /* If we don't have any bits left, return zero. */
7927 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7928 a power of two, we can replace this with an ASHIFT. */
7929 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7930 && (i
= exact_log2 (constop
)) >= 0)
7931 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7933 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7934 or XOR, then try to apply the distributive law. This may eliminate
7935 operations if either branch can be simplified because of the AND.
7936 It may also make some cases more complex, but those cases probably
7937 won't match a pattern either with or without this. */
7939 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7943 apply_distributive_law
7944 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7945 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7946 XEXP (varop
, 0), constop
),
7947 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7948 XEXP (varop
, 1), constop
))));
7950 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7951 the AND and see if one of the operands simplifies to zero. If so, we
7952 may eliminate it. */
7954 if (GET_CODE (varop
) == PLUS
7955 && exact_log2 (constop
+ 1) >= 0)
7959 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7960 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7961 if (o0
== const0_rtx
)
7963 if (o1
== const0_rtx
)
7967 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7968 if we already had one (just check for the simplest cases). */
7969 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7970 && GET_MODE (XEXP (x
, 0)) == mode
7971 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7972 varop
= XEXP (x
, 0);
7974 varop
= gen_lowpart (mode
, varop
);
7976 /* If we can't make the SUBREG, try to return what we were given. */
7977 if (GET_CODE (varop
) == CLOBBER
)
7978 return x
? x
: varop
;
7980 /* If we are only masking insignificant bits, return VAROP. */
7981 if (constop
== nonzero
)
7985 /* Otherwise, return an AND. */
7986 constop
= trunc_int_for_mode (constop
, mode
);
7987 /* See how much, if any, of X we can use. */
7988 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7989 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7993 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7994 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7995 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7997 SUBST (XEXP (x
, 0), varop
);
8004 /* Given a REG, X, compute which bits in X can be nonzero.
8005 We don't care about bits outside of those defined in MODE.
8007 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8008 a shift, AND, or zero_extract, we can do better. */
8011 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8012 rtx known_x ATTRIBUTE_UNUSED
,
8013 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8014 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8015 unsigned HOST_WIDE_INT
*nonzero
)
8019 /* If X is a register whose nonzero bits value is current, use it.
8020 Otherwise, if X is a register whose value we can find, use that
8021 value. Otherwise, use the previously-computed global nonzero bits
8022 for this register. */
8024 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8025 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8026 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8027 && GET_MODE_CLASS (mode
) == MODE_INT
))
8028 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8029 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8030 && REG_N_SETS (REGNO (x
)) == 1
8031 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8033 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8035 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8039 tem
= get_last_value (x
);
8043 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8044 /* If X is narrower than MODE and TEM is a non-negative
8045 constant that would appear negative in the mode of X,
8046 sign-extend it for use in reg_nonzero_bits because some
8047 machines (maybe most) will actually do the sign-extension
8048 and this is the conservative approach.
8050 ??? For 2.5, try to tighten up the MD files in this regard
8051 instead of this kludge. */
8053 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8054 && GET_CODE (tem
) == CONST_INT
8056 && 0 != (INTVAL (tem
)
8057 & ((HOST_WIDE_INT
) 1
8058 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8059 tem
= GEN_INT (INTVAL (tem
)
8060 | ((HOST_WIDE_INT
) (-1)
8061 << GET_MODE_BITSIZE (GET_MODE (x
))));
8065 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8067 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8069 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8070 /* We don't know anything about the upper bits. */
8071 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8078 /* Return the number of bits at the high-order end of X that are known to
8079 be equal to the sign bit. X will be used in mode MODE; if MODE is
8080 VOIDmode, X will be used in its own mode. The returned value will always
8081 be between 1 and the number of bits in MODE. */
8084 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8085 rtx known_x ATTRIBUTE_UNUSED
,
8086 enum machine_mode known_mode
8088 unsigned int known_ret ATTRIBUTE_UNUSED
,
8089 unsigned int *result
)
8093 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8094 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8095 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8096 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8097 && REG_N_SETS (REGNO (x
)) == 1
8098 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8100 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8102 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8106 tem
= get_last_value (x
);
8110 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8111 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8112 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8117 /* Return the number of "extended" bits there are in X, when interpreted
8118 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8119 unsigned quantities, this is the number of high-order zero bits.
8120 For signed quantities, this is the number of copies of the sign bit
8121 minus 1. In both case, this function returns the number of "spare"
8122 bits. For example, if two quantities for which this function returns
8123 at least 1 are added, the addition is known not to overflow.
8125 This function will always return 0 unless called during combine, which
8126 implies that it must be called from a define_split. */
8129 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8131 if (nonzero_sign_valid
== 0)
8135 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8136 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8137 - floor_log2 (nonzero_bits (x
, mode
)))
8139 : num_sign_bit_copies (x
, mode
) - 1);
8142 /* This function is called from `simplify_shift_const' to merge two
8143 outer operations. Specifically, we have already found that we need
8144 to perform operation *POP0 with constant *PCONST0 at the outermost
8145 position. We would now like to also perform OP1 with constant CONST1
8146 (with *POP0 being done last).
8148 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8149 the resulting operation. *PCOMP_P is set to 1 if we would need to
8150 complement the innermost operand, otherwise it is unchanged.
8152 MODE is the mode in which the operation will be done. No bits outside
8153 the width of this mode matter. It is assumed that the width of this mode
8154 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8156 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8157 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8158 result is simply *PCONST0.
8160 If the resulting operation cannot be expressed as one operation, we
8161 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8164 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8166 enum rtx_code op0
= *pop0
;
8167 HOST_WIDE_INT const0
= *pconst0
;
8169 const0
&= GET_MODE_MASK (mode
);
8170 const1
&= GET_MODE_MASK (mode
);
8172 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8176 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8179 if (op1
== NIL
|| op0
== SET
)
8182 else if (op0
== NIL
)
8183 op0
= op1
, const0
= const1
;
8185 else if (op0
== op1
)
8209 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8210 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8213 /* If the two constants aren't the same, we can't do anything. The
8214 remaining six cases can all be done. */
8215 else if (const0
!= const1
)
8223 /* (a & b) | b == b */
8225 else /* op1 == XOR */
8226 /* (a ^ b) | b == a | b */
8232 /* (a & b) ^ b == (~a) & b */
8233 op0
= AND
, *pcomp_p
= 1;
8234 else /* op1 == IOR */
8235 /* (a | b) ^ b == a & ~b */
8236 op0
= AND
, const0
= ~const0
;
8241 /* (a | b) & b == b */
8243 else /* op1 == XOR */
8244 /* (a ^ b) & b) == (~a) & b */
8251 /* Check for NO-OP cases. */
8252 const0
&= GET_MODE_MASK (mode
);
8254 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8256 else if (const0
== 0 && op0
== AND
)
8258 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8262 /* ??? Slightly redundant with the above mask, but not entirely.
8263 Moving this above means we'd have to sign-extend the mode mask
8264 for the final test. */
8265 const0
= trunc_int_for_mode (const0
, mode
);
8273 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8274 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8275 that we started with.
8277 The shift is normally computed in the widest mode we find in VAROP, as
8278 long as it isn't a different number of words than RESULT_MODE. Exceptions
8279 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8282 simplify_shift_const (rtx x
, enum rtx_code code
,
8283 enum machine_mode result_mode
, rtx varop
,
8286 enum rtx_code orig_code
= code
;
8289 enum machine_mode mode
= result_mode
;
8290 enum machine_mode shift_mode
, tmode
;
8291 unsigned int mode_words
8292 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8293 /* We form (outer_op (code varop count) (outer_const)). */
8294 enum rtx_code outer_op
= NIL
;
8295 HOST_WIDE_INT outer_const
= 0;
8297 int complement_p
= 0;
8300 /* Make sure and truncate the "natural" shift on the way in. We don't
8301 want to do this inside the loop as it makes it more difficult to
8303 if (SHIFT_COUNT_TRUNCATED
)
8304 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8306 /* If we were given an invalid count, don't do anything except exactly
8307 what was requested. */
8309 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8314 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8319 /* Unless one of the branches of the `if' in this loop does a `continue',
8320 we will `break' the loop after the `if'. */
8324 /* If we have an operand of (clobber (const_int 0)), just return that
8326 if (GET_CODE (varop
) == CLOBBER
)
8329 /* If we discovered we had to complement VAROP, leave. Making a NOT
8330 here would cause an infinite loop. */
8334 /* Convert ROTATERT to ROTATE. */
8335 if (code
== ROTATERT
)
8337 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8339 if (VECTOR_MODE_P (result_mode
))
8340 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8342 count
= bitsize
- count
;
8345 /* We need to determine what mode we will do the shift in. If the
8346 shift is a right shift or a ROTATE, we must always do it in the mode
8347 it was originally done in. Otherwise, we can do it in MODE, the
8348 widest mode encountered. */
8350 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8351 ? result_mode
: mode
);
8353 /* Handle cases where the count is greater than the size of the mode
8354 minus 1. For ASHIFT, use the size minus one as the count (this can
8355 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8356 take the count modulo the size. For other shifts, the result is
8359 Since these shifts are being produced by the compiler by combining
8360 multiple operations, each of which are defined, we know what the
8361 result is supposed to be. */
8363 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8365 if (code
== ASHIFTRT
)
8366 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8367 else if (code
== ROTATE
|| code
== ROTATERT
)
8368 count
%= GET_MODE_BITSIZE (shift_mode
);
8371 /* We can't simply return zero because there may be an
8379 /* An arithmetic right shift of a quantity known to be -1 or 0
8381 if (code
== ASHIFTRT
8382 && (num_sign_bit_copies (varop
, shift_mode
)
8383 == GET_MODE_BITSIZE (shift_mode
)))
8389 /* If we are doing an arithmetic right shift and discarding all but
8390 the sign bit copies, this is equivalent to doing a shift by the
8391 bitsize minus one. Convert it into that shift because it will often
8392 allow other simplifications. */
8394 if (code
== ASHIFTRT
8395 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8396 >= GET_MODE_BITSIZE (shift_mode
)))
8397 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8399 /* We simplify the tests below and elsewhere by converting
8400 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8401 `make_compound_operation' will convert it to an ASHIFTRT for
8402 those machines (such as VAX) that don't have an LSHIFTRT. */
8403 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8405 && ((nonzero_bits (varop
, shift_mode
)
8406 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8410 if (code
== LSHIFTRT
8411 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8412 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8415 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8416 && !((nonzero_bits (varop
, shift_mode
) << count
)
8417 & GET_MODE_MASK (shift_mode
)))
8420 switch (GET_CODE (varop
))
8426 new = expand_compound_operation (varop
);
8435 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8436 minus the width of a smaller mode, we can do this with a
8437 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8438 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8439 && ! mode_dependent_address_p (XEXP (varop
, 0))
8440 && ! MEM_VOLATILE_P (varop
)
8441 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8442 MODE_INT
, 1)) != BLKmode
)
8444 new = adjust_address_nv (varop
, tmode
,
8445 BYTES_BIG_ENDIAN
? 0
8446 : count
/ BITS_PER_UNIT
);
8448 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8449 : ZERO_EXTEND
, mode
, new);
8456 /* Similar to the case above, except that we can only do this if
8457 the resulting mode is the same as that of the underlying
8458 MEM and adjust the address depending on the *bits* endianness
8459 because of the way that bit-field extract insns are defined. */
8460 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8461 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8462 MODE_INT
, 1)) != BLKmode
8463 && tmode
== GET_MODE (XEXP (varop
, 0)))
8465 if (BITS_BIG_ENDIAN
)
8466 new = XEXP (varop
, 0);
8469 new = copy_rtx (XEXP (varop
, 0));
8470 SUBST (XEXP (new, 0),
8471 plus_constant (XEXP (new, 0),
8472 count
/ BITS_PER_UNIT
));
8475 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8476 : ZERO_EXTEND
, mode
, new);
8483 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8484 the same number of words as what we've seen so far. Then store
8485 the widest mode in MODE. */
8486 if (subreg_lowpart_p (varop
)
8487 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8488 > GET_MODE_SIZE (GET_MODE (varop
)))
8489 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8490 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8493 varop
= SUBREG_REG (varop
);
8494 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8495 mode
= GET_MODE (varop
);
8501 /* Some machines use MULT instead of ASHIFT because MULT
8502 is cheaper. But it is still better on those machines to
8503 merge two shifts into one. */
8504 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8505 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8508 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8509 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8515 /* Similar, for when divides are cheaper. */
8516 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8517 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8520 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8521 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8527 /* If we are extracting just the sign bit of an arithmetic
8528 right shift, that shift is not needed. However, the sign
8529 bit of a wider mode may be different from what would be
8530 interpreted as the sign bit in a narrower mode, so, if
8531 the result is narrower, don't discard the shift. */
8532 if (code
== LSHIFTRT
8533 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8534 && (GET_MODE_BITSIZE (result_mode
)
8535 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8537 varop
= XEXP (varop
, 0);
8541 /* ... fall through ... */
8546 /* Here we have two nested shifts. The result is usually the
8547 AND of a new shift with a mask. We compute the result below. */
8548 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8549 && INTVAL (XEXP (varop
, 1)) >= 0
8550 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8551 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8552 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8554 enum rtx_code first_code
= GET_CODE (varop
);
8555 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8556 unsigned HOST_WIDE_INT mask
;
8559 /* We have one common special case. We can't do any merging if
8560 the inner code is an ASHIFTRT of a smaller mode. However, if
8561 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8562 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8563 we can convert it to
8564 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8565 This simplifies certain SIGN_EXTEND operations. */
8566 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8567 && count
== (unsigned int)
8568 (GET_MODE_BITSIZE (result_mode
)
8569 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8571 /* C3 has the low-order C1 bits zero. */
8573 mask
= (GET_MODE_MASK (mode
)
8574 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8576 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8577 XEXP (varop
, 0), mask
);
8578 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8580 count
= first_count
;
8585 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8586 than C1 high-order bits equal to the sign bit, we can convert
8587 this to either an ASHIFT or an ASHIFTRT depending on the
8590 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8592 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8593 && GET_MODE (varop
) == shift_mode
8594 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8597 varop
= XEXP (varop
, 0);
8599 signed_count
= count
- first_count
;
8600 if (signed_count
< 0)
8601 count
= -signed_count
, code
= ASHIFT
;
8603 count
= signed_count
;
8608 /* There are some cases we can't do. If CODE is ASHIFTRT,
8609 we can only do this if FIRST_CODE is also ASHIFTRT.
8611 We can't do the case when CODE is ROTATE and FIRST_CODE is
8614 If the mode of this shift is not the mode of the outer shift,
8615 we can't do this if either shift is a right shift or ROTATE.
8617 Finally, we can't do any of these if the mode is too wide
8618 unless the codes are the same.
8620 Handle the case where the shift codes are the same
8623 if (code
== first_code
)
8625 if (GET_MODE (varop
) != result_mode
8626 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8630 count
+= first_count
;
8631 varop
= XEXP (varop
, 0);
8635 if (code
== ASHIFTRT
8636 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8637 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8638 || (GET_MODE (varop
) != result_mode
8639 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8640 || first_code
== ROTATE
8641 || code
== ROTATE
)))
8644 /* To compute the mask to apply after the shift, shift the
8645 nonzero bits of the inner shift the same way the
8646 outer shift will. */
8648 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8651 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8654 /* Give up if we can't compute an outer operation to use. */
8656 || GET_CODE (mask_rtx
) != CONST_INT
8657 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8659 result_mode
, &complement_p
))
8662 /* If the shifts are in the same direction, we add the
8663 counts. Otherwise, we subtract them. */
8664 signed_count
= count
;
8665 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8666 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8667 signed_count
+= first_count
;
8669 signed_count
-= first_count
;
8671 /* If COUNT is positive, the new shift is usually CODE,
8672 except for the two exceptions below, in which case it is
8673 FIRST_CODE. If the count is negative, FIRST_CODE should
8675 if (signed_count
> 0
8676 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8677 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8678 code
= first_code
, count
= signed_count
;
8679 else if (signed_count
< 0)
8680 code
= first_code
, count
= -signed_count
;
8682 count
= signed_count
;
8684 varop
= XEXP (varop
, 0);
8688 /* If we have (A << B << C) for any shift, we can convert this to
8689 (A << C << B). This wins if A is a constant. Only try this if
8690 B is not a constant. */
8692 else if (GET_CODE (varop
) == code
8693 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8695 = simplify_binary_operation (code
, mode
,
8699 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
8706 /* Make this fit the case below. */
8707 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
8708 GEN_INT (GET_MODE_MASK (mode
)));
8714 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8715 with C the size of VAROP - 1 and the shift is logical if
8716 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8717 we have an (le X 0) operation. If we have an arithmetic shift
8718 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8719 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8721 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8722 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8723 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8724 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8725 && count
== (unsigned int)
8726 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8727 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8730 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
8733 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8734 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8739 /* If we have (shift (logical)), move the logical to the outside
8740 to allow it to possibly combine with another logical and the
8741 shift to combine with another shift. This also canonicalizes to
8742 what a ZERO_EXTRACT looks like. Also, some machines have
8743 (and (shift)) insns. */
8745 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8746 /* We can't do this if we have (ashiftrt (xor)) and the
8747 constant has its sign bit set in shift_mode. */
8748 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8749 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8751 && (new = simplify_binary_operation (code
, result_mode
,
8753 GEN_INT (count
))) != 0
8754 && GET_CODE (new) == CONST_INT
8755 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8756 INTVAL (new), result_mode
, &complement_p
))
8758 varop
= XEXP (varop
, 0);
8762 /* If we can't do that, try to simplify the shift in each arm of the
8763 logical expression, make a new logical expression, and apply
8764 the inverse distributive law. This also can't be done
8765 for some (ashiftrt (xor)). */
8766 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8767 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8768 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8771 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8772 XEXP (varop
, 0), count
);
8773 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8774 XEXP (varop
, 1), count
);
8776 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
8777 varop
= apply_distributive_law (varop
);
8785 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8786 says that the sign bit can be tested, FOO has mode MODE, C is
8787 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8788 that may be nonzero. */
8789 if (code
== LSHIFTRT
8790 && XEXP (varop
, 1) == const0_rtx
8791 && GET_MODE (XEXP (varop
, 0)) == result_mode
8792 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8793 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8794 && ((STORE_FLAG_VALUE
8795 & ((HOST_WIDE_INT
) 1
8796 < (GET_MODE_BITSIZE (result_mode
) - 1))))
8797 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8798 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8799 (HOST_WIDE_INT
) 1, result_mode
,
8802 varop
= XEXP (varop
, 0);
8809 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8810 than the number of bits in the mode is equivalent to A. */
8811 if (code
== LSHIFTRT
8812 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8813 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
8815 varop
= XEXP (varop
, 0);
8820 /* NEG commutes with ASHIFT since it is multiplication. Move the
8821 NEG outside to allow shifts to combine. */
8823 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
8824 (HOST_WIDE_INT
) 0, result_mode
,
8827 varop
= XEXP (varop
, 0);
8833 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8834 is one less than the number of bits in the mode is
8835 equivalent to (xor A 1). */
8836 if (code
== LSHIFTRT
8837 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8838 && XEXP (varop
, 1) == constm1_rtx
8839 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8840 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8841 (HOST_WIDE_INT
) 1, result_mode
,
8845 varop
= XEXP (varop
, 0);
8849 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8850 that might be nonzero in BAR are those being shifted out and those
8851 bits are known zero in FOO, we can replace the PLUS with FOO.
8852 Similarly in the other operand order. This code occurs when
8853 we are computing the size of a variable-size array. */
8855 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8856 && count
< HOST_BITS_PER_WIDE_INT
8857 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
8858 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
8859 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
8861 varop
= XEXP (varop
, 0);
8864 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8865 && count
< HOST_BITS_PER_WIDE_INT
8866 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8867 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8869 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
8870 & nonzero_bits (XEXP (varop
, 1),
8873 varop
= XEXP (varop
, 1);
8877 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8879 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
8880 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
8882 GEN_INT (count
))) != 0
8883 && GET_CODE (new) == CONST_INT
8884 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
8885 INTVAL (new), result_mode
, &complement_p
))
8887 varop
= XEXP (varop
, 0);
8893 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8894 with C the size of VAROP - 1 and the shift is logical if
8895 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8896 we have a (gt X 0) operation. If the shift is arithmetic with
8897 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8898 we have a (neg (gt X 0)) operation. */
8900 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8901 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
8902 && count
== (unsigned int)
8903 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8904 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8905 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
8906 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
8908 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8911 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
8914 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8915 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8922 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8923 if the truncate does not affect the value. */
8924 if (code
== LSHIFTRT
8925 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
8926 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
8927 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
8928 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
8929 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
8931 rtx varop_inner
= XEXP (varop
, 0);
8934 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
8935 XEXP (varop_inner
, 0),
8937 (count
+ INTVAL (XEXP (varop_inner
, 1))));
8938 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
8951 /* We need to determine what mode to do the shift in. If the shift is
8952 a right shift or ROTATE, we must always do it in the mode it was
8953 originally done in. Otherwise, we can do it in MODE, the widest mode
8954 encountered. The code we care about is that of the shift that will
8955 actually be done, not the shift that was originally requested. */
8957 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8958 ? result_mode
: mode
);
8960 /* We have now finished analyzing the shift. The result should be
8961 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8962 OUTER_OP is non-NIL, it is an operation that needs to be applied
8963 to the result of the shift. OUTER_CONST is the relevant constant,
8964 but we must turn off all bits turned off in the shift.
8966 If we were passed a value for X, see if we can use any pieces of
8967 it. If not, make new rtx. */
8969 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
8970 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8971 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
8972 const_rtx
= XEXP (x
, 1);
8974 const_rtx
= GEN_INT (count
);
8976 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8977 && GET_MODE (XEXP (x
, 0)) == shift_mode
8978 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8979 varop
= XEXP (x
, 0);
8980 else if (GET_MODE (varop
) != shift_mode
)
8981 varop
= gen_lowpart (shift_mode
, varop
);
8983 /* If we can't make the SUBREG, try to return what we were given. */
8984 if (GET_CODE (varop
) == CLOBBER
)
8985 return x
? x
: varop
;
8987 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
8991 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
8993 /* If we have an outer operation and we just made a shift, it is
8994 possible that we could have simplified the shift were it not
8995 for the outer operation. So try to do the simplification
8998 if (outer_op
!= NIL
&& GET_CODE (x
) == code
8999 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9000 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9001 INTVAL (XEXP (x
, 1)));
9003 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9004 turn off all the bits that the shift would have turned off. */
9005 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9006 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9007 GET_MODE_MASK (result_mode
) >> orig_count
);
9009 /* Do the remainder of the processing in RESULT_MODE. */
9010 x
= gen_lowpart (result_mode
, x
);
9012 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9015 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9017 if (outer_op
!= NIL
)
9019 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9020 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9022 if (outer_op
== AND
)
9023 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9024 else if (outer_op
== SET
)
9025 /* This means that we have determined that the result is
9026 equivalent to a constant. This should be rare. */
9027 x
= GEN_INT (outer_const
);
9028 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9029 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9031 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9037 /* Like recog, but we receive the address of a pointer to a new pattern.
9038 We try to match the rtx that the pointer points to.
9039 If that fails, we may try to modify or replace the pattern,
9040 storing the replacement into the same pointer object.
9042 Modifications include deletion or addition of CLOBBERs.
9044 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9045 the CLOBBERs are placed.
9047 The value is the final insn code from the pattern ultimately matched,
9051 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9054 int insn_code_number
;
9055 int num_clobbers_to_add
= 0;
9058 rtx old_notes
, old_pat
;
9060 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9061 we use to indicate that something didn't match. If we find such a
9062 thing, force rejection. */
9063 if (GET_CODE (pat
) == PARALLEL
)
9064 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9065 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9066 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9069 old_pat
= PATTERN (insn
);
9070 old_notes
= REG_NOTES (insn
);
9071 PATTERN (insn
) = pat
;
9072 REG_NOTES (insn
) = 0;
9074 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9076 /* If it isn't, there is the possibility that we previously had an insn
9077 that clobbered some register as a side effect, but the combined
9078 insn doesn't need to do that. So try once more without the clobbers
9079 unless this represents an ASM insn. */
9081 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9082 && GET_CODE (pat
) == PARALLEL
)
9086 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9087 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9090 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9094 SUBST_INT (XVECLEN (pat
, 0), pos
);
9097 pat
= XVECEXP (pat
, 0, 0);
9099 PATTERN (insn
) = pat
;
9100 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9102 PATTERN (insn
) = old_pat
;
9103 REG_NOTES (insn
) = old_notes
;
9105 /* Recognize all noop sets, these will be killed by followup pass. */
9106 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9107 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9109 /* If we had any clobbers to add, make a new pattern than contains
9110 them. Then check to make sure that all of them are dead. */
9111 if (num_clobbers_to_add
)
9113 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9114 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9116 + num_clobbers_to_add
)
9117 : num_clobbers_to_add
+ 1));
9119 if (GET_CODE (pat
) == PARALLEL
)
9120 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9121 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9123 XVECEXP (newpat
, 0, 0) = pat
;
9125 add_clobbers (newpat
, insn_code_number
);
9127 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9128 i
< XVECLEN (newpat
, 0); i
++)
9130 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9131 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9133 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9134 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9142 return insn_code_number
;
9145 /* Like gen_lowpart_general but for use by combine. In combine it
9146 is not possible to create any new pseudoregs. However, it is
9147 safe to create invalid memory addresses, because combine will
9148 try to recognize them and all they will do is make the combine
9151 If for some reason this cannot do its job, an rtx
9152 (clobber (const_int 0)) is returned.
9153 An insn containing that will not be recognized. */
9156 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9160 if (GET_MODE (x
) == mode
)
9163 /* Return identity if this is a CONST or symbolic
9166 && (GET_CODE (x
) == CONST
9167 || GET_CODE (x
) == SYMBOL_REF
9168 || GET_CODE (x
) == LABEL_REF
))
9171 /* We can only support MODE being wider than a word if X is a
9172 constant integer or has a mode the same size. */
9174 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9175 && ! ((GET_MODE (x
) == VOIDmode
9176 && (GET_CODE (x
) == CONST_INT
9177 || GET_CODE (x
) == CONST_DOUBLE
))
9178 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9179 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9181 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9182 won't know what to do. So we will strip off the SUBREG here and
9183 process normally. */
9184 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9187 if (GET_MODE (x
) == mode
)
9191 result
= gen_lowpart_common (mode
, x
);
9192 #ifdef CANNOT_CHANGE_MODE_CLASS
9194 && GET_CODE (result
) == SUBREG
9195 && GET_CODE (SUBREG_REG (result
)) == REG
9196 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
9197 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
9199 + GET_MODE (result
));
9205 if (GET_CODE (x
) == MEM
)
9209 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9211 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9212 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9214 /* If we want to refer to something bigger than the original memref,
9215 generate a paradoxical subreg instead. That will force a reload
9216 of the original memref X. */
9217 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9218 return gen_rtx_SUBREG (mode
, x
, 0);
9220 if (WORDS_BIG_ENDIAN
)
9221 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9222 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9224 if (BYTES_BIG_ENDIAN
)
9226 /* Adjust the address so that the address-after-the-data is
9228 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9229 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9232 return adjust_address_nv (x
, mode
, offset
);
9235 /* If X is a comparison operator, rewrite it in a new mode. This
9236 probably won't match, but may allow further simplifications. */
9237 else if (COMPARISON_P (x
))
9238 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9240 /* If we couldn't simplify X any other way, just enclose it in a
9241 SUBREG. Normally, this SUBREG won't match, but some patterns may
9242 include an explicit SUBREG or we may simplify it further in combine. */
9247 enum machine_mode sub_mode
= GET_MODE (x
);
9249 offset
= subreg_lowpart_offset (mode
, sub_mode
);
9250 if (sub_mode
== VOIDmode
)
9252 sub_mode
= int_mode_for_mode (mode
);
9253 x
= gen_lowpart_common (sub_mode
, x
);
9255 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
9257 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
9260 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9264 /* These routines make binary and unary operations by first seeing if they
9265 fold; if not, a new expression is allocated. */
9268 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
9273 if (GET_CODE (op0
) == CLOBBER
)
9275 else if (GET_CODE (op1
) == CLOBBER
)
9278 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9279 && swap_commutative_operands_p (op0
, op1
))
9280 tem
= op0
, op0
= op1
, op1
= tem
;
9282 if (GET_RTX_CLASS (code
) == RTX_COMPARE
9283 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
9285 enum machine_mode op_mode
= GET_MODE (op0
);
9287 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9288 just (REL_OP X Y). */
9289 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9291 op1
= XEXP (op0
, 1);
9292 op0
= XEXP (op0
, 0);
9293 op_mode
= GET_MODE (op0
);
9296 if (op_mode
== VOIDmode
)
9297 op_mode
= GET_MODE (op1
);
9298 result
= simplify_relational_operation (code
, mode
, op_mode
, op0
, op1
);
9301 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9306 /* Put complex operands first and constants second. */
9307 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9308 && swap_commutative_operands_p (op0
, op1
))
9309 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9311 /* If we are turning off bits already known off in OP0, we need not do
9313 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9314 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9315 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9318 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9321 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9322 comparison code that will be tested.
9324 The result is a possibly different comparison code to use. *POP0 and
9325 *POP1 may be updated.
9327 It is possible that we might detect that a comparison is either always
9328 true or always false. However, we do not perform general constant
9329 folding in combine, so this knowledge isn't useful. Such tautologies
9330 should have been detected earlier. Hence we ignore all such cases. */
9332 static enum rtx_code
9333 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9339 enum machine_mode mode
, tmode
;
9341 /* Try a few ways of applying the same transformation to both operands. */
9344 #ifndef WORD_REGISTER_OPERATIONS
9345 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9346 so check specially. */
9347 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9348 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9349 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9350 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9351 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9352 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9353 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9354 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9355 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9356 && XEXP (op0
, 1) == XEXP (op1
, 1)
9357 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9358 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9359 && (INTVAL (XEXP (op0
, 1))
9360 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9362 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9364 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9365 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9369 /* If both operands are the same constant shift, see if we can ignore the
9370 shift. We can if the shift is a rotate or if the bits shifted out of
9371 this shift are known to be zero for both inputs and if the type of
9372 comparison is compatible with the shift. */
9373 if (GET_CODE (op0
) == GET_CODE (op1
)
9374 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9375 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9376 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9377 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9378 || (GET_CODE (op0
) == ASHIFTRT
9379 && (code
!= GTU
&& code
!= LTU
9380 && code
!= GEU
&& code
!= LEU
)))
9381 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9382 && INTVAL (XEXP (op0
, 1)) >= 0
9383 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9384 && XEXP (op0
, 1) == XEXP (op1
, 1))
9386 enum machine_mode mode
= GET_MODE (op0
);
9387 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9388 int shift_count
= INTVAL (XEXP (op0
, 1));
9390 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9391 mask
&= (mask
>> shift_count
) << shift_count
;
9392 else if (GET_CODE (op0
) == ASHIFT
)
9393 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9395 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9396 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9397 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9402 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9403 SUBREGs are of the same mode, and, in both cases, the AND would
9404 be redundant if the comparison was done in the narrower mode,
9405 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9406 and the operand's possibly nonzero bits are 0xffffff01; in that case
9407 if we only care about QImode, we don't need the AND). This case
9408 occurs if the output mode of an scc insn is not SImode and
9409 STORE_FLAG_VALUE == 1 (e.g., the 386).
9411 Similarly, check for a case where the AND's are ZERO_EXTEND
9412 operations from some narrower mode even though a SUBREG is not
9415 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9416 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9417 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9419 rtx inner_op0
= XEXP (op0
, 0);
9420 rtx inner_op1
= XEXP (op1
, 0);
9421 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9422 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9425 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9426 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9427 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9428 && (GET_MODE (SUBREG_REG (inner_op0
))
9429 == GET_MODE (SUBREG_REG (inner_op1
)))
9430 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9431 <= HOST_BITS_PER_WIDE_INT
)
9432 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9433 GET_MODE (SUBREG_REG (inner_op0
)))))
9434 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9435 GET_MODE (SUBREG_REG (inner_op1
))))))
9437 op0
= SUBREG_REG (inner_op0
);
9438 op1
= SUBREG_REG (inner_op1
);
9440 /* The resulting comparison is always unsigned since we masked
9441 off the original sign bit. */
9442 code
= unsigned_condition (code
);
9448 for (tmode
= GET_CLASS_NARROWEST_MODE
9449 (GET_MODE_CLASS (GET_MODE (op0
)));
9450 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9451 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9453 op0
= gen_lowpart (tmode
, inner_op0
);
9454 op1
= gen_lowpart (tmode
, inner_op1
);
9455 code
= unsigned_condition (code
);
9464 /* If both operands are NOT, we can strip off the outer operation
9465 and adjust the comparison code for swapped operands; similarly for
9466 NEG, except that this must be an equality comparison. */
9467 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9468 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9469 && (code
== EQ
|| code
== NE
)))
9470 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9476 /* If the first operand is a constant, swap the operands and adjust the
9477 comparison code appropriately, but don't do this if the second operand
9478 is already a constant integer. */
9479 if (swap_commutative_operands_p (op0
, op1
))
9481 tem
= op0
, op0
= op1
, op1
= tem
;
9482 code
= swap_condition (code
);
9485 /* We now enter a loop during which we will try to simplify the comparison.
9486 For the most part, we only are concerned with comparisons with zero,
9487 but some things may really be comparisons with zero but not start
9488 out looking that way. */
9490 while (GET_CODE (op1
) == CONST_INT
)
9492 enum machine_mode mode
= GET_MODE (op0
);
9493 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9494 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9495 int equality_comparison_p
;
9496 int sign_bit_comparison_p
;
9497 int unsigned_comparison_p
;
9498 HOST_WIDE_INT const_op
;
9500 /* We only want to handle integral modes. This catches VOIDmode,
9501 CCmode, and the floating-point modes. An exception is that we
9502 can handle VOIDmode if OP0 is a COMPARE or a comparison
9505 if (GET_MODE_CLASS (mode
) != MODE_INT
9506 && ! (mode
== VOIDmode
9507 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9510 /* Get the constant we are comparing against and turn off all bits
9511 not on in our mode. */
9512 const_op
= INTVAL (op1
);
9513 if (mode
!= VOIDmode
)
9514 const_op
= trunc_int_for_mode (const_op
, mode
);
9515 op1
= GEN_INT (const_op
);
9517 /* If we are comparing against a constant power of two and the value
9518 being compared can only have that single bit nonzero (e.g., it was
9519 `and'ed with that bit), we can replace this with a comparison
9522 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9523 || code
== LT
|| code
== LTU
)
9524 && mode_width
<= HOST_BITS_PER_WIDE_INT
9525 && exact_log2 (const_op
) >= 0
9526 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9528 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9529 op1
= const0_rtx
, const_op
= 0;
9532 /* Similarly, if we are comparing a value known to be either -1 or
9533 0 with -1, change it to the opposite comparison against zero. */
9536 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9537 || code
== GEU
|| code
== LTU
)
9538 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9540 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9541 op1
= const0_rtx
, const_op
= 0;
9544 /* Do some canonicalizations based on the comparison code. We prefer
9545 comparisons against zero and then prefer equality comparisons.
9546 If we can reduce the size of a constant, we will do that too. */
9551 /* < C is equivalent to <= (C - 1) */
9555 op1
= GEN_INT (const_op
);
9557 /* ... fall through to LE case below. */
9563 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9567 op1
= GEN_INT (const_op
);
9571 /* If we are doing a <= 0 comparison on a value known to have
9572 a zero sign bit, we can replace this with == 0. */
9573 else if (const_op
== 0
9574 && mode_width
<= HOST_BITS_PER_WIDE_INT
9575 && (nonzero_bits (op0
, mode
)
9576 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9581 /* >= C is equivalent to > (C - 1). */
9585 op1
= GEN_INT (const_op
);
9587 /* ... fall through to GT below. */
9593 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9597 op1
= GEN_INT (const_op
);
9601 /* If we are doing a > 0 comparison on a value known to have
9602 a zero sign bit, we can replace this with != 0. */
9603 else if (const_op
== 0
9604 && mode_width
<= HOST_BITS_PER_WIDE_INT
9605 && (nonzero_bits (op0
, mode
)
9606 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9611 /* < C is equivalent to <= (C - 1). */
9615 op1
= GEN_INT (const_op
);
9617 /* ... fall through ... */
9620 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9621 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9622 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9624 const_op
= 0, op1
= const0_rtx
;
9632 /* unsigned <= 0 is equivalent to == 0 */
9636 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9637 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9638 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9640 const_op
= 0, op1
= const0_rtx
;
9646 /* >= C is equivalent to < (C - 1). */
9650 op1
= GEN_INT (const_op
);
9652 /* ... fall through ... */
9655 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9656 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9657 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9659 const_op
= 0, op1
= const0_rtx
;
9667 /* unsigned > 0 is equivalent to != 0 */
9671 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9672 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9673 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9675 const_op
= 0, op1
= const0_rtx
;
9684 /* Compute some predicates to simplify code below. */
9686 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9687 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9688 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9691 /* If this is a sign bit comparison and we can do arithmetic in
9692 MODE, say that we will only be needing the sign bit of OP0. */
9693 if (sign_bit_comparison_p
9694 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9695 op0
= force_to_mode (op0
, mode
,
9697 << (GET_MODE_BITSIZE (mode
) - 1)),
9700 /* Now try cases based on the opcode of OP0. If none of the cases
9701 does a "continue", we exit this loop immediately after the
9704 switch (GET_CODE (op0
))
9707 /* If we are extracting a single bit from a variable position in
9708 a constant that has only a single bit set and are comparing it
9709 with zero, we can convert this into an equality comparison
9710 between the position and the location of the single bit. */
9711 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9712 have already reduced the shift count modulo the word size. */
9713 if (!SHIFT_COUNT_TRUNCATED
9714 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
9715 && XEXP (op0
, 1) == const1_rtx
9716 && equality_comparison_p
&& const_op
== 0
9717 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9719 if (BITS_BIG_ENDIAN
)
9721 enum machine_mode new_mode
9722 = mode_for_extraction (EP_extzv
, 1);
9723 if (new_mode
== MAX_MACHINE_MODE
)
9724 i
= BITS_PER_WORD
- 1 - i
;
9728 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9732 op0
= XEXP (op0
, 2);
9736 /* Result is nonzero iff shift count is equal to I. */
9737 code
= reverse_condition (code
);
9741 /* ... fall through ... */
9744 tem
= expand_compound_operation (op0
);
9753 /* If testing for equality, we can take the NOT of the constant. */
9754 if (equality_comparison_p
9755 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9757 op0
= XEXP (op0
, 0);
9762 /* If just looking at the sign bit, reverse the sense of the
9764 if (sign_bit_comparison_p
)
9766 op0
= XEXP (op0
, 0);
9767 code
= (code
== GE
? LT
: GE
);
9773 /* If testing for equality, we can take the NEG of the constant. */
9774 if (equality_comparison_p
9775 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9777 op0
= XEXP (op0
, 0);
9782 /* The remaining cases only apply to comparisons with zero. */
9786 /* When X is ABS or is known positive,
9787 (neg X) is < 0 if and only if X != 0. */
9789 if (sign_bit_comparison_p
9790 && (GET_CODE (XEXP (op0
, 0)) == ABS
9791 || (mode_width
<= HOST_BITS_PER_WIDE_INT
9792 && (nonzero_bits (XEXP (op0
, 0), mode
)
9793 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
9795 op0
= XEXP (op0
, 0);
9796 code
= (code
== LT
? NE
: EQ
);
9800 /* If we have NEG of something whose two high-order bits are the
9801 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9802 if (num_sign_bit_copies (op0
, mode
) >= 2)
9804 op0
= XEXP (op0
, 0);
9805 code
= swap_condition (code
);
9811 /* If we are testing equality and our count is a constant, we
9812 can perform the inverse operation on our RHS. */
9813 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9814 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
9815 op1
, XEXP (op0
, 1))) != 0)
9817 op0
= XEXP (op0
, 0);
9822 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9823 a particular bit. Convert it to an AND of a constant of that
9824 bit. This will be converted into a ZERO_EXTRACT. */
9825 if (const_op
== 0 && sign_bit_comparison_p
9826 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9827 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
9829 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9832 - INTVAL (XEXP (op0
, 1)))));
9833 code
= (code
== LT
? NE
: EQ
);
9840 /* ABS is ignorable inside an equality comparison with zero. */
9841 if (const_op
== 0 && equality_comparison_p
)
9843 op0
= XEXP (op0
, 0);
9849 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9850 to (compare FOO CONST) if CONST fits in FOO's mode and we
9851 are either testing inequality or have an unsigned comparison
9852 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9853 if (! unsigned_comparison_p
9854 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
9855 <= HOST_BITS_PER_WIDE_INT
)
9856 && ((unsigned HOST_WIDE_INT
) const_op
9857 < (((unsigned HOST_WIDE_INT
) 1
9858 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
9860 op0
= XEXP (op0
, 0);
9866 /* Check for the case where we are comparing A - C1 with C2,
9867 both constants are smaller than 1/2 the maximum positive
9868 value in MODE, and the comparison is equality or unsigned.
9869 In that case, if A is either zero-extended to MODE or has
9870 sufficient sign bits so that the high-order bit in MODE
9871 is a copy of the sign in the inner mode, we can prove that it is
9872 safe to do the operation in the wider mode. This simplifies
9873 many range checks. */
9875 if (mode_width
<= HOST_BITS_PER_WIDE_INT
9876 && subreg_lowpart_p (op0
)
9877 && GET_CODE (SUBREG_REG (op0
)) == PLUS
9878 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
9879 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
9880 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
9881 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
9882 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
9883 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
9884 GET_MODE (SUBREG_REG (op0
)))
9885 & ~GET_MODE_MASK (mode
))
9886 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
9887 GET_MODE (SUBREG_REG (op0
)))
9889 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
9890 - GET_MODE_BITSIZE (mode
)))))
9892 op0
= SUBREG_REG (op0
);
9896 /* If the inner mode is narrower and we are extracting the low part,
9897 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9898 if (subreg_lowpart_p (op0
)
9899 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
9900 /* Fall through */ ;
9904 /* ... fall through ... */
9907 if ((unsigned_comparison_p
|| equality_comparison_p
)
9908 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
9909 <= HOST_BITS_PER_WIDE_INT
)
9910 && ((unsigned HOST_WIDE_INT
) const_op
9911 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
9913 op0
= XEXP (op0
, 0);
9919 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9920 this for equality comparisons due to pathological cases involving
9922 if (equality_comparison_p
9923 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
9924 op1
, XEXP (op0
, 1))))
9926 op0
= XEXP (op0
, 0);
9931 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9932 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
9933 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
9935 op0
= XEXP (XEXP (op0
, 0), 0);
9936 code
= (code
== LT
? EQ
: NE
);
9942 /* We used to optimize signed comparisons against zero, but that
9943 was incorrect. Unsigned comparisons against zero (GTU, LEU)
9944 arrive here as equality comparisons, or (GEU, LTU) are
9945 optimized away. No need to special-case them. */
9947 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9948 (eq B (minus A C)), whichever simplifies. We can only do
9949 this for equality comparisons due to pathological cases involving
9951 if (equality_comparison_p
9952 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
9953 XEXP (op0
, 1), op1
)))
9955 op0
= XEXP (op0
, 0);
9960 if (equality_comparison_p
9961 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
9962 XEXP (op0
, 0), op1
)))
9964 op0
= XEXP (op0
, 1);
9969 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9970 of bits in X minus 1, is one iff X > 0. */
9971 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
9972 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9973 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
9975 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
9977 op0
= XEXP (op0
, 1);
9978 code
= (code
== GE
? LE
: GT
);
9984 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9985 if C is zero or B is a constant. */
9986 if (equality_comparison_p
9987 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
9988 XEXP (op0
, 1), op1
)))
9990 op0
= XEXP (op0
, 0);
9997 case UNEQ
: case LTGT
:
9998 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
9999 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10000 case UNORDERED
: case ORDERED
:
10001 /* We can't do anything if OP0 is a condition code value, rather
10002 than an actual data value. */
10004 || CC0_P (XEXP (op0
, 0))
10005 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10008 /* Get the two operands being compared. */
10009 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10010 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10012 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10014 /* Check for the cases where we simply want the result of the
10015 earlier test or the opposite of that result. */
10016 if (code
== NE
|| code
== EQ
10017 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10018 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10019 && (STORE_FLAG_VALUE
10020 & (((HOST_WIDE_INT
) 1
10021 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10022 && (code
== LT
|| code
== GE
)))
10024 enum rtx_code new_code
;
10025 if (code
== LT
|| code
== NE
)
10026 new_code
= GET_CODE (op0
);
10028 new_code
= combine_reversed_comparison_code (op0
);
10030 if (new_code
!= UNKNOWN
)
10041 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10043 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10044 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10045 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10047 op0
= XEXP (op0
, 1);
10048 code
= (code
== GE
? GT
: LE
);
10054 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10055 will be converted to a ZERO_EXTRACT later. */
10056 if (const_op
== 0 && equality_comparison_p
10057 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10058 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10060 op0
= simplify_and_const_int
10061 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10063 XEXP (XEXP (op0
, 0), 1)),
10064 (HOST_WIDE_INT
) 1);
10068 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10069 zero and X is a comparison and C1 and C2 describe only bits set
10070 in STORE_FLAG_VALUE, we can compare with X. */
10071 if (const_op
== 0 && equality_comparison_p
10072 && mode_width
<= HOST_BITS_PER_WIDE_INT
10073 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10074 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10075 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10076 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10077 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10079 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10080 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10081 if ((~STORE_FLAG_VALUE
& mask
) == 0
10082 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10083 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10084 && COMPARISON_P (tem
))))
10086 op0
= XEXP (XEXP (op0
, 0), 0);
10091 /* If we are doing an equality comparison of an AND of a bit equal
10092 to the sign bit, replace this with a LT or GE comparison of
10093 the underlying value. */
10094 if (equality_comparison_p
10096 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10097 && mode_width
<= HOST_BITS_PER_WIDE_INT
10098 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10099 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10101 op0
= XEXP (op0
, 0);
10102 code
= (code
== EQ
? GE
: LT
);
10106 /* If this AND operation is really a ZERO_EXTEND from a narrower
10107 mode, the constant fits within that mode, and this is either an
10108 equality or unsigned comparison, try to do this comparison in
10109 the narrower mode. */
10110 if ((equality_comparison_p
|| unsigned_comparison_p
)
10111 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10112 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10113 & GET_MODE_MASK (mode
))
10115 && const_op
>> i
== 0
10116 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10118 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10122 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10123 fits in both M1 and M2 and the SUBREG is either paradoxical
10124 or represents the low part, permute the SUBREG and the AND
10126 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10128 unsigned HOST_WIDE_INT c1
;
10129 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10130 /* Require an integral mode, to avoid creating something like
10132 if (SCALAR_INT_MODE_P (tmode
)
10133 /* It is unsafe to commute the AND into the SUBREG if the
10134 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10135 not defined. As originally written the upper bits
10136 have a defined value due to the AND operation.
10137 However, if we commute the AND inside the SUBREG then
10138 they no longer have defined values and the meaning of
10139 the code has been changed. */
10141 #ifdef WORD_REGISTER_OPERATIONS
10142 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10143 && mode_width
<= BITS_PER_WORD
)
10145 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10146 && subreg_lowpart_p (XEXP (op0
, 0))))
10147 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10148 && mode_width
<= HOST_BITS_PER_WIDE_INT
10149 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10150 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10151 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10153 && c1
!= GET_MODE_MASK (tmode
))
10155 op0
= gen_binary (AND
, tmode
,
10156 SUBREG_REG (XEXP (op0
, 0)),
10157 gen_int_mode (c1
, tmode
));
10158 op0
= gen_lowpart (mode
, op0
);
10163 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10164 if (const_op
== 0 && equality_comparison_p
10165 && XEXP (op0
, 1) == const1_rtx
10166 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10168 op0
= simplify_and_const_int
10169 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10170 code
= (code
== NE
? EQ
: NE
);
10174 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10175 (eq (and (lshiftrt X) 1) 0).
10176 Also handle the case where (not X) is expressed using xor. */
10177 if (const_op
== 0 && equality_comparison_p
10178 && XEXP (op0
, 1) == const1_rtx
10179 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10181 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10182 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10184 if (GET_CODE (shift_op
) == NOT
10185 || (GET_CODE (shift_op
) == XOR
10186 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10187 && GET_CODE (shift_count
) == CONST_INT
10188 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10189 && (INTVAL (XEXP (shift_op
, 1))
10190 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10192 op0
= simplify_and_const_int
10194 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10195 (HOST_WIDE_INT
) 1);
10196 code
= (code
== NE
? EQ
: NE
);
10203 /* If we have (compare (ashift FOO N) (const_int C)) and
10204 the high order N bits of FOO (N+1 if an inequality comparison)
10205 are known to be zero, we can do this by comparing FOO with C
10206 shifted right N bits so long as the low-order N bits of C are
10208 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10209 && INTVAL (XEXP (op0
, 1)) >= 0
10210 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10211 < HOST_BITS_PER_WIDE_INT
)
10213 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10214 && mode_width
<= HOST_BITS_PER_WIDE_INT
10215 && (nonzero_bits (XEXP (op0
, 0), mode
)
10216 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10217 + ! equality_comparison_p
))) == 0)
10219 /* We must perform a logical shift, not an arithmetic one,
10220 as we want the top N bits of C to be zero. */
10221 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10223 temp
>>= INTVAL (XEXP (op0
, 1));
10224 op1
= gen_int_mode (temp
, mode
);
10225 op0
= XEXP (op0
, 0);
10229 /* If we are doing a sign bit comparison, it means we are testing
10230 a particular bit. Convert it to the appropriate AND. */
10231 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10232 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10234 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10237 - INTVAL (XEXP (op0
, 1)))));
10238 code
= (code
== LT
? NE
: EQ
);
10242 /* If this an equality comparison with zero and we are shifting
10243 the low bit to the sign bit, we can convert this to an AND of the
10245 if (const_op
== 0 && equality_comparison_p
10246 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10247 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10250 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10251 (HOST_WIDE_INT
) 1);
10257 /* If this is an equality comparison with zero, we can do this
10258 as a logical shift, which might be much simpler. */
10259 if (equality_comparison_p
&& const_op
== 0
10260 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10262 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10264 INTVAL (XEXP (op0
, 1)));
10268 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10269 do the comparison in a narrower mode. */
10270 if (! unsigned_comparison_p
10271 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10272 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10273 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10274 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10275 MODE_INT
, 1)) != BLKmode
10276 && (((unsigned HOST_WIDE_INT
) const_op
10277 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10278 <= GET_MODE_MASK (tmode
)))
10280 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10284 /* Likewise if OP0 is a PLUS of a sign extension with a
10285 constant, which is usually represented with the PLUS
10286 between the shifts. */
10287 if (! unsigned_comparison_p
10288 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10289 && GET_CODE (XEXP (op0
, 0)) == PLUS
10290 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10291 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10292 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10293 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10294 MODE_INT
, 1)) != BLKmode
10295 && (((unsigned HOST_WIDE_INT
) const_op
10296 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10297 <= GET_MODE_MASK (tmode
)))
10299 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10300 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10301 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10304 op0
= gen_binary (PLUS
, tmode
,
10305 gen_lowpart (tmode
, inner
),
10310 /* ... fall through ... */
10312 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10313 the low order N bits of FOO are known to be zero, we can do this
10314 by comparing FOO with C shifted left N bits so long as no
10315 overflow occurs. */
10316 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10317 && INTVAL (XEXP (op0
, 1)) >= 0
10318 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10319 && mode_width
<= HOST_BITS_PER_WIDE_INT
10320 && (nonzero_bits (XEXP (op0
, 0), mode
)
10321 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10322 && (((unsigned HOST_WIDE_INT
) const_op
10323 + (GET_CODE (op0
) != LSHIFTRT
10324 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10327 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10329 /* If the shift was logical, then we must make the condition
10331 if (GET_CODE (op0
) == LSHIFTRT
)
10332 code
= unsigned_condition (code
);
10334 const_op
<<= INTVAL (XEXP (op0
, 1));
10335 op1
= GEN_INT (const_op
);
10336 op0
= XEXP (op0
, 0);
10340 /* If we are using this shift to extract just the sign bit, we
10341 can replace this with an LT or GE comparison. */
10343 && (equality_comparison_p
|| sign_bit_comparison_p
)
10344 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10345 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10348 op0
= XEXP (op0
, 0);
10349 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10361 /* Now make any compound operations involved in this comparison. Then,
10362 check for an outmost SUBREG on OP0 that is not doing anything or is
10363 paradoxical. The latter transformation must only be performed when
10364 it is known that the "extra" bits will be the same in op0 and op1 or
10365 that they don't matter. There are three cases to consider:
10367 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10368 care bits and we can assume they have any convenient value. So
10369 making the transformation is safe.
10371 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10372 In this case the upper bits of op0 are undefined. We should not make
10373 the simplification in that case as we do not know the contents of
10376 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10377 NIL. In that case we know those bits are zeros or ones. We must
10378 also be sure that they are the same as the upper bits of op1.
10380 We can never remove a SUBREG for a non-equality comparison because
10381 the sign bit is in a different place in the underlying object. */
10383 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10384 op1
= make_compound_operation (op1
, SET
);
10386 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10387 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10388 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10389 && (code
== NE
|| code
== EQ
))
10391 if (GET_MODE_SIZE (GET_MODE (op0
))
10392 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10394 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10396 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
10398 op0
= SUBREG_REG (op0
);
10399 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10402 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10403 <= HOST_BITS_PER_WIDE_INT
)
10404 && (nonzero_bits (SUBREG_REG (op0
),
10405 GET_MODE (SUBREG_REG (op0
)))
10406 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10408 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10410 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10411 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10412 op0
= SUBREG_REG (op0
), op1
= tem
;
10416 /* We now do the opposite procedure: Some machines don't have compare
10417 insns in all modes. If OP0's mode is an integer mode smaller than a
10418 word and we can't do a compare in that mode, see if there is a larger
10419 mode for which we can do the compare. There are a number of cases in
10420 which we can use the wider mode. */
10422 mode
= GET_MODE (op0
);
10423 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10424 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10425 && ! have_insn_for (COMPARE
, mode
))
10426 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10428 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10429 tmode
= GET_MODE_WIDER_MODE (tmode
))
10430 if (have_insn_for (COMPARE
, tmode
))
10434 /* If the only nonzero bits in OP0 and OP1 are those in the
10435 narrower mode and this is an equality or unsigned comparison,
10436 we can use the wider mode. Similarly for sign-extended
10437 values, in which case it is true for all comparisons. */
10438 zero_extended
= ((code
== EQ
|| code
== NE
10439 || code
== GEU
|| code
== GTU
10440 || code
== LEU
|| code
== LTU
)
10441 && (nonzero_bits (op0
, tmode
)
10442 & ~GET_MODE_MASK (mode
)) == 0
10443 && ((GET_CODE (op1
) == CONST_INT
10444 || (nonzero_bits (op1
, tmode
)
10445 & ~GET_MODE_MASK (mode
)) == 0)));
10448 || ((num_sign_bit_copies (op0
, tmode
)
10449 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10450 - GET_MODE_BITSIZE (mode
)))
10451 && (num_sign_bit_copies (op1
, tmode
)
10452 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10453 - GET_MODE_BITSIZE (mode
)))))
10455 /* If OP0 is an AND and we don't have an AND in MODE either,
10456 make a new AND in the proper mode. */
10457 if (GET_CODE (op0
) == AND
10458 && !have_insn_for (AND
, mode
))
10459 op0
= gen_binary (AND
, tmode
,
10460 gen_lowpart (tmode
,
10462 gen_lowpart (tmode
,
10465 op0
= gen_lowpart (tmode
, op0
);
10466 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10467 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10468 op1
= gen_lowpart (tmode
, op1
);
10472 /* If this is a test for negative, we can make an explicit
10473 test of the sign bit. */
10475 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10476 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10478 op0
= gen_binary (AND
, tmode
,
10479 gen_lowpart (tmode
, op0
),
10480 GEN_INT ((HOST_WIDE_INT
) 1
10481 << (GET_MODE_BITSIZE (mode
) - 1)));
10482 code
= (code
== LT
) ? NE
: EQ
;
10487 #ifdef CANONICALIZE_COMPARISON
10488 /* If this machine only supports a subset of valid comparisons, see if we
10489 can convert an unsupported one into a supported one. */
10490 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10499 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10500 searching backward. */
10501 static enum rtx_code
10502 combine_reversed_comparison_code (rtx exp
)
10504 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10507 if (code1
!= UNKNOWN
10508 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10510 /* Otherwise try and find where the condition codes were last set and
10512 x
= get_last_value (XEXP (exp
, 0));
10513 if (!x
|| GET_CODE (x
) != COMPARE
)
10515 return reversed_comparison_code_parts (GET_CODE (exp
),
10516 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10519 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10520 Return NULL_RTX in case we fail to do the reversal. */
10522 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
10524 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10525 if (reversed_code
== UNKNOWN
)
10528 return gen_binary (reversed_code
, mode
, op0
, op1
);
10531 /* Utility function for following routine. Called when X is part of a value
10532 being stored into last_set_value. Sets last_set_table_tick
10533 for each register mentioned. Similar to mention_regs in cse.c */
10536 update_table_tick (rtx x
)
10538 enum rtx_code code
= GET_CODE (x
);
10539 const char *fmt
= GET_RTX_FORMAT (code
);
10544 unsigned int regno
= REGNO (x
);
10545 unsigned int endregno
10546 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10547 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10550 for (r
= regno
; r
< endregno
; r
++)
10551 reg_stat
[r
].last_set_table_tick
= label_tick
;
10556 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10557 /* Note that we can't have an "E" in values stored; see
10558 get_last_value_validate. */
10561 /* Check for identical subexpressions. If x contains
10562 identical subexpression we only have to traverse one of
10564 if (i
== 0 && ARITHMETIC_P (x
))
10566 /* Note that at this point x1 has already been
10568 rtx x0
= XEXP (x
, 0);
10569 rtx x1
= XEXP (x
, 1);
10571 /* If x0 and x1 are identical then there is no need to
10576 /* If x0 is identical to a subexpression of x1 then while
10577 processing x1, x0 has already been processed. Thus we
10578 are done with x. */
10579 if (ARITHMETIC_P (x1
)
10580 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10583 /* If x1 is identical to a subexpression of x0 then we
10584 still have to process the rest of x0. */
10585 if (ARITHMETIC_P (x0
)
10586 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10588 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10593 update_table_tick (XEXP (x
, i
));
10597 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10598 are saying that the register is clobbered and we no longer know its
10599 value. If INSN is zero, don't update reg_stat[].last_set; this is
10600 only permitted with VALUE also zero and is used to invalidate the
10604 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10606 unsigned int regno
= REGNO (reg
);
10607 unsigned int endregno
10608 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10609 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10612 /* If VALUE contains REG and we have a previous value for REG, substitute
10613 the previous value. */
10614 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10618 /* Set things up so get_last_value is allowed to see anything set up to
10620 subst_low_cuid
= INSN_CUID (insn
);
10621 tem
= get_last_value (reg
);
10623 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10624 it isn't going to be useful and will take a lot of time to process,
10625 so just use the CLOBBER. */
10629 if (ARITHMETIC_P (tem
)
10630 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10631 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10632 tem
= XEXP (tem
, 0);
10634 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10638 /* For each register modified, show we don't know its value, that
10639 we don't know about its bitwise content, that its value has been
10640 updated, and that we don't know the location of the death of the
10642 for (i
= regno
; i
< endregno
; i
++)
10645 reg_stat
[i
].last_set
= insn
;
10647 reg_stat
[i
].last_set_value
= 0;
10648 reg_stat
[i
].last_set_mode
= 0;
10649 reg_stat
[i
].last_set_nonzero_bits
= 0;
10650 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10651 reg_stat
[i
].last_death
= 0;
10654 /* Mark registers that are being referenced in this value. */
10656 update_table_tick (value
);
10658 /* Now update the status of each register being set.
10659 If someone is using this register in this block, set this register
10660 to invalid since we will get confused between the two lives in this
10661 basic block. This makes using this register always invalid. In cse, we
10662 scan the table to invalidate all entries using this register, but this
10663 is too much work for us. */
10665 for (i
= regno
; i
< endregno
; i
++)
10667 reg_stat
[i
].last_set_label
= label_tick
;
10668 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
10669 reg_stat
[i
].last_set_invalid
= 1;
10671 reg_stat
[i
].last_set_invalid
= 0;
10674 /* The value being assigned might refer to X (like in "x++;"). In that
10675 case, we must replace it with (clobber (const_int 0)) to prevent
10677 if (value
&& ! get_last_value_validate (&value
, insn
,
10678 reg_stat
[regno
].last_set_label
, 0))
10680 value
= copy_rtx (value
);
10681 if (! get_last_value_validate (&value
, insn
,
10682 reg_stat
[regno
].last_set_label
, 1))
10686 /* For the main register being modified, update the value, the mode, the
10687 nonzero bits, and the number of sign bit copies. */
10689 reg_stat
[regno
].last_set_value
= value
;
10693 enum machine_mode mode
= GET_MODE (reg
);
10694 subst_low_cuid
= INSN_CUID (insn
);
10695 reg_stat
[regno
].last_set_mode
= mode
;
10696 if (GET_MODE_CLASS (mode
) == MODE_INT
10697 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10698 mode
= nonzero_bits_mode
;
10699 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
10700 reg_stat
[regno
].last_set_sign_bit_copies
10701 = num_sign_bit_copies (value
, GET_MODE (reg
));
10705 /* Called via note_stores from record_dead_and_set_regs to handle one
10706 SET or CLOBBER in an insn. DATA is the instruction in which the
10707 set is occurring. */
10710 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
10712 rtx record_dead_insn
= (rtx
) data
;
10714 if (GET_CODE (dest
) == SUBREG
)
10715 dest
= SUBREG_REG (dest
);
10717 if (GET_CODE (dest
) == REG
)
10719 /* If we are setting the whole register, we know its value. Otherwise
10720 show that we don't know the value. We can handle SUBREG in
10722 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10723 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10724 else if (GET_CODE (setter
) == SET
10725 && GET_CODE (SET_DEST (setter
)) == SUBREG
10726 && SUBREG_REG (SET_DEST (setter
)) == dest
10727 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
10728 && subreg_lowpart_p (SET_DEST (setter
)))
10729 record_value_for_reg (dest
, record_dead_insn
,
10730 gen_lowpart (GET_MODE (dest
),
10731 SET_SRC (setter
)));
10733 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
10735 else if (GET_CODE (dest
) == MEM
10736 /* Ignore pushes, they clobber nothing. */
10737 && ! push_operand (dest
, GET_MODE (dest
)))
10738 mem_last_set
= INSN_CUID (record_dead_insn
);
10741 /* Update the records of when each REG was most recently set or killed
10742 for the things done by INSN. This is the last thing done in processing
10743 INSN in the combiner loop.
10745 We update reg_stat[], in particular fields last_set, last_set_value,
10746 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10747 last_death, and also the similar information mem_last_set (which insn
10748 most recently modified memory) and last_call_cuid (which insn was the
10749 most recent subroutine call). */
10752 record_dead_and_set_regs (rtx insn
)
10757 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
10759 if (REG_NOTE_KIND (link
) == REG_DEAD
10760 && GET_CODE (XEXP (link
, 0)) == REG
)
10762 unsigned int regno
= REGNO (XEXP (link
, 0));
10763 unsigned int endregno
10764 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10765 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
10768 for (i
= regno
; i
< endregno
; i
++)
10769 reg_stat
[i
].last_death
= insn
;
10771 else if (REG_NOTE_KIND (link
) == REG_INC
)
10772 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
10775 if (GET_CODE (insn
) == CALL_INSN
)
10777 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
10778 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
10780 reg_stat
[i
].last_set_value
= 0;
10781 reg_stat
[i
].last_set_mode
= 0;
10782 reg_stat
[i
].last_set_nonzero_bits
= 0;
10783 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10784 reg_stat
[i
].last_death
= 0;
10787 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
10789 /* Don't bother recording what this insn does. It might set the
10790 return value register, but we can't combine into a call
10791 pattern anyway, so there's no point trying (and it may cause
10792 a crash, if e.g. we wind up asking for last_set_value of a
10793 SUBREG of the return value register). */
10797 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
10800 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10801 register present in the SUBREG, so for each such SUBREG go back and
10802 adjust nonzero and sign bit information of the registers that are
10803 known to have some zero/sign bits set.
10805 This is needed because when combine blows the SUBREGs away, the
10806 information on zero/sign bits is lost and further combines can be
10807 missed because of that. */
10810 record_promoted_value (rtx insn
, rtx subreg
)
10813 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
10814 enum machine_mode mode
= GET_MODE (subreg
);
10816 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
10819 for (links
= LOG_LINKS (insn
); links
;)
10821 insn
= XEXP (links
, 0);
10822 set
= single_set (insn
);
10824 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
10825 || REGNO (SET_DEST (set
)) != regno
10826 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
10828 links
= XEXP (links
, 1);
10832 if (reg_stat
[regno
].last_set
== insn
)
10834 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
10835 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
10838 if (GET_CODE (SET_SRC (set
)) == REG
)
10840 regno
= REGNO (SET_SRC (set
));
10841 links
= LOG_LINKS (insn
);
10848 /* Scan X for promoted SUBREGs. For each one found,
10849 note what it implies to the registers used in it. */
10852 check_promoted_subreg (rtx insn
, rtx x
)
10854 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
10855 && GET_CODE (SUBREG_REG (x
)) == REG
)
10856 record_promoted_value (insn
, x
);
10859 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
10862 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
10866 check_promoted_subreg (insn
, XEXP (x
, i
));
10870 if (XVEC (x
, i
) != 0)
10871 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
10872 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
10878 /* Utility routine for the following function. Verify that all the registers
10879 mentioned in *LOC are valid when *LOC was part of a value set when
10880 label_tick == TICK. Return 0 if some are not.
10882 If REPLACE is nonzero, replace the invalid reference with
10883 (clobber (const_int 0)) and return 1. This replacement is useful because
10884 we often can get useful information about the form of a value (e.g., if
10885 it was produced by a shift that always produces -1 or 0) even though
10886 we don't know exactly what registers it was produced from. */
10889 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
10892 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10893 int len
= GET_RTX_LENGTH (GET_CODE (x
));
10896 if (GET_CODE (x
) == REG
)
10898 unsigned int regno
= REGNO (x
);
10899 unsigned int endregno
10900 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10901 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10904 for (j
= regno
; j
< endregno
; j
++)
10905 if (reg_stat
[j
].last_set_invalid
10906 /* If this is a pseudo-register that was only set once and not
10907 live at the beginning of the function, it is always valid. */
10908 || (! (regno
>= FIRST_PSEUDO_REGISTER
10909 && REG_N_SETS (regno
) == 1
10910 && (! REGNO_REG_SET_P
10911 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
10912 && reg_stat
[j
].last_set_label
> tick
))
10915 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10921 /* If this is a memory reference, make sure that there were
10922 no stores after it that might have clobbered the value. We don't
10923 have alias info, so we assume any store invalidates it. */
10924 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
10925 && INSN_CUID (insn
) <= mem_last_set
)
10928 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10932 for (i
= 0; i
< len
; i
++)
10936 /* Check for identical subexpressions. If x contains
10937 identical subexpression we only have to traverse one of
10939 if (i
== 1 && ARITHMETIC_P (x
))
10941 /* Note that at this point x0 has already been checked
10942 and found valid. */
10943 rtx x0
= XEXP (x
, 0);
10944 rtx x1
= XEXP (x
, 1);
10946 /* If x0 and x1 are identical then x is also valid. */
10950 /* If x1 is identical to a subexpression of x0 then
10951 while checking x0, x1 has already been checked. Thus
10952 it is valid and so as x. */
10953 if (ARITHMETIC_P (x0
)
10954 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10957 /* If x0 is identical to a subexpression of x1 then x is
10958 valid iff the rest of x1 is valid. */
10959 if (ARITHMETIC_P (x1
)
10960 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10962 get_last_value_validate (&XEXP (x1
,
10963 x0
== XEXP (x1
, 0) ? 1 : 0),
10964 insn
, tick
, replace
);
10967 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
10971 /* Don't bother with these. They shouldn't occur anyway. */
10972 else if (fmt
[i
] == 'E')
10976 /* If we haven't found a reason for it to be invalid, it is valid. */
10980 /* Get the last value assigned to X, if known. Some registers
10981 in the value may be replaced with (clobber (const_int 0)) if their value
10982 is known longer known reliably. */
10985 get_last_value (rtx x
)
10987 unsigned int regno
;
10990 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10991 then convert it to the desired mode. If this is a paradoxical SUBREG,
10992 we cannot predict what values the "extra" bits might have. */
10993 if (GET_CODE (x
) == SUBREG
10994 && subreg_lowpart_p (x
)
10995 && (GET_MODE_SIZE (GET_MODE (x
))
10996 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
10997 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
10998 return gen_lowpart (GET_MODE (x
), value
);
11000 if (GET_CODE (x
) != REG
)
11004 value
= reg_stat
[regno
].last_set_value
;
11006 /* If we don't have a value, or if it isn't for this basic block and
11007 it's either a hard register, set more than once, or it's a live
11008 at the beginning of the function, return 0.
11010 Because if it's not live at the beginning of the function then the reg
11011 is always set before being used (is never used without being set).
11012 And, if it's set only once, and it's always set before use, then all
11013 uses must have the same last value, even if it's not from this basic
11017 || (reg_stat
[regno
].last_set_label
!= label_tick
11018 && (regno
< FIRST_PSEUDO_REGISTER
11019 || REG_N_SETS (regno
) != 1
11020 || (REGNO_REG_SET_P
11021 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11024 /* If the value was set in a later insn than the ones we are processing,
11025 we can't use it even if the register was only set once. */
11026 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11029 /* If the value has all its registers valid, return it. */
11030 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11031 reg_stat
[regno
].last_set_label
, 0))
11034 /* Otherwise, make a copy and replace any invalid register with
11035 (clobber (const_int 0)). If that fails for some reason, return 0. */
11037 value
= copy_rtx (value
);
11038 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11039 reg_stat
[regno
].last_set_label
, 1))
11045 /* Return nonzero if expression X refers to a REG or to memory
11046 that is set in an instruction more recent than FROM_CUID. */
11049 use_crosses_set_p (rtx x
, int from_cuid
)
11053 enum rtx_code code
= GET_CODE (x
);
11057 unsigned int regno
= REGNO (x
);
11058 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11059 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11061 #ifdef PUSH_ROUNDING
11062 /* Don't allow uses of the stack pointer to be moved,
11063 because we don't know whether the move crosses a push insn. */
11064 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11067 for (; regno
< endreg
; regno
++)
11068 if (reg_stat
[regno
].last_set
11069 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11074 if (code
== MEM
&& mem_last_set
> from_cuid
)
11077 fmt
= GET_RTX_FORMAT (code
);
11079 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11084 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11085 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11088 else if (fmt
[i
] == 'e'
11089 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11095 /* Define three variables used for communication between the following
11098 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11099 static int reg_dead_flag
;
11101 /* Function called via note_stores from reg_dead_at_p.
11103 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11104 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11107 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11109 unsigned int regno
, endregno
;
11111 if (GET_CODE (dest
) != REG
)
11114 regno
= REGNO (dest
);
11115 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11116 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11118 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11119 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11122 /* Return nonzero if REG is known to be dead at INSN.
11124 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11125 referencing REG, it is dead. If we hit a SET referencing REG, it is
11126 live. Otherwise, see if it is live or dead at the start of the basic
11127 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11128 must be assumed to be always live. */
11131 reg_dead_at_p (rtx reg
, rtx insn
)
11136 /* Set variables for reg_dead_at_p_1. */
11137 reg_dead_regno
= REGNO (reg
);
11138 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11139 ? hard_regno_nregs
[reg_dead_regno
]
11145 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11146 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11148 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11149 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11153 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11154 beginning of function. */
11155 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11156 insn
= prev_nonnote_insn (insn
))
11158 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11160 return reg_dead_flag
== 1 ? 1 : 0;
11162 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11166 /* Get the basic block that we were in. */
11168 block
= ENTRY_BLOCK_PTR
->next_bb
;
11171 FOR_EACH_BB (block
)
11172 if (insn
== BB_HEAD (block
))
11175 if (block
== EXIT_BLOCK_PTR
)
11179 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11180 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11186 /* Note hard registers in X that are used. This code is similar to
11187 that in flow.c, but much simpler since we don't care about pseudos. */
11190 mark_used_regs_combine (rtx x
)
11192 RTX_CODE code
= GET_CODE (x
);
11193 unsigned int regno
;
11206 case ADDR_DIFF_VEC
:
11209 /* CC0 must die in the insn after it is set, so we don't need to take
11210 special note of it here. */
11216 /* If we are clobbering a MEM, mark any hard registers inside the
11217 address as used. */
11218 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11219 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11224 /* A hard reg in a wide mode may really be multiple registers.
11225 If so, mark all of them just like the first. */
11226 if (regno
< FIRST_PSEUDO_REGISTER
)
11228 unsigned int endregno
, r
;
11230 /* None of this applies to the stack, frame or arg pointers. */
11231 if (regno
== STACK_POINTER_REGNUM
11232 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11233 || regno
== HARD_FRAME_POINTER_REGNUM
11235 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11236 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11238 || regno
== FRAME_POINTER_REGNUM
)
11241 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11242 for (r
= regno
; r
< endregno
; r
++)
11243 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11249 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11251 rtx testreg
= SET_DEST (x
);
11253 while (GET_CODE (testreg
) == SUBREG
11254 || GET_CODE (testreg
) == ZERO_EXTRACT
11255 || GET_CODE (testreg
) == SIGN_EXTRACT
11256 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11257 testreg
= XEXP (testreg
, 0);
11259 if (GET_CODE (testreg
) == MEM
)
11260 mark_used_regs_combine (XEXP (testreg
, 0));
11262 mark_used_regs_combine (SET_SRC (x
));
11270 /* Recursively scan the operands of this expression. */
11273 const char *fmt
= GET_RTX_FORMAT (code
);
11275 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11278 mark_used_regs_combine (XEXP (x
, i
));
11279 else if (fmt
[i
] == 'E')
11283 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11284 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11290 /* Remove register number REGNO from the dead registers list of INSN.
11292 Return the note used to record the death, if there was one. */
11295 remove_death (unsigned int regno
, rtx insn
)
11297 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11301 REG_N_DEATHS (regno
)--;
11302 remove_note (insn
, note
);
11308 /* For each register (hardware or pseudo) used within expression X, if its
11309 death is in an instruction with cuid between FROM_CUID (inclusive) and
11310 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11311 list headed by PNOTES.
11313 That said, don't move registers killed by maybe_kill_insn.
11315 This is done when X is being merged by combination into TO_INSN. These
11316 notes will then be distributed as needed. */
11319 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11324 enum rtx_code code
= GET_CODE (x
);
11328 unsigned int regno
= REGNO (x
);
11329 rtx where_dead
= reg_stat
[regno
].last_death
;
11330 rtx before_dead
, after_dead
;
11332 /* Don't move the register if it gets killed in between from and to. */
11333 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11334 && ! reg_referenced_p (x
, maybe_kill_insn
))
11337 /* WHERE_DEAD could be a USE insn made by combine, so first we
11338 make sure that we have insns with valid INSN_CUID values. */
11339 before_dead
= where_dead
;
11340 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11341 before_dead
= PREV_INSN (before_dead
);
11343 after_dead
= where_dead
;
11344 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11345 after_dead
= NEXT_INSN (after_dead
);
11347 if (before_dead
&& after_dead
11348 && INSN_CUID (before_dead
) >= from_cuid
11349 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11350 || (where_dead
!= after_dead
11351 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11353 rtx note
= remove_death (regno
, where_dead
);
11355 /* It is possible for the call above to return 0. This can occur
11356 when last_death points to I2 or I1 that we combined with.
11357 In that case make a new note.
11359 We must also check for the case where X is a hard register
11360 and NOTE is a death note for a range of hard registers
11361 including X. In that case, we must put REG_DEAD notes for
11362 the remaining registers in place of NOTE. */
11364 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11365 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11366 > GET_MODE_SIZE (GET_MODE (x
))))
11368 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11369 unsigned int deadend
11370 = (deadregno
+ hard_regno_nregs
[deadregno
]
11371 [GET_MODE (XEXP (note
, 0))]);
11372 unsigned int ourend
11373 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11376 for (i
= deadregno
; i
< deadend
; i
++)
11377 if (i
< regno
|| i
>= ourend
)
11378 REG_NOTES (where_dead
)
11379 = gen_rtx_EXPR_LIST (REG_DEAD
,
11381 REG_NOTES (where_dead
));
11384 /* If we didn't find any note, or if we found a REG_DEAD note that
11385 covers only part of the given reg, and we have a multi-reg hard
11386 register, then to be safe we must check for REG_DEAD notes
11387 for each register other than the first. They could have
11388 their own REG_DEAD notes lying around. */
11389 else if ((note
== 0
11391 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11392 < GET_MODE_SIZE (GET_MODE (x
)))))
11393 && regno
< FIRST_PSEUDO_REGISTER
11394 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11396 unsigned int ourend
11397 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11398 unsigned int i
, offset
;
11402 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11406 for (i
= regno
+ offset
; i
< ourend
; i
++)
11407 move_deaths (regno_reg_rtx
[i
],
11408 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11411 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11413 XEXP (note
, 1) = *pnotes
;
11417 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11419 REG_N_DEATHS (regno
)++;
11425 else if (GET_CODE (x
) == SET
)
11427 rtx dest
= SET_DEST (x
);
11429 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11431 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11432 that accesses one word of a multi-word item, some
11433 piece of everything register in the expression is used by
11434 this insn, so remove any old death. */
11435 /* ??? So why do we test for equality of the sizes? */
11437 if (GET_CODE (dest
) == ZERO_EXTRACT
11438 || GET_CODE (dest
) == STRICT_LOW_PART
11439 || (GET_CODE (dest
) == SUBREG
11440 && (((GET_MODE_SIZE (GET_MODE (dest
))
11441 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11442 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11443 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11445 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11449 /* If this is some other SUBREG, we know it replaces the entire
11450 value, so use that as the destination. */
11451 if (GET_CODE (dest
) == SUBREG
)
11452 dest
= SUBREG_REG (dest
);
11454 /* If this is a MEM, adjust deaths of anything used in the address.
11455 For a REG (the only other possibility), the entire value is
11456 being replaced so the old value is not used in this insn. */
11458 if (GET_CODE (dest
) == MEM
)
11459 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11464 else if (GET_CODE (x
) == CLOBBER
)
11467 len
= GET_RTX_LENGTH (code
);
11468 fmt
= GET_RTX_FORMAT (code
);
11470 for (i
= 0; i
< len
; i
++)
11475 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11476 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11479 else if (fmt
[i
] == 'e')
11480 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11484 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11485 pattern of an insn. X must be a REG. */
11488 reg_bitfield_target_p (rtx x
, rtx body
)
11492 if (GET_CODE (body
) == SET
)
11494 rtx dest
= SET_DEST (body
);
11496 unsigned int regno
, tregno
, endregno
, endtregno
;
11498 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11499 target
= XEXP (dest
, 0);
11500 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11501 target
= SUBREG_REG (XEXP (dest
, 0));
11505 if (GET_CODE (target
) == SUBREG
)
11506 target
= SUBREG_REG (target
);
11508 if (GET_CODE (target
) != REG
)
11511 tregno
= REGNO (target
), regno
= REGNO (x
);
11512 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11513 return target
== x
;
11515 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11516 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11518 return endregno
> tregno
&& regno
< endtregno
;
11521 else if (GET_CODE (body
) == PARALLEL
)
11522 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11523 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11529 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11530 as appropriate. I3 and I2 are the insns resulting from the combination
11531 insns including FROM (I2 may be zero).
11533 Each note in the list is either ignored or placed on some insns, depending
11534 on the type of note. */
11537 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
11539 rtx note
, next_note
;
11542 for (note
= notes
; note
; note
= next_note
)
11544 rtx place
= 0, place2
= 0;
11546 /* If this NOTE references a pseudo register, ensure it references
11547 the latest copy of that register. */
11548 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11549 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11550 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11552 next_note
= XEXP (note
, 1);
11553 switch (REG_NOTE_KIND (note
))
11557 /* Doesn't matter much where we put this, as long as it's somewhere.
11558 It is preferable to keep these notes on branches, which is most
11559 likely to be i3. */
11563 case REG_VALUE_PROFILE
:
11564 /* Just get rid of this note, as it is unused later anyway. */
11567 case REG_VTABLE_REF
:
11568 /* ??? Should remain with *a particular* memory load. Given the
11569 nature of vtable data, the last insn seems relatively safe. */
11573 case REG_NON_LOCAL_GOTO
:
11574 if (GET_CODE (i3
) == JUMP_INSN
)
11576 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
11582 case REG_EH_REGION
:
11583 /* These notes must remain with the call or trapping instruction. */
11584 if (GET_CODE (i3
) == CALL_INSN
)
11586 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11588 else if (flag_non_call_exceptions
)
11590 if (may_trap_p (i3
))
11592 else if (i2
&& may_trap_p (i2
))
11594 /* ??? Otherwise assume we've combined things such that we
11595 can now prove that the instructions can't trap. Drop the
11596 note in this case. */
11602 case REG_ALWAYS_RETURN
:
11605 /* These notes must remain with the call. It should not be
11606 possible for both I2 and I3 to be a call. */
11607 if (GET_CODE (i3
) == CALL_INSN
)
11609 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11616 /* Any clobbers for i3 may still exist, and so we must process
11617 REG_UNUSED notes from that insn.
11619 Any clobbers from i2 or i1 can only exist if they were added by
11620 recog_for_combine. In that case, recog_for_combine created the
11621 necessary REG_UNUSED notes. Trying to keep any original
11622 REG_UNUSED notes from these insns can cause incorrect output
11623 if it is for the same register as the original i3 dest.
11624 In that case, we will notice that the register is set in i3,
11625 and then add a REG_UNUSED note for the destination of i3, which
11626 is wrong. However, it is possible to have REG_UNUSED notes from
11627 i2 or i1 for register which were both used and clobbered, so
11628 we keep notes from i2 or i1 if they will turn into REG_DEAD
11631 /* If this register is set or clobbered in I3, put the note there
11632 unless there is one already. */
11633 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11635 if (from_insn
!= i3
)
11638 if (! (GET_CODE (XEXP (note
, 0)) == REG
11639 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11640 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11643 /* Otherwise, if this register is used by I3, then this register
11644 now dies here, so we must put a REG_DEAD note here unless there
11646 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11647 && ! (GET_CODE (XEXP (note
, 0)) == REG
11648 ? find_regno_note (i3
, REG_DEAD
,
11649 REGNO (XEXP (note
, 0)))
11650 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11652 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11660 /* These notes say something about results of an insn. We can
11661 only support them if they used to be on I3 in which case they
11662 remain on I3. Otherwise they are ignored.
11664 If the note refers to an expression that is not a constant, we
11665 must also ignore the note since we cannot tell whether the
11666 equivalence is still true. It might be possible to do
11667 slightly better than this (we only have a problem if I2DEST
11668 or I1DEST is present in the expression), but it doesn't
11669 seem worth the trouble. */
11671 if (from_insn
== i3
11672 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11677 case REG_NO_CONFLICT
:
11678 /* These notes say something about how a register is used. They must
11679 be present on any use of the register in I2 or I3. */
11680 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11683 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11693 /* This can show up in several ways -- either directly in the
11694 pattern, or hidden off in the constant pool with (or without?)
11695 a REG_EQUAL note. */
11696 /* ??? Ignore the without-reg_equal-note problem for now. */
11697 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11698 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11699 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11700 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11704 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11705 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11706 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11707 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11715 /* Don't attach REG_LABEL note to a JUMP_INSN which has
11716 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
11717 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
11719 if (JUMP_LABEL (place
) != XEXP (note
, 0))
11721 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
11722 LABEL_NUSES (JUMP_LABEL (place
))--;
11725 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
11727 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
11729 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
11730 LABEL_NUSES (JUMP_LABEL (place2
))--;
11736 /* This note says something about the value of a register prior
11737 to the execution of an insn. It is too much trouble to see
11738 if the note is still correct in all situations. It is better
11739 to simply delete it. */
11743 /* If the insn previously containing this note still exists,
11744 put it back where it was. Otherwise move it to the previous
11745 insn. Adjust the corresponding REG_LIBCALL note. */
11746 if (GET_CODE (from_insn
) != NOTE
)
11750 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
11751 place
= prev_real_insn (from_insn
);
11753 XEXP (tem
, 0) = place
;
11754 /* If we're deleting the last remaining instruction of a
11755 libcall sequence, don't add the notes. */
11756 else if (XEXP (note
, 0) == from_insn
)
11758 /* Don't add the dangling REG_RETVAL note. */
11765 /* This is handled similarly to REG_RETVAL. */
11766 if (GET_CODE (from_insn
) != NOTE
)
11770 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
11771 place
= next_real_insn (from_insn
);
11773 XEXP (tem
, 0) = place
;
11774 /* If we're deleting the last remaining instruction of a
11775 libcall sequence, don't add the notes. */
11776 else if (XEXP (note
, 0) == from_insn
)
11778 /* Don't add the dangling REG_LIBCALL note. */
11785 /* If the register is used as an input in I3, it dies there.
11786 Similarly for I2, if it is nonzero and adjacent to I3.
11788 If the register is not used as an input in either I3 or I2
11789 and it is not one of the registers we were supposed to eliminate,
11790 there are two possibilities. We might have a non-adjacent I2
11791 or we might have somehow eliminated an additional register
11792 from a computation. For example, we might have had A & B where
11793 we discover that B will always be zero. In this case we will
11794 eliminate the reference to A.
11796 In both cases, we must search to see if we can find a previous
11797 use of A and put the death note there. */
11800 && GET_CODE (from_insn
) == CALL_INSN
11801 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
11803 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
11805 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
11806 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11811 basic_block bb
= this_basic_block
;
11813 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
11815 if (! INSN_P (tem
))
11817 if (tem
== BB_HEAD (bb
))
11822 /* If the register is being set at TEM, see if that is all
11823 TEM is doing. If so, delete TEM. Otherwise, make this
11824 into a REG_UNUSED note instead. */
11825 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
11827 rtx set
= single_set (tem
);
11828 rtx inner_dest
= 0;
11830 rtx cc0_setter
= NULL_RTX
;
11834 for (inner_dest
= SET_DEST (set
);
11835 (GET_CODE (inner_dest
) == STRICT_LOW_PART
11836 || GET_CODE (inner_dest
) == SUBREG
11837 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
11838 inner_dest
= XEXP (inner_dest
, 0))
11841 /* Verify that it was the set, and not a clobber that
11842 modified the register.
11844 CC0 targets must be careful to maintain setter/user
11845 pairs. If we cannot delete the setter due to side
11846 effects, mark the user with an UNUSED note instead
11849 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
11850 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
11852 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
11853 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
11854 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
11858 /* Move the notes and links of TEM elsewhere.
11859 This might delete other dead insns recursively.
11860 First set the pattern to something that won't use
11862 rtx old_notes
= REG_NOTES (tem
);
11864 PATTERN (tem
) = pc_rtx
;
11865 REG_NOTES (tem
) = NULL
;
11867 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
11868 distribute_links (LOG_LINKS (tem
));
11870 PUT_CODE (tem
, NOTE
);
11871 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
11872 NOTE_SOURCE_FILE (tem
) = 0;
11875 /* Delete the setter too. */
11878 PATTERN (cc0_setter
) = pc_rtx
;
11879 old_notes
= REG_NOTES (cc0_setter
);
11880 REG_NOTES (cc0_setter
) = NULL
;
11882 distribute_notes (old_notes
, cc0_setter
,
11883 cc0_setter
, NULL_RTX
);
11884 distribute_links (LOG_LINKS (cc0_setter
));
11886 PUT_CODE (cc0_setter
, NOTE
);
11887 NOTE_LINE_NUMBER (cc0_setter
)
11888 = NOTE_INSN_DELETED
;
11889 NOTE_SOURCE_FILE (cc0_setter
) = 0;
11895 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
11897 /* If there isn't already a REG_UNUSED note, put one
11898 here. Do not place a REG_DEAD note, even if
11899 the register is also used here; that would not
11900 match the algorithm used in lifetime analysis
11901 and can cause the consistency check in the
11902 scheduler to fail. */
11903 if (! find_regno_note (tem
, REG_UNUSED
,
11904 REGNO (XEXP (note
, 0))))
11909 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
11910 || (GET_CODE (tem
) == CALL_INSN
11911 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
11915 /* If we are doing a 3->2 combination, and we have a
11916 register which formerly died in i3 and was not used
11917 by i2, which now no longer dies in i3 and is used in
11918 i2 but does not die in i2, and place is between i2
11919 and i3, then we may need to move a link from place to
11921 if (i2
&& INSN_UID (place
) <= max_uid_cuid
11922 && INSN_CUID (place
) > INSN_CUID (i2
)
11924 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
11925 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11927 rtx links
= LOG_LINKS (place
);
11928 LOG_LINKS (place
) = 0;
11929 distribute_links (links
);
11934 if (tem
== BB_HEAD (bb
))
11938 /* We haven't found an insn for the death note and it
11939 is still a REG_DEAD note, but we have hit the beginning
11940 of the block. If the existing life info says the reg
11941 was dead, there's nothing left to do. Otherwise, we'll
11942 need to do a global life update after combine. */
11943 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
11944 && REGNO_REG_SET_P (bb
->global_live_at_start
,
11945 REGNO (XEXP (note
, 0))))
11946 SET_BIT (refresh_blocks
, this_basic_block
->index
);
11949 /* If the register is set or already dead at PLACE, we needn't do
11950 anything with this note if it is still a REG_DEAD note.
11951 We check here if it is set at all, not if is it totally replaced,
11952 which is what `dead_or_set_p' checks, so also check for it being
11955 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
11957 unsigned int regno
= REGNO (XEXP (note
, 0));
11959 /* Similarly, if the instruction on which we want to place
11960 the note is a noop, we'll need do a global live update
11961 after we remove them in delete_noop_moves. */
11962 if (noop_move_p (place
))
11963 SET_BIT (refresh_blocks
, this_basic_block
->index
);
11965 if (dead_or_set_p (place
, XEXP (note
, 0))
11966 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
11968 /* Unless the register previously died in PLACE, clear
11969 last_death. [I no longer understand why this is
11971 if (reg_stat
[regno
].last_death
!= place
)
11972 reg_stat
[regno
].last_death
= 0;
11976 reg_stat
[regno
].last_death
= place
;
11978 /* If this is a death note for a hard reg that is occupying
11979 multiple registers, ensure that we are still using all
11980 parts of the object. If we find a piece of the object
11981 that is unused, we must arrange for an appropriate REG_DEAD
11982 note to be added for it. However, we can't just emit a USE
11983 and tag the note to it, since the register might actually
11984 be dead; so we recourse, and the recursive call then finds
11985 the previous insn that used this register. */
11987 if (place
&& regno
< FIRST_PSEUDO_REGISTER
11988 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
11990 unsigned int endregno
11991 = regno
+ hard_regno_nregs
[regno
]
11992 [GET_MODE (XEXP (note
, 0))];
11996 for (i
= regno
; i
< endregno
; i
++)
11997 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
11998 && ! find_regno_fusage (place
, USE
, i
))
11999 || dead_or_set_regno_p (place
, i
))
12004 /* Put only REG_DEAD notes for pieces that are
12005 not already dead or set. */
12007 for (i
= regno
; i
< endregno
;
12008 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12010 rtx piece
= regno_reg_rtx
[i
];
12011 basic_block bb
= this_basic_block
;
12013 if (! dead_or_set_p (place
, piece
)
12014 && ! reg_bitfield_target_p (piece
,
12018 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12020 distribute_notes (new_note
, place
, place
,
12023 else if (! refers_to_regno_p (i
, i
+ 1,
12024 PATTERN (place
), 0)
12025 && ! find_regno_fusage (place
, USE
, i
))
12026 for (tem
= PREV_INSN (place
); ;
12027 tem
= PREV_INSN (tem
))
12029 if (! INSN_P (tem
))
12031 if (tem
== BB_HEAD (bb
))
12033 SET_BIT (refresh_blocks
,
12034 this_basic_block
->index
);
12039 if (dead_or_set_p (tem
, piece
)
12040 || reg_bitfield_target_p (piece
,
12044 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12059 /* Any other notes should not be present at this point in the
12066 XEXP (note
, 1) = REG_NOTES (place
);
12067 REG_NOTES (place
) = note
;
12069 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12070 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12071 && GET_CODE (XEXP (note
, 0)) == REG
)
12072 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12076 if ((REG_NOTE_KIND (note
) == REG_DEAD
12077 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12078 && GET_CODE (XEXP (note
, 0)) == REG
)
12079 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12081 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12082 REG_NOTE_KIND (note
),
12084 REG_NOTES (place2
));
12089 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12090 I3, I2, and I1 to new locations. This is also called to add a link
12091 pointing at I3 when I3's destination is changed. */
12094 distribute_links (rtx links
)
12096 rtx link
, next_link
;
12098 for (link
= links
; link
; link
= next_link
)
12104 next_link
= XEXP (link
, 1);
12106 /* If the insn that this link points to is a NOTE or isn't a single
12107 set, ignore it. In the latter case, it isn't clear what we
12108 can do other than ignore the link, since we can't tell which
12109 register it was for. Such links wouldn't be used by combine
12112 It is not possible for the destination of the target of the link to
12113 have been changed by combine. The only potential of this is if we
12114 replace I3, I2, and I1 by I3 and I2. But in that case the
12115 destination of I2 also remains unchanged. */
12117 if (GET_CODE (XEXP (link
, 0)) == NOTE
12118 || (set
= single_set (XEXP (link
, 0))) == 0)
12121 reg
= SET_DEST (set
);
12122 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12123 || GET_CODE (reg
) == SIGN_EXTRACT
12124 || GET_CODE (reg
) == STRICT_LOW_PART
)
12125 reg
= XEXP (reg
, 0);
12127 /* A LOG_LINK is defined as being placed on the first insn that uses
12128 a register and points to the insn that sets the register. Start
12129 searching at the next insn after the target of the link and stop
12130 when we reach a set of the register or the end of the basic block.
12132 Note that this correctly handles the link that used to point from
12133 I3 to I2. Also note that not much searching is typically done here
12134 since most links don't point very far away. */
12136 for (insn
= NEXT_INSN (XEXP (link
, 0));
12137 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12138 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12139 insn
= NEXT_INSN (insn
))
12140 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12142 if (reg_referenced_p (reg
, PATTERN (insn
)))
12146 else if (GET_CODE (insn
) == CALL_INSN
12147 && find_reg_fusage (insn
, USE
, reg
))
12152 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12155 /* If we found a place to put the link, place it there unless there
12156 is already a link to the same insn as LINK at that point. */
12162 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12163 if (XEXP (link2
, 0) == XEXP (link
, 0))
12168 XEXP (link
, 1) = LOG_LINKS (place
);
12169 LOG_LINKS (place
) = link
;
12171 /* Set added_links_insn to the earliest insn we added a
12173 if (added_links_insn
== 0
12174 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12175 added_links_insn
= place
;
12181 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12182 Check whether the expression pointer to by LOC is a register or
12183 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12184 Otherwise return zero. */
12187 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12192 && (GET_CODE (x
) == REG
|| GET_CODE (x
) == MEM
)
12193 && ! reg_mentioned_p (x
, (rtx
) expr
))
12198 /* Check for any register or memory mentioned in EQUIV that is not
12199 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12200 of EXPR where some registers may have been replaced by constants. */
12203 unmentioned_reg_p (rtx equiv
, rtx expr
)
12205 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12208 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12211 insn_cuid (rtx insn
)
12213 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12214 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12215 insn
= NEXT_INSN (insn
);
12217 if (INSN_UID (insn
) > max_uid_cuid
)
12220 return INSN_CUID (insn
);
12224 dump_combine_stats (FILE *file
)
12228 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12229 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12233 dump_combine_total_stats (FILE *file
)
12237 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12238 total_attempts
, total_merges
, total_extras
, total_successes
);