gcc/config/aarch64/aarch64.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_H
  23 #define GCC_AARCH64_H
  24
  25 /* Target CPU builtins.  */
  26 #define TARGET_CPU_CPP_BUILTINS()       \
  27   aarch64_cpu_cpp_builtins (pfile)
  28
  29 /* Target CPU versions for D.  */
  30 #define TARGET_D_CPU_VERSIONS aarch64_d_target_versions
  31
  32 \f
  33
  34 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
  35
  36 /* Target machine storage layout.  */
  37
  38 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  39   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  40       && GET_MODE_SIZE (MODE) < 4)              \
  41     {                                           \
  42       if (MODE == QImode || MODE == HImode)     \
  43         {                                       \
  44           MODE = SImode;                        \
  45         }                                       \
  46     }
  47
  48 /* Bits are always numbered from the LSBit.  */
  49 #define BITS_BIG_ENDIAN 0
  50
  51 /* Big/little-endian flavour.  */
  52 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
  53 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
  54
  55 /* AdvSIMD is supported in the default configuration, unless disabled by
  56    -mgeneral-regs-only or by the +nosimd extension.  */
  57 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
  58 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
  59
  60 #define UNITS_PER_WORD          8
  61
  62 #define UNITS_PER_VREG          16
  63
  64 #define PARM_BOUNDARY           64
  65
  66 #define STACK_BOUNDARY          128
  67
  68 #define FUNCTION_BOUNDARY       32
  69
  70 #define EMPTY_FIELD_BOUNDARY    32
  71
  72 #define BIGGEST_ALIGNMENT       128
  73
  74 #define SHORT_TYPE_SIZE         16
  75
  76 #define INT_TYPE_SIZE           32
  77
  78 #define LONG_TYPE_SIZE          (TARGET_ILP32 ? 32 : 64)
  79
  80 #define POINTER_SIZE            (TARGET_ILP32 ? 32 : 64)
  81
  82 #define LONG_LONG_TYPE_SIZE     64
  83
  84 #define FLOAT_TYPE_SIZE         32
  85
  86 #define DOUBLE_TYPE_SIZE        64
  87
  88 #define LONG_DOUBLE_TYPE_SIZE   128
  89
  90 /* This value is the amount of bytes a caller is allowed to drop the stack
  91    before probing has to be done for stack clash protection.  */
  92 #define STACK_CLASH_CALLER_GUARD 1024
  93
  94 /* This value represents the minimum amount of bytes we expect the function's
  95    outgoing arguments to be when stack-clash is enabled.  */
  96 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8
  97
  98 /* This value controls how many pages we manually unroll the loop for when
  99    generating stack clash probes.  */
 100 #define STACK_CLASH_MAX_UNROLL_PAGES 4
 101
 102 /* The architecture reserves all bits of the address for hardware use,
 103    so the vbit must go into the delta field of pointers to member
 104    functions.  This is the same config as that in the AArch32
 105    port.  */
 106 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
 107
 108 /* Align definitions of arrays, unions and structures so that
 109    initializations and copies can be made more efficient.  This is not
 110    ABI-changing, so it only affects places where we can see the
 111    definition.  Increasing the alignment tends to introduce padding,
 112    so don't do this when optimizing for size/conserving stack space.  */
 113 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN)                      \
 114   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 115     && (TREE_CODE (EXP) == ARRAY_TYPE                                   \
 116         || TREE_CODE (EXP) == UNION_TYPE                                \
 117         || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 118
 119 /* Align global data.  */
 120 #define DATA_ALIGNMENT(EXP, ALIGN)                      \
 121   AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
 122
 123 /* Similarly, make sure that objects on the stack are sensibly aligned.  */
 124 #define LOCAL_ALIGNMENT(EXP, ALIGN)                             \
 125   AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
 126
 127 #define STRUCTURE_SIZE_BOUNDARY         8
 128
 129 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY).  */
 130 #define MALLOC_ABI_ALIGNMENT  128
 131
 132 /* Defined by the ABI */
 133 #define WCHAR_TYPE "unsigned int"
 134 #define WCHAR_TYPE_SIZE                 32
 135
 136 /* Using long long breaks -ansi and -std=c90, so these will need to be
 137    made conditional for an LLP64 ABI.  */
 138
 139 #define SIZE_TYPE       "long unsigned int"
 140
 141 #define PTRDIFF_TYPE    "long int"
 142
 143 #define PCC_BITFIELD_TYPE_MATTERS       1
 144
 145 /* Major revision number of the ARM Architecture implemented by the target.  */
 146 extern unsigned aarch64_architecture_version;
 147
 148 /* Instruction tuning/selection flags.  */
 149
 150 /* Bit values used to identify processor capabilities.  */
 151 #define AARCH64_FL_SIMD       (1 << 0)  /* Has SIMD instructions.  */
 152 #define AARCH64_FL_FP         (1 << 1)  /* Has FP.  */
 153 #define AARCH64_FL_CRYPTO     (1 << 2)  /* Has crypto.  */
 154 #define AARCH64_FL_CRC        (1 << 3)  /* Has CRC.  */
 155 /* ARMv8.1-A architecture extensions.  */
 156 #define AARCH64_FL_LSE        (1 << 4)  /* Has Large System Extensions.  */
 157 #define AARCH64_FL_RDMA       (1 << 5)  /* Has Round Double Multiply Add.  */
 158 #define AARCH64_FL_V8_1       (1 << 6)  /* Has ARMv8.1-A extensions.  */
 159 /* ARMv8.2-A architecture extensions.  */
 160 #define AARCH64_FL_V8_2       (1 << 8)  /* Has ARMv8.2-A features.  */
 161 #define AARCH64_FL_F16        (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
 162 #define AARCH64_FL_SVE        (1 << 10) /* Has Scalable Vector Extensions.  */
 163 /* ARMv8.3-A architecture extensions.  */
 164 #define AARCH64_FL_V8_3       (1 << 11)  /* Has ARMv8.3-A features.  */
 165 #define AARCH64_FL_RCPC       (1 << 12)  /* Has support for RCpc model.  */
 166 #define AARCH64_FL_DOTPROD    (1 << 13)  /* Has ARMv8.2-A Dot Product ins.  */
 167 /* New flags to split crypto into aes and sha2.  */
 168 #define AARCH64_FL_AES        (1 << 14)  /* Has Crypto AES.  */
 169 #define AARCH64_FL_SHA2       (1 << 15)  /* Has Crypto SHA2.  */
 170 /* ARMv8.4-A architecture extensions.  */
 171 #define AARCH64_FL_V8_4       (1 << 16)  /* Has ARMv8.4-A features.  */
 172 #define AARCH64_FL_SM4        (1 << 17)  /* Has ARMv8.4-A SM3 and SM4.  */
 173 #define AARCH64_FL_SHA3       (1 << 18)  /* Has ARMv8.4-a SHA3 and SHA512.  */
 174 #define AARCH64_FL_F16FML     (1 << 19)  /* Has ARMv8.4-a FP16 extensions.  */
 175 #define AARCH64_FL_RCPC8_4    (1 << 20)  /* Has ARMv8.4-a RCPC extensions.  */
 176
 177 /* Statistical Profiling extensions.  */
 178 #define AARCH64_FL_PROFILE    (1 << 21)
 179
 180 /* ARMv8.5-A architecture extensions.  */
 181 #define AARCH64_FL_V8_5       (1 << 22)  /* Has ARMv8.5-A features.  */
 182 #define AARCH64_FL_RNG        (1 << 23)  /* ARMv8.5-A Random Number Insns.  */
 183 #define AARCH64_FL_MEMTAG     (1 << 24)  /* ARMv8.5-A Memory Tagging
 184                                             Extensions.  */
 185
 186 /* Speculation Barrier instruction supported.  */
 187 #define AARCH64_FL_SB         (1 << 25)
 188
 189 /* Speculative Store Bypass Safe instruction supported.  */
 190 #define AARCH64_FL_SSBS       (1 << 26)
 191
 192 /* Execution and Data Prediction Restriction instructions supported.  */
 193 #define AARCH64_FL_PREDRES    (1 << 27)
 194
 195 /* SVE2 instruction supported.  */
 196 #define AARCH64_FL_SVE2         (1 << 28)
 197 #define AARCH64_FL_SVE2_AES     (1 << 29)
 198 #define AARCH64_FL_SVE2_SM4     (1 << 30)
 199 #define AARCH64_FL_SVE2_SHA3    (1ULL << 31)
 200 #define AARCH64_FL_SVE2_BITPERM (1ULL << 32)
 201
 202 /* Transactional Memory Extension.  */
 203 #define AARCH64_FL_TME        (1ULL << 33)  /* Has TME instructions.  */
 204
 205 /* Has FP and SIMD.  */
 206 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 207
 208 /* Has FP without SIMD.  */
 209 #define AARCH64_FL_FPQ16      (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
 210
 211 /* Architecture flags that effect instruction selection.  */
 212 #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
 213 #define AARCH64_FL_FOR_ARCH8_1                         \
 214   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \
 215    | AARCH64_FL_RDMA | AARCH64_FL_V8_1)
 216 #define AARCH64_FL_FOR_ARCH8_2                  \
 217   (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
 218 #define AARCH64_FL_FOR_ARCH8_3                  \
 219   (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
 220 #define AARCH64_FL_FOR_ARCH8_4                  \
 221   (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \
 222    | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4)
 223 #define AARCH64_FL_FOR_ARCH8_5                  \
 224   (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5     \
 225    | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES)
 226
 227 /* Macros to test ISA flags.  */
 228
 229 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
 230 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 231 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 232 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
 233 #define AARCH64_ISA_LSE            (aarch64_isa_flags & AARCH64_FL_LSE)
 234 #define AARCH64_ISA_RDMA           (aarch64_isa_flags & AARCH64_FL_RDMA)
 235 #define AARCH64_ISA_V8_2           (aarch64_isa_flags & AARCH64_FL_V8_2)
 236 #define AARCH64_ISA_F16            (aarch64_isa_flags & AARCH64_FL_F16)
 237 #define AARCH64_ISA_SVE            (aarch64_isa_flags & AARCH64_FL_SVE)
 238 #define AARCH64_ISA_SVE2           (aarch64_isa_flags & AARCH64_FL_SVE2)
 239 #define AARCH64_ISA_V8_3           (aarch64_isa_flags & AARCH64_FL_V8_3)
 240 #define AARCH64_ISA_DOTPROD        (aarch64_isa_flags & AARCH64_FL_DOTPROD)
 241 #define AARCH64_ISA_AES            (aarch64_isa_flags & AARCH64_FL_AES)
 242 #define AARCH64_ISA_SHA2           (aarch64_isa_flags & AARCH64_FL_SHA2)
 243 #define AARCH64_ISA_V8_4           (aarch64_isa_flags & AARCH64_FL_V8_4)
 244 #define AARCH64_ISA_SM4            (aarch64_isa_flags & AARCH64_FL_SM4)
 245 #define AARCH64_ISA_SHA3           (aarch64_isa_flags & AARCH64_FL_SHA3)
 246 #define AARCH64_ISA_F16FML         (aarch64_isa_flags & AARCH64_FL_F16FML)
 247 #define AARCH64_ISA_RCPC8_4        (aarch64_isa_flags & AARCH64_FL_RCPC8_4)
 248 #define AARCH64_ISA_V8_5           (aarch64_isa_flags & AARCH64_FL_V8_5)
 249 #define AARCH64_ISA_TME            (aarch64_isa_flags & AARCH64_FL_TME)
 250
 251 /* Crypto is an optional extension to AdvSIMD.  */
 252 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
 253
 254 /* SHA2 is an optional extension to AdvSIMD.  */
 255 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO)
 256
 257 /* SHA3 is an optional extension to AdvSIMD.  */
 258 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3)
 259
 260 /* AES is an optional extension to AdvSIMD.  */
 261 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO)
 262
 263 /* SM is an optional extension to AdvSIMD.  */
 264 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4)
 265
 266 /* FP16FML is an optional extension to AdvSIMD.  */
 267 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST)
 268
 269 /* CRC instructions that can be enabled through +crc arch extension.  */
 270 #define TARGET_CRC32 (AARCH64_ISA_CRC)
 271
 272 /* Atomic instructions that can be enabled through the +lse extension.  */
 273 #define TARGET_LSE (AARCH64_ISA_LSE)
 274
 275 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
 276 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
 277 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
 278
 279 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod.  */
 280 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD)
 281
 282 /* SVE instructions, enabled through +sve.  */
 283 #define TARGET_SVE (AARCH64_ISA_SVE)
 284
 285 /* SVE2 instructions, enabled through +sve2.  */
 286 #define TARGET_SVE2 (AARCH64_ISA_SVE2)
 287
 288 /* ARMv8.3-A features.  */
 289 #define TARGET_ARMV8_3  (AARCH64_ISA_V8_3)
 290
 291 /* Javascript conversion instruction from Armv8.3-a.  */
 292 #define TARGET_JSCVT    (TARGET_FLOAT && AARCH64_ISA_V8_3)
 293
 294 /* Armv8.3-a Complex number extension to AdvSIMD extensions.  */
 295 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
 296
 297 /* Floating-point rounding instructions from Armv8.5-a.  */
 298 #define TARGET_FRINT (AARCH64_ISA_V8_5 && TARGET_FLOAT)
 299
 300 /* TME instructions are enabled.  */
 301 #define TARGET_TME (AARCH64_ISA_TME)
 302
 303 /* Make sure this is always defined so we don't have to check for ifdefs
 304    but rather use normal ifs.  */
 305 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
 306 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
 307 #else
 308 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
 309 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
 310 #endif
 311
 312 /* Apply the workaround for Cortex-A53 erratum 835769.  */
 313 #define TARGET_FIX_ERR_A53_835769       \
 314   ((aarch64_fix_a53_err835769 == 2)     \
 315   ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
 316
 317 /* Make sure this is always defined so we don't have to check for ifdefs
 318    but rather use normal ifs.  */
 319 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
 320 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
 321 #else
 322 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
 323 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
 324 #endif
 325
 326 /* Apply the workaround for Cortex-A53 erratum 843419.  */
 327 #define TARGET_FIX_ERR_A53_843419       \
 328   ((aarch64_fix_a53_err843419 == 2)     \
 329   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
 330
 331 /* ARMv8.1-A Adv.SIMD support.  */
 332 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
 333
 334 /* Standard register usage.  */
 335
 336 /* 31 64-bit general purpose registers R0-R30:
 337    R30          LR (link register)
 338    R29          FP (frame pointer)
 339    R19-R28      Callee-saved registers
 340    R18          The platform register; use as temporary register.
 341    R17          IP1 The second intra-procedure-call temporary register
 342                 (can be used by call veneers and PLT code); otherwise use
 343                 as a temporary register
 344    R16          IP0 The first intra-procedure-call temporary register (can
 345                 be used by call veneers and PLT code); otherwise use as a
 346                 temporary register
 347    R9-R15       Temporary registers
 348    R8           Structure value parameter / temporary register
 349    R0-R7        Parameter/result registers
 350
 351    SP           stack pointer, encoded as X/R31 where permitted.
 352    ZR           zero register, encoded as X/R31 elsewhere
 353
 354    32 x 128-bit floating-point/vector registers
 355    V16-V31      Caller-saved (temporary) registers
 356    V8-V15       Callee-saved registers
 357    V0-V7        Parameter/result registers
 358
 359    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
 360    significant bits.  Unlike AArch32 S1 is not packed into D0, etc.
 361
 362    P0-P7        Predicate low registers: valid in all predicate contexts
 363    P8-P15       Predicate high registers: used as scratch space
 364
 365    VG           Pseudo "vector granules" register
 366
 367    VG is the number of 64-bit elements in an SVE vector.  We define
 368    it as a hard register so that we can easily map it to the DWARF VG
 369    register.  GCC internally uses the poly_int variable aarch64_sve_vg
 370    instead.  */
 371
 372 #define FIXED_REGISTERS                                 \
 373   {                                                     \
 374     0, 0, 0, 0,   0, 0, 0, 0,   /* R0 - R7 */           \
 375     0, 0, 0, 0,   0, 0, 0, 0,   /* R8 - R15 */          \
 376     0, 0, 0, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 377     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 378     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
 379     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 380     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
 381     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
 382     1, 1, 1, 1,                 /* SFP, AP, CC, VG */   \
 383     0, 0, 0, 0,   0, 0, 0, 0,   /* P0 - P7 */           \
 384     0, 0, 0, 0,   0, 0, 0, 0,   /* P8 - P15 */          \
 385   }
 386
 387 /* X30 is marked as caller-saved which is in line with regular function call
 388    behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does
 389    that for regular function calls and avoids it for sibcalls.  X30 is
 390    considered live for sibcalls; EPILOGUE_USES helps achieve that by returning
 391    true but not until function epilogues have been generated.  This ensures
 392    that X30 is available for use in leaf functions if needed.  */
 393
 394 #define CALL_USED_REGISTERS                             \
 395   {                                                     \
 396     1, 1, 1, 1,   1, 1, 1, 1,   /* R0 - R7 */           \
 397     1, 1, 1, 1,   1, 1, 1, 1,   /* R8 - R15 */          \
 398     1, 1, 1, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 399     0, 0, 0, 0,   0, 1, 1, 1,   /* R24 - R30, SP */     \
 400     1, 1, 1, 1,   1, 1, 1, 1,   /* V0 - V7 */           \
 401     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 402     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
 403     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
 404     1, 1, 1, 1,                 /* SFP, AP, CC, VG */   \
 405     1, 1, 1, 1,   1, 1, 1, 1,   /* P0 - P7 */           \
 406     1, 1, 1, 1,   1, 1, 1, 1,   /* P8 - P15 */          \
 407   }
 408
 409 #define REGISTER_NAMES                                          \
 410   {                                                             \
 411     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",      \
 412     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     \
 413     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",     \
 414     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",      \
 415     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",      \
 416     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",     \
 417     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",     \
 418     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",     \
 419     "sfp", "ap",  "cc",  "vg",                                  \
 420     "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",      \
 421     "p8",  "p9",  "p10", "p11", "p12", "p13", "p14", "p15",     \
 422   }
 423
 424 /* Generate the register aliases for core register N */
 425 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
 426                      {"w" # N, R0_REGNUM + (N)}
 427
 428 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
 429                      {"d" # N, V0_REGNUM + (N)}, \
 430                      {"s" # N, V0_REGNUM + (N)}, \
 431                      {"h" # N, V0_REGNUM + (N)}, \
 432                      {"b" # N, V0_REGNUM + (N)}, \
 433                      {"z" # N, V0_REGNUM + (N)}
 434
 435 /* Provide aliases for all of the ISA defined register name forms.
 436    These aliases are convenient for use in the clobber lists of inline
 437    asm statements.  */
 438
 439 #define ADDITIONAL_REGISTER_NAMES \
 440   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
 441     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
 442     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
 443     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
 444     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
 445     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
 446     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
 447     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
 448     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
 449     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
 450     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
 451     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
 452     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
 453     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
 454     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
 455     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
 456   }
 457
 458 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO))
 459
 460 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 461    the stack pointer does not matter.  This is only true if the function
 462    uses alloca.  */
 463 #define EXIT_IGNORE_STACK       (cfun->calls_alloca)
 464
 465 #define STATIC_CHAIN_REGNUM             R18_REGNUM
 466 #define HARD_FRAME_POINTER_REGNUM       R29_REGNUM
 467 #define FRAME_POINTER_REGNUM            SFP_REGNUM
 468 #define STACK_POINTER_REGNUM            SP_REGNUM
 469 #define ARG_POINTER_REGNUM              AP_REGNUM
 470 #define FIRST_PSEUDO_REGISTER           (P15_REGNUM + 1)
 471
 472 /* The number of (integer) argument register available.  */
 473 #define NUM_ARG_REGS                    8
 474 #define NUM_FP_ARG_REGS                 8
 475
 476 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
 477    four members.  */
 478 #define HA_MAX_NUM_FLDS         4
 479
 480 /* External dwarf register number scheme.  These number are used to
 481    identify registers in dwarf debug information, the values are
 482    defined by the AArch64 ABI.  The numbering scheme is independent of
 483    GCC's internal register numbering scheme.  */
 484
 485 #define AARCH64_DWARF_R0        0
 486
 487 /* The number of R registers, note 31! not 32.  */
 488 #define AARCH64_DWARF_NUMBER_R 31
 489
 490 #define AARCH64_DWARF_SP       31
 491 #define AARCH64_DWARF_VG       46
 492 #define AARCH64_DWARF_P0       48
 493 #define AARCH64_DWARF_V0       64
 494
 495 /* The number of V registers.  */
 496 #define AARCH64_DWARF_NUMBER_V 32
 497
 498 /* For signal frames we need to use an alternative return column.  This
 499    value must not correspond to a hard register and must be out of the
 500    range of DWARF_FRAME_REGNUM().  */
 501 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
 502   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
 503
 504 /* We add 1 extra frame register for use as the
 505    DWARF_ALT_FRAME_RETURN_COLUMN.  */
 506 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
 507
 508
 509 #define DBX_REGISTER_NUMBER(REGNO)      aarch64_dbx_register_number (REGNO)
 510 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
 511    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
 512    as the default definition in dwarf2out.c.  */
 513 #undef DWARF_FRAME_REGNUM
 514 #define DWARF_FRAME_REGNUM(REGNO)       DBX_REGISTER_NUMBER (REGNO)
 515
 516 #define DWARF_FRAME_RETURN_COLUMN       DWARF_FRAME_REGNUM (LR_REGNUM)
 517
 518 #define DWARF2_UNWIND_INFO 1
 519
 520 /* Use R0 through R3 to pass exception handling information.  */
 521 #define EH_RETURN_DATA_REGNO(N) \
 522   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
 523
 524 /* Select a format to encode pointers in exception handling data.  */
 525 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
 526   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
 527
 528 /* Output the assembly strings we want to add to a function definition.  */
 529 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)      \
 530   aarch64_declare_function_name (STR, NAME, DECL)
 531
 532 /* Output assembly strings for alias definition.  */
 533 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \
 534   aarch64_asm_output_alias (STR, DECL, TARGET)
 535
 536 /* Output assembly strings for undefined extern symbols.  */
 537 #undef ASM_OUTPUT_EXTERNAL
 538 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \
 539   aarch64_asm_output_external (STR, DECL, NAME)
 540
 541 /* Output assembly strings after .cfi_startproc is emitted.  */
 542 #define ASM_POST_CFI_STARTPROC  aarch64_post_cfi_startproc
 543
 544 /* For EH returns X4 contains the stack adjustment.  */
 545 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, R4_REGNUM)
 546 #define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
 547
 548 /* Don't use __builtin_setjmp until we've defined it.  */
 549 #undef DONT_USE_BUILTIN_SETJMP
 550 #define DONT_USE_BUILTIN_SETJMP 1
 551
 552 #undef TARGET_COMPUTE_FRAME_LAYOUT
 553 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame
 554
 555 /* Register in which the structure value is to be returned.  */
 556 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
 557
 558 /* Non-zero if REGNO is part of the Core register set.
 559
 560    The rather unusual way of expressing this check is to avoid
 561    warnings when building the compiler when R0_REGNUM is 0 and REGNO
 562    is unsigned.  */
 563 #define GP_REGNUM_P(REGNO)                                              \
 564   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
 565
 566 #define FP_REGNUM_P(REGNO)                      \
 567   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
 568
 569 #define FP_LO_REGNUM_P(REGNO)            \
 570   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
 571
 572 #define FP_LO8_REGNUM_P(REGNO)            \
 573   (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM))
 574
 575 #define PR_REGNUM_P(REGNO)\
 576   (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM))
 577
 578 #define PR_LO_REGNUM_P(REGNO)\
 579   (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM))
 580
 581 #define FP_SIMD_SAVED_REGNUM_P(REGNO)                   \
 582   (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM))
 583 \f
 584 /* Register and constant classes.  */
 585
 586 enum reg_class
 587 {
 588   NO_REGS,
 589   TAILCALL_ADDR_REGS,
 590   GENERAL_REGS,
 591   STACK_REG,
 592   POINTER_REGS,
 593   FP_LO8_REGS,
 594   FP_LO_REGS,
 595   FP_REGS,
 596   POINTER_AND_FP_REGS,
 597   PR_LO_REGS,
 598   PR_HI_REGS,
 599   PR_REGS,
 600   ALL_REGS,
 601   LIM_REG_CLASSES               /* Last */
 602 };
 603
 604 #define N_REG_CLASSES   ((int) LIM_REG_CLASSES)
 605
 606 #define REG_CLASS_NAMES                         \
 607 {                                               \
 608   "NO_REGS",                                    \
 609   "TAILCALL_ADDR_REGS",                         \
 610   "GENERAL_REGS",                               \
 611   "STACK_REG",                                  \
 612   "POINTER_REGS",                               \
 613   "FP_LO8_REGS",                                \
 614   "FP_LO_REGS",                                 \
 615   "FP_REGS",                                    \
 616   "POINTER_AND_FP_REGS",                        \
 617   "PR_LO_REGS",                                 \
 618   "PR_HI_REGS",                                 \
 619   "PR_REGS",                                    \
 620   "ALL_REGS"                                    \
 621 }
 622
 623 #define REG_CLASS_CONTENTS                                              \
 624 {                                                                       \
 625   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 626   { 0x00030000, 0x00000000, 0x00000000 },       /* TAILCALL_ADDR_REGS */\
 627   { 0x7fffffff, 0x00000000, 0x00000003 },       /* GENERAL_REGS */      \
 628   { 0x80000000, 0x00000000, 0x00000000 },       /* STACK_REG */         \
 629   { 0xffffffff, 0x00000000, 0x00000003 },       /* POINTER_REGS */      \
 630   { 0x00000000, 0x000000ff, 0x00000000 },       /* FP_LO8_REGS  */      \
 631   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */       \
 632   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */          \
 633   { 0xffffffff, 0xffffffff, 0x00000003 },       /* POINTER_AND_FP_REGS */\
 634   { 0x00000000, 0x00000000, 0x00000ff0 },       /* PR_LO_REGS */        \
 635   { 0x00000000, 0x00000000, 0x000ff000 },       /* PR_HI_REGS */        \
 636   { 0x00000000, 0x00000000, 0x000ffff0 },       /* PR_REGS */           \
 637   { 0xffffffff, 0xffffffff, 0x000fffff }        /* ALL_REGS */          \
 638 }
 639
 640 #define REGNO_REG_CLASS(REGNO)  aarch64_regno_regclass (REGNO)
 641
 642 #define INDEX_REG_CLASS GENERAL_REGS
 643 #define BASE_REG_CLASS  POINTER_REGS
 644
 645 /* Register pairs used to eliminate unneeded registers that point into
 646    the stack frame.  */
 647 #define ELIMINABLE_REGS                                                 \
 648 {                                                                       \
 649   { ARG_POINTER_REGNUM,         STACK_POINTER_REGNUM            },      \
 650   { ARG_POINTER_REGNUM,         HARD_FRAME_POINTER_REGNUM       },      \
 651   { FRAME_POINTER_REGNUM,       STACK_POINTER_REGNUM            },      \
 652   { FRAME_POINTER_REGNUM,       HARD_FRAME_POINTER_REGNUM       },      \
 653 }
 654
 655 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 656   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
 657
 658 /* CPU/ARCH option handling.  */
 659 #include "config/aarch64/aarch64-opts.h"
 660
 661 enum target_cpus
 662 {
 663 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
 664   TARGET_CPU_##INTERNAL_IDENT,
 665 #include "aarch64-cores.def"
 666   TARGET_CPU_generic
 667 };
 668
 669 /* If there is no CPU defined at configure, use generic as default.  */
 670 #ifndef TARGET_CPU_DEFAULT
 671 #define TARGET_CPU_DEFAULT \
 672   (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
 673 #endif
 674
 675 /* If inserting NOP before a mult-accumulate insn remember to adjust the
 676    length so that conditional branching code is updated appropriately.  */
 677 #define ADJUST_INSN_LENGTH(insn, length)        \
 678   do                                            \
 679     {                                           \
 680        if (aarch64_madd_needs_nop (insn))       \
 681          length += 4;                           \
 682     } while (0)
 683
 684 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)      \
 685     aarch64_final_prescan_insn (INSN);                  \
 686
 687 /* The processor for which instructions should be scheduled.  */
 688 extern enum aarch64_processor aarch64_tune;
 689
 690 /* RTL generation support.  */
 691 #define INIT_EXPANDERS aarch64_init_expanders ()
 692 \f
 693
 694 /* Stack layout; function entry, exit and calling.  */
 695 #define STACK_GROWS_DOWNWARD    1
 696
 697 #define FRAME_GROWS_DOWNWARD    1
 698
 699 #define ACCUMULATE_OUTGOING_ARGS        1
 700
 701 #define FIRST_PARM_OFFSET(FNDECL) 0
 702
 703 /* Fix for VFP */
 704 #define LIBCALL_VALUE(MODE)  \
 705   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
 706
 707 #define DEFAULT_PCC_STRUCT_RETURN 0
 708
 709 #ifdef HAVE_POLY_INT_H
 710 struct GTY (()) aarch64_frame
 711 {
 712   HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
 713
 714   /* The number of extra stack bytes taken up by register varargs.
 715      This area is allocated by the callee at the very top of the
 716      frame.  This value is rounded up to a multiple of
 717      STACK_BOUNDARY.  */
 718   HOST_WIDE_INT saved_varargs_size;
 719
 720   /* The size of the saved callee-save int/FP registers.  */
 721
 722   HOST_WIDE_INT saved_regs_size;
 723
 724   /* Offset from the base of the frame (incomming SP) to the
 725      top of the locals area.  This value is always a multiple of
 726      STACK_BOUNDARY.  */
 727   poly_int64 locals_offset;
 728
 729   /* Offset from the base of the frame (incomming SP) to the
 730      hard_frame_pointer.  This value is always a multiple of
 731      STACK_BOUNDARY.  */
 732   poly_int64 hard_fp_offset;
 733
 734   /* The size of the frame.  This value is the offset from base of the
 735      frame (incomming SP) to the stack_pointer.  This value is always
 736      a multiple of STACK_BOUNDARY.  */
 737   poly_int64 frame_size;
 738
 739   /* The size of the initial stack adjustment before saving callee-saves.  */
 740   poly_int64 initial_adjust;
 741
 742   /* The writeback value when pushing callee-save registers.
 743      It is zero when no push is used.  */
 744   HOST_WIDE_INT callee_adjust;
 745
 746   /* The offset from SP to the callee-save registers after initial_adjust.
 747      It may be non-zero if no push is used (ie. callee_adjust == 0).  */
 748   poly_int64 callee_offset;
 749
 750   /* The size of the stack adjustment after saving callee-saves.  */
 751   poly_int64 final_adjust;
 752
 753   /* Store FP,LR and setup a frame pointer.  */
 754   bool emit_frame_chain;
 755
 756   unsigned wb_candidate1;
 757   unsigned wb_candidate2;
 758
 759   bool laid_out;
 760 };
 761
 762 typedef struct GTY (()) machine_function
 763 {
 764   struct aarch64_frame frame;
 765   /* One entry for each hard register.  */
 766   bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
 767 } machine_function;
 768 #endif
 769
 770 /* Which ABI to use.  */
 771 enum aarch64_abi_type
 772 {
 773   AARCH64_ABI_LP64 = 0,
 774   AARCH64_ABI_ILP32 = 1
 775 };
 776
 777 #ifndef AARCH64_ABI_DEFAULT
 778 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
 779 #endif
 780
 781 #define TARGET_ILP32    (aarch64_abi & AARCH64_ABI_ILP32)
 782
 783 enum arm_pcs
 784 {
 785   ARM_PCS_AAPCS64,              /* Base standard AAPCS for 64 bit.  */
 786   ARM_PCS_SIMD,                 /* For aarch64_vector_pcs functions.  */
 787   ARM_PCS_TLSDESC,              /* For targets of tlsdesc calls.  */
 788   ARM_PCS_UNKNOWN
 789 };
 790
 791
 792
 793
 794 /* We can't use machine_mode inside a generator file because it
 795    hasn't been created yet; we shouldn't be using any code that
 796    needs the real definition though, so this ought to be safe.  */
 797 #ifdef GENERATOR_FILE
 798 #define MACHMODE int
 799 #else
 800 #include "insn-modes.h"
 801 #define MACHMODE machine_mode
 802 #endif
 803
 804 #ifndef USED_FOR_TARGET
 805 /* AAPCS related state tracking.  */
 806 typedef struct
 807 {
 808   enum arm_pcs pcs_variant;
 809   int aapcs_arg_processed;      /* No need to lay out this argument again.  */
 810   int aapcs_ncrn;               /* Next Core register number.  */
 811   int aapcs_nextncrn;           /* Next next core register number.  */
 812   int aapcs_nvrn;               /* Next Vector register number.  */
 813   int aapcs_nextnvrn;           /* Next Next Vector register number.  */
 814   rtx aapcs_reg;                /* Register assigned to this argument.  This
 815                                    is NULL_RTX if this parameter goes on
 816                                    the stack.  */
 817   MACHMODE aapcs_vfp_rmode;
 818   int aapcs_stack_words;        /* If the argument is passed on the stack, this
 819                                    is the number of words needed, after rounding
 820                                    up.  Only meaningful when
 821                                    aapcs_reg == NULL_RTX.  */
 822   int aapcs_stack_size;         /* The total size (in words, per 8 byte) of the
 823                                    stack arg area so far.  */
 824 } CUMULATIVE_ARGS;
 825 #endif
 826
 827 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 828   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
 829
 830 #define PAD_VARARGS_DOWN        0
 831
 832 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 833   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
 834
 835 #define FUNCTION_ARG_REGNO_P(REGNO) \
 836   aarch64_function_arg_regno_p(REGNO)
 837 \f
 838
 839 /* ISA Features.  */
 840
 841 /* Addressing modes, etc.  */
 842 #define HAVE_POST_INCREMENT     1
 843 #define HAVE_PRE_INCREMENT      1
 844 #define HAVE_POST_DECREMENT     1
 845 #define HAVE_PRE_DECREMENT      1
 846 #define HAVE_POST_MODIFY_DISP   1
 847 #define HAVE_PRE_MODIFY_DISP    1
 848
 849 #define MAX_REGS_PER_ADDRESS    2
 850
 851 #define CONSTANT_ADDRESS_P(X)           aarch64_constant_address_p(X)
 852
 853 #define REGNO_OK_FOR_BASE_P(REGNO)      \
 854   aarch64_regno_ok_for_base_p (REGNO, true)
 855
 856 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 857   aarch64_regno_ok_for_index_p (REGNO, true)
 858
 859 #define LEGITIMATE_PIC_OPERAND_P(X) \
 860   aarch64_legitimate_pic_operand_p (X)
 861
 862 #define CASE_VECTOR_MODE Pmode
 863
 864 #define DEFAULT_SIGNED_CHAR 0
 865
 866 /* An integer expression for the size in bits of the largest integer machine
 867    mode that should actually be used.  We allow pairs of registers.  */
 868 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 869
 870 /* Maximum bytes moved by a single instruction (load/store pair).  */
 871 #define MOVE_MAX (UNITS_PER_WORD * 2)
 872
 873 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
 874 #define AARCH64_CALL_RATIO 8
 875
 876 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
 877    move_by_pieces will continually copy the largest safe chunks.  So a
 878    7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
 879    for both size and speed of copy, so we will instead use the "cpymem"
 880    standard name to implement the copy.  This logic does not apply when
 881    targeting -mstrict-align, so keep a sensible default in that case.  */
 882 #define MOVE_RATIO(speed) \
 883   (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
 884
 885 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 886    of the length of a memset call, but use the default otherwise.  */
 887 #define CLEAR_RATIO(speed) \
 888   ((speed) ? 15 : AARCH64_CALL_RATIO)
 889
 890 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
 891    optimizing for size adjust the ratio to account for the overhead of loading
 892    the constant.  */
 893 #define SET_RATIO(speed) \
 894   ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
 895
 896 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
 897    rarely a good idea in straight-line code since it adds an extra address
 898    dependency between each instruction.  Better to use incrementing offsets.  */
 899 #define USE_LOAD_POST_INCREMENT(MODE)   0
 900 #define USE_LOAD_POST_DECREMENT(MODE)   0
 901 #define USE_LOAD_PRE_INCREMENT(MODE)    0
 902 #define USE_LOAD_PRE_DECREMENT(MODE)    0
 903 #define USE_STORE_POST_INCREMENT(MODE)  0
 904 #define USE_STORE_POST_DECREMENT(MODE)  0
 905 #define USE_STORE_PRE_INCREMENT(MODE)   0
 906 #define USE_STORE_PRE_DECREMENT(MODE)   0
 907
 908 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
 909    The assigned word_mode is DImode but operations narrower than SImode
 910    behave as 32-bit operations if using the W-form of the registers rather
 911    than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
 912    expects.  */
 913 #define WORD_REGISTER_OPERATIONS 0
 914
 915 /* Define if loading from memory in MODE, an integral mode narrower than
 916    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
 917    macro should be the code that says which one of the two operations is
 918    implicitly done, or UNKNOWN if none.  */
 919 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 920
 921 /* Define this macro to be non-zero if instructions will fail to work
 922    if given data not on the nominal alignment.  */
 923 #define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN
 924
 925 /* Define this macro to be non-zero if accessing less than a word of
 926    memory is no faster than accessing a word of memory, i.e., if such
 927    accesses require more than one instruction or if there is no
 928    difference in cost.
 929    Although there's no difference in instruction count or cycles,
 930    in AArch64 we don't want to expand to a sub-word to a 64-bit access
 931    if we don't have to, for power-saving reasons.  */
 932 #define SLOW_BYTE_ACCESS                0
 933
 934 #define NO_FUNCTION_CSE 1
 935
 936 /* Specify the machine mode that the hardware addresses have.
 937    After generation of rtl, the compiler makes no further distinction
 938    between pointers and any other objects of this machine mode.  */
 939 #define Pmode           DImode
 940
 941 /* A C expression whose value is zero if pointers that need to be extended
 942    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
 943    greater then zero if they are zero-extended and less then zero if the
 944    ptr_extend instruction should be used.  */
 945 #define POINTERS_EXTEND_UNSIGNED 1
 946
 947 /* Mode of a function address in a call instruction (for indexing purposes).  */
 948 #define FUNCTION_MODE   Pmode
 949
 950 #define SELECT_CC_MODE(OP, X, Y)        aarch64_select_cc_mode (OP, X, Y)
 951
 952 #define REVERSIBLE_CC_MODE(MODE) 1
 953
 954 #define REVERSE_CONDITION(CODE, MODE)           \
 955   (((MODE) == CCFPmode || (MODE) == CCFPEmode)  \
 956    ? reverse_condition_maybe_unordered (CODE)   \
 957    : reverse_condition (CODE))
 958
 959 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 960   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 961 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 962   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 963
 964 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 965
 966 #define RETURN_ADDR_RTX aarch64_return_addr
 967
 968 /* BTI c + 3 insns + 2 pointer-sized entries.  */
 969 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
 970
 971 /* Trampolines contain dwords, so must be dword aligned.  */
 972 #define TRAMPOLINE_ALIGNMENT 64
 973
 974 /* Put trampolines in the text section so that mapping symbols work
 975    correctly.  */
 976 #define TRAMPOLINE_SECTION text_section
 977
 978 /* To start with.  */
 979 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
 980   (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
 981 \f
 982
 983 /* Assembly output.  */
 984
 985 /* For now we'll make all jump tables pc-relative.  */
 986 #define CASE_VECTOR_PC_RELATIVE 1
 987
 988 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)        \
 989   ((min < -0x1fff0 || max > 0x1fff0) ? SImode           \
 990    : (min < -0x1f0 || max > 0x1f0) ? HImode             \
 991    : QImode)
 992
 993 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
 994 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
 995
 996 #define MCOUNT_NAME "_mcount"
 997
 998 #define NO_PROFILE_COUNTERS 1
 999
1000 /* Emit rtl for profiling.  Output assembler code to FILE
1001    to call "_mcount" for profiling a function entry.  */
1002 #define PROFILE_HOOK(LABEL)                                             \
1003   {                                                                     \
1004     rtx fun, lr;                                                        \
1005     lr = get_hard_reg_initial_val (Pmode, LR_REGNUM);                   \
1006     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
1007     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);           \
1008   }
1009
1010 /* All the work done in PROFILE_HOOK, but still required.  */
1011 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
1012
1013 /* For some reason, the Linux headers think they know how to define
1014    these macros.  They don't!!!  */
1015 #undef ASM_APP_ON
1016 #undef ASM_APP_OFF
1017 #define ASM_APP_ON      "\t" ASM_COMMENT_START " Start of user assembly\n"
1018 #define ASM_APP_OFF     "\t" ASM_COMMENT_START " End of user assembly\n"
1019
1020 #define CONSTANT_POOL_BEFORE_FUNCTION 0
1021
1022 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
1023    should be undefined in aarch64-linux.h and a clear_cache pattern
1024    implmented to emit either the call to __aarch64_sync_cache_range()
1025    directly or preferably the appropriate sycall or cache clear
1026    instructions inline.  */
1027 #define CLEAR_INSN_CACHE(beg, end)                              \
1028   extern void  __aarch64_sync_cache_range (void *, void *);     \
1029   __aarch64_sync_cache_range (beg, end)
1030
1031 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
1032
1033 /* Choose appropriate mode for caller saves, so we do the minimum
1034    required size of load/store.  */
1035 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1036   aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
1037
1038 #undef SWITCHABLE_TARGET
1039 #define SWITCHABLE_TARGET 1
1040
1041 /* Check TLS Descriptors mechanism is selected.  */
1042 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
1043
1044 extern enum aarch64_code_model aarch64_cmodel;
1045
1046 /* When using the tiny addressing model conditional and unconditional branches
1047    can span the whole of the available address space (1MB).  */
1048 #define HAS_LONG_COND_BRANCH                            \
1049   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
1050    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1051
1052 #define HAS_LONG_UNCOND_BRANCH                          \
1053   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
1054    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1055
1056 #define TARGET_SUPPORTS_WIDE_INT 1
1057
1058 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
1059 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
1060   ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1061    || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
1062    || (MODE) == DFmode)
1063
1064 /* Modes valid for AdvSIMD Q registers.  */
1065 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
1066   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1067    || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
1068    || (MODE) == V2DFmode)
1069
1070 #define ENDIAN_LANE_N(NUNITS, N) \
1071   (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N)
1072
1073 /* Support for a configure-time default CPU, etc.  We currently support
1074    --with-arch and --with-cpu.  Both are ignored if either is specified
1075    explicitly on the command line at run time.  */
1076 #define OPTION_DEFAULT_SPECS                            \
1077   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" },  \
1078   {"cpu",  "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },
1079
1080 #define MCPU_TO_MARCH_SPEC \
1081    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
1082
1083 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
1084 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
1085   { "rewrite_mcpu", aarch64_rewrite_mcpu },
1086
1087 #if defined(__aarch64__)
1088 extern const char *host_detect_local_cpu (int argc, const char **argv);
1089 #define HAVE_LOCAL_CPU_DETECT
1090 # define EXTRA_SPEC_FUNCTIONS                                           \
1091   { "local_cpu_detect", host_detect_local_cpu },                        \
1092   MCPU_TO_MARCH_SPEC_FUNCTIONS
1093
1094 # define MCPU_MTUNE_NATIVE_SPECS                                        \
1095    " %{march=native:%<march=native %:local_cpu_detect(arch)}"           \
1096    " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"              \
1097    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
1098 #else
1099 # define MCPU_MTUNE_NATIVE_SPECS ""
1100 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
1101 #endif
1102
1103 #define ASM_CPU_SPEC \
1104    MCPU_TO_MARCH_SPEC
1105
1106 #define EXTRA_SPECS                                             \
1107   { "asm_cpu_spec",             ASM_CPU_SPEC }
1108
1109 #define ASM_OUTPUT_POOL_EPILOGUE  aarch64_asm_output_pool_epilogue
1110
1111 /* This type is the user-visible __fp16, and a pointer to that type.  We
1112    need it in many places in the backend.  Defined in aarch64-builtins.c.  */
1113 extern tree aarch64_fp16_type_node;
1114 extern tree aarch64_fp16_ptr_type_node;
1115
1116 /* The generic unwind code in libgcc does not initialize the frame pointer.
1117    So in order to unwind a function using a frame pointer, the very first
1118    function that is unwound must save the frame pointer.  That way the frame
1119    pointer is restored and its value is now valid - otherwise _Unwind_GetGR
1120    crashes.  Libgcc can now be safely built with -fomit-frame-pointer.  */
1121 #define LIBGCC2_UNWIND_ATTRIBUTE \
1122   __attribute__((optimize ("no-omit-frame-pointer")))
1123
1124 #ifndef USED_FOR_TARGET
1125 extern poly_uint16 aarch64_sve_vg;
1126
1127 /* The number of bits and bytes in an SVE vector.  */
1128 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64))
1129 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8))
1130
1131 /* The number of bytes in an SVE predicate.  */
1132 #define BYTES_PER_SVE_PRED aarch64_sve_vg
1133
1134 /* The SVE mode for a vector of bytes.  */
1135 #define SVE_BYTE_MODE VNx16QImode
1136
1137 /* The maximum number of bytes in a fixed-size vector.  This is 256 bytes
1138    (for -msve-vector-bits=2048) multiplied by the maximum number of
1139    vectors in a structure mode (4).
1140
1141    This limit must not be used for variable-size vectors, since
1142    VL-agnostic code must work with arbitary vector lengths.  */
1143 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4)
1144 #endif
1145
1146 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE)
1147
1148 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the
1149    outgoing arguments if stack clash protection is enabled.  This is essential
1150    as the extra arg space allows us to skip a check in alloca.  */
1151 #undef STACK_DYNAMIC_OFFSET
1152 #define STACK_DYNAMIC_OFFSET(FUNDECL)                      \
1153    ((flag_stack_clash_protection                           \
1154      && cfun->calls_alloca                                 \
1155      && known_lt (crtl->outgoing_args_size,                \
1156                   STACK_CLASH_MIN_BYTES_OUTGOING_ARGS))    \
1157     ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS,       \
1158                 STACK_BOUNDARY / BITS_PER_UNIT)            \
1159     : (crtl->outgoing_args_size + STACK_POINTER_OFFSET))
1160
1161 #endif /* GCC_AARCH64_H */