gcc/config/aarch64/constraints.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_register_constraint "k" "STACK_REG"
  22   "@internal The stack register.")
  23
  24 (define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
  25   "@internal Registers suitable for an indirect tail call")
  26
  27 (define_register_constraint "w" "FP_REGS"
  28   "Floating point and SIMD vector registers.")
  29
  30 (define_register_constraint "Upa" "PR_REGS"
  31   "SVE predicate registers p0 - p15.")
  32
  33 (define_register_constraint "Upl" "PR_LO_REGS"
  34   "SVE predicate registers p0 - p7.")
  35
  36 (define_register_constraint "x" "FP_LO_REGS"
  37   "Floating point and SIMD vector registers V0 - V15.")
  38
  39 (define_register_constraint "y" "FP_LO8_REGS"
  40   "Floating point and SIMD vector registers V0 - V7.")
  41
  42 (define_constraint "I"
  43  "A constant that can be used with an ADD operation."
  44  (and (match_code "const_int")
  45       (match_test "aarch64_uimm12_shift (ival)")))
  46
  47 (define_constraint "Uaa"
  48   "@internal A constant that matches two uses of add instructions."
  49   (and (match_code "const_int")
  50        (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
  51
  52 (define_constraint "Uai"
  53   "@internal
  54    A constraint that matches a VG-based constant that can be added by
  55    a single INC or DEC."
  56   (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate"))
  57
  58 (define_constraint "Uav"
  59   "@internal
  60    A constraint that matches a VG-based constant that can be added by
  61    a single ADDVL or ADDPL."
  62  (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))
  63
  64 (define_constraint "Uat"
  65   "@internal
  66    A constraint that matches a VG-based constant that can be added by
  67    using multiple instructions, with one temporary register."
  68  (match_operand 0 "aarch64_split_add_offset_immediate"))
  69
  70 (define_constraint "J"
  71  "A constant that can be used with a SUB operation (once negated)."
  72  (and (match_code "const_int")
  73       (match_test "aarch64_uimm12_shift (-ival)")))
  74
  75 ;; We can't use the mode of a CONST_INT to determine the context in
  76 ;; which it is being used, so we must have a separate constraint for
  77 ;; each context.
  78
  79 (define_constraint "K"
  80  "A constant that can be used with a 32-bit logical operation."
  81  (and (match_code "const_int")
  82       (match_test "aarch64_bitmask_imm (ival, SImode)")))
  83
  84 (define_constraint "L"
  85  "A constant that can be used with a 64-bit logical operation."
  86  (and (match_code "const_int")
  87       (match_test "aarch64_bitmask_imm (ival, DImode)")))
  88
  89 (define_constraint "M"
  90  "A constant that can be used with a 32-bit MOV immediate operation."
  91  (and (match_code "const_int")
  92       (match_test "aarch64_move_imm (ival, SImode)")))
  93
  94 (define_constraint "N"
  95  "A constant that can be used with a 64-bit MOV immediate operation."
  96  (and (match_code "const_int")
  97       (match_test "aarch64_move_imm (ival, DImode)")))
  98
  99 (define_constraint "Uti"
 100  "A constant that can be used with a 128-bit MOV immediate operation."
 101  (and (ior (match_code "const_int")
 102            (match_code "const_wide_int"))
 103       (match_test "aarch64_mov128_immediate (op)")))
 104
 105 (define_constraint "UsO"
 106  "A constant that can be used with a 32-bit and operation."
 107  (and (match_code "const_int")
 108       (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
 109
 110 (define_constraint "UsP"
 111  "A constant that can be used with a 64-bit and operation."
 112  (and (match_code "const_int")
 113       (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
 114
 115 (define_constraint "S"
 116   "A constraint that matches an absolute symbolic address."
 117   (and (match_code "const,symbol_ref,label_ref")
 118        (match_test "aarch64_symbolic_address_p (op)")))
 119
 120 (define_constraint "Y"
 121   "Floating point constant zero."
 122   (and (match_code "const_double")
 123        (match_test "aarch64_float_const_zero_rtx_p (op)")))
 124
 125 (define_constraint "Z"
 126   "Integer or floating-point constant zero."
 127   (match_test "op == CONST0_RTX (GET_MODE (op))"))
 128
 129 (define_constraint "Ush"
 130   "A constraint that matches an absolute symbolic address high part."
 131   (and (match_code "high")
 132        (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
 133
 134 (define_constraint "Usa"
 135   "@internal
 136    A constraint that matches an absolute symbolic address that can be
 137    loaded by a single ADR."
 138   (and (match_code "const,symbol_ref,label_ref")
 139        (match_test "aarch64_symbolic_address_p (op)")
 140        (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
 141
 142 (define_constraint "Uss"
 143   "@internal
 144   A constraint that matches an immediate shift constant in SImode."
 145   (and (match_code "const_int")
 146        (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
 147
 148 (define_constraint "Usn"
 149  "A constant that can be used with a CCMN operation (once negated)."
 150  (and (match_code "const_int")
 151       (match_test "IN_RANGE (ival, -31, 0)")))
 152
 153 (define_constraint "Usd"
 154   "@internal
 155   A constraint that matches an immediate shift constant in DImode."
 156   (and (match_code "const_int")
 157        (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
 158
 159 (define_constraint "Usf"
 160   "@internal Usf is a symbol reference under the context where plt stub allowed."
 161   (and (match_code "symbol_ref")
 162        (match_test "!(aarch64_is_noplt_call_p (op)
 163                       || aarch64_is_long_call_p (op))")))
 164
 165 (define_constraint "Usg"
 166   "@internal
 167   A constraint that matches an immediate right shift constant in SImode
 168   suitable for a SISD instruction."
 169   (and (match_code "const_int")
 170        (match_test "IN_RANGE (ival, 1, 31)")))
 171
 172 (define_constraint "Usj"
 173   "@internal
 174   A constraint that matches an immediate right shift constant in DImode
 175   suitable for a SISD instruction."
 176   (and (match_code "const_int")
 177        (match_test "IN_RANGE (ival, 1, 63)")))
 178
 179 (define_constraint "UsM"
 180   "@internal
 181   A constraint that matches the immediate constant -1."
 182   (match_test "op == constm1_rtx"))
 183
 184 (define_constraint "Ulc"
 185  "@internal
 186  A constraint that matches a constant integer whose bits are consecutive ones
 187  from the MSB."
 188  (and (match_code "const_int")
 189       (match_test "aarch64_high_bits_all_ones_p (ival)")))
 190
 191 (define_constraint "Usv"
 192   "@internal
 193    A constraint that matches a VG-based constant that can be loaded by
 194    a single CNT[BHWD]."
 195  (match_operand 0 "aarch64_sve_cnt_immediate"))
 196
 197 (define_constraint "Usi"
 198   "@internal
 199  A constraint that matches an immediate operand valid for
 200  the SVE INDEX instruction."
 201  (match_operand 0 "aarch64_sve_index_immediate"))
 202
 203 (define_constraint "Ui1"
 204   "@internal
 205   A constraint that matches the immediate constant +1."
 206   (match_test "op == const1_rtx"))
 207
 208 (define_constraint "Ui2"
 209   "@internal
 210   A constraint that matches the integers 0...3."
 211   (and (match_code "const_int")
 212        (match_test "(unsigned HOST_WIDE_INT) ival <= 3")))
 213
 214 (define_constraint "Ui3"
 215   "@internal
 216   A constraint that matches the integers 0...4."
 217   (and (match_code "const_int")
 218        (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
 219
 220 (define_constraint "Ui7"
 221   "@internal
 222   A constraint that matches the integers 0...7."
 223   (and (match_code "const_int")
 224        (match_test "(unsigned HOST_WIDE_INT) ival <= 7")))
 225
 226 (define_constraint "Up3"
 227   "@internal
 228   A constraint that matches the integers 2^(0...4)."
 229   (and (match_code "const_int")
 230        (match_test "(unsigned) exact_log2 (ival) <= 4")))
 231
 232 (define_memory_constraint "Q"
 233  "A memory address which uses a single base register with no offset."
 234  (and (match_code "mem")
 235       (match_test "REG_P (XEXP (op, 0))")))
 236
 237 (define_memory_constraint "Ust"
 238   "@internal
 239   A memory address with 9bit unscaled offset."
 240   (match_operand 0 "aarch64_9bit_offset_memory_operand"))
 241
 242 (define_memory_constraint "Ump"
 243   "@internal
 244   A memory address suitable for a load/store pair operation."
 245   (and (match_code "mem")
 246        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 247                                                   true, ADDR_QUERY_LDP_STP)")))
 248
 249 ;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP
 250 ;; as a vector-concat.  The address mode uses the same constraints as if it
 251 ;; were for a single value.
 252 (define_memory_constraint "Umn"
 253   "@internal
 254   A memory address suitable for a load/store pair operation."
 255   (and (match_code "mem")
 256        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 257                                                   true,
 258                                                   ADDR_QUERY_LDP_STP_N)")))
 259
 260 (define_memory_constraint "Utr"
 261   "@internal
 262    An address valid for SVE LDR and STR instructions (as distinct from
 263    LD[1234] and ST[1234] patterns)."
 264   (and (match_code "mem")
 265        (match_test "aarch64_sve_ldr_operand_p (op)")))
 266
 267 (define_memory_constraint "Utv"
 268   "@internal
 269    An address valid for loading/storing opaque structure
 270    types wider than TImode."
 271   (and (match_code "mem")
 272        (match_test "aarch64_simd_mem_operand_p (op)")))
 273
 274 (define_memory_constraint "Utq"
 275   "@internal
 276    An address valid for loading or storing a 128-bit AdvSIMD register"
 277   (and (match_code "mem")
 278        (match_test "aarch64_legitimate_address_p (V2DImode,
 279                                                   XEXP (op, 0), 1)")))
 280
 281 (define_memory_constraint "UtQ"
 282   "@internal
 283    An address valid for SVE LD1RQs."
 284   (and (match_code "mem")
 285        (match_test "aarch64_sve_ld1rq_operand_p (op)")))
 286
 287 (define_memory_constraint "Uty"
 288   "@internal
 289    An address valid for SVE LD1Rs."
 290   (and (match_code "mem")
 291        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 292
 293 (define_memory_constraint "Utx"
 294   "@internal
 295    An address valid for SVE structure mov patterns (as distinct from
 296    LD[234] and ST[234] patterns)."
 297   (match_operand 0 "aarch64_sve_struct_memory_operand"))
 298
 299 (define_constraint "Ufc"
 300   "A floating point constant which can be used with an\
 301    FMOV immediate operation."
 302   (and (match_code "const_double,const_vector")
 303        (match_test "aarch64_float_const_representable_p (op)")))
 304
 305 (define_constraint "Uvi"
 306   "A floating point constant which can be used with a\
 307    MOVI immediate operation."
 308   (and (match_code "const_double")
 309        (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
 310
 311 (define_constraint "Do"
 312   "@internal
 313    A constraint that matches vector of immediates for orr."
 314  (and (match_code "const_vector")
 315       (match_test "aarch64_simd_valid_immediate (op, NULL,
 316                                                  AARCH64_CHECK_ORR)")))
 317
 318 (define_constraint "Db"
 319   "@internal
 320    A constraint that matches vector of immediates for bic."
 321  (and (match_code "const_vector")
 322       (match_test "aarch64_simd_valid_immediate (op, NULL,
 323                                                  AARCH64_CHECK_BIC)")))
 324
 325 (define_constraint "Dn"
 326   "@internal
 327  A constraint that matches vector of immediates."
 328  (and (match_code "const,const_vector")
 329       (match_test "aarch64_simd_valid_immediate (op, NULL)")))
 330
 331 (define_constraint "Dh"
 332   "@internal
 333  A constraint that matches an immediate operand valid for\
 334  AdvSIMD scalar move in HImode."
 335  (and (match_code "const_int")
 336       (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
 337                                                  HImode)")))
 338
 339 (define_constraint "Dq"
 340   "@internal
 341  A constraint that matches an immediate operand valid for\
 342  AdvSIMD scalar move in QImode."
 343  (and (match_code "const_int")
 344       (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
 345                                                  QImode)")))
 346
 347 (define_constraint "Dt"
 348   "@internal
 349  A const_double which is the reciprocal of an exact power of two, can be
 350  used in an scvtf with fract bits operation"
 351  (and (match_code "const_double")
 352       (match_test "aarch64_fpconst_pow2_recip (op) > 0")))
 353
 354 (define_constraint "Dl"
 355   "@internal
 356  A constraint that matches vector of immediates for left shifts."
 357  (and (match_code "const,const_vector")
 358       (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
 359                                                  true)")))
 360
 361 (define_constraint "Dr"
 362   "@internal
 363  A constraint that matches vector of immediates for right shifts."
 364  (and (match_code "const,const_vector")
 365       (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
 366                                                  false)")))
 367 (define_constraint "Dz"
 368   "@internal
 369  A constraint that matches a vector of immediate zero."
 370  (and (match_code "const,const_vector")
 371       (match_test "op == CONST0_RTX (GET_MODE (op))")))
 372
 373 (define_constraint "Dm"
 374   "@internal
 375  A constraint that matches a vector of immediate minus one."
 376  (and (match_code "const,const_vector")
 377       (match_test "op == CONST1_RTX (GET_MODE (op))")))
 378
 379 (define_constraint "Dd"
 380   "@internal
 381  A constraint that matches an integer immediate operand valid\
 382  for AdvSIMD scalar operations in DImode."
 383  (and (match_code "const_int")
 384       (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
 385
 386 (define_constraint "Ds"
 387   "@internal
 388  A constraint that matches an integer immediate operand valid\
 389  for AdvSIMD scalar operations in SImode."
 390  (and (match_code "const_int")
 391       (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
 392
 393 (define_address_constraint "Dp"
 394   "@internal
 395  An address valid for a prefetch instruction."
 396  (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))
 397
 398 (define_constraint "vsa"
 399   "@internal
 400    A constraint that matches an immediate operand valid for SVE
 401    arithmetic instructions."
 402  (match_operand 0 "aarch64_sve_arith_immediate"))
 403
 404 (define_constraint "vsb"
 405   "@internal
 406    A constraint that matches an immediate operand valid for SVE UMAX
 407    and UMIN operations."
 408  (match_operand 0 "aarch64_sve_vsb_immediate"))
 409
 410 (define_constraint "vsc"
 411   "@internal
 412    A constraint that matches a signed immediate operand valid for SVE
 413    CMP instructions."
 414  (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))
 415
 416 (define_constraint "vss"
 417   "@internal
 418    A constraint that matches a signed immediate operand valid for SVE
 419    DUP instructions."
 420  (match_test "aarch64_sve_dup_immediate_p (op)"))
 421
 422 (define_constraint "vsd"
 423   "@internal
 424    A constraint that matches an unsigned immediate operand valid for SVE
 425    CMP instructions."
 426  (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))
 427
 428 (define_constraint "vsi"
 429   "@internal
 430    A constraint that matches a vector count operand valid for SVE INC and
 431    DEC instructions."
 432  (match_operand 0 "aarch64_sve_vector_inc_dec_immediate"))
 433
 434 (define_constraint "vsn"
 435   "@internal
 436    A constraint that matches an immediate operand whose negative
 437    is valid for SVE SUB instructions."
 438  (match_operand 0 "aarch64_sve_sub_arith_immediate"))
 439
 440 (define_constraint "vsl"
 441   "@internal
 442    A constraint that matches an immediate operand valid for SVE logical
 443    operations."
 444  (match_operand 0 "aarch64_sve_logical_immediate"))
 445
 446 (define_constraint "vsm"
 447   "@internal
 448    A constraint that matches an immediate operand valid for SVE MUL,
 449    SMAX and SMIN operations."
 450  (match_operand 0 "aarch64_sve_vsm_immediate"))
 451
 452 (define_constraint "vsA"
 453   "@internal
 454    A constraint that matches an immediate operand valid for SVE FADD
 455    and FSUB operations."
 456  (match_operand 0 "aarch64_sve_float_arith_immediate"))
 457
 458 ;; "B" for "bound".
 459 (define_constraint "vsB"
 460   "@internal
 461    A constraint that matches an immediate operand valid for SVE FMAX
 462    and FMIN operations."
 463  (match_operand 0 "aarch64_sve_float_maxmin_immediate"))
 464
 465 (define_constraint "vsM"
 466   "@internal
 467    A constraint that matches an immediate operand valid for SVE FMUL
 468    operations."
 469  (match_operand 0 "aarch64_sve_float_mul_immediate"))
 470
 471 (define_constraint "vsN"
 472   "@internal
 473    A constraint that matches the negative of vsA"
 474  (match_operand 0 "aarch64_sve_float_negated_arith_immediate"))