1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_register_constraint "k" "STACK_REG"
22 "@internal The stack register.")
24 (define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
25 "@internal Registers suitable for an indirect tail call")
27 (define_register_constraint "w" "FP_REGS"
28 "Floating point and SIMD vector registers.")
30 (define_register_constraint "Upa" "PR_REGS"
31 "SVE predicate registers p0 - p15.")
33 (define_register_constraint "Upl" "PR_LO_REGS"
34 "SVE predicate registers p0 - p7.")
36 (define_register_constraint "x" "FP_LO_REGS"
37 "Floating point and SIMD vector registers V0 - V15.")
39 (define_register_constraint "y" "FP_LO8_REGS"
40 "Floating point and SIMD vector registers V0 - V7.")
42 (define_constraint "I"
43 "A constant that can be used with an ADD operation."
44 (and (match_code "const_int")
45 (match_test "aarch64_uimm12_shift (ival)")))
47 (define_constraint "Uaa"
48 "@internal A constant that matches two uses of add instructions."
49 (and (match_code "const_int")
50 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
52 (define_constraint "Uai"
54 A constraint that matches a VG-based constant that can be added by
56 (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate"))
58 (define_constraint "Uav"
60 A constraint that matches a VG-based constant that can be added by
61 a single ADDVL or ADDPL."
62 (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))
64 (define_constraint "Uat"
66 A constraint that matches a VG-based constant that can be added by
67 using multiple instructions, with one temporary register."
68 (match_operand 0 "aarch64_split_add_offset_immediate"))
70 (define_constraint "J"
71 "A constant that can be used with a SUB operation (once negated)."
72 (and (match_code "const_int")
73 (match_test "aarch64_uimm12_shift (-ival)")))
75 ;; We can't use the mode of a CONST_INT to determine the context in
76 ;; which it is being used, so we must have a separate constraint for
79 (define_constraint "K"
80 "A constant that can be used with a 32-bit logical operation."
81 (and (match_code "const_int")
82 (match_test "aarch64_bitmask_imm (ival, SImode)")))
84 (define_constraint "L"
85 "A constant that can be used with a 64-bit logical operation."
86 (and (match_code "const_int")
87 (match_test "aarch64_bitmask_imm (ival, DImode)")))
89 (define_constraint "M"
90 "A constant that can be used with a 32-bit MOV immediate operation."
91 (and (match_code "const_int")
92 (match_test "aarch64_move_imm (ival, SImode)")))
94 (define_constraint "N"
95 "A constant that can be used with a 64-bit MOV immediate operation."
96 (and (match_code "const_int")
97 (match_test "aarch64_move_imm (ival, DImode)")))
99 (define_constraint "Uti"
100 "A constant that can be used with a 128-bit MOV immediate operation."
101 (and (ior (match_code "const_int")
102 (match_code "const_wide_int"))
103 (match_test "aarch64_mov128_immediate (op)")))
105 (define_constraint "UsO"
106 "A constant that can be used with a 32-bit and operation."
107 (and (match_code "const_int")
108 (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
110 (define_constraint "UsP"
111 "A constant that can be used with a 64-bit and operation."
112 (and (match_code "const_int")
113 (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
115 (define_constraint "S"
116 "A constraint that matches an absolute symbolic address."
117 (and (match_code "const,symbol_ref,label_ref")
118 (match_test "aarch64_symbolic_address_p (op)")))
120 (define_constraint "Y"
121 "Floating point constant zero."
122 (and (match_code "const_double")
123 (match_test "aarch64_float_const_zero_rtx_p (op)")))
125 (define_constraint "Z"
126 "Integer or floating-point constant zero."
127 (match_test "op == CONST0_RTX (GET_MODE (op))"))
129 (define_constraint "Ush"
130 "A constraint that matches an absolute symbolic address high part."
131 (and (match_code "high")
132 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
134 (define_constraint "Usa"
136 A constraint that matches an absolute symbolic address that can be
137 loaded by a single ADR."
138 (and (match_code "const,symbol_ref,label_ref")
139 (match_test "aarch64_symbolic_address_p (op)")
140 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
142 (define_constraint "Uss"
144 A constraint that matches an immediate shift constant in SImode."
145 (and (match_code "const_int")
146 (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
148 (define_constraint "Usn"
149 "A constant that can be used with a CCMN operation (once negated)."
150 (and (match_code "const_int")
151 (match_test "IN_RANGE (ival, -31, 0)")))
153 (define_constraint "Usd"
155 A constraint that matches an immediate shift constant in DImode."
156 (and (match_code "const_int")
157 (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
159 (define_constraint "Usf"
160 "@internal Usf is a symbol reference under the context where plt stub allowed."
161 (and (match_code "symbol_ref")
162 (match_test "!(aarch64_is_noplt_call_p (op)
163 || aarch64_is_long_call_p (op))")))
165 (define_constraint "Usg"
167 A constraint that matches an immediate right shift constant in SImode
168 suitable for a SISD instruction."
169 (and (match_code "const_int")
170 (match_test "IN_RANGE (ival, 1, 31)")))
172 (define_constraint "Usj"
174 A constraint that matches an immediate right shift constant in DImode
175 suitable for a SISD instruction."
176 (and (match_code "const_int")
177 (match_test "IN_RANGE (ival, 1, 63)")))
179 (define_constraint "UsM"
181 A constraint that matches the immediate constant -1."
182 (match_test "op == constm1_rtx"))
184 (define_constraint "Ulc"
186 A constraint that matches a constant integer whose bits are consecutive ones
188 (and (match_code "const_int")
189 (match_test "aarch64_high_bits_all_ones_p (ival)")))
191 (define_constraint "Usv"
193 A constraint that matches a VG-based constant that can be loaded by
195 (match_operand 0 "aarch64_sve_cnt_immediate"))
197 (define_constraint "Usi"
199 A constraint that matches an immediate operand valid for
200 the SVE INDEX instruction."
201 (match_operand 0 "aarch64_sve_index_immediate"))
203 (define_constraint "Ui1"
205 A constraint that matches the immediate constant +1."
206 (match_test "op == const1_rtx"))
208 (define_constraint "Ui2"
210 A constraint that matches the integers 0...3."
211 (and (match_code "const_int")
212 (match_test "(unsigned HOST_WIDE_INT) ival <= 3")))
214 (define_constraint "Ui3"
216 A constraint that matches the integers 0...4."
217 (and (match_code "const_int")
218 (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
220 (define_constraint "Ui7"
222 A constraint that matches the integers 0...7."
223 (and (match_code "const_int")
224 (match_test "(unsigned HOST_WIDE_INT) ival <= 7")))
226 (define_constraint "Up3"
228 A constraint that matches the integers 2^(0...4)."
229 (and (match_code "const_int")
230 (match_test "(unsigned) exact_log2 (ival) <= 4")))
232 (define_memory_constraint "Q"
233 "A memory address which uses a single base register with no offset."
234 (and (match_code "mem")
235 (match_test "REG_P (XEXP (op, 0))")))
237 (define_memory_constraint "Ust"
239 A memory address with 9bit unscaled offset."
240 (match_operand 0 "aarch64_9bit_offset_memory_operand"))
242 (define_memory_constraint "Ump"
244 A memory address suitable for a load/store pair operation."
245 (and (match_code "mem")
246 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
247 true, ADDR_QUERY_LDP_STP)")))
249 ;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP
250 ;; as a vector-concat. The address mode uses the same constraints as if it
251 ;; were for a single value.
252 (define_memory_constraint "Umn"
254 A memory address suitable for a load/store pair operation."
255 (and (match_code "mem")
256 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
258 ADDR_QUERY_LDP_STP_N)")))
260 (define_memory_constraint "Utr"
262 An address valid for SVE LDR and STR instructions (as distinct from
263 LD[1234] and ST[1234] patterns)."
264 (and (match_code "mem")
265 (match_test "aarch64_sve_ldr_operand_p (op)")))
267 (define_memory_constraint "Utv"
269 An address valid for loading/storing opaque structure
270 types wider than TImode."
271 (and (match_code "mem")
272 (match_test "aarch64_simd_mem_operand_p (op)")))
274 (define_memory_constraint "Utq"
276 An address valid for loading or storing a 128-bit AdvSIMD register"
277 (and (match_code "mem")
278 (match_test "aarch64_legitimate_address_p (V2DImode,
281 (define_memory_constraint "UtQ"
283 An address valid for SVE LD1RQs."
284 (and (match_code "mem")
285 (match_test "aarch64_sve_ld1rq_operand_p (op)")))
287 (define_memory_constraint "Uty"
289 An address valid for SVE LD1Rs."
290 (and (match_code "mem")
291 (match_test "aarch64_sve_ld1r_operand_p (op)")))
293 (define_memory_constraint "Utx"
295 An address valid for SVE structure mov patterns (as distinct from
296 LD[234] and ST[234] patterns)."
297 (match_operand 0 "aarch64_sve_struct_memory_operand"))
299 (define_constraint "Ufc"
300 "A floating point constant which can be used with an\
301 FMOV immediate operation."
302 (and (match_code "const_double,const_vector")
303 (match_test "aarch64_float_const_representable_p (op)")))
305 (define_constraint "Uvi"
306 "A floating point constant which can be used with a\
307 MOVI immediate operation."
308 (and (match_code "const_double")
309 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
311 (define_constraint "Do"
313 A constraint that matches vector of immediates for orr."
314 (and (match_code "const_vector")
315 (match_test "aarch64_simd_valid_immediate (op, NULL,
316 AARCH64_CHECK_ORR)")))
318 (define_constraint "Db"
320 A constraint that matches vector of immediates for bic."
321 (and (match_code "const_vector")
322 (match_test "aarch64_simd_valid_immediate (op, NULL,
323 AARCH64_CHECK_BIC)")))
325 (define_constraint "Dn"
327 A constraint that matches vector of immediates."
328 (and (match_code "const,const_vector")
329 (match_test "aarch64_simd_valid_immediate (op, NULL)")))
331 (define_constraint "Dh"
333 A constraint that matches an immediate operand valid for\
334 AdvSIMD scalar move in HImode."
335 (and (match_code "const_int")
336 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
339 (define_constraint "Dq"
341 A constraint that matches an immediate operand valid for\
342 AdvSIMD scalar move in QImode."
343 (and (match_code "const_int")
344 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
347 (define_constraint "Dt"
349 A const_double which is the reciprocal of an exact power of two, can be
350 used in an scvtf with fract bits operation"
351 (and (match_code "const_double")
352 (match_test "aarch64_fpconst_pow2_recip (op) > 0")))
354 (define_constraint "Dl"
356 A constraint that matches vector of immediates for left shifts."
357 (and (match_code "const,const_vector")
358 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
361 (define_constraint "Dr"
363 A constraint that matches vector of immediates for right shifts."
364 (and (match_code "const,const_vector")
365 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
367 (define_constraint "Dz"
369 A constraint that matches a vector of immediate zero."
370 (and (match_code "const,const_vector")
371 (match_test "op == CONST0_RTX (GET_MODE (op))")))
373 (define_constraint "Dm"
375 A constraint that matches a vector of immediate minus one."
376 (and (match_code "const,const_vector")
377 (match_test "op == CONST1_RTX (GET_MODE (op))")))
379 (define_constraint "Dd"
381 A constraint that matches an integer immediate operand valid\
382 for AdvSIMD scalar operations in DImode."
383 (and (match_code "const_int")
384 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
386 (define_constraint "Ds"
388 A constraint that matches an integer immediate operand valid\
389 for AdvSIMD scalar operations in SImode."
390 (and (match_code "const_int")
391 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
393 (define_address_constraint "Dp"
395 An address valid for a prefetch instruction."
396 (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))
398 (define_constraint "vsa"
400 A constraint that matches an immediate operand valid for SVE
401 arithmetic instructions."
402 (match_operand 0 "aarch64_sve_arith_immediate"))
404 (define_constraint "vsb"
406 A constraint that matches an immediate operand valid for SVE UMAX
407 and UMIN operations."
408 (match_operand 0 "aarch64_sve_vsb_immediate"))
410 (define_constraint "vsc"
412 A constraint that matches a signed immediate operand valid for SVE
414 (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))
416 (define_constraint "vss"
418 A constraint that matches a signed immediate operand valid for SVE
420 (match_test "aarch64_sve_dup_immediate_p (op)"))
422 (define_constraint "vsd"
424 A constraint that matches an unsigned immediate operand valid for SVE
426 (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))
428 (define_constraint "vsi"
430 A constraint that matches a vector count operand valid for SVE INC and
432 (match_operand 0 "aarch64_sve_vector_inc_dec_immediate"))
434 (define_constraint "vsn"
436 A constraint that matches an immediate operand whose negative
437 is valid for SVE SUB instructions."
438 (match_operand 0 "aarch64_sve_sub_arith_immediate"))
440 (define_constraint "vsl"
442 A constraint that matches an immediate operand valid for SVE logical
444 (match_operand 0 "aarch64_sve_logical_immediate"))
446 (define_constraint "vsm"
448 A constraint that matches an immediate operand valid for SVE MUL,
449 SMAX and SMIN operations."
450 (match_operand 0 "aarch64_sve_vsm_immediate"))
452 (define_constraint "vsA"
454 A constraint that matches an immediate operand valid for SVE FADD
455 and FSUB operations."
456 (match_operand 0 "aarch64_sve_float_arith_immediate"))
459 (define_constraint "vsB"
461 A constraint that matches an immediate operand valid for SVE FMAX
462 and FMIN operations."
463 (match_operand 0 "aarch64_sve_float_maxmin_immediate"))
465 (define_constraint "vsM"
467 A constraint that matches an immediate operand valid for SVE FMUL
469 (match_operand 0 "aarch64_sve_float_mul_immediate"))
471 (define_constraint "vsN"
473 A constraint that matches the negative of vsA"
474 (match_operand 0 "aarch64_sve_float_negated_arith_immediate"))