gcc/config/aarch64/iterators.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; -------------------------------------------------------------------
  22 ;; Mode Iterators
  23 ;; -------------------------------------------------------------------
  24
  25
  26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
  27 (define_mode_iterator GPI [SI DI])
  28
  29 ;; Iterator for QI and HI modes
  30 (define_mode_iterator SHORT [QI HI])
  31
  32 ;; Iterator for all integer modes (up to 64-bit)
  33 (define_mode_iterator ALLI [QI HI SI DI])
  34
  35 ;; Iterator scalar modes (up to 64-bit)
  36 (define_mode_iterator SDQ_I [QI HI SI DI])
  37
  38 ;; Iterator for all integer modes that can be extended (up to 64-bit)
  39 (define_mode_iterator ALLX [QI HI SI])
  40
  41 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
  42 (define_mode_iterator GPF [SF DF])
  43
  44 ;; Integer vector modes.
  45 (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
  46
  47 ;; Integer vector modes.
  48 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
  49
  50 ;; vector and scalar, 64 & 128-bit container, all integer modes
  51 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
  52
  53 ;; vector and scalar, 64 & 128-bit container: all vector integer modes;
  54 ;; 64-bit scalar integer mode
  55 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
  56
  57 ;; Double vector modes.
  58 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
  59
  60 ;; vector, 64-bit container, all integer modes
  61 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
  62
  63 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
  64 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
  65
  66 ;; Quad vector modes.
  67 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF])
  68
  69 ;; All vector modes, except double.
  70 (define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])
  71
  72 ;; Vector and scalar, 64 & 128-bit container: all vector integer mode;
  73 ;; 8, 16, 32-bit scalar integer modes
  74 (define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI])
  75
  76 ;; Vector modes for moves.
  77 (define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI])
  78
  79 ;; This mode iterator allows :PTR to be used for patterns that operate on
  80 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
  81 (define_mode_iterator PTR [(SI "Pmode == SImode") (DI "Pmode == DImode")])
  82
  83 ;; Vector Float modes.
  84 (define_mode_iterator VDQF [V2SF V4SF V2DF])
  85
  86 ;; Vector Float modes with 2 elements.
  87 (define_mode_iterator V2F [V2SF V2DF])
  88
  89 ;; All modes.
  90 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
  91
  92 ;; Vector modes for Integer reduction across lanes.
  93 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI])
  94
  95 ;; All double integer narrow-able modes.
  96 (define_mode_iterator VDN [V4HI V2SI DI])
  97
  98 ;; All quad integer narrow-able modes.
  99 (define_mode_iterator VQN [V8HI V4SI V2DI])
 100
 101 ;; All double integer widen-able modes.
 102 (define_mode_iterator VDW [V8QI V4HI V2SI])
 103
 104 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
 105 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
 106
 107 ;; All quad integer widen-able modes.
 108 (define_mode_iterator VQW [V16QI V8HI V4SI])
 109
 110 ;; Double vector modes for combines.
 111 (define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF])
 112
 113 ;; Double vector modes for combines.
 114 (define_mode_iterator VDIC [V8QI V4HI V2SI])
 115
 116 ;; Double vector modes.
 117 (define_mode_iterator VD_RE [V8QI V4HI V2SI DI DF V2SF])
 118
 119 ;; Vector modes except double int.
 120 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 121
 122 ;; Vector modes for H and S types.
 123 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
 124
 125 ;; Vector and scalar integer modes for H and S
 126 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
 127
 128 ;; Vector and scalar 64-bit container: 16, 32-bit integer modes
 129 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
 130
 131 ;; Vector 64-bit container: 16, 32-bit integer modes
 132 (define_mode_iterator VD_HSI [V4HI V2SI])
 133
 134 ;; Scalar 64-bit container: 16, 32-bit integer modes
 135 (define_mode_iterator SD_HSI [HI SI])
 136
 137 ;; Vector 64-bit container: 16, 32-bit integer modes
 138 (define_mode_iterator VQ_HSI [V8HI V4SI])
 139
 140 ;; All byte modes.
 141 (define_mode_iterator VB [V8QI V16QI])
 142
 143 (define_mode_iterator TX [TI TF])
 144
 145 ;; Opaque structure modes.
 146 (define_mode_iterator VSTRUCT [OI CI XI])
 147
 148 ;; Double scalar modes
 149 (define_mode_iterator DX [DI DF])
 150
 151 ;; ------------------------------------------------------------------
 152 ;; Unspec enumerations for Advance SIMD. These could well go into
 153 ;; aarch64.md but for their use in int_iterators here.
 154 ;; ------------------------------------------------------------------
 155
 156 (define_c_enum "unspec"
 157  [
 158     UNSPEC_ASHIFT_SIGNED        ; Used in aarch-simd.md.
 159     UNSPEC_ASHIFT_UNSIGNED      ; Used in aarch64-simd.md.
 160     UNSPEC_FMAXV        ; Used in aarch64-simd.md.
 161     UNSPEC_FMINV        ; Used in aarch64-simd.md.
 162     UNSPEC_FADDV        ; Used in aarch64-simd.md.
 163     UNSPEC_ADDV         ; Used in aarch64-simd.md.
 164     UNSPEC_SMAXV        ; Used in aarch64-simd.md.
 165     UNSPEC_SMINV        ; Used in aarch64-simd.md.
 166     UNSPEC_UMAXV        ; Used in aarch64-simd.md.
 167     UNSPEC_UMINV        ; Used in aarch64-simd.md.
 168     UNSPEC_SHADD        ; Used in aarch64-simd.md.
 169     UNSPEC_UHADD        ; Used in aarch64-simd.md.
 170     UNSPEC_SRHADD       ; Used in aarch64-simd.md.
 171     UNSPEC_URHADD       ; Used in aarch64-simd.md.
 172     UNSPEC_SHSUB        ; Used in aarch64-simd.md.
 173     UNSPEC_UHSUB        ; Used in aarch64-simd.md.
 174     UNSPEC_SRHSUB       ; Used in aarch64-simd.md.
 175     UNSPEC_URHSUB       ; Used in aarch64-simd.md.
 176     UNSPEC_ADDHN        ; Used in aarch64-simd.md.
 177     UNSPEC_RADDHN       ; Used in aarch64-simd.md.
 178     UNSPEC_SUBHN        ; Used in aarch64-simd.md.
 179     UNSPEC_RSUBHN       ; Used in aarch64-simd.md.
 180     UNSPEC_ADDHN2       ; Used in aarch64-simd.md.
 181     UNSPEC_RADDHN2      ; Used in aarch64-simd.md.
 182     UNSPEC_SUBHN2       ; Used in aarch64-simd.md.
 183     UNSPEC_RSUBHN2      ; Used in aarch64-simd.md.
 184     UNSPEC_SQDMULH      ; Used in aarch64-simd.md.
 185     UNSPEC_SQRDMULH     ; Used in aarch64-simd.md.
 186     UNSPEC_PMUL         ; Used in aarch64-simd.md.
 187     UNSPEC_USQADD       ; Used in aarch64-simd.md.
 188     UNSPEC_SUQADD       ; Used in aarch64-simd.md.
 189     UNSPEC_SQXTUN       ; Used in aarch64-simd.md.
 190     UNSPEC_SQXTN        ; Used in aarch64-simd.md.
 191     UNSPEC_UQXTN        ; Used in aarch64-simd.md.
 192     UNSPEC_SSRA         ; Used in aarch64-simd.md.
 193     UNSPEC_USRA         ; Used in aarch64-simd.md.
 194     UNSPEC_SRSRA        ; Used in aarch64-simd.md.
 195     UNSPEC_URSRA        ; Used in aarch64-simd.md.
 196     UNSPEC_SRSHR        ; Used in aarch64-simd.md.
 197     UNSPEC_URSHR        ; Used in aarch64-simd.md.
 198     UNSPEC_SQSHLU       ; Used in aarch64-simd.md.
 199     UNSPEC_SQSHL        ; Used in aarch64-simd.md.
 200     UNSPEC_UQSHL        ; Used in aarch64-simd.md.
 201     UNSPEC_SQSHRUN      ; Used in aarch64-simd.md.
 202     UNSPEC_SQRSHRUN     ; Used in aarch64-simd.md.
 203     UNSPEC_SQSHRN       ; Used in aarch64-simd.md.
 204     UNSPEC_UQSHRN       ; Used in aarch64-simd.md.
 205     UNSPEC_SQRSHRN      ; Used in aarch64-simd.md.
 206     UNSPEC_UQRSHRN      ; Used in aarch64-simd.md.
 207     UNSPEC_SSHL         ; Used in aarch64-simd.md.
 208     UNSPEC_USHL         ; Used in aarch64-simd.md.
 209     UNSPEC_SRSHL        ; Used in aarch64-simd.md.
 210     UNSPEC_URSHL        ; Used in aarch64-simd.md.
 211     UNSPEC_SQRSHL       ; Used in aarch64-simd.md.
 212     UNSPEC_UQRSHL       ; Used in aarch64-simd.md.
 213     UNSPEC_CMEQ         ; Used in aarch64-simd.md.
 214     UNSPEC_CMLE         ; Used in aarch64-simd.md.
 215     UNSPEC_CMLT         ; Used in aarch64-simd.md.
 216     UNSPEC_CMGE         ; Used in aarch64-simd.md.
 217     UNSPEC_CMGT         ; Used in aarch64-simd.md.
 218     UNSPEC_CMHS         ; Used in aarch64-simd.md.
 219     UNSPEC_CMHI         ; Used in aarch64-simd.md.
 220     UNSPEC_SSLI         ; Used in aarch64-simd.md.
 221     UNSPEC_USLI         ; Used in aarch64-simd.md.
 222     UNSPEC_SSRI         ; Used in aarch64-simd.md.
 223     UNSPEC_USRI         ; Used in aarch64-simd.md.
 224     UNSPEC_SSHLL        ; Used in aarch64-simd.md.
 225     UNSPEC_USHLL        ; Used in aarch64-simd.md.
 226     UNSPEC_ADDP         ; Used in aarch64-simd.md.
 227     UNSPEC_CMTST        ; Used in aarch64-simd.md.
 228     UNSPEC_FMAX         ; Used in aarch64-simd.md.
 229     UNSPEC_FMIN         ; Used in aarch64-simd.md.
 230     UNSPEC_BSL          ; Used in aarch64-simd.md.
 231 ])
 232
 233 ;; -------------------------------------------------------------------
 234 ;; Mode attributes
 235 ;; -------------------------------------------------------------------
 236
 237 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
 238 ;; 32-bit version and "%x0" in the 64-bit version.
 239 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
 240
 241 ;; For scalar usage of vector/FP registers
 242 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
 243                     (V8QI "") (V16QI "")
 244                     (V4HI "") (V8HI "")
 245                     (V2SI "") (V4SI  "")
 246                     (V2DI "") (V2SF "")
 247                     (V4SF "") (V2DF "")])
 248
 249 ;; For scalar usage of vector/FP registers, narrowing
 250 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
 251                     (V8QI "") (V16QI "")
 252                     (V4HI "") (V8HI "")
 253                     (V2SI "") (V4SI  "")
 254                     (V2DI "") (V2SF "")
 255                     (V4SF "") (V2DF "")])
 256
 257 ;; For scalar usage of vector/FP registers, widening
 258 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
 259                     (V8QI "") (V16QI "")
 260                     (V4HI "") (V8HI "")
 261                     (V2SI "") (V4SI  "")
 262                     (V2DI "") (V2SF "")
 263                     (V4SF "") (V2DF "")])
 264
 265 ;; Map a floating point mode to the appropriate register name prefix
 266 (define_mode_attr s [(SF "s") (DF "d")])
 267
 268 ;; Give the length suffix letter for a sign- or zero-extension.
 269 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
 270
 271 ;; Give the number of bits in the mode
 272 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
 273
 274 ;; Give the ordinal of the MSB in the mode
 275 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
 276
 277 ;; Attribute to describe constants acceptable in logical operations
 278 (define_mode_attr lconst [(SI "K") (DI "L")])
 279
 280 ;; Map a mode to a specific constraint character.
 281 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
 282
 283 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
 284                          (V4HI "4h") (V8HI  "8h")
 285                          (V2SI "2s") (V4SI  "4s")
 286                          (DI   "1d") (DF    "1d")
 287                          (V2DI "2d") (V2SF "2s")
 288                          (V4SF "4s") (V2DF "2d")])
 289
 290 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
 291                          (V4HI ".4h") (V8HI  ".8h")
 292                          (V2SI ".2s") (V4SI  ".4s")
 293                          (V2DI ".2d") (V2SF ".2s")
 294                          (V4SF ".4s") (V2DF ".2d")
 295                          (DI   "")    (SI   "")
 296                          (HI   "")    (QI   "")
 297                          (TI   "")])
 298
 299 ;; Register suffix narrowed modes for VQN.
 300 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
 301                            (V2DI ".2s")
 302                            (DI   "")    (SI   "")
 303                            (HI   "")])
 304
 305 ;; Mode-to-individual element type mapping.
 306 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
 307                           (V4HI "h") (V8HI  "h")
 308                           (V2SI "s") (V4SI  "s")
 309                           (V2DI "d") (V2SF  "s")
 310                           (V4SF "s") (V2DF  "d")
 311                           (QI "b")   (HI "h")
 312                           (SI "s")   (DI "d")])
 313
 314 ;; Mode-to-bitwise operation type mapping.
 315 (define_mode_attr Vbtype [(V8QI "8b")  (V16QI "16b")
 316                           (V4HI "8b") (V8HI  "16b")
 317                           (V2SI "8b") (V4SI  "16b")
 318                           (V2DI "16b") (V2SF  "8b")
 319                           (V4SF "16b") (V2DF  "16b")])
 320
 321 ;; Define element mode for each vector mode.
 322 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
 323                         (V4HI "HI") (V8HI "HI")
 324                         (V2SI "SI") (V4SI "SI")
 325                         (DI "DI")   (V2DI "DI")
 326                         (V2SF "SF") (V4SF "SF")
 327                         (V2DF "DF")
 328                         (SI   "SI") (HI   "HI")
 329                         (QI   "QI")])
 330
 331 ;; Define container mode for lane selection.
 332 (define_mode_attr VCON [(V8QI "V16QI") (V16QI "V16QI")
 333                         (V4HI "V8HI") (V8HI "V8HI")
 334                         (V2SI "V4SI") (V4SI "V4SI")
 335                         (DI   "V2DI") (V2DI "V2DI")
 336                         (V2SF "V2SF") (V4SF "V4SF")
 337                         (V2DF "V2DF") (SI   "V4SI")
 338                         (HI   "V8HI") (QI   "V16QI")])
 339
 340 ;; Half modes of all vector modes.
 341 (define_mode_attr VHALF [(V8QI "V4QI")  (V16QI "V8QI")
 342                          (V4HI "V2HI")  (V8HI  "V4HI")
 343                          (V2SI "SI")    (V4SI  "V2SI")
 344                          (V2DI "DI")    (V2SF  "SF")
 345                          (V4SF "V2SF")  (V2DF  "DF")])
 346
 347 ;; Double modes of vector modes.
 348 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
 349                         (V2SI "V4SI")  (V2SF "V4SF")
 350                         (SI   "V2SI")  (DI   "V2DI")
 351                         (DF   "V2DF")])
 352
 353 ;; Double modes of vector modes (lower case).
 354 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
 355                         (V2SI "v4si")  (V2SF "v4sf")
 356                         (SI   "v2si")  (DI   "v2di")])
 357
 358 ;; Narrowed modes for VDN.
 359 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
 360                             (DI   "V2SI")])
 361
 362 ;; Narrowed double-modes for VQN (Used for XTN).
 363 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
 364                             (V2DI "V2SI")
 365                             (DI   "SI")   (SI   "HI")
 366                             (HI   "QI")])
 367
 368 ;; Narrowed quad-modes for VQN (Used for XTN2).
 369 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
 370                              (V2DI "V4SI")])
 371
 372 ;; Register suffix narrowed modes for VQN.
 373 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
 374                           (V2DI "2s")])
 375
 376 ;; Register suffix narrowed modes for VQN.
 377 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
 378                            (V2DI "4s")])
 379
 380 ;; Widened modes of vector modes.
 381 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
 382                          (V2SI "V2DI") (V16QI "V8HI")
 383                          (V8HI "V4SI") (V4SI "V2DI")
 384                          (HI "SI")     (SI "DI")]
 385
 386 )
 387
 388 ;; Widened mode register suffixes for VDW/VQW.
 389 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
 390                           (V2SI "2d") (V16QI "8h")
 391                           (V8HI "4s") (V4SI "2d")])
 392
 393 ;; Widened mode register suffixes for VDW/VQW.
 394 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
 395                            (V2SI ".2d") (V16QI ".8h")
 396                            (V8HI ".4s") (V4SI ".2d")
 397                            (SI   "")    (HI   "")])
 398
 399 ;; Lower part register suffixes for VQW.
 400 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
 401                              (V4SI "2s")])
 402
 403 ;; Define corresponding core/FP element mode for each vector mode.
 404 (define_mode_attr vw   [(V8QI "w") (V16QI "w")
 405                         (V4HI "w") (V8HI "w")
 406                         (V2SI "w") (V4SI "w")
 407                         (DI   "x") (V2DI "x")
 408                         (V2SF "s") (V4SF "s")
 409                         (V2DF "d")])
 410
 411 ;; Double vector types for ALLX.
 412 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
 413
 414 ;; Mode of result of comparison operations.
 415 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
 416                                 (V4HI "V4HI") (V8HI  "V8HI")
 417                                 (V2SI "V2SI") (V4SI  "V4SI")
 418                                 (V2SF "V2SI") (V4SF  "V4SI")
 419                                 (DI   "DI")   (V2DI  "V2DI")])
 420
 421 ;; Vm for lane instructions is restricted to FP_LO_REGS.
 422 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
 423                        (V2SI "w") (V4SI "w") (SI "w")])
 424
 425 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
 426
 427 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
 428
 429 (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI")
 430                         (V2SI "V8SI")  (V2SF "V8SF")
 431                         (DI   "V4DI")  (DF   "V4DF")
 432                         (V16QI "V32QI") (V8HI "V16HI")
 433                         (V4SI "V8SI")  (V4SF "V8SF")
 434                         (V2DI "V4DI")  (V2DF "V4DF")])
 435
 436 (define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI")
 437                         (V2SI "V12SI")  (V2SF "V12SF")
 438                         (DI   "V6DI")  (DF   "V6DF")
 439                         (V16QI "V48QI") (V8HI "V24HI")
 440                         (V4SI "V12SI")  (V4SF "V12SF")
 441                         (V2DI "V6DI")  (V2DF "V6DF")])
 442
 443 (define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI")
 444                         (V2SI "V16SI")  (V2SF "V16SF")
 445                         (DI   "V8DI")  (DF   "V8DF")
 446                         (V16QI "V64QI") (V8HI "V32HI")
 447                         (V4SI "V16SI")  (V4SF "V16SF")
 448                         (V2DI "V8DI")  (V2DF "V8DF")])
 449
 450 (define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
 451
 452 ;; Mode for atomic operation suffixes
 453 (define_mode_attr atomic_sfx
 454   [(QI "b") (HI "h") (SI "") (DI "")])
 455
 456 ;; -------------------------------------------------------------------
 457 ;; Code Iterators
 458 ;; -------------------------------------------------------------------
 459
 460 ;; This code iterator allows the various shifts supported on the core
 461 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
 462
 463 ;; This code iterator allows the shifts supported in arithmetic instructions
 464 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
 465
 466 ;; Code iterator for logical operations
 467 (define_code_iterator LOGICAL [and ior xor])
 468
 469 ;; Code iterator for sign/zero extension
 470 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
 471
 472 ;; All division operations (signed/unsigned)
 473 (define_code_iterator ANY_DIV [div udiv])
 474
 475 ;; Code iterator for sign/zero extraction
 476 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
 477
 478 ;; Code iterator for equality comparisons
 479 (define_code_iterator EQL [eq ne])
 480
 481 ;; Code iterator for less-than and greater/equal-to
 482 (define_code_iterator LTGE [lt ge])
 483
 484 ;; Iterator for __sync_<op> operations that where the operation can be
 485 ;; represented directly RTL.  This is all of the sync operations bar
 486 ;; nand.
 487 (define_code_iterator atomic_op [plus minus ior xor and])
 488
 489 ;; Iterator for integer conversions
 490 (define_code_iterator FIXUORS [fix unsigned_fix])
 491
 492 ;; Code iterator for variants of vector max and min.
 493 (define_code_iterator MAXMIN [smax smin umax umin])
 494
 495 ;; Code iterator for variants of vector max and min.
 496 (define_code_iterator ADDSUB [plus minus])
 497
 498 ;; Code iterator for variants of vector saturating binary ops.
 499 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
 500
 501 ;; Code iterator for variants of vector saturating unary ops.
 502 (define_code_iterator UNQOPS [ss_neg ss_abs])
 503
 504 ;; Code iterator for signed variants of vector saturating binary ops.
 505 (define_code_iterator SBINQOPS [ss_plus ss_minus])
 506
 507 ;; -------------------------------------------------------------------
 508 ;; Code Attributes
 509 ;; -------------------------------------------------------------------
 510 ;; Map rtl objects to optab names
 511 (define_code_attr optab [(ashift "ashl")
 512                          (ashiftrt "ashr")
 513                          (lshiftrt "lshr")
 514                          (rotatert "rotr")
 515                          (sign_extend "extend")
 516                          (zero_extend "zero_extend")
 517                          (sign_extract "extv")
 518                          (zero_extract "extzv")
 519                          (and "and")
 520                          (ior "ior")
 521                          (xor "xor")
 522                          (not "one_cmpl")
 523                          (neg "neg")
 524                          (plus "add")
 525                          (minus "sub")
 526                          (ss_plus "qadd")
 527                          (us_plus "qadd")
 528                          (ss_minus "qsub")
 529                          (us_minus "qsub")
 530                          (ss_neg "qneg")
 531                          (ss_abs "qabs")
 532                          (eq "eq")
 533                          (ne "ne")
 534                          (lt "lt")
 535                          (ge "ge")])
 536
 537 ;; Optab prefix for sign/zero-extending operations
 538 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
 539                             (div "") (udiv "u")
 540                             (fix "") (unsigned_fix "u")
 541                             (ss_plus "s") (us_plus "u")
 542                             (ss_minus "s") (us_minus "u")])
 543
 544 ;; Similar for the instruction mnemonics
 545 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
 546                          (lshiftrt "lsr") (rotatert "ror")])
 547
 548 ;; Map shift operators onto underlying bit-field instructions
 549 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
 550                            (lshiftrt "ubfx") (rotatert "extr")])
 551
 552 ;; Logical operator instruction mnemonics
 553 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
 554
 555 ;; Similar, but when not(op)
 556 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
 557
 558 ;; Sign- or zero-extending load
 559 (define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
 560
 561 ;; Sign- or zero-extending data-op
 562 (define_code_attr su [(sign_extend "s") (zero_extend "u")
 563                       (sign_extract "s") (zero_extract "u")
 564                       (fix "s") (unsigned_fix "u")
 565                       (div "s") (udiv "u")])
 566
 567 ;; Emit cbz/cbnz depending on comparison type.
 568 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
 569
 570 ;; Emit tbz/tbnz depending on comparison type.
 571 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
 572
 573 ;; Max/min attributes.
 574 (define_code_attr maxmin [(smax "smax")
 575                           (smin "smin")
 576                           (umax "umax")
 577                           (umin "umin")])
 578
 579 ;; MLA/MLS attributes.
 580 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
 581
 582 ;; Atomic operations
 583 (define_code_attr atomic_optab
 584   [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
 585
 586 (define_code_attr atomic_op_operand
 587   [(ior "aarch64_logical_operand")
 588    (xor "aarch64_logical_operand")
 589    (and "aarch64_logical_operand")
 590    (plus "aarch64_plus_operand")
 591    (minus "aarch64_plus_operand")])
 592
 593 ;; -------------------------------------------------------------------
 594 ;; Int Iterators.
 595 ;; -------------------------------------------------------------------
 596 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
 597                               UNSPEC_SMAXV UNSPEC_SMINV])
 598
 599 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV])
 600
 601 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
 602                               UNSPEC_SRHADD UNSPEC_URHADD
 603                               UNSPEC_SHSUB UNSPEC_UHSUB
 604                               UNSPEC_SRHSUB UNSPEC_URHSUB])
 605
 606
 607 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
 608                                UNSPEC_SUBHN UNSPEC_RSUBHN])
 609
 610 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
 611                                 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
 612
 613 (define_int_iterator FMAXMIN [UNSPEC_FMAX UNSPEC_FMIN])
 614
 615 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
 616
 617 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
 618
 619 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
 620
 621 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
 622                            UNSPEC_SRSHL UNSPEC_URSHL])
 623
 624 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
 625
 626 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
 627                             UNSPEC_SQRSHL UNSPEC_UQRSHL])
 628
 629 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
 630                              UNSPEC_SRSRA UNSPEC_URSRA])
 631
 632 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
 633                               UNSPEC_SSRI UNSPEC_USRI])
 634
 635
 636 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
 637
 638 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
 639
 640 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
 641                                UNSPEC_SQSHRN UNSPEC_UQSHRN
 642                                UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
 643
 644 (define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT
 645                              UNSPEC_CMLE UNSPEC_CMLT])
 646
 647 (define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST])
 648
 649
 650 ;; -------------------------------------------------------------------
 651 ;; Int Iterators Attributes.
 652 ;; -------------------------------------------------------------------
 653 (define_int_attr  maxminv [(UNSPEC_UMAXV "umax")
 654                            (UNSPEC_UMINV "umin")
 655                            (UNSPEC_SMAXV "smax")
 656                            (UNSPEC_SMINV "smin")])
 657
 658 (define_int_attr  fmaxminv [(UNSPEC_FMAXV "max")
 659                             (UNSPEC_FMINV "min")])
 660
 661 (define_int_attr  fmaxmin [(UNSPEC_FMAX "fmax")
 662                            (UNSPEC_FMIN "fmin")])
 663
 664 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
 665                       (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
 666                       (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
 667                       (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
 668                       (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
 669                       (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
 670                       (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
 671                       (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
 672                       (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
 673                       (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
 674                       (UNSPEC_SSLI  "s") (UNSPEC_USLI  "u")
 675                       (UNSPEC_SSRI  "s") (UNSPEC_USRI  "u")
 676                       (UNSPEC_USRA  "u") (UNSPEC_SSRA  "s")
 677                       (UNSPEC_URSRA  "ur") (UNSPEC_SRSRA  "sr")
 678                       (UNSPEC_URSHR  "ur") (UNSPEC_SRSHR  "sr")
 679                       (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL   "s")
 680                       (UNSPEC_UQSHL  "u")
 681                       (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
 682                       (UNSPEC_SQSHRN "s")  (UNSPEC_UQSHRN "u")
 683                       (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
 684                       (UNSPEC_USHL  "u")   (UNSPEC_SSHL  "s")
 685                       (UNSPEC_USHLL  "u")  (UNSPEC_SSHLL "s")
 686                       (UNSPEC_URSHL  "ur") (UNSPEC_SRSHL  "sr")
 687                       (UNSPEC_UQRSHL  "u") (UNSPEC_SQRSHL  "s")
 688 ])
 689
 690 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
 691                     (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
 692                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
 693                     (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
 694                     (UNSPEC_SQSHL   "")  (UNSPEC_UQSHL  "")
 695                     (UNSPEC_SQRSHL   "r")(UNSPEC_UQRSHL  "r")
 696 ])
 697
 698 (define_int_attr lr [(UNSPEC_SSLI  "l") (UNSPEC_USLI  "l")
 699                      (UNSPEC_SSRI  "r") (UNSPEC_USRI  "r")])
 700
 701 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
 702                     (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
 703                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
 704                     (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
 705
 706 (define_int_attr addsub [(UNSPEC_SHADD "add")
 707                          (UNSPEC_UHADD "add")
 708                          (UNSPEC_SRHADD "add")
 709                          (UNSPEC_URHADD "add")
 710                          (UNSPEC_SHSUB "sub")
 711                          (UNSPEC_UHSUB "sub")
 712                          (UNSPEC_SRHSUB "sub")
 713                          (UNSPEC_URHSUB "sub")
 714                          (UNSPEC_ADDHN "add")
 715                          (UNSPEC_SUBHN "sub")
 716                          (UNSPEC_RADDHN "add")
 717                          (UNSPEC_RSUBHN "sub")
 718                          (UNSPEC_ADDHN2 "add")
 719                          (UNSPEC_SUBHN2 "sub")
 720                          (UNSPEC_RADDHN2 "add")
 721                          (UNSPEC_RSUBHN2 "sub")])
 722
 723 (define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt")
 724                       (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt")
 725                       (UNSPEC_CMEQ "eq")
 726                       (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi")
 727                       (UNSPEC_CMTST "tst")])
 728
 729 (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1")
 730                            (UNSPEC_SSRI "0") (UNSPEC_USRI "0")])
 731