gcc/config/aarch64/iterators.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2015 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; -------------------------------------------------------------------
  22 ;; Mode Iterators
  23 ;; -------------------------------------------------------------------
  24
  25
  26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
  27 (define_mode_iterator GPI [SI DI])
  28
  29 ;; Iterator for QI and HI modes
  30 (define_mode_iterator SHORT [QI HI])
  31
  32 ;; Iterator for all integer modes (up to 64-bit)
  33 (define_mode_iterator ALLI [QI HI SI DI])
  34
  35 ;; Iterator for all integer modes that can be extended (up to 64-bit)
  36 (define_mode_iterator ALLX [QI HI SI])
  37
  38 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
  39 (define_mode_iterator GPF [SF DF])
  40
  41 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
  42 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
  43
  44 ;; Double vector modes.
  45 (define_mode_iterator VDF [V2SF V4HF])
  46
  47 ;; Integer vector modes.
  48 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
  49
  50 ;; vector and scalar, 64 & 128-bit container, all integer modes
  51 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
  52
  53 ;; vector and scalar, 64 & 128-bit container: all vector integer modes;
  54 ;; 64-bit scalar integer mode
  55 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
  56
  57 ;; Double vector modes.
  58 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
  59
  60 ;; vector, 64-bit container, all integer modes
  61 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
  62
  63 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
  64 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
  65
  66 ;; Quad vector modes.
  67 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
  68
  69 ;; VQ without 2 element modes.
  70 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
  71
  72 ;; Quad vector with only 2 element modes.
  73 (define_mode_iterator VQ_2E [V2DI V2DF])
  74
  75 ;; This mode iterator allows :P to be used for patterns that operate on
  76 ;; addresses in different modes.  In LP64, only DI will match, while in
  77 ;; ILP32, either can match.
  78 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
  79                          (DI "ptr_mode == DImode || Pmode == DImode")])
  80
  81 ;; This mode iterator allows :PTR to be used for patterns that operate on
  82 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
  83 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
  84
  85 ;; Vector Float modes suitable for moving, loading and storing.
  86 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
  87
  88 ;; Vector Float modes, barring HF modes.
  89 (define_mode_iterator VDQF [V2SF V4SF V2DF])
  90
  91 ;; Vector Float modes, and DF.
  92 (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
  93
  94 ;; Vector single Float modes.
  95 (define_mode_iterator VDQSF [V2SF V4SF])
  96
  97 ;; Quad vector Float modes with half/single elements.
  98 (define_mode_iterator VQ_HSF [V8HF V4SF])
  99
 100 ;; Modes suitable to use as the return type of a vcond expression.
 101 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
 102
 103 ;; All Float modes.
 104 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
 105
 106 ;; Vector Float modes with 2 elements.
 107 (define_mode_iterator V2F [V2SF V2DF])
 108
 109 ;; All vector modes on which we support any arithmetic operations.
 110 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
 111
 112 ;; All vector modes suitable for moving, loading, and storing.
 113 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 114                                 V4HF V8HF V2SF V4SF V2DF])
 115
 116 ;; All vector modes barring HF modes, plus DI.
 117 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
 118
 119 ;; All vector modes and DI.
 120 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 121                                   V4HF V8HF V2SF V4SF V2DF DI])
 122
 123 ;; All vector modes, plus DI and DF.
 124 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
 125                                V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
 126
 127 ;; Vector modes for Integer reduction across lanes.
 128 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
 129
 130 ;; Vector modes(except V2DI) for Integer reduction across lanes.
 131 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
 132
 133 ;; All double integer narrow-able modes.
 134 (define_mode_iterator VDN [V4HI V2SI DI])
 135
 136 ;; All quad integer narrow-able modes.
 137 (define_mode_iterator VQN [V8HI V4SI V2DI])
 138
 139 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
 140 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
 141
 142 ;; All quad integer widen-able modes.
 143 (define_mode_iterator VQW [V16QI V8HI V4SI])
 144
 145 ;; Double vector modes for combines.
 146 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
 147
 148 ;; Vector modes except double int.
 149 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 150
 151 ;; Vector modes for S type.
 152 (define_mode_iterator VDQ_SI [V2SI V4SI])
 153
 154 ;; Vector modes for Q and H types.
 155 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
 156
 157 ;; Vector modes for H and S types.
 158 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
 159
 160 ;; Vector modes for H, S and D types.
 161 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
 162
 163 ;; Vector and scalar integer modes for H and S
 164 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
 165
 166 ;; Vector and scalar 64-bit container: 16, 32-bit integer modes
 167 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
 168
 169 ;; Vector 64-bit container: 16, 32-bit integer modes
 170 (define_mode_iterator VD_HSI [V4HI V2SI])
 171
 172 ;; Scalar 64-bit container: 16, 32-bit integer modes
 173 (define_mode_iterator SD_HSI [HI SI])
 174
 175 ;; Vector 64-bit container: 16, 32-bit integer modes
 176 (define_mode_iterator VQ_HSI [V8HI V4SI])
 177
 178 ;; All byte modes.
 179 (define_mode_iterator VB [V8QI V16QI])
 180
 181 ;; 2 and 4 lane SI modes.
 182 (define_mode_iterator VS [V2SI V4SI])
 183
 184 (define_mode_iterator TX [TI TF])
 185
 186 ;; Opaque structure modes.
 187 (define_mode_iterator VSTRUCT [OI CI XI])
 188
 189 ;; Double scalar modes
 190 (define_mode_iterator DX [DI DF])
 191
 192 ;; Modes available for <f>mul lane operations.
 193 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 194
 195 ;; Modes available for <f>mul lane operations changing lane count.
 196 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
 197
 198 ;; ------------------------------------------------------------------
 199 ;; Unspec enumerations for Advance SIMD. These could well go into
 200 ;; aarch64.md but for their use in int_iterators here.
 201 ;; ------------------------------------------------------------------
 202
 203 (define_c_enum "unspec"
 204  [
 205     UNSPEC_ASHIFT_SIGNED        ; Used in aarch-simd.md.
 206     UNSPEC_ASHIFT_UNSIGNED      ; Used in aarch64-simd.md.
 207     UNSPEC_ABS          ; Used in aarch64-simd.md.
 208     UNSPEC_FMAX         ; Used in aarch64-simd.md.
 209     UNSPEC_FMAXNMV      ; Used in aarch64-simd.md.
 210     UNSPEC_FMAXV        ; Used in aarch64-simd.md.
 211     UNSPEC_FMIN         ; Used in aarch64-simd.md.
 212     UNSPEC_FMINNMV      ; Used in aarch64-simd.md.
 213     UNSPEC_FMINV        ; Used in aarch64-simd.md.
 214     UNSPEC_FADDV        ; Used in aarch64-simd.md.
 215     UNSPEC_ADDV         ; Used in aarch64-simd.md.
 216     UNSPEC_SMAXV        ; Used in aarch64-simd.md.
 217     UNSPEC_SMINV        ; Used in aarch64-simd.md.
 218     UNSPEC_UMAXV        ; Used in aarch64-simd.md.
 219     UNSPEC_UMINV        ; Used in aarch64-simd.md.
 220     UNSPEC_SHADD        ; Used in aarch64-simd.md.
 221     UNSPEC_UHADD        ; Used in aarch64-simd.md.
 222     UNSPEC_SRHADD       ; Used in aarch64-simd.md.
 223     UNSPEC_URHADD       ; Used in aarch64-simd.md.
 224     UNSPEC_SHSUB        ; Used in aarch64-simd.md.
 225     UNSPEC_UHSUB        ; Used in aarch64-simd.md.
 226     UNSPEC_SRHSUB       ; Used in aarch64-simd.md.
 227     UNSPEC_URHSUB       ; Used in aarch64-simd.md.
 228     UNSPEC_ADDHN        ; Used in aarch64-simd.md.
 229     UNSPEC_RADDHN       ; Used in aarch64-simd.md.
 230     UNSPEC_SUBHN        ; Used in aarch64-simd.md.
 231     UNSPEC_RSUBHN       ; Used in aarch64-simd.md.
 232     UNSPEC_ADDHN2       ; Used in aarch64-simd.md.
 233     UNSPEC_RADDHN2      ; Used in aarch64-simd.md.
 234     UNSPEC_SUBHN2       ; Used in aarch64-simd.md.
 235     UNSPEC_RSUBHN2      ; Used in aarch64-simd.md.
 236     UNSPEC_SQDMULH      ; Used in aarch64-simd.md.
 237     UNSPEC_SQRDMULH     ; Used in aarch64-simd.md.
 238     UNSPEC_PMUL         ; Used in aarch64-simd.md.
 239     UNSPEC_USQADD       ; Used in aarch64-simd.md.
 240     UNSPEC_SUQADD       ; Used in aarch64-simd.md.
 241     UNSPEC_SQXTUN       ; Used in aarch64-simd.md.
 242     UNSPEC_SQXTN        ; Used in aarch64-simd.md.
 243     UNSPEC_UQXTN        ; Used in aarch64-simd.md.
 244     UNSPEC_SSRA         ; Used in aarch64-simd.md.
 245     UNSPEC_USRA         ; Used in aarch64-simd.md.
 246     UNSPEC_SRSRA        ; Used in aarch64-simd.md.
 247     UNSPEC_URSRA        ; Used in aarch64-simd.md.
 248     UNSPEC_SRSHR        ; Used in aarch64-simd.md.
 249     UNSPEC_URSHR        ; Used in aarch64-simd.md.
 250     UNSPEC_SQSHLU       ; Used in aarch64-simd.md.
 251     UNSPEC_SQSHL        ; Used in aarch64-simd.md.
 252     UNSPEC_UQSHL        ; Used in aarch64-simd.md.
 253     UNSPEC_SQSHRUN      ; Used in aarch64-simd.md.
 254     UNSPEC_SQRSHRUN     ; Used in aarch64-simd.md.
 255     UNSPEC_SQSHRN       ; Used in aarch64-simd.md.
 256     UNSPEC_UQSHRN       ; Used in aarch64-simd.md.
 257     UNSPEC_SQRSHRN      ; Used in aarch64-simd.md.
 258     UNSPEC_UQRSHRN      ; Used in aarch64-simd.md.
 259     UNSPEC_SSHL         ; Used in aarch64-simd.md.
 260     UNSPEC_USHL         ; Used in aarch64-simd.md.
 261     UNSPEC_SRSHL        ; Used in aarch64-simd.md.
 262     UNSPEC_URSHL        ; Used in aarch64-simd.md.
 263     UNSPEC_SQRSHL       ; Used in aarch64-simd.md.
 264     UNSPEC_UQRSHL       ; Used in aarch64-simd.md.
 265     UNSPEC_SSLI         ; Used in aarch64-simd.md.
 266     UNSPEC_USLI         ; Used in aarch64-simd.md.
 267     UNSPEC_SSRI         ; Used in aarch64-simd.md.
 268     UNSPEC_USRI         ; Used in aarch64-simd.md.
 269     UNSPEC_SSHLL        ; Used in aarch64-simd.md.
 270     UNSPEC_USHLL        ; Used in aarch64-simd.md.
 271     UNSPEC_ADDP         ; Used in aarch64-simd.md.
 272     UNSPEC_TBL          ; Used in vector permute patterns.
 273     UNSPEC_CONCAT       ; Used in vector permute patterns.
 274     UNSPEC_ZIP1         ; Used in vector permute patterns.
 275     UNSPEC_ZIP2         ; Used in vector permute patterns.
 276     UNSPEC_UZP1         ; Used in vector permute patterns.
 277     UNSPEC_UZP2         ; Used in vector permute patterns.
 278     UNSPEC_TRN1         ; Used in vector permute patterns.
 279     UNSPEC_TRN2         ; Used in vector permute patterns.
 280     UNSPEC_EXT          ; Used in aarch64-simd.md.
 281     UNSPEC_REV64        ; Used in vector reverse patterns (permute).
 282     UNSPEC_REV32        ; Used in vector reverse patterns (permute).
 283     UNSPEC_REV16        ; Used in vector reverse patterns (permute).
 284     UNSPEC_AESE         ; Used in aarch64-simd.md.
 285     UNSPEC_AESD         ; Used in aarch64-simd.md.
 286     UNSPEC_AESMC        ; Used in aarch64-simd.md.
 287     UNSPEC_AESIMC       ; Used in aarch64-simd.md.
 288     UNSPEC_SHA1C        ; Used in aarch64-simd.md.
 289     UNSPEC_SHA1M        ; Used in aarch64-simd.md.
 290     UNSPEC_SHA1P        ; Used in aarch64-simd.md.
 291     UNSPEC_SHA1H        ; Used in aarch64-simd.md.
 292     UNSPEC_SHA1SU0      ; Used in aarch64-simd.md.
 293     UNSPEC_SHA1SU1      ; Used in aarch64-simd.md.
 294     UNSPEC_SHA256H      ; Used in aarch64-simd.md.
 295     UNSPEC_SHA256H2     ; Used in aarch64-simd.md.
 296     UNSPEC_SHA256SU0    ; Used in aarch64-simd.md.
 297     UNSPEC_SHA256SU1    ; Used in aarch64-simd.md.
 298     UNSPEC_PMULL        ; Used in aarch64-simd.md.
 299     UNSPEC_PMULL2       ; Used in aarch64-simd.md.
 300     UNSPEC_REV_REGLIST  ; Used in aarch64-simd.md.
 301     UNSPEC_VEC_SHR      ; Used in aarch64-simd.md.
 302 ])
 303
 304 ;; -------------------------------------------------------------------
 305 ;; Mode attributes
 306 ;; -------------------------------------------------------------------
 307
 308 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
 309 ;; 32-bit version and "%x0" in the 64-bit version.
 310 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
 311
 312 ;; For inequal width int to float conversion
 313 (define_mode_attr w1 [(SF "w") (DF "x")])
 314 (define_mode_attr w2 [(SF "x") (DF "w")])
 315
 316 ;; For constraints used in scalar immediate vector moves
 317 (define_mode_attr hq [(HI "h") (QI "q")])
 318
 319 ;; For scalar usage of vector/FP registers
 320 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
 321                     (SF "s") (DF "d")
 322                     (V8QI "") (V16QI "")
 323                     (V4HI "") (V8HI "")
 324                     (V2SI "") (V4SI  "")
 325                     (V2DI "") (V2SF "")
 326                     (V4SF "") (V2DF "")])
 327
 328 ;; For scalar usage of vector/FP registers, narrowing
 329 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
 330                     (V8QI "") (V16QI "")
 331                     (V4HI "") (V8HI "")
 332                     (V2SI "") (V4SI  "")
 333                     (V2DI "") (V2SF "")
 334                     (V4SF "") (V2DF "")])
 335
 336 ;; For scalar usage of vector/FP registers, widening
 337 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
 338                     (V8QI "") (V16QI "")
 339                     (V4HI "") (V8HI "")
 340                     (V2SI "") (V4SI  "")
 341                     (V2DI "") (V2SF "")
 342                     (V4SF "") (V2DF "")])
 343
 344 ;; Register Type Name and Vector Arrangement Specifier for when
 345 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
 346 ;; lane 0).
 347 (define_mode_attr rtn [(DI "d") (SI "")])
 348 (define_mode_attr vas [(DI "") (SI ".2s")])
 349
 350 ;; Map a floating point mode to the appropriate register name prefix
 351 (define_mode_attr s [(SF "s") (DF "d")])
 352
 353 ;; Give the length suffix letter for a sign- or zero-extension.
 354 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
 355
 356 ;; Give the number of bits in the mode
 357 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
 358
 359 ;; Give the ordinal of the MSB in the mode
 360 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
 361
 362 ;; Attribute to describe constants acceptable in logical operations
 363 (define_mode_attr lconst [(SI "K") (DI "L")])
 364
 365 ;; Map a mode to a specific constraint character.
 366 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
 367
 368 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
 369                          (V4HI "4h") (V8HI  "8h")
 370                          (V2SI "2s") (V4SI  "4s")
 371                          (DI   "1d") (DF    "1d")
 372                          (V2DI "2d") (V2SF "2s")
 373                          (V4SF "4s") (V2DF "2d")
 374                          (V4HF "4h") (V8HF "8h")])
 375
 376 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
 377                             (V4SI "32") (V2DI "64")])
 378
 379 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
 380                          (V4HI ".4h") (V8HI  ".8h")
 381                          (V2SI ".2s") (V4SI  ".4s")
 382                          (V2DI ".2d") (V4HF ".4h")
 383                          (V8HF ".8h") (V2SF ".2s")
 384                          (V4SF ".4s") (V2DF ".2d")
 385                          (DI   "")    (SI   "")
 386                          (HI   "")    (QI   "")
 387                          (TI   "")    (SF   "")
 388                          (DF   "")])
 389
 390 ;; Register suffix narrowed modes for VQN.
 391 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
 392                            (V2DI ".2s")
 393                            (DI   "")    (SI   "")
 394                            (HI   "")])
 395
 396 ;; Mode-to-individual element type mapping.
 397 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
 398                           (V4HI "h") (V8HI  "h")
 399                           (V2SI "s") (V4SI  "s")
 400                           (V2DI "d") (V4HF "h")
 401                           (V8HF "h") (V2SF  "s")
 402                           (V4SF "s") (V2DF  "d")
 403                           (SF   "s") (DF  "d")
 404                           (QI "b")   (HI "h")
 405                           (SI "s")   (DI "d")])
 406
 407 ;; Mode-to-bitwise operation type mapping.
 408 (define_mode_attr Vbtype [(V8QI "8b")  (V16QI "16b")
 409                           (V4HI "8b") (V8HI  "16b")
 410                           (V2SI "8b") (V4SI  "16b")
 411                           (V2DI "16b") (V4HF "8b")
 412                           (V8HF "16b") (V2SF  "8b")
 413                           (V4SF "16b") (V2DF  "16b")
 414                           (DI   "8b")  (DF    "8b")
 415                           (SI   "8b")])
 416
 417 ;; Define element mode for each vector mode.
 418 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
 419                         (V4HI "HI") (V8HI "HI")
 420                         (V2SI "SI") (V4SI "SI")
 421                         (DI "DI")   (V2DI "DI")
 422                         (V4HF "HF") (V8HF "HF")
 423                         (V2SF "SF") (V4SF "SF")
 424                         (V2DF "DF") (DF "DF")
 425                         (SI   "SI") (HI   "HI")
 426                         (QI   "QI")])
 427
 428 ;; 64-bit container modes the inner or scalar source mode.
 429 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
 430                          (V4HI "V4HI") (V8HI "V4HI")
 431                          (V2SI "V2SI") (V4SI "V2SI")
 432                          (DI   "DI") (V2DI "DI")
 433                          (V2SF "V2SF") (V4SF "V2SF")
 434                          (V2DF "DF")])
 435
 436 ;; 128-bit container modes the inner or scalar source mode.
 437 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
 438                          (V4HI "V8HI") (V8HI "V8HI")
 439                          (V2SI "V4SI") (V4SI "V4SI")
 440                          (DI   "V2DI") (V2DI "V2DI")
 441                          (V4HF "V8HF") (V8HF "V8HF")
 442                          (V2SF "V2SF") (V4SF "V4SF")
 443                          (V2DF "V2DF") (SI   "V4SI")
 444                          (HI   "V8HI") (QI   "V16QI")])
 445
 446 ;; Half modes of all vector modes.
 447 (define_mode_attr VHALF [(V8QI "V4QI")  (V16QI "V8QI")
 448                          (V4HI "V2HI")  (V8HI  "V4HI")
 449                          (V2SI "SI")    (V4SI  "V2SI")
 450                          (V2DI "DI")    (V2SF  "SF")
 451                          (V4SF "V2SF")  (V4HF "V2HF")
 452                          (V8HF "V4HF")  (V2DF  "DF")])
 453
 454 ;; Double modes of vector modes.
 455 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
 456                         (V4HF "V8HF")
 457                         (V2SI "V4SI")  (V2SF "V4SF")
 458                         (SI   "V2SI")  (DI   "V2DI")
 459                         (DF   "V2DF")])
 460
 461 ;; Register suffix for double-length mode.
 462 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
 463
 464 ;; Double modes of vector modes (lower case).
 465 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
 466                         (V4HF "v8hf")
 467                         (V2SI "v4si")  (V2SF "v4sf")
 468                         (SI   "v2si")  (DI   "v2di")
 469                         (DF   "v2df")])
 470
 471 ;; Narrowed modes for VDN.
 472 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
 473                             (DI   "V2SI")])
 474
 475 ;; Narrowed double-modes for VQN (Used for XTN).
 476 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
 477                             (V2DI "V2SI")
 478                             (DI   "SI")   (SI   "HI")
 479                             (HI   "QI")])
 480
 481 ;; Narrowed quad-modes for VQN (Used for XTN2).
 482 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
 483                              (V2DI "V4SI")])
 484
 485 ;; Register suffix narrowed modes for VQN.
 486 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
 487                           (V2DI "2s")])
 488
 489 ;; Register suffix narrowed modes for VQN.
 490 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
 491                            (V2DI "4s")])
 492
 493 ;; Widened modes of vector modes.
 494 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
 495                          (V2SI "V2DI") (V16QI "V8HI")
 496                          (V8HI "V4SI") (V4SI "V2DI")
 497                          (HI "SI")     (SI "DI")
 498                          (V8HF "V4SF") (V4SF "V2DF")
 499                          (V4HF "V4SF") (V2SF "V2DF")]
 500 )
 501
 502 ;; Widened modes of vector modes, lowercase
 503 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
 504
 505 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
 506 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
 507                           (V2SI "2d") (V16QI "8h")
 508                           (V8HI "4s") (V4SI "2d")
 509                           (V8HF "4s") (V4SF "2d")])
 510
 511 ;; Widened mode register suffixes for VDW/VQW.
 512 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
 513                            (V2SI ".2d") (V16QI ".8h")
 514                            (V8HI ".4s") (V4SI ".2d")
 515                            (V4HF ".4s") (V2SF ".2d")
 516                            (SI   "")    (HI   "")])
 517
 518 ;; Lower part register suffixes for VQW/VQ_HSF.
 519 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
 520                              (V4SI "2s") (V8HF "4h")
 521                              (V4SF "2s")])
 522
 523 ;; Define corresponding core/FP element mode for each vector mode.
 524 (define_mode_attr vw   [(V8QI "w") (V16QI "w")
 525                         (V4HI "w") (V8HI "w")
 526                         (V2SI "w") (V4SI "w")
 527                         (DI   "x") (V2DI "x")
 528                         (V2SF "s") (V4SF "s")
 529                         (V2DF "d")])
 530
 531 ;; Corresponding core element mode for each vector mode.  This is a
 532 ;; variation on <vw> mapping FP modes to GP regs.
 533 (define_mode_attr vwcore  [(V8QI "w") (V16QI "w")
 534                            (V4HI "w") (V8HI "w")
 535                            (V2SI "w") (V4SI "w")
 536                            (DI   "x") (V2DI "x")
 537                            (V2SF "w") (V4SF "w")
 538                            (V2DF "x")])
 539
 540 ;; Double vector types for ALLX.
 541 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
 542
 543 ;; Mode of result of comparison operations.
 544 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
 545                                 (V4HI "V4HI") (V8HI  "V8HI")
 546                                 (V2SI "V2SI") (V4SI  "V4SI")
 547                                 (DI   "DI")   (V2DI  "V2DI")
 548                                 (V4HF "V4HI") (V8HF  "V8HI")
 549                                 (V2SF "V2SI") (V4SF  "V4SI")
 550                                 (V2DF "V2DI") (DF    "DI")
 551                                 (SF   "SI")])
 552
 553 ;; Lower case mode of results of comparison operations.
 554 (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
 555                                 (V4HI "v4hi") (V8HI  "v8hi")
 556                                 (V2SI "v2si") (V4SI  "v4si")
 557                                 (DI   "di")   (V2DI  "v2di")
 558                                 (V4HF "v4hi") (V8HF  "v8hi")
 559                                 (V2SF "v2si") (V4SF  "v4si")
 560                                 (V2DF "v2di") (DF    "di")
 561                                 (SF   "si")])
 562
 563 ;; Lower case element modes (as used in shift immediate patterns).
 564 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
 565                            (V4HI "hi") (V8HI  "hi")
 566                            (V2SI "si") (V4SI  "si")
 567                            (DI   "di") (V2DI  "di")
 568                            (QI   "qi") (HI    "hi")
 569                            (SI   "si")])
 570
 571 ;; Vm for lane instructions is restricted to FP_LO_REGS.
 572 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
 573                        (V2SI "w") (V4SI "w") (SI "w")])
 574
 575 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
 576
 577 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
 578
 579 (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI")
 580                         (V4HF "V16HF")
 581                         (V2SI "V8SI")  (V2SF "V8SF")
 582                         (DI   "V4DI")  (DF   "V4DF")])
 583
 584 (define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI")
 585                         (V4HF "V24HF")
 586                         (V2SI "V12SI")  (V2SF "V12SF")
 587                         (DI   "V6DI")  (DF   "V6DF")])
 588
 589 (define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI")
 590                         (V4HF "V32HF")
 591                         (V2SI "V16SI")  (V2SF "V16SF")
 592                         (DI   "V8DI")  (DF   "V8DF")])
 593
 594 (define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
 595
 596 ;; Mode of pair of elements for each vector mode, to define transfer
 597 ;; size for structure lane/dup loads and stores.
 598 (define_mode_attr V_TWO_ELEM [(V8QI "HI")   (V16QI "HI")
 599                               (V4HI "SI")   (V8HI "SI")
 600                               (V2SI "V2SI") (V4SI "V2SI")
 601                               (DI "V2DI")   (V2DI "V2DI")
 602                               (V2SF "V2SF") (V4SF "V2SF")
 603                               (V4HF "SF") (V8HF "SF")
 604                               (DF "V2DI")   (V2DF "V2DI")])
 605
 606 ;; Similar, for three elements.
 607 (define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK")
 608                                 (V4HI "BLK") (V8HI "BLK")
 609                                 (V2SI "BLK") (V4SI "BLK")
 610                                 (DI "EI")    (V2DI "EI")
 611                                 (V2SF "BLK") (V4SF "BLK")
 612                                 (V4HF "BLK") (V8HF "BLK")
 613                                 (DF "EI")    (V2DF "EI")])
 614
 615 ;; Similar, for four elements.
 616 (define_mode_attr V_FOUR_ELEM [(V8QI "SI")   (V16QI "SI")
 617                                (V4HI "V4HI") (V8HI "V4HI")
 618                                (V2SI "V4SI") (V4SI "V4SI")
 619                                (DI "OI")     (V2DI "OI")
 620                                (V2SF "V4SF") (V4SF "V4SF")
 621                                (V4HF "V4HF") (V8HF "V4HF")
 622                                (DF "OI")     (V2DF "OI")])
 623
 624
 625 ;; Mode for atomic operation suffixes
 626 (define_mode_attr atomic_sfx
 627   [(QI "b") (HI "h") (SI "") (DI "")])
 628
 629 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
 630 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
 631
 632 ;; for the inequal width integer to fp conversions
 633 (define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
 634 (define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
 635
 636 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
 637                                 (V4HI "V8HI") (V8HI  "V4HI")
 638                                 (V2SI "V4SI") (V4SI  "V2SI")
 639                                 (DI   "V2DI") (V2DI  "DI")
 640                                 (V2SF "V4SF") (V4SF  "V2SF")
 641                                 (V4HF "V8HF") (V8HF  "V4HF")
 642                                 (DF   "V2DF") (V2DF  "DF")])
 643
 644 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
 645                                     (V4HI "to_128") (V8HI  "to_64")
 646                                     (V2SI "to_128") (V4SI  "to_64")
 647                                     (DI   "to_128") (V2DI  "to_64")
 648                                     (V4HF "to_128") (V8HF  "to_64")
 649                                     (V2SF "to_128") (V4SF  "to_64")
 650                                     (DF   "to_128") (V2DF  "to_64")])
 651
 652 ;; For certain vector-by-element multiplication instructions we must
 653 ;; constrain the HI cases to use only V0-V15.  This is covered by
 654 ;; the 'x' constraint.  All other modes may use the 'w' constraint.
 655 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
 656                          (V4HI "x") (V8HI "x")
 657                          (V2SF "w") (V4SF "w")
 658                          (V2DF "w") (DF "w")])
 659
 660 ;; Defined to 'f' for types whose element type is a float type.
 661 (define_mode_attr f [(V8QI "")  (V16QI "")
 662                      (V4HI "")  (V8HI  "")
 663                      (V2SI "")  (V4SI  "")
 664                      (DI   "")  (V2DI  "")
 665                      (V2SF "f") (V4SF  "f")
 666                      (V2DF "f") (DF    "f")])
 667
 668 ;; Defined to '_fp' for types whose element type is a float type.
 669 (define_mode_attr fp [(V8QI "")  (V16QI "")
 670                       (V4HI "")  (V8HI  "")
 671                       (V2SI "")  (V4SI  "")
 672                       (DI   "")  (V2DI  "")
 673                       (V2SF "_fp") (V4SF  "_fp")
 674                       (V2DF "_fp") (DF    "_fp")
 675                       (SF "_fp")])
 676
 677 ;; Defined to '_q' for 128-bit types.
 678 (define_mode_attr q [(V8QI "") (V16QI "_q")
 679                      (V4HI "") (V8HI  "_q")
 680                      (V2SI "") (V4SI  "_q")
 681                      (DI   "") (V2DI  "_q")
 682                      (V4HF "") (V8HF "_q")
 683                      (V2SF "") (V4SF  "_q")
 684                                (V2DF  "_q")
 685                      (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
 686
 687 (define_mode_attr vp [(V8QI "v") (V16QI "v")
 688                       (V4HI "v") (V8HI  "v")
 689                       (V2SI "p") (V4SI  "v")
 690                       (V2DI  "p") (V2DF  "p")
 691                       (V2SF "p") (V4SF  "v")])
 692
 693 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
 694 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
 695
 696 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
 697
 698 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
 699 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
 700 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
 701
 702 ;; -------------------------------------------------------------------
 703 ;; Code Iterators
 704 ;; -------------------------------------------------------------------
 705
 706 ;; This code iterator allows the various shifts supported on the core
 707 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
 708
 709 ;; This code iterator allows the shifts supported in arithmetic instructions
 710 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
 711
 712 ;; Code iterator for logical operations
 713 (define_code_iterator LOGICAL [and ior xor])
 714
 715 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
 716 (define_code_iterator NLOGICAL [and ior])
 717
 718 ;; Code iterator for sign/zero extension
 719 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
 720
 721 ;; All division operations (signed/unsigned)
 722 (define_code_iterator ANY_DIV [div udiv])
 723
 724 ;; Code iterator for sign/zero extraction
 725 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
 726
 727 ;; Code iterator for equality comparisons
 728 (define_code_iterator EQL [eq ne])
 729
 730 ;; Code iterator for less-than and greater/equal-to
 731 (define_code_iterator LTGE [lt ge])
 732
 733 ;; Iterator for __sync_<op> operations that where the operation can be
 734 ;; represented directly RTL.  This is all of the sync operations bar
 735 ;; nand.
 736 (define_code_iterator atomic_op [plus minus ior xor and])
 737
 738 ;; Iterator for integer conversions
 739 (define_code_iterator FIXUORS [fix unsigned_fix])
 740
 741 ;; Iterator for float conversions
 742 (define_code_iterator FLOATUORS [float unsigned_float])
 743
 744 ;; Code iterator for variants of vector max and min.
 745 (define_code_iterator MAXMIN [smax smin umax umin])
 746
 747 (define_code_iterator FMAXMIN [smax smin])
 748
 749 ;; Code iterator for variants of vector max and min.
 750 (define_code_iterator ADDSUB [plus minus])
 751
 752 ;; Code iterator for variants of vector saturating binary ops.
 753 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
 754
 755 ;; Code iterator for variants of vector saturating unary ops.
 756 (define_code_iterator UNQOPS [ss_neg ss_abs])
 757
 758 ;; Code iterator for signed variants of vector saturating binary ops.
 759 (define_code_iterator SBINQOPS [ss_plus ss_minus])
 760
 761 ;; Comparison operators for <F>CM.
 762 (define_code_iterator COMPARISONS [lt le eq ge gt])
 763
 764 ;; Unsigned comparison operators.
 765 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
 766
 767 ;; Unsigned comparison operators.
 768 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
 769
 770 ;; -------------------------------------------------------------------
 771 ;; Code Attributes
 772 ;; -------------------------------------------------------------------
 773 ;; Map rtl objects to optab names
 774 (define_code_attr optab [(ashift "ashl")
 775                          (ashiftrt "ashr")
 776                          (lshiftrt "lshr")
 777                          (rotatert "rotr")
 778                          (sign_extend "extend")
 779                          (zero_extend "zero_extend")
 780                          (sign_extract "extv")
 781                          (zero_extract "extzv")
 782                          (fix "fix")
 783                          (unsigned_fix "fixuns")
 784                          (float "float")
 785                          (unsigned_float "floatuns")
 786                          (and "and")
 787                          (ior "ior")
 788                          (xor "xor")
 789                          (not "one_cmpl")
 790                          (neg "neg")
 791                          (plus "add")
 792                          (minus "sub")
 793                          (ss_plus "qadd")
 794                          (us_plus "qadd")
 795                          (ss_minus "qsub")
 796                          (us_minus "qsub")
 797                          (ss_neg "qneg")
 798                          (ss_abs "qabs")
 799                          (eq "eq")
 800                          (ne "ne")
 801                          (lt "lt")
 802                          (ge "ge")
 803                          (le "le")
 804                          (gt "gt")
 805                          (ltu "ltu")
 806                          (leu "leu")
 807                          (geu "geu")
 808                          (gtu "gtu")])
 809
 810 ;; For comparison operators we use the FCM* and CM* instructions.
 811 ;; As there are no CMLE or CMLT instructions which act on 3 vector
 812 ;; operands, we must use CMGE or CMGT and swap the order of the
 813 ;; source operands.
 814
 815 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
 816                            (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
 817 (define_code_attr cmp_1   [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
 818                            (ltu "2") (leu "2") (geu "1") (gtu "1")])
 819 (define_code_attr cmp_2   [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
 820                            (ltu "1") (leu "1") (geu "2") (gtu "2")])
 821
 822 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
 823                            (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")])
 824
 825 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
 826                                    (unsigned_fix "fixuns_trunc")])
 827
 828 ;; Optab prefix for sign/zero-extending operations
 829 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
 830                             (div "") (udiv "u")
 831                             (fix "") (unsigned_fix "u")
 832                             (float "s") (unsigned_float "u")
 833                             (ss_plus "s") (us_plus "u")
 834                             (ss_minus "s") (us_minus "u")])
 835
 836 ;; Similar for the instruction mnemonics
 837 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
 838                          (lshiftrt "lsr") (rotatert "ror")])
 839
 840 ;; Map shift operators onto underlying bit-field instructions
 841 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
 842                            (lshiftrt "ubfx") (rotatert "extr")])
 843
 844 ;; Logical operator instruction mnemonics
 845 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
 846
 847 ;; Similar, but when not(op)
 848 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
 849
 850 ;; Sign- or zero-extending load
 851 (define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
 852
 853 ;; Sign- or zero-extending data-op
 854 (define_code_attr su [(sign_extend "s") (zero_extend "u")
 855                       (sign_extract "s") (zero_extract "u")
 856                       (fix "s") (unsigned_fix "u")
 857                       (div "s") (udiv "u")
 858                       (smax "s") (umax "u")
 859                       (smin "s") (umin "u")])
 860
 861 ;; Emit conditional branch instructions.
 862 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
 863
 864 ;; Emit cbz/cbnz depending on comparison type.
 865 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
 866
 867 ;; Emit inverted cbz/cbnz depending on comparison type.
 868 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
 869
 870 ;; Emit tbz/tbnz depending on comparison type.
 871 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
 872
 873 ;; Emit inverted tbz/tbnz depending on comparison type.
 874 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
 875
 876 ;; Max/min attributes.
 877 (define_code_attr maxmin [(smax "max")
 878                           (smin "min")
 879                           (umax "max")
 880                           (umin "min")])
 881
 882 ;; MLA/MLS attributes.
 883 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
 884
 885 ;; Atomic operations
 886 (define_code_attr atomic_optab
 887   [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
 888
 889 (define_code_attr atomic_op_operand
 890   [(ior "aarch64_logical_operand")
 891    (xor "aarch64_logical_operand")
 892    (and "aarch64_logical_operand")
 893    (plus "aarch64_plus_operand")
 894    (minus "aarch64_plus_operand")])
 895
 896 ;; Constants acceptable for atomic operations.
 897 ;; This definition must appear in this file before the iterators it refers to.
 898 (define_code_attr const_atomic
 899  [(plus "IJ") (minus "IJ")
 900   (xor "<lconst_atomic>") (ior "<lconst_atomic>")
 901   (and "<lconst_atomic>")])
 902
 903 ;; Attribute to describe constants acceptable in atomic logical operations
 904 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
 905
 906 ;; -------------------------------------------------------------------
 907 ;; Int Iterators.
 908 ;; -------------------------------------------------------------------
 909 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
 910                               UNSPEC_SMAXV UNSPEC_SMINV])
 911
 912 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
 913                                UNSPEC_FMAXNMV UNSPEC_FMINNMV])
 914
 915 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
 916                               UNSPEC_SRHADD UNSPEC_URHADD
 917                               UNSPEC_SHSUB UNSPEC_UHSUB
 918                               UNSPEC_SRHSUB UNSPEC_URHSUB])
 919
 920
 921 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
 922                                UNSPEC_SUBHN UNSPEC_RSUBHN])
 923
 924 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
 925                                 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
 926
 927 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN])
 928
 929 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
 930
 931 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
 932
 933 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
 934
 935 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
 936                            UNSPEC_SRSHL UNSPEC_URSHL])
 937
 938 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
 939
 940 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
 941                             UNSPEC_SQRSHL UNSPEC_UQRSHL])
 942
 943 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
 944                              UNSPEC_SRSRA UNSPEC_URSRA])
 945
 946 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
 947                               UNSPEC_SSRI UNSPEC_USRI])
 948
 949
 950 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
 951
 952 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
 953
 954 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
 955                                UNSPEC_SQSHRN UNSPEC_UQSHRN
 956                                UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
 957
 958 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
 959                               UNSPEC_TRN1 UNSPEC_TRN2
 960                               UNSPEC_UZP1 UNSPEC_UZP2])
 961
 962 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
 963
 964 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
 965                              UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
 966                              UNSPEC_FRINTA])
 967
 968 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
 969                             UNSPEC_FRINTA UNSPEC_FRINTN])
 970
 971 (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
 972
 973 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
 974                           UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
 975                           UNSPEC_CRC32CW UNSPEC_CRC32CX])
 976
 977 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
 978 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
 979
 980 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
 981
 982 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
 983
 984 ;; -------------------------------------------------------------------
 985 ;; Int Iterators Attributes.
 986 ;; -------------------------------------------------------------------
 987 (define_int_attr  maxmin_uns [(UNSPEC_UMAXV "umax")
 988                               (UNSPEC_UMINV "umin")
 989                               (UNSPEC_SMAXV "smax")
 990                               (UNSPEC_SMINV "smin")
 991                               (UNSPEC_FMAX  "smax_nan")
 992                               (UNSPEC_FMAXNMV "smax")
 993                               (UNSPEC_FMAXV "smax_nan")
 994                               (UNSPEC_FMIN "smin_nan")
 995                               (UNSPEC_FMINNMV "smin")
 996                               (UNSPEC_FMINV "smin_nan")])
 997
 998 (define_int_attr  maxmin_uns_op [(UNSPEC_UMAXV "umax")
 999                                  (UNSPEC_UMINV "umin")
1000                                  (UNSPEC_SMAXV "smax")
1001                                  (UNSPEC_SMINV "smin")
1002                                  (UNSPEC_FMAX "fmax")
1003                                  (UNSPEC_FMAXNMV "fmaxnm")
1004                                  (UNSPEC_FMAXV "fmax")
1005                                  (UNSPEC_FMIN "fmin")
1006                                  (UNSPEC_FMINNMV "fminnm")
1007                                  (UNSPEC_FMINV "fmin")])
1008
1009 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1010                       (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1011                       (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1012                       (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1013                       (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1014                       (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1015                       (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1016                       (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1017                       (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1018                       (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1019                       (UNSPEC_SSLI  "s") (UNSPEC_USLI  "u")
1020                       (UNSPEC_SSRI  "s") (UNSPEC_USRI  "u")
1021                       (UNSPEC_USRA  "u") (UNSPEC_SSRA  "s")
1022                       (UNSPEC_URSRA  "ur") (UNSPEC_SRSRA  "sr")
1023                       (UNSPEC_URSHR  "ur") (UNSPEC_SRSHR  "sr")
1024                       (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL   "s")
1025                       (UNSPEC_UQSHL  "u")
1026                       (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1027                       (UNSPEC_SQSHRN "s")  (UNSPEC_UQSHRN "u")
1028                       (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1029                       (UNSPEC_USHL  "u")   (UNSPEC_SSHL  "s")
1030                       (UNSPEC_USHLL  "u")  (UNSPEC_SSHLL "s")
1031                       (UNSPEC_URSHL  "ur") (UNSPEC_SRSHL  "sr")
1032                       (UNSPEC_UQRSHL  "u") (UNSPEC_SQRSHL  "s")
1033 ])
1034
1035 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1036                     (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1037                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1038                     (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1039                     (UNSPEC_SQSHL   "")  (UNSPEC_UQSHL  "")
1040                     (UNSPEC_SQRSHL   "r")(UNSPEC_UQRSHL  "r")
1041 ])
1042
1043 (define_int_attr lr [(UNSPEC_SSLI  "l") (UNSPEC_USLI  "l")
1044                      (UNSPEC_SSRI  "r") (UNSPEC_USRI  "r")])
1045
1046 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1047                     (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1048                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1049                     (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1050
1051 (define_int_attr addsub [(UNSPEC_SHADD "add")
1052                          (UNSPEC_UHADD "add")
1053                          (UNSPEC_SRHADD "add")
1054                          (UNSPEC_URHADD "add")
1055                          (UNSPEC_SHSUB "sub")
1056                          (UNSPEC_UHSUB "sub")
1057                          (UNSPEC_SRHSUB "sub")
1058                          (UNSPEC_URHSUB "sub")
1059                          (UNSPEC_ADDHN "add")
1060                          (UNSPEC_SUBHN "sub")
1061                          (UNSPEC_RADDHN "add")
1062                          (UNSPEC_RSUBHN "sub")
1063                          (UNSPEC_ADDHN2 "add")
1064                          (UNSPEC_SUBHN2 "sub")
1065                          (UNSPEC_RADDHN2 "add")
1066                          (UNSPEC_RSUBHN2 "sub")])
1067
1068 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1069                            (UNSPEC_SSRI "offset_")
1070                            (UNSPEC_USRI "offset_")])
1071
1072 ;; Standard pattern names for floating-point rounding instructions.
1073 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1074                                 (UNSPEC_FRINTP "ceil")
1075                                 (UNSPEC_FRINTM "floor")
1076                                 (UNSPEC_FRINTI "nearbyint")
1077                                 (UNSPEC_FRINTX "rint")
1078                                 (UNSPEC_FRINTA "round")
1079                                 (UNSPEC_FRINTN "frintn")])
1080
1081 ;; frint suffix for floating-point rounding instructions.
1082 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1083                                (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
1084                                (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1085                                (UNSPEC_FRINTN "n")])
1086
1087 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
1088                                (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1089                                (UNSPEC_FRINTN "frintn")])
1090
1091 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1092                             (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1093                             (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1094
1095 ; op code for REV instructions (size within which elements are reversed).
1096 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1097                          (UNSPEC_REV16 "16")])
1098
1099 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1100                             (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
1101                             (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
1102
1103 (define_int_attr frecp_suffix  [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
1104
1105 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1106                         (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1107                         (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1108                         (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1109
1110 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1111                         (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1112                         (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1113                         (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1114
1115 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1116 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
1117
1118 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1119                           (UNSPEC_SHA1M "m")])
1120
1121 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])