gcc/config/aarch64/iterators.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2015 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; -------------------------------------------------------------------
  22 ;; Mode Iterators
  23 ;; -------------------------------------------------------------------
  24
  25
  26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
  27 (define_mode_iterator GPI [SI DI])
  28
  29 ;; Iterator for QI and HI modes
  30 (define_mode_iterator SHORT [QI HI])
  31
  32 ;; Iterator for all integer modes (up to 64-bit)
  33 (define_mode_iterator ALLI [QI HI SI DI])
  34
  35 ;; Iterator for all integer modes that can be extended (up to 64-bit)
  36 (define_mode_iterator ALLX [QI HI SI])
  37
  38 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
  39 (define_mode_iterator GPF [SF DF])
  40
  41 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
  42 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
  43
  44 ;; Double vector modes.
  45 (define_mode_iterator VDF [V2SF V4HF])
  46
  47 ;; Iterator for all scalar floating point modes (SF, DF and TF)
  48 (define_mode_iterator GPF_TF [SF DF TF])
  49
  50 ;; Integer vector modes.
  51 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
  52
  53 ;; vector and scalar, 64 & 128-bit container, all integer modes
  54 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
  55
  56 ;; vector and scalar, 64 & 128-bit container: all vector integer modes;
  57 ;; 64-bit scalar integer mode
  58 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
  59
  60 ;; Double vector modes.
  61 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
  62
  63 ;; vector, 64-bit container, all integer modes
  64 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
  65
  66 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
  67 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
  68
  69 ;; Quad vector modes.
  70 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
  71
  72 ;; VQ without 2 element modes.
  73 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
  74
  75 ;; Quad vector with only 2 element modes.
  76 (define_mode_iterator VQ_2E [V2DI V2DF])
  77
  78 ;; This mode iterator allows :P to be used for patterns that operate on
  79 ;; addresses in different modes.  In LP64, only DI will match, while in
  80 ;; ILP32, either can match.
  81 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
  82                          (DI "ptr_mode == DImode || Pmode == DImode")])
  83
  84 ;; This mode iterator allows :PTR to be used for patterns that operate on
  85 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
  86 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
  87
  88 ;; Vector Float modes suitable for moving, loading and storing.
  89 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
  90
  91 ;; Vector Float modes, barring HF modes.
  92 (define_mode_iterator VDQF [V2SF V4SF V2DF])
  93
  94 ;; Vector Float modes, and DF.
  95 (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
  96
  97 ;; Vector single Float modes.
  98 (define_mode_iterator VDQSF [V2SF V4SF])
  99
 100 ;; Quad vector Float modes with half/single elements.
 101 (define_mode_iterator VQ_HSF [V8HF V4SF])
 102
 103 ;; Modes suitable to use as the return type of a vcond expression.
 104 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
 105
 106 ;; All Float modes.
 107 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
 108
 109 ;; Vector Float modes with 2 elements.
 110 (define_mode_iterator V2F [V2SF V2DF])
 111
 112 ;; All vector modes on which we support any arithmetic operations.
 113 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
 114
 115 ;; All vector modes suitable for moving, loading, and storing.
 116 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 117                                 V4HF V8HF V2SF V4SF V2DF])
 118
 119 ;; All vector modes barring HF modes, plus DI.
 120 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
 121
 122 ;; All vector modes and DI.
 123 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 124                                   V4HF V8HF V2SF V4SF V2DF DI])
 125
 126 ;; All vector modes, plus DI and DF.
 127 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
 128                                V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
 129
 130 ;; Vector modes for Integer reduction across lanes.
 131 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
 132
 133 ;; Vector modes(except V2DI) for Integer reduction across lanes.
 134 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
 135
 136 ;; All double integer narrow-able modes.
 137 (define_mode_iterator VDN [V4HI V2SI DI])
 138
 139 ;; All quad integer narrow-able modes.
 140 (define_mode_iterator VQN [V8HI V4SI V2DI])
 141
 142 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
 143 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
 144
 145 ;; All quad integer widen-able modes.
 146 (define_mode_iterator VQW [V16QI V8HI V4SI])
 147
 148 ;; Double vector modes for combines.
 149 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
 150
 151 ;; Vector modes except double int.
 152 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 153
 154 ;; Vector modes for S type.
 155 (define_mode_iterator VDQ_SI [V2SI V4SI])
 156
 157 ;; Vector modes for Q and H types.
 158 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
 159
 160 ;; Vector modes for H and S types.
 161 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
 162
 163 ;; Vector modes for H, S and D types.
 164 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
 165
 166 ;; Vector and scalar integer modes for H and S
 167 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
 168
 169 ;; Vector and scalar 64-bit container: 16, 32-bit integer modes
 170 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
 171
 172 ;; Vector 64-bit container: 16, 32-bit integer modes
 173 (define_mode_iterator VD_HSI [V4HI V2SI])
 174
 175 ;; Scalar 64-bit container: 16, 32-bit integer modes
 176 (define_mode_iterator SD_HSI [HI SI])
 177
 178 ;; Vector 64-bit container: 16, 32-bit integer modes
 179 (define_mode_iterator VQ_HSI [V8HI V4SI])
 180
 181 ;; All byte modes.
 182 (define_mode_iterator VB [V8QI V16QI])
 183
 184 ;; 2 and 4 lane SI modes.
 185 (define_mode_iterator VS [V2SI V4SI])
 186
 187 (define_mode_iterator TX [TI TF])
 188
 189 ;; Opaque structure modes.
 190 (define_mode_iterator VSTRUCT [OI CI XI])
 191
 192 ;; Double scalar modes
 193 (define_mode_iterator DX [DI DF])
 194
 195 ;; Modes available for <f>mul lane operations.
 196 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 197
 198 ;; Modes available for <f>mul lane operations changing lane count.
 199 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
 200
 201 ;; ------------------------------------------------------------------
 202 ;; Unspec enumerations for Advance SIMD. These could well go into
 203 ;; aarch64.md but for their use in int_iterators here.
 204 ;; ------------------------------------------------------------------
 205
 206 (define_c_enum "unspec"
 207  [
 208     UNSPEC_ASHIFT_SIGNED        ; Used in aarch-simd.md.
 209     UNSPEC_ASHIFT_UNSIGNED      ; Used in aarch64-simd.md.
 210     UNSPEC_ABS          ; Used in aarch64-simd.md.
 211     UNSPEC_FMAX         ; Used in aarch64-simd.md.
 212     UNSPEC_FMAXNMV      ; Used in aarch64-simd.md.
 213     UNSPEC_FMAXV        ; Used in aarch64-simd.md.
 214     UNSPEC_FMIN         ; Used in aarch64-simd.md.
 215     UNSPEC_FMINNMV      ; Used in aarch64-simd.md.
 216     UNSPEC_FMINV        ; Used in aarch64-simd.md.
 217     UNSPEC_FADDV        ; Used in aarch64-simd.md.
 218     UNSPEC_ADDV         ; Used in aarch64-simd.md.
 219     UNSPEC_SMAXV        ; Used in aarch64-simd.md.
 220     UNSPEC_SMINV        ; Used in aarch64-simd.md.
 221     UNSPEC_UMAXV        ; Used in aarch64-simd.md.
 222     UNSPEC_UMINV        ; Used in aarch64-simd.md.
 223     UNSPEC_SHADD        ; Used in aarch64-simd.md.
 224     UNSPEC_UHADD        ; Used in aarch64-simd.md.
 225     UNSPEC_SRHADD       ; Used in aarch64-simd.md.
 226     UNSPEC_URHADD       ; Used in aarch64-simd.md.
 227     UNSPEC_SHSUB        ; Used in aarch64-simd.md.
 228     UNSPEC_UHSUB        ; Used in aarch64-simd.md.
 229     UNSPEC_SRHSUB       ; Used in aarch64-simd.md.
 230     UNSPEC_URHSUB       ; Used in aarch64-simd.md.
 231     UNSPEC_ADDHN        ; Used in aarch64-simd.md.
 232     UNSPEC_RADDHN       ; Used in aarch64-simd.md.
 233     UNSPEC_SUBHN        ; Used in aarch64-simd.md.
 234     UNSPEC_RSUBHN       ; Used in aarch64-simd.md.
 235     UNSPEC_ADDHN2       ; Used in aarch64-simd.md.
 236     UNSPEC_RADDHN2      ; Used in aarch64-simd.md.
 237     UNSPEC_SUBHN2       ; Used in aarch64-simd.md.
 238     UNSPEC_RSUBHN2      ; Used in aarch64-simd.md.
 239     UNSPEC_SQDMULH      ; Used in aarch64-simd.md.
 240     UNSPEC_SQRDMULH     ; Used in aarch64-simd.md.
 241     UNSPEC_PMUL         ; Used in aarch64-simd.md.
 242     UNSPEC_FMULX        ; Used in aarch64-simd.md.
 243     UNSPEC_USQADD       ; Used in aarch64-simd.md.
 244     UNSPEC_SUQADD       ; Used in aarch64-simd.md.
 245     UNSPEC_SQXTUN       ; Used in aarch64-simd.md.
 246     UNSPEC_SQXTN        ; Used in aarch64-simd.md.
 247     UNSPEC_UQXTN        ; Used in aarch64-simd.md.
 248     UNSPEC_SSRA         ; Used in aarch64-simd.md.
 249     UNSPEC_USRA         ; Used in aarch64-simd.md.
 250     UNSPEC_SRSRA        ; Used in aarch64-simd.md.
 251     UNSPEC_URSRA        ; Used in aarch64-simd.md.
 252     UNSPEC_SRSHR        ; Used in aarch64-simd.md.
 253     UNSPEC_URSHR        ; Used in aarch64-simd.md.
 254     UNSPEC_SQSHLU       ; Used in aarch64-simd.md.
 255     UNSPEC_SQSHL        ; Used in aarch64-simd.md.
 256     UNSPEC_UQSHL        ; Used in aarch64-simd.md.
 257     UNSPEC_SQSHRUN      ; Used in aarch64-simd.md.
 258     UNSPEC_SQRSHRUN     ; Used in aarch64-simd.md.
 259     UNSPEC_SQSHRN       ; Used in aarch64-simd.md.
 260     UNSPEC_UQSHRN       ; Used in aarch64-simd.md.
 261     UNSPEC_SQRSHRN      ; Used in aarch64-simd.md.
 262     UNSPEC_UQRSHRN      ; Used in aarch64-simd.md.
 263     UNSPEC_SSHL         ; Used in aarch64-simd.md.
 264     UNSPEC_USHL         ; Used in aarch64-simd.md.
 265     UNSPEC_SRSHL        ; Used in aarch64-simd.md.
 266     UNSPEC_URSHL        ; Used in aarch64-simd.md.
 267     UNSPEC_SQRSHL       ; Used in aarch64-simd.md.
 268     UNSPEC_UQRSHL       ; Used in aarch64-simd.md.
 269     UNSPEC_SSLI         ; Used in aarch64-simd.md.
 270     UNSPEC_USLI         ; Used in aarch64-simd.md.
 271     UNSPEC_SSRI         ; Used in aarch64-simd.md.
 272     UNSPEC_USRI         ; Used in aarch64-simd.md.
 273     UNSPEC_SSHLL        ; Used in aarch64-simd.md.
 274     UNSPEC_USHLL        ; Used in aarch64-simd.md.
 275     UNSPEC_ADDP         ; Used in aarch64-simd.md.
 276     UNSPEC_TBL          ; Used in vector permute patterns.
 277     UNSPEC_TBX          ; Used in vector permute patterns.
 278     UNSPEC_CONCAT       ; Used in vector permute patterns.
 279     UNSPEC_ZIP1         ; Used in vector permute patterns.
 280     UNSPEC_ZIP2         ; Used in vector permute patterns.
 281     UNSPEC_UZP1         ; Used in vector permute patterns.
 282     UNSPEC_UZP2         ; Used in vector permute patterns.
 283     UNSPEC_TRN1         ; Used in vector permute patterns.
 284     UNSPEC_TRN2         ; Used in vector permute patterns.
 285     UNSPEC_EXT          ; Used in aarch64-simd.md.
 286     UNSPEC_REV64        ; Used in vector reverse patterns (permute).
 287     UNSPEC_REV32        ; Used in vector reverse patterns (permute).
 288     UNSPEC_REV16        ; Used in vector reverse patterns (permute).
 289     UNSPEC_AESE         ; Used in aarch64-simd.md.
 290     UNSPEC_AESD         ; Used in aarch64-simd.md.
 291     UNSPEC_AESMC        ; Used in aarch64-simd.md.
 292     UNSPEC_AESIMC       ; Used in aarch64-simd.md.
 293     UNSPEC_SHA1C        ; Used in aarch64-simd.md.
 294     UNSPEC_SHA1M        ; Used in aarch64-simd.md.
 295     UNSPEC_SHA1P        ; Used in aarch64-simd.md.
 296     UNSPEC_SHA1H        ; Used in aarch64-simd.md.
 297     UNSPEC_SHA1SU0      ; Used in aarch64-simd.md.
 298     UNSPEC_SHA1SU1      ; Used in aarch64-simd.md.
 299     UNSPEC_SHA256H      ; Used in aarch64-simd.md.
 300     UNSPEC_SHA256H2     ; Used in aarch64-simd.md.
 301     UNSPEC_SHA256SU0    ; Used in aarch64-simd.md.
 302     UNSPEC_SHA256SU1    ; Used in aarch64-simd.md.
 303     UNSPEC_PMULL        ; Used in aarch64-simd.md.
 304     UNSPEC_PMULL2       ; Used in aarch64-simd.md.
 305     UNSPEC_REV_REGLIST  ; Used in aarch64-simd.md.
 306     UNSPEC_VEC_SHR      ; Used in aarch64-simd.md.
 307 ])
 308
 309 ;; ------------------------------------------------------------------
 310 ;; Unspec enumerations for Atomics.  They are here so that they can be
 311 ;; used in the int_iterators for atomic operations.
 312 ;; ------------------------------------------------------------------
 313
 314 (define_c_enum "unspecv"
 315  [
 316     UNSPECV_LX                  ; Represent a load-exclusive.
 317     UNSPECV_SX                  ; Represent a store-exclusive.
 318     UNSPECV_LDA                 ; Represent an atomic load or load-acquire.
 319     UNSPECV_STL                 ; Represent an atomic store or store-release.
 320     UNSPECV_ATOMIC_CMPSW        ; Represent an atomic compare swap.
 321     UNSPECV_ATOMIC_EXCHG        ; Represent an atomic exchange.
 322     UNSPECV_ATOMIC_CAS          ; Represent an atomic CAS.
 323     UNSPECV_ATOMIC_SWP          ; Represent an atomic SWP.
 324     UNSPECV_ATOMIC_OP           ; Represent an atomic operation.
 325     UNSPECV_ATOMIC_LDOP         ; Represent an atomic load-operation
 326     UNSPECV_ATOMIC_LDOP_OR      ; Represent an atomic load-or
 327     UNSPECV_ATOMIC_LDOP_BIC     ; Represent an atomic load-bic
 328     UNSPECV_ATOMIC_LDOP_XOR     ; Represent an atomic load-xor
 329     UNSPECV_ATOMIC_LDOP_PLUS    ; Represent an atomic load-add
 330 ])
 331
 332 ;; -------------------------------------------------------------------
 333 ;; Mode attributes
 334 ;; -------------------------------------------------------------------
 335
 336 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
 337 ;; 32-bit version and "%x0" in the 64-bit version.
 338 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
 339
 340 ;; For inequal width int to float conversion
 341 (define_mode_attr w1 [(SF "w") (DF "x")])
 342 (define_mode_attr w2 [(SF "x") (DF "w")])
 343
 344 ;; For constraints used in scalar immediate vector moves
 345 (define_mode_attr hq [(HI "h") (QI "q")])
 346
 347 ;; For scalar usage of vector/FP registers
 348 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
 349                     (SF "s") (DF "d")
 350                     (V8QI "") (V16QI "")
 351                     (V4HI "") (V8HI "")
 352                     (V2SI "") (V4SI  "")
 353                     (V2DI "") (V2SF "")
 354                     (V4SF "") (V2DF "")])
 355
 356 ;; For scalar usage of vector/FP registers, narrowing
 357 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
 358                     (V8QI "") (V16QI "")
 359                     (V4HI "") (V8HI "")
 360                     (V2SI "") (V4SI  "")
 361                     (V2DI "") (V2SF "")
 362                     (V4SF "") (V2DF "")])
 363
 364 ;; For scalar usage of vector/FP registers, widening
 365 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
 366                     (V8QI "") (V16QI "")
 367                     (V4HI "") (V8HI "")
 368                     (V2SI "") (V4SI  "")
 369                     (V2DI "") (V2SF "")
 370                     (V4SF "") (V2DF "")])
 371
 372 ;; Register Type Name and Vector Arrangement Specifier for when
 373 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
 374 ;; lane 0).
 375 (define_mode_attr rtn [(DI "d") (SI "")])
 376 (define_mode_attr vas [(DI "") (SI ".2s")])
 377
 378 ;; Map a floating point mode to the appropriate register name prefix
 379 (define_mode_attr s [(SF "s") (DF "d")])
 380
 381 ;; Give the length suffix letter for a sign- or zero-extension.
 382 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
 383
 384 ;; Give the number of bits in the mode
 385 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
 386
 387 ;; Give the ordinal of the MSB in the mode
 388 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
 389
 390 ;; Attribute to describe constants acceptable in logical operations
 391 (define_mode_attr lconst [(SI "K") (DI "L")])
 392
 393 ;; Map a mode to a specific constraint character.
 394 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
 395
 396 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
 397                          (V4HI "4h") (V8HI  "8h")
 398                          (V2SI "2s") (V4SI  "4s")
 399                          (DI   "1d") (DF    "1d")
 400                          (V2DI "2d") (V2SF "2s")
 401                          (V4SF "4s") (V2DF "2d")
 402                          (V4HF "4h") (V8HF "8h")])
 403
 404 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
 405                             (V4SI "32") (V2DI "64")])
 406
 407 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
 408                          (V4HI ".4h") (V8HI  ".8h")
 409                          (V2SI ".2s") (V4SI  ".4s")
 410                          (V2DI ".2d") (V4HF ".4h")
 411                          (V8HF ".8h") (V2SF ".2s")
 412                          (V4SF ".4s") (V2DF ".2d")
 413                          (DI   "")    (SI   "")
 414                          (HI   "")    (QI   "")
 415                          (TI   "")    (SF   "")
 416                          (DF   "")])
 417
 418 ;; Register suffix narrowed modes for VQN.
 419 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
 420                            (V2DI ".2s")
 421                            (DI   "")    (SI   "")
 422                            (HI   "")])
 423
 424 ;; Mode-to-individual element type mapping.
 425 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
 426                           (V4HI "h") (V8HI  "h")
 427                           (V2SI "s") (V4SI  "s")
 428                           (V2DI "d") (V4HF "h")
 429                           (V8HF "h") (V2SF  "s")
 430                           (V4SF "s") (V2DF  "d")
 431                           (SF   "s") (DF  "d")
 432                           (QI "b")   (HI "h")
 433                           (SI "s")   (DI "d")])
 434
 435 ;; Mode-to-bitwise operation type mapping.
 436 (define_mode_attr Vbtype [(V8QI "8b")  (V16QI "16b")
 437                           (V4HI "8b") (V8HI  "16b")
 438                           (V2SI "8b") (V4SI  "16b")
 439                           (V2DI "16b") (V4HF "8b")
 440                           (V8HF "16b") (V2SF  "8b")
 441                           (V4SF "16b") (V2DF  "16b")
 442                           (DI   "8b")  (DF    "8b")
 443                           (SI   "8b")])
 444
 445 ;; Define element mode for each vector mode.
 446 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
 447                         (V4HI "HI") (V8HI "HI")
 448                         (V2SI "SI") (V4SI "SI")
 449                         (DI "DI")   (V2DI "DI")
 450                         (V4HF "HF") (V8HF "HF")
 451                         (V2SF "SF") (V4SF "SF")
 452                         (V2DF "DF") (DF "DF")
 453                         (SI   "SI") (HI   "HI")
 454                         (QI   "QI")])
 455
 456 ;; 64-bit container modes the inner or scalar source mode.
 457 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
 458                          (V4HI "V4HI") (V8HI "V4HI")
 459                          (V2SI "V2SI") (V4SI "V2SI")
 460                          (DI   "DI") (V2DI "DI")
 461                          (V2SF "V2SF") (V4SF "V2SF")
 462                          (V2DF "DF")])
 463
 464 ;; 128-bit container modes the inner or scalar source mode.
 465 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
 466                          (V4HI "V8HI") (V8HI "V8HI")
 467                          (V2SI "V4SI") (V4SI "V4SI")
 468                          (DI   "V2DI") (V2DI "V2DI")
 469                          (V4HF "V8HF") (V8HF "V8HF")
 470                          (V2SF "V2SF") (V4SF "V4SF")
 471                          (V2DF "V2DF") (SI   "V4SI")
 472                          (HI   "V8HI") (QI   "V16QI")])
 473
 474 ;; Half modes of all vector modes.
 475 (define_mode_attr VHALF [(V8QI "V4QI")  (V16QI "V8QI")
 476                          (V4HI "V2HI")  (V8HI  "V4HI")
 477                          (V2SI "SI")    (V4SI  "V2SI")
 478                          (V2DI "DI")    (V2SF  "SF")
 479                          (V4SF "V2SF")  (V4HF "V2HF")
 480                          (V8HF "V4HF")  (V2DF  "DF")])
 481
 482 ;; Double modes of vector modes.
 483 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
 484                         (V4HF "V8HF")
 485                         (V2SI "V4SI")  (V2SF "V4SF")
 486                         (SI   "V2SI")  (DI   "V2DI")
 487                         (DF   "V2DF")])
 488
 489 ;; Register suffix for double-length mode.
 490 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
 491
 492 ;; Double modes of vector modes (lower case).
 493 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
 494                         (V4HF "v8hf")
 495                         (V2SI "v4si")  (V2SF "v4sf")
 496                         (SI   "v2si")  (DI   "v2di")
 497                         (DF   "v2df")])
 498
 499 ;; Narrowed modes for VDN.
 500 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
 501                             (DI   "V2SI")])
 502
 503 ;; Narrowed double-modes for VQN (Used for XTN).
 504 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
 505                             (V2DI "V2SI")
 506                             (DI   "SI")   (SI   "HI")
 507                             (HI   "QI")])
 508
 509 ;; Narrowed quad-modes for VQN (Used for XTN2).
 510 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
 511                              (V2DI "V4SI")])
 512
 513 ;; Register suffix narrowed modes for VQN.
 514 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
 515                           (V2DI "2s")])
 516
 517 ;; Register suffix narrowed modes for VQN.
 518 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
 519                            (V2DI "4s")])
 520
 521 ;; Widened modes of vector modes.
 522 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
 523                          (V2SI "V2DI") (V16QI "V8HI")
 524                          (V8HI "V4SI") (V4SI "V2DI")
 525                          (HI "SI")     (SI "DI")
 526                          (V8HF "V4SF") (V4SF "V2DF")
 527                          (V4HF "V4SF") (V2SF "V2DF")]
 528 )
 529
 530 ;; Widened modes of vector modes, lowercase
 531 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
 532
 533 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
 534 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
 535                           (V2SI "2d") (V16QI "8h")
 536                           (V8HI "4s") (V4SI "2d")
 537                           (V8HF "4s") (V4SF "2d")])
 538
 539 ;; Widened mode register suffixes for VDW/VQW.
 540 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
 541                            (V2SI ".2d") (V16QI ".8h")
 542                            (V8HI ".4s") (V4SI ".2d")
 543                            (V4HF ".4s") (V2SF ".2d")
 544                            (SI   "")    (HI   "")])
 545
 546 ;; Lower part register suffixes for VQW/VQ_HSF.
 547 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
 548                              (V4SI "2s") (V8HF "4h")
 549                              (V4SF "2s")])
 550
 551 ;; Define corresponding core/FP element mode for each vector mode.
 552 (define_mode_attr vw   [(V8QI "w") (V16QI "w")
 553                         (V4HI "w") (V8HI "w")
 554                         (V2SI "w") (V4SI "w")
 555                         (DI   "x") (V2DI "x")
 556                         (V2SF "s") (V4SF "s")
 557                         (V2DF "d")])
 558
 559 ;; Corresponding core element mode for each vector mode.  This is a
 560 ;; variation on <vw> mapping FP modes to GP regs.
 561 (define_mode_attr vwcore  [(V8QI "w") (V16QI "w")
 562                            (V4HI "w") (V8HI "w")
 563                            (V2SI "w") (V4SI "w")
 564                            (DI   "x") (V2DI "x")
 565                            (V4HF "w") (V8HF "w")
 566                            (V2SF "w") (V4SF "w")
 567                            (V2DF "x")])
 568
 569 ;; Double vector types for ALLX.
 570 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
 571
 572 ;; Mode of result of comparison operations.
 573 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
 574                                 (V4HI "V4HI") (V8HI  "V8HI")
 575                                 (V2SI "V2SI") (V4SI  "V4SI")
 576                                 (DI   "DI")   (V2DI  "V2DI")
 577                                 (V4HF "V4HI") (V8HF  "V8HI")
 578                                 (V2SF "V2SI") (V4SF  "V4SI")
 579                                 (V2DF "V2DI") (DF    "DI")
 580                                 (SF   "SI")])
 581
 582 ;; Lower case mode of results of comparison operations.
 583 (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
 584                                 (V4HI "v4hi") (V8HI  "v8hi")
 585                                 (V2SI "v2si") (V4SI  "v4si")
 586                                 (DI   "di")   (V2DI  "v2di")
 587                                 (V4HF "v4hi") (V8HF  "v8hi")
 588                                 (V2SF "v2si") (V4SF  "v4si")
 589                                 (V2DF "v2di") (DF    "di")
 590                                 (SF   "si")])
 591
 592 ;; Lower case element modes (as used in shift immediate patterns).
 593 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
 594                            (V4HI "hi") (V8HI  "hi")
 595                            (V2SI "si") (V4SI  "si")
 596                            (DI   "di") (V2DI  "di")
 597                            (QI   "qi") (HI    "hi")
 598                            (SI   "si")])
 599
 600 ;; Vm for lane instructions is restricted to FP_LO_REGS.
 601 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
 602                        (V2SI "w") (V4SI "w") (SI "w")])
 603
 604 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
 605
 606 ;; This is both the number of Q-Registers needed to hold the corresponding
 607 ;; opaque large integer mode, and the number of elements touched by the
 608 ;; ld..._lane and st..._lane operations.
 609 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
 610
 611 (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI")
 612                         (V4HF "V16HF")
 613                         (V2SI "V8SI")  (V2SF "V8SF")
 614                         (DI   "V4DI")  (DF   "V4DF")])
 615
 616 (define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI")
 617                         (V4HF "V24HF")
 618                         (V2SI "V12SI")  (V2SF "V12SF")
 619                         (DI   "V6DI")  (DF   "V6DF")])
 620
 621 (define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI")
 622                         (V4HF "V32HF")
 623                         (V2SI "V16SI")  (V2SF "V16SF")
 624                         (DI   "V8DI")  (DF   "V8DF")])
 625
 626 ;; Mode for atomic operation suffixes
 627 (define_mode_attr atomic_sfx
 628   [(QI "b") (HI "h") (SI "") (DI "")])
 629
 630 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
 631 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
 632
 633 ;; for the inequal width integer to fp conversions
 634 (define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
 635 (define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
 636
 637 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
 638                                 (V4HI "V8HI") (V8HI  "V4HI")
 639                                 (V2SI "V4SI") (V4SI  "V2SI")
 640                                 (DI   "V2DI") (V2DI  "DI")
 641                                 (V2SF "V4SF") (V4SF  "V2SF")
 642                                 (V4HF "V8HF") (V8HF  "V4HF")
 643                                 (DF   "V2DF") (V2DF  "DF")])
 644
 645 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
 646                                     (V4HI "to_128") (V8HI  "to_64")
 647                                     (V2SI "to_128") (V4SI  "to_64")
 648                                     (DI   "to_128") (V2DI  "to_64")
 649                                     (V4HF "to_128") (V8HF  "to_64")
 650                                     (V2SF "to_128") (V4SF  "to_64")
 651                                     (DF   "to_128") (V2DF  "to_64")])
 652
 653 ;; For certain vector-by-element multiplication instructions we must
 654 ;; constrain the HI cases to use only V0-V15.  This is covered by
 655 ;; the 'x' constraint.  All other modes may use the 'w' constraint.
 656 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
 657                          (V4HI "x") (V8HI "x")
 658                          (V2SF "w") (V4SF "w")
 659                          (V2DF "w") (DF "w")])
 660
 661 ;; Defined to 'f' for types whose element type is a float type.
 662 (define_mode_attr f [(V8QI "")  (V16QI "")
 663                      (V4HI "")  (V8HI  "")
 664                      (V2SI "")  (V4SI  "")
 665                      (DI   "")  (V2DI  "")
 666                      (V2SF "f") (V4SF  "f")
 667                      (V2DF "f") (DF    "f")])
 668
 669 ;; Defined to '_fp' for types whose element type is a float type.
 670 (define_mode_attr fp [(V8QI "")  (V16QI "")
 671                       (V4HI "")  (V8HI  "")
 672                       (V2SI "")  (V4SI  "")
 673                       (DI   "")  (V2DI  "")
 674                       (V2SF "_fp") (V4SF  "_fp")
 675                       (V2DF "_fp") (DF    "_fp")
 676                       (SF "_fp")])
 677
 678 ;; Defined to '_q' for 128-bit types.
 679 (define_mode_attr q [(V8QI "") (V16QI "_q")
 680                      (V4HI "") (V8HI  "_q")
 681                      (V2SI "") (V4SI  "_q")
 682                      (DI   "") (V2DI  "_q")
 683                      (V4HF "") (V8HF "_q")
 684                      (V2SF "") (V4SF  "_q")
 685                                (V2DF  "_q")
 686                      (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
 687
 688 (define_mode_attr vp [(V8QI "v") (V16QI "v")
 689                       (V4HI "v") (V8HI  "v")
 690                       (V2SI "p") (V4SI  "v")
 691                       (V2DI  "p") (V2DF  "p")
 692                       (V2SF "p") (V4SF  "v")])
 693
 694 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
 695 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
 696
 697 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
 698
 699 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
 700 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
 701 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
 702
 703 ;; -------------------------------------------------------------------
 704 ;; Code Iterators
 705 ;; -------------------------------------------------------------------
 706
 707 ;; This code iterator allows the various shifts supported on the core
 708 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
 709
 710 ;; This code iterator allows the shifts supported in arithmetic instructions
 711 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
 712
 713 ;; Code iterator for logical operations
 714 (define_code_iterator LOGICAL [and ior xor])
 715
 716 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
 717 (define_code_iterator NLOGICAL [and ior])
 718
 719 ;; Code iterator for unary negate and bitwise complement.
 720 (define_code_iterator NEG_NOT [neg not])
 721
 722 ;; Code iterator for sign/zero extension
 723 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
 724
 725 ;; All division operations (signed/unsigned)
 726 (define_code_iterator ANY_DIV [div udiv])
 727
 728 ;; Code iterator for sign/zero extraction
 729 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
 730
 731 ;; Code iterator for equality comparisons
 732 (define_code_iterator EQL [eq ne])
 733
 734 ;; Code iterator for less-than and greater/equal-to
 735 (define_code_iterator LTGE [lt ge])
 736
 737 ;; Iterator for __sync_<op> operations that where the operation can be
 738 ;; represented directly RTL.  This is all of the sync operations bar
 739 ;; nand.
 740 (define_code_iterator atomic_op [plus minus ior xor and])
 741
 742 ;; Iterator for integer conversions
 743 (define_code_iterator FIXUORS [fix unsigned_fix])
 744
 745 ;; Iterator for float conversions
 746 (define_code_iterator FLOATUORS [float unsigned_float])
 747
 748 ;; Code iterator for variants of vector max and min.
 749 (define_code_iterator MAXMIN [smax smin umax umin])
 750
 751 (define_code_iterator FMAXMIN [smax smin])
 752
 753 ;; Code iterator for variants of vector max and min.
 754 (define_code_iterator ADDSUB [plus minus])
 755
 756 ;; Code iterator for variants of vector saturating binary ops.
 757 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
 758
 759 ;; Code iterator for variants of vector saturating unary ops.
 760 (define_code_iterator UNQOPS [ss_neg ss_abs])
 761
 762 ;; Code iterator for signed variants of vector saturating binary ops.
 763 (define_code_iterator SBINQOPS [ss_plus ss_minus])
 764
 765 ;; Comparison operators for <F>CM.
 766 (define_code_iterator COMPARISONS [lt le eq ge gt])
 767
 768 ;; Unsigned comparison operators.
 769 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
 770
 771 ;; Unsigned comparison operators.
 772 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
 773
 774 ;; -------------------------------------------------------------------
 775 ;; Code Attributes
 776 ;; -------------------------------------------------------------------
 777 ;; Map rtl objects to optab names
 778 (define_code_attr optab [(ashift "ashl")
 779                          (ashiftrt "ashr")
 780                          (lshiftrt "lshr")
 781                          (rotatert "rotr")
 782                          (sign_extend "extend")
 783                          (zero_extend "zero_extend")
 784                          (sign_extract "extv")
 785                          (zero_extract "extzv")
 786                          (fix "fix")
 787                          (unsigned_fix "fixuns")
 788                          (float "float")
 789                          (unsigned_float "floatuns")
 790                          (and "and")
 791                          (ior "ior")
 792                          (xor "xor")
 793                          (not "one_cmpl")
 794                          (neg "neg")
 795                          (plus "add")
 796                          (minus "sub")
 797                          (ss_plus "qadd")
 798                          (us_plus "qadd")
 799                          (ss_minus "qsub")
 800                          (us_minus "qsub")
 801                          (ss_neg "qneg")
 802                          (ss_abs "qabs")
 803                          (eq "eq")
 804                          (ne "ne")
 805                          (lt "lt")
 806                          (ge "ge")
 807                          (le "le")
 808                          (gt "gt")
 809                          (ltu "ltu")
 810                          (leu "leu")
 811                          (geu "geu")
 812                          (gtu "gtu")])
 813
 814 ;; For comparison operators we use the FCM* and CM* instructions.
 815 ;; As there are no CMLE or CMLT instructions which act on 3 vector
 816 ;; operands, we must use CMGE or CMGT and swap the order of the
 817 ;; source operands.
 818
 819 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
 820                            (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
 821 (define_code_attr cmp_1   [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
 822                            (ltu "2") (leu "2") (geu "1") (gtu "1")])
 823 (define_code_attr cmp_2   [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
 824                            (ltu "1") (leu "1") (geu "2") (gtu "2")])
 825
 826 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
 827                            (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")])
 828
 829 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
 830                                    (unsigned_fix "fixuns_trunc")])
 831
 832 ;; Optab prefix for sign/zero-extending operations
 833 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
 834                             (div "") (udiv "u")
 835                             (fix "") (unsigned_fix "u")
 836                             (float "s") (unsigned_float "u")
 837                             (ss_plus "s") (us_plus "u")
 838                             (ss_minus "s") (us_minus "u")])
 839
 840 ;; Similar for the instruction mnemonics
 841 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
 842                          (lshiftrt "lsr") (rotatert "ror")])
 843
 844 ;; Map shift operators onto underlying bit-field instructions
 845 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
 846                            (lshiftrt "ubfx") (rotatert "extr")])
 847
 848 ;; Logical operator instruction mnemonics
 849 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
 850
 851 ;; Operation names for negate and bitwise complement.
 852 (define_code_attr neg_not_op [(neg "neg") (not "not")])
 853
 854 ;; Similar, but when not(op)
 855 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
 856
 857 ;; Sign- or zero-extending load
 858 (define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
 859
 860 ;; Sign- or zero-extending data-op
 861 (define_code_attr su [(sign_extend "s") (zero_extend "u")
 862                       (sign_extract "s") (zero_extract "u")
 863                       (fix "s") (unsigned_fix "u")
 864                       (div "s") (udiv "u")
 865                       (smax "s") (umax "u")
 866                       (smin "s") (umin "u")])
 867
 868 ;; Emit conditional branch instructions.
 869 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
 870
 871 ;; Emit cbz/cbnz depending on comparison type.
 872 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
 873
 874 ;; Emit inverted cbz/cbnz depending on comparison type.
 875 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
 876
 877 ;; Emit tbz/tbnz depending on comparison type.
 878 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
 879
 880 ;; Emit inverted tbz/tbnz depending on comparison type.
 881 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
 882
 883 ;; Max/min attributes.
 884 (define_code_attr maxmin [(smax "max")
 885                           (smin "min")
 886                           (umax "max")
 887                           (umin "min")])
 888
 889 ;; MLA/MLS attributes.
 890 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
 891
 892 ;; Atomic operations
 893 (define_code_attr atomic_optab
 894   [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
 895
 896 (define_code_attr atomic_op_operand
 897   [(ior "aarch64_logical_operand")
 898    (xor "aarch64_logical_operand")
 899    (and "aarch64_logical_operand")
 900    (plus "aarch64_plus_operand")
 901    (minus "aarch64_plus_operand")])
 902
 903 ;; Constants acceptable for atomic operations.
 904 ;; This definition must appear in this file before the iterators it refers to.
 905 (define_code_attr const_atomic
 906  [(plus "IJ") (minus "IJ")
 907   (xor "<lconst_atomic>") (ior "<lconst_atomic>")
 908   (and "<lconst_atomic>")])
 909
 910 ;; Attribute to describe constants acceptable in atomic logical operations
 911 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
 912
 913 ;; -------------------------------------------------------------------
 914 ;; Int Iterators.
 915 ;; -------------------------------------------------------------------
 916 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
 917                               UNSPEC_SMAXV UNSPEC_SMINV])
 918
 919 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
 920                                UNSPEC_FMAXNMV UNSPEC_FMINNMV])
 921
 922 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
 923                               UNSPEC_SRHADD UNSPEC_URHADD
 924                               UNSPEC_SHSUB UNSPEC_UHSUB
 925                               UNSPEC_SRHSUB UNSPEC_URHSUB])
 926
 927
 928 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
 929                                UNSPEC_SUBHN UNSPEC_RSUBHN])
 930
 931 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
 932                                 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
 933
 934 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN])
 935
 936 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
 937
 938 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
 939
 940 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
 941
 942 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
 943                            UNSPEC_SRSHL UNSPEC_URSHL])
 944
 945 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
 946
 947 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
 948                             UNSPEC_SQRSHL UNSPEC_UQRSHL])
 949
 950 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
 951                              UNSPEC_SRSRA UNSPEC_URSRA])
 952
 953 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
 954                               UNSPEC_SSRI UNSPEC_USRI])
 955
 956
 957 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
 958
 959 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
 960
 961 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
 962                                UNSPEC_SQSHRN UNSPEC_UQSHRN
 963                                UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
 964
 965 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
 966                               UNSPEC_TRN1 UNSPEC_TRN2
 967                               UNSPEC_UZP1 UNSPEC_UZP2])
 968
 969 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
 970
 971 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
 972                              UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
 973                              UNSPEC_FRINTA])
 974
 975 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
 976                             UNSPEC_FRINTA UNSPEC_FRINTN])
 977
 978 (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
 979
 980 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
 981                           UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
 982                           UNSPEC_CRC32CW UNSPEC_CRC32CX])
 983
 984 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
 985 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
 986
 987 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
 988
 989 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
 990
 991 ;; Iterators for atomic operations.
 992
 993 (define_int_iterator ATOMIC_LDOP
 994  [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
 995   UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
 996
 997 (define_int_attr atomic_ldop
 998  [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
 999   (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1000
1001 ;; -------------------------------------------------------------------
1002 ;; Int Iterators Attributes.
1003 ;; -------------------------------------------------------------------
1004 (define_int_attr  maxmin_uns [(UNSPEC_UMAXV "umax")
1005                               (UNSPEC_UMINV "umin")
1006                               (UNSPEC_SMAXV "smax")
1007                               (UNSPEC_SMINV "smin")
1008                               (UNSPEC_FMAX  "smax_nan")
1009                               (UNSPEC_FMAXNMV "smax")
1010                               (UNSPEC_FMAXV "smax_nan")
1011                               (UNSPEC_FMIN "smin_nan")
1012                               (UNSPEC_FMINNMV "smin")
1013                               (UNSPEC_FMINV "smin_nan")])
1014
1015 (define_int_attr  maxmin_uns_op [(UNSPEC_UMAXV "umax")
1016                                  (UNSPEC_UMINV "umin")
1017                                  (UNSPEC_SMAXV "smax")
1018                                  (UNSPEC_SMINV "smin")
1019                                  (UNSPEC_FMAX "fmax")
1020                                  (UNSPEC_FMAXNMV "fmaxnm")
1021                                  (UNSPEC_FMAXV "fmax")
1022                                  (UNSPEC_FMIN "fmin")
1023                                  (UNSPEC_FMINNMV "fminnm")
1024                                  (UNSPEC_FMINV "fmin")])
1025
1026 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1027                       (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1028                       (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1029                       (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1030                       (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1031                       (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1032                       (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1033                       (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1034                       (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1035                       (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1036                       (UNSPEC_SSLI  "s") (UNSPEC_USLI  "u")
1037                       (UNSPEC_SSRI  "s") (UNSPEC_USRI  "u")
1038                       (UNSPEC_USRA  "u") (UNSPEC_SSRA  "s")
1039                       (UNSPEC_URSRA  "ur") (UNSPEC_SRSRA  "sr")
1040                       (UNSPEC_URSHR  "ur") (UNSPEC_SRSHR  "sr")
1041                       (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL   "s")
1042                       (UNSPEC_UQSHL  "u")
1043                       (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1044                       (UNSPEC_SQSHRN "s")  (UNSPEC_UQSHRN "u")
1045                       (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1046                       (UNSPEC_USHL  "u")   (UNSPEC_SSHL  "s")
1047                       (UNSPEC_USHLL  "u")  (UNSPEC_SSHLL "s")
1048                       (UNSPEC_URSHL  "ur") (UNSPEC_SRSHL  "sr")
1049                       (UNSPEC_UQRSHL  "u") (UNSPEC_SQRSHL  "s")
1050 ])
1051
1052 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1053                     (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1054                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1055                     (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1056                     (UNSPEC_SQSHL   "")  (UNSPEC_UQSHL  "")
1057                     (UNSPEC_SQRSHL   "r")(UNSPEC_UQRSHL  "r")
1058 ])
1059
1060 (define_int_attr lr [(UNSPEC_SSLI  "l") (UNSPEC_USLI  "l")
1061                      (UNSPEC_SSRI  "r") (UNSPEC_USRI  "r")])
1062
1063 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1064                     (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1065                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1066                     (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1067
1068 (define_int_attr addsub [(UNSPEC_SHADD "add")
1069                          (UNSPEC_UHADD "add")
1070                          (UNSPEC_SRHADD "add")
1071                          (UNSPEC_URHADD "add")
1072                          (UNSPEC_SHSUB "sub")
1073                          (UNSPEC_UHSUB "sub")
1074                          (UNSPEC_SRHSUB "sub")
1075                          (UNSPEC_URHSUB "sub")
1076                          (UNSPEC_ADDHN "add")
1077                          (UNSPEC_SUBHN "sub")
1078                          (UNSPEC_RADDHN "add")
1079                          (UNSPEC_RSUBHN "sub")
1080                          (UNSPEC_ADDHN2 "add")
1081                          (UNSPEC_SUBHN2 "sub")
1082                          (UNSPEC_RADDHN2 "add")
1083                          (UNSPEC_RSUBHN2 "sub")])
1084
1085 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1086                            (UNSPEC_SSRI "offset_")
1087                            (UNSPEC_USRI "offset_")])
1088
1089 ;; Standard pattern names for floating-point rounding instructions.
1090 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1091                                 (UNSPEC_FRINTP "ceil")
1092                                 (UNSPEC_FRINTM "floor")
1093                                 (UNSPEC_FRINTI "nearbyint")
1094                                 (UNSPEC_FRINTX "rint")
1095                                 (UNSPEC_FRINTA "round")
1096                                 (UNSPEC_FRINTN "frintn")])
1097
1098 ;; frint suffix for floating-point rounding instructions.
1099 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1100                                (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
1101                                (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1102                                (UNSPEC_FRINTN "n")])
1103
1104 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
1105                                (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1106                                (UNSPEC_FRINTN "frintn")])
1107
1108 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1109                             (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1110                             (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1111
1112 ; op code for REV instructions (size within which elements are reversed).
1113 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1114                          (UNSPEC_REV16 "16")])
1115
1116 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1117                             (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
1118                             (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
1119
1120 (define_int_attr frecp_suffix  [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
1121
1122 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1123                         (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1124                         (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1125                         (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1126
1127 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1128                         (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1129                         (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1130                         (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1131
1132 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1133 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
1134
1135 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1136                           (UNSPEC_SHA1M "m")])
1137
1138 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])