1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
55 /* Specify which cpu to schedule for. */
57 enum processor_type alpha_cpu
;
58 static const char * const alpha_cpu_name
[] =
63 /* Specify how accurate floating-point traps need to be. */
65 enum alpha_trap_precision alpha_tp
;
67 /* Specify the floating-point rounding mode. */
69 enum alpha_fp_rounding_mode alpha_fprm
;
71 /* Specify which things cause traps. */
73 enum alpha_fp_trap_mode alpha_fptm
;
75 /* Specify bit size of immediate TLS offsets. */
77 int alpha_tls_size
= 32;
79 /* Strings decoded into the above options. */
81 const char *alpha_cpu_string
; /* -mcpu= */
82 const char *alpha_tune_string
; /* -mtune= */
83 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
84 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
85 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
86 const char *alpha_mlat_string
; /* -mmemory-latency= */
87 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
89 /* Save information from a "cmpxx" operation until the branch or scc is
92 struct alpha_compare alpha_compare
;
94 /* Nonzero if inside of a function, because the Alpha asm can't
95 handle .files inside of functions. */
97 static int inside_function
= FALSE
;
99 /* The number of cycles of latency we should assume on memory reads. */
101 int alpha_memory_latency
= 3;
103 /* Whether the function needs the GP. */
105 static int alpha_function_needs_gp
;
107 /* The alias set for prologue/epilogue register save/restore. */
109 static GTY(()) int alpha_sr_alias_set
;
111 /* The assembler name of the current function. */
113 static const char *alpha_fnname
;
115 /* The next explicit relocation sequence number. */
116 extern GTY(()) int alpha_next_sequence_number
;
117 int alpha_next_sequence_number
= 1;
119 /* The literal and gpdisp sequence numbers for this insn, as printed
120 by %# and %* respectively. */
121 extern GTY(()) int alpha_this_literal_sequence_number
;
122 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
123 int alpha_this_literal_sequence_number
;
124 int alpha_this_gpdisp_sequence_number
;
126 /* Costs of various operations on the different architectures. */
128 struct alpha_rtx_cost_data
130 unsigned char fp_add
;
131 unsigned char fp_mult
;
132 unsigned char fp_div_sf
;
133 unsigned char fp_div_df
;
134 unsigned char int_mult_si
;
135 unsigned char int_mult_di
;
136 unsigned char int_shift
;
137 unsigned char int_cmov
;
140 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
143 COSTS_N_INSNS (6), /* fp_add */
144 COSTS_N_INSNS (6), /* fp_mult */
145 COSTS_N_INSNS (34), /* fp_div_sf */
146 COSTS_N_INSNS (63), /* fp_div_df */
147 COSTS_N_INSNS (23), /* int_mult_si */
148 COSTS_N_INSNS (23), /* int_mult_di */
149 COSTS_N_INSNS (2), /* int_shift */
150 COSTS_N_INSNS (2), /* int_cmov */
153 COSTS_N_INSNS (4), /* fp_add */
154 COSTS_N_INSNS (4), /* fp_mult */
155 COSTS_N_INSNS (15), /* fp_div_sf */
156 COSTS_N_INSNS (22), /* fp_div_df */
157 COSTS_N_INSNS (8), /* int_mult_si */
158 COSTS_N_INSNS (12), /* int_mult_di */
159 COSTS_N_INSNS (1) + 1, /* int_shift */
160 COSTS_N_INSNS (1), /* int_cmov */
163 COSTS_N_INSNS (4), /* fp_add */
164 COSTS_N_INSNS (4), /* fp_mult */
165 COSTS_N_INSNS (12), /* fp_div_sf */
166 COSTS_N_INSNS (15), /* fp_div_df */
167 COSTS_N_INSNS (7), /* int_mult_si */
168 COSTS_N_INSNS (7), /* int_mult_di */
169 COSTS_N_INSNS (1), /* int_shift */
170 COSTS_N_INSNS (2), /* int_cmov */
174 /* Declarations of static functions. */
175 static bool alpha_function_ok_for_sibcall
176 PARAMS ((tree
, tree
));
177 static int tls_symbolic_operand_1
178 PARAMS ((rtx
, enum machine_mode
, int, int));
179 static enum tls_model tls_symbolic_operand_type
181 static bool decl_has_samegp
183 static bool alpha_in_small_data_p
185 static rtx get_tls_get_addr
187 static int some_small_symbolic_operand_1
188 PARAMS ((rtx
*, void *));
189 static int split_small_symbolic_operand_1
190 PARAMS ((rtx
*, void *));
191 static bool alpha_cannot_copy_insn_p
193 static bool alpha_rtx_costs
194 PARAMS ((rtx
, int, int, int *));
195 static void alpha_set_memflags_1
196 PARAMS ((rtx
, int, int, int));
197 static rtx alpha_emit_set_const_1
198 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
199 static void alpha_expand_unaligned_load_words
200 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
201 static void alpha_expand_unaligned_store_words
202 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
203 static void alpha_init_builtins
205 static rtx alpha_expand_builtin
206 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
207 static void alpha_sa_mask
208 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
209 static int find_lo_sum_using_gp
210 PARAMS ((rtx
*, void *));
211 static int alpha_does_function_need_gp
213 static int alpha_ra_ever_killed
215 static const char *get_trap_mode_suffix
217 static const char *get_round_mode_suffix
219 static const char *get_some_local_dynamic_name
221 static int get_some_local_dynamic_name_1
222 PARAMS ((rtx
*, void *));
223 static rtx set_frame_related_p
225 static const char *alpha_lookup_xfloating_lib_func
226 PARAMS ((enum rtx_code
));
227 static int alpha_compute_xfloating_mode_arg
228 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
229 static void alpha_emit_xfloating_libcall
230 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
231 static rtx alpha_emit_xfloating_compare
232 PARAMS ((enum rtx_code
, rtx
, rtx
));
233 static void alpha_output_function_end_prologue
235 static int alpha_adjust_cost
236 PARAMS ((rtx
, rtx
, rtx
, int));
237 static int alpha_issue_rate
239 static int alpha_use_dfa_pipeline_interface
241 static int alpha_multipass_dfa_lookahead
243 static void alpha_reorg
246 #ifdef OBJECT_FORMAT_ELF
247 static void alpha_elf_select_rtx_section
248 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
251 #if TARGET_ABI_OPEN_VMS
252 static bool alpha_linkage_symbol_p
253 PARAMS ((const char *symname
));
254 static int alpha_write_one_linkage
255 PARAMS ((splay_tree_node
, void *));
256 static void alpha_write_linkage
257 PARAMS ((FILE *, const char *, tree
));
261 static void alpha_output_mi_thunk_osf
262 PARAMS ((FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
));
265 static struct machine_function
* alpha_init_machine_status
268 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
269 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
270 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
271 static int unicosmk_need_dex
PARAMS ((rtx
));
272 static void unicosmk_file_end
PARAMS ((void));
274 /* Get the number of args of a function in one of two ways. */
275 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
276 #define NUM_ARGS current_function_args_info.num_args
278 #define NUM_ARGS current_function_args_info
284 /* Initialize the GCC target structure. */
285 #if TARGET_ABI_OPEN_VMS
286 const struct attribute_spec vms_attribute_table
[];
287 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
288 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
289 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
290 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
291 # undef TARGET_ATTRIBUTE_TABLE
292 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
293 # undef TARGET_SECTION_TYPE_FLAGS
294 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
297 #undef TARGET_IN_SMALL_DATA_P
298 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
300 #if TARGET_ABI_UNICOSMK
301 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
302 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
303 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
305 static void unicosmk_unique_section
PARAMS ((tree
, int));
306 # undef TARGET_INSERT_ATTRIBUTES
307 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
308 # undef TARGET_SECTION_TYPE_FLAGS
309 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
310 # undef TARGET_ASM_UNIQUE_SECTION
311 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
312 # undef TARGET_ASM_GLOBALIZE_LABEL
313 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
316 #undef TARGET_ASM_ALIGNED_HI_OP
317 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
318 #undef TARGET_ASM_ALIGNED_DI_OP
319 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
321 /* Default unaligned ops are provided for ELF systems. To get unaligned
322 data for non-ELF systems, we have to turn off auto alignment. */
323 #ifndef OBJECT_FORMAT_ELF
324 #undef TARGET_ASM_UNALIGNED_HI_OP
325 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
326 #undef TARGET_ASM_UNALIGNED_SI_OP
327 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
328 #undef TARGET_ASM_UNALIGNED_DI_OP
329 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
332 #ifdef OBJECT_FORMAT_ELF
333 #undef TARGET_ASM_SELECT_RTX_SECTION
334 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
337 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
338 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
340 #undef TARGET_SCHED_ADJUST_COST
341 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
342 #undef TARGET_SCHED_ISSUE_RATE
343 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
344 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
345 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
346 alpha_use_dfa_pipeline_interface
347 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
348 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
349 alpha_multipass_dfa_lookahead
351 #undef TARGET_HAVE_TLS
352 #define TARGET_HAVE_TLS HAVE_AS_TLS
354 #undef TARGET_INIT_BUILTINS
355 #define TARGET_INIT_BUILTINS alpha_init_builtins
356 #undef TARGET_EXPAND_BUILTIN
357 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
359 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
360 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
361 #undef TARGET_CANNOT_COPY_INSN_P
362 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
365 #undef TARGET_ASM_OUTPUT_MI_THUNK
366 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
367 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
368 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
371 #undef TARGET_RTX_COSTS
372 #define TARGET_RTX_COSTS alpha_rtx_costs
373 #undef TARGET_ADDRESS_COST
374 #define TARGET_ADDRESS_COST hook_int_rtx_0
376 #undef TARGET_MACHINE_DEPENDENT_REORG
377 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
379 struct gcc_target targetm
= TARGET_INITIALIZER
;
381 /* Parse target option strings. */
387 static const struct cpu_table
{
388 const char *const name
;
389 const enum processor_type processor
;
392 #define EV5_MASK (MASK_CPU_EV5)
393 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
394 { "ev4", PROCESSOR_EV4
, 0 },
395 { "ev45", PROCESSOR_EV4
, 0 },
396 { "21064", PROCESSOR_EV4
, 0 },
397 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
398 { "21164", PROCESSOR_EV5
, EV5_MASK
},
399 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
400 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
401 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
402 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
403 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
404 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
405 { "21264", PROCESSOR_EV6
, EV6_MASK
},
406 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
407 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
411 /* Unicos/Mk doesn't have shared libraries. */
412 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
414 warning ("-f%s ignored for Unicos/Mk (not supported)",
415 (flag_pic
> 1) ? "PIC" : "pic");
419 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
420 floating-point instructions. Make that the default for this target. */
421 if (TARGET_ABI_UNICOSMK
)
422 alpha_fprm
= ALPHA_FPRM_DYN
;
424 alpha_fprm
= ALPHA_FPRM_NORM
;
426 alpha_tp
= ALPHA_TP_PROG
;
427 alpha_fptm
= ALPHA_FPTM_N
;
429 /* We cannot use su and sui qualifiers for conversion instructions on
430 Unicos/Mk. I'm not sure if this is due to assembler or hardware
431 limitations. Right now, we issue a warning if -mieee is specified
432 and then ignore it; eventually, we should either get it right or
433 disable the option altogether. */
437 if (TARGET_ABI_UNICOSMK
)
438 warning ("-mieee not supported on Unicos/Mk");
441 alpha_tp
= ALPHA_TP_INSN
;
442 alpha_fptm
= ALPHA_FPTM_SU
;
446 if (TARGET_IEEE_WITH_INEXACT
)
448 if (TARGET_ABI_UNICOSMK
)
449 warning ("-mieee-with-inexact not supported on Unicos/Mk");
452 alpha_tp
= ALPHA_TP_INSN
;
453 alpha_fptm
= ALPHA_FPTM_SUI
;
459 if (! strcmp (alpha_tp_string
, "p"))
460 alpha_tp
= ALPHA_TP_PROG
;
461 else if (! strcmp (alpha_tp_string
, "f"))
462 alpha_tp
= ALPHA_TP_FUNC
;
463 else if (! strcmp (alpha_tp_string
, "i"))
464 alpha_tp
= ALPHA_TP_INSN
;
466 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
469 if (alpha_fprm_string
)
471 if (! strcmp (alpha_fprm_string
, "n"))
472 alpha_fprm
= ALPHA_FPRM_NORM
;
473 else if (! strcmp (alpha_fprm_string
, "m"))
474 alpha_fprm
= ALPHA_FPRM_MINF
;
475 else if (! strcmp (alpha_fprm_string
, "c"))
476 alpha_fprm
= ALPHA_FPRM_CHOP
;
477 else if (! strcmp (alpha_fprm_string
,"d"))
478 alpha_fprm
= ALPHA_FPRM_DYN
;
480 error ("bad value `%s' for -mfp-rounding-mode switch",
484 if (alpha_fptm_string
)
486 if (strcmp (alpha_fptm_string
, "n") == 0)
487 alpha_fptm
= ALPHA_FPTM_N
;
488 else if (strcmp (alpha_fptm_string
, "u") == 0)
489 alpha_fptm
= ALPHA_FPTM_U
;
490 else if (strcmp (alpha_fptm_string
, "su") == 0)
491 alpha_fptm
= ALPHA_FPTM_SU
;
492 else if (strcmp (alpha_fptm_string
, "sui") == 0)
493 alpha_fptm
= ALPHA_FPTM_SUI
;
495 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
498 if (alpha_tls_size_string
)
500 if (strcmp (alpha_tls_size_string
, "16") == 0)
502 else if (strcmp (alpha_tls_size_string
, "32") == 0)
504 else if (strcmp (alpha_tls_size_string
, "64") == 0)
507 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
511 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
512 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
514 if (alpha_cpu_string
)
516 for (i
= 0; cpu_table
[i
].name
; i
++)
517 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
519 alpha_cpu
= cpu_table
[i
].processor
;
520 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
521 | MASK_CPU_EV5
| MASK_CPU_EV6
);
522 target_flags
|= cpu_table
[i
].flags
;
525 if (! cpu_table
[i
].name
)
526 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
529 if (alpha_tune_string
)
531 for (i
= 0; cpu_table
[i
].name
; i
++)
532 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
534 alpha_cpu
= cpu_table
[i
].processor
;
537 if (! cpu_table
[i
].name
)
538 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
541 /* Do some sanity checks on the above options. */
543 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
545 warning ("trap mode not supported on Unicos/Mk");
546 alpha_fptm
= ALPHA_FPTM_N
;
549 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
550 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
552 warning ("fp software completion requires -mtrap-precision=i");
553 alpha_tp
= ALPHA_TP_INSN
;
558 /* Except for EV6 pass 1 (not released), we always have precise
559 arithmetic traps. Which means we can do software completion
560 without minding trap shadows. */
561 alpha_tp
= ALPHA_TP_PROG
;
564 if (TARGET_FLOAT_VAX
)
566 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
568 warning ("rounding mode not supported for VAX floats");
569 alpha_fprm
= ALPHA_FPRM_NORM
;
571 if (alpha_fptm
== ALPHA_FPTM_SUI
)
573 warning ("trap mode not supported for VAX floats");
574 alpha_fptm
= ALPHA_FPTM_SU
;
582 if (!alpha_mlat_string
)
583 alpha_mlat_string
= "L1";
585 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
586 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
588 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
589 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
590 && alpha_mlat_string
[2] == '\0')
592 static int const cache_latency
[][4] =
594 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
595 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
596 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
599 lat
= alpha_mlat_string
[1] - '0';
600 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
602 warning ("L%d cache latency unknown for %s",
603 lat
, alpha_cpu_name
[alpha_cpu
]);
607 lat
= cache_latency
[alpha_cpu
][lat
-1];
609 else if (! strcmp (alpha_mlat_string
, "main"))
611 /* Most current memories have about 370ns latency. This is
612 a reasonable guess for a fast cpu. */
617 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
621 alpha_memory_latency
= lat
;
624 /* Default the definition of "small data" to 8 bytes. */
628 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
630 target_flags
|= MASK_SMALL_DATA
;
631 else if (flag_pic
== 2)
632 target_flags
&= ~MASK_SMALL_DATA
;
634 /* Align labels and loops for optimal branching. */
635 /* ??? Kludge these by not doing anything if we don't optimize and also if
636 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
637 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
639 if (align_loops
<= 0)
641 if (align_jumps
<= 0)
644 if (align_functions
<= 0)
645 align_functions
= 16;
647 /* Acquire a unique set number for our register saves and restores. */
648 alpha_sr_alias_set
= new_alias_set ();
650 /* Register variables and functions with the garbage collector. */
652 /* Set up function hooks. */
653 init_machine_status
= alpha_init_machine_status
;
655 /* Tell the compiler when we're using VAX floating point. */
656 if (TARGET_FLOAT_VAX
)
658 real_format_for_mode
[SFmode
- QFmode
] = &vax_f_format
;
659 real_format_for_mode
[DFmode
- QFmode
] = &vax_g_format
;
660 real_format_for_mode
[TFmode
- QFmode
] = NULL
;
664 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
672 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
674 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
680 /* Returns 1 if OP is either the constant zero or a register. If a
681 register, it must be in the proper mode unless MODE is VOIDmode. */
684 reg_or_0_operand (op
, mode
)
686 enum machine_mode mode
;
688 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
691 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
695 reg_or_6bit_operand (op
, mode
)
697 enum machine_mode mode
;
699 return ((GET_CODE (op
) == CONST_INT
700 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
701 || register_operand (op
, mode
));
705 /* Return 1 if OP is an 8-bit constant or any register. */
708 reg_or_8bit_operand (op
, mode
)
710 enum machine_mode mode
;
712 return ((GET_CODE (op
) == CONST_INT
713 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
714 || register_operand (op
, mode
));
717 /* Return 1 if OP is a constant or any register. */
720 reg_or_const_int_operand (op
, mode
)
722 enum machine_mode mode
;
724 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
727 /* Return 1 if OP is an 8-bit constant. */
730 cint8_operand (op
, mode
)
732 enum machine_mode mode ATTRIBUTE_UNUSED
;
734 return ((GET_CODE (op
) == CONST_INT
735 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
738 /* Return 1 if the operand is a valid second operand to an add insn. */
741 add_operand (op
, mode
)
743 enum machine_mode mode
;
745 if (GET_CODE (op
) == CONST_INT
)
746 /* Constraints I, J, O and P are covered by K. */
747 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
748 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
750 return register_operand (op
, mode
);
753 /* Return 1 if the operand is a valid second operand to a sign-extending
757 sext_add_operand (op
, mode
)
759 enum machine_mode mode
;
761 if (GET_CODE (op
) == CONST_INT
)
762 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
763 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
765 return reg_not_elim_operand (op
, mode
);
768 /* Return 1 if OP is the constant 4 or 8. */
771 const48_operand (op
, mode
)
773 enum machine_mode mode ATTRIBUTE_UNUSED
;
775 return (GET_CODE (op
) == CONST_INT
776 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
779 /* Return 1 if OP is a valid first operand to an AND insn. */
782 and_operand (op
, mode
)
784 enum machine_mode mode
;
786 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
787 return (zap_mask (CONST_DOUBLE_LOW (op
))
788 && zap_mask (CONST_DOUBLE_HIGH (op
)));
790 if (GET_CODE (op
) == CONST_INT
)
791 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
792 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
793 || zap_mask (INTVAL (op
)));
795 return register_operand (op
, mode
);
798 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
801 or_operand (op
, mode
)
803 enum machine_mode mode
;
805 if (GET_CODE (op
) == CONST_INT
)
806 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
807 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
809 return register_operand (op
, mode
);
812 /* Return 1 if OP is a constant that is the width, in bits, of an integral
813 mode smaller than DImode. */
816 mode_width_operand (op
, mode
)
818 enum machine_mode mode ATTRIBUTE_UNUSED
;
820 return (GET_CODE (op
) == CONST_INT
821 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
822 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
825 /* Return 1 if OP is a constant that is the width of an integral machine mode
826 smaller than an integer. */
829 mode_mask_operand (op
, mode
)
831 enum machine_mode mode ATTRIBUTE_UNUSED
;
833 if (GET_CODE (op
) == CONST_INT
)
835 HOST_WIDE_INT value
= INTVAL (op
);
841 if (value
== 0xffffffff)
846 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
848 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
855 /* Return 1 if OP is a multiple of 8 less than 64. */
858 mul8_operand (op
, mode
)
860 enum machine_mode mode ATTRIBUTE_UNUSED
;
862 return (GET_CODE (op
) == CONST_INT
863 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
864 && (INTVAL (op
) & 7) == 0);
867 /* Return 1 if OP is the zero constant for MODE. */
870 const0_operand (op
, mode
)
872 enum machine_mode mode
;
874 return op
== CONST0_RTX (mode
);
877 /* Return 1 if OP is a hard floating-point register. */
880 hard_fp_register_operand (op
, mode
)
882 enum machine_mode mode
;
884 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
887 if (GET_CODE (op
) == SUBREG
)
888 op
= SUBREG_REG (op
);
889 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
892 /* Return 1 if OP is a hard general register. */
895 hard_int_register_operand (op
, mode
)
897 enum machine_mode mode
;
899 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
902 if (GET_CODE (op
) == SUBREG
)
903 op
= SUBREG_REG (op
);
904 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
907 /* Return 1 if OP is a register or a constant integer. */
911 reg_or_cint_operand (op
, mode
)
913 enum machine_mode mode
;
915 return (GET_CODE (op
) == CONST_INT
916 || register_operand (op
, mode
));
919 /* Return 1 if OP is something that can be reloaded into a register;
920 if it is a MEM, it need not be valid. */
923 some_operand (op
, mode
)
925 enum machine_mode mode
;
927 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
930 switch (GET_CODE (op
))
944 return some_operand (SUBREG_REG (op
), VOIDmode
);
953 /* Likewise, but don't accept constants. */
956 some_ni_operand (op
, mode
)
958 enum machine_mode mode
;
960 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
963 if (GET_CODE (op
) == SUBREG
)
964 op
= SUBREG_REG (op
);
966 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
969 /* Return 1 if OP is a valid operand for the source of a move insn. */
972 input_operand (op
, mode
)
974 enum machine_mode mode
;
976 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
979 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
982 switch (GET_CODE (op
))
987 if (TARGET_EXPLICIT_RELOCS
)
989 /* We don't split symbolic operands into something unintelligable
990 until after reload, but we do not wish non-small, non-global
991 symbolic operands to be reconstructed from their high/lo_sum
993 return (small_symbolic_operand (op
, mode
)
994 || global_symbolic_operand (op
, mode
)
995 || gotdtp_symbolic_operand (op
, mode
)
996 || gottp_symbolic_operand (op
, mode
));
999 /* This handles both the Windows/NT and OSF cases. */
1000 return mode
== ptr_mode
|| mode
== DImode
;
1003 return (TARGET_EXPLICIT_RELOCS
1004 && local_symbolic_operand (XEXP (op
, 0), mode
));
1011 if (register_operand (op
, mode
))
1013 /* ... fall through ... */
1015 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
1016 && general_operand (op
, mode
));
1020 return op
== CONST0_RTX (mode
);
1023 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
1025 case CONSTANT_P_RTX
:
1035 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
1036 file, and in the same section as the current function. */
1039 samegp_function_operand (op
, mode
)
1041 enum machine_mode mode ATTRIBUTE_UNUSED
;
1043 if (GET_CODE (op
) != SYMBOL_REF
)
1046 /* Easy test for recursion. */
1047 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
1050 /* Functions that are not local can be overridden, and thus may
1051 not share the same gp. */
1052 if (! SYMBOL_REF_LOCAL_P (op
))
1055 /* If -msmall-data is in effect, assume that there is only one GP
1056 for the module, and so any local symbol has this property. We
1057 need explicit relocations to be able to enforce this for symbols
1058 not defined in this unit of translation, however. */
1059 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1062 /* Functions that are not external are defined in this UoT,
1063 and thus must share the same gp. */
1064 return ! SYMBOL_REF_EXTERNAL_P (op
);
1067 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
1070 direct_call_operand (op
, mode
)
1072 enum machine_mode mode
;
1074 tree op_decl
, cfun_sec
, op_sec
;
1076 /* Must share the same GP. */
1077 if (!samegp_function_operand (op
, mode
))
1080 /* If profiling is implemented via linker tricks, we can't jump
1081 to the nogp alternate entry point. Note that current_function_profile
1082 would not be correct, since that doesn't indicate if the target
1083 function uses profiling. */
1084 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
1085 but is approximately correct for the OSF ABIs. Don't know
1086 what to do for VMS, NT, or UMK. */
1087 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
1090 /* Must be a function. In some cases folks create thunks in static
1091 data structures and then make calls to them. If we allow the
1092 direct call, we'll get an error from the linker about !samegp reloc
1093 against a symbol without a .prologue directive. */
1094 if (!SYMBOL_REF_FUNCTION_P (op
))
1097 /* Must be "near" so that the branch is assumed to reach. With
1098 -msmall-text, this is assumed true of all local symbols. Since
1099 we've already checked samegp, locality is already assured. */
1100 if (TARGET_SMALL_TEXT
)
1103 /* Otherwise, a decl is "near" if it is defined in the same section. */
1104 if (flag_function_sections
)
1107 op_decl
= SYMBOL_REF_DECL (op
);
1108 if (DECL_ONE_ONLY (current_function_decl
)
1109 || (op_decl
&& DECL_ONE_ONLY (op_decl
)))
1112 cfun_sec
= DECL_SECTION_NAME (current_function_decl
);
1113 op_sec
= op_decl
? DECL_SECTION_NAME (op_decl
) : NULL
;
1114 return ((!cfun_sec
&& !op_sec
)
1115 || (cfun_sec
&& op_sec
1116 && strcmp (TREE_STRING_POINTER (cfun_sec
),
1117 TREE_STRING_POINTER (op_sec
)) == 0));
1120 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
1121 a (non-tls) variable known to be defined in this file. */
1124 local_symbolic_operand (op
, mode
)
1126 enum machine_mode mode
;
1128 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1131 if (GET_CODE (op
) == LABEL_REF
)
1134 if (GET_CODE (op
) == CONST
1135 && GET_CODE (XEXP (op
, 0)) == PLUS
1136 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1137 op
= XEXP (XEXP (op
, 0), 0);
1139 if (GET_CODE (op
) != SYMBOL_REF
)
1142 return SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
1145 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1146 known to be defined in this file in the small data area. */
1149 small_symbolic_operand (op
, mode
)
1151 enum machine_mode mode ATTRIBUTE_UNUSED
;
1153 if (! TARGET_SMALL_DATA
)
1156 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1159 if (GET_CODE (op
) == CONST
1160 && GET_CODE (XEXP (op
, 0)) == PLUS
1161 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1162 op
= XEXP (XEXP (op
, 0), 0);
1164 if (GET_CODE (op
) != SYMBOL_REF
)
1167 /* ??? There's no encode_section_info equivalent for the rtl
1168 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
1169 if (CONSTANT_POOL_ADDRESS_P (op
))
1170 return GET_MODE_SIZE (get_pool_mode (op
)) <= g_switch_value
;
1172 return (SYMBOL_REF_LOCAL_P (op
)
1173 && SYMBOL_REF_SMALL_P (op
)
1174 && SYMBOL_REF_TLS_MODEL (op
) == 0);
1177 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1178 not known (or known not) to be defined in this file. */
1181 global_symbolic_operand (op
, mode
)
1183 enum machine_mode mode
;
1185 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1188 if (GET_CODE (op
) == CONST
1189 && GET_CODE (XEXP (op
, 0)) == PLUS
1190 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1191 op
= XEXP (XEXP (op
, 0), 0);
1193 if (GET_CODE (op
) != SYMBOL_REF
)
1196 return !SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
1199 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1202 call_operand (op
, mode
)
1204 enum machine_mode mode
;
1209 if (GET_CODE (op
) == REG
)
1213 /* Disallow virtual registers to cope with pathalogical test cases
1214 such as compile/930117-1.c in which the virtual reg decomposes
1215 to the frame pointer. Which is a hard reg that is not $27. */
1216 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1221 if (TARGET_ABI_UNICOSMK
)
1223 if (GET_CODE (op
) == SYMBOL_REF
)
1229 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1230 possibly with an offset. */
1233 symbolic_operand (op
, mode
)
1235 enum machine_mode mode
;
1237 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1239 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1241 if (GET_CODE (op
) == CONST
1242 && GET_CODE (XEXP (op
,0)) == PLUS
1243 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1244 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1249 /* Return true if OP is valid for a particular TLS relocation. */
1252 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1254 enum machine_mode mode
;
1257 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1260 if (GET_CODE (op
) != CONST
)
1264 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1266 op
= XVECEXP (op
, 0, 0);
1268 if (GET_CODE (op
) != SYMBOL_REF
)
1271 if (SYMBOL_REF_LOCAL_P (op
))
1273 if (alpha_tls_size
> size
)
1282 switch (SYMBOL_REF_TLS_MODEL (op
))
1284 case TLS_MODEL_LOCAL_DYNAMIC
:
1285 return unspec
== UNSPEC_DTPREL
;
1286 case TLS_MODEL_INITIAL_EXEC
:
1287 return unspec
== UNSPEC_TPREL
&& size
== 64;
1288 case TLS_MODEL_LOCAL_EXEC
:
1289 return unspec
== UNSPEC_TPREL
;
1295 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1298 dtp16_symbolic_operand (op
, mode
)
1300 enum machine_mode mode
;
1302 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1305 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1308 dtp32_symbolic_operand (op
, mode
)
1310 enum machine_mode mode
;
1312 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1315 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1318 gotdtp_symbolic_operand (op
, mode
)
1320 enum machine_mode mode
;
1322 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1325 /* Return true if OP is valid for 16-bit TP relative relocations. */
1328 tp16_symbolic_operand (op
, mode
)
1330 enum machine_mode mode
;
1332 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1335 /* Return true if OP is valid for 32-bit TP relative relocations. */
1338 tp32_symbolic_operand (op
, mode
)
1340 enum machine_mode mode
;
1342 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1345 /* Return true if OP is valid for 64-bit TP relative relocations. */
1348 gottp_symbolic_operand (op
, mode
)
1350 enum machine_mode mode
;
1352 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1355 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1356 comparisons are valid in which insn. */
1359 alpha_comparison_operator (op
, mode
)
1361 enum machine_mode mode
;
1363 enum rtx_code code
= GET_CODE (op
);
1365 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1368 return (code
== EQ
|| code
== LE
|| code
== LT
1369 || code
== LEU
|| code
== LTU
);
1372 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1373 Here we know which comparisons are valid in which insn. */
1376 alpha_zero_comparison_operator (op
, mode
)
1378 enum machine_mode mode
;
1380 enum rtx_code code
= GET_CODE (op
);
1382 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1385 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1386 || code
== LEU
|| code
== LTU
);
1389 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1392 alpha_swapped_comparison_operator (op
, mode
)
1394 enum machine_mode mode
;
1396 enum rtx_code code
= GET_CODE (op
);
1398 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1399 || GET_RTX_CLASS (code
) != '<')
1402 code
= swap_condition (code
);
1403 return (code
== EQ
|| code
== LE
|| code
== LT
1404 || code
== LEU
|| code
== LTU
);
1407 /* Return 1 if OP is a signed comparison operation. */
1410 signed_comparison_operator (op
, mode
)
1412 enum machine_mode mode ATTRIBUTE_UNUSED
;
1414 enum rtx_code code
= GET_CODE (op
);
1416 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1419 return (code
== EQ
|| code
== NE
1420 || code
== LE
|| code
== LT
1421 || code
== GE
|| code
== GT
);
1424 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1425 Here we know which comparisons are valid in which insn. */
1428 alpha_fp_comparison_operator (op
, mode
)
1430 enum machine_mode mode
;
1432 enum rtx_code code
= GET_CODE (op
);
1434 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1437 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1440 /* Return 1 if this is a divide or modulus operator. */
1443 divmod_operator (op
, mode
)
1445 enum machine_mode mode ATTRIBUTE_UNUSED
;
1447 switch (GET_CODE (op
))
1449 case DIV
: case MOD
: case UDIV
: case UMOD
:
1459 /* Return 1 if this memory address is a known aligned register plus
1460 a constant. It must be a valid address. This means that we can do
1461 this as an aligned reference plus some offset.
1463 Take into account what reload will do. */
1466 aligned_memory_operand (op
, mode
)
1468 enum machine_mode mode
;
1472 if (reload_in_progress
)
1475 if (GET_CODE (tmp
) == SUBREG
)
1476 tmp
= SUBREG_REG (tmp
);
1477 if (GET_CODE (tmp
) == REG
1478 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1480 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1486 if (GET_CODE (op
) != MEM
1487 || GET_MODE (op
) != mode
)
1491 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1492 sorts of constructs. Dig for the real base register. */
1493 if (reload_in_progress
1494 && GET_CODE (op
) == PLUS
1495 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1496 base
= XEXP (XEXP (op
, 0), 0);
1499 if (! memory_address_p (mode
, op
))
1501 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1504 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1507 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1510 unaligned_memory_operand (op
, mode
)
1512 enum machine_mode mode
;
1516 if (reload_in_progress
)
1519 if (GET_CODE (tmp
) == SUBREG
)
1520 tmp
= SUBREG_REG (tmp
);
1521 if (GET_CODE (tmp
) == REG
1522 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1524 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1530 if (GET_CODE (op
) != MEM
1531 || GET_MODE (op
) != mode
)
1535 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1536 sorts of constructs. Dig for the real base register. */
1537 if (reload_in_progress
1538 && GET_CODE (op
) == PLUS
1539 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1540 base
= XEXP (XEXP (op
, 0), 0);
1543 if (! memory_address_p (mode
, op
))
1545 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1548 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1551 /* Return 1 if OP is either a register or an unaligned memory location. */
1554 reg_or_unaligned_mem_operand (op
, mode
)
1556 enum machine_mode mode
;
1558 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1561 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1564 any_memory_operand (op
, mode
)
1566 enum machine_mode mode ATTRIBUTE_UNUSED
;
1568 return (GET_CODE (op
) == MEM
1569 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1570 || (reload_in_progress
&& GET_CODE (op
) == REG
1571 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1572 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1573 && GET_CODE (SUBREG_REG (op
)) == REG
1574 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1577 /* Returns 1 if OP is not an eliminable register.
1579 This exists to cure a pathological abort in the s8addq (et al) patterns,
1581 long foo () { long t; bar(); return (long) &t * 26107; }
1583 which run afoul of a hack in reload to cure a (presumably) similar
1584 problem with lea-type instructions on other targets. But there is
1585 one of us and many of them, so work around the problem by selectively
1586 preventing combine from making the optimization. */
1589 reg_not_elim_operand (op
, mode
)
1591 enum machine_mode mode
;
1594 if (GET_CODE (op
) == SUBREG
)
1595 inner
= SUBREG_REG (op
);
1596 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1599 return register_operand (op
, mode
);
1602 /* Return 1 is OP is a memory location that is not a reference (using
1603 an AND) to an unaligned location. Take into account what reload
1607 normal_memory_operand (op
, mode
)
1609 enum machine_mode mode ATTRIBUTE_UNUSED
;
1611 if (reload_in_progress
)
1614 if (GET_CODE (tmp
) == SUBREG
)
1615 tmp
= SUBREG_REG (tmp
);
1616 if (GET_CODE (tmp
) == REG
1617 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1619 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1621 /* This may not have been assigned an equivalent address if it will
1622 be eliminated. In that case, it doesn't matter what we do. */
1628 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1631 /* Accept a register, but not a subreg of any kind. This allows us to
1632 avoid pathological cases in reload wrt data movement common in
1633 int->fp conversion. */
1636 reg_no_subreg_operand (op
, mode
)
1638 enum machine_mode mode
;
1640 if (GET_CODE (op
) != REG
)
1642 return register_operand (op
, mode
);
1645 /* Recognize an addition operation that includes a constant. Used to
1646 convince reload to canonize (plus (plus reg c1) c2) during register
1650 addition_operation (op
, mode
)
1652 enum machine_mode mode
;
1654 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1656 if (GET_CODE (op
) == PLUS
1657 && register_operand (XEXP (op
, 0), mode
)
1658 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1659 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1664 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1665 the range defined for C in [I-P]. */
1668 alpha_const_ok_for_letter_p (value
, c
)
1669 HOST_WIDE_INT value
;
1675 /* An unsigned 8 bit constant. */
1676 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1678 /* The constant zero. */
1681 /* A signed 16 bit constant. */
1682 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1684 /* A shifted signed 16 bit constant appropriate for LDAH. */
1685 return ((value
& 0xffff) == 0
1686 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1688 /* A constant that can be AND'ed with using a ZAP insn. */
1689 return zap_mask (value
);
1691 /* A complemented unsigned 8 bit constant. */
1692 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1694 /* A negated unsigned 8 bit constant. */
1695 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1697 /* The constant 1, 2 or 3. */
1698 return value
== 1 || value
== 2 || value
== 3;
1705 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1706 matches for C in [GH]. */
1709 alpha_const_double_ok_for_letter_p (value
, c
)
1716 /* The floating point zero constant. */
1717 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1718 && value
== CONST0_RTX (GET_MODE (value
)));
1721 /* A valid operand of a ZAP insn. */
1722 return (GET_MODE (value
) == VOIDmode
1723 && zap_mask (CONST_DOUBLE_LOW (value
))
1724 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1731 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1735 alpha_extra_constraint (value
, c
)
1742 return normal_memory_operand (value
, VOIDmode
);
1744 return direct_call_operand (value
, Pmode
);
1746 return (GET_CODE (value
) == CONST_INT
1747 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1749 return GET_CODE (value
) == HIGH
;
1751 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1753 return (GET_CODE (value
) == CONST_VECTOR
1754 && value
== CONST0_RTX (GET_MODE (value
)));
1760 /* Return 1 if this function can directly return via $26. */
1765 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1767 && alpha_sa_size () == 0
1768 && get_frame_size () == 0
1769 && current_function_outgoing_args_size
== 0
1770 && current_function_pretend_args_size
== 0);
1773 /* Return the ADDR_VEC associated with a tablejump insn. */
1776 alpha_tablejump_addr_vec (insn
)
1781 tmp
= JUMP_LABEL (insn
);
1784 tmp
= NEXT_INSN (tmp
);
1787 if (GET_CODE (tmp
) == JUMP_INSN
1788 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1789 return PATTERN (tmp
);
1793 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1796 alpha_tablejump_best_label (insn
)
1799 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1800 rtx best_label
= NULL_RTX
;
1802 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1803 there for edge frequency counts from profile data. */
1807 int n_labels
= XVECLEN (jump_table
, 1);
1808 int best_count
= -1;
1811 for (i
= 0; i
< n_labels
; i
++)
1815 for (j
= i
+ 1; j
< n_labels
; j
++)
1816 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1817 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1820 if (count
> best_count
)
1821 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1825 return best_label
? best_label
: const0_rtx
;
1828 /* Return the TLS model to use for SYMBOL. */
1830 static enum tls_model
1831 tls_symbolic_operand_type (symbol
)
1834 enum tls_model model
;
1836 if (GET_CODE (symbol
) != SYMBOL_REF
)
1838 model
= SYMBOL_REF_TLS_MODEL (symbol
);
1840 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1841 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
1842 model
= TLS_MODEL_INITIAL_EXEC
;
1847 /* Return true if the function DECL will share the same GP as any
1848 function in the current unit of translation. */
1851 decl_has_samegp (decl
)
1854 /* Functions that are not local can be overridden, and thus may
1855 not share the same gp. */
1856 if (!(*targetm
.binds_local_p
) (decl
))
1859 /* If -msmall-data is in effect, assume that there is only one GP
1860 for the module, and so any local symbol has this property. We
1861 need explicit relocations to be able to enforce this for symbols
1862 not defined in this unit of translation, however. */
1863 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1866 /* Functions that are not external are defined in this UoT. */
1867 /* ??? Irritatingly, static functions not yet emitted are still
1868 marked "external". Apply this to non-static functions only. */
1869 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1872 /* Return true if EXP should be placed in the small data section. */
1875 alpha_in_small_data_p (exp
)
1878 /* We want to merge strings, so we never consider them small data. */
1879 if (TREE_CODE (exp
) == STRING_CST
)
1882 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1884 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1885 if (strcmp (section
, ".sdata") == 0
1886 || strcmp (section
, ".sbss") == 0)
1891 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1893 /* If this is an incomplete type with size 0, then we can't put it
1894 in sdata because it might be too big when completed. */
1895 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
1902 #if TARGET_ABI_OPEN_VMS
1904 alpha_linkage_symbol_p (symname
)
1905 const char *symname
;
1907 int symlen
= strlen (symname
);
1910 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1915 #define LINKAGE_SYMBOL_REF_P(X) \
1916 ((GET_CODE (X) == SYMBOL_REF \
1917 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1918 || (GET_CODE (X) == CONST \
1919 && GET_CODE (XEXP (X, 0)) == PLUS \
1920 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1921 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1924 /* legitimate_address_p recognizes an RTL expression that is a valid
1925 memory address for an instruction. The MODE argument is the
1926 machine mode for the MEM expression that wants to use this address.
1928 For Alpha, we have either a constant address or the sum of a
1929 register and a constant address, or just a register. For DImode,
1930 any of those forms can be surrounded with an AND that clear the
1931 low-order three bits; this is an "unaligned" access. */
1934 alpha_legitimate_address_p (mode
, x
, strict
)
1935 enum machine_mode mode
;
1939 /* If this is an ldq_u type address, discard the outer AND. */
1941 && GET_CODE (x
) == AND
1942 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1943 && INTVAL (XEXP (x
, 1)) == -8)
1946 /* Discard non-paradoxical subregs. */
1947 if (GET_CODE (x
) == SUBREG
1948 && (GET_MODE_SIZE (GET_MODE (x
))
1949 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1952 /* Unadorned general registers are valid. */
1955 ? STRICT_REG_OK_FOR_BASE_P (x
)
1956 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1959 /* Constant addresses (i.e. +/- 32k) are valid. */
1960 if (CONSTANT_ADDRESS_P (x
))
1963 #if TARGET_ABI_OPEN_VMS
1964 if (LINKAGE_SYMBOL_REF_P (x
))
1968 /* Register plus a small constant offset is valid. */
1969 if (GET_CODE (x
) == PLUS
)
1971 rtx ofs
= XEXP (x
, 1);
1974 /* Discard non-paradoxical subregs. */
1975 if (GET_CODE (x
) == SUBREG
1976 && (GET_MODE_SIZE (GET_MODE (x
))
1977 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1983 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1984 && GET_CODE (ofs
) == CONST_INT
)
1987 ? STRICT_REG_OK_FOR_BASE_P (x
)
1988 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1989 && CONSTANT_ADDRESS_P (ofs
))
1992 else if (GET_CODE (x
) == ADDRESSOF
1993 && GET_CODE (ofs
) == CONST_INT
)
1997 /* If we're managing explicit relocations, LO_SUM is valid, as
1998 are small data symbols. */
1999 else if (TARGET_EXPLICIT_RELOCS
)
2001 if (small_symbolic_operand (x
, Pmode
))
2004 if (GET_CODE (x
) == LO_SUM
)
2006 rtx ofs
= XEXP (x
, 1);
2009 /* Discard non-paradoxical subregs. */
2010 if (GET_CODE (x
) == SUBREG
2011 && (GET_MODE_SIZE (GET_MODE (x
))
2012 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2015 /* Must have a valid base register. */
2018 ? STRICT_REG_OK_FOR_BASE_P (x
)
2019 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2022 /* The symbol must be local. */
2023 if (local_symbolic_operand (ofs
, Pmode
)
2024 || dtp32_symbolic_operand (ofs
, Pmode
)
2025 || tp32_symbolic_operand (ofs
, Pmode
))
2033 /* Build the SYMBOL_REF for __tls_get_addr. */
2035 static GTY(()) rtx tls_get_addr_libfunc
;
2040 if (!tls_get_addr_libfunc
)
2041 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
2042 return tls_get_addr_libfunc
;
2045 /* Try machine-dependent ways of modifying an illegitimate address
2046 to be legitimate. If we find one, return the new, valid address. */
2049 alpha_legitimize_address (x
, scratch
, mode
)
2052 enum machine_mode mode ATTRIBUTE_UNUSED
;
2054 HOST_WIDE_INT addend
;
2056 /* If the address is (plus reg const_int) and the CONST_INT is not a
2057 valid offset, compute the high part of the constant and add it to
2058 the register. Then our address is (plus temp low-part-const). */
2059 if (GET_CODE (x
) == PLUS
2060 && GET_CODE (XEXP (x
, 0)) == REG
2061 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2062 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2064 addend
= INTVAL (XEXP (x
, 1));
2069 /* If the address is (const (plus FOO const_int)), find the low-order
2070 part of the CONST_INT. Then load FOO plus any high-order part of the
2071 CONST_INT into a register. Our address is (plus reg low-part-const).
2072 This is done to reduce the number of GOT entries. */
2074 && GET_CODE (x
) == CONST
2075 && GET_CODE (XEXP (x
, 0)) == PLUS
2076 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2078 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2079 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2083 /* If we have a (plus reg const), emit the load as in (2), then add
2084 the two registers, and finally generate (plus reg low-part-const) as
2087 && GET_CODE (x
) == PLUS
2088 && GET_CODE (XEXP (x
, 0)) == REG
2089 && GET_CODE (XEXP (x
, 1)) == CONST
2090 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2091 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2093 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2094 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2095 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2096 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2100 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2101 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2103 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2105 switch (tls_symbolic_operand_type (x
))
2107 case TLS_MODEL_GLOBAL_DYNAMIC
:
2110 r0
= gen_rtx_REG (Pmode
, 0);
2111 r16
= gen_rtx_REG (Pmode
, 16);
2112 tga
= get_tls_get_addr ();
2113 dest
= gen_reg_rtx (Pmode
);
2114 seq
= GEN_INT (alpha_next_sequence_number
++);
2116 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2117 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2118 insn
= emit_call_insn (insn
);
2119 CONST_OR_PURE_CALL_P (insn
) = 1;
2120 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2122 insn
= get_insns ();
2125 emit_libcall_block (insn
, dest
, r0
, x
);
2128 case TLS_MODEL_LOCAL_DYNAMIC
:
2131 r0
= gen_rtx_REG (Pmode
, 0);
2132 r16
= gen_rtx_REG (Pmode
, 16);
2133 tga
= get_tls_get_addr ();
2134 scratch
= gen_reg_rtx (Pmode
);
2135 seq
= GEN_INT (alpha_next_sequence_number
++);
2137 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2138 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2139 insn
= emit_call_insn (insn
);
2140 CONST_OR_PURE_CALL_P (insn
) = 1;
2141 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2143 insn
= get_insns ();
2146 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2147 UNSPEC_TLSLDM_CALL
);
2148 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2150 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2151 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2153 if (alpha_tls_size
== 64)
2155 dest
= gen_reg_rtx (Pmode
);
2156 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2157 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2160 if (alpha_tls_size
== 32)
2162 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2163 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2164 scratch
= gen_reg_rtx (Pmode
);
2165 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2167 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2169 case TLS_MODEL_INITIAL_EXEC
:
2170 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2171 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2172 tp
= gen_reg_rtx (Pmode
);
2173 scratch
= gen_reg_rtx (Pmode
);
2174 dest
= gen_reg_rtx (Pmode
);
2176 emit_insn (gen_load_tp (tp
));
2177 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2178 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2181 case TLS_MODEL_LOCAL_EXEC
:
2182 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2183 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2184 tp
= gen_reg_rtx (Pmode
);
2186 emit_insn (gen_load_tp (tp
));
2187 if (alpha_tls_size
== 32)
2189 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2190 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2191 tp
= gen_reg_rtx (Pmode
);
2192 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2194 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2197 if (local_symbolic_operand (x
, Pmode
))
2199 if (small_symbolic_operand (x
, Pmode
))
2203 if (!no_new_pseudos
)
2204 scratch
= gen_reg_rtx (Pmode
);
2205 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2206 gen_rtx_HIGH (Pmode
, x
)));
2207 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2216 HOST_WIDE_INT low
, high
;
2218 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2220 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2224 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2225 (no_new_pseudos
? scratch
: NULL_RTX
),
2226 1, OPTAB_LIB_WIDEN
);
2228 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2229 (no_new_pseudos
? scratch
: NULL_RTX
),
2230 1, OPTAB_LIB_WIDEN
);
2232 return plus_constant (x
, low
);
2236 /* We do not allow indirect calls to be optimized into sibling calls, nor
2237 can we allow a call to a function with a different GP to be optimized
2241 alpha_function_ok_for_sibcall (decl
, exp
)
2243 tree exp ATTRIBUTE_UNUSED
;
2245 /* Can't do indirect tail calls, since we don't know if the target
2246 uses the same GP. */
2250 /* Otherwise, we can make a tail call if the target function shares
2252 return decl_has_samegp (decl
);
2255 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2256 small symbolic operand until after reload. At which point we need
2257 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2258 so that sched2 has the proper dependency information. */
2261 some_small_symbolic_operand (x
, mode
)
2263 enum machine_mode mode ATTRIBUTE_UNUSED
;
2265 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2269 some_small_symbolic_operand_1 (px
, data
)
2271 void *data ATTRIBUTE_UNUSED
;
2275 /* Don't re-split. */
2276 if (GET_CODE (x
) == LO_SUM
)
2279 return small_symbolic_operand (x
, Pmode
) != 0;
2283 split_small_symbolic_operand (x
)
2287 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2292 split_small_symbolic_operand_1 (px
, data
)
2294 void *data ATTRIBUTE_UNUSED
;
2298 /* Don't re-split. */
2299 if (GET_CODE (x
) == LO_SUM
)
2302 if (small_symbolic_operand (x
, Pmode
))
2304 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2312 /* Indicate that INSN cannot be duplicated. This is true for any insn
2313 that we've marked with gpdisp relocs, since those have to stay in
2314 1-1 correspondence with one another.
2316 Techinically we could copy them if we could set up a mapping from one
2317 sequence number to another, across the set of insns to be duplicated.
2318 This seems overly complicated and error-prone since interblock motion
2319 from sched-ebb could move one of the pair of insns to a different block. */
2322 alpha_cannot_copy_insn_p (insn
)
2327 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2330 if (GET_CODE (insn
) != INSN
)
2332 if (asm_noperands (insn
) >= 0)
2335 pat
= PATTERN (insn
);
2336 if (GET_CODE (pat
) != SET
)
2338 pat
= SET_SRC (pat
);
2339 if (GET_CODE (pat
) == UNSPEC_VOLATILE
)
2341 if (XINT (pat
, 1) == UNSPECV_LDGP1
2342 || XINT (pat
, 1) == UNSPECV_PLDGP2
)
2345 else if (GET_CODE (pat
) == UNSPEC
)
2347 if (XINT (pat
, 1) == UNSPEC_LDGP2
)
2355 /* Try a machine-dependent way of reloading an illegitimate address
2356 operand. If we find one, push the reload and return the new rtx. */
2359 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2361 enum machine_mode mode ATTRIBUTE_UNUSED
;
2364 int ind_levels ATTRIBUTE_UNUSED
;
2366 /* We must recognize output that we have already generated ourselves. */
2367 if (GET_CODE (x
) == PLUS
2368 && GET_CODE (XEXP (x
, 0)) == PLUS
2369 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2370 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2371 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2373 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2374 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2379 /* We wish to handle large displacements off a base register by
2380 splitting the addend across an ldah and the mem insn. This
2381 cuts number of extra insns needed from 3 to 1. */
2382 if (GET_CODE (x
) == PLUS
2383 && GET_CODE (XEXP (x
, 0)) == REG
2384 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2385 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2386 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2388 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2389 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2391 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2393 /* Check for 32-bit overflow. */
2394 if (high
+ low
!= val
)
2397 /* Reload the high part into a base reg; leave the low part
2398 in the mem directly. */
2399 x
= gen_rtx_PLUS (GET_MODE (x
),
2400 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2404 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2405 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2413 /* Compute a (partial) cost for rtx X. Return true if the complete
2414 cost has been computed, and false if subexpressions should be
2415 scanned. In either case, *TOTAL contains the cost result. */
2418 alpha_rtx_costs (x
, code
, outer_code
, total
)
2420 int code
, outer_code
;
2423 enum machine_mode mode
= GET_MODE (x
);
2424 bool float_mode_p
= FLOAT_MODE_P (mode
);
2428 /* If this is an 8-bit constant, return zero since it can be used
2429 nearly anywhere with no cost. If it is a valid operand for an
2430 ADD or AND, likewise return 0 if we know it will be used in that
2431 context. Otherwise, return 2 since it might be used there later.
2432 All other constants take at least two insns. */
2434 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2442 if (x
== CONST0_RTX (mode
))
2444 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2445 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2447 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2450 *total
= COSTS_N_INSNS (2);
2456 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2457 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2458 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2459 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2460 else if (tls_symbolic_operand_type (x
))
2461 /* Estimate of cost for call_pal rduniq. */
2462 *total
= COSTS_N_INSNS (15);
2464 /* Otherwise we do a load from the GOT. */
2465 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2471 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2472 else if (GET_CODE (XEXP (x
, 0)) == MULT
2473 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2475 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2476 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2483 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2484 else if (mode
== DImode
)
2485 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2487 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2491 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2492 && INTVAL (XEXP (x
, 1)) <= 3)
2494 *total
= COSTS_N_INSNS (1);
2501 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2506 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2508 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2516 *total
= COSTS_N_INSNS (70); /* ??? */
2517 else if (mode
== SFmode
)
2518 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2520 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2524 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2530 *total
= COSTS_N_INSNS (1);
2538 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2544 case UNSIGNED_FLOAT
:
2548 case FLOAT_TRUNCATE
:
2549 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2557 /* REF is an alignable memory location. Place an aligned SImode
2558 reference into *PALIGNED_MEM and the number of bits to shift into
2559 *PBITNUM. SCRATCH is a free register for use in reloading out
2560 of range stack slots. */
2563 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2565 rtx
*paligned_mem
, *pbitnum
;
2568 HOST_WIDE_INT offset
= 0;
2570 if (GET_CODE (ref
) != MEM
)
2573 if (reload_in_progress
2574 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2576 base
= find_replacement (&XEXP (ref
, 0));
2578 if (! memory_address_p (GET_MODE (ref
), base
))
2583 base
= XEXP (ref
, 0);
2586 if (GET_CODE (base
) == PLUS
)
2587 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2590 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2592 if (WORDS_BIG_ENDIAN
)
2593 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2594 + (offset
& 3) * 8));
2596 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2599 /* Similar, but just get the address. Handle the two reload cases.
2600 Add EXTRA_OFFSET to the address we return. */
2603 get_unaligned_address (ref
, extra_offset
)
2608 HOST_WIDE_INT offset
= 0;
2610 if (GET_CODE (ref
) != MEM
)
2613 if (reload_in_progress
2614 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2616 base
= find_replacement (&XEXP (ref
, 0));
2618 if (! memory_address_p (GET_MODE (ref
), base
))
2623 base
= XEXP (ref
, 0);
2626 if (GET_CODE (base
) == PLUS
)
2627 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2629 return plus_constant (base
, offset
+ extra_offset
);
2632 /* On the Alpha, all (non-symbolic) constants except zero go into
2633 a floating-point register via memory. Note that we cannot
2634 return anything that is not a subset of CLASS, and that some
2635 symbolic constants cannot be dropped to memory. */
2638 alpha_preferred_reload_class(x
, class)
2640 enum reg_class
class;
2642 /* Zero is present in any register class. */
2643 if (x
== CONST0_RTX (GET_MODE (x
)))
2646 /* These sorts of constants we can easily drop to memory. */
2647 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2649 if (class == FLOAT_REGS
)
2651 if (class == ALL_REGS
)
2652 return GENERAL_REGS
;
2656 /* All other kinds of constants should not (and in the case of HIGH
2657 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2658 secondary reload. */
2660 return (class == ALL_REGS
? GENERAL_REGS
: class);
2665 /* Loading and storing HImode or QImode values to and from memory
2666 usually requires a scratch register. The exceptions are loading
2667 QImode and HImode from an aligned address to a general register
2668 unless byte instructions are permitted.
2670 We also cannot load an unaligned address or a paradoxical SUBREG
2671 into an FP register.
2673 We also cannot do integral arithmetic into FP regs, as might result
2674 from register elimination into a DImode fp register. */
2677 secondary_reload_class (class, mode
, x
, in
)
2678 enum reg_class
class;
2679 enum machine_mode mode
;
2683 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2685 if (GET_CODE (x
) == MEM
2686 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2687 || (GET_CODE (x
) == SUBREG
2688 && (GET_CODE (SUBREG_REG (x
)) == MEM
2689 || (GET_CODE (SUBREG_REG (x
)) == REG
2690 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2692 if (!in
|| !aligned_memory_operand(x
, mode
))
2693 return GENERAL_REGS
;
2697 if (class == FLOAT_REGS
)
2699 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2700 return GENERAL_REGS
;
2702 if (GET_CODE (x
) == SUBREG
2703 && (GET_MODE_SIZE (GET_MODE (x
))
2704 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2705 return GENERAL_REGS
;
2707 if (in
&& INTEGRAL_MODE_P (mode
)
2708 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2709 return GENERAL_REGS
;
2715 /* Subfunction of the following function. Update the flags of any MEM
2716 found in part of X. */
2719 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2721 int in_struct_p
, volatile_p
, unchanging_p
;
2725 switch (GET_CODE (x
))
2731 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2732 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2737 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2742 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2744 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2749 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2750 MEM_VOLATILE_P (x
) = volatile_p
;
2751 RTX_UNCHANGING_P (x
) = unchanging_p
;
2752 /* Sadly, we cannot use alias sets because the extra aliasing
2753 produced by the AND interferes. Given that two-byte quantities
2754 are the only thing we would be able to differentiate anyway,
2755 there does not seem to be any point in convoluting the early
2756 out of the alias check. */
2764 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2765 generated to perform a memory operation, look for any MEMs in either
2766 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2767 volatile flags from REF into each of the MEMs found. If REF is not
2768 a MEM, don't do anything. */
2771 alpha_set_memflags (insn
, ref
)
2775 int in_struct_p
, volatile_p
, unchanging_p
;
2777 if (GET_CODE (ref
) != MEM
)
2780 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2781 volatile_p
= MEM_VOLATILE_P (ref
);
2782 unchanging_p
= RTX_UNCHANGING_P (ref
);
2784 /* This is only called from alpha.md, after having had something
2785 generated from one of the insn patterns. So if everything is
2786 zero, the pattern is already up-to-date. */
2787 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2790 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2793 /* Try to output insns to set TARGET equal to the constant C if it can be
2794 done in less than N insns. Do all computations in MODE. Returns the place
2795 where the output has been placed if it can be done and the insns have been
2796 emitted. If it would take more than N insns, zero is returned and no
2797 insns and emitted. */
2800 alpha_emit_set_const (target
, mode
, c
, n
)
2802 enum machine_mode mode
;
2807 rtx orig_target
= target
;
2810 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2811 can't load this constant in one insn, do this in DImode. */
2812 if (no_new_pseudos
&& mode
== SImode
2813 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2814 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2816 target
= gen_lowpart (DImode
, target
);
2820 /* Try 1 insn, then 2, then up to N. */
2821 for (i
= 1; i
<= n
; i
++)
2823 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2826 rtx insn
= get_last_insn ();
2827 rtx set
= single_set (insn
);
2828 if (! CONSTANT_P (SET_SRC (set
)))
2829 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2834 /* Allow for the case where we changed the mode of TARGET. */
2835 if (result
== target
)
2836 result
= orig_target
;
2841 /* Internal routine for the above to check for N or below insns. */
2844 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2846 enum machine_mode mode
;
2852 /* Use a pseudo if highly optimizing and still generating RTL. */
2854 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2857 /* If this is a sign-extended 32-bit constant, we can do this in at most
2858 three insns, so do it if we have enough insns left. We always have
2859 a sign-extended 32-bit constant when compiling on a narrow machine. */
2861 if (HOST_BITS_PER_WIDE_INT
!= 64
2862 || c
>> 31 == -1 || c
>> 31 == 0)
2864 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2865 HOST_WIDE_INT tmp1
= c
- low
;
2866 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2867 HOST_WIDE_INT extra
= 0;
2869 /* If HIGH will be interpreted as negative but the constant is
2870 positive, we must adjust it to do two ldha insns. */
2872 if ((high
& 0x8000) != 0 && c
>= 0)
2876 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2879 if (c
== low
|| (low
== 0 && extra
== 0))
2881 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2882 but that meant that we can't handle INT_MIN on 32-bit machines
2883 (like NT/Alpha), because we recurse indefinitely through
2884 emit_move_insn to gen_movdi. So instead, since we know exactly
2885 what we want, create it explicitly. */
2888 target
= gen_reg_rtx (mode
);
2889 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2892 else if (n
>= 2 + (extra
!= 0))
2894 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2896 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2897 This means that if we go through expand_binop, we'll try to
2898 generate extensions, etc, which will require new pseudos, which
2899 will fail during some split phases. The SImode add patterns
2900 still exist, but are not named. So build the insns by hand. */
2905 subtarget
= gen_reg_rtx (mode
);
2906 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2907 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2913 target
= gen_reg_rtx (mode
);
2914 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2915 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2921 /* If we couldn't do it that way, try some other methods. But if we have
2922 no instructions left, don't bother. Likewise, if this is SImode and
2923 we can't make pseudos, we can't do anything since the expand_binop
2924 and expand_unop calls will widen and try to make pseudos. */
2926 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2929 /* Next, see if we can load a related constant and then shift and possibly
2930 negate it to get the constant we want. Try this once each increasing
2931 numbers of insns. */
2933 for (i
= 1; i
< n
; i
++)
2935 /* First, see if minus some low bits, we've an easy load of
2938 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2940 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2941 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2942 target
, 0, OPTAB_WIDEN
);
2944 /* Next try complementing. */
2945 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2946 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2948 /* Next try to form a constant and do a left shift. We can do this
2949 if some low-order bits are zero; the exact_log2 call below tells
2950 us that information. The bits we are shifting out could be any
2951 value, but here we'll just try the 0- and sign-extended forms of
2952 the constant. To try to increase the chance of having the same
2953 constant in more than one insn, start at the highest number of
2954 bits to shift, but try all possibilities in case a ZAPNOT will
2957 if ((bits
= exact_log2 (c
& - c
)) > 0)
2958 for (; bits
> 0; bits
--)
2959 if ((temp
= (alpha_emit_set_const
2960 (subtarget
, mode
, c
>> bits
, i
))) != 0
2961 || ((temp
= (alpha_emit_set_const
2963 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2965 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2966 target
, 0, OPTAB_WIDEN
);
2968 /* Now try high-order zero bits. Here we try the shifted-in bits as
2969 all zero and all ones. Be careful to avoid shifting outside the
2970 mode and to avoid shifting outside the host wide int size. */
2971 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2972 confuse the recursive call and set all of the high 32 bits. */
2974 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2975 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2976 for (; bits
> 0; bits
--)
2977 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2979 || ((temp
= (alpha_emit_set_const
2981 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2984 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2985 target
, 1, OPTAB_WIDEN
);
2987 /* Now try high-order 1 bits. We get that with a sign-extension.
2988 But one bit isn't enough here. Be careful to avoid shifting outside
2989 the mode and to avoid shifting outside the host wide int size. */
2991 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2992 - floor_log2 (~ c
) - 2)) > 0)
2993 for (; bits
> 0; bits
--)
2994 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2996 || ((temp
= (alpha_emit_set_const
2998 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
3001 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
3002 target
, 0, OPTAB_WIDEN
);
3005 #if HOST_BITS_PER_WIDE_INT == 64
3006 /* Finally, see if can load a value into the target that is the same as the
3007 constant except that all bytes that are 0 are changed to be 0xff. If we
3008 can, then we can do a ZAPNOT to obtain the desired constant. */
3011 for (i
= 0; i
< 64; i
+= 8)
3012 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
3013 new |= (HOST_WIDE_INT
) 0xff << i
;
3015 /* We are only called for SImode and DImode. If this is SImode, ensure that
3016 we are sign extended to a full word. */
3019 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
3021 if (new != c
&& new != -1
3022 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
3023 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
3024 target
, 0, OPTAB_WIDEN
);
3030 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
3031 fall back to a straight forward decomposition. We do this to avoid
3032 exponential run times encountered when looking for longer sequences
3033 with alpha_emit_set_const. */
3036 alpha_emit_set_long_const (target
, c1
, c2
)
3038 HOST_WIDE_INT c1
, c2
;
3040 HOST_WIDE_INT d1
, d2
, d3
, d4
;
3042 /* Decompose the entire word */
3043 #if HOST_BITS_PER_WIDE_INT >= 64
3044 if (c2
!= -(c1
< 0))
3046 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3048 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3049 c1
= (c1
- d2
) >> 32;
3050 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3052 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3056 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3058 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3062 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
3064 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3069 /* Construct the high word */
3072 emit_move_insn (target
, GEN_INT (d4
));
3074 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
3077 emit_move_insn (target
, GEN_INT (d3
));
3079 /* Shift it into place */
3080 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
3082 /* Add in the low bits. */
3084 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
3086 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
3091 /* Expand a move instruction; return true if all work is done.
3092 We don't handle non-bwx subword loads here. */
3095 alpha_expand_mov (mode
, operands
)
3096 enum machine_mode mode
;
3099 /* If the output is not a register, the input must be. */
3100 if (GET_CODE (operands
[0]) == MEM
3101 && ! reg_or_0_operand (operands
[1], mode
))
3102 operands
[1] = force_reg (mode
, operands
[1]);
3104 /* Allow legitimize_address to perform some simplifications. */
3105 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
3109 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
3110 compiled at the end of compilation. In the meantime, someone can
3111 re-encode-section-info on some symbol changing it e.g. from global
3112 to local-not-small. If this happens, we'd have emitted a plain
3113 load rather than a high+losum load and not recognize the insn.
3115 So if rtl inlining is in effect, we delay the global/not-global
3116 decision until rest_of_compilation by wrapping it in an
3118 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
3119 && rtx_equal_function_value_matters
3120 && global_symbolic_operand (operands
[1], mode
))
3122 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
3126 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
3129 if (tmp
== operands
[0])
3136 /* Early out for non-constants and valid constants. */
3137 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
3140 /* Split large integers. */
3141 if (GET_CODE (operands
[1]) == CONST_INT
3142 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
3144 HOST_WIDE_INT i0
, i1
;
3145 rtx temp
= NULL_RTX
;
3147 if (GET_CODE (operands
[1]) == CONST_INT
)
3149 i0
= INTVAL (operands
[1]);
3152 else if (HOST_BITS_PER_WIDE_INT
>= 64)
3154 i0
= CONST_DOUBLE_LOW (operands
[1]);
3159 i0
= CONST_DOUBLE_LOW (operands
[1]);
3160 i1
= CONST_DOUBLE_HIGH (operands
[1]);
3163 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
3164 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
3166 if (!temp
&& TARGET_BUILD_CONSTANTS
)
3167 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
3171 if (rtx_equal_p (operands
[0], temp
))
3178 /* Otherwise we've nothing left but to drop the thing to memory. */
3179 operands
[1] = force_const_mem (mode
, operands
[1]);
3180 if (reload_in_progress
)
3182 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
3183 operands
[1] = copy_rtx (operands
[1]);
3184 XEXP (operands
[1], 0) = operands
[0];
3187 operands
[1] = validize_mem (operands
[1]);
3191 /* Expand a non-bwx QImode or HImode move instruction;
3192 return true if all work is done. */
3195 alpha_expand_mov_nobwx (mode
, operands
)
3196 enum machine_mode mode
;
3199 /* If the output is not a register, the input must be. */
3200 if (GET_CODE (operands
[0]) == MEM
)
3201 operands
[1] = force_reg (mode
, operands
[1]);
3203 /* Handle four memory cases, unaligned and aligned for either the input
3204 or the output. The only case where we can be called during reload is
3205 for aligned loads; all other cases require temporaries. */
3207 if (GET_CODE (operands
[1]) == MEM
3208 || (GET_CODE (operands
[1]) == SUBREG
3209 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3210 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3211 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3212 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3213 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3214 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3216 if (aligned_memory_operand (operands
[1], mode
))
3218 if (reload_in_progress
)
3220 emit_insn ((mode
== QImode
3221 ? gen_reload_inqi_help
3222 : gen_reload_inhi_help
)
3223 (operands
[0], operands
[1],
3224 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3228 rtx aligned_mem
, bitnum
;
3229 rtx scratch
= gen_reg_rtx (SImode
);
3231 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3233 emit_insn ((mode
== QImode
3234 ? gen_aligned_loadqi
3235 : gen_aligned_loadhi
)
3236 (operands
[0], aligned_mem
, bitnum
, scratch
));
3241 /* Don't pass these as parameters since that makes the generated
3242 code depend on parameter evaluation order which will cause
3243 bootstrap failures. */
3245 rtx temp1
= gen_reg_rtx (DImode
);
3246 rtx temp2
= gen_reg_rtx (DImode
);
3247 rtx seq
= ((mode
== QImode
3248 ? gen_unaligned_loadqi
3249 : gen_unaligned_loadhi
)
3250 (operands
[0], get_unaligned_address (operands
[1], 0),
3253 alpha_set_memflags (seq
, operands
[1]);
3259 if (GET_CODE (operands
[0]) == MEM
3260 || (GET_CODE (operands
[0]) == SUBREG
3261 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3262 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3263 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3264 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3265 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3266 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3268 if (aligned_memory_operand (operands
[0], mode
))
3270 rtx aligned_mem
, bitnum
;
3271 rtx temp1
= gen_reg_rtx (SImode
);
3272 rtx temp2
= gen_reg_rtx (SImode
);
3274 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3276 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3281 rtx temp1
= gen_reg_rtx (DImode
);
3282 rtx temp2
= gen_reg_rtx (DImode
);
3283 rtx temp3
= gen_reg_rtx (DImode
);
3284 rtx seq
= ((mode
== QImode
3285 ? gen_unaligned_storeqi
3286 : gen_unaligned_storehi
)
3287 (get_unaligned_address (operands
[0], 0),
3288 operands
[1], temp1
, temp2
, temp3
));
3290 alpha_set_memflags (seq
, operands
[0]);
3299 /* Generate an unsigned DImode to FP conversion. This is the same code
3300 optabs would emit if we didn't have TFmode patterns.
3302 For SFmode, this is the only construction I've found that can pass
3303 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3304 intermediates will work, because you'll get intermediate rounding
3305 that ruins the end result. Some of this could be fixed by turning
3306 on round-to-positive-infinity, but that requires diddling the fpsr,
3307 which kills performance. I tried turning this around and converting
3308 to a negative number, so that I could turn on /m, but either I did
3309 it wrong or there's something else cause I wound up with the exact
3310 same single-bit error. There is a branch-less form of this same code:
3321 fcmoveq $f10,$f11,$f0
3323 I'm not using it because it's the same number of instructions as
3324 this branch-full form, and it has more serialized long latency
3325 instructions on the critical path.
3327 For DFmode, we can avoid rounding errors by breaking up the word
3328 into two pieces, converting them separately, and adding them back:
3330 LC0: .long 0,0x5f800000
3335 cpyse $f11,$f31,$f10
3336 cpyse $f31,$f11,$f11
3344 This doesn't seem to be a clear-cut win over the optabs form.
3345 It probably all depends on the distribution of numbers being
3346 converted -- in the optabs form, all but high-bit-set has a
3347 much lower minimum execution time. */
3350 alpha_emit_floatuns (operands
)
3353 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3354 enum machine_mode mode
;
3357 in
= force_reg (DImode
, operands
[1]);
3358 mode
= GET_MODE (out
);
3359 neglab
= gen_label_rtx ();
3360 donelab
= gen_label_rtx ();
3361 i0
= gen_reg_rtx (DImode
);
3362 i1
= gen_reg_rtx (DImode
);
3363 f0
= gen_reg_rtx (mode
);
3365 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3367 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3368 emit_jump_insn (gen_jump (donelab
));
3371 emit_label (neglab
);
3373 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3374 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3375 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3376 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3377 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3379 emit_label (donelab
);
3382 /* Generate the comparison for a conditional branch. */
3385 alpha_emit_conditional_branch (code
)
3388 enum rtx_code cmp_code
, branch_code
;
3389 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3390 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3393 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3395 if (! TARGET_HAS_XFLOATING_LIBS
)
3398 /* X_floating library comparison functions return
3402 Convert the compare against the raw return value. */
3424 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3426 alpha_compare
.fp_p
= 0;
3429 /* The general case: fold the comparison code to the types of compares
3430 that we have, choosing the branch as necessary. */
3433 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3435 /* We have these compares: */
3436 cmp_code
= code
, branch_code
= NE
;
3441 /* These must be reversed. */
3442 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3445 case GE
: case GT
: case GEU
: case GTU
:
3446 /* For FP, we swap them, for INT, we reverse them. */
3447 if (alpha_compare
.fp_p
)
3449 cmp_code
= swap_condition (code
);
3451 tem
= op0
, op0
= op1
, op1
= tem
;
3455 cmp_code
= reverse_condition (code
);
3464 if (alpha_compare
.fp_p
)
3467 if (flag_unsafe_math_optimizations
)
3469 /* When we are not as concerned about non-finite values, and we
3470 are comparing against zero, we can branch directly. */
3471 if (op1
== CONST0_RTX (DFmode
))
3472 cmp_code
= NIL
, branch_code
= code
;
3473 else if (op0
== CONST0_RTX (DFmode
))
3475 /* Undo the swap we probably did just above. */
3476 tem
= op0
, op0
= op1
, op1
= tem
;
3477 branch_code
= swap_condition (cmp_code
);
3483 /* ??? We mark the branch mode to be CCmode to prevent the
3484 compare and branch from being combined, since the compare
3485 insn follows IEEE rules that the branch does not. */
3486 branch_mode
= CCmode
;
3493 /* The following optimizations are only for signed compares. */
3494 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3496 /* Whee. Compare and branch against 0 directly. */
3497 if (op1
== const0_rtx
)
3498 cmp_code
= NIL
, branch_code
= code
;
3500 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3501 bypass between logicals and br/cmov on EV5. But we don't want to
3502 force valid immediate constants into registers needlessly. */
3503 else if (GET_CODE (op1
) == CONST_INT
)
3505 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3507 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3508 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3509 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3511 cmp_code
= PLUS
, branch_code
= code
;
3517 if (!reg_or_0_operand (op0
, DImode
))
3518 op0
= force_reg (DImode
, op0
);
3519 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3520 op1
= force_reg (DImode
, op1
);
3523 /* Emit an initial compare instruction, if necessary. */
3525 if (cmp_code
!= NIL
)
3527 tem
= gen_reg_rtx (cmp_mode
);
3528 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3531 /* Zero the operands. */
3532 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3534 /* Return the branch comparison. */
3535 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3538 /* Certain simplifications can be done to make invalid setcc operations
3539 valid. Return the final comparison, or NULL if we can't work. */
3542 alpha_emit_setcc (code
)
3545 enum rtx_code cmp_code
;
3546 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3547 int fp_p
= alpha_compare
.fp_p
;
3550 /* Zero the operands. */
3551 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3553 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3555 if (! TARGET_HAS_XFLOATING_LIBS
)
3558 /* X_floating library comparison functions return
3562 Convert the compare against the raw return value. */
3564 if (code
== UNORDERED
|| code
== ORDERED
)
3569 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3573 if (code
== UNORDERED
)
3575 else if (code
== ORDERED
)
3581 if (fp_p
&& !TARGET_FIX
)
3584 /* The general case: fold the comparison code to the types of compares
3585 that we have, choosing the branch as necessary. */
3590 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3592 /* We have these compares. */
3594 cmp_code
= code
, code
= NE
;
3598 if (!fp_p
&& op1
== const0_rtx
)
3603 cmp_code
= reverse_condition (code
);
3607 case GE
: case GT
: case GEU
: case GTU
:
3608 /* These normally need swapping, but for integer zero we have
3609 special patterns that recognize swapped operands. */
3610 if (!fp_p
&& op1
== const0_rtx
)
3612 code
= swap_condition (code
);
3614 cmp_code
= code
, code
= NE
;
3615 tmp
= op0
, op0
= op1
, op1
= tmp
;
3624 if (!register_operand (op0
, DImode
))
3625 op0
= force_reg (DImode
, op0
);
3626 if (!reg_or_8bit_operand (op1
, DImode
))
3627 op1
= force_reg (DImode
, op1
);
3630 /* Emit an initial compare instruction, if necessary. */
3631 if (cmp_code
!= NIL
)
3633 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3635 tmp
= gen_reg_rtx (mode
);
3636 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3637 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3639 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3643 /* Return the setcc comparison. */
3644 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3648 /* Rewrite a comparison against zero CMP of the form
3649 (CODE (cc0) (const_int 0)) so it can be written validly in
3650 a conditional move (if_then_else CMP ...).
3651 If both of the operands that set cc0 are nonzero we must emit
3652 an insn to perform the compare (it can't be done within
3653 the conditional move). */
3655 alpha_emit_conditional_move (cmp
, mode
)
3657 enum machine_mode mode
;
3659 enum rtx_code code
= GET_CODE (cmp
);
3660 enum rtx_code cmov_code
= NE
;
3661 rtx op0
= alpha_compare
.op0
;
3662 rtx op1
= alpha_compare
.op1
;
3663 int fp_p
= alpha_compare
.fp_p
;
3664 enum machine_mode cmp_mode
3665 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3666 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3667 enum machine_mode cmov_mode
= VOIDmode
;
3668 int local_fast_math
= flag_unsafe_math_optimizations
;
3671 /* Zero the operands. */
3672 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3674 if (fp_p
!= FLOAT_MODE_P (mode
))
3676 enum rtx_code cmp_code
;
3681 /* If we have fp<->int register move instructions, do a cmov by
3682 performing the comparison in fp registers, and move the
3683 zero/nonzero value to integer registers, where we can then
3684 use a normal cmov, or vice-versa. */
3688 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3689 /* We have these compares. */
3690 cmp_code
= code
, code
= NE
;
3694 /* This must be reversed. */
3695 cmp_code
= EQ
, code
= EQ
;
3698 case GE
: case GT
: case GEU
: case GTU
:
3699 /* These normally need swapping, but for integer zero we have
3700 special patterns that recognize swapped operands. */
3701 if (!fp_p
&& op1
== const0_rtx
)
3702 cmp_code
= code
, code
= NE
;
3705 cmp_code
= swap_condition (code
);
3707 tem
= op0
, op0
= op1
, op1
= tem
;
3715 tem
= gen_reg_rtx (cmp_op_mode
);
3716 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3717 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3720 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3721 op0
= gen_lowpart (cmp_op_mode
, tem
);
3722 op1
= CONST0_RTX (cmp_op_mode
);
3724 local_fast_math
= 1;
3727 /* We may be able to use a conditional move directly.
3728 This avoids emitting spurious compares. */
3729 if (signed_comparison_operator (cmp
, VOIDmode
)
3730 && (!fp_p
|| local_fast_math
)
3731 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3732 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3734 /* We can't put the comparison inside the conditional move;
3735 emit a compare instruction and put that inside the
3736 conditional move. Make sure we emit only comparisons we have;
3737 swap or reverse as necessary. */
3744 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3745 /* We have these compares: */
3749 /* This must be reversed. */
3750 code
= reverse_condition (code
);
3754 case GE
: case GT
: case GEU
: case GTU
:
3755 /* These must be swapped. */
3756 if (op1
!= CONST0_RTX (cmp_mode
))
3758 code
= swap_condition (code
);
3759 tem
= op0
, op0
= op1
, op1
= tem
;
3769 if (!reg_or_0_operand (op0
, DImode
))
3770 op0
= force_reg (DImode
, op0
);
3771 if (!reg_or_8bit_operand (op1
, DImode
))
3772 op1
= force_reg (DImode
, op1
);
3775 /* ??? We mark the branch mode to be CCmode to prevent the compare
3776 and cmov from being combined, since the compare insn follows IEEE
3777 rules that the cmov does not. */
3778 if (fp_p
&& !local_fast_math
)
3781 tem
= gen_reg_rtx (cmp_op_mode
);
3782 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3783 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3786 /* Simplify a conditional move of two constants into a setcc with
3787 arithmetic. This is done with a splitter since combine would
3788 just undo the work if done during code generation. It also catches
3789 cases we wouldn't have before cse. */
3792 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3794 rtx dest
, cond
, t_rtx
, f_rtx
;
3796 HOST_WIDE_INT t
, f
, diff
;
3797 enum machine_mode mode
;
3798 rtx target
, subtarget
, tmp
;
3800 mode
= GET_MODE (dest
);
3805 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3806 || (code
== GE
|| code
== GT
))
3808 code
= reverse_condition (code
);
3809 diff
= t
, t
= f
, f
= diff
;
3813 subtarget
= target
= dest
;
3816 target
= gen_lowpart (DImode
, dest
);
3817 if (! no_new_pseudos
)
3818 subtarget
= gen_reg_rtx (DImode
);
3822 /* Below, we must be careful to use copy_rtx on target and subtarget
3823 in intermediate insns, as they may be a subreg rtx, which may not
3826 if (f
== 0 && exact_log2 (diff
) > 0
3827 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3828 viable over a longer latency cmove. On EV5, the E0 slot is a
3829 scarce resource, and on EV4 shift has the same latency as a cmove. */
3830 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3832 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3833 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3835 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3836 GEN_INT (exact_log2 (t
)));
3837 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3839 else if (f
== 0 && t
== -1)
3841 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3842 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3844 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3846 else if (diff
== 1 || diff
== 4 || diff
== 8)
3850 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3851 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3854 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3857 add_op
= GEN_INT (f
);
3858 if (sext_add_operand (add_op
, mode
))
3860 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3862 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3863 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3875 /* Look up the function X_floating library function name for the
3879 alpha_lookup_xfloating_lib_func (code
)
3884 const enum rtx_code code
;
3885 const char *const func
;
3888 static const struct xfloating_op vms_xfloating_ops
[] =
3890 { PLUS
, "OTS$ADD_X" },
3891 { MINUS
, "OTS$SUB_X" },
3892 { MULT
, "OTS$MUL_X" },
3893 { DIV
, "OTS$DIV_X" },
3894 { EQ
, "OTS$EQL_X" },
3895 { NE
, "OTS$NEQ_X" },
3896 { LT
, "OTS$LSS_X" },
3897 { LE
, "OTS$LEQ_X" },
3898 { GT
, "OTS$GTR_X" },
3899 { GE
, "OTS$GEQ_X" },
3900 { FIX
, "OTS$CVTXQ" },
3901 { FLOAT
, "OTS$CVTQX" },
3902 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3903 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3904 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3907 static const struct xfloating_op osf_xfloating_ops
[] =
3909 { PLUS
, "_OtsAddX" },
3910 { MINUS
, "_OtsSubX" },
3911 { MULT
, "_OtsMulX" },
3912 { DIV
, "_OtsDivX" },
3919 { FIX
, "_OtsCvtXQ" },
3920 { FLOAT
, "_OtsCvtQX" },
3921 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3922 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3923 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3926 const struct xfloating_op
*ops
;
3927 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3930 /* How irritating. Nothing to key off for the table. Hardcode
3931 knowledge of the G_floating routines. */
3932 if (TARGET_FLOAT_VAX
)
3934 if (TARGET_ABI_OPEN_VMS
)
3936 if (code
== FLOAT_EXTEND
)
3937 return "OTS$CVT_FLOAT_G_X";
3938 if (code
== FLOAT_TRUNCATE
)
3939 return "OTS$CVT_FLOAT_X_G";
3943 if (code
== FLOAT_EXTEND
)
3944 return "_OtsConvertFloatGX";
3945 if (code
== FLOAT_TRUNCATE
)
3946 return "_OtsConvertFloatXG";
3950 if (TARGET_ABI_OPEN_VMS
)
3951 ops
= vms_xfloating_ops
;
3953 ops
= osf_xfloating_ops
;
3955 for (i
= 0; i
< n
; ++i
)
3956 if (ops
[i
].code
== code
)
3962 /* Most X_floating operations take the rounding mode as an argument.
3963 Compute that here. */
3966 alpha_compute_xfloating_mode_arg (code
, round
)
3968 enum alpha_fp_rounding_mode round
;
3974 case ALPHA_FPRM_NORM
:
3977 case ALPHA_FPRM_MINF
:
3980 case ALPHA_FPRM_CHOP
:
3983 case ALPHA_FPRM_DYN
:
3989 /* XXX For reference, round to +inf is mode = 3. */
3992 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3998 /* Emit an X_floating library function call.
4000 Note that these functions do not follow normal calling conventions:
4001 TFmode arguments are passed in two integer registers (as opposed to
4002 indirect); TFmode return values appear in R16+R17.
4004 FUNC is the function name to call.
4005 TARGET is where the output belongs.
4006 OPERANDS are the inputs.
4007 NOPERANDS is the count of inputs.
4008 EQUIV is the expression equivalent for the function.
4012 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
4019 rtx usage
= NULL_RTX
, tmp
, reg
;
4024 for (i
= 0; i
< noperands
; ++i
)
4026 switch (GET_MODE (operands
[i
]))
4029 reg
= gen_rtx_REG (TFmode
, regno
);
4034 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
4039 if (GET_CODE (operands
[i
]) != CONST_INT
)
4043 reg
= gen_rtx_REG (DImode
, regno
);
4051 emit_move_insn (reg
, operands
[i
]);
4052 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
4055 switch (GET_MODE (target
))
4058 reg
= gen_rtx_REG (TFmode
, 16);
4061 reg
= gen_rtx_REG (DFmode
, 32);
4064 reg
= gen_rtx_REG (DImode
, 0);
4070 tmp
= gen_rtx_MEM (QImode
, init_one_libfunc (func
));
4071 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
4072 const0_rtx
, const0_rtx
));
4073 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
4078 emit_libcall_block (tmp
, target
, reg
, equiv
);
4081 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
4084 alpha_emit_xfloating_arith (code
, operands
)
4090 rtx out_operands
[3];
4092 func
= alpha_lookup_xfloating_lib_func (code
);
4093 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4095 out_operands
[0] = operands
[1];
4096 out_operands
[1] = operands
[2];
4097 out_operands
[2] = GEN_INT (mode
);
4098 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
4099 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
4103 /* Emit an X_floating library function call for a comparison. */
4106 alpha_emit_xfloating_compare (code
, op0
, op1
)
4111 rtx out
, operands
[2];
4113 func
= alpha_lookup_xfloating_lib_func (code
);
4117 out
= gen_reg_rtx (DImode
);
4119 /* ??? Strange mode for equiv because what's actually returned
4120 is -1,0,1, not a proper boolean value. */
4121 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
4122 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
4127 /* Emit an X_floating library function call for a conversion. */
4130 alpha_emit_xfloating_cvt (code
, operands
)
4134 int noperands
= 1, mode
;
4135 rtx out_operands
[2];
4138 func
= alpha_lookup_xfloating_lib_func (code
);
4140 out_operands
[0] = operands
[1];
4145 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
4146 out_operands
[1] = GEN_INT (mode
);
4149 case FLOAT_TRUNCATE
:
4150 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4151 out_operands
[1] = GEN_INT (mode
);
4158 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
4159 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
4163 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
4164 OP[0] into OP[0,1]. Naturally, output operand ordering is
4168 alpha_split_tfmode_pair (operands
)
4171 if (GET_CODE (operands
[1]) == REG
)
4173 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
4174 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
4176 else if (GET_CODE (operands
[1]) == MEM
)
4178 operands
[3] = adjust_address (operands
[1], DImode
, 8);
4179 operands
[2] = adjust_address (operands
[1], DImode
, 0);
4181 else if (operands
[1] == CONST0_RTX (TFmode
))
4182 operands
[2] = operands
[3] = const0_rtx
;
4186 if (GET_CODE (operands
[0]) == REG
)
4188 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
4189 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
4191 else if (GET_CODE (operands
[0]) == MEM
)
4193 operands
[1] = adjust_address (operands
[0], DImode
, 8);
4194 operands
[0] = adjust_address (operands
[0], DImode
, 0);
4200 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4201 op2 is a register containing the sign bit, operation is the
4202 logical operation to be performed. */
4205 alpha_split_tfmode_frobsign (operands
, operation
)
4207 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4209 rtx high_bit
= operands
[2];
4213 alpha_split_tfmode_pair (operands
);
4215 /* Detect three flavors of operand overlap. */
4217 if (rtx_equal_p (operands
[0], operands
[2]))
4219 else if (rtx_equal_p (operands
[1], operands
[2]))
4221 if (rtx_equal_p (operands
[0], high_bit
))
4228 emit_move_insn (operands
[0], operands
[2]);
4230 /* ??? If the destination overlaps both source tf and high_bit, then
4231 assume source tf is dead in its entirety and use the other half
4232 for a scratch register. Otherwise "scratch" is just the proper
4233 destination register. */
4234 scratch
= operands
[move
< 2 ? 1 : 3];
4236 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4240 emit_move_insn (operands
[0], operands
[2]);
4242 emit_move_insn (operands
[1], scratch
);
4246 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4250 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4251 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4252 lda r3,X(r11) lda r3,X+2(r11)
4253 extwl r1,r3,r1 extql r1,r3,r1
4254 extwh r2,r3,r2 extqh r2,r3,r2
4255 or r1.r2.r1 or r1,r2,r1
4258 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4259 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4260 lda r3,X(r11) lda r3,X(r11)
4261 extll r1,r3,r1 extll r1,r3,r1
4262 extlh r2,r3,r2 extlh r2,r3,r2
4263 or r1.r2.r1 addl r1,r2,r1
4265 quad: ldq_u r1,X(r11)
4274 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4276 HOST_WIDE_INT size
, ofs
;
4279 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4280 enum machine_mode mode
;
4282 meml
= gen_reg_rtx (DImode
);
4283 memh
= gen_reg_rtx (DImode
);
4284 addr
= gen_reg_rtx (DImode
);
4285 extl
= gen_reg_rtx (DImode
);
4286 exth
= gen_reg_rtx (DImode
);
4288 mema
= XEXP (mem
, 0);
4289 if (GET_CODE (mema
) == LO_SUM
)
4290 mema
= force_reg (Pmode
, mema
);
4292 /* AND addresses cannot be in any alias set, since they may implicitly
4293 alias surrounding code. Ideally we'd have some alias set that
4294 covered all types except those with alignment 8 or higher. */
4296 tmp
= change_address (mem
, DImode
,
4297 gen_rtx_AND (DImode
,
4298 plus_constant (mema
, ofs
),
4300 set_mem_alias_set (tmp
, 0);
4301 emit_move_insn (meml
, tmp
);
4303 tmp
= change_address (mem
, DImode
,
4304 gen_rtx_AND (DImode
,
4305 plus_constant (mema
, ofs
+ size
- 1),
4307 set_mem_alias_set (tmp
, 0);
4308 emit_move_insn (memh
, tmp
);
4310 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4312 emit_move_insn (addr
, plus_constant (mema
, -1));
4314 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4315 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4317 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4318 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4319 addr
, 1, OPTAB_WIDEN
);
4321 else if (sign
&& size
== 2)
4323 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4325 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4326 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4328 /* We must use tgt here for the target. Alpha-vms port fails if we use
4329 addr for the target, because addr is marked as a pointer and combine
4330 knows that pointers are always sign-extended 32 bit values. */
4331 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4332 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4333 addr
, 1, OPTAB_WIDEN
);
4337 if (WORDS_BIG_ENDIAN
)
4339 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4343 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4348 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4353 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4360 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4364 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4365 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4369 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4374 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4379 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4388 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4389 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4394 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4397 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4400 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4402 HOST_WIDE_INT size
, ofs
;
4404 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4406 dstl
= gen_reg_rtx (DImode
);
4407 dsth
= gen_reg_rtx (DImode
);
4408 insl
= gen_reg_rtx (DImode
);
4409 insh
= gen_reg_rtx (DImode
);
4411 dsta
= XEXP (dst
, 0);
4412 if (GET_CODE (dsta
) == LO_SUM
)
4413 dsta
= force_reg (Pmode
, dsta
);
4415 /* AND addresses cannot be in any alias set, since they may implicitly
4416 alias surrounding code. Ideally we'd have some alias set that
4417 covered all types except those with alignment 8 or higher. */
4419 meml
= change_address (dst
, DImode
,
4420 gen_rtx_AND (DImode
,
4421 plus_constant (dsta
, ofs
),
4423 set_mem_alias_set (meml
, 0);
4425 memh
= change_address (dst
, DImode
,
4426 gen_rtx_AND (DImode
,
4427 plus_constant (dsta
, ofs
+ size
- 1),
4429 set_mem_alias_set (memh
, 0);
4431 emit_move_insn (dsth
, memh
);
4432 emit_move_insn (dstl
, meml
);
4433 if (WORDS_BIG_ENDIAN
)
4435 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4437 if (src
!= const0_rtx
)
4442 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4445 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4448 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4451 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4452 GEN_INT (size
*8), addr
));
4458 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4462 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4463 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4467 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4471 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4475 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4477 if (src
!= const0_rtx
)
4479 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4480 GEN_INT (size
*8), addr
));
4485 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4488 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4491 emit_insn (gen_insql_le (insl
, src
, addr
));
4496 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4501 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4505 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4506 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4510 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4515 if (src
!= const0_rtx
)
4517 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4518 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4521 if (WORDS_BIG_ENDIAN
)
4523 emit_move_insn (meml
, dstl
);
4524 emit_move_insn (memh
, dsth
);
4528 /* Must store high before low for degenerate case of aligned. */
4529 emit_move_insn (memh
, dsth
);
4530 emit_move_insn (meml
, dstl
);
4534 /* The block move code tries to maximize speed by separating loads and
4535 stores at the expense of register pressure: we load all of the data
4536 before we store it back out. There are two secondary effects worth
4537 mentioning, that this speeds copying to/from aligned and unaligned
4538 buffers, and that it makes the code significantly easier to write. */
4540 #define MAX_MOVE_WORDS 8
4542 /* Load an integral number of consecutive unaligned quadwords. */
4545 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4548 HOST_WIDE_INT words
, ofs
;
4550 rtx
const im8
= GEN_INT (-8);
4551 rtx
const i64
= GEN_INT (64);
4552 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4553 rtx sreg
, areg
, tmp
, smema
;
4556 smema
= XEXP (smem
, 0);
4557 if (GET_CODE (smema
) == LO_SUM
)
4558 smema
= force_reg (Pmode
, smema
);
4560 /* Generate all the tmp registers we need. */
4561 for (i
= 0; i
< words
; ++i
)
4563 data_regs
[i
] = out_regs
[i
];
4564 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4566 data_regs
[words
] = gen_reg_rtx (DImode
);
4569 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4571 /* Load up all of the source data. */
4572 for (i
= 0; i
< words
; ++i
)
4574 tmp
= change_address (smem
, DImode
,
4575 gen_rtx_AND (DImode
,
4576 plus_constant (smema
, 8*i
),
4578 set_mem_alias_set (tmp
, 0);
4579 emit_move_insn (data_regs
[i
], tmp
);
4582 tmp
= change_address (smem
, DImode
,
4583 gen_rtx_AND (DImode
,
4584 plus_constant (smema
, 8*words
- 1),
4586 set_mem_alias_set (tmp
, 0);
4587 emit_move_insn (data_regs
[words
], tmp
);
4589 /* Extract the half-word fragments. Unfortunately DEC decided to make
4590 extxh with offset zero a noop instead of zeroing the register, so
4591 we must take care of that edge condition ourselves with cmov. */
4593 sreg
= copy_addr_to_reg (smema
);
4594 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4596 if (WORDS_BIG_ENDIAN
)
4597 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4598 for (i
= 0; i
< words
; ++i
)
4600 if (WORDS_BIG_ENDIAN
)
4602 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4603 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4607 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4608 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4610 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4611 gen_rtx_IF_THEN_ELSE (DImode
,
4612 gen_rtx_EQ (DImode
, areg
,
4614 const0_rtx
, ext_tmps
[i
])));
4617 /* Merge the half-words into whole words. */
4618 for (i
= 0; i
< words
; ++i
)
4620 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4621 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4625 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4626 may be NULL to store zeros. */
4629 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4632 HOST_WIDE_INT words
, ofs
;
4634 rtx
const im8
= GEN_INT (-8);
4635 rtx
const i64
= GEN_INT (64);
4636 rtx ins_tmps
[MAX_MOVE_WORDS
];
4637 rtx st_tmp_1
, st_tmp_2
, dreg
;
4638 rtx st_addr_1
, st_addr_2
, dmema
;
4641 dmema
= XEXP (dmem
, 0);
4642 if (GET_CODE (dmema
) == LO_SUM
)
4643 dmema
= force_reg (Pmode
, dmema
);
4645 /* Generate all the tmp registers we need. */
4646 if (data_regs
!= NULL
)
4647 for (i
= 0; i
< words
; ++i
)
4648 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4649 st_tmp_1
= gen_reg_rtx(DImode
);
4650 st_tmp_2
= gen_reg_rtx(DImode
);
4653 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4655 st_addr_2
= change_address (dmem
, DImode
,
4656 gen_rtx_AND (DImode
,
4657 plus_constant (dmema
, words
*8 - 1),
4659 set_mem_alias_set (st_addr_2
, 0);
4661 st_addr_1
= change_address (dmem
, DImode
,
4662 gen_rtx_AND (DImode
, dmema
, im8
));
4663 set_mem_alias_set (st_addr_1
, 0);
4665 /* Load up the destination end bits. */
4666 emit_move_insn (st_tmp_2
, st_addr_2
);
4667 emit_move_insn (st_tmp_1
, st_addr_1
);
4669 /* Shift the input data into place. */
4670 dreg
= copy_addr_to_reg (dmema
);
4671 if (WORDS_BIG_ENDIAN
)
4672 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4673 if (data_regs
!= NULL
)
4675 for (i
= words
-1; i
>= 0; --i
)
4677 if (WORDS_BIG_ENDIAN
)
4679 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4680 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4684 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4685 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4688 for (i
= words
-1; i
> 0; --i
)
4690 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4691 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4696 /* Split and merge the ends with the destination data. */
4697 if (WORDS_BIG_ENDIAN
)
4699 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4700 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4704 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4705 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4708 if (data_regs
!= NULL
)
4710 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4711 st_tmp_2
, 1, OPTAB_WIDEN
);
4712 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4713 st_tmp_1
, 1, OPTAB_WIDEN
);
4717 if (WORDS_BIG_ENDIAN
)
4718 emit_move_insn (st_addr_1
, st_tmp_1
);
4720 emit_move_insn (st_addr_2
, st_tmp_2
);
4721 for (i
= words
-1; i
> 0; --i
)
4723 rtx tmp
= change_address (dmem
, DImode
,
4724 gen_rtx_AND (DImode
,
4725 plus_constant(dmema
,
4726 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4728 set_mem_alias_set (tmp
, 0);
4729 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4731 if (WORDS_BIG_ENDIAN
)
4732 emit_move_insn (st_addr_2
, st_tmp_2
);
4734 emit_move_insn (st_addr_1
, st_tmp_1
);
4738 /* Expand string/block move operations.
4740 operands[0] is the pointer to the destination.
4741 operands[1] is the pointer to the source.
4742 operands[2] is the number of bytes to move.
4743 operands[3] is the alignment. */
4746 alpha_expand_block_move (operands
)
4749 rtx bytes_rtx
= operands
[2];
4750 rtx align_rtx
= operands
[3];
4751 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4752 HOST_WIDE_INT bytes
= orig_bytes
;
4753 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4754 HOST_WIDE_INT dst_align
= src_align
;
4755 rtx orig_src
= operands
[1];
4756 rtx orig_dst
= operands
[0];
4757 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4759 unsigned int i
, words
, ofs
, nregs
= 0;
4761 if (orig_bytes
<= 0)
4763 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4766 /* Look for additional alignment information from recorded register info. */
4768 tmp
= XEXP (orig_src
, 0);
4769 if (GET_CODE (tmp
) == REG
)
4770 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4771 else if (GET_CODE (tmp
) == PLUS
4772 && GET_CODE (XEXP (tmp
, 0)) == REG
4773 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4775 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4776 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4780 if (a
>= 64 && c
% 8 == 0)
4782 else if (a
>= 32 && c
% 4 == 0)
4784 else if (a
>= 16 && c
% 2 == 0)
4789 tmp
= XEXP (orig_dst
, 0);
4790 if (GET_CODE (tmp
) == REG
)
4791 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4792 else if (GET_CODE (tmp
) == PLUS
4793 && GET_CODE (XEXP (tmp
, 0)) == REG
4794 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4796 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4797 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4801 if (a
>= 64 && c
% 8 == 0)
4803 else if (a
>= 32 && c
% 4 == 0)
4805 else if (a
>= 16 && c
% 2 == 0)
4810 /* Load the entire block into registers. */
4811 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4813 enum machine_mode mode
;
4815 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4817 /* Don't use the existing register if we're reading more than
4818 is held in the register. Nor if there is not a mode that
4819 handles the exact size. */
4820 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4822 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4826 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4827 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4831 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4836 /* No appropriate mode; fall back on memory. */
4837 orig_src
= replace_equiv_address (orig_src
,
4838 copy_addr_to_reg (XEXP (orig_src
, 0)));
4839 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4843 if (src_align
>= 64 && bytes
>= 8)
4847 for (i
= 0; i
< words
; ++i
)
4848 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4850 for (i
= 0; i
< words
; ++i
)
4851 emit_move_insn (data_regs
[nregs
+ i
],
4852 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4859 if (src_align
>= 32 && bytes
>= 4)
4863 for (i
= 0; i
< words
; ++i
)
4864 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4866 for (i
= 0; i
< words
; ++i
)
4867 emit_move_insn (data_regs
[nregs
+ i
],
4868 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4879 for (i
= 0; i
< words
+1; ++i
)
4880 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4882 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4890 if (! TARGET_BWX
&& bytes
>= 4)
4892 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4893 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4900 if (src_align
>= 16)
4903 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4904 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4907 } while (bytes
>= 2);
4909 else if (! TARGET_BWX
)
4911 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4912 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4920 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4921 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4928 if (nregs
> ARRAY_SIZE (data_regs
))
4931 /* Now save it back out again. */
4935 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4937 enum machine_mode mode
;
4938 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4940 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4941 if (GET_MODE (tmp
) == mode
)
4945 emit_move_insn (tmp
, data_regs
[0]);
4950 else if (nregs
== 2 && mode
== TImode
)
4952 /* Undo the subregging done above when copying between
4953 two TImode registers. */
4954 if (GET_CODE (data_regs
[0]) == SUBREG
4955 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4956 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4962 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4963 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4967 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4968 data_regs
[1], NULL_RTX
);
4976 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4977 /* ??? Optimize mode < dst_mode with strict_low_part. */
4979 /* No appropriate mode; fall back on memory. We can speed things
4980 up by recognizing extra alignment information. */
4981 orig_dst
= replace_equiv_address (orig_dst
,
4982 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4983 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4986 /* Write out the data in whatever chunks reading the source allowed. */
4987 if (dst_align
>= 64)
4989 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4991 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4998 if (dst_align
>= 32)
5000 /* If the source has remaining DImode regs, write them out in
5002 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5004 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
5005 NULL_RTX
, 1, OPTAB_WIDEN
);
5007 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5008 gen_lowpart (SImode
, data_regs
[i
]));
5009 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
5010 gen_lowpart (SImode
, tmp
));
5015 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5017 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5024 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5026 /* Write out a remaining block of words using unaligned methods. */
5028 for (words
= 1; i
+ words
< nregs
; words
++)
5029 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
5033 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
5035 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
5042 /* Due to the above, this won't be aligned. */
5043 /* ??? If we have more than one of these, consider constructing full
5044 words in registers and using alpha_expand_unaligned_store_words. */
5045 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5047 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
5052 if (dst_align
>= 16)
5053 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5055 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
5060 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5062 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
5067 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
5069 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
5083 alpha_expand_block_clear (operands
)
5086 rtx bytes_rtx
= operands
[1];
5087 rtx align_rtx
= operands
[2];
5088 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
5089 HOST_WIDE_INT bytes
= orig_bytes
;
5090 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
5091 HOST_WIDE_INT alignofs
= 0;
5092 rtx orig_dst
= operands
[0];
5094 int i
, words
, ofs
= 0;
5096 if (orig_bytes
<= 0)
5098 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
5101 /* Look for stricter alignment. */
5102 tmp
= XEXP (orig_dst
, 0);
5103 if (GET_CODE (tmp
) == REG
)
5104 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
5105 else if (GET_CODE (tmp
) == PLUS
5106 && GET_CODE (XEXP (tmp
, 0)) == REG
5107 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
5109 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
5110 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
5115 align
= a
, alignofs
= 8 - c
% 8;
5117 align
= a
, alignofs
= 4 - c
% 4;
5119 align
= a
, alignofs
= 2 - c
% 2;
5122 else if (GET_CODE (tmp
) == ADDRESSOF
)
5124 enum machine_mode mode
;
5126 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
5127 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
5129 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
5133 /* No appropriate mode; fall back on memory. */
5134 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
5135 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
5138 /* Handle an unaligned prefix first. */
5142 #if HOST_BITS_PER_WIDE_INT >= 64
5143 /* Given that alignofs is bounded by align, the only time BWX could
5144 generate three stores is for a 7 byte fill. Prefer two individual
5145 stores over a load/mask/store sequence. */
5146 if ((!TARGET_BWX
|| alignofs
== 7)
5148 && !(alignofs
== 4 && bytes
>= 4))
5150 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
5151 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
5155 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
5156 set_mem_alias_set (mem
, 0);
5158 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
5159 if (bytes
< alignofs
)
5161 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
5172 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
5173 NULL_RTX
, 1, OPTAB_WIDEN
);
5175 emit_move_insn (mem
, tmp
);
5179 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
5181 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5186 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
5188 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
5193 if (alignofs
== 4 && bytes
>= 4)
5195 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5201 /* If we've not used the extra lead alignment information by now,
5202 we won't be able to. Downgrade align to match what's left over. */
5205 alignofs
= alignofs
& -alignofs
;
5206 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5210 /* Handle a block of contiguous long-words. */
5212 if (align
>= 64 && bytes
>= 8)
5216 for (i
= 0; i
< words
; ++i
)
5217 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5224 /* If the block is large and appropriately aligned, emit a single
5225 store followed by a sequence of stq_u insns. */
5227 if (align
>= 32 && bytes
> 16)
5231 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5235 orig_dsta
= XEXP (orig_dst
, 0);
5236 if (GET_CODE (orig_dsta
) == LO_SUM
)
5237 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5240 for (i
= 0; i
< words
; ++i
)
5243 = change_address (orig_dst
, DImode
,
5244 gen_rtx_AND (DImode
,
5245 plus_constant (orig_dsta
, ofs
+ i
*8),
5247 set_mem_alias_set (mem
, 0);
5248 emit_move_insn (mem
, const0_rtx
);
5251 /* Depending on the alignment, the first stq_u may have overlapped
5252 with the initial stl, which means that the last stq_u didn't
5253 write as much as it would appear. Leave those questionable bytes
5255 bytes
-= words
* 8 - 4;
5256 ofs
+= words
* 8 - 4;
5259 /* Handle a smaller block of aligned words. */
5261 if ((align
>= 64 && bytes
== 4)
5262 || (align
== 32 && bytes
>= 4))
5266 for (i
= 0; i
< words
; ++i
)
5267 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5274 /* An unaligned block uses stq_u stores for as many as possible. */
5280 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5286 /* Next clean up any trailing pieces. */
5288 #if HOST_BITS_PER_WIDE_INT >= 64
5289 /* Count the number of bits in BYTES for which aligned stores could
5292 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5296 /* If we have appropriate alignment (and it wouldn't take too many
5297 instructions otherwise), mask out the bytes we need. */
5298 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5305 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5306 set_mem_alias_set (mem
, 0);
5308 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5310 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5311 NULL_RTX
, 1, OPTAB_WIDEN
);
5313 emit_move_insn (mem
, tmp
);
5316 else if (align
>= 32 && bytes
< 4)
5321 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5322 set_mem_alias_set (mem
, 0);
5324 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5326 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5327 NULL_RTX
, 1, OPTAB_WIDEN
);
5329 emit_move_insn (mem
, tmp
);
5335 if (!TARGET_BWX
&& bytes
>= 4)
5337 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5347 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5351 } while (bytes
>= 2);
5353 else if (! TARGET_BWX
)
5355 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5363 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5371 /* Returns a mask so that zap(x, value) == x & mask. */
5374 alpha_expand_zap_mask (value
)
5375 HOST_WIDE_INT value
;
5380 if (HOST_BITS_PER_WIDE_INT
>= 64)
5382 HOST_WIDE_INT mask
= 0;
5384 for (i
= 7; i
>= 0; --i
)
5387 if (!((value
>> i
) & 1))
5391 result
= gen_int_mode (mask
, DImode
);
5393 else if (HOST_BITS_PER_WIDE_INT
== 32)
5395 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5397 for (i
= 7; i
>= 4; --i
)
5400 if (!((value
>> i
) & 1))
5404 for (i
= 3; i
>= 0; --i
)
5407 if (!((value
>> i
) & 1))
5411 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5420 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5421 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5422 enum machine_mode mode
;
5425 op0
= gen_lowpart (mode
, op0
);
5427 if (op1
== const0_rtx
)
5428 op1
= CONST0_RTX (mode
);
5430 op1
= gen_lowpart (mode
, op1
);
5432 if (op2
== const0_rtx
)
5433 op2
= CONST0_RTX (mode
);
5435 op2
= gen_lowpart (mode
, op2
);
5437 emit_insn ((*gen
) (op0
, op1
, op2
));
5440 /* Adjust the cost of a scheduling dependency. Return the new cost of
5441 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5444 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5450 enum attr_type insn_type
, dep_insn_type
;
5452 /* If the dependence is an anti-dependence, there is no cost. For an
5453 output dependence, there is sometimes a cost, but it doesn't seem
5454 worth handling those few cases. */
5455 if (REG_NOTE_KIND (link
) != 0)
5458 /* If we can't recognize the insns, we can't really do anything. */
5459 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5462 insn_type
= get_attr_type (insn
);
5463 dep_insn_type
= get_attr_type (dep_insn
);
5465 /* Bring in the user-defined memory latency. */
5466 if (dep_insn_type
== TYPE_ILD
5467 || dep_insn_type
== TYPE_FLD
5468 || dep_insn_type
== TYPE_LDSYM
)
5469 cost
+= alpha_memory_latency
-1;
5471 /* Everything else handled in DFA bypasses now. */
5476 /* The number of instructions that can be issued per cycle. */
5481 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5485 alpha_use_dfa_pipeline_interface ()
5490 /* How many alternative schedules to try. This should be as wide as the
5491 scheduling freedom in the DFA, but no wider. Making this value too
5492 large results extra work for the scheduler.
5494 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5495 alternative schedules. For EV5, we can choose between E0/E1 and
5496 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5499 alpha_multipass_dfa_lookahead ()
5501 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5504 /* Machine-specific function data. */
5506 struct machine_function
GTY(())
5509 /* List of call information words for calls from this function. */
5510 struct rtx_def
*first_ciw
;
5511 struct rtx_def
*last_ciw
;
5514 /* List of deferred case vectors. */
5515 struct rtx_def
*addr_list
;
5518 const char *some_ld_name
;
5521 /* How to allocate a 'struct machine_function'. */
5523 static struct machine_function
*
5524 alpha_init_machine_status ()
5526 return ((struct machine_function
*)
5527 ggc_alloc_cleared (sizeof (struct machine_function
)));
5530 /* Functions to save and restore alpha_return_addr_rtx. */
5532 /* Start the ball rolling with RETURN_ADDR_RTX. */
5535 alpha_return_addr (count
, frame
)
5537 rtx frame ATTRIBUTE_UNUSED
;
5542 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5545 /* Return or create a pseudo containing the gp value for the current
5546 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5549 alpha_gp_save_rtx ()
5551 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5552 if (GET_CODE (r
) != MEM
)
5553 r
= gen_mem_addressof (r
, NULL_TREE
, /*rescan=*/true);
5558 alpha_ra_ever_killed ()
5562 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5563 return regs_ever_live
[REG_RA
];
5565 push_topmost_sequence ();
5567 pop_topmost_sequence ();
5569 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5573 /* Return the trap mode suffix applicable to the current
5574 instruction, or NULL. */
5577 get_trap_mode_suffix ()
5579 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5583 case TRAP_SUFFIX_NONE
:
5586 case TRAP_SUFFIX_SU
:
5587 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5591 case TRAP_SUFFIX_SUI
:
5592 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5596 case TRAP_SUFFIX_V_SV
:
5604 case ALPHA_FPTM_SUI
:
5609 case TRAP_SUFFIX_V_SV_SVI
:
5618 case ALPHA_FPTM_SUI
:
5623 case TRAP_SUFFIX_U_SU_SUI
:
5632 case ALPHA_FPTM_SUI
:
5640 /* Return the rounding mode suffix applicable to the current
5641 instruction, or NULL. */
5644 get_round_mode_suffix ()
5646 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5650 case ROUND_SUFFIX_NONE
:
5652 case ROUND_SUFFIX_NORMAL
:
5655 case ALPHA_FPRM_NORM
:
5657 case ALPHA_FPRM_MINF
:
5659 case ALPHA_FPRM_CHOP
:
5661 case ALPHA_FPRM_DYN
:
5666 case ROUND_SUFFIX_C
:
5672 /* Locate some local-dynamic symbol still in use by this function
5673 so that we can print its name in some movdi_er_tlsldm pattern. */
5676 get_some_local_dynamic_name ()
5680 if (cfun
->machine
->some_ld_name
)
5681 return cfun
->machine
->some_ld_name
;
5683 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5685 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5686 return cfun
->machine
->some_ld_name
;
5692 get_some_local_dynamic_name_1 (px
, data
)
5694 void *data ATTRIBUTE_UNUSED
;
5698 if (GET_CODE (x
) == SYMBOL_REF
5699 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5701 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5708 /* Print an operand. Recognize special options, documented below. */
5711 print_operand (file
, x
, code
)
5721 /* Print the assembler name of the current function. */
5722 assemble_name (file
, alpha_fnname
);
5726 assemble_name (file
, get_some_local_dynamic_name ());
5731 const char *trap
= get_trap_mode_suffix ();
5732 const char *round
= get_round_mode_suffix ();
5735 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5736 (trap
? trap
: ""), (round
? round
: ""));
5741 /* Generates single precision instruction suffix. */
5742 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5746 /* Generates double precision instruction suffix. */
5747 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5751 /* Generates a nop after a noreturn call at the very end of the
5753 if (next_real_insn (current_output_insn
) == 0)
5754 fprintf (file
, "\n\tnop");
5758 if (alpha_this_literal_sequence_number
== 0)
5759 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5760 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5764 if (alpha_this_gpdisp_sequence_number
== 0)
5765 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5766 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5770 if (GET_CODE (x
) == HIGH
)
5771 output_addr_const (file
, XEXP (x
, 0));
5773 output_operand_lossage ("invalid %%H value");
5780 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5782 x
= XVECEXP (x
, 0, 0);
5783 lituse
= "lituse_tlsgd";
5785 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5787 x
= XVECEXP (x
, 0, 0);
5788 lituse
= "lituse_tlsldm";
5790 else if (GET_CODE (x
) == CONST_INT
)
5791 lituse
= "lituse_jsr";
5794 output_operand_lossage ("invalid %%J value");
5798 if (x
!= const0_rtx
)
5799 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5804 /* If this operand is the constant zero, write it as "$31". */
5805 if (GET_CODE (x
) == REG
)
5806 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5807 else if (x
== CONST0_RTX (GET_MODE (x
)))
5808 fprintf (file
, "$31");
5810 output_operand_lossage ("invalid %%r value");
5814 /* Similar, but for floating-point. */
5815 if (GET_CODE (x
) == REG
)
5816 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5817 else if (x
== CONST0_RTX (GET_MODE (x
)))
5818 fprintf (file
, "$f31");
5820 output_operand_lossage ("invalid %%R value");
5824 /* Write the 1's complement of a constant. */
5825 if (GET_CODE (x
) != CONST_INT
)
5826 output_operand_lossage ("invalid %%N value");
5828 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5832 /* Write 1 << C, for a constant C. */
5833 if (GET_CODE (x
) != CONST_INT
)
5834 output_operand_lossage ("invalid %%P value");
5836 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5840 /* Write the high-order 16 bits of a constant, sign-extended. */
5841 if (GET_CODE (x
) != CONST_INT
)
5842 output_operand_lossage ("invalid %%h value");
5844 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5848 /* Write the low-order 16 bits of a constant, sign-extended. */
5849 if (GET_CODE (x
) != CONST_INT
)
5850 output_operand_lossage ("invalid %%L value");
5852 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5853 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5857 /* Write mask for ZAP insn. */
5858 if (GET_CODE (x
) == CONST_DOUBLE
)
5860 HOST_WIDE_INT mask
= 0;
5861 HOST_WIDE_INT value
;
5863 value
= CONST_DOUBLE_LOW (x
);
5864 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5869 value
= CONST_DOUBLE_HIGH (x
);
5870 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5873 mask
|= (1 << (i
+ sizeof (int)));
5875 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5878 else if (GET_CODE (x
) == CONST_INT
)
5880 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5882 for (i
= 0; i
< 8; i
++, value
>>= 8)
5886 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5889 output_operand_lossage ("invalid %%m value");
5893 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5894 if (GET_CODE (x
) != CONST_INT
5895 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5896 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5897 output_operand_lossage ("invalid %%M value");
5899 fprintf (file
, "%s",
5900 (INTVAL (x
) == 8 ? "b"
5901 : INTVAL (x
) == 16 ? "w"
5902 : INTVAL (x
) == 32 ? "l"
5907 /* Similar, except do it from the mask. */
5908 if (GET_CODE (x
) == CONST_INT
)
5910 HOST_WIDE_INT value
= INTVAL (x
);
5917 if (value
== 0xffff)
5922 if (value
== 0xffffffff)
5933 else if (HOST_BITS_PER_WIDE_INT
== 32
5934 && GET_CODE (x
) == CONST_DOUBLE
5935 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5936 && CONST_DOUBLE_HIGH (x
) == 0)
5941 output_operand_lossage ("invalid %%U value");
5945 /* Write the constant value divided by 8 for little-endian mode or
5946 (56 - value) / 8 for big-endian mode. */
5948 if (GET_CODE (x
) != CONST_INT
5949 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5952 || (INTVAL (x
) & 7) != 0)
5953 output_operand_lossage ("invalid %%s value");
5955 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5957 ? (56 - INTVAL (x
)) / 8
5962 /* Same, except compute (64 - c) / 8 */
5964 if (GET_CODE (x
) != CONST_INT
5965 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5966 && (INTVAL (x
) & 7) != 8)
5967 output_operand_lossage ("invalid %%s value");
5969 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5974 /* On Unicos/Mk systems: use a DEX expression if the symbol
5975 clashes with a register name. */
5976 int dex
= unicosmk_need_dex (x
);
5978 fprintf (file
, "DEX(%d)", dex
);
5980 output_addr_const (file
, x
);
5984 case 'C': case 'D': case 'c': case 'd':
5985 /* Write out comparison name. */
5987 enum rtx_code c
= GET_CODE (x
);
5989 if (GET_RTX_CLASS (c
) != '<')
5990 output_operand_lossage ("invalid %%C value");
5992 else if (code
== 'D')
5993 c
= reverse_condition (c
);
5994 else if (code
== 'c')
5995 c
= swap_condition (c
);
5996 else if (code
== 'd')
5997 c
= swap_condition (reverse_condition (c
));
6000 fprintf (file
, "ule");
6002 fprintf (file
, "ult");
6003 else if (c
== UNORDERED
)
6004 fprintf (file
, "un");
6006 fprintf (file
, "%s", GET_RTX_NAME (c
));
6011 /* Write the divide or modulus operator. */
6012 switch (GET_CODE (x
))
6015 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
6018 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
6021 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
6024 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
6027 output_operand_lossage ("invalid %%E value");
6033 /* Write "_u" for unaligned access. */
6034 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
6035 fprintf (file
, "_u");
6039 if (GET_CODE (x
) == REG
)
6040 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
6041 else if (GET_CODE (x
) == MEM
)
6042 output_address (XEXP (x
, 0));
6043 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6045 switch (XINT (XEXP (x
, 0), 1))
6049 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
6052 output_operand_lossage ("unknown relocation unspec");
6057 output_addr_const (file
, x
);
6061 output_operand_lossage ("invalid %%xn code");
6066 print_operand_address (file
, addr
)
6071 HOST_WIDE_INT offset
= 0;
6073 if (GET_CODE (addr
) == AND
)
6074 addr
= XEXP (addr
, 0);
6076 if (GET_CODE (addr
) == PLUS
6077 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
6079 offset
= INTVAL (XEXP (addr
, 1));
6080 addr
= XEXP (addr
, 0);
6083 if (GET_CODE (addr
) == LO_SUM
)
6085 const char *reloc16
, *reloclo
;
6086 rtx op1
= XEXP (addr
, 1);
6088 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
6090 op1
= XEXP (op1
, 0);
6091 switch (XINT (op1
, 1))
6095 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
6099 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
6102 output_operand_lossage ("unknown relocation unspec");
6106 output_addr_const (file
, XVECEXP (op1
, 0, 0));
6111 reloclo
= "gprellow";
6112 output_addr_const (file
, op1
);
6116 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
6118 addr
= XEXP (addr
, 0);
6119 if (GET_CODE (addr
) == REG
)
6120 basereg
= REGNO (addr
);
6121 else if (GET_CODE (addr
) == SUBREG
6122 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6123 basereg
= subreg_regno (addr
);
6127 fprintf (file
, "($%d)\t\t!%s", basereg
,
6128 (basereg
== 29 ? reloc16
: reloclo
));
6132 if (GET_CODE (addr
) == REG
)
6133 basereg
= REGNO (addr
);
6134 else if (GET_CODE (addr
) == SUBREG
6135 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6136 basereg
= subreg_regno (addr
);
6137 else if (GET_CODE (addr
) == CONST_INT
)
6138 offset
= INTVAL (addr
);
6140 #if TARGET_ABI_OPEN_VMS
6141 else if (GET_CODE (addr
) == SYMBOL_REF
)
6143 fprintf (file
, "%s", XSTR (addr
, 0));
6146 else if (GET_CODE (addr
) == CONST
6147 && GET_CODE (XEXP (addr
, 0)) == PLUS
6148 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
6150 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
6151 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
6152 INTVAL (XEXP (XEXP (addr
, 0), 1)));
6160 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
6163 /* Emit RTL insns to initialize the variable parts of a trampoline at
6164 TRAMP. FNADDR is an RTX for the address of the function's pure
6165 code. CXT is an RTX for the static chain value for the function.
6167 The three offset parameters are for the individual template's
6168 layout. A JMPOFS < 0 indicates that the trampoline does not
6169 contain instructions at all.
6171 We assume here that a function will be called many more times than
6172 its address is taken (e.g., it might be passed to qsort), so we
6173 take the trouble to initialize the "hint" field in the JMP insn.
6174 Note that the hint field is PC (new) + 4 * bits 13:0. */
6177 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
6178 rtx tramp
, fnaddr
, cxt
;
6179 int fnofs
, cxtofs
, jmpofs
;
6181 rtx temp
, temp1
, addr
;
6182 /* VMS really uses DImode pointers in memory at this point. */
6183 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
6185 #ifdef POINTERS_EXTEND_UNSIGNED
6186 fnaddr
= convert_memory_address (mode
, fnaddr
);
6187 cxt
= convert_memory_address (mode
, cxt
);
6190 /* Store function address and CXT. */
6191 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
6192 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
6193 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
6194 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
6196 /* This has been disabled since the hint only has a 32k range, and in
6197 no existing OS is the stack within 32k of the text segment. */
6198 if (0 && jmpofs
>= 0)
6200 /* Compute hint value. */
6201 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
6202 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
6204 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
6205 build_int_2 (2, 0), NULL_RTX
, 1);
6206 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
6207 GEN_INT (0x3fff), 0);
6209 /* Merge in the hint. */
6210 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
6211 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
6212 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
6213 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
6215 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
6218 #ifdef TRANSFER_FROM_TRAMPOLINE
6219 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
6220 0, VOIDmode
, 1, tramp
, Pmode
);
6224 emit_insn (gen_imb ());
6227 /* Determine where to put an argument to a function.
6228 Value is zero to push the argument on the stack,
6229 or a hard register in which to store the argument.
6231 MODE is the argument's machine mode.
6232 TYPE is the data type of the argument (as a tree).
6233 This is null for libcalls where that information may
6235 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6236 the preceding args and about the function being called.
6237 NAMED is nonzero if this argument is a named parameter
6238 (otherwise it is an extra parameter matching an ellipsis).
6240 On Alpha the first 6 words of args are normally in registers
6241 and the rest are pushed. */
6244 function_arg (cum
, mode
, type
, named
)
6245 CUMULATIVE_ARGS cum
;
6246 enum machine_mode mode
;
6248 int named ATTRIBUTE_UNUSED
;
6253 /* Set up defaults for FP operands passed in FP registers, and
6254 integral operands passed in integer registers. */
6256 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6257 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6262 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6263 the three platforms, so we can't avoid conditional compilation. */
6264 #if TARGET_ABI_OPEN_VMS
6266 if (mode
== VOIDmode
)
6267 return alpha_arg_info_reg_val (cum
);
6269 num_args
= cum
.num_args
;
6270 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6274 #if TARGET_ABI_UNICOSMK
6278 /* If this is the last argument, generate the call info word (CIW). */
6279 /* ??? We don't include the caller's line number in the CIW because
6280 I don't know how to determine it if debug infos are turned off. */
6281 if (mode
== VOIDmode
)
6290 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6291 if (cum
.reg_args_type
[i
])
6292 lo
|= (1 << (7 - i
));
6294 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6297 lo
|= cum
.num_reg_words
;
6299 #if HOST_BITS_PER_WIDE_INT == 32
6300 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6302 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6303 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6306 ciw
= immed_double_const (lo
, hi
, DImode
);
6308 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6309 UNSPEC_UMK_LOAD_CIW
);
6312 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6313 num_args
= cum
.num_reg_words
;
6314 if (MUST_PASS_IN_STACK (mode
, type
)
6315 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6317 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6321 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6322 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6324 /* The argument fits in two registers. Note that we still need to
6325 reserve a register for empty structures. */
6329 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6332 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6333 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6334 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6344 /* VOID is passed as a special flag for "last argument". */
6345 if (type
== void_type_node
)
6347 else if (MUST_PASS_IN_STACK (mode
, type
))
6349 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6352 #endif /* TARGET_ABI_UNICOSMK */
6353 #endif /* TARGET_ABI_OPEN_VMS */
6355 return gen_rtx_REG (mode
, num_args
+ basereg
);
6359 alpha_build_va_list ()
6361 tree base
, ofs
, record
, type_decl
;
6363 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6364 return ptr_type_node
;
6366 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6367 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6368 TREE_CHAIN (record
) = type_decl
;
6369 TYPE_NAME (record
) = type_decl
;
6371 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6373 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6375 DECL_FIELD_CONTEXT (ofs
) = record
;
6377 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6379 DECL_FIELD_CONTEXT (base
) = record
;
6380 TREE_CHAIN (base
) = ofs
;
6382 TYPE_FIELDS (record
) = base
;
6383 layout_type (record
);
6388 /* Perform any needed actions needed for a function that is receiving a
6389 variable number of arguments.
6391 On the Alpha, we allocate space for all 12 arg registers, but only
6392 push those that are remaining. However, if NO registers need to be
6393 saved, don't allocate any space. This is not only because we won't
6394 need the space, but because AP includes the current_pretend_args_size
6395 and we don't want to mess up any ap-relative addresses already made.
6397 If we are not to use the floating-point registers, save the integer
6398 registers where we would put the floating-point registers. This is
6399 not the most efficient way to implement varargs with just one register
6400 class, but it isn't worth doing anything more efficient in this rare
6405 alpha_setup_incoming_varargs(cum
, mode
, type
, pretend_size
, no_rtl
)
6406 CUMULATIVE_ARGS cum
;
6407 enum machine_mode mode ATTRIBUTE_UNUSED
;
6408 tree type ATTRIBUTE_UNUSED
;
6417 int set
= get_varargs_alias_set ();
6420 tmp
= gen_rtx_MEM (BLKmode
,
6421 plus_constant (virtual_incoming_args_rtx
,
6422 (cum
+ 6) * UNITS_PER_WORD
));
6423 set_mem_alias_set (tmp
, set
);
6424 move_block_from_reg (16 + cum
, tmp
, 6 - cum
);
6426 tmp
= gen_rtx_MEM (BLKmode
,
6427 plus_constant (virtual_incoming_args_rtx
,
6428 cum
* UNITS_PER_WORD
));
6429 set_mem_alias_set (tmp
, set
);
6430 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
6433 *pretend_size
= 12 * UNITS_PER_WORD
;
6438 alpha_va_start (valist
, nextarg
)
6440 rtx nextarg ATTRIBUTE_UNUSED
;
6442 HOST_WIDE_INT offset
;
6443 tree t
, offset_field
, base_field
;
6445 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6448 if (TARGET_ABI_UNICOSMK
)
6449 std_expand_builtin_va_start (valist
, nextarg
);
6451 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6452 up by 48, storing fp arg registers in the first 48 bytes, and the
6453 integer arg registers in the next 48 bytes. This is only done,
6454 however, if any integer registers need to be stored.
6456 If no integer registers need be stored, then we must subtract 48
6457 in order to account for the integer arg registers which are counted
6458 in argsize above, but which are not actually stored on the stack.
6459 Must further be careful here about structures straddling the last
6460 integer argument register; that futzes with pretend_args_size,
6461 which changes the meaning of AP. */
6464 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6466 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6468 if (TARGET_ABI_OPEN_VMS
)
6470 nextarg
= plus_constant (nextarg
, offset
);
6471 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6472 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6473 make_tree (ptr_type_node
, nextarg
));
6474 TREE_SIDE_EFFECTS (t
) = 1;
6476 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6480 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6481 offset_field
= TREE_CHAIN (base_field
);
6483 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6484 valist
, base_field
);
6485 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6486 valist
, offset_field
);
6488 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6489 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6490 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6491 TREE_SIDE_EFFECTS (t
) = 1;
6492 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6494 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6495 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6496 TREE_SIDE_EFFECTS (t
) = 1;
6497 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6502 alpha_va_arg (valist
, type
)
6506 tree t
, type_size
, rounded_size
;
6507 tree offset_field
, base_field
, addr_tree
, addend
;
6508 tree wide_type
, wide_ofs
;
6511 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6512 return std_expand_builtin_va_arg (valist
, type
);
6514 if (type
== error_mark_node
6515 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6516 || TREE_OVERFLOW (type_size
))
6517 rounded_size
= size_zero_node
;
6519 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6520 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6521 fold (build (PLUS_EXPR
, sizetype
,
6527 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6528 offset_field
= TREE_CHAIN (base_field
);
6530 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6531 valist
, base_field
);
6532 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6533 valist
, offset_field
);
6535 /* If the type could not be passed in registers, skip the block
6536 reserved for the registers. */
6537 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6539 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6540 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6541 offset_field
, build_int_2 (6*8, 0)));
6542 TREE_SIDE_EFFECTS (t
) = 1;
6543 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6546 wide_type
= make_signed_type (64);
6547 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6551 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6554 rounded_size
= size_int (UNITS_PER_WORD
);
6556 else if (FLOAT_TYPE_P (type
))
6558 tree fpaddend
, cond
;
6560 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6561 addend
, build_int_2 (-6*8, 0)));
6563 cond
= fold (build (LT_EXPR
, integer_type_node
,
6564 wide_ofs
, build_int_2 (6*8, 0)));
6566 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6570 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6571 base_field
, addend
);
6573 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6574 addr
= copy_to_reg (addr
);
6576 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6577 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6578 offset_field
, rounded_size
));
6579 TREE_SIDE_EFFECTS (t
) = 1;
6580 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6584 addr
= force_reg (Pmode
, addr
);
6585 addr
= gen_rtx_MEM (Pmode
, addr
);
6595 ALPHA_BUILTIN_CMPBGE
,
6596 ALPHA_BUILTIN_EXTBL
,
6597 ALPHA_BUILTIN_EXTWL
,
6598 ALPHA_BUILTIN_EXTLL
,
6599 ALPHA_BUILTIN_EXTQL
,
6600 ALPHA_BUILTIN_EXTWH
,
6601 ALPHA_BUILTIN_EXTLH
,
6602 ALPHA_BUILTIN_EXTQH
,
6603 ALPHA_BUILTIN_INSBL
,
6604 ALPHA_BUILTIN_INSWL
,
6605 ALPHA_BUILTIN_INSLL
,
6606 ALPHA_BUILTIN_INSQL
,
6607 ALPHA_BUILTIN_INSWH
,
6608 ALPHA_BUILTIN_INSLH
,
6609 ALPHA_BUILTIN_INSQH
,
6610 ALPHA_BUILTIN_MSKBL
,
6611 ALPHA_BUILTIN_MSKWL
,
6612 ALPHA_BUILTIN_MSKLL
,
6613 ALPHA_BUILTIN_MSKQL
,
6614 ALPHA_BUILTIN_MSKWH
,
6615 ALPHA_BUILTIN_MSKLH
,
6616 ALPHA_BUILTIN_MSKQH
,
6617 ALPHA_BUILTIN_UMULH
,
6619 ALPHA_BUILTIN_ZAPNOT
,
6620 ALPHA_BUILTIN_AMASK
,
6621 ALPHA_BUILTIN_IMPLVER
,
6623 ALPHA_BUILTIN_THREAD_POINTER
,
6624 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6627 ALPHA_BUILTIN_MINUB8
,
6628 ALPHA_BUILTIN_MINSB8
,
6629 ALPHA_BUILTIN_MINUW4
,
6630 ALPHA_BUILTIN_MINSW4
,
6631 ALPHA_BUILTIN_MAXUB8
,
6632 ALPHA_BUILTIN_MAXSB8
,
6633 ALPHA_BUILTIN_MAXUW4
,
6634 ALPHA_BUILTIN_MAXSW4
,
6638 ALPHA_BUILTIN_UNPKBL
,
6639 ALPHA_BUILTIN_UNPKBW
,
6644 ALPHA_BUILTIN_CTPOP
,
6649 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6650 CODE_FOR_builtin_cmpbge
,
6651 CODE_FOR_builtin_extbl
,
6652 CODE_FOR_builtin_extwl
,
6653 CODE_FOR_builtin_extll
,
6654 CODE_FOR_builtin_extql
,
6655 CODE_FOR_builtin_extwh
,
6656 CODE_FOR_builtin_extlh
,
6657 CODE_FOR_builtin_extqh
,
6658 CODE_FOR_builtin_insbl
,
6659 CODE_FOR_builtin_inswl
,
6660 CODE_FOR_builtin_insll
,
6661 CODE_FOR_builtin_insql
,
6662 CODE_FOR_builtin_inswh
,
6663 CODE_FOR_builtin_inslh
,
6664 CODE_FOR_builtin_insqh
,
6665 CODE_FOR_builtin_mskbl
,
6666 CODE_FOR_builtin_mskwl
,
6667 CODE_FOR_builtin_mskll
,
6668 CODE_FOR_builtin_mskql
,
6669 CODE_FOR_builtin_mskwh
,
6670 CODE_FOR_builtin_msklh
,
6671 CODE_FOR_builtin_mskqh
,
6672 CODE_FOR_umuldi3_highpart
,
6673 CODE_FOR_builtin_zap
,
6674 CODE_FOR_builtin_zapnot
,
6675 CODE_FOR_builtin_amask
,
6676 CODE_FOR_builtin_implver
,
6677 CODE_FOR_builtin_rpcc
,
6682 CODE_FOR_builtin_minub8
,
6683 CODE_FOR_builtin_minsb8
,
6684 CODE_FOR_builtin_minuw4
,
6685 CODE_FOR_builtin_minsw4
,
6686 CODE_FOR_builtin_maxub8
,
6687 CODE_FOR_builtin_maxsb8
,
6688 CODE_FOR_builtin_maxuw4
,
6689 CODE_FOR_builtin_maxsw4
,
6690 CODE_FOR_builtin_perr
,
6691 CODE_FOR_builtin_pklb
,
6692 CODE_FOR_builtin_pkwb
,
6693 CODE_FOR_builtin_unpkbl
,
6694 CODE_FOR_builtin_unpkbw
,
6697 CODE_FOR_builtin_cttz
,
6698 CODE_FOR_builtin_ctlz
,
6699 CODE_FOR_builtin_ctpop
6702 struct alpha_builtin_def
6705 enum alpha_builtin code
;
6706 unsigned int target_mask
;
6709 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6710 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6711 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6714 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6715 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6716 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6717 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6718 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6719 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6720 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6721 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6722 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6725 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6726 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6727 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6728 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6729 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6730 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6731 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6732 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6733 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6734 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6735 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6736 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6737 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6738 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6739 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6740 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6741 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6742 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6743 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6744 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6745 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6746 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6747 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6748 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6749 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6750 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6751 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6752 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6753 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6754 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6755 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6756 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6757 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6758 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6759 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6763 alpha_init_builtins ()
6765 const struct alpha_builtin_def
*p
;
6769 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6771 p
= zero_arg_builtins
;
6772 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6773 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6774 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6777 ftype
= build_function_type_list (long_integer_type_node
,
6778 long_integer_type_node
, NULL_TREE
);
6780 p
= one_arg_builtins
;
6781 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6782 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6783 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6786 ftype
= build_function_type_list (long_integer_type_node
,
6787 long_integer_type_node
,
6788 long_integer_type_node
, NULL_TREE
);
6790 p
= two_arg_builtins
;
6791 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6792 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6793 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6796 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6797 builtin_function ("__builtin_thread_pointer", ftype
,
6798 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6801 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6802 builtin_function ("__builtin_set_thread_pointer", ftype
,
6803 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6807 /* Expand an expression EXP that calls a built-in function,
6808 with result going to TARGET if that's convenient
6809 (and in mode MODE if that's convenient).
6810 SUBTARGET may be used as the target for computing one of EXP's operands.
6811 IGNORE is nonzero if the value is to be ignored. */
6814 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6817 rtx subtarget ATTRIBUTE_UNUSED
;
6818 enum machine_mode mode ATTRIBUTE_UNUSED
;
6819 int ignore ATTRIBUTE_UNUSED
;
6823 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6824 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6825 tree arglist
= TREE_OPERAND (exp
, 1);
6826 enum insn_code icode
;
6827 rtx op
[MAX_ARGS
], pat
;
6831 if (fcode
>= ALPHA_BUILTIN_max
)
6832 internal_error ("bad builtin fcode");
6833 icode
= code_for_builtin
[fcode
];
6835 internal_error ("bad builtin fcode");
6837 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6839 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6841 arglist
= TREE_CHAIN (arglist
), arity
++)
6843 const struct insn_operand_data
*insn_op
;
6845 tree arg
= TREE_VALUE (arglist
);
6846 if (arg
== error_mark_node
)
6848 if (arity
> MAX_ARGS
)
6851 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6853 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6855 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6856 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6861 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6863 || GET_MODE (target
) != tmode
6864 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6865 target
= gen_reg_rtx (tmode
);
6871 pat
= GEN_FCN (icode
) (target
);
6875 pat
= GEN_FCN (icode
) (target
, op
[0]);
6877 pat
= GEN_FCN (icode
) (op
[0]);
6880 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6895 /* This page contains routines that are used to determine what the function
6896 prologue and epilogue code will do and write them out. */
6898 /* Compute the size of the save area in the stack. */
6900 /* These variables are used for communication between the following functions.
6901 They indicate various things about the current function being compiled
6902 that are used to tell what kind of prologue, epilogue and procedure
6903 descriptior to generate. */
6905 /* Nonzero if we need a stack procedure. */
6906 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6907 static enum alpha_procedure_types alpha_procedure_type
;
6909 /* Register number (either FP or SP) that is used to unwind the frame. */
6910 static int vms_unwind_regno
;
6912 /* Register number used to save FP. We need not have one for RA since
6913 we don't modify it for register procedures. This is only defined
6914 for register frame procedures. */
6915 static int vms_save_fp_regno
;
6917 /* Register number used to reference objects off our PV. */
6918 static int vms_base_regno
;
6920 /* Compute register masks for saved registers. */
6923 alpha_sa_mask (imaskP
, fmaskP
)
6924 unsigned long *imaskP
;
6925 unsigned long *fmaskP
;
6927 unsigned long imask
= 0;
6928 unsigned long fmask
= 0;
6931 /* Irritatingly, there are two kinds of thunks -- those created with
6932 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6933 through the regular part of the compiler. In the
6934 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6935 info, but assemble_start_function wants to output .frame and
6936 .mask directives. */
6937 if (current_function_is_thunk
&& !no_new_pseudos
)
6944 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6945 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6947 /* One for every register we have to save. */
6948 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6949 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6950 && regs_ever_live
[i
] && i
!= REG_RA
6951 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6954 imask
|= (1UL << i
);
6956 fmask
|= (1UL << (i
- 32));
6959 /* We need to restore these for the handler. */
6960 if (current_function_calls_eh_return
)
6963 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6964 if (regno
== INVALID_REGNUM
)
6966 imask
|= 1UL << regno
;
6969 /* If any register spilled, then spill the return address also. */
6970 /* ??? This is required by the Digital stack unwind specification
6971 and isn't needed if we're doing Dwarf2 unwinding. */
6972 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6973 imask
|= (1UL << REG_RA
);
6982 unsigned long mask
[2];
6986 alpha_sa_mask (&mask
[0], &mask
[1]);
6988 if (TARGET_ABI_UNICOSMK
)
6990 if (mask
[0] || mask
[1])
6995 for (j
= 0; j
< 2; ++j
)
6996 for (i
= 0; i
< 32; ++i
)
6997 if ((mask
[j
] >> i
) & 1)
7001 if (TARGET_ABI_UNICOSMK
)
7003 /* We might not need to generate a frame if we don't make any calls
7004 (including calls to __T3E_MISMATCH if this is a vararg function),
7005 don't have any local variables which require stack slots, don't
7006 use alloca and have not determined that we need a frame for other
7009 alpha_procedure_type
7010 = (sa_size
|| get_frame_size() != 0
7011 || current_function_outgoing_args_size
7012 || current_function_stdarg
|| current_function_calls_alloca
7013 || frame_pointer_needed
)
7014 ? PT_STACK
: PT_REGISTER
;
7016 /* Always reserve space for saving callee-saved registers if we
7017 need a frame as required by the calling convention. */
7018 if (alpha_procedure_type
== PT_STACK
)
7021 else if (TARGET_ABI_OPEN_VMS
)
7023 /* Start by assuming we can use a register procedure if we don't
7024 make any calls (REG_RA not used) or need to save any
7025 registers and a stack procedure if we do. */
7026 if ((mask
[0] >> REG_RA
) & 1)
7027 alpha_procedure_type
= PT_STACK
;
7028 else if (get_frame_size() != 0)
7029 alpha_procedure_type
= PT_REGISTER
;
7031 alpha_procedure_type
= PT_NULL
;
7033 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7034 made the final decision on stack procedure vs register procedure. */
7035 if (alpha_procedure_type
== PT_STACK
)
7038 /* Decide whether to refer to objects off our PV via FP or PV.
7039 If we need FP for something else or if we receive a nonlocal
7040 goto (which expects PV to contain the value), we must use PV.
7041 Otherwise, start by assuming we can use FP. */
7044 = (frame_pointer_needed
7045 || current_function_has_nonlocal_label
7046 || alpha_procedure_type
== PT_STACK
7047 || current_function_outgoing_args_size
)
7048 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7050 /* If we want to copy PV into FP, we need to find some register
7051 in which to save FP. */
7053 vms_save_fp_regno
= -1;
7054 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7055 for (i
= 0; i
< 32; i
++)
7056 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
7057 vms_save_fp_regno
= i
;
7059 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7060 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7061 else if (alpha_procedure_type
== PT_NULL
)
7062 vms_base_regno
= REG_PV
;
7064 /* Stack unwinding should be done via FP unless we use it for PV. */
7065 vms_unwind_regno
= (vms_base_regno
== REG_PV
7066 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7068 /* If this is a stack procedure, allow space for saving FP and RA. */
7069 if (alpha_procedure_type
== PT_STACK
)
7074 /* Our size must be even (multiple of 16 bytes). */
7082 /* Define the offset between two registers, one to be eliminated,
7083 and the other its replacement, at the start of a routine. */
7086 alpha_initial_elimination_offset (from
, to
)
7087 unsigned int from
, to ATTRIBUTE_UNUSED
;
7091 ret
= alpha_sa_size ();
7092 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
7094 if (from
== FRAME_POINTER_REGNUM
)
7096 else if (from
== ARG_POINTER_REGNUM
)
7097 ret
+= (ALPHA_ROUND (get_frame_size ()
7098 + current_function_pretend_args_size
)
7099 - current_function_pretend_args_size
);
7107 alpha_pv_save_size ()
7110 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7117 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7120 #if TARGET_ABI_OPEN_VMS
7122 const struct attribute_spec vms_attribute_table
[] =
7124 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7125 { "overlaid", 0, 0, true, false, false, NULL
},
7126 { "global", 0, 0, true, false, false, NULL
},
7127 { "initialize", 0, 0, true, false, false, NULL
},
7128 { NULL
, 0, 0, false, false, false, NULL
}
7134 find_lo_sum_using_gp (px
, data
)
7136 void *data ATTRIBUTE_UNUSED
;
7138 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7142 alpha_find_lo_sum_using_gp (insn
)
7145 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7149 alpha_does_function_need_gp ()
7153 /* The GP being variable is an OSF abi thing. */
7154 if (! TARGET_ABI_OSF
)
7157 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7160 if (current_function_is_thunk
)
7163 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7164 Even if we are a static function, we still need to do this in case
7165 our address is taken and passed to something like qsort. */
7167 push_topmost_sequence ();
7168 insn
= get_insns ();
7169 pop_topmost_sequence ();
7171 for (; insn
; insn
= NEXT_INSN (insn
))
7173 && GET_CODE (PATTERN (insn
)) != USE
7174 && GET_CODE (PATTERN (insn
)) != CLOBBER
7175 && get_attr_usegp (insn
))
7181 /* Write a version stamp. Don't write anything if we are running as a
7182 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
7189 alpha_write_verstamp (file
)
7190 FILE *file ATTRIBUTE_UNUSED
;
7193 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
7197 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7201 set_frame_related_p ()
7203 rtx seq
= get_insns ();
7214 while (insn
!= NULL_RTX
)
7216 RTX_FRAME_RELATED_P (insn
) = 1;
7217 insn
= NEXT_INSN (insn
);
7219 seq
= emit_insn (seq
);
7223 seq
= emit_insn (seq
);
7224 RTX_FRAME_RELATED_P (seq
) = 1;
7229 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7231 /* Write function prologue. */
7233 /* On vms we have two kinds of functions:
7235 - stack frame (PROC_STACK)
7236 these are 'normal' functions with local vars and which are
7237 calling other functions
7238 - register frame (PROC_REGISTER)
7239 keeps all data in registers, needs no stack
7241 We must pass this to the assembler so it can generate the
7242 proper pdsc (procedure descriptor)
7243 This is done with the '.pdesc' command.
7245 On not-vms, we don't really differentiate between the two, as we can
7246 simply allocate stack without saving registers. */
7249 alpha_expand_prologue ()
7251 /* Registers to save. */
7252 unsigned long imask
= 0;
7253 unsigned long fmask
= 0;
7254 /* Stack space needed for pushing registers clobbered by us. */
7255 HOST_WIDE_INT sa_size
;
7256 /* Complete stack size needed. */
7257 HOST_WIDE_INT frame_size
;
7258 /* Offset from base reg to register save area. */
7259 HOST_WIDE_INT reg_offset
;
7263 sa_size
= alpha_sa_size ();
7265 frame_size
= get_frame_size ();
7266 if (TARGET_ABI_OPEN_VMS
)
7267 frame_size
= ALPHA_ROUND (sa_size
7268 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7270 + current_function_pretend_args_size
);
7271 else if (TARGET_ABI_UNICOSMK
)
7272 /* We have to allocate space for the DSIB if we generate a frame. */
7273 frame_size
= ALPHA_ROUND (sa_size
7274 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7275 + ALPHA_ROUND (frame_size
7276 + current_function_outgoing_args_size
);
7278 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7280 + ALPHA_ROUND (frame_size
7281 + current_function_pretend_args_size
));
7283 if (TARGET_ABI_OPEN_VMS
)
7286 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7288 alpha_sa_mask (&imask
, &fmask
);
7290 /* Emit an insn to reload GP, if needed. */
7293 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7294 if (alpha_function_needs_gp
)
7295 emit_insn (gen_prologue_ldgp ());
7298 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7299 the call to mcount ourselves, rather than having the linker do it
7300 magically in response to -pg. Since _mcount has special linkage,
7301 don't represent the call as a call. */
7302 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7303 emit_insn (gen_prologue_mcount ());
7305 if (TARGET_ABI_UNICOSMK
)
7306 unicosmk_gen_dsib (&imask
);
7308 /* Adjust the stack by the frame size. If the frame size is > 4096
7309 bytes, we need to be sure we probe somewhere in the first and last
7310 4096 bytes (we can probably get away without the latter test) and
7311 every 8192 bytes in between. If the frame size is > 32768, we
7312 do this in a loop. Otherwise, we generate the explicit probe
7315 Note that we are only allowed to adjust sp once in the prologue. */
7317 if (frame_size
<= 32768)
7319 if (frame_size
> 4096)
7324 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7327 while ((probed
+= 8192) < frame_size
);
7329 /* We only have to do this probe if we aren't saving registers. */
7330 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7331 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7334 if (frame_size
!= 0)
7335 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7336 GEN_INT (TARGET_ABI_UNICOSMK
7342 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7343 number of 8192 byte blocks to probe. We then probe each block
7344 in the loop and then set SP to the proper location. If the
7345 amount remaining is > 4096, we have to do one more probe if we
7346 are not saving any registers. */
7348 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7349 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7350 rtx ptr
= gen_rtx_REG (DImode
, 22);
7351 rtx count
= gen_rtx_REG (DImode
, 23);
7354 emit_move_insn (count
, GEN_INT (blocks
));
7355 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7356 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7358 /* Because of the difficulty in emitting a new basic block this
7359 late in the compilation, generate the loop as a single insn. */
7360 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7362 if (leftover
> 4096 && sa_size
== 0)
7364 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7365 MEM_VOLATILE_P (last
) = 1;
7366 emit_move_insn (last
, const0_rtx
);
7369 if (TARGET_ABI_WINDOWS_NT
)
7371 /* For NT stack unwind (done by 'reverse execution'), it's
7372 not OK to take the result of a loop, even though the value
7373 is already in ptr, so we reload it via a single operation
7374 and subtract it to sp.
7376 Yes, that's correct -- we have to reload the whole constant
7377 into a temporary via ldah+lda then subtract from sp. To
7378 ensure we get ldah+lda, we use a special pattern. */
7380 HOST_WIDE_INT lo
, hi
;
7381 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7382 hi
= frame_size
- lo
;
7384 emit_move_insn (ptr
, GEN_INT (hi
));
7385 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7386 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7391 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7392 GEN_INT (-leftover
)));
7395 /* This alternative is special, because the DWARF code cannot
7396 possibly intuit through the loop above. So we invent this
7397 note it looks at instead. */
7398 RTX_FRAME_RELATED_P (seq
) = 1;
7400 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7401 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7402 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7403 GEN_INT (TARGET_ABI_UNICOSMK
7409 if (!TARGET_ABI_UNICOSMK
)
7411 /* Cope with very large offsets to the register save area. */
7412 sa_reg
= stack_pointer_rtx
;
7413 if (reg_offset
+ sa_size
> 0x8000)
7415 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7418 if (low
+ sa_size
<= 0x8000)
7419 bias
= reg_offset
- low
, reg_offset
= low
;
7421 bias
= reg_offset
, reg_offset
= 0;
7423 sa_reg
= gen_rtx_REG (DImode
, 24);
7424 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7428 /* Save regs in stack order. Beginning with VMS PV. */
7429 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7431 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7432 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7433 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7436 /* Save register RA next. */
7437 if (imask
& (1UL << REG_RA
))
7439 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7440 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7441 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7442 imask
&= ~(1UL << REG_RA
);
7446 /* Now save any other registers required to be saved. */
7447 for (i
= 0; i
< 32; i
++)
7448 if (imask
& (1UL << i
))
7450 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7451 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7452 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7456 for (i
= 0; i
< 32; i
++)
7457 if (fmask
& (1UL << i
))
7459 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7460 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7461 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7465 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7467 /* The standard frame on the T3E includes space for saving registers.
7468 We just have to use it. We don't have to save the return address and
7469 the old frame pointer here - they are saved in the DSIB. */
7472 for (i
= 9; i
< 15; i
++)
7473 if (imask
& (1UL << i
))
7475 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7477 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7478 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7481 for (i
= 2; i
< 10; i
++)
7482 if (fmask
& (1UL << i
))
7484 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7486 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7487 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7492 if (TARGET_ABI_OPEN_VMS
)
7494 if (alpha_procedure_type
== PT_REGISTER
)
7495 /* Register frame procedures save the fp.
7496 ?? Ought to have a dwarf2 save for this. */
7497 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7498 hard_frame_pointer_rtx
);
7500 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7501 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7502 gen_rtx_REG (DImode
, REG_PV
)));
7504 if (alpha_procedure_type
!= PT_NULL
7505 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7506 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7508 /* If we have to allocate space for outgoing args, do it now. */
7509 if (current_function_outgoing_args_size
!= 0)
7512 = emit_move_insn (stack_pointer_rtx
,
7514 (hard_frame_pointer_rtx
,
7516 (current_function_outgoing_args_size
))));
7518 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7519 if ! frame_pointer_needed. Setting the bit will change the CFA
7520 computation rule to use sp again, which would be wrong if we had
7521 frame_pointer_needed, as this means sp might move unpredictably
7525 frame_pointer_needed
7526 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7528 current_function_outgoing_args_size != 0
7529 => alpha_procedure_type != PT_NULL,
7531 so when we are not setting the bit here, we are guaranteed to
7532 have emited an FRP frame pointer update just before. */
7533 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7536 else if (!TARGET_ABI_UNICOSMK
)
7538 /* If we need a frame pointer, set it from the stack pointer. */
7539 if (frame_pointer_needed
)
7541 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7542 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7544 /* This must always be the last instruction in the
7545 prologue, thus we emit a special move + clobber. */
7546 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7547 stack_pointer_rtx
, sa_reg
)));
7551 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7552 the prologue, for exception handling reasons, we cannot do this for
7553 any insn that might fault. We could prevent this for mems with a
7554 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7555 have to prevent all such scheduling with a blockage.
7557 Linux, on the other hand, never bothered to implement OSF/1's
7558 exception handling, and so doesn't care about such things. Anyone
7559 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7561 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7562 emit_insn (gen_blockage ());
7565 /* Output the textual info surrounding the prologue. */
7568 alpha_start_function (file
, fnname
, decl
)
7571 tree decl ATTRIBUTE_UNUSED
;
7573 unsigned long imask
= 0;
7574 unsigned long fmask
= 0;
7575 /* Stack space needed for pushing registers clobbered by us. */
7576 HOST_WIDE_INT sa_size
;
7577 /* Complete stack size needed. */
7578 unsigned HOST_WIDE_INT frame_size
;
7579 /* Offset from base reg to register save area. */
7580 HOST_WIDE_INT reg_offset
;
7581 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7584 /* Don't emit an extern directive for functions defined in the same file. */
7585 if (TARGET_ABI_UNICOSMK
)
7588 name_tree
= get_identifier (fnname
);
7589 TREE_ASM_WRITTEN (name_tree
) = 1;
7592 alpha_fnname
= fnname
;
7593 sa_size
= alpha_sa_size ();
7595 frame_size
= get_frame_size ();
7596 if (TARGET_ABI_OPEN_VMS
)
7597 frame_size
= ALPHA_ROUND (sa_size
7598 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7600 + current_function_pretend_args_size
);
7601 else if (TARGET_ABI_UNICOSMK
)
7602 frame_size
= ALPHA_ROUND (sa_size
7603 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7604 + ALPHA_ROUND (frame_size
7605 + current_function_outgoing_args_size
);
7607 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7609 + ALPHA_ROUND (frame_size
7610 + current_function_pretend_args_size
));
7612 if (TARGET_ABI_OPEN_VMS
)
7615 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7617 alpha_sa_mask (&imask
, &fmask
);
7619 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7620 We have to do that before the .ent directive as we cannot switch
7621 files within procedures with native ecoff because line numbers are
7622 linked to procedure descriptors.
7623 Outputting the lineno helps debugging of one line functions as they
7624 would otherwise get no line number at all. Please note that we would
7625 like to put out last_linenum from final.c, but it is not accessible. */
7627 if (write_symbols
== SDB_DEBUG
)
7629 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7630 ASM_OUTPUT_SOURCE_FILENAME (file
,
7631 DECL_SOURCE_FILE (current_function_decl
));
7633 #ifdef ASM_OUTPUT_SOURCE_LINE
7634 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7635 ASM_OUTPUT_SOURCE_LINE (file
,
7636 DECL_SOURCE_LINE (current_function_decl
));
7640 /* Issue function start and label. */
7641 if (TARGET_ABI_OPEN_VMS
7642 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7644 fputs ("\t.ent ", file
);
7645 assemble_name (file
, fnname
);
7648 /* If the function needs GP, we'll write the "..ng" label there.
7649 Otherwise, do it here. */
7651 && ! alpha_function_needs_gp
7652 && ! current_function_is_thunk
)
7655 assemble_name (file
, fnname
);
7656 fputs ("..ng:\n", file
);
7660 strcpy (entry_label
, fnname
);
7661 if (TARGET_ABI_OPEN_VMS
)
7662 strcat (entry_label
, "..en");
7664 /* For public functions, the label must be globalized by appending an
7665 additional colon. */
7666 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7667 strcat (entry_label
, ":");
7669 ASM_OUTPUT_LABEL (file
, entry_label
);
7670 inside_function
= TRUE
;
7672 if (TARGET_ABI_OPEN_VMS
)
7673 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7675 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7676 && !flag_inhibit_size_directive
)
7678 /* Set flags in procedure descriptor to request IEEE-conformant
7679 math-library routines. The value we set it to is PDSC_EXC_IEEE
7680 (/usr/include/pdsc.h). */
7681 fputs ("\t.eflag 48\n", file
);
7684 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7685 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7686 alpha_arg_offset
= -frame_size
+ 48;
7688 /* Describe our frame. If the frame size is larger than an integer,
7689 print it as zero to avoid an assembler error. We won't be
7690 properly describing such a frame, but that's the best we can do. */
7691 if (TARGET_ABI_UNICOSMK
)
7693 else if (TARGET_ABI_OPEN_VMS
)
7694 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7695 HOST_WIDE_INT_PRINT_DEC
"\n",
7697 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7699 else if (!flag_inhibit_size_directive
)
7700 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7701 (frame_pointer_needed
7702 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7703 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7704 current_function_pretend_args_size
);
7706 /* Describe which registers were spilled. */
7707 if (TARGET_ABI_UNICOSMK
)
7709 else if (TARGET_ABI_OPEN_VMS
)
7712 /* ??? Does VMS care if mask contains ra? The old code didn't
7713 set it, so I don't here. */
7714 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7716 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7717 if (alpha_procedure_type
== PT_REGISTER
)
7718 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7720 else if (!flag_inhibit_size_directive
)
7724 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7725 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7727 for (i
= 0; i
< 32; ++i
)
7728 if (imask
& (1UL << i
))
7733 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7734 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7737 #if TARGET_ABI_OPEN_VMS
7738 /* Ifdef'ed cause link_section are only available then. */
7739 readonly_data_section ();
7740 fprintf (file
, "\t.align 3\n");
7741 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7742 fputs ("\t.ascii \"", file
);
7743 assemble_name (file
, fnname
);
7744 fputs ("\\0\"\n", file
);
7745 alpha_need_linkage (fnname
, 1);
7750 /* Emit the .prologue note at the scheduled end of the prologue. */
7753 alpha_output_function_end_prologue (file
)
7756 if (TARGET_ABI_UNICOSMK
)
7758 else if (TARGET_ABI_OPEN_VMS
)
7759 fputs ("\t.prologue\n", file
);
7760 else if (TARGET_ABI_WINDOWS_NT
)
7761 fputs ("\t.prologue 0\n", file
);
7762 else if (!flag_inhibit_size_directive
)
7763 fprintf (file
, "\t.prologue %d\n",
7764 alpha_function_needs_gp
|| current_function_is_thunk
);
7767 /* Write function epilogue. */
7769 /* ??? At some point we will want to support full unwind, and so will
7770 need to mark the epilogue as well. At the moment, we just confuse
7773 #define FRP(exp) exp
7776 alpha_expand_epilogue ()
7778 /* Registers to save. */
7779 unsigned long imask
= 0;
7780 unsigned long fmask
= 0;
7781 /* Stack space needed for pushing registers clobbered by us. */
7782 HOST_WIDE_INT sa_size
;
7783 /* Complete stack size needed. */
7784 HOST_WIDE_INT frame_size
;
7785 /* Offset from base reg to register save area. */
7786 HOST_WIDE_INT reg_offset
;
7787 int fp_is_frame_pointer
, fp_offset
;
7788 rtx sa_reg
, sa_reg_exp
= NULL
;
7789 rtx sp_adj1
, sp_adj2
, mem
;
7793 sa_size
= alpha_sa_size ();
7795 frame_size
= get_frame_size ();
7796 if (TARGET_ABI_OPEN_VMS
)
7797 frame_size
= ALPHA_ROUND (sa_size
7798 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7800 + current_function_pretend_args_size
);
7801 else if (TARGET_ABI_UNICOSMK
)
7802 frame_size
= ALPHA_ROUND (sa_size
7803 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7804 + ALPHA_ROUND (frame_size
7805 + current_function_outgoing_args_size
);
7807 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7809 + ALPHA_ROUND (frame_size
7810 + current_function_pretend_args_size
));
7812 if (TARGET_ABI_OPEN_VMS
)
7814 if (alpha_procedure_type
== PT_STACK
)
7820 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7822 alpha_sa_mask (&imask
, &fmask
);
7825 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7826 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7828 sa_reg
= stack_pointer_rtx
;
7830 if (current_function_calls_eh_return
)
7831 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7835 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7837 /* If we have a frame pointer, restore SP from it. */
7838 if ((TARGET_ABI_OPEN_VMS
7839 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7840 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7841 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7843 /* Cope with very large offsets to the register save area. */
7844 if (reg_offset
+ sa_size
> 0x8000)
7846 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7849 if (low
+ sa_size
<= 0x8000)
7850 bias
= reg_offset
- low
, reg_offset
= low
;
7852 bias
= reg_offset
, reg_offset
= 0;
7854 sa_reg
= gen_rtx_REG (DImode
, 22);
7855 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7857 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7860 /* Restore registers in order, excepting a true frame pointer. */
7862 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7864 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7865 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7868 imask
&= ~(1UL << REG_RA
);
7870 for (i
= 0; i
< 32; ++i
)
7871 if (imask
& (1UL << i
))
7873 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7874 fp_offset
= reg_offset
;
7877 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7878 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7879 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7884 for (i
= 0; i
< 32; ++i
)
7885 if (fmask
& (1UL << i
))
7887 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7888 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7889 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7893 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7895 /* Restore callee-saved general-purpose registers. */
7899 for (i
= 9; i
< 15; i
++)
7900 if (imask
& (1UL << i
))
7902 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7904 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7905 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7909 for (i
= 2; i
< 10; i
++)
7910 if (fmask
& (1UL << i
))
7912 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7914 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7915 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7919 /* Restore the return address from the DSIB. */
7921 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7922 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7923 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7926 if (frame_size
|| eh_ofs
)
7928 sp_adj1
= stack_pointer_rtx
;
7932 sp_adj1
= gen_rtx_REG (DImode
, 23);
7933 emit_move_insn (sp_adj1
,
7934 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7937 /* If the stack size is large, begin computation into a temporary
7938 register so as not to interfere with a potential fp restore,
7939 which must be consecutive with an SP restore. */
7940 if (frame_size
< 32768
7941 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7942 sp_adj2
= GEN_INT (frame_size
);
7943 else if (TARGET_ABI_UNICOSMK
)
7945 sp_adj1
= gen_rtx_REG (DImode
, 23);
7946 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7947 sp_adj2
= const0_rtx
;
7949 else if (frame_size
< 0x40007fffL
)
7951 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7953 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7954 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7958 sp_adj1
= gen_rtx_REG (DImode
, 23);
7959 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7961 sp_adj2
= GEN_INT (low
);
7965 rtx tmp
= gen_rtx_REG (DImode
, 23);
7966 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7969 /* We can't drop new things to memory this late, afaik,
7970 so build it up by pieces. */
7971 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7972 -(frame_size
< 0)));
7978 /* From now on, things must be in order. So emit blockages. */
7980 /* Restore the frame pointer. */
7981 if (TARGET_ABI_UNICOSMK
)
7983 emit_insn (gen_blockage ());
7984 mem
= gen_rtx_MEM (DImode
,
7985 plus_constant (hard_frame_pointer_rtx
, -16));
7986 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7987 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7989 else if (fp_is_frame_pointer
)
7991 emit_insn (gen_blockage ());
7992 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7993 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7994 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7996 else if (TARGET_ABI_OPEN_VMS
)
7998 emit_insn (gen_blockage ());
7999 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8000 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8003 /* Restore the stack pointer. */
8004 emit_insn (gen_blockage ());
8005 if (sp_adj2
== const0_rtx
)
8006 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
8008 FRP (emit_move_insn (stack_pointer_rtx
,
8009 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
8013 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8015 emit_insn (gen_blockage ());
8016 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8017 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8019 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8021 /* Decrement the frame pointer if the function does not have a
8024 emit_insn (gen_blockage ());
8025 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8026 hard_frame_pointer_rtx
, GEN_INT (-1))));
8031 /* Output the rest of the textual info surrounding the epilogue. */
8034 alpha_end_function (file
, fnname
, decl
)
8037 tree decl ATTRIBUTE_UNUSED
;
8039 /* End the function. */
8040 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8042 fputs ("\t.end ", file
);
8043 assemble_name (file
, fnname
);
8046 inside_function
= FALSE
;
8048 #if TARGET_ABI_OPEN_VMS
8049 alpha_write_linkage (file
, fnname
, decl
);
8052 /* Output jump tables and the static subroutine information block. */
8053 if (TARGET_ABI_UNICOSMK
)
8055 unicosmk_output_ssib (file
, fnname
);
8056 unicosmk_output_deferred_case_vectors (file
);
8061 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8063 In order to avoid the hordes of differences between generated code
8064 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8065 lots of code loading up large constants, generate rtl and emit it
8066 instead of going straight to text.
8068 Not sure why this idea hasn't been explored before... */
8071 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
8073 tree thunk_fndecl ATTRIBUTE_UNUSED
;
8074 HOST_WIDE_INT delta
;
8075 HOST_WIDE_INT vcall_offset
;
8078 HOST_WIDE_INT hi
, lo
;
8079 rtx
this, insn
, funexp
;
8081 /* We always require a valid GP. */
8082 emit_insn (gen_prologue_ldgp ());
8083 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
8085 /* Find the "this" pointer. If the function returns a structure,
8086 the structure return pointer is in $16. */
8087 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
8088 this = gen_rtx_REG (Pmode
, 17);
8090 this = gen_rtx_REG (Pmode
, 16);
8092 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8093 entire constant for the add. */
8094 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8095 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8096 if (hi
+ lo
== delta
)
8099 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
8101 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
8105 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8106 delta
, -(delta
< 0));
8107 emit_insn (gen_adddi3 (this, this, tmp
));
8110 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8115 tmp
= gen_rtx_REG (Pmode
, 0);
8116 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8118 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8119 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8120 if (hi
+ lo
== vcall_offset
)
8123 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8127 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8128 vcall_offset
, -(vcall_offset
< 0));
8129 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8133 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8136 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8138 emit_insn (gen_adddi3 (this, this, tmp
));
8141 /* Generate a tail call to the target function. */
8142 if (! TREE_USED (function
))
8144 assemble_external (function
);
8145 TREE_USED (function
) = 1;
8147 funexp
= XEXP (DECL_RTL (function
), 0);
8148 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8149 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8150 SIBLING_CALL_P (insn
) = 1;
8152 /* Run just enough of rest_of_compilation to get the insns emitted.
8153 There's not really enough bulk here to make other passes such as
8154 instruction scheduling worth while. Note that use_thunk calls
8155 assemble_start_function and assemble_end_function. */
8156 insn
= get_insns ();
8157 shorten_branches (insn
);
8158 final_start_function (insn
, file
, 1);
8159 final (insn
, file
, 1, 0);
8160 final_end_function ();
8162 #endif /* TARGET_ABI_OSF */
8164 /* Debugging support. */
8168 /* Count the number of sdb related labels are generated (to find block
8169 start and end boundaries). */
8171 int sdb_label_count
= 0;
8173 /* Next label # for each statement. */
8175 static int sym_lineno
= 0;
8177 /* Count the number of .file directives, so that .loc is up to date. */
8179 static int num_source_filenames
= 0;
8181 /* Name of the file containing the current function. */
8183 static const char *current_function_file
= "";
8185 /* Offsets to alpha virtual arg/local debugging pointers. */
8187 long alpha_arg_offset
;
8188 long alpha_auto_offset
;
8190 /* Emit a new filename to a stream. */
8193 alpha_output_filename (stream
, name
)
8197 static int first_time
= TRUE
;
8198 char ltext_label_name
[100];
8203 ++num_source_filenames
;
8204 current_function_file
= name
;
8205 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8206 output_quoted_string (stream
, name
);
8207 fprintf (stream
, "\n");
8208 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8209 fprintf (stream
, "\t#@stabs\n");
8212 else if (write_symbols
== DBX_DEBUG
)
8214 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
8215 fprintf (stream
, "%s", ASM_STABS_OP
);
8216 output_quoted_string (stream
, name
);
8217 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8220 else if (name
!= current_function_file
8221 && strcmp (name
, current_function_file
) != 0)
8223 if (inside_function
&& ! TARGET_GAS
)
8224 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8227 ++num_source_filenames
;
8228 current_function_file
= name
;
8229 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8232 output_quoted_string (stream
, name
);
8233 fprintf (stream
, "\n");
8237 /* Emit a linenumber to a stream. */
8240 alpha_output_lineno (stream
, line
)
8244 if (write_symbols
== DBX_DEBUG
)
8246 /* mips-tfile doesn't understand .stabd directives. */
8248 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8249 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8252 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8255 /* Structure to show the current status of registers and memory. */
8257 struct shadow_summary
8260 unsigned int i
: 31; /* Mask of int regs */
8261 unsigned int fp
: 31; /* Mask of fp regs */
8262 unsigned int mem
: 1; /* mem == imem | fpmem */
8266 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
8267 static void alpha_handle_trap_shadows
PARAMS ((void));
8269 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8270 to the summary structure. SET is nonzero if the insn is setting the
8271 object, otherwise zero. */
8274 summarize_insn (x
, sum
, set
)
8276 struct shadow_summary
*sum
;
8279 const char *format_ptr
;
8285 switch (GET_CODE (x
))
8287 /* ??? Note that this case would be incorrect if the Alpha had a
8288 ZERO_EXTRACT in SET_DEST. */
8290 summarize_insn (SET_SRC (x
), sum
, 0);
8291 summarize_insn (SET_DEST (x
), sum
, 1);
8295 summarize_insn (XEXP (x
, 0), sum
, 1);
8299 summarize_insn (XEXP (x
, 0), sum
, 0);
8303 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8304 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8308 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8309 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8313 summarize_insn (SUBREG_REG (x
), sum
, 0);
8318 int regno
= REGNO (x
);
8319 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8321 if (regno
== 31 || regno
== 63)
8327 sum
->defd
.i
|= mask
;
8329 sum
->defd
.fp
|= mask
;
8334 sum
->used
.i
|= mask
;
8336 sum
->used
.fp
|= mask
;
8347 /* Find the regs used in memory address computation: */
8348 summarize_insn (XEXP (x
, 0), sum
, 0);
8351 case CONST_INT
: case CONST_DOUBLE
:
8352 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8353 case SCRATCH
: case ASM_INPUT
:
8356 /* Handle common unary and binary ops for efficiency. */
8357 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8358 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8359 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8360 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8361 case NE
: case EQ
: case GE
: case GT
: case LE
:
8362 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8363 summarize_insn (XEXP (x
, 0), sum
, 0);
8364 summarize_insn (XEXP (x
, 1), sum
, 0);
8367 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8368 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8369 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8370 case SQRT
: case FFS
:
8371 summarize_insn (XEXP (x
, 0), sum
, 0);
8375 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8376 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8377 switch (format_ptr
[i
])
8380 summarize_insn (XEXP (x
, i
), sum
, 0);
8384 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8385 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8397 /* Ensure a sufficient number of `trapb' insns are in the code when
8398 the user requests code with a trap precision of functions or
8401 In naive mode, when the user requests a trap-precision of
8402 "instruction", a trapb is needed after every instruction that may
8403 generate a trap. This ensures that the code is resumption safe but
8406 When optimizations are turned on, we delay issuing a trapb as long
8407 as possible. In this context, a trap shadow is the sequence of
8408 instructions that starts with a (potentially) trap generating
8409 instruction and extends to the next trapb or call_pal instruction
8410 (but GCC never generates call_pal by itself). We can delay (and
8411 therefore sometimes omit) a trapb subject to the following
8414 (a) On entry to the trap shadow, if any Alpha register or memory
8415 location contains a value that is used as an operand value by some
8416 instruction in the trap shadow (live on entry), then no instruction
8417 in the trap shadow may modify the register or memory location.
8419 (b) Within the trap shadow, the computation of the base register
8420 for a memory load or store instruction may not involve using the
8421 result of an instruction that might generate an UNPREDICTABLE
8424 (c) Within the trap shadow, no register may be used more than once
8425 as a destination register. (This is to make life easier for the
8428 (d) The trap shadow may not include any branch instructions. */
8431 alpha_handle_trap_shadows ()
8433 struct shadow_summary shadow
;
8434 int trap_pending
, exception_nesting
;
8438 exception_nesting
= 0;
8441 shadow
.used
.mem
= 0;
8442 shadow
.defd
= shadow
.used
;
8444 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8446 if (GET_CODE (i
) == NOTE
)
8448 switch (NOTE_LINE_NUMBER (i
))
8450 case NOTE_INSN_EH_REGION_BEG
:
8451 exception_nesting
++;
8456 case NOTE_INSN_EH_REGION_END
:
8457 exception_nesting
--;
8462 case NOTE_INSN_EPILOGUE_BEG
:
8463 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8468 else if (trap_pending
)
8470 if (alpha_tp
== ALPHA_TP_FUNC
)
8472 if (GET_CODE (i
) == JUMP_INSN
8473 && GET_CODE (PATTERN (i
)) == RETURN
)
8476 else if (alpha_tp
== ALPHA_TP_INSN
)
8480 struct shadow_summary sum
;
8485 sum
.defd
= sum
.used
;
8487 switch (GET_CODE (i
))
8490 /* Annoyingly, get_attr_trap will abort on these. */
8491 if (GET_CODE (PATTERN (i
)) == USE
8492 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8495 summarize_insn (PATTERN (i
), &sum
, 0);
8497 if ((sum
.defd
.i
& shadow
.defd
.i
)
8498 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8500 /* (c) would be violated */
8504 /* Combine shadow with summary of current insn: */
8505 shadow
.used
.i
|= sum
.used
.i
;
8506 shadow
.used
.fp
|= sum
.used
.fp
;
8507 shadow
.used
.mem
|= sum
.used
.mem
;
8508 shadow
.defd
.i
|= sum
.defd
.i
;
8509 shadow
.defd
.fp
|= sum
.defd
.fp
;
8510 shadow
.defd
.mem
|= sum
.defd
.mem
;
8512 if ((sum
.defd
.i
& shadow
.used
.i
)
8513 || (sum
.defd
.fp
& shadow
.used
.fp
)
8514 || (sum
.defd
.mem
& shadow
.used
.mem
))
8516 /* (a) would be violated (also takes care of (b)) */
8517 if (get_attr_trap (i
) == TRAP_YES
8518 && ((sum
.defd
.i
& sum
.used
.i
)
8519 || (sum
.defd
.fp
& sum
.used
.fp
)))
8538 n
= emit_insn_before (gen_trapb (), i
);
8539 PUT_MODE (n
, TImode
);
8540 PUT_MODE (i
, TImode
);
8544 shadow
.used
.mem
= 0;
8545 shadow
.defd
= shadow
.used
;
8550 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8551 && GET_CODE (i
) == INSN
8552 && GET_CODE (PATTERN (i
)) != USE
8553 && GET_CODE (PATTERN (i
)) != CLOBBER
8554 && get_attr_trap (i
) == TRAP_YES
)
8556 if (optimize
&& !trap_pending
)
8557 summarize_insn (PATTERN (i
), &shadow
, 0);
8563 /* Alpha can only issue instruction groups simultaneously if they are
8564 suitibly aligned. This is very processor-specific. */
8566 enum alphaev4_pipe
{
8573 enum alphaev5_pipe
{
8584 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8585 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8586 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8587 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8588 static rtx alphaev4_next_nop
PARAMS ((int *));
8589 static rtx alphaev5_next_nop
PARAMS ((int *));
8591 static void alpha_align_insns
8592 PARAMS ((unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8594 static enum alphaev4_pipe
8595 alphaev4_insn_pipe (insn
)
8598 if (recog_memoized (insn
) < 0)
8600 if (get_attr_length (insn
) != 4)
8603 switch (get_attr_type (insn
))
8637 static enum alphaev5_pipe
8638 alphaev5_insn_pipe (insn
)
8641 if (recog_memoized (insn
) < 0)
8643 if (get_attr_length (insn
) != 4)
8646 switch (get_attr_type (insn
))
8687 /* IN_USE is a mask of the slots currently filled within the insn group.
8688 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8689 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8691 LEN is, of course, the length of the group in bytes. */
8694 alphaev4_next_group (insn
, pin_use
, plen
)
8696 int *pin_use
, *plen
;
8703 || GET_CODE (PATTERN (insn
)) == CLOBBER
8704 || GET_CODE (PATTERN (insn
)) == USE
)
8709 enum alphaev4_pipe pipe
;
8711 pipe
= alphaev4_insn_pipe (insn
);
8715 /* Force complex instructions to start new groups. */
8719 /* If this is a completely unrecognized insn, its an asm.
8720 We don't know how long it is, so record length as -1 to
8721 signal a needed realignment. */
8722 if (recog_memoized (insn
) < 0)
8725 len
= get_attr_length (insn
);
8729 if (in_use
& EV4_IB0
)
8731 if (in_use
& EV4_IB1
)
8736 in_use
|= EV4_IB0
| EV4_IBX
;
8740 if (in_use
& EV4_IB0
)
8742 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8750 if (in_use
& EV4_IB1
)
8760 /* Haifa doesn't do well scheduling branches. */
8761 if (GET_CODE (insn
) == JUMP_INSN
)
8765 insn
= next_nonnote_insn (insn
);
8767 if (!insn
|| ! INSN_P (insn
))
8770 /* Let Haifa tell us where it thinks insn group boundaries are. */
8771 if (GET_MODE (insn
) == TImode
)
8774 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8779 insn
= next_nonnote_insn (insn
);
8787 /* IN_USE is a mask of the slots currently filled within the insn group.
8788 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8789 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8791 LEN is, of course, the length of the group in bytes. */
8794 alphaev5_next_group (insn
, pin_use
, plen
)
8796 int *pin_use
, *plen
;
8803 || GET_CODE (PATTERN (insn
)) == CLOBBER
8804 || GET_CODE (PATTERN (insn
)) == USE
)
8809 enum alphaev5_pipe pipe
;
8811 pipe
= alphaev5_insn_pipe (insn
);
8815 /* Force complex instructions to start new groups. */
8819 /* If this is a completely unrecognized insn, its an asm.
8820 We don't know how long it is, so record length as -1 to
8821 signal a needed realignment. */
8822 if (recog_memoized (insn
) < 0)
8825 len
= get_attr_length (insn
);
8828 /* ??? Most of the places below, we would like to abort, as
8829 it would indicate an error either in Haifa, or in the
8830 scheduling description. Unfortunately, Haifa never
8831 schedules the last instruction of the BB, so we don't
8832 have an accurate TI bit to go off. */
8834 if (in_use
& EV5_E0
)
8836 if (in_use
& EV5_E1
)
8841 in_use
|= EV5_E0
| EV5_E01
;
8845 if (in_use
& EV5_E0
)
8847 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8855 if (in_use
& EV5_E1
)
8861 if (in_use
& EV5_FA
)
8863 if (in_use
& EV5_FM
)
8868 in_use
|= EV5_FA
| EV5_FAM
;
8872 if (in_use
& EV5_FA
)
8878 if (in_use
& EV5_FM
)
8891 /* Haifa doesn't do well scheduling branches. */
8892 /* ??? If this is predicted not-taken, slotting continues, except
8893 that no more IBR, FBR, or JSR insns may be slotted. */
8894 if (GET_CODE (insn
) == JUMP_INSN
)
8898 insn
= next_nonnote_insn (insn
);
8900 if (!insn
|| ! INSN_P (insn
))
8903 /* Let Haifa tell us where it thinks insn group boundaries are. */
8904 if (GET_MODE (insn
) == TImode
)
8907 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8912 insn
= next_nonnote_insn (insn
);
8921 alphaev4_next_nop (pin_use
)
8924 int in_use
= *pin_use
;
8927 if (!(in_use
& EV4_IB0
))
8932 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8937 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8950 alphaev5_next_nop (pin_use
)
8953 int in_use
= *pin_use
;
8956 if (!(in_use
& EV5_E1
))
8961 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8966 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8978 /* The instruction group alignment main loop. */
8981 alpha_align_insns (max_align
, next_group
, next_nop
)
8982 unsigned int max_align
;
8983 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
8984 rtx (*next_nop
) PARAMS ((int *));
8986 /* ALIGN is the known alignment for the insn group. */
8988 /* OFS is the offset of the current insn in the insn group. */
8990 int prev_in_use
, in_use
, len
;
8993 /* Let shorten branches care for assigning alignments to code labels. */
8994 shorten_branches (get_insns ());
8996 if (align_functions
< 4)
8998 else if ((unsigned int) align_functions
< max_align
)
8999 align
= align_functions
;
9003 ofs
= prev_in_use
= 0;
9005 if (GET_CODE (i
) == NOTE
)
9006 i
= next_nonnote_insn (i
);
9010 next
= (*next_group
) (i
, &in_use
, &len
);
9012 /* When we see a label, resync alignment etc. */
9013 if (GET_CODE (i
) == CODE_LABEL
)
9015 unsigned int new_align
= 1 << label_to_alignment (i
);
9017 if (new_align
>= align
)
9019 align
= new_align
< max_align
? new_align
: max_align
;
9023 else if (ofs
& (new_align
-1))
9024 ofs
= (ofs
| (new_align
-1)) + 1;
9029 /* Handle complex instructions special. */
9030 else if (in_use
== 0)
9032 /* Asms will have length < 0. This is a signal that we have
9033 lost alignment knowledge. Assume, however, that the asm
9034 will not mis-align instructions. */
9043 /* If the known alignment is smaller than the recognized insn group,
9044 realign the output. */
9045 else if ((int) align
< len
)
9047 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9050 where
= prev
= prev_nonnote_insn (i
);
9051 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
9054 /* Can't realign between a call and its gp reload. */
9055 if (! (TARGET_EXPLICIT_RELOCS
9056 && prev
&& GET_CODE (prev
) == CALL_INSN
))
9058 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9059 align
= 1 << new_log_align
;
9064 /* If the group won't fit in the same INT16 as the previous,
9065 we need to add padding to keep the group together. Rather
9066 than simply leaving the insn filling to the assembler, we
9067 can make use of the knowledge of what sorts of instructions
9068 were issued in the previous group to make sure that all of
9069 the added nops are really free. */
9070 else if (ofs
+ len
> (int) align
)
9072 int nop_count
= (align
- ofs
) / 4;
9075 /* Insert nops before labels, branches, and calls to truely merge
9076 the execution of the nops with the previous instruction group. */
9077 where
= prev_nonnote_insn (i
);
9080 if (GET_CODE (where
) == CODE_LABEL
)
9082 rtx where2
= prev_nonnote_insn (where
);
9083 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
9086 else if (GET_CODE (where
) == INSN
)
9093 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9094 while (--nop_count
);
9098 ofs
= (ofs
+ len
) & (align
- 1);
9099 prev_in_use
= in_use
;
9104 /* Machine dependent reorg pass. */
9109 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9110 alpha_handle_trap_shadows ();
9112 /* Due to the number of extra trapb insns, don't bother fixing up
9113 alignment when trap precision is instruction. Moreover, we can
9114 only do our job when sched2 is run. */
9115 if (optimize
&& !optimize_size
9116 && alpha_tp
!= ALPHA_TP_INSN
9117 && flag_schedule_insns_after_reload
)
9119 if (alpha_cpu
== PROCESSOR_EV4
)
9120 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
9121 else if (alpha_cpu
== PROCESSOR_EV5
)
9122 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
9126 #ifdef OBJECT_FORMAT_ELF
9128 /* Switch to the section to which we should output X. The only thing
9129 special we do here is to honor small data. */
9132 alpha_elf_select_rtx_section (mode
, x
, align
)
9133 enum machine_mode mode
;
9135 unsigned HOST_WIDE_INT align
;
9137 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9138 /* ??? Consider using mergable sdata sections. */
9141 default_elf_select_rtx_section (mode
, x
, align
);
9144 #endif /* OBJECT_FORMAT_ELF */
9146 /* Structure to collect function names for final output in link section. */
9147 /* Note that items marked with GTY can't be ifdef'ed out. */
9149 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9150 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9152 struct alpha_links
GTY(())
9156 enum links_kind lkind
;
9157 enum reloc_kind rkind
;
9160 struct alpha_funcs
GTY(())
9163 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9167 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9168 splay_tree alpha_links_tree
;
9169 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9170 splay_tree alpha_funcs_tree
;
9172 static GTY(()) int alpha_funcs_num
;
9174 #if TARGET_ABI_OPEN_VMS
9176 /* Return the VMS argument type corresponding to MODE. */
9179 alpha_arg_type (mode
)
9180 enum machine_mode mode
;
9185 return TARGET_FLOAT_VAX
? FF
: FS
;
9187 return TARGET_FLOAT_VAX
? FD
: FT
;
9193 /* Return an rtx for an integer representing the VMS Argument Information
9197 alpha_arg_info_reg_val (cum
)
9198 CUMULATIVE_ARGS cum
;
9200 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9203 for (i
= 0; i
< 6; i
++)
9204 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9206 return GEN_INT (regval
);
9209 /* Make (or fake) .linkage entry for function call.
9211 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9213 Return an SYMBOL_REF rtx for the linkage. */
9216 alpha_need_linkage (name
, is_local
)
9220 splay_tree_node node
;
9221 struct alpha_links
*al
;
9228 struct alpha_funcs
*cfaf
;
9230 if (!alpha_funcs_tree
)
9231 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9232 splay_tree_compare_pointers
);
9234 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9237 cfaf
->num
= ++alpha_funcs_num
;
9239 splay_tree_insert (alpha_funcs_tree
,
9240 (splay_tree_key
) current_function_decl
,
9241 (splay_tree_value
) cfaf
);
9244 if (alpha_links_tree
)
9246 /* Is this name already defined? */
9248 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9251 al
= (struct alpha_links
*) node
->value
;
9254 /* Defined here but external assumed. */
9255 if (al
->lkind
== KIND_EXTERN
)
9256 al
->lkind
= KIND_LOCAL
;
9260 /* Used here but unused assumed. */
9261 if (al
->lkind
== KIND_UNUSED
)
9262 al
->lkind
= KIND_LOCAL
;
9268 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9270 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9271 name
= ggc_strdup (name
);
9273 /* Assume external if no definition. */
9274 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9276 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9277 get_identifier (name
);
9279 /* Construct a SYMBOL_REF for us to call. */
9281 size_t name_len
= strlen (name
);
9282 char *linksym
= alloca (name_len
+ 6);
9284 memcpy (linksym
+ 1, name
, name_len
);
9285 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9286 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9287 ggc_alloc_string (linksym
, name_len
+ 5));
9290 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9291 (splay_tree_value
) al
);
9297 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9303 splay_tree_node cfunnode
;
9304 struct alpha_funcs
*cfaf
;
9305 struct alpha_links
*al
;
9306 const char *name
= XSTR (linkage
, 0);
9308 cfaf
= (struct alpha_funcs
*) 0;
9309 al
= (struct alpha_links
*) 0;
9311 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9312 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9316 splay_tree_node lnode
;
9318 /* Is this name already defined? */
9320 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9322 al
= (struct alpha_links
*) lnode
->value
;
9325 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9333 splay_tree_node node
= 0;
9334 struct alpha_links
*anl
;
9339 name_len
= strlen (name
);
9341 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9342 al
->num
= cfaf
->num
;
9344 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9347 anl
= (struct alpha_links
*) node
->value
;
9348 al
->lkind
= anl
->lkind
;
9351 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9352 buflen
= strlen (buf
);
9353 linksym
= alloca (buflen
+ 1);
9354 memcpy (linksym
, buf
, buflen
+ 1);
9356 al
->linkage
= gen_rtx_SYMBOL_REF
9357 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9359 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9360 (splay_tree_value
) al
);
9364 al
->rkind
= KIND_CODEADDR
;
9366 al
->rkind
= KIND_LINKAGE
;
9369 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9375 alpha_write_one_linkage (node
, data
)
9376 splay_tree_node node
;
9379 const char *const name
= (const char *) node
->key
;
9380 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9381 FILE *stream
= (FILE *) data
;
9383 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9384 if (link
->rkind
== KIND_CODEADDR
)
9386 if (link
->lkind
== KIND_LOCAL
)
9388 /* Local and used */
9389 fprintf (stream
, "\t.quad %s..en\n", name
);
9393 /* External and used, request code address. */
9394 fprintf (stream
, "\t.code_address %s\n", name
);
9399 if (link
->lkind
== KIND_LOCAL
)
9401 /* Local and used, build linkage pair. */
9402 fprintf (stream
, "\t.quad %s..en\n", name
);
9403 fprintf (stream
, "\t.quad %s\n", name
);
9407 /* External and used, request linkage pair. */
9408 fprintf (stream
, "\t.linkage %s\n", name
);
9416 alpha_write_linkage (stream
, funname
, fundecl
)
9418 const char *funname
;
9421 splay_tree_node node
;
9422 struct alpha_funcs
*func
;
9425 fprintf (stream
, "\t.align 3\n");
9426 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9427 func
= (struct alpha_funcs
*) node
->value
;
9429 fputs ("\t.name ", stream
);
9430 assemble_name (stream
, funname
);
9431 fputs ("..na\n", stream
);
9432 ASM_OUTPUT_LABEL (stream
, funname
);
9433 fprintf (stream
, "\t.pdesc ");
9434 assemble_name (stream
, funname
);
9435 fprintf (stream
, "..en,%s\n",
9436 alpha_procedure_type
== PT_STACK
? "stack"
9437 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9441 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9442 /* splay_tree_delete (func->links); */
9446 /* Given a decl, a section name, and whether the decl initializer
9447 has relocs, choose attributes for the section. */
9449 #define SECTION_VMS_OVERLAY SECTION_FORGET
9450 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9451 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9454 vms_section_type_flags (decl
, name
, reloc
)
9459 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9461 if (decl
&& DECL_ATTRIBUTES (decl
)
9462 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9463 flags
|= SECTION_VMS_OVERLAY
;
9464 if (decl
&& DECL_ATTRIBUTES (decl
)
9465 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9466 flags
|= SECTION_VMS_GLOBAL
;
9467 if (decl
&& DECL_ATTRIBUTES (decl
)
9468 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9469 flags
|= SECTION_VMS_INITIALIZE
;
9474 /* Switch to an arbitrary section NAME with attributes as specified
9475 by FLAGS. ALIGN specifies any known alignment requirements for
9476 the section; 0 if the default should be used. */
9479 vms_asm_named_section (name
, flags
)
9483 fputc ('\n', asm_out_file
);
9484 fprintf (asm_out_file
, ".section\t%s", name
);
9486 if (flags
& SECTION_VMS_OVERLAY
)
9487 fprintf (asm_out_file
, ",OVR");
9488 if (flags
& SECTION_VMS_GLOBAL
)
9489 fprintf (asm_out_file
, ",GBL");
9490 if (flags
& SECTION_VMS_INITIALIZE
)
9491 fprintf (asm_out_file
, ",NOMOD");
9492 if (flags
& SECTION_DEBUG
)
9493 fprintf (asm_out_file
, ",NOWRT");
9495 fputc ('\n', asm_out_file
);
9498 /* Record an element in the table of global constructors. SYMBOL is
9499 a SYMBOL_REF of the function to be called; PRIORITY is a number
9500 between 0 and MAX_INIT_PRIORITY.
9502 Differs from default_ctors_section_asm_out_constructor in that the
9503 width of the .ctors entry is always 64 bits, rather than the 32 bits
9504 used by a normal pointer. */
9507 vms_asm_out_constructor (symbol
, priority
)
9509 int priority ATTRIBUTE_UNUSED
;
9512 assemble_align (BITS_PER_WORD
);
9513 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9517 vms_asm_out_destructor (symbol
, priority
)
9519 int priority ATTRIBUTE_UNUSED
;
9522 assemble_align (BITS_PER_WORD
);
9523 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9528 alpha_need_linkage (name
, is_local
)
9529 const char *name ATTRIBUTE_UNUSED
;
9530 int is_local ATTRIBUTE_UNUSED
;
9536 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9537 rtx linkage ATTRIBUTE_UNUSED
;
9538 tree cfundecl ATTRIBUTE_UNUSED
;
9539 int lflag ATTRIBUTE_UNUSED
;
9540 int rflag ATTRIBUTE_UNUSED
;
9545 #endif /* TARGET_ABI_OPEN_VMS */
9547 #if TARGET_ABI_UNICOSMK
9549 static void unicosmk_output_module_name
PARAMS ((FILE *));
9550 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9551 static void unicosmk_output_dex
PARAMS ((FILE *));
9552 static void unicosmk_output_externs
PARAMS ((FILE *));
9553 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9554 static const char *unicosmk_ssib_name
PARAMS ((void));
9555 static int unicosmk_special_name
PARAMS ((const char *));
9557 /* Define the offset between two registers, one to be eliminated, and the
9558 other its replacement, at the start of a routine. */
9561 unicosmk_initial_elimination_offset (from
, to
)
9567 fixed_size
= alpha_sa_size();
9568 if (fixed_size
!= 0)
9571 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9573 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9575 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9576 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9577 + ALPHA_ROUND (get_frame_size()));
9578 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9579 return (ALPHA_ROUND (fixed_size
)
9580 + ALPHA_ROUND (get_frame_size()
9581 + current_function_outgoing_args_size
));
9586 /* Output the module name for .ident and .end directives. We have to strip
9587 directories and add make sure that the module name starts with a letter
9591 unicosmk_output_module_name (file
)
9596 /* Strip directories. */
9598 name
= strrchr (main_input_filename
, '/');
9602 name
= main_input_filename
;
9604 /* CAM only accepts module names that start with a letter or '$'. We
9605 prefix the module name with a '$' if necessary. */
9607 if (!ISALPHA (*name
))
9609 output_clean_symbol_name (file
, name
);
9612 /* Output text that to appear at the beginning of an assembler file. */
9615 unicosmk_asm_file_start (file
)
9620 fputs ("\t.ident\t", file
);
9621 unicosmk_output_module_name (file
);
9622 fputs ("\n\n", file
);
9624 /* The Unicos/Mk assembler uses different register names. Instead of trying
9625 to support them, we simply use micro definitions. */
9627 /* CAM has different register names: rN for the integer register N and fN
9628 for the floating-point register N. Instead of trying to use these in
9629 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9632 for (i
= 0; i
< 32; ++i
)
9633 fprintf (file
, "$%d <- r%d\n", i
, i
);
9635 for (i
= 0; i
< 32; ++i
)
9636 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9640 /* The .align directive fill unused space with zeroes which does not work
9641 in code sections. We define the macro 'gcc@code@align' which uses nops
9642 instead. Note that it assumes that code sections always have the
9643 biggest possible alignment since . refers to the current offset from
9644 the beginning of the section. */
9646 fputs ("\t.macro gcc@code@align n\n", file
);
9647 fputs ("gcc@n@bytes = 1 << n\n", file
);
9648 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9649 fputs ("\t.if ne, gcc@here, 0\n", file
);
9650 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9651 fputs ("\tbis r31,r31,r31\n", file
);
9652 fputs ("\t.endr\n", file
);
9653 fputs ("\t.endif\n", file
);
9654 fputs ("\t.endm gcc@code@align\n\n", file
);
9656 /* Output extern declarations which should always be visible. */
9657 unicosmk_output_default_externs (file
);
9659 /* Open a dummy section. We always need to be inside a section for the
9660 section-switching code to work correctly.
9661 ??? This should be a module id or something like that. I still have to
9662 figure out what the rules for those are. */
9663 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9666 /* Output text to appear at the end of an assembler file. This includes all
9667 pending extern declarations and DEX expressions. */
9670 unicosmk_file_end ()
9672 fputs ("\t.endp\n\n", asm_out_file
);
9674 /* Output all pending externs. */
9676 unicosmk_output_externs (asm_out_file
);
9678 /* Output dex definitions used for functions whose names conflict with
9681 unicosmk_output_dex (asm_out_file
);
9683 fputs ("\t.end\t", asm_out_file
);
9684 unicosmk_output_module_name (asm_out_file
);
9685 putc ('\n', asm_out_file
);
9688 /* Output the definition of a common variable. */
9691 unicosmk_output_common (file
, name
, size
, align
)
9698 printf ("T3E__: common %s\n", name
);
9701 fputs("\t.endp\n\n\t.psect ", file
);
9702 assemble_name(file
, name
);
9703 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9704 fprintf(file
, "\t.byte\t0:%d\n", size
);
9706 /* Mark the symbol as defined in this module. */
9707 name_tree
= get_identifier (name
);
9708 TREE_ASM_WRITTEN (name_tree
) = 1;
9711 #define SECTION_PUBLIC SECTION_MACH_DEP
9712 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9713 static int current_section_align
;
9716 unicosmk_section_type_flags (decl
, name
, reloc
)
9719 int reloc ATTRIBUTE_UNUSED
;
9721 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9726 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9728 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9729 if (align_functions_log
> current_section_align
)
9730 current_section_align
= align_functions_log
;
9732 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9733 flags
|= SECTION_MAIN
;
9736 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9738 if (TREE_PUBLIC (decl
))
9739 flags
|= SECTION_PUBLIC
;
9744 /* Generate a section name for decl and associate it with the
9748 unicosmk_unique_section (decl
, reloc
)
9750 int reloc ATTRIBUTE_UNUSED
;
9758 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9759 name
= default_strip_name_encoding (name
);
9760 len
= strlen (name
);
9762 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9766 /* It is essential that we prefix the section name here because
9767 otherwise the section names generated for constructors and
9768 destructors confuse collect2. */
9770 string
= alloca (len
+ 6);
9771 sprintf (string
, "code@%s", name
);
9772 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9774 else if (TREE_PUBLIC (decl
))
9775 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9780 string
= alloca (len
+ 6);
9781 sprintf (string
, "data@%s", name
);
9782 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9786 /* Switch to an arbitrary section NAME with attributes as specified
9787 by FLAGS. ALIGN specifies any known alignment requirements for
9788 the section; 0 if the default should be used. */
9791 unicosmk_asm_named_section (name
, flags
)
9797 /* Close the previous section. */
9799 fputs ("\t.endp\n\n", asm_out_file
);
9801 /* Find out what kind of section we are opening. */
9803 if (flags
& SECTION_MAIN
)
9804 fputs ("\t.start\tmain\n", asm_out_file
);
9806 if (flags
& SECTION_CODE
)
9808 else if (flags
& SECTION_PUBLIC
)
9813 if (current_section_align
!= 0)
9814 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9815 current_section_align
, kind
);
9817 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9821 unicosmk_insert_attributes (decl
, attr_ptr
)
9823 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9826 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9827 unicosmk_unique_section (decl
, 0);
9830 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9831 in code sections because .align fill unused space with zeroes. */
9834 unicosmk_output_align (file
, align
)
9838 if (inside_function
)
9839 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9841 fprintf (file
, "\t.align\t%d\n", align
);
9844 /* Add a case vector to the current function's list of deferred case
9845 vectors. Case vectors have to be put into a separate section because CAM
9846 does not allow data definitions in code sections. */
9849 unicosmk_defer_case_vector (lab
, vec
)
9853 struct machine_function
*machine
= cfun
->machine
;
9855 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9856 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9857 machine
->addr_list
);
9860 /* Output a case vector. */
9863 unicosmk_output_addr_vec (file
, vec
)
9867 rtx lab
= XEXP (vec
, 0);
9868 rtx body
= XEXP (vec
, 1);
9869 int vlen
= XVECLEN (body
, 0);
9872 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9874 for (idx
= 0; idx
< vlen
; idx
++)
9876 ASM_OUTPUT_ADDR_VEC_ELT
9877 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9881 /* Output current function's deferred case vectors. */
9884 unicosmk_output_deferred_case_vectors (file
)
9887 struct machine_function
*machine
= cfun
->machine
;
9890 if (machine
->addr_list
== NULL_RTX
)
9894 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9895 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9898 /* Set up the dynamic subprogram information block (DSIB) and update the
9899 frame pointer register ($15) for subroutines which have a frame. If the
9900 subroutine doesn't have a frame, simply increment $15. */
9903 unicosmk_gen_dsib (imaskP
)
9904 unsigned long * imaskP
;
9906 if (alpha_procedure_type
== PT_STACK
)
9908 const char *ssib_name
;
9911 /* Allocate 64 bytes for the DSIB. */
9913 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9915 emit_insn (gen_blockage ());
9917 /* Save the return address. */
9919 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9920 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9921 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9922 (*imaskP
) &= ~(1UL << REG_RA
);
9924 /* Save the old frame pointer. */
9926 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9927 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9928 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9929 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9931 emit_insn (gen_blockage ());
9933 /* Store the SSIB pointer. */
9935 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9936 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9937 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9939 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9940 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9941 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9943 /* Save the CIW index. */
9945 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9946 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9947 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9949 emit_insn (gen_blockage ());
9951 /* Set the new frame pointer. */
9953 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9954 stack_pointer_rtx
, GEN_INT (64))));
9959 /* Increment the frame pointer register to indicate that we do not
9962 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9963 hard_frame_pointer_rtx
, GEN_INT (1))));
9967 #define SSIB_PREFIX "__SSIB_"
9968 #define SSIB_PREFIX_LEN 7
9970 /* Generate the name of the SSIB section for the current function. */
9973 unicosmk_ssib_name ()
9975 /* This is ok since CAM won't be able to deal with names longer than that
9978 static char name
[256];
9984 x
= DECL_RTL (cfun
->decl
);
9985 if (GET_CODE (x
) != MEM
)
9988 if (GET_CODE (x
) != SYMBOL_REF
)
9990 fnname
= XSTR (x
, 0);
9992 len
= strlen (fnname
);
9993 if (len
+ SSIB_PREFIX_LEN
> 255)
9994 len
= 255 - SSIB_PREFIX_LEN
;
9996 strcpy (name
, SSIB_PREFIX
);
9997 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9998 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10003 /* Output the static subroutine information block for the current
10007 unicosmk_output_ssib (file
, fnname
)
10009 const char *fnname
;
10015 struct machine_function
*machine
= cfun
->machine
;
10018 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10019 unicosmk_ssib_name ());
10021 /* Some required stuff and the function name length. */
10023 len
= strlen (fnname
);
10024 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10027 ??? We don't do that yet. */
10029 fputs ("\t.quad\t0\n", file
);
10031 /* Function address. */
10033 fputs ("\t.quad\t", file
);
10034 assemble_name (file
, fnname
);
10037 fputs ("\t.quad\t0\n", file
);
10038 fputs ("\t.quad\t0\n", file
);
10041 ??? We do it the same way Cray CC does it but this could be
10044 for( i
= 0; i
< len
; i
++ )
10045 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10046 if( (len
% 8) == 0 )
10047 fputs ("\t.quad\t0\n", file
);
10049 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10051 /* All call information words used in the function. */
10053 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10056 #if HOST_BITS_PER_WIDE_INT == 32
10057 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
10058 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10060 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
10065 /* Add a call information word (CIW) to the list of the current function's
10066 CIWs and return its index.
10068 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10071 unicosmk_add_call_info_word (x
)
10075 struct machine_function
*machine
= cfun
->machine
;
10077 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10078 if (machine
->first_ciw
== NULL_RTX
)
10079 machine
->first_ciw
= node
;
10081 XEXP (machine
->last_ciw
, 1) = node
;
10083 machine
->last_ciw
= node
;
10084 ++machine
->ciw_count
;
10086 return GEN_INT (machine
->ciw_count
10087 + strlen (current_function_name
)/8 + 5);
10090 static char unicosmk_section_buf
[100];
10093 unicosmk_text_section ()
10095 static int count
= 0;
10096 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
10098 return unicosmk_section_buf
;
10102 unicosmk_data_section ()
10104 static int count
= 1;
10105 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
10107 return unicosmk_section_buf
;
10110 /* The Cray assembler doesn't accept extern declarations for symbols which
10111 are defined in the same file. We have to keep track of all global
10112 symbols which are referenced and/or defined in a source file and output
10113 extern declarations for those which are referenced but not defined at
10114 the end of file. */
10116 /* List of identifiers for which an extern declaration might have to be
10118 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10120 struct unicosmk_extern_list
10122 struct unicosmk_extern_list
*next
;
10126 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10128 /* Output extern declarations which are required for every asm file. */
10131 unicosmk_output_default_externs (file
)
10134 static const char *const externs
[] =
10135 { "__T3E_MISMATCH" };
10140 n
= ARRAY_SIZE (externs
);
10142 for (i
= 0; i
< n
; i
++)
10143 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10146 /* Output extern declarations for global symbols which are have been
10147 referenced but not defined. */
10150 unicosmk_output_externs (file
)
10153 struct unicosmk_extern_list
*p
;
10154 const char *real_name
;
10158 len
= strlen (user_label_prefix
);
10159 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10161 /* We have to strip the encoding and possibly remove user_label_prefix
10162 from the identifier in order to handle -fleading-underscore and
10163 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10164 real_name
= default_strip_name_encoding (p
->name
);
10165 if (len
&& p
->name
[0] == '*'
10166 && !memcmp (real_name
, user_label_prefix
, len
))
10169 name_tree
= get_identifier (real_name
);
10170 if (! TREE_ASM_WRITTEN (name_tree
))
10172 TREE_ASM_WRITTEN (name_tree
) = 1;
10173 fputs ("\t.extern\t", file
);
10174 assemble_name (file
, p
->name
);
10180 /* Record an extern. */
10183 unicosmk_add_extern (name
)
10186 struct unicosmk_extern_list
*p
;
10188 p
= (struct unicosmk_extern_list
*)
10189 xmalloc (sizeof (struct unicosmk_extern_list
));
10190 p
->next
= unicosmk_extern_head
;
10192 unicosmk_extern_head
= p
;
10195 /* The Cray assembler generates incorrect code if identifiers which
10196 conflict with register names are used as instruction operands. We have
10197 to replace such identifiers with DEX expressions. */
10199 /* Structure to collect identifiers which have been replaced by DEX
10201 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10203 struct unicosmk_dex
{
10204 struct unicosmk_dex
*next
;
10208 /* List of identifiers which have been replaced by DEX expressions. The DEX
10209 number is determined by the position in the list. */
10211 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10213 /* The number of elements in the DEX list. */
10215 static int unicosmk_dex_count
= 0;
10217 /* Check if NAME must be replaced by a DEX expression. */
10220 unicosmk_special_name (name
)
10223 if (name
[0] == '*')
10226 if (name
[0] == '$')
10229 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10234 case '1': case '2':
10235 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10238 return (name
[2] == '\0'
10239 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10242 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10246 /* Return the DEX number if X must be replaced by a DEX expression and 0
10250 unicosmk_need_dex (x
)
10253 struct unicosmk_dex
*dex
;
10257 if (GET_CODE (x
) != SYMBOL_REF
)
10261 if (! unicosmk_special_name (name
))
10264 i
= unicosmk_dex_count
;
10265 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10267 if (! strcmp (name
, dex
->name
))
10272 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10274 dex
->next
= unicosmk_dex_list
;
10275 unicosmk_dex_list
= dex
;
10277 ++unicosmk_dex_count
;
10278 return unicosmk_dex_count
;
10281 /* Output the DEX definitions for this file. */
10284 unicosmk_output_dex (file
)
10287 struct unicosmk_dex
*dex
;
10290 if (unicosmk_dex_list
== NULL
)
10293 fprintf (file
, "\t.dexstart\n");
10295 i
= unicosmk_dex_count
;
10296 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10298 fprintf (file
, "\tDEX (%d) = ", i
);
10299 assemble_name (file
, dex
->name
);
10304 fprintf (file
, "\t.dexend\n");
10310 unicosmk_output_deferred_case_vectors (file
)
10311 FILE *file ATTRIBUTE_UNUSED
;
10315 unicosmk_gen_dsib (imaskP
)
10316 unsigned long * imaskP ATTRIBUTE_UNUSED
;
10320 unicosmk_output_ssib (file
, fnname
)
10321 FILE * file ATTRIBUTE_UNUSED
;
10322 const char * fnname ATTRIBUTE_UNUSED
;
10326 unicosmk_add_call_info_word (x
)
10327 rtx x ATTRIBUTE_UNUSED
;
10333 unicosmk_need_dex (x
)
10334 rtx x ATTRIBUTE_UNUSED
;
10339 #endif /* TARGET_ABI_UNICOSMK */
10341 #include "gt-alpha.h"