1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 /* Specify which cpu to schedule for. */
58 enum processor_type alpha_cpu
;
59 static const char * const alpha_cpu_name
[] =
64 /* Specify how accurate floating-point traps need to be. */
66 enum alpha_trap_precision alpha_tp
;
68 /* Specify the floating-point rounding mode. */
70 enum alpha_fp_rounding_mode alpha_fprm
;
72 /* Specify which things cause traps. */
74 enum alpha_fp_trap_mode alpha_fptm
;
76 /* Specify bit size of immediate TLS offsets. */
78 int alpha_tls_size
= 32;
80 /* Strings decoded into the above options. */
82 const char *alpha_cpu_string
; /* -mcpu= */
83 const char *alpha_tune_string
; /* -mtune= */
84 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
85 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
86 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
87 const char *alpha_mlat_string
; /* -mmemory-latency= */
88 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
90 /* Save information from a "cmpxx" operation until the branch or scc is
93 struct alpha_compare alpha_compare
;
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
98 static int inside_function
= FALSE
;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency
= 3;
104 /* Whether the function needs the GP. */
106 static int alpha_function_needs_gp
;
108 /* The alias set for prologue/epilogue register save/restore. */
110 static GTY(()) int alpha_sr_alias_set
;
112 /* The assembler name of the current function. */
114 static const char *alpha_fnname
;
116 /* The next explicit relocation sequence number. */
117 extern GTY(()) int alpha_next_sequence_number
;
118 int alpha_next_sequence_number
= 1;
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
122 extern GTY(()) int alpha_this_literal_sequence_number
;
123 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
124 int alpha_this_literal_sequence_number
;
125 int alpha_this_gpdisp_sequence_number
;
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
131 unsigned char fp_add
;
132 unsigned char fp_mult
;
133 unsigned char fp_div_sf
;
134 unsigned char fp_div_df
;
135 unsigned char int_mult_si
;
136 unsigned char int_mult_di
;
137 unsigned char int_shift
;
138 unsigned char int_cmov
;
141 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
144 COSTS_N_INSNS (6), /* fp_add */
145 COSTS_N_INSNS (6), /* fp_mult */
146 COSTS_N_INSNS (34), /* fp_div_sf */
147 COSTS_N_INSNS (63), /* fp_div_df */
148 COSTS_N_INSNS (23), /* int_mult_si */
149 COSTS_N_INSNS (23), /* int_mult_di */
150 COSTS_N_INSNS (2), /* int_shift */
151 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (15), /* fp_div_sf */
157 COSTS_N_INSNS (22), /* fp_div_df */
158 COSTS_N_INSNS (8), /* int_mult_si */
159 COSTS_N_INSNS (12), /* int_mult_di */
160 COSTS_N_INSNS (1) + 1, /* int_shift */
161 COSTS_N_INSNS (1), /* int_cmov */
164 COSTS_N_INSNS (4), /* fp_add */
165 COSTS_N_INSNS (4), /* fp_mult */
166 COSTS_N_INSNS (12), /* fp_div_sf */
167 COSTS_N_INSNS (15), /* fp_div_df */
168 COSTS_N_INSNS (7), /* int_mult_si */
169 COSTS_N_INSNS (7), /* int_mult_di */
170 COSTS_N_INSNS (1), /* int_shift */
171 COSTS_N_INSNS (2), /* int_cmov */
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
179 #define NUM_ARGS current_function_args_info
185 /* Declarations of static functions. */
186 static struct machine_function
*alpha_init_machine_status (void);
187 static rtx
alpha_emit_xfloating_compare (enum rtx_code
, rtx
, rtx
);
189 #if TARGET_ABI_OPEN_VMS
190 static void alpha_write_linkage (FILE *, const char *, tree
);
193 static void unicosmk_output_deferred_case_vectors (FILE *);
194 static void unicosmk_gen_dsib (unsigned long *);
195 static void unicosmk_output_ssib (FILE *, const char *);
196 static int unicosmk_need_dex (rtx
);
198 /* Parse target option strings. */
201 override_options (void)
204 static const struct cpu_table
{
205 const char *const name
;
206 const enum processor_type processor
;
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
211 { "ev4", PROCESSOR_EV4
, 0 },
212 { "ev45", PROCESSOR_EV4
, 0 },
213 { "21064", PROCESSOR_EV4
, 0 },
214 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
215 { "21164", PROCESSOR_EV5
, EV5_MASK
},
216 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
217 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
218 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
219 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
220 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
221 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
222 { "21264", PROCESSOR_EV6
, EV6_MASK
},
223 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
224 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
228 /* Unicos/Mk doesn't have shared libraries. */
229 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
231 warning ("-f%s ignored for Unicos/Mk (not supported)",
232 (flag_pic
> 1) ? "PIC" : "pic");
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
238 if (TARGET_ABI_UNICOSMK
)
239 alpha_fprm
= ALPHA_FPRM_DYN
;
241 alpha_fprm
= ALPHA_FPRM_NORM
;
243 alpha_tp
= ALPHA_TP_PROG
;
244 alpha_fptm
= ALPHA_FPTM_N
;
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
254 if (TARGET_ABI_UNICOSMK
)
255 warning ("-mieee not supported on Unicos/Mk");
258 alpha_tp
= ALPHA_TP_INSN
;
259 alpha_fptm
= ALPHA_FPTM_SU
;
263 if (TARGET_IEEE_WITH_INEXACT
)
265 if (TARGET_ABI_UNICOSMK
)
266 warning ("-mieee-with-inexact not supported on Unicos/Mk");
269 alpha_tp
= ALPHA_TP_INSN
;
270 alpha_fptm
= ALPHA_FPTM_SUI
;
276 if (! strcmp (alpha_tp_string
, "p"))
277 alpha_tp
= ALPHA_TP_PROG
;
278 else if (! strcmp (alpha_tp_string
, "f"))
279 alpha_tp
= ALPHA_TP_FUNC
;
280 else if (! strcmp (alpha_tp_string
, "i"))
281 alpha_tp
= ALPHA_TP_INSN
;
283 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
286 if (alpha_fprm_string
)
288 if (! strcmp (alpha_fprm_string
, "n"))
289 alpha_fprm
= ALPHA_FPRM_NORM
;
290 else if (! strcmp (alpha_fprm_string
, "m"))
291 alpha_fprm
= ALPHA_FPRM_MINF
;
292 else if (! strcmp (alpha_fprm_string
, "c"))
293 alpha_fprm
= ALPHA_FPRM_CHOP
;
294 else if (! strcmp (alpha_fprm_string
,"d"))
295 alpha_fprm
= ALPHA_FPRM_DYN
;
297 error ("bad value `%s' for -mfp-rounding-mode switch",
301 if (alpha_fptm_string
)
303 if (strcmp (alpha_fptm_string
, "n") == 0)
304 alpha_fptm
= ALPHA_FPTM_N
;
305 else if (strcmp (alpha_fptm_string
, "u") == 0)
306 alpha_fptm
= ALPHA_FPTM_U
;
307 else if (strcmp (alpha_fptm_string
, "su") == 0)
308 alpha_fptm
= ALPHA_FPTM_SU
;
309 else if (strcmp (alpha_fptm_string
, "sui") == 0)
310 alpha_fptm
= ALPHA_FPTM_SUI
;
312 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
315 if (alpha_tls_size_string
)
317 if (strcmp (alpha_tls_size_string
, "16") == 0)
319 else if (strcmp (alpha_tls_size_string
, "32") == 0)
321 else if (strcmp (alpha_tls_size_string
, "64") == 0)
324 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
328 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
329 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
331 if (alpha_cpu_string
)
333 for (i
= 0; cpu_table
[i
].name
; i
++)
334 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
336 alpha_cpu
= cpu_table
[i
].processor
;
337 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
338 | MASK_CPU_EV5
| MASK_CPU_EV6
);
339 target_flags
|= cpu_table
[i
].flags
;
342 if (! cpu_table
[i
].name
)
343 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
346 if (alpha_tune_string
)
348 for (i
= 0; cpu_table
[i
].name
; i
++)
349 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
351 alpha_cpu
= cpu_table
[i
].processor
;
354 if (! cpu_table
[i
].name
)
355 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
358 /* Do some sanity checks on the above options. */
360 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
362 warning ("trap mode not supported on Unicos/Mk");
363 alpha_fptm
= ALPHA_FPTM_N
;
366 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
367 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
369 warning ("fp software completion requires -mtrap-precision=i");
370 alpha_tp
= ALPHA_TP_INSN
;
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
378 alpha_tp
= ALPHA_TP_PROG
;
381 if (TARGET_FLOAT_VAX
)
383 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
385 warning ("rounding mode not supported for VAX floats");
386 alpha_fprm
= ALPHA_FPRM_NORM
;
388 if (alpha_fptm
== ALPHA_FPTM_SUI
)
390 warning ("trap mode not supported for VAX floats");
391 alpha_fptm
= ALPHA_FPTM_SU
;
399 if (!alpha_mlat_string
)
400 alpha_mlat_string
= "L1";
402 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
403 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
405 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
406 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
407 && alpha_mlat_string
[2] == '\0')
409 static int const cache_latency
[][4] =
411 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
412 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
413 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
416 lat
= alpha_mlat_string
[1] - '0';
417 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
419 warning ("L%d cache latency unknown for %s",
420 lat
, alpha_cpu_name
[alpha_cpu
]);
424 lat
= cache_latency
[alpha_cpu
][lat
-1];
426 else if (! strcmp (alpha_mlat_string
, "main"))
428 /* Most current memories have about 370ns latency. This is
429 a reasonable guess for a fast cpu. */
434 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
438 alpha_memory_latency
= lat
;
441 /* Default the definition of "small data" to 8 bytes. */
445 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
447 target_flags
|= MASK_SMALL_DATA
;
448 else if (flag_pic
== 2)
449 target_flags
&= ~MASK_SMALL_DATA
;
451 /* Align labels and loops for optimal branching. */
452 /* ??? Kludge these by not doing anything if we don't optimize and also if
453 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
454 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
456 if (align_loops
<= 0)
458 if (align_jumps
<= 0)
461 if (align_functions
<= 0)
462 align_functions
= 16;
464 /* Acquire a unique set number for our register saves and restores. */
465 alpha_sr_alias_set
= new_alias_set ();
467 /* Register variables and functions with the garbage collector. */
469 /* Set up function hooks. */
470 init_machine_status
= alpha_init_machine_status
;
472 /* Tell the compiler when we're using VAX floating point. */
473 if (TARGET_FLOAT_VAX
)
475 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
476 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
477 REAL_MODE_FORMAT (TFmode
) = NULL
;
481 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
484 zap_mask (HOST_WIDE_INT value
)
488 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
490 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
496 /* Returns 1 if OP is either the constant zero or a register. If a
497 register, it must be in the proper mode unless MODE is VOIDmode. */
500 reg_or_0_operand (rtx op
, enum machine_mode mode
)
502 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
505 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
509 reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
511 return ((GET_CODE (op
) == CONST_INT
512 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
513 || register_operand (op
, mode
));
517 /* Return 1 if OP is an 8-bit constant or any register. */
520 reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
522 return ((GET_CODE (op
) == CONST_INT
523 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
524 || register_operand (op
, mode
));
527 /* Return 1 if OP is a constant or any register. */
530 reg_or_const_int_operand (rtx op
, enum machine_mode mode
)
532 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
535 /* Return 1 if OP is an 8-bit constant. */
538 cint8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
540 return ((GET_CODE (op
) == CONST_INT
541 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
544 /* Return 1 if the operand is a valid second operand to an add insn. */
547 add_operand (rtx op
, enum machine_mode mode
)
549 if (GET_CODE (op
) == CONST_INT
)
550 /* Constraints I, J, O and P are covered by K. */
551 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
552 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
554 return register_operand (op
, mode
);
557 /* Return 1 if the operand is a valid second operand to a sign-extending
561 sext_add_operand (rtx op
, enum machine_mode mode
)
563 if (GET_CODE (op
) == CONST_INT
)
564 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
565 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
567 return reg_not_elim_operand (op
, mode
);
570 /* Return 1 if OP is the constant 4 or 8. */
573 const48_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
575 return (GET_CODE (op
) == CONST_INT
576 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
579 /* Return 1 if OP is a valid first operand to an AND insn. */
582 and_operand (rtx op
, enum machine_mode mode
)
584 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
585 return (zap_mask (CONST_DOUBLE_LOW (op
))
586 && zap_mask (CONST_DOUBLE_HIGH (op
)));
588 if (GET_CODE (op
) == CONST_INT
)
589 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
590 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
591 || zap_mask (INTVAL (op
)));
593 return register_operand (op
, mode
);
596 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
599 or_operand (rtx op
, enum machine_mode mode
)
601 if (GET_CODE (op
) == CONST_INT
)
602 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
603 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
605 return register_operand (op
, mode
);
608 /* Return 1 if OP is a constant that is the width, in bits, of an integral
609 mode smaller than DImode. */
612 mode_width_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
614 return (GET_CODE (op
) == CONST_INT
615 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
616 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
619 /* Return 1 if OP is a constant that is the width of an integral machine mode
620 smaller than an integer. */
623 mode_mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
625 if (GET_CODE (op
) == CONST_INT
)
627 HOST_WIDE_INT value
= INTVAL (op
);
633 if (value
== 0xffffffff)
638 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
640 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
647 /* Return 1 if OP is a multiple of 8 less than 64. */
650 mul8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
652 return (GET_CODE (op
) == CONST_INT
653 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
654 && (INTVAL (op
) & 7) == 0);
657 /* Return 1 if OP is the zero constant for MODE. */
660 const0_operand (rtx op
, enum machine_mode mode
)
662 return op
== CONST0_RTX (mode
);
665 /* Return 1 if OP is a hard floating-point register. */
668 hard_fp_register_operand (rtx op
, enum machine_mode mode
)
670 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
673 if (GET_CODE (op
) == SUBREG
)
674 op
= SUBREG_REG (op
);
675 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
678 /* Return 1 if OP is a hard general register. */
681 hard_int_register_operand (rtx op
, enum machine_mode mode
)
683 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
686 if (GET_CODE (op
) == SUBREG
)
687 op
= SUBREG_REG (op
);
688 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
691 /* Return 1 if OP is a register or a constant integer. */
695 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
697 return (GET_CODE (op
) == CONST_INT
698 || register_operand (op
, mode
));
701 /* Return 1 if OP is something that can be reloaded into a register;
702 if it is a MEM, it need not be valid. */
705 some_operand (rtx op
, enum machine_mode mode
)
707 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
710 switch (GET_CODE (op
))
724 return some_operand (SUBREG_REG (op
), VOIDmode
);
733 /* Likewise, but don't accept constants. */
736 some_ni_operand (rtx op
, enum machine_mode mode
)
738 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
741 if (GET_CODE (op
) == SUBREG
)
742 op
= SUBREG_REG (op
);
744 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
747 /* Return 1 if OP is a valid operand for the source of a move insn. */
750 input_operand (rtx op
, enum machine_mode mode
)
752 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
755 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
758 switch (GET_CODE (op
))
763 if (TARGET_EXPLICIT_RELOCS
)
765 /* We don't split symbolic operands into something unintelligable
766 until after reload, but we do not wish non-small, non-global
767 symbolic operands to be reconstructed from their high/lo_sum
769 return (small_symbolic_operand (op
, mode
)
770 || global_symbolic_operand (op
, mode
)
771 || gotdtp_symbolic_operand (op
, mode
)
772 || gottp_symbolic_operand (op
, mode
));
775 /* This handles both the Windows/NT and OSF cases. */
776 return mode
== ptr_mode
|| mode
== DImode
;
779 return (TARGET_EXPLICIT_RELOCS
780 && local_symbolic_operand (XEXP (op
, 0), mode
));
787 if (register_operand (op
, mode
))
789 /* ... fall through ... */
791 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
792 && general_operand (op
, mode
));
796 return op
== CONST0_RTX (mode
);
799 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
811 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
812 file, and in the same section as the current function. */
815 samegp_function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
817 if (GET_CODE (op
) != SYMBOL_REF
)
820 /* Easy test for recursion. */
821 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
824 /* Functions that are not local can be overridden, and thus may
825 not share the same gp. */
826 if (! SYMBOL_REF_LOCAL_P (op
))
829 /* If -msmall-data is in effect, assume that there is only one GP
830 for the module, and so any local symbol has this property. We
831 need explicit relocations to be able to enforce this for symbols
832 not defined in this unit of translation, however. */
833 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
836 /* Functions that are not external are defined in this UoT,
837 and thus must share the same gp. */
838 return ! SYMBOL_REF_EXTERNAL_P (op
);
841 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
844 direct_call_operand (rtx op
, enum machine_mode mode
)
846 tree op_decl
, cfun_sec
, op_sec
;
848 /* Must share the same GP. */
849 if (!samegp_function_operand (op
, mode
))
852 /* If profiling is implemented via linker tricks, we can't jump
853 to the nogp alternate entry point. Note that current_function_profile
854 would not be correct, since that doesn't indicate if the target
855 function uses profiling. */
856 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
857 but is approximately correct for the OSF ABIs. Don't know
858 what to do for VMS, NT, or UMK. */
859 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
862 /* Must be a function. In some cases folks create thunks in static
863 data structures and then make calls to them. If we allow the
864 direct call, we'll get an error from the linker about !samegp reloc
865 against a symbol without a .prologue directive. */
866 if (!SYMBOL_REF_FUNCTION_P (op
))
869 /* Must be "near" so that the branch is assumed to reach. With
870 -msmall-text, this is assumed true of all local symbols. Since
871 we've already checked samegp, locality is already assured. */
872 if (TARGET_SMALL_TEXT
)
875 /* Otherwise, a decl is "near" if it is defined in the same section. */
876 if (flag_function_sections
)
879 op_decl
= SYMBOL_REF_DECL (op
);
880 if (DECL_ONE_ONLY (current_function_decl
)
881 || (op_decl
&& DECL_ONE_ONLY (op_decl
)))
884 cfun_sec
= DECL_SECTION_NAME (current_function_decl
);
885 op_sec
= op_decl
? DECL_SECTION_NAME (op_decl
) : NULL
;
886 return ((!cfun_sec
&& !op_sec
)
887 || (cfun_sec
&& op_sec
888 && strcmp (TREE_STRING_POINTER (cfun_sec
),
889 TREE_STRING_POINTER (op_sec
)) == 0));
892 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
893 a (non-tls) variable known to be defined in this file. */
896 local_symbolic_operand (rtx op
, enum machine_mode mode
)
898 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
901 if (GET_CODE (op
) == LABEL_REF
)
904 if (GET_CODE (op
) == CONST
905 && GET_CODE (XEXP (op
, 0)) == PLUS
906 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
907 op
= XEXP (XEXP (op
, 0), 0);
909 if (GET_CODE (op
) != SYMBOL_REF
)
912 return SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
915 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
916 known to be defined in this file in the small data area. */
919 small_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
921 if (! TARGET_SMALL_DATA
)
924 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
927 if (GET_CODE (op
) == CONST
928 && GET_CODE (XEXP (op
, 0)) == PLUS
929 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
930 op
= XEXP (XEXP (op
, 0), 0);
932 if (GET_CODE (op
) != SYMBOL_REF
)
935 /* ??? There's no encode_section_info equivalent for the rtl
936 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
937 if (CONSTANT_POOL_ADDRESS_P (op
))
938 return GET_MODE_SIZE (get_pool_mode (op
)) <= g_switch_value
;
940 return (SYMBOL_REF_LOCAL_P (op
)
941 && SYMBOL_REF_SMALL_P (op
)
942 && SYMBOL_REF_TLS_MODEL (op
) == 0);
945 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
946 not known (or known not) to be defined in this file. */
949 global_symbolic_operand (rtx op
, enum machine_mode mode
)
951 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
954 if (GET_CODE (op
) == CONST
955 && GET_CODE (XEXP (op
, 0)) == PLUS
956 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
957 op
= XEXP (XEXP (op
, 0), 0);
959 if (GET_CODE (op
) != SYMBOL_REF
)
962 return !SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
965 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
968 call_operand (rtx op
, enum machine_mode mode
)
973 if (GET_CODE (op
) == REG
)
977 /* Disallow virtual registers to cope with pathological test cases
978 such as compile/930117-1.c in which the virtual reg decomposes
979 to the frame pointer. Which is a hard reg that is not $27. */
980 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
985 if (TARGET_ABI_UNICOSMK
)
987 if (GET_CODE (op
) == SYMBOL_REF
)
993 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
994 possibly with an offset. */
997 symbolic_operand (rtx op
, enum machine_mode mode
)
999 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1001 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1003 if (GET_CODE (op
) == CONST
1004 && GET_CODE (XEXP (op
,0)) == PLUS
1005 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1006 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1011 /* Return true if OP is valid for a particular TLS relocation. */
1014 tls_symbolic_operand_1 (rtx op
, enum machine_mode mode
, int size
, int unspec
)
1016 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1019 if (GET_CODE (op
) != CONST
)
1023 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1025 op
= XVECEXP (op
, 0, 0);
1027 if (GET_CODE (op
) != SYMBOL_REF
)
1030 if (SYMBOL_REF_LOCAL_P (op
))
1032 if (alpha_tls_size
> size
)
1041 switch (SYMBOL_REF_TLS_MODEL (op
))
1043 case TLS_MODEL_LOCAL_DYNAMIC
:
1044 return unspec
== UNSPEC_DTPREL
;
1045 case TLS_MODEL_INITIAL_EXEC
:
1046 return unspec
== UNSPEC_TPREL
&& size
== 64;
1047 case TLS_MODEL_LOCAL_EXEC
:
1048 return unspec
== UNSPEC_TPREL
;
1054 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1057 dtp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1059 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1062 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1065 dtp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1067 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1070 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1073 gotdtp_symbolic_operand (rtx op
, enum machine_mode mode
)
1075 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1078 /* Return true if OP is valid for 16-bit TP relative relocations. */
1081 tp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1083 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1086 /* Return true if OP is valid for 32-bit TP relative relocations. */
1089 tp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1091 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1094 /* Return true if OP is valid for 64-bit TP relative relocations. */
1097 gottp_symbolic_operand (rtx op
, enum machine_mode mode
)
1099 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1102 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1103 comparisons are valid in which insn. */
1106 alpha_comparison_operator (rtx op
, enum machine_mode mode
)
1108 enum rtx_code code
= GET_CODE (op
);
1110 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1113 return (code
== EQ
|| code
== LE
|| code
== LT
1114 || code
== LEU
|| code
== LTU
);
1117 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1118 Here we know which comparisons are valid in which insn. */
1121 alpha_zero_comparison_operator (rtx op
, enum machine_mode mode
)
1123 enum rtx_code code
= GET_CODE (op
);
1125 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1128 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1129 || code
== LEU
|| code
== LTU
);
1132 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1135 alpha_swapped_comparison_operator (rtx op
, enum machine_mode mode
)
1137 enum rtx_code code
= GET_CODE (op
);
1139 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1140 || GET_RTX_CLASS (code
) != '<')
1143 code
= swap_condition (code
);
1144 return (code
== EQ
|| code
== LE
|| code
== LT
1145 || code
== LEU
|| code
== LTU
);
1148 /* Return 1 if OP is a signed comparison operation. */
1151 signed_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1153 enum rtx_code code
= GET_CODE (op
);
1155 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1158 return (code
== EQ
|| code
== NE
1159 || code
== LE
|| code
== LT
1160 || code
== GE
|| code
== GT
);
1163 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1164 Here we know which comparisons are valid in which insn. */
1167 alpha_fp_comparison_operator (rtx op
, enum machine_mode mode
)
1169 enum rtx_code code
= GET_CODE (op
);
1171 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1174 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1177 /* Return 1 if this is a divide or modulus operator. */
1180 divmod_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1182 switch (GET_CODE (op
))
1184 case DIV
: case MOD
: case UDIV
: case UMOD
:
1194 /* Return 1 if this memory address is a known aligned register plus
1195 a constant. It must be a valid address. This means that we can do
1196 this as an aligned reference plus some offset.
1198 Take into account what reload will do. */
1201 aligned_memory_operand (rtx op
, enum machine_mode mode
)
1205 if (reload_in_progress
)
1208 if (GET_CODE (tmp
) == SUBREG
)
1209 tmp
= SUBREG_REG (tmp
);
1210 if (GET_CODE (tmp
) == REG
1211 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1213 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1219 if (GET_CODE (op
) != MEM
1220 || GET_MODE (op
) != mode
)
1224 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1225 sorts of constructs. Dig for the real base register. */
1226 if (reload_in_progress
1227 && GET_CODE (op
) == PLUS
1228 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1229 base
= XEXP (XEXP (op
, 0), 0);
1232 if (! memory_address_p (mode
, op
))
1234 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1237 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1240 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1243 unaligned_memory_operand (rtx op
, enum machine_mode mode
)
1247 if (reload_in_progress
)
1250 if (GET_CODE (tmp
) == SUBREG
)
1251 tmp
= SUBREG_REG (tmp
);
1252 if (GET_CODE (tmp
) == REG
1253 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1255 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1261 if (GET_CODE (op
) != MEM
1262 || GET_MODE (op
) != mode
)
1266 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1267 sorts of constructs. Dig for the real base register. */
1268 if (reload_in_progress
1269 && GET_CODE (op
) == PLUS
1270 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1271 base
= XEXP (XEXP (op
, 0), 0);
1274 if (! memory_address_p (mode
, op
))
1276 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1279 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1282 /* Return 1 if OP is either a register or an unaligned memory location. */
1285 reg_or_unaligned_mem_operand (rtx op
, enum machine_mode mode
)
1287 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1290 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1293 any_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1295 return (GET_CODE (op
) == MEM
1296 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1297 || (reload_in_progress
&& GET_CODE (op
) == REG
1298 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1299 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1300 && GET_CODE (SUBREG_REG (op
)) == REG
1301 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1304 /* Returns 1 if OP is not an eliminable register.
1306 This exists to cure a pathological abort in the s8addq (et al) patterns,
1308 long foo () { long t; bar(); return (long) &t * 26107; }
1310 which run afoul of a hack in reload to cure a (presumably) similar
1311 problem with lea-type instructions on other targets. But there is
1312 one of us and many of them, so work around the problem by selectively
1313 preventing combine from making the optimization. */
1316 reg_not_elim_operand (rtx op
, enum machine_mode mode
)
1319 if (GET_CODE (op
) == SUBREG
)
1320 inner
= SUBREG_REG (op
);
1321 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1324 return register_operand (op
, mode
);
1327 /* Return 1 is OP is a memory location that is not a reference (using
1328 an AND) to an unaligned location. Take into account what reload
1332 normal_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1334 if (reload_in_progress
)
1337 if (GET_CODE (tmp
) == SUBREG
)
1338 tmp
= SUBREG_REG (tmp
);
1339 if (GET_CODE (tmp
) == REG
1340 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1342 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1344 /* This may not have been assigned an equivalent address if it will
1345 be eliminated. In that case, it doesn't matter what we do. */
1351 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1354 /* Accept a register, but not a subreg of any kind. This allows us to
1355 avoid pathological cases in reload wrt data movement common in
1356 int->fp conversion. */
1359 reg_no_subreg_operand (rtx op
, enum machine_mode mode
)
1361 if (GET_CODE (op
) != REG
)
1363 return register_operand (op
, mode
);
1366 /* Recognize an addition operation that includes a constant. Used to
1367 convince reload to canonize (plus (plus reg c1) c2) during register
1371 addition_operation (rtx op
, enum machine_mode mode
)
1373 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1375 if (GET_CODE (op
) == PLUS
1376 && register_operand (XEXP (op
, 0), mode
)
1377 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1378 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1383 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1384 the range defined for C in [I-P]. */
1387 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
1392 /* An unsigned 8 bit constant. */
1393 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1395 /* The constant zero. */
1398 /* A signed 16 bit constant. */
1399 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1401 /* A shifted signed 16 bit constant appropriate for LDAH. */
1402 return ((value
& 0xffff) == 0
1403 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1405 /* A constant that can be AND'ed with using a ZAP insn. */
1406 return zap_mask (value
);
1408 /* A complemented unsigned 8 bit constant. */
1409 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1411 /* A negated unsigned 8 bit constant. */
1412 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1414 /* The constant 1, 2 or 3. */
1415 return value
== 1 || value
== 2 || value
== 3;
1422 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1423 matches for C in [GH]. */
1426 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
1431 /* The floating point zero constant. */
1432 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1433 && value
== CONST0_RTX (GET_MODE (value
)));
1436 /* A valid operand of a ZAP insn. */
1437 return (GET_MODE (value
) == VOIDmode
1438 && zap_mask (CONST_DOUBLE_LOW (value
))
1439 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1446 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1450 alpha_extra_constraint (rtx value
, int c
)
1455 return normal_memory_operand (value
, VOIDmode
);
1457 return direct_call_operand (value
, Pmode
);
1459 return (GET_CODE (value
) == CONST_INT
1460 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1462 return GET_CODE (value
) == HIGH
;
1464 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1466 return (GET_CODE (value
) == CONST_VECTOR
1467 && value
== CONST0_RTX (GET_MODE (value
)));
1473 /* Return 1 if this function can directly return via $26. */
1476 direct_return (void)
1478 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1480 && alpha_sa_size () == 0
1481 && get_frame_size () == 0
1482 && current_function_outgoing_args_size
== 0
1483 && current_function_pretend_args_size
== 0);
1486 /* Return the ADDR_VEC associated with a tablejump insn. */
1489 alpha_tablejump_addr_vec (rtx insn
)
1493 tmp
= JUMP_LABEL (insn
);
1496 tmp
= NEXT_INSN (tmp
);
1499 if (GET_CODE (tmp
) == JUMP_INSN
1500 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1501 return PATTERN (tmp
);
1505 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1508 alpha_tablejump_best_label (rtx insn
)
1510 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1511 rtx best_label
= NULL_RTX
;
1513 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1514 there for edge frequency counts from profile data. */
1518 int n_labels
= XVECLEN (jump_table
, 1);
1519 int best_count
= -1;
1522 for (i
= 0; i
< n_labels
; i
++)
1526 for (j
= i
+ 1; j
< n_labels
; j
++)
1527 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1528 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1531 if (count
> best_count
)
1532 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1536 return best_label
? best_label
: const0_rtx
;
1539 /* Return the TLS model to use for SYMBOL. */
1541 static enum tls_model
1542 tls_symbolic_operand_type (rtx symbol
)
1544 enum tls_model model
;
1546 if (GET_CODE (symbol
) != SYMBOL_REF
)
1548 model
= SYMBOL_REF_TLS_MODEL (symbol
);
1550 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1551 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
1552 model
= TLS_MODEL_INITIAL_EXEC
;
1557 /* Return true if the function DECL will share the same GP as any
1558 function in the current unit of translation. */
1561 decl_has_samegp (tree decl
)
1563 /* Functions that are not local can be overridden, and thus may
1564 not share the same gp. */
1565 if (!(*targetm
.binds_local_p
) (decl
))
1568 /* If -msmall-data is in effect, assume that there is only one GP
1569 for the module, and so any local symbol has this property. We
1570 need explicit relocations to be able to enforce this for symbols
1571 not defined in this unit of translation, however. */
1572 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1575 /* Functions that are not external are defined in this UoT. */
1576 /* ??? Irritatingly, static functions not yet emitted are still
1577 marked "external". Apply this to non-static functions only. */
1578 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1581 /* Return true if EXP should be placed in the small data section. */
1584 alpha_in_small_data_p (tree exp
)
1586 /* We want to merge strings, so we never consider them small data. */
1587 if (TREE_CODE (exp
) == STRING_CST
)
1590 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1592 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1593 if (strcmp (section
, ".sdata") == 0
1594 || strcmp (section
, ".sbss") == 0)
1599 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1601 /* If this is an incomplete type with size 0, then we can't put it
1602 in sdata because it might be too big when completed. */
1603 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
1610 #if TARGET_ABI_OPEN_VMS
1612 alpha_linkage_symbol_p (const char *symname
)
1614 int symlen
= strlen (symname
);
1617 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1622 #define LINKAGE_SYMBOL_REF_P(X) \
1623 ((GET_CODE (X) == SYMBOL_REF \
1624 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1625 || (GET_CODE (X) == CONST \
1626 && GET_CODE (XEXP (X, 0)) == PLUS \
1627 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1628 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1631 /* legitimate_address_p recognizes an RTL expression that is a valid
1632 memory address for an instruction. The MODE argument is the
1633 machine mode for the MEM expression that wants to use this address.
1635 For Alpha, we have either a constant address or the sum of a
1636 register and a constant address, or just a register. For DImode,
1637 any of those forms can be surrounded with an AND that clear the
1638 low-order three bits; this is an "unaligned" access. */
1641 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1643 /* If this is an ldq_u type address, discard the outer AND. */
1645 && GET_CODE (x
) == AND
1646 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1647 && INTVAL (XEXP (x
, 1)) == -8)
1650 /* Discard non-paradoxical subregs. */
1651 if (GET_CODE (x
) == SUBREG
1652 && (GET_MODE_SIZE (GET_MODE (x
))
1653 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1656 /* Unadorned general registers are valid. */
1659 ? STRICT_REG_OK_FOR_BASE_P (x
)
1660 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1663 /* Constant addresses (i.e. +/- 32k) are valid. */
1664 if (CONSTANT_ADDRESS_P (x
))
1667 #if TARGET_ABI_OPEN_VMS
1668 if (LINKAGE_SYMBOL_REF_P (x
))
1672 /* Register plus a small constant offset is valid. */
1673 if (GET_CODE (x
) == PLUS
)
1675 rtx ofs
= XEXP (x
, 1);
1678 /* Discard non-paradoxical subregs. */
1679 if (GET_CODE (x
) == SUBREG
1680 && (GET_MODE_SIZE (GET_MODE (x
))
1681 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1687 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1688 && GET_CODE (ofs
) == CONST_INT
)
1691 ? STRICT_REG_OK_FOR_BASE_P (x
)
1692 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1693 && CONSTANT_ADDRESS_P (ofs
))
1696 else if (GET_CODE (x
) == ADDRESSOF
1697 && GET_CODE (ofs
) == CONST_INT
)
1701 /* If we're managing explicit relocations, LO_SUM is valid, as
1702 are small data symbols. */
1703 else if (TARGET_EXPLICIT_RELOCS
)
1705 if (small_symbolic_operand (x
, Pmode
))
1708 if (GET_CODE (x
) == LO_SUM
)
1710 rtx ofs
= XEXP (x
, 1);
1713 /* Discard non-paradoxical subregs. */
1714 if (GET_CODE (x
) == SUBREG
1715 && (GET_MODE_SIZE (GET_MODE (x
))
1716 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1719 /* Must have a valid base register. */
1722 ? STRICT_REG_OK_FOR_BASE_P (x
)
1723 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1726 /* The symbol must be local. */
1727 if (local_symbolic_operand (ofs
, Pmode
)
1728 || dtp32_symbolic_operand (ofs
, Pmode
)
1729 || tp32_symbolic_operand (ofs
, Pmode
))
1737 /* Build the SYMBOL_REF for __tls_get_addr. */
1739 static GTY(()) rtx tls_get_addr_libfunc
;
1742 get_tls_get_addr (void)
1744 if (!tls_get_addr_libfunc
)
1745 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
1746 return tls_get_addr_libfunc
;
1749 /* Try machine-dependent ways of modifying an illegitimate address
1750 to be legitimate. If we find one, return the new, valid address. */
1753 alpha_legitimize_address (rtx x
, rtx scratch
,
1754 enum machine_mode mode ATTRIBUTE_UNUSED
)
1756 HOST_WIDE_INT addend
;
1758 /* If the address is (plus reg const_int) and the CONST_INT is not a
1759 valid offset, compute the high part of the constant and add it to
1760 the register. Then our address is (plus temp low-part-const). */
1761 if (GET_CODE (x
) == PLUS
1762 && GET_CODE (XEXP (x
, 0)) == REG
1763 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1764 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1766 addend
= INTVAL (XEXP (x
, 1));
1771 /* If the address is (const (plus FOO const_int)), find the low-order
1772 part of the CONST_INT. Then load FOO plus any high-order part of the
1773 CONST_INT into a register. Our address is (plus reg low-part-const).
1774 This is done to reduce the number of GOT entries. */
1776 && GET_CODE (x
) == CONST
1777 && GET_CODE (XEXP (x
, 0)) == PLUS
1778 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1780 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1781 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1785 /* If we have a (plus reg const), emit the load as in (2), then add
1786 the two registers, and finally generate (plus reg low-part-const) as
1789 && GET_CODE (x
) == PLUS
1790 && GET_CODE (XEXP (x
, 0)) == REG
1791 && GET_CODE (XEXP (x
, 1)) == CONST
1792 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1793 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1795 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1796 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1797 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1798 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1802 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1803 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1805 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1807 switch (tls_symbolic_operand_type (x
))
1809 case TLS_MODEL_GLOBAL_DYNAMIC
:
1812 r0
= gen_rtx_REG (Pmode
, 0);
1813 r16
= gen_rtx_REG (Pmode
, 16);
1814 tga
= get_tls_get_addr ();
1815 dest
= gen_reg_rtx (Pmode
);
1816 seq
= GEN_INT (alpha_next_sequence_number
++);
1818 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1819 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1820 insn
= emit_call_insn (insn
);
1821 CONST_OR_PURE_CALL_P (insn
) = 1;
1822 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1824 insn
= get_insns ();
1827 emit_libcall_block (insn
, dest
, r0
, x
);
1830 case TLS_MODEL_LOCAL_DYNAMIC
:
1833 r0
= gen_rtx_REG (Pmode
, 0);
1834 r16
= gen_rtx_REG (Pmode
, 16);
1835 tga
= get_tls_get_addr ();
1836 scratch
= gen_reg_rtx (Pmode
);
1837 seq
= GEN_INT (alpha_next_sequence_number
++);
1839 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1840 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1841 insn
= emit_call_insn (insn
);
1842 CONST_OR_PURE_CALL_P (insn
) = 1;
1843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1845 insn
= get_insns ();
1848 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1849 UNSPEC_TLSLDM_CALL
);
1850 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1852 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1853 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1855 if (alpha_tls_size
== 64)
1857 dest
= gen_reg_rtx (Pmode
);
1858 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1859 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1862 if (alpha_tls_size
== 32)
1864 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1865 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1866 scratch
= gen_reg_rtx (Pmode
);
1867 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1869 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1871 case TLS_MODEL_INITIAL_EXEC
:
1872 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1873 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1874 tp
= gen_reg_rtx (Pmode
);
1875 scratch
= gen_reg_rtx (Pmode
);
1876 dest
= gen_reg_rtx (Pmode
);
1878 emit_insn (gen_load_tp (tp
));
1879 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1880 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1883 case TLS_MODEL_LOCAL_EXEC
:
1884 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1885 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1886 tp
= gen_reg_rtx (Pmode
);
1888 emit_insn (gen_load_tp (tp
));
1889 if (alpha_tls_size
== 32)
1891 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1892 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1893 tp
= gen_reg_rtx (Pmode
);
1894 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1896 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1899 if (local_symbolic_operand (x
, Pmode
))
1901 if (small_symbolic_operand (x
, Pmode
))
1905 if (!no_new_pseudos
)
1906 scratch
= gen_reg_rtx (Pmode
);
1907 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1908 gen_rtx_HIGH (Pmode
, x
)));
1909 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1918 HOST_WIDE_INT low
, high
;
1920 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1922 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1926 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1927 (no_new_pseudos
? scratch
: NULL_RTX
),
1928 1, OPTAB_LIB_WIDEN
);
1930 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1931 (no_new_pseudos
? scratch
: NULL_RTX
),
1932 1, OPTAB_LIB_WIDEN
);
1934 return plus_constant (x
, low
);
1938 /* We do not allow indirect calls to be optimized into sibling calls, nor
1939 can we allow a call to a function with a different GP to be optimized
1943 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1945 /* Can't do indirect tail calls, since we don't know if the target
1946 uses the same GP. */
1950 /* Otherwise, we can make a tail call if the target function shares
1952 return decl_has_samegp (decl
);
1955 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1956 small symbolic operand until after reload. At which point we need
1957 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1958 so that sched2 has the proper dependency information. */
1961 some_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1965 /* Don't re-split. */
1966 if (GET_CODE (x
) == LO_SUM
)
1969 return small_symbolic_operand (x
, Pmode
) != 0;
1973 some_small_symbolic_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1975 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
1979 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1983 /* Don't re-split. */
1984 if (GET_CODE (x
) == LO_SUM
)
1987 if (small_symbolic_operand (x
, Pmode
))
1989 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1998 split_small_symbolic_operand (rtx x
)
2001 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2005 /* Indicate that INSN cannot be duplicated. This is true for any insn
2006 that we've marked with gpdisp relocs, since those have to stay in
2007 1-1 correspondence with one another.
2009 Technically we could copy them if we could set up a mapping from one
2010 sequence number to another, across the set of insns to be duplicated.
2011 This seems overly complicated and error-prone since interblock motion
2012 from sched-ebb could move one of the pair of insns to a different block. */
2015 alpha_cannot_copy_insn_p (rtx insn
)
2019 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2022 if (GET_CODE (insn
) != INSN
)
2024 if (asm_noperands (insn
) >= 0)
2027 pat
= PATTERN (insn
);
2028 if (GET_CODE (pat
) != SET
)
2030 pat
= SET_SRC (pat
);
2031 if (GET_CODE (pat
) == UNSPEC_VOLATILE
)
2033 if (XINT (pat
, 1) == UNSPECV_LDGP1
2034 || XINT (pat
, 1) == UNSPECV_PLDGP2
)
2037 else if (GET_CODE (pat
) == UNSPEC
)
2039 if (XINT (pat
, 1) == UNSPEC_LDGP2
)
2047 /* Try a machine-dependent way of reloading an illegitimate address
2048 operand. If we find one, push the reload and return the new rtx. */
2051 alpha_legitimize_reload_address (rtx x
,
2052 enum machine_mode mode ATTRIBUTE_UNUSED
,
2053 int opnum
, int type
,
2054 int ind_levels ATTRIBUTE_UNUSED
)
2056 /* We must recognize output that we have already generated ourselves. */
2057 if (GET_CODE (x
) == PLUS
2058 && GET_CODE (XEXP (x
, 0)) == PLUS
2059 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2060 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2061 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2063 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2064 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2069 /* We wish to handle large displacements off a base register by
2070 splitting the addend across an ldah and the mem insn. This
2071 cuts number of extra insns needed from 3 to 1. */
2072 if (GET_CODE (x
) == PLUS
2073 && GET_CODE (XEXP (x
, 0)) == REG
2074 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2075 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2076 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2078 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2079 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2081 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2083 /* Check for 32-bit overflow. */
2084 if (high
+ low
!= val
)
2087 /* Reload the high part into a base reg; leave the low part
2088 in the mem directly. */
2089 x
= gen_rtx_PLUS (GET_MODE (x
),
2090 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2094 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2095 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2103 /* Compute a (partial) cost for rtx X. Return true if the complete
2104 cost has been computed, and false if subexpressions should be
2105 scanned. In either case, *TOTAL contains the cost result. */
2108 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2110 enum machine_mode mode
= GET_MODE (x
);
2111 bool float_mode_p
= FLOAT_MODE_P (mode
);
2115 /* If this is an 8-bit constant, return zero since it can be used
2116 nearly anywhere with no cost. If it is a valid operand for an
2117 ADD or AND, likewise return 0 if we know it will be used in that
2118 context. Otherwise, return 2 since it might be used there later.
2119 All other constants take at least two insns. */
2121 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2129 if (x
== CONST0_RTX (mode
))
2131 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2132 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2134 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2137 *total
= COSTS_N_INSNS (2);
2143 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2144 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2145 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2146 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2147 else if (tls_symbolic_operand_type (x
))
2148 /* Estimate of cost for call_pal rduniq. */
2149 *total
= COSTS_N_INSNS (15);
2151 /* Otherwise we do a load from the GOT. */
2152 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2158 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2159 else if (GET_CODE (XEXP (x
, 0)) == MULT
2160 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2162 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2163 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2170 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2171 else if (mode
== DImode
)
2172 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2174 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2178 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2179 && INTVAL (XEXP (x
, 1)) <= 3)
2181 *total
= COSTS_N_INSNS (1);
2188 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2193 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2195 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2203 *total
= COSTS_N_INSNS (70); /* ??? */
2204 else if (mode
== SFmode
)
2205 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2207 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2211 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2217 *total
= COSTS_N_INSNS (1);
2225 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2231 case UNSIGNED_FLOAT
:
2235 case FLOAT_TRUNCATE
:
2236 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2244 /* REF is an alignable memory location. Place an aligned SImode
2245 reference into *PALIGNED_MEM and the number of bits to shift into
2246 *PBITNUM. SCRATCH is a free register for use in reloading out
2247 of range stack slots. */
2250 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
2253 HOST_WIDE_INT offset
= 0;
2255 if (GET_CODE (ref
) != MEM
)
2258 if (reload_in_progress
2259 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2261 base
= find_replacement (&XEXP (ref
, 0));
2263 if (! memory_address_p (GET_MODE (ref
), base
))
2268 base
= XEXP (ref
, 0);
2271 if (GET_CODE (base
) == PLUS
)
2272 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2275 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2277 if (WORDS_BIG_ENDIAN
)
2278 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2279 + (offset
& 3) * 8));
2281 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2284 /* Similar, but just get the address. Handle the two reload cases.
2285 Add EXTRA_OFFSET to the address we return. */
2288 get_unaligned_address (rtx ref
, int extra_offset
)
2291 HOST_WIDE_INT offset
= 0;
2293 if (GET_CODE (ref
) != MEM
)
2296 if (reload_in_progress
2297 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2299 base
= find_replacement (&XEXP (ref
, 0));
2301 if (! memory_address_p (GET_MODE (ref
), base
))
2306 base
= XEXP (ref
, 0);
2309 if (GET_CODE (base
) == PLUS
)
2310 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2312 return plus_constant (base
, offset
+ extra_offset
);
2315 /* On the Alpha, all (non-symbolic) constants except zero go into
2316 a floating-point register via memory. Note that we cannot
2317 return anything that is not a subset of CLASS, and that some
2318 symbolic constants cannot be dropped to memory. */
2321 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
2323 /* Zero is present in any register class. */
2324 if (x
== CONST0_RTX (GET_MODE (x
)))
2327 /* These sorts of constants we can easily drop to memory. */
2328 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2330 if (class == FLOAT_REGS
)
2332 if (class == ALL_REGS
)
2333 return GENERAL_REGS
;
2337 /* All other kinds of constants should not (and in the case of HIGH
2338 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2339 secondary reload. */
2341 return (class == ALL_REGS
? GENERAL_REGS
: class);
2346 /* Loading and storing HImode or QImode values to and from memory
2347 usually requires a scratch register. The exceptions are loading
2348 QImode and HImode from an aligned address to a general register
2349 unless byte instructions are permitted.
2351 We also cannot load an unaligned address or a paradoxical SUBREG
2352 into an FP register.
2354 We also cannot do integral arithmetic into FP regs, as might result
2355 from register elimination into a DImode fp register. */
2358 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
2361 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2363 if (GET_CODE (x
) == MEM
2364 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2365 || (GET_CODE (x
) == SUBREG
2366 && (GET_CODE (SUBREG_REG (x
)) == MEM
2367 || (GET_CODE (SUBREG_REG (x
)) == REG
2368 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2370 if (!in
|| !aligned_memory_operand(x
, mode
))
2371 return GENERAL_REGS
;
2375 if (class == FLOAT_REGS
)
2377 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2378 return GENERAL_REGS
;
2380 if (GET_CODE (x
) == SUBREG
2381 && (GET_MODE_SIZE (GET_MODE (x
))
2382 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2383 return GENERAL_REGS
;
2385 if (in
&& INTEGRAL_MODE_P (mode
)
2386 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2387 return GENERAL_REGS
;
2393 /* Subfunction of the following function. Update the flags of any MEM
2394 found in part of X. */
2397 alpha_set_memflags_1 (rtx x
, int in_struct_p
, int volatile_p
, int unchanging_p
)
2401 switch (GET_CODE (x
))
2407 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2408 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2413 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2418 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2420 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2425 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2426 MEM_VOLATILE_P (x
) = volatile_p
;
2427 RTX_UNCHANGING_P (x
) = unchanging_p
;
2428 /* Sadly, we cannot use alias sets because the extra aliasing
2429 produced by the AND interferes. Given that two-byte quantities
2430 are the only thing we would be able to differentiate anyway,
2431 there does not seem to be any point in convoluting the early
2432 out of the alias check. */
2440 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2441 generated to perform a memory operation, look for any MEMs in either
2442 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2443 volatile flags from REF into each of the MEMs found. If REF is not
2444 a MEM, don't do anything. */
2447 alpha_set_memflags (rtx insn
, rtx ref
)
2449 int in_struct_p
, volatile_p
, unchanging_p
;
2451 if (GET_CODE (ref
) != MEM
)
2454 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2455 volatile_p
= MEM_VOLATILE_P (ref
);
2456 unchanging_p
= RTX_UNCHANGING_P (ref
);
2458 /* This is only called from alpha.md, after having had something
2459 generated from one of the insn patterns. So if everything is
2460 zero, the pattern is already up-to-date. */
2461 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2464 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2467 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2470 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
2471 HOST_WIDE_INT c
, int n
)
2475 /* Use a pseudo if highly optimizing and still generating RTL. */
2477 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2480 /* If this is a sign-extended 32-bit constant, we can do this in at most
2481 three insns, so do it if we have enough insns left. We always have
2482 a sign-extended 32-bit constant when compiling on a narrow machine. */
2484 if (HOST_BITS_PER_WIDE_INT
!= 64
2485 || c
>> 31 == -1 || c
>> 31 == 0)
2487 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2488 HOST_WIDE_INT tmp1
= c
- low
;
2489 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2490 HOST_WIDE_INT extra
= 0;
2492 /* If HIGH will be interpreted as negative but the constant is
2493 positive, we must adjust it to do two ldha insns. */
2495 if ((high
& 0x8000) != 0 && c
>= 0)
2499 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2502 if (c
== low
|| (low
== 0 && extra
== 0))
2504 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2505 but that meant that we can't handle INT_MIN on 32-bit machines
2506 (like NT/Alpha), because we recurse indefinitely through
2507 emit_move_insn to gen_movdi. So instead, since we know exactly
2508 what we want, create it explicitly. */
2511 target
= gen_reg_rtx (mode
);
2512 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2515 else if (n
>= 2 + (extra
!= 0))
2517 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2519 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2520 This means that if we go through expand_binop, we'll try to
2521 generate extensions, etc, which will require new pseudos, which
2522 will fail during some split phases. The SImode add patterns
2523 still exist, but are not named. So build the insns by hand. */
2528 subtarget
= gen_reg_rtx (mode
);
2529 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2530 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2536 target
= gen_reg_rtx (mode
);
2537 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2538 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2544 /* If we couldn't do it that way, try some other methods. But if we have
2545 no instructions left, don't bother. Likewise, if this is SImode and
2546 we can't make pseudos, we can't do anything since the expand_binop
2547 and expand_unop calls will widen and try to make pseudos. */
2549 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2552 /* Next, see if we can load a related constant and then shift and possibly
2553 negate it to get the constant we want. Try this once each increasing
2554 numbers of insns. */
2556 for (i
= 1; i
< n
; i
++)
2558 /* First, see if minus some low bits, we've an easy load of
2561 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2563 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2564 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2565 target
, 0, OPTAB_WIDEN
);
2567 /* Next try complementing. */
2568 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2569 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2571 /* Next try to form a constant and do a left shift. We can do this
2572 if some low-order bits are zero; the exact_log2 call below tells
2573 us that information. The bits we are shifting out could be any
2574 value, but here we'll just try the 0- and sign-extended forms of
2575 the constant. To try to increase the chance of having the same
2576 constant in more than one insn, start at the highest number of
2577 bits to shift, but try all possibilities in case a ZAPNOT will
2580 if ((bits
= exact_log2 (c
& - c
)) > 0)
2581 for (; bits
> 0; bits
--)
2582 if ((temp
= (alpha_emit_set_const
2583 (subtarget
, mode
, c
>> bits
, i
))) != 0
2584 || ((temp
= (alpha_emit_set_const
2586 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2588 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2589 target
, 0, OPTAB_WIDEN
);
2591 /* Now try high-order zero bits. Here we try the shifted-in bits as
2592 all zero and all ones. Be careful to avoid shifting outside the
2593 mode and to avoid shifting outside the host wide int size. */
2594 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2595 confuse the recursive call and set all of the high 32 bits. */
2597 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2598 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2599 for (; bits
> 0; bits
--)
2600 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2602 || ((temp
= (alpha_emit_set_const
2604 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2607 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2608 target
, 1, OPTAB_WIDEN
);
2610 /* Now try high-order 1 bits. We get that with a sign-extension.
2611 But one bit isn't enough here. Be careful to avoid shifting outside
2612 the mode and to avoid shifting outside the host wide int size. */
2614 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2615 - floor_log2 (~ c
) - 2)) > 0)
2616 for (; bits
> 0; bits
--)
2617 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2619 || ((temp
= (alpha_emit_set_const
2621 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2624 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2625 target
, 0, OPTAB_WIDEN
);
2628 #if HOST_BITS_PER_WIDE_INT == 64
2629 /* Finally, see if can load a value into the target that is the same as the
2630 constant except that all bytes that are 0 are changed to be 0xff. If we
2631 can, then we can do a ZAPNOT to obtain the desired constant. */
2634 for (i
= 0; i
< 64; i
+= 8)
2635 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2636 new |= (HOST_WIDE_INT
) 0xff << i
;
2638 /* We are only called for SImode and DImode. If this is SImode, ensure that
2639 we are sign extended to a full word. */
2642 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2644 if (new != c
&& new != -1
2645 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2646 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2647 target
, 0, OPTAB_WIDEN
);
2653 /* Try to output insns to set TARGET equal to the constant C if it can be
2654 done in less than N insns. Do all computations in MODE. Returns the place
2655 where the output has been placed if it can be done and the insns have been
2656 emitted. If it would take more than N insns, zero is returned and no
2657 insns and emitted. */
2660 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
2661 HOST_WIDE_INT c
, int n
)
2664 rtx orig_target
= target
;
2667 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2668 can't load this constant in one insn, do this in DImode. */
2669 if (no_new_pseudos
&& mode
== SImode
2670 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2671 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2673 target
= gen_lowpart (DImode
, target
);
2677 /* Try 1 insn, then 2, then up to N. */
2678 for (i
= 1; i
<= n
; i
++)
2680 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2683 rtx insn
= get_last_insn ();
2684 rtx set
= single_set (insn
);
2685 if (! CONSTANT_P (SET_SRC (set
)))
2686 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2691 /* Allow for the case where we changed the mode of TARGET. */
2692 if (result
== target
)
2693 result
= orig_target
;
2698 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2699 fall back to a straight forward decomposition. We do this to avoid
2700 exponential run times encountered when looking for longer sequences
2701 with alpha_emit_set_const. */
2704 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2706 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2708 /* Decompose the entire word */
2709 #if HOST_BITS_PER_WIDE_INT >= 64
2710 if (c2
!= -(c1
< 0))
2712 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2714 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2715 c1
= (c1
- d2
) >> 32;
2716 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2718 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2722 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2724 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2728 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2730 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2735 /* Construct the high word */
2738 emit_move_insn (target
, GEN_INT (d4
));
2740 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2743 emit_move_insn (target
, GEN_INT (d3
));
2745 /* Shift it into place */
2746 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2748 /* Add in the low bits. */
2750 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2752 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2757 /* Expand a move instruction; return true if all work is done.
2758 We don't handle non-bwx subword loads here. */
2761 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2763 /* If the output is not a register, the input must be. */
2764 if (GET_CODE (operands
[0]) == MEM
2765 && ! reg_or_0_operand (operands
[1], mode
))
2766 operands
[1] = force_reg (mode
, operands
[1]);
2768 /* Allow legitimize_address to perform some simplifications. */
2769 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2773 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2774 compiled at the end of compilation. In the meantime, someone can
2775 re-encode-section-info on some symbol changing it e.g. from global
2776 to local-not-small. If this happens, we'd have emitted a plain
2777 load rather than a high+losum load and not recognize the insn.
2779 So if rtl inlining is in effect, we delay the global/not-global
2780 decision until rest_of_compilation by wrapping it in an
2782 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2783 && rtx_equal_function_value_matters
2784 && global_symbolic_operand (operands
[1], mode
))
2786 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2790 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2793 if (tmp
== operands
[0])
2800 /* Early out for non-constants and valid constants. */
2801 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2804 /* Split large integers. */
2805 if (GET_CODE (operands
[1]) == CONST_INT
2806 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2808 HOST_WIDE_INT i0
, i1
;
2809 rtx temp
= NULL_RTX
;
2811 if (GET_CODE (operands
[1]) == CONST_INT
)
2813 i0
= INTVAL (operands
[1]);
2816 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2818 i0
= CONST_DOUBLE_LOW (operands
[1]);
2823 i0
= CONST_DOUBLE_LOW (operands
[1]);
2824 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2827 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2828 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2830 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2831 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2835 if (rtx_equal_p (operands
[0], temp
))
2842 /* Otherwise we've nothing left but to drop the thing to memory. */
2843 operands
[1] = force_const_mem (mode
, operands
[1]);
2844 if (reload_in_progress
)
2846 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2847 operands
[1] = copy_rtx (operands
[1]);
2848 XEXP (operands
[1], 0) = operands
[0];
2851 operands
[1] = validize_mem (operands
[1]);
2855 /* Expand a non-bwx QImode or HImode move instruction;
2856 return true if all work is done. */
2859 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2861 /* If the output is not a register, the input must be. */
2862 if (GET_CODE (operands
[0]) == MEM
)
2863 operands
[1] = force_reg (mode
, operands
[1]);
2865 /* Handle four memory cases, unaligned and aligned for either the input
2866 or the output. The only case where we can be called during reload is
2867 for aligned loads; all other cases require temporaries. */
2869 if (GET_CODE (operands
[1]) == MEM
2870 || (GET_CODE (operands
[1]) == SUBREG
2871 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2872 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2873 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2874 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2875 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2876 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2878 if (aligned_memory_operand (operands
[1], mode
))
2880 if (reload_in_progress
)
2882 emit_insn ((mode
== QImode
2883 ? gen_reload_inqi_help
2884 : gen_reload_inhi_help
)
2885 (operands
[0], operands
[1],
2886 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2890 rtx aligned_mem
, bitnum
;
2891 rtx scratch
= gen_reg_rtx (SImode
);
2893 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2895 emit_insn ((mode
== QImode
2896 ? gen_aligned_loadqi
2897 : gen_aligned_loadhi
)
2898 (operands
[0], aligned_mem
, bitnum
, scratch
));
2903 /* Don't pass these as parameters since that makes the generated
2904 code depend on parameter evaluation order which will cause
2905 bootstrap failures. */
2907 rtx temp1
= gen_reg_rtx (DImode
);
2908 rtx temp2
= gen_reg_rtx (DImode
);
2909 rtx seq
= ((mode
== QImode
2910 ? gen_unaligned_loadqi
2911 : gen_unaligned_loadhi
)
2912 (operands
[0], get_unaligned_address (operands
[1], 0),
2915 alpha_set_memflags (seq
, operands
[1]);
2921 if (GET_CODE (operands
[0]) == MEM
2922 || (GET_CODE (operands
[0]) == SUBREG
2923 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2924 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2925 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2926 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2927 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2928 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2930 if (aligned_memory_operand (operands
[0], mode
))
2932 rtx aligned_mem
, bitnum
;
2933 rtx temp1
= gen_reg_rtx (SImode
);
2934 rtx temp2
= gen_reg_rtx (SImode
);
2936 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2938 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2943 rtx temp1
= gen_reg_rtx (DImode
);
2944 rtx temp2
= gen_reg_rtx (DImode
);
2945 rtx temp3
= gen_reg_rtx (DImode
);
2946 rtx seq
= ((mode
== QImode
2947 ? gen_unaligned_storeqi
2948 : gen_unaligned_storehi
)
2949 (get_unaligned_address (operands
[0], 0),
2950 operands
[1], temp1
, temp2
, temp3
));
2952 alpha_set_memflags (seq
, operands
[0]);
2961 /* Generate an unsigned DImode to FP conversion. This is the same code
2962 optabs would emit if we didn't have TFmode patterns.
2964 For SFmode, this is the only construction I've found that can pass
2965 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2966 intermediates will work, because you'll get intermediate rounding
2967 that ruins the end result. Some of this could be fixed by turning
2968 on round-to-positive-infinity, but that requires diddling the fpsr,
2969 which kills performance. I tried turning this around and converting
2970 to a negative number, so that I could turn on /m, but either I did
2971 it wrong or there's something else cause I wound up with the exact
2972 same single-bit error. There is a branch-less form of this same code:
2983 fcmoveq $f10,$f11,$f0
2985 I'm not using it because it's the same number of instructions as
2986 this branch-full form, and it has more serialized long latency
2987 instructions on the critical path.
2989 For DFmode, we can avoid rounding errors by breaking up the word
2990 into two pieces, converting them separately, and adding them back:
2992 LC0: .long 0,0x5f800000
2997 cpyse $f11,$f31,$f10
2998 cpyse $f31,$f11,$f11
3006 This doesn't seem to be a clear-cut win over the optabs form.
3007 It probably all depends on the distribution of numbers being
3008 converted -- in the optabs form, all but high-bit-set has a
3009 much lower minimum execution time. */
3012 alpha_emit_floatuns (rtx operands
[2])
3014 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3015 enum machine_mode mode
;
3018 in
= force_reg (DImode
, operands
[1]);
3019 mode
= GET_MODE (out
);
3020 neglab
= gen_label_rtx ();
3021 donelab
= gen_label_rtx ();
3022 i0
= gen_reg_rtx (DImode
);
3023 i1
= gen_reg_rtx (DImode
);
3024 f0
= gen_reg_rtx (mode
);
3026 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3028 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3029 emit_jump_insn (gen_jump (donelab
));
3032 emit_label (neglab
);
3034 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3035 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3036 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3037 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3038 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3040 emit_label (donelab
);
3043 /* Generate the comparison for a conditional branch. */
3046 alpha_emit_conditional_branch (enum rtx_code code
)
3048 enum rtx_code cmp_code
, branch_code
;
3049 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3050 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3053 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3055 if (! TARGET_HAS_XFLOATING_LIBS
)
3058 /* X_floating library comparison functions return
3062 Convert the compare against the raw return value. */
3084 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3086 alpha_compare
.fp_p
= 0;
3089 /* The general case: fold the comparison code to the types of compares
3090 that we have, choosing the branch as necessary. */
3093 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3095 /* We have these compares: */
3096 cmp_code
= code
, branch_code
= NE
;
3101 /* These must be reversed. */
3102 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3105 case GE
: case GT
: case GEU
: case GTU
:
3106 /* For FP, we swap them, for INT, we reverse them. */
3107 if (alpha_compare
.fp_p
)
3109 cmp_code
= swap_condition (code
);
3111 tem
= op0
, op0
= op1
, op1
= tem
;
3115 cmp_code
= reverse_condition (code
);
3124 if (alpha_compare
.fp_p
)
3127 if (flag_unsafe_math_optimizations
)
3129 /* When we are not as concerned about non-finite values, and we
3130 are comparing against zero, we can branch directly. */
3131 if (op1
== CONST0_RTX (DFmode
))
3132 cmp_code
= NIL
, branch_code
= code
;
3133 else if (op0
== CONST0_RTX (DFmode
))
3135 /* Undo the swap we probably did just above. */
3136 tem
= op0
, op0
= op1
, op1
= tem
;
3137 branch_code
= swap_condition (cmp_code
);
3143 /* ??? We mark the branch mode to be CCmode to prevent the
3144 compare and branch from being combined, since the compare
3145 insn follows IEEE rules that the branch does not. */
3146 branch_mode
= CCmode
;
3153 /* The following optimizations are only for signed compares. */
3154 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3156 /* Whee. Compare and branch against 0 directly. */
3157 if (op1
== const0_rtx
)
3158 cmp_code
= NIL
, branch_code
= code
;
3160 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3161 bypass between logicals and br/cmov on EV5. But we don't want to
3162 force valid immediate constants into registers needlessly. */
3163 else if (GET_CODE (op1
) == CONST_INT
)
3165 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3167 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3168 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3169 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3171 cmp_code
= PLUS
, branch_code
= code
;
3177 if (!reg_or_0_operand (op0
, DImode
))
3178 op0
= force_reg (DImode
, op0
);
3179 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3180 op1
= force_reg (DImode
, op1
);
3183 /* Emit an initial compare instruction, if necessary. */
3185 if (cmp_code
!= NIL
)
3187 tem
= gen_reg_rtx (cmp_mode
);
3188 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3191 /* Zero the operands. */
3192 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3194 /* Return the branch comparison. */
3195 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3198 /* Certain simplifications can be done to make invalid setcc operations
3199 valid. Return the final comparison, or NULL if we can't work. */
3202 alpha_emit_setcc (enum rtx_code code
)
3204 enum rtx_code cmp_code
;
3205 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3206 int fp_p
= alpha_compare
.fp_p
;
3209 /* Zero the operands. */
3210 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3212 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3214 if (! TARGET_HAS_XFLOATING_LIBS
)
3217 /* X_floating library comparison functions return
3221 Convert the compare against the raw return value. */
3223 if (code
== UNORDERED
|| code
== ORDERED
)
3228 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3232 if (code
== UNORDERED
)
3234 else if (code
== ORDERED
)
3240 if (fp_p
&& !TARGET_FIX
)
3243 /* The general case: fold the comparison code to the types of compares
3244 that we have, choosing the branch as necessary. */
3249 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3251 /* We have these compares. */
3253 cmp_code
= code
, code
= NE
;
3257 if (!fp_p
&& op1
== const0_rtx
)
3262 cmp_code
= reverse_condition (code
);
3266 case GE
: case GT
: case GEU
: case GTU
:
3267 /* These normally need swapping, but for integer zero we have
3268 special patterns that recognize swapped operands. */
3269 if (!fp_p
&& op1
== const0_rtx
)
3271 code
= swap_condition (code
);
3273 cmp_code
= code
, code
= NE
;
3274 tmp
= op0
, op0
= op1
, op1
= tmp
;
3283 if (!register_operand (op0
, DImode
))
3284 op0
= force_reg (DImode
, op0
);
3285 if (!reg_or_8bit_operand (op1
, DImode
))
3286 op1
= force_reg (DImode
, op1
);
3289 /* Emit an initial compare instruction, if necessary. */
3290 if (cmp_code
!= NIL
)
3292 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3294 tmp
= gen_reg_rtx (mode
);
3295 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3296 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3298 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3302 /* Return the setcc comparison. */
3303 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3307 /* Rewrite a comparison against zero CMP of the form
3308 (CODE (cc0) (const_int 0)) so it can be written validly in
3309 a conditional move (if_then_else CMP ...).
3310 If both of the operands that set cc0 are nonzero we must emit
3311 an insn to perform the compare (it can't be done within
3312 the conditional move). */
3315 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
3317 enum rtx_code code
= GET_CODE (cmp
);
3318 enum rtx_code cmov_code
= NE
;
3319 rtx op0
= alpha_compare
.op0
;
3320 rtx op1
= alpha_compare
.op1
;
3321 int fp_p
= alpha_compare
.fp_p
;
3322 enum machine_mode cmp_mode
3323 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3324 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3325 enum machine_mode cmov_mode
= VOIDmode
;
3326 int local_fast_math
= flag_unsafe_math_optimizations
;
3329 /* Zero the operands. */
3330 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3332 if (fp_p
!= FLOAT_MODE_P (mode
))
3334 enum rtx_code cmp_code
;
3339 /* If we have fp<->int register move instructions, do a cmov by
3340 performing the comparison in fp registers, and move the
3341 zero/nonzero value to integer registers, where we can then
3342 use a normal cmov, or vice-versa. */
3346 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3347 /* We have these compares. */
3348 cmp_code
= code
, code
= NE
;
3352 /* This must be reversed. */
3353 cmp_code
= EQ
, code
= EQ
;
3356 case GE
: case GT
: case GEU
: case GTU
:
3357 /* These normally need swapping, but for integer zero we have
3358 special patterns that recognize swapped operands. */
3359 if (!fp_p
&& op1
== const0_rtx
)
3360 cmp_code
= code
, code
= NE
;
3363 cmp_code
= swap_condition (code
);
3365 tem
= op0
, op0
= op1
, op1
= tem
;
3373 tem
= gen_reg_rtx (cmp_op_mode
);
3374 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3375 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3378 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3379 op0
= gen_lowpart (cmp_op_mode
, tem
);
3380 op1
= CONST0_RTX (cmp_op_mode
);
3382 local_fast_math
= 1;
3385 /* We may be able to use a conditional move directly.
3386 This avoids emitting spurious compares. */
3387 if (signed_comparison_operator (cmp
, VOIDmode
)
3388 && (!fp_p
|| local_fast_math
)
3389 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3390 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3392 /* We can't put the comparison inside the conditional move;
3393 emit a compare instruction and put that inside the
3394 conditional move. Make sure we emit only comparisons we have;
3395 swap or reverse as necessary. */
3402 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3403 /* We have these compares: */
3407 /* This must be reversed. */
3408 code
= reverse_condition (code
);
3412 case GE
: case GT
: case GEU
: case GTU
:
3413 /* These must be swapped. */
3414 if (op1
!= CONST0_RTX (cmp_mode
))
3416 code
= swap_condition (code
);
3417 tem
= op0
, op0
= op1
, op1
= tem
;
3427 if (!reg_or_0_operand (op0
, DImode
))
3428 op0
= force_reg (DImode
, op0
);
3429 if (!reg_or_8bit_operand (op1
, DImode
))
3430 op1
= force_reg (DImode
, op1
);
3433 /* ??? We mark the branch mode to be CCmode to prevent the compare
3434 and cmov from being combined, since the compare insn follows IEEE
3435 rules that the cmov does not. */
3436 if (fp_p
&& !local_fast_math
)
3439 tem
= gen_reg_rtx (cmp_op_mode
);
3440 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3441 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3444 /* Simplify a conditional move of two constants into a setcc with
3445 arithmetic. This is done with a splitter since combine would
3446 just undo the work if done during code generation. It also catches
3447 cases we wouldn't have before cse. */
3450 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
3451 rtx t_rtx
, rtx f_rtx
)
3453 HOST_WIDE_INT t
, f
, diff
;
3454 enum machine_mode mode
;
3455 rtx target
, subtarget
, tmp
;
3457 mode
= GET_MODE (dest
);
3462 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3463 || (code
== GE
|| code
== GT
))
3465 code
= reverse_condition (code
);
3466 diff
= t
, t
= f
, f
= diff
;
3470 subtarget
= target
= dest
;
3473 target
= gen_lowpart (DImode
, dest
);
3474 if (! no_new_pseudos
)
3475 subtarget
= gen_reg_rtx (DImode
);
3479 /* Below, we must be careful to use copy_rtx on target and subtarget
3480 in intermediate insns, as they may be a subreg rtx, which may not
3483 if (f
== 0 && exact_log2 (diff
) > 0
3484 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3485 viable over a longer latency cmove. On EV5, the E0 slot is a
3486 scarce resource, and on EV4 shift has the same latency as a cmove. */
3487 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3489 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3490 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3492 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3493 GEN_INT (exact_log2 (t
)));
3494 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3496 else if (f
== 0 && t
== -1)
3498 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3499 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3501 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3503 else if (diff
== 1 || diff
== 4 || diff
== 8)
3507 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3508 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3511 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3514 add_op
= GEN_INT (f
);
3515 if (sext_add_operand (add_op
, mode
))
3517 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3519 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3520 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3532 /* Look up the function X_floating library function name for the
3536 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
3540 const enum rtx_code code
;
3541 const char *const func
;
3544 static const struct xfloating_op vms_xfloating_ops
[] =
3546 { PLUS
, "OTS$ADD_X" },
3547 { MINUS
, "OTS$SUB_X" },
3548 { MULT
, "OTS$MUL_X" },
3549 { DIV
, "OTS$DIV_X" },
3550 { EQ
, "OTS$EQL_X" },
3551 { NE
, "OTS$NEQ_X" },
3552 { LT
, "OTS$LSS_X" },
3553 { LE
, "OTS$LEQ_X" },
3554 { GT
, "OTS$GTR_X" },
3555 { GE
, "OTS$GEQ_X" },
3556 { FIX
, "OTS$CVTXQ" },
3557 { FLOAT
, "OTS$CVTQX" },
3558 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3559 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3560 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3563 static const struct xfloating_op osf_xfloating_ops
[] =
3565 { PLUS
, "_OtsAddX" },
3566 { MINUS
, "_OtsSubX" },
3567 { MULT
, "_OtsMulX" },
3568 { DIV
, "_OtsDivX" },
3575 { FIX
, "_OtsCvtXQ" },
3576 { FLOAT
, "_OtsCvtQX" },
3577 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3578 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3579 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3582 const struct xfloating_op
*ops
;
3583 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3586 /* How irritating. Nothing to key off for the table. Hardcode
3587 knowledge of the G_floating routines. */
3588 if (TARGET_FLOAT_VAX
)
3590 if (TARGET_ABI_OPEN_VMS
)
3592 if (code
== FLOAT_EXTEND
)
3593 return "OTS$CVT_FLOAT_G_X";
3594 if (code
== FLOAT_TRUNCATE
)
3595 return "OTS$CVT_FLOAT_X_G";
3599 if (code
== FLOAT_EXTEND
)
3600 return "_OtsConvertFloatGX";
3601 if (code
== FLOAT_TRUNCATE
)
3602 return "_OtsConvertFloatXG";
3606 if (TARGET_ABI_OPEN_VMS
)
3607 ops
= vms_xfloating_ops
;
3609 ops
= osf_xfloating_ops
;
3611 for (i
= 0; i
< n
; ++i
)
3612 if (ops
[i
].code
== code
)
3618 /* Most X_floating operations take the rounding mode as an argument.
3619 Compute that here. */
3622 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
3623 enum alpha_fp_rounding_mode round
)
3629 case ALPHA_FPRM_NORM
:
3632 case ALPHA_FPRM_MINF
:
3635 case ALPHA_FPRM_CHOP
:
3638 case ALPHA_FPRM_DYN
:
3644 /* XXX For reference, round to +inf is mode = 3. */
3647 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3653 /* Emit an X_floating library function call.
3655 Note that these functions do not follow normal calling conventions:
3656 TFmode arguments are passed in two integer registers (as opposed to
3657 indirect); TFmode return values appear in R16+R17.
3659 FUNC is the function name to call.
3660 TARGET is where the output belongs.
3661 OPERANDS are the inputs.
3662 NOPERANDS is the count of inputs.
3663 EQUIV is the expression equivalent for the function.
3667 alpha_emit_xfloating_libcall (const char *func
, rtx target
, rtx operands
[],
3668 int noperands
, rtx equiv
)
3670 rtx usage
= NULL_RTX
, tmp
, reg
;
3675 for (i
= 0; i
< noperands
; ++i
)
3677 switch (GET_MODE (operands
[i
]))
3680 reg
= gen_rtx_REG (TFmode
, regno
);
3685 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3690 if (GET_CODE (operands
[i
]) != CONST_INT
)
3694 reg
= gen_rtx_REG (DImode
, regno
);
3702 emit_move_insn (reg
, operands
[i
]);
3703 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3706 switch (GET_MODE (target
))
3709 reg
= gen_rtx_REG (TFmode
, 16);
3712 reg
= gen_rtx_REG (DFmode
, 32);
3715 reg
= gen_rtx_REG (DImode
, 0);
3721 tmp
= gen_rtx_MEM (QImode
, init_one_libfunc (func
));
3722 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3723 const0_rtx
, const0_rtx
));
3724 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3729 emit_libcall_block (tmp
, target
, reg
, equiv
);
3732 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3735 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3739 rtx out_operands
[3];
3741 func
= alpha_lookup_xfloating_lib_func (code
);
3742 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3744 out_operands
[0] = operands
[1];
3745 out_operands
[1] = operands
[2];
3746 out_operands
[2] = GEN_INT (mode
);
3747 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3748 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3752 /* Emit an X_floating library function call for a comparison. */
3755 alpha_emit_xfloating_compare (enum rtx_code code
, rtx op0
, rtx op1
)
3758 rtx out
, operands
[2];
3760 func
= alpha_lookup_xfloating_lib_func (code
);
3764 out
= gen_reg_rtx (DImode
);
3766 /* ??? Strange mode for equiv because what's actually returned
3767 is -1,0,1, not a proper boolean value. */
3768 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3769 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3774 /* Emit an X_floating library function call for a conversion. */
3777 alpha_emit_xfloating_cvt (enum rtx_code code
, rtx operands
[])
3779 int noperands
= 1, mode
;
3780 rtx out_operands
[2];
3783 func
= alpha_lookup_xfloating_lib_func (code
);
3785 out_operands
[0] = operands
[1];
3790 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3791 out_operands
[1] = GEN_INT (mode
);
3794 case FLOAT_TRUNCATE
:
3795 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3796 out_operands
[1] = GEN_INT (mode
);
3803 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3804 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
3808 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3809 OP[0] into OP[0,1]. Naturally, output operand ordering is
3813 alpha_split_tfmode_pair (rtx operands
[4])
3815 if (GET_CODE (operands
[1]) == REG
)
3817 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3818 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3820 else if (GET_CODE (operands
[1]) == MEM
)
3822 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3823 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3825 else if (operands
[1] == CONST0_RTX (TFmode
))
3826 operands
[2] = operands
[3] = const0_rtx
;
3830 if (GET_CODE (operands
[0]) == REG
)
3832 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3833 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3835 else if (GET_CODE (operands
[0]) == MEM
)
3837 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3838 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3844 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3845 op2 is a register containing the sign bit, operation is the
3846 logical operation to be performed. */
3849 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3851 rtx high_bit
= operands
[2];
3855 alpha_split_tfmode_pair (operands
);
3857 /* Detect three flavors of operand overlap. */
3859 if (rtx_equal_p (operands
[0], operands
[2]))
3861 else if (rtx_equal_p (operands
[1], operands
[2]))
3863 if (rtx_equal_p (operands
[0], high_bit
))
3870 emit_move_insn (operands
[0], operands
[2]);
3872 /* ??? If the destination overlaps both source tf and high_bit, then
3873 assume source tf is dead in its entirety and use the other half
3874 for a scratch register. Otherwise "scratch" is just the proper
3875 destination register. */
3876 scratch
= operands
[move
< 2 ? 1 : 3];
3878 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3882 emit_move_insn (operands
[0], operands
[2]);
3884 emit_move_insn (operands
[1], scratch
);
3888 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3892 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3893 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3894 lda r3,X(r11) lda r3,X+2(r11)
3895 extwl r1,r3,r1 extql r1,r3,r1
3896 extwh r2,r3,r2 extqh r2,r3,r2
3897 or r1.r2.r1 or r1,r2,r1
3900 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3901 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3902 lda r3,X(r11) lda r3,X(r11)
3903 extll r1,r3,r1 extll r1,r3,r1
3904 extlh r2,r3,r2 extlh r2,r3,r2
3905 or r1.r2.r1 addl r1,r2,r1
3907 quad: ldq_u r1,X(r11)
3916 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3917 HOST_WIDE_INT ofs
, int sign
)
3919 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3920 enum machine_mode mode
;
3922 meml
= gen_reg_rtx (DImode
);
3923 memh
= gen_reg_rtx (DImode
);
3924 addr
= gen_reg_rtx (DImode
);
3925 extl
= gen_reg_rtx (DImode
);
3926 exth
= gen_reg_rtx (DImode
);
3928 mema
= XEXP (mem
, 0);
3929 if (GET_CODE (mema
) == LO_SUM
)
3930 mema
= force_reg (Pmode
, mema
);
3932 /* AND addresses cannot be in any alias set, since they may implicitly
3933 alias surrounding code. Ideally we'd have some alias set that
3934 covered all types except those with alignment 8 or higher. */
3936 tmp
= change_address (mem
, DImode
,
3937 gen_rtx_AND (DImode
,
3938 plus_constant (mema
, ofs
),
3940 set_mem_alias_set (tmp
, 0);
3941 emit_move_insn (meml
, tmp
);
3943 tmp
= change_address (mem
, DImode
,
3944 gen_rtx_AND (DImode
,
3945 plus_constant (mema
, ofs
+ size
- 1),
3947 set_mem_alias_set (tmp
, 0);
3948 emit_move_insn (memh
, tmp
);
3950 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3952 emit_move_insn (addr
, plus_constant (mema
, -1));
3954 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3955 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3957 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3958 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3959 addr
, 1, OPTAB_WIDEN
);
3961 else if (sign
&& size
== 2)
3963 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3965 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3966 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3968 /* We must use tgt here for the target. Alpha-vms port fails if we use
3969 addr for the target, because addr is marked as a pointer and combine
3970 knows that pointers are always sign-extended 32 bit values. */
3971 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3972 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3973 addr
, 1, OPTAB_WIDEN
);
3977 if (WORDS_BIG_ENDIAN
)
3979 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3983 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3988 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3993 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4000 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4004 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4005 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4009 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4014 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4019 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4028 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4029 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4034 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4037 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4040 alpha_expand_unaligned_store (rtx dst
, rtx src
,
4041 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
4043 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4045 dstl
= gen_reg_rtx (DImode
);
4046 dsth
= gen_reg_rtx (DImode
);
4047 insl
= gen_reg_rtx (DImode
);
4048 insh
= gen_reg_rtx (DImode
);
4050 dsta
= XEXP (dst
, 0);
4051 if (GET_CODE (dsta
) == LO_SUM
)
4052 dsta
= force_reg (Pmode
, dsta
);
4054 /* AND addresses cannot be in any alias set, since they may implicitly
4055 alias surrounding code. Ideally we'd have some alias set that
4056 covered all types except those with alignment 8 or higher. */
4058 meml
= change_address (dst
, DImode
,
4059 gen_rtx_AND (DImode
,
4060 plus_constant (dsta
, ofs
),
4062 set_mem_alias_set (meml
, 0);
4064 memh
= change_address (dst
, DImode
,
4065 gen_rtx_AND (DImode
,
4066 plus_constant (dsta
, ofs
+ size
- 1),
4068 set_mem_alias_set (memh
, 0);
4070 emit_move_insn (dsth
, memh
);
4071 emit_move_insn (dstl
, meml
);
4072 if (WORDS_BIG_ENDIAN
)
4074 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4076 if (src
!= const0_rtx
)
4081 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4084 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4087 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4090 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4091 GEN_INT (size
*8), addr
));
4097 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4101 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4102 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4106 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4110 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4114 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4116 if (src
!= const0_rtx
)
4118 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4119 GEN_INT (size
*8), addr
));
4124 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4127 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4130 emit_insn (gen_insql_le (insl
, src
, addr
));
4135 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4140 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4144 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4145 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4149 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4154 if (src
!= const0_rtx
)
4156 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4157 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4160 if (WORDS_BIG_ENDIAN
)
4162 emit_move_insn (meml
, dstl
);
4163 emit_move_insn (memh
, dsth
);
4167 /* Must store high before low for degenerate case of aligned. */
4168 emit_move_insn (memh
, dsth
);
4169 emit_move_insn (meml
, dstl
);
4173 /* The block move code tries to maximize speed by separating loads and
4174 stores at the expense of register pressure: we load all of the data
4175 before we store it back out. There are two secondary effects worth
4176 mentioning, that this speeds copying to/from aligned and unaligned
4177 buffers, and that it makes the code significantly easier to write. */
4179 #define MAX_MOVE_WORDS 8
4181 /* Load an integral number of consecutive unaligned quadwords. */
4184 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
4185 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4187 rtx
const im8
= GEN_INT (-8);
4188 rtx
const i64
= GEN_INT (64);
4189 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4190 rtx sreg
, areg
, tmp
, smema
;
4193 smema
= XEXP (smem
, 0);
4194 if (GET_CODE (smema
) == LO_SUM
)
4195 smema
= force_reg (Pmode
, smema
);
4197 /* Generate all the tmp registers we need. */
4198 for (i
= 0; i
< words
; ++i
)
4200 data_regs
[i
] = out_regs
[i
];
4201 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4203 data_regs
[words
] = gen_reg_rtx (DImode
);
4206 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4208 /* Load up all of the source data. */
4209 for (i
= 0; i
< words
; ++i
)
4211 tmp
= change_address (smem
, DImode
,
4212 gen_rtx_AND (DImode
,
4213 plus_constant (smema
, 8*i
),
4215 set_mem_alias_set (tmp
, 0);
4216 emit_move_insn (data_regs
[i
], tmp
);
4219 tmp
= change_address (smem
, DImode
,
4220 gen_rtx_AND (DImode
,
4221 plus_constant (smema
, 8*words
- 1),
4223 set_mem_alias_set (tmp
, 0);
4224 emit_move_insn (data_regs
[words
], tmp
);
4226 /* Extract the half-word fragments. Unfortunately DEC decided to make
4227 extxh with offset zero a noop instead of zeroing the register, so
4228 we must take care of that edge condition ourselves with cmov. */
4230 sreg
= copy_addr_to_reg (smema
);
4231 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4233 if (WORDS_BIG_ENDIAN
)
4234 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4235 for (i
= 0; i
< words
; ++i
)
4237 if (WORDS_BIG_ENDIAN
)
4239 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4240 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4244 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4245 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4247 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4248 gen_rtx_IF_THEN_ELSE (DImode
,
4249 gen_rtx_EQ (DImode
, areg
,
4251 const0_rtx
, ext_tmps
[i
])));
4254 /* Merge the half-words into whole words. */
4255 for (i
= 0; i
< words
; ++i
)
4257 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4258 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4262 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4263 may be NULL to store zeros. */
4266 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
4267 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4269 rtx
const im8
= GEN_INT (-8);
4270 rtx
const i64
= GEN_INT (64);
4271 rtx ins_tmps
[MAX_MOVE_WORDS
];
4272 rtx st_tmp_1
, st_tmp_2
, dreg
;
4273 rtx st_addr_1
, st_addr_2
, dmema
;
4276 dmema
= XEXP (dmem
, 0);
4277 if (GET_CODE (dmema
) == LO_SUM
)
4278 dmema
= force_reg (Pmode
, dmema
);
4280 /* Generate all the tmp registers we need. */
4281 if (data_regs
!= NULL
)
4282 for (i
= 0; i
< words
; ++i
)
4283 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4284 st_tmp_1
= gen_reg_rtx(DImode
);
4285 st_tmp_2
= gen_reg_rtx(DImode
);
4288 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4290 st_addr_2
= change_address (dmem
, DImode
,
4291 gen_rtx_AND (DImode
,
4292 plus_constant (dmema
, words
*8 - 1),
4294 set_mem_alias_set (st_addr_2
, 0);
4296 st_addr_1
= change_address (dmem
, DImode
,
4297 gen_rtx_AND (DImode
, dmema
, im8
));
4298 set_mem_alias_set (st_addr_1
, 0);
4300 /* Load up the destination end bits. */
4301 emit_move_insn (st_tmp_2
, st_addr_2
);
4302 emit_move_insn (st_tmp_1
, st_addr_1
);
4304 /* Shift the input data into place. */
4305 dreg
= copy_addr_to_reg (dmema
);
4306 if (WORDS_BIG_ENDIAN
)
4307 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4308 if (data_regs
!= NULL
)
4310 for (i
= words
-1; i
>= 0; --i
)
4312 if (WORDS_BIG_ENDIAN
)
4314 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4315 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4319 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4320 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4323 for (i
= words
-1; i
> 0; --i
)
4325 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4326 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4331 /* Split and merge the ends with the destination data. */
4332 if (WORDS_BIG_ENDIAN
)
4334 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4335 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4339 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4340 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4343 if (data_regs
!= NULL
)
4345 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4346 st_tmp_2
, 1, OPTAB_WIDEN
);
4347 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4348 st_tmp_1
, 1, OPTAB_WIDEN
);
4352 if (WORDS_BIG_ENDIAN
)
4353 emit_move_insn (st_addr_1
, st_tmp_1
);
4355 emit_move_insn (st_addr_2
, st_tmp_2
);
4356 for (i
= words
-1; i
> 0; --i
)
4358 rtx tmp
= change_address (dmem
, DImode
,
4359 gen_rtx_AND (DImode
,
4360 plus_constant(dmema
,
4361 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4363 set_mem_alias_set (tmp
, 0);
4364 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4366 if (WORDS_BIG_ENDIAN
)
4367 emit_move_insn (st_addr_2
, st_tmp_2
);
4369 emit_move_insn (st_addr_1
, st_tmp_1
);
4373 /* Expand string/block move operations.
4375 operands[0] is the pointer to the destination.
4376 operands[1] is the pointer to the source.
4377 operands[2] is the number of bytes to move.
4378 operands[3] is the alignment. */
4381 alpha_expand_block_move (rtx operands
[])
4383 rtx bytes_rtx
= operands
[2];
4384 rtx align_rtx
= operands
[3];
4385 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4386 HOST_WIDE_INT bytes
= orig_bytes
;
4387 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4388 HOST_WIDE_INT dst_align
= src_align
;
4389 rtx orig_src
= operands
[1];
4390 rtx orig_dst
= operands
[0];
4391 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4393 unsigned int i
, words
, ofs
, nregs
= 0;
4395 if (orig_bytes
<= 0)
4397 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4400 /* Look for additional alignment information from recorded register info. */
4402 tmp
= XEXP (orig_src
, 0);
4403 if (GET_CODE (tmp
) == REG
)
4404 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4405 else if (GET_CODE (tmp
) == PLUS
4406 && GET_CODE (XEXP (tmp
, 0)) == REG
4407 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4409 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4410 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4414 if (a
>= 64 && c
% 8 == 0)
4416 else if (a
>= 32 && c
% 4 == 0)
4418 else if (a
>= 16 && c
% 2 == 0)
4423 tmp
= XEXP (orig_dst
, 0);
4424 if (GET_CODE (tmp
) == REG
)
4425 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4426 else if (GET_CODE (tmp
) == PLUS
4427 && GET_CODE (XEXP (tmp
, 0)) == REG
4428 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4430 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4431 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4435 if (a
>= 64 && c
% 8 == 0)
4437 else if (a
>= 32 && c
% 4 == 0)
4439 else if (a
>= 16 && c
% 2 == 0)
4444 /* Load the entire block into registers. */
4445 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4447 enum machine_mode mode
;
4449 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4451 /* Don't use the existing register if we're reading more than
4452 is held in the register. Nor if there is not a mode that
4453 handles the exact size. */
4454 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4455 if (GET_CODE (tmp
) == REG
4457 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4461 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4462 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4466 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4471 /* No appropriate mode; fall back on memory. */
4472 orig_src
= replace_equiv_address (orig_src
,
4473 copy_addr_to_reg (XEXP (orig_src
, 0)));
4474 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4478 if (src_align
>= 64 && bytes
>= 8)
4482 for (i
= 0; i
< words
; ++i
)
4483 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4485 for (i
= 0; i
< words
; ++i
)
4486 emit_move_insn (data_regs
[nregs
+ i
],
4487 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4494 if (src_align
>= 32 && bytes
>= 4)
4498 for (i
= 0; i
< words
; ++i
)
4499 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4501 for (i
= 0; i
< words
; ++i
)
4502 emit_move_insn (data_regs
[nregs
+ i
],
4503 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4514 for (i
= 0; i
< words
+1; ++i
)
4515 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4517 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4525 if (! TARGET_BWX
&& bytes
>= 4)
4527 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4528 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4535 if (src_align
>= 16)
4538 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4539 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4542 } while (bytes
>= 2);
4544 else if (! TARGET_BWX
)
4546 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4547 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4555 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4556 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4563 if (nregs
> ARRAY_SIZE (data_regs
))
4566 /* Now save it back out again. */
4570 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4572 enum machine_mode mode
;
4573 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4575 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4576 if (GET_CODE (tmp
) == REG
&& GET_MODE (tmp
) == mode
)
4580 emit_move_insn (tmp
, data_regs
[0]);
4585 else if (nregs
== 2 && mode
== TImode
)
4587 /* Undo the subregging done above when copying between
4588 two TImode registers. */
4589 if (GET_CODE (data_regs
[0]) == SUBREG
4590 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4591 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4597 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4598 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4602 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4603 data_regs
[1], NULL_RTX
);
4611 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4612 /* ??? Optimize mode < dst_mode with strict_low_part. */
4614 /* No appropriate mode; fall back on memory. We can speed things
4615 up by recognizing extra alignment information. */
4616 orig_dst
= replace_equiv_address (orig_dst
,
4617 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4618 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4621 /* Write out the data in whatever chunks reading the source allowed. */
4622 if (dst_align
>= 64)
4624 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4626 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4633 if (dst_align
>= 32)
4635 /* If the source has remaining DImode regs, write them out in
4637 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4639 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4640 NULL_RTX
, 1, OPTAB_WIDEN
);
4642 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4643 gen_lowpart (SImode
, data_regs
[i
]));
4644 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4645 gen_lowpart (SImode
, tmp
));
4650 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4652 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4659 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4661 /* Write out a remaining block of words using unaligned methods. */
4663 for (words
= 1; i
+ words
< nregs
; words
++)
4664 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4668 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4670 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4677 /* Due to the above, this won't be aligned. */
4678 /* ??? If we have more than one of these, consider constructing full
4679 words in registers and using alpha_expand_unaligned_store_words. */
4680 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4682 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4687 if (dst_align
>= 16)
4688 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4690 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4695 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4697 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4702 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4704 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4718 alpha_expand_block_clear (rtx operands
[])
4720 rtx bytes_rtx
= operands
[1];
4721 rtx align_rtx
= operands
[2];
4722 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4723 HOST_WIDE_INT bytes
= orig_bytes
;
4724 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4725 HOST_WIDE_INT alignofs
= 0;
4726 rtx orig_dst
= operands
[0];
4728 int i
, words
, ofs
= 0;
4730 if (orig_bytes
<= 0)
4732 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4735 /* Look for stricter alignment. */
4736 tmp
= XEXP (orig_dst
, 0);
4737 if (GET_CODE (tmp
) == REG
)
4738 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4739 else if (GET_CODE (tmp
) == PLUS
4740 && GET_CODE (XEXP (tmp
, 0)) == REG
4741 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4743 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4744 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4749 align
= a
, alignofs
= 8 - c
% 8;
4751 align
= a
, alignofs
= 4 - c
% 4;
4753 align
= a
, alignofs
= 2 - c
% 2;
4756 else if (GET_CODE (tmp
) == ADDRESSOF
)
4758 enum machine_mode mode
;
4760 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4761 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4763 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4767 /* No appropriate mode; fall back on memory. */
4768 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4769 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4772 /* Handle an unaligned prefix first. */
4776 #if HOST_BITS_PER_WIDE_INT >= 64
4777 /* Given that alignofs is bounded by align, the only time BWX could
4778 generate three stores is for a 7 byte fill. Prefer two individual
4779 stores over a load/mask/store sequence. */
4780 if ((!TARGET_BWX
|| alignofs
== 7)
4782 && !(alignofs
== 4 && bytes
>= 4))
4784 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4785 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4789 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4790 set_mem_alias_set (mem
, 0);
4792 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4793 if (bytes
< alignofs
)
4795 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4806 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4807 NULL_RTX
, 1, OPTAB_WIDEN
);
4809 emit_move_insn (mem
, tmp
);
4813 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4815 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4820 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4822 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4827 if (alignofs
== 4 && bytes
>= 4)
4829 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4835 /* If we've not used the extra lead alignment information by now,
4836 we won't be able to. Downgrade align to match what's left over. */
4839 alignofs
= alignofs
& -alignofs
;
4840 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4844 /* Handle a block of contiguous long-words. */
4846 if (align
>= 64 && bytes
>= 8)
4850 for (i
= 0; i
< words
; ++i
)
4851 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4858 /* If the block is large and appropriately aligned, emit a single
4859 store followed by a sequence of stq_u insns. */
4861 if (align
>= 32 && bytes
> 16)
4865 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4869 orig_dsta
= XEXP (orig_dst
, 0);
4870 if (GET_CODE (orig_dsta
) == LO_SUM
)
4871 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4874 for (i
= 0; i
< words
; ++i
)
4877 = change_address (orig_dst
, DImode
,
4878 gen_rtx_AND (DImode
,
4879 plus_constant (orig_dsta
, ofs
+ i
*8),
4881 set_mem_alias_set (mem
, 0);
4882 emit_move_insn (mem
, const0_rtx
);
4885 /* Depending on the alignment, the first stq_u may have overlapped
4886 with the initial stl, which means that the last stq_u didn't
4887 write as much as it would appear. Leave those questionable bytes
4889 bytes
-= words
* 8 - 4;
4890 ofs
+= words
* 8 - 4;
4893 /* Handle a smaller block of aligned words. */
4895 if ((align
>= 64 && bytes
== 4)
4896 || (align
== 32 && bytes
>= 4))
4900 for (i
= 0; i
< words
; ++i
)
4901 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4908 /* An unaligned block uses stq_u stores for as many as possible. */
4914 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4920 /* Next clean up any trailing pieces. */
4922 #if HOST_BITS_PER_WIDE_INT >= 64
4923 /* Count the number of bits in BYTES for which aligned stores could
4926 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4930 /* If we have appropriate alignment (and it wouldn't take too many
4931 instructions otherwise), mask out the bytes we need. */
4932 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4939 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4940 set_mem_alias_set (mem
, 0);
4942 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4944 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4945 NULL_RTX
, 1, OPTAB_WIDEN
);
4947 emit_move_insn (mem
, tmp
);
4950 else if (align
>= 32 && bytes
< 4)
4955 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4956 set_mem_alias_set (mem
, 0);
4958 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4960 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4961 NULL_RTX
, 1, OPTAB_WIDEN
);
4963 emit_move_insn (mem
, tmp
);
4969 if (!TARGET_BWX
&& bytes
>= 4)
4971 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4981 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4985 } while (bytes
>= 2);
4987 else if (! TARGET_BWX
)
4989 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4997 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5005 /* Returns a mask so that zap(x, value) == x & mask. */
5008 alpha_expand_zap_mask (HOST_WIDE_INT value
)
5013 if (HOST_BITS_PER_WIDE_INT
>= 64)
5015 HOST_WIDE_INT mask
= 0;
5017 for (i
= 7; i
>= 0; --i
)
5020 if (!((value
>> i
) & 1))
5024 result
= gen_int_mode (mask
, DImode
);
5026 else if (HOST_BITS_PER_WIDE_INT
== 32)
5028 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5030 for (i
= 7; i
>= 4; --i
)
5033 if (!((value
>> i
) & 1))
5037 for (i
= 3; i
>= 0; --i
)
5040 if (!((value
>> i
) & 1))
5044 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5053 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
5054 enum machine_mode mode
,
5055 rtx op0
, rtx op1
, rtx op2
)
5057 op0
= gen_lowpart (mode
, op0
);
5059 if (op1
== const0_rtx
)
5060 op1
= CONST0_RTX (mode
);
5062 op1
= gen_lowpart (mode
, op1
);
5064 if (op2
== const0_rtx
)
5065 op2
= CONST0_RTX (mode
);
5067 op2
= gen_lowpart (mode
, op2
);
5069 emit_insn ((*gen
) (op0
, op1
, op2
));
5072 /* Adjust the cost of a scheduling dependency. Return the new cost of
5073 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5076 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5078 enum attr_type insn_type
, dep_insn_type
;
5080 /* If the dependence is an anti-dependence, there is no cost. For an
5081 output dependence, there is sometimes a cost, but it doesn't seem
5082 worth handling those few cases. */
5083 if (REG_NOTE_KIND (link
) != 0)
5086 /* If we can't recognize the insns, we can't really do anything. */
5087 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5090 insn_type
= get_attr_type (insn
);
5091 dep_insn_type
= get_attr_type (dep_insn
);
5093 /* Bring in the user-defined memory latency. */
5094 if (dep_insn_type
== TYPE_ILD
5095 || dep_insn_type
== TYPE_FLD
5096 || dep_insn_type
== TYPE_LDSYM
)
5097 cost
+= alpha_memory_latency
-1;
5099 /* Everything else handled in DFA bypasses now. */
5104 /* The number of instructions that can be issued per cycle. */
5107 alpha_issue_rate (void)
5109 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5113 alpha_use_dfa_pipeline_interface (void)
5118 /* How many alternative schedules to try. This should be as wide as the
5119 scheduling freedom in the DFA, but no wider. Making this value too
5120 large results extra work for the scheduler.
5122 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5123 alternative schedules. For EV5, we can choose between E0/E1 and
5124 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5127 alpha_multipass_dfa_lookahead (void)
5129 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5132 /* Machine-specific function data. */
5134 struct machine_function
GTY(())
5137 /* List of call information words for calls from this function. */
5138 struct rtx_def
*first_ciw
;
5139 struct rtx_def
*last_ciw
;
5142 /* List of deferred case vectors. */
5143 struct rtx_def
*addr_list
;
5146 const char *some_ld_name
;
5149 /* How to allocate a 'struct machine_function'. */
5151 static struct machine_function
*
5152 alpha_init_machine_status (void)
5154 return ((struct machine_function
*)
5155 ggc_alloc_cleared (sizeof (struct machine_function
)));
5158 /* Functions to save and restore alpha_return_addr_rtx. */
5160 /* Start the ball rolling with RETURN_ADDR_RTX. */
5163 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
5168 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5171 /* Return or create a pseudo containing the gp value for the current
5172 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5175 alpha_gp_save_rtx (void)
5177 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5178 if (GET_CODE (r
) != MEM
)
5179 r
= gen_mem_addressof (r
, NULL_TREE
, /*rescan=*/true);
5184 alpha_ra_ever_killed (void)
5188 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5189 return regs_ever_live
[REG_RA
];
5191 push_topmost_sequence ();
5193 pop_topmost_sequence ();
5195 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5199 /* Return the trap mode suffix applicable to the current
5200 instruction, or NULL. */
5203 get_trap_mode_suffix (void)
5205 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5209 case TRAP_SUFFIX_NONE
:
5212 case TRAP_SUFFIX_SU
:
5213 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5217 case TRAP_SUFFIX_SUI
:
5218 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5222 case TRAP_SUFFIX_V_SV
:
5230 case ALPHA_FPTM_SUI
:
5235 case TRAP_SUFFIX_V_SV_SVI
:
5244 case ALPHA_FPTM_SUI
:
5249 case TRAP_SUFFIX_U_SU_SUI
:
5258 case ALPHA_FPTM_SUI
:
5266 /* Return the rounding mode suffix applicable to the current
5267 instruction, or NULL. */
5270 get_round_mode_suffix (void)
5272 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5276 case ROUND_SUFFIX_NONE
:
5278 case ROUND_SUFFIX_NORMAL
:
5281 case ALPHA_FPRM_NORM
:
5283 case ALPHA_FPRM_MINF
:
5285 case ALPHA_FPRM_CHOP
:
5287 case ALPHA_FPRM_DYN
:
5292 case ROUND_SUFFIX_C
:
5298 /* Locate some local-dynamic symbol still in use by this function
5299 so that we can print its name in some movdi_er_tlsldm pattern. */
5302 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5306 if (GET_CODE (x
) == SYMBOL_REF
5307 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5309 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5317 get_some_local_dynamic_name (void)
5321 if (cfun
->machine
->some_ld_name
)
5322 return cfun
->machine
->some_ld_name
;
5324 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5326 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5327 return cfun
->machine
->some_ld_name
;
5332 /* Print an operand. Recognize special options, documented below. */
5335 print_operand (FILE *file
, rtx x
, int code
)
5342 /* Print the assembler name of the current function. */
5343 assemble_name (file
, alpha_fnname
);
5347 assemble_name (file
, get_some_local_dynamic_name ());
5352 const char *trap
= get_trap_mode_suffix ();
5353 const char *round
= get_round_mode_suffix ();
5356 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5357 (trap
? trap
: ""), (round
? round
: ""));
5362 /* Generates single precision instruction suffix. */
5363 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5367 /* Generates double precision instruction suffix. */
5368 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5372 /* Generates a nop after a noreturn call at the very end of the
5374 if (next_real_insn (current_output_insn
) == 0)
5375 fprintf (file
, "\n\tnop");
5379 if (alpha_this_literal_sequence_number
== 0)
5380 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5381 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5385 if (alpha_this_gpdisp_sequence_number
== 0)
5386 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5387 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5391 if (GET_CODE (x
) == HIGH
)
5392 output_addr_const (file
, XEXP (x
, 0));
5394 output_operand_lossage ("invalid %%H value");
5401 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5403 x
= XVECEXP (x
, 0, 0);
5404 lituse
= "lituse_tlsgd";
5406 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5408 x
= XVECEXP (x
, 0, 0);
5409 lituse
= "lituse_tlsldm";
5411 else if (GET_CODE (x
) == CONST_INT
)
5412 lituse
= "lituse_jsr";
5415 output_operand_lossage ("invalid %%J value");
5419 if (x
!= const0_rtx
)
5420 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5425 /* If this operand is the constant zero, write it as "$31". */
5426 if (GET_CODE (x
) == REG
)
5427 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5428 else if (x
== CONST0_RTX (GET_MODE (x
)))
5429 fprintf (file
, "$31");
5431 output_operand_lossage ("invalid %%r value");
5435 /* Similar, but for floating-point. */
5436 if (GET_CODE (x
) == REG
)
5437 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5438 else if (x
== CONST0_RTX (GET_MODE (x
)))
5439 fprintf (file
, "$f31");
5441 output_operand_lossage ("invalid %%R value");
5445 /* Write the 1's complement of a constant. */
5446 if (GET_CODE (x
) != CONST_INT
)
5447 output_operand_lossage ("invalid %%N value");
5449 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5453 /* Write 1 << C, for a constant C. */
5454 if (GET_CODE (x
) != CONST_INT
)
5455 output_operand_lossage ("invalid %%P value");
5457 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5461 /* Write the high-order 16 bits of a constant, sign-extended. */
5462 if (GET_CODE (x
) != CONST_INT
)
5463 output_operand_lossage ("invalid %%h value");
5465 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5469 /* Write the low-order 16 bits of a constant, sign-extended. */
5470 if (GET_CODE (x
) != CONST_INT
)
5471 output_operand_lossage ("invalid %%L value");
5473 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5474 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5478 /* Write mask for ZAP insn. */
5479 if (GET_CODE (x
) == CONST_DOUBLE
)
5481 HOST_WIDE_INT mask
= 0;
5482 HOST_WIDE_INT value
;
5484 value
= CONST_DOUBLE_LOW (x
);
5485 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5490 value
= CONST_DOUBLE_HIGH (x
);
5491 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5494 mask
|= (1 << (i
+ sizeof (int)));
5496 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5499 else if (GET_CODE (x
) == CONST_INT
)
5501 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5503 for (i
= 0; i
< 8; i
++, value
>>= 8)
5507 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5510 output_operand_lossage ("invalid %%m value");
5514 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5515 if (GET_CODE (x
) != CONST_INT
5516 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5517 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5518 output_operand_lossage ("invalid %%M value");
5520 fprintf (file
, "%s",
5521 (INTVAL (x
) == 8 ? "b"
5522 : INTVAL (x
) == 16 ? "w"
5523 : INTVAL (x
) == 32 ? "l"
5528 /* Similar, except do it from the mask. */
5529 if (GET_CODE (x
) == CONST_INT
)
5531 HOST_WIDE_INT value
= INTVAL (x
);
5538 if (value
== 0xffff)
5543 if (value
== 0xffffffff)
5554 else if (HOST_BITS_PER_WIDE_INT
== 32
5555 && GET_CODE (x
) == CONST_DOUBLE
5556 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5557 && CONST_DOUBLE_HIGH (x
) == 0)
5562 output_operand_lossage ("invalid %%U value");
5566 /* Write the constant value divided by 8 for little-endian mode or
5567 (56 - value) / 8 for big-endian mode. */
5569 if (GET_CODE (x
) != CONST_INT
5570 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5573 || (INTVAL (x
) & 7) != 0)
5574 output_operand_lossage ("invalid %%s value");
5576 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5578 ? (56 - INTVAL (x
)) / 8
5583 /* Same, except compute (64 - c) / 8 */
5585 if (GET_CODE (x
) != CONST_INT
5586 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5587 && (INTVAL (x
) & 7) != 8)
5588 output_operand_lossage ("invalid %%s value");
5590 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5595 /* On Unicos/Mk systems: use a DEX expression if the symbol
5596 clashes with a register name. */
5597 int dex
= unicosmk_need_dex (x
);
5599 fprintf (file
, "DEX(%d)", dex
);
5601 output_addr_const (file
, x
);
5605 case 'C': case 'D': case 'c': case 'd':
5606 /* Write out comparison name. */
5608 enum rtx_code c
= GET_CODE (x
);
5610 if (GET_RTX_CLASS (c
) != '<')
5611 output_operand_lossage ("invalid %%C value");
5613 else if (code
== 'D')
5614 c
= reverse_condition (c
);
5615 else if (code
== 'c')
5616 c
= swap_condition (c
);
5617 else if (code
== 'd')
5618 c
= swap_condition (reverse_condition (c
));
5621 fprintf (file
, "ule");
5623 fprintf (file
, "ult");
5624 else if (c
== UNORDERED
)
5625 fprintf (file
, "un");
5627 fprintf (file
, "%s", GET_RTX_NAME (c
));
5632 /* Write the divide or modulus operator. */
5633 switch (GET_CODE (x
))
5636 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5639 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5642 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5645 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5648 output_operand_lossage ("invalid %%E value");
5654 /* Write "_u" for unaligned access. */
5655 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5656 fprintf (file
, "_u");
5660 if (GET_CODE (x
) == REG
)
5661 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5662 else if (GET_CODE (x
) == MEM
)
5663 output_address (XEXP (x
, 0));
5664 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5666 switch (XINT (XEXP (x
, 0), 1))
5670 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5673 output_operand_lossage ("unknown relocation unspec");
5678 output_addr_const (file
, x
);
5682 output_operand_lossage ("invalid %%xn code");
5687 print_operand_address (FILE *file
, rtx addr
)
5690 HOST_WIDE_INT offset
= 0;
5692 if (GET_CODE (addr
) == AND
)
5693 addr
= XEXP (addr
, 0);
5695 if (GET_CODE (addr
) == PLUS
5696 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5698 offset
= INTVAL (XEXP (addr
, 1));
5699 addr
= XEXP (addr
, 0);
5702 if (GET_CODE (addr
) == LO_SUM
)
5704 const char *reloc16
, *reloclo
;
5705 rtx op1
= XEXP (addr
, 1);
5707 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5709 op1
= XEXP (op1
, 0);
5710 switch (XINT (op1
, 1))
5714 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5718 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5721 output_operand_lossage ("unknown relocation unspec");
5725 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5730 reloclo
= "gprellow";
5731 output_addr_const (file
, op1
);
5735 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5737 addr
= XEXP (addr
, 0);
5738 if (GET_CODE (addr
) == REG
)
5739 basereg
= REGNO (addr
);
5740 else if (GET_CODE (addr
) == SUBREG
5741 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5742 basereg
= subreg_regno (addr
);
5746 fprintf (file
, "($%d)\t\t!%s", basereg
,
5747 (basereg
== 29 ? reloc16
: reloclo
));
5751 if (GET_CODE (addr
) == REG
)
5752 basereg
= REGNO (addr
);
5753 else if (GET_CODE (addr
) == SUBREG
5754 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5755 basereg
= subreg_regno (addr
);
5756 else if (GET_CODE (addr
) == CONST_INT
)
5757 offset
= INTVAL (addr
);
5759 #if TARGET_ABI_OPEN_VMS
5760 else if (GET_CODE (addr
) == SYMBOL_REF
)
5762 fprintf (file
, "%s", XSTR (addr
, 0));
5765 else if (GET_CODE (addr
) == CONST
5766 && GET_CODE (XEXP (addr
, 0)) == PLUS
5767 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5769 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5770 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5771 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5779 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5782 /* Emit RTL insns to initialize the variable parts of a trampoline at
5783 TRAMP. FNADDR is an RTX for the address of the function's pure
5784 code. CXT is an RTX for the static chain value for the function.
5786 The three offset parameters are for the individual template's
5787 layout. A JMPOFS < 0 indicates that the trampoline does not
5788 contain instructions at all.
5790 We assume here that a function will be called many more times than
5791 its address is taken (e.g., it might be passed to qsort), so we
5792 take the trouble to initialize the "hint" field in the JMP insn.
5793 Note that the hint field is PC (new) + 4 * bits 13:0. */
5796 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5797 int fnofs
, int cxtofs
, int jmpofs
)
5799 rtx temp
, temp1
, addr
;
5800 /* VMS really uses DImode pointers in memory at this point. */
5801 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5803 #ifdef POINTERS_EXTEND_UNSIGNED
5804 fnaddr
= convert_memory_address (mode
, fnaddr
);
5805 cxt
= convert_memory_address (mode
, cxt
);
5808 /* Store function address and CXT. */
5809 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5810 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5811 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5812 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5814 /* This has been disabled since the hint only has a 32k range, and in
5815 no existing OS is the stack within 32k of the text segment. */
5816 if (0 && jmpofs
>= 0)
5818 /* Compute hint value. */
5819 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5820 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5822 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5823 build_int_2 (2, 0), NULL_RTX
, 1);
5824 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5825 GEN_INT (0x3fff), 0);
5827 /* Merge in the hint. */
5828 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5829 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5830 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5831 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5833 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5836 #ifdef TRANSFER_FROM_TRAMPOLINE
5837 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5838 0, VOIDmode
, 1, tramp
, Pmode
);
5842 emit_insn (gen_imb ());
5845 /* Determine where to put an argument to a function.
5846 Value is zero to push the argument on the stack,
5847 or a hard register in which to store the argument.
5849 MODE is the argument's machine mode.
5850 TYPE is the data type of the argument (as a tree).
5851 This is null for libcalls where that information may
5853 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5854 the preceding args and about the function being called.
5855 NAMED is nonzero if this argument is a named parameter
5856 (otherwise it is an extra parameter matching an ellipsis).
5858 On Alpha the first 6 words of args are normally in registers
5859 and the rest are pushed. */
5862 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5863 int named ATTRIBUTE_UNUSED
)
5868 /* Don't get confused and pass small structures in FP registers. */
5869 if (type
&& AGGREGATE_TYPE_P (type
))
5873 #ifdef ENABLE_CHECKING
5874 /* With SPLIT_COMPLEX_ARGS, we shouldn't see any raw complex
5876 if (COMPLEX_MODE_P (mode
))
5880 /* Set up defaults for FP operands passed in FP registers, and
5881 integral operands passed in integer registers. */
5882 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5888 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5889 the three platforms, so we can't avoid conditional compilation. */
5890 #if TARGET_ABI_OPEN_VMS
5892 if (mode
== VOIDmode
)
5893 return alpha_arg_info_reg_val (cum
);
5895 num_args
= cum
.num_args
;
5896 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5899 #elif TARGET_ABI_UNICOSMK
5903 /* If this is the last argument, generate the call info word (CIW). */
5904 /* ??? We don't include the caller's line number in the CIW because
5905 I don't know how to determine it if debug infos are turned off. */
5906 if (mode
== VOIDmode
)
5915 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5916 if (cum
.reg_args_type
[i
])
5917 lo
|= (1 << (7 - i
));
5919 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5922 lo
|= cum
.num_reg_words
;
5924 #if HOST_BITS_PER_WIDE_INT == 32
5925 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5927 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5928 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5931 ciw
= immed_double_const (lo
, hi
, DImode
);
5933 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5934 UNSPEC_UMK_LOAD_CIW
);
5937 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5938 num_args
= cum
.num_reg_words
;
5939 if (MUST_PASS_IN_STACK (mode
, type
)
5940 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5942 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5946 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5947 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5949 /* The argument fits in two registers. Note that we still need to
5950 reserve a register for empty structures. */
5954 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5957 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5958 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5959 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5963 #elif TARGET_ABI_OSF
5969 /* VOID is passed as a special flag for "last argument". */
5970 if (type
== void_type_node
)
5972 else if (MUST_PASS_IN_STACK (mode
, type
))
5974 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5978 #error Unhandled ABI
5981 return gen_rtx_REG (mode
, num_args
+ basereg
);
5984 /* Return true if TYPE must be returned in memory, instead of in registers. */
5987 return_in_memory (tree type
, enum machine_mode mode
)
5993 mode
= TYPE_MODE (type
);
5995 /* All aggregates are returned in memory. */
5996 if (AGGREGATE_TYPE_P (type
))
6000 size
= GET_MODE_SIZE (mode
);
6001 switch (GET_MODE_CLASS (mode
))
6003 case MODE_VECTOR_FLOAT
:
6004 /* Pass all float vectors in memory, like an aggregate. */
6007 case MODE_COMPLEX_FLOAT
:
6008 /* We judge complex floats on the size of their element,
6009 not the size of the whole type. */
6010 size
= GET_MODE_UNIT_SIZE (mode
);
6015 case MODE_COMPLEX_INT
:
6016 case MODE_VECTOR_INT
:
6020 /* ??? We get called on all sorts of random stuff from
6021 aggregate_value_p. We can't abort, but it's not clear
6022 what's safe to return. Pretend it's a struct I guess. */
6026 /* Otherwise types must fit in one register. */
6027 return size
> UNITS_PER_WORD
;
6030 /* Define how to find the value returned by a function. VALTYPE is the
6031 data type of the value (as a tree). If the precise function being
6032 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6033 MODE is set instead of VALTYPE for libcalls.
6035 On Alpha the value is found in $0 for integer functions and
6036 $f0 for floating-point functions. */
6039 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
6040 enum machine_mode mode
)
6042 unsigned int regnum
;
6043 enum mode_class
class;
6045 #ifdef ENABLE_CHECKING
6046 if (return_in_memory (valtype
, mode
))
6051 mode
= TYPE_MODE (valtype
);
6053 class = GET_MODE_CLASS (mode
);
6057 /* Do the same thing as PROMOTE_MODE. */
6061 case MODE_COMPLEX_INT
:
6062 case MODE_VECTOR_INT
:
6070 case MODE_COMPLEX_FLOAT
:
6072 enum machine_mode cmode
= GET_MODE_INNER (mode
);
6074 return gen_rtx_PARALLEL
6077 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
6079 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
6080 GEN_INT (GET_MODE_SIZE (cmode
)))));
6087 return gen_rtx_REG (mode
, regnum
);
6091 alpha_build_va_list (void)
6093 tree base
, ofs
, record
, type_decl
;
6095 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6096 return ptr_type_node
;
6098 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6099 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6100 TREE_CHAIN (record
) = type_decl
;
6101 TYPE_NAME (record
) = type_decl
;
6103 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6105 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6107 DECL_FIELD_CONTEXT (ofs
) = record
;
6109 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6111 DECL_FIELD_CONTEXT (base
) = record
;
6112 TREE_CHAIN (base
) = ofs
;
6114 TYPE_FIELDS (record
) = base
;
6115 layout_type (record
);
6120 /* Perform any needed actions needed for a function that is receiving a
6121 variable number of arguments.
6123 On the Alpha, we allocate space for all 12 arg registers, but only
6124 push those that are remaining. However, if NO registers need to be
6125 saved, don't allocate any space. This is not only because we won't
6126 need the space, but because AP includes the current_pretend_args_size
6127 and we don't want to mess up any ap-relative addresses already made.
6129 If we are not to use the floating-point registers, save the integer
6130 registers where we would put the floating-point registers. This is
6131 not the most efficient way to implement varargs with just one register
6132 class, but it isn't worth doing anything more efficient in this rare
6137 alpha_setup_incoming_varargs(CUMULATIVE_ARGS cum
,
6138 enum machine_mode mode ATTRIBUTE_UNUSED
,
6139 tree type ATTRIBUTE_UNUSED
,
6140 int *pretend_size
, int no_rtl
)
6147 int set
= get_varargs_alias_set ();
6150 tmp
= gen_rtx_MEM (BLKmode
,
6151 plus_constant (virtual_incoming_args_rtx
,
6152 (cum
+ 6) * UNITS_PER_WORD
));
6153 set_mem_alias_set (tmp
, set
);
6154 move_block_from_reg (16 + cum
, tmp
, 6 - cum
);
6156 tmp
= gen_rtx_MEM (BLKmode
,
6157 plus_constant (virtual_incoming_args_rtx
,
6158 cum
* UNITS_PER_WORD
));
6159 set_mem_alias_set (tmp
, set
);
6160 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
6163 *pretend_size
= 12 * UNITS_PER_WORD
;
6168 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6170 HOST_WIDE_INT offset
;
6171 tree t
, offset_field
, base_field
;
6173 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6176 if (TARGET_ABI_UNICOSMK
)
6177 std_expand_builtin_va_start (valist
, nextarg
);
6179 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6180 up by 48, storing fp arg registers in the first 48 bytes, and the
6181 integer arg registers in the next 48 bytes. This is only done,
6182 however, if any integer registers need to be stored.
6184 If no integer registers need be stored, then we must subtract 48
6185 in order to account for the integer arg registers which are counted
6186 in argsize above, but which are not actually stored on the stack.
6187 Must further be careful here about structures straddling the last
6188 integer argument register; that futzes with pretend_args_size,
6189 which changes the meaning of AP. */
6192 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6194 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6196 if (TARGET_ABI_OPEN_VMS
)
6198 nextarg
= plus_constant (nextarg
, offset
);
6199 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6200 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6201 make_tree (ptr_type_node
, nextarg
));
6202 TREE_SIDE_EFFECTS (t
) = 1;
6204 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6208 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6209 offset_field
= TREE_CHAIN (base_field
);
6211 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6212 valist
, base_field
);
6213 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6214 valist
, offset_field
);
6216 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6217 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6218 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6219 TREE_SIDE_EFFECTS (t
) = 1;
6220 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6222 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6223 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6224 TREE_SIDE_EFFECTS (t
) = 1;
6225 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6230 alpha_va_arg (tree valist
, tree type
)
6233 tree t
, type_size
, rounded_size
;
6234 tree offset_field
, base_field
, addr_tree
, addend
;
6235 tree wide_type
, wide_ofs
;
6238 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6239 return std_expand_builtin_va_arg (valist
, type
);
6241 if (type
== error_mark_node
6242 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6243 || TREE_OVERFLOW (type_size
))
6244 rounded_size
= size_zero_node
;
6246 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6247 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6248 fold (build (PLUS_EXPR
, sizetype
,
6254 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6255 offset_field
= TREE_CHAIN (base_field
);
6257 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6258 valist
, base_field
);
6259 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6260 valist
, offset_field
);
6262 /* If the type could not be passed in registers, skip the block
6263 reserved for the registers. */
6264 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6266 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6267 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6268 offset_field
, build_int_2 (6*8, 0)));
6269 TREE_SIDE_EFFECTS (t
) = 1;
6270 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6273 wide_type
= make_signed_type (64);
6274 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6278 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6281 rounded_size
= size_int (UNITS_PER_WORD
);
6283 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
6285 rtx real_part
, imag_part
, value
, tmp
;
6287 real_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6288 imag_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6290 /* ??? Most irritatingly, we're not returning the value here,
6291 but the address. Since real_part and imag_part are not
6292 necessarily contiguous, we must copy to local storage. */
6294 real_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), real_part
);
6295 imag_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), imag_part
);
6296 value
= gen_rtx_CONCAT (TYPE_MODE (type
), real_part
, imag_part
);
6298 tmp
= assign_temp (type
, 0, 1, 0);
6299 emit_move_insn (tmp
, value
);
6301 return XEXP (tmp
, 0);
6303 else if (TREE_CODE (type
) == REAL_TYPE
)
6305 tree fpaddend
, cond
;
6307 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6308 addend
, build_int_2 (-6*8, 0)));
6310 cond
= fold (build (LT_EXPR
, integer_type_node
,
6311 wide_ofs
, build_int_2 (6*8, 0)));
6313 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6317 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6318 base_field
, addend
);
6320 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6321 addr
= copy_to_reg (addr
);
6323 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6324 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6325 offset_field
, rounded_size
));
6326 TREE_SIDE_EFFECTS (t
) = 1;
6327 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6331 addr
= force_reg (Pmode
, addr
);
6332 addr
= gen_rtx_MEM (Pmode
, addr
);
6342 ALPHA_BUILTIN_CMPBGE
,
6343 ALPHA_BUILTIN_EXTBL
,
6344 ALPHA_BUILTIN_EXTWL
,
6345 ALPHA_BUILTIN_EXTLL
,
6346 ALPHA_BUILTIN_EXTQL
,
6347 ALPHA_BUILTIN_EXTWH
,
6348 ALPHA_BUILTIN_EXTLH
,
6349 ALPHA_BUILTIN_EXTQH
,
6350 ALPHA_BUILTIN_INSBL
,
6351 ALPHA_BUILTIN_INSWL
,
6352 ALPHA_BUILTIN_INSLL
,
6353 ALPHA_BUILTIN_INSQL
,
6354 ALPHA_BUILTIN_INSWH
,
6355 ALPHA_BUILTIN_INSLH
,
6356 ALPHA_BUILTIN_INSQH
,
6357 ALPHA_BUILTIN_MSKBL
,
6358 ALPHA_BUILTIN_MSKWL
,
6359 ALPHA_BUILTIN_MSKLL
,
6360 ALPHA_BUILTIN_MSKQL
,
6361 ALPHA_BUILTIN_MSKWH
,
6362 ALPHA_BUILTIN_MSKLH
,
6363 ALPHA_BUILTIN_MSKQH
,
6364 ALPHA_BUILTIN_UMULH
,
6366 ALPHA_BUILTIN_ZAPNOT
,
6367 ALPHA_BUILTIN_AMASK
,
6368 ALPHA_BUILTIN_IMPLVER
,
6370 ALPHA_BUILTIN_THREAD_POINTER
,
6371 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6374 ALPHA_BUILTIN_MINUB8
,
6375 ALPHA_BUILTIN_MINSB8
,
6376 ALPHA_BUILTIN_MINUW4
,
6377 ALPHA_BUILTIN_MINSW4
,
6378 ALPHA_BUILTIN_MAXUB8
,
6379 ALPHA_BUILTIN_MAXSB8
,
6380 ALPHA_BUILTIN_MAXUW4
,
6381 ALPHA_BUILTIN_MAXSW4
,
6385 ALPHA_BUILTIN_UNPKBL
,
6386 ALPHA_BUILTIN_UNPKBW
,
6391 ALPHA_BUILTIN_CTPOP
,
6396 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6397 CODE_FOR_builtin_cmpbge
,
6398 CODE_FOR_builtin_extbl
,
6399 CODE_FOR_builtin_extwl
,
6400 CODE_FOR_builtin_extll
,
6401 CODE_FOR_builtin_extql
,
6402 CODE_FOR_builtin_extwh
,
6403 CODE_FOR_builtin_extlh
,
6404 CODE_FOR_builtin_extqh
,
6405 CODE_FOR_builtin_insbl
,
6406 CODE_FOR_builtin_inswl
,
6407 CODE_FOR_builtin_insll
,
6408 CODE_FOR_builtin_insql
,
6409 CODE_FOR_builtin_inswh
,
6410 CODE_FOR_builtin_inslh
,
6411 CODE_FOR_builtin_insqh
,
6412 CODE_FOR_builtin_mskbl
,
6413 CODE_FOR_builtin_mskwl
,
6414 CODE_FOR_builtin_mskll
,
6415 CODE_FOR_builtin_mskql
,
6416 CODE_FOR_builtin_mskwh
,
6417 CODE_FOR_builtin_msklh
,
6418 CODE_FOR_builtin_mskqh
,
6419 CODE_FOR_umuldi3_highpart
,
6420 CODE_FOR_builtin_zap
,
6421 CODE_FOR_builtin_zapnot
,
6422 CODE_FOR_builtin_amask
,
6423 CODE_FOR_builtin_implver
,
6424 CODE_FOR_builtin_rpcc
,
6429 CODE_FOR_builtin_minub8
,
6430 CODE_FOR_builtin_minsb8
,
6431 CODE_FOR_builtin_minuw4
,
6432 CODE_FOR_builtin_minsw4
,
6433 CODE_FOR_builtin_maxub8
,
6434 CODE_FOR_builtin_maxsb8
,
6435 CODE_FOR_builtin_maxuw4
,
6436 CODE_FOR_builtin_maxsw4
,
6437 CODE_FOR_builtin_perr
,
6438 CODE_FOR_builtin_pklb
,
6439 CODE_FOR_builtin_pkwb
,
6440 CODE_FOR_builtin_unpkbl
,
6441 CODE_FOR_builtin_unpkbw
,
6444 CODE_FOR_builtin_cttz
,
6445 CODE_FOR_builtin_ctlz
,
6446 CODE_FOR_builtin_ctpop
6449 struct alpha_builtin_def
6452 enum alpha_builtin code
;
6453 unsigned int target_mask
;
6456 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6457 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6458 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6461 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6462 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6463 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6464 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6465 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6466 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6467 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6468 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6469 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6472 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6473 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6474 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6475 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6476 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6477 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6478 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6479 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6480 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6481 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6482 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6483 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6484 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6485 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6486 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6487 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6488 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6489 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6490 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6491 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6492 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6493 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6494 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6495 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6496 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6497 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6498 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6499 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6500 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6501 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6502 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6503 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6504 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6505 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6506 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6510 alpha_init_builtins (void)
6512 const struct alpha_builtin_def
*p
;
6516 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6518 p
= zero_arg_builtins
;
6519 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6520 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6521 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6524 ftype
= build_function_type_list (long_integer_type_node
,
6525 long_integer_type_node
, NULL_TREE
);
6527 p
= one_arg_builtins
;
6528 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6529 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6530 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6533 ftype
= build_function_type_list (long_integer_type_node
,
6534 long_integer_type_node
,
6535 long_integer_type_node
, NULL_TREE
);
6537 p
= two_arg_builtins
;
6538 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6539 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6540 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6543 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6544 builtin_function ("__builtin_thread_pointer", ftype
,
6545 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6548 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6549 builtin_function ("__builtin_set_thread_pointer", ftype
,
6550 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6554 /* Expand an expression EXP that calls a built-in function,
6555 with result going to TARGET if that's convenient
6556 (and in mode MODE if that's convenient).
6557 SUBTARGET may be used as the target for computing one of EXP's operands.
6558 IGNORE is nonzero if the value is to be ignored. */
6561 alpha_expand_builtin (tree exp
, rtx target
,
6562 rtx subtarget ATTRIBUTE_UNUSED
,
6563 enum machine_mode mode ATTRIBUTE_UNUSED
,
6564 int ignore ATTRIBUTE_UNUSED
)
6568 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6569 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6570 tree arglist
= TREE_OPERAND (exp
, 1);
6571 enum insn_code icode
;
6572 rtx op
[MAX_ARGS
], pat
;
6576 if (fcode
>= ALPHA_BUILTIN_max
)
6577 internal_error ("bad builtin fcode");
6578 icode
= code_for_builtin
[fcode
];
6580 internal_error ("bad builtin fcode");
6582 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6584 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6586 arglist
= TREE_CHAIN (arglist
), arity
++)
6588 const struct insn_operand_data
*insn_op
;
6590 tree arg
= TREE_VALUE (arglist
);
6591 if (arg
== error_mark_node
)
6593 if (arity
> MAX_ARGS
)
6596 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6598 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6600 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6601 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6606 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6608 || GET_MODE (target
) != tmode
6609 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6610 target
= gen_reg_rtx (tmode
);
6616 pat
= GEN_FCN (icode
) (target
);
6620 pat
= GEN_FCN (icode
) (target
, op
[0]);
6622 pat
= GEN_FCN (icode
) (op
[0]);
6625 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6640 /* This page contains routines that are used to determine what the function
6641 prologue and epilogue code will do and write them out. */
6643 /* Compute the size of the save area in the stack. */
6645 /* These variables are used for communication between the following functions.
6646 They indicate various things about the current function being compiled
6647 that are used to tell what kind of prologue, epilogue and procedure
6648 descriptior to generate. */
6650 /* Nonzero if we need a stack procedure. */
6651 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6652 static enum alpha_procedure_types alpha_procedure_type
;
6654 /* Register number (either FP or SP) that is used to unwind the frame. */
6655 static int vms_unwind_regno
;
6657 /* Register number used to save FP. We need not have one for RA since
6658 we don't modify it for register procedures. This is only defined
6659 for register frame procedures. */
6660 static int vms_save_fp_regno
;
6662 /* Register number used to reference objects off our PV. */
6663 static int vms_base_regno
;
6665 /* Compute register masks for saved registers. */
6668 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
6670 unsigned long imask
= 0;
6671 unsigned long fmask
= 0;
6674 /* Irritatingly, there are two kinds of thunks -- those created with
6675 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6676 through the regular part of the compiler. In the
6677 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6678 info, but assemble_start_function wants to output .frame and
6679 .mask directives. */
6680 if (current_function_is_thunk
&& !no_new_pseudos
)
6687 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6688 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6690 /* One for every register we have to save. */
6691 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6692 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6693 && regs_ever_live
[i
] && i
!= REG_RA
6694 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6697 imask
|= (1UL << i
);
6699 fmask
|= (1UL << (i
- 32));
6702 /* We need to restore these for the handler. */
6703 if (current_function_calls_eh_return
)
6707 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6708 if (regno
== INVALID_REGNUM
)
6710 imask
|= 1UL << regno
;
6713 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6714 avoid hackery in unwind-dw2.c, we need to actively store a
6715 zero in the prologue of _Unwind_RaiseException et al. */
6719 /* If any register spilled, then spill the return address also. */
6720 /* ??? This is required by the Digital stack unwind specification
6721 and isn't needed if we're doing Dwarf2 unwinding. */
6722 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6723 imask
|= (1UL << REG_RA
);
6730 alpha_sa_size (void)
6732 unsigned long mask
[2];
6736 alpha_sa_mask (&mask
[0], &mask
[1]);
6738 if (TARGET_ABI_UNICOSMK
)
6740 if (mask
[0] || mask
[1])
6745 for (j
= 0; j
< 2; ++j
)
6746 for (i
= 0; i
< 32; ++i
)
6747 if ((mask
[j
] >> i
) & 1)
6751 if (TARGET_ABI_UNICOSMK
)
6753 /* We might not need to generate a frame if we don't make any calls
6754 (including calls to __T3E_MISMATCH if this is a vararg function),
6755 don't have any local variables which require stack slots, don't
6756 use alloca and have not determined that we need a frame for other
6759 alpha_procedure_type
6760 = (sa_size
|| get_frame_size() != 0
6761 || current_function_outgoing_args_size
6762 || current_function_stdarg
|| current_function_calls_alloca
6763 || frame_pointer_needed
)
6764 ? PT_STACK
: PT_REGISTER
;
6766 /* Always reserve space for saving callee-saved registers if we
6767 need a frame as required by the calling convention. */
6768 if (alpha_procedure_type
== PT_STACK
)
6771 else if (TARGET_ABI_OPEN_VMS
)
6773 /* Start by assuming we can use a register procedure if we don't
6774 make any calls (REG_RA not used) or need to save any
6775 registers and a stack procedure if we do. */
6776 if ((mask
[0] >> REG_RA
) & 1)
6777 alpha_procedure_type
= PT_STACK
;
6778 else if (get_frame_size() != 0)
6779 alpha_procedure_type
= PT_REGISTER
;
6781 alpha_procedure_type
= PT_NULL
;
6783 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6784 made the final decision on stack procedure vs register procedure. */
6785 if (alpha_procedure_type
== PT_STACK
)
6788 /* Decide whether to refer to objects off our PV via FP or PV.
6789 If we need FP for something else or if we receive a nonlocal
6790 goto (which expects PV to contain the value), we must use PV.
6791 Otherwise, start by assuming we can use FP. */
6794 = (frame_pointer_needed
6795 || current_function_has_nonlocal_label
6796 || alpha_procedure_type
== PT_STACK
6797 || current_function_outgoing_args_size
)
6798 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6800 /* If we want to copy PV into FP, we need to find some register
6801 in which to save FP. */
6803 vms_save_fp_regno
= -1;
6804 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6805 for (i
= 0; i
< 32; i
++)
6806 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6807 vms_save_fp_regno
= i
;
6809 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6810 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6811 else if (alpha_procedure_type
== PT_NULL
)
6812 vms_base_regno
= REG_PV
;
6814 /* Stack unwinding should be done via FP unless we use it for PV. */
6815 vms_unwind_regno
= (vms_base_regno
== REG_PV
6816 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6818 /* If this is a stack procedure, allow space for saving FP and RA. */
6819 if (alpha_procedure_type
== PT_STACK
)
6824 /* Our size must be even (multiple of 16 bytes). */
6832 /* Define the offset between two registers, one to be eliminated,
6833 and the other its replacement, at the start of a routine. */
6836 alpha_initial_elimination_offset (unsigned int from
,
6837 unsigned int to ATTRIBUTE_UNUSED
)
6841 ret
= alpha_sa_size ();
6842 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
6844 if (from
== FRAME_POINTER_REGNUM
)
6846 else if (from
== ARG_POINTER_REGNUM
)
6847 ret
+= (ALPHA_ROUND (get_frame_size ()
6848 + current_function_pretend_args_size
)
6849 - current_function_pretend_args_size
);
6857 alpha_pv_save_size (void)
6860 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6864 alpha_using_fp (void)
6867 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6870 #if TARGET_ABI_OPEN_VMS
6872 const struct attribute_spec vms_attribute_table
[] =
6874 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6875 { "overlaid", 0, 0, true, false, false, NULL
},
6876 { "global", 0, 0, true, false, false, NULL
},
6877 { "initialize", 0, 0, true, false, false, NULL
},
6878 { NULL
, 0, 0, false, false, false, NULL
}
6884 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6886 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
6890 alpha_find_lo_sum_using_gp (rtx insn
)
6892 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
6896 alpha_does_function_need_gp (void)
6900 /* The GP being variable is an OSF abi thing. */
6901 if (! TARGET_ABI_OSF
)
6904 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6907 if (current_function_is_thunk
)
6910 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6911 Even if we are a static function, we still need to do this in case
6912 our address is taken and passed to something like qsort. */
6914 push_topmost_sequence ();
6915 insn
= get_insns ();
6916 pop_topmost_sequence ();
6918 for (; insn
; insn
= NEXT_INSN (insn
))
6920 && GET_CODE (PATTERN (insn
)) != USE
6921 && GET_CODE (PATTERN (insn
)) != CLOBBER
6922 && get_attr_usegp (insn
))
6929 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6933 set_frame_related_p (void)
6935 rtx seq
= get_insns ();
6946 while (insn
!= NULL_RTX
)
6948 RTX_FRAME_RELATED_P (insn
) = 1;
6949 insn
= NEXT_INSN (insn
);
6951 seq
= emit_insn (seq
);
6955 seq
= emit_insn (seq
);
6956 RTX_FRAME_RELATED_P (seq
) = 1;
6961 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6963 /* Write function prologue. */
6965 /* On vms we have two kinds of functions:
6967 - stack frame (PROC_STACK)
6968 these are 'normal' functions with local vars and which are
6969 calling other functions
6970 - register frame (PROC_REGISTER)
6971 keeps all data in registers, needs no stack
6973 We must pass this to the assembler so it can generate the
6974 proper pdsc (procedure descriptor)
6975 This is done with the '.pdesc' command.
6977 On not-vms, we don't really differentiate between the two, as we can
6978 simply allocate stack without saving registers. */
6981 alpha_expand_prologue (void)
6983 /* Registers to save. */
6984 unsigned long imask
= 0;
6985 unsigned long fmask
= 0;
6986 /* Stack space needed for pushing registers clobbered by us. */
6987 HOST_WIDE_INT sa_size
;
6988 /* Complete stack size needed. */
6989 HOST_WIDE_INT frame_size
;
6990 /* Offset from base reg to register save area. */
6991 HOST_WIDE_INT reg_offset
;
6995 sa_size
= alpha_sa_size ();
6997 frame_size
= get_frame_size ();
6998 if (TARGET_ABI_OPEN_VMS
)
6999 frame_size
= ALPHA_ROUND (sa_size
7000 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7002 + current_function_pretend_args_size
);
7003 else if (TARGET_ABI_UNICOSMK
)
7004 /* We have to allocate space for the DSIB if we generate a frame. */
7005 frame_size
= ALPHA_ROUND (sa_size
7006 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7007 + ALPHA_ROUND (frame_size
7008 + current_function_outgoing_args_size
);
7010 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7012 + ALPHA_ROUND (frame_size
7013 + current_function_pretend_args_size
));
7015 if (TARGET_ABI_OPEN_VMS
)
7018 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7020 alpha_sa_mask (&imask
, &fmask
);
7022 /* Emit an insn to reload GP, if needed. */
7025 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7026 if (alpha_function_needs_gp
)
7027 emit_insn (gen_prologue_ldgp ());
7030 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7031 the call to mcount ourselves, rather than having the linker do it
7032 magically in response to -pg. Since _mcount has special linkage,
7033 don't represent the call as a call. */
7034 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7035 emit_insn (gen_prologue_mcount ());
7037 if (TARGET_ABI_UNICOSMK
)
7038 unicosmk_gen_dsib (&imask
);
7040 /* Adjust the stack by the frame size. If the frame size is > 4096
7041 bytes, we need to be sure we probe somewhere in the first and last
7042 4096 bytes (we can probably get away without the latter test) and
7043 every 8192 bytes in between. If the frame size is > 32768, we
7044 do this in a loop. Otherwise, we generate the explicit probe
7047 Note that we are only allowed to adjust sp once in the prologue. */
7049 if (frame_size
<= 32768)
7051 if (frame_size
> 4096)
7056 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7059 while ((probed
+= 8192) < frame_size
);
7061 /* We only have to do this probe if we aren't saving registers. */
7062 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7063 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7066 if (frame_size
!= 0)
7067 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7068 GEN_INT (TARGET_ABI_UNICOSMK
7074 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7075 number of 8192 byte blocks to probe. We then probe each block
7076 in the loop and then set SP to the proper location. If the
7077 amount remaining is > 4096, we have to do one more probe if we
7078 are not saving any registers. */
7080 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7081 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7082 rtx ptr
= gen_rtx_REG (DImode
, 22);
7083 rtx count
= gen_rtx_REG (DImode
, 23);
7086 emit_move_insn (count
, GEN_INT (blocks
));
7087 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7088 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7090 /* Because of the difficulty in emitting a new basic block this
7091 late in the compilation, generate the loop as a single insn. */
7092 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7094 if (leftover
> 4096 && sa_size
== 0)
7096 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7097 MEM_VOLATILE_P (last
) = 1;
7098 emit_move_insn (last
, const0_rtx
);
7101 if (TARGET_ABI_WINDOWS_NT
)
7103 /* For NT stack unwind (done by 'reverse execution'), it's
7104 not OK to take the result of a loop, even though the value
7105 is already in ptr, so we reload it via a single operation
7106 and subtract it to sp.
7108 Yes, that's correct -- we have to reload the whole constant
7109 into a temporary via ldah+lda then subtract from sp. To
7110 ensure we get ldah+lda, we use a special pattern. */
7112 HOST_WIDE_INT lo
, hi
;
7113 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7114 hi
= frame_size
- lo
;
7116 emit_move_insn (ptr
, GEN_INT (hi
));
7117 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7118 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7123 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7124 GEN_INT (-leftover
)));
7127 /* This alternative is special, because the DWARF code cannot
7128 possibly intuit through the loop above. So we invent this
7129 note it looks at instead. */
7130 RTX_FRAME_RELATED_P (seq
) = 1;
7132 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7133 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7134 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7135 GEN_INT (TARGET_ABI_UNICOSMK
7141 if (!TARGET_ABI_UNICOSMK
)
7143 /* Cope with very large offsets to the register save area. */
7144 sa_reg
= stack_pointer_rtx
;
7145 if (reg_offset
+ sa_size
> 0x8000)
7147 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7150 if (low
+ sa_size
<= 0x8000)
7151 bias
= reg_offset
- low
, reg_offset
= low
;
7153 bias
= reg_offset
, reg_offset
= 0;
7155 sa_reg
= gen_rtx_REG (DImode
, 24);
7156 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7160 /* Save regs in stack order. Beginning with VMS PV. */
7161 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7163 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7164 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7165 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7168 /* Save register RA next. */
7169 if (imask
& (1UL << REG_RA
))
7171 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7172 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7173 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7174 imask
&= ~(1UL << REG_RA
);
7178 /* Now save any other registers required to be saved. */
7179 for (i
= 0; i
< 31; i
++)
7180 if (imask
& (1UL << i
))
7182 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7183 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7184 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7188 /* Store a zero if requested for unwinding. */
7189 if (imask
& (1UL << 31))
7193 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7194 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7195 insn
= emit_move_insn (mem
, const0_rtx
);
7197 RTX_FRAME_RELATED_P (insn
) = 1;
7198 t
= gen_rtx_REG (Pmode
, 31);
7199 t
= gen_rtx_SET (VOIDmode
, mem
, t
);
7200 t
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, t
, REG_NOTES (insn
));
7201 REG_NOTES (insn
) = t
;
7206 for (i
= 0; i
< 31; i
++)
7207 if (fmask
& (1UL << i
))
7209 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7210 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7211 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7215 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7217 /* The standard frame on the T3E includes space for saving registers.
7218 We just have to use it. We don't have to save the return address and
7219 the old frame pointer here - they are saved in the DSIB. */
7222 for (i
= 9; i
< 15; i
++)
7223 if (imask
& (1UL << i
))
7225 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7227 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7228 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7231 for (i
= 2; i
< 10; i
++)
7232 if (fmask
& (1UL << i
))
7234 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7236 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7237 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7242 if (TARGET_ABI_OPEN_VMS
)
7244 if (alpha_procedure_type
== PT_REGISTER
)
7245 /* Register frame procedures save the fp.
7246 ?? Ought to have a dwarf2 save for this. */
7247 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7248 hard_frame_pointer_rtx
);
7250 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7251 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7252 gen_rtx_REG (DImode
, REG_PV
)));
7254 if (alpha_procedure_type
!= PT_NULL
7255 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7256 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7258 /* If we have to allocate space for outgoing args, do it now. */
7259 if (current_function_outgoing_args_size
!= 0)
7262 = emit_move_insn (stack_pointer_rtx
,
7264 (hard_frame_pointer_rtx
,
7266 (current_function_outgoing_args_size
))));
7268 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7269 if ! frame_pointer_needed. Setting the bit will change the CFA
7270 computation rule to use sp again, which would be wrong if we had
7271 frame_pointer_needed, as this means sp might move unpredictably
7275 frame_pointer_needed
7276 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7278 current_function_outgoing_args_size != 0
7279 => alpha_procedure_type != PT_NULL,
7281 so when we are not setting the bit here, we are guaranteed to
7282 have emitted an FRP frame pointer update just before. */
7283 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7286 else if (!TARGET_ABI_UNICOSMK
)
7288 /* If we need a frame pointer, set it from the stack pointer. */
7289 if (frame_pointer_needed
)
7291 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7292 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7294 /* This must always be the last instruction in the
7295 prologue, thus we emit a special move + clobber. */
7296 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7297 stack_pointer_rtx
, sa_reg
)));
7301 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7302 the prologue, for exception handling reasons, we cannot do this for
7303 any insn that might fault. We could prevent this for mems with a
7304 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7305 have to prevent all such scheduling with a blockage.
7307 Linux, on the other hand, never bothered to implement OSF/1's
7308 exception handling, and so doesn't care about such things. Anyone
7309 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7311 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7312 emit_insn (gen_blockage ());
7315 /* Output the textual info surrounding the prologue. */
7318 alpha_start_function (FILE *file
, const char *fnname
,
7319 tree decl ATTRIBUTE_UNUSED
)
7321 unsigned long imask
= 0;
7322 unsigned long fmask
= 0;
7323 /* Stack space needed for pushing registers clobbered by us. */
7324 HOST_WIDE_INT sa_size
;
7325 /* Complete stack size needed. */
7326 unsigned HOST_WIDE_INT frame_size
;
7327 /* Offset from base reg to register save area. */
7328 HOST_WIDE_INT reg_offset
;
7329 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7332 /* Don't emit an extern directive for functions defined in the same file. */
7333 if (TARGET_ABI_UNICOSMK
)
7336 name_tree
= get_identifier (fnname
);
7337 TREE_ASM_WRITTEN (name_tree
) = 1;
7340 alpha_fnname
= fnname
;
7341 sa_size
= alpha_sa_size ();
7343 frame_size
= get_frame_size ();
7344 if (TARGET_ABI_OPEN_VMS
)
7345 frame_size
= ALPHA_ROUND (sa_size
7346 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7348 + current_function_pretend_args_size
);
7349 else if (TARGET_ABI_UNICOSMK
)
7350 frame_size
= ALPHA_ROUND (sa_size
7351 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7352 + ALPHA_ROUND (frame_size
7353 + current_function_outgoing_args_size
);
7355 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7357 + ALPHA_ROUND (frame_size
7358 + current_function_pretend_args_size
));
7360 if (TARGET_ABI_OPEN_VMS
)
7363 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7365 alpha_sa_mask (&imask
, &fmask
);
7367 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7368 We have to do that before the .ent directive as we cannot switch
7369 files within procedures with native ecoff because line numbers are
7370 linked to procedure descriptors.
7371 Outputting the lineno helps debugging of one line functions as they
7372 would otherwise get no line number at all. Please note that we would
7373 like to put out last_linenum from final.c, but it is not accessible. */
7375 if (write_symbols
== SDB_DEBUG
)
7377 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7378 ASM_OUTPUT_SOURCE_FILENAME (file
,
7379 DECL_SOURCE_FILE (current_function_decl
));
7381 #ifdef ASM_OUTPUT_SOURCE_LINE
7382 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7383 ASM_OUTPUT_SOURCE_LINE (file
,
7384 DECL_SOURCE_LINE (current_function_decl
), 0);
7388 /* Issue function start and label. */
7389 if (TARGET_ABI_OPEN_VMS
7390 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7392 fputs ("\t.ent ", file
);
7393 assemble_name (file
, fnname
);
7396 /* If the function needs GP, we'll write the "..ng" label there.
7397 Otherwise, do it here. */
7399 && ! alpha_function_needs_gp
7400 && ! current_function_is_thunk
)
7403 assemble_name (file
, fnname
);
7404 fputs ("..ng:\n", file
);
7408 strcpy (entry_label
, fnname
);
7409 if (TARGET_ABI_OPEN_VMS
)
7410 strcat (entry_label
, "..en");
7412 /* For public functions, the label must be globalized by appending an
7413 additional colon. */
7414 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7415 strcat (entry_label
, ":");
7417 ASM_OUTPUT_LABEL (file
, entry_label
);
7418 inside_function
= TRUE
;
7420 if (TARGET_ABI_OPEN_VMS
)
7421 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7423 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7424 && !flag_inhibit_size_directive
)
7426 /* Set flags in procedure descriptor to request IEEE-conformant
7427 math-library routines. The value we set it to is PDSC_EXC_IEEE
7428 (/usr/include/pdsc.h). */
7429 fputs ("\t.eflag 48\n", file
);
7432 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7433 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7434 alpha_arg_offset
= -frame_size
+ 48;
7436 /* Describe our frame. If the frame size is larger than an integer,
7437 print it as zero to avoid an assembler error. We won't be
7438 properly describing such a frame, but that's the best we can do. */
7439 if (TARGET_ABI_UNICOSMK
)
7441 else if (TARGET_ABI_OPEN_VMS
)
7442 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7443 HOST_WIDE_INT_PRINT_DEC
"\n",
7445 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7447 else if (!flag_inhibit_size_directive
)
7448 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7449 (frame_pointer_needed
7450 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7451 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7452 current_function_pretend_args_size
);
7454 /* Describe which registers were spilled. */
7455 if (TARGET_ABI_UNICOSMK
)
7457 else if (TARGET_ABI_OPEN_VMS
)
7460 /* ??? Does VMS care if mask contains ra? The old code didn't
7461 set it, so I don't here. */
7462 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7464 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7465 if (alpha_procedure_type
== PT_REGISTER
)
7466 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7468 else if (!flag_inhibit_size_directive
)
7472 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7473 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7475 for (i
= 0; i
< 32; ++i
)
7476 if (imask
& (1UL << i
))
7481 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7482 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7485 #if TARGET_ABI_OPEN_VMS
7486 /* Ifdef'ed cause link_section are only available then. */
7487 readonly_data_section ();
7488 fprintf (file
, "\t.align 3\n");
7489 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7490 fputs ("\t.ascii \"", file
);
7491 assemble_name (file
, fnname
);
7492 fputs ("\\0\"\n", file
);
7493 alpha_need_linkage (fnname
, 1);
7498 /* Emit the .prologue note at the scheduled end of the prologue. */
7501 alpha_output_function_end_prologue (FILE *file
)
7503 if (TARGET_ABI_UNICOSMK
)
7505 else if (TARGET_ABI_OPEN_VMS
)
7506 fputs ("\t.prologue\n", file
);
7507 else if (TARGET_ABI_WINDOWS_NT
)
7508 fputs ("\t.prologue 0\n", file
);
7509 else if (!flag_inhibit_size_directive
)
7510 fprintf (file
, "\t.prologue %d\n",
7511 alpha_function_needs_gp
|| current_function_is_thunk
);
7514 /* Write function epilogue. */
7516 /* ??? At some point we will want to support full unwind, and so will
7517 need to mark the epilogue as well. At the moment, we just confuse
7520 #define FRP(exp) exp
7523 alpha_expand_epilogue (void)
7525 /* Registers to save. */
7526 unsigned long imask
= 0;
7527 unsigned long fmask
= 0;
7528 /* Stack space needed for pushing registers clobbered by us. */
7529 HOST_WIDE_INT sa_size
;
7530 /* Complete stack size needed. */
7531 HOST_WIDE_INT frame_size
;
7532 /* Offset from base reg to register save area. */
7533 HOST_WIDE_INT reg_offset
;
7534 int fp_is_frame_pointer
, fp_offset
;
7535 rtx sa_reg
, sa_reg_exp
= NULL
;
7536 rtx sp_adj1
, sp_adj2
, mem
;
7540 sa_size
= alpha_sa_size ();
7542 frame_size
= get_frame_size ();
7543 if (TARGET_ABI_OPEN_VMS
)
7544 frame_size
= ALPHA_ROUND (sa_size
7545 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7547 + current_function_pretend_args_size
);
7548 else if (TARGET_ABI_UNICOSMK
)
7549 frame_size
= ALPHA_ROUND (sa_size
7550 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7551 + ALPHA_ROUND (frame_size
7552 + current_function_outgoing_args_size
);
7554 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7556 + ALPHA_ROUND (frame_size
7557 + current_function_pretend_args_size
));
7559 if (TARGET_ABI_OPEN_VMS
)
7561 if (alpha_procedure_type
== PT_STACK
)
7567 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7569 alpha_sa_mask (&imask
, &fmask
);
7572 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7573 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7575 sa_reg
= stack_pointer_rtx
;
7577 if (current_function_calls_eh_return
)
7578 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7582 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7584 /* If we have a frame pointer, restore SP from it. */
7585 if ((TARGET_ABI_OPEN_VMS
7586 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7587 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7588 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7590 /* Cope with very large offsets to the register save area. */
7591 if (reg_offset
+ sa_size
> 0x8000)
7593 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7596 if (low
+ sa_size
<= 0x8000)
7597 bias
= reg_offset
- low
, reg_offset
= low
;
7599 bias
= reg_offset
, reg_offset
= 0;
7601 sa_reg
= gen_rtx_REG (DImode
, 22);
7602 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7604 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7607 /* Restore registers in order, excepting a true frame pointer. */
7609 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7611 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7612 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7615 imask
&= ~(1UL << REG_RA
);
7617 for (i
= 0; i
< 31; ++i
)
7618 if (imask
& (1UL << i
))
7620 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7621 fp_offset
= reg_offset
;
7624 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7625 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7626 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7631 if (imask
& (1UL << 31))
7634 for (i
= 0; i
< 31; ++i
)
7635 if (fmask
& (1UL << i
))
7637 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7638 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7639 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7643 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7645 /* Restore callee-saved general-purpose registers. */
7649 for (i
= 9; i
< 15; i
++)
7650 if (imask
& (1UL << i
))
7652 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7654 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7655 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7659 for (i
= 2; i
< 10; i
++)
7660 if (fmask
& (1UL << i
))
7662 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7664 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7665 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7669 /* Restore the return address from the DSIB. */
7671 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7672 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7673 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7676 if (frame_size
|| eh_ofs
)
7678 sp_adj1
= stack_pointer_rtx
;
7682 sp_adj1
= gen_rtx_REG (DImode
, 23);
7683 emit_move_insn (sp_adj1
,
7684 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7687 /* If the stack size is large, begin computation into a temporary
7688 register so as not to interfere with a potential fp restore,
7689 which must be consecutive with an SP restore. */
7690 if (frame_size
< 32768
7691 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7692 sp_adj2
= GEN_INT (frame_size
);
7693 else if (TARGET_ABI_UNICOSMK
)
7695 sp_adj1
= gen_rtx_REG (DImode
, 23);
7696 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7697 sp_adj2
= const0_rtx
;
7699 else if (frame_size
< 0x40007fffL
)
7701 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7703 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7704 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7708 sp_adj1
= gen_rtx_REG (DImode
, 23);
7709 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7711 sp_adj2
= GEN_INT (low
);
7715 rtx tmp
= gen_rtx_REG (DImode
, 23);
7716 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7719 /* We can't drop new things to memory this late, afaik,
7720 so build it up by pieces. */
7721 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7722 -(frame_size
< 0)));
7728 /* From now on, things must be in order. So emit blockages. */
7730 /* Restore the frame pointer. */
7731 if (TARGET_ABI_UNICOSMK
)
7733 emit_insn (gen_blockage ());
7734 mem
= gen_rtx_MEM (DImode
,
7735 plus_constant (hard_frame_pointer_rtx
, -16));
7736 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7737 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7739 else if (fp_is_frame_pointer
)
7741 emit_insn (gen_blockage ());
7742 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7743 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7744 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7746 else if (TARGET_ABI_OPEN_VMS
)
7748 emit_insn (gen_blockage ());
7749 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7750 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7753 /* Restore the stack pointer. */
7754 emit_insn (gen_blockage ());
7755 if (sp_adj2
== const0_rtx
)
7756 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7758 FRP (emit_move_insn (stack_pointer_rtx
,
7759 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7763 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7765 emit_insn (gen_blockage ());
7766 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7767 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7769 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7771 /* Decrement the frame pointer if the function does not have a
7774 emit_insn (gen_blockage ());
7775 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7776 hard_frame_pointer_rtx
, GEN_INT (-1))));
7781 /* Output the rest of the textual info surrounding the epilogue. */
7784 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
7786 /* End the function. */
7787 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7789 fputs ("\t.end ", file
);
7790 assemble_name (file
, fnname
);
7793 inside_function
= FALSE
;
7795 #if TARGET_ABI_OPEN_VMS
7796 alpha_write_linkage (file
, fnname
, decl
);
7799 /* Output jump tables and the static subroutine information block. */
7800 if (TARGET_ABI_UNICOSMK
)
7802 unicosmk_output_ssib (file
, fnname
);
7803 unicosmk_output_deferred_case_vectors (file
);
7808 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7810 In order to avoid the hordes of differences between generated code
7811 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7812 lots of code loading up large constants, generate rtl and emit it
7813 instead of going straight to text.
7815 Not sure why this idea hasn't been explored before... */
7818 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7819 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
7822 HOST_WIDE_INT hi
, lo
;
7823 rtx
this, insn
, funexp
;
7825 /* We always require a valid GP. */
7826 emit_insn (gen_prologue_ldgp ());
7827 emit_note (NOTE_INSN_PROLOGUE_END
);
7829 /* Find the "this" pointer. If the function returns a structure,
7830 the structure return pointer is in $16. */
7831 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7832 this = gen_rtx_REG (Pmode
, 17);
7834 this = gen_rtx_REG (Pmode
, 16);
7836 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7837 entire constant for the add. */
7838 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7839 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7840 if (hi
+ lo
== delta
)
7843 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7845 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7849 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7850 delta
, -(delta
< 0));
7851 emit_insn (gen_adddi3 (this, this, tmp
));
7854 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7859 tmp
= gen_rtx_REG (Pmode
, 0);
7860 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
7862 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
7863 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7864 if (hi
+ lo
== vcall_offset
)
7867 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
7871 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
7872 vcall_offset
, -(vcall_offset
< 0));
7873 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
7877 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
7880 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
7882 emit_insn (gen_adddi3 (this, this, tmp
));
7885 /* Generate a tail call to the target function. */
7886 if (! TREE_USED (function
))
7888 assemble_external (function
);
7889 TREE_USED (function
) = 1;
7891 funexp
= XEXP (DECL_RTL (function
), 0);
7892 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7893 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7894 SIBLING_CALL_P (insn
) = 1;
7896 /* Run just enough of rest_of_compilation to get the insns emitted.
7897 There's not really enough bulk here to make other passes such as
7898 instruction scheduling worth while. Note that use_thunk calls
7899 assemble_start_function and assemble_end_function. */
7900 insn
= get_insns ();
7901 insn_locators_initialize ();
7902 shorten_branches (insn
);
7903 final_start_function (insn
, file
, 1);
7904 final (insn
, file
, 1, 0);
7905 final_end_function ();
7907 #endif /* TARGET_ABI_OSF */
7909 /* Debugging support. */
7913 /* Count the number of sdb related labels are generated (to find block
7914 start and end boundaries). */
7916 int sdb_label_count
= 0;
7918 /* Next label # for each statement. */
7920 static int sym_lineno
= 0;
7922 /* Count the number of .file directives, so that .loc is up to date. */
7924 static int num_source_filenames
= 0;
7926 /* Name of the file containing the current function. */
7928 static const char *current_function_file
= "";
7930 /* Offsets to alpha virtual arg/local debugging pointers. */
7932 long alpha_arg_offset
;
7933 long alpha_auto_offset
;
7935 /* Emit a new filename to a stream. */
7938 alpha_output_filename (FILE *stream
, const char *name
)
7940 static int first_time
= TRUE
;
7941 char ltext_label_name
[100];
7946 ++num_source_filenames
;
7947 current_function_file
= name
;
7948 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7949 output_quoted_string (stream
, name
);
7950 fprintf (stream
, "\n");
7951 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7952 fprintf (stream
, "\t#@stabs\n");
7955 else if (write_symbols
== DBX_DEBUG
)
7957 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7958 fprintf (stream
, "%s", ASM_STABS_OP
);
7959 output_quoted_string (stream
, name
);
7960 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7963 else if (name
!= current_function_file
7964 && strcmp (name
, current_function_file
) != 0)
7966 if (inside_function
&& ! TARGET_GAS
)
7967 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7970 ++num_source_filenames
;
7971 current_function_file
= name
;
7972 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7975 output_quoted_string (stream
, name
);
7976 fprintf (stream
, "\n");
7980 /* Emit a linenumber to a stream. */
7983 alpha_output_lineno (FILE *stream
, int line
)
7985 if (write_symbols
== DBX_DEBUG
)
7987 /* mips-tfile doesn't understand .stabd directives. */
7989 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7990 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
7993 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
7996 /* Structure to show the current status of registers and memory. */
7998 struct shadow_summary
8001 unsigned int i
: 31; /* Mask of int regs */
8002 unsigned int fp
: 31; /* Mask of fp regs */
8003 unsigned int mem
: 1; /* mem == imem | fpmem */
8007 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8008 to the summary structure. SET is nonzero if the insn is setting the
8009 object, otherwise zero. */
8012 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8014 const char *format_ptr
;
8020 switch (GET_CODE (x
))
8022 /* ??? Note that this case would be incorrect if the Alpha had a
8023 ZERO_EXTRACT in SET_DEST. */
8025 summarize_insn (SET_SRC (x
), sum
, 0);
8026 summarize_insn (SET_DEST (x
), sum
, 1);
8030 summarize_insn (XEXP (x
, 0), sum
, 1);
8034 summarize_insn (XEXP (x
, 0), sum
, 0);
8038 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8039 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8043 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8044 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8048 summarize_insn (SUBREG_REG (x
), sum
, 0);
8053 int regno
= REGNO (x
);
8054 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8056 if (regno
== 31 || regno
== 63)
8062 sum
->defd
.i
|= mask
;
8064 sum
->defd
.fp
|= mask
;
8069 sum
->used
.i
|= mask
;
8071 sum
->used
.fp
|= mask
;
8082 /* Find the regs used in memory address computation: */
8083 summarize_insn (XEXP (x
, 0), sum
, 0);
8086 case CONST_INT
: case CONST_DOUBLE
:
8087 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8088 case SCRATCH
: case ASM_INPUT
:
8091 /* Handle common unary and binary ops for efficiency. */
8092 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8093 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8094 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8095 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8096 case NE
: case EQ
: case GE
: case GT
: case LE
:
8097 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8098 summarize_insn (XEXP (x
, 0), sum
, 0);
8099 summarize_insn (XEXP (x
, 1), sum
, 0);
8102 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8103 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8104 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8105 case SQRT
: case FFS
:
8106 summarize_insn (XEXP (x
, 0), sum
, 0);
8110 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8111 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8112 switch (format_ptr
[i
])
8115 summarize_insn (XEXP (x
, i
), sum
, 0);
8119 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8120 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8132 /* Ensure a sufficient number of `trapb' insns are in the code when
8133 the user requests code with a trap precision of functions or
8136 In naive mode, when the user requests a trap-precision of
8137 "instruction", a trapb is needed after every instruction that may
8138 generate a trap. This ensures that the code is resumption safe but
8141 When optimizations are turned on, we delay issuing a trapb as long
8142 as possible. In this context, a trap shadow is the sequence of
8143 instructions that starts with a (potentially) trap generating
8144 instruction and extends to the next trapb or call_pal instruction
8145 (but GCC never generates call_pal by itself). We can delay (and
8146 therefore sometimes omit) a trapb subject to the following
8149 (a) On entry to the trap shadow, if any Alpha register or memory
8150 location contains a value that is used as an operand value by some
8151 instruction in the trap shadow (live on entry), then no instruction
8152 in the trap shadow may modify the register or memory location.
8154 (b) Within the trap shadow, the computation of the base register
8155 for a memory load or store instruction may not involve using the
8156 result of an instruction that might generate an UNPREDICTABLE
8159 (c) Within the trap shadow, no register may be used more than once
8160 as a destination register. (This is to make life easier for the
8163 (d) The trap shadow may not include any branch instructions. */
8166 alpha_handle_trap_shadows (void)
8168 struct shadow_summary shadow
;
8169 int trap_pending
, exception_nesting
;
8173 exception_nesting
= 0;
8176 shadow
.used
.mem
= 0;
8177 shadow
.defd
= shadow
.used
;
8179 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8181 if (GET_CODE (i
) == NOTE
)
8183 switch (NOTE_LINE_NUMBER (i
))
8185 case NOTE_INSN_EH_REGION_BEG
:
8186 exception_nesting
++;
8191 case NOTE_INSN_EH_REGION_END
:
8192 exception_nesting
--;
8197 case NOTE_INSN_EPILOGUE_BEG
:
8198 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8203 else if (trap_pending
)
8205 if (alpha_tp
== ALPHA_TP_FUNC
)
8207 if (GET_CODE (i
) == JUMP_INSN
8208 && GET_CODE (PATTERN (i
)) == RETURN
)
8211 else if (alpha_tp
== ALPHA_TP_INSN
)
8215 struct shadow_summary sum
;
8220 sum
.defd
= sum
.used
;
8222 switch (GET_CODE (i
))
8225 /* Annoyingly, get_attr_trap will abort on these. */
8226 if (GET_CODE (PATTERN (i
)) == USE
8227 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8230 summarize_insn (PATTERN (i
), &sum
, 0);
8232 if ((sum
.defd
.i
& shadow
.defd
.i
)
8233 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8235 /* (c) would be violated */
8239 /* Combine shadow with summary of current insn: */
8240 shadow
.used
.i
|= sum
.used
.i
;
8241 shadow
.used
.fp
|= sum
.used
.fp
;
8242 shadow
.used
.mem
|= sum
.used
.mem
;
8243 shadow
.defd
.i
|= sum
.defd
.i
;
8244 shadow
.defd
.fp
|= sum
.defd
.fp
;
8245 shadow
.defd
.mem
|= sum
.defd
.mem
;
8247 if ((sum
.defd
.i
& shadow
.used
.i
)
8248 || (sum
.defd
.fp
& shadow
.used
.fp
)
8249 || (sum
.defd
.mem
& shadow
.used
.mem
))
8251 /* (a) would be violated (also takes care of (b)) */
8252 if (get_attr_trap (i
) == TRAP_YES
8253 && ((sum
.defd
.i
& sum
.used
.i
)
8254 || (sum
.defd
.fp
& sum
.used
.fp
)))
8273 n
= emit_insn_before (gen_trapb (), i
);
8274 PUT_MODE (n
, TImode
);
8275 PUT_MODE (i
, TImode
);
8279 shadow
.used
.mem
= 0;
8280 shadow
.defd
= shadow
.used
;
8285 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8286 && GET_CODE (i
) == INSN
8287 && GET_CODE (PATTERN (i
)) != USE
8288 && GET_CODE (PATTERN (i
)) != CLOBBER
8289 && get_attr_trap (i
) == TRAP_YES
)
8291 if (optimize
&& !trap_pending
)
8292 summarize_insn (PATTERN (i
), &shadow
, 0);
8298 /* Alpha can only issue instruction groups simultaneously if they are
8299 suitably aligned. This is very processor-specific. */
8301 enum alphaev4_pipe
{
8308 enum alphaev5_pipe
{
8319 static enum alphaev4_pipe
8320 alphaev4_insn_pipe (rtx insn
)
8322 if (recog_memoized (insn
) < 0)
8324 if (get_attr_length (insn
) != 4)
8327 switch (get_attr_type (insn
))
8361 static enum alphaev5_pipe
8362 alphaev5_insn_pipe (rtx insn
)
8364 if (recog_memoized (insn
) < 0)
8366 if (get_attr_length (insn
) != 4)
8369 switch (get_attr_type (insn
))
8410 /* IN_USE is a mask of the slots currently filled within the insn group.
8411 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8412 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8414 LEN is, of course, the length of the group in bytes. */
8417 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8424 || GET_CODE (PATTERN (insn
)) == CLOBBER
8425 || GET_CODE (PATTERN (insn
)) == USE
)
8430 enum alphaev4_pipe pipe
;
8432 pipe
= alphaev4_insn_pipe (insn
);
8436 /* Force complex instructions to start new groups. */
8440 /* If this is a completely unrecognized insn, its an asm.
8441 We don't know how long it is, so record length as -1 to
8442 signal a needed realignment. */
8443 if (recog_memoized (insn
) < 0)
8446 len
= get_attr_length (insn
);
8450 if (in_use
& EV4_IB0
)
8452 if (in_use
& EV4_IB1
)
8457 in_use
|= EV4_IB0
| EV4_IBX
;
8461 if (in_use
& EV4_IB0
)
8463 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8471 if (in_use
& EV4_IB1
)
8481 /* Haifa doesn't do well scheduling branches. */
8482 if (GET_CODE (insn
) == JUMP_INSN
)
8486 insn
= next_nonnote_insn (insn
);
8488 if (!insn
|| ! INSN_P (insn
))
8491 /* Let Haifa tell us where it thinks insn group boundaries are. */
8492 if (GET_MODE (insn
) == TImode
)
8495 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8500 insn
= next_nonnote_insn (insn
);
8508 /* IN_USE is a mask of the slots currently filled within the insn group.
8509 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8510 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8512 LEN is, of course, the length of the group in bytes. */
8515 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8522 || GET_CODE (PATTERN (insn
)) == CLOBBER
8523 || GET_CODE (PATTERN (insn
)) == USE
)
8528 enum alphaev5_pipe pipe
;
8530 pipe
= alphaev5_insn_pipe (insn
);
8534 /* Force complex instructions to start new groups. */
8538 /* If this is a completely unrecognized insn, its an asm.
8539 We don't know how long it is, so record length as -1 to
8540 signal a needed realignment. */
8541 if (recog_memoized (insn
) < 0)
8544 len
= get_attr_length (insn
);
8547 /* ??? Most of the places below, we would like to abort, as
8548 it would indicate an error either in Haifa, or in the
8549 scheduling description. Unfortunately, Haifa never
8550 schedules the last instruction of the BB, so we don't
8551 have an accurate TI bit to go off. */
8553 if (in_use
& EV5_E0
)
8555 if (in_use
& EV5_E1
)
8560 in_use
|= EV5_E0
| EV5_E01
;
8564 if (in_use
& EV5_E0
)
8566 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8574 if (in_use
& EV5_E1
)
8580 if (in_use
& EV5_FA
)
8582 if (in_use
& EV5_FM
)
8587 in_use
|= EV5_FA
| EV5_FAM
;
8591 if (in_use
& EV5_FA
)
8597 if (in_use
& EV5_FM
)
8610 /* Haifa doesn't do well scheduling branches. */
8611 /* ??? If this is predicted not-taken, slotting continues, except
8612 that no more IBR, FBR, or JSR insns may be slotted. */
8613 if (GET_CODE (insn
) == JUMP_INSN
)
8617 insn
= next_nonnote_insn (insn
);
8619 if (!insn
|| ! INSN_P (insn
))
8622 /* Let Haifa tell us where it thinks insn group boundaries are. */
8623 if (GET_MODE (insn
) == TImode
)
8626 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8631 insn
= next_nonnote_insn (insn
);
8640 alphaev4_next_nop (int *pin_use
)
8642 int in_use
= *pin_use
;
8645 if (!(in_use
& EV4_IB0
))
8650 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8655 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8668 alphaev5_next_nop (int *pin_use
)
8670 int in_use
= *pin_use
;
8673 if (!(in_use
& EV5_E1
))
8678 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8683 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8695 /* The instruction group alignment main loop. */
8698 alpha_align_insns (unsigned int max_align
,
8699 rtx (*next_group
) (rtx
, int *, int *),
8700 rtx (*next_nop
) (int *))
8702 /* ALIGN is the known alignment for the insn group. */
8704 /* OFS is the offset of the current insn in the insn group. */
8706 int prev_in_use
, in_use
, len
;
8709 /* Let shorten branches care for assigning alignments to code labels. */
8710 shorten_branches (get_insns ());
8712 if (align_functions
< 4)
8714 else if ((unsigned int) align_functions
< max_align
)
8715 align
= align_functions
;
8719 ofs
= prev_in_use
= 0;
8721 if (GET_CODE (i
) == NOTE
)
8722 i
= next_nonnote_insn (i
);
8726 next
= (*next_group
) (i
, &in_use
, &len
);
8728 /* When we see a label, resync alignment etc. */
8729 if (GET_CODE (i
) == CODE_LABEL
)
8731 unsigned int new_align
= 1 << label_to_alignment (i
);
8733 if (new_align
>= align
)
8735 align
= new_align
< max_align
? new_align
: max_align
;
8739 else if (ofs
& (new_align
-1))
8740 ofs
= (ofs
| (new_align
-1)) + 1;
8745 /* Handle complex instructions special. */
8746 else if (in_use
== 0)
8748 /* Asms will have length < 0. This is a signal that we have
8749 lost alignment knowledge. Assume, however, that the asm
8750 will not mis-align instructions. */
8759 /* If the known alignment is smaller than the recognized insn group,
8760 realign the output. */
8761 else if ((int) align
< len
)
8763 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8766 where
= prev
= prev_nonnote_insn (i
);
8767 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8770 /* Can't realign between a call and its gp reload. */
8771 if (! (TARGET_EXPLICIT_RELOCS
8772 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8774 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8775 align
= 1 << new_log_align
;
8780 /* If the group won't fit in the same INT16 as the previous,
8781 we need to add padding to keep the group together. Rather
8782 than simply leaving the insn filling to the assembler, we
8783 can make use of the knowledge of what sorts of instructions
8784 were issued in the previous group to make sure that all of
8785 the added nops are really free. */
8786 else if (ofs
+ len
> (int) align
)
8788 int nop_count
= (align
- ofs
) / 4;
8791 /* Insert nops before labels, branches, and calls to truely merge
8792 the execution of the nops with the previous instruction group. */
8793 where
= prev_nonnote_insn (i
);
8796 if (GET_CODE (where
) == CODE_LABEL
)
8798 rtx where2
= prev_nonnote_insn (where
);
8799 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8802 else if (GET_CODE (where
) == INSN
)
8809 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8810 while (--nop_count
);
8814 ofs
= (ofs
+ len
) & (align
- 1);
8815 prev_in_use
= in_use
;
8820 /* Machine dependent reorg pass. */
8825 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8826 alpha_handle_trap_shadows ();
8828 /* Due to the number of extra trapb insns, don't bother fixing up
8829 alignment when trap precision is instruction. Moreover, we can
8830 only do our job when sched2 is run. */
8831 if (optimize
&& !optimize_size
8832 && alpha_tp
!= ALPHA_TP_INSN
8833 && flag_schedule_insns_after_reload
)
8835 if (alpha_cpu
== PROCESSOR_EV4
)
8836 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
8837 else if (alpha_cpu
== PROCESSOR_EV5
)
8838 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
8842 #if !TARGET_ABI_UNICOSMK
8849 alpha_file_start (void)
8851 #ifdef OBJECT_FORMAT_ELF
8852 /* If emitting dwarf2 debug information, we cannot generate a .file
8853 directive to start the file, as it will conflict with dwarf2out
8854 file numbers. So it's only useful when emitting mdebug output. */
8855 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
8858 default_file_start ();
8860 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
8863 fputs ("\t.set noreorder\n", asm_out_file
);
8864 fputs ("\t.set volatile\n", asm_out_file
);
8865 if (!TARGET_ABI_OPEN_VMS
)
8866 fputs ("\t.set noat\n", asm_out_file
);
8867 if (TARGET_EXPLICIT_RELOCS
)
8868 fputs ("\t.set nomacro\n", asm_out_file
);
8869 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
8870 fprintf (asm_out_file
,
8872 TARGET_CPU_EV6
? "ev6"
8874 ? (TARGET_MAX
? "pca56" : TARGET_BWX
? "ev56" : "ev5")
8879 #ifdef OBJECT_FORMAT_ELF
8881 /* Switch to the section to which we should output X. The only thing
8882 special we do here is to honor small data. */
8885 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
8886 unsigned HOST_WIDE_INT align
)
8888 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8889 /* ??? Consider using mergeable sdata sections. */
8892 default_elf_select_rtx_section (mode
, x
, align
);
8895 #endif /* OBJECT_FORMAT_ELF */
8897 /* Structure to collect function names for final output in link section. */
8898 /* Note that items marked with GTY can't be ifdef'ed out. */
8900 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8901 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
8903 struct alpha_links
GTY(())
8907 enum links_kind lkind
;
8908 enum reloc_kind rkind
;
8911 struct alpha_funcs
GTY(())
8914 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8918 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8919 splay_tree alpha_links_tree
;
8920 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
8921 splay_tree alpha_funcs_tree
;
8923 static GTY(()) int alpha_funcs_num
;
8925 #if TARGET_ABI_OPEN_VMS
8927 /* Return the VMS argument type corresponding to MODE. */
8930 alpha_arg_type (enum machine_mode mode
)
8935 return TARGET_FLOAT_VAX
? FF
: FS
;
8937 return TARGET_FLOAT_VAX
? FD
: FT
;
8943 /* Return an rtx for an integer representing the VMS Argument Information
8947 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
8949 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8952 for (i
= 0; i
< 6; i
++)
8953 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8955 return GEN_INT (regval
);
8958 /* Make (or fake) .linkage entry for function call.
8960 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8962 Return an SYMBOL_REF rtx for the linkage. */
8965 alpha_need_linkage (const char *name
, int is_local
)
8967 splay_tree_node node
;
8968 struct alpha_links
*al
;
8975 struct alpha_funcs
*cfaf
;
8977 if (!alpha_funcs_tree
)
8978 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
8979 splay_tree_compare_pointers
);
8981 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
8984 cfaf
->num
= ++alpha_funcs_num
;
8986 splay_tree_insert (alpha_funcs_tree
,
8987 (splay_tree_key
) current_function_decl
,
8988 (splay_tree_value
) cfaf
);
8991 if (alpha_links_tree
)
8993 /* Is this name already defined? */
8995 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
8998 al
= (struct alpha_links
*) node
->value
;
9001 /* Defined here but external assumed. */
9002 if (al
->lkind
== KIND_EXTERN
)
9003 al
->lkind
= KIND_LOCAL
;
9007 /* Used here but unused assumed. */
9008 if (al
->lkind
== KIND_UNUSED
)
9009 al
->lkind
= KIND_LOCAL
;
9015 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9017 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9018 name
= ggc_strdup (name
);
9020 /* Assume external if no definition. */
9021 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9023 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9024 get_identifier (name
);
9026 /* Construct a SYMBOL_REF for us to call. */
9028 size_t name_len
= strlen (name
);
9029 char *linksym
= alloca (name_len
+ 6);
9031 memcpy (linksym
+ 1, name
, name_len
);
9032 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9033 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9034 ggc_alloc_string (linksym
, name_len
+ 5));
9037 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9038 (splay_tree_value
) al
);
9044 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9046 splay_tree_node cfunnode
;
9047 struct alpha_funcs
*cfaf
;
9048 struct alpha_links
*al
;
9049 const char *name
= XSTR (linkage
, 0);
9051 cfaf
= (struct alpha_funcs
*) 0;
9052 al
= (struct alpha_links
*) 0;
9054 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9055 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9059 splay_tree_node lnode
;
9061 /* Is this name already defined? */
9063 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9065 al
= (struct alpha_links
*) lnode
->value
;
9068 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9076 splay_tree_node node
= 0;
9077 struct alpha_links
*anl
;
9082 name_len
= strlen (name
);
9084 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9085 al
->num
= cfaf
->num
;
9087 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9090 anl
= (struct alpha_links
*) node
->value
;
9091 al
->lkind
= anl
->lkind
;
9094 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9095 buflen
= strlen (buf
);
9096 linksym
= alloca (buflen
+ 1);
9097 memcpy (linksym
, buf
, buflen
+ 1);
9099 al
->linkage
= gen_rtx_SYMBOL_REF
9100 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9102 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9103 (splay_tree_value
) al
);
9107 al
->rkind
= KIND_CODEADDR
;
9109 al
->rkind
= KIND_LINKAGE
;
9112 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9118 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9120 const char *const name
= (const char *) node
->key
;
9121 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9122 FILE *stream
= (FILE *) data
;
9124 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9125 if (link
->rkind
== KIND_CODEADDR
)
9127 if (link
->lkind
== KIND_LOCAL
)
9129 /* Local and used */
9130 fprintf (stream
, "\t.quad %s..en\n", name
);
9134 /* External and used, request code address. */
9135 fprintf (stream
, "\t.code_address %s\n", name
);
9140 if (link
->lkind
== KIND_LOCAL
)
9142 /* Local and used, build linkage pair. */
9143 fprintf (stream
, "\t.quad %s..en\n", name
);
9144 fprintf (stream
, "\t.quad %s\n", name
);
9148 /* External and used, request linkage pair. */
9149 fprintf (stream
, "\t.linkage %s\n", name
);
9157 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9159 splay_tree_node node
;
9160 struct alpha_funcs
*func
;
9163 fprintf (stream
, "\t.align 3\n");
9164 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9165 func
= (struct alpha_funcs
*) node
->value
;
9167 fputs ("\t.name ", stream
);
9168 assemble_name (stream
, funname
);
9169 fputs ("..na\n", stream
);
9170 ASM_OUTPUT_LABEL (stream
, funname
);
9171 fprintf (stream
, "\t.pdesc ");
9172 assemble_name (stream
, funname
);
9173 fprintf (stream
, "..en,%s\n",
9174 alpha_procedure_type
== PT_STACK
? "stack"
9175 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9179 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9180 /* splay_tree_delete (func->links); */
9184 /* Given a decl, a section name, and whether the decl initializer
9185 has relocs, choose attributes for the section. */
9187 #define SECTION_VMS_OVERLAY SECTION_FORGET
9188 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9189 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9192 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9194 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9196 if (decl
&& DECL_ATTRIBUTES (decl
)
9197 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9198 flags
|= SECTION_VMS_OVERLAY
;
9199 if (decl
&& DECL_ATTRIBUTES (decl
)
9200 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9201 flags
|= SECTION_VMS_GLOBAL
;
9202 if (decl
&& DECL_ATTRIBUTES (decl
)
9203 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9204 flags
|= SECTION_VMS_INITIALIZE
;
9209 /* Switch to an arbitrary section NAME with attributes as specified
9210 by FLAGS. ALIGN specifies any known alignment requirements for
9211 the section; 0 if the default should be used. */
9214 vms_asm_named_section (const char *name
, unsigned int flags
)
9216 fputc ('\n', asm_out_file
);
9217 fprintf (asm_out_file
, ".section\t%s", name
);
9219 if (flags
& SECTION_VMS_OVERLAY
)
9220 fprintf (asm_out_file
, ",OVR");
9221 if (flags
& SECTION_VMS_GLOBAL
)
9222 fprintf (asm_out_file
, ",GBL");
9223 if (flags
& SECTION_VMS_INITIALIZE
)
9224 fprintf (asm_out_file
, ",NOMOD");
9225 if (flags
& SECTION_DEBUG
)
9226 fprintf (asm_out_file
, ",NOWRT");
9228 fputc ('\n', asm_out_file
);
9231 /* Record an element in the table of global constructors. SYMBOL is
9232 a SYMBOL_REF of the function to be called; PRIORITY is a number
9233 between 0 and MAX_INIT_PRIORITY.
9235 Differs from default_ctors_section_asm_out_constructor in that the
9236 width of the .ctors entry is always 64 bits, rather than the 32 bits
9237 used by a normal pointer. */
9240 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9243 assemble_align (BITS_PER_WORD
);
9244 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9248 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9251 assemble_align (BITS_PER_WORD
);
9252 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9257 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9258 int is_local ATTRIBUTE_UNUSED
)
9264 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9265 tree cfundecl ATTRIBUTE_UNUSED
,
9266 int lflag ATTRIBUTE_UNUSED
,
9267 int rflag ATTRIBUTE_UNUSED
)
9272 #endif /* TARGET_ABI_OPEN_VMS */
9274 #if TARGET_ABI_UNICOSMK
9276 /* Define the offset between two registers, one to be eliminated, and the
9277 other its replacement, at the start of a routine. */
9280 unicosmk_initial_elimination_offset (int from
, int to
)
9284 fixed_size
= alpha_sa_size();
9285 if (fixed_size
!= 0)
9288 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9290 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9292 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9293 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9294 + ALPHA_ROUND (get_frame_size()));
9295 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9296 return (ALPHA_ROUND (fixed_size
)
9297 + ALPHA_ROUND (get_frame_size()
9298 + current_function_outgoing_args_size
));
9303 /* Output the module name for .ident and .end directives. We have to strip
9304 directories and add make sure that the module name starts with a letter
9308 unicosmk_output_module_name (FILE *file
)
9310 const char *name
= lbasename (main_input_filename
);
9311 unsigned len
= strlen (name
);
9312 char *clean_name
= alloca (len
+ 2);
9313 char *ptr
= clean_name
;
9315 /* CAM only accepts module names that start with a letter or '$'. We
9316 prefix the module name with a '$' if necessary. */
9318 if (!ISALPHA (*name
))
9320 memcpy (ptr
, name
, len
+ 1);
9321 clean_symbol_name (clean_name
);
9322 fputs (clean_name
, file
);
9325 /* Output the definition of a common variable. */
9328 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9331 printf ("T3E__: common %s\n", name
);
9334 fputs("\t.endp\n\n\t.psect ", file
);
9335 assemble_name(file
, name
);
9336 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9337 fprintf(file
, "\t.byte\t0:%d\n", size
);
9339 /* Mark the symbol as defined in this module. */
9340 name_tree
= get_identifier (name
);
9341 TREE_ASM_WRITTEN (name_tree
) = 1;
9344 #define SECTION_PUBLIC SECTION_MACH_DEP
9345 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9346 static int current_section_align
;
9349 unicosmk_section_type_flags (tree decl
, const char *name
,
9350 int reloc ATTRIBUTE_UNUSED
)
9352 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9357 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9359 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9360 if (align_functions_log
> current_section_align
)
9361 current_section_align
= align_functions_log
;
9363 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9364 flags
|= SECTION_MAIN
;
9367 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9369 if (TREE_PUBLIC (decl
))
9370 flags
|= SECTION_PUBLIC
;
9375 /* Generate a section name for decl and associate it with the
9379 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9387 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9388 name
= default_strip_name_encoding (name
);
9389 len
= strlen (name
);
9391 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9395 /* It is essential that we prefix the section name here because
9396 otherwise the section names generated for constructors and
9397 destructors confuse collect2. */
9399 string
= alloca (len
+ 6);
9400 sprintf (string
, "code@%s", name
);
9401 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9403 else if (TREE_PUBLIC (decl
))
9404 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9409 string
= alloca (len
+ 6);
9410 sprintf (string
, "data@%s", name
);
9411 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9415 /* Switch to an arbitrary section NAME with attributes as specified
9416 by FLAGS. ALIGN specifies any known alignment requirements for
9417 the section; 0 if the default should be used. */
9420 unicosmk_asm_named_section (const char *name
, unsigned int flags
)
9424 /* Close the previous section. */
9426 fputs ("\t.endp\n\n", asm_out_file
);
9428 /* Find out what kind of section we are opening. */
9430 if (flags
& SECTION_MAIN
)
9431 fputs ("\t.start\tmain\n", asm_out_file
);
9433 if (flags
& SECTION_CODE
)
9435 else if (flags
& SECTION_PUBLIC
)
9440 if (current_section_align
!= 0)
9441 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9442 current_section_align
, kind
);
9444 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9448 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9451 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9452 unicosmk_unique_section (decl
, 0);
9455 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9456 in code sections because .align fill unused space with zeroes. */
9459 unicosmk_output_align (FILE *file
, int align
)
9461 if (inside_function
)
9462 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9464 fprintf (file
, "\t.align\t%d\n", align
);
9467 /* Add a case vector to the current function's list of deferred case
9468 vectors. Case vectors have to be put into a separate section because CAM
9469 does not allow data definitions in code sections. */
9472 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9474 struct machine_function
*machine
= cfun
->machine
;
9476 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9477 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9478 machine
->addr_list
);
9481 /* Output a case vector. */
9484 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9486 rtx lab
= XEXP (vec
, 0);
9487 rtx body
= XEXP (vec
, 1);
9488 int vlen
= XVECLEN (body
, 0);
9491 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9493 for (idx
= 0; idx
< vlen
; idx
++)
9495 ASM_OUTPUT_ADDR_VEC_ELT
9496 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9500 /* Output current function's deferred case vectors. */
9503 unicosmk_output_deferred_case_vectors (FILE *file
)
9505 struct machine_function
*machine
= cfun
->machine
;
9508 if (machine
->addr_list
== NULL_RTX
)
9512 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9513 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9516 /* Generate the name of the SSIB section for the current function. */
9518 #define SSIB_PREFIX "__SSIB_"
9519 #define SSIB_PREFIX_LEN 7
9522 unicosmk_ssib_name (void)
9524 /* This is ok since CAM won't be able to deal with names longer than that
9527 static char name
[256];
9533 x
= DECL_RTL (cfun
->decl
);
9534 if (GET_CODE (x
) != MEM
)
9537 if (GET_CODE (x
) != SYMBOL_REF
)
9539 fnname
= XSTR (x
, 0);
9541 len
= strlen (fnname
);
9542 if (len
+ SSIB_PREFIX_LEN
> 255)
9543 len
= 255 - SSIB_PREFIX_LEN
;
9545 strcpy (name
, SSIB_PREFIX
);
9546 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9547 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9552 /* Set up the dynamic subprogram information block (DSIB) and update the
9553 frame pointer register ($15) for subroutines which have a frame. If the
9554 subroutine doesn't have a frame, simply increment $15. */
9557 unicosmk_gen_dsib (unsigned long *imaskP
)
9559 if (alpha_procedure_type
== PT_STACK
)
9561 const char *ssib_name
;
9564 /* Allocate 64 bytes for the DSIB. */
9566 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9568 emit_insn (gen_blockage ());
9570 /* Save the return address. */
9572 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9573 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9574 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9575 (*imaskP
) &= ~(1UL << REG_RA
);
9577 /* Save the old frame pointer. */
9579 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9580 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9581 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9582 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9584 emit_insn (gen_blockage ());
9586 /* Store the SSIB pointer. */
9588 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9589 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9590 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9592 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9593 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9594 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9596 /* Save the CIW index. */
9598 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9599 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9600 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9602 emit_insn (gen_blockage ());
9604 /* Set the new frame pointer. */
9606 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9607 stack_pointer_rtx
, GEN_INT (64))));
9612 /* Increment the frame pointer register to indicate that we do not
9615 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9616 hard_frame_pointer_rtx
, GEN_INT (1))));
9620 /* Output the static subroutine information block for the current
9624 unicosmk_output_ssib (FILE *file
, const char *fnname
)
9630 struct machine_function
*machine
= cfun
->machine
;
9633 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9634 unicosmk_ssib_name ());
9636 /* Some required stuff and the function name length. */
9638 len
= strlen (fnname
);
9639 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9642 ??? We don't do that yet. */
9644 fputs ("\t.quad\t0\n", file
);
9646 /* Function address. */
9648 fputs ("\t.quad\t", file
);
9649 assemble_name (file
, fnname
);
9652 fputs ("\t.quad\t0\n", file
);
9653 fputs ("\t.quad\t0\n", file
);
9656 ??? We do it the same way Cray CC does it but this could be
9659 for( i
= 0; i
< len
; i
++ )
9660 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9661 if( (len
% 8) == 0 )
9662 fputs ("\t.quad\t0\n", file
);
9664 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9666 /* All call information words used in the function. */
9668 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9671 #if HOST_BITS_PER_WIDE_INT == 32
9672 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
9673 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9675 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
9680 /* Add a call information word (CIW) to the list of the current function's
9681 CIWs and return its index.
9683 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9686 unicosmk_add_call_info_word (rtx x
)
9689 struct machine_function
*machine
= cfun
->machine
;
9691 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9692 if (machine
->first_ciw
== NULL_RTX
)
9693 machine
->first_ciw
= node
;
9695 XEXP (machine
->last_ciw
, 1) = node
;
9697 machine
->last_ciw
= node
;
9698 ++machine
->ciw_count
;
9700 return GEN_INT (machine
->ciw_count
9701 + strlen (current_function_name
)/8 + 5);
9704 static char unicosmk_section_buf
[100];
9707 unicosmk_text_section (void)
9709 static int count
= 0;
9710 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9712 return unicosmk_section_buf
;
9716 unicosmk_data_section (void)
9718 static int count
= 1;
9719 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9721 return unicosmk_section_buf
;
9724 /* The Cray assembler doesn't accept extern declarations for symbols which
9725 are defined in the same file. We have to keep track of all global
9726 symbols which are referenced and/or defined in a source file and output
9727 extern declarations for those which are referenced but not defined at
9730 /* List of identifiers for which an extern declaration might have to be
9732 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9734 struct unicosmk_extern_list
9736 struct unicosmk_extern_list
*next
;
9740 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9742 /* Output extern declarations which are required for every asm file. */
9745 unicosmk_output_default_externs (FILE *file
)
9747 static const char *const externs
[] =
9748 { "__T3E_MISMATCH" };
9753 n
= ARRAY_SIZE (externs
);
9755 for (i
= 0; i
< n
; i
++)
9756 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9759 /* Output extern declarations for global symbols which are have been
9760 referenced but not defined. */
9763 unicosmk_output_externs (FILE *file
)
9765 struct unicosmk_extern_list
*p
;
9766 const char *real_name
;
9770 len
= strlen (user_label_prefix
);
9771 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9773 /* We have to strip the encoding and possibly remove user_label_prefix
9774 from the identifier in order to handle -fleading-underscore and
9775 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9776 real_name
= default_strip_name_encoding (p
->name
);
9777 if (len
&& p
->name
[0] == '*'
9778 && !memcmp (real_name
, user_label_prefix
, len
))
9781 name_tree
= get_identifier (real_name
);
9782 if (! TREE_ASM_WRITTEN (name_tree
))
9784 TREE_ASM_WRITTEN (name_tree
) = 1;
9785 fputs ("\t.extern\t", file
);
9786 assemble_name (file
, p
->name
);
9792 /* Record an extern. */
9795 unicosmk_add_extern (const char *name
)
9797 struct unicosmk_extern_list
*p
;
9799 p
= (struct unicosmk_extern_list
*)
9800 xmalloc (sizeof (struct unicosmk_extern_list
));
9801 p
->next
= unicosmk_extern_head
;
9803 unicosmk_extern_head
= p
;
9806 /* The Cray assembler generates incorrect code if identifiers which
9807 conflict with register names are used as instruction operands. We have
9808 to replace such identifiers with DEX expressions. */
9810 /* Structure to collect identifiers which have been replaced by DEX
9812 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9814 struct unicosmk_dex
{
9815 struct unicosmk_dex
*next
;
9819 /* List of identifiers which have been replaced by DEX expressions. The DEX
9820 number is determined by the position in the list. */
9822 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9824 /* The number of elements in the DEX list. */
9826 static int unicosmk_dex_count
= 0;
9828 /* Check if NAME must be replaced by a DEX expression. */
9831 unicosmk_special_name (const char *name
)
9839 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9845 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9848 return (name
[2] == '\0'
9849 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9852 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9856 /* Return the DEX number if X must be replaced by a DEX expression and 0
9860 unicosmk_need_dex (rtx x
)
9862 struct unicosmk_dex
*dex
;
9866 if (GET_CODE (x
) != SYMBOL_REF
)
9870 if (! unicosmk_special_name (name
))
9873 i
= unicosmk_dex_count
;
9874 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9876 if (! strcmp (name
, dex
->name
))
9881 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
9883 dex
->next
= unicosmk_dex_list
;
9884 unicosmk_dex_list
= dex
;
9886 ++unicosmk_dex_count
;
9887 return unicosmk_dex_count
;
9890 /* Output the DEX definitions for this file. */
9893 unicosmk_output_dex (FILE *file
)
9895 struct unicosmk_dex
*dex
;
9898 if (unicosmk_dex_list
== NULL
)
9901 fprintf (file
, "\t.dexstart\n");
9903 i
= unicosmk_dex_count
;
9904 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9906 fprintf (file
, "\tDEX (%d) = ", i
);
9907 assemble_name (file
, dex
->name
);
9912 fprintf (file
, "\t.dexend\n");
9915 /* Output text that to appear at the beginning of an assembler file. */
9918 unicosmk_file_start (void)
9922 fputs ("\t.ident\t", asm_out_file
);
9923 unicosmk_output_module_name (asm_out_file
);
9924 fputs ("\n\n", asm_out_file
);
9926 /* The Unicos/Mk assembler uses different register names. Instead of trying
9927 to support them, we simply use micro definitions. */
9929 /* CAM has different register names: rN for the integer register N and fN
9930 for the floating-point register N. Instead of trying to use these in
9931 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9934 for (i
= 0; i
< 32; ++i
)
9935 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
9937 for (i
= 0; i
< 32; ++i
)
9938 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
9940 putc ('\n', asm_out_file
);
9942 /* The .align directive fill unused space with zeroes which does not work
9943 in code sections. We define the macro 'gcc@code@align' which uses nops
9944 instead. Note that it assumes that code sections always have the
9945 biggest possible alignment since . refers to the current offset from
9946 the beginning of the section. */
9948 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
9949 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
9950 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
9951 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
9952 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
9953 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
9954 fputs ("\t.endr\n", asm_out_file
);
9955 fputs ("\t.endif\n", asm_out_file
);
9956 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
9958 /* Output extern declarations which should always be visible. */
9959 unicosmk_output_default_externs (asm_out_file
);
9961 /* Open a dummy section. We always need to be inside a section for the
9962 section-switching code to work correctly.
9963 ??? This should be a module id or something like that. I still have to
9964 figure out what the rules for those are. */
9965 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
9968 /* Output text to appear at the end of an assembler file. This includes all
9969 pending extern declarations and DEX expressions. */
9972 unicosmk_file_end (void)
9974 fputs ("\t.endp\n\n", asm_out_file
);
9976 /* Output all pending externs. */
9978 unicosmk_output_externs (asm_out_file
);
9980 /* Output dex definitions used for functions whose names conflict with
9983 unicosmk_output_dex (asm_out_file
);
9985 fputs ("\t.end\t", asm_out_file
);
9986 unicosmk_output_module_name (asm_out_file
);
9987 putc ('\n', asm_out_file
);
9993 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
9997 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10001 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10002 const char * fnname ATTRIBUTE_UNUSED
)
10006 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10012 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10017 #endif /* TARGET_ABI_UNICOSMK */
10020 alpha_init_libfuncs (void)
10022 if (TARGET_ABI_UNICOSMK
)
10024 /* Prevent gcc from generating calls to __divsi3. */
10025 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10026 set_optab_libfunc (udiv_optab
, SImode
, 0);
10028 /* Use the functions provided by the system library
10029 for DImode integer division. */
10030 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10031 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10033 else if (TARGET_ABI_OPEN_VMS
)
10035 /* Use the VMS runtime library functions for division and
10037 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10038 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10039 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10040 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10041 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10042 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10043 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10044 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10049 /* Initialize the GCC target structure. */
10050 #if TARGET_ABI_OPEN_VMS
10051 # undef TARGET_ATTRIBUTE_TABLE
10052 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10053 # undef TARGET_SECTION_TYPE_FLAGS
10054 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10057 #undef TARGET_IN_SMALL_DATA_P
10058 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10060 #if TARGET_ABI_UNICOSMK
10061 # undef TARGET_INSERT_ATTRIBUTES
10062 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10063 # undef TARGET_SECTION_TYPE_FLAGS
10064 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10065 # undef TARGET_ASM_UNIQUE_SECTION
10066 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10067 # undef TARGET_ASM_GLOBALIZE_LABEL
10068 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10071 #undef TARGET_ASM_ALIGNED_HI_OP
10072 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10073 #undef TARGET_ASM_ALIGNED_DI_OP
10074 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10076 /* Default unaligned ops are provided for ELF systems. To get unaligned
10077 data for non-ELF systems, we have to turn off auto alignment. */
10078 #ifndef OBJECT_FORMAT_ELF
10079 #undef TARGET_ASM_UNALIGNED_HI_OP
10080 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10081 #undef TARGET_ASM_UNALIGNED_SI_OP
10082 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10083 #undef TARGET_ASM_UNALIGNED_DI_OP
10084 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10087 #ifdef OBJECT_FORMAT_ELF
10088 #undef TARGET_ASM_SELECT_RTX_SECTION
10089 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10092 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10093 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10095 #undef TARGET_INIT_LIBFUNCS
10096 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10098 #if TARGET_ABI_UNICOSMK
10099 #undef TARGET_ASM_FILE_START
10100 #define TARGET_ASM_FILE_START unicosmk_file_start
10101 #undef TARGET_ASM_FILE_END
10102 #define TARGET_ASM_FILE_END unicosmk_file_end
10104 #undef TARGET_ASM_FILE_START
10105 #define TARGET_ASM_FILE_START alpha_file_start
10106 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10107 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10110 #undef TARGET_SCHED_ADJUST_COST
10111 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10112 #undef TARGET_SCHED_ISSUE_RATE
10113 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10114 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10115 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10116 alpha_use_dfa_pipeline_interface
10117 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10118 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10119 alpha_multipass_dfa_lookahead
10121 #undef TARGET_HAVE_TLS
10122 #define TARGET_HAVE_TLS HAVE_AS_TLS
10124 #undef TARGET_INIT_BUILTINS
10125 #define TARGET_INIT_BUILTINS alpha_init_builtins
10126 #undef TARGET_EXPAND_BUILTIN
10127 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10129 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10130 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10131 #undef TARGET_CANNOT_COPY_INSN_P
10132 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10135 #undef TARGET_ASM_OUTPUT_MI_THUNK
10136 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10137 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10138 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10141 #undef TARGET_RTX_COSTS
10142 #define TARGET_RTX_COSTS alpha_rtx_costs
10143 #undef TARGET_ADDRESS_COST
10144 #define TARGET_ADDRESS_COST hook_int_rtx_0
10146 #undef TARGET_MACHINE_DEPENDENT_REORG
10147 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10149 struct gcc_target targetm
= TARGET_INITIALIZER
;
10152 #include "gt-alpha.h"