1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 /* Specify which cpu to schedule for. */
58 enum processor_type alpha_cpu
;
59 static const char * const alpha_cpu_name
[] =
64 /* Specify how accurate floating-point traps need to be. */
66 enum alpha_trap_precision alpha_tp
;
68 /* Specify the floating-point rounding mode. */
70 enum alpha_fp_rounding_mode alpha_fprm
;
72 /* Specify which things cause traps. */
74 enum alpha_fp_trap_mode alpha_fptm
;
76 /* Specify bit size of immediate TLS offsets. */
78 int alpha_tls_size
= 32;
80 /* Strings decoded into the above options. */
82 const char *alpha_cpu_string
; /* -mcpu= */
83 const char *alpha_tune_string
; /* -mtune= */
84 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
85 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
86 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
87 const char *alpha_mlat_string
; /* -mmemory-latency= */
88 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
90 /* Save information from a "cmpxx" operation until the branch or scc is
93 struct alpha_compare alpha_compare
;
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
98 static int inside_function
= FALSE
;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency
= 3;
104 /* Whether the function needs the GP. */
106 static int alpha_function_needs_gp
;
108 /* The alias set for prologue/epilogue register save/restore. */
110 static GTY(()) int alpha_sr_alias_set
;
112 /* The assembler name of the current function. */
114 static const char *alpha_fnname
;
116 /* The next explicit relocation sequence number. */
117 extern GTY(()) int alpha_next_sequence_number
;
118 int alpha_next_sequence_number
= 1;
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
122 extern GTY(()) int alpha_this_literal_sequence_number
;
123 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
124 int alpha_this_literal_sequence_number
;
125 int alpha_this_gpdisp_sequence_number
;
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
131 unsigned char fp_add
;
132 unsigned char fp_mult
;
133 unsigned char fp_div_sf
;
134 unsigned char fp_div_df
;
135 unsigned char int_mult_si
;
136 unsigned char int_mult_di
;
137 unsigned char int_shift
;
138 unsigned char int_cmov
;
141 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
144 COSTS_N_INSNS (6), /* fp_add */
145 COSTS_N_INSNS (6), /* fp_mult */
146 COSTS_N_INSNS (34), /* fp_div_sf */
147 COSTS_N_INSNS (63), /* fp_div_df */
148 COSTS_N_INSNS (23), /* int_mult_si */
149 COSTS_N_INSNS (23), /* int_mult_di */
150 COSTS_N_INSNS (2), /* int_shift */
151 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (15), /* fp_div_sf */
157 COSTS_N_INSNS (22), /* fp_div_df */
158 COSTS_N_INSNS (8), /* int_mult_si */
159 COSTS_N_INSNS (12), /* int_mult_di */
160 COSTS_N_INSNS (1) + 1, /* int_shift */
161 COSTS_N_INSNS (1), /* int_cmov */
164 COSTS_N_INSNS (4), /* fp_add */
165 COSTS_N_INSNS (4), /* fp_mult */
166 COSTS_N_INSNS (12), /* fp_div_sf */
167 COSTS_N_INSNS (15), /* fp_div_df */
168 COSTS_N_INSNS (7), /* int_mult_si */
169 COSTS_N_INSNS (7), /* int_mult_di */
170 COSTS_N_INSNS (1), /* int_shift */
171 COSTS_N_INSNS (2), /* int_cmov */
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
179 #define NUM_ARGS current_function_args_info
185 /* Declarations of static functions. */
186 static struct machine_function
*alpha_init_machine_status (void);
187 static rtx
alpha_emit_xfloating_compare (enum rtx_code
, rtx
, rtx
);
189 #if TARGET_ABI_OPEN_VMS
190 static void alpha_write_linkage (FILE *, const char *, tree
);
193 static void unicosmk_output_deferred_case_vectors (FILE *);
194 static void unicosmk_gen_dsib (unsigned long *);
195 static void unicosmk_output_ssib (FILE *, const char *);
196 static int unicosmk_need_dex (rtx
);
198 /* Parse target option strings. */
201 override_options (void)
204 static const struct cpu_table
{
205 const char *const name
;
206 const enum processor_type processor
;
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
211 { "ev4", PROCESSOR_EV4
, 0 },
212 { "ev45", PROCESSOR_EV4
, 0 },
213 { "21064", PROCESSOR_EV4
, 0 },
214 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
215 { "21164", PROCESSOR_EV5
, EV5_MASK
},
216 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
217 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
218 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
219 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
220 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
221 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
222 { "21264", PROCESSOR_EV6
, EV6_MASK
},
223 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
224 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
228 /* Unicos/Mk doesn't have shared libraries. */
229 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
231 warning ("-f%s ignored for Unicos/Mk (not supported)",
232 (flag_pic
> 1) ? "PIC" : "pic");
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
238 if (TARGET_ABI_UNICOSMK
)
239 alpha_fprm
= ALPHA_FPRM_DYN
;
241 alpha_fprm
= ALPHA_FPRM_NORM
;
243 alpha_tp
= ALPHA_TP_PROG
;
244 alpha_fptm
= ALPHA_FPTM_N
;
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
254 if (TARGET_ABI_UNICOSMK
)
255 warning ("-mieee not supported on Unicos/Mk");
258 alpha_tp
= ALPHA_TP_INSN
;
259 alpha_fptm
= ALPHA_FPTM_SU
;
263 if (TARGET_IEEE_WITH_INEXACT
)
265 if (TARGET_ABI_UNICOSMK
)
266 warning ("-mieee-with-inexact not supported on Unicos/Mk");
269 alpha_tp
= ALPHA_TP_INSN
;
270 alpha_fptm
= ALPHA_FPTM_SUI
;
276 if (! strcmp (alpha_tp_string
, "p"))
277 alpha_tp
= ALPHA_TP_PROG
;
278 else if (! strcmp (alpha_tp_string
, "f"))
279 alpha_tp
= ALPHA_TP_FUNC
;
280 else if (! strcmp (alpha_tp_string
, "i"))
281 alpha_tp
= ALPHA_TP_INSN
;
283 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
286 if (alpha_fprm_string
)
288 if (! strcmp (alpha_fprm_string
, "n"))
289 alpha_fprm
= ALPHA_FPRM_NORM
;
290 else if (! strcmp (alpha_fprm_string
, "m"))
291 alpha_fprm
= ALPHA_FPRM_MINF
;
292 else if (! strcmp (alpha_fprm_string
, "c"))
293 alpha_fprm
= ALPHA_FPRM_CHOP
;
294 else if (! strcmp (alpha_fprm_string
,"d"))
295 alpha_fprm
= ALPHA_FPRM_DYN
;
297 error ("bad value `%s' for -mfp-rounding-mode switch",
301 if (alpha_fptm_string
)
303 if (strcmp (alpha_fptm_string
, "n") == 0)
304 alpha_fptm
= ALPHA_FPTM_N
;
305 else if (strcmp (alpha_fptm_string
, "u") == 0)
306 alpha_fptm
= ALPHA_FPTM_U
;
307 else if (strcmp (alpha_fptm_string
, "su") == 0)
308 alpha_fptm
= ALPHA_FPTM_SU
;
309 else if (strcmp (alpha_fptm_string
, "sui") == 0)
310 alpha_fptm
= ALPHA_FPTM_SUI
;
312 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
315 if (alpha_tls_size_string
)
317 if (strcmp (alpha_tls_size_string
, "16") == 0)
319 else if (strcmp (alpha_tls_size_string
, "32") == 0)
321 else if (strcmp (alpha_tls_size_string
, "64") == 0)
324 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
328 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
329 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
331 if (alpha_cpu_string
)
333 for (i
= 0; cpu_table
[i
].name
; i
++)
334 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
336 alpha_cpu
= cpu_table
[i
].processor
;
337 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
338 | MASK_CPU_EV5
| MASK_CPU_EV6
);
339 target_flags
|= cpu_table
[i
].flags
;
342 if (! cpu_table
[i
].name
)
343 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
346 if (alpha_tune_string
)
348 for (i
= 0; cpu_table
[i
].name
; i
++)
349 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
351 alpha_cpu
= cpu_table
[i
].processor
;
354 if (! cpu_table
[i
].name
)
355 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
358 /* Do some sanity checks on the above options. */
360 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
362 warning ("trap mode not supported on Unicos/Mk");
363 alpha_fptm
= ALPHA_FPTM_N
;
366 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
367 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
369 warning ("fp software completion requires -mtrap-precision=i");
370 alpha_tp
= ALPHA_TP_INSN
;
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
378 alpha_tp
= ALPHA_TP_PROG
;
381 if (TARGET_FLOAT_VAX
)
383 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
385 warning ("rounding mode not supported for VAX floats");
386 alpha_fprm
= ALPHA_FPRM_NORM
;
388 if (alpha_fptm
== ALPHA_FPTM_SUI
)
390 warning ("trap mode not supported for VAX floats");
391 alpha_fptm
= ALPHA_FPTM_SU
;
393 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
394 warning ("128-bit long double not supported for VAX floats");
395 target_flags
&= ~MASK_LONG_DOUBLE_128
;
402 if (!alpha_mlat_string
)
403 alpha_mlat_string
= "L1";
405 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
406 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
408 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
409 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
410 && alpha_mlat_string
[2] == '\0')
412 static int const cache_latency
[][4] =
414 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
415 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
416 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
419 lat
= alpha_mlat_string
[1] - '0';
420 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
422 warning ("L%d cache latency unknown for %s",
423 lat
, alpha_cpu_name
[alpha_cpu
]);
427 lat
= cache_latency
[alpha_cpu
][lat
-1];
429 else if (! strcmp (alpha_mlat_string
, "main"))
431 /* Most current memories have about 370ns latency. This is
432 a reasonable guess for a fast cpu. */
437 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
441 alpha_memory_latency
= lat
;
444 /* Default the definition of "small data" to 8 bytes. */
448 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
450 target_flags
|= MASK_SMALL_DATA
;
451 else if (flag_pic
== 2)
452 target_flags
&= ~MASK_SMALL_DATA
;
454 /* Align labels and loops for optimal branching. */
455 /* ??? Kludge these by not doing anything if we don't optimize and also if
456 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
457 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
459 if (align_loops
<= 0)
461 if (align_jumps
<= 0)
464 if (align_functions
<= 0)
465 align_functions
= 16;
467 /* Acquire a unique set number for our register saves and restores. */
468 alpha_sr_alias_set
= new_alias_set ();
470 /* Register variables and functions with the garbage collector. */
472 /* Set up function hooks. */
473 init_machine_status
= alpha_init_machine_status
;
475 /* Tell the compiler when we're using VAX floating point. */
476 if (TARGET_FLOAT_VAX
)
478 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
479 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
480 REAL_MODE_FORMAT (TFmode
) = NULL
;
484 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
487 zap_mask (HOST_WIDE_INT value
)
491 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
493 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
499 /* Returns 1 if OP is either the constant zero or a register. If a
500 register, it must be in the proper mode unless MODE is VOIDmode. */
503 reg_or_0_operand (rtx op
, enum machine_mode mode
)
505 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
508 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
512 reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
514 return ((GET_CODE (op
) == CONST_INT
515 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
516 || register_operand (op
, mode
));
520 /* Return 1 if OP is an 8-bit constant or any register. */
523 reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
525 return ((GET_CODE (op
) == CONST_INT
526 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
527 || register_operand (op
, mode
));
530 /* Return 1 if OP is a constant or any register. */
533 reg_or_const_int_operand (rtx op
, enum machine_mode mode
)
535 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
538 /* Return 1 if OP is an 8-bit constant. */
541 cint8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
543 return ((GET_CODE (op
) == CONST_INT
544 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
547 /* Return 1 if the operand is a valid second operand to an add insn. */
550 add_operand (rtx op
, enum machine_mode mode
)
552 if (GET_CODE (op
) == CONST_INT
)
553 /* Constraints I, J, O and P are covered by K. */
554 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
555 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
557 return register_operand (op
, mode
);
560 /* Return 1 if the operand is a valid second operand to a sign-extending
564 sext_add_operand (rtx op
, enum machine_mode mode
)
566 if (GET_CODE (op
) == CONST_INT
)
567 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
568 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
570 return reg_not_elim_operand (op
, mode
);
573 /* Return 1 if OP is the constant 4 or 8. */
576 const48_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
578 return (GET_CODE (op
) == CONST_INT
579 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
582 /* Return 1 if OP is a valid first operand to an AND insn. */
585 and_operand (rtx op
, enum machine_mode mode
)
587 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
588 return (zap_mask (CONST_DOUBLE_LOW (op
))
589 && zap_mask (CONST_DOUBLE_HIGH (op
)));
591 if (GET_CODE (op
) == CONST_INT
)
592 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
593 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
594 || zap_mask (INTVAL (op
)));
596 return register_operand (op
, mode
);
599 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
602 or_operand (rtx op
, enum machine_mode mode
)
604 if (GET_CODE (op
) == CONST_INT
)
605 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
606 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
608 return register_operand (op
, mode
);
611 /* Return 1 if OP is a constant that is the width, in bits, of an integral
612 mode smaller than DImode. */
615 mode_width_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
617 return (GET_CODE (op
) == CONST_INT
618 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
619 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
622 /* Return 1 if OP is a constant that is the width of an integral machine mode
623 smaller than an integer. */
626 mode_mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
628 if (GET_CODE (op
) == CONST_INT
)
630 HOST_WIDE_INT value
= INTVAL (op
);
636 if (value
== 0xffffffff)
641 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
643 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
650 /* Return 1 if OP is a multiple of 8 less than 64. */
653 mul8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
655 return (GET_CODE (op
) == CONST_INT
656 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
657 && (INTVAL (op
) & 7) == 0);
660 /* Return 1 if OP is the zero constant for MODE. */
663 const0_operand (rtx op
, enum machine_mode mode
)
665 return op
== CONST0_RTX (mode
);
668 /* Return 1 if OP is a hard floating-point register. */
671 hard_fp_register_operand (rtx op
, enum machine_mode mode
)
673 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
676 if (GET_CODE (op
) == SUBREG
)
677 op
= SUBREG_REG (op
);
678 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
681 /* Return 1 if OP is a hard general register. */
684 hard_int_register_operand (rtx op
, enum machine_mode mode
)
686 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
689 if (GET_CODE (op
) == SUBREG
)
690 op
= SUBREG_REG (op
);
691 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
694 /* Return 1 if OP is a register or a constant integer. */
698 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
700 return (GET_CODE (op
) == CONST_INT
701 || register_operand (op
, mode
));
704 /* Return 1 if OP is something that can be reloaded into a register;
705 if it is a MEM, it need not be valid. */
708 some_operand (rtx op
, enum machine_mode mode
)
710 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
713 switch (GET_CODE (op
))
727 return some_operand (SUBREG_REG (op
), VOIDmode
);
736 /* Likewise, but don't accept constants. */
739 some_ni_operand (rtx op
, enum machine_mode mode
)
741 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
744 if (GET_CODE (op
) == SUBREG
)
745 op
= SUBREG_REG (op
);
747 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
750 /* Return 1 if OP is a valid operand for the source of a move insn. */
753 input_operand (rtx op
, enum machine_mode mode
)
755 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
758 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
761 switch (GET_CODE (op
))
766 if (TARGET_EXPLICIT_RELOCS
)
768 /* We don't split symbolic operands into something unintelligable
769 until after reload, but we do not wish non-small, non-global
770 symbolic operands to be reconstructed from their high/lo_sum
772 return (small_symbolic_operand (op
, mode
)
773 || global_symbolic_operand (op
, mode
)
774 || gotdtp_symbolic_operand (op
, mode
)
775 || gottp_symbolic_operand (op
, mode
));
778 /* This handles both the Windows/NT and OSF cases. */
779 return mode
== ptr_mode
|| mode
== DImode
;
782 return (TARGET_EXPLICIT_RELOCS
783 && local_symbolic_operand (XEXP (op
, 0), mode
));
790 if (register_operand (op
, mode
))
792 /* ... fall through ... */
794 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
795 && general_operand (op
, mode
));
799 return op
== CONST0_RTX (mode
);
802 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
814 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
815 file, and in the same section as the current function. */
818 samegp_function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
820 if (GET_CODE (op
) != SYMBOL_REF
)
823 /* Easy test for recursion. */
824 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
827 /* Functions that are not local can be overridden, and thus may
828 not share the same gp. */
829 if (! SYMBOL_REF_LOCAL_P (op
))
832 /* If -msmall-data is in effect, assume that there is only one GP
833 for the module, and so any local symbol has this property. We
834 need explicit relocations to be able to enforce this for symbols
835 not defined in this unit of translation, however. */
836 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
839 /* Functions that are not external are defined in this UoT,
840 and thus must share the same gp. */
841 return ! SYMBOL_REF_EXTERNAL_P (op
);
844 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
847 direct_call_operand (rtx op
, enum machine_mode mode
)
849 tree op_decl
, cfun_sec
, op_sec
;
851 /* Must share the same GP. */
852 if (!samegp_function_operand (op
, mode
))
855 /* If profiling is implemented via linker tricks, we can't jump
856 to the nogp alternate entry point. Note that current_function_profile
857 would not be correct, since that doesn't indicate if the target
858 function uses profiling. */
859 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
860 but is approximately correct for the OSF ABIs. Don't know
861 what to do for VMS, NT, or UMK. */
862 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
865 /* Must be a function. In some cases folks create thunks in static
866 data structures and then make calls to them. If we allow the
867 direct call, we'll get an error from the linker about !samegp reloc
868 against a symbol without a .prologue directive. */
869 if (!SYMBOL_REF_FUNCTION_P (op
))
872 /* Must be "near" so that the branch is assumed to reach. With
873 -msmall-text, this is assumed true of all local symbols. Since
874 we've already checked samegp, locality is already assured. */
875 if (TARGET_SMALL_TEXT
)
878 /* Otherwise, a decl is "near" if it is defined in the same section. */
879 if (flag_function_sections
)
882 op_decl
= SYMBOL_REF_DECL (op
);
883 if (DECL_ONE_ONLY (current_function_decl
)
884 || (op_decl
&& DECL_ONE_ONLY (op_decl
)))
887 cfun_sec
= DECL_SECTION_NAME (current_function_decl
);
888 op_sec
= op_decl
? DECL_SECTION_NAME (op_decl
) : NULL
;
889 return ((!cfun_sec
&& !op_sec
)
890 || (cfun_sec
&& op_sec
891 && strcmp (TREE_STRING_POINTER (cfun_sec
),
892 TREE_STRING_POINTER (op_sec
)) == 0));
895 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
896 a (non-tls) variable known to be defined in this file. */
899 local_symbolic_operand (rtx op
, enum machine_mode mode
)
901 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
904 if (GET_CODE (op
) == LABEL_REF
)
907 if (GET_CODE (op
) == CONST
908 && GET_CODE (XEXP (op
, 0)) == PLUS
909 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
910 op
= XEXP (XEXP (op
, 0), 0);
912 if (GET_CODE (op
) != SYMBOL_REF
)
915 return SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
918 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
919 known to be defined in this file in the small data area. */
922 small_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
924 if (! TARGET_SMALL_DATA
)
927 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
930 if (GET_CODE (op
) == CONST
931 && GET_CODE (XEXP (op
, 0)) == PLUS
932 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
933 op
= XEXP (XEXP (op
, 0), 0);
935 if (GET_CODE (op
) != SYMBOL_REF
)
938 /* ??? There's no encode_section_info equivalent for the rtl
939 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
940 if (CONSTANT_POOL_ADDRESS_P (op
))
941 return GET_MODE_SIZE (get_pool_mode (op
)) <= g_switch_value
;
943 return (SYMBOL_REF_LOCAL_P (op
)
944 && SYMBOL_REF_SMALL_P (op
)
945 && SYMBOL_REF_TLS_MODEL (op
) == 0);
948 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
949 not known (or known not) to be defined in this file. */
952 global_symbolic_operand (rtx op
, enum machine_mode mode
)
954 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
957 if (GET_CODE (op
) == CONST
958 && GET_CODE (XEXP (op
, 0)) == PLUS
959 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
960 op
= XEXP (XEXP (op
, 0), 0);
962 if (GET_CODE (op
) != SYMBOL_REF
)
965 return !SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
968 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
971 call_operand (rtx op
, enum machine_mode mode
)
976 if (GET_CODE (op
) == REG
)
980 /* Disallow virtual registers to cope with pathological test cases
981 such as compile/930117-1.c in which the virtual reg decomposes
982 to the frame pointer. Which is a hard reg that is not $27. */
983 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
988 if (TARGET_ABI_UNICOSMK
)
990 if (GET_CODE (op
) == SYMBOL_REF
)
996 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
997 possibly with an offset. */
1000 symbolic_operand (rtx op
, enum machine_mode mode
)
1002 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1004 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1006 if (GET_CODE (op
) == CONST
1007 && GET_CODE (XEXP (op
,0)) == PLUS
1008 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1009 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1014 /* Return true if OP is valid for a particular TLS relocation. */
1017 tls_symbolic_operand_1 (rtx op
, enum machine_mode mode
, int size
, int unspec
)
1019 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1022 if (GET_CODE (op
) != CONST
)
1026 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1028 op
= XVECEXP (op
, 0, 0);
1030 if (GET_CODE (op
) != SYMBOL_REF
)
1033 if (SYMBOL_REF_LOCAL_P (op
))
1035 if (alpha_tls_size
> size
)
1044 switch (SYMBOL_REF_TLS_MODEL (op
))
1046 case TLS_MODEL_LOCAL_DYNAMIC
:
1047 return unspec
== UNSPEC_DTPREL
;
1048 case TLS_MODEL_INITIAL_EXEC
:
1049 return unspec
== UNSPEC_TPREL
&& size
== 64;
1050 case TLS_MODEL_LOCAL_EXEC
:
1051 return unspec
== UNSPEC_TPREL
;
1057 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1060 dtp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1062 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1065 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1068 dtp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1070 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1073 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1076 gotdtp_symbolic_operand (rtx op
, enum machine_mode mode
)
1078 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1081 /* Return true if OP is valid for 16-bit TP relative relocations. */
1084 tp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1086 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1089 /* Return true if OP is valid for 32-bit TP relative relocations. */
1092 tp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1094 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1097 /* Return true if OP is valid for 64-bit TP relative relocations. */
1100 gottp_symbolic_operand (rtx op
, enum machine_mode mode
)
1102 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1105 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1106 comparisons are valid in which insn. */
1109 alpha_comparison_operator (rtx op
, enum machine_mode mode
)
1111 enum rtx_code code
= GET_CODE (op
);
1113 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1116 return (code
== EQ
|| code
== LE
|| code
== LT
1117 || code
== LEU
|| code
== LTU
);
1120 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1121 Here we know which comparisons are valid in which insn. */
1124 alpha_zero_comparison_operator (rtx op
, enum machine_mode mode
)
1126 enum rtx_code code
= GET_CODE (op
);
1128 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1131 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1132 || code
== LEU
|| code
== LTU
);
1135 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1138 alpha_swapped_comparison_operator (rtx op
, enum machine_mode mode
)
1142 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1143 || !COMPARISON_P (op
))
1146 code
= swap_condition (GET_CODE (op
));
1147 return (code
== EQ
|| code
== LE
|| code
== LT
1148 || code
== LEU
|| code
== LTU
);
1151 /* Return 1 if OP is a signed comparison operation. */
1154 signed_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1156 enum rtx_code code
= GET_CODE (op
);
1158 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1161 return (code
== EQ
|| code
== NE
1162 || code
== LE
|| code
== LT
1163 || code
== GE
|| code
== GT
);
1166 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1167 Here we know which comparisons are valid in which insn. */
1170 alpha_fp_comparison_operator (rtx op
, enum machine_mode mode
)
1172 enum rtx_code code
= GET_CODE (op
);
1174 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1177 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1180 /* Return 1 if this is a divide or modulus operator. */
1183 divmod_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1185 enum rtx_code code
= GET_CODE (op
);
1187 return (code
== DIV
|| code
== MOD
|| code
== UDIV
|| code
== UMOD
);
1190 /* Return 1 if this is a float->int conversion operator. */
1193 fix_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1195 enum rtx_code code
= GET_CODE (op
);
1197 return (code
== FIX
|| code
== UNSIGNED_FIX
);
1200 /* Return 1 if this memory address is a known aligned register plus
1201 a constant. It must be a valid address. This means that we can do
1202 this as an aligned reference plus some offset.
1204 Take into account what reload will do. */
1207 aligned_memory_operand (rtx op
, enum machine_mode mode
)
1211 if (reload_in_progress
)
1214 if (GET_CODE (tmp
) == SUBREG
)
1215 tmp
= SUBREG_REG (tmp
);
1216 if (GET_CODE (tmp
) == REG
1217 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1219 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1225 if (GET_CODE (op
) != MEM
)
1227 if (MEM_ALIGN (op
) >= 32)
1231 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1232 sorts of constructs. Dig for the real base register. */
1233 if (reload_in_progress
1234 && GET_CODE (op
) == PLUS
1235 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1236 base
= XEXP (XEXP (op
, 0), 0);
1239 if (! memory_address_p (mode
, op
))
1241 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1244 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1247 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1250 unaligned_memory_operand (rtx op
, enum machine_mode mode
)
1254 if (reload_in_progress
)
1257 if (GET_CODE (tmp
) == SUBREG
)
1258 tmp
= SUBREG_REG (tmp
);
1259 if (GET_CODE (tmp
) == REG
1260 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1262 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1268 if (GET_CODE (op
) != MEM
)
1270 if (MEM_ALIGN (op
) >= 32)
1274 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1275 sorts of constructs. Dig for the real base register. */
1276 if (reload_in_progress
1277 && GET_CODE (op
) == PLUS
1278 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1279 base
= XEXP (XEXP (op
, 0), 0);
1282 if (! memory_address_p (mode
, op
))
1284 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1287 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1290 /* Return 1 if OP is either a register or an unaligned memory location. */
1293 reg_or_unaligned_mem_operand (rtx op
, enum machine_mode mode
)
1295 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1298 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1301 any_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1303 return (GET_CODE (op
) == MEM
1304 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1305 || (reload_in_progress
&& GET_CODE (op
) == REG
1306 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1307 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1308 && GET_CODE (SUBREG_REG (op
)) == REG
1309 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1312 /* Returns 1 if OP is not an eliminable register.
1314 This exists to cure a pathological abort in the s8addq (et al) patterns,
1316 long foo () { long t; bar(); return (long) &t * 26107; }
1318 which run afoul of a hack in reload to cure a (presumably) similar
1319 problem with lea-type instructions on other targets. But there is
1320 one of us and many of them, so work around the problem by selectively
1321 preventing combine from making the optimization. */
1324 reg_not_elim_operand (rtx op
, enum machine_mode mode
)
1327 if (GET_CODE (op
) == SUBREG
)
1328 inner
= SUBREG_REG (op
);
1329 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1332 return register_operand (op
, mode
);
1335 /* Return 1 is OP is a memory location that is not a reference (using
1336 an AND) to an unaligned location. Take into account what reload
1340 normal_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1342 if (reload_in_progress
)
1345 if (GET_CODE (tmp
) == SUBREG
)
1346 tmp
= SUBREG_REG (tmp
);
1347 if (GET_CODE (tmp
) == REG
1348 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1350 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1352 /* This may not have been assigned an equivalent address if it will
1353 be eliminated. In that case, it doesn't matter what we do. */
1359 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1362 /* Accept a register, but not a subreg of any kind. This allows us to
1363 avoid pathological cases in reload wrt data movement common in
1364 int->fp conversion. */
1367 reg_no_subreg_operand (rtx op
, enum machine_mode mode
)
1369 if (GET_CODE (op
) != REG
)
1371 return register_operand (op
, mode
);
1374 /* Recognize an addition operation that includes a constant. Used to
1375 convince reload to canonize (plus (plus reg c1) c2) during register
1379 addition_operation (rtx op
, enum machine_mode mode
)
1381 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1383 if (GET_CODE (op
) == PLUS
1384 && register_operand (XEXP (op
, 0), mode
)
1385 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1386 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1391 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1392 the range defined for C in [I-P]. */
1395 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
1400 /* An unsigned 8 bit constant. */
1401 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1403 /* The constant zero. */
1406 /* A signed 16 bit constant. */
1407 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1409 /* A shifted signed 16 bit constant appropriate for LDAH. */
1410 return ((value
& 0xffff) == 0
1411 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1413 /* A constant that can be AND'ed with using a ZAP insn. */
1414 return zap_mask (value
);
1416 /* A complemented unsigned 8 bit constant. */
1417 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1419 /* A negated unsigned 8 bit constant. */
1420 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1422 /* The constant 1, 2 or 3. */
1423 return value
== 1 || value
== 2 || value
== 3;
1430 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1431 matches for C in [GH]. */
1434 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
1439 /* The floating point zero constant. */
1440 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1441 && value
== CONST0_RTX (GET_MODE (value
)));
1444 /* A valid operand of a ZAP insn. */
1445 return (GET_MODE (value
) == VOIDmode
1446 && zap_mask (CONST_DOUBLE_LOW (value
))
1447 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1454 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1458 alpha_extra_constraint (rtx value
, int c
)
1463 return normal_memory_operand (value
, VOIDmode
);
1465 return direct_call_operand (value
, Pmode
);
1467 return (GET_CODE (value
) == CONST_INT
1468 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1470 return GET_CODE (value
) == HIGH
;
1472 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1474 return (GET_CODE (value
) == CONST_VECTOR
1475 && value
== CONST0_RTX (GET_MODE (value
)));
1481 /* Return 1 if this function can directly return via $26. */
1484 direct_return (void)
1486 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1488 && alpha_sa_size () == 0
1489 && get_frame_size () == 0
1490 && current_function_outgoing_args_size
== 0
1491 && current_function_pretend_args_size
== 0);
1494 /* Return the ADDR_VEC associated with a tablejump insn. */
1497 alpha_tablejump_addr_vec (rtx insn
)
1501 tmp
= JUMP_LABEL (insn
);
1504 tmp
= NEXT_INSN (tmp
);
1507 if (GET_CODE (tmp
) == JUMP_INSN
1508 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1509 return PATTERN (tmp
);
1513 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1516 alpha_tablejump_best_label (rtx insn
)
1518 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1519 rtx best_label
= NULL_RTX
;
1521 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1522 there for edge frequency counts from profile data. */
1526 int n_labels
= XVECLEN (jump_table
, 1);
1527 int best_count
= -1;
1530 for (i
= 0; i
< n_labels
; i
++)
1534 for (j
= i
+ 1; j
< n_labels
; j
++)
1535 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1536 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1539 if (count
> best_count
)
1540 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1544 return best_label
? best_label
: const0_rtx
;
1547 /* Return the TLS model to use for SYMBOL. */
1549 static enum tls_model
1550 tls_symbolic_operand_type (rtx symbol
)
1552 enum tls_model model
;
1554 if (GET_CODE (symbol
) != SYMBOL_REF
)
1556 model
= SYMBOL_REF_TLS_MODEL (symbol
);
1558 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1559 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
1560 model
= TLS_MODEL_INITIAL_EXEC
;
1565 /* Return true if the function DECL will share the same GP as any
1566 function in the current unit of translation. */
1569 decl_has_samegp (tree decl
)
1571 /* Functions that are not local can be overridden, and thus may
1572 not share the same gp. */
1573 if (!(*targetm
.binds_local_p
) (decl
))
1576 /* If -msmall-data is in effect, assume that there is only one GP
1577 for the module, and so any local symbol has this property. We
1578 need explicit relocations to be able to enforce this for symbols
1579 not defined in this unit of translation, however. */
1580 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1583 /* Functions that are not external are defined in this UoT. */
1584 /* ??? Irritatingly, static functions not yet emitted are still
1585 marked "external". Apply this to non-static functions only. */
1586 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1589 /* Return true if EXP should be placed in the small data section. */
1592 alpha_in_small_data_p (tree exp
)
1594 /* We want to merge strings, so we never consider them small data. */
1595 if (TREE_CODE (exp
) == STRING_CST
)
1598 /* Functions are never in the small data area. Duh. */
1599 if (TREE_CODE (exp
) == FUNCTION_DECL
)
1602 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1604 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1605 if (strcmp (section
, ".sdata") == 0
1606 || strcmp (section
, ".sbss") == 0)
1611 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1613 /* If this is an incomplete type with size 0, then we can't put it
1614 in sdata because it might be too big when completed. */
1615 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
1622 #if TARGET_ABI_OPEN_VMS
1624 alpha_linkage_symbol_p (const char *symname
)
1626 int symlen
= strlen (symname
);
1629 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1634 #define LINKAGE_SYMBOL_REF_P(X) \
1635 ((GET_CODE (X) == SYMBOL_REF \
1636 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1637 || (GET_CODE (X) == CONST \
1638 && GET_CODE (XEXP (X, 0)) == PLUS \
1639 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1640 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1643 /* legitimate_address_p recognizes an RTL expression that is a valid
1644 memory address for an instruction. The MODE argument is the
1645 machine mode for the MEM expression that wants to use this address.
1647 For Alpha, we have either a constant address or the sum of a
1648 register and a constant address, or just a register. For DImode,
1649 any of those forms can be surrounded with an AND that clear the
1650 low-order three bits; this is an "unaligned" access. */
1653 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1655 /* If this is an ldq_u type address, discard the outer AND. */
1657 && GET_CODE (x
) == AND
1658 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1659 && INTVAL (XEXP (x
, 1)) == -8)
1662 /* Discard non-paradoxical subregs. */
1663 if (GET_CODE (x
) == SUBREG
1664 && (GET_MODE_SIZE (GET_MODE (x
))
1665 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1668 /* Unadorned general registers are valid. */
1671 ? STRICT_REG_OK_FOR_BASE_P (x
)
1672 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1675 /* Constant addresses (i.e. +/- 32k) are valid. */
1676 if (CONSTANT_ADDRESS_P (x
))
1679 #if TARGET_ABI_OPEN_VMS
1680 if (LINKAGE_SYMBOL_REF_P (x
))
1684 /* Register plus a small constant offset is valid. */
1685 if (GET_CODE (x
) == PLUS
)
1687 rtx ofs
= XEXP (x
, 1);
1690 /* Discard non-paradoxical subregs. */
1691 if (GET_CODE (x
) == SUBREG
1692 && (GET_MODE_SIZE (GET_MODE (x
))
1693 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1699 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1700 && GET_CODE (ofs
) == CONST_INT
)
1703 ? STRICT_REG_OK_FOR_BASE_P (x
)
1704 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1705 && CONSTANT_ADDRESS_P (ofs
))
1708 else if (GET_CODE (x
) == ADDRESSOF
1709 && GET_CODE (ofs
) == CONST_INT
)
1713 /* If we're managing explicit relocations, LO_SUM is valid, as
1714 are small data symbols. */
1715 else if (TARGET_EXPLICIT_RELOCS
)
1717 if (small_symbolic_operand (x
, Pmode
))
1720 if (GET_CODE (x
) == LO_SUM
)
1722 rtx ofs
= XEXP (x
, 1);
1725 /* Discard non-paradoxical subregs. */
1726 if (GET_CODE (x
) == SUBREG
1727 && (GET_MODE_SIZE (GET_MODE (x
))
1728 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1731 /* Must have a valid base register. */
1734 ? STRICT_REG_OK_FOR_BASE_P (x
)
1735 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1738 /* The symbol must be local. */
1739 if (local_symbolic_operand (ofs
, Pmode
)
1740 || dtp32_symbolic_operand (ofs
, Pmode
)
1741 || tp32_symbolic_operand (ofs
, Pmode
))
1749 /* Build the SYMBOL_REF for __tls_get_addr. */
1751 static GTY(()) rtx tls_get_addr_libfunc
;
1754 get_tls_get_addr (void)
1756 if (!tls_get_addr_libfunc
)
1757 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
1758 return tls_get_addr_libfunc
;
1761 /* Try machine-dependent ways of modifying an illegitimate address
1762 to be legitimate. If we find one, return the new, valid address. */
1765 alpha_legitimize_address (rtx x
, rtx scratch
,
1766 enum machine_mode mode ATTRIBUTE_UNUSED
)
1768 HOST_WIDE_INT addend
;
1770 /* If the address is (plus reg const_int) and the CONST_INT is not a
1771 valid offset, compute the high part of the constant and add it to
1772 the register. Then our address is (plus temp low-part-const). */
1773 if (GET_CODE (x
) == PLUS
1774 && GET_CODE (XEXP (x
, 0)) == REG
1775 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1776 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1778 addend
= INTVAL (XEXP (x
, 1));
1783 /* If the address is (const (plus FOO const_int)), find the low-order
1784 part of the CONST_INT. Then load FOO plus any high-order part of the
1785 CONST_INT into a register. Our address is (plus reg low-part-const).
1786 This is done to reduce the number of GOT entries. */
1788 && GET_CODE (x
) == CONST
1789 && GET_CODE (XEXP (x
, 0)) == PLUS
1790 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1792 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1793 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1797 /* If we have a (plus reg const), emit the load as in (2), then add
1798 the two registers, and finally generate (plus reg low-part-const) as
1801 && GET_CODE (x
) == PLUS
1802 && GET_CODE (XEXP (x
, 0)) == REG
1803 && GET_CODE (XEXP (x
, 1)) == CONST
1804 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1805 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1807 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1808 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1809 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1810 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1814 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1815 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1817 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1819 switch (tls_symbolic_operand_type (x
))
1821 case TLS_MODEL_GLOBAL_DYNAMIC
:
1824 r0
= gen_rtx_REG (Pmode
, 0);
1825 r16
= gen_rtx_REG (Pmode
, 16);
1826 tga
= get_tls_get_addr ();
1827 dest
= gen_reg_rtx (Pmode
);
1828 seq
= GEN_INT (alpha_next_sequence_number
++);
1830 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1831 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1832 insn
= emit_call_insn (insn
);
1833 CONST_OR_PURE_CALL_P (insn
) = 1;
1834 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1836 insn
= get_insns ();
1839 emit_libcall_block (insn
, dest
, r0
, x
);
1842 case TLS_MODEL_LOCAL_DYNAMIC
:
1845 r0
= gen_rtx_REG (Pmode
, 0);
1846 r16
= gen_rtx_REG (Pmode
, 16);
1847 tga
= get_tls_get_addr ();
1848 scratch
= gen_reg_rtx (Pmode
);
1849 seq
= GEN_INT (alpha_next_sequence_number
++);
1851 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1852 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1853 insn
= emit_call_insn (insn
);
1854 CONST_OR_PURE_CALL_P (insn
) = 1;
1855 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1857 insn
= get_insns ();
1860 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1861 UNSPEC_TLSLDM_CALL
);
1862 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1864 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1865 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1867 if (alpha_tls_size
== 64)
1869 dest
= gen_reg_rtx (Pmode
);
1870 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1871 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1874 if (alpha_tls_size
== 32)
1876 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1877 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1878 scratch
= gen_reg_rtx (Pmode
);
1879 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1881 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1883 case TLS_MODEL_INITIAL_EXEC
:
1884 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1885 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1886 tp
= gen_reg_rtx (Pmode
);
1887 scratch
= gen_reg_rtx (Pmode
);
1888 dest
= gen_reg_rtx (Pmode
);
1890 emit_insn (gen_load_tp (tp
));
1891 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1892 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1895 case TLS_MODEL_LOCAL_EXEC
:
1896 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1897 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1898 tp
= gen_reg_rtx (Pmode
);
1900 emit_insn (gen_load_tp (tp
));
1901 if (alpha_tls_size
== 32)
1903 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1904 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1905 tp
= gen_reg_rtx (Pmode
);
1906 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1908 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1911 if (local_symbolic_operand (x
, Pmode
))
1913 if (small_symbolic_operand (x
, Pmode
))
1917 if (!no_new_pseudos
)
1918 scratch
= gen_reg_rtx (Pmode
);
1919 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1920 gen_rtx_HIGH (Pmode
, x
)));
1921 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1930 HOST_WIDE_INT low
, high
;
1932 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1934 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1938 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1939 (no_new_pseudos
? scratch
: NULL_RTX
),
1940 1, OPTAB_LIB_WIDEN
);
1942 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1943 (no_new_pseudos
? scratch
: NULL_RTX
),
1944 1, OPTAB_LIB_WIDEN
);
1946 return plus_constant (x
, low
);
1950 /* We do not allow indirect calls to be optimized into sibling calls, nor
1951 can we allow a call to a function with a different GP to be optimized
1955 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1957 /* Can't do indirect tail calls, since we don't know if the target
1958 uses the same GP. */
1962 /* Otherwise, we can make a tail call if the target function shares
1964 return decl_has_samegp (decl
);
1967 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1968 small symbolic operand until after reload. At which point we need
1969 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1970 so that sched2 has the proper dependency information. */
1973 some_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1977 /* Don't re-split. */
1978 if (GET_CODE (x
) == LO_SUM
)
1981 return small_symbolic_operand (x
, Pmode
) != 0;
1985 some_small_symbolic_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1987 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
1991 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1995 /* Don't re-split. */
1996 if (GET_CODE (x
) == LO_SUM
)
1999 if (small_symbolic_operand (x
, Pmode
))
2001 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2010 split_small_symbolic_operand (rtx x
)
2013 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2017 /* Indicate that INSN cannot be duplicated. This is true for any insn
2018 that we've marked with gpdisp relocs, since those have to stay in
2019 1-1 correspondence with one another.
2021 Technically we could copy them if we could set up a mapping from one
2022 sequence number to another, across the set of insns to be duplicated.
2023 This seems overly complicated and error-prone since interblock motion
2024 from sched-ebb could move one of the pair of insns to a different block.
2026 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2027 then they'll be in a different block from their ldgp. Which could lead
2028 the bb reorder code to think that it would be ok to copy just the block
2029 containing the call and branch to the block containing the ldgp. */
2032 alpha_cannot_copy_insn_p (rtx insn
)
2034 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2036 if (recog_memoized (insn
) >= 0)
2037 return get_attr_cannot_copy (insn
);
2043 /* Try a machine-dependent way of reloading an illegitimate address
2044 operand. If we find one, push the reload and return the new rtx. */
2047 alpha_legitimize_reload_address (rtx x
,
2048 enum machine_mode mode ATTRIBUTE_UNUSED
,
2049 int opnum
, int type
,
2050 int ind_levels ATTRIBUTE_UNUSED
)
2052 /* We must recognize output that we have already generated ourselves. */
2053 if (GET_CODE (x
) == PLUS
2054 && GET_CODE (XEXP (x
, 0)) == PLUS
2055 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2056 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2057 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2059 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2060 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2065 /* We wish to handle large displacements off a base register by
2066 splitting the addend across an ldah and the mem insn. This
2067 cuts number of extra insns needed from 3 to 1. */
2068 if (GET_CODE (x
) == PLUS
2069 && GET_CODE (XEXP (x
, 0)) == REG
2070 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2071 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2072 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2074 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2075 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2077 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2079 /* Check for 32-bit overflow. */
2080 if (high
+ low
!= val
)
2083 /* Reload the high part into a base reg; leave the low part
2084 in the mem directly. */
2085 x
= gen_rtx_PLUS (GET_MODE (x
),
2086 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2090 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2091 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2099 /* Compute a (partial) cost for rtx X. Return true if the complete
2100 cost has been computed, and false if subexpressions should be
2101 scanned. In either case, *TOTAL contains the cost result. */
2104 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2106 enum machine_mode mode
= GET_MODE (x
);
2107 bool float_mode_p
= FLOAT_MODE_P (mode
);
2111 /* If this is an 8-bit constant, return zero since it can be used
2112 nearly anywhere with no cost. If it is a valid operand for an
2113 ADD or AND, likewise return 0 if we know it will be used in that
2114 context. Otherwise, return 2 since it might be used there later.
2115 All other constants take at least two insns. */
2117 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2125 if (x
== CONST0_RTX (mode
))
2127 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2128 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2130 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2133 *total
= COSTS_N_INSNS (2);
2139 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2140 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2141 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2142 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2143 else if (tls_symbolic_operand_type (x
))
2144 /* Estimate of cost for call_pal rduniq. */
2145 *total
= COSTS_N_INSNS (15);
2147 /* Otherwise we do a load from the GOT. */
2148 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2154 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2155 else if (GET_CODE (XEXP (x
, 0)) == MULT
2156 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2158 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2159 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2166 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2167 else if (mode
== DImode
)
2168 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2170 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2174 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2175 && INTVAL (XEXP (x
, 1)) <= 3)
2177 *total
= COSTS_N_INSNS (1);
2184 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2189 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2191 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2199 *total
= COSTS_N_INSNS (70); /* ??? */
2200 else if (mode
== SFmode
)
2201 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2203 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2207 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2213 *total
= COSTS_N_INSNS (1);
2221 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2227 case UNSIGNED_FLOAT
:
2231 case FLOAT_TRUNCATE
:
2232 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2240 /* REF is an alignable memory location. Place an aligned SImode
2241 reference into *PALIGNED_MEM and the number of bits to shift into
2242 *PBITNUM. SCRATCH is a free register for use in reloading out
2243 of range stack slots. */
2246 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
2249 HOST_WIDE_INT offset
= 0;
2251 if (GET_CODE (ref
) != MEM
)
2254 if (reload_in_progress
2255 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2257 base
= find_replacement (&XEXP (ref
, 0));
2259 if (! memory_address_p (GET_MODE (ref
), base
))
2264 base
= XEXP (ref
, 0);
2267 if (GET_CODE (base
) == PLUS
)
2268 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2271 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2273 if (WORDS_BIG_ENDIAN
)
2274 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2275 + (offset
& 3) * 8));
2277 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2280 /* Similar, but just get the address. Handle the two reload cases.
2281 Add EXTRA_OFFSET to the address we return. */
2284 get_unaligned_address (rtx ref
, int extra_offset
)
2287 HOST_WIDE_INT offset
= 0;
2289 if (GET_CODE (ref
) != MEM
)
2292 if (reload_in_progress
2293 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2295 base
= find_replacement (&XEXP (ref
, 0));
2297 if (! memory_address_p (GET_MODE (ref
), base
))
2302 base
= XEXP (ref
, 0);
2305 if (GET_CODE (base
) == PLUS
)
2306 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2308 return plus_constant (base
, offset
+ extra_offset
);
2311 /* On the Alpha, all (non-symbolic) constants except zero go into
2312 a floating-point register via memory. Note that we cannot
2313 return anything that is not a subset of CLASS, and that some
2314 symbolic constants cannot be dropped to memory. */
2317 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
2319 /* Zero is present in any register class. */
2320 if (x
== CONST0_RTX (GET_MODE (x
)))
2323 /* These sorts of constants we can easily drop to memory. */
2324 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2326 if (class == FLOAT_REGS
)
2328 if (class == ALL_REGS
)
2329 return GENERAL_REGS
;
2333 /* All other kinds of constants should not (and in the case of HIGH
2334 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2335 secondary reload. */
2337 return (class == ALL_REGS
? GENERAL_REGS
: class);
2342 /* Loading and storing HImode or QImode values to and from memory
2343 usually requires a scratch register. The exceptions are loading
2344 QImode and HImode from an aligned address to a general register
2345 unless byte instructions are permitted.
2347 We also cannot load an unaligned address or a paradoxical SUBREG
2348 into an FP register.
2350 We also cannot do integral arithmetic into FP regs, as might result
2351 from register elimination into a DImode fp register. */
2354 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
2357 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2359 if (GET_CODE (x
) == MEM
2360 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2361 || (GET_CODE (x
) == SUBREG
2362 && (GET_CODE (SUBREG_REG (x
)) == MEM
2363 || (GET_CODE (SUBREG_REG (x
)) == REG
2364 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2366 if (!in
|| !aligned_memory_operand(x
, mode
))
2367 return GENERAL_REGS
;
2371 if (class == FLOAT_REGS
)
2373 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2374 return GENERAL_REGS
;
2376 if (GET_CODE (x
) == SUBREG
2377 && (GET_MODE_SIZE (GET_MODE (x
))
2378 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2379 return GENERAL_REGS
;
2381 if (in
&& INTEGRAL_MODE_P (mode
)
2382 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2383 return GENERAL_REGS
;
2389 /* Subfunction of the following function. Update the flags of any MEM
2390 found in part of X. */
2393 alpha_set_memflags_1 (rtx x
, int in_struct_p
, int volatile_p
, int unchanging_p
)
2397 switch (GET_CODE (x
))
2403 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2404 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2409 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2414 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2416 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2421 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2422 MEM_VOLATILE_P (x
) = volatile_p
;
2423 RTX_UNCHANGING_P (x
) = unchanging_p
;
2424 /* Sadly, we cannot use alias sets because the extra aliasing
2425 produced by the AND interferes. Given that two-byte quantities
2426 are the only thing we would be able to differentiate anyway,
2427 there does not seem to be any point in convoluting the early
2428 out of the alias check. */
2436 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2437 generated to perform a memory operation, look for any MEMs in either
2438 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2439 volatile flags from REF into each of the MEMs found. If REF is not
2440 a MEM, don't do anything. */
2443 alpha_set_memflags (rtx insn
, rtx ref
)
2445 int in_struct_p
, volatile_p
, unchanging_p
;
2447 if (GET_CODE (ref
) != MEM
)
2450 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2451 volatile_p
= MEM_VOLATILE_P (ref
);
2452 unchanging_p
= RTX_UNCHANGING_P (ref
);
2454 /* This is only called from alpha.md, after having had something
2455 generated from one of the insn patterns. So if everything is
2456 zero, the pattern is already up-to-date. */
2457 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2460 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2463 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2466 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
2467 HOST_WIDE_INT c
, int n
)
2471 /* Use a pseudo if highly optimizing and still generating RTL. */
2473 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2476 /* If this is a sign-extended 32-bit constant, we can do this in at most
2477 three insns, so do it if we have enough insns left. We always have
2478 a sign-extended 32-bit constant when compiling on a narrow machine. */
2480 if (HOST_BITS_PER_WIDE_INT
!= 64
2481 || c
>> 31 == -1 || c
>> 31 == 0)
2483 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2484 HOST_WIDE_INT tmp1
= c
- low
;
2485 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2486 HOST_WIDE_INT extra
= 0;
2488 /* If HIGH will be interpreted as negative but the constant is
2489 positive, we must adjust it to do two ldha insns. */
2491 if ((high
& 0x8000) != 0 && c
>= 0)
2495 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2498 if (c
== low
|| (low
== 0 && extra
== 0))
2500 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2501 but that meant that we can't handle INT_MIN on 32-bit machines
2502 (like NT/Alpha), because we recurse indefinitely through
2503 emit_move_insn to gen_movdi. So instead, since we know exactly
2504 what we want, create it explicitly. */
2507 target
= gen_reg_rtx (mode
);
2508 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2511 else if (n
>= 2 + (extra
!= 0))
2515 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
2519 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
2522 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2523 This means that if we go through expand_binop, we'll try to
2524 generate extensions, etc, which will require new pseudos, which
2525 will fail during some split phases. The SImode add patterns
2526 still exist, but are not named. So build the insns by hand. */
2531 subtarget
= gen_reg_rtx (mode
);
2532 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2533 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2539 target
= gen_reg_rtx (mode
);
2540 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2541 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2547 /* If we couldn't do it that way, try some other methods. But if we have
2548 no instructions left, don't bother. Likewise, if this is SImode and
2549 we can't make pseudos, we can't do anything since the expand_binop
2550 and expand_unop calls will widen and try to make pseudos. */
2552 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2555 /* Next, see if we can load a related constant and then shift and possibly
2556 negate it to get the constant we want. Try this once each increasing
2557 numbers of insns. */
2559 for (i
= 1; i
< n
; i
++)
2561 /* First, see if minus some low bits, we've an easy load of
2564 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2566 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2567 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2568 target
, 0, OPTAB_WIDEN
);
2570 /* Next try complementing. */
2571 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2572 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2574 /* Next try to form a constant and do a left shift. We can do this
2575 if some low-order bits are zero; the exact_log2 call below tells
2576 us that information. The bits we are shifting out could be any
2577 value, but here we'll just try the 0- and sign-extended forms of
2578 the constant. To try to increase the chance of having the same
2579 constant in more than one insn, start at the highest number of
2580 bits to shift, but try all possibilities in case a ZAPNOT will
2583 if ((bits
= exact_log2 (c
& - c
)) > 0)
2584 for (; bits
> 0; bits
--)
2585 if ((temp
= (alpha_emit_set_const
2586 (subtarget
, mode
, c
>> bits
, i
))) != 0
2587 || ((temp
= (alpha_emit_set_const
2589 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2591 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2592 target
, 0, OPTAB_WIDEN
);
2594 /* Now try high-order zero bits. Here we try the shifted-in bits as
2595 all zero and all ones. Be careful to avoid shifting outside the
2596 mode and to avoid shifting outside the host wide int size. */
2597 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2598 confuse the recursive call and set all of the high 32 bits. */
2600 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2601 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2602 for (; bits
> 0; bits
--)
2603 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2605 || ((temp
= (alpha_emit_set_const
2607 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2610 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2611 target
, 1, OPTAB_WIDEN
);
2613 /* Now try high-order 1 bits. We get that with a sign-extension.
2614 But one bit isn't enough here. Be careful to avoid shifting outside
2615 the mode and to avoid shifting outside the host wide int size. */
2617 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2618 - floor_log2 (~ c
) - 2)) > 0)
2619 for (; bits
> 0; bits
--)
2620 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2622 || ((temp
= (alpha_emit_set_const
2624 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2627 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2628 target
, 0, OPTAB_WIDEN
);
2631 #if HOST_BITS_PER_WIDE_INT == 64
2632 /* Finally, see if can load a value into the target that is the same as the
2633 constant except that all bytes that are 0 are changed to be 0xff. If we
2634 can, then we can do a ZAPNOT to obtain the desired constant. */
2637 for (i
= 0; i
< 64; i
+= 8)
2638 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2639 new |= (HOST_WIDE_INT
) 0xff << i
;
2641 /* We are only called for SImode and DImode. If this is SImode, ensure that
2642 we are sign extended to a full word. */
2645 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2647 if (new != c
&& new != -1
2648 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2649 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2650 target
, 0, OPTAB_WIDEN
);
2656 /* Try to output insns to set TARGET equal to the constant C if it can be
2657 done in less than N insns. Do all computations in MODE. Returns the place
2658 where the output has been placed if it can be done and the insns have been
2659 emitted. If it would take more than N insns, zero is returned and no
2660 insns and emitted. */
2663 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
2664 HOST_WIDE_INT c
, int n
)
2667 rtx orig_target
= target
;
2670 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2671 can't load this constant in one insn, do this in DImode. */
2672 if (no_new_pseudos
&& mode
== SImode
2673 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2674 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2676 target
= gen_lowpart (DImode
, target
);
2680 /* Try 1 insn, then 2, then up to N. */
2681 for (i
= 1; i
<= n
; i
++)
2683 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2686 rtx insn
= get_last_insn ();
2687 rtx set
= single_set (insn
);
2688 if (! CONSTANT_P (SET_SRC (set
)))
2689 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2694 /* Allow for the case where we changed the mode of TARGET. */
2695 if (result
== target
)
2696 result
= orig_target
;
2701 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2702 fall back to a straight forward decomposition. We do this to avoid
2703 exponential run times encountered when looking for longer sequences
2704 with alpha_emit_set_const. */
2707 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2709 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2711 /* Decompose the entire word */
2712 #if HOST_BITS_PER_WIDE_INT >= 64
2713 if (c2
!= -(c1
< 0))
2715 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2717 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2718 c1
= (c1
- d2
) >> 32;
2719 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2721 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2725 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2727 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2731 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2733 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2738 /* Construct the high word */
2741 emit_move_insn (target
, GEN_INT (d4
));
2743 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2746 emit_move_insn (target
, GEN_INT (d3
));
2748 /* Shift it into place */
2749 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2751 /* Add in the low bits. */
2753 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2755 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2760 /* Expand a move instruction; return true if all work is done.
2761 We don't handle non-bwx subword loads here. */
2764 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2766 /* If the output is not a register, the input must be. */
2767 if (GET_CODE (operands
[0]) == MEM
2768 && ! reg_or_0_operand (operands
[1], mode
))
2769 operands
[1] = force_reg (mode
, operands
[1]);
2771 /* Allow legitimize_address to perform some simplifications. */
2772 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2776 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2777 compiled at the end of compilation. In the meantime, someone can
2778 re-encode-section-info on some symbol changing it e.g. from global
2779 to local-not-small. If this happens, we'd have emitted a plain
2780 load rather than a high+losum load and not recognize the insn.
2782 So if rtl inlining is in effect, we delay the global/not-global
2783 decision until rest_of_compilation by wrapping it in an
2785 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2786 && rtx_equal_function_value_matters
2787 && global_symbolic_operand (operands
[1], mode
))
2789 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2793 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2796 if (tmp
== operands
[0])
2803 /* Early out for non-constants and valid constants. */
2804 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2807 /* Split large integers. */
2808 if (GET_CODE (operands
[1]) == CONST_INT
2809 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2811 HOST_WIDE_INT i0
, i1
;
2812 rtx temp
= NULL_RTX
;
2814 if (GET_CODE (operands
[1]) == CONST_INT
)
2816 i0
= INTVAL (operands
[1]);
2819 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2821 i0
= CONST_DOUBLE_LOW (operands
[1]);
2826 i0
= CONST_DOUBLE_LOW (operands
[1]);
2827 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2830 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2831 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2833 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2834 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2838 if (rtx_equal_p (operands
[0], temp
))
2845 /* Otherwise we've nothing left but to drop the thing to memory. */
2846 operands
[1] = force_const_mem (mode
, operands
[1]);
2847 if (reload_in_progress
)
2849 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2850 operands
[1] = copy_rtx (operands
[1]);
2851 XEXP (operands
[1], 0) = operands
[0];
2854 operands
[1] = validize_mem (operands
[1]);
2858 /* Expand a non-bwx QImode or HImode move instruction;
2859 return true if all work is done. */
2862 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2864 /* If the output is not a register, the input must be. */
2865 if (GET_CODE (operands
[0]) == MEM
)
2866 operands
[1] = force_reg (mode
, operands
[1]);
2868 /* Handle four memory cases, unaligned and aligned for either the input
2869 or the output. The only case where we can be called during reload is
2870 for aligned loads; all other cases require temporaries. */
2872 if (GET_CODE (operands
[1]) == MEM
2873 || (GET_CODE (operands
[1]) == SUBREG
2874 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2875 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2876 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2877 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2878 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2879 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2881 if (aligned_memory_operand (operands
[1], mode
))
2883 if (reload_in_progress
)
2885 emit_insn ((mode
== QImode
2886 ? gen_reload_inqi_help
2887 : gen_reload_inhi_help
)
2888 (operands
[0], operands
[1],
2889 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2893 rtx aligned_mem
, bitnum
;
2894 rtx scratch
= gen_reg_rtx (SImode
);
2898 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2900 subtarget
= operands
[0];
2901 if (GET_CODE (subtarget
) == REG
)
2902 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2904 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2906 emit_insn ((mode
== QImode
2907 ? gen_aligned_loadqi
2908 : gen_aligned_loadhi
)
2909 (subtarget
, aligned_mem
, bitnum
, scratch
));
2912 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2917 /* Don't pass these as parameters since that makes the generated
2918 code depend on parameter evaluation order which will cause
2919 bootstrap failures. */
2921 rtx temp1
, temp2
, seq
, subtarget
;
2924 temp1
= gen_reg_rtx (DImode
);
2925 temp2
= gen_reg_rtx (DImode
);
2927 subtarget
= operands
[0];
2928 if (GET_CODE (subtarget
) == REG
)
2929 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2931 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2933 seq
= ((mode
== QImode
2934 ? gen_unaligned_loadqi
2935 : gen_unaligned_loadhi
)
2936 (subtarget
, get_unaligned_address (operands
[1], 0),
2938 alpha_set_memflags (seq
, operands
[1]);
2942 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2947 if (GET_CODE (operands
[0]) == MEM
2948 || (GET_CODE (operands
[0]) == SUBREG
2949 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2950 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2951 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2952 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2953 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2954 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2956 if (aligned_memory_operand (operands
[0], mode
))
2958 rtx aligned_mem
, bitnum
;
2959 rtx temp1
= gen_reg_rtx (SImode
);
2960 rtx temp2
= gen_reg_rtx (SImode
);
2962 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2964 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2969 rtx temp1
= gen_reg_rtx (DImode
);
2970 rtx temp2
= gen_reg_rtx (DImode
);
2971 rtx temp3
= gen_reg_rtx (DImode
);
2972 rtx seq
= ((mode
== QImode
2973 ? gen_unaligned_storeqi
2974 : gen_unaligned_storehi
)
2975 (get_unaligned_address (operands
[0], 0),
2976 operands
[1], temp1
, temp2
, temp3
));
2978 alpha_set_memflags (seq
, operands
[0]);
2987 /* Generate an unsigned DImode to FP conversion. This is the same code
2988 optabs would emit if we didn't have TFmode patterns.
2990 For SFmode, this is the only construction I've found that can pass
2991 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2992 intermediates will work, because you'll get intermediate rounding
2993 that ruins the end result. Some of this could be fixed by turning
2994 on round-to-positive-infinity, but that requires diddling the fpsr,
2995 which kills performance. I tried turning this around and converting
2996 to a negative number, so that I could turn on /m, but either I did
2997 it wrong or there's something else cause I wound up with the exact
2998 same single-bit error. There is a branch-less form of this same code:
3009 fcmoveq $f10,$f11,$f0
3011 I'm not using it because it's the same number of instructions as
3012 this branch-full form, and it has more serialized long latency
3013 instructions on the critical path.
3015 For DFmode, we can avoid rounding errors by breaking up the word
3016 into two pieces, converting them separately, and adding them back:
3018 LC0: .long 0,0x5f800000
3023 cpyse $f11,$f31,$f10
3024 cpyse $f31,$f11,$f11
3032 This doesn't seem to be a clear-cut win over the optabs form.
3033 It probably all depends on the distribution of numbers being
3034 converted -- in the optabs form, all but high-bit-set has a
3035 much lower minimum execution time. */
3038 alpha_emit_floatuns (rtx operands
[2])
3040 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3041 enum machine_mode mode
;
3044 in
= force_reg (DImode
, operands
[1]);
3045 mode
= GET_MODE (out
);
3046 neglab
= gen_label_rtx ();
3047 donelab
= gen_label_rtx ();
3048 i0
= gen_reg_rtx (DImode
);
3049 i1
= gen_reg_rtx (DImode
);
3050 f0
= gen_reg_rtx (mode
);
3052 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3054 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3055 emit_jump_insn (gen_jump (donelab
));
3058 emit_label (neglab
);
3060 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3061 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3062 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3063 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3064 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3066 emit_label (donelab
);
3069 /* Generate the comparison for a conditional branch. */
3072 alpha_emit_conditional_branch (enum rtx_code code
)
3074 enum rtx_code cmp_code
, branch_code
;
3075 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3076 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3079 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3081 if (! TARGET_HAS_XFLOATING_LIBS
)
3084 /* X_floating library comparison functions return
3088 Convert the compare against the raw return value. */
3110 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3112 alpha_compare
.fp_p
= 0;
3115 /* The general case: fold the comparison code to the types of compares
3116 that we have, choosing the branch as necessary. */
3119 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3121 /* We have these compares: */
3122 cmp_code
= code
, branch_code
= NE
;
3127 /* These must be reversed. */
3128 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3131 case GE
: case GT
: case GEU
: case GTU
:
3132 /* For FP, we swap them, for INT, we reverse them. */
3133 if (alpha_compare
.fp_p
)
3135 cmp_code
= swap_condition (code
);
3137 tem
= op0
, op0
= op1
, op1
= tem
;
3141 cmp_code
= reverse_condition (code
);
3150 if (alpha_compare
.fp_p
)
3153 if (flag_unsafe_math_optimizations
)
3155 /* When we are not as concerned about non-finite values, and we
3156 are comparing against zero, we can branch directly. */
3157 if (op1
== CONST0_RTX (DFmode
))
3158 cmp_code
= NIL
, branch_code
= code
;
3159 else if (op0
== CONST0_RTX (DFmode
))
3161 /* Undo the swap we probably did just above. */
3162 tem
= op0
, op0
= op1
, op1
= tem
;
3163 branch_code
= swap_condition (cmp_code
);
3169 /* ??? We mark the branch mode to be CCmode to prevent the
3170 compare and branch from being combined, since the compare
3171 insn follows IEEE rules that the branch does not. */
3172 branch_mode
= CCmode
;
3179 /* The following optimizations are only for signed compares. */
3180 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3182 /* Whee. Compare and branch against 0 directly. */
3183 if (op1
== const0_rtx
)
3184 cmp_code
= NIL
, branch_code
= code
;
3186 /* If the constants doesn't fit into an immediate, but can
3187 be generated by lda/ldah, we adjust the argument and
3188 compare against zero, so we can use beq/bne directly. */
3189 /* ??? Don't do this when comparing against symbols, otherwise
3190 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
3191 be declared false out of hand (at least for non-weak). */
3192 else if (GET_CODE (op1
) == CONST_INT
3193 && (code
== EQ
|| code
== NE
)
3194 && !(symbolic_operand (op0
, VOIDmode
)
3195 || (GET_CODE (op0
) == REG
&& REG_POINTER (op0
))))
3197 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3199 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3200 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3201 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3203 cmp_code
= PLUS
, branch_code
= code
;
3209 if (!reg_or_0_operand (op0
, DImode
))
3210 op0
= force_reg (DImode
, op0
);
3211 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3212 op1
= force_reg (DImode
, op1
);
3215 /* Emit an initial compare instruction, if necessary. */
3217 if (cmp_code
!= NIL
)
3219 tem
= gen_reg_rtx (cmp_mode
);
3220 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3223 /* Zero the operands. */
3224 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3226 /* Return the branch comparison. */
3227 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3230 /* Certain simplifications can be done to make invalid setcc operations
3231 valid. Return the final comparison, or NULL if we can't work. */
3234 alpha_emit_setcc (enum rtx_code code
)
3236 enum rtx_code cmp_code
;
3237 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3238 int fp_p
= alpha_compare
.fp_p
;
3241 /* Zero the operands. */
3242 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3244 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3246 if (! TARGET_HAS_XFLOATING_LIBS
)
3249 /* X_floating library comparison functions return
3253 Convert the compare against the raw return value. */
3255 if (code
== UNORDERED
|| code
== ORDERED
)
3260 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3264 if (code
== UNORDERED
)
3266 else if (code
== ORDERED
)
3272 if (fp_p
&& !TARGET_FIX
)
3275 /* The general case: fold the comparison code to the types of compares
3276 that we have, choosing the branch as necessary. */
3281 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3283 /* We have these compares. */
3285 cmp_code
= code
, code
= NE
;
3289 if (!fp_p
&& op1
== const0_rtx
)
3294 cmp_code
= reverse_condition (code
);
3298 case GE
: case GT
: case GEU
: case GTU
:
3299 /* These normally need swapping, but for integer zero we have
3300 special patterns that recognize swapped operands. */
3301 if (!fp_p
&& op1
== const0_rtx
)
3303 code
= swap_condition (code
);
3305 cmp_code
= code
, code
= NE
;
3306 tmp
= op0
, op0
= op1
, op1
= tmp
;
3315 if (!register_operand (op0
, DImode
))
3316 op0
= force_reg (DImode
, op0
);
3317 if (!reg_or_8bit_operand (op1
, DImode
))
3318 op1
= force_reg (DImode
, op1
);
3321 /* Emit an initial compare instruction, if necessary. */
3322 if (cmp_code
!= NIL
)
3324 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3326 tmp
= gen_reg_rtx (mode
);
3327 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3328 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3330 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3334 /* Return the setcc comparison. */
3335 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3339 /* Rewrite a comparison against zero CMP of the form
3340 (CODE (cc0) (const_int 0)) so it can be written validly in
3341 a conditional move (if_then_else CMP ...).
3342 If both of the operands that set cc0 are nonzero we must emit
3343 an insn to perform the compare (it can't be done within
3344 the conditional move). */
3347 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
3349 enum rtx_code code
= GET_CODE (cmp
);
3350 enum rtx_code cmov_code
= NE
;
3351 rtx op0
= alpha_compare
.op0
;
3352 rtx op1
= alpha_compare
.op1
;
3353 int fp_p
= alpha_compare
.fp_p
;
3354 enum machine_mode cmp_mode
3355 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3356 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3357 enum machine_mode cmov_mode
= VOIDmode
;
3358 int local_fast_math
= flag_unsafe_math_optimizations
;
3361 /* Zero the operands. */
3362 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3364 if (fp_p
!= FLOAT_MODE_P (mode
))
3366 enum rtx_code cmp_code
;
3371 /* If we have fp<->int register move instructions, do a cmov by
3372 performing the comparison in fp registers, and move the
3373 zero/nonzero value to integer registers, where we can then
3374 use a normal cmov, or vice-versa. */
3378 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3379 /* We have these compares. */
3380 cmp_code
= code
, code
= NE
;
3384 /* This must be reversed. */
3385 cmp_code
= EQ
, code
= EQ
;
3388 case GE
: case GT
: case GEU
: case GTU
:
3389 /* These normally need swapping, but for integer zero we have
3390 special patterns that recognize swapped operands. */
3391 if (!fp_p
&& op1
== const0_rtx
)
3392 cmp_code
= code
, code
= NE
;
3395 cmp_code
= swap_condition (code
);
3397 tem
= op0
, op0
= op1
, op1
= tem
;
3405 tem
= gen_reg_rtx (cmp_op_mode
);
3406 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3407 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3410 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3411 op0
= gen_lowpart (cmp_op_mode
, tem
);
3412 op1
= CONST0_RTX (cmp_op_mode
);
3414 local_fast_math
= 1;
3417 /* We may be able to use a conditional move directly.
3418 This avoids emitting spurious compares. */
3419 if (signed_comparison_operator (cmp
, VOIDmode
)
3420 && (!fp_p
|| local_fast_math
)
3421 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3422 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3424 /* We can't put the comparison inside the conditional move;
3425 emit a compare instruction and put that inside the
3426 conditional move. Make sure we emit only comparisons we have;
3427 swap or reverse as necessary. */
3434 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3435 /* We have these compares: */
3439 /* This must be reversed. */
3440 code
= reverse_condition (code
);
3444 case GE
: case GT
: case GEU
: case GTU
:
3445 /* These must be swapped. */
3446 if (op1
!= CONST0_RTX (cmp_mode
))
3448 code
= swap_condition (code
);
3449 tem
= op0
, op0
= op1
, op1
= tem
;
3459 if (!reg_or_0_operand (op0
, DImode
))
3460 op0
= force_reg (DImode
, op0
);
3461 if (!reg_or_8bit_operand (op1
, DImode
))
3462 op1
= force_reg (DImode
, op1
);
3465 /* ??? We mark the branch mode to be CCmode to prevent the compare
3466 and cmov from being combined, since the compare insn follows IEEE
3467 rules that the cmov does not. */
3468 if (fp_p
&& !local_fast_math
)
3471 tem
= gen_reg_rtx (cmp_op_mode
);
3472 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3473 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3476 /* Simplify a conditional move of two constants into a setcc with
3477 arithmetic. This is done with a splitter since combine would
3478 just undo the work if done during code generation. It also catches
3479 cases we wouldn't have before cse. */
3482 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
3483 rtx t_rtx
, rtx f_rtx
)
3485 HOST_WIDE_INT t
, f
, diff
;
3486 enum machine_mode mode
;
3487 rtx target
, subtarget
, tmp
;
3489 mode
= GET_MODE (dest
);
3494 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3495 || (code
== GE
|| code
== GT
))
3497 code
= reverse_condition (code
);
3498 diff
= t
, t
= f
, f
= diff
;
3502 subtarget
= target
= dest
;
3505 target
= gen_lowpart (DImode
, dest
);
3506 if (! no_new_pseudos
)
3507 subtarget
= gen_reg_rtx (DImode
);
3511 /* Below, we must be careful to use copy_rtx on target and subtarget
3512 in intermediate insns, as they may be a subreg rtx, which may not
3515 if (f
== 0 && exact_log2 (diff
) > 0
3516 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3517 viable over a longer latency cmove. On EV5, the E0 slot is a
3518 scarce resource, and on EV4 shift has the same latency as a cmove. */
3519 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3521 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3522 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3524 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3525 GEN_INT (exact_log2 (t
)));
3526 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3528 else if (f
== 0 && t
== -1)
3530 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3531 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3533 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3535 else if (diff
== 1 || diff
== 4 || diff
== 8)
3539 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3540 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3543 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3546 add_op
= GEN_INT (f
);
3547 if (sext_add_operand (add_op
, mode
))
3549 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3551 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3552 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3564 /* Look up the function X_floating library function name for the
3567 struct xfloating_op
GTY(())
3569 const enum rtx_code code
;
3570 const char *const GTY((skip
)) osf_func
;
3571 const char *const GTY((skip
)) vms_func
;
3575 static GTY(()) struct xfloating_op xfloating_ops
[] =
3577 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
3578 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
3579 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
3580 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
3581 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
3582 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
3583 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
3584 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
3585 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
3586 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
3587 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
3588 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
3589 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
3590 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
3591 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
3594 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
3596 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
3597 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
3601 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
3603 struct xfloating_op
*ops
= xfloating_ops
;
3604 long n
= ARRAY_SIZE (xfloating_ops
);
3607 /* How irritating. Nothing to key off for the main table. */
3608 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
3611 n
= ARRAY_SIZE (vax_cvt_ops
);
3614 for (i
= 0; i
< n
; ++i
, ++ops
)
3615 if (ops
->code
== code
)
3617 rtx func
= ops
->libcall
;
3620 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
3621 ? ops
->vms_func
: ops
->osf_func
);
3622 ops
->libcall
= func
;
3630 /* Most X_floating operations take the rounding mode as an argument.
3631 Compute that here. */
3634 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
3635 enum alpha_fp_rounding_mode round
)
3641 case ALPHA_FPRM_NORM
:
3644 case ALPHA_FPRM_MINF
:
3647 case ALPHA_FPRM_CHOP
:
3650 case ALPHA_FPRM_DYN
:
3656 /* XXX For reference, round to +inf is mode = 3. */
3659 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3665 /* Emit an X_floating library function call.
3667 Note that these functions do not follow normal calling conventions:
3668 TFmode arguments are passed in two integer registers (as opposed to
3669 indirect); TFmode return values appear in R16+R17.
3671 FUNC is the function to call.
3672 TARGET is where the output belongs.
3673 OPERANDS are the inputs.
3674 NOPERANDS is the count of inputs.
3675 EQUIV is the expression equivalent for the function.
3679 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
3680 int noperands
, rtx equiv
)
3682 rtx usage
= NULL_RTX
, tmp
, reg
;
3687 for (i
= 0; i
< noperands
; ++i
)
3689 switch (GET_MODE (operands
[i
]))
3692 reg
= gen_rtx_REG (TFmode
, regno
);
3697 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3702 if (GET_CODE (operands
[i
]) != CONST_INT
)
3706 reg
= gen_rtx_REG (DImode
, regno
);
3714 emit_move_insn (reg
, operands
[i
]);
3715 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3718 switch (GET_MODE (target
))
3721 reg
= gen_rtx_REG (TFmode
, 16);
3724 reg
= gen_rtx_REG (DFmode
, 32);
3727 reg
= gen_rtx_REG (DImode
, 0);
3733 tmp
= gen_rtx_MEM (QImode
, func
);
3734 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3735 const0_rtx
, const0_rtx
));
3736 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3737 CONST_OR_PURE_CALL_P (tmp
) = 1;
3742 emit_libcall_block (tmp
, target
, reg
, equiv
);
3745 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3748 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3752 rtx out_operands
[3];
3754 func
= alpha_lookup_xfloating_lib_func (code
);
3755 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3757 out_operands
[0] = operands
[1];
3758 out_operands
[1] = operands
[2];
3759 out_operands
[2] = GEN_INT (mode
);
3760 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3761 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3765 /* Emit an X_floating library function call for a comparison. */
3768 alpha_emit_xfloating_compare (enum rtx_code code
, rtx op0
, rtx op1
)
3771 rtx out
, operands
[2];
3773 func
= alpha_lookup_xfloating_lib_func (code
);
3777 out
= gen_reg_rtx (DImode
);
3779 /* ??? Strange mode for equiv because what's actually returned
3780 is -1,0,1, not a proper boolean value. */
3781 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3782 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3787 /* Emit an X_floating library function call for a conversion. */
3790 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3792 int noperands
= 1, mode
;
3793 rtx out_operands
[2];
3795 enum rtx_code code
= orig_code
;
3797 if (code
== UNSIGNED_FIX
)
3800 func
= alpha_lookup_xfloating_lib_func (code
);
3802 out_operands
[0] = operands
[1];
3807 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3808 out_operands
[1] = GEN_INT (mode
);
3811 case FLOAT_TRUNCATE
:
3812 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3813 out_operands
[1] = GEN_INT (mode
);
3820 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3821 gen_rtx_fmt_e (orig_code
,
3822 GET_MODE (operands
[0]),
3826 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3827 OP[0] into OP[0,1]. Naturally, output operand ordering is
3831 alpha_split_tfmode_pair (rtx operands
[4])
3833 if (GET_CODE (operands
[1]) == REG
)
3835 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3836 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3838 else if (GET_CODE (operands
[1]) == MEM
)
3840 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3841 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3843 else if (operands
[1] == CONST0_RTX (TFmode
))
3844 operands
[2] = operands
[3] = const0_rtx
;
3848 if (GET_CODE (operands
[0]) == REG
)
3850 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3851 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3853 else if (GET_CODE (operands
[0]) == MEM
)
3855 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3856 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3862 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3863 op2 is a register containing the sign bit, operation is the
3864 logical operation to be performed. */
3867 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3869 rtx high_bit
= operands
[2];
3873 alpha_split_tfmode_pair (operands
);
3875 /* Detect three flavors of operand overlap. */
3877 if (rtx_equal_p (operands
[0], operands
[2]))
3879 else if (rtx_equal_p (operands
[1], operands
[2]))
3881 if (rtx_equal_p (operands
[0], high_bit
))
3888 emit_move_insn (operands
[0], operands
[2]);
3890 /* ??? If the destination overlaps both source tf and high_bit, then
3891 assume source tf is dead in its entirety and use the other half
3892 for a scratch register. Otherwise "scratch" is just the proper
3893 destination register. */
3894 scratch
= operands
[move
< 2 ? 1 : 3];
3896 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3900 emit_move_insn (operands
[0], operands
[2]);
3902 emit_move_insn (operands
[1], scratch
);
3906 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3910 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3911 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3912 lda r3,X(r11) lda r3,X+2(r11)
3913 extwl r1,r3,r1 extql r1,r3,r1
3914 extwh r2,r3,r2 extqh r2,r3,r2
3915 or r1.r2.r1 or r1,r2,r1
3918 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3919 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3920 lda r3,X(r11) lda r3,X(r11)
3921 extll r1,r3,r1 extll r1,r3,r1
3922 extlh r2,r3,r2 extlh r2,r3,r2
3923 or r1.r2.r1 addl r1,r2,r1
3925 quad: ldq_u r1,X(r11)
3934 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3935 HOST_WIDE_INT ofs
, int sign
)
3937 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3938 enum machine_mode mode
;
3940 meml
= gen_reg_rtx (DImode
);
3941 memh
= gen_reg_rtx (DImode
);
3942 addr
= gen_reg_rtx (DImode
);
3943 extl
= gen_reg_rtx (DImode
);
3944 exth
= gen_reg_rtx (DImode
);
3946 mema
= XEXP (mem
, 0);
3947 if (GET_CODE (mema
) == LO_SUM
)
3948 mema
= force_reg (Pmode
, mema
);
3950 /* AND addresses cannot be in any alias set, since they may implicitly
3951 alias surrounding code. Ideally we'd have some alias set that
3952 covered all types except those with alignment 8 or higher. */
3954 tmp
= change_address (mem
, DImode
,
3955 gen_rtx_AND (DImode
,
3956 plus_constant (mema
, ofs
),
3958 set_mem_alias_set (tmp
, 0);
3959 emit_move_insn (meml
, tmp
);
3961 tmp
= change_address (mem
, DImode
,
3962 gen_rtx_AND (DImode
,
3963 plus_constant (mema
, ofs
+ size
- 1),
3965 set_mem_alias_set (tmp
, 0);
3966 emit_move_insn (memh
, tmp
);
3968 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3970 emit_move_insn (addr
, plus_constant (mema
, -1));
3972 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3973 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3975 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3976 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3977 addr
, 1, OPTAB_WIDEN
);
3979 else if (sign
&& size
== 2)
3981 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3983 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3984 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3986 /* We must use tgt here for the target. Alpha-vms port fails if we use
3987 addr for the target, because addr is marked as a pointer and combine
3988 knows that pointers are always sign-extended 32 bit values. */
3989 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3990 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3991 addr
, 1, OPTAB_WIDEN
);
3995 if (WORDS_BIG_ENDIAN
)
3997 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4001 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4006 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4011 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4018 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4022 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4023 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4027 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4032 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4037 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4046 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4047 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4052 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4055 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4058 alpha_expand_unaligned_store (rtx dst
, rtx src
,
4059 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
4061 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4063 dstl
= gen_reg_rtx (DImode
);
4064 dsth
= gen_reg_rtx (DImode
);
4065 insl
= gen_reg_rtx (DImode
);
4066 insh
= gen_reg_rtx (DImode
);
4068 dsta
= XEXP (dst
, 0);
4069 if (GET_CODE (dsta
) == LO_SUM
)
4070 dsta
= force_reg (Pmode
, dsta
);
4072 /* AND addresses cannot be in any alias set, since they may implicitly
4073 alias surrounding code. Ideally we'd have some alias set that
4074 covered all types except those with alignment 8 or higher. */
4076 meml
= change_address (dst
, DImode
,
4077 gen_rtx_AND (DImode
,
4078 plus_constant (dsta
, ofs
),
4080 set_mem_alias_set (meml
, 0);
4082 memh
= change_address (dst
, DImode
,
4083 gen_rtx_AND (DImode
,
4084 plus_constant (dsta
, ofs
+ size
- 1),
4086 set_mem_alias_set (memh
, 0);
4088 emit_move_insn (dsth
, memh
);
4089 emit_move_insn (dstl
, meml
);
4090 if (WORDS_BIG_ENDIAN
)
4092 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4094 if (src
!= const0_rtx
)
4099 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4102 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4105 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4108 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4109 GEN_INT (size
*8), addr
));
4115 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4119 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4120 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4124 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4128 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4132 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4134 if (src
!= const0_rtx
)
4136 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4137 GEN_INT (size
*8), addr
));
4142 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4145 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4148 emit_insn (gen_insql_le (insl
, src
, addr
));
4153 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4158 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4162 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4163 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4167 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4172 if (src
!= const0_rtx
)
4174 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4175 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4178 if (WORDS_BIG_ENDIAN
)
4180 emit_move_insn (meml
, dstl
);
4181 emit_move_insn (memh
, dsth
);
4185 /* Must store high before low for degenerate case of aligned. */
4186 emit_move_insn (memh
, dsth
);
4187 emit_move_insn (meml
, dstl
);
4191 /* The block move code tries to maximize speed by separating loads and
4192 stores at the expense of register pressure: we load all of the data
4193 before we store it back out. There are two secondary effects worth
4194 mentioning, that this speeds copying to/from aligned and unaligned
4195 buffers, and that it makes the code significantly easier to write. */
4197 #define MAX_MOVE_WORDS 8
4199 /* Load an integral number of consecutive unaligned quadwords. */
4202 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
4203 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4205 rtx
const im8
= GEN_INT (-8);
4206 rtx
const i64
= GEN_INT (64);
4207 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4208 rtx sreg
, areg
, tmp
, smema
;
4211 smema
= XEXP (smem
, 0);
4212 if (GET_CODE (smema
) == LO_SUM
)
4213 smema
= force_reg (Pmode
, smema
);
4215 /* Generate all the tmp registers we need. */
4216 for (i
= 0; i
< words
; ++i
)
4218 data_regs
[i
] = out_regs
[i
];
4219 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4221 data_regs
[words
] = gen_reg_rtx (DImode
);
4224 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4226 /* Load up all of the source data. */
4227 for (i
= 0; i
< words
; ++i
)
4229 tmp
= change_address (smem
, DImode
,
4230 gen_rtx_AND (DImode
,
4231 plus_constant (smema
, 8*i
),
4233 set_mem_alias_set (tmp
, 0);
4234 emit_move_insn (data_regs
[i
], tmp
);
4237 tmp
= change_address (smem
, DImode
,
4238 gen_rtx_AND (DImode
,
4239 plus_constant (smema
, 8*words
- 1),
4241 set_mem_alias_set (tmp
, 0);
4242 emit_move_insn (data_regs
[words
], tmp
);
4244 /* Extract the half-word fragments. Unfortunately DEC decided to make
4245 extxh with offset zero a noop instead of zeroing the register, so
4246 we must take care of that edge condition ourselves with cmov. */
4248 sreg
= copy_addr_to_reg (smema
);
4249 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4251 if (WORDS_BIG_ENDIAN
)
4252 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4253 for (i
= 0; i
< words
; ++i
)
4255 if (WORDS_BIG_ENDIAN
)
4257 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4258 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4262 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4263 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4265 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4266 gen_rtx_IF_THEN_ELSE (DImode
,
4267 gen_rtx_EQ (DImode
, areg
,
4269 const0_rtx
, ext_tmps
[i
])));
4272 /* Merge the half-words into whole words. */
4273 for (i
= 0; i
< words
; ++i
)
4275 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4276 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4280 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4281 may be NULL to store zeros. */
4284 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
4285 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4287 rtx
const im8
= GEN_INT (-8);
4288 rtx
const i64
= GEN_INT (64);
4289 rtx ins_tmps
[MAX_MOVE_WORDS
];
4290 rtx st_tmp_1
, st_tmp_2
, dreg
;
4291 rtx st_addr_1
, st_addr_2
, dmema
;
4294 dmema
= XEXP (dmem
, 0);
4295 if (GET_CODE (dmema
) == LO_SUM
)
4296 dmema
= force_reg (Pmode
, dmema
);
4298 /* Generate all the tmp registers we need. */
4299 if (data_regs
!= NULL
)
4300 for (i
= 0; i
< words
; ++i
)
4301 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4302 st_tmp_1
= gen_reg_rtx(DImode
);
4303 st_tmp_2
= gen_reg_rtx(DImode
);
4306 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4308 st_addr_2
= change_address (dmem
, DImode
,
4309 gen_rtx_AND (DImode
,
4310 plus_constant (dmema
, words
*8 - 1),
4312 set_mem_alias_set (st_addr_2
, 0);
4314 st_addr_1
= change_address (dmem
, DImode
,
4315 gen_rtx_AND (DImode
, dmema
, im8
));
4316 set_mem_alias_set (st_addr_1
, 0);
4318 /* Load up the destination end bits. */
4319 emit_move_insn (st_tmp_2
, st_addr_2
);
4320 emit_move_insn (st_tmp_1
, st_addr_1
);
4322 /* Shift the input data into place. */
4323 dreg
= copy_addr_to_reg (dmema
);
4324 if (WORDS_BIG_ENDIAN
)
4325 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4326 if (data_regs
!= NULL
)
4328 for (i
= words
-1; i
>= 0; --i
)
4330 if (WORDS_BIG_ENDIAN
)
4332 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4333 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4337 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4338 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4341 for (i
= words
-1; i
> 0; --i
)
4343 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4344 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4349 /* Split and merge the ends with the destination data. */
4350 if (WORDS_BIG_ENDIAN
)
4352 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4353 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4357 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4358 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4361 if (data_regs
!= NULL
)
4363 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4364 st_tmp_2
, 1, OPTAB_WIDEN
);
4365 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4366 st_tmp_1
, 1, OPTAB_WIDEN
);
4370 if (WORDS_BIG_ENDIAN
)
4371 emit_move_insn (st_addr_1
, st_tmp_1
);
4373 emit_move_insn (st_addr_2
, st_tmp_2
);
4374 for (i
= words
-1; i
> 0; --i
)
4376 rtx tmp
= change_address (dmem
, DImode
,
4377 gen_rtx_AND (DImode
,
4378 plus_constant(dmema
,
4379 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4381 set_mem_alias_set (tmp
, 0);
4382 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4384 if (WORDS_BIG_ENDIAN
)
4385 emit_move_insn (st_addr_2
, st_tmp_2
);
4387 emit_move_insn (st_addr_1
, st_tmp_1
);
4391 /* Expand string/block move operations.
4393 operands[0] is the pointer to the destination.
4394 operands[1] is the pointer to the source.
4395 operands[2] is the number of bytes to move.
4396 operands[3] is the alignment. */
4399 alpha_expand_block_move (rtx operands
[])
4401 rtx bytes_rtx
= operands
[2];
4402 rtx align_rtx
= operands
[3];
4403 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4404 HOST_WIDE_INT bytes
= orig_bytes
;
4405 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4406 HOST_WIDE_INT dst_align
= src_align
;
4407 rtx orig_src
= operands
[1];
4408 rtx orig_dst
= operands
[0];
4409 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4411 unsigned int i
, words
, ofs
, nregs
= 0;
4413 if (orig_bytes
<= 0)
4415 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4418 /* Look for additional alignment information from recorded register info. */
4420 tmp
= XEXP (orig_src
, 0);
4421 if (GET_CODE (tmp
) == REG
)
4422 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4423 else if (GET_CODE (tmp
) == PLUS
4424 && GET_CODE (XEXP (tmp
, 0)) == REG
4425 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4427 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4428 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4432 if (a
>= 64 && c
% 8 == 0)
4434 else if (a
>= 32 && c
% 4 == 0)
4436 else if (a
>= 16 && c
% 2 == 0)
4441 tmp
= XEXP (orig_dst
, 0);
4442 if (GET_CODE (tmp
) == REG
)
4443 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4444 else if (GET_CODE (tmp
) == PLUS
4445 && GET_CODE (XEXP (tmp
, 0)) == REG
4446 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4448 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4449 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4453 if (a
>= 64 && c
% 8 == 0)
4455 else if (a
>= 32 && c
% 4 == 0)
4457 else if (a
>= 16 && c
% 2 == 0)
4462 /* Load the entire block into registers. */
4463 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4465 enum machine_mode mode
;
4467 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4469 /* Don't use the existing register if we're reading more than
4470 is held in the register. Nor if there is not a mode that
4471 handles the exact size. */
4472 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4473 if (GET_CODE (tmp
) == REG
4475 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4479 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4480 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4484 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4489 /* No appropriate mode; fall back on memory. */
4490 orig_src
= replace_equiv_address (orig_src
,
4491 copy_addr_to_reg (XEXP (orig_src
, 0)));
4492 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4496 if (src_align
>= 64 && bytes
>= 8)
4500 for (i
= 0; i
< words
; ++i
)
4501 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4503 for (i
= 0; i
< words
; ++i
)
4504 emit_move_insn (data_regs
[nregs
+ i
],
4505 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4512 if (src_align
>= 32 && bytes
>= 4)
4516 for (i
= 0; i
< words
; ++i
)
4517 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4519 for (i
= 0; i
< words
; ++i
)
4520 emit_move_insn (data_regs
[nregs
+ i
],
4521 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4532 for (i
= 0; i
< words
+1; ++i
)
4533 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4535 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4543 if (! TARGET_BWX
&& bytes
>= 4)
4545 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4546 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4553 if (src_align
>= 16)
4556 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4557 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4560 } while (bytes
>= 2);
4562 else if (! TARGET_BWX
)
4564 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4565 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4573 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4574 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4581 if (nregs
> ARRAY_SIZE (data_regs
))
4584 /* Now save it back out again. */
4588 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4590 enum machine_mode mode
;
4591 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4593 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4594 if (GET_CODE (tmp
) == REG
&& GET_MODE (tmp
) == mode
)
4598 emit_move_insn (tmp
, data_regs
[0]);
4603 else if (nregs
== 2 && mode
== TImode
)
4605 /* Undo the subregging done above when copying between
4606 two TImode registers. */
4607 if (GET_CODE (data_regs
[0]) == SUBREG
4608 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4609 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4615 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4616 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4620 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4621 data_regs
[1], NULL_RTX
);
4629 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4630 /* ??? Optimize mode < dst_mode with strict_low_part. */
4632 /* No appropriate mode; fall back on memory. We can speed things
4633 up by recognizing extra alignment information. */
4634 orig_dst
= replace_equiv_address (orig_dst
,
4635 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4636 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4639 /* Write out the data in whatever chunks reading the source allowed. */
4640 if (dst_align
>= 64)
4642 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4644 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4651 if (dst_align
>= 32)
4653 /* If the source has remaining DImode regs, write them out in
4655 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4657 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4658 NULL_RTX
, 1, OPTAB_WIDEN
);
4660 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4661 gen_lowpart (SImode
, data_regs
[i
]));
4662 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4663 gen_lowpart (SImode
, tmp
));
4668 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4670 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4677 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4679 /* Write out a remaining block of words using unaligned methods. */
4681 for (words
= 1; i
+ words
< nregs
; words
++)
4682 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4686 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4688 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4695 /* Due to the above, this won't be aligned. */
4696 /* ??? If we have more than one of these, consider constructing full
4697 words in registers and using alpha_expand_unaligned_store_words. */
4698 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4700 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4705 if (dst_align
>= 16)
4706 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4708 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4713 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4715 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4720 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4722 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4736 alpha_expand_block_clear (rtx operands
[])
4738 rtx bytes_rtx
= operands
[1];
4739 rtx align_rtx
= operands
[2];
4740 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4741 HOST_WIDE_INT bytes
= orig_bytes
;
4742 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4743 HOST_WIDE_INT alignofs
= 0;
4744 rtx orig_dst
= operands
[0];
4746 int i
, words
, ofs
= 0;
4748 if (orig_bytes
<= 0)
4750 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4753 /* Look for stricter alignment. */
4754 tmp
= XEXP (orig_dst
, 0);
4755 if (GET_CODE (tmp
) == REG
)
4756 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4757 else if (GET_CODE (tmp
) == PLUS
4758 && GET_CODE (XEXP (tmp
, 0)) == REG
4759 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4761 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4762 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4767 align
= a
, alignofs
= 8 - c
% 8;
4769 align
= a
, alignofs
= 4 - c
% 4;
4771 align
= a
, alignofs
= 2 - c
% 2;
4774 else if (GET_CODE (tmp
) == ADDRESSOF
)
4776 enum machine_mode mode
;
4778 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4779 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4781 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4785 /* No appropriate mode; fall back on memory. */
4786 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4787 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4790 /* Handle an unaligned prefix first. */
4794 #if HOST_BITS_PER_WIDE_INT >= 64
4795 /* Given that alignofs is bounded by align, the only time BWX could
4796 generate three stores is for a 7 byte fill. Prefer two individual
4797 stores over a load/mask/store sequence. */
4798 if ((!TARGET_BWX
|| alignofs
== 7)
4800 && !(alignofs
== 4 && bytes
>= 4))
4802 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4803 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4807 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4808 set_mem_alias_set (mem
, 0);
4810 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4811 if (bytes
< alignofs
)
4813 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4824 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4825 NULL_RTX
, 1, OPTAB_WIDEN
);
4827 emit_move_insn (mem
, tmp
);
4831 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4833 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4838 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4840 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4845 if (alignofs
== 4 && bytes
>= 4)
4847 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4853 /* If we've not used the extra lead alignment information by now,
4854 we won't be able to. Downgrade align to match what's left over. */
4857 alignofs
= alignofs
& -alignofs
;
4858 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4862 /* Handle a block of contiguous long-words. */
4864 if (align
>= 64 && bytes
>= 8)
4868 for (i
= 0; i
< words
; ++i
)
4869 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4876 /* If the block is large and appropriately aligned, emit a single
4877 store followed by a sequence of stq_u insns. */
4879 if (align
>= 32 && bytes
> 16)
4883 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4887 orig_dsta
= XEXP (orig_dst
, 0);
4888 if (GET_CODE (orig_dsta
) == LO_SUM
)
4889 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4892 for (i
= 0; i
< words
; ++i
)
4895 = change_address (orig_dst
, DImode
,
4896 gen_rtx_AND (DImode
,
4897 plus_constant (orig_dsta
, ofs
+ i
*8),
4899 set_mem_alias_set (mem
, 0);
4900 emit_move_insn (mem
, const0_rtx
);
4903 /* Depending on the alignment, the first stq_u may have overlapped
4904 with the initial stl, which means that the last stq_u didn't
4905 write as much as it would appear. Leave those questionable bytes
4907 bytes
-= words
* 8 - 4;
4908 ofs
+= words
* 8 - 4;
4911 /* Handle a smaller block of aligned words. */
4913 if ((align
>= 64 && bytes
== 4)
4914 || (align
== 32 && bytes
>= 4))
4918 for (i
= 0; i
< words
; ++i
)
4919 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4926 /* An unaligned block uses stq_u stores for as many as possible. */
4932 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4938 /* Next clean up any trailing pieces. */
4940 #if HOST_BITS_PER_WIDE_INT >= 64
4941 /* Count the number of bits in BYTES for which aligned stores could
4944 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4948 /* If we have appropriate alignment (and it wouldn't take too many
4949 instructions otherwise), mask out the bytes we need. */
4950 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4957 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4958 set_mem_alias_set (mem
, 0);
4960 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4962 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4963 NULL_RTX
, 1, OPTAB_WIDEN
);
4965 emit_move_insn (mem
, tmp
);
4968 else if (align
>= 32 && bytes
< 4)
4973 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4974 set_mem_alias_set (mem
, 0);
4976 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4978 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4979 NULL_RTX
, 1, OPTAB_WIDEN
);
4981 emit_move_insn (mem
, tmp
);
4987 if (!TARGET_BWX
&& bytes
>= 4)
4989 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4999 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5003 } while (bytes
>= 2);
5005 else if (! TARGET_BWX
)
5007 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5015 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5023 /* Returns a mask so that zap(x, value) == x & mask. */
5026 alpha_expand_zap_mask (HOST_WIDE_INT value
)
5031 if (HOST_BITS_PER_WIDE_INT
>= 64)
5033 HOST_WIDE_INT mask
= 0;
5035 for (i
= 7; i
>= 0; --i
)
5038 if (!((value
>> i
) & 1))
5042 result
= gen_int_mode (mask
, DImode
);
5044 else if (HOST_BITS_PER_WIDE_INT
== 32)
5046 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5048 for (i
= 7; i
>= 4; --i
)
5051 if (!((value
>> i
) & 1))
5055 for (i
= 3; i
>= 0; --i
)
5058 if (!((value
>> i
) & 1))
5062 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5071 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
5072 enum machine_mode mode
,
5073 rtx op0
, rtx op1
, rtx op2
)
5075 op0
= gen_lowpart (mode
, op0
);
5077 if (op1
== const0_rtx
)
5078 op1
= CONST0_RTX (mode
);
5080 op1
= gen_lowpart (mode
, op1
);
5082 if (op2
== const0_rtx
)
5083 op2
= CONST0_RTX (mode
);
5085 op2
= gen_lowpart (mode
, op2
);
5087 emit_insn ((*gen
) (op0
, op1
, op2
));
5090 /* Adjust the cost of a scheduling dependency. Return the new cost of
5091 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5094 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5096 enum attr_type insn_type
, dep_insn_type
;
5098 /* If the dependence is an anti-dependence, there is no cost. For an
5099 output dependence, there is sometimes a cost, but it doesn't seem
5100 worth handling those few cases. */
5101 if (REG_NOTE_KIND (link
) != 0)
5104 /* If we can't recognize the insns, we can't really do anything. */
5105 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5108 insn_type
= get_attr_type (insn
);
5109 dep_insn_type
= get_attr_type (dep_insn
);
5111 /* Bring in the user-defined memory latency. */
5112 if (dep_insn_type
== TYPE_ILD
5113 || dep_insn_type
== TYPE_FLD
5114 || dep_insn_type
== TYPE_LDSYM
)
5115 cost
+= alpha_memory_latency
-1;
5117 /* Everything else handled in DFA bypasses now. */
5122 /* The number of instructions that can be issued per cycle. */
5125 alpha_issue_rate (void)
5127 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5131 alpha_use_dfa_pipeline_interface (void)
5136 /* How many alternative schedules to try. This should be as wide as the
5137 scheduling freedom in the DFA, but no wider. Making this value too
5138 large results extra work for the scheduler.
5140 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5141 alternative schedules. For EV5, we can choose between E0/E1 and
5142 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5145 alpha_multipass_dfa_lookahead (void)
5147 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5150 /* Machine-specific function data. */
5152 struct machine_function
GTY(())
5155 /* List of call information words for calls from this function. */
5156 struct rtx_def
*first_ciw
;
5157 struct rtx_def
*last_ciw
;
5160 /* List of deferred case vectors. */
5161 struct rtx_def
*addr_list
;
5164 const char *some_ld_name
;
5167 /* How to allocate a 'struct machine_function'. */
5169 static struct machine_function
*
5170 alpha_init_machine_status (void)
5172 return ((struct machine_function
*)
5173 ggc_alloc_cleared (sizeof (struct machine_function
)));
5176 /* Functions to save and restore alpha_return_addr_rtx. */
5178 /* Start the ball rolling with RETURN_ADDR_RTX. */
5181 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
5186 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5189 /* Return or create a pseudo containing the gp value for the current
5190 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5193 alpha_gp_save_rtx (void)
5195 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5196 if (GET_CODE (r
) != MEM
)
5197 r
= gen_mem_addressof (r
, NULL_TREE
, /*rescan=*/true);
5202 alpha_ra_ever_killed (void)
5206 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5207 return regs_ever_live
[REG_RA
];
5209 push_topmost_sequence ();
5211 pop_topmost_sequence ();
5213 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5217 /* Return the trap mode suffix applicable to the current
5218 instruction, or NULL. */
5221 get_trap_mode_suffix (void)
5223 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5227 case TRAP_SUFFIX_NONE
:
5230 case TRAP_SUFFIX_SU
:
5231 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5235 case TRAP_SUFFIX_SUI
:
5236 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5240 case TRAP_SUFFIX_V_SV
:
5248 case ALPHA_FPTM_SUI
:
5253 case TRAP_SUFFIX_V_SV_SVI
:
5262 case ALPHA_FPTM_SUI
:
5267 case TRAP_SUFFIX_U_SU_SUI
:
5276 case ALPHA_FPTM_SUI
:
5284 /* Return the rounding mode suffix applicable to the current
5285 instruction, or NULL. */
5288 get_round_mode_suffix (void)
5290 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5294 case ROUND_SUFFIX_NONE
:
5296 case ROUND_SUFFIX_NORMAL
:
5299 case ALPHA_FPRM_NORM
:
5301 case ALPHA_FPRM_MINF
:
5303 case ALPHA_FPRM_CHOP
:
5305 case ALPHA_FPRM_DYN
:
5310 case ROUND_SUFFIX_C
:
5316 /* Locate some local-dynamic symbol still in use by this function
5317 so that we can print its name in some movdi_er_tlsldm pattern. */
5320 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5324 if (GET_CODE (x
) == SYMBOL_REF
5325 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5327 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5335 get_some_local_dynamic_name (void)
5339 if (cfun
->machine
->some_ld_name
)
5340 return cfun
->machine
->some_ld_name
;
5342 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5344 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5345 return cfun
->machine
->some_ld_name
;
5350 /* Print an operand. Recognize special options, documented below. */
5353 print_operand (FILE *file
, rtx x
, int code
)
5360 /* Print the assembler name of the current function. */
5361 assemble_name (file
, alpha_fnname
);
5365 assemble_name (file
, get_some_local_dynamic_name ());
5370 const char *trap
= get_trap_mode_suffix ();
5371 const char *round
= get_round_mode_suffix ();
5374 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5375 (trap
? trap
: ""), (round
? round
: ""));
5380 /* Generates single precision instruction suffix. */
5381 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5385 /* Generates double precision instruction suffix. */
5386 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5390 /* Generates a nop after a noreturn call at the very end of the
5392 if (next_real_insn (current_output_insn
) == 0)
5393 fprintf (file
, "\n\tnop");
5397 if (alpha_this_literal_sequence_number
== 0)
5398 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5399 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5403 if (alpha_this_gpdisp_sequence_number
== 0)
5404 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5405 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5409 if (GET_CODE (x
) == HIGH
)
5410 output_addr_const (file
, XEXP (x
, 0));
5412 output_operand_lossage ("invalid %%H value");
5419 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5421 x
= XVECEXP (x
, 0, 0);
5422 lituse
= "lituse_tlsgd";
5424 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5426 x
= XVECEXP (x
, 0, 0);
5427 lituse
= "lituse_tlsldm";
5429 else if (GET_CODE (x
) == CONST_INT
)
5430 lituse
= "lituse_jsr";
5433 output_operand_lossage ("invalid %%J value");
5437 if (x
!= const0_rtx
)
5438 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5443 /* If this operand is the constant zero, write it as "$31". */
5444 if (GET_CODE (x
) == REG
)
5445 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5446 else if (x
== CONST0_RTX (GET_MODE (x
)))
5447 fprintf (file
, "$31");
5449 output_operand_lossage ("invalid %%r value");
5453 /* Similar, but for floating-point. */
5454 if (GET_CODE (x
) == REG
)
5455 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5456 else if (x
== CONST0_RTX (GET_MODE (x
)))
5457 fprintf (file
, "$f31");
5459 output_operand_lossage ("invalid %%R value");
5463 /* Write the 1's complement of a constant. */
5464 if (GET_CODE (x
) != CONST_INT
)
5465 output_operand_lossage ("invalid %%N value");
5467 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5471 /* Write 1 << C, for a constant C. */
5472 if (GET_CODE (x
) != CONST_INT
)
5473 output_operand_lossage ("invalid %%P value");
5475 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5479 /* Write the high-order 16 bits of a constant, sign-extended. */
5480 if (GET_CODE (x
) != CONST_INT
)
5481 output_operand_lossage ("invalid %%h value");
5483 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5487 /* Write the low-order 16 bits of a constant, sign-extended. */
5488 if (GET_CODE (x
) != CONST_INT
)
5489 output_operand_lossage ("invalid %%L value");
5491 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5492 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5496 /* Write mask for ZAP insn. */
5497 if (GET_CODE (x
) == CONST_DOUBLE
)
5499 HOST_WIDE_INT mask
= 0;
5500 HOST_WIDE_INT value
;
5502 value
= CONST_DOUBLE_LOW (x
);
5503 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5508 value
= CONST_DOUBLE_HIGH (x
);
5509 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5512 mask
|= (1 << (i
+ sizeof (int)));
5514 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5517 else if (GET_CODE (x
) == CONST_INT
)
5519 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5521 for (i
= 0; i
< 8; i
++, value
>>= 8)
5525 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5528 output_operand_lossage ("invalid %%m value");
5532 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5533 if (GET_CODE (x
) != CONST_INT
5534 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5535 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5536 output_operand_lossage ("invalid %%M value");
5538 fprintf (file
, "%s",
5539 (INTVAL (x
) == 8 ? "b"
5540 : INTVAL (x
) == 16 ? "w"
5541 : INTVAL (x
) == 32 ? "l"
5546 /* Similar, except do it from the mask. */
5547 if (GET_CODE (x
) == CONST_INT
)
5549 HOST_WIDE_INT value
= INTVAL (x
);
5556 if (value
== 0xffff)
5561 if (value
== 0xffffffff)
5572 else if (HOST_BITS_PER_WIDE_INT
== 32
5573 && GET_CODE (x
) == CONST_DOUBLE
5574 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5575 && CONST_DOUBLE_HIGH (x
) == 0)
5580 output_operand_lossage ("invalid %%U value");
5584 /* Write the constant value divided by 8 for little-endian mode or
5585 (56 - value) / 8 for big-endian mode. */
5587 if (GET_CODE (x
) != CONST_INT
5588 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5591 || (INTVAL (x
) & 7) != 0)
5592 output_operand_lossage ("invalid %%s value");
5594 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5596 ? (56 - INTVAL (x
)) / 8
5601 /* Same, except compute (64 - c) / 8 */
5603 if (GET_CODE (x
) != CONST_INT
5604 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5605 && (INTVAL (x
) & 7) != 8)
5606 output_operand_lossage ("invalid %%s value");
5608 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5613 /* On Unicos/Mk systems: use a DEX expression if the symbol
5614 clashes with a register name. */
5615 int dex
= unicosmk_need_dex (x
);
5617 fprintf (file
, "DEX(%d)", dex
);
5619 output_addr_const (file
, x
);
5623 case 'C': case 'D': case 'c': case 'd':
5624 /* Write out comparison name. */
5626 enum rtx_code c
= GET_CODE (x
);
5628 if (!COMPARISON_P (x
))
5629 output_operand_lossage ("invalid %%C value");
5631 else if (code
== 'D')
5632 c
= reverse_condition (c
);
5633 else if (code
== 'c')
5634 c
= swap_condition (c
);
5635 else if (code
== 'd')
5636 c
= swap_condition (reverse_condition (c
));
5639 fprintf (file
, "ule");
5641 fprintf (file
, "ult");
5642 else if (c
== UNORDERED
)
5643 fprintf (file
, "un");
5645 fprintf (file
, "%s", GET_RTX_NAME (c
));
5650 /* Write the divide or modulus operator. */
5651 switch (GET_CODE (x
))
5654 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5657 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5660 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5663 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5666 output_operand_lossage ("invalid %%E value");
5672 /* Write "_u" for unaligned access. */
5673 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5674 fprintf (file
, "_u");
5678 if (GET_CODE (x
) == REG
)
5679 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5680 else if (GET_CODE (x
) == MEM
)
5681 output_address (XEXP (x
, 0));
5682 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5684 switch (XINT (XEXP (x
, 0), 1))
5688 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5691 output_operand_lossage ("unknown relocation unspec");
5696 output_addr_const (file
, x
);
5700 output_operand_lossage ("invalid %%xn code");
5705 print_operand_address (FILE *file
, rtx addr
)
5708 HOST_WIDE_INT offset
= 0;
5710 if (GET_CODE (addr
) == AND
)
5711 addr
= XEXP (addr
, 0);
5713 if (GET_CODE (addr
) == PLUS
5714 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5716 offset
= INTVAL (XEXP (addr
, 1));
5717 addr
= XEXP (addr
, 0);
5720 if (GET_CODE (addr
) == LO_SUM
)
5722 const char *reloc16
, *reloclo
;
5723 rtx op1
= XEXP (addr
, 1);
5725 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5727 op1
= XEXP (op1
, 0);
5728 switch (XINT (op1
, 1))
5732 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5736 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5739 output_operand_lossage ("unknown relocation unspec");
5743 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5748 reloclo
= "gprellow";
5749 output_addr_const (file
, op1
);
5753 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5755 addr
= XEXP (addr
, 0);
5756 if (GET_CODE (addr
) == REG
)
5757 basereg
= REGNO (addr
);
5758 else if (GET_CODE (addr
) == SUBREG
5759 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5760 basereg
= subreg_regno (addr
);
5764 fprintf (file
, "($%d)\t\t!%s", basereg
,
5765 (basereg
== 29 ? reloc16
: reloclo
));
5769 if (GET_CODE (addr
) == REG
)
5770 basereg
= REGNO (addr
);
5771 else if (GET_CODE (addr
) == SUBREG
5772 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5773 basereg
= subreg_regno (addr
);
5774 else if (GET_CODE (addr
) == CONST_INT
)
5775 offset
= INTVAL (addr
);
5777 #if TARGET_ABI_OPEN_VMS
5778 else if (GET_CODE (addr
) == SYMBOL_REF
)
5780 fprintf (file
, "%s", XSTR (addr
, 0));
5783 else if (GET_CODE (addr
) == CONST
5784 && GET_CODE (XEXP (addr
, 0)) == PLUS
5785 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5787 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5788 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5789 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5797 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5800 /* Emit RTL insns to initialize the variable parts of a trampoline at
5801 TRAMP. FNADDR is an RTX for the address of the function's pure
5802 code. CXT is an RTX for the static chain value for the function.
5804 The three offset parameters are for the individual template's
5805 layout. A JMPOFS < 0 indicates that the trampoline does not
5806 contain instructions at all.
5808 We assume here that a function will be called many more times than
5809 its address is taken (e.g., it might be passed to qsort), so we
5810 take the trouble to initialize the "hint" field in the JMP insn.
5811 Note that the hint field is PC (new) + 4 * bits 13:0. */
5814 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5815 int fnofs
, int cxtofs
, int jmpofs
)
5817 rtx temp
, temp1
, addr
;
5818 /* VMS really uses DImode pointers in memory at this point. */
5819 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5821 #ifdef POINTERS_EXTEND_UNSIGNED
5822 fnaddr
= convert_memory_address (mode
, fnaddr
);
5823 cxt
= convert_memory_address (mode
, cxt
);
5826 /* Store function address and CXT. */
5827 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5828 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5829 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5830 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5832 /* This has been disabled since the hint only has a 32k range, and in
5833 no existing OS is the stack within 32k of the text segment. */
5834 if (0 && jmpofs
>= 0)
5836 /* Compute hint value. */
5837 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5838 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5840 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5841 build_int_2 (2, 0), NULL_RTX
, 1);
5842 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5843 GEN_INT (0x3fff), 0);
5845 /* Merge in the hint. */
5846 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5847 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5848 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5849 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5851 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5854 #ifdef TRANSFER_FROM_TRAMPOLINE
5855 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5856 0, VOIDmode
, 1, tramp
, Pmode
);
5860 emit_insn (gen_imb ());
5863 /* Determine where to put an argument to a function.
5864 Value is zero to push the argument on the stack,
5865 or a hard register in which to store the argument.
5867 MODE is the argument's machine mode.
5868 TYPE is the data type of the argument (as a tree).
5869 This is null for libcalls where that information may
5871 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5872 the preceding args and about the function being called.
5873 NAMED is nonzero if this argument is a named parameter
5874 (otherwise it is an extra parameter matching an ellipsis).
5876 On Alpha the first 6 words of args are normally in registers
5877 and the rest are pushed. */
5880 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5881 int named ATTRIBUTE_UNUSED
)
5886 /* Don't get confused and pass small structures in FP registers. */
5887 if (type
&& AGGREGATE_TYPE_P (type
))
5891 #ifdef ENABLE_CHECKING
5892 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5894 if (COMPLEX_MODE_P (mode
))
5898 /* Set up defaults for FP operands passed in FP registers, and
5899 integral operands passed in integer registers. */
5900 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5906 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5907 the three platforms, so we can't avoid conditional compilation. */
5908 #if TARGET_ABI_OPEN_VMS
5910 if (mode
== VOIDmode
)
5911 return alpha_arg_info_reg_val (cum
);
5913 num_args
= cum
.num_args
;
5914 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5917 #elif TARGET_ABI_UNICOSMK
5921 /* If this is the last argument, generate the call info word (CIW). */
5922 /* ??? We don't include the caller's line number in the CIW because
5923 I don't know how to determine it if debug infos are turned off. */
5924 if (mode
== VOIDmode
)
5933 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5934 if (cum
.reg_args_type
[i
])
5935 lo
|= (1 << (7 - i
));
5937 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5940 lo
|= cum
.num_reg_words
;
5942 #if HOST_BITS_PER_WIDE_INT == 32
5943 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5945 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5946 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5949 ciw
= immed_double_const (lo
, hi
, DImode
);
5951 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5952 UNSPEC_UMK_LOAD_CIW
);
5955 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5956 num_args
= cum
.num_reg_words
;
5957 if (MUST_PASS_IN_STACK (mode
, type
)
5958 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5960 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5964 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5965 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5967 /* The argument fits in two registers. Note that we still need to
5968 reserve a register for empty structures. */
5972 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5975 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5976 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5977 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5981 #elif TARGET_ABI_OSF
5987 /* VOID is passed as a special flag for "last argument". */
5988 if (type
== void_type_node
)
5990 else if (MUST_PASS_IN_STACK (mode
, type
))
5992 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5996 #error Unhandled ABI
5999 return gen_rtx_REG (mode
, num_args
+ basereg
);
6002 /* Return true if TYPE must be returned in memory, instead of in registers. */
6005 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
6007 enum machine_mode mode
= VOIDmode
;
6012 mode
= TYPE_MODE (type
);
6014 /* All aggregates are returned in memory. */
6015 if (AGGREGATE_TYPE_P (type
))
6019 size
= GET_MODE_SIZE (mode
);
6020 switch (GET_MODE_CLASS (mode
))
6022 case MODE_VECTOR_FLOAT
:
6023 /* Pass all float vectors in memory, like an aggregate. */
6026 case MODE_COMPLEX_FLOAT
:
6027 /* We judge complex floats on the size of their element,
6028 not the size of the whole type. */
6029 size
= GET_MODE_UNIT_SIZE (mode
);
6034 case MODE_COMPLEX_INT
:
6035 case MODE_VECTOR_INT
:
6039 /* ??? We get called on all sorts of random stuff from
6040 aggregate_value_p. We can't abort, but it's not clear
6041 what's safe to return. Pretend it's a struct I guess. */
6045 /* Otherwise types must fit in one register. */
6046 return size
> UNITS_PER_WORD
;
6049 /* Define how to find the value returned by a function. VALTYPE is the
6050 data type of the value (as a tree). If the precise function being
6051 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6052 MODE is set instead of VALTYPE for libcalls.
6054 On Alpha the value is found in $0 for integer functions and
6055 $f0 for floating-point functions. */
6058 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
6059 enum machine_mode mode
)
6061 unsigned int regnum
;
6062 enum mode_class
class;
6064 #ifdef ENABLE_CHECKING
6065 if (valtype
&& alpha_return_in_memory (valtype
, func
))
6070 mode
= TYPE_MODE (valtype
);
6072 class = GET_MODE_CLASS (mode
);
6076 /* Do the same thing as PROMOTE_MODE. */
6080 case MODE_COMPLEX_INT
:
6081 case MODE_VECTOR_INT
:
6089 case MODE_COMPLEX_FLOAT
:
6091 enum machine_mode cmode
= GET_MODE_INNER (mode
);
6093 return gen_rtx_PARALLEL
6096 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
6098 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
6099 GEN_INT (GET_MODE_SIZE (cmode
)))));
6106 return gen_rtx_REG (mode
, regnum
);
6109 /* TCmode complex values are passed by invisible reference. We
6110 should not split these values. */
6113 alpha_split_complex_arg (tree type
)
6115 return TYPE_MODE (type
) != TCmode
;
6119 alpha_build_builtin_va_list (void)
6121 tree base
, ofs
, space
, record
, type_decl
;
6123 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6124 return ptr_type_node
;
6126 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6127 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6128 TREE_CHAIN (record
) = type_decl
;
6129 TYPE_NAME (record
) = type_decl
;
6131 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6133 /* Dummy field to prevent alignment warnings. */
6134 space
= build_decl (FIELD_DECL
, NULL_TREE
, integer_type_node
);
6135 DECL_FIELD_CONTEXT (space
) = record
;
6136 DECL_ARTIFICIAL (space
) = 1;
6137 DECL_IGNORED_P (space
) = 1;
6139 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6141 DECL_FIELD_CONTEXT (ofs
) = record
;
6142 TREE_CHAIN (ofs
) = space
;
6144 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6146 DECL_FIELD_CONTEXT (base
) = record
;
6147 TREE_CHAIN (base
) = ofs
;
6149 TYPE_FIELDS (record
) = base
;
6150 layout_type (record
);
6155 /* Perform any needed actions needed for a function that is receiving a
6156 variable number of arguments. */
6159 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
,
6160 enum machine_mode mode ATTRIBUTE_UNUSED
,
6161 tree type ATTRIBUTE_UNUSED
,
6162 int *pretend_size
, int no_rtl
)
6164 #if TARGET_ABI_UNICOSMK
6165 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6166 arguments on the stack. Unfortunately, it doesn't always store the first
6167 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6168 with stdargs as we always have at least one named argument there. */
6169 int num_reg_words
= pcum
->num_reg_words
;
6170 if (num_reg_words
< 6)
6174 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words
+ 1)));
6175 emit_insn (gen_arg_home_umk ());
6179 #elif TARGET_ABI_OPEN_VMS
6180 /* For VMS, we allocate space for all 6 arg registers plus a count.
6182 However, if NO registers need to be saved, don't allocate any space.
6183 This is not only because we won't need the space, but because AP
6184 includes the current_pretend_args_size and we don't want to mess up
6185 any ap-relative addresses already made. */
6186 if (pcum
->num_args
< 6)
6190 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6191 emit_insn (gen_arg_home ());
6193 *pretend_size
= 7 * UNITS_PER_WORD
;
6196 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6197 only push those that are remaining. However, if NO registers need to
6198 be saved, don't allocate any space. This is not only because we won't
6199 need the space, but because AP includes the current_pretend_args_size
6200 and we don't want to mess up any ap-relative addresses already made.
6202 If we are not to use the floating-point registers, save the integer
6203 registers where we would put the floating-point registers. This is
6204 not the most efficient way to implement varargs with just one register
6205 class, but it isn't worth doing anything more efficient in this rare
6207 CUMULATIVE_ARGS cum
= *pcum
;
6214 int set
= get_varargs_alias_set ();
6217 tmp
= gen_rtx_MEM (BLKmode
,
6218 plus_constant (virtual_incoming_args_rtx
,
6219 (cum
+ 6) * UNITS_PER_WORD
));
6220 set_mem_alias_set (tmp
, set
);
6221 move_block_from_reg (16 + cum
, tmp
, 6 - cum
);
6223 tmp
= gen_rtx_MEM (BLKmode
,
6224 plus_constant (virtual_incoming_args_rtx
,
6225 cum
* UNITS_PER_WORD
));
6226 set_mem_alias_set (tmp
, set
);
6227 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
6230 *pretend_size
= 12 * UNITS_PER_WORD
;
6235 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6237 HOST_WIDE_INT offset
;
6238 tree t
, offset_field
, base_field
;
6240 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6243 if (TARGET_ABI_UNICOSMK
)
6244 std_expand_builtin_va_start (valist
, nextarg
);
6246 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6247 up by 48, storing fp arg registers in the first 48 bytes, and the
6248 integer arg registers in the next 48 bytes. This is only done,
6249 however, if any integer registers need to be stored.
6251 If no integer registers need be stored, then we must subtract 48
6252 in order to account for the integer arg registers which are counted
6253 in argsize above, but which are not actually stored on the stack.
6254 Must further be careful here about structures straddling the last
6255 integer argument register; that futzes with pretend_args_size,
6256 which changes the meaning of AP. */
6259 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6261 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6263 if (TARGET_ABI_OPEN_VMS
)
6265 nextarg
= plus_constant (nextarg
, offset
);
6266 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6267 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6268 make_tree (ptr_type_node
, nextarg
));
6269 TREE_SIDE_EFFECTS (t
) = 1;
6271 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6275 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6276 offset_field
= TREE_CHAIN (base_field
);
6278 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6279 valist
, base_field
);
6280 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6281 valist
, offset_field
);
6283 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6284 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6285 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6286 TREE_SIDE_EFFECTS (t
) = 1;
6287 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6289 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6290 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6291 TREE_SIDE_EFFECTS (t
) = 1;
6292 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6297 alpha_va_arg (tree valist
, tree type
)
6300 tree t
, type_size
, rounded_size
;
6301 tree offset_field
, base_field
, addr_tree
, addend
;
6302 tree wide_type
, wide_ofs
;
6305 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6306 return std_expand_builtin_va_arg (valist
, type
);
6308 if (type
== error_mark_node
6309 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6310 || TREE_OVERFLOW (type_size
))
6311 rounded_size
= size_zero_node
;
6313 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6314 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6315 fold (build (PLUS_EXPR
, sizetype
,
6321 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6322 offset_field
= TREE_CHAIN (base_field
);
6324 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6325 valist
, base_field
);
6326 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6327 valist
, offset_field
);
6329 /* If the type could not be passed in registers, skip the block
6330 reserved for the registers. */
6331 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6333 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6334 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6335 offset_field
, build_int_2 (6*8, 0)));
6336 TREE_SIDE_EFFECTS (t
) = 1;
6337 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6340 wide_type
= make_signed_type (64);
6341 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6345 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6348 rounded_size
= size_int (UNITS_PER_WORD
);
6350 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
6352 rtx real_part
, imag_part
, value
, tmp
;
6354 real_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6355 imag_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6357 /* ??? Most irritatingly, we're not returning the value here,
6358 but the address. Since real_part and imag_part are not
6359 necessarily contiguous, we must copy to local storage. */
6361 real_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), real_part
);
6362 imag_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), imag_part
);
6363 value
= gen_rtx_CONCAT (TYPE_MODE (type
), real_part
, imag_part
);
6365 tmp
= assign_temp (type
, 0, 1, 0);
6366 emit_move_insn (tmp
, value
);
6368 return XEXP (tmp
, 0);
6370 else if (TREE_CODE (type
) == REAL_TYPE
)
6372 tree fpaddend
, cond
;
6374 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6375 addend
, build_int_2 (-6*8, 0)));
6377 cond
= fold (build (LT_EXPR
, integer_type_node
,
6378 wide_ofs
, build_int_2 (6*8, 0)));
6380 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6384 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6385 base_field
, addend
);
6387 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6388 addr
= copy_to_reg (addr
);
6390 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6391 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6392 offset_field
, rounded_size
));
6393 TREE_SIDE_EFFECTS (t
) = 1;
6394 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6398 addr
= force_reg (Pmode
, addr
);
6399 addr
= gen_rtx_MEM (Pmode
, addr
);
6409 ALPHA_BUILTIN_CMPBGE
,
6410 ALPHA_BUILTIN_EXTBL
,
6411 ALPHA_BUILTIN_EXTWL
,
6412 ALPHA_BUILTIN_EXTLL
,
6413 ALPHA_BUILTIN_EXTQL
,
6414 ALPHA_BUILTIN_EXTWH
,
6415 ALPHA_BUILTIN_EXTLH
,
6416 ALPHA_BUILTIN_EXTQH
,
6417 ALPHA_BUILTIN_INSBL
,
6418 ALPHA_BUILTIN_INSWL
,
6419 ALPHA_BUILTIN_INSLL
,
6420 ALPHA_BUILTIN_INSQL
,
6421 ALPHA_BUILTIN_INSWH
,
6422 ALPHA_BUILTIN_INSLH
,
6423 ALPHA_BUILTIN_INSQH
,
6424 ALPHA_BUILTIN_MSKBL
,
6425 ALPHA_BUILTIN_MSKWL
,
6426 ALPHA_BUILTIN_MSKLL
,
6427 ALPHA_BUILTIN_MSKQL
,
6428 ALPHA_BUILTIN_MSKWH
,
6429 ALPHA_BUILTIN_MSKLH
,
6430 ALPHA_BUILTIN_MSKQH
,
6431 ALPHA_BUILTIN_UMULH
,
6433 ALPHA_BUILTIN_ZAPNOT
,
6434 ALPHA_BUILTIN_AMASK
,
6435 ALPHA_BUILTIN_IMPLVER
,
6437 ALPHA_BUILTIN_THREAD_POINTER
,
6438 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6441 ALPHA_BUILTIN_MINUB8
,
6442 ALPHA_BUILTIN_MINSB8
,
6443 ALPHA_BUILTIN_MINUW4
,
6444 ALPHA_BUILTIN_MINSW4
,
6445 ALPHA_BUILTIN_MAXUB8
,
6446 ALPHA_BUILTIN_MAXSB8
,
6447 ALPHA_BUILTIN_MAXUW4
,
6448 ALPHA_BUILTIN_MAXSW4
,
6452 ALPHA_BUILTIN_UNPKBL
,
6453 ALPHA_BUILTIN_UNPKBW
,
6458 ALPHA_BUILTIN_CTPOP
,
6463 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6464 CODE_FOR_builtin_cmpbge
,
6465 CODE_FOR_builtin_extbl
,
6466 CODE_FOR_builtin_extwl
,
6467 CODE_FOR_builtin_extll
,
6468 CODE_FOR_builtin_extql
,
6469 CODE_FOR_builtin_extwh
,
6470 CODE_FOR_builtin_extlh
,
6471 CODE_FOR_builtin_extqh
,
6472 CODE_FOR_builtin_insbl
,
6473 CODE_FOR_builtin_inswl
,
6474 CODE_FOR_builtin_insll
,
6475 CODE_FOR_builtin_insql
,
6476 CODE_FOR_builtin_inswh
,
6477 CODE_FOR_builtin_inslh
,
6478 CODE_FOR_builtin_insqh
,
6479 CODE_FOR_builtin_mskbl
,
6480 CODE_FOR_builtin_mskwl
,
6481 CODE_FOR_builtin_mskll
,
6482 CODE_FOR_builtin_mskql
,
6483 CODE_FOR_builtin_mskwh
,
6484 CODE_FOR_builtin_msklh
,
6485 CODE_FOR_builtin_mskqh
,
6486 CODE_FOR_umuldi3_highpart
,
6487 CODE_FOR_builtin_zap
,
6488 CODE_FOR_builtin_zapnot
,
6489 CODE_FOR_builtin_amask
,
6490 CODE_FOR_builtin_implver
,
6491 CODE_FOR_builtin_rpcc
,
6496 CODE_FOR_builtin_minub8
,
6497 CODE_FOR_builtin_minsb8
,
6498 CODE_FOR_builtin_minuw4
,
6499 CODE_FOR_builtin_minsw4
,
6500 CODE_FOR_builtin_maxub8
,
6501 CODE_FOR_builtin_maxsb8
,
6502 CODE_FOR_builtin_maxuw4
,
6503 CODE_FOR_builtin_maxsw4
,
6504 CODE_FOR_builtin_perr
,
6505 CODE_FOR_builtin_pklb
,
6506 CODE_FOR_builtin_pkwb
,
6507 CODE_FOR_builtin_unpkbl
,
6508 CODE_FOR_builtin_unpkbw
,
6511 CODE_FOR_builtin_cttz
,
6512 CODE_FOR_builtin_ctlz
,
6513 CODE_FOR_builtin_ctpop
6516 struct alpha_builtin_def
6519 enum alpha_builtin code
;
6520 unsigned int target_mask
;
6523 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6524 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6525 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6528 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6529 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6530 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6531 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6532 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6533 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6534 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6535 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6536 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6539 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6540 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6541 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6542 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6543 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6544 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6545 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6546 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6547 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6548 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6549 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6550 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6551 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6552 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6553 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6554 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6555 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6556 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6557 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6558 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6559 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6560 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6561 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6562 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6563 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6564 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6565 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6566 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6567 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6568 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6569 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6570 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6571 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6572 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6573 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6577 alpha_init_builtins (void)
6579 const struct alpha_builtin_def
*p
;
6583 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6585 p
= zero_arg_builtins
;
6586 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6587 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6588 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6591 ftype
= build_function_type_list (long_integer_type_node
,
6592 long_integer_type_node
, NULL_TREE
);
6594 p
= one_arg_builtins
;
6595 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6596 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6597 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6600 ftype
= build_function_type_list (long_integer_type_node
,
6601 long_integer_type_node
,
6602 long_integer_type_node
, NULL_TREE
);
6604 p
= two_arg_builtins
;
6605 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6606 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6607 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6610 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6611 builtin_function ("__builtin_thread_pointer", ftype
,
6612 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6615 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6616 builtin_function ("__builtin_set_thread_pointer", ftype
,
6617 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6621 /* Expand an expression EXP that calls a built-in function,
6622 with result going to TARGET if that's convenient
6623 (and in mode MODE if that's convenient).
6624 SUBTARGET may be used as the target for computing one of EXP's operands.
6625 IGNORE is nonzero if the value is to be ignored. */
6628 alpha_expand_builtin (tree exp
, rtx target
,
6629 rtx subtarget ATTRIBUTE_UNUSED
,
6630 enum machine_mode mode ATTRIBUTE_UNUSED
,
6631 int ignore ATTRIBUTE_UNUSED
)
6635 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6636 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6637 tree arglist
= TREE_OPERAND (exp
, 1);
6638 enum insn_code icode
;
6639 rtx op
[MAX_ARGS
], pat
;
6643 if (fcode
>= ALPHA_BUILTIN_max
)
6644 internal_error ("bad builtin fcode");
6645 icode
= code_for_builtin
[fcode
];
6647 internal_error ("bad builtin fcode");
6649 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6651 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6653 arglist
= TREE_CHAIN (arglist
), arity
++)
6655 const struct insn_operand_data
*insn_op
;
6657 tree arg
= TREE_VALUE (arglist
);
6658 if (arg
== error_mark_node
)
6660 if (arity
> MAX_ARGS
)
6663 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6665 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6667 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6668 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6673 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6675 || GET_MODE (target
) != tmode
6676 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6677 target
= gen_reg_rtx (tmode
);
6683 pat
= GEN_FCN (icode
) (target
);
6687 pat
= GEN_FCN (icode
) (target
, op
[0]);
6689 pat
= GEN_FCN (icode
) (op
[0]);
6692 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6707 /* This page contains routines that are used to determine what the function
6708 prologue and epilogue code will do and write them out. */
6710 /* Compute the size of the save area in the stack. */
6712 /* These variables are used for communication between the following functions.
6713 They indicate various things about the current function being compiled
6714 that are used to tell what kind of prologue, epilogue and procedure
6715 descriptor to generate. */
6717 /* Nonzero if we need a stack procedure. */
6718 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6719 static enum alpha_procedure_types alpha_procedure_type
;
6721 /* Register number (either FP or SP) that is used to unwind the frame. */
6722 static int vms_unwind_regno
;
6724 /* Register number used to save FP. We need not have one for RA since
6725 we don't modify it for register procedures. This is only defined
6726 for register frame procedures. */
6727 static int vms_save_fp_regno
;
6729 /* Register number used to reference objects off our PV. */
6730 static int vms_base_regno
;
6732 /* Compute register masks for saved registers. */
6735 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
6737 unsigned long imask
= 0;
6738 unsigned long fmask
= 0;
6741 /* When outputting a thunk, we don't have valid register life info,
6742 but assemble_start_function wants to output .frame and .mask
6744 if (current_function_is_thunk
)
6751 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6752 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6754 /* One for every register we have to save. */
6755 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6756 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6757 && regs_ever_live
[i
] && i
!= REG_RA
6758 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6761 imask
|= (1UL << i
);
6763 fmask
|= (1UL << (i
- 32));
6766 /* We need to restore these for the handler. */
6767 if (current_function_calls_eh_return
)
6771 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6772 if (regno
== INVALID_REGNUM
)
6774 imask
|= 1UL << regno
;
6777 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6778 avoid hackery in unwind-dw2.c, we need to actively store a
6779 zero in the prologue of _Unwind_RaiseException et al. */
6783 /* If any register spilled, then spill the return address also. */
6784 /* ??? This is required by the Digital stack unwind specification
6785 and isn't needed if we're doing Dwarf2 unwinding. */
6786 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6787 imask
|= (1UL << REG_RA
);
6794 alpha_sa_size (void)
6796 unsigned long mask
[2];
6800 alpha_sa_mask (&mask
[0], &mask
[1]);
6802 if (TARGET_ABI_UNICOSMK
)
6804 if (mask
[0] || mask
[1])
6809 for (j
= 0; j
< 2; ++j
)
6810 for (i
= 0; i
< 32; ++i
)
6811 if ((mask
[j
] >> i
) & 1)
6815 if (TARGET_ABI_UNICOSMK
)
6817 /* We might not need to generate a frame if we don't make any calls
6818 (including calls to __T3E_MISMATCH if this is a vararg function),
6819 don't have any local variables which require stack slots, don't
6820 use alloca and have not determined that we need a frame for other
6823 alpha_procedure_type
6824 = (sa_size
|| get_frame_size() != 0
6825 || current_function_outgoing_args_size
6826 || current_function_stdarg
|| current_function_calls_alloca
6827 || frame_pointer_needed
)
6828 ? PT_STACK
: PT_REGISTER
;
6830 /* Always reserve space for saving callee-saved registers if we
6831 need a frame as required by the calling convention. */
6832 if (alpha_procedure_type
== PT_STACK
)
6835 else if (TARGET_ABI_OPEN_VMS
)
6837 /* Start by assuming we can use a register procedure if we don't
6838 make any calls (REG_RA not used) or need to save any
6839 registers and a stack procedure if we do. */
6840 if ((mask
[0] >> REG_RA
) & 1)
6841 alpha_procedure_type
= PT_STACK
;
6842 else if (get_frame_size() != 0)
6843 alpha_procedure_type
= PT_REGISTER
;
6845 alpha_procedure_type
= PT_NULL
;
6847 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6848 made the final decision on stack procedure vs register procedure. */
6849 if (alpha_procedure_type
== PT_STACK
)
6852 /* Decide whether to refer to objects off our PV via FP or PV.
6853 If we need FP for something else or if we receive a nonlocal
6854 goto (which expects PV to contain the value), we must use PV.
6855 Otherwise, start by assuming we can use FP. */
6858 = (frame_pointer_needed
6859 || current_function_has_nonlocal_label
6860 || alpha_procedure_type
== PT_STACK
6861 || current_function_outgoing_args_size
)
6862 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6864 /* If we want to copy PV into FP, we need to find some register
6865 in which to save FP. */
6867 vms_save_fp_regno
= -1;
6868 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6869 for (i
= 0; i
< 32; i
++)
6870 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6871 vms_save_fp_regno
= i
;
6873 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6874 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6875 else if (alpha_procedure_type
== PT_NULL
)
6876 vms_base_regno
= REG_PV
;
6878 /* Stack unwinding should be done via FP unless we use it for PV. */
6879 vms_unwind_regno
= (vms_base_regno
== REG_PV
6880 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6882 /* If this is a stack procedure, allow space for saving FP and RA. */
6883 if (alpha_procedure_type
== PT_STACK
)
6888 /* Our size must be even (multiple of 16 bytes). */
6896 /* Define the offset between two registers, one to be eliminated,
6897 and the other its replacement, at the start of a routine. */
6900 alpha_initial_elimination_offset (unsigned int from
,
6901 unsigned int to ATTRIBUTE_UNUSED
)
6905 ret
= alpha_sa_size ();
6906 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
6908 if (from
== FRAME_POINTER_REGNUM
)
6910 else if (from
== ARG_POINTER_REGNUM
)
6911 ret
+= (ALPHA_ROUND (get_frame_size ()
6912 + current_function_pretend_args_size
)
6913 - current_function_pretend_args_size
);
6921 alpha_pv_save_size (void)
6924 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6928 alpha_using_fp (void)
6931 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6934 #if TARGET_ABI_OPEN_VMS
6936 const struct attribute_spec vms_attribute_table
[] =
6938 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6939 { "overlaid", 0, 0, true, false, false, NULL
},
6940 { "global", 0, 0, true, false, false, NULL
},
6941 { "initialize", 0, 0, true, false, false, NULL
},
6942 { NULL
, 0, 0, false, false, false, NULL
}
6948 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6950 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
6954 alpha_find_lo_sum_using_gp (rtx insn
)
6956 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
6960 alpha_does_function_need_gp (void)
6964 /* The GP being variable is an OSF abi thing. */
6965 if (! TARGET_ABI_OSF
)
6968 /* We need the gp to load the address of __mcount. */
6969 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6972 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6973 if (current_function_is_thunk
)
6976 /* The nonlocal receiver pattern assumes that the gp is valid for
6977 the nested function. Reasonable because it's almost always set
6978 correctly already. For the cases where that's wrong, make sure
6979 the nested function loads its gp on entry. */
6980 if (current_function_has_nonlocal_goto
)
6983 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6984 Even if we are a static function, we still need to do this in case
6985 our address is taken and passed to something like qsort. */
6987 push_topmost_sequence ();
6988 insn
= get_insns ();
6989 pop_topmost_sequence ();
6991 for (; insn
; insn
= NEXT_INSN (insn
))
6993 && GET_CODE (PATTERN (insn
)) != USE
6994 && GET_CODE (PATTERN (insn
)) != CLOBBER
6995 && get_attr_usegp (insn
))
7002 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7006 set_frame_related_p (void)
7008 rtx seq
= get_insns ();
7019 while (insn
!= NULL_RTX
)
7021 RTX_FRAME_RELATED_P (insn
) = 1;
7022 insn
= NEXT_INSN (insn
);
7024 seq
= emit_insn (seq
);
7028 seq
= emit_insn (seq
);
7029 RTX_FRAME_RELATED_P (seq
) = 1;
7034 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7036 /* Write function prologue. */
7038 /* On vms we have two kinds of functions:
7040 - stack frame (PROC_STACK)
7041 these are 'normal' functions with local vars and which are
7042 calling other functions
7043 - register frame (PROC_REGISTER)
7044 keeps all data in registers, needs no stack
7046 We must pass this to the assembler so it can generate the
7047 proper pdsc (procedure descriptor)
7048 This is done with the '.pdesc' command.
7050 On not-vms, we don't really differentiate between the two, as we can
7051 simply allocate stack without saving registers. */
7054 alpha_expand_prologue (void)
7056 /* Registers to save. */
7057 unsigned long imask
= 0;
7058 unsigned long fmask
= 0;
7059 /* Stack space needed for pushing registers clobbered by us. */
7060 HOST_WIDE_INT sa_size
;
7061 /* Complete stack size needed. */
7062 HOST_WIDE_INT frame_size
;
7063 /* Offset from base reg to register save area. */
7064 HOST_WIDE_INT reg_offset
;
7068 sa_size
= alpha_sa_size ();
7070 frame_size
= get_frame_size ();
7071 if (TARGET_ABI_OPEN_VMS
)
7072 frame_size
= ALPHA_ROUND (sa_size
7073 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7075 + current_function_pretend_args_size
);
7076 else if (TARGET_ABI_UNICOSMK
)
7077 /* We have to allocate space for the DSIB if we generate a frame. */
7078 frame_size
= ALPHA_ROUND (sa_size
7079 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7080 + ALPHA_ROUND (frame_size
7081 + current_function_outgoing_args_size
);
7083 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7085 + ALPHA_ROUND (frame_size
7086 + current_function_pretend_args_size
));
7088 if (TARGET_ABI_OPEN_VMS
)
7091 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7093 alpha_sa_mask (&imask
, &fmask
);
7095 /* Emit an insn to reload GP, if needed. */
7098 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7099 if (alpha_function_needs_gp
)
7100 emit_insn (gen_prologue_ldgp ());
7103 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7104 the call to mcount ourselves, rather than having the linker do it
7105 magically in response to -pg. Since _mcount has special linkage,
7106 don't represent the call as a call. */
7107 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7108 emit_insn (gen_prologue_mcount ());
7110 if (TARGET_ABI_UNICOSMK
)
7111 unicosmk_gen_dsib (&imask
);
7113 /* Adjust the stack by the frame size. If the frame size is > 4096
7114 bytes, we need to be sure we probe somewhere in the first and last
7115 4096 bytes (we can probably get away without the latter test) and
7116 every 8192 bytes in between. If the frame size is > 32768, we
7117 do this in a loop. Otherwise, we generate the explicit probe
7120 Note that we are only allowed to adjust sp once in the prologue. */
7122 if (frame_size
<= 32768)
7124 if (frame_size
> 4096)
7129 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7132 while ((probed
+= 8192) < frame_size
);
7134 /* We only have to do this probe if we aren't saving registers. */
7135 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7136 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7139 if (frame_size
!= 0)
7140 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7141 GEN_INT (TARGET_ABI_UNICOSMK
7147 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7148 number of 8192 byte blocks to probe. We then probe each block
7149 in the loop and then set SP to the proper location. If the
7150 amount remaining is > 4096, we have to do one more probe if we
7151 are not saving any registers. */
7153 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7154 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7155 rtx ptr
= gen_rtx_REG (DImode
, 22);
7156 rtx count
= gen_rtx_REG (DImode
, 23);
7159 emit_move_insn (count
, GEN_INT (blocks
));
7160 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7161 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7163 /* Because of the difficulty in emitting a new basic block this
7164 late in the compilation, generate the loop as a single insn. */
7165 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7167 if (leftover
> 4096 && sa_size
== 0)
7169 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7170 MEM_VOLATILE_P (last
) = 1;
7171 emit_move_insn (last
, const0_rtx
);
7174 if (TARGET_ABI_WINDOWS_NT
)
7176 /* For NT stack unwind (done by 'reverse execution'), it's
7177 not OK to take the result of a loop, even though the value
7178 is already in ptr, so we reload it via a single operation
7179 and subtract it to sp.
7181 Yes, that's correct -- we have to reload the whole constant
7182 into a temporary via ldah+lda then subtract from sp. */
7184 HOST_WIDE_INT lo
, hi
;
7185 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7186 hi
= frame_size
- lo
;
7188 emit_move_insn (ptr
, GEN_INT (hi
));
7189 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7190 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7195 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7196 GEN_INT (-leftover
)));
7199 /* This alternative is special, because the DWARF code cannot
7200 possibly intuit through the loop above. So we invent this
7201 note it looks at instead. */
7202 RTX_FRAME_RELATED_P (seq
) = 1;
7204 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7205 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7206 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7207 GEN_INT (TARGET_ABI_UNICOSMK
7213 if (!TARGET_ABI_UNICOSMK
)
7215 /* Cope with very large offsets to the register save area. */
7216 sa_reg
= stack_pointer_rtx
;
7217 if (reg_offset
+ sa_size
> 0x8000)
7219 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7222 if (low
+ sa_size
<= 0x8000)
7223 bias
= reg_offset
- low
, reg_offset
= low
;
7225 bias
= reg_offset
, reg_offset
= 0;
7227 sa_reg
= gen_rtx_REG (DImode
, 24);
7228 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7232 /* Save regs in stack order. Beginning with VMS PV. */
7233 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7235 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7236 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7237 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7240 /* Save register RA next. */
7241 if (imask
& (1UL << REG_RA
))
7243 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7244 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7245 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7246 imask
&= ~(1UL << REG_RA
);
7250 /* Now save any other registers required to be saved. */
7251 for (i
= 0; i
< 31; i
++)
7252 if (imask
& (1UL << i
))
7254 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7255 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7256 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7260 /* Store a zero if requested for unwinding. */
7261 if (imask
& (1UL << 31))
7265 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7266 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7267 insn
= emit_move_insn (mem
, const0_rtx
);
7269 RTX_FRAME_RELATED_P (insn
) = 1;
7270 t
= gen_rtx_REG (Pmode
, 31);
7271 t
= gen_rtx_SET (VOIDmode
, mem
, t
);
7272 t
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, t
, REG_NOTES (insn
));
7273 REG_NOTES (insn
) = t
;
7278 for (i
= 0; i
< 31; i
++)
7279 if (fmask
& (1UL << i
))
7281 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7282 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7283 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7287 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7289 /* The standard frame on the T3E includes space for saving registers.
7290 We just have to use it. We don't have to save the return address and
7291 the old frame pointer here - they are saved in the DSIB. */
7294 for (i
= 9; i
< 15; i
++)
7295 if (imask
& (1UL << i
))
7297 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7299 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7300 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7303 for (i
= 2; i
< 10; i
++)
7304 if (fmask
& (1UL << i
))
7306 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7308 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7309 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7314 if (TARGET_ABI_OPEN_VMS
)
7316 if (alpha_procedure_type
== PT_REGISTER
)
7317 /* Register frame procedures save the fp.
7318 ?? Ought to have a dwarf2 save for this. */
7319 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7320 hard_frame_pointer_rtx
);
7322 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7323 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7324 gen_rtx_REG (DImode
, REG_PV
)));
7326 if (alpha_procedure_type
!= PT_NULL
7327 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7328 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7330 /* If we have to allocate space for outgoing args, do it now. */
7331 if (current_function_outgoing_args_size
!= 0)
7334 = emit_move_insn (stack_pointer_rtx
,
7336 (hard_frame_pointer_rtx
,
7338 (current_function_outgoing_args_size
))));
7340 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7341 if ! frame_pointer_needed. Setting the bit will change the CFA
7342 computation rule to use sp again, which would be wrong if we had
7343 frame_pointer_needed, as this means sp might move unpredictably
7347 frame_pointer_needed
7348 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7350 current_function_outgoing_args_size != 0
7351 => alpha_procedure_type != PT_NULL,
7353 so when we are not setting the bit here, we are guaranteed to
7354 have emitted an FRP frame pointer update just before. */
7355 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7358 else if (!TARGET_ABI_UNICOSMK
)
7360 /* If we need a frame pointer, set it from the stack pointer. */
7361 if (frame_pointer_needed
)
7363 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7364 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7366 /* This must always be the last instruction in the
7367 prologue, thus we emit a special move + clobber. */
7368 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7369 stack_pointer_rtx
, sa_reg
)));
7373 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7374 the prologue, for exception handling reasons, we cannot do this for
7375 any insn that might fault. We could prevent this for mems with a
7376 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7377 have to prevent all such scheduling with a blockage.
7379 Linux, on the other hand, never bothered to implement OSF/1's
7380 exception handling, and so doesn't care about such things. Anyone
7381 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7383 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7384 emit_insn (gen_blockage ());
7387 /* Output the textual info surrounding the prologue. */
7390 alpha_start_function (FILE *file
, const char *fnname
,
7391 tree decl ATTRIBUTE_UNUSED
)
7393 unsigned long imask
= 0;
7394 unsigned long fmask
= 0;
7395 /* Stack space needed for pushing registers clobbered by us. */
7396 HOST_WIDE_INT sa_size
;
7397 /* Complete stack size needed. */
7398 unsigned HOST_WIDE_INT frame_size
;
7399 /* Offset from base reg to register save area. */
7400 HOST_WIDE_INT reg_offset
;
7401 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7404 /* Don't emit an extern directive for functions defined in the same file. */
7405 if (TARGET_ABI_UNICOSMK
)
7408 name_tree
= get_identifier (fnname
);
7409 TREE_ASM_WRITTEN (name_tree
) = 1;
7412 alpha_fnname
= fnname
;
7413 sa_size
= alpha_sa_size ();
7415 frame_size
= get_frame_size ();
7416 if (TARGET_ABI_OPEN_VMS
)
7417 frame_size
= ALPHA_ROUND (sa_size
7418 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7420 + current_function_pretend_args_size
);
7421 else if (TARGET_ABI_UNICOSMK
)
7422 frame_size
= ALPHA_ROUND (sa_size
7423 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7424 + ALPHA_ROUND (frame_size
7425 + current_function_outgoing_args_size
);
7427 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7429 + ALPHA_ROUND (frame_size
7430 + current_function_pretend_args_size
));
7432 if (TARGET_ABI_OPEN_VMS
)
7435 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7437 alpha_sa_mask (&imask
, &fmask
);
7439 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7440 We have to do that before the .ent directive as we cannot switch
7441 files within procedures with native ecoff because line numbers are
7442 linked to procedure descriptors.
7443 Outputting the lineno helps debugging of one line functions as they
7444 would otherwise get no line number at all. Please note that we would
7445 like to put out last_linenum from final.c, but it is not accessible. */
7447 if (write_symbols
== SDB_DEBUG
)
7449 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7450 ASM_OUTPUT_SOURCE_FILENAME (file
,
7451 DECL_SOURCE_FILE (current_function_decl
));
7453 #ifdef ASM_OUTPUT_SOURCE_LINE
7454 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7455 ASM_OUTPUT_SOURCE_LINE (file
,
7456 DECL_SOURCE_LINE (current_function_decl
), 0);
7460 /* Issue function start and label. */
7461 if (TARGET_ABI_OPEN_VMS
7462 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7464 fputs ("\t.ent ", file
);
7465 assemble_name (file
, fnname
);
7468 /* If the function needs GP, we'll write the "..ng" label there.
7469 Otherwise, do it here. */
7471 && ! alpha_function_needs_gp
7472 && ! current_function_is_thunk
)
7475 assemble_name (file
, fnname
);
7476 fputs ("..ng:\n", file
);
7480 strcpy (entry_label
, fnname
);
7481 if (TARGET_ABI_OPEN_VMS
)
7482 strcat (entry_label
, "..en");
7484 /* For public functions, the label must be globalized by appending an
7485 additional colon. */
7486 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7487 strcat (entry_label
, ":");
7489 ASM_OUTPUT_LABEL (file
, entry_label
);
7490 inside_function
= TRUE
;
7492 if (TARGET_ABI_OPEN_VMS
)
7493 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7495 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7496 && !flag_inhibit_size_directive
)
7498 /* Set flags in procedure descriptor to request IEEE-conformant
7499 math-library routines. The value we set it to is PDSC_EXC_IEEE
7500 (/usr/include/pdsc.h). */
7501 fputs ("\t.eflag 48\n", file
);
7504 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7505 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7506 alpha_arg_offset
= -frame_size
+ 48;
7508 /* Describe our frame. If the frame size is larger than an integer,
7509 print it as zero to avoid an assembler error. We won't be
7510 properly describing such a frame, but that's the best we can do. */
7511 if (TARGET_ABI_UNICOSMK
)
7513 else if (TARGET_ABI_OPEN_VMS
)
7514 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7515 HOST_WIDE_INT_PRINT_DEC
"\n",
7517 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7519 else if (!flag_inhibit_size_directive
)
7520 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7521 (frame_pointer_needed
7522 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7523 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7524 current_function_pretend_args_size
);
7526 /* Describe which registers were spilled. */
7527 if (TARGET_ABI_UNICOSMK
)
7529 else if (TARGET_ABI_OPEN_VMS
)
7532 /* ??? Does VMS care if mask contains ra? The old code didn't
7533 set it, so I don't here. */
7534 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7536 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7537 if (alpha_procedure_type
== PT_REGISTER
)
7538 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7540 else if (!flag_inhibit_size_directive
)
7544 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7545 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7547 for (i
= 0; i
< 32; ++i
)
7548 if (imask
& (1UL << i
))
7553 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7554 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7557 #if TARGET_ABI_OPEN_VMS
7558 /* Ifdef'ed cause link_section are only available then. */
7559 readonly_data_section ();
7560 fprintf (file
, "\t.align 3\n");
7561 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7562 fputs ("\t.ascii \"", file
);
7563 assemble_name (file
, fnname
);
7564 fputs ("\\0\"\n", file
);
7565 alpha_need_linkage (fnname
, 1);
7570 /* Emit the .prologue note at the scheduled end of the prologue. */
7573 alpha_output_function_end_prologue (FILE *file
)
7575 if (TARGET_ABI_UNICOSMK
)
7577 else if (TARGET_ABI_OPEN_VMS
)
7578 fputs ("\t.prologue\n", file
);
7579 else if (TARGET_ABI_WINDOWS_NT
)
7580 fputs ("\t.prologue 0\n", file
);
7581 else if (!flag_inhibit_size_directive
)
7582 fprintf (file
, "\t.prologue %d\n",
7583 alpha_function_needs_gp
|| current_function_is_thunk
);
7586 /* Write function epilogue. */
7588 /* ??? At some point we will want to support full unwind, and so will
7589 need to mark the epilogue as well. At the moment, we just confuse
7592 #define FRP(exp) exp
7595 alpha_expand_epilogue (void)
7597 /* Registers to save. */
7598 unsigned long imask
= 0;
7599 unsigned long fmask
= 0;
7600 /* Stack space needed for pushing registers clobbered by us. */
7601 HOST_WIDE_INT sa_size
;
7602 /* Complete stack size needed. */
7603 HOST_WIDE_INT frame_size
;
7604 /* Offset from base reg to register save area. */
7605 HOST_WIDE_INT reg_offset
;
7606 int fp_is_frame_pointer
, fp_offset
;
7607 rtx sa_reg
, sa_reg_exp
= NULL
;
7608 rtx sp_adj1
, sp_adj2
, mem
;
7612 sa_size
= alpha_sa_size ();
7614 frame_size
= get_frame_size ();
7615 if (TARGET_ABI_OPEN_VMS
)
7616 frame_size
= ALPHA_ROUND (sa_size
7617 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7619 + current_function_pretend_args_size
);
7620 else if (TARGET_ABI_UNICOSMK
)
7621 frame_size
= ALPHA_ROUND (sa_size
7622 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7623 + ALPHA_ROUND (frame_size
7624 + current_function_outgoing_args_size
);
7626 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7628 + ALPHA_ROUND (frame_size
7629 + current_function_pretend_args_size
));
7631 if (TARGET_ABI_OPEN_VMS
)
7633 if (alpha_procedure_type
== PT_STACK
)
7639 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7641 alpha_sa_mask (&imask
, &fmask
);
7644 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7645 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7647 sa_reg
= stack_pointer_rtx
;
7649 if (current_function_calls_eh_return
)
7650 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7654 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7656 /* If we have a frame pointer, restore SP from it. */
7657 if ((TARGET_ABI_OPEN_VMS
7658 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7659 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7660 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7662 /* Cope with very large offsets to the register save area. */
7663 if (reg_offset
+ sa_size
> 0x8000)
7665 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7668 if (low
+ sa_size
<= 0x8000)
7669 bias
= reg_offset
- low
, reg_offset
= low
;
7671 bias
= reg_offset
, reg_offset
= 0;
7673 sa_reg
= gen_rtx_REG (DImode
, 22);
7674 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7676 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7679 /* Restore registers in order, excepting a true frame pointer. */
7681 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7683 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7684 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7687 imask
&= ~(1UL << REG_RA
);
7689 for (i
= 0; i
< 31; ++i
)
7690 if (imask
& (1UL << i
))
7692 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7693 fp_offset
= reg_offset
;
7696 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7697 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7698 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7703 if (imask
& (1UL << 31))
7706 for (i
= 0; i
< 31; ++i
)
7707 if (fmask
& (1UL << i
))
7709 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7710 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7711 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7715 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7717 /* Restore callee-saved general-purpose registers. */
7721 for (i
= 9; i
< 15; i
++)
7722 if (imask
& (1UL << i
))
7724 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7726 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7727 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7731 for (i
= 2; i
< 10; i
++)
7732 if (fmask
& (1UL << i
))
7734 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7736 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7737 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7741 /* Restore the return address from the DSIB. */
7743 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7744 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7745 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7748 if (frame_size
|| eh_ofs
)
7750 sp_adj1
= stack_pointer_rtx
;
7754 sp_adj1
= gen_rtx_REG (DImode
, 23);
7755 emit_move_insn (sp_adj1
,
7756 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7759 /* If the stack size is large, begin computation into a temporary
7760 register so as not to interfere with a potential fp restore,
7761 which must be consecutive with an SP restore. */
7762 if (frame_size
< 32768
7763 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7764 sp_adj2
= GEN_INT (frame_size
);
7765 else if (TARGET_ABI_UNICOSMK
)
7767 sp_adj1
= gen_rtx_REG (DImode
, 23);
7768 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7769 sp_adj2
= const0_rtx
;
7771 else if (frame_size
< 0x40007fffL
)
7773 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7775 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7776 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7780 sp_adj1
= gen_rtx_REG (DImode
, 23);
7781 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7783 sp_adj2
= GEN_INT (low
);
7787 rtx tmp
= gen_rtx_REG (DImode
, 23);
7788 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7791 /* We can't drop new things to memory this late, afaik,
7792 so build it up by pieces. */
7793 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7794 -(frame_size
< 0)));
7800 /* From now on, things must be in order. So emit blockages. */
7802 /* Restore the frame pointer. */
7803 if (TARGET_ABI_UNICOSMK
)
7805 emit_insn (gen_blockage ());
7806 mem
= gen_rtx_MEM (DImode
,
7807 plus_constant (hard_frame_pointer_rtx
, -16));
7808 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7809 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7811 else if (fp_is_frame_pointer
)
7813 emit_insn (gen_blockage ());
7814 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7815 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7816 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7818 else if (TARGET_ABI_OPEN_VMS
)
7820 emit_insn (gen_blockage ());
7821 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7822 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7825 /* Restore the stack pointer. */
7826 emit_insn (gen_blockage ());
7827 if (sp_adj2
== const0_rtx
)
7828 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7830 FRP (emit_move_insn (stack_pointer_rtx
,
7831 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7835 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7837 emit_insn (gen_blockage ());
7838 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7839 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7841 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7843 /* Decrement the frame pointer if the function does not have a
7846 emit_insn (gen_blockage ());
7847 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7848 hard_frame_pointer_rtx
, constm1_rtx
)));
7853 /* Output the rest of the textual info surrounding the epilogue. */
7856 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
7858 /* End the function. */
7859 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7861 fputs ("\t.end ", file
);
7862 assemble_name (file
, fnname
);
7865 inside_function
= FALSE
;
7867 #if TARGET_ABI_OPEN_VMS
7868 alpha_write_linkage (file
, fnname
, decl
);
7871 /* Output jump tables and the static subroutine information block. */
7872 if (TARGET_ABI_UNICOSMK
)
7874 unicosmk_output_ssib (file
, fnname
);
7875 unicosmk_output_deferred_case_vectors (file
);
7880 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7882 In order to avoid the hordes of differences between generated code
7883 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7884 lots of code loading up large constants, generate rtl and emit it
7885 instead of going straight to text.
7887 Not sure why this idea hasn't been explored before... */
7890 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7891 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
7894 HOST_WIDE_INT hi
, lo
;
7895 rtx
this, insn
, funexp
;
7897 /* We always require a valid GP. */
7898 emit_insn (gen_prologue_ldgp ());
7899 emit_note (NOTE_INSN_PROLOGUE_END
);
7901 /* Find the "this" pointer. If the function returns a structure,
7902 the structure return pointer is in $16. */
7903 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7904 this = gen_rtx_REG (Pmode
, 17);
7906 this = gen_rtx_REG (Pmode
, 16);
7908 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7909 entire constant for the add. */
7910 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7911 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7912 if (hi
+ lo
== delta
)
7915 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7917 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7921 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7922 delta
, -(delta
< 0));
7923 emit_insn (gen_adddi3 (this, this, tmp
));
7926 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7931 tmp
= gen_rtx_REG (Pmode
, 0);
7932 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
7934 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
7935 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7936 if (hi
+ lo
== vcall_offset
)
7939 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
7943 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
7944 vcall_offset
, -(vcall_offset
< 0));
7945 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
7949 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
7952 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
7954 emit_insn (gen_adddi3 (this, this, tmp
));
7957 /* Generate a tail call to the target function. */
7958 if (! TREE_USED (function
))
7960 assemble_external (function
);
7961 TREE_USED (function
) = 1;
7963 funexp
= XEXP (DECL_RTL (function
), 0);
7964 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7965 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7966 SIBLING_CALL_P (insn
) = 1;
7968 /* Run just enough of rest_of_compilation to get the insns emitted.
7969 There's not really enough bulk here to make other passes such as
7970 instruction scheduling worth while. Note that use_thunk calls
7971 assemble_start_function and assemble_end_function. */
7972 insn
= get_insns ();
7973 insn_locators_initialize ();
7974 shorten_branches (insn
);
7975 final_start_function (insn
, file
, 1);
7976 final (insn
, file
, 1, 0);
7977 final_end_function ();
7979 #endif /* TARGET_ABI_OSF */
7981 /* Debugging support. */
7985 /* Count the number of sdb related labels are generated (to find block
7986 start and end boundaries). */
7988 int sdb_label_count
= 0;
7990 /* Next label # for each statement. */
7992 static int sym_lineno
= 0;
7994 /* Count the number of .file directives, so that .loc is up to date. */
7996 static int num_source_filenames
= 0;
7998 /* Name of the file containing the current function. */
8000 static const char *current_function_file
= "";
8002 /* Offsets to alpha virtual arg/local debugging pointers. */
8004 long alpha_arg_offset
;
8005 long alpha_auto_offset
;
8007 /* Emit a new filename to a stream. */
8010 alpha_output_filename (FILE *stream
, const char *name
)
8012 static int first_time
= TRUE
;
8013 char ltext_label_name
[100];
8018 ++num_source_filenames
;
8019 current_function_file
= name
;
8020 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8021 output_quoted_string (stream
, name
);
8022 fprintf (stream
, "\n");
8023 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8024 fprintf (stream
, "\t#@stabs\n");
8027 else if (write_symbols
== DBX_DEBUG
)
8029 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
8030 fprintf (stream
, "%s", ASM_STABS_OP
);
8031 output_quoted_string (stream
, name
);
8032 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8035 else if (name
!= current_function_file
8036 && strcmp (name
, current_function_file
) != 0)
8038 if (inside_function
&& ! TARGET_GAS
)
8039 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8042 ++num_source_filenames
;
8043 current_function_file
= name
;
8044 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8047 output_quoted_string (stream
, name
);
8048 fprintf (stream
, "\n");
8052 /* Emit a linenumber to a stream. */
8055 alpha_output_lineno (FILE *stream
, int line
)
8057 if (write_symbols
== DBX_DEBUG
)
8059 /* mips-tfile doesn't understand .stabd directives. */
8061 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8062 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8065 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8068 /* Structure to show the current status of registers and memory. */
8070 struct shadow_summary
8073 unsigned int i
: 31; /* Mask of int regs */
8074 unsigned int fp
: 31; /* Mask of fp regs */
8075 unsigned int mem
: 1; /* mem == imem | fpmem */
8079 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8080 to the summary structure. SET is nonzero if the insn is setting the
8081 object, otherwise zero. */
8084 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8086 const char *format_ptr
;
8092 switch (GET_CODE (x
))
8094 /* ??? Note that this case would be incorrect if the Alpha had a
8095 ZERO_EXTRACT in SET_DEST. */
8097 summarize_insn (SET_SRC (x
), sum
, 0);
8098 summarize_insn (SET_DEST (x
), sum
, 1);
8102 summarize_insn (XEXP (x
, 0), sum
, 1);
8106 summarize_insn (XEXP (x
, 0), sum
, 0);
8110 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8111 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8115 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8116 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8120 summarize_insn (SUBREG_REG (x
), sum
, 0);
8125 int regno
= REGNO (x
);
8126 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8128 if (regno
== 31 || regno
== 63)
8134 sum
->defd
.i
|= mask
;
8136 sum
->defd
.fp
|= mask
;
8141 sum
->used
.i
|= mask
;
8143 sum
->used
.fp
|= mask
;
8154 /* Find the regs used in memory address computation: */
8155 summarize_insn (XEXP (x
, 0), sum
, 0);
8158 case CONST_INT
: case CONST_DOUBLE
:
8159 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8160 case SCRATCH
: case ASM_INPUT
:
8163 /* Handle common unary and binary ops for efficiency. */
8164 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8165 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8166 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8167 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8168 case NE
: case EQ
: case GE
: case GT
: case LE
:
8169 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8170 summarize_insn (XEXP (x
, 0), sum
, 0);
8171 summarize_insn (XEXP (x
, 1), sum
, 0);
8174 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8175 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8176 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8177 case SQRT
: case FFS
:
8178 summarize_insn (XEXP (x
, 0), sum
, 0);
8182 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8183 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8184 switch (format_ptr
[i
])
8187 summarize_insn (XEXP (x
, i
), sum
, 0);
8191 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8192 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8204 /* Ensure a sufficient number of `trapb' insns are in the code when
8205 the user requests code with a trap precision of functions or
8208 In naive mode, when the user requests a trap-precision of
8209 "instruction", a trapb is needed after every instruction that may
8210 generate a trap. This ensures that the code is resumption safe but
8213 When optimizations are turned on, we delay issuing a trapb as long
8214 as possible. In this context, a trap shadow is the sequence of
8215 instructions that starts with a (potentially) trap generating
8216 instruction and extends to the next trapb or call_pal instruction
8217 (but GCC never generates call_pal by itself). We can delay (and
8218 therefore sometimes omit) a trapb subject to the following
8221 (a) On entry to the trap shadow, if any Alpha register or memory
8222 location contains a value that is used as an operand value by some
8223 instruction in the trap shadow (live on entry), then no instruction
8224 in the trap shadow may modify the register or memory location.
8226 (b) Within the trap shadow, the computation of the base register
8227 for a memory load or store instruction may not involve using the
8228 result of an instruction that might generate an UNPREDICTABLE
8231 (c) Within the trap shadow, no register may be used more than once
8232 as a destination register. (This is to make life easier for the
8235 (d) The trap shadow may not include any branch instructions. */
8238 alpha_handle_trap_shadows (void)
8240 struct shadow_summary shadow
;
8241 int trap_pending
, exception_nesting
;
8245 exception_nesting
= 0;
8248 shadow
.used
.mem
= 0;
8249 shadow
.defd
= shadow
.used
;
8251 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8253 if (GET_CODE (i
) == NOTE
)
8255 switch (NOTE_LINE_NUMBER (i
))
8257 case NOTE_INSN_EH_REGION_BEG
:
8258 exception_nesting
++;
8263 case NOTE_INSN_EH_REGION_END
:
8264 exception_nesting
--;
8269 case NOTE_INSN_EPILOGUE_BEG
:
8270 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8275 else if (trap_pending
)
8277 if (alpha_tp
== ALPHA_TP_FUNC
)
8279 if (GET_CODE (i
) == JUMP_INSN
8280 && GET_CODE (PATTERN (i
)) == RETURN
)
8283 else if (alpha_tp
== ALPHA_TP_INSN
)
8287 struct shadow_summary sum
;
8292 sum
.defd
= sum
.used
;
8294 switch (GET_CODE (i
))
8297 /* Annoyingly, get_attr_trap will abort on these. */
8298 if (GET_CODE (PATTERN (i
)) == USE
8299 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8302 summarize_insn (PATTERN (i
), &sum
, 0);
8304 if ((sum
.defd
.i
& shadow
.defd
.i
)
8305 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8307 /* (c) would be violated */
8311 /* Combine shadow with summary of current insn: */
8312 shadow
.used
.i
|= sum
.used
.i
;
8313 shadow
.used
.fp
|= sum
.used
.fp
;
8314 shadow
.used
.mem
|= sum
.used
.mem
;
8315 shadow
.defd
.i
|= sum
.defd
.i
;
8316 shadow
.defd
.fp
|= sum
.defd
.fp
;
8317 shadow
.defd
.mem
|= sum
.defd
.mem
;
8319 if ((sum
.defd
.i
& shadow
.used
.i
)
8320 || (sum
.defd
.fp
& shadow
.used
.fp
)
8321 || (sum
.defd
.mem
& shadow
.used
.mem
))
8323 /* (a) would be violated (also takes care of (b)) */
8324 if (get_attr_trap (i
) == TRAP_YES
8325 && ((sum
.defd
.i
& sum
.used
.i
)
8326 || (sum
.defd
.fp
& sum
.used
.fp
)))
8345 n
= emit_insn_before (gen_trapb (), i
);
8346 PUT_MODE (n
, TImode
);
8347 PUT_MODE (i
, TImode
);
8351 shadow
.used
.mem
= 0;
8352 shadow
.defd
= shadow
.used
;
8357 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8358 && GET_CODE (i
) == INSN
8359 && GET_CODE (PATTERN (i
)) != USE
8360 && GET_CODE (PATTERN (i
)) != CLOBBER
8361 && get_attr_trap (i
) == TRAP_YES
)
8363 if (optimize
&& !trap_pending
)
8364 summarize_insn (PATTERN (i
), &shadow
, 0);
8370 /* Alpha can only issue instruction groups simultaneously if they are
8371 suitably aligned. This is very processor-specific. */
8373 enum alphaev4_pipe
{
8380 enum alphaev5_pipe
{
8391 static enum alphaev4_pipe
8392 alphaev4_insn_pipe (rtx insn
)
8394 if (recog_memoized (insn
) < 0)
8396 if (get_attr_length (insn
) != 4)
8399 switch (get_attr_type (insn
))
8433 static enum alphaev5_pipe
8434 alphaev5_insn_pipe (rtx insn
)
8436 if (recog_memoized (insn
) < 0)
8438 if (get_attr_length (insn
) != 4)
8441 switch (get_attr_type (insn
))
8482 /* IN_USE is a mask of the slots currently filled within the insn group.
8483 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8484 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8486 LEN is, of course, the length of the group in bytes. */
8489 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8496 || GET_CODE (PATTERN (insn
)) == CLOBBER
8497 || GET_CODE (PATTERN (insn
)) == USE
)
8502 enum alphaev4_pipe pipe
;
8504 pipe
= alphaev4_insn_pipe (insn
);
8508 /* Force complex instructions to start new groups. */
8512 /* If this is a completely unrecognized insn, its an asm.
8513 We don't know how long it is, so record length as -1 to
8514 signal a needed realignment. */
8515 if (recog_memoized (insn
) < 0)
8518 len
= get_attr_length (insn
);
8522 if (in_use
& EV4_IB0
)
8524 if (in_use
& EV4_IB1
)
8529 in_use
|= EV4_IB0
| EV4_IBX
;
8533 if (in_use
& EV4_IB0
)
8535 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8543 if (in_use
& EV4_IB1
)
8553 /* Haifa doesn't do well scheduling branches. */
8554 if (GET_CODE (insn
) == JUMP_INSN
)
8558 insn
= next_nonnote_insn (insn
);
8560 if (!insn
|| ! INSN_P (insn
))
8563 /* Let Haifa tell us where it thinks insn group boundaries are. */
8564 if (GET_MODE (insn
) == TImode
)
8567 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8572 insn
= next_nonnote_insn (insn
);
8580 /* IN_USE is a mask of the slots currently filled within the insn group.
8581 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8582 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8584 LEN is, of course, the length of the group in bytes. */
8587 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8594 || GET_CODE (PATTERN (insn
)) == CLOBBER
8595 || GET_CODE (PATTERN (insn
)) == USE
)
8600 enum alphaev5_pipe pipe
;
8602 pipe
= alphaev5_insn_pipe (insn
);
8606 /* Force complex instructions to start new groups. */
8610 /* If this is a completely unrecognized insn, its an asm.
8611 We don't know how long it is, so record length as -1 to
8612 signal a needed realignment. */
8613 if (recog_memoized (insn
) < 0)
8616 len
= get_attr_length (insn
);
8619 /* ??? Most of the places below, we would like to abort, as
8620 it would indicate an error either in Haifa, or in the
8621 scheduling description. Unfortunately, Haifa never
8622 schedules the last instruction of the BB, so we don't
8623 have an accurate TI bit to go off. */
8625 if (in_use
& EV5_E0
)
8627 if (in_use
& EV5_E1
)
8632 in_use
|= EV5_E0
| EV5_E01
;
8636 if (in_use
& EV5_E0
)
8638 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8646 if (in_use
& EV5_E1
)
8652 if (in_use
& EV5_FA
)
8654 if (in_use
& EV5_FM
)
8659 in_use
|= EV5_FA
| EV5_FAM
;
8663 if (in_use
& EV5_FA
)
8669 if (in_use
& EV5_FM
)
8682 /* Haifa doesn't do well scheduling branches. */
8683 /* ??? If this is predicted not-taken, slotting continues, except
8684 that no more IBR, FBR, or JSR insns may be slotted. */
8685 if (GET_CODE (insn
) == JUMP_INSN
)
8689 insn
= next_nonnote_insn (insn
);
8691 if (!insn
|| ! INSN_P (insn
))
8694 /* Let Haifa tell us where it thinks insn group boundaries are. */
8695 if (GET_MODE (insn
) == TImode
)
8698 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8703 insn
= next_nonnote_insn (insn
);
8712 alphaev4_next_nop (int *pin_use
)
8714 int in_use
= *pin_use
;
8717 if (!(in_use
& EV4_IB0
))
8722 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8727 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8740 alphaev5_next_nop (int *pin_use
)
8742 int in_use
= *pin_use
;
8745 if (!(in_use
& EV5_E1
))
8750 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8755 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8767 /* The instruction group alignment main loop. */
8770 alpha_align_insns (unsigned int max_align
,
8771 rtx (*next_group
) (rtx
, int *, int *),
8772 rtx (*next_nop
) (int *))
8774 /* ALIGN is the known alignment for the insn group. */
8776 /* OFS is the offset of the current insn in the insn group. */
8778 int prev_in_use
, in_use
, len
;
8781 /* Let shorten branches care for assigning alignments to code labels. */
8782 shorten_branches (get_insns ());
8784 if (align_functions
< 4)
8786 else if ((unsigned int) align_functions
< max_align
)
8787 align
= align_functions
;
8791 ofs
= prev_in_use
= 0;
8793 if (GET_CODE (i
) == NOTE
)
8794 i
= next_nonnote_insn (i
);
8798 next
= (*next_group
) (i
, &in_use
, &len
);
8800 /* When we see a label, resync alignment etc. */
8801 if (GET_CODE (i
) == CODE_LABEL
)
8803 unsigned int new_align
= 1 << label_to_alignment (i
);
8805 if (new_align
>= align
)
8807 align
= new_align
< max_align
? new_align
: max_align
;
8811 else if (ofs
& (new_align
-1))
8812 ofs
= (ofs
| (new_align
-1)) + 1;
8817 /* Handle complex instructions special. */
8818 else if (in_use
== 0)
8820 /* Asms will have length < 0. This is a signal that we have
8821 lost alignment knowledge. Assume, however, that the asm
8822 will not mis-align instructions. */
8831 /* If the known alignment is smaller than the recognized insn group,
8832 realign the output. */
8833 else if ((int) align
< len
)
8835 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8838 where
= prev
= prev_nonnote_insn (i
);
8839 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8842 /* Can't realign between a call and its gp reload. */
8843 if (! (TARGET_EXPLICIT_RELOCS
8844 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8846 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8847 align
= 1 << new_log_align
;
8852 /* If the group won't fit in the same INT16 as the previous,
8853 we need to add padding to keep the group together. Rather
8854 than simply leaving the insn filling to the assembler, we
8855 can make use of the knowledge of what sorts of instructions
8856 were issued in the previous group to make sure that all of
8857 the added nops are really free. */
8858 else if (ofs
+ len
> (int) align
)
8860 int nop_count
= (align
- ofs
) / 4;
8863 /* Insert nops before labels, branches, and calls to truly merge
8864 the execution of the nops with the previous instruction group. */
8865 where
= prev_nonnote_insn (i
);
8868 if (GET_CODE (where
) == CODE_LABEL
)
8870 rtx where2
= prev_nonnote_insn (where
);
8871 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8874 else if (GET_CODE (where
) == INSN
)
8881 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8882 while (--nop_count
);
8886 ofs
= (ofs
+ len
) & (align
- 1);
8887 prev_in_use
= in_use
;
8892 /* Machine dependent reorg pass. */
8897 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8898 alpha_handle_trap_shadows ();
8900 /* Due to the number of extra trapb insns, don't bother fixing up
8901 alignment when trap precision is instruction. Moreover, we can
8902 only do our job when sched2 is run. */
8903 if (optimize
&& !optimize_size
8904 && alpha_tp
!= ALPHA_TP_INSN
8905 && flag_schedule_insns_after_reload
)
8907 if (alpha_cpu
== PROCESSOR_EV4
)
8908 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
8909 else if (alpha_cpu
== PROCESSOR_EV5
)
8910 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
8914 #if !TARGET_ABI_UNICOSMK
8921 alpha_file_start (void)
8923 #ifdef OBJECT_FORMAT_ELF
8924 /* If emitting dwarf2 debug information, we cannot generate a .file
8925 directive to start the file, as it will conflict with dwarf2out
8926 file numbers. So it's only useful when emitting mdebug output. */
8927 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
8930 default_file_start ();
8932 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
8935 fputs ("\t.set noreorder\n", asm_out_file
);
8936 fputs ("\t.set volatile\n", asm_out_file
);
8937 if (!TARGET_ABI_OPEN_VMS
)
8938 fputs ("\t.set noat\n", asm_out_file
);
8939 if (TARGET_EXPLICIT_RELOCS
)
8940 fputs ("\t.set nomacro\n", asm_out_file
);
8941 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
8942 fprintf (asm_out_file
,
8944 TARGET_CPU_EV6
? "ev6"
8946 ? (TARGET_MAX
? "pca56" : TARGET_BWX
? "ev56" : "ev5")
8951 #ifdef OBJECT_FORMAT_ELF
8953 /* Switch to the section to which we should output X. The only thing
8954 special we do here is to honor small data. */
8957 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
8958 unsigned HOST_WIDE_INT align
)
8960 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8961 /* ??? Consider using mergeable sdata sections. */
8964 default_elf_select_rtx_section (mode
, x
, align
);
8967 #endif /* OBJECT_FORMAT_ELF */
8969 /* Structure to collect function names for final output in link section. */
8970 /* Note that items marked with GTY can't be ifdef'ed out. */
8972 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8973 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
8975 struct alpha_links
GTY(())
8979 enum links_kind lkind
;
8980 enum reloc_kind rkind
;
8983 struct alpha_funcs
GTY(())
8986 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8990 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8991 splay_tree alpha_links_tree
;
8992 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
8993 splay_tree alpha_funcs_tree
;
8995 static GTY(()) int alpha_funcs_num
;
8997 #if TARGET_ABI_OPEN_VMS
8999 /* Return the VMS argument type corresponding to MODE. */
9002 alpha_arg_type (enum machine_mode mode
)
9007 return TARGET_FLOAT_VAX
? FF
: FS
;
9009 return TARGET_FLOAT_VAX
? FD
: FT
;
9015 /* Return an rtx for an integer representing the VMS Argument Information
9019 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9021 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9024 for (i
= 0; i
< 6; i
++)
9025 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9027 return GEN_INT (regval
);
9030 /* Make (or fake) .linkage entry for function call.
9032 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9034 Return an SYMBOL_REF rtx for the linkage. */
9037 alpha_need_linkage (const char *name
, int is_local
)
9039 splay_tree_node node
;
9040 struct alpha_links
*al
;
9047 struct alpha_funcs
*cfaf
;
9049 if (!alpha_funcs_tree
)
9050 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9051 splay_tree_compare_pointers
);
9053 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9056 cfaf
->num
= ++alpha_funcs_num
;
9058 splay_tree_insert (alpha_funcs_tree
,
9059 (splay_tree_key
) current_function_decl
,
9060 (splay_tree_value
) cfaf
);
9063 if (alpha_links_tree
)
9065 /* Is this name already defined? */
9067 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9070 al
= (struct alpha_links
*) node
->value
;
9073 /* Defined here but external assumed. */
9074 if (al
->lkind
== KIND_EXTERN
)
9075 al
->lkind
= KIND_LOCAL
;
9079 /* Used here but unused assumed. */
9080 if (al
->lkind
== KIND_UNUSED
)
9081 al
->lkind
= KIND_LOCAL
;
9087 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9089 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9090 name
= ggc_strdup (name
);
9092 /* Assume external if no definition. */
9093 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9095 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9096 get_identifier (name
);
9098 /* Construct a SYMBOL_REF for us to call. */
9100 size_t name_len
= strlen (name
);
9101 char *linksym
= alloca (name_len
+ 6);
9103 memcpy (linksym
+ 1, name
, name_len
);
9104 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9105 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9106 ggc_alloc_string (linksym
, name_len
+ 5));
9109 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9110 (splay_tree_value
) al
);
9116 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9118 splay_tree_node cfunnode
;
9119 struct alpha_funcs
*cfaf
;
9120 struct alpha_links
*al
;
9121 const char *name
= XSTR (linkage
, 0);
9123 cfaf
= (struct alpha_funcs
*) 0;
9124 al
= (struct alpha_links
*) 0;
9126 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9127 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9131 splay_tree_node lnode
;
9133 /* Is this name already defined? */
9135 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9137 al
= (struct alpha_links
*) lnode
->value
;
9140 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9148 splay_tree_node node
= 0;
9149 struct alpha_links
*anl
;
9154 name_len
= strlen (name
);
9156 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9157 al
->num
= cfaf
->num
;
9159 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9162 anl
= (struct alpha_links
*) node
->value
;
9163 al
->lkind
= anl
->lkind
;
9166 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9167 buflen
= strlen (buf
);
9168 linksym
= alloca (buflen
+ 1);
9169 memcpy (linksym
, buf
, buflen
+ 1);
9171 al
->linkage
= gen_rtx_SYMBOL_REF
9172 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9174 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9175 (splay_tree_value
) al
);
9179 al
->rkind
= KIND_CODEADDR
;
9181 al
->rkind
= KIND_LINKAGE
;
9184 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9190 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9192 const char *const name
= (const char *) node
->key
;
9193 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9194 FILE *stream
= (FILE *) data
;
9196 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9197 if (link
->rkind
== KIND_CODEADDR
)
9199 if (link
->lkind
== KIND_LOCAL
)
9201 /* Local and used */
9202 fprintf (stream
, "\t.quad %s..en\n", name
);
9206 /* External and used, request code address. */
9207 fprintf (stream
, "\t.code_address %s\n", name
);
9212 if (link
->lkind
== KIND_LOCAL
)
9214 /* Local and used, build linkage pair. */
9215 fprintf (stream
, "\t.quad %s..en\n", name
);
9216 fprintf (stream
, "\t.quad %s\n", name
);
9220 /* External and used, request linkage pair. */
9221 fprintf (stream
, "\t.linkage %s\n", name
);
9229 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9231 splay_tree_node node
;
9232 struct alpha_funcs
*func
;
9235 fprintf (stream
, "\t.align 3\n");
9236 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9237 func
= (struct alpha_funcs
*) node
->value
;
9239 fputs ("\t.name ", stream
);
9240 assemble_name (stream
, funname
);
9241 fputs ("..na\n", stream
);
9242 ASM_OUTPUT_LABEL (stream
, funname
);
9243 fprintf (stream
, "\t.pdesc ");
9244 assemble_name (stream
, funname
);
9245 fprintf (stream
, "..en,%s\n",
9246 alpha_procedure_type
== PT_STACK
? "stack"
9247 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9251 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9252 /* splay_tree_delete (func->links); */
9256 /* Given a decl, a section name, and whether the decl initializer
9257 has relocs, choose attributes for the section. */
9259 #define SECTION_VMS_OVERLAY SECTION_FORGET
9260 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9261 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9264 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9266 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9268 if (decl
&& DECL_ATTRIBUTES (decl
)
9269 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9270 flags
|= SECTION_VMS_OVERLAY
;
9271 if (decl
&& DECL_ATTRIBUTES (decl
)
9272 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9273 flags
|= SECTION_VMS_GLOBAL
;
9274 if (decl
&& DECL_ATTRIBUTES (decl
)
9275 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9276 flags
|= SECTION_VMS_INITIALIZE
;
9281 /* Switch to an arbitrary section NAME with attributes as specified
9282 by FLAGS. ALIGN specifies any known alignment requirements for
9283 the section; 0 if the default should be used. */
9286 vms_asm_named_section (const char *name
, unsigned int flags
)
9288 fputc ('\n', asm_out_file
);
9289 fprintf (asm_out_file
, ".section\t%s", name
);
9291 if (flags
& SECTION_VMS_OVERLAY
)
9292 fprintf (asm_out_file
, ",OVR");
9293 if (flags
& SECTION_VMS_GLOBAL
)
9294 fprintf (asm_out_file
, ",GBL");
9295 if (flags
& SECTION_VMS_INITIALIZE
)
9296 fprintf (asm_out_file
, ",NOMOD");
9297 if (flags
& SECTION_DEBUG
)
9298 fprintf (asm_out_file
, ",NOWRT");
9300 fputc ('\n', asm_out_file
);
9303 /* Record an element in the table of global constructors. SYMBOL is
9304 a SYMBOL_REF of the function to be called; PRIORITY is a number
9305 between 0 and MAX_INIT_PRIORITY.
9307 Differs from default_ctors_section_asm_out_constructor in that the
9308 width of the .ctors entry is always 64 bits, rather than the 32 bits
9309 used by a normal pointer. */
9312 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9315 assemble_align (BITS_PER_WORD
);
9316 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9320 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9323 assemble_align (BITS_PER_WORD
);
9324 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9329 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9330 int is_local ATTRIBUTE_UNUSED
)
9336 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9337 tree cfundecl ATTRIBUTE_UNUSED
,
9338 int lflag ATTRIBUTE_UNUSED
,
9339 int rflag ATTRIBUTE_UNUSED
)
9344 #endif /* TARGET_ABI_OPEN_VMS */
9346 #if TARGET_ABI_UNICOSMK
9348 /* Define the offset between two registers, one to be eliminated, and the
9349 other its replacement, at the start of a routine. */
9352 unicosmk_initial_elimination_offset (int from
, int to
)
9356 fixed_size
= alpha_sa_size();
9357 if (fixed_size
!= 0)
9360 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9362 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9364 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9365 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9366 + ALPHA_ROUND (get_frame_size()));
9367 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9368 return (ALPHA_ROUND (fixed_size
)
9369 + ALPHA_ROUND (get_frame_size()
9370 + current_function_outgoing_args_size
));
9375 /* Output the module name for .ident and .end directives. We have to strip
9376 directories and add make sure that the module name starts with a letter
9380 unicosmk_output_module_name (FILE *file
)
9382 const char *name
= lbasename (main_input_filename
);
9383 unsigned len
= strlen (name
);
9384 char *clean_name
= alloca (len
+ 2);
9385 char *ptr
= clean_name
;
9387 /* CAM only accepts module names that start with a letter or '$'. We
9388 prefix the module name with a '$' if necessary. */
9390 if (!ISALPHA (*name
))
9392 memcpy (ptr
, name
, len
+ 1);
9393 clean_symbol_name (clean_name
);
9394 fputs (clean_name
, file
);
9397 /* Output the definition of a common variable. */
9400 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9403 printf ("T3E__: common %s\n", name
);
9406 fputs("\t.endp\n\n\t.psect ", file
);
9407 assemble_name(file
, name
);
9408 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9409 fprintf(file
, "\t.byte\t0:%d\n", size
);
9411 /* Mark the symbol as defined in this module. */
9412 name_tree
= get_identifier (name
);
9413 TREE_ASM_WRITTEN (name_tree
) = 1;
9416 #define SECTION_PUBLIC SECTION_MACH_DEP
9417 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9418 static int current_section_align
;
9421 unicosmk_section_type_flags (tree decl
, const char *name
,
9422 int reloc ATTRIBUTE_UNUSED
)
9424 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9429 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9431 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9432 if (align_functions_log
> current_section_align
)
9433 current_section_align
= align_functions_log
;
9435 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9436 flags
|= SECTION_MAIN
;
9439 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9441 if (TREE_PUBLIC (decl
))
9442 flags
|= SECTION_PUBLIC
;
9447 /* Generate a section name for decl and associate it with the
9451 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9459 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9460 name
= default_strip_name_encoding (name
);
9461 len
= strlen (name
);
9463 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9467 /* It is essential that we prefix the section name here because
9468 otherwise the section names generated for constructors and
9469 destructors confuse collect2. */
9471 string
= alloca (len
+ 6);
9472 sprintf (string
, "code@%s", name
);
9473 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9475 else if (TREE_PUBLIC (decl
))
9476 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9481 string
= alloca (len
+ 6);
9482 sprintf (string
, "data@%s", name
);
9483 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9487 /* Switch to an arbitrary section NAME with attributes as specified
9488 by FLAGS. ALIGN specifies any known alignment requirements for
9489 the section; 0 if the default should be used. */
9492 unicosmk_asm_named_section (const char *name
, unsigned int flags
)
9496 /* Close the previous section. */
9498 fputs ("\t.endp\n\n", asm_out_file
);
9500 /* Find out what kind of section we are opening. */
9502 if (flags
& SECTION_MAIN
)
9503 fputs ("\t.start\tmain\n", asm_out_file
);
9505 if (flags
& SECTION_CODE
)
9507 else if (flags
& SECTION_PUBLIC
)
9512 if (current_section_align
!= 0)
9513 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9514 current_section_align
, kind
);
9516 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9520 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9523 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9524 unicosmk_unique_section (decl
, 0);
9527 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9528 in code sections because .align fill unused space with zeroes. */
9531 unicosmk_output_align (FILE *file
, int align
)
9533 if (inside_function
)
9534 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9536 fprintf (file
, "\t.align\t%d\n", align
);
9539 /* Add a case vector to the current function's list of deferred case
9540 vectors. Case vectors have to be put into a separate section because CAM
9541 does not allow data definitions in code sections. */
9544 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9546 struct machine_function
*machine
= cfun
->machine
;
9548 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9549 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9550 machine
->addr_list
);
9553 /* Output a case vector. */
9556 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9558 rtx lab
= XEXP (vec
, 0);
9559 rtx body
= XEXP (vec
, 1);
9560 int vlen
= XVECLEN (body
, 0);
9563 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9565 for (idx
= 0; idx
< vlen
; idx
++)
9567 ASM_OUTPUT_ADDR_VEC_ELT
9568 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9572 /* Output current function's deferred case vectors. */
9575 unicosmk_output_deferred_case_vectors (FILE *file
)
9577 struct machine_function
*machine
= cfun
->machine
;
9580 if (machine
->addr_list
== NULL_RTX
)
9584 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9585 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9588 /* Generate the name of the SSIB section for the current function. */
9590 #define SSIB_PREFIX "__SSIB_"
9591 #define SSIB_PREFIX_LEN 7
9594 unicosmk_ssib_name (void)
9596 /* This is ok since CAM won't be able to deal with names longer than that
9599 static char name
[256];
9605 x
= DECL_RTL (cfun
->decl
);
9606 if (GET_CODE (x
) != MEM
)
9609 if (GET_CODE (x
) != SYMBOL_REF
)
9611 fnname
= XSTR (x
, 0);
9613 len
= strlen (fnname
);
9614 if (len
+ SSIB_PREFIX_LEN
> 255)
9615 len
= 255 - SSIB_PREFIX_LEN
;
9617 strcpy (name
, SSIB_PREFIX
);
9618 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9619 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9624 /* Set up the dynamic subprogram information block (DSIB) and update the
9625 frame pointer register ($15) for subroutines which have a frame. If the
9626 subroutine doesn't have a frame, simply increment $15. */
9629 unicosmk_gen_dsib (unsigned long *imaskP
)
9631 if (alpha_procedure_type
== PT_STACK
)
9633 const char *ssib_name
;
9636 /* Allocate 64 bytes for the DSIB. */
9638 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9640 emit_insn (gen_blockage ());
9642 /* Save the return address. */
9644 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9645 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9646 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9647 (*imaskP
) &= ~(1UL << REG_RA
);
9649 /* Save the old frame pointer. */
9651 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9652 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9653 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9654 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9656 emit_insn (gen_blockage ());
9658 /* Store the SSIB pointer. */
9660 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9661 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9662 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9664 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9665 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9666 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9668 /* Save the CIW index. */
9670 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9671 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9672 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9674 emit_insn (gen_blockage ());
9676 /* Set the new frame pointer. */
9678 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9679 stack_pointer_rtx
, GEN_INT (64))));
9684 /* Increment the frame pointer register to indicate that we do not
9687 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9688 hard_frame_pointer_rtx
, const1_rtx
)));
9692 /* Output the static subroutine information block for the current
9696 unicosmk_output_ssib (FILE *file
, const char *fnname
)
9702 struct machine_function
*machine
= cfun
->machine
;
9705 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9706 unicosmk_ssib_name ());
9708 /* Some required stuff and the function name length. */
9710 len
= strlen (fnname
);
9711 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9714 ??? We don't do that yet. */
9716 fputs ("\t.quad\t0\n", file
);
9718 /* Function address. */
9720 fputs ("\t.quad\t", file
);
9721 assemble_name (file
, fnname
);
9724 fputs ("\t.quad\t0\n", file
);
9725 fputs ("\t.quad\t0\n", file
);
9728 ??? We do it the same way Cray CC does it but this could be
9731 for( i
= 0; i
< len
; i
++ )
9732 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9733 if( (len
% 8) == 0 )
9734 fputs ("\t.quad\t0\n", file
);
9736 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9738 /* All call information words used in the function. */
9740 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9743 #if HOST_BITS_PER_WIDE_INT == 32
9744 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
9745 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9747 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
9752 /* Add a call information word (CIW) to the list of the current function's
9753 CIWs and return its index.
9755 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9758 unicosmk_add_call_info_word (rtx x
)
9761 struct machine_function
*machine
= cfun
->machine
;
9763 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9764 if (machine
->first_ciw
== NULL_RTX
)
9765 machine
->first_ciw
= node
;
9767 XEXP (machine
->last_ciw
, 1) = node
;
9769 machine
->last_ciw
= node
;
9770 ++machine
->ciw_count
;
9772 return GEN_INT (machine
->ciw_count
9773 + strlen (current_function_name ())/8 + 5);
9776 static char unicosmk_section_buf
[100];
9779 unicosmk_text_section (void)
9781 static int count
= 0;
9782 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9784 return unicosmk_section_buf
;
9788 unicosmk_data_section (void)
9790 static int count
= 1;
9791 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9793 return unicosmk_section_buf
;
9796 /* The Cray assembler doesn't accept extern declarations for symbols which
9797 are defined in the same file. We have to keep track of all global
9798 symbols which are referenced and/or defined in a source file and output
9799 extern declarations for those which are referenced but not defined at
9802 /* List of identifiers for which an extern declaration might have to be
9804 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9806 struct unicosmk_extern_list
9808 struct unicosmk_extern_list
*next
;
9812 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9814 /* Output extern declarations which are required for every asm file. */
9817 unicosmk_output_default_externs (FILE *file
)
9819 static const char *const externs
[] =
9820 { "__T3E_MISMATCH" };
9825 n
= ARRAY_SIZE (externs
);
9827 for (i
= 0; i
< n
; i
++)
9828 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9831 /* Output extern declarations for global symbols which are have been
9832 referenced but not defined. */
9835 unicosmk_output_externs (FILE *file
)
9837 struct unicosmk_extern_list
*p
;
9838 const char *real_name
;
9842 len
= strlen (user_label_prefix
);
9843 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9845 /* We have to strip the encoding and possibly remove user_label_prefix
9846 from the identifier in order to handle -fleading-underscore and
9847 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9848 real_name
= default_strip_name_encoding (p
->name
);
9849 if (len
&& p
->name
[0] == '*'
9850 && !memcmp (real_name
, user_label_prefix
, len
))
9853 name_tree
= get_identifier (real_name
);
9854 if (! TREE_ASM_WRITTEN (name_tree
))
9856 TREE_ASM_WRITTEN (name_tree
) = 1;
9857 fputs ("\t.extern\t", file
);
9858 assemble_name (file
, p
->name
);
9864 /* Record an extern. */
9867 unicosmk_add_extern (const char *name
)
9869 struct unicosmk_extern_list
*p
;
9871 p
= (struct unicosmk_extern_list
*)
9872 xmalloc (sizeof (struct unicosmk_extern_list
));
9873 p
->next
= unicosmk_extern_head
;
9875 unicosmk_extern_head
= p
;
9878 /* The Cray assembler generates incorrect code if identifiers which
9879 conflict with register names are used as instruction operands. We have
9880 to replace such identifiers with DEX expressions. */
9882 /* Structure to collect identifiers which have been replaced by DEX
9884 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9886 struct unicosmk_dex
{
9887 struct unicosmk_dex
*next
;
9891 /* List of identifiers which have been replaced by DEX expressions. The DEX
9892 number is determined by the position in the list. */
9894 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9896 /* The number of elements in the DEX list. */
9898 static int unicosmk_dex_count
= 0;
9900 /* Check if NAME must be replaced by a DEX expression. */
9903 unicosmk_special_name (const char *name
)
9911 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9917 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9920 return (name
[2] == '\0'
9921 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9924 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9928 /* Return the DEX number if X must be replaced by a DEX expression and 0
9932 unicosmk_need_dex (rtx x
)
9934 struct unicosmk_dex
*dex
;
9938 if (GET_CODE (x
) != SYMBOL_REF
)
9942 if (! unicosmk_special_name (name
))
9945 i
= unicosmk_dex_count
;
9946 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9948 if (! strcmp (name
, dex
->name
))
9953 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
9955 dex
->next
= unicosmk_dex_list
;
9956 unicosmk_dex_list
= dex
;
9958 ++unicosmk_dex_count
;
9959 return unicosmk_dex_count
;
9962 /* Output the DEX definitions for this file. */
9965 unicosmk_output_dex (FILE *file
)
9967 struct unicosmk_dex
*dex
;
9970 if (unicosmk_dex_list
== NULL
)
9973 fprintf (file
, "\t.dexstart\n");
9975 i
= unicosmk_dex_count
;
9976 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9978 fprintf (file
, "\tDEX (%d) = ", i
);
9979 assemble_name (file
, dex
->name
);
9984 fprintf (file
, "\t.dexend\n");
9987 /* Output text that to appear at the beginning of an assembler file. */
9990 unicosmk_file_start (void)
9994 fputs ("\t.ident\t", asm_out_file
);
9995 unicosmk_output_module_name (asm_out_file
);
9996 fputs ("\n\n", asm_out_file
);
9998 /* The Unicos/Mk assembler uses different register names. Instead of trying
9999 to support them, we simply use micro definitions. */
10001 /* CAM has different register names: rN for the integer register N and fN
10002 for the floating-point register N. Instead of trying to use these in
10003 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10006 for (i
= 0; i
< 32; ++i
)
10007 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
10009 for (i
= 0; i
< 32; ++i
)
10010 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
10012 putc ('\n', asm_out_file
);
10014 /* The .align directive fill unused space with zeroes which does not work
10015 in code sections. We define the macro 'gcc@code@align' which uses nops
10016 instead. Note that it assumes that code sections always have the
10017 biggest possible alignment since . refers to the current offset from
10018 the beginning of the section. */
10020 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
10021 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
10022 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
10023 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
10024 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
10025 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
10026 fputs ("\t.endr\n", asm_out_file
);
10027 fputs ("\t.endif\n", asm_out_file
);
10028 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
10030 /* Output extern declarations which should always be visible. */
10031 unicosmk_output_default_externs (asm_out_file
);
10033 /* Open a dummy section. We always need to be inside a section for the
10034 section-switching code to work correctly.
10035 ??? This should be a module id or something like that. I still have to
10036 figure out what the rules for those are. */
10037 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10040 /* Output text to appear at the end of an assembler file. This includes all
10041 pending extern declarations and DEX expressions. */
10044 unicosmk_file_end (void)
10046 fputs ("\t.endp\n\n", asm_out_file
);
10048 /* Output all pending externs. */
10050 unicosmk_output_externs (asm_out_file
);
10052 /* Output dex definitions used for functions whose names conflict with
10055 unicosmk_output_dex (asm_out_file
);
10057 fputs ("\t.end\t", asm_out_file
);
10058 unicosmk_output_module_name (asm_out_file
);
10059 putc ('\n', asm_out_file
);
10065 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10069 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10073 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10074 const char * fnname ATTRIBUTE_UNUSED
)
10078 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10084 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10089 #endif /* TARGET_ABI_UNICOSMK */
10092 alpha_init_libfuncs (void)
10094 if (TARGET_ABI_UNICOSMK
)
10096 /* Prevent gcc from generating calls to __divsi3. */
10097 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10098 set_optab_libfunc (udiv_optab
, SImode
, 0);
10100 /* Use the functions provided by the system library
10101 for DImode integer division. */
10102 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10103 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10105 else if (TARGET_ABI_OPEN_VMS
)
10107 /* Use the VMS runtime library functions for division and
10109 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10110 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10111 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10112 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10113 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10114 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10115 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10116 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10121 /* Initialize the GCC target structure. */
10122 #if TARGET_ABI_OPEN_VMS
10123 # undef TARGET_ATTRIBUTE_TABLE
10124 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10125 # undef TARGET_SECTION_TYPE_FLAGS
10126 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10129 #undef TARGET_IN_SMALL_DATA_P
10130 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10132 #if TARGET_ABI_UNICOSMK
10133 # undef TARGET_INSERT_ATTRIBUTES
10134 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10135 # undef TARGET_SECTION_TYPE_FLAGS
10136 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10137 # undef TARGET_ASM_UNIQUE_SECTION
10138 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10139 # undef TARGET_ASM_GLOBALIZE_LABEL
10140 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10143 #undef TARGET_ASM_ALIGNED_HI_OP
10144 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10145 #undef TARGET_ASM_ALIGNED_DI_OP
10146 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10148 /* Default unaligned ops are provided for ELF systems. To get unaligned
10149 data for non-ELF systems, we have to turn off auto alignment. */
10150 #ifndef OBJECT_FORMAT_ELF
10151 #undef TARGET_ASM_UNALIGNED_HI_OP
10152 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10153 #undef TARGET_ASM_UNALIGNED_SI_OP
10154 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10155 #undef TARGET_ASM_UNALIGNED_DI_OP
10156 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10159 #ifdef OBJECT_FORMAT_ELF
10160 #undef TARGET_ASM_SELECT_RTX_SECTION
10161 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10164 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10165 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10167 #undef TARGET_INIT_LIBFUNCS
10168 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10170 #if TARGET_ABI_UNICOSMK
10171 #undef TARGET_ASM_FILE_START
10172 #define TARGET_ASM_FILE_START unicosmk_file_start
10173 #undef TARGET_ASM_FILE_END
10174 #define TARGET_ASM_FILE_END unicosmk_file_end
10176 #undef TARGET_ASM_FILE_START
10177 #define TARGET_ASM_FILE_START alpha_file_start
10178 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10179 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10182 #undef TARGET_SCHED_ADJUST_COST
10183 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10184 #undef TARGET_SCHED_ISSUE_RATE
10185 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10186 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10187 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10188 alpha_use_dfa_pipeline_interface
10189 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10190 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10191 alpha_multipass_dfa_lookahead
10193 #undef TARGET_HAVE_TLS
10194 #define TARGET_HAVE_TLS HAVE_AS_TLS
10196 #undef TARGET_INIT_BUILTINS
10197 #define TARGET_INIT_BUILTINS alpha_init_builtins
10198 #undef TARGET_EXPAND_BUILTIN
10199 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10201 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10202 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10203 #undef TARGET_CANNOT_COPY_INSN_P
10204 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10207 #undef TARGET_ASM_OUTPUT_MI_THUNK
10208 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10209 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10210 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10213 #undef TARGET_RTX_COSTS
10214 #define TARGET_RTX_COSTS alpha_rtx_costs
10215 #undef TARGET_ADDRESS_COST
10216 #define TARGET_ADDRESS_COST hook_int_rtx_0
10218 #undef TARGET_MACHINE_DEPENDENT_REORG
10219 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10221 #undef TARGET_PROMOTE_FUNCTION_ARGS
10222 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10223 #undef TARGET_PROMOTE_FUNCTION_RETURN
10224 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10225 #undef TARGET_PROMOTE_PROTOTYPES
10226 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10227 #undef TARGET_RETURN_IN_MEMORY
10228 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10229 #undef TARGET_SETUP_INCOMING_VARARGS
10230 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10231 #undef TARGET_STRICT_ARGUMENT_NAMING
10232 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10233 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10234 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10235 #undef TARGET_SPLIT_COMPLEX_ARG
10236 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10238 #undef TARGET_BUILD_BUILTIN_VA_LIST
10239 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10241 struct gcc_target targetm
= TARGET_INITIALIZER
;
10244 #include "gt-alpha.h"