1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
56 #include "tree-flow.h"
57 #include "tree-stdarg.h"
59 /* Specify which cpu to schedule for. */
60 enum processor_type alpha_tune
;
62 /* Which cpu we're generating code for. */
63 enum processor_type alpha_cpu
;
65 static const char * const alpha_cpu_name
[] =
70 /* Specify how accurate floating-point traps need to be. */
72 enum alpha_trap_precision alpha_tp
;
74 /* Specify the floating-point rounding mode. */
76 enum alpha_fp_rounding_mode alpha_fprm
;
78 /* Specify which things cause traps. */
80 enum alpha_fp_trap_mode alpha_fptm
;
82 /* Save information from a "cmpxx" operation until the branch or scc is
85 struct alpha_compare alpha_compare
;
87 /* Nonzero if inside of a function, because the Alpha asm can't
88 handle .files inside of functions. */
90 static int inside_function
= FALSE
;
92 /* The number of cycles of latency we should assume on memory reads. */
94 int alpha_memory_latency
= 3;
96 /* Whether the function needs the GP. */
98 static int alpha_function_needs_gp
;
100 /* The alias set for prologue/epilogue register save/restore. */
102 static GTY(()) int alpha_sr_alias_set
;
104 /* The assembler name of the current function. */
106 static const char *alpha_fnname
;
108 /* The next explicit relocation sequence number. */
109 extern GTY(()) int alpha_next_sequence_number
;
110 int alpha_next_sequence_number
= 1;
112 /* The literal and gpdisp sequence numbers for this insn, as printed
113 by %# and %* respectively. */
114 extern GTY(()) int alpha_this_literal_sequence_number
;
115 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
116 int alpha_this_literal_sequence_number
;
117 int alpha_this_gpdisp_sequence_number
;
119 /* Costs of various operations on the different architectures. */
121 struct alpha_rtx_cost_data
123 unsigned char fp_add
;
124 unsigned char fp_mult
;
125 unsigned char fp_div_sf
;
126 unsigned char fp_div_df
;
127 unsigned char int_mult_si
;
128 unsigned char int_mult_di
;
129 unsigned char int_shift
;
130 unsigned char int_cmov
;
131 unsigned short int_div
;
134 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
137 COSTS_N_INSNS (6), /* fp_add */
138 COSTS_N_INSNS (6), /* fp_mult */
139 COSTS_N_INSNS (34), /* fp_div_sf */
140 COSTS_N_INSNS (63), /* fp_div_df */
141 COSTS_N_INSNS (23), /* int_mult_si */
142 COSTS_N_INSNS (23), /* int_mult_di */
143 COSTS_N_INSNS (2), /* int_shift */
144 COSTS_N_INSNS (2), /* int_cmov */
145 COSTS_N_INSNS (97), /* int_div */
148 COSTS_N_INSNS (4), /* fp_add */
149 COSTS_N_INSNS (4), /* fp_mult */
150 COSTS_N_INSNS (15), /* fp_div_sf */
151 COSTS_N_INSNS (22), /* fp_div_df */
152 COSTS_N_INSNS (8), /* int_mult_si */
153 COSTS_N_INSNS (12), /* int_mult_di */
154 COSTS_N_INSNS (1) + 1, /* int_shift */
155 COSTS_N_INSNS (1), /* int_cmov */
156 COSTS_N_INSNS (83), /* int_div */
159 COSTS_N_INSNS (4), /* fp_add */
160 COSTS_N_INSNS (4), /* fp_mult */
161 COSTS_N_INSNS (12), /* fp_div_sf */
162 COSTS_N_INSNS (15), /* fp_div_df */
163 COSTS_N_INSNS (7), /* int_mult_si */
164 COSTS_N_INSNS (7), /* int_mult_di */
165 COSTS_N_INSNS (1), /* int_shift */
166 COSTS_N_INSNS (2), /* int_cmov */
167 COSTS_N_INSNS (86), /* int_div */
171 /* Similar but tuned for code size instead of execution latency. The
172 extra +N is fractional cost tuning based on latency. It's used to
173 encourage use of cheaper insns like shift, but only if there's just
176 static struct alpha_rtx_cost_data
const alpha_rtx_cost_size
=
178 COSTS_N_INSNS (1), /* fp_add */
179 COSTS_N_INSNS (1), /* fp_mult */
180 COSTS_N_INSNS (1), /* fp_div_sf */
181 COSTS_N_INSNS (1) + 1, /* fp_div_df */
182 COSTS_N_INSNS (1) + 1, /* int_mult_si */
183 COSTS_N_INSNS (1) + 2, /* int_mult_di */
184 COSTS_N_INSNS (1), /* int_shift */
185 COSTS_N_INSNS (1), /* int_cmov */
186 COSTS_N_INSNS (6), /* int_div */
189 /* Get the number of args of a function in one of two ways. */
190 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
191 #define NUM_ARGS current_function_args_info.num_args
193 #define NUM_ARGS current_function_args_info
199 /* Declarations of static functions. */
200 static struct machine_function
*alpha_init_machine_status (void);
201 static rtx
alpha_emit_xfloating_compare (enum rtx_code
*, rtx
, rtx
);
203 #if TARGET_ABI_OPEN_VMS
204 static void alpha_write_linkage (FILE *, const char *, tree
);
207 static void unicosmk_output_deferred_case_vectors (FILE *);
208 static void unicosmk_gen_dsib (unsigned long *);
209 static void unicosmk_output_ssib (FILE *, const char *);
210 static int unicosmk_need_dex (rtx
);
212 /* Implement TARGET_HANDLE_OPTION. */
215 alpha_handle_option (size_t code
, const char *arg
, int value
)
221 target_flags
|= MASK_SOFT_FP
;
225 case OPT_mieee_with_inexact
:
226 target_flags
|= MASK_IEEE_CONFORMANT
;
230 if (value
!= 16 && value
!= 32 && value
!= 64)
231 error ("bad value %qs for -mtls-size switch", arg
);
238 /* Parse target option strings. */
241 override_options (void)
243 static const struct cpu_table
{
244 const char *const name
;
245 const enum processor_type processor
;
248 { "ev4", PROCESSOR_EV4
, 0 },
249 { "ev45", PROCESSOR_EV4
, 0 },
250 { "21064", PROCESSOR_EV4
, 0 },
251 { "ev5", PROCESSOR_EV5
, 0 },
252 { "21164", PROCESSOR_EV5
, 0 },
253 { "ev56", PROCESSOR_EV5
, MASK_BWX
},
254 { "21164a", PROCESSOR_EV5
, MASK_BWX
},
255 { "pca56", PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
256 { "21164PC",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
257 { "21164pc",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
258 { "ev6", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
259 { "21264", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
260 { "ev67", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
261 { "21264a", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
267 /* Unicos/Mk doesn't have shared libraries. */
268 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
270 warning (0, "-f%s ignored for Unicos/Mk (not supported)",
271 (flag_pic
> 1) ? "PIC" : "pic");
275 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
276 floating-point instructions. Make that the default for this target. */
277 if (TARGET_ABI_UNICOSMK
)
278 alpha_fprm
= ALPHA_FPRM_DYN
;
280 alpha_fprm
= ALPHA_FPRM_NORM
;
282 alpha_tp
= ALPHA_TP_PROG
;
283 alpha_fptm
= ALPHA_FPTM_N
;
285 /* We cannot use su and sui qualifiers for conversion instructions on
286 Unicos/Mk. I'm not sure if this is due to assembler or hardware
287 limitations. Right now, we issue a warning if -mieee is specified
288 and then ignore it; eventually, we should either get it right or
289 disable the option altogether. */
293 if (TARGET_ABI_UNICOSMK
)
294 warning (0, "-mieee not supported on Unicos/Mk");
297 alpha_tp
= ALPHA_TP_INSN
;
298 alpha_fptm
= ALPHA_FPTM_SU
;
302 if (TARGET_IEEE_WITH_INEXACT
)
304 if (TARGET_ABI_UNICOSMK
)
305 warning (0, "-mieee-with-inexact not supported on Unicos/Mk");
308 alpha_tp
= ALPHA_TP_INSN
;
309 alpha_fptm
= ALPHA_FPTM_SUI
;
315 if (! strcmp (alpha_tp_string
, "p"))
316 alpha_tp
= ALPHA_TP_PROG
;
317 else if (! strcmp (alpha_tp_string
, "f"))
318 alpha_tp
= ALPHA_TP_FUNC
;
319 else if (! strcmp (alpha_tp_string
, "i"))
320 alpha_tp
= ALPHA_TP_INSN
;
322 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string
);
325 if (alpha_fprm_string
)
327 if (! strcmp (alpha_fprm_string
, "n"))
328 alpha_fprm
= ALPHA_FPRM_NORM
;
329 else if (! strcmp (alpha_fprm_string
, "m"))
330 alpha_fprm
= ALPHA_FPRM_MINF
;
331 else if (! strcmp (alpha_fprm_string
, "c"))
332 alpha_fprm
= ALPHA_FPRM_CHOP
;
333 else if (! strcmp (alpha_fprm_string
,"d"))
334 alpha_fprm
= ALPHA_FPRM_DYN
;
336 error ("bad value %qs for -mfp-rounding-mode switch",
340 if (alpha_fptm_string
)
342 if (strcmp (alpha_fptm_string
, "n") == 0)
343 alpha_fptm
= ALPHA_FPTM_N
;
344 else if (strcmp (alpha_fptm_string
, "u") == 0)
345 alpha_fptm
= ALPHA_FPTM_U
;
346 else if (strcmp (alpha_fptm_string
, "su") == 0)
347 alpha_fptm
= ALPHA_FPTM_SU
;
348 else if (strcmp (alpha_fptm_string
, "sui") == 0)
349 alpha_fptm
= ALPHA_FPTM_SUI
;
351 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string
);
354 if (alpha_cpu_string
)
356 for (i
= 0; cpu_table
[i
].name
; i
++)
357 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
359 alpha_tune
= alpha_cpu
= cpu_table
[i
].processor
;
360 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
);
361 target_flags
|= cpu_table
[i
].flags
;
364 if (! cpu_table
[i
].name
)
365 error ("bad value %qs for -mcpu switch", alpha_cpu_string
);
368 if (alpha_tune_string
)
370 for (i
= 0; cpu_table
[i
].name
; i
++)
371 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
373 alpha_tune
= cpu_table
[i
].processor
;
376 if (! cpu_table
[i
].name
)
377 error ("bad value %qs for -mcpu switch", alpha_tune_string
);
380 /* Do some sanity checks on the above options. */
382 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
384 warning (0, "trap mode not supported on Unicos/Mk");
385 alpha_fptm
= ALPHA_FPTM_N
;
388 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
389 && alpha_tp
!= ALPHA_TP_INSN
&& alpha_cpu
!= PROCESSOR_EV6
)
391 warning (0, "fp software completion requires -mtrap-precision=i");
392 alpha_tp
= ALPHA_TP_INSN
;
395 if (alpha_cpu
== PROCESSOR_EV6
)
397 /* Except for EV6 pass 1 (not released), we always have precise
398 arithmetic traps. Which means we can do software completion
399 without minding trap shadows. */
400 alpha_tp
= ALPHA_TP_PROG
;
403 if (TARGET_FLOAT_VAX
)
405 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
407 warning (0, "rounding mode not supported for VAX floats");
408 alpha_fprm
= ALPHA_FPRM_NORM
;
410 if (alpha_fptm
== ALPHA_FPTM_SUI
)
412 warning (0, "trap mode not supported for VAX floats");
413 alpha_fptm
= ALPHA_FPTM_SU
;
415 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
416 warning (0, "128-bit long double not supported for VAX floats");
417 target_flags
&= ~MASK_LONG_DOUBLE_128
;
424 if (!alpha_mlat_string
)
425 alpha_mlat_string
= "L1";
427 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
428 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
430 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
431 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
432 && alpha_mlat_string
[2] == '\0')
434 static int const cache_latency
[][4] =
436 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
437 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
438 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
441 lat
= alpha_mlat_string
[1] - '0';
442 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_tune
][lat
-1] == -1)
444 warning (0, "L%d cache latency unknown for %s",
445 lat
, alpha_cpu_name
[alpha_tune
]);
449 lat
= cache_latency
[alpha_tune
][lat
-1];
451 else if (! strcmp (alpha_mlat_string
, "main"))
453 /* Most current memories have about 370ns latency. This is
454 a reasonable guess for a fast cpu. */
459 warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string
);
463 alpha_memory_latency
= lat
;
466 /* Default the definition of "small data" to 8 bytes. */
470 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
472 target_flags
|= MASK_SMALL_DATA
;
473 else if (flag_pic
== 2)
474 target_flags
&= ~MASK_SMALL_DATA
;
476 /* Align labels and loops for optimal branching. */
477 /* ??? Kludge these by not doing anything if we don't optimize and also if
478 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
479 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
481 if (align_loops
<= 0)
483 if (align_jumps
<= 0)
486 if (align_functions
<= 0)
487 align_functions
= 16;
489 /* Acquire a unique set number for our register saves and restores. */
490 alpha_sr_alias_set
= new_alias_set ();
492 /* Register variables and functions with the garbage collector. */
494 /* Set up function hooks. */
495 init_machine_status
= alpha_init_machine_status
;
497 /* Tell the compiler when we're using VAX floating point. */
498 if (TARGET_FLOAT_VAX
)
500 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
501 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
502 REAL_MODE_FORMAT (TFmode
) = NULL
;
506 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
509 zap_mask (HOST_WIDE_INT value
)
513 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
515 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
521 /* Return true if OP is valid for a particular TLS relocation.
522 We are already guaranteed that OP is a CONST. */
525 tls_symbolic_operand_1 (rtx op
, int size
, int unspec
)
529 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
531 op
= XVECEXP (op
, 0, 0);
533 if (GET_CODE (op
) != SYMBOL_REF
)
536 if (SYMBOL_REF_LOCAL_P (op
))
538 if (alpha_tls_size
> size
)
547 switch (SYMBOL_REF_TLS_MODEL (op
))
549 case TLS_MODEL_LOCAL_DYNAMIC
:
550 return unspec
== UNSPEC_DTPREL
;
551 case TLS_MODEL_INITIAL_EXEC
:
552 return unspec
== UNSPEC_TPREL
&& size
== 64;
553 case TLS_MODEL_LOCAL_EXEC
:
554 return unspec
== UNSPEC_TPREL
;
560 /* Used by aligned_memory_operand and unaligned_memory_operand to
561 resolve what reload is going to do with OP if it's a register. */
564 resolve_reload_operand (rtx op
)
566 if (reload_in_progress
)
569 if (GET_CODE (tmp
) == SUBREG
)
570 tmp
= SUBREG_REG (tmp
);
571 if (GET_CODE (tmp
) == REG
572 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
574 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
582 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
583 the range defined for C in [I-P]. */
586 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
591 /* An unsigned 8 bit constant. */
592 return (unsigned HOST_WIDE_INT
) value
< 0x100;
594 /* The constant zero. */
597 /* A signed 16 bit constant. */
598 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
600 /* A shifted signed 16 bit constant appropriate for LDAH. */
601 return ((value
& 0xffff) == 0
602 && ((value
) >> 31 == -1 || value
>> 31 == 0));
604 /* A constant that can be AND'ed with using a ZAP insn. */
605 return zap_mask (value
);
607 /* A complemented unsigned 8 bit constant. */
608 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
610 /* A negated unsigned 8 bit constant. */
611 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
613 /* The constant 1, 2 or 3. */
614 return value
== 1 || value
== 2 || value
== 3;
621 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
622 matches for C in [GH]. */
625 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
630 /* The floating point zero constant. */
631 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
632 && value
== CONST0_RTX (GET_MODE (value
)));
635 /* A valid operand of a ZAP insn. */
636 return (GET_MODE (value
) == VOIDmode
637 && zap_mask (CONST_DOUBLE_LOW (value
))
638 && zap_mask (CONST_DOUBLE_HIGH (value
)));
645 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
649 alpha_extra_constraint (rtx value
, int c
)
654 return normal_memory_operand (value
, VOIDmode
);
656 return direct_call_operand (value
, Pmode
);
658 return (GET_CODE (value
) == CONST_INT
659 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
661 return GET_CODE (value
) == HIGH
;
663 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
665 return (GET_CODE (value
) == CONST_VECTOR
666 && value
== CONST0_RTX (GET_MODE (value
)));
672 /* The scalar modes supported differs from the default check-what-c-supports
673 version in that sometimes TFmode is available even when long double
674 indicates only DFmode. On unicosmk, we have the situation that HImode
675 doesn't map to any C type, but of course we still support that. */
678 alpha_scalar_mode_supported_p (enum machine_mode mode
)
686 case TImode
: /* via optabs.c */
694 return TARGET_HAS_XFLOATING_LIBS
;
701 /* Alpha implements a couple of integer vector mode operations when
702 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
703 which allows the vectorizer to operate on e.g. move instructions,
704 or when expand_vector_operations can do something useful. */
707 alpha_vector_mode_supported_p (enum machine_mode mode
)
709 return mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
;
712 /* Return 1 if this function can directly return via $26. */
717 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
719 && alpha_sa_size () == 0
720 && get_frame_size () == 0
721 && current_function_outgoing_args_size
== 0
722 && current_function_pretend_args_size
== 0);
725 /* Return the ADDR_VEC associated with a tablejump insn. */
728 alpha_tablejump_addr_vec (rtx insn
)
732 tmp
= JUMP_LABEL (insn
);
735 tmp
= NEXT_INSN (tmp
);
738 if (GET_CODE (tmp
) == JUMP_INSN
739 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
740 return PATTERN (tmp
);
744 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
747 alpha_tablejump_best_label (rtx insn
)
749 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
750 rtx best_label
= NULL_RTX
;
752 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
753 there for edge frequency counts from profile data. */
757 int n_labels
= XVECLEN (jump_table
, 1);
761 for (i
= 0; i
< n_labels
; i
++)
765 for (j
= i
+ 1; j
< n_labels
; j
++)
766 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
767 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
770 if (count
> best_count
)
771 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
775 return best_label
? best_label
: const0_rtx
;
778 /* Return the TLS model to use for SYMBOL. */
780 static enum tls_model
781 tls_symbolic_operand_type (rtx symbol
)
783 enum tls_model model
;
785 if (GET_CODE (symbol
) != SYMBOL_REF
)
787 model
= SYMBOL_REF_TLS_MODEL (symbol
);
789 /* Local-exec with a 64-bit size is the same code as initial-exec. */
790 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
791 model
= TLS_MODEL_INITIAL_EXEC
;
796 /* Return true if the function DECL will share the same GP as any
797 function in the current unit of translation. */
800 decl_has_samegp (tree decl
)
802 /* Functions that are not local can be overridden, and thus may
803 not share the same gp. */
804 if (!(*targetm
.binds_local_p
) (decl
))
807 /* If -msmall-data is in effect, assume that there is only one GP
808 for the module, and so any local symbol has this property. We
809 need explicit relocations to be able to enforce this for symbols
810 not defined in this unit of translation, however. */
811 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
814 /* Functions that are not external are defined in this UoT. */
815 /* ??? Irritatingly, static functions not yet emitted are still
816 marked "external". Apply this to non-static functions only. */
817 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
820 /* Return true if EXP should be placed in the small data section. */
823 alpha_in_small_data_p (tree exp
)
825 /* We want to merge strings, so we never consider them small data. */
826 if (TREE_CODE (exp
) == STRING_CST
)
829 /* Functions are never in the small data area. Duh. */
830 if (TREE_CODE (exp
) == FUNCTION_DECL
)
833 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
835 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
836 if (strcmp (section
, ".sdata") == 0
837 || strcmp (section
, ".sbss") == 0)
842 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
844 /* If this is an incomplete type with size 0, then we can't put it
845 in sdata because it might be too big when completed. */
846 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
853 #if TARGET_ABI_OPEN_VMS
855 alpha_linkage_symbol_p (const char *symname
)
857 int symlen
= strlen (symname
);
860 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
865 #define LINKAGE_SYMBOL_REF_P(X) \
866 ((GET_CODE (X) == SYMBOL_REF \
867 && alpha_linkage_symbol_p (XSTR (X, 0))) \
868 || (GET_CODE (X) == CONST \
869 && GET_CODE (XEXP (X, 0)) == PLUS \
870 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
871 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
874 /* legitimate_address_p recognizes an RTL expression that is a valid
875 memory address for an instruction. The MODE argument is the
876 machine mode for the MEM expression that wants to use this address.
878 For Alpha, we have either a constant address or the sum of a
879 register and a constant address, or just a register. For DImode,
880 any of those forms can be surrounded with an AND that clear the
881 low-order three bits; this is an "unaligned" access. */
884 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
886 /* If this is an ldq_u type address, discard the outer AND. */
888 && GET_CODE (x
) == AND
889 && GET_CODE (XEXP (x
, 1)) == CONST_INT
890 && INTVAL (XEXP (x
, 1)) == -8)
893 /* Discard non-paradoxical subregs. */
894 if (GET_CODE (x
) == SUBREG
895 && (GET_MODE_SIZE (GET_MODE (x
))
896 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
899 /* Unadorned general registers are valid. */
902 ? STRICT_REG_OK_FOR_BASE_P (x
)
903 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
906 /* Constant addresses (i.e. +/- 32k) are valid. */
907 if (CONSTANT_ADDRESS_P (x
))
910 #if TARGET_ABI_OPEN_VMS
911 if (LINKAGE_SYMBOL_REF_P (x
))
915 /* Register plus a small constant offset is valid. */
916 if (GET_CODE (x
) == PLUS
)
918 rtx ofs
= XEXP (x
, 1);
921 /* Discard non-paradoxical subregs. */
922 if (GET_CODE (x
) == SUBREG
923 && (GET_MODE_SIZE (GET_MODE (x
))
924 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
930 && NONSTRICT_REG_OK_FP_BASE_P (x
)
931 && GET_CODE (ofs
) == CONST_INT
)
934 ? STRICT_REG_OK_FOR_BASE_P (x
)
935 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
936 && CONSTANT_ADDRESS_P (ofs
))
941 /* If we're managing explicit relocations, LO_SUM is valid, as
942 are small data symbols. */
943 else if (TARGET_EXPLICIT_RELOCS
)
945 if (small_symbolic_operand (x
, Pmode
))
948 if (GET_CODE (x
) == LO_SUM
)
950 rtx ofs
= XEXP (x
, 1);
953 /* Discard non-paradoxical subregs. */
954 if (GET_CODE (x
) == SUBREG
955 && (GET_MODE_SIZE (GET_MODE (x
))
956 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
959 /* Must have a valid base register. */
962 ? STRICT_REG_OK_FOR_BASE_P (x
)
963 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
966 /* The symbol must be local. */
967 if (local_symbolic_operand (ofs
, Pmode
)
968 || dtp32_symbolic_operand (ofs
, Pmode
)
969 || tp32_symbolic_operand (ofs
, Pmode
))
977 /* Build the SYMBOL_REF for __tls_get_addr. */
979 static GTY(()) rtx tls_get_addr_libfunc
;
982 get_tls_get_addr (void)
984 if (!tls_get_addr_libfunc
)
985 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
986 return tls_get_addr_libfunc
;
989 /* Try machine-dependent ways of modifying an illegitimate address
990 to be legitimate. If we find one, return the new, valid address. */
993 alpha_legitimize_address (rtx x
, rtx scratch
,
994 enum machine_mode mode ATTRIBUTE_UNUSED
)
996 HOST_WIDE_INT addend
;
998 /* If the address is (plus reg const_int) and the CONST_INT is not a
999 valid offset, compute the high part of the constant and add it to
1000 the register. Then our address is (plus temp low-part-const). */
1001 if (GET_CODE (x
) == PLUS
1002 && GET_CODE (XEXP (x
, 0)) == REG
1003 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1004 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1006 addend
= INTVAL (XEXP (x
, 1));
1011 /* If the address is (const (plus FOO const_int)), find the low-order
1012 part of the CONST_INT. Then load FOO plus any high-order part of the
1013 CONST_INT into a register. Our address is (plus reg low-part-const).
1014 This is done to reduce the number of GOT entries. */
1016 && GET_CODE (x
) == CONST
1017 && GET_CODE (XEXP (x
, 0)) == PLUS
1018 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1020 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1021 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1025 /* If we have a (plus reg const), emit the load as in (2), then add
1026 the two registers, and finally generate (plus reg low-part-const) as
1029 && GET_CODE (x
) == PLUS
1030 && GET_CODE (XEXP (x
, 0)) == REG
1031 && GET_CODE (XEXP (x
, 1)) == CONST
1032 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1033 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1035 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1036 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1037 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1038 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1042 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1043 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1045 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1047 switch (tls_symbolic_operand_type (x
))
1049 case TLS_MODEL_NONE
:
1052 case TLS_MODEL_GLOBAL_DYNAMIC
:
1055 r0
= gen_rtx_REG (Pmode
, 0);
1056 r16
= gen_rtx_REG (Pmode
, 16);
1057 tga
= get_tls_get_addr ();
1058 dest
= gen_reg_rtx (Pmode
);
1059 seq
= GEN_INT (alpha_next_sequence_number
++);
1061 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1062 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1063 insn
= emit_call_insn (insn
);
1064 CONST_OR_PURE_CALL_P (insn
) = 1;
1065 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1067 insn
= get_insns ();
1070 emit_libcall_block (insn
, dest
, r0
, x
);
1073 case TLS_MODEL_LOCAL_DYNAMIC
:
1076 r0
= gen_rtx_REG (Pmode
, 0);
1077 r16
= gen_rtx_REG (Pmode
, 16);
1078 tga
= get_tls_get_addr ();
1079 scratch
= gen_reg_rtx (Pmode
);
1080 seq
= GEN_INT (alpha_next_sequence_number
++);
1082 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1083 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1084 insn
= emit_call_insn (insn
);
1085 CONST_OR_PURE_CALL_P (insn
) = 1;
1086 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1088 insn
= get_insns ();
1091 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1092 UNSPEC_TLSLDM_CALL
);
1093 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1095 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1096 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1098 if (alpha_tls_size
== 64)
1100 dest
= gen_reg_rtx (Pmode
);
1101 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1102 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1105 if (alpha_tls_size
== 32)
1107 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1108 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1109 scratch
= gen_reg_rtx (Pmode
);
1110 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1112 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1114 case TLS_MODEL_INITIAL_EXEC
:
1115 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1116 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1117 tp
= gen_reg_rtx (Pmode
);
1118 scratch
= gen_reg_rtx (Pmode
);
1119 dest
= gen_reg_rtx (Pmode
);
1121 emit_insn (gen_load_tp (tp
));
1122 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1123 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1126 case TLS_MODEL_LOCAL_EXEC
:
1127 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1128 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1129 tp
= gen_reg_rtx (Pmode
);
1131 emit_insn (gen_load_tp (tp
));
1132 if (alpha_tls_size
== 32)
1134 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1135 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1136 tp
= gen_reg_rtx (Pmode
);
1137 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1139 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1145 if (local_symbolic_operand (x
, Pmode
))
1147 if (small_symbolic_operand (x
, Pmode
))
1151 if (!no_new_pseudos
)
1152 scratch
= gen_reg_rtx (Pmode
);
1153 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1154 gen_rtx_HIGH (Pmode
, x
)));
1155 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1164 HOST_WIDE_INT low
, high
;
1166 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1168 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1172 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1173 (no_new_pseudos
? scratch
: NULL_RTX
),
1174 1, OPTAB_LIB_WIDEN
);
1176 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1177 (no_new_pseudos
? scratch
: NULL_RTX
),
1178 1, OPTAB_LIB_WIDEN
);
1180 return plus_constant (x
, low
);
1184 /* Primarily this is required for TLS symbols, but given that our move
1185 patterns *ought* to be able to handle any symbol at any time, we
1186 should never be spilling symbolic operands to the constant pool, ever. */
1189 alpha_cannot_force_const_mem (rtx x
)
1191 enum rtx_code code
= GET_CODE (x
);
1192 return code
== SYMBOL_REF
|| code
== LABEL_REF
|| code
== CONST
;
1195 /* We do not allow indirect calls to be optimized into sibling calls, nor
1196 can we allow a call to a function with a different GP to be optimized
1200 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1202 /* Can't do indirect tail calls, since we don't know if the target
1203 uses the same GP. */
1207 /* Otherwise, we can make a tail call if the target function shares
1209 return decl_has_samegp (decl
);
1213 some_small_symbolic_operand_int (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1217 /* Don't re-split. */
1218 if (GET_CODE (x
) == LO_SUM
)
1221 return small_symbolic_operand (x
, Pmode
) != 0;
1225 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1229 /* Don't re-split. */
1230 if (GET_CODE (x
) == LO_SUM
)
1233 if (small_symbolic_operand (x
, Pmode
))
1235 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1244 split_small_symbolic_operand (rtx x
)
1247 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1251 /* Indicate that INSN cannot be duplicated. This is true for any insn
1252 that we've marked with gpdisp relocs, since those have to stay in
1253 1-1 correspondence with one another.
1255 Technically we could copy them if we could set up a mapping from one
1256 sequence number to another, across the set of insns to be duplicated.
1257 This seems overly complicated and error-prone since interblock motion
1258 from sched-ebb could move one of the pair of insns to a different block.
1260 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1261 then they'll be in a different block from their ldgp. Which could lead
1262 the bb reorder code to think that it would be ok to copy just the block
1263 containing the call and branch to the block containing the ldgp. */
1266 alpha_cannot_copy_insn_p (rtx insn
)
1268 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
1270 if (recog_memoized (insn
) >= 0)
1271 return get_attr_cannot_copy (insn
);
1277 /* Try a machine-dependent way of reloading an illegitimate address
1278 operand. If we find one, push the reload and return the new rtx. */
1281 alpha_legitimize_reload_address (rtx x
,
1282 enum machine_mode mode ATTRIBUTE_UNUSED
,
1283 int opnum
, int type
,
1284 int ind_levels ATTRIBUTE_UNUSED
)
1286 /* We must recognize output that we have already generated ourselves. */
1287 if (GET_CODE (x
) == PLUS
1288 && GET_CODE (XEXP (x
, 0)) == PLUS
1289 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1290 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1291 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1293 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1294 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1299 /* We wish to handle large displacements off a base register by
1300 splitting the addend across an ldah and the mem insn. This
1301 cuts number of extra insns needed from 3 to 1. */
1302 if (GET_CODE (x
) == PLUS
1303 && GET_CODE (XEXP (x
, 0)) == REG
1304 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1305 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1306 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1308 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1309 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1311 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1313 /* Check for 32-bit overflow. */
1314 if (high
+ low
!= val
)
1317 /* Reload the high part into a base reg; leave the low part
1318 in the mem directly. */
1319 x
= gen_rtx_PLUS (GET_MODE (x
),
1320 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1324 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1325 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1333 /* Compute a (partial) cost for rtx X. Return true if the complete
1334 cost has been computed, and false if subexpressions should be
1335 scanned. In either case, *TOTAL contains the cost result. */
1338 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1340 enum machine_mode mode
= GET_MODE (x
);
1341 bool float_mode_p
= FLOAT_MODE_P (mode
);
1342 const struct alpha_rtx_cost_data
*cost_data
;
1345 cost_data
= &alpha_rtx_cost_size
;
1347 cost_data
= &alpha_rtx_cost_data
[alpha_tune
];
1352 /* If this is an 8-bit constant, return zero since it can be used
1353 nearly anywhere with no cost. If it is a valid operand for an
1354 ADD or AND, likewise return 0 if we know it will be used in that
1355 context. Otherwise, return 2 since it might be used there later.
1356 All other constants take at least two insns. */
1357 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
1365 if (x
== CONST0_RTX (mode
))
1367 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
1368 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
1370 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
1373 *total
= COSTS_N_INSNS (2);
1379 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
1380 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
1381 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
1382 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
1383 else if (tls_symbolic_operand_type (x
))
1384 /* Estimate of cost for call_pal rduniq. */
1385 /* ??? How many insns do we emit here? More than one... */
1386 *total
= COSTS_N_INSNS (15);
1388 /* Otherwise we do a load from the GOT. */
1389 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1393 /* This is effectively an add_operand. */
1400 *total
= cost_data
->fp_add
;
1401 else if (GET_CODE (XEXP (x
, 0)) == MULT
1402 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
1404 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
1405 + rtx_cost (XEXP (x
, 1), outer_code
) + COSTS_N_INSNS (1));
1412 *total
= cost_data
->fp_mult
;
1413 else if (mode
== DImode
)
1414 *total
= cost_data
->int_mult_di
;
1416 *total
= cost_data
->int_mult_si
;
1420 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1421 && INTVAL (XEXP (x
, 1)) <= 3)
1423 *total
= COSTS_N_INSNS (1);
1430 *total
= cost_data
->int_shift
;
1435 *total
= cost_data
->fp_add
;
1437 *total
= cost_data
->int_cmov
;
1445 *total
= cost_data
->int_div
;
1446 else if (mode
== SFmode
)
1447 *total
= cost_data
->fp_div_sf
;
1449 *total
= cost_data
->fp_div_df
;
1453 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1459 *total
= COSTS_N_INSNS (1);
1467 *total
= COSTS_N_INSNS (1) + cost_data
->int_cmov
;
1473 case UNSIGNED_FLOAT
:
1477 case FLOAT_TRUNCATE
:
1478 *total
= cost_data
->fp_add
;
1486 /* REF is an alignable memory location. Place an aligned SImode
1487 reference into *PALIGNED_MEM and the number of bits to shift into
1488 *PBITNUM. SCRATCH is a free register for use in reloading out
1489 of range stack slots. */
1492 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
1495 HOST_WIDE_INT offset
= 0;
1497 gcc_assert (GET_CODE (ref
) == MEM
);
1499 if (reload_in_progress
1500 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1502 base
= find_replacement (&XEXP (ref
, 0));
1504 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1507 base
= XEXP (ref
, 0);
1509 if (GET_CODE (base
) == PLUS
)
1510 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1513 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
1515 if (WORDS_BIG_ENDIAN
)
1516 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
1517 + (offset
& 3) * 8));
1519 *pbitnum
= GEN_INT ((offset
& 3) * 8);
1522 /* Similar, but just get the address. Handle the two reload cases.
1523 Add EXTRA_OFFSET to the address we return. */
1526 get_unaligned_address (rtx ref
, int extra_offset
)
1529 HOST_WIDE_INT offset
= 0;
1531 gcc_assert (GET_CODE (ref
) == MEM
);
1533 if (reload_in_progress
1534 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1536 base
= find_replacement (&XEXP (ref
, 0));
1538 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1541 base
= XEXP (ref
, 0);
1543 if (GET_CODE (base
) == PLUS
)
1544 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1546 return plus_constant (base
, offset
+ extra_offset
);
1549 /* On the Alpha, all (non-symbolic) constants except zero go into
1550 a floating-point register via memory. Note that we cannot
1551 return anything that is not a subset of CLASS, and that some
1552 symbolic constants cannot be dropped to memory. */
1555 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
1557 /* Zero is present in any register class. */
1558 if (x
== CONST0_RTX (GET_MODE (x
)))
1561 /* These sorts of constants we can easily drop to memory. */
1562 if (GET_CODE (x
) == CONST_INT
1563 || GET_CODE (x
) == CONST_DOUBLE
1564 || GET_CODE (x
) == CONST_VECTOR
)
1566 if (class == FLOAT_REGS
)
1568 if (class == ALL_REGS
)
1569 return GENERAL_REGS
;
1573 /* All other kinds of constants should not (and in the case of HIGH
1574 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1575 secondary reload. */
1577 return (class == ALL_REGS
? GENERAL_REGS
: class);
1582 /* Loading and storing HImode or QImode values to and from memory
1583 usually requires a scratch register. The exceptions are loading
1584 QImode and HImode from an aligned address to a general register
1585 unless byte instructions are permitted.
1587 We also cannot load an unaligned address or a paradoxical SUBREG
1588 into an FP register.
1590 We also cannot do integral arithmetic into FP regs, as might result
1591 from register elimination into a DImode fp register. */
1594 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
1597 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
1599 if (GET_CODE (x
) == MEM
1600 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
1601 || (GET_CODE (x
) == SUBREG
1602 && (GET_CODE (SUBREG_REG (x
)) == MEM
1603 || (GET_CODE (SUBREG_REG (x
)) == REG
1604 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
1606 if (!in
|| !aligned_memory_operand(x
, mode
))
1607 return GENERAL_REGS
;
1611 if (class == FLOAT_REGS
)
1613 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
1614 return GENERAL_REGS
;
1616 if (GET_CODE (x
) == SUBREG
1617 && (GET_MODE_SIZE (GET_MODE (x
))
1618 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1619 return GENERAL_REGS
;
1621 if (in
&& INTEGRAL_MODE_P (mode
)
1622 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
1623 return GENERAL_REGS
;
1629 /* Subfunction of the following function. Update the flags of any MEM
1630 found in part of X. */
1633 alpha_set_memflags_1 (rtx
*xp
, void *data
)
1635 rtx x
= *xp
, orig
= (rtx
) data
;
1637 if (GET_CODE (x
) != MEM
)
1640 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (orig
);
1641 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (orig
);
1642 MEM_SCALAR_P (x
) = MEM_SCALAR_P (orig
);
1643 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (orig
);
1644 MEM_READONLY_P (x
) = MEM_READONLY_P (orig
);
1646 /* Sadly, we cannot use alias sets because the extra aliasing
1647 produced by the AND interferes. Given that two-byte quantities
1648 are the only thing we would be able to differentiate anyway,
1649 there does not seem to be any point in convoluting the early
1650 out of the alias check. */
1655 /* Given INSN, which is an INSN list or the PATTERN of a single insn
1656 generated to perform a memory operation, look for any MEMs in either
1657 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1658 volatile flags from REF into each of the MEMs found. If REF is not
1659 a MEM, don't do anything. */
1662 alpha_set_memflags (rtx insn
, rtx ref
)
1666 if (GET_CODE (ref
) != MEM
)
1669 /* This is only called from alpha.md, after having had something
1670 generated from one of the insn patterns. So if everything is
1671 zero, the pattern is already up-to-date. */
1672 if (!MEM_VOLATILE_P (ref
)
1673 && !MEM_IN_STRUCT_P (ref
)
1674 && !MEM_SCALAR_P (ref
)
1675 && !MEM_NOTRAP_P (ref
)
1676 && !MEM_READONLY_P (ref
))
1680 base_ptr
= &PATTERN (insn
);
1683 for_each_rtx (base_ptr
, alpha_set_memflags_1
, (void *) ref
);
1686 static rtx
alpha_emit_set_const (rtx
, enum machine_mode
, HOST_WIDE_INT
,
1689 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1690 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1691 and return pc_rtx if successful. */
1694 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
1695 HOST_WIDE_INT c
, int n
, bool no_output
)
1699 /* Use a pseudo if highly optimizing and still generating RTL. */
1701 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
1704 /* If this is a sign-extended 32-bit constant, we can do this in at most
1705 three insns, so do it if we have enough insns left. We always have
1706 a sign-extended 32-bit constant when compiling on a narrow machine. */
1708 if (HOST_BITS_PER_WIDE_INT
!= 64
1709 || c
>> 31 == -1 || c
>> 31 == 0)
1711 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1712 HOST_WIDE_INT tmp1
= c
- low
;
1713 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
1714 HOST_WIDE_INT extra
= 0;
1716 /* If HIGH will be interpreted as negative but the constant is
1717 positive, we must adjust it to do two ldha insns. */
1719 if ((high
& 0x8000) != 0 && c
>= 0)
1723 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1726 if (c
== low
|| (low
== 0 && extra
== 0))
1728 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1729 but that meant that we can't handle INT_MIN on 32-bit machines
1730 (like NT/Alpha), because we recurse indefinitely through
1731 emit_move_insn to gen_movdi. So instead, since we know exactly
1732 what we want, create it explicitly. */
1737 target
= gen_reg_rtx (mode
);
1738 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
1741 else if (n
>= 2 + (extra
!= 0))
1747 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
1751 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
1754 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1755 This means that if we go through expand_binop, we'll try to
1756 generate extensions, etc, which will require new pseudos, which
1757 will fail during some split phases. The SImode add patterns
1758 still exist, but are not named. So build the insns by hand. */
1763 subtarget
= gen_reg_rtx (mode
);
1764 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
1765 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
1771 target
= gen_reg_rtx (mode
);
1772 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
1773 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
1779 /* If we couldn't do it that way, try some other methods. But if we have
1780 no instructions left, don't bother. Likewise, if this is SImode and
1781 we can't make pseudos, we can't do anything since the expand_binop
1782 and expand_unop calls will widen and try to make pseudos. */
1784 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
1787 /* Next, see if we can load a related constant and then shift and possibly
1788 negate it to get the constant we want. Try this once each increasing
1789 numbers of insns. */
1791 for (i
= 1; i
< n
; i
++)
1793 /* First, see if minus some low bits, we've an easy load of
1796 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
1799 temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
, no_output
);
1804 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
1805 target
, 0, OPTAB_WIDEN
);
1809 /* Next try complementing. */
1810 temp
= alpha_emit_set_const (subtarget
, mode
, ~c
, i
, no_output
);
1815 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
1818 /* Next try to form a constant and do a left shift. We can do this
1819 if some low-order bits are zero; the exact_log2 call below tells
1820 us that information. The bits we are shifting out could be any
1821 value, but here we'll just try the 0- and sign-extended forms of
1822 the constant. To try to increase the chance of having the same
1823 constant in more than one insn, start at the highest number of
1824 bits to shift, but try all possibilities in case a ZAPNOT will
1827 bits
= exact_log2 (c
& -c
);
1829 for (; bits
> 0; bits
--)
1832 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1835 new = (unsigned HOST_WIDE_INT
)c
>> bits
;
1836 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1843 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
1844 target
, 0, OPTAB_WIDEN
);
1848 /* Now try high-order zero bits. Here we try the shifted-in bits as
1849 all zero and all ones. Be careful to avoid shifting outside the
1850 mode and to avoid shifting outside the host wide int size. */
1851 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1852 confuse the recursive call and set all of the high 32 bits. */
1854 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1855 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64));
1857 for (; bits
> 0; bits
--)
1860 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1863 new = (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1864 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1871 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
1872 target
, 1, OPTAB_WIDEN
);
1876 /* Now try high-order 1 bits. We get that with a sign-extension.
1877 But one bit isn't enough here. Be careful to avoid shifting outside
1878 the mode and to avoid shifting outside the host wide int size. */
1880 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1881 - floor_log2 (~ c
) - 2);
1883 for (; bits
> 0; bits
--)
1886 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1889 new = (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1890 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1897 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
1898 target
, 0, OPTAB_WIDEN
);
1903 #if HOST_BITS_PER_WIDE_INT == 64
1904 /* Finally, see if can load a value into the target that is the same as the
1905 constant except that all bytes that are 0 are changed to be 0xff. If we
1906 can, then we can do a ZAPNOT to obtain the desired constant. */
1909 for (i
= 0; i
< 64; i
+= 8)
1910 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
1911 new |= (HOST_WIDE_INT
) 0xff << i
;
1913 /* We are only called for SImode and DImode. If this is SImode, ensure that
1914 we are sign extended to a full word. */
1917 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
1921 temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1, no_output
);
1926 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
1927 target
, 0, OPTAB_WIDEN
);
1935 /* Try to output insns to set TARGET equal to the constant C if it can be
1936 done in less than N insns. Do all computations in MODE. Returns the place
1937 where the output has been placed if it can be done and the insns have been
1938 emitted. If it would take more than N insns, zero is returned and no
1939 insns and emitted. */
1942 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
1943 HOST_WIDE_INT c
, int n
, bool no_output
)
1945 enum machine_mode orig_mode
= mode
;
1946 rtx orig_target
= target
;
1950 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1951 can't load this constant in one insn, do this in DImode. */
1952 if (no_new_pseudos
&& mode
== SImode
1953 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
)
1955 result
= alpha_emit_set_const_1 (target
, mode
, c
, 1, no_output
);
1959 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1962 else if (mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
)
1964 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1968 /* Try 1 insn, then 2, then up to N. */
1969 for (i
= 1; i
<= n
; i
++)
1971 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
, no_output
);
1979 insn
= get_last_insn ();
1980 set
= single_set (insn
);
1981 if (! CONSTANT_P (SET_SRC (set
)))
1982 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
1987 /* Allow for the case where we changed the mode of TARGET. */
1990 if (result
== target
)
1991 result
= orig_target
;
1992 else if (mode
!= orig_mode
)
1993 result
= gen_lowpart (orig_mode
, result
);
1999 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2000 fall back to a straight forward decomposition. We do this to avoid
2001 exponential run times encountered when looking for longer sequences
2002 with alpha_emit_set_const. */
2005 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2007 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2009 /* Decompose the entire word */
2010 #if HOST_BITS_PER_WIDE_INT >= 64
2011 gcc_assert (c2
== -(c1
< 0));
2012 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2014 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2015 c1
= (c1
- d2
) >> 32;
2016 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2018 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2019 gcc_assert (c1
== d4
);
2021 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2023 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2024 gcc_assert (c1
== d2
);
2026 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2028 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2029 gcc_assert (c2
== d4
);
2032 /* Construct the high word */
2035 emit_move_insn (target
, GEN_INT (d4
));
2037 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2040 emit_move_insn (target
, GEN_INT (d3
));
2042 /* Shift it into place */
2043 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2045 /* Add in the low bits. */
2047 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2049 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2054 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
2058 alpha_extract_integer (rtx x
, HOST_WIDE_INT
*p0
, HOST_WIDE_INT
*p1
)
2060 HOST_WIDE_INT i0
, i1
;
2062 if (GET_CODE (x
) == CONST_VECTOR
)
2063 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
2066 if (GET_CODE (x
) == CONST_INT
)
2071 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2073 i0
= CONST_DOUBLE_LOW (x
);
2078 i0
= CONST_DOUBLE_LOW (x
);
2079 i1
= CONST_DOUBLE_HIGH (x
);
2086 /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
2087 are willing to load the value into a register via a move pattern.
2088 Normally this is all symbolic constants, integral constants that
2089 take three or fewer instructions, and floating-point zero. */
2092 alpha_legitimate_constant_p (rtx x
)
2094 enum machine_mode mode
= GET_MODE (x
);
2095 HOST_WIDE_INT i0
, i1
;
2097 switch (GET_CODE (x
))
2106 if (x
== CONST0_RTX (mode
))
2108 if (FLOAT_MODE_P (mode
))
2113 if (x
== CONST0_RTX (mode
))
2115 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2117 if (GET_MODE_SIZE (mode
) != 8)
2123 if (TARGET_BUILD_CONSTANTS
)
2125 alpha_extract_integer (x
, &i0
, &i1
);
2126 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== (-i0
< 0))
2127 return alpha_emit_set_const_1 (x
, mode
, i0
, 3, true) != NULL
;
2135 /* Operand 1 is known to be a constant, and should require more than one
2136 instruction to load. Emit that multi-part load. */
2139 alpha_split_const_mov (enum machine_mode mode
, rtx
*operands
)
2141 HOST_WIDE_INT i0
, i1
;
2142 rtx temp
= NULL_RTX
;
2144 alpha_extract_integer (operands
[1], &i0
, &i1
);
2146 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2147 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3, false);
2149 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2150 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2154 if (!rtx_equal_p (operands
[0], temp
))
2155 emit_move_insn (operands
[0], temp
);
2162 /* Expand a move instruction; return true if all work is done.
2163 We don't handle non-bwx subword loads here. */
2166 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2168 /* If the output is not a register, the input must be. */
2169 if (GET_CODE (operands
[0]) == MEM
2170 && ! reg_or_0_operand (operands
[1], mode
))
2171 operands
[1] = force_reg (mode
, operands
[1]);
2173 /* Allow legitimize_address to perform some simplifications. */
2174 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2178 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2181 if (tmp
== operands
[0])
2188 /* Early out for non-constants and valid constants. */
2189 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2192 /* Split large integers. */
2193 if (GET_CODE (operands
[1]) == CONST_INT
2194 || GET_CODE (operands
[1]) == CONST_DOUBLE
2195 || GET_CODE (operands
[1]) == CONST_VECTOR
)
2197 if (alpha_split_const_mov (mode
, operands
))
2201 /* Otherwise we've nothing left but to drop the thing to memory. */
2202 operands
[1] = force_const_mem (mode
, operands
[1]);
2203 if (reload_in_progress
)
2205 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2206 operands
[1] = copy_rtx (operands
[1]);
2207 XEXP (operands
[1], 0) = operands
[0];
2210 operands
[1] = validize_mem (operands
[1]);
2214 /* Expand a non-bwx QImode or HImode move instruction;
2215 return true if all work is done. */
2218 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2220 /* If the output is not a register, the input must be. */
2221 if (GET_CODE (operands
[0]) == MEM
)
2222 operands
[1] = force_reg (mode
, operands
[1]);
2224 /* Handle four memory cases, unaligned and aligned for either the input
2225 or the output. The only case where we can be called during reload is
2226 for aligned loads; all other cases require temporaries. */
2228 if (GET_CODE (operands
[1]) == MEM
2229 || (GET_CODE (operands
[1]) == SUBREG
2230 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2231 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2232 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2233 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2234 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2235 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2237 if (aligned_memory_operand (operands
[1], mode
))
2239 if (reload_in_progress
)
2241 emit_insn ((mode
== QImode
2242 ? gen_reload_inqi_help
2243 : gen_reload_inhi_help
)
2244 (operands
[0], operands
[1],
2245 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2249 rtx aligned_mem
, bitnum
;
2250 rtx scratch
= gen_reg_rtx (SImode
);
2254 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2256 subtarget
= operands
[0];
2257 if (GET_CODE (subtarget
) == REG
)
2258 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2260 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2262 emit_insn ((mode
== QImode
2263 ? gen_aligned_loadqi
2264 : gen_aligned_loadhi
)
2265 (subtarget
, aligned_mem
, bitnum
, scratch
));
2268 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2273 /* Don't pass these as parameters since that makes the generated
2274 code depend on parameter evaluation order which will cause
2275 bootstrap failures. */
2277 rtx temp1
, temp2
, seq
, subtarget
;
2280 temp1
= gen_reg_rtx (DImode
);
2281 temp2
= gen_reg_rtx (DImode
);
2283 subtarget
= operands
[0];
2284 if (GET_CODE (subtarget
) == REG
)
2285 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2287 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2289 seq
= ((mode
== QImode
2290 ? gen_unaligned_loadqi
2291 : gen_unaligned_loadhi
)
2292 (subtarget
, get_unaligned_address (operands
[1], 0),
2294 alpha_set_memflags (seq
, operands
[1]);
2298 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2303 if (GET_CODE (operands
[0]) == MEM
2304 || (GET_CODE (operands
[0]) == SUBREG
2305 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2306 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2307 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2308 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2309 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2310 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2312 if (aligned_memory_operand (operands
[0], mode
))
2314 rtx aligned_mem
, bitnum
;
2315 rtx temp1
= gen_reg_rtx (SImode
);
2316 rtx temp2
= gen_reg_rtx (SImode
);
2318 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2320 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2325 rtx temp1
= gen_reg_rtx (DImode
);
2326 rtx temp2
= gen_reg_rtx (DImode
);
2327 rtx temp3
= gen_reg_rtx (DImode
);
2328 rtx seq
= ((mode
== QImode
2329 ? gen_unaligned_storeqi
2330 : gen_unaligned_storehi
)
2331 (get_unaligned_address (operands
[0], 0),
2332 operands
[1], temp1
, temp2
, temp3
));
2334 alpha_set_memflags (seq
, operands
[0]);
2343 /* Implement the movmisalign patterns. One of the operands is a memory
2344 that is not naturally aligned. Emit instructions to load it. */
2347 alpha_expand_movmisalign (enum machine_mode mode
, rtx
*operands
)
2349 /* Honor misaligned loads, for those we promised to do so. */
2350 if (MEM_P (operands
[1]))
2354 if (register_operand (operands
[0], mode
))
2357 tmp
= gen_reg_rtx (mode
);
2359 alpha_expand_unaligned_load (tmp
, operands
[1], 8, 0, 0);
2360 if (tmp
!= operands
[0])
2361 emit_move_insn (operands
[0], tmp
);
2363 else if (MEM_P (operands
[0]))
2365 if (!reg_or_0_operand (operands
[1], mode
))
2366 operands
[1] = force_reg (mode
, operands
[1]);
2367 alpha_expand_unaligned_store (operands
[0], operands
[1], 8, 0);
2373 /* Generate an unsigned DImode to FP conversion. This is the same code
2374 optabs would emit if we didn't have TFmode patterns.
2376 For SFmode, this is the only construction I've found that can pass
2377 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2378 intermediates will work, because you'll get intermediate rounding
2379 that ruins the end result. Some of this could be fixed by turning
2380 on round-to-positive-infinity, but that requires diddling the fpsr,
2381 which kills performance. I tried turning this around and converting
2382 to a negative number, so that I could turn on /m, but either I did
2383 it wrong or there's something else cause I wound up with the exact
2384 same single-bit error. There is a branch-less form of this same code:
2395 fcmoveq $f10,$f11,$f0
2397 I'm not using it because it's the same number of instructions as
2398 this branch-full form, and it has more serialized long latency
2399 instructions on the critical path.
2401 For DFmode, we can avoid rounding errors by breaking up the word
2402 into two pieces, converting them separately, and adding them back:
2404 LC0: .long 0,0x5f800000
2409 cpyse $f11,$f31,$f10
2410 cpyse $f31,$f11,$f11
2418 This doesn't seem to be a clear-cut win over the optabs form.
2419 It probably all depends on the distribution of numbers being
2420 converted -- in the optabs form, all but high-bit-set has a
2421 much lower minimum execution time. */
2424 alpha_emit_floatuns (rtx operands
[2])
2426 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2427 enum machine_mode mode
;
2430 in
= force_reg (DImode
, operands
[1]);
2431 mode
= GET_MODE (out
);
2432 neglab
= gen_label_rtx ();
2433 donelab
= gen_label_rtx ();
2434 i0
= gen_reg_rtx (DImode
);
2435 i1
= gen_reg_rtx (DImode
);
2436 f0
= gen_reg_rtx (mode
);
2438 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2440 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2441 emit_jump_insn (gen_jump (donelab
));
2444 emit_label (neglab
);
2446 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2447 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2448 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2449 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2450 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2452 emit_label (donelab
);
2455 /* Generate the comparison for a conditional branch. */
2458 alpha_emit_conditional_branch (enum rtx_code code
)
2460 enum rtx_code cmp_code
, branch_code
;
2461 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
2462 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2465 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
2467 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2469 alpha_compare
.fp_p
= 0;
2472 /* The general case: fold the comparison code to the types of compares
2473 that we have, choosing the branch as necessary. */
2476 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2478 /* We have these compares: */
2479 cmp_code
= code
, branch_code
= NE
;
2484 /* These must be reversed. */
2485 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2488 case GE
: case GT
: case GEU
: case GTU
:
2489 /* For FP, we swap them, for INT, we reverse them. */
2490 if (alpha_compare
.fp_p
)
2492 cmp_code
= swap_condition (code
);
2494 tem
= op0
, op0
= op1
, op1
= tem
;
2498 cmp_code
= reverse_condition (code
);
2507 if (alpha_compare
.fp_p
)
2510 if (flag_unsafe_math_optimizations
)
2512 /* When we are not as concerned about non-finite values, and we
2513 are comparing against zero, we can branch directly. */
2514 if (op1
== CONST0_RTX (DFmode
))
2515 cmp_code
= UNKNOWN
, branch_code
= code
;
2516 else if (op0
== CONST0_RTX (DFmode
))
2518 /* Undo the swap we probably did just above. */
2519 tem
= op0
, op0
= op1
, op1
= tem
;
2520 branch_code
= swap_condition (cmp_code
);
2526 /* ??? We mark the branch mode to be CCmode to prevent the
2527 compare and branch from being combined, since the compare
2528 insn follows IEEE rules that the branch does not. */
2529 branch_mode
= CCmode
;
2536 /* The following optimizations are only for signed compares. */
2537 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2539 /* Whee. Compare and branch against 0 directly. */
2540 if (op1
== const0_rtx
)
2541 cmp_code
= UNKNOWN
, branch_code
= code
;
2543 /* If the constants doesn't fit into an immediate, but can
2544 be generated by lda/ldah, we adjust the argument and
2545 compare against zero, so we can use beq/bne directly. */
2546 /* ??? Don't do this when comparing against symbols, otherwise
2547 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2548 be declared false out of hand (at least for non-weak). */
2549 else if (GET_CODE (op1
) == CONST_INT
2550 && (code
== EQ
|| code
== NE
)
2551 && !(symbolic_operand (op0
, VOIDmode
)
2552 || (GET_CODE (op0
) == REG
&& REG_POINTER (op0
))))
2554 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
2556 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
2557 && (CONST_OK_FOR_LETTER_P (n
, 'K')
2558 || CONST_OK_FOR_LETTER_P (n
, 'L')))
2560 cmp_code
= PLUS
, branch_code
= code
;
2566 if (!reg_or_0_operand (op0
, DImode
))
2567 op0
= force_reg (DImode
, op0
);
2568 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2569 op1
= force_reg (DImode
, op1
);
2572 /* Emit an initial compare instruction, if necessary. */
2574 if (cmp_code
!= UNKNOWN
)
2576 tem
= gen_reg_rtx (cmp_mode
);
2577 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2580 /* Zero the operands. */
2581 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2583 /* Return the branch comparison. */
2584 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
2587 /* Certain simplifications can be done to make invalid setcc operations
2588 valid. Return the final comparison, or NULL if we can't work. */
2591 alpha_emit_setcc (enum rtx_code code
)
2593 enum rtx_code cmp_code
;
2594 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2595 int fp_p
= alpha_compare
.fp_p
;
2598 /* Zero the operands. */
2599 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2601 if (fp_p
&& GET_MODE (op0
) == TFmode
)
2603 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2608 if (fp_p
&& !TARGET_FIX
)
2611 /* The general case: fold the comparison code to the types of compares
2612 that we have, choosing the branch as necessary. */
2617 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2619 /* We have these compares. */
2621 cmp_code
= code
, code
= NE
;
2625 if (!fp_p
&& op1
== const0_rtx
)
2630 cmp_code
= reverse_condition (code
);
2634 case GE
: case GT
: case GEU
: case GTU
:
2635 /* These normally need swapping, but for integer zero we have
2636 special patterns that recognize swapped operands. */
2637 if (!fp_p
&& op1
== const0_rtx
)
2639 code
= swap_condition (code
);
2641 cmp_code
= code
, code
= NE
;
2642 tmp
= op0
, op0
= op1
, op1
= tmp
;
2651 if (!register_operand (op0
, DImode
))
2652 op0
= force_reg (DImode
, op0
);
2653 if (!reg_or_8bit_operand (op1
, DImode
))
2654 op1
= force_reg (DImode
, op1
);
2657 /* Emit an initial compare instruction, if necessary. */
2658 if (cmp_code
!= UNKNOWN
)
2660 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
2662 tmp
= gen_reg_rtx (mode
);
2663 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
2664 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
2666 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
2670 /* Return the setcc comparison. */
2671 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
2675 /* Rewrite a comparison against zero CMP of the form
2676 (CODE (cc0) (const_int 0)) so it can be written validly in
2677 a conditional move (if_then_else CMP ...).
2678 If both of the operands that set cc0 are nonzero we must emit
2679 an insn to perform the compare (it can't be done within
2680 the conditional move). */
2683 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
2685 enum rtx_code code
= GET_CODE (cmp
);
2686 enum rtx_code cmov_code
= NE
;
2687 rtx op0
= alpha_compare
.op0
;
2688 rtx op1
= alpha_compare
.op1
;
2689 int fp_p
= alpha_compare
.fp_p
;
2690 enum machine_mode cmp_mode
2691 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
2692 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
2693 enum machine_mode cmov_mode
= VOIDmode
;
2694 int local_fast_math
= flag_unsafe_math_optimizations
;
2697 /* Zero the operands. */
2698 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2700 if (fp_p
!= FLOAT_MODE_P (mode
))
2702 enum rtx_code cmp_code
;
2707 /* If we have fp<->int register move instructions, do a cmov by
2708 performing the comparison in fp registers, and move the
2709 zero/nonzero value to integer registers, where we can then
2710 use a normal cmov, or vice-versa. */
2714 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2715 /* We have these compares. */
2716 cmp_code
= code
, code
= NE
;
2720 /* This must be reversed. */
2721 cmp_code
= EQ
, code
= EQ
;
2724 case GE
: case GT
: case GEU
: case GTU
:
2725 /* These normally need swapping, but for integer zero we have
2726 special patterns that recognize swapped operands. */
2727 if (!fp_p
&& op1
== const0_rtx
)
2728 cmp_code
= code
, code
= NE
;
2731 cmp_code
= swap_condition (code
);
2733 tem
= op0
, op0
= op1
, op1
= tem
;
2741 tem
= gen_reg_rtx (cmp_op_mode
);
2742 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2743 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
2746 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
2747 op0
= gen_lowpart (cmp_op_mode
, tem
);
2748 op1
= CONST0_RTX (cmp_op_mode
);
2750 local_fast_math
= 1;
2753 /* We may be able to use a conditional move directly.
2754 This avoids emitting spurious compares. */
2755 if (signed_comparison_operator (cmp
, VOIDmode
)
2756 && (!fp_p
|| local_fast_math
)
2757 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
2758 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2760 /* We can't put the comparison inside the conditional move;
2761 emit a compare instruction and put that inside the
2762 conditional move. Make sure we emit only comparisons we have;
2763 swap or reverse as necessary. */
2770 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2771 /* We have these compares: */
2775 /* This must be reversed. */
2776 code
= reverse_condition (code
);
2780 case GE
: case GT
: case GEU
: case GTU
:
2781 /* These must be swapped. */
2782 if (op1
!= CONST0_RTX (cmp_mode
))
2784 code
= swap_condition (code
);
2785 tem
= op0
, op0
= op1
, op1
= tem
;
2795 if (!reg_or_0_operand (op0
, DImode
))
2796 op0
= force_reg (DImode
, op0
);
2797 if (!reg_or_8bit_operand (op1
, DImode
))
2798 op1
= force_reg (DImode
, op1
);
2801 /* ??? We mark the branch mode to be CCmode to prevent the compare
2802 and cmov from being combined, since the compare insn follows IEEE
2803 rules that the cmov does not. */
2804 if (fp_p
&& !local_fast_math
)
2807 tem
= gen_reg_rtx (cmp_op_mode
);
2808 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
2809 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
2812 /* Simplify a conditional move of two constants into a setcc with
2813 arithmetic. This is done with a splitter since combine would
2814 just undo the work if done during code generation. It also catches
2815 cases we wouldn't have before cse. */
2818 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
2819 rtx t_rtx
, rtx f_rtx
)
2821 HOST_WIDE_INT t
, f
, diff
;
2822 enum machine_mode mode
;
2823 rtx target
, subtarget
, tmp
;
2825 mode
= GET_MODE (dest
);
2830 if (((code
== NE
|| code
== EQ
) && diff
< 0)
2831 || (code
== GE
|| code
== GT
))
2833 code
= reverse_condition (code
);
2834 diff
= t
, t
= f
, f
= diff
;
2838 subtarget
= target
= dest
;
2841 target
= gen_lowpart (DImode
, dest
);
2842 if (! no_new_pseudos
)
2843 subtarget
= gen_reg_rtx (DImode
);
2847 /* Below, we must be careful to use copy_rtx on target and subtarget
2848 in intermediate insns, as they may be a subreg rtx, which may not
2851 if (f
== 0 && exact_log2 (diff
) > 0
2852 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2853 viable over a longer latency cmove. On EV5, the E0 slot is a
2854 scarce resource, and on EV4 shift has the same latency as a cmove. */
2855 && (diff
<= 8 || alpha_tune
== PROCESSOR_EV6
))
2857 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2858 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2860 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
2861 GEN_INT (exact_log2 (t
)));
2862 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2864 else if (f
== 0 && t
== -1)
2866 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2867 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2869 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
2871 else if (diff
== 1 || diff
== 4 || diff
== 8)
2875 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2876 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2879 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
2882 add_op
= GEN_INT (f
);
2883 if (sext_add_operand (add_op
, mode
))
2885 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
2887 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
2888 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2900 /* Look up the function X_floating library function name for the
2903 struct xfloating_op
GTY(())
2905 const enum rtx_code code
;
2906 const char *const GTY((skip
)) osf_func
;
2907 const char *const GTY((skip
)) vms_func
;
2911 static GTY(()) struct xfloating_op xfloating_ops
[] =
2913 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
2914 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
2915 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
2916 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
2917 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
2918 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
2919 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
2920 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
2921 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
2922 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
2923 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2924 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
2925 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2926 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2927 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2930 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
2932 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2933 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2937 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
2939 struct xfloating_op
*ops
= xfloating_ops
;
2940 long n
= ARRAY_SIZE (xfloating_ops
);
2943 gcc_assert (TARGET_HAS_XFLOATING_LIBS
);
2945 /* How irritating. Nothing to key off for the main table. */
2946 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
2949 n
= ARRAY_SIZE (vax_cvt_ops
);
2952 for (i
= 0; i
< n
; ++i
, ++ops
)
2953 if (ops
->code
== code
)
2955 rtx func
= ops
->libcall
;
2958 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
2959 ? ops
->vms_func
: ops
->osf_func
);
2960 ops
->libcall
= func
;
2968 /* Most X_floating operations take the rounding mode as an argument.
2969 Compute that here. */
2972 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
2973 enum alpha_fp_rounding_mode round
)
2979 case ALPHA_FPRM_NORM
:
2982 case ALPHA_FPRM_MINF
:
2985 case ALPHA_FPRM_CHOP
:
2988 case ALPHA_FPRM_DYN
:
2994 /* XXX For reference, round to +inf is mode = 3. */
2997 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3003 /* Emit an X_floating library function call.
3005 Note that these functions do not follow normal calling conventions:
3006 TFmode arguments are passed in two integer registers (as opposed to
3007 indirect); TFmode return values appear in R16+R17.
3009 FUNC is the function to call.
3010 TARGET is where the output belongs.
3011 OPERANDS are the inputs.
3012 NOPERANDS is the count of inputs.
3013 EQUIV is the expression equivalent for the function.
3017 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
3018 int noperands
, rtx equiv
)
3020 rtx usage
= NULL_RTX
, tmp
, reg
;
3025 for (i
= 0; i
< noperands
; ++i
)
3027 switch (GET_MODE (operands
[i
]))
3030 reg
= gen_rtx_REG (TFmode
, regno
);
3035 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3040 gcc_assert (GET_CODE (operands
[i
]) == CONST_INT
);
3043 reg
= gen_rtx_REG (DImode
, regno
);
3051 emit_move_insn (reg
, operands
[i
]);
3052 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3055 switch (GET_MODE (target
))
3058 reg
= gen_rtx_REG (TFmode
, 16);
3061 reg
= gen_rtx_REG (DFmode
, 32);
3064 reg
= gen_rtx_REG (DImode
, 0);
3070 tmp
= gen_rtx_MEM (QImode
, func
);
3071 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3072 const0_rtx
, const0_rtx
));
3073 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3074 CONST_OR_PURE_CALL_P (tmp
) = 1;
3079 emit_libcall_block (tmp
, target
, reg
, equiv
);
3082 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3085 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3089 rtx out_operands
[3];
3091 func
= alpha_lookup_xfloating_lib_func (code
);
3092 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3094 out_operands
[0] = operands
[1];
3095 out_operands
[1] = operands
[2];
3096 out_operands
[2] = GEN_INT (mode
);
3097 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3098 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3102 /* Emit an X_floating library function call for a comparison. */
3105 alpha_emit_xfloating_compare (enum rtx_code
*pcode
, rtx op0
, rtx op1
)
3107 enum rtx_code cmp_code
, res_code
;
3108 rtx func
, out
, operands
[2];
3110 /* X_floating library comparison functions return
3114 Convert the compare against the raw return value. */
3142 func
= alpha_lookup_xfloating_lib_func (cmp_code
);
3146 out
= gen_reg_rtx (DImode
);
3148 /* ??? Strange mode for equiv because what's actually returned
3149 is -1,0,1, not a proper boolean value. */
3150 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3151 gen_rtx_fmt_ee (cmp_code
, CCmode
, op0
, op1
));
3156 /* Emit an X_floating library function call for a conversion. */
3159 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3161 int noperands
= 1, mode
;
3162 rtx out_operands
[2];
3164 enum rtx_code code
= orig_code
;
3166 if (code
== UNSIGNED_FIX
)
3169 func
= alpha_lookup_xfloating_lib_func (code
);
3171 out_operands
[0] = operands
[1];
3176 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3177 out_operands
[1] = GEN_INT (mode
);
3180 case FLOAT_TRUNCATE
:
3181 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3182 out_operands
[1] = GEN_INT (mode
);
3189 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3190 gen_rtx_fmt_e (orig_code
,
3191 GET_MODE (operands
[0]),
3195 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3196 OP[0] into OP[0,1]. Naturally, output operand ordering is
3200 alpha_split_tfmode_pair (rtx operands
[4])
3202 switch (GET_CODE (operands
[1]))
3205 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3206 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3210 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3211 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3215 gcc_assert (operands
[1] == CONST0_RTX (TFmode
));
3216 operands
[2] = operands
[3] = const0_rtx
;
3223 switch (GET_CODE (operands
[0]))
3226 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3227 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3231 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3232 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3240 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3241 op2 is a register containing the sign bit, operation is the
3242 logical operation to be performed. */
3245 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3247 rtx high_bit
= operands
[2];
3251 alpha_split_tfmode_pair (operands
);
3253 /* Detect three flavors of operand overlap. */
3255 if (rtx_equal_p (operands
[0], operands
[2]))
3257 else if (rtx_equal_p (operands
[1], operands
[2]))
3259 if (rtx_equal_p (operands
[0], high_bit
))
3266 emit_move_insn (operands
[0], operands
[2]);
3268 /* ??? If the destination overlaps both source tf and high_bit, then
3269 assume source tf is dead in its entirety and use the other half
3270 for a scratch register. Otherwise "scratch" is just the proper
3271 destination register. */
3272 scratch
= operands
[move
< 2 ? 1 : 3];
3274 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3278 emit_move_insn (operands
[0], operands
[2]);
3280 emit_move_insn (operands
[1], scratch
);
3284 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3288 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3289 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3290 lda r3,X(r11) lda r3,X+2(r11)
3291 extwl r1,r3,r1 extql r1,r3,r1
3292 extwh r2,r3,r2 extqh r2,r3,r2
3293 or r1.r2.r1 or r1,r2,r1
3296 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3297 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3298 lda r3,X(r11) lda r3,X(r11)
3299 extll r1,r3,r1 extll r1,r3,r1
3300 extlh r2,r3,r2 extlh r2,r3,r2
3301 or r1.r2.r1 addl r1,r2,r1
3303 quad: ldq_u r1,X(r11)
3312 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3313 HOST_WIDE_INT ofs
, int sign
)
3315 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3316 enum machine_mode mode
;
3318 if (TARGET_BWX
&& size
== 2)
3320 meml
= adjust_address (mem
, QImode
, ofs
);
3321 memh
= adjust_address (mem
, QImode
, ofs
+1);
3322 if (BYTES_BIG_ENDIAN
)
3323 tmp
= meml
, meml
= memh
, memh
= tmp
;
3324 extl
= gen_reg_rtx (DImode
);
3325 exth
= gen_reg_rtx (DImode
);
3326 emit_insn (gen_zero_extendqidi2 (extl
, meml
));
3327 emit_insn (gen_zero_extendqidi2 (exth
, memh
));
3328 exth
= expand_simple_binop (DImode
, ASHIFT
, exth
, GEN_INT (8),
3329 NULL
, 1, OPTAB_LIB_WIDEN
);
3330 addr
= expand_simple_binop (DImode
, IOR
, extl
, exth
,
3331 NULL
, 1, OPTAB_LIB_WIDEN
);
3333 if (sign
&& GET_MODE (tgt
) != HImode
)
3335 addr
= gen_lowpart (HImode
, addr
);
3336 emit_insn (gen_extend_insn (tgt
, addr
, GET_MODE (tgt
), HImode
, 0));
3340 if (GET_MODE (tgt
) != DImode
)
3341 addr
= gen_lowpart (GET_MODE (tgt
), addr
);
3342 emit_move_insn (tgt
, addr
);
3347 meml
= gen_reg_rtx (DImode
);
3348 memh
= gen_reg_rtx (DImode
);
3349 addr
= gen_reg_rtx (DImode
);
3350 extl
= gen_reg_rtx (DImode
);
3351 exth
= gen_reg_rtx (DImode
);
3353 mema
= XEXP (mem
, 0);
3354 if (GET_CODE (mema
) == LO_SUM
)
3355 mema
= force_reg (Pmode
, mema
);
3357 /* AND addresses cannot be in any alias set, since they may implicitly
3358 alias surrounding code. Ideally we'd have some alias set that
3359 covered all types except those with alignment 8 or higher. */
3361 tmp
= change_address (mem
, DImode
,
3362 gen_rtx_AND (DImode
,
3363 plus_constant (mema
, ofs
),
3365 set_mem_alias_set (tmp
, 0);
3366 emit_move_insn (meml
, tmp
);
3368 tmp
= change_address (mem
, DImode
,
3369 gen_rtx_AND (DImode
,
3370 plus_constant (mema
, ofs
+ size
- 1),
3372 set_mem_alias_set (tmp
, 0);
3373 emit_move_insn (memh
, tmp
);
3375 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3377 emit_move_insn (addr
, plus_constant (mema
, -1));
3379 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3380 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3382 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3383 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3384 addr
, 1, OPTAB_WIDEN
);
3386 else if (sign
&& size
== 2)
3388 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3390 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3391 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3393 /* We must use tgt here for the target. Alpha-vms port fails if we use
3394 addr for the target, because addr is marked as a pointer and combine
3395 knows that pointers are always sign-extended 32 bit values. */
3396 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3397 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3398 addr
, 1, OPTAB_WIDEN
);
3402 if (WORDS_BIG_ENDIAN
)
3404 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3408 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3413 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3418 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3425 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3429 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3430 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3434 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3439 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3444 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3453 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3454 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3459 emit_move_insn (tgt
, gen_lowpart (GET_MODE (tgt
), addr
));
3462 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3465 alpha_expand_unaligned_store (rtx dst
, rtx src
,
3466 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
3468 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3470 if (TARGET_BWX
&& size
== 2)
3472 if (src
!= const0_rtx
)
3474 dstl
= gen_lowpart (QImode
, src
);
3475 dsth
= expand_simple_binop (DImode
, LSHIFTRT
, src
, GEN_INT (8),
3476 NULL
, 1, OPTAB_LIB_WIDEN
);
3477 dsth
= gen_lowpart (QImode
, dsth
);
3480 dstl
= dsth
= const0_rtx
;
3482 meml
= adjust_address (dst
, QImode
, ofs
);
3483 memh
= adjust_address (dst
, QImode
, ofs
+1);
3484 if (BYTES_BIG_ENDIAN
)
3485 addr
= meml
, meml
= memh
, memh
= addr
;
3487 emit_move_insn (meml
, dstl
);
3488 emit_move_insn (memh
, dsth
);
3492 dstl
= gen_reg_rtx (DImode
);
3493 dsth
= gen_reg_rtx (DImode
);
3494 insl
= gen_reg_rtx (DImode
);
3495 insh
= gen_reg_rtx (DImode
);
3497 dsta
= XEXP (dst
, 0);
3498 if (GET_CODE (dsta
) == LO_SUM
)
3499 dsta
= force_reg (Pmode
, dsta
);
3501 /* AND addresses cannot be in any alias set, since they may implicitly
3502 alias surrounding code. Ideally we'd have some alias set that
3503 covered all types except those with alignment 8 or higher. */
3505 meml
= change_address (dst
, DImode
,
3506 gen_rtx_AND (DImode
,
3507 plus_constant (dsta
, ofs
),
3509 set_mem_alias_set (meml
, 0);
3511 memh
= change_address (dst
, DImode
,
3512 gen_rtx_AND (DImode
,
3513 plus_constant (dsta
, ofs
+ size
- 1),
3515 set_mem_alias_set (memh
, 0);
3517 emit_move_insn (dsth
, memh
);
3518 emit_move_insn (dstl
, meml
);
3519 if (WORDS_BIG_ENDIAN
)
3521 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3523 if (src
!= const0_rtx
)
3528 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3531 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3534 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3537 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3538 GEN_INT (size
*8), addr
));
3544 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3548 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3549 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3553 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
3557 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3561 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3563 if (src
!= CONST0_RTX (GET_MODE (src
)))
3565 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3566 GEN_INT (size
*8), addr
));
3571 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3574 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3577 emit_insn (gen_insql_le (insl
, src
, addr
));
3582 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3587 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3591 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3592 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3596 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
3601 if (src
!= CONST0_RTX (GET_MODE (src
)))
3603 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3604 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3607 if (WORDS_BIG_ENDIAN
)
3609 emit_move_insn (meml
, dstl
);
3610 emit_move_insn (memh
, dsth
);
3614 /* Must store high before low for degenerate case of aligned. */
3615 emit_move_insn (memh
, dsth
);
3616 emit_move_insn (meml
, dstl
);
3620 /* The block move code tries to maximize speed by separating loads and
3621 stores at the expense of register pressure: we load all of the data
3622 before we store it back out. There are two secondary effects worth
3623 mentioning, that this speeds copying to/from aligned and unaligned
3624 buffers, and that it makes the code significantly easier to write. */
3626 #define MAX_MOVE_WORDS 8
3628 /* Load an integral number of consecutive unaligned quadwords. */
3631 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
3632 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3634 rtx
const im8
= GEN_INT (-8);
3635 rtx
const i64
= GEN_INT (64);
3636 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3637 rtx sreg
, areg
, tmp
, smema
;
3640 smema
= XEXP (smem
, 0);
3641 if (GET_CODE (smema
) == LO_SUM
)
3642 smema
= force_reg (Pmode
, smema
);
3644 /* Generate all the tmp registers we need. */
3645 for (i
= 0; i
< words
; ++i
)
3647 data_regs
[i
] = out_regs
[i
];
3648 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3650 data_regs
[words
] = gen_reg_rtx (DImode
);
3653 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3655 /* Load up all of the source data. */
3656 for (i
= 0; i
< words
; ++i
)
3658 tmp
= change_address (smem
, DImode
,
3659 gen_rtx_AND (DImode
,
3660 plus_constant (smema
, 8*i
),
3662 set_mem_alias_set (tmp
, 0);
3663 emit_move_insn (data_regs
[i
], tmp
);
3666 tmp
= change_address (smem
, DImode
,
3667 gen_rtx_AND (DImode
,
3668 plus_constant (smema
, 8*words
- 1),
3670 set_mem_alias_set (tmp
, 0);
3671 emit_move_insn (data_regs
[words
], tmp
);
3673 /* Extract the half-word fragments. Unfortunately DEC decided to make
3674 extxh with offset zero a noop instead of zeroing the register, so
3675 we must take care of that edge condition ourselves with cmov. */
3677 sreg
= copy_addr_to_reg (smema
);
3678 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3680 if (WORDS_BIG_ENDIAN
)
3681 emit_move_insn (sreg
, plus_constant (sreg
, 7));
3682 for (i
= 0; i
< words
; ++i
)
3684 if (WORDS_BIG_ENDIAN
)
3686 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
3687 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
3691 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
3692 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3694 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3695 gen_rtx_IF_THEN_ELSE (DImode
,
3696 gen_rtx_EQ (DImode
, areg
,
3698 const0_rtx
, ext_tmps
[i
])));
3701 /* Merge the half-words into whole words. */
3702 for (i
= 0; i
< words
; ++i
)
3704 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3705 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
3709 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3710 may be NULL to store zeros. */
3713 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
3714 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3716 rtx
const im8
= GEN_INT (-8);
3717 rtx
const i64
= GEN_INT (64);
3718 rtx ins_tmps
[MAX_MOVE_WORDS
];
3719 rtx st_tmp_1
, st_tmp_2
, dreg
;
3720 rtx st_addr_1
, st_addr_2
, dmema
;
3723 dmema
= XEXP (dmem
, 0);
3724 if (GET_CODE (dmema
) == LO_SUM
)
3725 dmema
= force_reg (Pmode
, dmema
);
3727 /* Generate all the tmp registers we need. */
3728 if (data_regs
!= NULL
)
3729 for (i
= 0; i
< words
; ++i
)
3730 ins_tmps
[i
] = gen_reg_rtx(DImode
);
3731 st_tmp_1
= gen_reg_rtx(DImode
);
3732 st_tmp_2
= gen_reg_rtx(DImode
);
3735 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
3737 st_addr_2
= change_address (dmem
, DImode
,
3738 gen_rtx_AND (DImode
,
3739 plus_constant (dmema
, words
*8 - 1),
3741 set_mem_alias_set (st_addr_2
, 0);
3743 st_addr_1
= change_address (dmem
, DImode
,
3744 gen_rtx_AND (DImode
, dmema
, im8
));
3745 set_mem_alias_set (st_addr_1
, 0);
3747 /* Load up the destination end bits. */
3748 emit_move_insn (st_tmp_2
, st_addr_2
);
3749 emit_move_insn (st_tmp_1
, st_addr_1
);
3751 /* Shift the input data into place. */
3752 dreg
= copy_addr_to_reg (dmema
);
3753 if (WORDS_BIG_ENDIAN
)
3754 emit_move_insn (dreg
, plus_constant (dreg
, 7));
3755 if (data_regs
!= NULL
)
3757 for (i
= words
-1; i
>= 0; --i
)
3759 if (WORDS_BIG_ENDIAN
)
3761 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
3762 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
3766 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
3767 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
3770 for (i
= words
-1; i
> 0; --i
)
3772 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3773 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
3778 /* Split and merge the ends with the destination data. */
3779 if (WORDS_BIG_ENDIAN
)
3781 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
3782 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
3786 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
3787 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
3790 if (data_regs
!= NULL
)
3792 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
3793 st_tmp_2
, 1, OPTAB_WIDEN
);
3794 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
3795 st_tmp_1
, 1, OPTAB_WIDEN
);
3799 if (WORDS_BIG_ENDIAN
)
3800 emit_move_insn (st_addr_1
, st_tmp_1
);
3802 emit_move_insn (st_addr_2
, st_tmp_2
);
3803 for (i
= words
-1; i
> 0; --i
)
3805 rtx tmp
= change_address (dmem
, DImode
,
3806 gen_rtx_AND (DImode
,
3807 plus_constant(dmema
,
3808 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
3810 set_mem_alias_set (tmp
, 0);
3811 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
3813 if (WORDS_BIG_ENDIAN
)
3814 emit_move_insn (st_addr_2
, st_tmp_2
);
3816 emit_move_insn (st_addr_1
, st_tmp_1
);
3820 /* Expand string/block move operations.
3822 operands[0] is the pointer to the destination.
3823 operands[1] is the pointer to the source.
3824 operands[2] is the number of bytes to move.
3825 operands[3] is the alignment. */
3828 alpha_expand_block_move (rtx operands
[])
3830 rtx bytes_rtx
= operands
[2];
3831 rtx align_rtx
= operands
[3];
3832 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3833 HOST_WIDE_INT bytes
= orig_bytes
;
3834 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3835 HOST_WIDE_INT dst_align
= src_align
;
3836 rtx orig_src
= operands
[1];
3837 rtx orig_dst
= operands
[0];
3838 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
3840 unsigned int i
, words
, ofs
, nregs
= 0;
3842 if (orig_bytes
<= 0)
3844 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3847 /* Look for additional alignment information from recorded register info. */
3849 tmp
= XEXP (orig_src
, 0);
3850 if (GET_CODE (tmp
) == REG
)
3851 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3852 else if (GET_CODE (tmp
) == PLUS
3853 && GET_CODE (XEXP (tmp
, 0)) == REG
3854 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3856 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3857 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3861 if (a
>= 64 && c
% 8 == 0)
3863 else if (a
>= 32 && c
% 4 == 0)
3865 else if (a
>= 16 && c
% 2 == 0)
3870 tmp
= XEXP (orig_dst
, 0);
3871 if (GET_CODE (tmp
) == REG
)
3872 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3873 else if (GET_CODE (tmp
) == PLUS
3874 && GET_CODE (XEXP (tmp
, 0)) == REG
3875 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3877 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3878 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3882 if (a
>= 64 && c
% 8 == 0)
3884 else if (a
>= 32 && c
% 4 == 0)
3886 else if (a
>= 16 && c
% 2 == 0)
3892 if (src_align
>= 64 && bytes
>= 8)
3896 for (i
= 0; i
< words
; ++i
)
3897 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3899 for (i
= 0; i
< words
; ++i
)
3900 emit_move_insn (data_regs
[nregs
+ i
],
3901 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
3908 if (src_align
>= 32 && bytes
>= 4)
3912 for (i
= 0; i
< words
; ++i
)
3913 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
3915 for (i
= 0; i
< words
; ++i
)
3916 emit_move_insn (data_regs
[nregs
+ i
],
3917 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
3928 for (i
= 0; i
< words
+1; ++i
)
3929 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3931 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
3939 if (! TARGET_BWX
&& bytes
>= 4)
3941 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
3942 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
3949 if (src_align
>= 16)
3952 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3953 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
3956 } while (bytes
>= 2);
3958 else if (! TARGET_BWX
)
3960 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3961 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
3969 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
3970 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
3975 gcc_assert (nregs
<= ARRAY_SIZE (data_regs
));
3977 /* Now save it back out again. */
3981 /* Write out the data in whatever chunks reading the source allowed. */
3982 if (dst_align
>= 64)
3984 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3986 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
3993 if (dst_align
>= 32)
3995 /* If the source has remaining DImode regs, write them out in
3997 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3999 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4000 NULL_RTX
, 1, OPTAB_WIDEN
);
4002 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4003 gen_lowpart (SImode
, data_regs
[i
]));
4004 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4005 gen_lowpart (SImode
, tmp
));
4010 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4012 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4019 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4021 /* Write out a remaining block of words using unaligned methods. */
4023 for (words
= 1; i
+ words
< nregs
; words
++)
4024 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4028 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4030 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4037 /* Due to the above, this won't be aligned. */
4038 /* ??? If we have more than one of these, consider constructing full
4039 words in registers and using alpha_expand_unaligned_store_words. */
4040 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4042 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4047 if (dst_align
>= 16)
4048 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4050 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4055 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4057 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4062 /* The remainder must be byte copies. */
4065 gcc_assert (GET_MODE (data_regs
[i
]) == QImode
);
4066 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4075 alpha_expand_block_clear (rtx operands
[])
4077 rtx bytes_rtx
= operands
[1];
4078 rtx align_rtx
= operands
[3];
4079 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4080 HOST_WIDE_INT bytes
= orig_bytes
;
4081 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4082 HOST_WIDE_INT alignofs
= 0;
4083 rtx orig_dst
= operands
[0];
4085 int i
, words
, ofs
= 0;
4087 if (orig_bytes
<= 0)
4089 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4092 /* Look for stricter alignment. */
4093 tmp
= XEXP (orig_dst
, 0);
4094 if (GET_CODE (tmp
) == REG
)
4095 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4096 else if (GET_CODE (tmp
) == PLUS
4097 && GET_CODE (XEXP (tmp
, 0)) == REG
4098 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4100 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4101 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4106 align
= a
, alignofs
= 8 - c
% 8;
4108 align
= a
, alignofs
= 4 - c
% 4;
4110 align
= a
, alignofs
= 2 - c
% 2;
4114 /* Handle an unaligned prefix first. */
4118 #if HOST_BITS_PER_WIDE_INT >= 64
4119 /* Given that alignofs is bounded by align, the only time BWX could
4120 generate three stores is for a 7 byte fill. Prefer two individual
4121 stores over a load/mask/store sequence. */
4122 if ((!TARGET_BWX
|| alignofs
== 7)
4124 && !(alignofs
== 4 && bytes
>= 4))
4126 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4127 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4131 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4132 set_mem_alias_set (mem
, 0);
4134 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4135 if (bytes
< alignofs
)
4137 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4148 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4149 NULL_RTX
, 1, OPTAB_WIDEN
);
4151 emit_move_insn (mem
, tmp
);
4155 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4157 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4162 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4164 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4169 if (alignofs
== 4 && bytes
>= 4)
4171 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4177 /* If we've not used the extra lead alignment information by now,
4178 we won't be able to. Downgrade align to match what's left over. */
4181 alignofs
= alignofs
& -alignofs
;
4182 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4186 /* Handle a block of contiguous long-words. */
4188 if (align
>= 64 && bytes
>= 8)
4192 for (i
= 0; i
< words
; ++i
)
4193 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4200 /* If the block is large and appropriately aligned, emit a single
4201 store followed by a sequence of stq_u insns. */
4203 if (align
>= 32 && bytes
> 16)
4207 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4211 orig_dsta
= XEXP (orig_dst
, 0);
4212 if (GET_CODE (orig_dsta
) == LO_SUM
)
4213 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4216 for (i
= 0; i
< words
; ++i
)
4219 = change_address (orig_dst
, DImode
,
4220 gen_rtx_AND (DImode
,
4221 plus_constant (orig_dsta
, ofs
+ i
*8),
4223 set_mem_alias_set (mem
, 0);
4224 emit_move_insn (mem
, const0_rtx
);
4227 /* Depending on the alignment, the first stq_u may have overlapped
4228 with the initial stl, which means that the last stq_u didn't
4229 write as much as it would appear. Leave those questionable bytes
4231 bytes
-= words
* 8 - 4;
4232 ofs
+= words
* 8 - 4;
4235 /* Handle a smaller block of aligned words. */
4237 if ((align
>= 64 && bytes
== 4)
4238 || (align
== 32 && bytes
>= 4))
4242 for (i
= 0; i
< words
; ++i
)
4243 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4250 /* An unaligned block uses stq_u stores for as many as possible. */
4256 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4262 /* Next clean up any trailing pieces. */
4264 #if HOST_BITS_PER_WIDE_INT >= 64
4265 /* Count the number of bits in BYTES for which aligned stores could
4268 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4272 /* If we have appropriate alignment (and it wouldn't take too many
4273 instructions otherwise), mask out the bytes we need. */
4274 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4281 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4282 set_mem_alias_set (mem
, 0);
4284 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4286 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4287 NULL_RTX
, 1, OPTAB_WIDEN
);
4289 emit_move_insn (mem
, tmp
);
4292 else if (align
>= 32 && bytes
< 4)
4297 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4298 set_mem_alias_set (mem
, 0);
4300 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4302 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4303 NULL_RTX
, 1, OPTAB_WIDEN
);
4305 emit_move_insn (mem
, tmp
);
4311 if (!TARGET_BWX
&& bytes
>= 4)
4313 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4323 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4327 } while (bytes
>= 2);
4329 else if (! TARGET_BWX
)
4331 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4339 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4347 /* Returns a mask so that zap(x, value) == x & mask. */
4350 alpha_expand_zap_mask (HOST_WIDE_INT value
)
4355 if (HOST_BITS_PER_WIDE_INT
>= 64)
4357 HOST_WIDE_INT mask
= 0;
4359 for (i
= 7; i
>= 0; --i
)
4362 if (!((value
>> i
) & 1))
4366 result
= gen_int_mode (mask
, DImode
);
4370 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
4372 gcc_assert (HOST_BITS_PER_WIDE_INT
== 32);
4374 for (i
= 7; i
>= 4; --i
)
4377 if (!((value
>> i
) & 1))
4381 for (i
= 3; i
>= 0; --i
)
4384 if (!((value
>> i
) & 1))
4388 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
4395 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
4396 enum machine_mode mode
,
4397 rtx op0
, rtx op1
, rtx op2
)
4399 op0
= gen_lowpart (mode
, op0
);
4401 if (op1
== const0_rtx
)
4402 op1
= CONST0_RTX (mode
);
4404 op1
= gen_lowpart (mode
, op1
);
4406 if (op2
== const0_rtx
)
4407 op2
= CONST0_RTX (mode
);
4409 op2
= gen_lowpart (mode
, op2
);
4411 emit_insn ((*gen
) (op0
, op1
, op2
));
4414 /* A subroutine of the atomic operation splitters. Jump to LABEL if
4415 COND is true. Mark the jump as unlikely to be taken. */
4418 emit_unlikely_jump (rtx cond
, rtx label
)
4420 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
4423 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
4424 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
4425 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_BR_PROB
, very_unlikely
, NULL_RTX
);
4428 /* A subroutine of the atomic operation splitters. Emit a load-locked
4429 instruction in MODE. */
4432 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
4434 rtx (*fn
) (rtx
, rtx
) = NULL
;
4436 fn
= gen_load_locked_si
;
4437 else if (mode
== DImode
)
4438 fn
= gen_load_locked_di
;
4439 emit_insn (fn (reg
, mem
));
4442 /* A subroutine of the atomic operation splitters. Emit a store-conditional
4443 instruction in MODE. */
4446 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
4448 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
4450 fn
= gen_store_conditional_si
;
4451 else if (mode
== DImode
)
4452 fn
= gen_store_conditional_di
;
4453 emit_insn (fn (res
, mem
, val
));
4456 /* A subroutine of the atomic operation splitters. Emit an insxl
4457 instruction in MODE. */
4460 emit_insxl (enum machine_mode mode
, rtx op1
, rtx op2
)
4462 rtx ret
= gen_reg_rtx (DImode
);
4463 rtx (*fn
) (rtx
, rtx
, rtx
);
4465 if (WORDS_BIG_ENDIAN
)
4479 emit_insn (fn (ret
, op1
, op2
));
4484 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
4485 to perform. MEM is the memory on which to operate. VAL is the second
4486 operand of the binary operator. BEFORE and AFTER are optional locations to
4487 return the value of MEM either before of after the operation. SCRATCH is
4488 a scratch register. */
4491 alpha_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
4492 rtx before
, rtx after
, rtx scratch
)
4494 enum machine_mode mode
= GET_MODE (mem
);
4495 rtx label
, x
, cond
= gen_rtx_REG (DImode
, REGNO (scratch
));
4497 emit_insn (gen_memory_barrier ());
4499 label
= gen_label_rtx ();
4501 label
= gen_rtx_LABEL_REF (DImode
, label
);
4505 emit_load_locked (mode
, before
, mem
);
4508 x
= gen_rtx_AND (mode
, gen_rtx_NOT (mode
, before
), val
);
4510 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
4512 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
4513 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
4515 emit_store_conditional (mode
, cond
, mem
, scratch
);
4517 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4518 emit_unlikely_jump (x
, label
);
4520 emit_insn (gen_memory_barrier ());
4523 /* Expand a compare and swap operation. */
4526 alpha_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
4529 enum machine_mode mode
= GET_MODE (mem
);
4530 rtx label1
, label2
, x
, cond
= gen_lowpart (DImode
, scratch
);
4532 emit_insn (gen_memory_barrier ());
4534 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4535 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4536 emit_label (XEXP (label1
, 0));
4538 emit_load_locked (mode
, retval
, mem
);
4540 x
= gen_lowpart (DImode
, retval
);
4541 if (oldval
== const0_rtx
)
4542 x
= gen_rtx_NE (DImode
, x
, const0_rtx
);
4545 x
= gen_rtx_EQ (DImode
, x
, oldval
);
4546 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4547 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4549 emit_unlikely_jump (x
, label2
);
4551 emit_move_insn (scratch
, newval
);
4552 emit_store_conditional (mode
, cond
, mem
, scratch
);
4554 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4555 emit_unlikely_jump (x
, label1
);
4557 emit_insn (gen_memory_barrier ());
4558 emit_label (XEXP (label2
, 0));
4562 alpha_expand_compare_and_swap_12 (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
4564 enum machine_mode mode
= GET_MODE (mem
);
4565 rtx addr
, align
, wdst
;
4566 rtx (*fn5
) (rtx
, rtx
, rtx
, rtx
, rtx
);
4568 addr
= force_reg (DImode
, XEXP (mem
, 0));
4569 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4570 NULL_RTX
, 1, OPTAB_DIRECT
);
4572 oldval
= convert_modes (DImode
, mode
, oldval
, 1);
4573 newval
= emit_insxl (mode
, newval
, addr
);
4575 wdst
= gen_reg_rtx (DImode
);
4577 fn5
= gen_sync_compare_and_swapqi_1
;
4579 fn5
= gen_sync_compare_and_swaphi_1
;
4580 emit_insn (fn5 (wdst
, addr
, oldval
, newval
, align
));
4582 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4586 alpha_split_compare_and_swap_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4587 rtx oldval
, rtx newval
, rtx align
,
4588 rtx scratch
, rtx cond
)
4590 rtx label1
, label2
, mem
, width
, mask
, x
;
4592 mem
= gen_rtx_MEM (DImode
, align
);
4593 MEM_VOLATILE_P (mem
) = 1;
4595 emit_insn (gen_memory_barrier ());
4596 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4597 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4598 emit_label (XEXP (label1
, 0));
4600 emit_load_locked (DImode
, scratch
, mem
);
4602 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4603 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4604 if (WORDS_BIG_ENDIAN
)
4605 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4607 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4609 if (oldval
== const0_rtx
)
4610 x
= gen_rtx_NE (DImode
, dest
, const0_rtx
);
4613 x
= gen_rtx_EQ (DImode
, dest
, oldval
);
4614 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4615 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4617 emit_unlikely_jump (x
, label2
);
4619 if (WORDS_BIG_ENDIAN
)
4620 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4622 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4623 emit_insn (gen_iordi3 (scratch
, scratch
, newval
));
4625 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4627 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4628 emit_unlikely_jump (x
, label1
);
4630 emit_insn (gen_memory_barrier ());
4631 emit_label (XEXP (label2
, 0));
4634 /* Expand an atomic exchange operation. */
4637 alpha_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
4639 enum machine_mode mode
= GET_MODE (mem
);
4640 rtx label
, x
, cond
= gen_lowpart (DImode
, scratch
);
4642 emit_insn (gen_memory_barrier ());
4644 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4645 emit_label (XEXP (label
, 0));
4647 emit_load_locked (mode
, retval
, mem
);
4648 emit_move_insn (scratch
, val
);
4649 emit_store_conditional (mode
, cond
, mem
, scratch
);
4651 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4652 emit_unlikely_jump (x
, label
);
4656 alpha_expand_lock_test_and_set_12 (rtx dst
, rtx mem
, rtx val
)
4658 enum machine_mode mode
= GET_MODE (mem
);
4659 rtx addr
, align
, wdst
;
4660 rtx (*fn4
) (rtx
, rtx
, rtx
, rtx
);
4662 /* Force the address into a register. */
4663 addr
= force_reg (DImode
, XEXP (mem
, 0));
4665 /* Align it to a multiple of 8. */
4666 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4667 NULL_RTX
, 1, OPTAB_DIRECT
);
4669 /* Insert val into the correct byte location within the word. */
4670 val
= emit_insxl (mode
, val
, addr
);
4672 wdst
= gen_reg_rtx (DImode
);
4674 fn4
= gen_sync_lock_test_and_setqi_1
;
4676 fn4
= gen_sync_lock_test_and_sethi_1
;
4677 emit_insn (fn4 (wdst
, addr
, val
, align
));
4679 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4683 alpha_split_lock_test_and_set_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4684 rtx val
, rtx align
, rtx scratch
)
4686 rtx label
, mem
, width
, mask
, x
;
4688 mem
= gen_rtx_MEM (DImode
, align
);
4689 MEM_VOLATILE_P (mem
) = 1;
4691 emit_insn (gen_memory_barrier ());
4692 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4693 emit_label (XEXP (label
, 0));
4695 emit_load_locked (DImode
, scratch
, mem
);
4697 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4698 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4699 if (WORDS_BIG_ENDIAN
)
4701 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4702 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4706 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4707 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4709 emit_insn (gen_iordi3 (scratch
, scratch
, val
));
4711 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4713 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4714 emit_unlikely_jump (x
, label
);
4717 /* Adjust the cost of a scheduling dependency. Return the new cost of
4718 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4721 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4723 enum attr_type insn_type
, dep_insn_type
;
4725 /* If the dependence is an anti-dependence, there is no cost. For an
4726 output dependence, there is sometimes a cost, but it doesn't seem
4727 worth handling those few cases. */
4728 if (REG_NOTE_KIND (link
) != 0)
4731 /* If we can't recognize the insns, we can't really do anything. */
4732 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4735 insn_type
= get_attr_type (insn
);
4736 dep_insn_type
= get_attr_type (dep_insn
);
4738 /* Bring in the user-defined memory latency. */
4739 if (dep_insn_type
== TYPE_ILD
4740 || dep_insn_type
== TYPE_FLD
4741 || dep_insn_type
== TYPE_LDSYM
)
4742 cost
+= alpha_memory_latency
-1;
4744 /* Everything else handled in DFA bypasses now. */
4749 /* The number of instructions that can be issued per cycle. */
4752 alpha_issue_rate (void)
4754 return (alpha_tune
== PROCESSOR_EV4
? 2 : 4);
4757 /* How many alternative schedules to try. This should be as wide as the
4758 scheduling freedom in the DFA, but no wider. Making this value too
4759 large results extra work for the scheduler.
4761 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4762 alternative schedules. For EV5, we can choose between E0/E1 and
4763 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4766 alpha_multipass_dfa_lookahead (void)
4768 return (alpha_tune
== PROCESSOR_EV6
? 4 : 2);
4771 /* Machine-specific function data. */
4773 struct machine_function
GTY(())
4776 /* List of call information words for calls from this function. */
4777 struct rtx_def
*first_ciw
;
4778 struct rtx_def
*last_ciw
;
4781 /* List of deferred case vectors. */
4782 struct rtx_def
*addr_list
;
4785 const char *some_ld_name
;
4787 /* For TARGET_LD_BUGGY_LDGP. */
4788 struct rtx_def
*gp_save_rtx
;
4791 /* How to allocate a 'struct machine_function'. */
4793 static struct machine_function
*
4794 alpha_init_machine_status (void)
4796 return ((struct machine_function
*)
4797 ggc_alloc_cleared (sizeof (struct machine_function
)));
4800 /* Functions to save and restore alpha_return_addr_rtx. */
4802 /* Start the ball rolling with RETURN_ADDR_RTX. */
4805 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
4810 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4813 /* Return or create a memory slot containing the gp value for the current
4814 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4817 alpha_gp_save_rtx (void)
4819 rtx seq
, m
= cfun
->machine
->gp_save_rtx
;
4825 m
= assign_stack_local (DImode
, UNITS_PER_WORD
, BITS_PER_WORD
);
4826 m
= validize_mem (m
);
4827 emit_move_insn (m
, pic_offset_table_rtx
);
4831 emit_insn_after (seq
, entry_of_function ());
4833 cfun
->machine
->gp_save_rtx
= m
;
4840 alpha_ra_ever_killed (void)
4844 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4845 return regs_ever_live
[REG_RA
];
4847 push_topmost_sequence ();
4849 pop_topmost_sequence ();
4851 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
4855 /* Return the trap mode suffix applicable to the current
4856 instruction, or NULL. */
4859 get_trap_mode_suffix (void)
4861 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
4865 case TRAP_SUFFIX_NONE
:
4868 case TRAP_SUFFIX_SU
:
4869 if (alpha_fptm
>= ALPHA_FPTM_SU
)
4873 case TRAP_SUFFIX_SUI
:
4874 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
4878 case TRAP_SUFFIX_V_SV
:
4886 case ALPHA_FPTM_SUI
:
4892 case TRAP_SUFFIX_V_SV_SVI
:
4901 case ALPHA_FPTM_SUI
:
4908 case TRAP_SUFFIX_U_SU_SUI
:
4917 case ALPHA_FPTM_SUI
:
4930 /* Return the rounding mode suffix applicable to the current
4931 instruction, or NULL. */
4934 get_round_mode_suffix (void)
4936 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
4940 case ROUND_SUFFIX_NONE
:
4942 case ROUND_SUFFIX_NORMAL
:
4945 case ALPHA_FPRM_NORM
:
4947 case ALPHA_FPRM_MINF
:
4949 case ALPHA_FPRM_CHOP
:
4951 case ALPHA_FPRM_DYN
:
4958 case ROUND_SUFFIX_C
:
4967 /* Locate some local-dynamic symbol still in use by this function
4968 so that we can print its name in some movdi_er_tlsldm pattern. */
4971 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4975 if (GET_CODE (x
) == SYMBOL_REF
4976 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4978 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4986 get_some_local_dynamic_name (void)
4990 if (cfun
->machine
->some_ld_name
)
4991 return cfun
->machine
->some_ld_name
;
4993 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4995 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4996 return cfun
->machine
->some_ld_name
;
5001 /* Print an operand. Recognize special options, documented below. */
5004 print_operand (FILE *file
, rtx x
, int code
)
5011 /* Print the assembler name of the current function. */
5012 assemble_name (file
, alpha_fnname
);
5016 assemble_name (file
, get_some_local_dynamic_name ());
5021 const char *trap
= get_trap_mode_suffix ();
5022 const char *round
= get_round_mode_suffix ();
5025 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5026 (trap
? trap
: ""), (round
? round
: ""));
5031 /* Generates single precision instruction suffix. */
5032 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5036 /* Generates double precision instruction suffix. */
5037 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5041 /* Generates a nop after a noreturn call at the very end of the
5043 if (next_real_insn (current_output_insn
) == 0)
5044 fprintf (file
, "\n\tnop");
5048 if (alpha_this_literal_sequence_number
== 0)
5049 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5050 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5054 if (alpha_this_gpdisp_sequence_number
== 0)
5055 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5056 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5060 if (GET_CODE (x
) == HIGH
)
5061 output_addr_const (file
, XEXP (x
, 0));
5063 output_operand_lossage ("invalid %%H value");
5070 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5072 x
= XVECEXP (x
, 0, 0);
5073 lituse
= "lituse_tlsgd";
5075 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5077 x
= XVECEXP (x
, 0, 0);
5078 lituse
= "lituse_tlsldm";
5080 else if (GET_CODE (x
) == CONST_INT
)
5081 lituse
= "lituse_jsr";
5084 output_operand_lossage ("invalid %%J value");
5088 if (x
!= const0_rtx
)
5089 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5097 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5098 lituse
= "lituse_jsrdirect";
5100 lituse
= "lituse_jsr";
5103 gcc_assert (INTVAL (x
) != 0);
5104 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5108 /* If this operand is the constant zero, write it as "$31". */
5109 if (GET_CODE (x
) == REG
)
5110 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5111 else if (x
== CONST0_RTX (GET_MODE (x
)))
5112 fprintf (file
, "$31");
5114 output_operand_lossage ("invalid %%r value");
5118 /* Similar, but for floating-point. */
5119 if (GET_CODE (x
) == REG
)
5120 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5121 else if (x
== CONST0_RTX (GET_MODE (x
)))
5122 fprintf (file
, "$f31");
5124 output_operand_lossage ("invalid %%R value");
5128 /* Write the 1's complement of a constant. */
5129 if (GET_CODE (x
) != CONST_INT
)
5130 output_operand_lossage ("invalid %%N value");
5132 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5136 /* Write 1 << C, for a constant C. */
5137 if (GET_CODE (x
) != CONST_INT
)
5138 output_operand_lossage ("invalid %%P value");
5140 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5144 /* Write the high-order 16 bits of a constant, sign-extended. */
5145 if (GET_CODE (x
) != CONST_INT
)
5146 output_operand_lossage ("invalid %%h value");
5148 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5152 /* Write the low-order 16 bits of a constant, sign-extended. */
5153 if (GET_CODE (x
) != CONST_INT
)
5154 output_operand_lossage ("invalid %%L value");
5156 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5157 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5161 /* Write mask for ZAP insn. */
5162 if (GET_CODE (x
) == CONST_DOUBLE
)
5164 HOST_WIDE_INT mask
= 0;
5165 HOST_WIDE_INT value
;
5167 value
= CONST_DOUBLE_LOW (x
);
5168 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5173 value
= CONST_DOUBLE_HIGH (x
);
5174 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5177 mask
|= (1 << (i
+ sizeof (int)));
5179 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5182 else if (GET_CODE (x
) == CONST_INT
)
5184 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5186 for (i
= 0; i
< 8; i
++, value
>>= 8)
5190 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5193 output_operand_lossage ("invalid %%m value");
5197 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5198 if (GET_CODE (x
) != CONST_INT
5199 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5200 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5201 output_operand_lossage ("invalid %%M value");
5203 fprintf (file
, "%s",
5204 (INTVAL (x
) == 8 ? "b"
5205 : INTVAL (x
) == 16 ? "w"
5206 : INTVAL (x
) == 32 ? "l"
5211 /* Similar, except do it from the mask. */
5212 if (GET_CODE (x
) == CONST_INT
)
5214 HOST_WIDE_INT value
= INTVAL (x
);
5221 if (value
== 0xffff)
5226 if (value
== 0xffffffff)
5237 else if (HOST_BITS_PER_WIDE_INT
== 32
5238 && GET_CODE (x
) == CONST_DOUBLE
5239 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5240 && CONST_DOUBLE_HIGH (x
) == 0)
5245 output_operand_lossage ("invalid %%U value");
5249 /* Write the constant value divided by 8 for little-endian mode or
5250 (56 - value) / 8 for big-endian mode. */
5252 if (GET_CODE (x
) != CONST_INT
5253 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5256 || (INTVAL (x
) & 7) != 0)
5257 output_operand_lossage ("invalid %%s value");
5259 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5261 ? (56 - INTVAL (x
)) / 8
5266 /* Same, except compute (64 - c) / 8 */
5268 if (GET_CODE (x
) != CONST_INT
5269 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5270 && (INTVAL (x
) & 7) != 8)
5271 output_operand_lossage ("invalid %%s value");
5273 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5278 /* On Unicos/Mk systems: use a DEX expression if the symbol
5279 clashes with a register name. */
5280 int dex
= unicosmk_need_dex (x
);
5282 fprintf (file
, "DEX(%d)", dex
);
5284 output_addr_const (file
, x
);
5288 case 'C': case 'D': case 'c': case 'd':
5289 /* Write out comparison name. */
5291 enum rtx_code c
= GET_CODE (x
);
5293 if (!COMPARISON_P (x
))
5294 output_operand_lossage ("invalid %%C value");
5296 else if (code
== 'D')
5297 c
= reverse_condition (c
);
5298 else if (code
== 'c')
5299 c
= swap_condition (c
);
5300 else if (code
== 'd')
5301 c
= swap_condition (reverse_condition (c
));
5304 fprintf (file
, "ule");
5306 fprintf (file
, "ult");
5307 else if (c
== UNORDERED
)
5308 fprintf (file
, "un");
5310 fprintf (file
, "%s", GET_RTX_NAME (c
));
5315 /* Write the divide or modulus operator. */
5316 switch (GET_CODE (x
))
5319 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5322 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5325 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5328 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5331 output_operand_lossage ("invalid %%E value");
5337 /* Write "_u" for unaligned access. */
5338 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5339 fprintf (file
, "_u");
5343 if (GET_CODE (x
) == REG
)
5344 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5345 else if (GET_CODE (x
) == MEM
)
5346 output_address (XEXP (x
, 0));
5347 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5349 switch (XINT (XEXP (x
, 0), 1))
5353 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5356 output_operand_lossage ("unknown relocation unspec");
5361 output_addr_const (file
, x
);
5365 output_operand_lossage ("invalid %%xn code");
5370 print_operand_address (FILE *file
, rtx addr
)
5373 HOST_WIDE_INT offset
= 0;
5375 if (GET_CODE (addr
) == AND
)
5376 addr
= XEXP (addr
, 0);
5378 if (GET_CODE (addr
) == PLUS
5379 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5381 offset
= INTVAL (XEXP (addr
, 1));
5382 addr
= XEXP (addr
, 0);
5385 if (GET_CODE (addr
) == LO_SUM
)
5387 const char *reloc16
, *reloclo
;
5388 rtx op1
= XEXP (addr
, 1);
5390 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5392 op1
= XEXP (op1
, 0);
5393 switch (XINT (op1
, 1))
5397 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5401 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5404 output_operand_lossage ("unknown relocation unspec");
5408 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5413 reloclo
= "gprellow";
5414 output_addr_const (file
, op1
);
5418 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5420 addr
= XEXP (addr
, 0);
5421 switch (GET_CODE (addr
))
5424 basereg
= REGNO (addr
);
5428 basereg
= subreg_regno (addr
);
5435 fprintf (file
, "($%d)\t\t!%s", basereg
,
5436 (basereg
== 29 ? reloc16
: reloclo
));
5440 switch (GET_CODE (addr
))
5443 basereg
= REGNO (addr
);
5447 basereg
= subreg_regno (addr
);
5451 offset
= INTVAL (addr
);
5454 #if TARGET_ABI_OPEN_VMS
5456 fprintf (file
, "%s", XSTR (addr
, 0));
5460 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
5461 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
);
5462 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5463 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5464 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5472 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5475 /* Emit RTL insns to initialize the variable parts of a trampoline at
5476 TRAMP. FNADDR is an RTX for the address of the function's pure
5477 code. CXT is an RTX for the static chain value for the function.
5479 The three offset parameters are for the individual template's
5480 layout. A JMPOFS < 0 indicates that the trampoline does not
5481 contain instructions at all.
5483 We assume here that a function will be called many more times than
5484 its address is taken (e.g., it might be passed to qsort), so we
5485 take the trouble to initialize the "hint" field in the JMP insn.
5486 Note that the hint field is PC (new) + 4 * bits 13:0. */
5489 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5490 int fnofs
, int cxtofs
, int jmpofs
)
5492 rtx temp
, temp1
, addr
;
5493 /* VMS really uses DImode pointers in memory at this point. */
5494 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5496 #ifdef POINTERS_EXTEND_UNSIGNED
5497 fnaddr
= convert_memory_address (mode
, fnaddr
);
5498 cxt
= convert_memory_address (mode
, cxt
);
5501 /* Store function address and CXT. */
5502 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5503 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5504 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5505 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5507 /* This has been disabled since the hint only has a 32k range, and in
5508 no existing OS is the stack within 32k of the text segment. */
5509 if (0 && jmpofs
>= 0)
5511 /* Compute hint value. */
5512 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5513 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5515 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5516 build_int_cst (NULL_TREE
, 2), NULL_RTX
, 1);
5517 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5518 GEN_INT (0x3fff), 0);
5520 /* Merge in the hint. */
5521 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5522 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5523 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5524 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5526 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5529 #ifdef ENABLE_EXECUTE_STACK
5530 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5531 0, VOIDmode
, 1, tramp
, Pmode
);
5535 emit_insn (gen_imb ());
5538 /* Determine where to put an argument to a function.
5539 Value is zero to push the argument on the stack,
5540 or a hard register in which to store the argument.
5542 MODE is the argument's machine mode.
5543 TYPE is the data type of the argument (as a tree).
5544 This is null for libcalls where that information may
5546 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5547 the preceding args and about the function being called.
5548 NAMED is nonzero if this argument is a named parameter
5549 (otherwise it is an extra parameter matching an ellipsis).
5551 On Alpha the first 6 words of args are normally in registers
5552 and the rest are pushed. */
5555 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5556 int named ATTRIBUTE_UNUSED
)
5561 /* Don't get confused and pass small structures in FP registers. */
5562 if (type
&& AGGREGATE_TYPE_P (type
))
5566 #ifdef ENABLE_CHECKING
5567 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5569 gcc_assert (!COMPLEX_MODE_P (mode
));
5572 /* Set up defaults for FP operands passed in FP registers, and
5573 integral operands passed in integer registers. */
5574 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5580 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5581 the three platforms, so we can't avoid conditional compilation. */
5582 #if TARGET_ABI_OPEN_VMS
5584 if (mode
== VOIDmode
)
5585 return alpha_arg_info_reg_val (cum
);
5587 num_args
= cum
.num_args
;
5589 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5592 #elif TARGET_ABI_UNICOSMK
5596 /* If this is the last argument, generate the call info word (CIW). */
5597 /* ??? We don't include the caller's line number in the CIW because
5598 I don't know how to determine it if debug infos are turned off. */
5599 if (mode
== VOIDmode
)
5608 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5609 if (cum
.reg_args_type
[i
])
5610 lo
|= (1 << (7 - i
));
5612 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5615 lo
|= cum
.num_reg_words
;
5617 #if HOST_BITS_PER_WIDE_INT == 32
5618 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5620 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5621 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5624 ciw
= immed_double_const (lo
, hi
, DImode
);
5626 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5627 UNSPEC_UMK_LOAD_CIW
);
5630 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5631 num_args
= cum
.num_reg_words
;
5633 || cum
.num_reg_words
+ size
> 6
5634 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5636 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5640 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5641 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5643 /* The argument fits in two registers. Note that we still need to
5644 reserve a register for empty structures. */
5648 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5651 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5652 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5653 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5657 #elif TARGET_ABI_OSF
5663 /* VOID is passed as a special flag for "last argument". */
5664 if (type
== void_type_node
)
5666 else if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5670 #error Unhandled ABI
5673 return gen_rtx_REG (mode
, num_args
+ basereg
);
5677 alpha_arg_partial_bytes (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5678 enum machine_mode mode ATTRIBUTE_UNUSED
,
5679 tree type ATTRIBUTE_UNUSED
,
5680 bool named ATTRIBUTE_UNUSED
)
5684 #if TARGET_ABI_OPEN_VMS
5685 if (cum
->num_args
< 6
5686 && 6 < cum
->num_args
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5687 words
= 6 - (CUM
).num_args
;
5688 #elif TARGET_ABI_UNICOSMK
5689 /* Never any split arguments. */
5690 #elif TARGET_ABI_OSF
5691 if (*cum
< 6 && 6 < *cum
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5694 #error Unhandled ABI
5697 return words
* UNITS_PER_WORD
;
5701 /* Return true if TYPE must be returned in memory, instead of in registers. */
5704 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
5706 enum machine_mode mode
= VOIDmode
;
5711 mode
= TYPE_MODE (type
);
5713 /* All aggregates are returned in memory. */
5714 if (AGGREGATE_TYPE_P (type
))
5718 size
= GET_MODE_SIZE (mode
);
5719 switch (GET_MODE_CLASS (mode
))
5721 case MODE_VECTOR_FLOAT
:
5722 /* Pass all float vectors in memory, like an aggregate. */
5725 case MODE_COMPLEX_FLOAT
:
5726 /* We judge complex floats on the size of their element,
5727 not the size of the whole type. */
5728 size
= GET_MODE_UNIT_SIZE (mode
);
5733 case MODE_COMPLEX_INT
:
5734 case MODE_VECTOR_INT
:
5738 /* ??? We get called on all sorts of random stuff from
5739 aggregate_value_p. We must return something, but it's not
5740 clear what's safe to return. Pretend it's a struct I
5745 /* Otherwise types must fit in one register. */
5746 return size
> UNITS_PER_WORD
;
5749 /* Return true if TYPE should be passed by invisible reference. */
5752 alpha_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
5753 enum machine_mode mode
,
5754 tree type ATTRIBUTE_UNUSED
,
5755 bool named ATTRIBUTE_UNUSED
)
5757 return mode
== TFmode
|| mode
== TCmode
;
5760 /* Define how to find the value returned by a function. VALTYPE is the
5761 data type of the value (as a tree). If the precise function being
5762 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5763 MODE is set instead of VALTYPE for libcalls.
5765 On Alpha the value is found in $0 for integer functions and
5766 $f0 for floating-point functions. */
5769 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
5770 enum machine_mode mode
)
5772 unsigned int regnum
, dummy
;
5773 enum mode_class
class;
5775 gcc_assert (!valtype
|| !alpha_return_in_memory (valtype
, func
));
5778 mode
= TYPE_MODE (valtype
);
5780 class = GET_MODE_CLASS (mode
);
5784 PROMOTE_MODE (mode
, dummy
, valtype
);
5787 case MODE_COMPLEX_INT
:
5788 case MODE_VECTOR_INT
:
5796 case MODE_COMPLEX_FLOAT
:
5798 enum machine_mode cmode
= GET_MODE_INNER (mode
);
5800 return gen_rtx_PARALLEL
5803 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
5805 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
5806 GEN_INT (GET_MODE_SIZE (cmode
)))));
5813 return gen_rtx_REG (mode
, regnum
);
5816 /* TCmode complex values are passed by invisible reference. We
5817 should not split these values. */
5820 alpha_split_complex_arg (tree type
)
5822 return TYPE_MODE (type
) != TCmode
;
5826 alpha_build_builtin_va_list (void)
5828 tree base
, ofs
, space
, record
, type_decl
;
5830 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5831 return ptr_type_node
;
5833 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5834 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5835 TREE_CHAIN (record
) = type_decl
;
5836 TYPE_NAME (record
) = type_decl
;
5838 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5840 /* Dummy field to prevent alignment warnings. */
5841 space
= build_decl (FIELD_DECL
, NULL_TREE
, integer_type_node
);
5842 DECL_FIELD_CONTEXT (space
) = record
;
5843 DECL_ARTIFICIAL (space
) = 1;
5844 DECL_IGNORED_P (space
) = 1;
5846 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
5848 DECL_FIELD_CONTEXT (ofs
) = record
;
5849 TREE_CHAIN (ofs
) = space
;
5851 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
5853 DECL_FIELD_CONTEXT (base
) = record
;
5854 TREE_CHAIN (base
) = ofs
;
5856 TYPE_FIELDS (record
) = base
;
5857 layout_type (record
);
5859 va_list_gpr_counter_field
= ofs
;
5864 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5865 and constant additions. */
5868 va_list_skip_additions (tree lhs
)
5872 if (TREE_CODE (lhs
) != SSA_NAME
)
5877 stmt
= SSA_NAME_DEF_STMT (lhs
);
5879 if (TREE_CODE (stmt
) == PHI_NODE
)
5882 if (TREE_CODE (stmt
) != MODIFY_EXPR
5883 || TREE_OPERAND (stmt
, 0) != lhs
)
5886 rhs
= TREE_OPERAND (stmt
, 1);
5887 if (TREE_CODE (rhs
) == WITH_SIZE_EXPR
)
5888 rhs
= TREE_OPERAND (rhs
, 0);
5890 if ((TREE_CODE (rhs
) != NOP_EXPR
5891 && TREE_CODE (rhs
) != CONVERT_EXPR
5892 && (TREE_CODE (rhs
) != PLUS_EXPR
5893 || TREE_CODE (TREE_OPERAND (rhs
, 1)) != INTEGER_CST
5894 || !host_integerp (TREE_OPERAND (rhs
, 1), 1)))
5895 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5898 lhs
= TREE_OPERAND (rhs
, 0);
5902 /* Check if LHS = RHS statement is
5903 LHS = *(ap.__base + ap.__offset + cst)
5906 + ((ap.__offset + cst <= 47)
5907 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
5908 If the former, indicate that GPR registers are needed,
5909 if the latter, indicate that FPR registers are needed.
5910 On alpha, cfun->va_list_gpr_size is used as size of the needed
5911 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if
5912 GPR registers are needed and bit 1 set if FPR registers are needed.
5913 Return true if va_list references should not be scanned for the current
5917 alpha_stdarg_optimize_hook (struct stdarg_info
*si
, tree lhs
, tree rhs
)
5919 tree base
, offset
, arg1
, arg2
;
5922 if (TREE_CODE (rhs
) != INDIRECT_REF
5923 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5926 lhs
= va_list_skip_additions (TREE_OPERAND (rhs
, 0));
5927 if (lhs
== NULL_TREE
5928 || TREE_CODE (lhs
) != PLUS_EXPR
)
5931 base
= TREE_OPERAND (lhs
, 0);
5932 if (TREE_CODE (base
) == SSA_NAME
)
5933 base
= va_list_skip_additions (base
);
5935 if (TREE_CODE (base
) != COMPONENT_REF
5936 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5938 base
= TREE_OPERAND (lhs
, 0);
5939 if (TREE_CODE (base
) == SSA_NAME
)
5940 base
= va_list_skip_additions (base
);
5942 if (TREE_CODE (base
) != COMPONENT_REF
5943 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5949 base
= get_base_address (base
);
5950 if (TREE_CODE (base
) != VAR_DECL
5951 || !bitmap_bit_p (si
->va_list_vars
, DECL_UID (base
)))
5954 offset
= TREE_OPERAND (lhs
, offset_arg
);
5955 if (TREE_CODE (offset
) == SSA_NAME
)
5956 offset
= va_list_skip_additions (offset
);
5958 if (TREE_CODE (offset
) == PHI_NODE
)
5962 if (PHI_NUM_ARGS (offset
) != 2)
5965 arg1
= va_list_skip_additions (PHI_ARG_DEF (offset
, 0));
5966 arg2
= va_list_skip_additions (PHI_ARG_DEF (offset
, 1));
5967 if (TREE_CODE (arg2
) != MINUS_EXPR
&& TREE_CODE (arg2
) != PLUS_EXPR
)
5973 if (TREE_CODE (arg2
) != MINUS_EXPR
&& TREE_CODE (arg2
) != PLUS_EXPR
)
5976 if (!host_integerp (TREE_OPERAND (arg2
, 1), 0))
5979 sub
= tree_low_cst (TREE_OPERAND (arg2
, 1), 0);
5980 if (TREE_CODE (arg2
) == MINUS_EXPR
)
5982 if (sub
< -48 || sub
> -32)
5985 arg2
= va_list_skip_additions (TREE_OPERAND (arg2
, 0));
5989 if (TREE_CODE (arg1
) == SSA_NAME
)
5990 arg1
= va_list_skip_additions (arg1
);
5992 if (TREE_CODE (arg1
) != COMPONENT_REF
5993 || TREE_OPERAND (arg1
, 1) != va_list_gpr_counter_field
5994 || get_base_address (arg1
) != base
)
5997 /* Need floating point regs. */
5998 cfun
->va_list_fpr_size
|= 2;
6000 else if (TREE_CODE (offset
) != COMPONENT_REF
6001 || TREE_OPERAND (offset
, 1) != va_list_gpr_counter_field
6002 || get_base_address (offset
) != base
)
6005 /* Need general regs. */
6006 cfun
->va_list_fpr_size
|= 1;
6010 si
->va_list_escapes
= true;
6015 /* Perform any needed actions needed for a function that is receiving a
6016 variable number of arguments. */
6019 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
6020 tree type
, int *pretend_size
, int no_rtl
)
6022 CUMULATIVE_ARGS cum
= *pcum
;
6024 /* Skip the current argument. */
6025 FUNCTION_ARG_ADVANCE (cum
, mode
, type
, 1);
6027 #if TARGET_ABI_UNICOSMK
6028 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6029 arguments on the stack. Unfortunately, it doesn't always store the first
6030 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6031 with stdargs as we always have at least one named argument there. */
6032 if (cum
.num_reg_words
< 6)
6036 emit_insn (gen_umk_mismatch_args (GEN_INT (cum
.num_reg_words
)));
6037 emit_insn (gen_arg_home_umk ());
6041 #elif TARGET_ABI_OPEN_VMS
6042 /* For VMS, we allocate space for all 6 arg registers plus a count.
6044 However, if NO registers need to be saved, don't allocate any space.
6045 This is not only because we won't need the space, but because AP
6046 includes the current_pretend_args_size and we don't want to mess up
6047 any ap-relative addresses already made. */
6048 if (cum
.num_args
< 6)
6052 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6053 emit_insn (gen_arg_home ());
6055 *pretend_size
= 7 * UNITS_PER_WORD
;
6058 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6059 only push those that are remaining. However, if NO registers need to
6060 be saved, don't allocate any space. This is not only because we won't
6061 need the space, but because AP includes the current_pretend_args_size
6062 and we don't want to mess up any ap-relative addresses already made.
6064 If we are not to use the floating-point registers, save the integer
6065 registers where we would put the floating-point registers. This is
6066 not the most efficient way to implement varargs with just one register
6067 class, but it isn't worth doing anything more efficient in this rare
6074 int count
, set
= get_varargs_alias_set ();
6077 count
= cfun
->va_list_gpr_size
/ UNITS_PER_WORD
;
6078 if (count
> 6 - cum
)
6081 /* Detect whether integer registers or floating-point registers
6082 are needed by the detected va_arg statements. See above for
6083 how these values are computed. Note that the "escape" value
6084 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
6086 gcc_assert ((VA_LIST_MAX_FPR_SIZE
& 3) == 3);
6088 if (cfun
->va_list_fpr_size
& 1)
6090 tmp
= gen_rtx_MEM (BLKmode
,
6091 plus_constant (virtual_incoming_args_rtx
,
6092 (cum
+ 6) * UNITS_PER_WORD
));
6093 set_mem_alias_set (tmp
, set
);
6094 move_block_from_reg (16 + cum
, tmp
, count
);
6097 if (cfun
->va_list_fpr_size
& 2)
6099 tmp
= gen_rtx_MEM (BLKmode
,
6100 plus_constant (virtual_incoming_args_rtx
,
6101 cum
* UNITS_PER_WORD
));
6102 set_mem_alias_set (tmp
, set
);
6103 move_block_from_reg (16 + cum
+ TARGET_FPREGS
*32, tmp
, count
);
6106 *pretend_size
= 12 * UNITS_PER_WORD
;
6111 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6113 HOST_WIDE_INT offset
;
6114 tree t
, offset_field
, base_field
;
6116 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6119 if (TARGET_ABI_UNICOSMK
)
6120 std_expand_builtin_va_start (valist
, nextarg
);
6122 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6123 up by 48, storing fp arg registers in the first 48 bytes, and the
6124 integer arg registers in the next 48 bytes. This is only done,
6125 however, if any integer registers need to be stored.
6127 If no integer registers need be stored, then we must subtract 48
6128 in order to account for the integer arg registers which are counted
6129 in argsize above, but which are not actually stored on the stack.
6130 Must further be careful here about structures straddling the last
6131 integer argument register; that futzes with pretend_args_size,
6132 which changes the meaning of AP. */
6135 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6137 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6139 if (TARGET_ABI_OPEN_VMS
)
6141 nextarg
= plus_constant (nextarg
, offset
);
6142 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6143 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6144 make_tree (ptr_type_node
, nextarg
));
6145 TREE_SIDE_EFFECTS (t
) = 1;
6147 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6151 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6152 offset_field
= TREE_CHAIN (base_field
);
6154 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6155 valist
, base_field
, NULL_TREE
);
6156 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6157 valist
, offset_field
, NULL_TREE
);
6159 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6160 t
= build (PLUS_EXPR
, ptr_type_node
, t
,
6161 build_int_cst (NULL_TREE
, offset
));
6162 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6163 TREE_SIDE_EFFECTS (t
) = 1;
6164 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6166 t
= build_int_cst (NULL_TREE
, NUM_ARGS
* UNITS_PER_WORD
);
6167 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6168 TREE_SIDE_EFFECTS (t
) = 1;
6169 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6174 alpha_gimplify_va_arg_1 (tree type
, tree base
, tree offset
, tree
*pre_p
)
6176 tree type_size
, ptr_type
, addend
, t
, addr
, internal_post
;
6178 /* If the type could not be passed in registers, skip the block
6179 reserved for the registers. */
6180 if (targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
6182 t
= build_int_cst (TREE_TYPE (offset
), 6*8);
6183 t
= build (MODIFY_EXPR
, TREE_TYPE (offset
), offset
,
6184 build (MAX_EXPR
, TREE_TYPE (offset
), offset
, t
));
6185 gimplify_and_add (t
, pre_p
);
6189 ptr_type
= build_pointer_type (type
);
6191 if (TREE_CODE (type
) == COMPLEX_TYPE
)
6193 tree real_part
, imag_part
, real_temp
;
6195 real_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6198 /* Copy the value into a new temporary, lest the formal temporary
6199 be reused out from under us. */
6200 real_temp
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
6202 imag_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6205 return build (COMPLEX_EXPR
, type
, real_temp
, imag_part
);
6207 else if (TREE_CODE (type
) == REAL_TYPE
)
6209 tree fpaddend
, cond
, fourtyeight
;
6211 fourtyeight
= build_int_cst (TREE_TYPE (addend
), 6*8);
6212 fpaddend
= fold (build (MINUS_EXPR
, TREE_TYPE (addend
),
6213 addend
, fourtyeight
));
6214 cond
= fold (build (LT_EXPR
, boolean_type_node
, addend
, fourtyeight
));
6215 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6219 /* Build the final address and force that value into a temporary. */
6220 addr
= build (PLUS_EXPR
, ptr_type
, fold_convert (ptr_type
, base
),
6221 fold_convert (ptr_type
, addend
));
6222 internal_post
= NULL
;
6223 gimplify_expr (&addr
, pre_p
, &internal_post
, is_gimple_val
, fb_rvalue
);
6224 append_to_statement_list (internal_post
, pre_p
);
6226 /* Update the offset field. */
6227 type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
));
6228 if (type_size
== NULL
|| TREE_OVERFLOW (type_size
))
6232 t
= size_binop (PLUS_EXPR
, type_size
, size_int (7));
6233 t
= size_binop (TRUNC_DIV_EXPR
, t
, size_int (8));
6234 t
= size_binop (MULT_EXPR
, t
, size_int (8));
6236 t
= fold_convert (TREE_TYPE (offset
), t
);
6237 t
= build (MODIFY_EXPR
, void_type_node
, offset
,
6238 build (PLUS_EXPR
, TREE_TYPE (offset
), offset
, t
));
6239 gimplify_and_add (t
, pre_p
);
6241 return build_fold_indirect_ref (addr
);
6245 alpha_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
6247 tree offset_field
, base_field
, offset
, base
, t
, r
;
6250 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6251 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6253 base_field
= TYPE_FIELDS (va_list_type_node
);
6254 offset_field
= TREE_CHAIN (base_field
);
6255 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6256 valist
, base_field
, NULL_TREE
);
6257 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6258 valist
, offset_field
, NULL_TREE
);
6260 /* Pull the fields of the structure out into temporaries. Since we never
6261 modify the base field, we can use a formal temporary. Sign-extend the
6262 offset field so that it's the proper width for pointer arithmetic. */
6263 base
= get_formal_tmp_var (base_field
, pre_p
);
6265 t
= fold_convert (lang_hooks
.types
.type_for_size (64, 0), offset_field
);
6266 offset
= get_initialized_tmp_var (t
, pre_p
, NULL
);
6268 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6270 type
= build_pointer_type (type
);
6272 /* Find the value. Note that this will be a stable indirection, or
6273 a composite of stable indirections in the case of complex. */
6274 r
= alpha_gimplify_va_arg_1 (type
, base
, offset
, pre_p
);
6276 /* Stuff the offset temporary back into its field. */
6277 t
= build (MODIFY_EXPR
, void_type_node
, offset_field
,
6278 fold_convert (TREE_TYPE (offset_field
), offset
));
6279 gimplify_and_add (t
, pre_p
);
6282 r
= build_fold_indirect_ref (r
);
6291 ALPHA_BUILTIN_CMPBGE
,
6292 ALPHA_BUILTIN_EXTBL
,
6293 ALPHA_BUILTIN_EXTWL
,
6294 ALPHA_BUILTIN_EXTLL
,
6295 ALPHA_BUILTIN_EXTQL
,
6296 ALPHA_BUILTIN_EXTWH
,
6297 ALPHA_BUILTIN_EXTLH
,
6298 ALPHA_BUILTIN_EXTQH
,
6299 ALPHA_BUILTIN_INSBL
,
6300 ALPHA_BUILTIN_INSWL
,
6301 ALPHA_BUILTIN_INSLL
,
6302 ALPHA_BUILTIN_INSQL
,
6303 ALPHA_BUILTIN_INSWH
,
6304 ALPHA_BUILTIN_INSLH
,
6305 ALPHA_BUILTIN_INSQH
,
6306 ALPHA_BUILTIN_MSKBL
,
6307 ALPHA_BUILTIN_MSKWL
,
6308 ALPHA_BUILTIN_MSKLL
,
6309 ALPHA_BUILTIN_MSKQL
,
6310 ALPHA_BUILTIN_MSKWH
,
6311 ALPHA_BUILTIN_MSKLH
,
6312 ALPHA_BUILTIN_MSKQH
,
6313 ALPHA_BUILTIN_UMULH
,
6315 ALPHA_BUILTIN_ZAPNOT
,
6316 ALPHA_BUILTIN_AMASK
,
6317 ALPHA_BUILTIN_IMPLVER
,
6319 ALPHA_BUILTIN_THREAD_POINTER
,
6320 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6323 ALPHA_BUILTIN_MINUB8
,
6324 ALPHA_BUILTIN_MINSB8
,
6325 ALPHA_BUILTIN_MINUW4
,
6326 ALPHA_BUILTIN_MINSW4
,
6327 ALPHA_BUILTIN_MAXUB8
,
6328 ALPHA_BUILTIN_MAXSB8
,
6329 ALPHA_BUILTIN_MAXUW4
,
6330 ALPHA_BUILTIN_MAXSW4
,
6334 ALPHA_BUILTIN_UNPKBL
,
6335 ALPHA_BUILTIN_UNPKBW
,
6340 ALPHA_BUILTIN_CTPOP
,
6345 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6346 CODE_FOR_builtin_cmpbge
,
6347 CODE_FOR_builtin_extbl
,
6348 CODE_FOR_builtin_extwl
,
6349 CODE_FOR_builtin_extll
,
6350 CODE_FOR_builtin_extql
,
6351 CODE_FOR_builtin_extwh
,
6352 CODE_FOR_builtin_extlh
,
6353 CODE_FOR_builtin_extqh
,
6354 CODE_FOR_builtin_insbl
,
6355 CODE_FOR_builtin_inswl
,
6356 CODE_FOR_builtin_insll
,
6357 CODE_FOR_builtin_insql
,
6358 CODE_FOR_builtin_inswh
,
6359 CODE_FOR_builtin_inslh
,
6360 CODE_FOR_builtin_insqh
,
6361 CODE_FOR_builtin_mskbl
,
6362 CODE_FOR_builtin_mskwl
,
6363 CODE_FOR_builtin_mskll
,
6364 CODE_FOR_builtin_mskql
,
6365 CODE_FOR_builtin_mskwh
,
6366 CODE_FOR_builtin_msklh
,
6367 CODE_FOR_builtin_mskqh
,
6368 CODE_FOR_umuldi3_highpart
,
6369 CODE_FOR_builtin_zap
,
6370 CODE_FOR_builtin_zapnot
,
6371 CODE_FOR_builtin_amask
,
6372 CODE_FOR_builtin_implver
,
6373 CODE_FOR_builtin_rpcc
,
6378 CODE_FOR_builtin_minub8
,
6379 CODE_FOR_builtin_minsb8
,
6380 CODE_FOR_builtin_minuw4
,
6381 CODE_FOR_builtin_minsw4
,
6382 CODE_FOR_builtin_maxub8
,
6383 CODE_FOR_builtin_maxsb8
,
6384 CODE_FOR_builtin_maxuw4
,
6385 CODE_FOR_builtin_maxsw4
,
6386 CODE_FOR_builtin_perr
,
6387 CODE_FOR_builtin_pklb
,
6388 CODE_FOR_builtin_pkwb
,
6389 CODE_FOR_builtin_unpkbl
,
6390 CODE_FOR_builtin_unpkbw
,
6395 CODE_FOR_popcountdi2
6398 struct alpha_builtin_def
6401 enum alpha_builtin code
;
6402 unsigned int target_mask
;
6406 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6407 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0, true },
6408 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0, false }
6411 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6412 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0, true },
6413 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
, true },
6414 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
, true },
6415 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
, true },
6416 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
, true },
6417 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
, true },
6418 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
, true },
6419 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
, true }
6422 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6423 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0, true },
6424 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0, true },
6425 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0, true },
6426 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0, true },
6427 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0, true },
6428 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0, true },
6429 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0, true },
6430 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0, true },
6431 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0, true },
6432 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0, true },
6433 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0, true },
6434 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0, true },
6435 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0, true },
6436 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0, true },
6437 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0, true },
6438 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0, true },
6439 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0, true },
6440 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0, true },
6441 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0, true },
6442 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0, true },
6443 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0, true },
6444 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0, true },
6445 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0, true },
6446 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0, true },
6447 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0, true },
6448 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
, true },
6449 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
, true },
6450 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
, true },
6451 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
, true },
6452 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
, true },
6453 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
, true },
6454 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
, true },
6455 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
, true },
6456 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
, true }
6459 static GTY(()) tree alpha_v8qi_u
;
6460 static GTY(()) tree alpha_v8qi_s
;
6461 static GTY(()) tree alpha_v4hi_u
;
6462 static GTY(()) tree alpha_v4hi_s
;
6465 alpha_init_builtins (void)
6467 const struct alpha_builtin_def
*p
;
6468 tree ftype
, attrs
[2];
6471 attrs
[0] = tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
6472 attrs
[1] = tree_cons (get_identifier ("const"), NULL
, attrs
[0]);
6474 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6476 p
= zero_arg_builtins
;
6477 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6478 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6479 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6480 NULL
, attrs
[p
->is_const
]);
6482 ftype
= build_function_type_list (long_integer_type_node
,
6483 long_integer_type_node
, NULL_TREE
);
6485 p
= one_arg_builtins
;
6486 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6487 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6488 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6489 NULL
, attrs
[p
->is_const
]);
6491 ftype
= build_function_type_list (long_integer_type_node
,
6492 long_integer_type_node
,
6493 long_integer_type_node
, NULL_TREE
);
6495 p
= two_arg_builtins
;
6496 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6497 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6498 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6499 NULL
, attrs
[p
->is_const
]);
6501 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6502 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
6503 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6506 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6507 lang_hooks
.builtin_function ("__builtin_set_thread_pointer", ftype
,
6508 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6511 alpha_v8qi_u
= build_vector_type (unsigned_intQI_type_node
, 8);
6512 alpha_v8qi_s
= build_vector_type (intQI_type_node
, 8);
6513 alpha_v4hi_u
= build_vector_type (unsigned_intHI_type_node
, 4);
6514 alpha_v4hi_s
= build_vector_type (intHI_type_node
, 4);
6517 /* Expand an expression EXP that calls a built-in function,
6518 with result going to TARGET if that's convenient
6519 (and in mode MODE if that's convenient).
6520 SUBTARGET may be used as the target for computing one of EXP's operands.
6521 IGNORE is nonzero if the value is to be ignored. */
6524 alpha_expand_builtin (tree exp
, rtx target
,
6525 rtx subtarget ATTRIBUTE_UNUSED
,
6526 enum machine_mode mode ATTRIBUTE_UNUSED
,
6527 int ignore ATTRIBUTE_UNUSED
)
6531 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6532 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6533 tree arglist
= TREE_OPERAND (exp
, 1);
6534 enum insn_code icode
;
6535 rtx op
[MAX_ARGS
], pat
;
6539 if (fcode
>= ALPHA_BUILTIN_max
)
6540 internal_error ("bad builtin fcode");
6541 icode
= code_for_builtin
[fcode
];
6543 internal_error ("bad builtin fcode");
6545 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6547 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6549 arglist
= TREE_CHAIN (arglist
), arity
++)
6551 const struct insn_operand_data
*insn_op
;
6553 tree arg
= TREE_VALUE (arglist
);
6554 if (arg
== error_mark_node
)
6556 if (arity
> MAX_ARGS
)
6559 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6561 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6563 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6564 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6569 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6571 || GET_MODE (target
) != tmode
6572 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6573 target
= gen_reg_rtx (tmode
);
6579 pat
= GEN_FCN (icode
) (target
);
6583 pat
= GEN_FCN (icode
) (target
, op
[0]);
6585 pat
= GEN_FCN (icode
) (op
[0]);
6588 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6604 /* Several bits below assume HWI >= 64 bits. This should be enforced
6606 #if HOST_BITS_PER_WIDE_INT < 64
6607 # error "HOST_WIDE_INT too small"
6610 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6611 with an 8 bit output vector. OPINT contains the integer operands; bit N
6612 of OP_CONST is set if OPINT[N] is valid. */
6615 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint
[], long op_const
)
6620 for (i
= 0, val
= 0; i
< 8; ++i
)
6622 unsigned HOST_WIDE_INT c0
= (opint
[0] >> (i
* 8)) & 0xff;
6623 unsigned HOST_WIDE_INT c1
= (opint
[1] >> (i
* 8)) & 0xff;
6627 return build_int_cst (long_integer_type_node
, val
);
6629 else if (op_const
== 2 && opint
[1] == 0)
6630 return build_int_cst (long_integer_type_node
, 0xff);
6634 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6635 specialized form of an AND operation. Other byte manipulation instructions
6636 are defined in terms of this instruction, so this is also used as a
6637 subroutine for other builtins.
6639 OP contains the tree operands; OPINT contains the extracted integer values.
6640 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6641 OPINT may be considered. */
6644 alpha_fold_builtin_zapnot (tree
*op
, unsigned HOST_WIDE_INT opint
[],
6649 unsigned HOST_WIDE_INT mask
= 0;
6652 for (i
= 0; i
< 8; ++i
)
6653 if ((opint
[1] >> i
) & 1)
6654 mask
|= (unsigned HOST_WIDE_INT
)0xff << (i
* 8);
6657 return build_int_cst (long_integer_type_node
, opint
[0] & mask
);
6660 return fold (build2 (BIT_AND_EXPR
, long_integer_type_node
, op
[0],
6661 build_int_cst (long_integer_type_node
, mask
)));
6663 else if ((op_const
& 1) && opint
[0] == 0)
6664 return build_int_cst (long_integer_type_node
, 0);
6668 /* Fold the builtins for the EXT family of instructions. */
6671 alpha_fold_builtin_extxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6672 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6676 tree
*zap_op
= NULL
;
6680 unsigned HOST_WIDE_INT loc
;
6683 if (BYTES_BIG_ENDIAN
)
6691 unsigned HOST_WIDE_INT temp
= opint
[0];
6704 opint
[1] = bytemask
;
6705 return alpha_fold_builtin_zapnot (zap_op
, opint
, zap_const
);
6708 /* Fold the builtins for the INS family of instructions. */
6711 alpha_fold_builtin_insxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6712 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6715 if ((op_const
& 1) && opint
[0] == 0)
6716 return build_int_cst (long_integer_type_node
, 0);
6720 unsigned HOST_WIDE_INT temp
, loc
, byteloc
;
6721 tree
*zap_op
= NULL
;
6724 if (BYTES_BIG_ENDIAN
)
6731 byteloc
= (64 - (loc
* 8)) & 0x3f;
6748 opint
[1] = bytemask
;
6749 return alpha_fold_builtin_zapnot (zap_op
, opint
, op_const
);
6756 alpha_fold_builtin_mskxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6757 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6762 unsigned HOST_WIDE_INT loc
;
6765 if (BYTES_BIG_ENDIAN
)
6772 opint
[1] = bytemask
^ 0xff;
6775 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
6779 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint
[], long op_const
)
6785 unsigned HOST_WIDE_INT l
;
6788 mul_double (opint
[0], 0, opint
[1], 0, &l
, &h
);
6790 #if HOST_BITS_PER_WIDE_INT > 64
6794 return build_int_cst (long_integer_type_node
, h
);
6798 opint
[1] = opint
[0];
6801 /* Note that (X*1) >> 64 == 0. */
6802 if (opint
[1] == 0 || opint
[1] == 1)
6803 return build_int_cst (long_integer_type_node
, 0);
6810 alpha_fold_vector_minmax (enum tree_code code
, tree op
[], tree vtype
)
6812 tree op0
= fold_convert (vtype
, op
[0]);
6813 tree op1
= fold_convert (vtype
, op
[1]);
6814 tree val
= fold (build2 (code
, vtype
, op0
, op1
));
6815 return fold_convert (long_integer_type_node
, val
);
6819 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint
[], long op_const
)
6821 unsigned HOST_WIDE_INT temp
= 0;
6827 for (i
= 0; i
< 8; ++i
)
6829 unsigned HOST_WIDE_INT a
= (opint
[0] >> (i
* 8)) & 0xff;
6830 unsigned HOST_WIDE_INT b
= (opint
[1] >> (i
* 8)) & 0xff;
6837 return build_int_cst (long_integer_type_node
, temp
);
6841 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6843 unsigned HOST_WIDE_INT temp
;
6848 temp
= opint
[0] & 0xff;
6849 temp
|= (opint
[0] >> 24) & 0xff00;
6851 return build_int_cst (long_integer_type_node
, temp
);
6855 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6857 unsigned HOST_WIDE_INT temp
;
6862 temp
= opint
[0] & 0xff;
6863 temp
|= (opint
[0] >> 8) & 0xff00;
6864 temp
|= (opint
[0] >> 16) & 0xff0000;
6865 temp
|= (opint
[0] >> 24) & 0xff000000;
6867 return build_int_cst (long_integer_type_node
, temp
);
6871 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint
[], long op_const
)
6873 unsigned HOST_WIDE_INT temp
;
6878 temp
= opint
[0] & 0xff;
6879 temp
|= (opint
[0] & 0xff00) << 24;
6881 return build_int_cst (long_integer_type_node
, temp
);
6885 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint
[], long op_const
)
6887 unsigned HOST_WIDE_INT temp
;
6892 temp
= opint
[0] & 0xff;
6893 temp
|= (opint
[0] & 0x0000ff00) << 8;
6894 temp
|= (opint
[0] & 0x00ff0000) << 16;
6895 temp
|= (opint
[0] & 0xff000000) << 24;
6897 return build_int_cst (long_integer_type_node
, temp
);
6901 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6903 unsigned HOST_WIDE_INT temp
;
6911 temp
= exact_log2 (opint
[0] & -opint
[0]);
6913 return build_int_cst (long_integer_type_node
, temp
);
6917 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6919 unsigned HOST_WIDE_INT temp
;
6927 temp
= 64 - floor_log2 (opint
[0]) - 1;
6929 return build_int_cst (long_integer_type_node
, temp
);
6933 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint
[], long op_const
)
6935 unsigned HOST_WIDE_INT temp
, op
;
6943 temp
++, op
&= op
- 1;
6945 return build_int_cst (long_integer_type_node
, temp
);
6948 /* Fold one of our builtin functions. */
6951 alpha_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
6953 tree op
[MAX_ARGS
], t
;
6954 unsigned HOST_WIDE_INT opint
[MAX_ARGS
];
6955 long op_const
= 0, arity
= 0;
6957 for (t
= arglist
; t
; t
= TREE_CHAIN (t
), ++arity
)
6959 tree arg
= TREE_VALUE (t
);
6960 if (arg
== error_mark_node
)
6962 if (arity
>= MAX_ARGS
)
6967 if (TREE_CODE (arg
) == INTEGER_CST
)
6969 op_const
|= 1L << arity
;
6970 opint
[arity
] = int_cst_value (arg
);
6974 switch (DECL_FUNCTION_CODE (fndecl
))
6976 case ALPHA_BUILTIN_CMPBGE
:
6977 return alpha_fold_builtin_cmpbge (opint
, op_const
);
6979 case ALPHA_BUILTIN_EXTBL
:
6980 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x01, false);
6981 case ALPHA_BUILTIN_EXTWL
:
6982 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, false);
6983 case ALPHA_BUILTIN_EXTLL
:
6984 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, false);
6985 case ALPHA_BUILTIN_EXTQL
:
6986 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, false);
6987 case ALPHA_BUILTIN_EXTWH
:
6988 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, true);
6989 case ALPHA_BUILTIN_EXTLH
:
6990 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, true);
6991 case ALPHA_BUILTIN_EXTQH
:
6992 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, true);
6994 case ALPHA_BUILTIN_INSBL
:
6995 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x01, false);
6996 case ALPHA_BUILTIN_INSWL
:
6997 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, false);
6998 case ALPHA_BUILTIN_INSLL
:
6999 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, false);
7000 case ALPHA_BUILTIN_INSQL
:
7001 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, false);
7002 case ALPHA_BUILTIN_INSWH
:
7003 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, true);
7004 case ALPHA_BUILTIN_INSLH
:
7005 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, true);
7006 case ALPHA_BUILTIN_INSQH
:
7007 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, true);
7009 case ALPHA_BUILTIN_MSKBL
:
7010 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x01, false);
7011 case ALPHA_BUILTIN_MSKWL
:
7012 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, false);
7013 case ALPHA_BUILTIN_MSKLL
:
7014 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, false);
7015 case ALPHA_BUILTIN_MSKQL
:
7016 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, false);
7017 case ALPHA_BUILTIN_MSKWH
:
7018 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, true);
7019 case ALPHA_BUILTIN_MSKLH
:
7020 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, true);
7021 case ALPHA_BUILTIN_MSKQH
:
7022 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, true);
7024 case ALPHA_BUILTIN_UMULH
:
7025 return alpha_fold_builtin_umulh (opint
, op_const
);
7027 case ALPHA_BUILTIN_ZAP
:
7030 case ALPHA_BUILTIN_ZAPNOT
:
7031 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
7033 case ALPHA_BUILTIN_MINUB8
:
7034 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_u
);
7035 case ALPHA_BUILTIN_MINSB8
:
7036 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_s
);
7037 case ALPHA_BUILTIN_MINUW4
:
7038 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_u
);
7039 case ALPHA_BUILTIN_MINSW4
:
7040 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_s
);
7041 case ALPHA_BUILTIN_MAXUB8
:
7042 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_u
);
7043 case ALPHA_BUILTIN_MAXSB8
:
7044 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_s
);
7045 case ALPHA_BUILTIN_MAXUW4
:
7046 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_u
);
7047 case ALPHA_BUILTIN_MAXSW4
:
7048 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_s
);
7050 case ALPHA_BUILTIN_PERR
:
7051 return alpha_fold_builtin_perr (opint
, op_const
);
7052 case ALPHA_BUILTIN_PKLB
:
7053 return alpha_fold_builtin_pklb (opint
, op_const
);
7054 case ALPHA_BUILTIN_PKWB
:
7055 return alpha_fold_builtin_pkwb (opint
, op_const
);
7056 case ALPHA_BUILTIN_UNPKBL
:
7057 return alpha_fold_builtin_unpkbl (opint
, op_const
);
7058 case ALPHA_BUILTIN_UNPKBW
:
7059 return alpha_fold_builtin_unpkbw (opint
, op_const
);
7061 case ALPHA_BUILTIN_CTTZ
:
7062 return alpha_fold_builtin_cttz (opint
, op_const
);
7063 case ALPHA_BUILTIN_CTLZ
:
7064 return alpha_fold_builtin_ctlz (opint
, op_const
);
7065 case ALPHA_BUILTIN_CTPOP
:
7066 return alpha_fold_builtin_ctpop (opint
, op_const
);
7068 case ALPHA_BUILTIN_AMASK
:
7069 case ALPHA_BUILTIN_IMPLVER
:
7070 case ALPHA_BUILTIN_RPCC
:
7071 case ALPHA_BUILTIN_THREAD_POINTER
:
7072 case ALPHA_BUILTIN_SET_THREAD_POINTER
:
7073 /* None of these are foldable at compile-time. */
7079 /* This page contains routines that are used to determine what the function
7080 prologue and epilogue code will do and write them out. */
7082 /* Compute the size of the save area in the stack. */
7084 /* These variables are used for communication between the following functions.
7085 They indicate various things about the current function being compiled
7086 that are used to tell what kind of prologue, epilogue and procedure
7087 descriptor to generate. */
7089 /* Nonzero if we need a stack procedure. */
7090 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
7091 static enum alpha_procedure_types alpha_procedure_type
;
7093 /* Register number (either FP or SP) that is used to unwind the frame. */
7094 static int vms_unwind_regno
;
7096 /* Register number used to save FP. We need not have one for RA since
7097 we don't modify it for register procedures. This is only defined
7098 for register frame procedures. */
7099 static int vms_save_fp_regno
;
7101 /* Register number used to reference objects off our PV. */
7102 static int vms_base_regno
;
7104 /* Compute register masks for saved registers. */
7107 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
7109 unsigned long imask
= 0;
7110 unsigned long fmask
= 0;
7113 /* When outputting a thunk, we don't have valid register life info,
7114 but assemble_start_function wants to output .frame and .mask
7116 if (current_function_is_thunk
)
7123 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7124 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
7126 /* One for every register we have to save. */
7127 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7128 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
7129 && regs_ever_live
[i
] && i
!= REG_RA
7130 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
7133 imask
|= (1UL << i
);
7135 fmask
|= (1UL << (i
- 32));
7138 /* We need to restore these for the handler. */
7139 if (current_function_calls_eh_return
)
7143 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
7144 if (regno
== INVALID_REGNUM
)
7146 imask
|= 1UL << regno
;
7150 /* If any register spilled, then spill the return address also. */
7151 /* ??? This is required by the Digital stack unwind specification
7152 and isn't needed if we're doing Dwarf2 unwinding. */
7153 if (imask
|| fmask
|| alpha_ra_ever_killed ())
7154 imask
|= (1UL << REG_RA
);
7161 alpha_sa_size (void)
7163 unsigned long mask
[2];
7167 alpha_sa_mask (&mask
[0], &mask
[1]);
7169 if (TARGET_ABI_UNICOSMK
)
7171 if (mask
[0] || mask
[1])
7176 for (j
= 0; j
< 2; ++j
)
7177 for (i
= 0; i
< 32; ++i
)
7178 if ((mask
[j
] >> i
) & 1)
7182 if (TARGET_ABI_UNICOSMK
)
7184 /* We might not need to generate a frame if we don't make any calls
7185 (including calls to __T3E_MISMATCH if this is a vararg function),
7186 don't have any local variables which require stack slots, don't
7187 use alloca and have not determined that we need a frame for other
7190 alpha_procedure_type
7191 = (sa_size
|| get_frame_size() != 0
7192 || current_function_outgoing_args_size
7193 || current_function_stdarg
|| current_function_calls_alloca
7194 || frame_pointer_needed
)
7195 ? PT_STACK
: PT_REGISTER
;
7197 /* Always reserve space for saving callee-saved registers if we
7198 need a frame as required by the calling convention. */
7199 if (alpha_procedure_type
== PT_STACK
)
7202 else if (TARGET_ABI_OPEN_VMS
)
7204 /* Start by assuming we can use a register procedure if we don't
7205 make any calls (REG_RA not used) or need to save any
7206 registers and a stack procedure if we do. */
7207 if ((mask
[0] >> REG_RA
) & 1)
7208 alpha_procedure_type
= PT_STACK
;
7209 else if (get_frame_size() != 0)
7210 alpha_procedure_type
= PT_REGISTER
;
7212 alpha_procedure_type
= PT_NULL
;
7214 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7215 made the final decision on stack procedure vs register procedure. */
7216 if (alpha_procedure_type
== PT_STACK
)
7219 /* Decide whether to refer to objects off our PV via FP or PV.
7220 If we need FP for something else or if we receive a nonlocal
7221 goto (which expects PV to contain the value), we must use PV.
7222 Otherwise, start by assuming we can use FP. */
7225 = (frame_pointer_needed
7226 || current_function_has_nonlocal_label
7227 || alpha_procedure_type
== PT_STACK
7228 || current_function_outgoing_args_size
)
7229 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7231 /* If we want to copy PV into FP, we need to find some register
7232 in which to save FP. */
7234 vms_save_fp_regno
= -1;
7235 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7236 for (i
= 0; i
< 32; i
++)
7237 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
7238 vms_save_fp_regno
= i
;
7240 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7241 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7242 else if (alpha_procedure_type
== PT_NULL
)
7243 vms_base_regno
= REG_PV
;
7245 /* Stack unwinding should be done via FP unless we use it for PV. */
7246 vms_unwind_regno
= (vms_base_regno
== REG_PV
7247 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7249 /* If this is a stack procedure, allow space for saving FP and RA. */
7250 if (alpha_procedure_type
== PT_STACK
)
7255 /* Our size must be even (multiple of 16 bytes). */
7263 /* Define the offset between two registers, one to be eliminated,
7264 and the other its replacement, at the start of a routine. */
7267 alpha_initial_elimination_offset (unsigned int from
,
7268 unsigned int to ATTRIBUTE_UNUSED
)
7272 ret
= alpha_sa_size ();
7273 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
7277 case FRAME_POINTER_REGNUM
:
7280 case ARG_POINTER_REGNUM
:
7281 ret
+= (ALPHA_ROUND (get_frame_size ()
7282 + current_function_pretend_args_size
)
7283 - current_function_pretend_args_size
);
7294 alpha_pv_save_size (void)
7297 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7301 alpha_using_fp (void)
7304 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7307 #if TARGET_ABI_OPEN_VMS
7309 const struct attribute_spec vms_attribute_table
[] =
7311 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7312 { "overlaid", 0, 0, true, false, false, NULL
},
7313 { "global", 0, 0, true, false, false, NULL
},
7314 { "initialize", 0, 0, true, false, false, NULL
},
7315 { NULL
, 0, 0, false, false, false, NULL
}
7321 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
7323 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7327 alpha_find_lo_sum_using_gp (rtx insn
)
7329 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7333 alpha_does_function_need_gp (void)
7337 /* The GP being variable is an OSF abi thing. */
7338 if (! TARGET_ABI_OSF
)
7341 /* We need the gp to load the address of __mcount. */
7342 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7345 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7346 if (current_function_is_thunk
)
7349 /* The nonlocal receiver pattern assumes that the gp is valid for
7350 the nested function. Reasonable because it's almost always set
7351 correctly already. For the cases where that's wrong, make sure
7352 the nested function loads its gp on entry. */
7353 if (current_function_has_nonlocal_goto
)
7356 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7357 Even if we are a static function, we still need to do this in case
7358 our address is taken and passed to something like qsort. */
7360 push_topmost_sequence ();
7361 insn
= get_insns ();
7362 pop_topmost_sequence ();
7364 for (; insn
; insn
= NEXT_INSN (insn
))
7366 && GET_CODE (PATTERN (insn
)) != USE
7367 && GET_CODE (PATTERN (insn
)) != CLOBBER
7368 && get_attr_usegp (insn
))
7375 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7379 set_frame_related_p (void)
7381 rtx seq
= get_insns ();
7392 while (insn
!= NULL_RTX
)
7394 RTX_FRAME_RELATED_P (insn
) = 1;
7395 insn
= NEXT_INSN (insn
);
7397 seq
= emit_insn (seq
);
7401 seq
= emit_insn (seq
);
7402 RTX_FRAME_RELATED_P (seq
) = 1;
7407 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7409 /* Generates a store with the proper unwind info attached. VALUE is
7410 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7411 contains SP+FRAME_BIAS, and that is the unwind info that should be
7412 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7413 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7416 emit_frame_store_1 (rtx value
, rtx base_reg
, HOST_WIDE_INT frame_bias
,
7417 HOST_WIDE_INT base_ofs
, rtx frame_reg
)
7419 rtx addr
, mem
, insn
;
7421 addr
= plus_constant (base_reg
, base_ofs
);
7422 mem
= gen_rtx_MEM (DImode
, addr
);
7423 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7425 insn
= emit_move_insn (mem
, value
);
7426 RTX_FRAME_RELATED_P (insn
) = 1;
7428 if (frame_bias
|| value
!= frame_reg
)
7432 addr
= plus_constant (stack_pointer_rtx
, frame_bias
+ base_ofs
);
7433 mem
= gen_rtx_MEM (DImode
, addr
);
7437 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7438 gen_rtx_SET (VOIDmode
, mem
, frame_reg
),
7444 emit_frame_store (unsigned int regno
, rtx base_reg
,
7445 HOST_WIDE_INT frame_bias
, HOST_WIDE_INT base_ofs
)
7447 rtx reg
= gen_rtx_REG (DImode
, regno
);
7448 emit_frame_store_1 (reg
, base_reg
, frame_bias
, base_ofs
, reg
);
7451 /* Write function prologue. */
7453 /* On vms we have two kinds of functions:
7455 - stack frame (PROC_STACK)
7456 these are 'normal' functions with local vars and which are
7457 calling other functions
7458 - register frame (PROC_REGISTER)
7459 keeps all data in registers, needs no stack
7461 We must pass this to the assembler so it can generate the
7462 proper pdsc (procedure descriptor)
7463 This is done with the '.pdesc' command.
7465 On not-vms, we don't really differentiate between the two, as we can
7466 simply allocate stack without saving registers. */
7469 alpha_expand_prologue (void)
7471 /* Registers to save. */
7472 unsigned long imask
= 0;
7473 unsigned long fmask
= 0;
7474 /* Stack space needed for pushing registers clobbered by us. */
7475 HOST_WIDE_INT sa_size
;
7476 /* Complete stack size needed. */
7477 HOST_WIDE_INT frame_size
;
7478 /* Offset from base reg to register save area. */
7479 HOST_WIDE_INT reg_offset
;
7483 sa_size
= alpha_sa_size ();
7485 frame_size
= get_frame_size ();
7486 if (TARGET_ABI_OPEN_VMS
)
7487 frame_size
= ALPHA_ROUND (sa_size
7488 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7490 + current_function_pretend_args_size
);
7491 else if (TARGET_ABI_UNICOSMK
)
7492 /* We have to allocate space for the DSIB if we generate a frame. */
7493 frame_size
= ALPHA_ROUND (sa_size
7494 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7495 + ALPHA_ROUND (frame_size
7496 + current_function_outgoing_args_size
);
7498 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7500 + ALPHA_ROUND (frame_size
7501 + current_function_pretend_args_size
));
7503 if (TARGET_ABI_OPEN_VMS
)
7506 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7508 alpha_sa_mask (&imask
, &fmask
);
7510 /* Emit an insn to reload GP, if needed. */
7513 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7514 if (alpha_function_needs_gp
)
7515 emit_insn (gen_prologue_ldgp ());
7518 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7519 the call to mcount ourselves, rather than having the linker do it
7520 magically in response to -pg. Since _mcount has special linkage,
7521 don't represent the call as a call. */
7522 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7523 emit_insn (gen_prologue_mcount ());
7525 if (TARGET_ABI_UNICOSMK
)
7526 unicosmk_gen_dsib (&imask
);
7528 /* Adjust the stack by the frame size. If the frame size is > 4096
7529 bytes, we need to be sure we probe somewhere in the first and last
7530 4096 bytes (we can probably get away without the latter test) and
7531 every 8192 bytes in between. If the frame size is > 32768, we
7532 do this in a loop. Otherwise, we generate the explicit probe
7535 Note that we are only allowed to adjust sp once in the prologue. */
7537 if (frame_size
<= 32768)
7539 if (frame_size
> 4096)
7544 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7547 while ((probed
+= 8192) < frame_size
);
7549 /* We only have to do this probe if we aren't saving registers. */
7550 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7551 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7554 if (frame_size
!= 0)
7555 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7556 GEN_INT (TARGET_ABI_UNICOSMK
7562 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7563 number of 8192 byte blocks to probe. We then probe each block
7564 in the loop and then set SP to the proper location. If the
7565 amount remaining is > 4096, we have to do one more probe if we
7566 are not saving any registers. */
7568 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7569 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7570 rtx ptr
= gen_rtx_REG (DImode
, 22);
7571 rtx count
= gen_rtx_REG (DImode
, 23);
7574 emit_move_insn (count
, GEN_INT (blocks
));
7575 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7576 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7578 /* Because of the difficulty in emitting a new basic block this
7579 late in the compilation, generate the loop as a single insn. */
7580 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7582 if (leftover
> 4096 && sa_size
== 0)
7584 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7585 MEM_VOLATILE_P (last
) = 1;
7586 emit_move_insn (last
, const0_rtx
);
7589 if (TARGET_ABI_WINDOWS_NT
)
7591 /* For NT stack unwind (done by 'reverse execution'), it's
7592 not OK to take the result of a loop, even though the value
7593 is already in ptr, so we reload it via a single operation
7594 and subtract it to sp.
7596 Yes, that's correct -- we have to reload the whole constant
7597 into a temporary via ldah+lda then subtract from sp. */
7599 HOST_WIDE_INT lo
, hi
;
7600 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7601 hi
= frame_size
- lo
;
7603 emit_move_insn (ptr
, GEN_INT (hi
));
7604 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7605 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7610 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7611 GEN_INT (-leftover
)));
7614 /* This alternative is special, because the DWARF code cannot
7615 possibly intuit through the loop above. So we invent this
7616 note it looks at instead. */
7617 RTX_FRAME_RELATED_P (seq
) = 1;
7619 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7620 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7621 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7622 GEN_INT (TARGET_ABI_UNICOSMK
7628 if (!TARGET_ABI_UNICOSMK
)
7630 HOST_WIDE_INT sa_bias
= 0;
7632 /* Cope with very large offsets to the register save area. */
7633 sa_reg
= stack_pointer_rtx
;
7634 if (reg_offset
+ sa_size
> 0x8000)
7636 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7639 if (low
+ sa_size
<= 0x8000)
7640 sa_bias
= reg_offset
- low
, reg_offset
= low
;
7642 sa_bias
= reg_offset
, reg_offset
= 0;
7644 sa_reg
= gen_rtx_REG (DImode
, 24);
7645 sa_bias_rtx
= GEN_INT (sa_bias
);
7647 if (add_operand (sa_bias_rtx
, DImode
))
7648 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_bias_rtx
));
7651 emit_move_insn (sa_reg
, sa_bias_rtx
);
7652 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_reg
));
7656 /* Save regs in stack order. Beginning with VMS PV. */
7657 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7658 emit_frame_store (REG_PV
, stack_pointer_rtx
, 0, 0);
7660 /* Save register RA next. */
7661 if (imask
& (1UL << REG_RA
))
7663 emit_frame_store (REG_RA
, sa_reg
, sa_bias
, reg_offset
);
7664 imask
&= ~(1UL << REG_RA
);
7668 /* Now save any other registers required to be saved. */
7669 for (i
= 0; i
< 31; i
++)
7670 if (imask
& (1UL << i
))
7672 emit_frame_store (i
, sa_reg
, sa_bias
, reg_offset
);
7676 for (i
= 0; i
< 31; i
++)
7677 if (fmask
& (1UL << i
))
7679 emit_frame_store (i
+32, sa_reg
, sa_bias
, reg_offset
);
7683 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7685 /* The standard frame on the T3E includes space for saving registers.
7686 We just have to use it. We don't have to save the return address and
7687 the old frame pointer here - they are saved in the DSIB. */
7690 for (i
= 9; i
< 15; i
++)
7691 if (imask
& (1UL << i
))
7693 emit_frame_store (i
, hard_frame_pointer_rtx
, 0, reg_offset
);
7696 for (i
= 2; i
< 10; i
++)
7697 if (fmask
& (1UL << i
))
7699 emit_frame_store (i
+32, hard_frame_pointer_rtx
, 0, reg_offset
);
7704 if (TARGET_ABI_OPEN_VMS
)
7706 if (alpha_procedure_type
== PT_REGISTER
)
7707 /* Register frame procedures save the fp.
7708 ?? Ought to have a dwarf2 save for this. */
7709 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7710 hard_frame_pointer_rtx
);
7712 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7713 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7714 gen_rtx_REG (DImode
, REG_PV
)));
7716 if (alpha_procedure_type
!= PT_NULL
7717 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7718 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7720 /* If we have to allocate space for outgoing args, do it now. */
7721 if (current_function_outgoing_args_size
!= 0)
7724 = emit_move_insn (stack_pointer_rtx
,
7726 (hard_frame_pointer_rtx
,
7728 (current_function_outgoing_args_size
))));
7730 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7731 if ! frame_pointer_needed. Setting the bit will change the CFA
7732 computation rule to use sp again, which would be wrong if we had
7733 frame_pointer_needed, as this means sp might move unpredictably
7737 frame_pointer_needed
7738 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7740 current_function_outgoing_args_size != 0
7741 => alpha_procedure_type != PT_NULL,
7743 so when we are not setting the bit here, we are guaranteed to
7744 have emitted an FRP frame pointer update just before. */
7745 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7748 else if (!TARGET_ABI_UNICOSMK
)
7750 /* If we need a frame pointer, set it from the stack pointer. */
7751 if (frame_pointer_needed
)
7753 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7754 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7756 /* This must always be the last instruction in the
7757 prologue, thus we emit a special move + clobber. */
7758 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7759 stack_pointer_rtx
, sa_reg
)));
7763 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7764 the prologue, for exception handling reasons, we cannot do this for
7765 any insn that might fault. We could prevent this for mems with a
7766 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7767 have to prevent all such scheduling with a blockage.
7769 Linux, on the other hand, never bothered to implement OSF/1's
7770 exception handling, and so doesn't care about such things. Anyone
7771 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7773 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7774 emit_insn (gen_blockage ());
7777 /* Count the number of .file directives, so that .loc is up to date. */
7778 int num_source_filenames
= 0;
7780 /* Output the textual info surrounding the prologue. */
7783 alpha_start_function (FILE *file
, const char *fnname
,
7784 tree decl ATTRIBUTE_UNUSED
)
7786 unsigned long imask
= 0;
7787 unsigned long fmask
= 0;
7788 /* Stack space needed for pushing registers clobbered by us. */
7789 HOST_WIDE_INT sa_size
;
7790 /* Complete stack size needed. */
7791 unsigned HOST_WIDE_INT frame_size
;
7792 /* Offset from base reg to register save area. */
7793 HOST_WIDE_INT reg_offset
;
7794 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7797 /* Don't emit an extern directive for functions defined in the same file. */
7798 if (TARGET_ABI_UNICOSMK
)
7801 name_tree
= get_identifier (fnname
);
7802 TREE_ASM_WRITTEN (name_tree
) = 1;
7805 alpha_fnname
= fnname
;
7806 sa_size
= alpha_sa_size ();
7808 frame_size
= get_frame_size ();
7809 if (TARGET_ABI_OPEN_VMS
)
7810 frame_size
= ALPHA_ROUND (sa_size
7811 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7813 + current_function_pretend_args_size
);
7814 else if (TARGET_ABI_UNICOSMK
)
7815 frame_size
= ALPHA_ROUND (sa_size
7816 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7817 + ALPHA_ROUND (frame_size
7818 + current_function_outgoing_args_size
);
7820 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7822 + ALPHA_ROUND (frame_size
7823 + current_function_pretend_args_size
));
7825 if (TARGET_ABI_OPEN_VMS
)
7828 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7830 alpha_sa_mask (&imask
, &fmask
);
7832 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7833 We have to do that before the .ent directive as we cannot switch
7834 files within procedures with native ecoff because line numbers are
7835 linked to procedure descriptors.
7836 Outputting the lineno helps debugging of one line functions as they
7837 would otherwise get no line number at all. Please note that we would
7838 like to put out last_linenum from final.c, but it is not accessible. */
7840 if (write_symbols
== SDB_DEBUG
)
7842 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7843 ASM_OUTPUT_SOURCE_FILENAME (file
,
7844 DECL_SOURCE_FILE (current_function_decl
));
7846 #ifdef SDB_OUTPUT_SOURCE_LINE
7847 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7848 SDB_OUTPUT_SOURCE_LINE (file
,
7849 DECL_SOURCE_LINE (current_function_decl
));
7853 /* Issue function start and label. */
7854 if (TARGET_ABI_OPEN_VMS
7855 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7857 fputs ("\t.ent ", file
);
7858 assemble_name (file
, fnname
);
7861 /* If the function needs GP, we'll write the "..ng" label there.
7862 Otherwise, do it here. */
7864 && ! alpha_function_needs_gp
7865 && ! current_function_is_thunk
)
7868 assemble_name (file
, fnname
);
7869 fputs ("..ng:\n", file
);
7873 strcpy (entry_label
, fnname
);
7874 if (TARGET_ABI_OPEN_VMS
)
7875 strcat (entry_label
, "..en");
7877 /* For public functions, the label must be globalized by appending an
7878 additional colon. */
7879 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7880 strcat (entry_label
, ":");
7882 ASM_OUTPUT_LABEL (file
, entry_label
);
7883 inside_function
= TRUE
;
7885 if (TARGET_ABI_OPEN_VMS
)
7886 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7888 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7889 && !flag_inhibit_size_directive
)
7891 /* Set flags in procedure descriptor to request IEEE-conformant
7892 math-library routines. The value we set it to is PDSC_EXC_IEEE
7893 (/usr/include/pdsc.h). */
7894 fputs ("\t.eflag 48\n", file
);
7897 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7898 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7899 alpha_arg_offset
= -frame_size
+ 48;
7901 /* Describe our frame. If the frame size is larger than an integer,
7902 print it as zero to avoid an assembler error. We won't be
7903 properly describing such a frame, but that's the best we can do. */
7904 if (TARGET_ABI_UNICOSMK
)
7906 else if (TARGET_ABI_OPEN_VMS
)
7907 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7908 HOST_WIDE_INT_PRINT_DEC
"\n",
7910 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7912 else if (!flag_inhibit_size_directive
)
7913 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7914 (frame_pointer_needed
7915 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7916 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7917 current_function_pretend_args_size
);
7919 /* Describe which registers were spilled. */
7920 if (TARGET_ABI_UNICOSMK
)
7922 else if (TARGET_ABI_OPEN_VMS
)
7925 /* ??? Does VMS care if mask contains ra? The old code didn't
7926 set it, so I don't here. */
7927 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7929 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7930 if (alpha_procedure_type
== PT_REGISTER
)
7931 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7933 else if (!flag_inhibit_size_directive
)
7937 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7938 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7940 for (i
= 0; i
< 32; ++i
)
7941 if (imask
& (1UL << i
))
7946 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7947 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7950 #if TARGET_ABI_OPEN_VMS
7951 /* Ifdef'ed cause link_section are only available then. */
7952 readonly_data_section ();
7953 fprintf (file
, "\t.align 3\n");
7954 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7955 fputs ("\t.ascii \"", file
);
7956 assemble_name (file
, fnname
);
7957 fputs ("\\0\"\n", file
);
7958 alpha_need_linkage (fnname
, 1);
7963 /* Emit the .prologue note at the scheduled end of the prologue. */
7966 alpha_output_function_end_prologue (FILE *file
)
7968 if (TARGET_ABI_UNICOSMK
)
7970 else if (TARGET_ABI_OPEN_VMS
)
7971 fputs ("\t.prologue\n", file
);
7972 else if (TARGET_ABI_WINDOWS_NT
)
7973 fputs ("\t.prologue 0\n", file
);
7974 else if (!flag_inhibit_size_directive
)
7975 fprintf (file
, "\t.prologue %d\n",
7976 alpha_function_needs_gp
|| current_function_is_thunk
);
7979 /* Write function epilogue. */
7981 /* ??? At some point we will want to support full unwind, and so will
7982 need to mark the epilogue as well. At the moment, we just confuse
7985 #define FRP(exp) exp
7988 alpha_expand_epilogue (void)
7990 /* Registers to save. */
7991 unsigned long imask
= 0;
7992 unsigned long fmask
= 0;
7993 /* Stack space needed for pushing registers clobbered by us. */
7994 HOST_WIDE_INT sa_size
;
7995 /* Complete stack size needed. */
7996 HOST_WIDE_INT frame_size
;
7997 /* Offset from base reg to register save area. */
7998 HOST_WIDE_INT reg_offset
;
7999 int fp_is_frame_pointer
, fp_offset
;
8000 rtx sa_reg
, sa_reg_exp
= NULL
;
8001 rtx sp_adj1
, sp_adj2
, mem
;
8005 sa_size
= alpha_sa_size ();
8007 frame_size
= get_frame_size ();
8008 if (TARGET_ABI_OPEN_VMS
)
8009 frame_size
= ALPHA_ROUND (sa_size
8010 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
8012 + current_function_pretend_args_size
);
8013 else if (TARGET_ABI_UNICOSMK
)
8014 frame_size
= ALPHA_ROUND (sa_size
8015 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
8016 + ALPHA_ROUND (frame_size
8017 + current_function_outgoing_args_size
);
8019 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
8021 + ALPHA_ROUND (frame_size
8022 + current_function_pretend_args_size
));
8024 if (TARGET_ABI_OPEN_VMS
)
8026 if (alpha_procedure_type
== PT_STACK
)
8032 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
8034 alpha_sa_mask (&imask
, &fmask
);
8037 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
8038 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
8040 sa_reg
= stack_pointer_rtx
;
8042 if (current_function_calls_eh_return
)
8043 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
8047 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
8049 /* If we have a frame pointer, restore SP from it. */
8050 if ((TARGET_ABI_OPEN_VMS
8051 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
8052 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
8053 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
8055 /* Cope with very large offsets to the register save area. */
8056 if (reg_offset
+ sa_size
> 0x8000)
8058 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
8061 if (low
+ sa_size
<= 0x8000)
8062 bias
= reg_offset
- low
, reg_offset
= low
;
8064 bias
= reg_offset
, reg_offset
= 0;
8066 sa_reg
= gen_rtx_REG (DImode
, 22);
8067 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
8069 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
8072 /* Restore registers in order, excepting a true frame pointer. */
8074 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
8076 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8077 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
8080 imask
&= ~(1UL << REG_RA
);
8082 for (i
= 0; i
< 31; ++i
)
8083 if (imask
& (1UL << i
))
8085 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
8086 fp_offset
= reg_offset
;
8089 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
8090 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8091 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
8096 for (i
= 0; i
< 31; ++i
)
8097 if (fmask
& (1UL << i
))
8099 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
8100 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8101 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
8105 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
8107 /* Restore callee-saved general-purpose registers. */
8111 for (i
= 9; i
< 15; i
++)
8112 if (imask
& (1UL << i
))
8114 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
8116 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8117 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
8121 for (i
= 2; i
< 10; i
++)
8122 if (fmask
& (1UL << i
))
8124 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
8126 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8127 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
8131 /* Restore the return address from the DSIB. */
8133 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
8134 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8135 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
8138 if (frame_size
|| eh_ofs
)
8140 sp_adj1
= stack_pointer_rtx
;
8144 sp_adj1
= gen_rtx_REG (DImode
, 23);
8145 emit_move_insn (sp_adj1
,
8146 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
8149 /* If the stack size is large, begin computation into a temporary
8150 register so as not to interfere with a potential fp restore,
8151 which must be consecutive with an SP restore. */
8152 if (frame_size
< 32768
8153 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
8154 sp_adj2
= GEN_INT (frame_size
);
8155 else if (TARGET_ABI_UNICOSMK
)
8157 sp_adj1
= gen_rtx_REG (DImode
, 23);
8158 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
8159 sp_adj2
= const0_rtx
;
8161 else if (frame_size
< 0x40007fffL
)
8163 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
8165 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
8166 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
8170 sp_adj1
= gen_rtx_REG (DImode
, 23);
8171 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
8173 sp_adj2
= GEN_INT (low
);
8177 rtx tmp
= gen_rtx_REG (DImode
, 23);
8178 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
,
8182 /* We can't drop new things to memory this late, afaik,
8183 so build it up by pieces. */
8184 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
8185 -(frame_size
< 0)));
8186 gcc_assert (sp_adj2
);
8190 /* From now on, things must be in order. So emit blockages. */
8192 /* Restore the frame pointer. */
8193 if (TARGET_ABI_UNICOSMK
)
8195 emit_insn (gen_blockage ());
8196 mem
= gen_rtx_MEM (DImode
,
8197 plus_constant (hard_frame_pointer_rtx
, -16));
8198 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8199 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8201 else if (fp_is_frame_pointer
)
8203 emit_insn (gen_blockage ());
8204 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
8205 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8206 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8208 else if (TARGET_ABI_OPEN_VMS
)
8210 emit_insn (gen_blockage ());
8211 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8212 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8215 /* Restore the stack pointer. */
8216 emit_insn (gen_blockage ());
8217 if (sp_adj2
== const0_rtx
)
8218 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
8220 FRP (emit_move_insn (stack_pointer_rtx
,
8221 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
8225 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8227 emit_insn (gen_blockage ());
8228 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8229 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8231 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8233 /* Decrement the frame pointer if the function does not have a
8236 emit_insn (gen_blockage ());
8237 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8238 hard_frame_pointer_rtx
, constm1_rtx
)));
8243 /* Output the rest of the textual info surrounding the epilogue. */
8246 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
8248 #if TARGET_ABI_OPEN_VMS
8249 alpha_write_linkage (file
, fnname
, decl
);
8252 /* End the function. */
8253 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8255 fputs ("\t.end ", file
);
8256 assemble_name (file
, fnname
);
8259 inside_function
= FALSE
;
8261 /* Output jump tables and the static subroutine information block. */
8262 if (TARGET_ABI_UNICOSMK
)
8264 unicosmk_output_ssib (file
, fnname
);
8265 unicosmk_output_deferred_case_vectors (file
);
8270 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8272 In order to avoid the hordes of differences between generated code
8273 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8274 lots of code loading up large constants, generate rtl and emit it
8275 instead of going straight to text.
8277 Not sure why this idea hasn't been explored before... */
8280 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8281 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8284 HOST_WIDE_INT hi
, lo
;
8285 rtx
this, insn
, funexp
;
8287 reset_block_changes ();
8289 /* We always require a valid GP. */
8290 emit_insn (gen_prologue_ldgp ());
8291 emit_note (NOTE_INSN_PROLOGUE_END
);
8293 /* Find the "this" pointer. If the function returns a structure,
8294 the structure return pointer is in $16. */
8295 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8296 this = gen_rtx_REG (Pmode
, 17);
8298 this = gen_rtx_REG (Pmode
, 16);
8300 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8301 entire constant for the add. */
8302 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8303 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8304 if (hi
+ lo
== delta
)
8307 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
8309 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
8313 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8314 delta
, -(delta
< 0));
8315 emit_insn (gen_adddi3 (this, this, tmp
));
8318 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8323 tmp
= gen_rtx_REG (Pmode
, 0);
8324 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8326 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8327 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8328 if (hi
+ lo
== vcall_offset
)
8331 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8335 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8336 vcall_offset
, -(vcall_offset
< 0));
8337 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8341 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8344 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8346 emit_insn (gen_adddi3 (this, this, tmp
));
8349 /* Generate a tail call to the target function. */
8350 if (! TREE_USED (function
))
8352 assemble_external (function
);
8353 TREE_USED (function
) = 1;
8355 funexp
= XEXP (DECL_RTL (function
), 0);
8356 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8357 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8358 SIBLING_CALL_P (insn
) = 1;
8360 /* Run just enough of rest_of_compilation to get the insns emitted.
8361 There's not really enough bulk here to make other passes such as
8362 instruction scheduling worth while. Note that use_thunk calls
8363 assemble_start_function and assemble_end_function. */
8364 insn
= get_insns ();
8365 insn_locators_initialize ();
8366 shorten_branches (insn
);
8367 final_start_function (insn
, file
, 1);
8368 final (insn
, file
, 1);
8369 final_end_function ();
8371 #endif /* TARGET_ABI_OSF */
8373 /* Debugging support. */
8377 /* Count the number of sdb related labels are generated (to find block
8378 start and end boundaries). */
8380 int sdb_label_count
= 0;
8382 /* Name of the file containing the current function. */
8384 static const char *current_function_file
= "";
8386 /* Offsets to alpha virtual arg/local debugging pointers. */
8388 long alpha_arg_offset
;
8389 long alpha_auto_offset
;
8391 /* Emit a new filename to a stream. */
8394 alpha_output_filename (FILE *stream
, const char *name
)
8396 static int first_time
= TRUE
;
8401 ++num_source_filenames
;
8402 current_function_file
= name
;
8403 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8404 output_quoted_string (stream
, name
);
8405 fprintf (stream
, "\n");
8406 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8407 fprintf (stream
, "\t#@stabs\n");
8410 else if (write_symbols
== DBX_DEBUG
)
8411 /* dbxout.c will emit an appropriate .stabs directive. */
8414 else if (name
!= current_function_file
8415 && strcmp (name
, current_function_file
) != 0)
8417 if (inside_function
&& ! TARGET_GAS
)
8418 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8421 ++num_source_filenames
;
8422 current_function_file
= name
;
8423 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8426 output_quoted_string (stream
, name
);
8427 fprintf (stream
, "\n");
8431 /* Structure to show the current status of registers and memory. */
8433 struct shadow_summary
8436 unsigned int i
: 31; /* Mask of int regs */
8437 unsigned int fp
: 31; /* Mask of fp regs */
8438 unsigned int mem
: 1; /* mem == imem | fpmem */
8442 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8443 to the summary structure. SET is nonzero if the insn is setting the
8444 object, otherwise zero. */
8447 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8449 const char *format_ptr
;
8455 switch (GET_CODE (x
))
8457 /* ??? Note that this case would be incorrect if the Alpha had a
8458 ZERO_EXTRACT in SET_DEST. */
8460 summarize_insn (SET_SRC (x
), sum
, 0);
8461 summarize_insn (SET_DEST (x
), sum
, 1);
8465 summarize_insn (XEXP (x
, 0), sum
, 1);
8469 summarize_insn (XEXP (x
, 0), sum
, 0);
8473 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8474 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8478 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8479 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8483 summarize_insn (SUBREG_REG (x
), sum
, 0);
8488 int regno
= REGNO (x
);
8489 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8491 if (regno
== 31 || regno
== 63)
8497 sum
->defd
.i
|= mask
;
8499 sum
->defd
.fp
|= mask
;
8504 sum
->used
.i
|= mask
;
8506 sum
->used
.fp
|= mask
;
8517 /* Find the regs used in memory address computation: */
8518 summarize_insn (XEXP (x
, 0), sum
, 0);
8521 case CONST_INT
: case CONST_DOUBLE
:
8522 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8523 case SCRATCH
: case ASM_INPUT
:
8526 /* Handle common unary and binary ops for efficiency. */
8527 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8528 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8529 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8530 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8531 case NE
: case EQ
: case GE
: case GT
: case LE
:
8532 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8533 summarize_insn (XEXP (x
, 0), sum
, 0);
8534 summarize_insn (XEXP (x
, 1), sum
, 0);
8537 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8538 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8539 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8540 case SQRT
: case FFS
:
8541 summarize_insn (XEXP (x
, 0), sum
, 0);
8545 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8546 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8547 switch (format_ptr
[i
])
8550 summarize_insn (XEXP (x
, i
), sum
, 0);
8554 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8555 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8567 /* Ensure a sufficient number of `trapb' insns are in the code when
8568 the user requests code with a trap precision of functions or
8571 In naive mode, when the user requests a trap-precision of
8572 "instruction", a trapb is needed after every instruction that may
8573 generate a trap. This ensures that the code is resumption safe but
8576 When optimizations are turned on, we delay issuing a trapb as long
8577 as possible. In this context, a trap shadow is the sequence of
8578 instructions that starts with a (potentially) trap generating
8579 instruction and extends to the next trapb or call_pal instruction
8580 (but GCC never generates call_pal by itself). We can delay (and
8581 therefore sometimes omit) a trapb subject to the following
8584 (a) On entry to the trap shadow, if any Alpha register or memory
8585 location contains a value that is used as an operand value by some
8586 instruction in the trap shadow (live on entry), then no instruction
8587 in the trap shadow may modify the register or memory location.
8589 (b) Within the trap shadow, the computation of the base register
8590 for a memory load or store instruction may not involve using the
8591 result of an instruction that might generate an UNPREDICTABLE
8594 (c) Within the trap shadow, no register may be used more than once
8595 as a destination register. (This is to make life easier for the
8598 (d) The trap shadow may not include any branch instructions. */
8601 alpha_handle_trap_shadows (void)
8603 struct shadow_summary shadow
;
8604 int trap_pending
, exception_nesting
;
8608 exception_nesting
= 0;
8611 shadow
.used
.mem
= 0;
8612 shadow
.defd
= shadow
.used
;
8614 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8616 if (GET_CODE (i
) == NOTE
)
8618 switch (NOTE_LINE_NUMBER (i
))
8620 case NOTE_INSN_EH_REGION_BEG
:
8621 exception_nesting
++;
8626 case NOTE_INSN_EH_REGION_END
:
8627 exception_nesting
--;
8632 case NOTE_INSN_EPILOGUE_BEG
:
8633 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8638 else if (trap_pending
)
8640 if (alpha_tp
== ALPHA_TP_FUNC
)
8642 if (GET_CODE (i
) == JUMP_INSN
8643 && GET_CODE (PATTERN (i
)) == RETURN
)
8646 else if (alpha_tp
== ALPHA_TP_INSN
)
8650 struct shadow_summary sum
;
8655 sum
.defd
= sum
.used
;
8657 switch (GET_CODE (i
))
8660 /* Annoyingly, get_attr_trap will die on these. */
8661 if (GET_CODE (PATTERN (i
)) == USE
8662 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8665 summarize_insn (PATTERN (i
), &sum
, 0);
8667 if ((sum
.defd
.i
& shadow
.defd
.i
)
8668 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8670 /* (c) would be violated */
8674 /* Combine shadow with summary of current insn: */
8675 shadow
.used
.i
|= sum
.used
.i
;
8676 shadow
.used
.fp
|= sum
.used
.fp
;
8677 shadow
.used
.mem
|= sum
.used
.mem
;
8678 shadow
.defd
.i
|= sum
.defd
.i
;
8679 shadow
.defd
.fp
|= sum
.defd
.fp
;
8680 shadow
.defd
.mem
|= sum
.defd
.mem
;
8682 if ((sum
.defd
.i
& shadow
.used
.i
)
8683 || (sum
.defd
.fp
& shadow
.used
.fp
)
8684 || (sum
.defd
.mem
& shadow
.used
.mem
))
8686 /* (a) would be violated (also takes care of (b)) */
8687 gcc_assert (get_attr_trap (i
) != TRAP_YES
8688 || (!(sum
.defd
.i
& sum
.used
.i
)
8689 && !(sum
.defd
.fp
& sum
.used
.fp
)));
8707 n
= emit_insn_before (gen_trapb (), i
);
8708 PUT_MODE (n
, TImode
);
8709 PUT_MODE (i
, TImode
);
8713 shadow
.used
.mem
= 0;
8714 shadow
.defd
= shadow
.used
;
8719 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8720 && GET_CODE (i
) == INSN
8721 && GET_CODE (PATTERN (i
)) != USE
8722 && GET_CODE (PATTERN (i
)) != CLOBBER
8723 && get_attr_trap (i
) == TRAP_YES
)
8725 if (optimize
&& !trap_pending
)
8726 summarize_insn (PATTERN (i
), &shadow
, 0);
8732 /* Alpha can only issue instruction groups simultaneously if they are
8733 suitably aligned. This is very processor-specific. */
8735 enum alphaev4_pipe
{
8742 enum alphaev5_pipe
{
8753 static enum alphaev4_pipe
8754 alphaev4_insn_pipe (rtx insn
)
8756 if (recog_memoized (insn
) < 0)
8758 if (get_attr_length (insn
) != 4)
8761 switch (get_attr_type (insn
))
8798 static enum alphaev5_pipe
8799 alphaev5_insn_pipe (rtx insn
)
8801 if (recog_memoized (insn
) < 0)
8803 if (get_attr_length (insn
) != 4)
8806 switch (get_attr_type (insn
))
8850 /* IN_USE is a mask of the slots currently filled within the insn group.
8851 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8852 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8854 LEN is, of course, the length of the group in bytes. */
8857 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8864 || GET_CODE (PATTERN (insn
)) == CLOBBER
8865 || GET_CODE (PATTERN (insn
)) == USE
)
8870 enum alphaev4_pipe pipe
;
8872 pipe
= alphaev4_insn_pipe (insn
);
8876 /* Force complex instructions to start new groups. */
8880 /* If this is a completely unrecognized insn, it's an asm.
8881 We don't know how long it is, so record length as -1 to
8882 signal a needed realignment. */
8883 if (recog_memoized (insn
) < 0)
8886 len
= get_attr_length (insn
);
8890 if (in_use
& EV4_IB0
)
8892 if (in_use
& EV4_IB1
)
8897 in_use
|= EV4_IB0
| EV4_IBX
;
8901 if (in_use
& EV4_IB0
)
8903 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8911 if (in_use
& EV4_IB1
)
8921 /* Haifa doesn't do well scheduling branches. */
8922 if (GET_CODE (insn
) == JUMP_INSN
)
8926 insn
= next_nonnote_insn (insn
);
8928 if (!insn
|| ! INSN_P (insn
))
8931 /* Let Haifa tell us where it thinks insn group boundaries are. */
8932 if (GET_MODE (insn
) == TImode
)
8935 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8940 insn
= next_nonnote_insn (insn
);
8948 /* IN_USE is a mask of the slots currently filled within the insn group.
8949 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8950 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8952 LEN is, of course, the length of the group in bytes. */
8955 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8962 || GET_CODE (PATTERN (insn
)) == CLOBBER
8963 || GET_CODE (PATTERN (insn
)) == USE
)
8968 enum alphaev5_pipe pipe
;
8970 pipe
= alphaev5_insn_pipe (insn
);
8974 /* Force complex instructions to start new groups. */
8978 /* If this is a completely unrecognized insn, it's an asm.
8979 We don't know how long it is, so record length as -1 to
8980 signal a needed realignment. */
8981 if (recog_memoized (insn
) < 0)
8984 len
= get_attr_length (insn
);
8987 /* ??? Most of the places below, we would like to assert never
8988 happen, as it would indicate an error either in Haifa, or
8989 in the scheduling description. Unfortunately, Haifa never
8990 schedules the last instruction of the BB, so we don't have
8991 an accurate TI bit to go off. */
8993 if (in_use
& EV5_E0
)
8995 if (in_use
& EV5_E1
)
9000 in_use
|= EV5_E0
| EV5_E01
;
9004 if (in_use
& EV5_E0
)
9006 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
9014 if (in_use
& EV5_E1
)
9020 if (in_use
& EV5_FA
)
9022 if (in_use
& EV5_FM
)
9027 in_use
|= EV5_FA
| EV5_FAM
;
9031 if (in_use
& EV5_FA
)
9037 if (in_use
& EV5_FM
)
9050 /* Haifa doesn't do well scheduling branches. */
9051 /* ??? If this is predicted not-taken, slotting continues, except
9052 that no more IBR, FBR, or JSR insns may be slotted. */
9053 if (GET_CODE (insn
) == JUMP_INSN
)
9057 insn
= next_nonnote_insn (insn
);
9059 if (!insn
|| ! INSN_P (insn
))
9062 /* Let Haifa tell us where it thinks insn group boundaries are. */
9063 if (GET_MODE (insn
) == TImode
)
9066 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9071 insn
= next_nonnote_insn (insn
);
9080 alphaev4_next_nop (int *pin_use
)
9082 int in_use
= *pin_use
;
9085 if (!(in_use
& EV4_IB0
))
9090 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
9095 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
9108 alphaev5_next_nop (int *pin_use
)
9110 int in_use
= *pin_use
;
9113 if (!(in_use
& EV5_E1
))
9118 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
9123 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
9135 /* The instruction group alignment main loop. */
9138 alpha_align_insns (unsigned int max_align
,
9139 rtx (*next_group
) (rtx
, int *, int *),
9140 rtx (*next_nop
) (int *))
9142 /* ALIGN is the known alignment for the insn group. */
9144 /* OFS is the offset of the current insn in the insn group. */
9146 int prev_in_use
, in_use
, len
, ldgp
;
9149 /* Let shorten branches care for assigning alignments to code labels. */
9150 shorten_branches (get_insns ());
9152 if (align_functions
< 4)
9154 else if ((unsigned int) align_functions
< max_align
)
9155 align
= align_functions
;
9159 ofs
= prev_in_use
= 0;
9161 if (GET_CODE (i
) == NOTE
)
9162 i
= next_nonnote_insn (i
);
9164 ldgp
= alpha_function_needs_gp
? 8 : 0;
9168 next
= (*next_group
) (i
, &in_use
, &len
);
9170 /* When we see a label, resync alignment etc. */
9171 if (GET_CODE (i
) == CODE_LABEL
)
9173 unsigned int new_align
= 1 << label_to_alignment (i
);
9175 if (new_align
>= align
)
9177 align
= new_align
< max_align
? new_align
: max_align
;
9181 else if (ofs
& (new_align
-1))
9182 ofs
= (ofs
| (new_align
-1)) + 1;
9186 /* Handle complex instructions special. */
9187 else if (in_use
== 0)
9189 /* Asms will have length < 0. This is a signal that we have
9190 lost alignment knowledge. Assume, however, that the asm
9191 will not mis-align instructions. */
9200 /* If the known alignment is smaller than the recognized insn group,
9201 realign the output. */
9202 else if ((int) align
< len
)
9204 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9207 where
= prev
= prev_nonnote_insn (i
);
9208 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
9211 /* Can't realign between a call and its gp reload. */
9212 if (! (TARGET_EXPLICIT_RELOCS
9213 && prev
&& GET_CODE (prev
) == CALL_INSN
))
9215 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9216 align
= 1 << new_log_align
;
9221 /* We may not insert padding inside the initial ldgp sequence. */
9225 /* If the group won't fit in the same INT16 as the previous,
9226 we need to add padding to keep the group together. Rather
9227 than simply leaving the insn filling to the assembler, we
9228 can make use of the knowledge of what sorts of instructions
9229 were issued in the previous group to make sure that all of
9230 the added nops are really free. */
9231 else if (ofs
+ len
> (int) align
)
9233 int nop_count
= (align
- ofs
) / 4;
9236 /* Insert nops before labels, branches, and calls to truly merge
9237 the execution of the nops with the previous instruction group. */
9238 where
= prev_nonnote_insn (i
);
9241 if (GET_CODE (where
) == CODE_LABEL
)
9243 rtx where2
= prev_nonnote_insn (where
);
9244 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
9247 else if (GET_CODE (where
) == INSN
)
9254 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9255 while (--nop_count
);
9259 ofs
= (ofs
+ len
) & (align
- 1);
9260 prev_in_use
= in_use
;
9265 /* Machine dependent reorg pass. */
9270 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9271 alpha_handle_trap_shadows ();
9273 /* Due to the number of extra trapb insns, don't bother fixing up
9274 alignment when trap precision is instruction. Moreover, we can
9275 only do our job when sched2 is run. */
9276 if (optimize
&& !optimize_size
9277 && alpha_tp
!= ALPHA_TP_INSN
9278 && flag_schedule_insns_after_reload
)
9280 if (alpha_tune
== PROCESSOR_EV4
)
9281 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
9282 else if (alpha_tune
== PROCESSOR_EV5
)
9283 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
9287 #if !TARGET_ABI_UNICOSMK
9294 alpha_file_start (void)
9296 #ifdef OBJECT_FORMAT_ELF
9297 /* If emitting dwarf2 debug information, we cannot generate a .file
9298 directive to start the file, as it will conflict with dwarf2out
9299 file numbers. So it's only useful when emitting mdebug output. */
9300 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
9303 default_file_start ();
9305 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
9308 fputs ("\t.set noreorder\n", asm_out_file
);
9309 fputs ("\t.set volatile\n", asm_out_file
);
9310 if (!TARGET_ABI_OPEN_VMS
)
9311 fputs ("\t.set noat\n", asm_out_file
);
9312 if (TARGET_EXPLICIT_RELOCS
)
9313 fputs ("\t.set nomacro\n", asm_out_file
);
9314 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
9318 if (alpha_cpu
== PROCESSOR_EV6
|| TARGET_FIX
|| TARGET_CIX
)
9320 else if (TARGET_MAX
)
9322 else if (TARGET_BWX
)
9324 else if (alpha_cpu
== PROCESSOR_EV5
)
9329 fprintf (asm_out_file
, "\t.arch %s\n", arch
);
9334 #ifdef OBJECT_FORMAT_ELF
9336 /* Switch to the section to which we should output X. The only thing
9337 special we do here is to honor small data. */
9340 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
9341 unsigned HOST_WIDE_INT align
)
9343 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9344 /* ??? Consider using mergeable sdata sections. */
9347 default_elf_select_rtx_section (mode
, x
, align
);
9350 #endif /* OBJECT_FORMAT_ELF */
9352 /* Structure to collect function names for final output in link section. */
9353 /* Note that items marked with GTY can't be ifdef'ed out. */
9355 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9356 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9358 struct alpha_links
GTY(())
9362 enum links_kind lkind
;
9363 enum reloc_kind rkind
;
9366 struct alpha_funcs
GTY(())
9369 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9373 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9374 splay_tree alpha_links_tree
;
9375 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9376 splay_tree alpha_funcs_tree
;
9378 static GTY(()) int alpha_funcs_num
;
9380 #if TARGET_ABI_OPEN_VMS
9382 /* Return the VMS argument type corresponding to MODE. */
9385 alpha_arg_type (enum machine_mode mode
)
9390 return TARGET_FLOAT_VAX
? FF
: FS
;
9392 return TARGET_FLOAT_VAX
? FD
: FT
;
9398 /* Return an rtx for an integer representing the VMS Argument Information
9402 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9404 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9407 for (i
= 0; i
< 6; i
++)
9408 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9410 return GEN_INT (regval
);
9413 /* Make (or fake) .linkage entry for function call.
9415 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9417 Return an SYMBOL_REF rtx for the linkage. */
9420 alpha_need_linkage (const char *name
, int is_local
)
9422 splay_tree_node node
;
9423 struct alpha_links
*al
;
9430 struct alpha_funcs
*cfaf
;
9432 if (!alpha_funcs_tree
)
9433 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9434 splay_tree_compare_pointers
);
9436 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9439 cfaf
->num
= ++alpha_funcs_num
;
9441 splay_tree_insert (alpha_funcs_tree
,
9442 (splay_tree_key
) current_function_decl
,
9443 (splay_tree_value
) cfaf
);
9446 if (alpha_links_tree
)
9448 /* Is this name already defined? */
9450 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9453 al
= (struct alpha_links
*) node
->value
;
9456 /* Defined here but external assumed. */
9457 if (al
->lkind
== KIND_EXTERN
)
9458 al
->lkind
= KIND_LOCAL
;
9462 /* Used here but unused assumed. */
9463 if (al
->lkind
== KIND_UNUSED
)
9464 al
->lkind
= KIND_LOCAL
;
9470 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9472 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9473 name
= ggc_strdup (name
);
9475 /* Assume external if no definition. */
9476 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9478 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9479 get_identifier (name
);
9481 /* Construct a SYMBOL_REF for us to call. */
9483 size_t name_len
= strlen (name
);
9484 char *linksym
= alloca (name_len
+ 6);
9486 memcpy (linksym
+ 1, name
, name_len
);
9487 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9488 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9489 ggc_alloc_string (linksym
, name_len
+ 5));
9492 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9493 (splay_tree_value
) al
);
9499 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9501 splay_tree_node cfunnode
;
9502 struct alpha_funcs
*cfaf
;
9503 struct alpha_links
*al
;
9504 const char *name
= XSTR (linkage
, 0);
9506 cfaf
= (struct alpha_funcs
*) 0;
9507 al
= (struct alpha_links
*) 0;
9509 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9510 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9514 splay_tree_node lnode
;
9516 /* Is this name already defined? */
9518 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9520 al
= (struct alpha_links
*) lnode
->value
;
9523 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9531 splay_tree_node node
= 0;
9532 struct alpha_links
*anl
;
9537 name_len
= strlen (name
);
9539 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9540 al
->num
= cfaf
->num
;
9542 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9545 anl
= (struct alpha_links
*) node
->value
;
9546 al
->lkind
= anl
->lkind
;
9549 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9550 buflen
= strlen (buf
);
9551 linksym
= alloca (buflen
+ 1);
9552 memcpy (linksym
, buf
, buflen
+ 1);
9554 al
->linkage
= gen_rtx_SYMBOL_REF
9555 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9557 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9558 (splay_tree_value
) al
);
9562 al
->rkind
= KIND_CODEADDR
;
9564 al
->rkind
= KIND_LINKAGE
;
9567 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9573 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9575 const char *const name
= (const char *) node
->key
;
9576 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9577 FILE *stream
= (FILE *) data
;
9579 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9580 if (link
->rkind
== KIND_CODEADDR
)
9582 if (link
->lkind
== KIND_LOCAL
)
9584 /* Local and used */
9585 fprintf (stream
, "\t.quad %s..en\n", name
);
9589 /* External and used, request code address. */
9590 fprintf (stream
, "\t.code_address %s\n", name
);
9595 if (link
->lkind
== KIND_LOCAL
)
9597 /* Local and used, build linkage pair. */
9598 fprintf (stream
, "\t.quad %s..en\n", name
);
9599 fprintf (stream
, "\t.quad %s\n", name
);
9603 /* External and used, request linkage pair. */
9604 fprintf (stream
, "\t.linkage %s\n", name
);
9612 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9614 splay_tree_node node
;
9615 struct alpha_funcs
*func
;
9618 fprintf (stream
, "\t.align 3\n");
9619 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9620 func
= (struct alpha_funcs
*) node
->value
;
9622 fputs ("\t.name ", stream
);
9623 assemble_name (stream
, funname
);
9624 fputs ("..na\n", stream
);
9625 ASM_OUTPUT_LABEL (stream
, funname
);
9626 fprintf (stream
, "\t.pdesc ");
9627 assemble_name (stream
, funname
);
9628 fprintf (stream
, "..en,%s\n",
9629 alpha_procedure_type
== PT_STACK
? "stack"
9630 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9634 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9635 /* splay_tree_delete (func->links); */
9639 /* Given a decl, a section name, and whether the decl initializer
9640 has relocs, choose attributes for the section. */
9642 #define SECTION_VMS_OVERLAY SECTION_FORGET
9643 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9644 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9647 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9649 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9651 if (decl
&& DECL_ATTRIBUTES (decl
)
9652 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9653 flags
|= SECTION_VMS_OVERLAY
;
9654 if (decl
&& DECL_ATTRIBUTES (decl
)
9655 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9656 flags
|= SECTION_VMS_GLOBAL
;
9657 if (decl
&& DECL_ATTRIBUTES (decl
)
9658 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9659 flags
|= SECTION_VMS_INITIALIZE
;
9664 /* Switch to an arbitrary section NAME with attributes as specified
9665 by FLAGS. ALIGN specifies any known alignment requirements for
9666 the section; 0 if the default should be used. */
9669 vms_asm_named_section (const char *name
, unsigned int flags
,
9670 tree decl ATTRIBUTE_UNUSED
)
9672 fputc ('\n', asm_out_file
);
9673 fprintf (asm_out_file
, ".section\t%s", name
);
9675 if (flags
& SECTION_VMS_OVERLAY
)
9676 fprintf (asm_out_file
, ",OVR");
9677 if (flags
& SECTION_VMS_GLOBAL
)
9678 fprintf (asm_out_file
, ",GBL");
9679 if (flags
& SECTION_VMS_INITIALIZE
)
9680 fprintf (asm_out_file
, ",NOMOD");
9681 if (flags
& SECTION_DEBUG
)
9682 fprintf (asm_out_file
, ",NOWRT");
9684 fputc ('\n', asm_out_file
);
9687 /* Record an element in the table of global constructors. SYMBOL is
9688 a SYMBOL_REF of the function to be called; PRIORITY is a number
9689 between 0 and MAX_INIT_PRIORITY.
9691 Differs from default_ctors_section_asm_out_constructor in that the
9692 width of the .ctors entry is always 64 bits, rather than the 32 bits
9693 used by a normal pointer. */
9696 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9699 assemble_align (BITS_PER_WORD
);
9700 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9704 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9707 assemble_align (BITS_PER_WORD
);
9708 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9713 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9714 int is_local ATTRIBUTE_UNUSED
)
9720 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9721 tree cfundecl ATTRIBUTE_UNUSED
,
9722 int lflag ATTRIBUTE_UNUSED
,
9723 int rflag ATTRIBUTE_UNUSED
)
9728 #endif /* TARGET_ABI_OPEN_VMS */
9730 #if TARGET_ABI_UNICOSMK
9732 /* This evaluates to true if we do not know how to pass TYPE solely in
9733 registers. This is the case for all arguments that do not fit in two
9737 unicosmk_must_pass_in_stack (enum machine_mode mode
, tree type
)
9742 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9744 if (TREE_ADDRESSABLE (type
))
9747 return ALPHA_ARG_SIZE (mode
, type
, 0) > 2;
9750 /* Define the offset between two registers, one to be eliminated, and the
9751 other its replacement, at the start of a routine. */
9754 unicosmk_initial_elimination_offset (int from
, int to
)
9758 fixed_size
= alpha_sa_size();
9759 if (fixed_size
!= 0)
9762 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9764 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9766 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9767 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9768 + ALPHA_ROUND (get_frame_size()));
9769 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9770 return (ALPHA_ROUND (fixed_size
)
9771 + ALPHA_ROUND (get_frame_size()
9772 + current_function_outgoing_args_size
));
9777 /* Output the module name for .ident and .end directives. We have to strip
9778 directories and add make sure that the module name starts with a letter
9782 unicosmk_output_module_name (FILE *file
)
9784 const char *name
= lbasename (main_input_filename
);
9785 unsigned len
= strlen (name
);
9786 char *clean_name
= alloca (len
+ 2);
9787 char *ptr
= clean_name
;
9789 /* CAM only accepts module names that start with a letter or '$'. We
9790 prefix the module name with a '$' if necessary. */
9792 if (!ISALPHA (*name
))
9794 memcpy (ptr
, name
, len
+ 1);
9795 clean_symbol_name (clean_name
);
9796 fputs (clean_name
, file
);
9799 /* Output the definition of a common variable. */
9802 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9805 printf ("T3E__: common %s\n", name
);
9808 fputs("\t.endp\n\n\t.psect ", file
);
9809 assemble_name(file
, name
);
9810 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9811 fprintf(file
, "\t.byte\t0:%d\n", size
);
9813 /* Mark the symbol as defined in this module. */
9814 name_tree
= get_identifier (name
);
9815 TREE_ASM_WRITTEN (name_tree
) = 1;
9818 #define SECTION_PUBLIC SECTION_MACH_DEP
9819 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9820 static int current_section_align
;
9823 unicosmk_section_type_flags (tree decl
, const char *name
,
9824 int reloc ATTRIBUTE_UNUSED
)
9826 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9831 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9833 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9834 if (align_functions_log
> current_section_align
)
9835 current_section_align
= align_functions_log
;
9837 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9838 flags
|= SECTION_MAIN
;
9841 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9843 if (TREE_PUBLIC (decl
))
9844 flags
|= SECTION_PUBLIC
;
9849 /* Generate a section name for decl and associate it with the
9853 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9860 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9861 name
= default_strip_name_encoding (name
);
9862 len
= strlen (name
);
9864 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9868 /* It is essential that we prefix the section name here because
9869 otherwise the section names generated for constructors and
9870 destructors confuse collect2. */
9872 string
= alloca (len
+ 6);
9873 sprintf (string
, "code@%s", name
);
9874 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9876 else if (TREE_PUBLIC (decl
))
9877 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9882 string
= alloca (len
+ 6);
9883 sprintf (string
, "data@%s", name
);
9884 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9888 /* Switch to an arbitrary section NAME with attributes as specified
9889 by FLAGS. ALIGN specifies any known alignment requirements for
9890 the section; 0 if the default should be used. */
9893 unicosmk_asm_named_section (const char *name
, unsigned int flags
,
9894 tree decl ATTRIBUTE_UNUSED
)
9898 /* Close the previous section. */
9900 fputs ("\t.endp\n\n", asm_out_file
);
9902 /* Find out what kind of section we are opening. */
9904 if (flags
& SECTION_MAIN
)
9905 fputs ("\t.start\tmain\n", asm_out_file
);
9907 if (flags
& SECTION_CODE
)
9909 else if (flags
& SECTION_PUBLIC
)
9914 if (current_section_align
!= 0)
9915 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9916 current_section_align
, kind
);
9918 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9922 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9925 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9926 unicosmk_unique_section (decl
, 0);
9929 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9930 in code sections because .align fill unused space with zeroes. */
9933 unicosmk_output_align (FILE *file
, int align
)
9935 if (inside_function
)
9936 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9938 fprintf (file
, "\t.align\t%d\n", align
);
9941 /* Add a case vector to the current function's list of deferred case
9942 vectors. Case vectors have to be put into a separate section because CAM
9943 does not allow data definitions in code sections. */
9946 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9948 struct machine_function
*machine
= cfun
->machine
;
9950 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9951 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9952 machine
->addr_list
);
9955 /* Output a case vector. */
9958 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9960 rtx lab
= XEXP (vec
, 0);
9961 rtx body
= XEXP (vec
, 1);
9962 int vlen
= XVECLEN (body
, 0);
9965 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9967 for (idx
= 0; idx
< vlen
; idx
++)
9969 ASM_OUTPUT_ADDR_VEC_ELT
9970 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9974 /* Output current function's deferred case vectors. */
9977 unicosmk_output_deferred_case_vectors (FILE *file
)
9979 struct machine_function
*machine
= cfun
->machine
;
9982 if (machine
->addr_list
== NULL_RTX
)
9986 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9987 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9990 /* Generate the name of the SSIB section for the current function. */
9992 #define SSIB_PREFIX "__SSIB_"
9993 #define SSIB_PREFIX_LEN 7
9996 unicosmk_ssib_name (void)
9998 /* This is ok since CAM won't be able to deal with names longer than that
10001 static char name
[256];
10004 const char *fnname
;
10007 x
= DECL_RTL (cfun
->decl
);
10008 gcc_assert (GET_CODE (x
) == MEM
);
10010 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
10011 fnname
= XSTR (x
, 0);
10013 len
= strlen (fnname
);
10014 if (len
+ SSIB_PREFIX_LEN
> 255)
10015 len
= 255 - SSIB_PREFIX_LEN
;
10017 strcpy (name
, SSIB_PREFIX
);
10018 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
10019 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10024 /* Set up the dynamic subprogram information block (DSIB) and update the
10025 frame pointer register ($15) for subroutines which have a frame. If the
10026 subroutine doesn't have a frame, simply increment $15. */
10029 unicosmk_gen_dsib (unsigned long *imaskP
)
10031 if (alpha_procedure_type
== PT_STACK
)
10033 const char *ssib_name
;
10036 /* Allocate 64 bytes for the DSIB. */
10038 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10040 emit_insn (gen_blockage ());
10042 /* Save the return address. */
10044 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
10045 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10046 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
10047 (*imaskP
) &= ~(1UL << REG_RA
);
10049 /* Save the old frame pointer. */
10051 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
10052 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10053 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
10054 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
10056 emit_insn (gen_blockage ());
10058 /* Store the SSIB pointer. */
10060 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
10061 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
10062 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10064 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
10065 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
10066 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
10068 /* Save the CIW index. */
10070 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
10071 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10072 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
10074 emit_insn (gen_blockage ());
10076 /* Set the new frame pointer. */
10078 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10079 stack_pointer_rtx
, GEN_INT (64))));
10084 /* Increment the frame pointer register to indicate that we do not
10087 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10088 hard_frame_pointer_rtx
, const1_rtx
)));
10092 /* Output the static subroutine information block for the current
10096 unicosmk_output_ssib (FILE *file
, const char *fnname
)
10102 struct machine_function
*machine
= cfun
->machine
;
10105 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10106 unicosmk_ssib_name ());
10108 /* Some required stuff and the function name length. */
10110 len
= strlen (fnname
);
10111 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10114 ??? We don't do that yet. */
10116 fputs ("\t.quad\t0\n", file
);
10118 /* Function address. */
10120 fputs ("\t.quad\t", file
);
10121 assemble_name (file
, fnname
);
10124 fputs ("\t.quad\t0\n", file
);
10125 fputs ("\t.quad\t0\n", file
);
10128 ??? We do it the same way Cray CC does it but this could be
10131 for( i
= 0; i
< len
; i
++ )
10132 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10133 if( (len
% 8) == 0 )
10134 fputs ("\t.quad\t0\n", file
);
10136 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10138 /* All call information words used in the function. */
10140 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10143 #if HOST_BITS_PER_WIDE_INT == 32
10144 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
10145 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10147 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
10152 /* Add a call information word (CIW) to the list of the current function's
10153 CIWs and return its index.
10155 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10158 unicosmk_add_call_info_word (rtx x
)
10161 struct machine_function
*machine
= cfun
->machine
;
10163 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10164 if (machine
->first_ciw
== NULL_RTX
)
10165 machine
->first_ciw
= node
;
10167 XEXP (machine
->last_ciw
, 1) = node
;
10169 machine
->last_ciw
= node
;
10170 ++machine
->ciw_count
;
10172 return GEN_INT (machine
->ciw_count
10173 + strlen (current_function_name ())/8 + 5);
10176 static char unicosmk_section_buf
[100];
10179 unicosmk_text_section (void)
10181 static int count
= 0;
10182 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
10184 return unicosmk_section_buf
;
10188 unicosmk_data_section (void)
10190 static int count
= 1;
10191 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
10193 return unicosmk_section_buf
;
10196 /* The Cray assembler doesn't accept extern declarations for symbols which
10197 are defined in the same file. We have to keep track of all global
10198 symbols which are referenced and/or defined in a source file and output
10199 extern declarations for those which are referenced but not defined at
10200 the end of file. */
10202 /* List of identifiers for which an extern declaration might have to be
10204 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10206 struct unicosmk_extern_list
10208 struct unicosmk_extern_list
*next
;
10212 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10214 /* Output extern declarations which are required for every asm file. */
10217 unicosmk_output_default_externs (FILE *file
)
10219 static const char *const externs
[] =
10220 { "__T3E_MISMATCH" };
10225 n
= ARRAY_SIZE (externs
);
10227 for (i
= 0; i
< n
; i
++)
10228 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10231 /* Output extern declarations for global symbols which are have been
10232 referenced but not defined. */
10235 unicosmk_output_externs (FILE *file
)
10237 struct unicosmk_extern_list
*p
;
10238 const char *real_name
;
10242 len
= strlen (user_label_prefix
);
10243 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10245 /* We have to strip the encoding and possibly remove user_label_prefix
10246 from the identifier in order to handle -fleading-underscore and
10247 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10248 real_name
= default_strip_name_encoding (p
->name
);
10249 if (len
&& p
->name
[0] == '*'
10250 && !memcmp (real_name
, user_label_prefix
, len
))
10253 name_tree
= get_identifier (real_name
);
10254 if (! TREE_ASM_WRITTEN (name_tree
))
10256 TREE_ASM_WRITTEN (name_tree
) = 1;
10257 fputs ("\t.extern\t", file
);
10258 assemble_name (file
, p
->name
);
10264 /* Record an extern. */
10267 unicosmk_add_extern (const char *name
)
10269 struct unicosmk_extern_list
*p
;
10271 p
= (struct unicosmk_extern_list
*)
10272 xmalloc (sizeof (struct unicosmk_extern_list
));
10273 p
->next
= unicosmk_extern_head
;
10275 unicosmk_extern_head
= p
;
10278 /* The Cray assembler generates incorrect code if identifiers which
10279 conflict with register names are used as instruction operands. We have
10280 to replace such identifiers with DEX expressions. */
10282 /* Structure to collect identifiers which have been replaced by DEX
10284 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10286 struct unicosmk_dex
{
10287 struct unicosmk_dex
*next
;
10291 /* List of identifiers which have been replaced by DEX expressions. The DEX
10292 number is determined by the position in the list. */
10294 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10296 /* The number of elements in the DEX list. */
10298 static int unicosmk_dex_count
= 0;
10300 /* Check if NAME must be replaced by a DEX expression. */
10303 unicosmk_special_name (const char *name
)
10305 if (name
[0] == '*')
10308 if (name
[0] == '$')
10311 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10316 case '1': case '2':
10317 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10320 return (name
[2] == '\0'
10321 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10324 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10328 /* Return the DEX number if X must be replaced by a DEX expression and 0
10332 unicosmk_need_dex (rtx x
)
10334 struct unicosmk_dex
*dex
;
10338 if (GET_CODE (x
) != SYMBOL_REF
)
10342 if (! unicosmk_special_name (name
))
10345 i
= unicosmk_dex_count
;
10346 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10348 if (! strcmp (name
, dex
->name
))
10353 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10355 dex
->next
= unicosmk_dex_list
;
10356 unicosmk_dex_list
= dex
;
10358 ++unicosmk_dex_count
;
10359 return unicosmk_dex_count
;
10362 /* Output the DEX definitions for this file. */
10365 unicosmk_output_dex (FILE *file
)
10367 struct unicosmk_dex
*dex
;
10370 if (unicosmk_dex_list
== NULL
)
10373 fprintf (file
, "\t.dexstart\n");
10375 i
= unicosmk_dex_count
;
10376 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10378 fprintf (file
, "\tDEX (%d) = ", i
);
10379 assemble_name (file
, dex
->name
);
10384 fprintf (file
, "\t.dexend\n");
10387 /* Output text that to appear at the beginning of an assembler file. */
10390 unicosmk_file_start (void)
10394 fputs ("\t.ident\t", asm_out_file
);
10395 unicosmk_output_module_name (asm_out_file
);
10396 fputs ("\n\n", asm_out_file
);
10398 /* The Unicos/Mk assembler uses different register names. Instead of trying
10399 to support them, we simply use micro definitions. */
10401 /* CAM has different register names: rN for the integer register N and fN
10402 for the floating-point register N. Instead of trying to use these in
10403 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10406 for (i
= 0; i
< 32; ++i
)
10407 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
10409 for (i
= 0; i
< 32; ++i
)
10410 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
10412 putc ('\n', asm_out_file
);
10414 /* The .align directive fill unused space with zeroes which does not work
10415 in code sections. We define the macro 'gcc@code@align' which uses nops
10416 instead. Note that it assumes that code sections always have the
10417 biggest possible alignment since . refers to the current offset from
10418 the beginning of the section. */
10420 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
10421 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
10422 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
10423 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
10424 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
10425 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
10426 fputs ("\t.endr\n", asm_out_file
);
10427 fputs ("\t.endif\n", asm_out_file
);
10428 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
10430 /* Output extern declarations which should always be visible. */
10431 unicosmk_output_default_externs (asm_out_file
);
10433 /* Open a dummy section. We always need to be inside a section for the
10434 section-switching code to work correctly.
10435 ??? This should be a module id or something like that. I still have to
10436 figure out what the rules for those are. */
10437 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10440 /* Output text to appear at the end of an assembler file. This includes all
10441 pending extern declarations and DEX expressions. */
10444 unicosmk_file_end (void)
10446 fputs ("\t.endp\n\n", asm_out_file
);
10448 /* Output all pending externs. */
10450 unicosmk_output_externs (asm_out_file
);
10452 /* Output dex definitions used for functions whose names conflict with
10455 unicosmk_output_dex (asm_out_file
);
10457 fputs ("\t.end\t", asm_out_file
);
10458 unicosmk_output_module_name (asm_out_file
);
10459 putc ('\n', asm_out_file
);
10465 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10469 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10473 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10474 const char * fnname ATTRIBUTE_UNUSED
)
10478 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10484 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10489 #endif /* TARGET_ABI_UNICOSMK */
10492 alpha_init_libfuncs (void)
10494 if (TARGET_ABI_UNICOSMK
)
10496 /* Prevent gcc from generating calls to __divsi3. */
10497 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10498 set_optab_libfunc (udiv_optab
, SImode
, 0);
10500 /* Use the functions provided by the system library
10501 for DImode integer division. */
10502 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10503 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10505 else if (TARGET_ABI_OPEN_VMS
)
10507 /* Use the VMS runtime library functions for division and
10509 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10510 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10511 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10512 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10513 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10514 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10515 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10516 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10521 /* Initialize the GCC target structure. */
10522 #if TARGET_ABI_OPEN_VMS
10523 # undef TARGET_ATTRIBUTE_TABLE
10524 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10525 # undef TARGET_SECTION_TYPE_FLAGS
10526 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10529 #undef TARGET_IN_SMALL_DATA_P
10530 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10532 #if TARGET_ABI_UNICOSMK
10533 # undef TARGET_INSERT_ATTRIBUTES
10534 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10535 # undef TARGET_SECTION_TYPE_FLAGS
10536 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10537 # undef TARGET_ASM_UNIQUE_SECTION
10538 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10539 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
10540 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
10541 # undef TARGET_ASM_GLOBALIZE_LABEL
10542 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10543 # undef TARGET_MUST_PASS_IN_STACK
10544 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
10547 #undef TARGET_ASM_ALIGNED_HI_OP
10548 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10549 #undef TARGET_ASM_ALIGNED_DI_OP
10550 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10552 /* Default unaligned ops are provided for ELF systems. To get unaligned
10553 data for non-ELF systems, we have to turn off auto alignment. */
10554 #ifndef OBJECT_FORMAT_ELF
10555 #undef TARGET_ASM_UNALIGNED_HI_OP
10556 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10557 #undef TARGET_ASM_UNALIGNED_SI_OP
10558 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10559 #undef TARGET_ASM_UNALIGNED_DI_OP
10560 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10563 #ifdef OBJECT_FORMAT_ELF
10564 #undef TARGET_ASM_SELECT_RTX_SECTION
10565 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10568 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10569 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10571 #undef TARGET_INIT_LIBFUNCS
10572 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10574 #if TARGET_ABI_UNICOSMK
10575 #undef TARGET_ASM_FILE_START
10576 #define TARGET_ASM_FILE_START unicosmk_file_start
10577 #undef TARGET_ASM_FILE_END
10578 #define TARGET_ASM_FILE_END unicosmk_file_end
10580 #undef TARGET_ASM_FILE_START
10581 #define TARGET_ASM_FILE_START alpha_file_start
10582 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10583 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10586 #undef TARGET_SCHED_ADJUST_COST
10587 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10588 #undef TARGET_SCHED_ISSUE_RATE
10589 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10590 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10591 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10592 alpha_multipass_dfa_lookahead
10594 #undef TARGET_HAVE_TLS
10595 #define TARGET_HAVE_TLS HAVE_AS_TLS
10597 #undef TARGET_INIT_BUILTINS
10598 #define TARGET_INIT_BUILTINS alpha_init_builtins
10599 #undef TARGET_EXPAND_BUILTIN
10600 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10601 #undef TARGET_FOLD_BUILTIN
10602 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
10604 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10605 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10606 #undef TARGET_CANNOT_COPY_INSN_P
10607 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10608 #undef TARGET_CANNOT_FORCE_CONST_MEM
10609 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
10612 #undef TARGET_ASM_OUTPUT_MI_THUNK
10613 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10614 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10615 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10616 #undef TARGET_STDARG_OPTIMIZE_HOOK
10617 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
10620 #undef TARGET_RTX_COSTS
10621 #define TARGET_RTX_COSTS alpha_rtx_costs
10622 #undef TARGET_ADDRESS_COST
10623 #define TARGET_ADDRESS_COST hook_int_rtx_0
10625 #undef TARGET_MACHINE_DEPENDENT_REORG
10626 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10628 #undef TARGET_PROMOTE_FUNCTION_ARGS
10629 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10630 #undef TARGET_PROMOTE_FUNCTION_RETURN
10631 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10632 #undef TARGET_PROMOTE_PROTOTYPES
10633 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10634 #undef TARGET_RETURN_IN_MEMORY
10635 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10636 #undef TARGET_PASS_BY_REFERENCE
10637 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
10638 #undef TARGET_SETUP_INCOMING_VARARGS
10639 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10640 #undef TARGET_STRICT_ARGUMENT_NAMING
10641 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10642 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10643 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10644 #undef TARGET_SPLIT_COMPLEX_ARG
10645 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10646 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10647 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10648 #undef TARGET_ARG_PARTIAL_BYTES
10649 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
10651 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10652 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
10653 #undef TARGET_VECTOR_MODE_SUPPORTED_P
10654 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
10656 #undef TARGET_BUILD_BUILTIN_VA_LIST
10657 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10659 /* The Alpha architecture does not require sequential consistency. See
10660 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
10661 for an example of how it can be violated in practice. */
10662 #undef TARGET_RELAXED_ORDERING
10663 #define TARGET_RELAXED_ORDERING true
10665 #undef TARGET_DEFAULT_TARGET_FLAGS
10666 #define TARGET_DEFAULT_TARGET_FLAGS \
10667 (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
10668 #undef TARGET_HANDLE_OPTION
10669 #define TARGET_HANDLE_OPTION alpha_handle_option
10671 struct gcc_target targetm
= TARGET_INITIALIZER
;
10674 #include "gt-alpha.h"