1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 #include "tree-flow.h"
57 #include "tree-stdarg.h"
58 #include "tm-constrs.h"
61 /* Specify which cpu to schedule for. */
62 enum processor_type alpha_tune
;
64 /* Which cpu we're generating code for. */
65 enum processor_type alpha_cpu
;
67 static const char * const alpha_cpu_name
[] =
72 /* Specify how accurate floating-point traps need to be. */
74 enum alpha_trap_precision alpha_tp
;
76 /* Specify the floating-point rounding mode. */
78 enum alpha_fp_rounding_mode alpha_fprm
;
80 /* Specify which things cause traps. */
82 enum alpha_fp_trap_mode alpha_fptm
;
84 /* Nonzero if inside of a function, because the Alpha asm can't
85 handle .files inside of functions. */
87 static int inside_function
= FALSE
;
89 /* The number of cycles of latency we should assume on memory reads. */
91 int alpha_memory_latency
= 3;
93 /* Whether the function needs the GP. */
95 static int alpha_function_needs_gp
;
97 /* The alias set for prologue/epilogue register save/restore. */
99 static GTY(()) alias_set_type alpha_sr_alias_set
;
101 /* The assembler name of the current function. */
103 static const char *alpha_fnname
;
105 /* The next explicit relocation sequence number. */
106 extern GTY(()) int alpha_next_sequence_number
;
107 int alpha_next_sequence_number
= 1;
109 /* The literal and gpdisp sequence numbers for this insn, as printed
110 by %# and %* respectively. */
111 extern GTY(()) int alpha_this_literal_sequence_number
;
112 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
113 int alpha_this_literal_sequence_number
;
114 int alpha_this_gpdisp_sequence_number
;
116 /* Costs of various operations on the different architectures. */
118 struct alpha_rtx_cost_data
120 unsigned char fp_add
;
121 unsigned char fp_mult
;
122 unsigned char fp_div_sf
;
123 unsigned char fp_div_df
;
124 unsigned char int_mult_si
;
125 unsigned char int_mult_di
;
126 unsigned char int_shift
;
127 unsigned char int_cmov
;
128 unsigned short int_div
;
131 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
134 COSTS_N_INSNS (6), /* fp_add */
135 COSTS_N_INSNS (6), /* fp_mult */
136 COSTS_N_INSNS (34), /* fp_div_sf */
137 COSTS_N_INSNS (63), /* fp_div_df */
138 COSTS_N_INSNS (23), /* int_mult_si */
139 COSTS_N_INSNS (23), /* int_mult_di */
140 COSTS_N_INSNS (2), /* int_shift */
141 COSTS_N_INSNS (2), /* int_cmov */
142 COSTS_N_INSNS (97), /* int_div */
145 COSTS_N_INSNS (4), /* fp_add */
146 COSTS_N_INSNS (4), /* fp_mult */
147 COSTS_N_INSNS (15), /* fp_div_sf */
148 COSTS_N_INSNS (22), /* fp_div_df */
149 COSTS_N_INSNS (8), /* int_mult_si */
150 COSTS_N_INSNS (12), /* int_mult_di */
151 COSTS_N_INSNS (1) + 1, /* int_shift */
152 COSTS_N_INSNS (1), /* int_cmov */
153 COSTS_N_INSNS (83), /* int_div */
156 COSTS_N_INSNS (4), /* fp_add */
157 COSTS_N_INSNS (4), /* fp_mult */
158 COSTS_N_INSNS (12), /* fp_div_sf */
159 COSTS_N_INSNS (15), /* fp_div_df */
160 COSTS_N_INSNS (7), /* int_mult_si */
161 COSTS_N_INSNS (7), /* int_mult_di */
162 COSTS_N_INSNS (1), /* int_shift */
163 COSTS_N_INSNS (2), /* int_cmov */
164 COSTS_N_INSNS (86), /* int_div */
168 /* Similar but tuned for code size instead of execution latency. The
169 extra +N is fractional cost tuning based on latency. It's used to
170 encourage use of cheaper insns like shift, but only if there's just
173 static struct alpha_rtx_cost_data
const alpha_rtx_cost_size
=
175 COSTS_N_INSNS (1), /* fp_add */
176 COSTS_N_INSNS (1), /* fp_mult */
177 COSTS_N_INSNS (1), /* fp_div_sf */
178 COSTS_N_INSNS (1) + 1, /* fp_div_df */
179 COSTS_N_INSNS (1) + 1, /* int_mult_si */
180 COSTS_N_INSNS (1) + 2, /* int_mult_di */
181 COSTS_N_INSNS (1), /* int_shift */
182 COSTS_N_INSNS (1), /* int_cmov */
183 COSTS_N_INSNS (6), /* int_div */
186 /* Get the number of args of a function in one of two ways. */
187 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
188 #define NUM_ARGS crtl->args.info.num_args
190 #define NUM_ARGS crtl->args.info
196 /* Declarations of static functions. */
197 static struct machine_function
*alpha_init_machine_status (void);
198 static rtx
alpha_emit_xfloating_compare (enum rtx_code
*, rtx
, rtx
);
200 #if TARGET_ABI_OPEN_VMS
201 static void alpha_write_linkage (FILE *, const char *, tree
);
204 static void unicosmk_output_deferred_case_vectors (FILE *);
205 static void unicosmk_gen_dsib (unsigned long *);
206 static void unicosmk_output_ssib (FILE *, const char *);
207 static int unicosmk_need_dex (rtx
);
209 /* Implement TARGET_HANDLE_OPTION. */
212 alpha_handle_option (size_t code
, const char *arg
, int value
)
218 target_flags
|= MASK_SOFT_FP
;
222 case OPT_mieee_with_inexact
:
223 target_flags
|= MASK_IEEE_CONFORMANT
;
227 if (value
!= 16 && value
!= 32 && value
!= 64)
228 error ("bad value %qs for -mtls-size switch", arg
);
235 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
236 /* Implement TARGET_MANGLE_TYPE. */
239 alpha_mangle_type (const_tree type
)
241 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
242 && TARGET_LONG_DOUBLE_128
)
245 /* For all other types, use normal C++ mangling. */
250 /* Parse target option strings. */
253 override_options (void)
255 static const struct cpu_table
{
256 const char *const name
;
257 const enum processor_type processor
;
260 { "ev4", PROCESSOR_EV4
, 0 },
261 { "ev45", PROCESSOR_EV4
, 0 },
262 { "21064", PROCESSOR_EV4
, 0 },
263 { "ev5", PROCESSOR_EV5
, 0 },
264 { "21164", PROCESSOR_EV5
, 0 },
265 { "ev56", PROCESSOR_EV5
, MASK_BWX
},
266 { "21164a", PROCESSOR_EV5
, MASK_BWX
},
267 { "pca56", PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
268 { "21164PC",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
269 { "21164pc",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
270 { "ev6", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
271 { "21264", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
272 { "ev67", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
273 { "21264a", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
}
276 int const ct_size
= ARRAY_SIZE (cpu_table
);
279 /* Unicos/Mk doesn't have shared libraries. */
280 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
282 warning (0, "-f%s ignored for Unicos/Mk (not supported)",
283 (flag_pic
> 1) ? "PIC" : "pic");
287 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
288 floating-point instructions. Make that the default for this target. */
289 if (TARGET_ABI_UNICOSMK
)
290 alpha_fprm
= ALPHA_FPRM_DYN
;
292 alpha_fprm
= ALPHA_FPRM_NORM
;
294 alpha_tp
= ALPHA_TP_PROG
;
295 alpha_fptm
= ALPHA_FPTM_N
;
297 /* We cannot use su and sui qualifiers for conversion instructions on
298 Unicos/Mk. I'm not sure if this is due to assembler or hardware
299 limitations. Right now, we issue a warning if -mieee is specified
300 and then ignore it; eventually, we should either get it right or
301 disable the option altogether. */
305 if (TARGET_ABI_UNICOSMK
)
306 warning (0, "-mieee not supported on Unicos/Mk");
309 alpha_tp
= ALPHA_TP_INSN
;
310 alpha_fptm
= ALPHA_FPTM_SU
;
314 if (TARGET_IEEE_WITH_INEXACT
)
316 if (TARGET_ABI_UNICOSMK
)
317 warning (0, "-mieee-with-inexact not supported on Unicos/Mk");
320 alpha_tp
= ALPHA_TP_INSN
;
321 alpha_fptm
= ALPHA_FPTM_SUI
;
327 if (! strcmp (alpha_tp_string
, "p"))
328 alpha_tp
= ALPHA_TP_PROG
;
329 else if (! strcmp (alpha_tp_string
, "f"))
330 alpha_tp
= ALPHA_TP_FUNC
;
331 else if (! strcmp (alpha_tp_string
, "i"))
332 alpha_tp
= ALPHA_TP_INSN
;
334 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string
);
337 if (alpha_fprm_string
)
339 if (! strcmp (alpha_fprm_string
, "n"))
340 alpha_fprm
= ALPHA_FPRM_NORM
;
341 else if (! strcmp (alpha_fprm_string
, "m"))
342 alpha_fprm
= ALPHA_FPRM_MINF
;
343 else if (! strcmp (alpha_fprm_string
, "c"))
344 alpha_fprm
= ALPHA_FPRM_CHOP
;
345 else if (! strcmp (alpha_fprm_string
,"d"))
346 alpha_fprm
= ALPHA_FPRM_DYN
;
348 error ("bad value %qs for -mfp-rounding-mode switch",
352 if (alpha_fptm_string
)
354 if (strcmp (alpha_fptm_string
, "n") == 0)
355 alpha_fptm
= ALPHA_FPTM_N
;
356 else if (strcmp (alpha_fptm_string
, "u") == 0)
357 alpha_fptm
= ALPHA_FPTM_U
;
358 else if (strcmp (alpha_fptm_string
, "su") == 0)
359 alpha_fptm
= ALPHA_FPTM_SU
;
360 else if (strcmp (alpha_fptm_string
, "sui") == 0)
361 alpha_fptm
= ALPHA_FPTM_SUI
;
363 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string
);
366 if (alpha_cpu_string
)
368 for (i
= 0; i
< ct_size
; i
++)
369 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
371 alpha_tune
= alpha_cpu
= cpu_table
[i
].processor
;
372 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
);
373 target_flags
|= cpu_table
[i
].flags
;
377 error ("bad value %qs for -mcpu switch", alpha_cpu_string
);
380 if (alpha_tune_string
)
382 for (i
= 0; i
< ct_size
; i
++)
383 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
385 alpha_tune
= cpu_table
[i
].processor
;
389 error ("bad value %qs for -mcpu switch", alpha_tune_string
);
392 /* Do some sanity checks on the above options. */
394 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
396 warning (0, "trap mode not supported on Unicos/Mk");
397 alpha_fptm
= ALPHA_FPTM_N
;
400 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
401 && alpha_tp
!= ALPHA_TP_INSN
&& alpha_cpu
!= PROCESSOR_EV6
)
403 warning (0, "fp software completion requires -mtrap-precision=i");
404 alpha_tp
= ALPHA_TP_INSN
;
407 if (alpha_cpu
== PROCESSOR_EV6
)
409 /* Except for EV6 pass 1 (not released), we always have precise
410 arithmetic traps. Which means we can do software completion
411 without minding trap shadows. */
412 alpha_tp
= ALPHA_TP_PROG
;
415 if (TARGET_FLOAT_VAX
)
417 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
419 warning (0, "rounding mode not supported for VAX floats");
420 alpha_fprm
= ALPHA_FPRM_NORM
;
422 if (alpha_fptm
== ALPHA_FPTM_SUI
)
424 warning (0, "trap mode not supported for VAX floats");
425 alpha_fptm
= ALPHA_FPTM_SU
;
427 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
428 warning (0, "128-bit long double not supported for VAX floats");
429 target_flags
&= ~MASK_LONG_DOUBLE_128
;
436 if (!alpha_mlat_string
)
437 alpha_mlat_string
= "L1";
439 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
440 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
442 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
443 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
444 && alpha_mlat_string
[2] == '\0')
446 static int const cache_latency
[][4] =
448 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
449 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
450 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
453 lat
= alpha_mlat_string
[1] - '0';
454 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_tune
][lat
-1] == -1)
456 warning (0, "L%d cache latency unknown for %s",
457 lat
, alpha_cpu_name
[alpha_tune
]);
461 lat
= cache_latency
[alpha_tune
][lat
-1];
463 else if (! strcmp (alpha_mlat_string
, "main"))
465 /* Most current memories have about 370ns latency. This is
466 a reasonable guess for a fast cpu. */
471 warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string
);
475 alpha_memory_latency
= lat
;
478 /* Default the definition of "small data" to 8 bytes. */
482 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
484 target_flags
|= MASK_SMALL_DATA
;
485 else if (flag_pic
== 2)
486 target_flags
&= ~MASK_SMALL_DATA
;
488 /* Align labels and loops for optimal branching. */
489 /* ??? Kludge these by not doing anything if we don't optimize and also if
490 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
491 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
493 if (align_loops
<= 0)
495 if (align_jumps
<= 0)
498 if (align_functions
<= 0)
499 align_functions
= 16;
501 /* Acquire a unique set number for our register saves and restores. */
502 alpha_sr_alias_set
= new_alias_set ();
504 /* Register variables and functions with the garbage collector. */
506 /* Set up function hooks. */
507 init_machine_status
= alpha_init_machine_status
;
509 /* Tell the compiler when we're using VAX floating point. */
510 if (TARGET_FLOAT_VAX
)
512 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
513 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
514 REAL_MODE_FORMAT (TFmode
) = NULL
;
517 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
518 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
519 target_flags
|= MASK_LONG_DOUBLE_128
;
522 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
523 can be optimized to ap = __builtin_next_arg (0). */
524 if (TARGET_ABI_UNICOSMK
)
525 targetm
.expand_builtin_va_start
= NULL
;
528 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
531 zap_mask (HOST_WIDE_INT value
)
535 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
537 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
543 /* Return true if OP is valid for a particular TLS relocation.
544 We are already guaranteed that OP is a CONST. */
547 tls_symbolic_operand_1 (rtx op
, int size
, int unspec
)
551 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
553 op
= XVECEXP (op
, 0, 0);
555 if (GET_CODE (op
) != SYMBOL_REF
)
558 switch (SYMBOL_REF_TLS_MODEL (op
))
560 case TLS_MODEL_LOCAL_DYNAMIC
:
561 return unspec
== UNSPEC_DTPREL
&& size
== alpha_tls_size
;
562 case TLS_MODEL_INITIAL_EXEC
:
563 return unspec
== UNSPEC_TPREL
&& size
== 64;
564 case TLS_MODEL_LOCAL_EXEC
:
565 return unspec
== UNSPEC_TPREL
&& size
== alpha_tls_size
;
571 /* Used by aligned_memory_operand and unaligned_memory_operand to
572 resolve what reload is going to do with OP if it's a register. */
575 resolve_reload_operand (rtx op
)
577 if (reload_in_progress
)
580 if (GET_CODE (tmp
) == SUBREG
)
581 tmp
= SUBREG_REG (tmp
);
583 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
585 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
593 /* The scalar modes supported differs from the default check-what-c-supports
594 version in that sometimes TFmode is available even when long double
595 indicates only DFmode. On unicosmk, we have the situation that HImode
596 doesn't map to any C type, but of course we still support that. */
599 alpha_scalar_mode_supported_p (enum machine_mode mode
)
607 case TImode
: /* via optabs.c */
615 return TARGET_HAS_XFLOATING_LIBS
;
622 /* Alpha implements a couple of integer vector mode operations when
623 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
624 which allows the vectorizer to operate on e.g. move instructions,
625 or when expand_vector_operations can do something useful. */
628 alpha_vector_mode_supported_p (enum machine_mode mode
)
630 return mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
;
633 /* Return 1 if this function can directly return via $26. */
638 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
640 && alpha_sa_size () == 0
641 && get_frame_size () == 0
642 && crtl
->outgoing_args_size
== 0
643 && crtl
->args
.pretend_args_size
== 0);
646 /* Return the ADDR_VEC associated with a tablejump insn. */
649 alpha_tablejump_addr_vec (rtx insn
)
653 tmp
= JUMP_LABEL (insn
);
656 tmp
= NEXT_INSN (tmp
);
660 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
661 return PATTERN (tmp
);
665 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
668 alpha_tablejump_best_label (rtx insn
)
670 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
671 rtx best_label
= NULL_RTX
;
673 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
674 there for edge frequency counts from profile data. */
678 int n_labels
= XVECLEN (jump_table
, 1);
682 for (i
= 0; i
< n_labels
; i
++)
686 for (j
= i
+ 1; j
< n_labels
; j
++)
687 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
688 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
691 if (count
> best_count
)
692 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
696 return best_label
? best_label
: const0_rtx
;
699 /* Return the TLS model to use for SYMBOL. */
701 static enum tls_model
702 tls_symbolic_operand_type (rtx symbol
)
704 enum tls_model model
;
706 if (GET_CODE (symbol
) != SYMBOL_REF
)
707 return TLS_MODEL_NONE
;
708 model
= SYMBOL_REF_TLS_MODEL (symbol
);
710 /* Local-exec with a 64-bit size is the same code as initial-exec. */
711 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
712 model
= TLS_MODEL_INITIAL_EXEC
;
717 /* Return true if the function DECL will share the same GP as any
718 function in the current unit of translation. */
721 decl_has_samegp (const_tree decl
)
723 /* Functions that are not local can be overridden, and thus may
724 not share the same gp. */
725 if (!(*targetm
.binds_local_p
) (decl
))
728 /* If -msmall-data is in effect, assume that there is only one GP
729 for the module, and so any local symbol has this property. We
730 need explicit relocations to be able to enforce this for symbols
731 not defined in this unit of translation, however. */
732 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
735 /* Functions that are not external are defined in this UoT. */
736 /* ??? Irritatingly, static functions not yet emitted are still
737 marked "external". Apply this to non-static functions only. */
738 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
741 /* Return true if EXP should be placed in the small data section. */
744 alpha_in_small_data_p (const_tree exp
)
746 /* We want to merge strings, so we never consider them small data. */
747 if (TREE_CODE (exp
) == STRING_CST
)
750 /* Functions are never in the small data area. Duh. */
751 if (TREE_CODE (exp
) == FUNCTION_DECL
)
754 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
756 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
757 if (strcmp (section
, ".sdata") == 0
758 || strcmp (section
, ".sbss") == 0)
763 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
765 /* If this is an incomplete type with size 0, then we can't put it
766 in sdata because it might be too big when completed. */
767 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
774 #if TARGET_ABI_OPEN_VMS
776 alpha_linkage_symbol_p (const char *symname
)
778 int symlen
= strlen (symname
);
781 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
786 #define LINKAGE_SYMBOL_REF_P(X) \
787 ((GET_CODE (X) == SYMBOL_REF \
788 && alpha_linkage_symbol_p (XSTR (X, 0))) \
789 || (GET_CODE (X) == CONST \
790 && GET_CODE (XEXP (X, 0)) == PLUS \
791 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
792 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
795 /* legitimate_address_p recognizes an RTL expression that is a valid
796 memory address for an instruction. The MODE argument is the
797 machine mode for the MEM expression that wants to use this address.
799 For Alpha, we have either a constant address or the sum of a
800 register and a constant address, or just a register. For DImode,
801 any of those forms can be surrounded with an AND that clear the
802 low-order three bits; this is an "unaligned" access. */
805 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
807 /* If this is an ldq_u type address, discard the outer AND. */
809 && GET_CODE (x
) == AND
810 && CONST_INT_P (XEXP (x
, 1))
811 && INTVAL (XEXP (x
, 1)) == -8)
814 /* Discard non-paradoxical subregs. */
815 if (GET_CODE (x
) == SUBREG
816 && (GET_MODE_SIZE (GET_MODE (x
))
817 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
820 /* Unadorned general registers are valid. */
823 ? STRICT_REG_OK_FOR_BASE_P (x
)
824 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
827 /* Constant addresses (i.e. +/- 32k) are valid. */
828 if (CONSTANT_ADDRESS_P (x
))
831 #if TARGET_ABI_OPEN_VMS
832 if (LINKAGE_SYMBOL_REF_P (x
))
836 /* Register plus a small constant offset is valid. */
837 if (GET_CODE (x
) == PLUS
)
839 rtx ofs
= XEXP (x
, 1);
842 /* Discard non-paradoxical subregs. */
843 if (GET_CODE (x
) == SUBREG
844 && (GET_MODE_SIZE (GET_MODE (x
))
845 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
851 && NONSTRICT_REG_OK_FP_BASE_P (x
)
852 && CONST_INT_P (ofs
))
855 ? STRICT_REG_OK_FOR_BASE_P (x
)
856 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
857 && CONSTANT_ADDRESS_P (ofs
))
862 /* If we're managing explicit relocations, LO_SUM is valid, as are small
863 data symbols. Avoid explicit relocations of modes larger than word
864 mode since i.e. $LC0+8($1) can fold around +/- 32k offset. */
865 else if (TARGET_EXPLICIT_RELOCS
866 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
868 if (small_symbolic_operand (x
, Pmode
))
871 if (GET_CODE (x
) == LO_SUM
)
873 rtx ofs
= XEXP (x
, 1);
876 /* Discard non-paradoxical subregs. */
877 if (GET_CODE (x
) == SUBREG
878 && (GET_MODE_SIZE (GET_MODE (x
))
879 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
882 /* Must have a valid base register. */
885 ? STRICT_REG_OK_FOR_BASE_P (x
)
886 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
889 /* The symbol must be local. */
890 if (local_symbolic_operand (ofs
, Pmode
)
891 || dtp32_symbolic_operand (ofs
, Pmode
)
892 || tp32_symbolic_operand (ofs
, Pmode
))
900 /* Build the SYMBOL_REF for __tls_get_addr. */
902 static GTY(()) rtx tls_get_addr_libfunc
;
905 get_tls_get_addr (void)
907 if (!tls_get_addr_libfunc
)
908 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
909 return tls_get_addr_libfunc
;
912 /* Try machine-dependent ways of modifying an illegitimate address
913 to be legitimate. If we find one, return the new, valid address. */
916 alpha_legitimize_address_1 (rtx x
, rtx scratch
, enum machine_mode mode
)
918 HOST_WIDE_INT addend
;
920 /* If the address is (plus reg const_int) and the CONST_INT is not a
921 valid offset, compute the high part of the constant and add it to
922 the register. Then our address is (plus temp low-part-const). */
923 if (GET_CODE (x
) == PLUS
924 && REG_P (XEXP (x
, 0))
925 && CONST_INT_P (XEXP (x
, 1))
926 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
928 addend
= INTVAL (XEXP (x
, 1));
933 /* If the address is (const (plus FOO const_int)), find the low-order
934 part of the CONST_INT. Then load FOO plus any high-order part of the
935 CONST_INT into a register. Our address is (plus reg low-part-const).
936 This is done to reduce the number of GOT entries. */
937 if (can_create_pseudo_p ()
938 && GET_CODE (x
) == CONST
939 && GET_CODE (XEXP (x
, 0)) == PLUS
940 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
942 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
943 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
947 /* If we have a (plus reg const), emit the load as in (2), then add
948 the two registers, and finally generate (plus reg low-part-const) as
950 if (can_create_pseudo_p ()
951 && GET_CODE (x
) == PLUS
952 && REG_P (XEXP (x
, 0))
953 && GET_CODE (XEXP (x
, 1)) == CONST
954 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
955 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 1), 0), 1)))
957 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
958 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
959 XEXP (XEXP (XEXP (x
, 1), 0), 0),
960 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
964 /* If this is a local symbol, split the address into HIGH/LO_SUM parts.
965 Avoid modes larger than word mode since i.e. $LC0+8($1) can fold
966 around +/- 32k offset. */
967 if (TARGET_EXPLICIT_RELOCS
968 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
969 && symbolic_operand (x
, Pmode
))
971 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
973 switch (tls_symbolic_operand_type (x
))
978 case TLS_MODEL_GLOBAL_DYNAMIC
:
981 r0
= gen_rtx_REG (Pmode
, 0);
982 r16
= gen_rtx_REG (Pmode
, 16);
983 tga
= get_tls_get_addr ();
984 dest
= gen_reg_rtx (Pmode
);
985 seq
= GEN_INT (alpha_next_sequence_number
++);
987 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
988 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
989 insn
= emit_call_insn (insn
);
990 RTL_CONST_CALL_P (insn
) = 1;
991 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
996 emit_libcall_block (insn
, dest
, r0
, x
);
999 case TLS_MODEL_LOCAL_DYNAMIC
:
1002 r0
= gen_rtx_REG (Pmode
, 0);
1003 r16
= gen_rtx_REG (Pmode
, 16);
1004 tga
= get_tls_get_addr ();
1005 scratch
= gen_reg_rtx (Pmode
);
1006 seq
= GEN_INT (alpha_next_sequence_number
++);
1008 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1009 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1010 insn
= emit_call_insn (insn
);
1011 RTL_CONST_CALL_P (insn
) = 1;
1012 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1014 insn
= get_insns ();
1017 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1018 UNSPEC_TLSLDM_CALL
);
1019 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1021 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1022 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1024 if (alpha_tls_size
== 64)
1026 dest
= gen_reg_rtx (Pmode
);
1027 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1028 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1031 if (alpha_tls_size
== 32)
1033 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1034 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1035 scratch
= gen_reg_rtx (Pmode
);
1036 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1038 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1040 case TLS_MODEL_INITIAL_EXEC
:
1041 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1042 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1043 tp
= gen_reg_rtx (Pmode
);
1044 scratch
= gen_reg_rtx (Pmode
);
1045 dest
= gen_reg_rtx (Pmode
);
1047 emit_insn (gen_load_tp (tp
));
1048 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1049 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1052 case TLS_MODEL_LOCAL_EXEC
:
1053 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1054 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1055 tp
= gen_reg_rtx (Pmode
);
1057 emit_insn (gen_load_tp (tp
));
1058 if (alpha_tls_size
== 32)
1060 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1061 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1062 tp
= gen_reg_rtx (Pmode
);
1063 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1065 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1071 if (local_symbolic_operand (x
, Pmode
))
1073 if (small_symbolic_operand (x
, Pmode
))
1077 if (can_create_pseudo_p ())
1078 scratch
= gen_reg_rtx (Pmode
);
1079 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1080 gen_rtx_HIGH (Pmode
, x
)));
1081 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1090 HOST_WIDE_INT low
, high
;
1092 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1094 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1098 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1099 (!can_create_pseudo_p () ? scratch
: NULL_RTX
),
1100 1, OPTAB_LIB_WIDEN
);
1102 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1103 (!can_create_pseudo_p () ? scratch
: NULL_RTX
),
1104 1, OPTAB_LIB_WIDEN
);
1106 return plus_constant (x
, low
);
1111 /* Try machine-dependent ways of modifying an illegitimate address
1112 to be legitimate. Return X or the new, valid address. */
1115 alpha_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1116 enum machine_mode mode
)
1118 rtx new_x
= alpha_legitimize_address_1 (x
, NULL_RTX
, mode
);
1119 return new_x
? new_x
: x
;
1122 /* Primarily this is required for TLS symbols, but given that our move
1123 patterns *ought* to be able to handle any symbol at any time, we
1124 should never be spilling symbolic operands to the constant pool, ever. */
1127 alpha_cannot_force_const_mem (rtx x
)
1129 enum rtx_code code
= GET_CODE (x
);
1130 return code
== SYMBOL_REF
|| code
== LABEL_REF
|| code
== CONST
;
1133 /* We do not allow indirect calls to be optimized into sibling calls, nor
1134 can we allow a call to a function with a different GP to be optimized
1138 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1140 /* Can't do indirect tail calls, since we don't know if the target
1141 uses the same GP. */
1145 /* Otherwise, we can make a tail call if the target function shares
1147 return decl_has_samegp (decl
);
1151 some_small_symbolic_operand_int (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1155 /* Don't re-split. */
1156 if (GET_CODE (x
) == LO_SUM
)
1159 return small_symbolic_operand (x
, Pmode
) != 0;
1163 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1167 /* Don't re-split. */
1168 if (GET_CODE (x
) == LO_SUM
)
1171 if (small_symbolic_operand (x
, Pmode
))
1173 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1182 split_small_symbolic_operand (rtx x
)
1185 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1189 /* Indicate that INSN cannot be duplicated. This is true for any insn
1190 that we've marked with gpdisp relocs, since those have to stay in
1191 1-1 correspondence with one another.
1193 Technically we could copy them if we could set up a mapping from one
1194 sequence number to another, across the set of insns to be duplicated.
1195 This seems overly complicated and error-prone since interblock motion
1196 from sched-ebb could move one of the pair of insns to a different block.
1198 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1199 then they'll be in a different block from their ldgp. Which could lead
1200 the bb reorder code to think that it would be ok to copy just the block
1201 containing the call and branch to the block containing the ldgp. */
1204 alpha_cannot_copy_insn_p (rtx insn
)
1206 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
1208 if (recog_memoized (insn
) >= 0)
1209 return get_attr_cannot_copy (insn
);
1215 /* Try a machine-dependent way of reloading an illegitimate address
1216 operand. If we find one, push the reload and return the new rtx. */
1219 alpha_legitimize_reload_address (rtx x
,
1220 enum machine_mode mode ATTRIBUTE_UNUSED
,
1221 int opnum
, int type
,
1222 int ind_levels ATTRIBUTE_UNUSED
)
1224 /* We must recognize output that we have already generated ourselves. */
1225 if (GET_CODE (x
) == PLUS
1226 && GET_CODE (XEXP (x
, 0)) == PLUS
1227 && REG_P (XEXP (XEXP (x
, 0), 0))
1228 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
1229 && CONST_INT_P (XEXP (x
, 1)))
1231 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1232 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1233 opnum
, (enum reload_type
) type
);
1237 /* We wish to handle large displacements off a base register by
1238 splitting the addend across an ldah and the mem insn. This
1239 cuts number of extra insns needed from 3 to 1. */
1240 if (GET_CODE (x
) == PLUS
1241 && REG_P (XEXP (x
, 0))
1242 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1243 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1244 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1246 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1247 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1249 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1251 /* Check for 32-bit overflow. */
1252 if (high
+ low
!= val
)
1255 /* Reload the high part into a base reg; leave the low part
1256 in the mem directly. */
1257 x
= gen_rtx_PLUS (GET_MODE (x
),
1258 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1262 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1263 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1264 opnum
, (enum reload_type
) type
);
1271 /* Compute a (partial) cost for rtx X. Return true if the complete
1272 cost has been computed, and false if subexpressions should be
1273 scanned. In either case, *TOTAL contains the cost result. */
1276 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
1279 enum machine_mode mode
= GET_MODE (x
);
1280 bool float_mode_p
= FLOAT_MODE_P (mode
);
1281 const struct alpha_rtx_cost_data
*cost_data
;
1284 cost_data
= &alpha_rtx_cost_size
;
1286 cost_data
= &alpha_rtx_cost_data
[alpha_tune
];
1291 /* If this is an 8-bit constant, return zero since it can be used
1292 nearly anywhere with no cost. If it is a valid operand for an
1293 ADD or AND, likewise return 0 if we know it will be used in that
1294 context. Otherwise, return 2 since it might be used there later.
1295 All other constants take at least two insns. */
1296 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
1304 if (x
== CONST0_RTX (mode
))
1306 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
1307 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
1309 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
1312 *total
= COSTS_N_INSNS (2);
1318 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
1319 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
1320 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
1321 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
1322 else if (tls_symbolic_operand_type (x
))
1323 /* Estimate of cost for call_pal rduniq. */
1324 /* ??? How many insns do we emit here? More than one... */
1325 *total
= COSTS_N_INSNS (15);
1327 /* Otherwise we do a load from the GOT. */
1328 *total
= COSTS_N_INSNS (!speed
? 1 : alpha_memory_latency
);
1332 /* This is effectively an add_operand. */
1339 *total
= cost_data
->fp_add
;
1340 else if (GET_CODE (XEXP (x
, 0)) == MULT
1341 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
1343 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0),
1344 (enum rtx_code
) outer_code
, speed
)
1345 + rtx_cost (XEXP (x
, 1),
1346 (enum rtx_code
) outer_code
, speed
)
1347 + COSTS_N_INSNS (1));
1354 *total
= cost_data
->fp_mult
;
1355 else if (mode
== DImode
)
1356 *total
= cost_data
->int_mult_di
;
1358 *total
= cost_data
->int_mult_si
;
1362 if (CONST_INT_P (XEXP (x
, 1))
1363 && INTVAL (XEXP (x
, 1)) <= 3)
1365 *total
= COSTS_N_INSNS (1);
1372 *total
= cost_data
->int_shift
;
1377 *total
= cost_data
->fp_add
;
1379 *total
= cost_data
->int_cmov
;
1387 *total
= cost_data
->int_div
;
1388 else if (mode
== SFmode
)
1389 *total
= cost_data
->fp_div_sf
;
1391 *total
= cost_data
->fp_div_df
;
1395 *total
= COSTS_N_INSNS (!speed
? 1 : alpha_memory_latency
);
1401 *total
= COSTS_N_INSNS (1);
1409 *total
= COSTS_N_INSNS (1) + cost_data
->int_cmov
;
1415 case UNSIGNED_FLOAT
:
1418 case FLOAT_TRUNCATE
:
1419 *total
= cost_data
->fp_add
;
1423 if (MEM_P (XEXP (x
, 0)))
1426 *total
= cost_data
->fp_add
;
1434 /* REF is an alignable memory location. Place an aligned SImode
1435 reference into *PALIGNED_MEM and the number of bits to shift into
1436 *PBITNUM. SCRATCH is a free register for use in reloading out
1437 of range stack slots. */
1440 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
1443 HOST_WIDE_INT disp
, offset
;
1445 gcc_assert (MEM_P (ref
));
1447 if (reload_in_progress
1448 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1450 base
= find_replacement (&XEXP (ref
, 0));
1451 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1454 base
= XEXP (ref
, 0);
1456 if (GET_CODE (base
) == PLUS
)
1457 disp
= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1461 /* Find the byte offset within an aligned word. If the memory itself is
1462 claimed to be aligned, believe it. Otherwise, aligned_memory_operand
1463 will have examined the base register and determined it is aligned, and
1464 thus displacements from it are naturally alignable. */
1465 if (MEM_ALIGN (ref
) >= 32)
1470 /* Access the entire aligned word. */
1471 *paligned_mem
= widen_memory_access (ref
, SImode
, -offset
);
1473 /* Convert the byte offset within the word to a bit offset. */
1474 if (WORDS_BIG_ENDIAN
)
1475 offset
= 32 - (GET_MODE_BITSIZE (GET_MODE (ref
)) + offset
* 8);
1478 *pbitnum
= GEN_INT (offset
);
1481 /* Similar, but just get the address. Handle the two reload cases.
1482 Add EXTRA_OFFSET to the address we return. */
1485 get_unaligned_address (rtx ref
)
1488 HOST_WIDE_INT offset
= 0;
1490 gcc_assert (MEM_P (ref
));
1492 if (reload_in_progress
1493 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1495 base
= find_replacement (&XEXP (ref
, 0));
1497 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1500 base
= XEXP (ref
, 0);
1502 if (GET_CODE (base
) == PLUS
)
1503 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1505 return plus_constant (base
, offset
);
1508 /* Compute a value X, such that X & 7 == (ADDR + OFS) & 7.
1509 X is always returned in a register. */
1512 get_unaligned_offset (rtx addr
, HOST_WIDE_INT ofs
)
1514 if (GET_CODE (addr
) == PLUS
)
1516 ofs
+= INTVAL (XEXP (addr
, 1));
1517 addr
= XEXP (addr
, 0);
1520 return expand_simple_binop (Pmode
, PLUS
, addr
, GEN_INT (ofs
& 7),
1521 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1524 /* On the Alpha, all (non-symbolic) constants except zero go into
1525 a floating-point register via memory. Note that we cannot
1526 return anything that is not a subset of RCLASS, and that some
1527 symbolic constants cannot be dropped to memory. */
1530 alpha_preferred_reload_class(rtx x
, enum reg_class rclass
)
1532 /* Zero is present in any register class. */
1533 if (x
== CONST0_RTX (GET_MODE (x
)))
1536 /* These sorts of constants we can easily drop to memory. */
1538 || GET_CODE (x
) == CONST_DOUBLE
1539 || GET_CODE (x
) == CONST_VECTOR
)
1541 if (rclass
== FLOAT_REGS
)
1543 if (rclass
== ALL_REGS
)
1544 return GENERAL_REGS
;
1548 /* All other kinds of constants should not (and in the case of HIGH
1549 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1550 secondary reload. */
1552 return (rclass
== ALL_REGS
? GENERAL_REGS
: rclass
);
1557 /* Inform reload about cases where moving X with a mode MODE to a register in
1558 RCLASS requires an extra scratch or immediate register. Return the class
1559 needed for the immediate register. */
1561 static enum reg_class
1562 alpha_secondary_reload (bool in_p
, rtx x
, enum reg_class rclass
,
1563 enum machine_mode mode
, secondary_reload_info
*sri
)
1565 /* Loading and storing HImode or QImode values to and from memory
1566 usually requires a scratch register. */
1567 if (!TARGET_BWX
&& (mode
== QImode
|| mode
== HImode
|| mode
== CQImode
))
1569 if (any_memory_operand (x
, mode
))
1573 if (!aligned_memory_operand (x
, mode
))
1574 sri
->icode
= reload_in_optab
[mode
];
1577 sri
->icode
= reload_out_optab
[mode
];
1582 /* We also cannot do integral arithmetic into FP regs, as might result
1583 from register elimination into a DImode fp register. */
1584 if (rclass
== FLOAT_REGS
)
1586 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == AND
)
1587 return GENERAL_REGS
;
1588 if (in_p
&& INTEGRAL_MODE_P (mode
)
1589 && !MEM_P (x
) && !REG_P (x
) && !CONST_INT_P (x
))
1590 return GENERAL_REGS
;
1596 /* Subfunction of the following function. Update the flags of any MEM
1597 found in part of X. */
1600 alpha_set_memflags_1 (rtx
*xp
, void *data
)
1602 rtx x
= *xp
, orig
= (rtx
) data
;
1607 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (orig
);
1608 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (orig
);
1609 MEM_SCALAR_P (x
) = MEM_SCALAR_P (orig
);
1610 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (orig
);
1611 MEM_READONLY_P (x
) = MEM_READONLY_P (orig
);
1613 /* Sadly, we cannot use alias sets because the extra aliasing
1614 produced by the AND interferes. Given that two-byte quantities
1615 are the only thing we would be able to differentiate anyway,
1616 there does not seem to be any point in convoluting the early
1617 out of the alias check. */
1622 /* Given SEQ, which is an INSN list, look for any MEMs in either
1623 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1624 volatile flags from REF into each of the MEMs found. If REF is not
1625 a MEM, don't do anything. */
1628 alpha_set_memflags (rtx seq
, rtx ref
)
1635 /* This is only called from alpha.md, after having had something
1636 generated from one of the insn patterns. So if everything is
1637 zero, the pattern is already up-to-date. */
1638 if (!MEM_VOLATILE_P (ref
)
1639 && !MEM_IN_STRUCT_P (ref
)
1640 && !MEM_SCALAR_P (ref
)
1641 && !MEM_NOTRAP_P (ref
)
1642 && !MEM_READONLY_P (ref
))
1645 for (insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
1647 for_each_rtx (&PATTERN (insn
), alpha_set_memflags_1
, (void *) ref
);
1652 static rtx
alpha_emit_set_const (rtx
, enum machine_mode
, HOST_WIDE_INT
,
1655 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1656 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1657 and return pc_rtx if successful. */
1660 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
1661 HOST_WIDE_INT c
, int n
, bool no_output
)
1663 HOST_WIDE_INT new_const
;
1665 /* Use a pseudo if highly optimizing and still generating RTL. */
1667 = (flag_expensive_optimizations
&& can_create_pseudo_p () ? 0 : target
);
1670 /* If this is a sign-extended 32-bit constant, we can do this in at most
1671 three insns, so do it if we have enough insns left. We always have
1672 a sign-extended 32-bit constant when compiling on a narrow machine. */
1674 if (HOST_BITS_PER_WIDE_INT
!= 64
1675 || c
>> 31 == -1 || c
>> 31 == 0)
1677 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1678 HOST_WIDE_INT tmp1
= c
- low
;
1679 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
1680 HOST_WIDE_INT extra
= 0;
1682 /* If HIGH will be interpreted as negative but the constant is
1683 positive, we must adjust it to do two ldha insns. */
1685 if ((high
& 0x8000) != 0 && c
>= 0)
1689 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1692 if (c
== low
|| (low
== 0 && extra
== 0))
1694 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1695 but that meant that we can't handle INT_MIN on 32-bit machines
1696 (like NT/Alpha), because we recurse indefinitely through
1697 emit_move_insn to gen_movdi. So instead, since we know exactly
1698 what we want, create it explicitly. */
1703 target
= gen_reg_rtx (mode
);
1704 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
1707 else if (n
>= 2 + (extra
!= 0))
1711 if (!can_create_pseudo_p ())
1713 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
1717 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
1720 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1721 This means that if we go through expand_binop, we'll try to
1722 generate extensions, etc, which will require new pseudos, which
1723 will fail during some split phases. The SImode add patterns
1724 still exist, but are not named. So build the insns by hand. */
1729 subtarget
= gen_reg_rtx (mode
);
1730 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
1731 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
1737 target
= gen_reg_rtx (mode
);
1738 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
1739 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
1745 /* If we couldn't do it that way, try some other methods. But if we have
1746 no instructions left, don't bother. Likewise, if this is SImode and
1747 we can't make pseudos, we can't do anything since the expand_binop
1748 and expand_unop calls will widen and try to make pseudos. */
1750 if (n
== 1 || (mode
== SImode
&& !can_create_pseudo_p ()))
1753 /* Next, see if we can load a related constant and then shift and possibly
1754 negate it to get the constant we want. Try this once each increasing
1755 numbers of insns. */
1757 for (i
= 1; i
< n
; i
++)
1759 /* First, see if minus some low bits, we've an easy load of
1762 new_const
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1765 temp
= alpha_emit_set_const (subtarget
, mode
, c
- new_const
, i
, no_output
);
1770 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new_const
),
1771 target
, 0, OPTAB_WIDEN
);
1775 /* Next try complementing. */
1776 temp
= alpha_emit_set_const (subtarget
, mode
, ~c
, i
, no_output
);
1781 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
1784 /* Next try to form a constant and do a left shift. We can do this
1785 if some low-order bits are zero; the exact_log2 call below tells
1786 us that information. The bits we are shifting out could be any
1787 value, but here we'll just try the 0- and sign-extended forms of
1788 the constant. To try to increase the chance of having the same
1789 constant in more than one insn, start at the highest number of
1790 bits to shift, but try all possibilities in case a ZAPNOT will
1793 bits
= exact_log2 (c
& -c
);
1795 for (; bits
> 0; bits
--)
1797 new_const
= c
>> bits
;
1798 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1801 new_const
= (unsigned HOST_WIDE_INT
)c
>> bits
;
1802 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1809 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
1810 target
, 0, OPTAB_WIDEN
);
1814 /* Now try high-order zero bits. Here we try the shifted-in bits as
1815 all zero and all ones. Be careful to avoid shifting outside the
1816 mode and to avoid shifting outside the host wide int size. */
1817 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1818 confuse the recursive call and set all of the high 32 bits. */
1820 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1821 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64));
1823 for (; bits
> 0; bits
--)
1825 new_const
= c
<< bits
;
1826 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1829 new_const
= (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1830 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1837 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
1838 target
, 1, OPTAB_WIDEN
);
1842 /* Now try high-order 1 bits. We get that with a sign-extension.
1843 But one bit isn't enough here. Be careful to avoid shifting outside
1844 the mode and to avoid shifting outside the host wide int size. */
1846 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1847 - floor_log2 (~ c
) - 2);
1849 for (; bits
> 0; bits
--)
1851 new_const
= c
<< bits
;
1852 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1855 new_const
= (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1856 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1863 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
1864 target
, 0, OPTAB_WIDEN
);
1869 #if HOST_BITS_PER_WIDE_INT == 64
1870 /* Finally, see if can load a value into the target that is the same as the
1871 constant except that all bytes that are 0 are changed to be 0xff. If we
1872 can, then we can do a ZAPNOT to obtain the desired constant. */
1875 for (i
= 0; i
< 64; i
+= 8)
1876 if ((new_const
& ((HOST_WIDE_INT
) 0xff << i
)) == 0)
1877 new_const
|= (HOST_WIDE_INT
) 0xff << i
;
1879 /* We are only called for SImode and DImode. If this is SImode, ensure that
1880 we are sign extended to a full word. */
1883 new_const
= ((new_const
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1887 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, n
- 1, no_output
);
1892 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new_const
),
1893 target
, 0, OPTAB_WIDEN
);
1901 /* Try to output insns to set TARGET equal to the constant C if it can be
1902 done in less than N insns. Do all computations in MODE. Returns the place
1903 where the output has been placed if it can be done and the insns have been
1904 emitted. If it would take more than N insns, zero is returned and no
1905 insns and emitted. */
1908 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
1909 HOST_WIDE_INT c
, int n
, bool no_output
)
1911 enum machine_mode orig_mode
= mode
;
1912 rtx orig_target
= target
;
1916 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1917 can't load this constant in one insn, do this in DImode. */
1918 if (!can_create_pseudo_p () && mode
== SImode
1919 && REG_P (target
) && REGNO (target
) < FIRST_PSEUDO_REGISTER
)
1921 result
= alpha_emit_set_const_1 (target
, mode
, c
, 1, no_output
);
1925 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1928 else if (mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
)
1930 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1934 /* Try 1 insn, then 2, then up to N. */
1935 for (i
= 1; i
<= n
; i
++)
1937 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
, no_output
);
1945 insn
= get_last_insn ();
1946 set
= single_set (insn
);
1947 if (! CONSTANT_P (SET_SRC (set
)))
1948 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
1953 /* Allow for the case where we changed the mode of TARGET. */
1956 if (result
== target
)
1957 result
= orig_target
;
1958 else if (mode
!= orig_mode
)
1959 result
= gen_lowpart (orig_mode
, result
);
1965 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1966 fall back to a straight forward decomposition. We do this to avoid
1967 exponential run times encountered when looking for longer sequences
1968 with alpha_emit_set_const. */
1971 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
1973 HOST_WIDE_INT d1
, d2
, d3
, d4
;
1975 /* Decompose the entire word */
1976 #if HOST_BITS_PER_WIDE_INT >= 64
1977 gcc_assert (c2
== -(c1
< 0));
1978 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1980 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1981 c1
= (c1
- d2
) >> 32;
1982 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1984 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1985 gcc_assert (c1
== d4
);
1987 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1989 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1990 gcc_assert (c1
== d2
);
1992 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
1994 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1995 gcc_assert (c2
== d4
);
1998 /* Construct the high word */
2001 emit_move_insn (target
, GEN_INT (d4
));
2003 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2006 emit_move_insn (target
, GEN_INT (d3
));
2008 /* Shift it into place */
2009 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2011 /* Add in the low bits. */
2013 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2015 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2020 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
2024 alpha_extract_integer (rtx x
, HOST_WIDE_INT
*p0
, HOST_WIDE_INT
*p1
)
2026 HOST_WIDE_INT i0
, i1
;
2028 if (GET_CODE (x
) == CONST_VECTOR
)
2029 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
2032 if (CONST_INT_P (x
))
2037 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2039 i0
= CONST_DOUBLE_LOW (x
);
2044 i0
= CONST_DOUBLE_LOW (x
);
2045 i1
= CONST_DOUBLE_HIGH (x
);
2052 /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
2053 are willing to load the value into a register via a move pattern.
2054 Normally this is all symbolic constants, integral constants that
2055 take three or fewer instructions, and floating-point zero. */
2058 alpha_legitimate_constant_p (rtx x
)
2060 enum machine_mode mode
= GET_MODE (x
);
2061 HOST_WIDE_INT i0
, i1
;
2063 switch (GET_CODE (x
))
2070 if (GET_CODE (XEXP (x
, 0)) == PLUS
2071 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2072 x
= XEXP (XEXP (x
, 0), 0);
2076 if (GET_CODE (x
) != SYMBOL_REF
)
2082 /* TLS symbols are never valid. */
2083 return SYMBOL_REF_TLS_MODEL (x
) == 0;
2086 if (x
== CONST0_RTX (mode
))
2088 if (FLOAT_MODE_P (mode
))
2093 if (x
== CONST0_RTX (mode
))
2095 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2097 if (GET_MODE_SIZE (mode
) != 8)
2103 if (TARGET_BUILD_CONSTANTS
)
2105 alpha_extract_integer (x
, &i0
, &i1
);
2106 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== (-i0
< 0))
2107 return alpha_emit_set_const_1 (x
, mode
, i0
, 3, true) != NULL
;
2115 /* Operand 1 is known to be a constant, and should require more than one
2116 instruction to load. Emit that multi-part load. */
2119 alpha_split_const_mov (enum machine_mode mode
, rtx
*operands
)
2121 HOST_WIDE_INT i0
, i1
;
2122 rtx temp
= NULL_RTX
;
2124 alpha_extract_integer (operands
[1], &i0
, &i1
);
2126 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2127 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3, false);
2129 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2130 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2134 if (!rtx_equal_p (operands
[0], temp
))
2135 emit_move_insn (operands
[0], temp
);
2142 /* Expand a move instruction; return true if all work is done.
2143 We don't handle non-bwx subword loads here. */
2146 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2150 /* If the output is not a register, the input must be. */
2151 if (MEM_P (operands
[0])
2152 && ! reg_or_0_operand (operands
[1], mode
))
2153 operands
[1] = force_reg (mode
, operands
[1]);
2155 /* Allow legitimize_address to perform some simplifications. */
2156 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2158 tmp
= alpha_legitimize_address_1 (operands
[1], operands
[0], mode
);
2161 if (tmp
== operands
[0])
2168 /* Early out for non-constants and valid constants. */
2169 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2172 /* Split large integers. */
2173 if (CONST_INT_P (operands
[1])
2174 || GET_CODE (operands
[1]) == CONST_DOUBLE
2175 || GET_CODE (operands
[1]) == CONST_VECTOR
)
2177 if (alpha_split_const_mov (mode
, operands
))
2181 /* Otherwise we've nothing left but to drop the thing to memory. */
2182 tmp
= force_const_mem (mode
, operands
[1]);
2184 if (tmp
== NULL_RTX
)
2187 if (reload_in_progress
)
2189 emit_move_insn (operands
[0], XEXP (tmp
, 0));
2190 operands
[1] = replace_equiv_address (tmp
, operands
[0]);
2193 operands
[1] = validize_mem (tmp
);
2197 /* Expand a non-bwx QImode or HImode move instruction;
2198 return true if all work is done. */
2201 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2205 /* If the output is not a register, the input must be. */
2206 if (MEM_P (operands
[0]))
2207 operands
[1] = force_reg (mode
, operands
[1]);
2209 /* Handle four memory cases, unaligned and aligned for either the input
2210 or the output. The only case where we can be called during reload is
2211 for aligned loads; all other cases require temporaries. */
2213 if (any_memory_operand (operands
[1], mode
))
2215 if (aligned_memory_operand (operands
[1], mode
))
2217 if (reload_in_progress
)
2220 seq
= gen_reload_inqi_aligned (operands
[0], operands
[1]);
2222 seq
= gen_reload_inhi_aligned (operands
[0], operands
[1]);
2227 rtx aligned_mem
, bitnum
;
2228 rtx scratch
= gen_reg_rtx (SImode
);
2232 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2234 subtarget
= operands
[0];
2235 if (REG_P (subtarget
))
2236 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2238 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2241 seq
= gen_aligned_loadqi (subtarget
, aligned_mem
,
2244 seq
= gen_aligned_loadhi (subtarget
, aligned_mem
,
2249 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2254 /* Don't pass these as parameters since that makes the generated
2255 code depend on parameter evaluation order which will cause
2256 bootstrap failures. */
2258 rtx temp1
, temp2
, subtarget
, ua
;
2261 temp1
= gen_reg_rtx (DImode
);
2262 temp2
= gen_reg_rtx (DImode
);
2264 subtarget
= operands
[0];
2265 if (REG_P (subtarget
))
2266 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2268 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2270 ua
= get_unaligned_address (operands
[1]);
2272 seq
= gen_unaligned_loadqi (subtarget
, ua
, temp1
, temp2
);
2274 seq
= gen_unaligned_loadhi (subtarget
, ua
, temp1
, temp2
);
2276 alpha_set_memflags (seq
, operands
[1]);
2280 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2285 if (any_memory_operand (operands
[0], mode
))
2287 if (aligned_memory_operand (operands
[0], mode
))
2289 rtx aligned_mem
, bitnum
;
2290 rtx temp1
= gen_reg_rtx (SImode
);
2291 rtx temp2
= gen_reg_rtx (SImode
);
2293 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2295 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2300 rtx temp1
= gen_reg_rtx (DImode
);
2301 rtx temp2
= gen_reg_rtx (DImode
);
2302 rtx temp3
= gen_reg_rtx (DImode
);
2303 rtx ua
= get_unaligned_address (operands
[0]);
2306 seq
= gen_unaligned_storeqi (ua
, operands
[1], temp1
, temp2
, temp3
);
2308 seq
= gen_unaligned_storehi (ua
, operands
[1], temp1
, temp2
, temp3
);
2310 alpha_set_memflags (seq
, operands
[0]);
2319 /* Implement the movmisalign patterns. One of the operands is a memory
2320 that is not naturally aligned. Emit instructions to load it. */
2323 alpha_expand_movmisalign (enum machine_mode mode
, rtx
*operands
)
2325 /* Honor misaligned loads, for those we promised to do so. */
2326 if (MEM_P (operands
[1]))
2330 if (register_operand (operands
[0], mode
))
2333 tmp
= gen_reg_rtx (mode
);
2335 alpha_expand_unaligned_load (tmp
, operands
[1], 8, 0, 0);
2336 if (tmp
!= operands
[0])
2337 emit_move_insn (operands
[0], tmp
);
2339 else if (MEM_P (operands
[0]))
2341 if (!reg_or_0_operand (operands
[1], mode
))
2342 operands
[1] = force_reg (mode
, operands
[1]);
2343 alpha_expand_unaligned_store (operands
[0], operands
[1], 8, 0);
2349 /* Generate an unsigned DImode to FP conversion. This is the same code
2350 optabs would emit if we didn't have TFmode patterns.
2352 For SFmode, this is the only construction I've found that can pass
2353 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2354 intermediates will work, because you'll get intermediate rounding
2355 that ruins the end result. Some of this could be fixed by turning
2356 on round-to-positive-infinity, but that requires diddling the fpsr,
2357 which kills performance. I tried turning this around and converting
2358 to a negative number, so that I could turn on /m, but either I did
2359 it wrong or there's something else cause I wound up with the exact
2360 same single-bit error. There is a branch-less form of this same code:
2371 fcmoveq $f10,$f11,$f0
2373 I'm not using it because it's the same number of instructions as
2374 this branch-full form, and it has more serialized long latency
2375 instructions on the critical path.
2377 For DFmode, we can avoid rounding errors by breaking up the word
2378 into two pieces, converting them separately, and adding them back:
2380 LC0: .long 0,0x5f800000
2385 cpyse $f11,$f31,$f10
2386 cpyse $f31,$f11,$f11
2394 This doesn't seem to be a clear-cut win over the optabs form.
2395 It probably all depends on the distribution of numbers being
2396 converted -- in the optabs form, all but high-bit-set has a
2397 much lower minimum execution time. */
2400 alpha_emit_floatuns (rtx operands
[2])
2402 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2403 enum machine_mode mode
;
2406 in
= force_reg (DImode
, operands
[1]);
2407 mode
= GET_MODE (out
);
2408 neglab
= gen_label_rtx ();
2409 donelab
= gen_label_rtx ();
2410 i0
= gen_reg_rtx (DImode
);
2411 i1
= gen_reg_rtx (DImode
);
2412 f0
= gen_reg_rtx (mode
);
2414 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2416 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2417 emit_jump_insn (gen_jump (donelab
));
2420 emit_label (neglab
);
2422 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2423 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2424 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2425 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2426 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2428 emit_label (donelab
);
2431 /* Generate the comparison for a conditional branch. */
2434 alpha_emit_conditional_branch (rtx operands
[], enum machine_mode cmp_mode
)
2436 enum rtx_code cmp_code
, branch_code
;
2437 enum machine_mode branch_mode
= VOIDmode
;
2438 enum rtx_code code
= GET_CODE (operands
[0]);
2439 rtx op0
= operands
[1], op1
= operands
[2];
2442 if (cmp_mode
== TFmode
)
2444 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2449 /* The general case: fold the comparison code to the types of compares
2450 that we have, choosing the branch as necessary. */
2453 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2455 /* We have these compares: */
2456 cmp_code
= code
, branch_code
= NE
;
2461 /* These must be reversed. */
2462 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2465 case GE
: case GT
: case GEU
: case GTU
:
2466 /* For FP, we swap them, for INT, we reverse them. */
2467 if (cmp_mode
== DFmode
)
2469 cmp_code
= swap_condition (code
);
2471 tem
= op0
, op0
= op1
, op1
= tem
;
2475 cmp_code
= reverse_condition (code
);
2484 if (cmp_mode
== DFmode
)
2486 if (flag_unsafe_math_optimizations
&& cmp_code
!= UNORDERED
)
2488 /* When we are not as concerned about non-finite values, and we
2489 are comparing against zero, we can branch directly. */
2490 if (op1
== CONST0_RTX (DFmode
))
2491 cmp_code
= UNKNOWN
, branch_code
= code
;
2492 else if (op0
== CONST0_RTX (DFmode
))
2494 /* Undo the swap we probably did just above. */
2495 tem
= op0
, op0
= op1
, op1
= tem
;
2496 branch_code
= swap_condition (cmp_code
);
2502 /* ??? We mark the branch mode to be CCmode to prevent the
2503 compare and branch from being combined, since the compare
2504 insn follows IEEE rules that the branch does not. */
2505 branch_mode
= CCmode
;
2510 /* The following optimizations are only for signed compares. */
2511 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2513 /* Whee. Compare and branch against 0 directly. */
2514 if (op1
== const0_rtx
)
2515 cmp_code
= UNKNOWN
, branch_code
= code
;
2517 /* If the constants doesn't fit into an immediate, but can
2518 be generated by lda/ldah, we adjust the argument and
2519 compare against zero, so we can use beq/bne directly. */
2520 /* ??? Don't do this when comparing against symbols, otherwise
2521 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2522 be declared false out of hand (at least for non-weak). */
2523 else if (CONST_INT_P (op1
)
2524 && (code
== EQ
|| code
== NE
)
2525 && !(symbolic_operand (op0
, VOIDmode
)
2526 || (REG_P (op0
) && REG_POINTER (op0
))))
2528 rtx n_op1
= GEN_INT (-INTVAL (op1
));
2530 if (! satisfies_constraint_I (op1
)
2531 && (satisfies_constraint_K (n_op1
)
2532 || satisfies_constraint_L (n_op1
)))
2533 cmp_code
= PLUS
, branch_code
= code
, op1
= n_op1
;
2537 if (!reg_or_0_operand (op0
, DImode
))
2538 op0
= force_reg (DImode
, op0
);
2539 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2540 op1
= force_reg (DImode
, op1
);
2543 /* Emit an initial compare instruction, if necessary. */
2545 if (cmp_code
!= UNKNOWN
)
2547 tem
= gen_reg_rtx (cmp_mode
);
2548 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2551 /* Emit the branch instruction. */
2552 tem
= gen_rtx_SET (VOIDmode
, pc_rtx
,
2553 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2554 gen_rtx_fmt_ee (branch_code
,
2556 CONST0_RTX (cmp_mode
)),
2557 gen_rtx_LABEL_REF (VOIDmode
,
2560 emit_jump_insn (tem
);
2563 /* Certain simplifications can be done to make invalid setcc operations
2564 valid. Return the final comparison, or NULL if we can't work. */
2567 alpha_emit_setcc (rtx operands
[], enum machine_mode cmp_mode
)
2569 enum rtx_code cmp_code
;
2570 enum rtx_code code
= GET_CODE (operands
[1]);
2571 rtx op0
= operands
[2], op1
= operands
[3];
2574 if (cmp_mode
== TFmode
)
2576 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2581 if (cmp_mode
== DFmode
&& !TARGET_FIX
)
2584 /* The general case: fold the comparison code to the types of compares
2585 that we have, choosing the branch as necessary. */
2590 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2592 /* We have these compares. */
2593 if (cmp_mode
== DFmode
)
2594 cmp_code
= code
, code
= NE
;
2598 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2603 cmp_code
= reverse_condition (code
);
2607 case GE
: case GT
: case GEU
: case GTU
:
2608 /* These normally need swapping, but for integer zero we have
2609 special patterns that recognize swapped operands. */
2610 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2612 code
= swap_condition (code
);
2613 if (cmp_mode
== DFmode
)
2614 cmp_code
= code
, code
= NE
;
2615 tmp
= op0
, op0
= op1
, op1
= tmp
;
2622 if (cmp_mode
== DImode
)
2624 if (!register_operand (op0
, DImode
))
2625 op0
= force_reg (DImode
, op0
);
2626 if (!reg_or_8bit_operand (op1
, DImode
))
2627 op1
= force_reg (DImode
, op1
);
2630 /* Emit an initial compare instruction, if necessary. */
2631 if (cmp_code
!= UNKNOWN
)
2633 tmp
= gen_reg_rtx (cmp_mode
);
2634 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
2635 gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
)));
2637 op0
= cmp_mode
!= DImode
? gen_lowpart (DImode
, tmp
) : tmp
;
2641 /* Emit the setcc instruction. */
2642 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2643 gen_rtx_fmt_ee (code
, DImode
, op0
, op1
)));
2648 /* Rewrite a comparison against zero CMP of the form
2649 (CODE (cc0) (const_int 0)) so it can be written validly in
2650 a conditional move (if_then_else CMP ...).
2651 If both of the operands that set cc0 are nonzero we must emit
2652 an insn to perform the compare (it can't be done within
2653 the conditional move). */
2656 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
2658 enum rtx_code code
= GET_CODE (cmp
);
2659 enum rtx_code cmov_code
= NE
;
2660 rtx op0
= XEXP (cmp
, 0);
2661 rtx op1
= XEXP (cmp
, 1);
2662 enum machine_mode cmp_mode
2663 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
2664 enum machine_mode cmov_mode
= VOIDmode
;
2665 int local_fast_math
= flag_unsafe_math_optimizations
;
2668 gcc_assert (cmp_mode
== DFmode
|| cmp_mode
== DImode
);
2670 if (FLOAT_MODE_P (cmp_mode
) != FLOAT_MODE_P (mode
))
2672 enum rtx_code cmp_code
;
2677 /* If we have fp<->int register move instructions, do a cmov by
2678 performing the comparison in fp registers, and move the
2679 zero/nonzero value to integer registers, where we can then
2680 use a normal cmov, or vice-versa. */
2684 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2685 /* We have these compares. */
2686 cmp_code
= code
, code
= NE
;
2690 /* This must be reversed. */
2691 cmp_code
= EQ
, code
= EQ
;
2694 case GE
: case GT
: case GEU
: case GTU
:
2695 /* These normally need swapping, but for integer zero we have
2696 special patterns that recognize swapped operands. */
2697 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2698 cmp_code
= code
, code
= NE
;
2701 cmp_code
= swap_condition (code
);
2703 tem
= op0
, op0
= op1
, op1
= tem
;
2711 tem
= gen_reg_rtx (cmp_mode
);
2712 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2713 gen_rtx_fmt_ee (cmp_code
, cmp_mode
,
2716 cmp_mode
= cmp_mode
== DImode
? DFmode
: DImode
;
2717 op0
= gen_lowpart (cmp_mode
, tem
);
2718 op1
= CONST0_RTX (cmp_mode
);
2719 local_fast_math
= 1;
2722 /* We may be able to use a conditional move directly.
2723 This avoids emitting spurious compares. */
2724 if (signed_comparison_operator (cmp
, VOIDmode
)
2725 && (cmp_mode
== DImode
|| local_fast_math
)
2726 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
2727 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2729 /* We can't put the comparison inside the conditional move;
2730 emit a compare instruction and put that inside the
2731 conditional move. Make sure we emit only comparisons we have;
2732 swap or reverse as necessary. */
2734 if (!can_create_pseudo_p ())
2739 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2740 /* We have these compares: */
2744 /* This must be reversed. */
2745 code
= reverse_condition (code
);
2749 case GE
: case GT
: case GEU
: case GTU
:
2750 /* These must be swapped. */
2751 if (op1
!= CONST0_RTX (cmp_mode
))
2753 code
= swap_condition (code
);
2754 tem
= op0
, op0
= op1
, op1
= tem
;
2762 if (cmp_mode
== DImode
)
2764 if (!reg_or_0_operand (op0
, DImode
))
2765 op0
= force_reg (DImode
, op0
);
2766 if (!reg_or_8bit_operand (op1
, DImode
))
2767 op1
= force_reg (DImode
, op1
);
2770 /* ??? We mark the branch mode to be CCmode to prevent the compare
2771 and cmov from being combined, since the compare insn follows IEEE
2772 rules that the cmov does not. */
2773 if (cmp_mode
== DFmode
&& !local_fast_math
)
2776 tem
= gen_reg_rtx (cmp_mode
);
2777 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_mode
, op0
, op1
));
2778 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_mode
));
2781 /* Simplify a conditional move of two constants into a setcc with
2782 arithmetic. This is done with a splitter since combine would
2783 just undo the work if done during code generation. It also catches
2784 cases we wouldn't have before cse. */
2787 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
2788 rtx t_rtx
, rtx f_rtx
)
2790 HOST_WIDE_INT t
, f
, diff
;
2791 enum machine_mode mode
;
2792 rtx target
, subtarget
, tmp
;
2794 mode
= GET_MODE (dest
);
2799 if (((code
== NE
|| code
== EQ
) && diff
< 0)
2800 || (code
== GE
|| code
== GT
))
2802 code
= reverse_condition (code
);
2803 diff
= t
, t
= f
, f
= diff
;
2807 subtarget
= target
= dest
;
2810 target
= gen_lowpart (DImode
, dest
);
2811 if (can_create_pseudo_p ())
2812 subtarget
= gen_reg_rtx (DImode
);
2816 /* Below, we must be careful to use copy_rtx on target and subtarget
2817 in intermediate insns, as they may be a subreg rtx, which may not
2820 if (f
== 0 && exact_log2 (diff
) > 0
2821 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2822 viable over a longer latency cmove. On EV5, the E0 slot is a
2823 scarce resource, and on EV4 shift has the same latency as a cmove. */
2824 && (diff
<= 8 || alpha_tune
== PROCESSOR_EV6
))
2826 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2827 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2829 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
2830 GEN_INT (exact_log2 (t
)));
2831 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2833 else if (f
== 0 && t
== -1)
2835 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2836 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2838 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
2840 else if (diff
== 1 || diff
== 4 || diff
== 8)
2844 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2845 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2848 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
2851 add_op
= GEN_INT (f
);
2852 if (sext_add_operand (add_op
, mode
))
2854 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
2856 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
2857 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2869 /* Look up the function X_floating library function name for the
2872 struct GTY(()) xfloating_op
2874 const enum rtx_code code
;
2875 const char *const GTY((skip
)) osf_func
;
2876 const char *const GTY((skip
)) vms_func
;
2880 static GTY(()) struct xfloating_op xfloating_ops
[] =
2882 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
2883 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
2884 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
2885 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
2886 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
2887 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
2888 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
2889 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
2890 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
2891 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
2892 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2893 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
2894 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2895 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2896 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2899 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
2901 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2902 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2906 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
2908 struct xfloating_op
*ops
= xfloating_ops
;
2909 long n
= ARRAY_SIZE (xfloating_ops
);
2912 gcc_assert (TARGET_HAS_XFLOATING_LIBS
);
2914 /* How irritating. Nothing to key off for the main table. */
2915 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
2918 n
= ARRAY_SIZE (vax_cvt_ops
);
2921 for (i
= 0; i
< n
; ++i
, ++ops
)
2922 if (ops
->code
== code
)
2924 rtx func
= ops
->libcall
;
2927 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
2928 ? ops
->vms_func
: ops
->osf_func
);
2929 ops
->libcall
= func
;
2937 /* Most X_floating operations take the rounding mode as an argument.
2938 Compute that here. */
2941 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
2942 enum alpha_fp_rounding_mode round
)
2948 case ALPHA_FPRM_NORM
:
2951 case ALPHA_FPRM_MINF
:
2954 case ALPHA_FPRM_CHOP
:
2957 case ALPHA_FPRM_DYN
:
2963 /* XXX For reference, round to +inf is mode = 3. */
2966 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
2972 /* Emit an X_floating library function call.
2974 Note that these functions do not follow normal calling conventions:
2975 TFmode arguments are passed in two integer registers (as opposed to
2976 indirect); TFmode return values appear in R16+R17.
2978 FUNC is the function to call.
2979 TARGET is where the output belongs.
2980 OPERANDS are the inputs.
2981 NOPERANDS is the count of inputs.
2982 EQUIV is the expression equivalent for the function.
2986 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
2987 int noperands
, rtx equiv
)
2989 rtx usage
= NULL_RTX
, tmp
, reg
;
2994 for (i
= 0; i
< noperands
; ++i
)
2996 switch (GET_MODE (operands
[i
]))
2999 reg
= gen_rtx_REG (TFmode
, regno
);
3004 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3009 gcc_assert (CONST_INT_P (operands
[i
]));
3012 reg
= gen_rtx_REG (DImode
, regno
);
3020 emit_move_insn (reg
, operands
[i
]);
3021 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3024 switch (GET_MODE (target
))
3027 reg
= gen_rtx_REG (TFmode
, 16);
3030 reg
= gen_rtx_REG (DFmode
, 32);
3033 reg
= gen_rtx_REG (DImode
, 0);
3039 tmp
= gen_rtx_MEM (QImode
, func
);
3040 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3041 const0_rtx
, const0_rtx
));
3042 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3043 RTL_CONST_CALL_P (tmp
) = 1;
3048 emit_libcall_block (tmp
, target
, reg
, equiv
);
3051 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3054 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3058 rtx out_operands
[3];
3060 func
= alpha_lookup_xfloating_lib_func (code
);
3061 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3063 out_operands
[0] = operands
[1];
3064 out_operands
[1] = operands
[2];
3065 out_operands
[2] = GEN_INT (mode
);
3066 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3067 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3071 /* Emit an X_floating library function call for a comparison. */
3074 alpha_emit_xfloating_compare (enum rtx_code
*pcode
, rtx op0
, rtx op1
)
3076 enum rtx_code cmp_code
, res_code
;
3077 rtx func
, out
, operands
[2], note
;
3079 /* X_floating library comparison functions return
3083 Convert the compare against the raw return value. */
3111 func
= alpha_lookup_xfloating_lib_func (cmp_code
);
3115 out
= gen_reg_rtx (DImode
);
3117 /* What's actually returned is -1,0,1, not a proper boolean value,
3118 so use an EXPR_LIST as with a generic libcall instead of a
3119 comparison type expression. */
3120 note
= gen_rtx_EXPR_LIST (VOIDmode
, op1
, NULL_RTX
);
3121 note
= gen_rtx_EXPR_LIST (VOIDmode
, op0
, note
);
3122 note
= gen_rtx_EXPR_LIST (VOIDmode
, func
, note
);
3123 alpha_emit_xfloating_libcall (func
, out
, operands
, 2, note
);
3128 /* Emit an X_floating library function call for a conversion. */
3131 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3133 int noperands
= 1, mode
;
3134 rtx out_operands
[2];
3136 enum rtx_code code
= orig_code
;
3138 if (code
== UNSIGNED_FIX
)
3141 func
= alpha_lookup_xfloating_lib_func (code
);
3143 out_operands
[0] = operands
[1];
3148 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3149 out_operands
[1] = GEN_INT (mode
);
3152 case FLOAT_TRUNCATE
:
3153 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3154 out_operands
[1] = GEN_INT (mode
);
3161 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3162 gen_rtx_fmt_e (orig_code
,
3163 GET_MODE (operands
[0]),
3167 /* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of
3168 DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true,
3169 guarantee that the sequence
3172 is valid. Naturally, output operand ordering is little-endian.
3173 This is used by *movtf_internal and *movti_internal. */
3176 alpha_split_tmode_pair (rtx operands
[4], enum machine_mode mode
,
3179 switch (GET_CODE (operands
[1]))
3182 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3183 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3187 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3188 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3193 gcc_assert (operands
[1] == CONST0_RTX (mode
));
3194 operands
[2] = operands
[3] = const0_rtx
;
3201 switch (GET_CODE (operands
[0]))
3204 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3205 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3209 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3210 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3217 if (fixup_overlap
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
3220 tmp
= operands
[0], operands
[0] = operands
[1], operands
[1] = tmp
;
3221 tmp
= operands
[2], operands
[2] = operands
[3], operands
[3] = tmp
;
3225 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3226 op2 is a register containing the sign bit, operation is the
3227 logical operation to be performed. */
3230 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3232 rtx high_bit
= operands
[2];
3236 alpha_split_tmode_pair (operands
, TFmode
, false);
3238 /* Detect three flavors of operand overlap. */
3240 if (rtx_equal_p (operands
[0], operands
[2]))
3242 else if (rtx_equal_p (operands
[1], operands
[2]))
3244 if (rtx_equal_p (operands
[0], high_bit
))
3251 emit_move_insn (operands
[0], operands
[2]);
3253 /* ??? If the destination overlaps both source tf and high_bit, then
3254 assume source tf is dead in its entirety and use the other half
3255 for a scratch register. Otherwise "scratch" is just the proper
3256 destination register. */
3257 scratch
= operands
[move
< 2 ? 1 : 3];
3259 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3263 emit_move_insn (operands
[0], operands
[2]);
3265 emit_move_insn (operands
[1], scratch
);
3269 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3273 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3274 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3275 lda r3,X(r11) lda r3,X+2(r11)
3276 extwl r1,r3,r1 extql r1,r3,r1
3277 extwh r2,r3,r2 extqh r2,r3,r2
3278 or r1.r2.r1 or r1,r2,r1
3281 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3282 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3283 lda r3,X(r11) lda r3,X(r11)
3284 extll r1,r3,r1 extll r1,r3,r1
3285 extlh r2,r3,r2 extlh r2,r3,r2
3286 or r1.r2.r1 addl r1,r2,r1
3288 quad: ldq_u r1,X(r11)
3297 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3298 HOST_WIDE_INT ofs
, int sign
)
3300 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3301 enum machine_mode mode
;
3303 if (TARGET_BWX
&& size
== 2)
3305 meml
= adjust_address (mem
, QImode
, ofs
);
3306 memh
= adjust_address (mem
, QImode
, ofs
+1);
3307 if (BYTES_BIG_ENDIAN
)
3308 tmp
= meml
, meml
= memh
, memh
= tmp
;
3309 extl
= gen_reg_rtx (DImode
);
3310 exth
= gen_reg_rtx (DImode
);
3311 emit_insn (gen_zero_extendqidi2 (extl
, meml
));
3312 emit_insn (gen_zero_extendqidi2 (exth
, memh
));
3313 exth
= expand_simple_binop (DImode
, ASHIFT
, exth
, GEN_INT (8),
3314 NULL
, 1, OPTAB_LIB_WIDEN
);
3315 addr
= expand_simple_binop (DImode
, IOR
, extl
, exth
,
3316 NULL
, 1, OPTAB_LIB_WIDEN
);
3318 if (sign
&& GET_MODE (tgt
) != HImode
)
3320 addr
= gen_lowpart (HImode
, addr
);
3321 emit_insn (gen_extend_insn (tgt
, addr
, GET_MODE (tgt
), HImode
, 0));
3325 if (GET_MODE (tgt
) != DImode
)
3326 addr
= gen_lowpart (GET_MODE (tgt
), addr
);
3327 emit_move_insn (tgt
, addr
);
3332 meml
= gen_reg_rtx (DImode
);
3333 memh
= gen_reg_rtx (DImode
);
3334 addr
= gen_reg_rtx (DImode
);
3335 extl
= gen_reg_rtx (DImode
);
3336 exth
= gen_reg_rtx (DImode
);
3338 mema
= XEXP (mem
, 0);
3339 if (GET_CODE (mema
) == LO_SUM
)
3340 mema
= force_reg (Pmode
, mema
);
3342 /* AND addresses cannot be in any alias set, since they may implicitly
3343 alias surrounding code. Ideally we'd have some alias set that
3344 covered all types except those with alignment 8 or higher. */
3346 tmp
= change_address (mem
, DImode
,
3347 gen_rtx_AND (DImode
,
3348 plus_constant (mema
, ofs
),
3350 set_mem_alias_set (tmp
, 0);
3351 emit_move_insn (meml
, tmp
);
3353 tmp
= change_address (mem
, DImode
,
3354 gen_rtx_AND (DImode
,
3355 plus_constant (mema
, ofs
+ size
- 1),
3357 set_mem_alias_set (tmp
, 0);
3358 emit_move_insn (memh
, tmp
);
3360 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3362 emit_move_insn (addr
, plus_constant (mema
, -1));
3364 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3365 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3367 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3368 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3369 addr
, 1, OPTAB_WIDEN
);
3371 else if (sign
&& size
== 2)
3373 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3375 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3376 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3378 /* We must use tgt here for the target. Alpha-vms port fails if we use
3379 addr for the target, because addr is marked as a pointer and combine
3380 knows that pointers are always sign-extended 32-bit values. */
3381 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3382 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3383 addr
, 1, OPTAB_WIDEN
);
3387 if (WORDS_BIG_ENDIAN
)
3389 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3393 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3398 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3403 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3410 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3414 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3415 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3419 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3424 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3429 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3438 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3439 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3444 emit_move_insn (tgt
, gen_lowpart (GET_MODE (tgt
), addr
));
3447 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3450 alpha_expand_unaligned_store (rtx dst
, rtx src
,
3451 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
3453 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3455 if (TARGET_BWX
&& size
== 2)
3457 if (src
!= const0_rtx
)
3459 dstl
= gen_lowpart (QImode
, src
);
3460 dsth
= expand_simple_binop (DImode
, LSHIFTRT
, src
, GEN_INT (8),
3461 NULL
, 1, OPTAB_LIB_WIDEN
);
3462 dsth
= gen_lowpart (QImode
, dsth
);
3465 dstl
= dsth
= const0_rtx
;
3467 meml
= adjust_address (dst
, QImode
, ofs
);
3468 memh
= adjust_address (dst
, QImode
, ofs
+1);
3469 if (BYTES_BIG_ENDIAN
)
3470 addr
= meml
, meml
= memh
, memh
= addr
;
3472 emit_move_insn (meml
, dstl
);
3473 emit_move_insn (memh
, dsth
);
3477 dstl
= gen_reg_rtx (DImode
);
3478 dsth
= gen_reg_rtx (DImode
);
3479 insl
= gen_reg_rtx (DImode
);
3480 insh
= gen_reg_rtx (DImode
);
3482 dsta
= XEXP (dst
, 0);
3483 if (GET_CODE (dsta
) == LO_SUM
)
3484 dsta
= force_reg (Pmode
, dsta
);
3486 /* AND addresses cannot be in any alias set, since they may implicitly
3487 alias surrounding code. Ideally we'd have some alias set that
3488 covered all types except those with alignment 8 or higher. */
3490 meml
= change_address (dst
, DImode
,
3491 gen_rtx_AND (DImode
,
3492 plus_constant (dsta
, ofs
),
3494 set_mem_alias_set (meml
, 0);
3496 memh
= change_address (dst
, DImode
,
3497 gen_rtx_AND (DImode
,
3498 plus_constant (dsta
, ofs
+ size
- 1),
3500 set_mem_alias_set (memh
, 0);
3502 emit_move_insn (dsth
, memh
);
3503 emit_move_insn (dstl
, meml
);
3504 if (WORDS_BIG_ENDIAN
)
3506 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3508 if (src
!= const0_rtx
)
3513 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3516 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3519 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3522 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3523 GEN_INT (size
*8), addr
));
3529 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3533 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3534 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3538 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
3542 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3546 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3548 if (src
!= CONST0_RTX (GET_MODE (src
)))
3550 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3551 GEN_INT (size
*8), addr
));
3556 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3559 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3562 emit_insn (gen_insql_le (insl
, gen_lowpart (DImode
, src
), addr
));
3567 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3572 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3576 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3577 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3581 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
3586 if (src
!= CONST0_RTX (GET_MODE (src
)))
3588 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3589 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3592 if (WORDS_BIG_ENDIAN
)
3594 emit_move_insn (meml
, dstl
);
3595 emit_move_insn (memh
, dsth
);
3599 /* Must store high before low for degenerate case of aligned. */
3600 emit_move_insn (memh
, dsth
);
3601 emit_move_insn (meml
, dstl
);
3605 /* The block move code tries to maximize speed by separating loads and
3606 stores at the expense of register pressure: we load all of the data
3607 before we store it back out. There are two secondary effects worth
3608 mentioning, that this speeds copying to/from aligned and unaligned
3609 buffers, and that it makes the code significantly easier to write. */
3611 #define MAX_MOVE_WORDS 8
3613 /* Load an integral number of consecutive unaligned quadwords. */
3616 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
3617 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3619 rtx
const im8
= GEN_INT (-8);
3620 rtx
const i64
= GEN_INT (64);
3621 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3622 rtx sreg
, areg
, tmp
, smema
;
3625 smema
= XEXP (smem
, 0);
3626 if (GET_CODE (smema
) == LO_SUM
)
3627 smema
= force_reg (Pmode
, smema
);
3629 /* Generate all the tmp registers we need. */
3630 for (i
= 0; i
< words
; ++i
)
3632 data_regs
[i
] = out_regs
[i
];
3633 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3635 data_regs
[words
] = gen_reg_rtx (DImode
);
3638 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3640 /* Load up all of the source data. */
3641 for (i
= 0; i
< words
; ++i
)
3643 tmp
= change_address (smem
, DImode
,
3644 gen_rtx_AND (DImode
,
3645 plus_constant (smema
, 8*i
),
3647 set_mem_alias_set (tmp
, 0);
3648 emit_move_insn (data_regs
[i
], tmp
);
3651 tmp
= change_address (smem
, DImode
,
3652 gen_rtx_AND (DImode
,
3653 plus_constant (smema
, 8*words
- 1),
3655 set_mem_alias_set (tmp
, 0);
3656 emit_move_insn (data_regs
[words
], tmp
);
3658 /* Extract the half-word fragments. Unfortunately DEC decided to make
3659 extxh with offset zero a noop instead of zeroing the register, so
3660 we must take care of that edge condition ourselves with cmov. */
3662 sreg
= copy_addr_to_reg (smema
);
3663 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3665 if (WORDS_BIG_ENDIAN
)
3666 emit_move_insn (sreg
, plus_constant (sreg
, 7));
3667 for (i
= 0; i
< words
; ++i
)
3669 if (WORDS_BIG_ENDIAN
)
3671 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
3672 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
3676 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
3677 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3679 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3680 gen_rtx_IF_THEN_ELSE (DImode
,
3681 gen_rtx_EQ (DImode
, areg
,
3683 const0_rtx
, ext_tmps
[i
])));
3686 /* Merge the half-words into whole words. */
3687 for (i
= 0; i
< words
; ++i
)
3689 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3690 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
3694 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3695 may be NULL to store zeros. */
3698 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
3699 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3701 rtx
const im8
= GEN_INT (-8);
3702 rtx
const i64
= GEN_INT (64);
3703 rtx ins_tmps
[MAX_MOVE_WORDS
];
3704 rtx st_tmp_1
, st_tmp_2
, dreg
;
3705 rtx st_addr_1
, st_addr_2
, dmema
;
3708 dmema
= XEXP (dmem
, 0);
3709 if (GET_CODE (dmema
) == LO_SUM
)
3710 dmema
= force_reg (Pmode
, dmema
);
3712 /* Generate all the tmp registers we need. */
3713 if (data_regs
!= NULL
)
3714 for (i
= 0; i
< words
; ++i
)
3715 ins_tmps
[i
] = gen_reg_rtx(DImode
);
3716 st_tmp_1
= gen_reg_rtx(DImode
);
3717 st_tmp_2
= gen_reg_rtx(DImode
);
3720 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
3722 st_addr_2
= change_address (dmem
, DImode
,
3723 gen_rtx_AND (DImode
,
3724 plus_constant (dmema
, words
*8 - 1),
3726 set_mem_alias_set (st_addr_2
, 0);
3728 st_addr_1
= change_address (dmem
, DImode
,
3729 gen_rtx_AND (DImode
, dmema
, im8
));
3730 set_mem_alias_set (st_addr_1
, 0);
3732 /* Load up the destination end bits. */
3733 emit_move_insn (st_tmp_2
, st_addr_2
);
3734 emit_move_insn (st_tmp_1
, st_addr_1
);
3736 /* Shift the input data into place. */
3737 dreg
= copy_addr_to_reg (dmema
);
3738 if (WORDS_BIG_ENDIAN
)
3739 emit_move_insn (dreg
, plus_constant (dreg
, 7));
3740 if (data_regs
!= NULL
)
3742 for (i
= words
-1; i
>= 0; --i
)
3744 if (WORDS_BIG_ENDIAN
)
3746 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
3747 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
3751 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
3752 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
3755 for (i
= words
-1; i
> 0; --i
)
3757 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3758 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
3763 /* Split and merge the ends with the destination data. */
3764 if (WORDS_BIG_ENDIAN
)
3766 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
3767 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
3771 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
3772 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
3775 if (data_regs
!= NULL
)
3777 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
3778 st_tmp_2
, 1, OPTAB_WIDEN
);
3779 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
3780 st_tmp_1
, 1, OPTAB_WIDEN
);
3784 if (WORDS_BIG_ENDIAN
)
3785 emit_move_insn (st_addr_1
, st_tmp_1
);
3787 emit_move_insn (st_addr_2
, st_tmp_2
);
3788 for (i
= words
-1; i
> 0; --i
)
3790 rtx tmp
= change_address (dmem
, DImode
,
3791 gen_rtx_AND (DImode
,
3792 plus_constant(dmema
,
3793 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
3795 set_mem_alias_set (tmp
, 0);
3796 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
3798 if (WORDS_BIG_ENDIAN
)
3799 emit_move_insn (st_addr_2
, st_tmp_2
);
3801 emit_move_insn (st_addr_1
, st_tmp_1
);
3805 /* Expand string/block move operations.
3807 operands[0] is the pointer to the destination.
3808 operands[1] is the pointer to the source.
3809 operands[2] is the number of bytes to move.
3810 operands[3] is the alignment. */
3813 alpha_expand_block_move (rtx operands
[])
3815 rtx bytes_rtx
= operands
[2];
3816 rtx align_rtx
= operands
[3];
3817 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3818 HOST_WIDE_INT bytes
= orig_bytes
;
3819 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3820 HOST_WIDE_INT dst_align
= src_align
;
3821 rtx orig_src
= operands
[1];
3822 rtx orig_dst
= operands
[0];
3823 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
3825 unsigned int i
, words
, ofs
, nregs
= 0;
3827 if (orig_bytes
<= 0)
3829 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3832 /* Look for additional alignment information from recorded register info. */
3834 tmp
= XEXP (orig_src
, 0);
3836 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3837 else if (GET_CODE (tmp
) == PLUS
3838 && REG_P (XEXP (tmp
, 0))
3839 && CONST_INT_P (XEXP (tmp
, 1)))
3841 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3842 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3846 if (a
>= 64 && c
% 8 == 0)
3848 else if (a
>= 32 && c
% 4 == 0)
3850 else if (a
>= 16 && c
% 2 == 0)
3855 tmp
= XEXP (orig_dst
, 0);
3857 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3858 else if (GET_CODE (tmp
) == PLUS
3859 && REG_P (XEXP (tmp
, 0))
3860 && CONST_INT_P (XEXP (tmp
, 1)))
3862 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3863 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3867 if (a
>= 64 && c
% 8 == 0)
3869 else if (a
>= 32 && c
% 4 == 0)
3871 else if (a
>= 16 && c
% 2 == 0)
3877 if (src_align
>= 64 && bytes
>= 8)
3881 for (i
= 0; i
< words
; ++i
)
3882 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3884 for (i
= 0; i
< words
; ++i
)
3885 emit_move_insn (data_regs
[nregs
+ i
],
3886 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
3893 if (src_align
>= 32 && bytes
>= 4)
3897 for (i
= 0; i
< words
; ++i
)
3898 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
3900 for (i
= 0; i
< words
; ++i
)
3901 emit_move_insn (data_regs
[nregs
+ i
],
3902 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
3913 for (i
= 0; i
< words
+1; ++i
)
3914 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3916 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
3924 if (! TARGET_BWX
&& bytes
>= 4)
3926 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
3927 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
3934 if (src_align
>= 16)
3937 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3938 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
3941 } while (bytes
>= 2);
3943 else if (! TARGET_BWX
)
3945 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3946 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
3954 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
3955 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
3960 gcc_assert (nregs
<= ARRAY_SIZE (data_regs
));
3962 /* Now save it back out again. */
3966 /* Write out the data in whatever chunks reading the source allowed. */
3967 if (dst_align
>= 64)
3969 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3971 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
3978 if (dst_align
>= 32)
3980 /* If the source has remaining DImode regs, write them out in
3982 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3984 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
3985 NULL_RTX
, 1, OPTAB_WIDEN
);
3987 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
3988 gen_lowpart (SImode
, data_regs
[i
]));
3989 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
3990 gen_lowpart (SImode
, tmp
));
3995 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
3997 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4004 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4006 /* Write out a remaining block of words using unaligned methods. */
4008 for (words
= 1; i
+ words
< nregs
; words
++)
4009 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4013 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4015 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4022 /* Due to the above, this won't be aligned. */
4023 /* ??? If we have more than one of these, consider constructing full
4024 words in registers and using alpha_expand_unaligned_store_words. */
4025 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4027 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4032 if (dst_align
>= 16)
4033 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4035 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4040 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4042 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4047 /* The remainder must be byte copies. */
4050 gcc_assert (GET_MODE (data_regs
[i
]) == QImode
);
4051 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4060 alpha_expand_block_clear (rtx operands
[])
4062 rtx bytes_rtx
= operands
[1];
4063 rtx align_rtx
= operands
[3];
4064 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4065 HOST_WIDE_INT bytes
= orig_bytes
;
4066 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4067 HOST_WIDE_INT alignofs
= 0;
4068 rtx orig_dst
= operands
[0];
4070 int i
, words
, ofs
= 0;
4072 if (orig_bytes
<= 0)
4074 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4077 /* Look for stricter alignment. */
4078 tmp
= XEXP (orig_dst
, 0);
4080 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4081 else if (GET_CODE (tmp
) == PLUS
4082 && REG_P (XEXP (tmp
, 0))
4083 && CONST_INT_P (XEXP (tmp
, 1)))
4085 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4086 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4091 align
= a
, alignofs
= 8 - c
% 8;
4093 align
= a
, alignofs
= 4 - c
% 4;
4095 align
= a
, alignofs
= 2 - c
% 2;
4099 /* Handle an unaligned prefix first. */
4103 #if HOST_BITS_PER_WIDE_INT >= 64
4104 /* Given that alignofs is bounded by align, the only time BWX could
4105 generate three stores is for a 7 byte fill. Prefer two individual
4106 stores over a load/mask/store sequence. */
4107 if ((!TARGET_BWX
|| alignofs
== 7)
4109 && !(alignofs
== 4 && bytes
>= 4))
4111 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4112 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4116 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4117 set_mem_alias_set (mem
, 0);
4119 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4120 if (bytes
< alignofs
)
4122 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4133 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4134 NULL_RTX
, 1, OPTAB_WIDEN
);
4136 emit_move_insn (mem
, tmp
);
4140 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4142 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4147 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4149 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4154 if (alignofs
== 4 && bytes
>= 4)
4156 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4162 /* If we've not used the extra lead alignment information by now,
4163 we won't be able to. Downgrade align to match what's left over. */
4166 alignofs
= alignofs
& -alignofs
;
4167 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4171 /* Handle a block of contiguous long-words. */
4173 if (align
>= 64 && bytes
>= 8)
4177 for (i
= 0; i
< words
; ++i
)
4178 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4185 /* If the block is large and appropriately aligned, emit a single
4186 store followed by a sequence of stq_u insns. */
4188 if (align
>= 32 && bytes
> 16)
4192 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4196 orig_dsta
= XEXP (orig_dst
, 0);
4197 if (GET_CODE (orig_dsta
) == LO_SUM
)
4198 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4201 for (i
= 0; i
< words
; ++i
)
4204 = change_address (orig_dst
, DImode
,
4205 gen_rtx_AND (DImode
,
4206 plus_constant (orig_dsta
, ofs
+ i
*8),
4208 set_mem_alias_set (mem
, 0);
4209 emit_move_insn (mem
, const0_rtx
);
4212 /* Depending on the alignment, the first stq_u may have overlapped
4213 with the initial stl, which means that the last stq_u didn't
4214 write as much as it would appear. Leave those questionable bytes
4216 bytes
-= words
* 8 - 4;
4217 ofs
+= words
* 8 - 4;
4220 /* Handle a smaller block of aligned words. */
4222 if ((align
>= 64 && bytes
== 4)
4223 || (align
== 32 && bytes
>= 4))
4227 for (i
= 0; i
< words
; ++i
)
4228 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4235 /* An unaligned block uses stq_u stores for as many as possible. */
4241 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4247 /* Next clean up any trailing pieces. */
4249 #if HOST_BITS_PER_WIDE_INT >= 64
4250 /* Count the number of bits in BYTES for which aligned stores could
4253 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4257 /* If we have appropriate alignment (and it wouldn't take too many
4258 instructions otherwise), mask out the bytes we need. */
4259 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4266 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4267 set_mem_alias_set (mem
, 0);
4269 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4271 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4272 NULL_RTX
, 1, OPTAB_WIDEN
);
4274 emit_move_insn (mem
, tmp
);
4277 else if (align
>= 32 && bytes
< 4)
4282 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4283 set_mem_alias_set (mem
, 0);
4285 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4287 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4288 NULL_RTX
, 1, OPTAB_WIDEN
);
4290 emit_move_insn (mem
, tmp
);
4296 if (!TARGET_BWX
&& bytes
>= 4)
4298 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4308 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4312 } while (bytes
>= 2);
4314 else if (! TARGET_BWX
)
4316 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4324 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4332 /* Returns a mask so that zap(x, value) == x & mask. */
4335 alpha_expand_zap_mask (HOST_WIDE_INT value
)
4340 if (HOST_BITS_PER_WIDE_INT
>= 64)
4342 HOST_WIDE_INT mask
= 0;
4344 for (i
= 7; i
>= 0; --i
)
4347 if (!((value
>> i
) & 1))
4351 result
= gen_int_mode (mask
, DImode
);
4355 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
4357 gcc_assert (HOST_BITS_PER_WIDE_INT
== 32);
4359 for (i
= 7; i
>= 4; --i
)
4362 if (!((value
>> i
) & 1))
4366 for (i
= 3; i
>= 0; --i
)
4369 if (!((value
>> i
) & 1))
4373 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
4380 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
4381 enum machine_mode mode
,
4382 rtx op0
, rtx op1
, rtx op2
)
4384 op0
= gen_lowpart (mode
, op0
);
4386 if (op1
== const0_rtx
)
4387 op1
= CONST0_RTX (mode
);
4389 op1
= gen_lowpart (mode
, op1
);
4391 if (op2
== const0_rtx
)
4392 op2
= CONST0_RTX (mode
);
4394 op2
= gen_lowpart (mode
, op2
);
4396 emit_insn ((*gen
) (op0
, op1
, op2
));
4399 /* A subroutine of the atomic operation splitters. Jump to LABEL if
4400 COND is true. Mark the jump as unlikely to be taken. */
4403 emit_unlikely_jump (rtx cond
, rtx label
)
4405 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
4408 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
4409 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
4410 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
4413 /* A subroutine of the atomic operation splitters. Emit a load-locked
4414 instruction in MODE. */
4417 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
4419 rtx (*fn
) (rtx
, rtx
) = NULL
;
4421 fn
= gen_load_locked_si
;
4422 else if (mode
== DImode
)
4423 fn
= gen_load_locked_di
;
4424 emit_insn (fn (reg
, mem
));
4427 /* A subroutine of the atomic operation splitters. Emit a store-conditional
4428 instruction in MODE. */
4431 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
4433 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
4435 fn
= gen_store_conditional_si
;
4436 else if (mode
== DImode
)
4437 fn
= gen_store_conditional_di
;
4438 emit_insn (fn (res
, mem
, val
));
4441 /* A subroutine of the atomic operation splitters. Emit an insxl
4442 instruction in MODE. */
4445 emit_insxl (enum machine_mode mode
, rtx op1
, rtx op2
)
4447 rtx ret
= gen_reg_rtx (DImode
);
4448 rtx (*fn
) (rtx
, rtx
, rtx
);
4450 if (WORDS_BIG_ENDIAN
)
4464 /* The insbl and inswl patterns require a register operand. */
4465 op1
= force_reg (mode
, op1
);
4466 emit_insn (fn (ret
, op1
, op2
));
4471 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
4472 to perform. MEM is the memory on which to operate. VAL is the second
4473 operand of the binary operator. BEFORE and AFTER are optional locations to
4474 return the value of MEM either before of after the operation. SCRATCH is
4475 a scratch register. */
4478 alpha_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
4479 rtx before
, rtx after
, rtx scratch
)
4481 enum machine_mode mode
= GET_MODE (mem
);
4482 rtx label
, x
, cond
= gen_rtx_REG (DImode
, REGNO (scratch
));
4484 emit_insn (gen_memory_barrier ());
4486 label
= gen_label_rtx ();
4488 label
= gen_rtx_LABEL_REF (DImode
, label
);
4492 emit_load_locked (mode
, before
, mem
);
4496 x
= gen_rtx_AND (mode
, before
, val
);
4497 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
4499 x
= gen_rtx_NOT (mode
, val
);
4502 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
4504 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
4505 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
4507 emit_store_conditional (mode
, cond
, mem
, scratch
);
4509 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4510 emit_unlikely_jump (x
, label
);
4512 emit_insn (gen_memory_barrier ());
4515 /* Expand a compare and swap operation. */
4518 alpha_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
4521 enum machine_mode mode
= GET_MODE (mem
);
4522 rtx label1
, label2
, x
, cond
= gen_lowpart (DImode
, scratch
);
4524 emit_insn (gen_memory_barrier ());
4526 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4527 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4528 emit_label (XEXP (label1
, 0));
4530 emit_load_locked (mode
, retval
, mem
);
4532 x
= gen_lowpart (DImode
, retval
);
4533 if (oldval
== const0_rtx
)
4534 x
= gen_rtx_NE (DImode
, x
, const0_rtx
);
4537 x
= gen_rtx_EQ (DImode
, x
, oldval
);
4538 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4539 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4541 emit_unlikely_jump (x
, label2
);
4543 emit_move_insn (scratch
, newval
);
4544 emit_store_conditional (mode
, cond
, mem
, scratch
);
4546 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4547 emit_unlikely_jump (x
, label1
);
4549 emit_insn (gen_memory_barrier ());
4550 emit_label (XEXP (label2
, 0));
4554 alpha_expand_compare_and_swap_12 (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
4556 enum machine_mode mode
= GET_MODE (mem
);
4557 rtx addr
, align
, wdst
;
4558 rtx (*fn5
) (rtx
, rtx
, rtx
, rtx
, rtx
);
4560 addr
= force_reg (DImode
, XEXP (mem
, 0));
4561 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4562 NULL_RTX
, 1, OPTAB_DIRECT
);
4564 oldval
= convert_modes (DImode
, mode
, oldval
, 1);
4565 newval
= emit_insxl (mode
, newval
, addr
);
4567 wdst
= gen_reg_rtx (DImode
);
4569 fn5
= gen_sync_compare_and_swapqi_1
;
4571 fn5
= gen_sync_compare_and_swaphi_1
;
4572 emit_insn (fn5 (wdst
, addr
, oldval
, newval
, align
));
4574 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4578 alpha_split_compare_and_swap_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4579 rtx oldval
, rtx newval
, rtx align
,
4580 rtx scratch
, rtx cond
)
4582 rtx label1
, label2
, mem
, width
, mask
, x
;
4584 mem
= gen_rtx_MEM (DImode
, align
);
4585 MEM_VOLATILE_P (mem
) = 1;
4587 emit_insn (gen_memory_barrier ());
4588 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4589 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4590 emit_label (XEXP (label1
, 0));
4592 emit_load_locked (DImode
, scratch
, mem
);
4594 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4595 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4596 if (WORDS_BIG_ENDIAN
)
4597 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4599 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4601 if (oldval
== const0_rtx
)
4602 x
= gen_rtx_NE (DImode
, dest
, const0_rtx
);
4605 x
= gen_rtx_EQ (DImode
, dest
, oldval
);
4606 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4607 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4609 emit_unlikely_jump (x
, label2
);
4611 if (WORDS_BIG_ENDIAN
)
4612 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4614 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4615 emit_insn (gen_iordi3 (scratch
, scratch
, newval
));
4617 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4619 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4620 emit_unlikely_jump (x
, label1
);
4622 emit_insn (gen_memory_barrier ());
4623 emit_label (XEXP (label2
, 0));
4626 /* Expand an atomic exchange operation. */
4629 alpha_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
4631 enum machine_mode mode
= GET_MODE (mem
);
4632 rtx label
, x
, cond
= gen_lowpart (DImode
, scratch
);
4634 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4635 emit_label (XEXP (label
, 0));
4637 emit_load_locked (mode
, retval
, mem
);
4638 emit_move_insn (scratch
, val
);
4639 emit_store_conditional (mode
, cond
, mem
, scratch
);
4641 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4642 emit_unlikely_jump (x
, label
);
4644 emit_insn (gen_memory_barrier ());
4648 alpha_expand_lock_test_and_set_12 (rtx dst
, rtx mem
, rtx val
)
4650 enum machine_mode mode
= GET_MODE (mem
);
4651 rtx addr
, align
, wdst
;
4652 rtx (*fn4
) (rtx
, rtx
, rtx
, rtx
);
4654 /* Force the address into a register. */
4655 addr
= force_reg (DImode
, XEXP (mem
, 0));
4657 /* Align it to a multiple of 8. */
4658 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4659 NULL_RTX
, 1, OPTAB_DIRECT
);
4661 /* Insert val into the correct byte location within the word. */
4662 val
= emit_insxl (mode
, val
, addr
);
4664 wdst
= gen_reg_rtx (DImode
);
4666 fn4
= gen_sync_lock_test_and_setqi_1
;
4668 fn4
= gen_sync_lock_test_and_sethi_1
;
4669 emit_insn (fn4 (wdst
, addr
, val
, align
));
4671 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4675 alpha_split_lock_test_and_set_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4676 rtx val
, rtx align
, rtx scratch
)
4678 rtx label
, mem
, width
, mask
, x
;
4680 mem
= gen_rtx_MEM (DImode
, align
);
4681 MEM_VOLATILE_P (mem
) = 1;
4683 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4684 emit_label (XEXP (label
, 0));
4686 emit_load_locked (DImode
, scratch
, mem
);
4688 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4689 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4690 if (WORDS_BIG_ENDIAN
)
4692 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4693 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4697 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4698 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4700 emit_insn (gen_iordi3 (scratch
, scratch
, val
));
4702 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4704 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4705 emit_unlikely_jump (x
, label
);
4707 emit_insn (gen_memory_barrier ());
4710 /* Adjust the cost of a scheduling dependency. Return the new cost of
4711 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4714 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4716 enum attr_type insn_type
, dep_insn_type
;
4718 /* If the dependence is an anti-dependence, there is no cost. For an
4719 output dependence, there is sometimes a cost, but it doesn't seem
4720 worth handling those few cases. */
4721 if (REG_NOTE_KIND (link
) != 0)
4724 /* If we can't recognize the insns, we can't really do anything. */
4725 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4728 insn_type
= get_attr_type (insn
);
4729 dep_insn_type
= get_attr_type (dep_insn
);
4731 /* Bring in the user-defined memory latency. */
4732 if (dep_insn_type
== TYPE_ILD
4733 || dep_insn_type
== TYPE_FLD
4734 || dep_insn_type
== TYPE_LDSYM
)
4735 cost
+= alpha_memory_latency
-1;
4737 /* Everything else handled in DFA bypasses now. */
4742 /* The number of instructions that can be issued per cycle. */
4745 alpha_issue_rate (void)
4747 return (alpha_tune
== PROCESSOR_EV4
? 2 : 4);
4750 /* How many alternative schedules to try. This should be as wide as the
4751 scheduling freedom in the DFA, but no wider. Making this value too
4752 large results extra work for the scheduler.
4754 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4755 alternative schedules. For EV5, we can choose between E0/E1 and
4756 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4759 alpha_multipass_dfa_lookahead (void)
4761 return (alpha_tune
== PROCESSOR_EV6
? 4 : 2);
4764 /* Machine-specific function data. */
4766 struct GTY(()) machine_function
4769 /* List of call information words for calls from this function. */
4770 struct rtx_def
*first_ciw
;
4771 struct rtx_def
*last_ciw
;
4774 /* List of deferred case vectors. */
4775 struct rtx_def
*addr_list
;
4778 const char *some_ld_name
;
4780 /* For TARGET_LD_BUGGY_LDGP. */
4781 struct rtx_def
*gp_save_rtx
;
4784 /* How to allocate a 'struct machine_function'. */
4786 static struct machine_function
*
4787 alpha_init_machine_status (void)
4789 return ((struct machine_function
*)
4790 ggc_alloc_cleared (sizeof (struct machine_function
)));
4793 /* Functions to save and restore alpha_return_addr_rtx. */
4795 /* Start the ball rolling with RETURN_ADDR_RTX. */
4798 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
4803 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4806 /* Return or create a memory slot containing the gp value for the current
4807 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4810 alpha_gp_save_rtx (void)
4812 rtx seq
, m
= cfun
->machine
->gp_save_rtx
;
4818 m
= assign_stack_local (DImode
, UNITS_PER_WORD
, BITS_PER_WORD
);
4819 m
= validize_mem (m
);
4820 emit_move_insn (m
, pic_offset_table_rtx
);
4825 /* We used to simply emit the sequence after entry_of_function.
4826 However this breaks the CFG if the first instruction in the
4827 first block is not the NOTE_INSN_BASIC_BLOCK, for example a
4828 label. Emit the sequence properly on the edge. We are only
4829 invoked from dw2_build_landing_pads and finish_eh_generation
4830 will call commit_edge_insertions thanks to a kludge. */
4831 insert_insn_on_edge (seq
, single_succ_edge (ENTRY_BLOCK_PTR
));
4833 cfun
->machine
->gp_save_rtx
= m
;
4840 alpha_ra_ever_killed (void)
4844 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4845 return (int)df_regs_ever_live_p (REG_RA
);
4847 push_topmost_sequence ();
4849 pop_topmost_sequence ();
4851 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
4855 /* Return the trap mode suffix applicable to the current
4856 instruction, or NULL. */
4859 get_trap_mode_suffix (void)
4861 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
4865 case TRAP_SUFFIX_NONE
:
4868 case TRAP_SUFFIX_SU
:
4869 if (alpha_fptm
>= ALPHA_FPTM_SU
)
4873 case TRAP_SUFFIX_SUI
:
4874 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
4878 case TRAP_SUFFIX_V_SV
:
4886 case ALPHA_FPTM_SUI
:
4892 case TRAP_SUFFIX_V_SV_SVI
:
4901 case ALPHA_FPTM_SUI
:
4908 case TRAP_SUFFIX_U_SU_SUI
:
4917 case ALPHA_FPTM_SUI
:
4930 /* Return the rounding mode suffix applicable to the current
4931 instruction, or NULL. */
4934 get_round_mode_suffix (void)
4936 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
4940 case ROUND_SUFFIX_NONE
:
4942 case ROUND_SUFFIX_NORMAL
:
4945 case ALPHA_FPRM_NORM
:
4947 case ALPHA_FPRM_MINF
:
4949 case ALPHA_FPRM_CHOP
:
4951 case ALPHA_FPRM_DYN
:
4958 case ROUND_SUFFIX_C
:
4967 /* Locate some local-dynamic symbol still in use by this function
4968 so that we can print its name in some movdi_er_tlsldm pattern. */
4971 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4975 if (GET_CODE (x
) == SYMBOL_REF
4976 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4978 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4986 get_some_local_dynamic_name (void)
4990 if (cfun
->machine
->some_ld_name
)
4991 return cfun
->machine
->some_ld_name
;
4993 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4995 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4996 return cfun
->machine
->some_ld_name
;
5001 /* Print an operand. Recognize special options, documented below. */
5004 print_operand (FILE *file
, rtx x
, int code
)
5011 /* Print the assembler name of the current function. */
5012 assemble_name (file
, alpha_fnname
);
5016 assemble_name (file
, get_some_local_dynamic_name ());
5021 const char *trap
= get_trap_mode_suffix ();
5022 const char *round
= get_round_mode_suffix ();
5025 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5026 (trap
? trap
: ""), (round
? round
: ""));
5031 /* Generates single precision instruction suffix. */
5032 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5036 /* Generates double precision instruction suffix. */
5037 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5041 if (alpha_this_literal_sequence_number
== 0)
5042 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5043 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5047 if (alpha_this_gpdisp_sequence_number
== 0)
5048 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5049 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5053 if (GET_CODE (x
) == HIGH
)
5054 output_addr_const (file
, XEXP (x
, 0));
5056 output_operand_lossage ("invalid %%H value");
5063 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5065 x
= XVECEXP (x
, 0, 0);
5066 lituse
= "lituse_tlsgd";
5068 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5070 x
= XVECEXP (x
, 0, 0);
5071 lituse
= "lituse_tlsldm";
5073 else if (CONST_INT_P (x
))
5074 lituse
= "lituse_jsr";
5077 output_operand_lossage ("invalid %%J value");
5081 if (x
!= const0_rtx
)
5082 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5090 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5091 lituse
= "lituse_jsrdirect";
5093 lituse
= "lituse_jsr";
5096 gcc_assert (INTVAL (x
) != 0);
5097 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5101 /* If this operand is the constant zero, write it as "$31". */
5103 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5104 else if (x
== CONST0_RTX (GET_MODE (x
)))
5105 fprintf (file
, "$31");
5107 output_operand_lossage ("invalid %%r value");
5111 /* Similar, but for floating-point. */
5113 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5114 else if (x
== CONST0_RTX (GET_MODE (x
)))
5115 fprintf (file
, "$f31");
5117 output_operand_lossage ("invalid %%R value");
5121 /* Write the 1's complement of a constant. */
5122 if (!CONST_INT_P (x
))
5123 output_operand_lossage ("invalid %%N value");
5125 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5129 /* Write 1 << C, for a constant C. */
5130 if (!CONST_INT_P (x
))
5131 output_operand_lossage ("invalid %%P value");
5133 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5137 /* Write the high-order 16 bits of a constant, sign-extended. */
5138 if (!CONST_INT_P (x
))
5139 output_operand_lossage ("invalid %%h value");
5141 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5145 /* Write the low-order 16 bits of a constant, sign-extended. */
5146 if (!CONST_INT_P (x
))
5147 output_operand_lossage ("invalid %%L value");
5149 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5150 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5154 /* Write mask for ZAP insn. */
5155 if (GET_CODE (x
) == CONST_DOUBLE
)
5157 HOST_WIDE_INT mask
= 0;
5158 HOST_WIDE_INT value
;
5160 value
= CONST_DOUBLE_LOW (x
);
5161 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5166 value
= CONST_DOUBLE_HIGH (x
);
5167 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5170 mask
|= (1 << (i
+ sizeof (int)));
5172 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5175 else if (CONST_INT_P (x
))
5177 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5179 for (i
= 0; i
< 8; i
++, value
>>= 8)
5183 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5186 output_operand_lossage ("invalid %%m value");
5190 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5191 if (!CONST_INT_P (x
)
5192 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5193 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5194 output_operand_lossage ("invalid %%M value");
5196 fprintf (file
, "%s",
5197 (INTVAL (x
) == 8 ? "b"
5198 : INTVAL (x
) == 16 ? "w"
5199 : INTVAL (x
) == 32 ? "l"
5204 /* Similar, except do it from the mask. */
5205 if (CONST_INT_P (x
))
5207 HOST_WIDE_INT value
= INTVAL (x
);
5214 if (value
== 0xffff)
5219 if (value
== 0xffffffff)
5230 else if (HOST_BITS_PER_WIDE_INT
== 32
5231 && GET_CODE (x
) == CONST_DOUBLE
5232 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5233 && CONST_DOUBLE_HIGH (x
) == 0)
5238 output_operand_lossage ("invalid %%U value");
5242 /* Write the constant value divided by 8 for little-endian mode or
5243 (56 - value) / 8 for big-endian mode. */
5245 if (!CONST_INT_P (x
)
5246 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5249 || (INTVAL (x
) & 7) != 0)
5250 output_operand_lossage ("invalid %%s value");
5252 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5254 ? (56 - INTVAL (x
)) / 8
5259 /* Same, except compute (64 - c) / 8 */
5261 if (!CONST_INT_P (x
)
5262 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5263 && (INTVAL (x
) & 7) != 8)
5264 output_operand_lossage ("invalid %%s value");
5266 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5271 /* On Unicos/Mk systems: use a DEX expression if the symbol
5272 clashes with a register name. */
5273 int dex
= unicosmk_need_dex (x
);
5275 fprintf (file
, "DEX(%d)", dex
);
5277 output_addr_const (file
, x
);
5281 case 'C': case 'D': case 'c': case 'd':
5282 /* Write out comparison name. */
5284 enum rtx_code c
= GET_CODE (x
);
5286 if (!COMPARISON_P (x
))
5287 output_operand_lossage ("invalid %%C value");
5289 else if (code
== 'D')
5290 c
= reverse_condition (c
);
5291 else if (code
== 'c')
5292 c
= swap_condition (c
);
5293 else if (code
== 'd')
5294 c
= swap_condition (reverse_condition (c
));
5297 fprintf (file
, "ule");
5299 fprintf (file
, "ult");
5300 else if (c
== UNORDERED
)
5301 fprintf (file
, "un");
5303 fprintf (file
, "%s", GET_RTX_NAME (c
));
5308 /* Write the divide or modulus operator. */
5309 switch (GET_CODE (x
))
5312 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5315 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5318 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5321 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5324 output_operand_lossage ("invalid %%E value");
5330 /* Write "_u" for unaligned access. */
5331 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == AND
)
5332 fprintf (file
, "_u");
5337 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5339 output_address (XEXP (x
, 0));
5340 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5342 switch (XINT (XEXP (x
, 0), 1))
5346 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5349 output_operand_lossage ("unknown relocation unspec");
5354 output_addr_const (file
, x
);
5358 output_operand_lossage ("invalid %%xn code");
5363 print_operand_address (FILE *file
, rtx addr
)
5366 HOST_WIDE_INT offset
= 0;
5368 if (GET_CODE (addr
) == AND
)
5369 addr
= XEXP (addr
, 0);
5371 if (GET_CODE (addr
) == PLUS
5372 && CONST_INT_P (XEXP (addr
, 1)))
5374 offset
= INTVAL (XEXP (addr
, 1));
5375 addr
= XEXP (addr
, 0);
5378 if (GET_CODE (addr
) == LO_SUM
)
5380 const char *reloc16
, *reloclo
;
5381 rtx op1
= XEXP (addr
, 1);
5383 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5385 op1
= XEXP (op1
, 0);
5386 switch (XINT (op1
, 1))
5390 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5394 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5397 output_operand_lossage ("unknown relocation unspec");
5401 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5406 reloclo
= "gprellow";
5407 output_addr_const (file
, op1
);
5411 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5413 addr
= XEXP (addr
, 0);
5414 switch (GET_CODE (addr
))
5417 basereg
= REGNO (addr
);
5421 basereg
= subreg_regno (addr
);
5428 fprintf (file
, "($%d)\t\t!%s", basereg
,
5429 (basereg
== 29 ? reloc16
: reloclo
));
5433 switch (GET_CODE (addr
))
5436 basereg
= REGNO (addr
);
5440 basereg
= subreg_regno (addr
);
5444 offset
= INTVAL (addr
);
5447 #if TARGET_ABI_OPEN_VMS
5449 fprintf (file
, "%s", XSTR (addr
, 0));
5453 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
5454 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
);
5455 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5456 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5457 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5465 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5468 /* Emit RTL insns to initialize the variable parts of a trampoline at
5469 TRAMP. FNADDR is an RTX for the address of the function's pure
5470 code. CXT is an RTX for the static chain value for the function.
5472 The three offset parameters are for the individual template's
5473 layout. A JMPOFS < 0 indicates that the trampoline does not
5474 contain instructions at all.
5476 We assume here that a function will be called many more times than
5477 its address is taken (e.g., it might be passed to qsort), so we
5478 take the trouble to initialize the "hint" field in the JMP insn.
5479 Note that the hint field is PC (new) + 4 * bits 13:0. */
5482 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5483 int fnofs
, int cxtofs
, int jmpofs
)
5486 /* VMS really uses DImode pointers in memory at this point. */
5487 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5489 #ifdef POINTERS_EXTEND_UNSIGNED
5490 fnaddr
= convert_memory_address (mode
, fnaddr
);
5491 cxt
= convert_memory_address (mode
, cxt
);
5494 if (TARGET_ABI_OPEN_VMS
)
5500 /* Construct the name of the trampoline entry point. */
5501 fnname
= XSTR (fnaddr
, 0);
5502 trname
= (char *) alloca (strlen (fnname
) + 5);
5503 strcpy (trname
, fnname
);
5504 strcat (trname
, "..tr");
5505 traddr
= gen_rtx_SYMBOL_REF
5506 (mode
, ggc_alloc_string (trname
, strlen (trname
) + 1));
5508 /* Trampoline (or "bounded") procedure descriptor is constructed from
5509 the function's procedure descriptor with certain fields zeroed IAW
5510 the VMS calling standard. This is stored in the first quadword. */
5511 temp1
= force_reg (DImode
, gen_rtx_MEM (DImode
, fnaddr
));
5512 temp1
= expand_and (DImode
, temp1
,
5513 GEN_INT (0xffff0fff0000fff0), NULL_RTX
);
5514 addr
= memory_address (mode
, plus_constant (tramp
, 0));
5515 emit_move_insn (gen_rtx_MEM (DImode
, addr
), temp1
);
5517 /* Trampoline transfer address is stored in the second quadword
5518 of the trampoline. */
5519 addr
= memory_address (mode
, plus_constant (tramp
, 8));
5520 emit_move_insn (gen_rtx_MEM (mode
, addr
), traddr
);
5523 /* Store function address and CXT. */
5524 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5525 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5526 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5527 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5529 #ifdef ENABLE_EXECUTE_STACK
5530 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5531 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
5535 emit_insn (gen_imb ());
5538 /* Determine where to put an argument to a function.
5539 Value is zero to push the argument on the stack,
5540 or a hard register in which to store the argument.
5542 MODE is the argument's machine mode.
5543 TYPE is the data type of the argument (as a tree).
5544 This is null for libcalls where that information may
5546 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5547 the preceding args and about the function being called.
5548 NAMED is nonzero if this argument is a named parameter
5549 (otherwise it is an extra parameter matching an ellipsis).
5551 On Alpha the first 6 words of args are normally in registers
5552 and the rest are pushed. */
5555 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5556 int named ATTRIBUTE_UNUSED
)
5561 /* Don't get confused and pass small structures in FP registers. */
5562 if (type
&& AGGREGATE_TYPE_P (type
))
5566 #ifdef ENABLE_CHECKING
5567 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5569 gcc_assert (!COMPLEX_MODE_P (mode
));
5572 /* Set up defaults for FP operands passed in FP registers, and
5573 integral operands passed in integer registers. */
5574 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5580 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5581 the three platforms, so we can't avoid conditional compilation. */
5582 #if TARGET_ABI_OPEN_VMS
5584 if (mode
== VOIDmode
)
5585 return alpha_arg_info_reg_val (cum
);
5587 num_args
= cum
.num_args
;
5589 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5592 #elif TARGET_ABI_UNICOSMK
5596 /* If this is the last argument, generate the call info word (CIW). */
5597 /* ??? We don't include the caller's line number in the CIW because
5598 I don't know how to determine it if debug infos are turned off. */
5599 if (mode
== VOIDmode
)
5608 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5609 if (cum
.reg_args_type
[i
])
5610 lo
|= (1 << (7 - i
));
5612 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5615 lo
|= cum
.num_reg_words
;
5617 #if HOST_BITS_PER_WIDE_INT == 32
5618 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5620 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5621 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5624 ciw
= immed_double_const (lo
, hi
, DImode
);
5626 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5627 UNSPEC_UMK_LOAD_CIW
);
5630 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5631 num_args
= cum
.num_reg_words
;
5633 || cum
.num_reg_words
+ size
> 6
5634 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5636 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5640 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5641 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5643 /* The argument fits in two registers. Note that we still need to
5644 reserve a register for empty structures. */
5648 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5651 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5652 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5653 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5657 #elif TARGET_ABI_OSF
5663 /* VOID is passed as a special flag for "last argument". */
5664 if (type
== void_type_node
)
5666 else if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5670 #error Unhandled ABI
5673 return gen_rtx_REG (mode
, num_args
+ basereg
);
5677 alpha_arg_partial_bytes (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5678 enum machine_mode mode ATTRIBUTE_UNUSED
,
5679 tree type ATTRIBUTE_UNUSED
,
5680 bool named ATTRIBUTE_UNUSED
)
5684 #if TARGET_ABI_OPEN_VMS
5685 if (cum
->num_args
< 6
5686 && 6 < cum
->num_args
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5687 words
= 6 - cum
->num_args
;
5688 #elif TARGET_ABI_UNICOSMK
5689 /* Never any split arguments. */
5690 #elif TARGET_ABI_OSF
5691 if (*cum
< 6 && 6 < *cum
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5694 #error Unhandled ABI
5697 return words
* UNITS_PER_WORD
;
5701 /* Return true if TYPE must be returned in memory, instead of in registers. */
5704 alpha_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5706 enum machine_mode mode
= VOIDmode
;
5711 mode
= TYPE_MODE (type
);
5713 /* All aggregates are returned in memory. */
5714 if (AGGREGATE_TYPE_P (type
))
5718 size
= GET_MODE_SIZE (mode
);
5719 switch (GET_MODE_CLASS (mode
))
5721 case MODE_VECTOR_FLOAT
:
5722 /* Pass all float vectors in memory, like an aggregate. */
5725 case MODE_COMPLEX_FLOAT
:
5726 /* We judge complex floats on the size of their element,
5727 not the size of the whole type. */
5728 size
= GET_MODE_UNIT_SIZE (mode
);
5733 case MODE_COMPLEX_INT
:
5734 case MODE_VECTOR_INT
:
5738 /* ??? We get called on all sorts of random stuff from
5739 aggregate_value_p. We must return something, but it's not
5740 clear what's safe to return. Pretend it's a struct I
5745 /* Otherwise types must fit in one register. */
5746 return size
> UNITS_PER_WORD
;
5749 /* Return true if TYPE should be passed by invisible reference. */
5752 alpha_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
5753 enum machine_mode mode
,
5754 const_tree type ATTRIBUTE_UNUSED
,
5755 bool named ATTRIBUTE_UNUSED
)
5757 return mode
== TFmode
|| mode
== TCmode
;
5760 /* Define how to find the value returned by a function. VALTYPE is the
5761 data type of the value (as a tree). If the precise function being
5762 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5763 MODE is set instead of VALTYPE for libcalls.
5765 On Alpha the value is found in $0 for integer functions and
5766 $f0 for floating-point functions. */
5769 function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
5770 enum machine_mode mode
)
5772 unsigned int regnum
, dummy
;
5773 enum mode_class mclass
;
5775 gcc_assert (!valtype
|| !alpha_return_in_memory (valtype
, func
));
5778 mode
= TYPE_MODE (valtype
);
5780 mclass
= GET_MODE_CLASS (mode
);
5784 PROMOTE_MODE (mode
, dummy
, valtype
);
5787 case MODE_COMPLEX_INT
:
5788 case MODE_VECTOR_INT
:
5796 case MODE_COMPLEX_FLOAT
:
5798 enum machine_mode cmode
= GET_MODE_INNER (mode
);
5800 return gen_rtx_PARALLEL
5803 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
5805 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
5806 GEN_INT (GET_MODE_SIZE (cmode
)))));
5813 return gen_rtx_REG (mode
, regnum
);
5816 /* TCmode complex values are passed by invisible reference. We
5817 should not split these values. */
5820 alpha_split_complex_arg (const_tree type
)
5822 return TYPE_MODE (type
) != TCmode
;
5826 alpha_build_builtin_va_list (void)
5828 tree base
, ofs
, space
, record
, type_decl
;
5830 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5831 return ptr_type_node
;
5833 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5834 type_decl
= build_decl (BUILTINS_LOCATION
,
5835 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5836 TREE_CHAIN (record
) = type_decl
;
5837 TYPE_NAME (record
) = type_decl
;
5839 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5841 /* Dummy field to prevent alignment warnings. */
5842 space
= build_decl (BUILTINS_LOCATION
,
5843 FIELD_DECL
, NULL_TREE
, integer_type_node
);
5844 DECL_FIELD_CONTEXT (space
) = record
;
5845 DECL_ARTIFICIAL (space
) = 1;
5846 DECL_IGNORED_P (space
) = 1;
5848 ofs
= build_decl (BUILTINS_LOCATION
,
5849 FIELD_DECL
, get_identifier ("__offset"),
5851 DECL_FIELD_CONTEXT (ofs
) = record
;
5852 TREE_CHAIN (ofs
) = space
;
5854 base
= build_decl (BUILTINS_LOCATION
,
5855 FIELD_DECL
, get_identifier ("__base"),
5857 DECL_FIELD_CONTEXT (base
) = record
;
5858 TREE_CHAIN (base
) = ofs
;
5860 TYPE_FIELDS (record
) = base
;
5861 layout_type (record
);
5863 va_list_gpr_counter_field
= ofs
;
5868 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5869 and constant additions. */
5872 va_list_skip_additions (tree lhs
)
5878 enum tree_code code
;
5880 stmt
= SSA_NAME_DEF_STMT (lhs
);
5882 if (gimple_code (stmt
) == GIMPLE_PHI
)
5885 if (!is_gimple_assign (stmt
)
5886 || gimple_assign_lhs (stmt
) != lhs
)
5889 if (TREE_CODE (gimple_assign_rhs1 (stmt
)) != SSA_NAME
)
5891 code
= gimple_assign_rhs_code (stmt
);
5892 if (!CONVERT_EXPR_CODE_P (code
)
5893 && ((code
!= PLUS_EXPR
&& code
!= POINTER_PLUS_EXPR
)
5894 || TREE_CODE (gimple_assign_rhs2 (stmt
)) != INTEGER_CST
5895 || !host_integerp (gimple_assign_rhs2 (stmt
), 1)))
5898 lhs
= gimple_assign_rhs1 (stmt
);
5902 /* Check if LHS = RHS statement is
5903 LHS = *(ap.__base + ap.__offset + cst)
5906 + ((ap.__offset + cst <= 47)
5907 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
5908 If the former, indicate that GPR registers are needed,
5909 if the latter, indicate that FPR registers are needed.
5911 Also look for LHS = (*ptr).field, where ptr is one of the forms
5914 On alpha, cfun->va_list_gpr_size is used as size of the needed
5915 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if GPR
5916 registers are needed and bit 1 set if FPR registers are needed.
5917 Return true if va_list references should not be scanned for the
5918 current statement. */
5921 alpha_stdarg_optimize_hook (struct stdarg_info
*si
, const_gimple stmt
)
5923 tree base
, offset
, rhs
;
5927 if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt
))
5928 != GIMPLE_SINGLE_RHS
)
5931 rhs
= gimple_assign_rhs1 (stmt
);
5932 while (handled_component_p (rhs
))
5933 rhs
= TREE_OPERAND (rhs
, 0);
5934 if (TREE_CODE (rhs
) != INDIRECT_REF
5935 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5938 stmt
= va_list_skip_additions (TREE_OPERAND (rhs
, 0));
5940 || !is_gimple_assign (stmt
)
5941 || gimple_assign_rhs_code (stmt
) != POINTER_PLUS_EXPR
)
5944 base
= gimple_assign_rhs1 (stmt
);
5945 if (TREE_CODE (base
) == SSA_NAME
)
5947 base_stmt
= va_list_skip_additions (base
);
5949 && is_gimple_assign (base_stmt
)
5950 && gimple_assign_rhs_code (base_stmt
) == COMPONENT_REF
)
5951 base
= gimple_assign_rhs1 (base_stmt
);
5954 if (TREE_CODE (base
) != COMPONENT_REF
5955 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5957 base
= gimple_assign_rhs2 (stmt
);
5958 if (TREE_CODE (base
) == SSA_NAME
)
5960 base_stmt
= va_list_skip_additions (base
);
5962 && is_gimple_assign (base_stmt
)
5963 && gimple_assign_rhs_code (base_stmt
) == COMPONENT_REF
)
5964 base
= gimple_assign_rhs1 (base_stmt
);
5967 if (TREE_CODE (base
) != COMPONENT_REF
5968 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5974 base
= get_base_address (base
);
5975 if (TREE_CODE (base
) != VAR_DECL
5976 || !bitmap_bit_p (si
->va_list_vars
, DECL_UID (base
)))
5979 offset
= gimple_op (stmt
, 1 + offset_arg
);
5980 if (TREE_CODE (offset
) == SSA_NAME
)
5982 gimple offset_stmt
= va_list_skip_additions (offset
);
5985 && gimple_code (offset_stmt
) == GIMPLE_PHI
)
5988 gimple arg1_stmt
, arg2_stmt
;
5990 enum tree_code code1
, code2
;
5992 if (gimple_phi_num_args (offset_stmt
) != 2)
5996 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt
, 0));
5998 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt
, 1));
5999 if (arg1_stmt
== NULL
6000 || !is_gimple_assign (arg1_stmt
)
6001 || arg2_stmt
== NULL
6002 || !is_gimple_assign (arg2_stmt
))
6005 code1
= gimple_assign_rhs_code (arg1_stmt
);
6006 code2
= gimple_assign_rhs_code (arg2_stmt
);
6007 if (code1
== COMPONENT_REF
6008 && (code2
== MINUS_EXPR
|| code2
== PLUS_EXPR
))
6010 else if (code2
== COMPONENT_REF
6011 && (code1
== MINUS_EXPR
|| code1
== PLUS_EXPR
))
6013 gimple tem
= arg1_stmt
;
6015 arg1_stmt
= arg2_stmt
;
6021 if (!host_integerp (gimple_assign_rhs2 (arg2_stmt
), 0))
6024 sub
= tree_low_cst (gimple_assign_rhs2 (arg2_stmt
), 0);
6025 if (code2
== MINUS_EXPR
)
6027 if (sub
< -48 || sub
> -32)
6030 arg1
= gimple_assign_rhs1 (arg1_stmt
);
6031 arg2
= gimple_assign_rhs1 (arg2_stmt
);
6032 if (TREE_CODE (arg2
) == SSA_NAME
)
6034 arg2_stmt
= va_list_skip_additions (arg2
);
6035 if (arg2_stmt
== NULL
6036 || !is_gimple_assign (arg2_stmt
)
6037 || gimple_assign_rhs_code (arg2_stmt
) != COMPONENT_REF
)
6039 arg2
= gimple_assign_rhs1 (arg2_stmt
);
6044 if (TREE_CODE (arg1
) != COMPONENT_REF
6045 || TREE_OPERAND (arg1
, 1) != va_list_gpr_counter_field
6046 || get_base_address (arg1
) != base
)
6049 /* Need floating point regs. */
6050 cfun
->va_list_fpr_size
|= 2;
6054 && is_gimple_assign (offset_stmt
)
6055 && gimple_assign_rhs_code (offset_stmt
) == COMPONENT_REF
)
6056 offset
= gimple_assign_rhs1 (offset_stmt
);
6058 if (TREE_CODE (offset
) != COMPONENT_REF
6059 || TREE_OPERAND (offset
, 1) != va_list_gpr_counter_field
6060 || get_base_address (offset
) != base
)
6063 /* Need general regs. */
6064 cfun
->va_list_fpr_size
|= 1;
6068 si
->va_list_escapes
= true;
6073 /* Perform any needed actions needed for a function that is receiving a
6074 variable number of arguments. */
6077 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
6078 tree type
, int *pretend_size
, int no_rtl
)
6080 CUMULATIVE_ARGS cum
= *pcum
;
6082 /* Skip the current argument. */
6083 FUNCTION_ARG_ADVANCE (cum
, mode
, type
, 1);
6085 #if TARGET_ABI_UNICOSMK
6086 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6087 arguments on the stack. Unfortunately, it doesn't always store the first
6088 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6089 with stdargs as we always have at least one named argument there. */
6090 if (cum
.num_reg_words
< 6)
6094 emit_insn (gen_umk_mismatch_args (GEN_INT (cum
.num_reg_words
)));
6095 emit_insn (gen_arg_home_umk ());
6099 #elif TARGET_ABI_OPEN_VMS
6100 /* For VMS, we allocate space for all 6 arg registers plus a count.
6102 However, if NO registers need to be saved, don't allocate any space.
6103 This is not only because we won't need the space, but because AP
6104 includes the current_pretend_args_size and we don't want to mess up
6105 any ap-relative addresses already made. */
6106 if (cum
.num_args
< 6)
6110 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6111 emit_insn (gen_arg_home ());
6113 *pretend_size
= 7 * UNITS_PER_WORD
;
6116 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6117 only push those that are remaining. However, if NO registers need to
6118 be saved, don't allocate any space. This is not only because we won't
6119 need the space, but because AP includes the current_pretend_args_size
6120 and we don't want to mess up any ap-relative addresses already made.
6122 If we are not to use the floating-point registers, save the integer
6123 registers where we would put the floating-point registers. This is
6124 not the most efficient way to implement varargs with just one register
6125 class, but it isn't worth doing anything more efficient in this rare
6133 alias_set_type set
= get_varargs_alias_set ();
6136 count
= cfun
->va_list_gpr_size
/ UNITS_PER_WORD
;
6137 if (count
> 6 - cum
)
6140 /* Detect whether integer registers or floating-point registers
6141 are needed by the detected va_arg statements. See above for
6142 how these values are computed. Note that the "escape" value
6143 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
6145 gcc_assert ((VA_LIST_MAX_FPR_SIZE
& 3) == 3);
6147 if (cfun
->va_list_fpr_size
& 1)
6149 tmp
= gen_rtx_MEM (BLKmode
,
6150 plus_constant (virtual_incoming_args_rtx
,
6151 (cum
+ 6) * UNITS_PER_WORD
));
6152 MEM_NOTRAP_P (tmp
) = 1;
6153 set_mem_alias_set (tmp
, set
);
6154 move_block_from_reg (16 + cum
, tmp
, count
);
6157 if (cfun
->va_list_fpr_size
& 2)
6159 tmp
= gen_rtx_MEM (BLKmode
,
6160 plus_constant (virtual_incoming_args_rtx
,
6161 cum
* UNITS_PER_WORD
));
6162 MEM_NOTRAP_P (tmp
) = 1;
6163 set_mem_alias_set (tmp
, set
);
6164 move_block_from_reg (16 + cum
+ TARGET_FPREGS
*32, tmp
, count
);
6167 *pretend_size
= 12 * UNITS_PER_WORD
;
6172 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6174 HOST_WIDE_INT offset
;
6175 tree t
, offset_field
, base_field
;
6177 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6180 if (TARGET_ABI_UNICOSMK
)
6181 std_expand_builtin_va_start (valist
, nextarg
);
6183 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6184 up by 48, storing fp arg registers in the first 48 bytes, and the
6185 integer arg registers in the next 48 bytes. This is only done,
6186 however, if any integer registers need to be stored.
6188 If no integer registers need be stored, then we must subtract 48
6189 in order to account for the integer arg registers which are counted
6190 in argsize above, but which are not actually stored on the stack.
6191 Must further be careful here about structures straddling the last
6192 integer argument register; that futzes with pretend_args_size,
6193 which changes the meaning of AP. */
6196 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6198 offset
= -6 * UNITS_PER_WORD
+ crtl
->args
.pretend_args_size
;
6200 if (TARGET_ABI_OPEN_VMS
)
6202 nextarg
= plus_constant (nextarg
, offset
);
6203 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6204 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6205 make_tree (ptr_type_node
, nextarg
));
6206 TREE_SIDE_EFFECTS (t
) = 1;
6208 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6212 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6213 offset_field
= TREE_CHAIN (base_field
);
6215 base_field
= build3 (COMPONENT_REF
, TREE_TYPE (base_field
),
6216 valist
, base_field
, NULL_TREE
);
6217 offset_field
= build3 (COMPONENT_REF
, TREE_TYPE (offset_field
),
6218 valist
, offset_field
, NULL_TREE
);
6220 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6221 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
6223 t
= build2 (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6224 TREE_SIDE_EFFECTS (t
) = 1;
6225 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6227 t
= build_int_cst (NULL_TREE
, NUM_ARGS
* UNITS_PER_WORD
);
6228 t
= build2 (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6229 TREE_SIDE_EFFECTS (t
) = 1;
6230 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6235 alpha_gimplify_va_arg_1 (tree type
, tree base
, tree offset
,
6238 tree type_size
, ptr_type
, addend
, t
, addr
;
6239 gimple_seq internal_post
;
6241 /* If the type could not be passed in registers, skip the block
6242 reserved for the registers. */
6243 if (targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
6245 t
= build_int_cst (TREE_TYPE (offset
), 6*8);
6246 gimplify_assign (offset
,
6247 build2 (MAX_EXPR
, TREE_TYPE (offset
), offset
, t
),
6252 ptr_type
= build_pointer_type (type
);
6254 if (TREE_CODE (type
) == COMPLEX_TYPE
)
6256 tree real_part
, imag_part
, real_temp
;
6258 real_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6261 /* Copy the value into a new temporary, lest the formal temporary
6262 be reused out from under us. */
6263 real_temp
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
6265 imag_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6268 return build2 (COMPLEX_EXPR
, type
, real_temp
, imag_part
);
6270 else if (TREE_CODE (type
) == REAL_TYPE
)
6272 tree fpaddend
, cond
, fourtyeight
;
6274 fourtyeight
= build_int_cst (TREE_TYPE (addend
), 6*8);
6275 fpaddend
= fold_build2 (MINUS_EXPR
, TREE_TYPE (addend
),
6276 addend
, fourtyeight
);
6277 cond
= fold_build2 (LT_EXPR
, boolean_type_node
, addend
, fourtyeight
);
6278 addend
= fold_build3 (COND_EXPR
, TREE_TYPE (addend
), cond
,
6282 /* Build the final address and force that value into a temporary. */
6283 addr
= build2 (POINTER_PLUS_EXPR
, ptr_type
, fold_convert (ptr_type
, base
),
6284 fold_convert (sizetype
, addend
));
6285 internal_post
= NULL
;
6286 gimplify_expr (&addr
, pre_p
, &internal_post
, is_gimple_val
, fb_rvalue
);
6287 gimple_seq_add_seq (pre_p
, internal_post
);
6289 /* Update the offset field. */
6290 type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
));
6291 if (type_size
== NULL
|| TREE_OVERFLOW (type_size
))
6295 t
= size_binop (PLUS_EXPR
, type_size
, size_int (7));
6296 t
= size_binop (TRUNC_DIV_EXPR
, t
, size_int (8));
6297 t
= size_binop (MULT_EXPR
, t
, size_int (8));
6299 t
= fold_convert (TREE_TYPE (offset
), t
);
6300 gimplify_assign (offset
, build2 (PLUS_EXPR
, TREE_TYPE (offset
), offset
, t
),
6303 return build_va_arg_indirect_ref (addr
);
6307 alpha_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6310 tree offset_field
, base_field
, offset
, base
, t
, r
;
6313 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6314 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6316 base_field
= TYPE_FIELDS (va_list_type_node
);
6317 offset_field
= TREE_CHAIN (base_field
);
6318 base_field
= build3 (COMPONENT_REF
, TREE_TYPE (base_field
),
6319 valist
, base_field
, NULL_TREE
);
6320 offset_field
= build3 (COMPONENT_REF
, TREE_TYPE (offset_field
),
6321 valist
, offset_field
, NULL_TREE
);
6323 /* Pull the fields of the structure out into temporaries. Since we never
6324 modify the base field, we can use a formal temporary. Sign-extend the
6325 offset field so that it's the proper width for pointer arithmetic. */
6326 base
= get_formal_tmp_var (base_field
, pre_p
);
6328 t
= fold_convert (lang_hooks
.types
.type_for_size (64, 0), offset_field
);
6329 offset
= get_initialized_tmp_var (t
, pre_p
, NULL
);
6331 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6333 type
= build_pointer_type (type
);
6335 /* Find the value. Note that this will be a stable indirection, or
6336 a composite of stable indirections in the case of complex. */
6337 r
= alpha_gimplify_va_arg_1 (type
, base
, offset
, pre_p
);
6339 /* Stuff the offset temporary back into its field. */
6340 gimplify_assign (unshare_expr (offset_field
),
6341 fold_convert (TREE_TYPE (offset_field
), offset
), pre_p
);
6344 r
= build_va_arg_indirect_ref (r
);
6353 ALPHA_BUILTIN_CMPBGE
,
6354 ALPHA_BUILTIN_EXTBL
,
6355 ALPHA_BUILTIN_EXTWL
,
6356 ALPHA_BUILTIN_EXTLL
,
6357 ALPHA_BUILTIN_EXTQL
,
6358 ALPHA_BUILTIN_EXTWH
,
6359 ALPHA_BUILTIN_EXTLH
,
6360 ALPHA_BUILTIN_EXTQH
,
6361 ALPHA_BUILTIN_INSBL
,
6362 ALPHA_BUILTIN_INSWL
,
6363 ALPHA_BUILTIN_INSLL
,
6364 ALPHA_BUILTIN_INSQL
,
6365 ALPHA_BUILTIN_INSWH
,
6366 ALPHA_BUILTIN_INSLH
,
6367 ALPHA_BUILTIN_INSQH
,
6368 ALPHA_BUILTIN_MSKBL
,
6369 ALPHA_BUILTIN_MSKWL
,
6370 ALPHA_BUILTIN_MSKLL
,
6371 ALPHA_BUILTIN_MSKQL
,
6372 ALPHA_BUILTIN_MSKWH
,
6373 ALPHA_BUILTIN_MSKLH
,
6374 ALPHA_BUILTIN_MSKQH
,
6375 ALPHA_BUILTIN_UMULH
,
6377 ALPHA_BUILTIN_ZAPNOT
,
6378 ALPHA_BUILTIN_AMASK
,
6379 ALPHA_BUILTIN_IMPLVER
,
6381 ALPHA_BUILTIN_THREAD_POINTER
,
6382 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6385 ALPHA_BUILTIN_MINUB8
,
6386 ALPHA_BUILTIN_MINSB8
,
6387 ALPHA_BUILTIN_MINUW4
,
6388 ALPHA_BUILTIN_MINSW4
,
6389 ALPHA_BUILTIN_MAXUB8
,
6390 ALPHA_BUILTIN_MAXSB8
,
6391 ALPHA_BUILTIN_MAXUW4
,
6392 ALPHA_BUILTIN_MAXSW4
,
6396 ALPHA_BUILTIN_UNPKBL
,
6397 ALPHA_BUILTIN_UNPKBW
,
6402 ALPHA_BUILTIN_CTPOP
,
6407 static enum insn_code
const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6408 CODE_FOR_builtin_cmpbge
,
6409 CODE_FOR_builtin_extbl
,
6410 CODE_FOR_builtin_extwl
,
6411 CODE_FOR_builtin_extll
,
6412 CODE_FOR_builtin_extql
,
6413 CODE_FOR_builtin_extwh
,
6414 CODE_FOR_builtin_extlh
,
6415 CODE_FOR_builtin_extqh
,
6416 CODE_FOR_builtin_insbl
,
6417 CODE_FOR_builtin_inswl
,
6418 CODE_FOR_builtin_insll
,
6419 CODE_FOR_builtin_insql
,
6420 CODE_FOR_builtin_inswh
,
6421 CODE_FOR_builtin_inslh
,
6422 CODE_FOR_builtin_insqh
,
6423 CODE_FOR_builtin_mskbl
,
6424 CODE_FOR_builtin_mskwl
,
6425 CODE_FOR_builtin_mskll
,
6426 CODE_FOR_builtin_mskql
,
6427 CODE_FOR_builtin_mskwh
,
6428 CODE_FOR_builtin_msklh
,
6429 CODE_FOR_builtin_mskqh
,
6430 CODE_FOR_umuldi3_highpart
,
6431 CODE_FOR_builtin_zap
,
6432 CODE_FOR_builtin_zapnot
,
6433 CODE_FOR_builtin_amask
,
6434 CODE_FOR_builtin_implver
,
6435 CODE_FOR_builtin_rpcc
,
6440 CODE_FOR_builtin_minub8
,
6441 CODE_FOR_builtin_minsb8
,
6442 CODE_FOR_builtin_minuw4
,
6443 CODE_FOR_builtin_minsw4
,
6444 CODE_FOR_builtin_maxub8
,
6445 CODE_FOR_builtin_maxsb8
,
6446 CODE_FOR_builtin_maxuw4
,
6447 CODE_FOR_builtin_maxsw4
,
6448 CODE_FOR_builtin_perr
,
6449 CODE_FOR_builtin_pklb
,
6450 CODE_FOR_builtin_pkwb
,
6451 CODE_FOR_builtin_unpkbl
,
6452 CODE_FOR_builtin_unpkbw
,
6457 CODE_FOR_popcountdi2
6460 struct alpha_builtin_def
6463 enum alpha_builtin code
;
6464 unsigned int target_mask
;
6468 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6469 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0, true },
6470 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0, false }
6473 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6474 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0, true },
6475 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
, true },
6476 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
, true },
6477 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
, true },
6478 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
, true },
6479 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
, true },
6480 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
, true },
6481 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
, true }
6484 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6485 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0, true },
6486 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0, true },
6487 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0, true },
6488 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0, true },
6489 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0, true },
6490 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0, true },
6491 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0, true },
6492 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0, true },
6493 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0, true },
6494 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0, true },
6495 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0, true },
6496 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0, true },
6497 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0, true },
6498 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0, true },
6499 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0, true },
6500 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0, true },
6501 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0, true },
6502 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0, true },
6503 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0, true },
6504 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0, true },
6505 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0, true },
6506 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0, true },
6507 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0, true },
6508 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0, true },
6509 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0, true },
6510 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
, true },
6511 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
, true },
6512 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
, true },
6513 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
, true },
6514 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
, true },
6515 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
, true },
6516 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
, true },
6517 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
, true },
6518 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
, true }
6521 static GTY(()) tree alpha_v8qi_u
;
6522 static GTY(()) tree alpha_v8qi_s
;
6523 static GTY(()) tree alpha_v4hi_u
;
6524 static GTY(()) tree alpha_v4hi_s
;
6526 /* Helper function of alpha_init_builtins. Add the COUNT built-in
6527 functions pointed to by P, with function type FTYPE. */
6530 alpha_add_builtins (const struct alpha_builtin_def
*p
, size_t count
,
6536 for (i
= 0; i
< count
; ++i
, ++p
)
6537 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6539 decl
= add_builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6542 TREE_READONLY (decl
) = 1;
6543 TREE_NOTHROW (decl
) = 1;
6549 alpha_init_builtins (void)
6551 tree dimode_integer_type_node
;
6554 dimode_integer_type_node
= lang_hooks
.types
.type_for_mode (DImode
, 0);
6556 ftype
= build_function_type (dimode_integer_type_node
, void_list_node
);
6557 alpha_add_builtins (zero_arg_builtins
, ARRAY_SIZE (zero_arg_builtins
),
6560 ftype
= build_function_type_list (dimode_integer_type_node
,
6561 dimode_integer_type_node
, NULL_TREE
);
6562 alpha_add_builtins (one_arg_builtins
, ARRAY_SIZE (one_arg_builtins
),
6565 ftype
= build_function_type_list (dimode_integer_type_node
,
6566 dimode_integer_type_node
,
6567 dimode_integer_type_node
, NULL_TREE
);
6568 alpha_add_builtins (two_arg_builtins
, ARRAY_SIZE (two_arg_builtins
),
6571 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6572 decl
= add_builtin_function ("__builtin_thread_pointer", ftype
,
6573 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6575 TREE_NOTHROW (decl
) = 1;
6577 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6578 decl
= add_builtin_function ("__builtin_set_thread_pointer", ftype
,
6579 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6581 TREE_NOTHROW (decl
) = 1;
6583 alpha_v8qi_u
= build_vector_type (unsigned_intQI_type_node
, 8);
6584 alpha_v8qi_s
= build_vector_type (intQI_type_node
, 8);
6585 alpha_v4hi_u
= build_vector_type (unsigned_intHI_type_node
, 4);
6586 alpha_v4hi_s
= build_vector_type (intHI_type_node
, 4);
6589 /* Expand an expression EXP that calls a built-in function,
6590 with result going to TARGET if that's convenient
6591 (and in mode MODE if that's convenient).
6592 SUBTARGET may be used as the target for computing one of EXP's operands.
6593 IGNORE is nonzero if the value is to be ignored. */
6596 alpha_expand_builtin (tree exp
, rtx target
,
6597 rtx subtarget ATTRIBUTE_UNUSED
,
6598 enum machine_mode mode ATTRIBUTE_UNUSED
,
6599 int ignore ATTRIBUTE_UNUSED
)
6603 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
6604 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6606 call_expr_arg_iterator iter
;
6607 enum insn_code icode
;
6608 rtx op
[MAX_ARGS
], pat
;
6612 if (fcode
>= ALPHA_BUILTIN_max
)
6613 internal_error ("bad builtin fcode");
6614 icode
= code_for_builtin
[fcode
];
6616 internal_error ("bad builtin fcode");
6618 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6621 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
6623 const struct insn_operand_data
*insn_op
;
6625 if (arg
== error_mark_node
)
6627 if (arity
> MAX_ARGS
)
6630 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6632 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
6634 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6635 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6641 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6643 || GET_MODE (target
) != tmode
6644 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6645 target
= gen_reg_rtx (tmode
);
6651 pat
= GEN_FCN (icode
) (target
);
6655 pat
= GEN_FCN (icode
) (target
, op
[0]);
6657 pat
= GEN_FCN (icode
) (op
[0]);
6660 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6676 /* Several bits below assume HWI >= 64 bits. This should be enforced
6678 #if HOST_BITS_PER_WIDE_INT < 64
6679 # error "HOST_WIDE_INT too small"
6682 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6683 with an 8-bit output vector. OPINT contains the integer operands; bit N
6684 of OP_CONST is set if OPINT[N] is valid. */
6687 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint
[], long op_const
)
6692 for (i
= 0, val
= 0; i
< 8; ++i
)
6694 unsigned HOST_WIDE_INT c0
= (opint
[0] >> (i
* 8)) & 0xff;
6695 unsigned HOST_WIDE_INT c1
= (opint
[1] >> (i
* 8)) & 0xff;
6699 return build_int_cst (long_integer_type_node
, val
);
6701 else if (op_const
== 2 && opint
[1] == 0)
6702 return build_int_cst (long_integer_type_node
, 0xff);
6706 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6707 specialized form of an AND operation. Other byte manipulation instructions
6708 are defined in terms of this instruction, so this is also used as a
6709 subroutine for other builtins.
6711 OP contains the tree operands; OPINT contains the extracted integer values.
6712 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6713 OPINT may be considered. */
6716 alpha_fold_builtin_zapnot (tree
*op
, unsigned HOST_WIDE_INT opint
[],
6721 unsigned HOST_WIDE_INT mask
= 0;
6724 for (i
= 0; i
< 8; ++i
)
6725 if ((opint
[1] >> i
) & 1)
6726 mask
|= (unsigned HOST_WIDE_INT
)0xff << (i
* 8);
6729 return build_int_cst (long_integer_type_node
, opint
[0] & mask
);
6732 return fold_build2 (BIT_AND_EXPR
, long_integer_type_node
, op
[0],
6733 build_int_cst (long_integer_type_node
, mask
));
6735 else if ((op_const
& 1) && opint
[0] == 0)
6736 return build_int_cst (long_integer_type_node
, 0);
6740 /* Fold the builtins for the EXT family of instructions. */
6743 alpha_fold_builtin_extxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6744 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6748 tree
*zap_op
= NULL
;
6752 unsigned HOST_WIDE_INT loc
;
6755 if (BYTES_BIG_ENDIAN
)
6763 unsigned HOST_WIDE_INT temp
= opint
[0];
6776 opint
[1] = bytemask
;
6777 return alpha_fold_builtin_zapnot (zap_op
, opint
, zap_const
);
6780 /* Fold the builtins for the INS family of instructions. */
6783 alpha_fold_builtin_insxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6784 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6787 if ((op_const
& 1) && opint
[0] == 0)
6788 return build_int_cst (long_integer_type_node
, 0);
6792 unsigned HOST_WIDE_INT temp
, loc
, byteloc
;
6793 tree
*zap_op
= NULL
;
6796 if (BYTES_BIG_ENDIAN
)
6803 byteloc
= (64 - (loc
* 8)) & 0x3f;
6820 opint
[1] = bytemask
;
6821 return alpha_fold_builtin_zapnot (zap_op
, opint
, op_const
);
6828 alpha_fold_builtin_mskxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6829 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6834 unsigned HOST_WIDE_INT loc
;
6837 if (BYTES_BIG_ENDIAN
)
6844 opint
[1] = bytemask
^ 0xff;
6847 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
6851 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint
[], long op_const
)
6857 unsigned HOST_WIDE_INT l
;
6860 mul_double (opint
[0], 0, opint
[1], 0, &l
, &h
);
6862 #if HOST_BITS_PER_WIDE_INT > 64
6866 return build_int_cst (long_integer_type_node
, h
);
6870 opint
[1] = opint
[0];
6873 /* Note that (X*1) >> 64 == 0. */
6874 if (opint
[1] == 0 || opint
[1] == 1)
6875 return build_int_cst (long_integer_type_node
, 0);
6882 alpha_fold_vector_minmax (enum tree_code code
, tree op
[], tree vtype
)
6884 tree op0
= fold_convert (vtype
, op
[0]);
6885 tree op1
= fold_convert (vtype
, op
[1]);
6886 tree val
= fold_build2 (code
, vtype
, op0
, op1
);
6887 return fold_build1 (VIEW_CONVERT_EXPR
, long_integer_type_node
, val
);
6891 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint
[], long op_const
)
6893 unsigned HOST_WIDE_INT temp
= 0;
6899 for (i
= 0; i
< 8; ++i
)
6901 unsigned HOST_WIDE_INT a
= (opint
[0] >> (i
* 8)) & 0xff;
6902 unsigned HOST_WIDE_INT b
= (opint
[1] >> (i
* 8)) & 0xff;
6909 return build_int_cst (long_integer_type_node
, temp
);
6913 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6915 unsigned HOST_WIDE_INT temp
;
6920 temp
= opint
[0] & 0xff;
6921 temp
|= (opint
[0] >> 24) & 0xff00;
6923 return build_int_cst (long_integer_type_node
, temp
);
6927 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6929 unsigned HOST_WIDE_INT temp
;
6934 temp
= opint
[0] & 0xff;
6935 temp
|= (opint
[0] >> 8) & 0xff00;
6936 temp
|= (opint
[0] >> 16) & 0xff0000;
6937 temp
|= (opint
[0] >> 24) & 0xff000000;
6939 return build_int_cst (long_integer_type_node
, temp
);
6943 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint
[], long op_const
)
6945 unsigned HOST_WIDE_INT temp
;
6950 temp
= opint
[0] & 0xff;
6951 temp
|= (opint
[0] & 0xff00) << 24;
6953 return build_int_cst (long_integer_type_node
, temp
);
6957 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint
[], long op_const
)
6959 unsigned HOST_WIDE_INT temp
;
6964 temp
= opint
[0] & 0xff;
6965 temp
|= (opint
[0] & 0x0000ff00) << 8;
6966 temp
|= (opint
[0] & 0x00ff0000) << 16;
6967 temp
|= (opint
[0] & 0xff000000) << 24;
6969 return build_int_cst (long_integer_type_node
, temp
);
6973 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6975 unsigned HOST_WIDE_INT temp
;
6983 temp
= exact_log2 (opint
[0] & -opint
[0]);
6985 return build_int_cst (long_integer_type_node
, temp
);
6989 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6991 unsigned HOST_WIDE_INT temp
;
6999 temp
= 64 - floor_log2 (opint
[0]) - 1;
7001 return build_int_cst (long_integer_type_node
, temp
);
7005 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint
[], long op_const
)
7007 unsigned HOST_WIDE_INT temp
, op
;
7015 temp
++, op
&= op
- 1;
7017 return build_int_cst (long_integer_type_node
, temp
);
7020 /* Fold one of our builtin functions. */
7023 alpha_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
7025 tree op
[MAX_ARGS
], t
;
7026 unsigned HOST_WIDE_INT opint
[MAX_ARGS
];
7027 long op_const
= 0, arity
= 0;
7029 for (t
= arglist
; t
; t
= TREE_CHAIN (t
), ++arity
)
7031 tree arg
= TREE_VALUE (t
);
7032 if (arg
== error_mark_node
)
7034 if (arity
>= MAX_ARGS
)
7039 if (TREE_CODE (arg
) == INTEGER_CST
)
7041 op_const
|= 1L << arity
;
7042 opint
[arity
] = int_cst_value (arg
);
7046 switch (DECL_FUNCTION_CODE (fndecl
))
7048 case ALPHA_BUILTIN_CMPBGE
:
7049 return alpha_fold_builtin_cmpbge (opint
, op_const
);
7051 case ALPHA_BUILTIN_EXTBL
:
7052 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x01, false);
7053 case ALPHA_BUILTIN_EXTWL
:
7054 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, false);
7055 case ALPHA_BUILTIN_EXTLL
:
7056 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, false);
7057 case ALPHA_BUILTIN_EXTQL
:
7058 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, false);
7059 case ALPHA_BUILTIN_EXTWH
:
7060 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, true);
7061 case ALPHA_BUILTIN_EXTLH
:
7062 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, true);
7063 case ALPHA_BUILTIN_EXTQH
:
7064 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, true);
7066 case ALPHA_BUILTIN_INSBL
:
7067 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x01, false);
7068 case ALPHA_BUILTIN_INSWL
:
7069 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, false);
7070 case ALPHA_BUILTIN_INSLL
:
7071 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, false);
7072 case ALPHA_BUILTIN_INSQL
:
7073 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, false);
7074 case ALPHA_BUILTIN_INSWH
:
7075 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, true);
7076 case ALPHA_BUILTIN_INSLH
:
7077 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, true);
7078 case ALPHA_BUILTIN_INSQH
:
7079 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, true);
7081 case ALPHA_BUILTIN_MSKBL
:
7082 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x01, false);
7083 case ALPHA_BUILTIN_MSKWL
:
7084 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, false);
7085 case ALPHA_BUILTIN_MSKLL
:
7086 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, false);
7087 case ALPHA_BUILTIN_MSKQL
:
7088 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, false);
7089 case ALPHA_BUILTIN_MSKWH
:
7090 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, true);
7091 case ALPHA_BUILTIN_MSKLH
:
7092 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, true);
7093 case ALPHA_BUILTIN_MSKQH
:
7094 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, true);
7096 case ALPHA_BUILTIN_UMULH
:
7097 return alpha_fold_builtin_umulh (opint
, op_const
);
7099 case ALPHA_BUILTIN_ZAP
:
7102 case ALPHA_BUILTIN_ZAPNOT
:
7103 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
7105 case ALPHA_BUILTIN_MINUB8
:
7106 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_u
);
7107 case ALPHA_BUILTIN_MINSB8
:
7108 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_s
);
7109 case ALPHA_BUILTIN_MINUW4
:
7110 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_u
);
7111 case ALPHA_BUILTIN_MINSW4
:
7112 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_s
);
7113 case ALPHA_BUILTIN_MAXUB8
:
7114 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_u
);
7115 case ALPHA_BUILTIN_MAXSB8
:
7116 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_s
);
7117 case ALPHA_BUILTIN_MAXUW4
:
7118 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_u
);
7119 case ALPHA_BUILTIN_MAXSW4
:
7120 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_s
);
7122 case ALPHA_BUILTIN_PERR
:
7123 return alpha_fold_builtin_perr (opint
, op_const
);
7124 case ALPHA_BUILTIN_PKLB
:
7125 return alpha_fold_builtin_pklb (opint
, op_const
);
7126 case ALPHA_BUILTIN_PKWB
:
7127 return alpha_fold_builtin_pkwb (opint
, op_const
);
7128 case ALPHA_BUILTIN_UNPKBL
:
7129 return alpha_fold_builtin_unpkbl (opint
, op_const
);
7130 case ALPHA_BUILTIN_UNPKBW
:
7131 return alpha_fold_builtin_unpkbw (opint
, op_const
);
7133 case ALPHA_BUILTIN_CTTZ
:
7134 return alpha_fold_builtin_cttz (opint
, op_const
);
7135 case ALPHA_BUILTIN_CTLZ
:
7136 return alpha_fold_builtin_ctlz (opint
, op_const
);
7137 case ALPHA_BUILTIN_CTPOP
:
7138 return alpha_fold_builtin_ctpop (opint
, op_const
);
7140 case ALPHA_BUILTIN_AMASK
:
7141 case ALPHA_BUILTIN_IMPLVER
:
7142 case ALPHA_BUILTIN_RPCC
:
7143 case ALPHA_BUILTIN_THREAD_POINTER
:
7144 case ALPHA_BUILTIN_SET_THREAD_POINTER
:
7145 /* None of these are foldable at compile-time. */
7151 /* This page contains routines that are used to determine what the function
7152 prologue and epilogue code will do and write them out. */
7154 /* Compute the size of the save area in the stack. */
7156 /* These variables are used for communication between the following functions.
7157 They indicate various things about the current function being compiled
7158 that are used to tell what kind of prologue, epilogue and procedure
7159 descriptor to generate. */
7161 /* Nonzero if we need a stack procedure. */
7162 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
7163 static enum alpha_procedure_types alpha_procedure_type
;
7165 /* Register number (either FP or SP) that is used to unwind the frame. */
7166 static int vms_unwind_regno
;
7168 /* Register number used to save FP. We need not have one for RA since
7169 we don't modify it for register procedures. This is only defined
7170 for register frame procedures. */
7171 static int vms_save_fp_regno
;
7173 /* Register number used to reference objects off our PV. */
7174 static int vms_base_regno
;
7176 /* Compute register masks for saved registers. */
7179 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
7181 unsigned long imask
= 0;
7182 unsigned long fmask
= 0;
7185 /* When outputting a thunk, we don't have valid register life info,
7186 but assemble_start_function wants to output .frame and .mask
7195 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7196 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
7198 /* One for every register we have to save. */
7199 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7200 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
7201 && df_regs_ever_live_p (i
) && i
!= REG_RA
7202 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
7205 imask
|= (1UL << i
);
7207 fmask
|= (1UL << (i
- 32));
7210 /* We need to restore these for the handler. */
7211 if (crtl
->calls_eh_return
)
7215 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
7216 if (regno
== INVALID_REGNUM
)
7218 imask
|= 1UL << regno
;
7222 /* If any register spilled, then spill the return address also. */
7223 /* ??? This is required by the Digital stack unwind specification
7224 and isn't needed if we're doing Dwarf2 unwinding. */
7225 if (imask
|| fmask
|| alpha_ra_ever_killed ())
7226 imask
|= (1UL << REG_RA
);
7233 alpha_sa_size (void)
7235 unsigned long mask
[2];
7239 alpha_sa_mask (&mask
[0], &mask
[1]);
7241 if (TARGET_ABI_UNICOSMK
)
7243 if (mask
[0] || mask
[1])
7248 for (j
= 0; j
< 2; ++j
)
7249 for (i
= 0; i
< 32; ++i
)
7250 if ((mask
[j
] >> i
) & 1)
7254 if (TARGET_ABI_UNICOSMK
)
7256 /* We might not need to generate a frame if we don't make any calls
7257 (including calls to __T3E_MISMATCH if this is a vararg function),
7258 don't have any local variables which require stack slots, don't
7259 use alloca and have not determined that we need a frame for other
7262 alpha_procedure_type
7263 = (sa_size
|| get_frame_size() != 0
7264 || crtl
->outgoing_args_size
7265 || cfun
->stdarg
|| cfun
->calls_alloca
7266 || frame_pointer_needed
)
7267 ? PT_STACK
: PT_REGISTER
;
7269 /* Always reserve space for saving callee-saved registers if we
7270 need a frame as required by the calling convention. */
7271 if (alpha_procedure_type
== PT_STACK
)
7274 else if (TARGET_ABI_OPEN_VMS
)
7276 /* Start by assuming we can use a register procedure if we don't
7277 make any calls (REG_RA not used) or need to save any
7278 registers and a stack procedure if we do. */
7279 if ((mask
[0] >> REG_RA
) & 1)
7280 alpha_procedure_type
= PT_STACK
;
7281 else if (get_frame_size() != 0)
7282 alpha_procedure_type
= PT_REGISTER
;
7284 alpha_procedure_type
= PT_NULL
;
7286 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7287 made the final decision on stack procedure vs register procedure. */
7288 if (alpha_procedure_type
== PT_STACK
)
7291 /* Decide whether to refer to objects off our PV via FP or PV.
7292 If we need FP for something else or if we receive a nonlocal
7293 goto (which expects PV to contain the value), we must use PV.
7294 Otherwise, start by assuming we can use FP. */
7297 = (frame_pointer_needed
7298 || cfun
->has_nonlocal_label
7299 || alpha_procedure_type
== PT_STACK
7300 || crtl
->outgoing_args_size
)
7301 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7303 /* If we want to copy PV into FP, we need to find some register
7304 in which to save FP. */
7306 vms_save_fp_regno
= -1;
7307 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7308 for (i
= 0; i
< 32; i
++)
7309 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! df_regs_ever_live_p (i
))
7310 vms_save_fp_regno
= i
;
7312 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7313 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7314 else if (alpha_procedure_type
== PT_NULL
)
7315 vms_base_regno
= REG_PV
;
7317 /* Stack unwinding should be done via FP unless we use it for PV. */
7318 vms_unwind_regno
= (vms_base_regno
== REG_PV
7319 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7321 /* If this is a stack procedure, allow space for saving FP and RA. */
7322 if (alpha_procedure_type
== PT_STACK
)
7327 /* Our size must be even (multiple of 16 bytes). */
7335 /* Define the offset between two registers, one to be eliminated,
7336 and the other its replacement, at the start of a routine. */
7339 alpha_initial_elimination_offset (unsigned int from
,
7340 unsigned int to ATTRIBUTE_UNUSED
)
7344 ret
= alpha_sa_size ();
7345 ret
+= ALPHA_ROUND (crtl
->outgoing_args_size
);
7349 case FRAME_POINTER_REGNUM
:
7352 case ARG_POINTER_REGNUM
:
7353 ret
+= (ALPHA_ROUND (get_frame_size ()
7354 + crtl
->args
.pretend_args_size
)
7355 - crtl
->args
.pretend_args_size
);
7366 alpha_pv_save_size (void)
7369 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7373 alpha_using_fp (void)
7376 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7379 #if TARGET_ABI_OPEN_VMS
7381 static const struct attribute_spec vms_attribute_table
[] =
7383 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7384 { "overlaid", 0, 0, true, false, false, NULL
},
7385 { "global", 0, 0, true, false, false, NULL
},
7386 { "initialize", 0, 0, true, false, false, NULL
},
7387 { NULL
, 0, 0, false, false, false, NULL
}
7393 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
7395 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7399 alpha_find_lo_sum_using_gp (rtx insn
)
7401 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7405 alpha_does_function_need_gp (void)
7409 /* The GP being variable is an OSF abi thing. */
7410 if (! TARGET_ABI_OSF
)
7413 /* We need the gp to load the address of __mcount. */
7414 if (TARGET_PROFILING_NEEDS_GP
&& crtl
->profile
)
7417 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7421 /* The nonlocal receiver pattern assumes that the gp is valid for
7422 the nested function. Reasonable because it's almost always set
7423 correctly already. For the cases where that's wrong, make sure
7424 the nested function loads its gp on entry. */
7425 if (crtl
->has_nonlocal_goto
)
7428 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7429 Even if we are a static function, we still need to do this in case
7430 our address is taken and passed to something like qsort. */
7432 push_topmost_sequence ();
7433 insn
= get_insns ();
7434 pop_topmost_sequence ();
7436 for (; insn
; insn
= NEXT_INSN (insn
))
7438 && ! JUMP_TABLE_DATA_P (insn
)
7439 && GET_CODE (PATTERN (insn
)) != USE
7440 && GET_CODE (PATTERN (insn
)) != CLOBBER
7441 && get_attr_usegp (insn
))
7448 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7452 set_frame_related_p (void)
7454 rtx seq
= get_insns ();
7465 while (insn
!= NULL_RTX
)
7467 RTX_FRAME_RELATED_P (insn
) = 1;
7468 insn
= NEXT_INSN (insn
);
7470 seq
= emit_insn (seq
);
7474 seq
= emit_insn (seq
);
7475 RTX_FRAME_RELATED_P (seq
) = 1;
7480 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7482 /* Generates a store with the proper unwind info attached. VALUE is
7483 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7484 contains SP+FRAME_BIAS, and that is the unwind info that should be
7485 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7486 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7489 emit_frame_store_1 (rtx value
, rtx base_reg
, HOST_WIDE_INT frame_bias
,
7490 HOST_WIDE_INT base_ofs
, rtx frame_reg
)
7492 rtx addr
, mem
, insn
;
7494 addr
= plus_constant (base_reg
, base_ofs
);
7495 mem
= gen_rtx_MEM (DImode
, addr
);
7496 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7498 insn
= emit_move_insn (mem
, value
);
7499 RTX_FRAME_RELATED_P (insn
) = 1;
7501 if (frame_bias
|| value
!= frame_reg
)
7505 addr
= plus_constant (stack_pointer_rtx
, frame_bias
+ base_ofs
);
7506 mem
= gen_rtx_MEM (DImode
, addr
);
7509 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
7510 gen_rtx_SET (VOIDmode
, mem
, frame_reg
));
7515 emit_frame_store (unsigned int regno
, rtx base_reg
,
7516 HOST_WIDE_INT frame_bias
, HOST_WIDE_INT base_ofs
)
7518 rtx reg
= gen_rtx_REG (DImode
, regno
);
7519 emit_frame_store_1 (reg
, base_reg
, frame_bias
, base_ofs
, reg
);
7522 /* Write function prologue. */
7524 /* On vms we have two kinds of functions:
7526 - stack frame (PROC_STACK)
7527 these are 'normal' functions with local vars and which are
7528 calling other functions
7529 - register frame (PROC_REGISTER)
7530 keeps all data in registers, needs no stack
7532 We must pass this to the assembler so it can generate the
7533 proper pdsc (procedure descriptor)
7534 This is done with the '.pdesc' command.
7536 On not-vms, we don't really differentiate between the two, as we can
7537 simply allocate stack without saving registers. */
7540 alpha_expand_prologue (void)
7542 /* Registers to save. */
7543 unsigned long imask
= 0;
7544 unsigned long fmask
= 0;
7545 /* Stack space needed for pushing registers clobbered by us. */
7546 HOST_WIDE_INT sa_size
;
7547 /* Complete stack size needed. */
7548 HOST_WIDE_INT frame_size
;
7549 /* Offset from base reg to register save area. */
7550 HOST_WIDE_INT reg_offset
;
7554 sa_size
= alpha_sa_size ();
7556 frame_size
= get_frame_size ();
7557 if (TARGET_ABI_OPEN_VMS
)
7558 frame_size
= ALPHA_ROUND (sa_size
7559 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7561 + crtl
->args
.pretend_args_size
);
7562 else if (TARGET_ABI_UNICOSMK
)
7563 /* We have to allocate space for the DSIB if we generate a frame. */
7564 frame_size
= ALPHA_ROUND (sa_size
7565 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7566 + ALPHA_ROUND (frame_size
7567 + crtl
->outgoing_args_size
);
7569 frame_size
= (ALPHA_ROUND (crtl
->outgoing_args_size
)
7571 + ALPHA_ROUND (frame_size
7572 + crtl
->args
.pretend_args_size
));
7574 if (TARGET_ABI_OPEN_VMS
)
7577 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
7579 alpha_sa_mask (&imask
, &fmask
);
7581 /* Emit an insn to reload GP, if needed. */
7584 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7585 if (alpha_function_needs_gp
)
7586 emit_insn (gen_prologue_ldgp ());
7589 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7590 the call to mcount ourselves, rather than having the linker do it
7591 magically in response to -pg. Since _mcount has special linkage,
7592 don't represent the call as a call. */
7593 if (TARGET_PROFILING_NEEDS_GP
&& crtl
->profile
)
7594 emit_insn (gen_prologue_mcount ());
7596 if (TARGET_ABI_UNICOSMK
)
7597 unicosmk_gen_dsib (&imask
);
7599 /* Adjust the stack by the frame size. If the frame size is > 4096
7600 bytes, we need to be sure we probe somewhere in the first and last
7601 4096 bytes (we can probably get away without the latter test) and
7602 every 8192 bytes in between. If the frame size is > 32768, we
7603 do this in a loop. Otherwise, we generate the explicit probe
7606 Note that we are only allowed to adjust sp once in the prologue. */
7608 if (frame_size
<= 32768)
7610 if (frame_size
> 4096)
7614 for (probed
= 4096; probed
< frame_size
; probed
+= 8192)
7615 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7619 /* We only have to do this probe if we aren't saving registers. */
7620 if (sa_size
== 0 && frame_size
> probed
- 4096)
7621 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7624 if (frame_size
!= 0)
7625 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7626 GEN_INT (TARGET_ABI_UNICOSMK
7632 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7633 number of 8192 byte blocks to probe. We then probe each block
7634 in the loop and then set SP to the proper location. If the
7635 amount remaining is > 4096, we have to do one more probe if we
7636 are not saving any registers. */
7638 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7639 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7640 rtx ptr
= gen_rtx_REG (DImode
, 22);
7641 rtx count
= gen_rtx_REG (DImode
, 23);
7644 emit_move_insn (count
, GEN_INT (blocks
));
7645 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7646 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7648 /* Because of the difficulty in emitting a new basic block this
7649 late in the compilation, generate the loop as a single insn. */
7650 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7652 if (leftover
> 4096 && sa_size
== 0)
7654 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7655 MEM_VOLATILE_P (last
) = 1;
7656 emit_move_insn (last
, const0_rtx
);
7659 if (TARGET_ABI_WINDOWS_NT
)
7661 /* For NT stack unwind (done by 'reverse execution'), it's
7662 not OK to take the result of a loop, even though the value
7663 is already in ptr, so we reload it via a single operation
7664 and subtract it to sp.
7666 Yes, that's correct -- we have to reload the whole constant
7667 into a temporary via ldah+lda then subtract from sp. */
7669 HOST_WIDE_INT lo
, hi
;
7670 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7671 hi
= frame_size
- lo
;
7673 emit_move_insn (ptr
, GEN_INT (hi
));
7674 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7675 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7680 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7681 GEN_INT (-leftover
)));
7684 /* This alternative is special, because the DWARF code cannot
7685 possibly intuit through the loop above. So we invent this
7686 note it looks at instead. */
7687 RTX_FRAME_RELATED_P (seq
) = 1;
7688 add_reg_note (seq
, REG_FRAME_RELATED_EXPR
,
7689 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7690 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7691 GEN_INT (TARGET_ABI_UNICOSMK
7696 if (!TARGET_ABI_UNICOSMK
)
7698 HOST_WIDE_INT sa_bias
= 0;
7700 /* Cope with very large offsets to the register save area. */
7701 sa_reg
= stack_pointer_rtx
;
7702 if (reg_offset
+ sa_size
> 0x8000)
7704 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7707 if (low
+ sa_size
<= 0x8000)
7708 sa_bias
= reg_offset
- low
, reg_offset
= low
;
7710 sa_bias
= reg_offset
, reg_offset
= 0;
7712 sa_reg
= gen_rtx_REG (DImode
, 24);
7713 sa_bias_rtx
= GEN_INT (sa_bias
);
7715 if (add_operand (sa_bias_rtx
, DImode
))
7716 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_bias_rtx
));
7719 emit_move_insn (sa_reg
, sa_bias_rtx
);
7720 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_reg
));
7724 /* Save regs in stack order. Beginning with VMS PV. */
7725 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7726 emit_frame_store (REG_PV
, stack_pointer_rtx
, 0, 0);
7728 /* Save register RA next. */
7729 if (imask
& (1UL << REG_RA
))
7731 emit_frame_store (REG_RA
, sa_reg
, sa_bias
, reg_offset
);
7732 imask
&= ~(1UL << REG_RA
);
7736 /* Now save any other registers required to be saved. */
7737 for (i
= 0; i
< 31; i
++)
7738 if (imask
& (1UL << i
))
7740 emit_frame_store (i
, sa_reg
, sa_bias
, reg_offset
);
7744 for (i
= 0; i
< 31; i
++)
7745 if (fmask
& (1UL << i
))
7747 emit_frame_store (i
+32, sa_reg
, sa_bias
, reg_offset
);
7751 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7753 /* The standard frame on the T3E includes space for saving registers.
7754 We just have to use it. We don't have to save the return address and
7755 the old frame pointer here - they are saved in the DSIB. */
7758 for (i
= 9; i
< 15; i
++)
7759 if (imask
& (1UL << i
))
7761 emit_frame_store (i
, hard_frame_pointer_rtx
, 0, reg_offset
);
7764 for (i
= 2; i
< 10; i
++)
7765 if (fmask
& (1UL << i
))
7767 emit_frame_store (i
+32, hard_frame_pointer_rtx
, 0, reg_offset
);
7772 if (TARGET_ABI_OPEN_VMS
)
7774 /* Register frame procedures save the fp. */
7775 if (alpha_procedure_type
== PT_REGISTER
)
7777 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7778 hard_frame_pointer_rtx
);
7779 add_reg_note (insn
, REG_CFA_REGISTER
, NULL
);
7780 RTX_FRAME_RELATED_P (insn
) = 1;
7783 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7784 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7785 gen_rtx_REG (DImode
, REG_PV
)));
7787 if (alpha_procedure_type
!= PT_NULL
7788 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7789 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7791 /* If we have to allocate space for outgoing args, do it now. */
7792 if (crtl
->outgoing_args_size
!= 0)
7795 = emit_move_insn (stack_pointer_rtx
,
7797 (hard_frame_pointer_rtx
,
7799 (crtl
->outgoing_args_size
))));
7801 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7802 if ! frame_pointer_needed. Setting the bit will change the CFA
7803 computation rule to use sp again, which would be wrong if we had
7804 frame_pointer_needed, as this means sp might move unpredictably
7808 frame_pointer_needed
7809 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7811 crtl->outgoing_args_size != 0
7812 => alpha_procedure_type != PT_NULL,
7814 so when we are not setting the bit here, we are guaranteed to
7815 have emitted an FRP frame pointer update just before. */
7816 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7819 else if (!TARGET_ABI_UNICOSMK
)
7821 /* If we need a frame pointer, set it from the stack pointer. */
7822 if (frame_pointer_needed
)
7824 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7825 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7827 /* This must always be the last instruction in the
7828 prologue, thus we emit a special move + clobber. */
7829 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7830 stack_pointer_rtx
, sa_reg
)));
7834 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7835 the prologue, for exception handling reasons, we cannot do this for
7836 any insn that might fault. We could prevent this for mems with a
7837 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7838 have to prevent all such scheduling with a blockage.
7840 Linux, on the other hand, never bothered to implement OSF/1's
7841 exception handling, and so doesn't care about such things. Anyone
7842 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7844 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7845 emit_insn (gen_blockage ());
7848 /* Count the number of .file directives, so that .loc is up to date. */
7849 int num_source_filenames
= 0;
7851 /* Output the textual info surrounding the prologue. */
7854 alpha_start_function (FILE *file
, const char *fnname
,
7855 tree decl ATTRIBUTE_UNUSED
)
7857 unsigned long imask
= 0;
7858 unsigned long fmask
= 0;
7859 /* Stack space needed for pushing registers clobbered by us. */
7860 HOST_WIDE_INT sa_size
;
7861 /* Complete stack size needed. */
7862 unsigned HOST_WIDE_INT frame_size
;
7863 /* The maximum debuggable frame size (512 Kbytes using Tru64 as). */
7864 unsigned HOST_WIDE_INT max_frame_size
= TARGET_ABI_OSF
&& !TARGET_GAS
7867 /* Offset from base reg to register save area. */
7868 HOST_WIDE_INT reg_offset
;
7869 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7870 char *tramp_label
= (char *) alloca (strlen (fnname
) + 6);
7873 /* Don't emit an extern directive for functions defined in the same file. */
7874 if (TARGET_ABI_UNICOSMK
)
7877 name_tree
= get_identifier (fnname
);
7878 TREE_ASM_WRITTEN (name_tree
) = 1;
7881 #if TARGET_ABI_OPEN_VMS
7883 && strncmp (vms_debug_main
, fnname
, strlen (vms_debug_main
)) == 0)
7885 targetm
.asm_out
.globalize_label (asm_out_file
, VMS_DEBUG_MAIN_POINTER
);
7886 ASM_OUTPUT_DEF (asm_out_file
, VMS_DEBUG_MAIN_POINTER
, fnname
);
7887 switch_to_section (text_section
);
7888 vms_debug_main
= NULL
;
7892 alpha_fnname
= fnname
;
7893 sa_size
= alpha_sa_size ();
7895 frame_size
= get_frame_size ();
7896 if (TARGET_ABI_OPEN_VMS
)
7897 frame_size
= ALPHA_ROUND (sa_size
7898 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7900 + crtl
->args
.pretend_args_size
);
7901 else if (TARGET_ABI_UNICOSMK
)
7902 frame_size
= ALPHA_ROUND (sa_size
7903 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7904 + ALPHA_ROUND (frame_size
7905 + crtl
->outgoing_args_size
);
7907 frame_size
= (ALPHA_ROUND (crtl
->outgoing_args_size
)
7909 + ALPHA_ROUND (frame_size
7910 + crtl
->args
.pretend_args_size
));
7912 if (TARGET_ABI_OPEN_VMS
)
7915 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
7917 alpha_sa_mask (&imask
, &fmask
);
7919 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7920 We have to do that before the .ent directive as we cannot switch
7921 files within procedures with native ecoff because line numbers are
7922 linked to procedure descriptors.
7923 Outputting the lineno helps debugging of one line functions as they
7924 would otherwise get no line number at all. Please note that we would
7925 like to put out last_linenum from final.c, but it is not accessible. */
7927 if (write_symbols
== SDB_DEBUG
)
7929 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7930 ASM_OUTPUT_SOURCE_FILENAME (file
,
7931 DECL_SOURCE_FILE (current_function_decl
));
7933 #ifdef SDB_OUTPUT_SOURCE_LINE
7934 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7935 SDB_OUTPUT_SOURCE_LINE (file
,
7936 DECL_SOURCE_LINE (current_function_decl
));
7940 /* Issue function start and label. */
7941 if (TARGET_ABI_OPEN_VMS
7942 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7944 fputs ("\t.ent ", file
);
7945 assemble_name (file
, fnname
);
7948 /* If the function needs GP, we'll write the "..ng" label there.
7949 Otherwise, do it here. */
7951 && ! alpha_function_needs_gp
7952 && ! cfun
->is_thunk
)
7955 assemble_name (file
, fnname
);
7956 fputs ("..ng:\n", file
);
7959 /* Nested functions on VMS that are potentially called via trampoline
7960 get a special transfer entry point that loads the called functions
7961 procedure descriptor and static chain. */
7962 if (TARGET_ABI_OPEN_VMS
7963 && !TREE_PUBLIC (decl
)
7964 && DECL_CONTEXT (decl
)
7965 && !TYPE_P (DECL_CONTEXT (decl
)))
7967 strcpy (tramp_label
, fnname
);
7968 strcat (tramp_label
, "..tr");
7969 ASM_OUTPUT_LABEL (file
, tramp_label
);
7970 fprintf (file
, "\tldq $1,24($27)\n");
7971 fprintf (file
, "\tldq $27,16($27)\n");
7974 strcpy (entry_label
, fnname
);
7975 if (TARGET_ABI_OPEN_VMS
)
7976 strcat (entry_label
, "..en");
7978 /* For public functions, the label must be globalized by appending an
7979 additional colon. */
7980 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7981 strcat (entry_label
, ":");
7983 ASM_OUTPUT_LABEL (file
, entry_label
);
7984 inside_function
= TRUE
;
7986 if (TARGET_ABI_OPEN_VMS
)
7987 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7989 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7990 && !flag_inhibit_size_directive
)
7992 /* Set flags in procedure descriptor to request IEEE-conformant
7993 math-library routines. The value we set it to is PDSC_EXC_IEEE
7994 (/usr/include/pdsc.h). */
7995 fputs ("\t.eflag 48\n", file
);
7998 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7999 alpha_auto_offset
= -frame_size
+ crtl
->args
.pretend_args_size
;
8000 alpha_arg_offset
= -frame_size
+ 48;
8002 /* Describe our frame. If the frame size is larger than an integer,
8003 print it as zero to avoid an assembler error. We won't be
8004 properly describing such a frame, but that's the best we can do. */
8005 if (TARGET_ABI_UNICOSMK
)
8007 else if (TARGET_ABI_OPEN_VMS
)
8008 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
8009 HOST_WIDE_INT_PRINT_DEC
"\n",
8011 frame_size
>= (1UL << 31) ? 0 : frame_size
,
8013 else if (!flag_inhibit_size_directive
)
8014 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
8015 (frame_pointer_needed
8016 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
8017 frame_size
>= max_frame_size
? 0 : frame_size
,
8018 crtl
->args
.pretend_args_size
);
8020 /* Describe which registers were spilled. */
8021 if (TARGET_ABI_UNICOSMK
)
8023 else if (TARGET_ABI_OPEN_VMS
)
8026 /* ??? Does VMS care if mask contains ra? The old code didn't
8027 set it, so I don't here. */
8028 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
8030 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
8031 if (alpha_procedure_type
== PT_REGISTER
)
8032 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
8034 else if (!flag_inhibit_size_directive
)
8038 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
8039 frame_size
>= max_frame_size
? 0 : reg_offset
- frame_size
);
8041 for (i
= 0; i
< 32; ++i
)
8042 if (imask
& (1UL << i
))
8047 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
8048 frame_size
>= max_frame_size
? 0 : reg_offset
- frame_size
);
8051 #if TARGET_ABI_OPEN_VMS
8052 /* Ifdef'ed cause link_section are only available then. */
8053 switch_to_section (readonly_data_section
);
8054 fprintf (file
, "\t.align 3\n");
8055 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
8056 fputs ("\t.ascii \"", file
);
8057 assemble_name (file
, fnname
);
8058 fputs ("\\0\"\n", file
);
8059 alpha_need_linkage (fnname
, 1);
8060 switch_to_section (text_section
);
8064 /* Emit the .prologue note at the scheduled end of the prologue. */
8067 alpha_output_function_end_prologue (FILE *file
)
8069 if (TARGET_ABI_UNICOSMK
)
8071 else if (TARGET_ABI_OPEN_VMS
)
8072 fputs ("\t.prologue\n", file
);
8073 else if (TARGET_ABI_WINDOWS_NT
)
8074 fputs ("\t.prologue 0\n", file
);
8075 else if (!flag_inhibit_size_directive
)
8076 fprintf (file
, "\t.prologue %d\n",
8077 alpha_function_needs_gp
|| cfun
->is_thunk
);
8080 /* Write function epilogue. */
8083 alpha_expand_epilogue (void)
8085 /* Registers to save. */
8086 unsigned long imask
= 0;
8087 unsigned long fmask
= 0;
8088 /* Stack space needed for pushing registers clobbered by us. */
8089 HOST_WIDE_INT sa_size
;
8090 /* Complete stack size needed. */
8091 HOST_WIDE_INT frame_size
;
8092 /* Offset from base reg to register save area. */
8093 HOST_WIDE_INT reg_offset
;
8094 int fp_is_frame_pointer
, fp_offset
;
8095 rtx sa_reg
, sa_reg_exp
= NULL
;
8096 rtx sp_adj1
, sp_adj2
, mem
, reg
, insn
;
8098 rtx cfa_restores
= NULL_RTX
;
8101 sa_size
= alpha_sa_size ();
8103 frame_size
= get_frame_size ();
8104 if (TARGET_ABI_OPEN_VMS
)
8105 frame_size
= ALPHA_ROUND (sa_size
8106 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
8108 + crtl
->args
.pretend_args_size
);
8109 else if (TARGET_ABI_UNICOSMK
)
8110 frame_size
= ALPHA_ROUND (sa_size
8111 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
8112 + ALPHA_ROUND (frame_size
8113 + crtl
->outgoing_args_size
);
8115 frame_size
= (ALPHA_ROUND (crtl
->outgoing_args_size
)
8117 + ALPHA_ROUND (frame_size
8118 + crtl
->args
.pretend_args_size
));
8120 if (TARGET_ABI_OPEN_VMS
)
8122 if (alpha_procedure_type
== PT_STACK
)
8128 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
8130 alpha_sa_mask (&imask
, &fmask
);
8133 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
8134 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
8136 sa_reg
= stack_pointer_rtx
;
8138 if (crtl
->calls_eh_return
)
8139 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
8143 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
8145 /* If we have a frame pointer, restore SP from it. */
8146 if ((TARGET_ABI_OPEN_VMS
8147 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
8148 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
8149 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
8151 /* Cope with very large offsets to the register save area. */
8152 if (reg_offset
+ sa_size
> 0x8000)
8154 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
8157 if (low
+ sa_size
<= 0x8000)
8158 bias
= reg_offset
- low
, reg_offset
= low
;
8160 bias
= reg_offset
, reg_offset
= 0;
8162 sa_reg
= gen_rtx_REG (DImode
, 22);
8163 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
8165 emit_move_insn (sa_reg
, sa_reg_exp
);
8168 /* Restore registers in order, excepting a true frame pointer. */
8170 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
8172 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8173 reg
= gen_rtx_REG (DImode
, REG_RA
);
8174 emit_move_insn (reg
, mem
);
8175 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8178 imask
&= ~(1UL << REG_RA
);
8180 for (i
= 0; i
< 31; ++i
)
8181 if (imask
& (1UL << i
))
8183 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
8184 fp_offset
= reg_offset
;
8187 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
8188 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8189 reg
= gen_rtx_REG (DImode
, i
);
8190 emit_move_insn (reg
, mem
);
8191 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8197 for (i
= 0; i
< 31; ++i
)
8198 if (fmask
& (1UL << i
))
8200 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
8201 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8202 reg
= gen_rtx_REG (DFmode
, i
+32);
8203 emit_move_insn (reg
, mem
);
8204 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8208 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
8210 /* Restore callee-saved general-purpose registers. */
8214 for (i
= 9; i
< 15; i
++)
8215 if (imask
& (1UL << i
))
8217 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
8219 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8220 reg
= gen_rtx_REG (DImode
, i
);
8221 emit_move_insn (reg
, mem
);
8222 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8226 for (i
= 2; i
< 10; i
++)
8227 if (fmask
& (1UL << i
))
8229 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
8231 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8232 reg
= gen_rtx_REG (DFmode
, i
+32);
8233 emit_move_insn (reg
, mem
);
8234 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8238 /* Restore the return address from the DSIB. */
8239 mem
= gen_rtx_MEM (DImode
, plus_constant (hard_frame_pointer_rtx
, -8));
8240 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8241 reg
= gen_rtx_REG (DImode
, REG_RA
);
8242 emit_move_insn (reg
, mem
);
8243 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8246 if (frame_size
|| eh_ofs
)
8248 sp_adj1
= stack_pointer_rtx
;
8252 sp_adj1
= gen_rtx_REG (DImode
, 23);
8253 emit_move_insn (sp_adj1
,
8254 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
8257 /* If the stack size is large, begin computation into a temporary
8258 register so as not to interfere with a potential fp restore,
8259 which must be consecutive with an SP restore. */
8260 if (frame_size
< 32768
8261 && ! (TARGET_ABI_UNICOSMK
&& cfun
->calls_alloca
))
8262 sp_adj2
= GEN_INT (frame_size
);
8263 else if (TARGET_ABI_UNICOSMK
)
8265 sp_adj1
= gen_rtx_REG (DImode
, 23);
8266 emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
);
8267 sp_adj2
= const0_rtx
;
8269 else if (frame_size
< 0x40007fffL
)
8271 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
8273 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
8274 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
8278 sp_adj1
= gen_rtx_REG (DImode
, 23);
8279 emit_move_insn (sp_adj1
, sp_adj2
);
8281 sp_adj2
= GEN_INT (low
);
8285 rtx tmp
= gen_rtx_REG (DImode
, 23);
8286 sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3, false);
8289 /* We can't drop new things to memory this late, afaik,
8290 so build it up by pieces. */
8291 sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
8293 gcc_assert (sp_adj2
);
8297 /* From now on, things must be in order. So emit blockages. */
8299 /* Restore the frame pointer. */
8300 if (TARGET_ABI_UNICOSMK
)
8302 emit_insn (gen_blockage ());
8303 mem
= gen_rtx_MEM (DImode
,
8304 plus_constant (hard_frame_pointer_rtx
, -16));
8305 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8306 emit_move_insn (hard_frame_pointer_rtx
, mem
);
8307 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8308 hard_frame_pointer_rtx
, cfa_restores
);
8310 else if (fp_is_frame_pointer
)
8312 emit_insn (gen_blockage ());
8313 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
8314 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8315 emit_move_insn (hard_frame_pointer_rtx
, mem
);
8316 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8317 hard_frame_pointer_rtx
, cfa_restores
);
8319 else if (TARGET_ABI_OPEN_VMS
)
8321 emit_insn (gen_blockage ());
8322 emit_move_insn (hard_frame_pointer_rtx
,
8323 gen_rtx_REG (DImode
, vms_save_fp_regno
));
8324 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8325 hard_frame_pointer_rtx
, cfa_restores
);
8328 /* Restore the stack pointer. */
8329 emit_insn (gen_blockage ());
8330 if (sp_adj2
== const0_rtx
)
8331 insn
= emit_move_insn (stack_pointer_rtx
, sp_adj1
);
8333 insn
= emit_move_insn (stack_pointer_rtx
,
8334 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
));
8335 REG_NOTES (insn
) = cfa_restores
;
8336 add_reg_note (insn
, REG_CFA_DEF_CFA
, stack_pointer_rtx
);
8337 RTX_FRAME_RELATED_P (insn
) = 1;
8341 gcc_assert (cfa_restores
== NULL
);
8343 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8345 emit_insn (gen_blockage ());
8346 insn
= emit_move_insn (hard_frame_pointer_rtx
,
8347 gen_rtx_REG (DImode
, vms_save_fp_regno
));
8348 add_reg_note (insn
, REG_CFA_RESTORE
, hard_frame_pointer_rtx
);
8349 RTX_FRAME_RELATED_P (insn
) = 1;
8351 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8353 /* Decrement the frame pointer if the function does not have a
8355 emit_insn (gen_blockage ());
8356 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8357 hard_frame_pointer_rtx
, constm1_rtx
));
8362 /* Output the rest of the textual info surrounding the epilogue. */
8365 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
8369 /* We output a nop after noreturn calls at the very end of the function to
8370 ensure that the return address always remains in the caller's code range,
8371 as not doing so might confuse unwinding engines. */
8372 insn
= get_last_insn ();
8374 insn
= prev_active_insn (insn
);
8376 output_asm_insn (get_insn_template (CODE_FOR_nop
, NULL
), NULL
);
8380 free_after_compilation (cfun
);
8383 #if TARGET_ABI_OPEN_VMS
8384 alpha_write_linkage (file
, fnname
, decl
);
8387 /* End the function. */
8388 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8390 fputs ("\t.end ", file
);
8391 assemble_name (file
, fnname
);
8394 inside_function
= FALSE
;
8396 /* Output jump tables and the static subroutine information block. */
8397 if (TARGET_ABI_UNICOSMK
)
8399 unicosmk_output_ssib (file
, fnname
);
8400 unicosmk_output_deferred_case_vectors (file
);
8405 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8407 In order to avoid the hordes of differences between generated code
8408 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8409 lots of code loading up large constants, generate rtl and emit it
8410 instead of going straight to text.
8412 Not sure why this idea hasn't been explored before... */
8415 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8416 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8419 HOST_WIDE_INT hi
, lo
;
8420 rtx this_rtx
, insn
, funexp
;
8422 gcc_assert (cfun
->is_thunk
);
8424 /* We always require a valid GP. */
8425 emit_insn (gen_prologue_ldgp ());
8426 emit_note (NOTE_INSN_PROLOGUE_END
);
8428 /* Find the "this" pointer. If the function returns a structure,
8429 the structure return pointer is in $16. */
8430 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8431 this_rtx
= gen_rtx_REG (Pmode
, 17);
8433 this_rtx
= gen_rtx_REG (Pmode
, 16);
8435 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8436 entire constant for the add. */
8437 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8438 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8439 if (hi
+ lo
== delta
)
8442 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, GEN_INT (hi
)));
8444 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, GEN_INT (lo
)));
8448 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8449 delta
, -(delta
< 0));
8450 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
8453 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8458 tmp
= gen_rtx_REG (Pmode
, 0);
8459 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
8461 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8462 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8463 if (hi
+ lo
== vcall_offset
)
8466 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8470 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8471 vcall_offset
, -(vcall_offset
< 0));
8472 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8476 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8479 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8481 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
8484 /* Generate a tail call to the target function. */
8485 if (! TREE_USED (function
))
8487 assemble_external (function
);
8488 TREE_USED (function
) = 1;
8490 funexp
= XEXP (DECL_RTL (function
), 0);
8491 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8492 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8493 SIBLING_CALL_P (insn
) = 1;
8495 /* Run just enough of rest_of_compilation to get the insns emitted.
8496 There's not really enough bulk here to make other passes such as
8497 instruction scheduling worth while. Note that use_thunk calls
8498 assemble_start_function and assemble_end_function. */
8499 insn
= get_insns ();
8500 insn_locators_alloc ();
8501 shorten_branches (insn
);
8502 final_start_function (insn
, file
, 1);
8503 final (insn
, file
, 1);
8504 final_end_function ();
8506 #endif /* TARGET_ABI_OSF */
8508 /* Debugging support. */
8512 /* Count the number of sdb related labels are generated (to find block
8513 start and end boundaries). */
8515 int sdb_label_count
= 0;
8517 /* Name of the file containing the current function. */
8519 static const char *current_function_file
= "";
8521 /* Offsets to alpha virtual arg/local debugging pointers. */
8523 long alpha_arg_offset
;
8524 long alpha_auto_offset
;
8526 /* Emit a new filename to a stream. */
8529 alpha_output_filename (FILE *stream
, const char *name
)
8531 static int first_time
= TRUE
;
8536 ++num_source_filenames
;
8537 current_function_file
= name
;
8538 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8539 output_quoted_string (stream
, name
);
8540 fprintf (stream
, "\n");
8541 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8542 fprintf (stream
, "\t#@stabs\n");
8545 else if (write_symbols
== DBX_DEBUG
)
8546 /* dbxout.c will emit an appropriate .stabs directive. */
8549 else if (name
!= current_function_file
8550 && strcmp (name
, current_function_file
) != 0)
8552 if (inside_function
&& ! TARGET_GAS
)
8553 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8556 ++num_source_filenames
;
8557 current_function_file
= name
;
8558 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8561 output_quoted_string (stream
, name
);
8562 fprintf (stream
, "\n");
8566 /* Structure to show the current status of registers and memory. */
8568 struct shadow_summary
8571 unsigned int i
: 31; /* Mask of int regs */
8572 unsigned int fp
: 31; /* Mask of fp regs */
8573 unsigned int mem
: 1; /* mem == imem | fpmem */
8577 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8578 to the summary structure. SET is nonzero if the insn is setting the
8579 object, otherwise zero. */
8582 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8584 const char *format_ptr
;
8590 switch (GET_CODE (x
))
8592 /* ??? Note that this case would be incorrect if the Alpha had a
8593 ZERO_EXTRACT in SET_DEST. */
8595 summarize_insn (SET_SRC (x
), sum
, 0);
8596 summarize_insn (SET_DEST (x
), sum
, 1);
8600 summarize_insn (XEXP (x
, 0), sum
, 1);
8604 summarize_insn (XEXP (x
, 0), sum
, 0);
8608 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8609 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8613 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8614 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8618 summarize_insn (SUBREG_REG (x
), sum
, 0);
8623 int regno
= REGNO (x
);
8624 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8626 if (regno
== 31 || regno
== 63)
8632 sum
->defd
.i
|= mask
;
8634 sum
->defd
.fp
|= mask
;
8639 sum
->used
.i
|= mask
;
8641 sum
->used
.fp
|= mask
;
8652 /* Find the regs used in memory address computation: */
8653 summarize_insn (XEXP (x
, 0), sum
, 0);
8656 case CONST_INT
: case CONST_DOUBLE
:
8657 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8658 case SCRATCH
: case ASM_INPUT
:
8661 /* Handle common unary and binary ops for efficiency. */
8662 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8663 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8664 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8665 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8666 case NE
: case EQ
: case GE
: case GT
: case LE
:
8667 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8668 summarize_insn (XEXP (x
, 0), sum
, 0);
8669 summarize_insn (XEXP (x
, 1), sum
, 0);
8672 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8673 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8674 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8675 case SQRT
: case FFS
:
8676 summarize_insn (XEXP (x
, 0), sum
, 0);
8680 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8681 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8682 switch (format_ptr
[i
])
8685 summarize_insn (XEXP (x
, i
), sum
, 0);
8689 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8690 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8702 /* Ensure a sufficient number of `trapb' insns are in the code when
8703 the user requests code with a trap precision of functions or
8706 In naive mode, when the user requests a trap-precision of
8707 "instruction", a trapb is needed after every instruction that may
8708 generate a trap. This ensures that the code is resumption safe but
8711 When optimizations are turned on, we delay issuing a trapb as long
8712 as possible. In this context, a trap shadow is the sequence of
8713 instructions that starts with a (potentially) trap generating
8714 instruction and extends to the next trapb or call_pal instruction
8715 (but GCC never generates call_pal by itself). We can delay (and
8716 therefore sometimes omit) a trapb subject to the following
8719 (a) On entry to the trap shadow, if any Alpha register or memory
8720 location contains a value that is used as an operand value by some
8721 instruction in the trap shadow (live on entry), then no instruction
8722 in the trap shadow may modify the register or memory location.
8724 (b) Within the trap shadow, the computation of the base register
8725 for a memory load or store instruction may not involve using the
8726 result of an instruction that might generate an UNPREDICTABLE
8729 (c) Within the trap shadow, no register may be used more than once
8730 as a destination register. (This is to make life easier for the
8733 (d) The trap shadow may not include any branch instructions. */
8736 alpha_handle_trap_shadows (void)
8738 struct shadow_summary shadow
;
8739 int trap_pending
, exception_nesting
;
8743 exception_nesting
= 0;
8746 shadow
.used
.mem
= 0;
8747 shadow
.defd
= shadow
.used
;
8749 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8753 switch (NOTE_KIND (i
))
8755 case NOTE_INSN_EH_REGION_BEG
:
8756 exception_nesting
++;
8761 case NOTE_INSN_EH_REGION_END
:
8762 exception_nesting
--;
8767 case NOTE_INSN_EPILOGUE_BEG
:
8768 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8773 else if (trap_pending
)
8775 if (alpha_tp
== ALPHA_TP_FUNC
)
8778 && GET_CODE (PATTERN (i
)) == RETURN
)
8781 else if (alpha_tp
== ALPHA_TP_INSN
)
8785 struct shadow_summary sum
;
8790 sum
.defd
= sum
.used
;
8792 switch (GET_CODE (i
))
8795 /* Annoyingly, get_attr_trap will die on these. */
8796 if (GET_CODE (PATTERN (i
)) == USE
8797 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8800 summarize_insn (PATTERN (i
), &sum
, 0);
8802 if ((sum
.defd
.i
& shadow
.defd
.i
)
8803 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8805 /* (c) would be violated */
8809 /* Combine shadow with summary of current insn: */
8810 shadow
.used
.i
|= sum
.used
.i
;
8811 shadow
.used
.fp
|= sum
.used
.fp
;
8812 shadow
.used
.mem
|= sum
.used
.mem
;
8813 shadow
.defd
.i
|= sum
.defd
.i
;
8814 shadow
.defd
.fp
|= sum
.defd
.fp
;
8815 shadow
.defd
.mem
|= sum
.defd
.mem
;
8817 if ((sum
.defd
.i
& shadow
.used
.i
)
8818 || (sum
.defd
.fp
& shadow
.used
.fp
)
8819 || (sum
.defd
.mem
& shadow
.used
.mem
))
8821 /* (a) would be violated (also takes care of (b)) */
8822 gcc_assert (get_attr_trap (i
) != TRAP_YES
8823 || (!(sum
.defd
.i
& sum
.used
.i
)
8824 && !(sum
.defd
.fp
& sum
.used
.fp
)));
8842 n
= emit_insn_before (gen_trapb (), i
);
8843 PUT_MODE (n
, TImode
);
8844 PUT_MODE (i
, TImode
);
8848 shadow
.used
.mem
= 0;
8849 shadow
.defd
= shadow
.used
;
8854 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8855 && NONJUMP_INSN_P (i
)
8856 && GET_CODE (PATTERN (i
)) != USE
8857 && GET_CODE (PATTERN (i
)) != CLOBBER
8858 && get_attr_trap (i
) == TRAP_YES
)
8860 if (optimize
&& !trap_pending
)
8861 summarize_insn (PATTERN (i
), &shadow
, 0);
8867 /* Alpha can only issue instruction groups simultaneously if they are
8868 suitably aligned. This is very processor-specific. */
8869 /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe
8870 that are marked "fake". These instructions do not exist on that target,
8871 but it is possible to see these insns with deranged combinations of
8872 command-line options, such as "-mtune=ev4 -mmax". Instead of aborting,
8873 choose a result at random. */
8875 enum alphaev4_pipe
{
8882 enum alphaev5_pipe
{
8893 static enum alphaev4_pipe
8894 alphaev4_insn_pipe (rtx insn
)
8896 if (recog_memoized (insn
) < 0)
8898 if (get_attr_length (insn
) != 4)
8901 switch (get_attr_type (insn
))
8917 case TYPE_MVI
: /* fake */
8932 case TYPE_FSQRT
: /* fake */
8933 case TYPE_FTOI
: /* fake */
8934 case TYPE_ITOF
: /* fake */
8942 static enum alphaev5_pipe
8943 alphaev5_insn_pipe (rtx insn
)
8945 if (recog_memoized (insn
) < 0)
8947 if (get_attr_length (insn
) != 4)
8950 switch (get_attr_type (insn
))
8970 case TYPE_FTOI
: /* fake */
8971 case TYPE_ITOF
: /* fake */
8986 case TYPE_FSQRT
: /* fake */
8997 /* IN_USE is a mask of the slots currently filled within the insn group.
8998 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8999 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
9001 LEN is, of course, the length of the group in bytes. */
9004 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
9011 || GET_CODE (PATTERN (insn
)) == CLOBBER
9012 || GET_CODE (PATTERN (insn
)) == USE
)
9017 enum alphaev4_pipe pipe
;
9019 pipe
= alphaev4_insn_pipe (insn
);
9023 /* Force complex instructions to start new groups. */
9027 /* If this is a completely unrecognized insn, it's an asm.
9028 We don't know how long it is, so record length as -1 to
9029 signal a needed realignment. */
9030 if (recog_memoized (insn
) < 0)
9033 len
= get_attr_length (insn
);
9037 if (in_use
& EV4_IB0
)
9039 if (in_use
& EV4_IB1
)
9044 in_use
|= EV4_IB0
| EV4_IBX
;
9048 if (in_use
& EV4_IB0
)
9050 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
9058 if (in_use
& EV4_IB1
)
9068 /* Haifa doesn't do well scheduling branches. */
9073 insn
= next_nonnote_insn (insn
);
9075 if (!insn
|| ! INSN_P (insn
))
9078 /* Let Haifa tell us where it thinks insn group boundaries are. */
9079 if (GET_MODE (insn
) == TImode
)
9082 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9087 insn
= next_nonnote_insn (insn
);
9095 /* IN_USE is a mask of the slots currently filled within the insn group.
9096 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
9097 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
9099 LEN is, of course, the length of the group in bytes. */
9102 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
9109 || GET_CODE (PATTERN (insn
)) == CLOBBER
9110 || GET_CODE (PATTERN (insn
)) == USE
)
9115 enum alphaev5_pipe pipe
;
9117 pipe
= alphaev5_insn_pipe (insn
);
9121 /* Force complex instructions to start new groups. */
9125 /* If this is a completely unrecognized insn, it's an asm.
9126 We don't know how long it is, so record length as -1 to
9127 signal a needed realignment. */
9128 if (recog_memoized (insn
) < 0)
9131 len
= get_attr_length (insn
);
9134 /* ??? Most of the places below, we would like to assert never
9135 happen, as it would indicate an error either in Haifa, or
9136 in the scheduling description. Unfortunately, Haifa never
9137 schedules the last instruction of the BB, so we don't have
9138 an accurate TI bit to go off. */
9140 if (in_use
& EV5_E0
)
9142 if (in_use
& EV5_E1
)
9147 in_use
|= EV5_E0
| EV5_E01
;
9151 if (in_use
& EV5_E0
)
9153 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
9161 if (in_use
& EV5_E1
)
9167 if (in_use
& EV5_FA
)
9169 if (in_use
& EV5_FM
)
9174 in_use
|= EV5_FA
| EV5_FAM
;
9178 if (in_use
& EV5_FA
)
9184 if (in_use
& EV5_FM
)
9197 /* Haifa doesn't do well scheduling branches. */
9198 /* ??? If this is predicted not-taken, slotting continues, except
9199 that no more IBR, FBR, or JSR insns may be slotted. */
9204 insn
= next_nonnote_insn (insn
);
9206 if (!insn
|| ! INSN_P (insn
))
9209 /* Let Haifa tell us where it thinks insn group boundaries are. */
9210 if (GET_MODE (insn
) == TImode
)
9213 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9218 insn
= next_nonnote_insn (insn
);
9227 alphaev4_next_nop (int *pin_use
)
9229 int in_use
= *pin_use
;
9232 if (!(in_use
& EV4_IB0
))
9237 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
9242 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
9255 alphaev5_next_nop (int *pin_use
)
9257 int in_use
= *pin_use
;
9260 if (!(in_use
& EV5_E1
))
9265 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
9270 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
9282 /* The instruction group alignment main loop. */
9285 alpha_align_insns (unsigned int max_align
,
9286 rtx (*next_group
) (rtx
, int *, int *),
9287 rtx (*next_nop
) (int *))
9289 /* ALIGN is the known alignment for the insn group. */
9291 /* OFS is the offset of the current insn in the insn group. */
9293 int prev_in_use
, in_use
, len
, ldgp
;
9296 /* Let shorten branches care for assigning alignments to code labels. */
9297 shorten_branches (get_insns ());
9299 if (align_functions
< 4)
9301 else if ((unsigned int) align_functions
< max_align
)
9302 align
= align_functions
;
9306 ofs
= prev_in_use
= 0;
9309 i
= next_nonnote_insn (i
);
9311 ldgp
= alpha_function_needs_gp
? 8 : 0;
9315 next
= (*next_group
) (i
, &in_use
, &len
);
9317 /* When we see a label, resync alignment etc. */
9320 unsigned int new_align
= 1 << label_to_alignment (i
);
9322 if (new_align
>= align
)
9324 align
= new_align
< max_align
? new_align
: max_align
;
9328 else if (ofs
& (new_align
-1))
9329 ofs
= (ofs
| (new_align
-1)) + 1;
9333 /* Handle complex instructions special. */
9334 else if (in_use
== 0)
9336 /* Asms will have length < 0. This is a signal that we have
9337 lost alignment knowledge. Assume, however, that the asm
9338 will not mis-align instructions. */
9347 /* If the known alignment is smaller than the recognized insn group,
9348 realign the output. */
9349 else if ((int) align
< len
)
9351 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9354 where
= prev
= prev_nonnote_insn (i
);
9355 if (!where
|| !LABEL_P (where
))
9358 /* Can't realign between a call and its gp reload. */
9359 if (! (TARGET_EXPLICIT_RELOCS
9360 && prev
&& CALL_P (prev
)))
9362 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9363 align
= 1 << new_log_align
;
9368 /* We may not insert padding inside the initial ldgp sequence. */
9372 /* If the group won't fit in the same INT16 as the previous,
9373 we need to add padding to keep the group together. Rather
9374 than simply leaving the insn filling to the assembler, we
9375 can make use of the knowledge of what sorts of instructions
9376 were issued in the previous group to make sure that all of
9377 the added nops are really free. */
9378 else if (ofs
+ len
> (int) align
)
9380 int nop_count
= (align
- ofs
) / 4;
9383 /* Insert nops before labels, branches, and calls to truly merge
9384 the execution of the nops with the previous instruction group. */
9385 where
= prev_nonnote_insn (i
);
9388 if (LABEL_P (where
))
9390 rtx where2
= prev_nonnote_insn (where
);
9391 if (where2
&& JUMP_P (where2
))
9394 else if (NONJUMP_INSN_P (where
))
9401 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9402 while (--nop_count
);
9406 ofs
= (ofs
+ len
) & (align
- 1);
9407 prev_in_use
= in_use
;
9412 /* Insert an unop between a noreturn function call and GP load. */
9415 alpha_pad_noreturn (void)
9419 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9422 || !find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
9425 next
= next_active_insn (insn
);
9429 rtx pat
= PATTERN (next
);
9431 if (GET_CODE (pat
) == SET
9432 && GET_CODE (SET_SRC (pat
)) == UNSPEC_VOLATILE
9433 && XINT (SET_SRC (pat
), 1) == UNSPECV_LDGP1
)
9434 emit_insn_after (gen_unop (), insn
);
9439 /* Machine dependent reorg pass. */
9444 /* Workaround for a linker error that triggers when an
9445 exception handler immediatelly follows a noreturn function.
9447 The instruction stream from an object file:
9449 54: 00 40 5b 6b jsr ra,(t12),58 <__func+0x58>
9450 58: 00 00 ba 27 ldah gp,0(ra)
9451 5c: 00 00 bd 23 lda gp,0(gp)
9452 60: 00 00 7d a7 ldq t12,0(gp)
9453 64: 00 40 5b 6b jsr ra,(t12),68 <__func+0x68>
9455 was converted in the final link pass to:
9457 fdb24: a0 03 40 d3 bsr ra,fe9a8 <_called_func+0x8>
9458 fdb28: 00 00 fe 2f unop
9459 fdb2c: 00 00 fe 2f unop
9460 fdb30: 30 82 7d a7 ldq t12,-32208(gp)
9461 fdb34: 00 40 5b 6b jsr ra,(t12),fdb38 <__func+0x68>
9463 GP load instructions were wrongly cleared by the linker relaxation
9464 pass. This workaround prevents removal of GP loads by inserting
9465 an unop instruction between a noreturn function call and
9466 exception handler prologue. */
9468 if (current_function_has_exception_handlers ())
9469 alpha_pad_noreturn ();
9471 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9472 alpha_handle_trap_shadows ();
9474 /* Due to the number of extra trapb insns, don't bother fixing up
9475 alignment when trap precision is instruction. Moreover, we can
9476 only do our job when sched2 is run. */
9477 if (optimize
&& !optimize_size
9478 && alpha_tp
!= ALPHA_TP_INSN
9479 && flag_schedule_insns_after_reload
)
9481 if (alpha_tune
== PROCESSOR_EV4
)
9482 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
9483 else if (alpha_tune
== PROCESSOR_EV5
)
9484 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
9488 #if !TARGET_ABI_UNICOSMK
9495 alpha_file_start (void)
9497 #ifdef OBJECT_FORMAT_ELF
9498 /* If emitting dwarf2 debug information, we cannot generate a .file
9499 directive to start the file, as it will conflict with dwarf2out
9500 file numbers. So it's only useful when emitting mdebug output. */
9501 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
9504 default_file_start ();
9506 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
9509 fputs ("\t.set noreorder\n", asm_out_file
);
9510 fputs ("\t.set volatile\n", asm_out_file
);
9511 if (!TARGET_ABI_OPEN_VMS
)
9512 fputs ("\t.set noat\n", asm_out_file
);
9513 if (TARGET_EXPLICIT_RELOCS
)
9514 fputs ("\t.set nomacro\n", asm_out_file
);
9515 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
9519 if (alpha_cpu
== PROCESSOR_EV6
|| TARGET_FIX
|| TARGET_CIX
)
9521 else if (TARGET_MAX
)
9523 else if (TARGET_BWX
)
9525 else if (alpha_cpu
== PROCESSOR_EV5
)
9530 fprintf (asm_out_file
, "\t.arch %s\n", arch
);
9535 #ifdef OBJECT_FORMAT_ELF
9536 /* Since we don't have a .dynbss section, we should not allow global
9537 relocations in the .rodata section. */
9540 alpha_elf_reloc_rw_mask (void)
9542 return flag_pic
? 3 : 2;
9545 /* Return a section for X. The only special thing we do here is to
9546 honor small data. */
9549 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
9550 unsigned HOST_WIDE_INT align
)
9552 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9553 /* ??? Consider using mergeable sdata sections. */
9554 return sdata_section
;
9556 return default_elf_select_rtx_section (mode
, x
, align
);
9560 alpha_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
9562 unsigned int flags
= 0;
9564 if (strcmp (name
, ".sdata") == 0
9565 || strncmp (name
, ".sdata.", 7) == 0
9566 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
9567 || strcmp (name
, ".sbss") == 0
9568 || strncmp (name
, ".sbss.", 6) == 0
9569 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
9570 flags
= SECTION_SMALL
;
9572 flags
|= default_section_type_flags (decl
, name
, reloc
);
9575 #endif /* OBJECT_FORMAT_ELF */
9577 /* Structure to collect function names for final output in link section. */
9578 /* Note that items marked with GTY can't be ifdef'ed out. */
9580 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9581 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9583 struct GTY(()) alpha_links
9587 enum links_kind lkind
;
9588 enum reloc_kind rkind
;
9591 struct GTY(()) alpha_funcs
9594 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9598 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9599 splay_tree alpha_links_tree
;
9600 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9601 splay_tree alpha_funcs_tree
;
9603 static GTY(()) int alpha_funcs_num
;
9605 #if TARGET_ABI_OPEN_VMS
9607 /* Return the VMS argument type corresponding to MODE. */
9610 alpha_arg_type (enum machine_mode mode
)
9615 return TARGET_FLOAT_VAX
? FF
: FS
;
9617 return TARGET_FLOAT_VAX
? FD
: FT
;
9623 /* Return an rtx for an integer representing the VMS Argument Information
9627 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9629 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9632 for (i
= 0; i
< 6; i
++)
9633 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9635 return GEN_INT (regval
);
9638 /* Make (or fake) .linkage entry for function call.
9640 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9642 Return an SYMBOL_REF rtx for the linkage. */
9645 alpha_need_linkage (const char *name
, int is_local
)
9647 splay_tree_node node
;
9648 struct alpha_links
*al
;
9655 struct alpha_funcs
*cfaf
;
9657 if (!alpha_funcs_tree
)
9658 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9659 splay_tree_compare_pointers
);
9661 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9664 cfaf
->num
= ++alpha_funcs_num
;
9666 splay_tree_insert (alpha_funcs_tree
,
9667 (splay_tree_key
) current_function_decl
,
9668 (splay_tree_value
) cfaf
);
9671 if (alpha_links_tree
)
9673 /* Is this name already defined? */
9675 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9678 al
= (struct alpha_links
*) node
->value
;
9681 /* Defined here but external assumed. */
9682 if (al
->lkind
== KIND_EXTERN
)
9683 al
->lkind
= KIND_LOCAL
;
9687 /* Used here but unused assumed. */
9688 if (al
->lkind
== KIND_UNUSED
)
9689 al
->lkind
= KIND_LOCAL
;
9695 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9697 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9698 name
= ggc_strdup (name
);
9700 /* Assume external if no definition. */
9701 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9703 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9704 get_identifier (name
);
9706 /* Construct a SYMBOL_REF for us to call. */
9708 size_t name_len
= strlen (name
);
9709 char *linksym
= XALLOCAVEC (char, name_len
+ 6);
9711 memcpy (linksym
+ 1, name
, name_len
);
9712 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9713 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9714 ggc_alloc_string (linksym
, name_len
+ 5));
9717 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9718 (splay_tree_value
) al
);
9724 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9726 splay_tree_node cfunnode
;
9727 struct alpha_funcs
*cfaf
;
9728 struct alpha_links
*al
;
9729 const char *name
= XSTR (linkage
, 0);
9731 cfaf
= (struct alpha_funcs
*) 0;
9732 al
= (struct alpha_links
*) 0;
9734 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9735 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9739 splay_tree_node lnode
;
9741 /* Is this name already defined? */
9743 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9745 al
= (struct alpha_links
*) lnode
->value
;
9748 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9756 splay_tree_node node
= 0;
9757 struct alpha_links
*anl
;
9762 name_len
= strlen (name
);
9764 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9765 al
->num
= cfaf
->num
;
9767 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9770 anl
= (struct alpha_links
*) node
->value
;
9771 al
->lkind
= anl
->lkind
;
9774 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9775 buflen
= strlen (buf
);
9776 linksym
= XALLOCAVEC (char, buflen
+ 1);
9777 memcpy (linksym
, buf
, buflen
+ 1);
9779 al
->linkage
= gen_rtx_SYMBOL_REF
9780 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9782 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9783 (splay_tree_value
) al
);
9787 al
->rkind
= KIND_CODEADDR
;
9789 al
->rkind
= KIND_LINKAGE
;
9792 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9798 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9800 const char *const name
= (const char *) node
->key
;
9801 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9802 FILE *stream
= (FILE *) data
;
9804 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9805 if (link
->rkind
== KIND_CODEADDR
)
9807 if (link
->lkind
== KIND_LOCAL
)
9809 /* Local and used */
9810 fprintf (stream
, "\t.quad %s..en\n", name
);
9814 /* External and used, request code address. */
9815 fprintf (stream
, "\t.code_address %s\n", name
);
9820 if (link
->lkind
== KIND_LOCAL
)
9822 /* Local and used, build linkage pair. */
9823 fprintf (stream
, "\t.quad %s..en\n", name
);
9824 fprintf (stream
, "\t.quad %s\n", name
);
9828 /* External and used, request linkage pair. */
9829 fprintf (stream
, "\t.linkage %s\n", name
);
9837 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9839 splay_tree_node node
;
9840 struct alpha_funcs
*func
;
9842 fprintf (stream
, "\t.link\n");
9843 fprintf (stream
, "\t.align 3\n");
9846 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9847 func
= (struct alpha_funcs
*) node
->value
;
9849 fputs ("\t.name ", stream
);
9850 assemble_name (stream
, funname
);
9851 fputs ("..na\n", stream
);
9852 ASM_OUTPUT_LABEL (stream
, funname
);
9853 fprintf (stream
, "\t.pdesc ");
9854 assemble_name (stream
, funname
);
9855 fprintf (stream
, "..en,%s\n",
9856 alpha_procedure_type
== PT_STACK
? "stack"
9857 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9861 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9862 /* splay_tree_delete (func->links); */
9866 /* Given a decl, a section name, and whether the decl initializer
9867 has relocs, choose attributes for the section. */
9869 #define SECTION_VMS_OVERLAY SECTION_FORGET
9870 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9871 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9874 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9876 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9878 if (decl
&& DECL_ATTRIBUTES (decl
)
9879 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9880 flags
|= SECTION_VMS_OVERLAY
;
9881 if (decl
&& DECL_ATTRIBUTES (decl
)
9882 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9883 flags
|= SECTION_VMS_GLOBAL
;
9884 if (decl
&& DECL_ATTRIBUTES (decl
)
9885 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9886 flags
|= SECTION_VMS_INITIALIZE
;
9891 /* Switch to an arbitrary section NAME with attributes as specified
9892 by FLAGS. ALIGN specifies any known alignment requirements for
9893 the section; 0 if the default should be used. */
9896 vms_asm_named_section (const char *name
, unsigned int flags
,
9897 tree decl ATTRIBUTE_UNUSED
)
9899 fputc ('\n', asm_out_file
);
9900 fprintf (asm_out_file
, ".section\t%s", name
);
9902 if (flags
& SECTION_VMS_OVERLAY
)
9903 fprintf (asm_out_file
, ",OVR");
9904 if (flags
& SECTION_VMS_GLOBAL
)
9905 fprintf (asm_out_file
, ",GBL");
9906 if (flags
& SECTION_VMS_INITIALIZE
)
9907 fprintf (asm_out_file
, ",NOMOD");
9908 if (flags
& SECTION_DEBUG
)
9909 fprintf (asm_out_file
, ",NOWRT");
9911 fputc ('\n', asm_out_file
);
9914 /* Record an element in the table of global constructors. SYMBOL is
9915 a SYMBOL_REF of the function to be called; PRIORITY is a number
9916 between 0 and MAX_INIT_PRIORITY.
9918 Differs from default_ctors_section_asm_out_constructor in that the
9919 width of the .ctors entry is always 64 bits, rather than the 32 bits
9920 used by a normal pointer. */
9923 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9925 switch_to_section (ctors_section
);
9926 assemble_align (BITS_PER_WORD
);
9927 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9931 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9933 switch_to_section (dtors_section
);
9934 assemble_align (BITS_PER_WORD
);
9935 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9940 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9941 int is_local ATTRIBUTE_UNUSED
)
9947 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9948 tree cfundecl ATTRIBUTE_UNUSED
,
9949 int lflag ATTRIBUTE_UNUSED
,
9950 int rflag ATTRIBUTE_UNUSED
)
9955 #endif /* TARGET_ABI_OPEN_VMS */
9957 #if TARGET_ABI_UNICOSMK
9959 /* This evaluates to true if we do not know how to pass TYPE solely in
9960 registers. This is the case for all arguments that do not fit in two
9964 unicosmk_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
9969 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9971 if (TREE_ADDRESSABLE (type
))
9974 return ALPHA_ARG_SIZE (mode
, type
, 0) > 2;
9977 /* Define the offset between two registers, one to be eliminated, and the
9978 other its replacement, at the start of a routine. */
9981 unicosmk_initial_elimination_offset (int from
, int to
)
9985 fixed_size
= alpha_sa_size();
9986 if (fixed_size
!= 0)
9989 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9991 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9993 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9994 return (ALPHA_ROUND (crtl
->outgoing_args_size
)
9995 + ALPHA_ROUND (get_frame_size()));
9996 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9997 return (ALPHA_ROUND (fixed_size
)
9998 + ALPHA_ROUND (get_frame_size()
9999 + crtl
->outgoing_args_size
));
10001 gcc_unreachable ();
10004 /* Output the module name for .ident and .end directives. We have to strip
10005 directories and add make sure that the module name starts with a letter
10009 unicosmk_output_module_name (FILE *file
)
10011 const char *name
= lbasename (main_input_filename
);
10012 unsigned len
= strlen (name
);
10013 char *clean_name
= alloca (len
+ 2);
10014 char *ptr
= clean_name
;
10016 /* CAM only accepts module names that start with a letter or '$'. We
10017 prefix the module name with a '$' if necessary. */
10019 if (!ISALPHA (*name
))
10021 memcpy (ptr
, name
, len
+ 1);
10022 clean_symbol_name (clean_name
);
10023 fputs (clean_name
, file
);
10026 /* Output the definition of a common variable. */
10029 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
10032 printf ("T3E__: common %s\n", name
);
10035 fputs("\t.endp\n\n\t.psect ", file
);
10036 assemble_name(file
, name
);
10037 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
10038 fprintf(file
, "\t.byte\t0:%d\n", size
);
10040 /* Mark the symbol as defined in this module. */
10041 name_tree
= get_identifier (name
);
10042 TREE_ASM_WRITTEN (name_tree
) = 1;
10045 #define SECTION_PUBLIC SECTION_MACH_DEP
10046 #define SECTION_MAIN (SECTION_PUBLIC << 1)
10047 static int current_section_align
;
10049 /* A get_unnamed_section callback for switching to the text section. */
10052 unicosmk_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
10054 static int count
= 0;
10055 fprintf (asm_out_file
, "\t.endp\n\n\t.psect\tgcc@text___%d,code\n", count
++);
10058 /* A get_unnamed_section callback for switching to the data section. */
10061 unicosmk_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
10063 static int count
= 1;
10064 fprintf (asm_out_file
, "\t.endp\n\n\t.psect\tgcc@data___%d,data\n", count
++);
10067 /* Implement TARGET_ASM_INIT_SECTIONS.
10069 The Cray assembler is really weird with respect to sections. It has only
10070 named sections and you can't reopen a section once it has been closed.
10071 This means that we have to generate unique names whenever we want to
10072 reenter the text or the data section. */
10075 unicosmk_init_sections (void)
10077 text_section
= get_unnamed_section (SECTION_CODE
,
10078 unicosmk_output_text_section_asm_op
,
10080 data_section
= get_unnamed_section (SECTION_WRITE
,
10081 unicosmk_output_data_section_asm_op
,
10083 readonly_data_section
= data_section
;
10086 static unsigned int
10087 unicosmk_section_type_flags (tree decl
, const char *name
,
10088 int reloc ATTRIBUTE_UNUSED
)
10090 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
10095 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10097 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10098 if (align_functions_log
> current_section_align
)
10099 current_section_align
= align_functions_log
;
10101 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
10102 flags
|= SECTION_MAIN
;
10105 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
10107 if (TREE_PUBLIC (decl
))
10108 flags
|= SECTION_PUBLIC
;
10113 /* Generate a section name for decl and associate it with the
10117 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
10124 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
10125 name
= default_strip_name_encoding (name
);
10126 len
= strlen (name
);
10128 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10132 /* It is essential that we prefix the section name here because
10133 otherwise the section names generated for constructors and
10134 destructors confuse collect2. */
10136 string
= alloca (len
+ 6);
10137 sprintf (string
, "code@%s", name
);
10138 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
10140 else if (TREE_PUBLIC (decl
))
10141 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
10146 string
= alloca (len
+ 6);
10147 sprintf (string
, "data@%s", name
);
10148 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
10152 /* Switch to an arbitrary section NAME with attributes as specified
10153 by FLAGS. ALIGN specifies any known alignment requirements for
10154 the section; 0 if the default should be used. */
10157 unicosmk_asm_named_section (const char *name
, unsigned int flags
,
10158 tree decl ATTRIBUTE_UNUSED
)
10162 /* Close the previous section. */
10164 fputs ("\t.endp\n\n", asm_out_file
);
10166 /* Find out what kind of section we are opening. */
10168 if (flags
& SECTION_MAIN
)
10169 fputs ("\t.start\tmain\n", asm_out_file
);
10171 if (flags
& SECTION_CODE
)
10173 else if (flags
& SECTION_PUBLIC
)
10178 if (current_section_align
!= 0)
10179 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
10180 current_section_align
, kind
);
10182 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
10186 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
10189 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
10190 unicosmk_unique_section (decl
, 0);
10193 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
10194 in code sections because .align fill unused space with zeroes. */
10197 unicosmk_output_align (FILE *file
, int align
)
10199 if (inside_function
)
10200 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
10202 fprintf (file
, "\t.align\t%d\n", align
);
10205 /* Add a case vector to the current function's list of deferred case
10206 vectors. Case vectors have to be put into a separate section because CAM
10207 does not allow data definitions in code sections. */
10210 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
10212 struct machine_function
*machine
= cfun
->machine
;
10214 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
10215 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
10216 machine
->addr_list
);
10219 /* Output a case vector. */
10222 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
10224 rtx lab
= XEXP (vec
, 0);
10225 rtx body
= XEXP (vec
, 1);
10226 int vlen
= XVECLEN (body
, 0);
10229 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
10231 for (idx
= 0; idx
< vlen
; idx
++)
10233 ASM_OUTPUT_ADDR_VEC_ELT
10234 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10238 /* Output current function's deferred case vectors. */
10241 unicosmk_output_deferred_case_vectors (FILE *file
)
10243 struct machine_function
*machine
= cfun
->machine
;
10246 if (machine
->addr_list
== NULL_RTX
)
10249 switch_to_section (data_section
);
10250 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
10251 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
10254 /* Generate the name of the SSIB section for the current function. */
10256 #define SSIB_PREFIX "__SSIB_"
10257 #define SSIB_PREFIX_LEN 7
10259 static const char *
10260 unicosmk_ssib_name (void)
10262 /* This is ok since CAM won't be able to deal with names longer than that
10265 static char name
[256];
10268 const char *fnname
;
10271 x
= DECL_RTL (cfun
->decl
);
10272 gcc_assert (MEM_P (x
));
10274 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
10275 fnname
= XSTR (x
, 0);
10277 len
= strlen (fnname
);
10278 if (len
+ SSIB_PREFIX_LEN
> 255)
10279 len
= 255 - SSIB_PREFIX_LEN
;
10281 strcpy (name
, SSIB_PREFIX
);
10282 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
10283 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10288 /* Set up the dynamic subprogram information block (DSIB) and update the
10289 frame pointer register ($15) for subroutines which have a frame. If the
10290 subroutine doesn't have a frame, simply increment $15. */
10293 unicosmk_gen_dsib (unsigned long *imaskP
)
10295 if (alpha_procedure_type
== PT_STACK
)
10297 const char *ssib_name
;
10300 /* Allocate 64 bytes for the DSIB. */
10302 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10304 emit_insn (gen_blockage ());
10306 /* Save the return address. */
10308 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
10309 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10310 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
10311 (*imaskP
) &= ~(1UL << REG_RA
);
10313 /* Save the old frame pointer. */
10315 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
10316 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10317 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
10318 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
10320 emit_insn (gen_blockage ());
10322 /* Store the SSIB pointer. */
10324 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
10325 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
10326 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10328 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
10329 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
10330 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
10332 /* Save the CIW index. */
10334 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
10335 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10336 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
10338 emit_insn (gen_blockage ());
10340 /* Set the new frame pointer. */
10341 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10342 stack_pointer_rtx
, GEN_INT (64))));
10346 /* Increment the frame pointer register to indicate that we do not
10348 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10349 hard_frame_pointer_rtx
, const1_rtx
));
10353 /* Output the static subroutine information block for the current
10357 unicosmk_output_ssib (FILE *file
, const char *fnname
)
10363 struct machine_function
*machine
= cfun
->machine
;
10366 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10367 unicosmk_ssib_name ());
10369 /* Some required stuff and the function name length. */
10371 len
= strlen (fnname
);
10372 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10375 ??? We don't do that yet. */
10377 fputs ("\t.quad\t0\n", file
);
10379 /* Function address. */
10381 fputs ("\t.quad\t", file
);
10382 assemble_name (file
, fnname
);
10385 fputs ("\t.quad\t0\n", file
);
10386 fputs ("\t.quad\t0\n", file
);
10389 ??? We do it the same way Cray CC does it but this could be
10392 for( i
= 0; i
< len
; i
++ )
10393 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10394 if( (len
% 8) == 0 )
10395 fputs ("\t.quad\t0\n", file
);
10397 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10399 /* All call information words used in the function. */
10401 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10404 #if HOST_BITS_PER_WIDE_INT == 32
10405 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
10406 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10408 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
10413 /* Add a call information word (CIW) to the list of the current function's
10414 CIWs and return its index.
10416 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10419 unicosmk_add_call_info_word (rtx x
)
10422 struct machine_function
*machine
= cfun
->machine
;
10424 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10425 if (machine
->first_ciw
== NULL_RTX
)
10426 machine
->first_ciw
= node
;
10428 XEXP (machine
->last_ciw
, 1) = node
;
10430 machine
->last_ciw
= node
;
10431 ++machine
->ciw_count
;
10433 return GEN_INT (machine
->ciw_count
10434 + strlen (current_function_name ())/8 + 5);
10437 /* The Cray assembler doesn't accept extern declarations for symbols which
10438 are defined in the same file. We have to keep track of all global
10439 symbols which are referenced and/or defined in a source file and output
10440 extern declarations for those which are referenced but not defined at
10441 the end of file. */
10443 /* List of identifiers for which an extern declaration might have to be
10445 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10447 struct unicosmk_extern_list
10449 struct unicosmk_extern_list
*next
;
10453 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10455 /* Output extern declarations which are required for every asm file. */
10458 unicosmk_output_default_externs (FILE *file
)
10460 static const char *const externs
[] =
10461 { "__T3E_MISMATCH" };
10466 n
= ARRAY_SIZE (externs
);
10468 for (i
= 0; i
< n
; i
++)
10469 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10472 /* Output extern declarations for global symbols which are have been
10473 referenced but not defined. */
10476 unicosmk_output_externs (FILE *file
)
10478 struct unicosmk_extern_list
*p
;
10479 const char *real_name
;
10483 len
= strlen (user_label_prefix
);
10484 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10486 /* We have to strip the encoding and possibly remove user_label_prefix
10487 from the identifier in order to handle -fleading-underscore and
10488 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10489 real_name
= default_strip_name_encoding (p
->name
);
10490 if (len
&& p
->name
[0] == '*'
10491 && !memcmp (real_name
, user_label_prefix
, len
))
10494 name_tree
= get_identifier (real_name
);
10495 if (! TREE_ASM_WRITTEN (name_tree
))
10497 TREE_ASM_WRITTEN (name_tree
) = 1;
10498 fputs ("\t.extern\t", file
);
10499 assemble_name (file
, p
->name
);
10505 /* Record an extern. */
10508 unicosmk_add_extern (const char *name
)
10510 struct unicosmk_extern_list
*p
;
10512 p
= (struct unicosmk_extern_list
*)
10513 xmalloc (sizeof (struct unicosmk_extern_list
));
10514 p
->next
= unicosmk_extern_head
;
10516 unicosmk_extern_head
= p
;
10519 /* The Cray assembler generates incorrect code if identifiers which
10520 conflict with register names are used as instruction operands. We have
10521 to replace such identifiers with DEX expressions. */
10523 /* Structure to collect identifiers which have been replaced by DEX
10525 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10527 struct unicosmk_dex
{
10528 struct unicosmk_dex
*next
;
10532 /* List of identifiers which have been replaced by DEX expressions. The DEX
10533 number is determined by the position in the list. */
10535 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10537 /* The number of elements in the DEX list. */
10539 static int unicosmk_dex_count
= 0;
10541 /* Check if NAME must be replaced by a DEX expression. */
10544 unicosmk_special_name (const char *name
)
10546 if (name
[0] == '*')
10549 if (name
[0] == '$')
10552 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10557 case '1': case '2':
10558 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10561 return (name
[2] == '\0'
10562 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10565 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10569 /* Return the DEX number if X must be replaced by a DEX expression and 0
10573 unicosmk_need_dex (rtx x
)
10575 struct unicosmk_dex
*dex
;
10579 if (GET_CODE (x
) != SYMBOL_REF
)
10583 if (! unicosmk_special_name (name
))
10586 i
= unicosmk_dex_count
;
10587 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10589 if (! strcmp (name
, dex
->name
))
10594 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10596 dex
->next
= unicosmk_dex_list
;
10597 unicosmk_dex_list
= dex
;
10599 ++unicosmk_dex_count
;
10600 return unicosmk_dex_count
;
10603 /* Output the DEX definitions for this file. */
10606 unicosmk_output_dex (FILE *file
)
10608 struct unicosmk_dex
*dex
;
10611 if (unicosmk_dex_list
== NULL
)
10614 fprintf (file
, "\t.dexstart\n");
10616 i
= unicosmk_dex_count
;
10617 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10619 fprintf (file
, "\tDEX (%d) = ", i
);
10620 assemble_name (file
, dex
->name
);
10625 fprintf (file
, "\t.dexend\n");
10628 /* Output text that to appear at the beginning of an assembler file. */
10631 unicosmk_file_start (void)
10635 fputs ("\t.ident\t", asm_out_file
);
10636 unicosmk_output_module_name (asm_out_file
);
10637 fputs ("\n\n", asm_out_file
);
10639 /* The Unicos/Mk assembler uses different register names. Instead of trying
10640 to support them, we simply use micro definitions. */
10642 /* CAM has different register names: rN for the integer register N and fN
10643 for the floating-point register N. Instead of trying to use these in
10644 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10647 for (i
= 0; i
< 32; ++i
)
10648 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
10650 for (i
= 0; i
< 32; ++i
)
10651 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
10653 putc ('\n', asm_out_file
);
10655 /* The .align directive fill unused space with zeroes which does not work
10656 in code sections. We define the macro 'gcc@code@align' which uses nops
10657 instead. Note that it assumes that code sections always have the
10658 biggest possible alignment since . refers to the current offset from
10659 the beginning of the section. */
10661 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
10662 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
10663 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
10664 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
10665 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
10666 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
10667 fputs ("\t.endr\n", asm_out_file
);
10668 fputs ("\t.endif\n", asm_out_file
);
10669 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
10671 /* Output extern declarations which should always be visible. */
10672 unicosmk_output_default_externs (asm_out_file
);
10674 /* Open a dummy section. We always need to be inside a section for the
10675 section-switching code to work correctly.
10676 ??? This should be a module id or something like that. I still have to
10677 figure out what the rules for those are. */
10678 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10681 /* Output text to appear at the end of an assembler file. This includes all
10682 pending extern declarations and DEX expressions. */
10685 unicosmk_file_end (void)
10687 fputs ("\t.endp\n\n", asm_out_file
);
10689 /* Output all pending externs. */
10691 unicosmk_output_externs (asm_out_file
);
10693 /* Output dex definitions used for functions whose names conflict with
10696 unicosmk_output_dex (asm_out_file
);
10698 fputs ("\t.end\t", asm_out_file
);
10699 unicosmk_output_module_name (asm_out_file
);
10700 putc ('\n', asm_out_file
);
10706 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10710 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10714 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10715 const char * fnname ATTRIBUTE_UNUSED
)
10719 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10725 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10730 #endif /* TARGET_ABI_UNICOSMK */
10733 alpha_init_libfuncs (void)
10735 if (TARGET_ABI_UNICOSMK
)
10737 /* Prevent gcc from generating calls to __divsi3. */
10738 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10739 set_optab_libfunc (udiv_optab
, SImode
, 0);
10741 /* Use the functions provided by the system library
10742 for DImode integer division. */
10743 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10744 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10746 else if (TARGET_ABI_OPEN_VMS
)
10748 /* Use the VMS runtime library functions for division and
10750 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10751 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10752 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10753 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10754 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10755 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10756 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10757 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10762 /* Initialize the GCC target structure. */
10763 #if TARGET_ABI_OPEN_VMS
10764 # undef TARGET_ATTRIBUTE_TABLE
10765 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10766 # undef TARGET_SECTION_TYPE_FLAGS
10767 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10770 #undef TARGET_IN_SMALL_DATA_P
10771 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10773 #if TARGET_ABI_UNICOSMK
10774 # undef TARGET_INSERT_ATTRIBUTES
10775 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10776 # undef TARGET_SECTION_TYPE_FLAGS
10777 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10778 # undef TARGET_ASM_UNIQUE_SECTION
10779 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10780 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
10781 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
10782 # undef TARGET_ASM_GLOBALIZE_LABEL
10783 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10784 # undef TARGET_MUST_PASS_IN_STACK
10785 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
10788 #undef TARGET_ASM_ALIGNED_HI_OP
10789 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10790 #undef TARGET_ASM_ALIGNED_DI_OP
10791 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10793 /* Default unaligned ops are provided for ELF systems. To get unaligned
10794 data for non-ELF systems, we have to turn off auto alignment. */
10795 #if !defined (OBJECT_FORMAT_ELF) || TARGET_ABI_OPEN_VMS
10796 #undef TARGET_ASM_UNALIGNED_HI_OP
10797 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10798 #undef TARGET_ASM_UNALIGNED_SI_OP
10799 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10800 #undef TARGET_ASM_UNALIGNED_DI_OP
10801 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10804 #ifdef OBJECT_FORMAT_ELF
10805 #undef TARGET_ASM_RELOC_RW_MASK
10806 #define TARGET_ASM_RELOC_RW_MASK alpha_elf_reloc_rw_mask
10807 #undef TARGET_ASM_SELECT_RTX_SECTION
10808 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10809 #undef TARGET_SECTION_TYPE_FLAGS
10810 #define TARGET_SECTION_TYPE_FLAGS alpha_elf_section_type_flags
10813 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10814 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10816 #undef TARGET_INIT_LIBFUNCS
10817 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10819 #undef TARGET_LEGITIMIZE_ADDRESS
10820 #define TARGET_LEGITIMIZE_ADDRESS alpha_legitimize_address
10822 #if TARGET_ABI_UNICOSMK
10823 #undef TARGET_ASM_FILE_START
10824 #define TARGET_ASM_FILE_START unicosmk_file_start
10825 #undef TARGET_ASM_FILE_END
10826 #define TARGET_ASM_FILE_END unicosmk_file_end
10828 #undef TARGET_ASM_FILE_START
10829 #define TARGET_ASM_FILE_START alpha_file_start
10830 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10831 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10834 #undef TARGET_SCHED_ADJUST_COST
10835 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10836 #undef TARGET_SCHED_ISSUE_RATE
10837 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10838 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10839 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10840 alpha_multipass_dfa_lookahead
10842 #undef TARGET_HAVE_TLS
10843 #define TARGET_HAVE_TLS HAVE_AS_TLS
10845 #undef TARGET_INIT_BUILTINS
10846 #define TARGET_INIT_BUILTINS alpha_init_builtins
10847 #undef TARGET_EXPAND_BUILTIN
10848 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10849 #undef TARGET_FOLD_BUILTIN
10850 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
10852 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10853 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10854 #undef TARGET_CANNOT_COPY_INSN_P
10855 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10856 #undef TARGET_CANNOT_FORCE_CONST_MEM
10857 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
10860 #undef TARGET_ASM_OUTPUT_MI_THUNK
10861 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10862 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10863 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10864 #undef TARGET_STDARG_OPTIMIZE_HOOK
10865 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
10868 #undef TARGET_RTX_COSTS
10869 #define TARGET_RTX_COSTS alpha_rtx_costs
10870 #undef TARGET_ADDRESS_COST
10871 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
10873 #undef TARGET_MACHINE_DEPENDENT_REORG
10874 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10876 #undef TARGET_PROMOTE_FUNCTION_MODE
10877 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
10878 #undef TARGET_PROMOTE_PROTOTYPES
10879 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_false
10880 #undef TARGET_RETURN_IN_MEMORY
10881 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10882 #undef TARGET_PASS_BY_REFERENCE
10883 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
10884 #undef TARGET_SETUP_INCOMING_VARARGS
10885 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10886 #undef TARGET_STRICT_ARGUMENT_NAMING
10887 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10888 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10889 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10890 #undef TARGET_SPLIT_COMPLEX_ARG
10891 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10892 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10893 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10894 #undef TARGET_ARG_PARTIAL_BYTES
10895 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
10897 #undef TARGET_SECONDARY_RELOAD
10898 #define TARGET_SECONDARY_RELOAD alpha_secondary_reload
10900 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10901 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
10902 #undef TARGET_VECTOR_MODE_SUPPORTED_P
10903 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
10905 #undef TARGET_BUILD_BUILTIN_VA_LIST
10906 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10908 #undef TARGET_EXPAND_BUILTIN_VA_START
10909 #define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start
10911 /* The Alpha architecture does not require sequential consistency. See
10912 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
10913 for an example of how it can be violated in practice. */
10914 #undef TARGET_RELAXED_ORDERING
10915 #define TARGET_RELAXED_ORDERING true
10917 #undef TARGET_DEFAULT_TARGET_FLAGS
10918 #define TARGET_DEFAULT_TARGET_FLAGS \
10919 (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
10920 #undef TARGET_HANDLE_OPTION
10921 #define TARGET_HANDLE_OPTION alpha_handle_option
10923 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10924 #undef TARGET_MANGLE_TYPE
10925 #define TARGET_MANGLE_TYPE alpha_mangle_type
10928 #undef TARGET_LEGITIMATE_ADDRESS_P
10929 #define TARGET_LEGITIMATE_ADDRESS_P alpha_legitimate_address_p
10931 struct gcc_target targetm
= TARGET_INITIALIZER
;
10934 #include "gt-alpha.h"