1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
55 /* Specify which cpu to schedule for. */
57 enum processor_type alpha_cpu
;
58 static const char * const alpha_cpu_name
[] =
63 /* Specify how accurate floating-point traps need to be. */
65 enum alpha_trap_precision alpha_tp
;
67 /* Specify the floating-point rounding mode. */
69 enum alpha_fp_rounding_mode alpha_fprm
;
71 /* Specify which things cause traps. */
73 enum alpha_fp_trap_mode alpha_fptm
;
75 /* Specify bit size of immediate TLS offsets. */
77 int alpha_tls_size
= 32;
79 /* Strings decoded into the above options. */
81 const char *alpha_cpu_string
; /* -mcpu= */
82 const char *alpha_tune_string
; /* -mtune= */
83 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
84 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
85 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
86 const char *alpha_mlat_string
; /* -mmemory-latency= */
87 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
89 /* Save information from a "cmpxx" operation until the branch or scc is
92 struct alpha_compare alpha_compare
;
94 /* Nonzero if inside of a function, because the Alpha asm can't
95 handle .files inside of functions. */
97 static int inside_function
= FALSE
;
99 /* The number of cycles of latency we should assume on memory reads. */
101 int alpha_memory_latency
= 3;
103 /* Whether the function needs the GP. */
105 static int alpha_function_needs_gp
;
107 /* The alias set for prologue/epilogue register save/restore. */
109 static GTY(()) int alpha_sr_alias_set
;
111 /* The assembler name of the current function. */
113 static const char *alpha_fnname
;
115 /* The next explicit relocation sequence number. */
116 extern GTY(()) int alpha_next_sequence_number
;
117 int alpha_next_sequence_number
= 1;
119 /* The literal and gpdisp sequence numbers for this insn, as printed
120 by %# and %* respectively. */
121 extern GTY(()) int alpha_this_literal_sequence_number
;
122 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
123 int alpha_this_literal_sequence_number
;
124 int alpha_this_gpdisp_sequence_number
;
126 /* Costs of various operations on the different architectures. */
128 struct alpha_rtx_cost_data
130 unsigned char fp_add
;
131 unsigned char fp_mult
;
132 unsigned char fp_div_sf
;
133 unsigned char fp_div_df
;
134 unsigned char int_mult_si
;
135 unsigned char int_mult_di
;
136 unsigned char int_shift
;
137 unsigned char int_cmov
;
140 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
143 COSTS_N_INSNS (6), /* fp_add */
144 COSTS_N_INSNS (6), /* fp_mult */
145 COSTS_N_INSNS (34), /* fp_div_sf */
146 COSTS_N_INSNS (63), /* fp_div_df */
147 COSTS_N_INSNS (23), /* int_mult_si */
148 COSTS_N_INSNS (23), /* int_mult_di */
149 COSTS_N_INSNS (2), /* int_shift */
150 COSTS_N_INSNS (2), /* int_cmov */
153 COSTS_N_INSNS (4), /* fp_add */
154 COSTS_N_INSNS (4), /* fp_mult */
155 COSTS_N_INSNS (15), /* fp_div_sf */
156 COSTS_N_INSNS (22), /* fp_div_df */
157 COSTS_N_INSNS (8), /* int_mult_si */
158 COSTS_N_INSNS (12), /* int_mult_di */
159 COSTS_N_INSNS (1) + 1, /* int_shift */
160 COSTS_N_INSNS (1), /* int_cmov */
163 COSTS_N_INSNS (4), /* fp_add */
164 COSTS_N_INSNS (4), /* fp_mult */
165 COSTS_N_INSNS (12), /* fp_div_sf */
166 COSTS_N_INSNS (15), /* fp_div_df */
167 COSTS_N_INSNS (7), /* int_mult_si */
168 COSTS_N_INSNS (7), /* int_mult_di */
169 COSTS_N_INSNS (1), /* int_shift */
170 COSTS_N_INSNS (2), /* int_cmov */
174 /* Declarations of static functions. */
175 static bool alpha_function_ok_for_sibcall
176 PARAMS ((tree
, tree
));
177 static int tls_symbolic_operand_1
178 PARAMS ((rtx
, enum machine_mode
, int, int));
179 static enum tls_model tls_symbolic_operand_type
181 static bool decl_has_samegp
183 static bool alpha_in_small_data_p
185 static rtx get_tls_get_addr
187 static int some_small_symbolic_operand_1
188 PARAMS ((rtx
*, void *));
189 static int split_small_symbolic_operand_1
190 PARAMS ((rtx
*, void *));
191 static bool alpha_cannot_copy_insn_p
193 static bool alpha_rtx_costs
194 PARAMS ((rtx
, int, int, int *));
195 static void alpha_set_memflags_1
196 PARAMS ((rtx
, int, int, int));
197 static rtx alpha_emit_set_const_1
198 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
199 static void alpha_expand_unaligned_load_words
200 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
201 static void alpha_expand_unaligned_store_words
202 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
203 static void alpha_init_builtins
205 static rtx alpha_expand_builtin
206 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
207 static void alpha_sa_mask
208 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
209 static int find_lo_sum_using_gp
210 PARAMS ((rtx
*, void *));
211 static int alpha_does_function_need_gp
213 static int alpha_ra_ever_killed
215 static const char *get_trap_mode_suffix
217 static const char *get_round_mode_suffix
219 static const char *get_some_local_dynamic_name
221 static int get_some_local_dynamic_name_1
222 PARAMS ((rtx
*, void *));
223 static rtx set_frame_related_p
225 static const char *alpha_lookup_xfloating_lib_func
226 PARAMS ((enum rtx_code
));
227 static int alpha_compute_xfloating_mode_arg
228 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
229 static void alpha_emit_xfloating_libcall
230 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
231 static rtx alpha_emit_xfloating_compare
232 PARAMS ((enum rtx_code
, rtx
, rtx
));
233 static void alpha_output_function_end_prologue
235 static int alpha_adjust_cost
236 PARAMS ((rtx
, rtx
, rtx
, int));
237 static int alpha_issue_rate
239 static int alpha_use_dfa_pipeline_interface
241 static int alpha_multipass_dfa_lookahead
244 #ifdef OBJECT_FORMAT_ELF
245 static void alpha_elf_select_rtx_section
246 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
249 #if TARGET_ABI_OPEN_VMS
250 static bool alpha_linkage_symbol_p
251 PARAMS ((const char *symname
));
252 static int alpha_write_one_linkage
253 PARAMS ((splay_tree_node
, void *));
254 static void alpha_write_linkage
255 PARAMS ((FILE *, const char *, tree
));
259 static void alpha_output_mi_thunk_osf
260 PARAMS ((FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
));
263 static struct machine_function
* alpha_init_machine_status
266 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
267 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
268 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
269 static int unicosmk_need_dex
PARAMS ((rtx
));
271 /* Get the number of args of a function in one of two ways. */
272 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
273 #define NUM_ARGS current_function_args_info.num_args
275 #define NUM_ARGS current_function_args_info
281 /* Initialize the GCC target structure. */
282 #if TARGET_ABI_OPEN_VMS
283 const struct attribute_spec vms_attribute_table
[];
284 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
285 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
286 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
287 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
288 # undef TARGET_ATTRIBUTE_TABLE
289 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
290 # undef TARGET_SECTION_TYPE_FLAGS
291 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
294 #undef TARGET_IN_SMALL_DATA_P
295 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
297 #if TARGET_ABI_UNICOSMK
298 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
299 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
300 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
302 static void unicosmk_unique_section
PARAMS ((tree
, int));
303 # undef TARGET_INSERT_ATTRIBUTES
304 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
305 # undef TARGET_SECTION_TYPE_FLAGS
306 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
307 # undef TARGET_ASM_UNIQUE_SECTION
308 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
309 # undef TARGET_ASM_GLOBALIZE_LABEL
310 # define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
313 #undef TARGET_ASM_ALIGNED_HI_OP
314 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
315 #undef TARGET_ASM_ALIGNED_DI_OP
316 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
318 /* Default unaligned ops are provided for ELF systems. To get unaligned
319 data for non-ELF systems, we have to turn off auto alignment. */
320 #ifndef OBJECT_FORMAT_ELF
321 #undef TARGET_ASM_UNALIGNED_HI_OP
322 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
323 #undef TARGET_ASM_UNALIGNED_SI_OP
324 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
325 #undef TARGET_ASM_UNALIGNED_DI_OP
326 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
329 #ifdef OBJECT_FORMAT_ELF
330 #undef TARGET_ASM_SELECT_RTX_SECTION
331 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
334 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
335 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
337 #undef TARGET_SCHED_ADJUST_COST
338 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
339 #undef TARGET_SCHED_ISSUE_RATE
340 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
341 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
342 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
343 alpha_use_dfa_pipeline_interface
344 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
345 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
346 alpha_multipass_dfa_lookahead
348 #undef TARGET_HAVE_TLS
349 #define TARGET_HAVE_TLS HAVE_AS_TLS
351 #undef TARGET_INIT_BUILTINS
352 #define TARGET_INIT_BUILTINS alpha_init_builtins
353 #undef TARGET_EXPAND_BUILTIN
354 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
356 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
357 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
358 #undef TARGET_CANNOT_COPY_INSN_P
359 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
362 #undef TARGET_ASM_OUTPUT_MI_THUNK
363 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
364 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
365 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
368 #undef TARGET_RTX_COSTS
369 #define TARGET_RTX_COSTS alpha_rtx_costs
370 #undef TARGET_ADDRESS_COST
371 #define TARGET_ADDRESS_COST hook_int_rtx_0
373 struct gcc_target targetm
= TARGET_INITIALIZER
;
375 /* Parse target option strings. */
381 static const struct cpu_table
{
382 const char *const name
;
383 const enum processor_type processor
;
386 #define EV5_MASK (MASK_CPU_EV5)
387 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
388 { "ev4", PROCESSOR_EV4
, 0 },
389 { "ev45", PROCESSOR_EV4
, 0 },
390 { "21064", PROCESSOR_EV4
, 0 },
391 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
392 { "21164", PROCESSOR_EV5
, EV5_MASK
},
393 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
394 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
395 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
396 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
397 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
398 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
399 { "21264", PROCESSOR_EV6
, EV6_MASK
},
400 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
401 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
405 /* Unicos/Mk doesn't have shared libraries. */
406 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
408 warning ("-f%s ignored for Unicos/Mk (not supported)",
409 (flag_pic
> 1) ? "PIC" : "pic");
413 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
414 floating-point instructions. Make that the default for this target. */
415 if (TARGET_ABI_UNICOSMK
)
416 alpha_fprm
= ALPHA_FPRM_DYN
;
418 alpha_fprm
= ALPHA_FPRM_NORM
;
420 alpha_tp
= ALPHA_TP_PROG
;
421 alpha_fptm
= ALPHA_FPTM_N
;
423 /* We cannot use su and sui qualifiers for conversion instructions on
424 Unicos/Mk. I'm not sure if this is due to assembler or hardware
425 limitations. Right now, we issue a warning if -mieee is specified
426 and then ignore it; eventually, we should either get it right or
427 disable the option altogether. */
431 if (TARGET_ABI_UNICOSMK
)
432 warning ("-mieee not supported on Unicos/Mk");
435 alpha_tp
= ALPHA_TP_INSN
;
436 alpha_fptm
= ALPHA_FPTM_SU
;
440 if (TARGET_IEEE_WITH_INEXACT
)
442 if (TARGET_ABI_UNICOSMK
)
443 warning ("-mieee-with-inexact not supported on Unicos/Mk");
446 alpha_tp
= ALPHA_TP_INSN
;
447 alpha_fptm
= ALPHA_FPTM_SUI
;
453 if (! strcmp (alpha_tp_string
, "p"))
454 alpha_tp
= ALPHA_TP_PROG
;
455 else if (! strcmp (alpha_tp_string
, "f"))
456 alpha_tp
= ALPHA_TP_FUNC
;
457 else if (! strcmp (alpha_tp_string
, "i"))
458 alpha_tp
= ALPHA_TP_INSN
;
460 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
463 if (alpha_fprm_string
)
465 if (! strcmp (alpha_fprm_string
, "n"))
466 alpha_fprm
= ALPHA_FPRM_NORM
;
467 else if (! strcmp (alpha_fprm_string
, "m"))
468 alpha_fprm
= ALPHA_FPRM_MINF
;
469 else if (! strcmp (alpha_fprm_string
, "c"))
470 alpha_fprm
= ALPHA_FPRM_CHOP
;
471 else if (! strcmp (alpha_fprm_string
,"d"))
472 alpha_fprm
= ALPHA_FPRM_DYN
;
474 error ("bad value `%s' for -mfp-rounding-mode switch",
478 if (alpha_fptm_string
)
480 if (strcmp (alpha_fptm_string
, "n") == 0)
481 alpha_fptm
= ALPHA_FPTM_N
;
482 else if (strcmp (alpha_fptm_string
, "u") == 0)
483 alpha_fptm
= ALPHA_FPTM_U
;
484 else if (strcmp (alpha_fptm_string
, "su") == 0)
485 alpha_fptm
= ALPHA_FPTM_SU
;
486 else if (strcmp (alpha_fptm_string
, "sui") == 0)
487 alpha_fptm
= ALPHA_FPTM_SUI
;
489 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
492 if (alpha_tls_size_string
)
494 if (strcmp (alpha_tls_size_string
, "16") == 0)
496 else if (strcmp (alpha_tls_size_string
, "32") == 0)
498 else if (strcmp (alpha_tls_size_string
, "64") == 0)
501 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
505 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
506 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
508 if (alpha_cpu_string
)
510 for (i
= 0; cpu_table
[i
].name
; i
++)
511 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
513 alpha_cpu
= cpu_table
[i
].processor
;
514 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
515 | MASK_CPU_EV5
| MASK_CPU_EV6
);
516 target_flags
|= cpu_table
[i
].flags
;
519 if (! cpu_table
[i
].name
)
520 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
523 if (alpha_tune_string
)
525 for (i
= 0; cpu_table
[i
].name
; i
++)
526 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
528 alpha_cpu
= cpu_table
[i
].processor
;
531 if (! cpu_table
[i
].name
)
532 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
535 /* Do some sanity checks on the above options. */
537 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
539 warning ("trap mode not supported on Unicos/Mk");
540 alpha_fptm
= ALPHA_FPTM_N
;
543 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
544 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
546 warning ("fp software completion requires -mtrap-precision=i");
547 alpha_tp
= ALPHA_TP_INSN
;
552 /* Except for EV6 pass 1 (not released), we always have precise
553 arithmetic traps. Which means we can do software completion
554 without minding trap shadows. */
555 alpha_tp
= ALPHA_TP_PROG
;
558 if (TARGET_FLOAT_VAX
)
560 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
562 warning ("rounding mode not supported for VAX floats");
563 alpha_fprm
= ALPHA_FPRM_NORM
;
565 if (alpha_fptm
== ALPHA_FPTM_SUI
)
567 warning ("trap mode not supported for VAX floats");
568 alpha_fptm
= ALPHA_FPTM_SU
;
576 if (!alpha_mlat_string
)
577 alpha_mlat_string
= "L1";
579 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
580 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
582 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
583 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
584 && alpha_mlat_string
[2] == '\0')
586 static int const cache_latency
[][4] =
588 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
589 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
590 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
593 lat
= alpha_mlat_string
[1] - '0';
594 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
596 warning ("L%d cache latency unknown for %s",
597 lat
, alpha_cpu_name
[alpha_cpu
]);
601 lat
= cache_latency
[alpha_cpu
][lat
-1];
603 else if (! strcmp (alpha_mlat_string
, "main"))
605 /* Most current memories have about 370ns latency. This is
606 a reasonable guess for a fast cpu. */
611 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
615 alpha_memory_latency
= lat
;
618 /* Default the definition of "small data" to 8 bytes. */
622 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
624 target_flags
|= MASK_SMALL_DATA
;
625 else if (flag_pic
== 2)
626 target_flags
&= ~MASK_SMALL_DATA
;
628 /* Align labels and loops for optimal branching. */
629 /* ??? Kludge these by not doing anything if we don't optimize and also if
630 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
631 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
633 if (align_loops
<= 0)
635 if (align_jumps
<= 0)
638 if (align_functions
<= 0)
639 align_functions
= 16;
641 /* Acquire a unique set number for our register saves and restores. */
642 alpha_sr_alias_set
= new_alias_set ();
644 /* Register variables and functions with the garbage collector. */
646 /* Set up function hooks. */
647 init_machine_status
= alpha_init_machine_status
;
649 /* Tell the compiler when we're using VAX floating point. */
650 if (TARGET_FLOAT_VAX
)
652 real_format_for_mode
[SFmode
- QFmode
] = &vax_f_format
;
653 real_format_for_mode
[DFmode
- QFmode
] = &vax_g_format
;
654 real_format_for_mode
[TFmode
- QFmode
] = NULL
;
658 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
666 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
668 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
674 /* Returns 1 if OP is either the constant zero or a register. If a
675 register, it must be in the proper mode unless MODE is VOIDmode. */
678 reg_or_0_operand (op
, mode
)
680 enum machine_mode mode
;
682 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
685 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
689 reg_or_6bit_operand (op
, mode
)
691 enum machine_mode mode
;
693 return ((GET_CODE (op
) == CONST_INT
694 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
695 || register_operand (op
, mode
));
699 /* Return 1 if OP is an 8-bit constant or any register. */
702 reg_or_8bit_operand (op
, mode
)
704 enum machine_mode mode
;
706 return ((GET_CODE (op
) == CONST_INT
707 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
708 || register_operand (op
, mode
));
711 /* Return 1 if OP is a constant or any register. */
714 reg_or_const_int_operand (op
, mode
)
716 enum machine_mode mode
;
718 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
721 /* Return 1 if OP is an 8-bit constant. */
724 cint8_operand (op
, mode
)
726 enum machine_mode mode ATTRIBUTE_UNUSED
;
728 return ((GET_CODE (op
) == CONST_INT
729 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
732 /* Return 1 if the operand is a valid second operand to an add insn. */
735 add_operand (op
, mode
)
737 enum machine_mode mode
;
739 if (GET_CODE (op
) == CONST_INT
)
740 /* Constraints I, J, O and P are covered by K. */
741 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
742 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
744 return register_operand (op
, mode
);
747 /* Return 1 if the operand is a valid second operand to a sign-extending
751 sext_add_operand (op
, mode
)
753 enum machine_mode mode
;
755 if (GET_CODE (op
) == CONST_INT
)
756 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
757 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
759 return reg_not_elim_operand (op
, mode
);
762 /* Return 1 if OP is the constant 4 or 8. */
765 const48_operand (op
, mode
)
767 enum machine_mode mode ATTRIBUTE_UNUSED
;
769 return (GET_CODE (op
) == CONST_INT
770 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
773 /* Return 1 if OP is a valid first operand to an AND insn. */
776 and_operand (op
, mode
)
778 enum machine_mode mode
;
780 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
781 return (zap_mask (CONST_DOUBLE_LOW (op
))
782 && zap_mask (CONST_DOUBLE_HIGH (op
)));
784 if (GET_CODE (op
) == CONST_INT
)
785 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
786 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
787 || zap_mask (INTVAL (op
)));
789 return register_operand (op
, mode
);
792 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
795 or_operand (op
, mode
)
797 enum machine_mode mode
;
799 if (GET_CODE (op
) == CONST_INT
)
800 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
801 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
803 return register_operand (op
, mode
);
806 /* Return 1 if OP is a constant that is the width, in bits, of an integral
807 mode smaller than DImode. */
810 mode_width_operand (op
, mode
)
812 enum machine_mode mode ATTRIBUTE_UNUSED
;
814 return (GET_CODE (op
) == CONST_INT
815 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
816 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
819 /* Return 1 if OP is a constant that is the width of an integral machine mode
820 smaller than an integer. */
823 mode_mask_operand (op
, mode
)
825 enum machine_mode mode ATTRIBUTE_UNUSED
;
827 if (GET_CODE (op
) == CONST_INT
)
829 HOST_WIDE_INT value
= INTVAL (op
);
835 if (value
== 0xffffffff)
840 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
842 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
849 /* Return 1 if OP is a multiple of 8 less than 64. */
852 mul8_operand (op
, mode
)
854 enum machine_mode mode ATTRIBUTE_UNUSED
;
856 return (GET_CODE (op
) == CONST_INT
857 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
858 && (INTVAL (op
) & 7) == 0);
861 /* Return 1 if OP is the zero constant for MODE. */
864 const0_operand (op
, mode
)
866 enum machine_mode mode
;
868 return op
== CONST0_RTX (mode
);
871 /* Return 1 if OP is a hard floating-point register. */
874 hard_fp_register_operand (op
, mode
)
876 enum machine_mode mode
;
878 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
881 if (GET_CODE (op
) == SUBREG
)
882 op
= SUBREG_REG (op
);
883 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
886 /* Return 1 if OP is a hard general register. */
889 hard_int_register_operand (op
, mode
)
891 enum machine_mode mode
;
893 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
896 if (GET_CODE (op
) == SUBREG
)
897 op
= SUBREG_REG (op
);
898 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
901 /* Return 1 if OP is a register or a constant integer. */
905 reg_or_cint_operand (op
, mode
)
907 enum machine_mode mode
;
909 return (GET_CODE (op
) == CONST_INT
910 || register_operand (op
, mode
));
913 /* Return 1 if OP is something that can be reloaded into a register;
914 if it is a MEM, it need not be valid. */
917 some_operand (op
, mode
)
919 enum machine_mode mode
;
921 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
924 switch (GET_CODE (op
))
938 return some_operand (SUBREG_REG (op
), VOIDmode
);
947 /* Likewise, but don't accept constants. */
950 some_ni_operand (op
, mode
)
952 enum machine_mode mode
;
954 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
957 if (GET_CODE (op
) == SUBREG
)
958 op
= SUBREG_REG (op
);
960 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
963 /* Return 1 if OP is a valid operand for the source of a move insn. */
966 input_operand (op
, mode
)
968 enum machine_mode mode
;
970 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
973 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
976 switch (GET_CODE (op
))
981 if (TARGET_EXPLICIT_RELOCS
)
983 /* We don't split symbolic operands into something unintelligable
984 until after reload, but we do not wish non-small, non-global
985 symbolic operands to be reconstructed from their high/lo_sum
987 return (small_symbolic_operand (op
, mode
)
988 || global_symbolic_operand (op
, mode
)
989 || gotdtp_symbolic_operand (op
, mode
)
990 || gottp_symbolic_operand (op
, mode
));
993 /* This handles both the Windows/NT and OSF cases. */
994 return mode
== ptr_mode
|| mode
== DImode
;
997 return (TARGET_EXPLICIT_RELOCS
998 && local_symbolic_operand (XEXP (op
, 0), mode
));
1005 if (register_operand (op
, mode
))
1007 /* ... fall through ... */
1009 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
1010 && general_operand (op
, mode
));
1014 return op
== CONST0_RTX (mode
);
1017 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
1019 case CONSTANT_P_RTX
:
1029 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
1030 file, and in the same section as the current function. */
1033 samegp_function_operand (op
, mode
)
1035 enum machine_mode mode ATTRIBUTE_UNUSED
;
1037 if (GET_CODE (op
) != SYMBOL_REF
)
1040 /* Easy test for recursion. */
1041 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
1044 /* Functions that are not local can be overridden, and thus may
1045 not share the same gp. */
1046 if (! SYMBOL_REF_LOCAL_P (op
))
1049 /* If -msmall-data is in effect, assume that there is only one GP
1050 for the module, and so any local symbol has this property. We
1051 need explicit relocations to be able to enforce this for symbols
1052 not defined in this unit of translation, however. */
1053 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1056 /* Functions that are not external are defined in this UoT,
1057 and thus must share the same gp. */
1058 return ! SYMBOL_REF_EXTERNAL_P (op
);
1061 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
1064 direct_call_operand (op
, mode
)
1066 enum machine_mode mode
;
1068 tree op_decl
, cfun_sec
, op_sec
;
1070 /* Must share the same GP. */
1071 if (!samegp_function_operand (op
, mode
))
1074 /* If profiling is implemented via linker tricks, we can't jump
1075 to the nogp alternate entry point. Note that current_function_profile
1076 would not be correct, since that doesn't indicate if the target
1077 function uses profiling. */
1078 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
1079 but is approximately correct for the OSF ABIs. Don't know
1080 what to do for VMS, NT, or UMK. */
1081 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
1084 /* Must be a function. In some cases folks create thunks in static
1085 data structures and then make calls to them. If we allow the
1086 direct call, we'll get an error from the linker about !samegp reloc
1087 against a symbol without a .prologue directive. */
1088 if (!SYMBOL_REF_FUNCTION_P (op
))
1091 /* Must be "near" so that the branch is assumed to reach. With
1092 -msmall-text, this is assumed true of all local symbols. Since
1093 we've already checked samegp, locality is already assured. */
1094 if (TARGET_SMALL_TEXT
)
1097 /* Otherwise, a decl is "near" if it is defined in the same section. */
1098 if (flag_function_sections
)
1101 op_decl
= SYMBOL_REF_DECL (op
);
1102 if (DECL_ONE_ONLY (current_function_decl
)
1103 || (op_decl
&& DECL_ONE_ONLY (op_decl
)))
1106 cfun_sec
= DECL_SECTION_NAME (current_function_decl
);
1107 op_sec
= op_decl
? DECL_SECTION_NAME (op_decl
) : NULL
;
1108 return ((!cfun_sec
&& !op_sec
)
1109 || (cfun_sec
&& op_sec
1110 && strcmp (TREE_STRING_POINTER (cfun_sec
),
1111 TREE_STRING_POINTER (op_sec
)) == 0));
1114 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
1115 a (non-tls) variable known to be defined in this file. */
1118 local_symbolic_operand (op
, mode
)
1120 enum machine_mode mode
;
1122 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1125 if (GET_CODE (op
) == LABEL_REF
)
1128 if (GET_CODE (op
) == CONST
1129 && GET_CODE (XEXP (op
, 0)) == PLUS
1130 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1131 op
= XEXP (XEXP (op
, 0), 0);
1133 if (GET_CODE (op
) != SYMBOL_REF
)
1136 return SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
1139 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1140 known to be defined in this file in the small data area. */
1143 small_symbolic_operand (op
, mode
)
1145 enum machine_mode mode ATTRIBUTE_UNUSED
;
1147 if (! TARGET_SMALL_DATA
)
1150 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1153 if (GET_CODE (op
) == CONST
1154 && GET_CODE (XEXP (op
, 0)) == PLUS
1155 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1156 op
= XEXP (XEXP (op
, 0), 0);
1158 if (GET_CODE (op
) != SYMBOL_REF
)
1161 /* ??? There's no encode_section_info equivalent for the rtl
1162 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
1163 if (CONSTANT_POOL_ADDRESS_P (op
))
1164 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1166 return (SYMBOL_REF_LOCAL_P (op
)
1167 && SYMBOL_REF_SMALL_P (op
)
1168 && SYMBOL_REF_TLS_MODEL (op
) == 0);
1171 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1172 not known (or known not) to be defined in this file. */
1175 global_symbolic_operand (op
, mode
)
1177 enum machine_mode mode
;
1179 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1182 if (GET_CODE (op
) == CONST
1183 && GET_CODE (XEXP (op
, 0)) == PLUS
1184 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1185 op
= XEXP (XEXP (op
, 0), 0);
1187 if (GET_CODE (op
) != SYMBOL_REF
)
1190 return !SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
1193 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1196 call_operand (op
, mode
)
1198 enum machine_mode mode
;
1203 if (GET_CODE (op
) == REG
)
1207 /* Disallow virtual registers to cope with pathalogical test cases
1208 such as compile/930117-1.c in which the virtual reg decomposes
1209 to the frame pointer. Which is a hard reg that is not $27. */
1210 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1215 if (TARGET_ABI_UNICOSMK
)
1217 if (GET_CODE (op
) == SYMBOL_REF
)
1223 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1224 possibly with an offset. */
1227 symbolic_operand (op
, mode
)
1229 enum machine_mode mode
;
1231 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1233 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1235 if (GET_CODE (op
) == CONST
1236 && GET_CODE (XEXP (op
,0)) == PLUS
1237 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1238 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1243 /* Return true if OP is valid for a particular TLS relocation. */
1246 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1248 enum machine_mode mode
;
1251 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1254 if (GET_CODE (op
) != CONST
)
1258 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1260 op
= XVECEXP (op
, 0, 0);
1262 if (GET_CODE (op
) != SYMBOL_REF
)
1265 if (SYMBOL_REF_LOCAL_P (op
))
1267 if (alpha_tls_size
> size
)
1276 switch (SYMBOL_REF_TLS_MODEL (op
))
1278 case TLS_MODEL_LOCAL_DYNAMIC
:
1279 return unspec
== UNSPEC_DTPREL
;
1280 case TLS_MODEL_INITIAL_EXEC
:
1281 return unspec
== UNSPEC_TPREL
&& size
== 64;
1282 case TLS_MODEL_LOCAL_EXEC
:
1283 return unspec
== UNSPEC_TPREL
;
1289 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1292 dtp16_symbolic_operand (op
, mode
)
1294 enum machine_mode mode
;
1296 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1299 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1302 dtp32_symbolic_operand (op
, mode
)
1304 enum machine_mode mode
;
1306 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1309 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1312 gotdtp_symbolic_operand (op
, mode
)
1314 enum machine_mode mode
;
1316 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1319 /* Return true if OP is valid for 16-bit TP relative relocations. */
1322 tp16_symbolic_operand (op
, mode
)
1324 enum machine_mode mode
;
1326 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1329 /* Return true if OP is valid for 32-bit TP relative relocations. */
1332 tp32_symbolic_operand (op
, mode
)
1334 enum machine_mode mode
;
1336 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1339 /* Return true if OP is valid for 64-bit TP relative relocations. */
1342 gottp_symbolic_operand (op
, mode
)
1344 enum machine_mode mode
;
1346 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1349 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1350 comparisons are valid in which insn. */
1353 alpha_comparison_operator (op
, mode
)
1355 enum machine_mode mode
;
1357 enum rtx_code code
= GET_CODE (op
);
1359 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1362 return (code
== EQ
|| code
== LE
|| code
== LT
1363 || code
== LEU
|| code
== LTU
);
1366 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1367 Here we know which comparisons are valid in which insn. */
1370 alpha_zero_comparison_operator (op
, mode
)
1372 enum machine_mode mode
;
1374 enum rtx_code code
= GET_CODE (op
);
1376 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1379 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1380 || code
== LEU
|| code
== LTU
);
1383 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1386 alpha_swapped_comparison_operator (op
, mode
)
1388 enum machine_mode mode
;
1390 enum rtx_code code
= GET_CODE (op
);
1392 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1393 || GET_RTX_CLASS (code
) != '<')
1396 code
= swap_condition (code
);
1397 return (code
== EQ
|| code
== LE
|| code
== LT
1398 || code
== LEU
|| code
== LTU
);
1401 /* Return 1 if OP is a signed comparison operation. */
1404 signed_comparison_operator (op
, mode
)
1406 enum machine_mode mode ATTRIBUTE_UNUSED
;
1408 enum rtx_code code
= GET_CODE (op
);
1410 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1413 return (code
== EQ
|| code
== NE
1414 || code
== LE
|| code
== LT
1415 || code
== GE
|| code
== GT
);
1418 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1419 Here we know which comparisons are valid in which insn. */
1422 alpha_fp_comparison_operator (op
, mode
)
1424 enum machine_mode mode
;
1426 enum rtx_code code
= GET_CODE (op
);
1428 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1431 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1434 /* Return 1 if this is a divide or modulus operator. */
1437 divmod_operator (op
, mode
)
1439 enum machine_mode mode ATTRIBUTE_UNUSED
;
1441 switch (GET_CODE (op
))
1443 case DIV
: case MOD
: case UDIV
: case UMOD
:
1453 /* Return 1 if this memory address is a known aligned register plus
1454 a constant. It must be a valid address. This means that we can do
1455 this as an aligned reference plus some offset.
1457 Take into account what reload will do. */
1460 aligned_memory_operand (op
, mode
)
1462 enum machine_mode mode
;
1466 if (reload_in_progress
)
1469 if (GET_CODE (tmp
) == SUBREG
)
1470 tmp
= SUBREG_REG (tmp
);
1471 if (GET_CODE (tmp
) == REG
1472 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1474 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1480 if (GET_CODE (op
) != MEM
1481 || GET_MODE (op
) != mode
)
1485 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1486 sorts of constructs. Dig for the real base register. */
1487 if (reload_in_progress
1488 && GET_CODE (op
) == PLUS
1489 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1490 base
= XEXP (XEXP (op
, 0), 0);
1493 if (! memory_address_p (mode
, op
))
1495 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1498 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1501 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1504 unaligned_memory_operand (op
, mode
)
1506 enum machine_mode mode
;
1510 if (reload_in_progress
)
1513 if (GET_CODE (tmp
) == SUBREG
)
1514 tmp
= SUBREG_REG (tmp
);
1515 if (GET_CODE (tmp
) == REG
1516 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1518 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1524 if (GET_CODE (op
) != MEM
1525 || GET_MODE (op
) != mode
)
1529 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1530 sorts of constructs. Dig for the real base register. */
1531 if (reload_in_progress
1532 && GET_CODE (op
) == PLUS
1533 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1534 base
= XEXP (XEXP (op
, 0), 0);
1537 if (! memory_address_p (mode
, op
))
1539 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1542 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1545 /* Return 1 if OP is either a register or an unaligned memory location. */
1548 reg_or_unaligned_mem_operand (op
, mode
)
1550 enum machine_mode mode
;
1552 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1555 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1558 any_memory_operand (op
, mode
)
1560 enum machine_mode mode ATTRIBUTE_UNUSED
;
1562 return (GET_CODE (op
) == MEM
1563 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1564 || (reload_in_progress
&& GET_CODE (op
) == REG
1565 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1566 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1567 && GET_CODE (SUBREG_REG (op
)) == REG
1568 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1571 /* Returns 1 if OP is not an eliminable register.
1573 This exists to cure a pathological abort in the s8addq (et al) patterns,
1575 long foo () { long t; bar(); return (long) &t * 26107; }
1577 which run afoul of a hack in reload to cure a (presumably) similar
1578 problem with lea-type instructions on other targets. But there is
1579 one of us and many of them, so work around the problem by selectively
1580 preventing combine from making the optimization. */
1583 reg_not_elim_operand (op
, mode
)
1585 enum machine_mode mode
;
1588 if (GET_CODE (op
) == SUBREG
)
1589 inner
= SUBREG_REG (op
);
1590 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1593 return register_operand (op
, mode
);
1596 /* Return 1 is OP is a memory location that is not a reference (using
1597 an AND) to an unaligned location. Take into account what reload
1601 normal_memory_operand (op
, mode
)
1603 enum machine_mode mode ATTRIBUTE_UNUSED
;
1605 if (reload_in_progress
)
1608 if (GET_CODE (tmp
) == SUBREG
)
1609 tmp
= SUBREG_REG (tmp
);
1610 if (GET_CODE (tmp
) == REG
1611 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1613 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1615 /* This may not have been assigned an equivalent address if it will
1616 be eliminated. In that case, it doesn't matter what we do. */
1622 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1625 /* Accept a register, but not a subreg of any kind. This allows us to
1626 avoid pathological cases in reload wrt data movement common in
1627 int->fp conversion. */
1630 reg_no_subreg_operand (op
, mode
)
1632 enum machine_mode mode
;
1634 if (GET_CODE (op
) != REG
)
1636 return register_operand (op
, mode
);
1639 /* Recognize an addition operation that includes a constant. Used to
1640 convince reload to canonize (plus (plus reg c1) c2) during register
1644 addition_operation (op
, mode
)
1646 enum machine_mode mode
;
1648 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1650 if (GET_CODE (op
) == PLUS
1651 && register_operand (XEXP (op
, 0), mode
)
1652 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1653 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1658 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1659 the range defined for C in [I-P]. */
1662 alpha_const_ok_for_letter_p (value
, c
)
1663 HOST_WIDE_INT value
;
1669 /* An unsigned 8 bit constant. */
1670 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1672 /* The constant zero. */
1675 /* A signed 16 bit constant. */
1676 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1678 /* A shifted signed 16 bit constant appropriate for LDAH. */
1679 return ((value
& 0xffff) == 0
1680 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1682 /* A constant that can be AND'ed with using a ZAP insn. */
1683 return zap_mask (value
);
1685 /* A complemented unsigned 8 bit constant. */
1686 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1688 /* A negated unsigned 8 bit constant. */
1689 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1691 /* The constant 1, 2 or 3. */
1692 return value
== 1 || value
== 2 || value
== 3;
1699 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1700 matches for C in [GH]. */
1703 alpha_const_double_ok_for_letter_p (value
, c
)
1710 /* The floating point zero constant. */
1711 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1712 && value
== CONST0_RTX (GET_MODE (value
)));
1715 /* A valid operand of a ZAP insn. */
1716 return (GET_MODE (value
) == VOIDmode
1717 && zap_mask (CONST_DOUBLE_LOW (value
))
1718 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1725 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1729 alpha_extra_constraint (value
, c
)
1736 return normal_memory_operand (value
, VOIDmode
);
1738 return direct_call_operand (value
, Pmode
);
1740 return (GET_CODE (value
) == CONST_INT
1741 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1743 return GET_CODE (value
) == HIGH
;
1745 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1747 return (GET_CODE (value
) == CONST_VECTOR
1748 && value
== CONST0_RTX (GET_MODE (value
)));
1754 /* Return 1 if this function can directly return via $26. */
1759 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1761 && alpha_sa_size () == 0
1762 && get_frame_size () == 0
1763 && current_function_outgoing_args_size
== 0
1764 && current_function_pretend_args_size
== 0);
1767 /* Return the ADDR_VEC associated with a tablejump insn. */
1770 alpha_tablejump_addr_vec (insn
)
1775 tmp
= JUMP_LABEL (insn
);
1778 tmp
= NEXT_INSN (tmp
);
1781 if (GET_CODE (tmp
) == JUMP_INSN
1782 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1783 return PATTERN (tmp
);
1787 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1790 alpha_tablejump_best_label (insn
)
1793 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1794 rtx best_label
= NULL_RTX
;
1796 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1797 there for edge frequency counts from profile data. */
1801 int n_labels
= XVECLEN (jump_table
, 1);
1802 int best_count
= -1;
1805 for (i
= 0; i
< n_labels
; i
++)
1809 for (j
= i
+ 1; j
< n_labels
; j
++)
1810 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1811 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1814 if (count
> best_count
)
1815 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1819 return best_label
? best_label
: const0_rtx
;
1822 /* Return the TLS model to use for SYMBOL. */
1824 static enum tls_model
1825 tls_symbolic_operand_type (symbol
)
1828 enum tls_model model
;
1830 if (GET_CODE (symbol
) != SYMBOL_REF
)
1832 model
= SYMBOL_REF_TLS_MODEL (symbol
);
1834 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1835 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
1836 model
= TLS_MODEL_INITIAL_EXEC
;
1841 /* Return true if the function DECL will share the same GP as any
1842 function in the current unit of translation. */
1845 decl_has_samegp (decl
)
1848 /* Functions that are not local can be overridden, and thus may
1849 not share the same gp. */
1850 if (!(*targetm
.binds_local_p
) (decl
))
1853 /* If -msmall-data is in effect, assume that there is only one GP
1854 for the module, and so any local symbol has this property. We
1855 need explicit relocations to be able to enforce this for symbols
1856 not defined in this unit of translation, however. */
1857 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1860 /* Functions that are not external are defined in this UoT. */
1861 /* ??? Irritatingly, static functions not yet emitted are still
1862 marked "external". Apply this to non-static functions only. */
1863 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1866 /* Return true if EXP should be placed in the small data section. */
1869 alpha_in_small_data_p (exp
)
1872 /* We want to merge strings, so we never consider them small data. */
1873 if (TREE_CODE (exp
) == STRING_CST
)
1876 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1878 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1879 if (strcmp (section
, ".sdata") == 0
1880 || strcmp (section
, ".sbss") == 0)
1885 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1887 /* If this is an incomplete type with size 0, then we can't put it
1888 in sdata because it might be too big when completed. */
1889 if (size
> 0 && size
<= g_switch_value
)
1896 #if TARGET_ABI_OPEN_VMS
1898 alpha_linkage_symbol_p (symname
)
1899 const char *symname
;
1901 int symlen
= strlen (symname
);
1904 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1909 #define LINKAGE_SYMBOL_REF_P(X) \
1910 ((GET_CODE (X) == SYMBOL_REF \
1911 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1912 || (GET_CODE (X) == CONST \
1913 && GET_CODE (XEXP (X, 0)) == PLUS \
1914 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1915 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1918 /* legitimate_address_p recognizes an RTL expression that is a valid
1919 memory address for an instruction. The MODE argument is the
1920 machine mode for the MEM expression that wants to use this address.
1922 For Alpha, we have either a constant address or the sum of a
1923 register and a constant address, or just a register. For DImode,
1924 any of those forms can be surrounded with an AND that clear the
1925 low-order three bits; this is an "unaligned" access. */
1928 alpha_legitimate_address_p (mode
, x
, strict
)
1929 enum machine_mode mode
;
1933 /* If this is an ldq_u type address, discard the outer AND. */
1935 && GET_CODE (x
) == AND
1936 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1937 && INTVAL (XEXP (x
, 1)) == -8)
1940 /* Discard non-paradoxical subregs. */
1941 if (GET_CODE (x
) == SUBREG
1942 && (GET_MODE_SIZE (GET_MODE (x
))
1943 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1946 /* Unadorned general registers are valid. */
1949 ? STRICT_REG_OK_FOR_BASE_P (x
)
1950 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1953 /* Constant addresses (i.e. +/- 32k) are valid. */
1954 if (CONSTANT_ADDRESS_P (x
))
1957 #if TARGET_ABI_OPEN_VMS
1958 if (LINKAGE_SYMBOL_REF_P (x
))
1962 /* Register plus a small constant offset is valid. */
1963 if (GET_CODE (x
) == PLUS
)
1965 rtx ofs
= XEXP (x
, 1);
1968 /* Discard non-paradoxical subregs. */
1969 if (GET_CODE (x
) == SUBREG
1970 && (GET_MODE_SIZE (GET_MODE (x
))
1971 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1977 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1978 && GET_CODE (ofs
) == CONST_INT
)
1981 ? STRICT_REG_OK_FOR_BASE_P (x
)
1982 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1983 && CONSTANT_ADDRESS_P (ofs
))
1986 else if (GET_CODE (x
) == ADDRESSOF
1987 && GET_CODE (ofs
) == CONST_INT
)
1991 /* If we're managing explicit relocations, LO_SUM is valid, as
1992 are small data symbols. */
1993 else if (TARGET_EXPLICIT_RELOCS
)
1995 if (small_symbolic_operand (x
, Pmode
))
1998 if (GET_CODE (x
) == LO_SUM
)
2000 rtx ofs
= XEXP (x
, 1);
2003 /* Discard non-paradoxical subregs. */
2004 if (GET_CODE (x
) == SUBREG
2005 && (GET_MODE_SIZE (GET_MODE (x
))
2006 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2009 /* Must have a valid base register. */
2012 ? STRICT_REG_OK_FOR_BASE_P (x
)
2013 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2016 /* The symbol must be local. */
2017 if (local_symbolic_operand (ofs
, Pmode
)
2018 || dtp32_symbolic_operand (ofs
, Pmode
)
2019 || tp32_symbolic_operand (ofs
, Pmode
))
2027 /* Build the SYMBOL_REF for __tls_get_addr. */
2029 static GTY(()) rtx tls_get_addr_libfunc
;
2034 if (!tls_get_addr_libfunc
)
2035 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
2036 return tls_get_addr_libfunc
;
2039 /* Try machine-dependent ways of modifying an illegitimate address
2040 to be legitimate. If we find one, return the new, valid address. */
2043 alpha_legitimize_address (x
, scratch
, mode
)
2046 enum machine_mode mode ATTRIBUTE_UNUSED
;
2048 HOST_WIDE_INT addend
;
2050 /* If the address is (plus reg const_int) and the CONST_INT is not a
2051 valid offset, compute the high part of the constant and add it to
2052 the register. Then our address is (plus temp low-part-const). */
2053 if (GET_CODE (x
) == PLUS
2054 && GET_CODE (XEXP (x
, 0)) == REG
2055 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2056 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2058 addend
= INTVAL (XEXP (x
, 1));
2063 /* If the address is (const (plus FOO const_int)), find the low-order
2064 part of the CONST_INT. Then load FOO plus any high-order part of the
2065 CONST_INT into a register. Our address is (plus reg low-part-const).
2066 This is done to reduce the number of GOT entries. */
2068 && GET_CODE (x
) == CONST
2069 && GET_CODE (XEXP (x
, 0)) == PLUS
2070 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2072 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2073 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2077 /* If we have a (plus reg const), emit the load as in (2), then add
2078 the two registers, and finally generate (plus reg low-part-const) as
2081 && GET_CODE (x
) == PLUS
2082 && GET_CODE (XEXP (x
, 0)) == REG
2083 && GET_CODE (XEXP (x
, 1)) == CONST
2084 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2085 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2087 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2088 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2089 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2090 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2094 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2095 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2097 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2099 switch (tls_symbolic_operand_type (x
))
2101 case TLS_MODEL_GLOBAL_DYNAMIC
:
2104 r0
= gen_rtx_REG (Pmode
, 0);
2105 r16
= gen_rtx_REG (Pmode
, 16);
2106 tga
= get_tls_get_addr ();
2107 dest
= gen_reg_rtx (Pmode
);
2108 seq
= GEN_INT (alpha_next_sequence_number
++);
2110 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2111 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2112 insn
= emit_call_insn (insn
);
2113 CONST_OR_PURE_CALL_P (insn
) = 1;
2114 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2116 insn
= get_insns ();
2119 emit_libcall_block (insn
, dest
, r0
, x
);
2122 case TLS_MODEL_LOCAL_DYNAMIC
:
2125 r0
= gen_rtx_REG (Pmode
, 0);
2126 r16
= gen_rtx_REG (Pmode
, 16);
2127 tga
= get_tls_get_addr ();
2128 scratch
= gen_reg_rtx (Pmode
);
2129 seq
= GEN_INT (alpha_next_sequence_number
++);
2131 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2132 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2133 insn
= emit_call_insn (insn
);
2134 CONST_OR_PURE_CALL_P (insn
) = 1;
2135 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2137 insn
= get_insns ();
2140 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2141 UNSPEC_TLSLDM_CALL
);
2142 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2144 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2145 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2147 if (alpha_tls_size
== 64)
2149 dest
= gen_reg_rtx (Pmode
);
2150 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2151 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2154 if (alpha_tls_size
== 32)
2156 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2157 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2158 scratch
= gen_reg_rtx (Pmode
);
2159 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2161 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2163 case TLS_MODEL_INITIAL_EXEC
:
2164 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2165 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2166 tp
= gen_reg_rtx (Pmode
);
2167 scratch
= gen_reg_rtx (Pmode
);
2168 dest
= gen_reg_rtx (Pmode
);
2170 emit_insn (gen_load_tp (tp
));
2171 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2172 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2175 case TLS_MODEL_LOCAL_EXEC
:
2176 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2177 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2178 tp
= gen_reg_rtx (Pmode
);
2180 emit_insn (gen_load_tp (tp
));
2181 if (alpha_tls_size
== 32)
2183 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2184 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2185 tp
= gen_reg_rtx (Pmode
);
2186 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2188 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2191 if (local_symbolic_operand (x
, Pmode
))
2193 if (small_symbolic_operand (x
, Pmode
))
2197 if (!no_new_pseudos
)
2198 scratch
= gen_reg_rtx (Pmode
);
2199 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2200 gen_rtx_HIGH (Pmode
, x
)));
2201 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2210 HOST_WIDE_INT low
, high
;
2212 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2214 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2218 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2219 (no_new_pseudos
? scratch
: NULL_RTX
),
2220 1, OPTAB_LIB_WIDEN
);
2222 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2223 (no_new_pseudos
? scratch
: NULL_RTX
),
2224 1, OPTAB_LIB_WIDEN
);
2226 return plus_constant (x
, low
);
2230 /* We do not allow indirect calls to be optimized into sibling calls, nor
2231 can we allow a call to a function with a different GP to be optimized
2235 alpha_function_ok_for_sibcall (decl
, exp
)
2237 tree exp ATTRIBUTE_UNUSED
;
2239 /* Can't do indirect tail calls, since we don't know if the target
2240 uses the same GP. */
2244 /* Otherwise, we can make a tail call if the target function shares
2246 return decl_has_samegp (decl
);
2249 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2250 small symbolic operand until after reload. At which point we need
2251 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2252 so that sched2 has the proper dependency information. */
2255 some_small_symbolic_operand (x
, mode
)
2257 enum machine_mode mode ATTRIBUTE_UNUSED
;
2259 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2263 some_small_symbolic_operand_1 (px
, data
)
2265 void *data ATTRIBUTE_UNUSED
;
2269 /* Don't re-split. */
2270 if (GET_CODE (x
) == LO_SUM
)
2273 return small_symbolic_operand (x
, Pmode
) != 0;
2277 split_small_symbolic_operand (x
)
2281 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2286 split_small_symbolic_operand_1 (px
, data
)
2288 void *data ATTRIBUTE_UNUSED
;
2292 /* Don't re-split. */
2293 if (GET_CODE (x
) == LO_SUM
)
2296 if (small_symbolic_operand (x
, Pmode
))
2298 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2306 /* Indicate that INSN cannot be duplicated. This is true for any insn
2307 that we've marked with gpdisp relocs, since those have to stay in
2308 1-1 correspondence with one another.
2310 Techinically we could copy them if we could set up a mapping from one
2311 sequence number to another, across the set of insns to be duplicated.
2312 This seems overly complicated and error-prone since interblock motion
2313 from sched-ebb could move one of the pair of insns to a different block. */
2316 alpha_cannot_copy_insn_p (insn
)
2321 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2324 if (GET_CODE (insn
) != INSN
)
2326 if (asm_noperands (insn
) >= 0)
2329 pat
= PATTERN (insn
);
2330 if (GET_CODE (pat
) != SET
)
2332 pat
= SET_SRC (pat
);
2333 if (GET_CODE (pat
) == UNSPEC_VOLATILE
)
2335 if (XINT (pat
, 1) == UNSPECV_LDGP1
2336 || XINT (pat
, 1) == UNSPECV_PLDGP2
)
2339 else if (GET_CODE (pat
) == UNSPEC
)
2341 if (XINT (pat
, 1) == UNSPEC_LDGP2
)
2349 /* Try a machine-dependent way of reloading an illegitimate address
2350 operand. If we find one, push the reload and return the new rtx. */
2353 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2355 enum machine_mode mode ATTRIBUTE_UNUSED
;
2358 int ind_levels ATTRIBUTE_UNUSED
;
2360 /* We must recognize output that we have already generated ourselves. */
2361 if (GET_CODE (x
) == PLUS
2362 && GET_CODE (XEXP (x
, 0)) == PLUS
2363 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2364 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2365 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2367 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2368 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2373 /* We wish to handle large displacements off a base register by
2374 splitting the addend across an ldah and the mem insn. This
2375 cuts number of extra insns needed from 3 to 1. */
2376 if (GET_CODE (x
) == PLUS
2377 && GET_CODE (XEXP (x
, 0)) == REG
2378 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2379 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2380 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2382 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2383 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2385 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2387 /* Check for 32-bit overflow. */
2388 if (high
+ low
!= val
)
2391 /* Reload the high part into a base reg; leave the low part
2392 in the mem directly. */
2393 x
= gen_rtx_PLUS (GET_MODE (x
),
2394 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2398 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2399 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2407 /* Compute a (partial) cost for rtx X. Return true if the complete
2408 cost has been computed, and false if subexpressions should be
2409 scanned. In either case, *TOTAL contains the cost result. */
2412 alpha_rtx_costs (x
, code
, outer_code
, total
)
2414 int code
, outer_code
;
2417 enum machine_mode mode
= GET_MODE (x
);
2418 bool float_mode_p
= FLOAT_MODE_P (mode
);
2422 /* If this is an 8-bit constant, return zero since it can be used
2423 nearly anywhere with no cost. If it is a valid operand for an
2424 ADD or AND, likewise return 0 if we know it will be used in that
2425 context. Otherwise, return 2 since it might be used there later.
2426 All other constants take at least two insns. */
2428 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2436 if (x
== CONST0_RTX (mode
))
2438 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2439 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2441 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2444 *total
= COSTS_N_INSNS (2);
2450 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2451 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2452 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2453 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2454 else if (tls_symbolic_operand_type (x
))
2455 /* Estimate of cost for call_pal rduniq. */
2456 *total
= COSTS_N_INSNS (15);
2458 /* Otherwise we do a load from the GOT. */
2459 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2465 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2466 else if (GET_CODE (XEXP (x
, 0)) == MULT
2467 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2469 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2470 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2477 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2478 else if (mode
== DImode
)
2479 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2481 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2485 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2486 && INTVAL (XEXP (x
, 1)) <= 3)
2488 *total
= COSTS_N_INSNS (1);
2495 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2500 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2502 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2510 *total
= COSTS_N_INSNS (70); /* ??? */
2511 else if (mode
== SFmode
)
2512 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2514 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2518 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2524 *total
= COSTS_N_INSNS (1);
2532 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2538 case UNSIGNED_FLOAT
:
2542 case FLOAT_TRUNCATE
:
2543 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2551 /* REF is an alignable memory location. Place an aligned SImode
2552 reference into *PALIGNED_MEM and the number of bits to shift into
2553 *PBITNUM. SCRATCH is a free register for use in reloading out
2554 of range stack slots. */
2557 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2559 rtx
*paligned_mem
, *pbitnum
;
2562 HOST_WIDE_INT offset
= 0;
2564 if (GET_CODE (ref
) != MEM
)
2567 if (reload_in_progress
2568 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2570 base
= find_replacement (&XEXP (ref
, 0));
2572 if (! memory_address_p (GET_MODE (ref
), base
))
2577 base
= XEXP (ref
, 0);
2580 if (GET_CODE (base
) == PLUS
)
2581 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2584 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2586 if (WORDS_BIG_ENDIAN
)
2587 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2588 + (offset
& 3) * 8));
2590 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2593 /* Similar, but just get the address. Handle the two reload cases.
2594 Add EXTRA_OFFSET to the address we return. */
2597 get_unaligned_address (ref
, extra_offset
)
2602 HOST_WIDE_INT offset
= 0;
2604 if (GET_CODE (ref
) != MEM
)
2607 if (reload_in_progress
2608 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2610 base
= find_replacement (&XEXP (ref
, 0));
2612 if (! memory_address_p (GET_MODE (ref
), base
))
2617 base
= XEXP (ref
, 0);
2620 if (GET_CODE (base
) == PLUS
)
2621 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2623 return plus_constant (base
, offset
+ extra_offset
);
2626 /* On the Alpha, all (non-symbolic) constants except zero go into
2627 a floating-point register via memory. Note that we cannot
2628 return anything that is not a subset of CLASS, and that some
2629 symbolic constants cannot be dropped to memory. */
2632 alpha_preferred_reload_class(x
, class)
2634 enum reg_class
class;
2636 /* Zero is present in any register class. */
2637 if (x
== CONST0_RTX (GET_MODE (x
)))
2640 /* These sorts of constants we can easily drop to memory. */
2641 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2643 if (class == FLOAT_REGS
)
2645 if (class == ALL_REGS
)
2646 return GENERAL_REGS
;
2650 /* All other kinds of constants should not (and in the case of HIGH
2651 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2652 secondary reload. */
2654 return (class == ALL_REGS
? GENERAL_REGS
: class);
2659 /* Loading and storing HImode or QImode values to and from memory
2660 usually requires a scratch register. The exceptions are loading
2661 QImode and HImode from an aligned address to a general register
2662 unless byte instructions are permitted.
2664 We also cannot load an unaligned address or a paradoxical SUBREG
2665 into an FP register.
2667 We also cannot do integral arithmetic into FP regs, as might result
2668 from register elimination into a DImode fp register. */
2671 secondary_reload_class (class, mode
, x
, in
)
2672 enum reg_class
class;
2673 enum machine_mode mode
;
2677 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2679 if (GET_CODE (x
) == MEM
2680 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2681 || (GET_CODE (x
) == SUBREG
2682 && (GET_CODE (SUBREG_REG (x
)) == MEM
2683 || (GET_CODE (SUBREG_REG (x
)) == REG
2684 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2686 if (!in
|| !aligned_memory_operand(x
, mode
))
2687 return GENERAL_REGS
;
2691 if (class == FLOAT_REGS
)
2693 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2694 return GENERAL_REGS
;
2696 if (GET_CODE (x
) == SUBREG
2697 && (GET_MODE_SIZE (GET_MODE (x
))
2698 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2699 return GENERAL_REGS
;
2701 if (in
&& INTEGRAL_MODE_P (mode
)
2702 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2703 return GENERAL_REGS
;
2709 /* Subfunction of the following function. Update the flags of any MEM
2710 found in part of X. */
2713 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2715 int in_struct_p
, volatile_p
, unchanging_p
;
2719 switch (GET_CODE (x
))
2725 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2726 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2731 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2736 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2738 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2743 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2744 MEM_VOLATILE_P (x
) = volatile_p
;
2745 RTX_UNCHANGING_P (x
) = unchanging_p
;
2746 /* Sadly, we cannot use alias sets because the extra aliasing
2747 produced by the AND interferes. Given that two-byte quantities
2748 are the only thing we would be able to differentiate anyway,
2749 there does not seem to be any point in convoluting the early
2750 out of the alias check. */
2758 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2759 generated to perform a memory operation, look for any MEMs in either
2760 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2761 volatile flags from REF into each of the MEMs found. If REF is not
2762 a MEM, don't do anything. */
2765 alpha_set_memflags (insn
, ref
)
2769 int in_struct_p
, volatile_p
, unchanging_p
;
2771 if (GET_CODE (ref
) != MEM
)
2774 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2775 volatile_p
= MEM_VOLATILE_P (ref
);
2776 unchanging_p
= RTX_UNCHANGING_P (ref
);
2778 /* This is only called from alpha.md, after having had something
2779 generated from one of the insn patterns. So if everything is
2780 zero, the pattern is already up-to-date. */
2781 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2784 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2787 /* Try to output insns to set TARGET equal to the constant C if it can be
2788 done in less than N insns. Do all computations in MODE. Returns the place
2789 where the output has been placed if it can be done and the insns have been
2790 emitted. If it would take more than N insns, zero is returned and no
2791 insns and emitted. */
2794 alpha_emit_set_const (target
, mode
, c
, n
)
2796 enum machine_mode mode
;
2801 rtx orig_target
= target
;
2804 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2805 can't load this constant in one insn, do this in DImode. */
2806 if (no_new_pseudos
&& mode
== SImode
2807 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2808 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2810 target
= gen_lowpart (DImode
, target
);
2814 /* Try 1 insn, then 2, then up to N. */
2815 for (i
= 1; i
<= n
; i
++)
2817 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2820 rtx insn
= get_last_insn ();
2821 rtx set
= single_set (insn
);
2822 if (! CONSTANT_P (SET_SRC (set
)))
2823 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2828 /* Allow for the case where we changed the mode of TARGET. */
2829 if (result
== target
)
2830 result
= orig_target
;
2835 /* Internal routine for the above to check for N or below insns. */
2838 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2840 enum machine_mode mode
;
2846 /* Use a pseudo if highly optimizing and still generating RTL. */
2848 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2851 /* If this is a sign-extended 32-bit constant, we can do this in at most
2852 three insns, so do it if we have enough insns left. We always have
2853 a sign-extended 32-bit constant when compiling on a narrow machine. */
2855 if (HOST_BITS_PER_WIDE_INT
!= 64
2856 || c
>> 31 == -1 || c
>> 31 == 0)
2858 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2859 HOST_WIDE_INT tmp1
= c
- low
;
2860 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2861 HOST_WIDE_INT extra
= 0;
2863 /* If HIGH will be interpreted as negative but the constant is
2864 positive, we must adjust it to do two ldha insns. */
2866 if ((high
& 0x8000) != 0 && c
>= 0)
2870 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2873 if (c
== low
|| (low
== 0 && extra
== 0))
2875 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2876 but that meant that we can't handle INT_MIN on 32-bit machines
2877 (like NT/Alpha), because we recurse indefinitely through
2878 emit_move_insn to gen_movdi. So instead, since we know exactly
2879 what we want, create it explicitly. */
2882 target
= gen_reg_rtx (mode
);
2883 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2886 else if (n
>= 2 + (extra
!= 0))
2888 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2890 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2891 This means that if we go through expand_binop, we'll try to
2892 generate extensions, etc, which will require new pseudos, which
2893 will fail during some split phases. The SImode add patterns
2894 still exist, but are not named. So build the insns by hand. */
2899 subtarget
= gen_reg_rtx (mode
);
2900 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2901 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2907 target
= gen_reg_rtx (mode
);
2908 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2909 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2915 /* If we couldn't do it that way, try some other methods. But if we have
2916 no instructions left, don't bother. Likewise, if this is SImode and
2917 we can't make pseudos, we can't do anything since the expand_binop
2918 and expand_unop calls will widen and try to make pseudos. */
2920 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2923 /* Next, see if we can load a related constant and then shift and possibly
2924 negate it to get the constant we want. Try this once each increasing
2925 numbers of insns. */
2927 for (i
= 1; i
< n
; i
++)
2929 /* First, see if minus some low bits, we've an easy load of
2932 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2934 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2935 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2936 target
, 0, OPTAB_WIDEN
);
2938 /* Next try complementing. */
2939 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2940 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2942 /* Next try to form a constant and do a left shift. We can do this
2943 if some low-order bits are zero; the exact_log2 call below tells
2944 us that information. The bits we are shifting out could be any
2945 value, but here we'll just try the 0- and sign-extended forms of
2946 the constant. To try to increase the chance of having the same
2947 constant in more than one insn, start at the highest number of
2948 bits to shift, but try all possibilities in case a ZAPNOT will
2951 if ((bits
= exact_log2 (c
& - c
)) > 0)
2952 for (; bits
> 0; bits
--)
2953 if ((temp
= (alpha_emit_set_const
2954 (subtarget
, mode
, c
>> bits
, i
))) != 0
2955 || ((temp
= (alpha_emit_set_const
2957 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2959 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2960 target
, 0, OPTAB_WIDEN
);
2962 /* Now try high-order zero bits. Here we try the shifted-in bits as
2963 all zero and all ones. Be careful to avoid shifting outside the
2964 mode and to avoid shifting outside the host wide int size. */
2965 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2966 confuse the recursive call and set all of the high 32 bits. */
2968 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2969 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2970 for (; bits
> 0; bits
--)
2971 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2973 || ((temp
= (alpha_emit_set_const
2975 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2978 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2979 target
, 1, OPTAB_WIDEN
);
2981 /* Now try high-order 1 bits. We get that with a sign-extension.
2982 But one bit isn't enough here. Be careful to avoid shifting outside
2983 the mode and to avoid shifting outside the host wide int size. */
2985 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2986 - floor_log2 (~ c
) - 2)) > 0)
2987 for (; bits
> 0; bits
--)
2988 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2990 || ((temp
= (alpha_emit_set_const
2992 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2995 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2996 target
, 0, OPTAB_WIDEN
);
2999 #if HOST_BITS_PER_WIDE_INT == 64
3000 /* Finally, see if can load a value into the target that is the same as the
3001 constant except that all bytes that are 0 are changed to be 0xff. If we
3002 can, then we can do a ZAPNOT to obtain the desired constant. */
3005 for (i
= 0; i
< 64; i
+= 8)
3006 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
3007 new |= (HOST_WIDE_INT
) 0xff << i
;
3009 /* We are only called for SImode and DImode. If this is SImode, ensure that
3010 we are sign extended to a full word. */
3013 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
3015 if (new != c
&& new != -1
3016 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
3017 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
3018 target
, 0, OPTAB_WIDEN
);
3024 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
3025 fall back to a straight forward decomposition. We do this to avoid
3026 exponential run times encountered when looking for longer sequences
3027 with alpha_emit_set_const. */
3030 alpha_emit_set_long_const (target
, c1
, c2
)
3032 HOST_WIDE_INT c1
, c2
;
3034 HOST_WIDE_INT d1
, d2
, d3
, d4
;
3036 /* Decompose the entire word */
3037 #if HOST_BITS_PER_WIDE_INT >= 64
3038 if (c2
!= -(c1
< 0))
3040 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3042 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3043 c1
= (c1
- d2
) >> 32;
3044 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3046 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3050 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3052 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3056 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
3058 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3063 /* Construct the high word */
3066 emit_move_insn (target
, GEN_INT (d4
));
3068 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
3071 emit_move_insn (target
, GEN_INT (d3
));
3073 /* Shift it into place */
3074 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
3076 /* Add in the low bits. */
3078 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
3080 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
3085 /* Expand a move instruction; return true if all work is done.
3086 We don't handle non-bwx subword loads here. */
3089 alpha_expand_mov (mode
, operands
)
3090 enum machine_mode mode
;
3093 /* If the output is not a register, the input must be. */
3094 if (GET_CODE (operands
[0]) == MEM
3095 && ! reg_or_0_operand (operands
[1], mode
))
3096 operands
[1] = force_reg (mode
, operands
[1]);
3098 /* Allow legitimize_address to perform some simplifications. */
3099 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
3103 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
3104 compiled at the end of compilation. In the meantime, someone can
3105 re-encode-section-info on some symbol changing it e.g. from global
3106 to local-not-small. If this happens, we'd have emitted a plain
3107 load rather than a high+losum load and not recognize the insn.
3109 So if rtl inlining is in effect, we delay the global/not-global
3110 decision until rest_of_compilation by wrapping it in an
3112 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
3113 && rtx_equal_function_value_matters
3114 && global_symbolic_operand (operands
[1], mode
))
3116 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
3120 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
3123 if (tmp
== operands
[0])
3130 /* Early out for non-constants and valid constants. */
3131 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
3134 /* Split large integers. */
3135 if (GET_CODE (operands
[1]) == CONST_INT
3136 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
3138 HOST_WIDE_INT i0
, i1
;
3139 rtx temp
= NULL_RTX
;
3141 if (GET_CODE (operands
[1]) == CONST_INT
)
3143 i0
= INTVAL (operands
[1]);
3146 else if (HOST_BITS_PER_WIDE_INT
>= 64)
3148 i0
= CONST_DOUBLE_LOW (operands
[1]);
3153 i0
= CONST_DOUBLE_LOW (operands
[1]);
3154 i1
= CONST_DOUBLE_HIGH (operands
[1]);
3157 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
3158 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
3160 if (!temp
&& TARGET_BUILD_CONSTANTS
)
3161 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
3165 if (rtx_equal_p (operands
[0], temp
))
3172 /* Otherwise we've nothing left but to drop the thing to memory. */
3173 operands
[1] = force_const_mem (mode
, operands
[1]);
3174 if (reload_in_progress
)
3176 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
3177 operands
[1] = copy_rtx (operands
[1]);
3178 XEXP (operands
[1], 0) = operands
[0];
3181 operands
[1] = validize_mem (operands
[1]);
3185 /* Expand a non-bwx QImode or HImode move instruction;
3186 return true if all work is done. */
3189 alpha_expand_mov_nobwx (mode
, operands
)
3190 enum machine_mode mode
;
3193 /* If the output is not a register, the input must be. */
3194 if (GET_CODE (operands
[0]) == MEM
)
3195 operands
[1] = force_reg (mode
, operands
[1]);
3197 /* Handle four memory cases, unaligned and aligned for either the input
3198 or the output. The only case where we can be called during reload is
3199 for aligned loads; all other cases require temporaries. */
3201 if (GET_CODE (operands
[1]) == MEM
3202 || (GET_CODE (operands
[1]) == SUBREG
3203 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3204 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3205 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3206 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3207 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3208 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3210 if (aligned_memory_operand (operands
[1], mode
))
3212 if (reload_in_progress
)
3214 emit_insn ((mode
== QImode
3215 ? gen_reload_inqi_help
3216 : gen_reload_inhi_help
)
3217 (operands
[0], operands
[1],
3218 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3222 rtx aligned_mem
, bitnum
;
3223 rtx scratch
= gen_reg_rtx (SImode
);
3225 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3227 emit_insn ((mode
== QImode
3228 ? gen_aligned_loadqi
3229 : gen_aligned_loadhi
)
3230 (operands
[0], aligned_mem
, bitnum
, scratch
));
3235 /* Don't pass these as parameters since that makes the generated
3236 code depend on parameter evaluation order which will cause
3237 bootstrap failures. */
3239 rtx temp1
= gen_reg_rtx (DImode
);
3240 rtx temp2
= gen_reg_rtx (DImode
);
3241 rtx seq
= ((mode
== QImode
3242 ? gen_unaligned_loadqi
3243 : gen_unaligned_loadhi
)
3244 (operands
[0], get_unaligned_address (operands
[1], 0),
3247 alpha_set_memflags (seq
, operands
[1]);
3253 if (GET_CODE (operands
[0]) == MEM
3254 || (GET_CODE (operands
[0]) == SUBREG
3255 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3256 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3257 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3258 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3259 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3260 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3262 if (aligned_memory_operand (operands
[0], mode
))
3264 rtx aligned_mem
, bitnum
;
3265 rtx temp1
= gen_reg_rtx (SImode
);
3266 rtx temp2
= gen_reg_rtx (SImode
);
3268 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3270 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3275 rtx temp1
= gen_reg_rtx (DImode
);
3276 rtx temp2
= gen_reg_rtx (DImode
);
3277 rtx temp3
= gen_reg_rtx (DImode
);
3278 rtx seq
= ((mode
== QImode
3279 ? gen_unaligned_storeqi
3280 : gen_unaligned_storehi
)
3281 (get_unaligned_address (operands
[0], 0),
3282 operands
[1], temp1
, temp2
, temp3
));
3284 alpha_set_memflags (seq
, operands
[0]);
3293 /* Generate an unsigned DImode to FP conversion. This is the same code
3294 optabs would emit if we didn't have TFmode patterns.
3296 For SFmode, this is the only construction I've found that can pass
3297 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3298 intermediates will work, because you'll get intermediate rounding
3299 that ruins the end result. Some of this could be fixed by turning
3300 on round-to-positive-infinity, but that requires diddling the fpsr,
3301 which kills performance. I tried turning this around and converting
3302 to a negative number, so that I could turn on /m, but either I did
3303 it wrong or there's something else cause I wound up with the exact
3304 same single-bit error. There is a branch-less form of this same code:
3315 fcmoveq $f10,$f11,$f0
3317 I'm not using it because it's the same number of instructions as
3318 this branch-full form, and it has more serialized long latency
3319 instructions on the critical path.
3321 For DFmode, we can avoid rounding errors by breaking up the word
3322 into two pieces, converting them separately, and adding them back:
3324 LC0: .long 0,0x5f800000
3329 cpyse $f11,$f31,$f10
3330 cpyse $f31,$f11,$f11
3338 This doesn't seem to be a clear-cut win over the optabs form.
3339 It probably all depends on the distribution of numbers being
3340 converted -- in the optabs form, all but high-bit-set has a
3341 much lower minimum execution time. */
3344 alpha_emit_floatuns (operands
)
3347 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3348 enum machine_mode mode
;
3351 in
= force_reg (DImode
, operands
[1]);
3352 mode
= GET_MODE (out
);
3353 neglab
= gen_label_rtx ();
3354 donelab
= gen_label_rtx ();
3355 i0
= gen_reg_rtx (DImode
);
3356 i1
= gen_reg_rtx (DImode
);
3357 f0
= gen_reg_rtx (mode
);
3359 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3361 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3362 emit_jump_insn (gen_jump (donelab
));
3365 emit_label (neglab
);
3367 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3368 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3369 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3370 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3371 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3373 emit_label (donelab
);
3376 /* Generate the comparison for a conditional branch. */
3379 alpha_emit_conditional_branch (code
)
3382 enum rtx_code cmp_code
, branch_code
;
3383 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3384 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3387 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3389 if (! TARGET_HAS_XFLOATING_LIBS
)
3392 /* X_floating library comparison functions return
3396 Convert the compare against the raw return value. */
3418 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3420 alpha_compare
.fp_p
= 0;
3423 /* The general case: fold the comparison code to the types of compares
3424 that we have, choosing the branch as necessary. */
3427 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3429 /* We have these compares: */
3430 cmp_code
= code
, branch_code
= NE
;
3435 /* These must be reversed. */
3436 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3439 case GE
: case GT
: case GEU
: case GTU
:
3440 /* For FP, we swap them, for INT, we reverse them. */
3441 if (alpha_compare
.fp_p
)
3443 cmp_code
= swap_condition (code
);
3445 tem
= op0
, op0
= op1
, op1
= tem
;
3449 cmp_code
= reverse_condition (code
);
3458 if (alpha_compare
.fp_p
)
3461 if (flag_unsafe_math_optimizations
)
3463 /* When we are not as concerned about non-finite values, and we
3464 are comparing against zero, we can branch directly. */
3465 if (op1
== CONST0_RTX (DFmode
))
3466 cmp_code
= NIL
, branch_code
= code
;
3467 else if (op0
== CONST0_RTX (DFmode
))
3469 /* Undo the swap we probably did just above. */
3470 tem
= op0
, op0
= op1
, op1
= tem
;
3471 branch_code
= swap_condition (cmp_code
);
3477 /* ??? We mark the branch mode to be CCmode to prevent the
3478 compare and branch from being combined, since the compare
3479 insn follows IEEE rules that the branch does not. */
3480 branch_mode
= CCmode
;
3487 /* The following optimizations are only for signed compares. */
3488 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3490 /* Whee. Compare and branch against 0 directly. */
3491 if (op1
== const0_rtx
)
3492 cmp_code
= NIL
, branch_code
= code
;
3494 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3495 bypass between logicals and br/cmov on EV5. But we don't want to
3496 force valid immediate constants into registers needlessly. */
3497 else if (GET_CODE (op1
) == CONST_INT
)
3499 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3501 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3502 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3503 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3505 cmp_code
= PLUS
, branch_code
= code
;
3511 if (!reg_or_0_operand (op0
, DImode
))
3512 op0
= force_reg (DImode
, op0
);
3513 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3514 op1
= force_reg (DImode
, op1
);
3517 /* Emit an initial compare instruction, if necessary. */
3519 if (cmp_code
!= NIL
)
3521 tem
= gen_reg_rtx (cmp_mode
);
3522 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3525 /* Zero the operands. */
3526 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3528 /* Return the branch comparison. */
3529 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3532 /* Certain simplifications can be done to make invalid setcc operations
3533 valid. Return the final comparison, or NULL if we can't work. */
3536 alpha_emit_setcc (code
)
3539 enum rtx_code cmp_code
;
3540 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3541 int fp_p
= alpha_compare
.fp_p
;
3544 /* Zero the operands. */
3545 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3547 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3549 if (! TARGET_HAS_XFLOATING_LIBS
)
3552 /* X_floating library comparison functions return
3556 Convert the compare against the raw return value. */
3558 if (code
== UNORDERED
|| code
== ORDERED
)
3563 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3567 if (code
== UNORDERED
)
3569 else if (code
== ORDERED
)
3575 if (fp_p
&& !TARGET_FIX
)
3578 /* The general case: fold the comparison code to the types of compares
3579 that we have, choosing the branch as necessary. */
3584 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3586 /* We have these compares. */
3588 cmp_code
= code
, code
= NE
;
3592 if (!fp_p
&& op1
== const0_rtx
)
3597 cmp_code
= reverse_condition (code
);
3601 case GE
: case GT
: case GEU
: case GTU
:
3602 /* These normally need swapping, but for integer zero we have
3603 special patterns that recognize swapped operands. */
3604 if (!fp_p
&& op1
== const0_rtx
)
3606 code
= swap_condition (code
);
3608 cmp_code
= code
, code
= NE
;
3609 tmp
= op0
, op0
= op1
, op1
= tmp
;
3618 if (!register_operand (op0
, DImode
))
3619 op0
= force_reg (DImode
, op0
);
3620 if (!reg_or_8bit_operand (op1
, DImode
))
3621 op1
= force_reg (DImode
, op1
);
3624 /* Emit an initial compare instruction, if necessary. */
3625 if (cmp_code
!= NIL
)
3627 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3629 tmp
= gen_reg_rtx (mode
);
3630 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3631 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3633 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3637 /* Return the setcc comparison. */
3638 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3642 /* Rewrite a comparison against zero CMP of the form
3643 (CODE (cc0) (const_int 0)) so it can be written validly in
3644 a conditional move (if_then_else CMP ...).
3645 If both of the operands that set cc0 are nonzero we must emit
3646 an insn to perform the compare (it can't be done within
3647 the conditional move). */
3649 alpha_emit_conditional_move (cmp
, mode
)
3651 enum machine_mode mode
;
3653 enum rtx_code code
= GET_CODE (cmp
);
3654 enum rtx_code cmov_code
= NE
;
3655 rtx op0
= alpha_compare
.op0
;
3656 rtx op1
= alpha_compare
.op1
;
3657 int fp_p
= alpha_compare
.fp_p
;
3658 enum machine_mode cmp_mode
3659 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3660 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3661 enum machine_mode cmov_mode
= VOIDmode
;
3662 int local_fast_math
= flag_unsafe_math_optimizations
;
3665 /* Zero the operands. */
3666 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3668 if (fp_p
!= FLOAT_MODE_P (mode
))
3670 enum rtx_code cmp_code
;
3675 /* If we have fp<->int register move instructions, do a cmov by
3676 performing the comparison in fp registers, and move the
3677 zero/nonzero value to integer registers, where we can then
3678 use a normal cmov, or vice-versa. */
3682 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3683 /* We have these compares. */
3684 cmp_code
= code
, code
= NE
;
3688 /* This must be reversed. */
3689 cmp_code
= EQ
, code
= EQ
;
3692 case GE
: case GT
: case GEU
: case GTU
:
3693 /* These normally need swapping, but for integer zero we have
3694 special patterns that recognize swapped operands. */
3695 if (!fp_p
&& op1
== const0_rtx
)
3696 cmp_code
= code
, code
= NE
;
3699 cmp_code
= swap_condition (code
);
3701 tem
= op0
, op0
= op1
, op1
= tem
;
3709 tem
= gen_reg_rtx (cmp_op_mode
);
3710 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3711 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3714 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3715 op0
= gen_lowpart (cmp_op_mode
, tem
);
3716 op1
= CONST0_RTX (cmp_op_mode
);
3718 local_fast_math
= 1;
3721 /* We may be able to use a conditional move directly.
3722 This avoids emitting spurious compares. */
3723 if (signed_comparison_operator (cmp
, VOIDmode
)
3724 && (!fp_p
|| local_fast_math
)
3725 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3726 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3728 /* We can't put the comparison inside the conditional move;
3729 emit a compare instruction and put that inside the
3730 conditional move. Make sure we emit only comparisons we have;
3731 swap or reverse as necessary. */
3738 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3739 /* We have these compares: */
3743 /* This must be reversed. */
3744 code
= reverse_condition (code
);
3748 case GE
: case GT
: case GEU
: case GTU
:
3749 /* These must be swapped. */
3750 if (op1
!= CONST0_RTX (cmp_mode
))
3752 code
= swap_condition (code
);
3753 tem
= op0
, op0
= op1
, op1
= tem
;
3763 if (!reg_or_0_operand (op0
, DImode
))
3764 op0
= force_reg (DImode
, op0
);
3765 if (!reg_or_8bit_operand (op1
, DImode
))
3766 op1
= force_reg (DImode
, op1
);
3769 /* ??? We mark the branch mode to be CCmode to prevent the compare
3770 and cmov from being combined, since the compare insn follows IEEE
3771 rules that the cmov does not. */
3772 if (fp_p
&& !local_fast_math
)
3775 tem
= gen_reg_rtx (cmp_op_mode
);
3776 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3777 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3780 /* Simplify a conditional move of two constants into a setcc with
3781 arithmetic. This is done with a splitter since combine would
3782 just undo the work if done during code generation. It also catches
3783 cases we wouldn't have before cse. */
3786 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3788 rtx dest
, cond
, t_rtx
, f_rtx
;
3790 HOST_WIDE_INT t
, f
, diff
;
3791 enum machine_mode mode
;
3792 rtx target
, subtarget
, tmp
;
3794 mode
= GET_MODE (dest
);
3799 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3800 || (code
== GE
|| code
== GT
))
3802 code
= reverse_condition (code
);
3803 diff
= t
, t
= f
, f
= diff
;
3807 subtarget
= target
= dest
;
3810 target
= gen_lowpart (DImode
, dest
);
3811 if (! no_new_pseudos
)
3812 subtarget
= gen_reg_rtx (DImode
);
3816 /* Below, we must be careful to use copy_rtx on target and subtarget
3817 in intermediate insns, as they may be a subreg rtx, which may not
3820 if (f
== 0 && exact_log2 (diff
) > 0
3821 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3822 viable over a longer latency cmove. On EV5, the E0 slot is a
3823 scarce resource, and on EV4 shift has the same latency as a cmove. */
3824 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3826 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3827 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3829 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3830 GEN_INT (exact_log2 (t
)));
3831 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3833 else if (f
== 0 && t
== -1)
3835 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3836 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3838 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3840 else if (diff
== 1 || diff
== 4 || diff
== 8)
3844 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3845 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3848 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3851 add_op
= GEN_INT (f
);
3852 if (sext_add_operand (add_op
, mode
))
3854 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3856 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3857 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3869 /* Look up the function X_floating library function name for the
3873 alpha_lookup_xfloating_lib_func (code
)
3878 const enum rtx_code code
;
3879 const char *const func
;
3882 static const struct xfloating_op vms_xfloating_ops
[] =
3884 { PLUS
, "OTS$ADD_X" },
3885 { MINUS
, "OTS$SUB_X" },
3886 { MULT
, "OTS$MUL_X" },
3887 { DIV
, "OTS$DIV_X" },
3888 { EQ
, "OTS$EQL_X" },
3889 { NE
, "OTS$NEQ_X" },
3890 { LT
, "OTS$LSS_X" },
3891 { LE
, "OTS$LEQ_X" },
3892 { GT
, "OTS$GTR_X" },
3893 { GE
, "OTS$GEQ_X" },
3894 { FIX
, "OTS$CVTXQ" },
3895 { FLOAT
, "OTS$CVTQX" },
3896 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3897 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3898 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3901 static const struct xfloating_op osf_xfloating_ops
[] =
3903 { PLUS
, "_OtsAddX" },
3904 { MINUS
, "_OtsSubX" },
3905 { MULT
, "_OtsMulX" },
3906 { DIV
, "_OtsDivX" },
3913 { FIX
, "_OtsCvtXQ" },
3914 { FLOAT
, "_OtsCvtQX" },
3915 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3916 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3917 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3920 const struct xfloating_op
*ops
;
3921 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3924 /* How irritating. Nothing to key off for the table. Hardcode
3925 knowledge of the G_floating routines. */
3926 if (TARGET_FLOAT_VAX
)
3928 if (TARGET_ABI_OPEN_VMS
)
3930 if (code
== FLOAT_EXTEND
)
3931 return "OTS$CVT_FLOAT_G_X";
3932 if (code
== FLOAT_TRUNCATE
)
3933 return "OTS$CVT_FLOAT_X_G";
3937 if (code
== FLOAT_EXTEND
)
3938 return "_OtsConvertFloatGX";
3939 if (code
== FLOAT_TRUNCATE
)
3940 return "_OtsConvertFloatXG";
3944 if (TARGET_ABI_OPEN_VMS
)
3945 ops
= vms_xfloating_ops
;
3947 ops
= osf_xfloating_ops
;
3949 for (i
= 0; i
< n
; ++i
)
3950 if (ops
[i
].code
== code
)
3956 /* Most X_floating operations take the rounding mode as an argument.
3957 Compute that here. */
3960 alpha_compute_xfloating_mode_arg (code
, round
)
3962 enum alpha_fp_rounding_mode round
;
3968 case ALPHA_FPRM_NORM
:
3971 case ALPHA_FPRM_MINF
:
3974 case ALPHA_FPRM_CHOP
:
3977 case ALPHA_FPRM_DYN
:
3983 /* XXX For reference, round to +inf is mode = 3. */
3986 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3992 /* Emit an X_floating library function call.
3994 Note that these functions do not follow normal calling conventions:
3995 TFmode arguments are passed in two integer registers (as opposed to
3996 indirect); TFmode return values appear in R16+R17.
3998 FUNC is the function name to call.
3999 TARGET is where the output belongs.
4000 OPERANDS are the inputs.
4001 NOPERANDS is the count of inputs.
4002 EQUIV is the expression equivalent for the function.
4006 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
4013 rtx usage
= NULL_RTX
, tmp
, reg
;
4018 for (i
= 0; i
< noperands
; ++i
)
4020 switch (GET_MODE (operands
[i
]))
4023 reg
= gen_rtx_REG (TFmode
, regno
);
4028 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
4033 if (GET_CODE (operands
[i
]) != CONST_INT
)
4037 reg
= gen_rtx_REG (DImode
, regno
);
4045 emit_move_insn (reg
, operands
[i
]);
4046 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
4049 switch (GET_MODE (target
))
4052 reg
= gen_rtx_REG (TFmode
, 16);
4055 reg
= gen_rtx_REG (DFmode
, 32);
4058 reg
= gen_rtx_REG (DImode
, 0);
4064 tmp
= gen_rtx_MEM (QImode
, init_one_libfunc (func
));
4065 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
4066 const0_rtx
, const0_rtx
));
4067 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
4072 emit_libcall_block (tmp
, target
, reg
, equiv
);
4075 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
4078 alpha_emit_xfloating_arith (code
, operands
)
4084 rtx out_operands
[3];
4086 func
= alpha_lookup_xfloating_lib_func (code
);
4087 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4089 out_operands
[0] = operands
[1];
4090 out_operands
[1] = operands
[2];
4091 out_operands
[2] = GEN_INT (mode
);
4092 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
4093 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
4097 /* Emit an X_floating library function call for a comparison. */
4100 alpha_emit_xfloating_compare (code
, op0
, op1
)
4105 rtx out
, operands
[2];
4107 func
= alpha_lookup_xfloating_lib_func (code
);
4111 out
= gen_reg_rtx (DImode
);
4113 /* ??? Strange mode for equiv because what's actually returned
4114 is -1,0,1, not a proper boolean value. */
4115 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
4116 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
4121 /* Emit an X_floating library function call for a conversion. */
4124 alpha_emit_xfloating_cvt (code
, operands
)
4128 int noperands
= 1, mode
;
4129 rtx out_operands
[2];
4132 func
= alpha_lookup_xfloating_lib_func (code
);
4134 out_operands
[0] = operands
[1];
4139 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
4140 out_operands
[1] = GEN_INT (mode
);
4143 case FLOAT_TRUNCATE
:
4144 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4145 out_operands
[1] = GEN_INT (mode
);
4152 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
4153 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
4157 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
4158 OP[0] into OP[0,1]. Naturally, output operand ordering is
4162 alpha_split_tfmode_pair (operands
)
4165 if (GET_CODE (operands
[1]) == REG
)
4167 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
4168 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
4170 else if (GET_CODE (operands
[1]) == MEM
)
4172 operands
[3] = adjust_address (operands
[1], DImode
, 8);
4173 operands
[2] = adjust_address (operands
[1], DImode
, 0);
4175 else if (operands
[1] == CONST0_RTX (TFmode
))
4176 operands
[2] = operands
[3] = const0_rtx
;
4180 if (GET_CODE (operands
[0]) == REG
)
4182 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
4183 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
4185 else if (GET_CODE (operands
[0]) == MEM
)
4187 operands
[1] = adjust_address (operands
[0], DImode
, 8);
4188 operands
[0] = adjust_address (operands
[0], DImode
, 0);
4194 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4195 op2 is a register containing the sign bit, operation is the
4196 logical operation to be performed. */
4199 alpha_split_tfmode_frobsign (operands
, operation
)
4201 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4203 rtx high_bit
= operands
[2];
4207 alpha_split_tfmode_pair (operands
);
4209 /* Detect three flavors of operand overlap. */
4211 if (rtx_equal_p (operands
[0], operands
[2]))
4213 else if (rtx_equal_p (operands
[1], operands
[2]))
4215 if (rtx_equal_p (operands
[0], high_bit
))
4222 emit_move_insn (operands
[0], operands
[2]);
4224 /* ??? If the destination overlaps both source tf and high_bit, then
4225 assume source tf is dead in its entirety and use the other half
4226 for a scratch register. Otherwise "scratch" is just the proper
4227 destination register. */
4228 scratch
= operands
[move
< 2 ? 1 : 3];
4230 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4234 emit_move_insn (operands
[0], operands
[2]);
4236 emit_move_insn (operands
[1], scratch
);
4240 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4244 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4245 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4246 lda r3,X(r11) lda r3,X+2(r11)
4247 extwl r1,r3,r1 extql r1,r3,r1
4248 extwh r2,r3,r2 extqh r2,r3,r2
4249 or r1.r2.r1 or r1,r2,r1
4252 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4253 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4254 lda r3,X(r11) lda r3,X(r11)
4255 extll r1,r3,r1 extll r1,r3,r1
4256 extlh r2,r3,r2 extlh r2,r3,r2
4257 or r1.r2.r1 addl r1,r2,r1
4259 quad: ldq_u r1,X(r11)
4268 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4270 HOST_WIDE_INT size
, ofs
;
4273 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4274 enum machine_mode mode
;
4276 meml
= gen_reg_rtx (DImode
);
4277 memh
= gen_reg_rtx (DImode
);
4278 addr
= gen_reg_rtx (DImode
);
4279 extl
= gen_reg_rtx (DImode
);
4280 exth
= gen_reg_rtx (DImode
);
4282 mema
= XEXP (mem
, 0);
4283 if (GET_CODE (mema
) == LO_SUM
)
4284 mema
= force_reg (Pmode
, mema
);
4286 /* AND addresses cannot be in any alias set, since they may implicitly
4287 alias surrounding code. Ideally we'd have some alias set that
4288 covered all types except those with alignment 8 or higher. */
4290 tmp
= change_address (mem
, DImode
,
4291 gen_rtx_AND (DImode
,
4292 plus_constant (mema
, ofs
),
4294 set_mem_alias_set (tmp
, 0);
4295 emit_move_insn (meml
, tmp
);
4297 tmp
= change_address (mem
, DImode
,
4298 gen_rtx_AND (DImode
,
4299 plus_constant (mema
, ofs
+ size
- 1),
4301 set_mem_alias_set (tmp
, 0);
4302 emit_move_insn (memh
, tmp
);
4304 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4306 emit_move_insn (addr
, plus_constant (mema
, -1));
4308 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4309 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4311 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4312 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4313 addr
, 1, OPTAB_WIDEN
);
4315 else if (sign
&& size
== 2)
4317 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4319 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4320 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4322 /* We must use tgt here for the target. Alpha-vms port fails if we use
4323 addr for the target, because addr is marked as a pointer and combine
4324 knows that pointers are always sign-extended 32 bit values. */
4325 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4326 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4327 addr
, 1, OPTAB_WIDEN
);
4331 if (WORDS_BIG_ENDIAN
)
4333 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4337 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4342 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4347 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4354 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4358 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4359 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4363 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4368 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4373 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4382 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4383 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4388 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4391 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4394 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4396 HOST_WIDE_INT size
, ofs
;
4398 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4400 dstl
= gen_reg_rtx (DImode
);
4401 dsth
= gen_reg_rtx (DImode
);
4402 insl
= gen_reg_rtx (DImode
);
4403 insh
= gen_reg_rtx (DImode
);
4405 dsta
= XEXP (dst
, 0);
4406 if (GET_CODE (dsta
) == LO_SUM
)
4407 dsta
= force_reg (Pmode
, dsta
);
4409 /* AND addresses cannot be in any alias set, since they may implicitly
4410 alias surrounding code. Ideally we'd have some alias set that
4411 covered all types except those with alignment 8 or higher. */
4413 meml
= change_address (dst
, DImode
,
4414 gen_rtx_AND (DImode
,
4415 plus_constant (dsta
, ofs
),
4417 set_mem_alias_set (meml
, 0);
4419 memh
= change_address (dst
, DImode
,
4420 gen_rtx_AND (DImode
,
4421 plus_constant (dsta
, ofs
+ size
- 1),
4423 set_mem_alias_set (memh
, 0);
4425 emit_move_insn (dsth
, memh
);
4426 emit_move_insn (dstl
, meml
);
4427 if (WORDS_BIG_ENDIAN
)
4429 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4431 if (src
!= const0_rtx
)
4436 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4439 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4442 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4445 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4446 GEN_INT (size
*8), addr
));
4452 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4456 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4457 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4461 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4465 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4469 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4471 if (src
!= const0_rtx
)
4473 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4474 GEN_INT (size
*8), addr
));
4479 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4482 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4485 emit_insn (gen_insql_le (insl
, src
, addr
));
4490 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4495 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4499 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4500 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4504 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4509 if (src
!= const0_rtx
)
4511 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4512 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4515 if (WORDS_BIG_ENDIAN
)
4517 emit_move_insn (meml
, dstl
);
4518 emit_move_insn (memh
, dsth
);
4522 /* Must store high before low for degenerate case of aligned. */
4523 emit_move_insn (memh
, dsth
);
4524 emit_move_insn (meml
, dstl
);
4528 /* The block move code tries to maximize speed by separating loads and
4529 stores at the expense of register pressure: we load all of the data
4530 before we store it back out. There are two secondary effects worth
4531 mentioning, that this speeds copying to/from aligned and unaligned
4532 buffers, and that it makes the code significantly easier to write. */
4534 #define MAX_MOVE_WORDS 8
4536 /* Load an integral number of consecutive unaligned quadwords. */
4539 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4542 HOST_WIDE_INT words
, ofs
;
4544 rtx
const im8
= GEN_INT (-8);
4545 rtx
const i64
= GEN_INT (64);
4546 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4547 rtx sreg
, areg
, tmp
, smema
;
4550 smema
= XEXP (smem
, 0);
4551 if (GET_CODE (smema
) == LO_SUM
)
4552 smema
= force_reg (Pmode
, smema
);
4554 /* Generate all the tmp registers we need. */
4555 for (i
= 0; i
< words
; ++i
)
4557 data_regs
[i
] = out_regs
[i
];
4558 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4560 data_regs
[words
] = gen_reg_rtx (DImode
);
4563 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4565 /* Load up all of the source data. */
4566 for (i
= 0; i
< words
; ++i
)
4568 tmp
= change_address (smem
, DImode
,
4569 gen_rtx_AND (DImode
,
4570 plus_constant (smema
, 8*i
),
4572 set_mem_alias_set (tmp
, 0);
4573 emit_move_insn (data_regs
[i
], tmp
);
4576 tmp
= change_address (smem
, DImode
,
4577 gen_rtx_AND (DImode
,
4578 plus_constant (smema
, 8*words
- 1),
4580 set_mem_alias_set (tmp
, 0);
4581 emit_move_insn (data_regs
[words
], tmp
);
4583 /* Extract the half-word fragments. Unfortunately DEC decided to make
4584 extxh with offset zero a noop instead of zeroing the register, so
4585 we must take care of that edge condition ourselves with cmov. */
4587 sreg
= copy_addr_to_reg (smema
);
4588 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4590 if (WORDS_BIG_ENDIAN
)
4591 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4592 for (i
= 0; i
< words
; ++i
)
4594 if (WORDS_BIG_ENDIAN
)
4596 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4597 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4601 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4602 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4604 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4605 gen_rtx_IF_THEN_ELSE (DImode
,
4606 gen_rtx_EQ (DImode
, areg
,
4608 const0_rtx
, ext_tmps
[i
])));
4611 /* Merge the half-words into whole words. */
4612 for (i
= 0; i
< words
; ++i
)
4614 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4615 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4619 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4620 may be NULL to store zeros. */
4623 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4626 HOST_WIDE_INT words
, ofs
;
4628 rtx
const im8
= GEN_INT (-8);
4629 rtx
const i64
= GEN_INT (64);
4630 rtx ins_tmps
[MAX_MOVE_WORDS
];
4631 rtx st_tmp_1
, st_tmp_2
, dreg
;
4632 rtx st_addr_1
, st_addr_2
, dmema
;
4635 dmema
= XEXP (dmem
, 0);
4636 if (GET_CODE (dmema
) == LO_SUM
)
4637 dmema
= force_reg (Pmode
, dmema
);
4639 /* Generate all the tmp registers we need. */
4640 if (data_regs
!= NULL
)
4641 for (i
= 0; i
< words
; ++i
)
4642 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4643 st_tmp_1
= gen_reg_rtx(DImode
);
4644 st_tmp_2
= gen_reg_rtx(DImode
);
4647 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4649 st_addr_2
= change_address (dmem
, DImode
,
4650 gen_rtx_AND (DImode
,
4651 plus_constant (dmema
, words
*8 - 1),
4653 set_mem_alias_set (st_addr_2
, 0);
4655 st_addr_1
= change_address (dmem
, DImode
,
4656 gen_rtx_AND (DImode
, dmema
, im8
));
4657 set_mem_alias_set (st_addr_1
, 0);
4659 /* Load up the destination end bits. */
4660 emit_move_insn (st_tmp_2
, st_addr_2
);
4661 emit_move_insn (st_tmp_1
, st_addr_1
);
4663 /* Shift the input data into place. */
4664 dreg
= copy_addr_to_reg (dmema
);
4665 if (WORDS_BIG_ENDIAN
)
4666 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4667 if (data_regs
!= NULL
)
4669 for (i
= words
-1; i
>= 0; --i
)
4671 if (WORDS_BIG_ENDIAN
)
4673 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4674 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4678 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4679 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4682 for (i
= words
-1; i
> 0; --i
)
4684 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4685 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4690 /* Split and merge the ends with the destination data. */
4691 if (WORDS_BIG_ENDIAN
)
4693 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4694 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4698 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4699 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4702 if (data_regs
!= NULL
)
4704 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4705 st_tmp_2
, 1, OPTAB_WIDEN
);
4706 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4707 st_tmp_1
, 1, OPTAB_WIDEN
);
4711 if (WORDS_BIG_ENDIAN
)
4712 emit_move_insn (st_addr_1
, st_tmp_1
);
4714 emit_move_insn (st_addr_2
, st_tmp_2
);
4715 for (i
= words
-1; i
> 0; --i
)
4717 rtx tmp
= change_address (dmem
, DImode
,
4718 gen_rtx_AND (DImode
,
4719 plus_constant(dmema
,
4720 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4722 set_mem_alias_set (tmp
, 0);
4723 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4725 if (WORDS_BIG_ENDIAN
)
4726 emit_move_insn (st_addr_2
, st_tmp_2
);
4728 emit_move_insn (st_addr_1
, st_tmp_1
);
4732 /* Expand string/block move operations.
4734 operands[0] is the pointer to the destination.
4735 operands[1] is the pointer to the source.
4736 operands[2] is the number of bytes to move.
4737 operands[3] is the alignment. */
4740 alpha_expand_block_move (operands
)
4743 rtx bytes_rtx
= operands
[2];
4744 rtx align_rtx
= operands
[3];
4745 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4746 HOST_WIDE_INT bytes
= orig_bytes
;
4747 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4748 HOST_WIDE_INT dst_align
= src_align
;
4749 rtx orig_src
= operands
[1];
4750 rtx orig_dst
= operands
[0];
4751 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4753 unsigned int i
, words
, ofs
, nregs
= 0;
4755 if (orig_bytes
<= 0)
4757 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4760 /* Look for additional alignment information from recorded register info. */
4762 tmp
= XEXP (orig_src
, 0);
4763 if (GET_CODE (tmp
) == REG
)
4764 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4765 else if (GET_CODE (tmp
) == PLUS
4766 && GET_CODE (XEXP (tmp
, 0)) == REG
4767 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4769 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4770 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4774 if (a
>= 64 && c
% 8 == 0)
4776 else if (a
>= 32 && c
% 4 == 0)
4778 else if (a
>= 16 && c
% 2 == 0)
4783 tmp
= XEXP (orig_dst
, 0);
4784 if (GET_CODE (tmp
) == REG
)
4785 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4786 else if (GET_CODE (tmp
) == PLUS
4787 && GET_CODE (XEXP (tmp
, 0)) == REG
4788 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4790 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4791 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4795 if (a
>= 64 && c
% 8 == 0)
4797 else if (a
>= 32 && c
% 4 == 0)
4799 else if (a
>= 16 && c
% 2 == 0)
4804 /* Load the entire block into registers. */
4805 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4807 enum machine_mode mode
;
4809 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4811 /* Don't use the existing register if we're reading more than
4812 is held in the register. Nor if there is not a mode that
4813 handles the exact size. */
4814 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4816 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4820 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4821 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4825 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4830 /* No appropriate mode; fall back on memory. */
4831 orig_src
= replace_equiv_address (orig_src
,
4832 copy_addr_to_reg (XEXP (orig_src
, 0)));
4833 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4837 if (src_align
>= 64 && bytes
>= 8)
4841 for (i
= 0; i
< words
; ++i
)
4842 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4844 for (i
= 0; i
< words
; ++i
)
4845 emit_move_insn (data_regs
[nregs
+ i
],
4846 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4853 if (src_align
>= 32 && bytes
>= 4)
4857 for (i
= 0; i
< words
; ++i
)
4858 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4860 for (i
= 0; i
< words
; ++i
)
4861 emit_move_insn (data_regs
[nregs
+ i
],
4862 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4873 for (i
= 0; i
< words
+1; ++i
)
4874 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4876 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4884 if (! TARGET_BWX
&& bytes
>= 4)
4886 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4887 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4894 if (src_align
>= 16)
4897 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4898 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4901 } while (bytes
>= 2);
4903 else if (! TARGET_BWX
)
4905 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4906 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4914 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4915 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4922 if (nregs
> ARRAY_SIZE (data_regs
))
4925 /* Now save it back out again. */
4929 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4931 enum machine_mode mode
;
4932 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4934 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4935 if (GET_MODE (tmp
) == mode
)
4939 emit_move_insn (tmp
, data_regs
[0]);
4944 else if (nregs
== 2 && mode
== TImode
)
4946 /* Undo the subregging done above when copying between
4947 two TImode registers. */
4948 if (GET_CODE (data_regs
[0]) == SUBREG
4949 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4950 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4956 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4957 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4961 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4962 data_regs
[1], NULL_RTX
);
4970 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4971 /* ??? Optimize mode < dst_mode with strict_low_part. */
4973 /* No appropriate mode; fall back on memory. We can speed things
4974 up by recognizing extra alignment information. */
4975 orig_dst
= replace_equiv_address (orig_dst
,
4976 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4977 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4980 /* Write out the data in whatever chunks reading the source allowed. */
4981 if (dst_align
>= 64)
4983 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4985 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4992 if (dst_align
>= 32)
4994 /* If the source has remaining DImode regs, write them out in
4996 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4998 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4999 NULL_RTX
, 1, OPTAB_WIDEN
);
5001 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5002 gen_lowpart (SImode
, data_regs
[i
]));
5003 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
5004 gen_lowpart (SImode
, tmp
));
5009 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5011 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5018 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5020 /* Write out a remaining block of words using unaligned methods. */
5022 for (words
= 1; i
+ words
< nregs
; words
++)
5023 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
5027 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
5029 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
5036 /* Due to the above, this won't be aligned. */
5037 /* ??? If we have more than one of these, consider constructing full
5038 words in registers and using alpha_expand_unaligned_store_words. */
5039 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5041 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
5046 if (dst_align
>= 16)
5047 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5049 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
5054 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5056 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
5061 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
5063 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
5077 alpha_expand_block_clear (operands
)
5080 rtx bytes_rtx
= operands
[1];
5081 rtx align_rtx
= operands
[2];
5082 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
5083 HOST_WIDE_INT bytes
= orig_bytes
;
5084 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
5085 HOST_WIDE_INT alignofs
= 0;
5086 rtx orig_dst
= operands
[0];
5088 int i
, words
, ofs
= 0;
5090 if (orig_bytes
<= 0)
5092 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
5095 /* Look for stricter alignment. */
5096 tmp
= XEXP (orig_dst
, 0);
5097 if (GET_CODE (tmp
) == REG
)
5098 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
5099 else if (GET_CODE (tmp
) == PLUS
5100 && GET_CODE (XEXP (tmp
, 0)) == REG
5101 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
5103 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
5104 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
5109 align
= a
, alignofs
= 8 - c
% 8;
5111 align
= a
, alignofs
= 4 - c
% 4;
5113 align
= a
, alignofs
= 2 - c
% 2;
5116 else if (GET_CODE (tmp
) == ADDRESSOF
)
5118 enum machine_mode mode
;
5120 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
5121 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
5123 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
5127 /* No appropriate mode; fall back on memory. */
5128 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
5129 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
5132 /* Handle an unaligned prefix first. */
5136 #if HOST_BITS_PER_WIDE_INT >= 64
5137 /* Given that alignofs is bounded by align, the only time BWX could
5138 generate three stores is for a 7 byte fill. Prefer two individual
5139 stores over a load/mask/store sequence. */
5140 if ((!TARGET_BWX
|| alignofs
== 7)
5142 && !(alignofs
== 4 && bytes
>= 4))
5144 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
5145 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
5149 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
5150 set_mem_alias_set (mem
, 0);
5152 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
5153 if (bytes
< alignofs
)
5155 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
5166 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
5167 NULL_RTX
, 1, OPTAB_WIDEN
);
5169 emit_move_insn (mem
, tmp
);
5173 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
5175 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5180 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
5182 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
5187 if (alignofs
== 4 && bytes
>= 4)
5189 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5195 /* If we've not used the extra lead alignment information by now,
5196 we won't be able to. Downgrade align to match what's left over. */
5199 alignofs
= alignofs
& -alignofs
;
5200 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5204 /* Handle a block of contiguous long-words. */
5206 if (align
>= 64 && bytes
>= 8)
5210 for (i
= 0; i
< words
; ++i
)
5211 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5218 /* If the block is large and appropriately aligned, emit a single
5219 store followed by a sequence of stq_u insns. */
5221 if (align
>= 32 && bytes
> 16)
5225 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5229 orig_dsta
= XEXP (orig_dst
, 0);
5230 if (GET_CODE (orig_dsta
) == LO_SUM
)
5231 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5234 for (i
= 0; i
< words
; ++i
)
5237 = change_address (orig_dst
, DImode
,
5238 gen_rtx_AND (DImode
,
5239 plus_constant (orig_dsta
, ofs
+ i
*8),
5241 set_mem_alias_set (mem
, 0);
5242 emit_move_insn (mem
, const0_rtx
);
5245 /* Depending on the alignment, the first stq_u may have overlapped
5246 with the initial stl, which means that the last stq_u didn't
5247 write as much as it would appear. Leave those questionable bytes
5249 bytes
-= words
* 8 - 4;
5250 ofs
+= words
* 8 - 4;
5253 /* Handle a smaller block of aligned words. */
5255 if ((align
>= 64 && bytes
== 4)
5256 || (align
== 32 && bytes
>= 4))
5260 for (i
= 0; i
< words
; ++i
)
5261 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5268 /* An unaligned block uses stq_u stores for as many as possible. */
5274 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5280 /* Next clean up any trailing pieces. */
5282 #if HOST_BITS_PER_WIDE_INT >= 64
5283 /* Count the number of bits in BYTES for which aligned stores could
5286 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5290 /* If we have appropriate alignment (and it wouldn't take too many
5291 instructions otherwise), mask out the bytes we need. */
5292 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5299 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5300 set_mem_alias_set (mem
, 0);
5302 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5304 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5305 NULL_RTX
, 1, OPTAB_WIDEN
);
5307 emit_move_insn (mem
, tmp
);
5310 else if (align
>= 32 && bytes
< 4)
5315 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5316 set_mem_alias_set (mem
, 0);
5318 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5320 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5321 NULL_RTX
, 1, OPTAB_WIDEN
);
5323 emit_move_insn (mem
, tmp
);
5329 if (!TARGET_BWX
&& bytes
>= 4)
5331 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5341 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5345 } while (bytes
>= 2);
5347 else if (! TARGET_BWX
)
5349 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5357 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5365 /* Returns a mask so that zap(x, value) == x & mask. */
5368 alpha_expand_zap_mask (value
)
5369 HOST_WIDE_INT value
;
5374 if (HOST_BITS_PER_WIDE_INT
>= 64)
5376 HOST_WIDE_INT mask
= 0;
5378 for (i
= 7; i
>= 0; --i
)
5381 if (!((value
>> i
) & 1))
5385 result
= gen_int_mode (mask
, DImode
);
5387 else if (HOST_BITS_PER_WIDE_INT
== 32)
5389 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5391 for (i
= 7; i
>= 4; --i
)
5394 if (!((value
>> i
) & 1))
5398 for (i
= 3; i
>= 0; --i
)
5401 if (!((value
>> i
) & 1))
5405 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5414 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5415 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5416 enum machine_mode mode
;
5419 op0
= gen_lowpart (mode
, op0
);
5421 if (op1
== const0_rtx
)
5422 op1
= CONST0_RTX (mode
);
5424 op1
= gen_lowpart (mode
, op1
);
5426 if (op2
== const0_rtx
)
5427 op2
= CONST0_RTX (mode
);
5429 op2
= gen_lowpart (mode
, op2
);
5431 emit_insn ((*gen
) (op0
, op1
, op2
));
5434 /* Adjust the cost of a scheduling dependency. Return the new cost of
5435 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5438 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5444 enum attr_type insn_type
, dep_insn_type
;
5446 /* If the dependence is an anti-dependence, there is no cost. For an
5447 output dependence, there is sometimes a cost, but it doesn't seem
5448 worth handling those few cases. */
5449 if (REG_NOTE_KIND (link
) != 0)
5452 /* If we can't recognize the insns, we can't really do anything. */
5453 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5456 insn_type
= get_attr_type (insn
);
5457 dep_insn_type
= get_attr_type (dep_insn
);
5459 /* Bring in the user-defined memory latency. */
5460 if (dep_insn_type
== TYPE_ILD
5461 || dep_insn_type
== TYPE_FLD
5462 || dep_insn_type
== TYPE_LDSYM
)
5463 cost
+= alpha_memory_latency
-1;
5465 /* Everything else handled in DFA bypasses now. */
5470 /* The number of instructions that can be issued per cycle. */
5475 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5479 alpha_use_dfa_pipeline_interface ()
5484 /* How many alternative schedules to try. This should be as wide as the
5485 scheduling freedom in the DFA, but no wider. Making this value too
5486 large results extra work for the scheduler.
5488 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5489 alternative schedules. For EV5, we can choose between E0/E1 and
5490 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5493 alpha_multipass_dfa_lookahead ()
5495 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5498 /* Machine-specific function data. */
5500 struct machine_function
GTY(())
5503 /* List of call information words for calls from this function. */
5504 struct rtx_def
*first_ciw
;
5505 struct rtx_def
*last_ciw
;
5508 /* List of deferred case vectors. */
5509 struct rtx_def
*addr_list
;
5512 const char *some_ld_name
;
5515 /* How to allocate a 'struct machine_function'. */
5517 static struct machine_function
*
5518 alpha_init_machine_status ()
5520 return ((struct machine_function
*)
5521 ggc_alloc_cleared (sizeof (struct machine_function
)));
5524 /* Functions to save and restore alpha_return_addr_rtx. */
5526 /* Start the ball rolling with RETURN_ADDR_RTX. */
5529 alpha_return_addr (count
, frame
)
5531 rtx frame ATTRIBUTE_UNUSED
;
5536 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5539 /* Return or create a pseudo containing the gp value for the current
5540 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5543 alpha_gp_save_rtx ()
5545 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5546 if (GET_CODE (r
) != MEM
)
5547 r
= gen_mem_addressof (r
, NULL_TREE
, /*rescan=*/true);
5552 alpha_ra_ever_killed ()
5556 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5557 return regs_ever_live
[REG_RA
];
5559 push_topmost_sequence ();
5561 pop_topmost_sequence ();
5563 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5567 /* Return the trap mode suffix applicable to the current
5568 instruction, or NULL. */
5571 get_trap_mode_suffix ()
5573 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5577 case TRAP_SUFFIX_NONE
:
5580 case TRAP_SUFFIX_SU
:
5581 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5585 case TRAP_SUFFIX_SUI
:
5586 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5590 case TRAP_SUFFIX_V_SV
:
5598 case ALPHA_FPTM_SUI
:
5603 case TRAP_SUFFIX_V_SV_SVI
:
5612 case ALPHA_FPTM_SUI
:
5617 case TRAP_SUFFIX_U_SU_SUI
:
5626 case ALPHA_FPTM_SUI
:
5634 /* Return the rounding mode suffix applicable to the current
5635 instruction, or NULL. */
5638 get_round_mode_suffix ()
5640 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5644 case ROUND_SUFFIX_NONE
:
5646 case ROUND_SUFFIX_NORMAL
:
5649 case ALPHA_FPRM_NORM
:
5651 case ALPHA_FPRM_MINF
:
5653 case ALPHA_FPRM_CHOP
:
5655 case ALPHA_FPRM_DYN
:
5660 case ROUND_SUFFIX_C
:
5666 /* Locate some local-dynamic symbol still in use by this function
5667 so that we can print its name in some movdi_er_tlsldm pattern. */
5670 get_some_local_dynamic_name ()
5674 if (cfun
->machine
->some_ld_name
)
5675 return cfun
->machine
->some_ld_name
;
5677 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5679 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5680 return cfun
->machine
->some_ld_name
;
5686 get_some_local_dynamic_name_1 (px
, data
)
5688 void *data ATTRIBUTE_UNUSED
;
5692 if (GET_CODE (x
) == SYMBOL_REF
5693 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5695 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5702 /* Print an operand. Recognize special options, documented below. */
5705 print_operand (file
, x
, code
)
5715 /* Print the assembler name of the current function. */
5716 assemble_name (file
, alpha_fnname
);
5720 assemble_name (file
, get_some_local_dynamic_name ());
5725 const char *trap
= get_trap_mode_suffix ();
5726 const char *round
= get_round_mode_suffix ();
5729 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5730 (trap
? trap
: ""), (round
? round
: ""));
5735 /* Generates single precision instruction suffix. */
5736 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5740 /* Generates double precision instruction suffix. */
5741 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5745 /* Generates a nop after a noreturn call at the very end of the
5747 if (next_real_insn (current_output_insn
) == 0)
5748 fprintf (file
, "\n\tnop");
5752 if (alpha_this_literal_sequence_number
== 0)
5753 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5754 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5758 if (alpha_this_gpdisp_sequence_number
== 0)
5759 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5760 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5764 if (GET_CODE (x
) == HIGH
)
5765 output_addr_const (file
, XEXP (x
, 0));
5767 output_operand_lossage ("invalid %%H value");
5774 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5776 x
= XVECEXP (x
, 0, 0);
5777 lituse
= "lituse_tlsgd";
5779 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5781 x
= XVECEXP (x
, 0, 0);
5782 lituse
= "lituse_tlsldm";
5784 else if (GET_CODE (x
) == CONST_INT
)
5785 lituse
= "lituse_jsr";
5788 output_operand_lossage ("invalid %%J value");
5792 if (x
!= const0_rtx
)
5793 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5798 /* If this operand is the constant zero, write it as "$31". */
5799 if (GET_CODE (x
) == REG
)
5800 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5801 else if (x
== CONST0_RTX (GET_MODE (x
)))
5802 fprintf (file
, "$31");
5804 output_operand_lossage ("invalid %%r value");
5808 /* Similar, but for floating-point. */
5809 if (GET_CODE (x
) == REG
)
5810 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5811 else if (x
== CONST0_RTX (GET_MODE (x
)))
5812 fprintf (file
, "$f31");
5814 output_operand_lossage ("invalid %%R value");
5818 /* Write the 1's complement of a constant. */
5819 if (GET_CODE (x
) != CONST_INT
)
5820 output_operand_lossage ("invalid %%N value");
5822 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5826 /* Write 1 << C, for a constant C. */
5827 if (GET_CODE (x
) != CONST_INT
)
5828 output_operand_lossage ("invalid %%P value");
5830 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5834 /* Write the high-order 16 bits of a constant, sign-extended. */
5835 if (GET_CODE (x
) != CONST_INT
)
5836 output_operand_lossage ("invalid %%h value");
5838 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5842 /* Write the low-order 16 bits of a constant, sign-extended. */
5843 if (GET_CODE (x
) != CONST_INT
)
5844 output_operand_lossage ("invalid %%L value");
5846 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5847 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5851 /* Write mask for ZAP insn. */
5852 if (GET_CODE (x
) == CONST_DOUBLE
)
5854 HOST_WIDE_INT mask
= 0;
5855 HOST_WIDE_INT value
;
5857 value
= CONST_DOUBLE_LOW (x
);
5858 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5863 value
= CONST_DOUBLE_HIGH (x
);
5864 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5867 mask
|= (1 << (i
+ sizeof (int)));
5869 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5872 else if (GET_CODE (x
) == CONST_INT
)
5874 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5876 for (i
= 0; i
< 8; i
++, value
>>= 8)
5880 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5883 output_operand_lossage ("invalid %%m value");
5887 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5888 if (GET_CODE (x
) != CONST_INT
5889 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5890 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5891 output_operand_lossage ("invalid %%M value");
5893 fprintf (file
, "%s",
5894 (INTVAL (x
) == 8 ? "b"
5895 : INTVAL (x
) == 16 ? "w"
5896 : INTVAL (x
) == 32 ? "l"
5901 /* Similar, except do it from the mask. */
5902 if (GET_CODE (x
) == CONST_INT
)
5904 HOST_WIDE_INT value
= INTVAL (x
);
5911 if (value
== 0xffff)
5916 if (value
== 0xffffffff)
5927 else if (HOST_BITS_PER_WIDE_INT
== 32
5928 && GET_CODE (x
) == CONST_DOUBLE
5929 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5930 && CONST_DOUBLE_HIGH (x
) == 0)
5935 output_operand_lossage ("invalid %%U value");
5939 /* Write the constant value divided by 8 for little-endian mode or
5940 (56 - value) / 8 for big-endian mode. */
5942 if (GET_CODE (x
) != CONST_INT
5943 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5946 || (INTVAL (x
) & 7) != 0)
5947 output_operand_lossage ("invalid %%s value");
5949 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5951 ? (56 - INTVAL (x
)) / 8
5956 /* Same, except compute (64 - c) / 8 */
5958 if (GET_CODE (x
) != CONST_INT
5959 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5960 && (INTVAL (x
) & 7) != 8)
5961 output_operand_lossage ("invalid %%s value");
5963 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5968 /* On Unicos/Mk systems: use a DEX expression if the symbol
5969 clashes with a register name. */
5970 int dex
= unicosmk_need_dex (x
);
5972 fprintf (file
, "DEX(%d)", dex
);
5974 output_addr_const (file
, x
);
5978 case 'C': case 'D': case 'c': case 'd':
5979 /* Write out comparison name. */
5981 enum rtx_code c
= GET_CODE (x
);
5983 if (GET_RTX_CLASS (c
) != '<')
5984 output_operand_lossage ("invalid %%C value");
5986 else if (code
== 'D')
5987 c
= reverse_condition (c
);
5988 else if (code
== 'c')
5989 c
= swap_condition (c
);
5990 else if (code
== 'd')
5991 c
= swap_condition (reverse_condition (c
));
5994 fprintf (file
, "ule");
5996 fprintf (file
, "ult");
5997 else if (c
== UNORDERED
)
5998 fprintf (file
, "un");
6000 fprintf (file
, "%s", GET_RTX_NAME (c
));
6005 /* Write the divide or modulus operator. */
6006 switch (GET_CODE (x
))
6009 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
6012 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
6015 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
6018 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
6021 output_operand_lossage ("invalid %%E value");
6027 /* Write "_u" for unaligned access. */
6028 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
6029 fprintf (file
, "_u");
6033 if (GET_CODE (x
) == REG
)
6034 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
6035 else if (GET_CODE (x
) == MEM
)
6036 output_address (XEXP (x
, 0));
6037 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6039 switch (XINT (XEXP (x
, 0), 1))
6043 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
6046 output_operand_lossage ("unknown relocation unspec");
6051 output_addr_const (file
, x
);
6055 output_operand_lossage ("invalid %%xn code");
6060 print_operand_address (file
, addr
)
6065 HOST_WIDE_INT offset
= 0;
6067 if (GET_CODE (addr
) == AND
)
6068 addr
= XEXP (addr
, 0);
6070 if (GET_CODE (addr
) == PLUS
6071 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
6073 offset
= INTVAL (XEXP (addr
, 1));
6074 addr
= XEXP (addr
, 0);
6077 if (GET_CODE (addr
) == LO_SUM
)
6079 const char *reloc16
, *reloclo
;
6080 rtx op1
= XEXP (addr
, 1);
6082 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
6084 op1
= XEXP (op1
, 0);
6085 switch (XINT (op1
, 1))
6089 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
6093 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
6096 output_operand_lossage ("unknown relocation unspec");
6100 output_addr_const (file
, XVECEXP (op1
, 0, 0));
6105 reloclo
= "gprellow";
6106 output_addr_const (file
, op1
);
6112 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6115 addr
= XEXP (addr
, 0);
6116 if (GET_CODE (addr
) == REG
)
6117 basereg
= REGNO (addr
);
6118 else if (GET_CODE (addr
) == SUBREG
6119 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6120 basereg
= subreg_regno (addr
);
6124 fprintf (file
, "($%d)\t\t!%s", basereg
,
6125 (basereg
== 29 ? reloc16
: reloclo
));
6129 if (GET_CODE (addr
) == REG
)
6130 basereg
= REGNO (addr
);
6131 else if (GET_CODE (addr
) == SUBREG
6132 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6133 basereg
= subreg_regno (addr
);
6134 else if (GET_CODE (addr
) == CONST_INT
)
6135 offset
= INTVAL (addr
);
6137 #if TARGET_ABI_OPEN_VMS
6138 else if (GET_CODE (addr
) == SYMBOL_REF
)
6140 fprintf (file
, "%s", XSTR (addr
, 0));
6143 else if (GET_CODE (addr
) == CONST
6144 && GET_CODE (XEXP (addr
, 0)) == PLUS
6145 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
6147 fprintf (file
, "%s+%d",
6148 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
6149 INTVAL (XEXP (XEXP (addr
, 0), 1)));
6157 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6158 fprintf (file
, "($%d)", basereg
);
6161 /* Emit RTL insns to initialize the variable parts of a trampoline at
6162 TRAMP. FNADDR is an RTX for the address of the function's pure
6163 code. CXT is an RTX for the static chain value for the function.
6165 The three offset parameters are for the individual template's
6166 layout. A JMPOFS < 0 indicates that the trampoline does not
6167 contain instructions at all.
6169 We assume here that a function will be called many more times than
6170 its address is taken (e.g., it might be passed to qsort), so we
6171 take the trouble to initialize the "hint" field in the JMP insn.
6172 Note that the hint field is PC (new) + 4 * bits 13:0. */
6175 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
6176 rtx tramp
, fnaddr
, cxt
;
6177 int fnofs
, cxtofs
, jmpofs
;
6179 rtx temp
, temp1
, addr
;
6180 /* VMS really uses DImode pointers in memory at this point. */
6181 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
6183 #ifdef POINTERS_EXTEND_UNSIGNED
6184 fnaddr
= convert_memory_address (mode
, fnaddr
);
6185 cxt
= convert_memory_address (mode
, cxt
);
6188 /* Store function address and CXT. */
6189 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
6190 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
6191 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
6192 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
6194 /* This has been disabled since the hint only has a 32k range, and in
6195 no existing OS is the stack within 32k of the text segment. */
6196 if (0 && jmpofs
>= 0)
6198 /* Compute hint value. */
6199 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
6200 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
6202 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
6203 build_int_2 (2, 0), NULL_RTX
, 1);
6204 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
6205 GEN_INT (0x3fff), 0);
6207 /* Merge in the hint. */
6208 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
6209 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
6210 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
6211 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
6213 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
6216 #ifdef TRANSFER_FROM_TRAMPOLINE
6217 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
6218 0, VOIDmode
, 1, tramp
, Pmode
);
6222 emit_insn (gen_imb ());
6225 /* Determine where to put an argument to a function.
6226 Value is zero to push the argument on the stack,
6227 or a hard register in which to store the argument.
6229 MODE is the argument's machine mode.
6230 TYPE is the data type of the argument (as a tree).
6231 This is null for libcalls where that information may
6233 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6234 the preceding args and about the function being called.
6235 NAMED is nonzero if this argument is a named parameter
6236 (otherwise it is an extra parameter matching an ellipsis).
6238 On Alpha the first 6 words of args are normally in registers
6239 and the rest are pushed. */
6242 function_arg (cum
, mode
, type
, named
)
6243 CUMULATIVE_ARGS cum
;
6244 enum machine_mode mode
;
6246 int named ATTRIBUTE_UNUSED
;
6251 /* Set up defaults for FP operands passed in FP registers, and
6252 integral operands passed in integer registers. */
6254 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6255 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6260 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6261 the three platforms, so we can't avoid conditional compilation. */
6262 #if TARGET_ABI_OPEN_VMS
6264 if (mode
== VOIDmode
)
6265 return alpha_arg_info_reg_val (cum
);
6267 num_args
= cum
.num_args
;
6268 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6272 #if TARGET_ABI_UNICOSMK
6276 /* If this is the last argument, generate the call info word (CIW). */
6277 /* ??? We don't include the caller's line number in the CIW because
6278 I don't know how to determine it if debug infos are turned off. */
6279 if (mode
== VOIDmode
)
6288 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6289 if (cum
.reg_args_type
[i
])
6290 lo
|= (1 << (7 - i
));
6292 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6295 lo
|= cum
.num_reg_words
;
6297 #if HOST_BITS_PER_WIDE_INT == 32
6298 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6300 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6301 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6304 ciw
= immed_double_const (lo
, hi
, DImode
);
6306 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6307 UNSPEC_UMK_LOAD_CIW
);
6310 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6311 num_args
= cum
.num_reg_words
;
6312 if (MUST_PASS_IN_STACK (mode
, type
)
6313 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6315 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6319 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6320 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6322 /* The argument fits in two registers. Note that we still need to
6323 reserve a register for empty structures. */
6327 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6330 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6331 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6332 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6342 /* VOID is passed as a special flag for "last argument". */
6343 if (type
== void_type_node
)
6345 else if (MUST_PASS_IN_STACK (mode
, type
))
6347 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6350 #endif /* TARGET_ABI_UNICOSMK */
6351 #endif /* TARGET_ABI_OPEN_VMS */
6353 return gen_rtx_REG (mode
, num_args
+ basereg
);
6357 alpha_build_va_list ()
6359 tree base
, ofs
, record
, type_decl
;
6361 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6362 return ptr_type_node
;
6364 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6365 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6366 TREE_CHAIN (record
) = type_decl
;
6367 TYPE_NAME (record
) = type_decl
;
6369 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6371 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6373 DECL_FIELD_CONTEXT (ofs
) = record
;
6375 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6377 DECL_FIELD_CONTEXT (base
) = record
;
6378 TREE_CHAIN (base
) = ofs
;
6380 TYPE_FIELDS (record
) = base
;
6381 layout_type (record
);
6386 /* Perform any needed actions needed for a function that is receiving a
6387 variable number of arguments.
6389 On the Alpha, we allocate space for all 12 arg registers, but only
6390 push those that are remaining. However, if NO registers need to be
6391 saved, don't allocate any space. This is not only because we won't
6392 need the space, but because AP includes the current_pretend_args_size
6393 and we don't want to mess up any ap-relative addresses already made.
6395 If we are not to use the floating-point registers, save the integer
6396 registers where we would put the floating-point registers. This is
6397 not the most efficient way to implement varargs with just one register
6398 class, but it isn't worth doing anything more efficient in this rare
6402 alpha_setup_incoming_varargs(cum
, mode
, type
, pretend_size
, no_rtl
)
6403 CUMULATIVE_ARGS cum
;
6404 enum machine_mode mode ATTRIBUTE_UNUSED
;
6405 tree type ATTRIBUTE_UNUSED
;
6414 int set
= get_varargs_alias_set ();
6417 tmp
= gen_rtx_MEM (BLKmode
,
6418 plus_constant (virtual_incoming_args_rtx
,
6419 (cum
+ 6) * UNITS_PER_WORD
));
6420 set_mem_alias_set (tmp
, set
);
6421 move_block_from_reg (16 + cum
, tmp
, 6 - cum
, (6 - cum
) * UNITS_PER_WORD
);
6423 tmp
= gen_rtx_MEM (BLKmode
,
6424 plus_constant (virtual_incoming_args_rtx
,
6425 cum
* UNITS_PER_WORD
));
6426 set_mem_alias_set (tmp
, set
);
6427 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
6428 6 - cum
, (6 - cum
) * UNITS_PER_WORD
);
6430 *pretend_size
= 12 * UNITS_PER_WORD
;
6434 alpha_va_start (valist
, nextarg
)
6436 rtx nextarg ATTRIBUTE_UNUSED
;
6438 HOST_WIDE_INT offset
;
6439 tree t
, offset_field
, base_field
;
6441 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6444 if (TARGET_ABI_UNICOSMK
)
6445 std_expand_builtin_va_start (valist
, nextarg
);
6447 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6448 up by 48, storing fp arg registers in the first 48 bytes, and the
6449 integer arg registers in the next 48 bytes. This is only done,
6450 however, if any integer registers need to be stored.
6452 If no integer registers need be stored, then we must subtract 48
6453 in order to account for the integer arg registers which are counted
6454 in argsize above, but which are not actually stored on the stack.
6455 Must further be careful here about structures straddling the last
6456 integer argument register; that futzes with pretend_args_size,
6457 which changes the meaning of AP. */
6460 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6462 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6464 if (TARGET_ABI_OPEN_VMS
)
6466 nextarg
= plus_constant (nextarg
, offset
);
6467 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6468 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6469 make_tree (ptr_type_node
, nextarg
));
6470 TREE_SIDE_EFFECTS (t
) = 1;
6472 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6476 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6477 offset_field
= TREE_CHAIN (base_field
);
6479 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6480 valist
, base_field
);
6481 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6482 valist
, offset_field
);
6484 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6485 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6486 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6487 TREE_SIDE_EFFECTS (t
) = 1;
6488 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6490 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6491 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6492 TREE_SIDE_EFFECTS (t
) = 1;
6493 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6498 alpha_va_arg (valist
, type
)
6502 tree t
, type_size
, rounded_size
;
6503 tree offset_field
, base_field
, addr_tree
, addend
;
6504 tree wide_type
, wide_ofs
;
6507 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6508 return std_expand_builtin_va_arg (valist
, type
);
6510 if (type
== error_mark_node
6511 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6512 || TREE_OVERFLOW (type_size
))
6513 rounded_size
= size_zero_node
;
6515 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6516 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6517 fold (build (PLUS_EXPR
, sizetype
,
6523 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6524 offset_field
= TREE_CHAIN (base_field
);
6526 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6527 valist
, base_field
);
6528 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6529 valist
, offset_field
);
6531 /* If the type could not be passed in registers, skip the block
6532 reserved for the registers. */
6533 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6535 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6536 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6537 offset_field
, build_int_2 (6*8, 0)));
6538 TREE_SIDE_EFFECTS (t
) = 1;
6539 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6542 wide_type
= make_signed_type (64);
6543 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6547 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6550 rounded_size
= size_int (UNITS_PER_WORD
);
6552 else if (FLOAT_TYPE_P (type
))
6554 tree fpaddend
, cond
;
6556 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6557 addend
, build_int_2 (-6*8, 0)));
6559 cond
= fold (build (LT_EXPR
, integer_type_node
,
6560 wide_ofs
, build_int_2 (6*8, 0)));
6562 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6566 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6567 base_field
, addend
);
6569 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6570 addr
= copy_to_reg (addr
);
6572 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6573 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6574 offset_field
, rounded_size
));
6575 TREE_SIDE_EFFECTS (t
) = 1;
6576 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6580 addr
= force_reg (Pmode
, addr
);
6581 addr
= gen_rtx_MEM (Pmode
, addr
);
6591 ALPHA_BUILTIN_CMPBGE
,
6592 ALPHA_BUILTIN_EXTBL
,
6593 ALPHA_BUILTIN_EXTWL
,
6594 ALPHA_BUILTIN_EXTLL
,
6595 ALPHA_BUILTIN_EXTQL
,
6596 ALPHA_BUILTIN_EXTWH
,
6597 ALPHA_BUILTIN_EXTLH
,
6598 ALPHA_BUILTIN_EXTQH
,
6599 ALPHA_BUILTIN_INSBL
,
6600 ALPHA_BUILTIN_INSWL
,
6601 ALPHA_BUILTIN_INSLL
,
6602 ALPHA_BUILTIN_INSQL
,
6603 ALPHA_BUILTIN_INSWH
,
6604 ALPHA_BUILTIN_INSLH
,
6605 ALPHA_BUILTIN_INSQH
,
6606 ALPHA_BUILTIN_MSKBL
,
6607 ALPHA_BUILTIN_MSKWL
,
6608 ALPHA_BUILTIN_MSKLL
,
6609 ALPHA_BUILTIN_MSKQL
,
6610 ALPHA_BUILTIN_MSKWH
,
6611 ALPHA_BUILTIN_MSKLH
,
6612 ALPHA_BUILTIN_MSKQH
,
6613 ALPHA_BUILTIN_UMULH
,
6615 ALPHA_BUILTIN_ZAPNOT
,
6616 ALPHA_BUILTIN_AMASK
,
6617 ALPHA_BUILTIN_IMPLVER
,
6619 ALPHA_BUILTIN_THREAD_POINTER
,
6620 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6623 ALPHA_BUILTIN_MINUB8
,
6624 ALPHA_BUILTIN_MINSB8
,
6625 ALPHA_BUILTIN_MINUW4
,
6626 ALPHA_BUILTIN_MINSW4
,
6627 ALPHA_BUILTIN_MAXUB8
,
6628 ALPHA_BUILTIN_MAXSB8
,
6629 ALPHA_BUILTIN_MAXUW4
,
6630 ALPHA_BUILTIN_MAXSW4
,
6634 ALPHA_BUILTIN_UNPKBL
,
6635 ALPHA_BUILTIN_UNPKBW
,
6640 ALPHA_BUILTIN_CTPOP
,
6645 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6646 CODE_FOR_builtin_cmpbge
,
6647 CODE_FOR_builtin_extbl
,
6648 CODE_FOR_builtin_extwl
,
6649 CODE_FOR_builtin_extll
,
6650 CODE_FOR_builtin_extql
,
6651 CODE_FOR_builtin_extwh
,
6652 CODE_FOR_builtin_extlh
,
6653 CODE_FOR_builtin_extqh
,
6654 CODE_FOR_builtin_insbl
,
6655 CODE_FOR_builtin_inswl
,
6656 CODE_FOR_builtin_insll
,
6657 CODE_FOR_builtin_insql
,
6658 CODE_FOR_builtin_inswh
,
6659 CODE_FOR_builtin_inslh
,
6660 CODE_FOR_builtin_insqh
,
6661 CODE_FOR_builtin_mskbl
,
6662 CODE_FOR_builtin_mskwl
,
6663 CODE_FOR_builtin_mskll
,
6664 CODE_FOR_builtin_mskql
,
6665 CODE_FOR_builtin_mskwh
,
6666 CODE_FOR_builtin_msklh
,
6667 CODE_FOR_builtin_mskqh
,
6668 CODE_FOR_umuldi3_highpart
,
6669 CODE_FOR_builtin_zap
,
6670 CODE_FOR_builtin_zapnot
,
6671 CODE_FOR_builtin_amask
,
6672 CODE_FOR_builtin_implver
,
6673 CODE_FOR_builtin_rpcc
,
6678 CODE_FOR_builtin_minub8
,
6679 CODE_FOR_builtin_minsb8
,
6680 CODE_FOR_builtin_minuw4
,
6681 CODE_FOR_builtin_minsw4
,
6682 CODE_FOR_builtin_maxub8
,
6683 CODE_FOR_builtin_maxsb8
,
6684 CODE_FOR_builtin_maxuw4
,
6685 CODE_FOR_builtin_maxsw4
,
6686 CODE_FOR_builtin_perr
,
6687 CODE_FOR_builtin_pklb
,
6688 CODE_FOR_builtin_pkwb
,
6689 CODE_FOR_builtin_unpkbl
,
6690 CODE_FOR_builtin_unpkbw
,
6693 CODE_FOR_builtin_cttz
,
6694 CODE_FOR_builtin_ctlz
,
6695 CODE_FOR_builtin_ctpop
6698 struct alpha_builtin_def
6701 enum alpha_builtin code
;
6702 unsigned int target_mask
;
6705 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6706 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6707 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6710 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6711 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6712 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6713 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6714 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6715 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6716 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6717 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6718 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6721 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6722 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6723 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6724 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6725 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6726 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6727 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6728 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6729 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6730 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6731 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6732 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6733 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6734 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6735 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6736 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6737 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6738 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6739 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6740 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6741 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6742 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6743 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6744 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6745 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6746 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6747 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6748 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6749 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6750 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6751 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6752 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6753 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6754 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6755 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6759 alpha_init_builtins ()
6761 const struct alpha_builtin_def
*p
;
6765 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6767 p
= zero_arg_builtins
;
6768 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6769 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6770 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6773 ftype
= build_function_type_list (long_integer_type_node
,
6774 long_integer_type_node
, NULL_TREE
);
6776 p
= one_arg_builtins
;
6777 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6778 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6779 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6782 ftype
= build_function_type_list (long_integer_type_node
,
6783 long_integer_type_node
,
6784 long_integer_type_node
, NULL_TREE
);
6786 p
= two_arg_builtins
;
6787 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6788 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6789 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6792 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6793 builtin_function ("__builtin_thread_pointer", ftype
,
6794 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6797 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6798 builtin_function ("__builtin_set_thread_pointer", ftype
,
6799 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6803 /* Expand an expression EXP that calls a built-in function,
6804 with result going to TARGET if that's convenient
6805 (and in mode MODE if that's convenient).
6806 SUBTARGET may be used as the target for computing one of EXP's operands.
6807 IGNORE is nonzero if the value is to be ignored. */
6810 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6813 rtx subtarget ATTRIBUTE_UNUSED
;
6814 enum machine_mode mode ATTRIBUTE_UNUSED
;
6815 int ignore ATTRIBUTE_UNUSED
;
6819 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6820 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6821 tree arglist
= TREE_OPERAND (exp
, 1);
6822 enum insn_code icode
;
6823 rtx op
[MAX_ARGS
], pat
;
6827 if (fcode
>= ALPHA_BUILTIN_max
)
6828 internal_error ("bad builtin fcode");
6829 icode
= code_for_builtin
[fcode
];
6831 internal_error ("bad builtin fcode");
6833 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6835 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6837 arglist
= TREE_CHAIN (arglist
), arity
++)
6839 const struct insn_operand_data
*insn_op
;
6841 tree arg
= TREE_VALUE (arglist
);
6842 if (arg
== error_mark_node
)
6844 if (arity
> MAX_ARGS
)
6847 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6849 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6851 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6852 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6857 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6859 || GET_MODE (target
) != tmode
6860 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6861 target
= gen_reg_rtx (tmode
);
6867 pat
= GEN_FCN (icode
) (target
);
6871 pat
= GEN_FCN (icode
) (target
, op
[0]);
6873 pat
= GEN_FCN (icode
) (op
[0]);
6876 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6891 /* This page contains routines that are used to determine what the function
6892 prologue and epilogue code will do and write them out. */
6894 /* Compute the size of the save area in the stack. */
6896 /* These variables are used for communication between the following functions.
6897 They indicate various things about the current function being compiled
6898 that are used to tell what kind of prologue, epilogue and procedure
6899 descriptior to generate. */
6901 /* Nonzero if we need a stack procedure. */
6902 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6903 static enum alpha_procedure_types alpha_procedure_type
;
6905 /* Register number (either FP or SP) that is used to unwind the frame. */
6906 static int vms_unwind_regno
;
6908 /* Register number used to save FP. We need not have one for RA since
6909 we don't modify it for register procedures. This is only defined
6910 for register frame procedures. */
6911 static int vms_save_fp_regno
;
6913 /* Register number used to reference objects off our PV. */
6914 static int vms_base_regno
;
6916 /* Compute register masks for saved registers. */
6919 alpha_sa_mask (imaskP
, fmaskP
)
6920 unsigned long *imaskP
;
6921 unsigned long *fmaskP
;
6923 unsigned long imask
= 0;
6924 unsigned long fmask
= 0;
6927 /* Irritatingly, there are two kinds of thunks -- those created with
6928 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6929 through the regular part of the compiler. In the
6930 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6931 info, but assemble_start_function wants to output .frame and
6932 .mask directives. */
6933 if (current_function_is_thunk
&& !no_new_pseudos
)
6940 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6941 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6943 /* One for every register we have to save. */
6944 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6945 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6946 && regs_ever_live
[i
] && i
!= REG_RA
6947 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6950 imask
|= (1UL << i
);
6952 fmask
|= (1UL << (i
- 32));
6955 /* We need to restore these for the handler. */
6956 if (current_function_calls_eh_return
)
6959 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6960 if (regno
== INVALID_REGNUM
)
6962 imask
|= 1UL << regno
;
6965 /* If any register spilled, then spill the return address also. */
6966 /* ??? This is required by the Digital stack unwind specification
6967 and isn't needed if we're doing Dwarf2 unwinding. */
6968 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6969 imask
|= (1UL << REG_RA
);
6978 unsigned long mask
[2];
6982 alpha_sa_mask (&mask
[0], &mask
[1]);
6984 if (TARGET_ABI_UNICOSMK
)
6986 if (mask
[0] || mask
[1])
6991 for (j
= 0; j
< 2; ++j
)
6992 for (i
= 0; i
< 32; ++i
)
6993 if ((mask
[j
] >> i
) & 1)
6997 if (TARGET_ABI_UNICOSMK
)
6999 /* We might not need to generate a frame if we don't make any calls
7000 (including calls to __T3E_MISMATCH if this is a vararg function),
7001 don't have any local variables which require stack slots, don't
7002 use alloca and have not determined that we need a frame for other
7005 alpha_procedure_type
7006 = (sa_size
|| get_frame_size() != 0
7007 || current_function_outgoing_args_size
7008 || current_function_stdarg
|| current_function_calls_alloca
7009 || frame_pointer_needed
)
7010 ? PT_STACK
: PT_REGISTER
;
7012 /* Always reserve space for saving callee-saved registers if we
7013 need a frame as required by the calling convention. */
7014 if (alpha_procedure_type
== PT_STACK
)
7017 else if (TARGET_ABI_OPEN_VMS
)
7019 /* Start by assuming we can use a register procedure if we don't
7020 make any calls (REG_RA not used) or need to save any
7021 registers and a stack procedure if we do. */
7022 if ((mask
[0] >> REG_RA
) & 1)
7023 alpha_procedure_type
= PT_STACK
;
7024 else if (get_frame_size() != 0)
7025 alpha_procedure_type
= PT_REGISTER
;
7027 alpha_procedure_type
= PT_NULL
;
7029 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7030 made the final decision on stack procedure vs register procedure. */
7031 if (alpha_procedure_type
== PT_STACK
)
7034 /* Decide whether to refer to objects off our PV via FP or PV.
7035 If we need FP for something else or if we receive a nonlocal
7036 goto (which expects PV to contain the value), we must use PV.
7037 Otherwise, start by assuming we can use FP. */
7040 = (frame_pointer_needed
7041 || current_function_has_nonlocal_label
7042 || alpha_procedure_type
== PT_STACK
7043 || current_function_outgoing_args_size
)
7044 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7046 /* If we want to copy PV into FP, we need to find some register
7047 in which to save FP. */
7049 vms_save_fp_regno
= -1;
7050 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7051 for (i
= 0; i
< 32; i
++)
7052 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
7053 vms_save_fp_regno
= i
;
7055 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7056 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7057 else if (alpha_procedure_type
== PT_NULL
)
7058 vms_base_regno
= REG_PV
;
7060 /* Stack unwinding should be done via FP unless we use it for PV. */
7061 vms_unwind_regno
= (vms_base_regno
== REG_PV
7062 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7064 /* If this is a stack procedure, allow space for saving FP and RA. */
7065 if (alpha_procedure_type
== PT_STACK
)
7070 /* Our size must be even (multiple of 16 bytes). */
7078 /* Define the offset between two registers, one to be eliminated,
7079 and the other its replacement, at the start of a routine. */
7082 alpha_initial_elimination_offset (from
, to
)
7083 unsigned int from
, to ATTRIBUTE_UNUSED
;
7087 ret
= alpha_sa_size ();
7088 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
7090 if (from
== FRAME_POINTER_REGNUM
)
7092 else if (from
== ARG_POINTER_REGNUM
)
7093 ret
+= (ALPHA_ROUND (get_frame_size ()
7094 + current_function_pretend_args_size
)
7095 - current_function_pretend_args_size
);
7103 alpha_pv_save_size ()
7106 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7113 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7116 #if TARGET_ABI_OPEN_VMS
7118 const struct attribute_spec vms_attribute_table
[] =
7120 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7121 { "overlaid", 0, 0, true, false, false, NULL
},
7122 { "global", 0, 0, true, false, false, NULL
},
7123 { "initialize", 0, 0, true, false, false, NULL
},
7124 { NULL
, 0, 0, false, false, false, NULL
}
7130 find_lo_sum_using_gp (px
, data
)
7132 void *data ATTRIBUTE_UNUSED
;
7134 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7138 alpha_find_lo_sum_using_gp (insn
)
7141 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7145 alpha_does_function_need_gp ()
7149 /* The GP being variable is an OSF abi thing. */
7150 if (! TARGET_ABI_OSF
)
7153 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7156 if (current_function_is_thunk
)
7159 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7160 Even if we are a static function, we still need to do this in case
7161 our address is taken and passed to something like qsort. */
7163 push_topmost_sequence ();
7164 insn
= get_insns ();
7165 pop_topmost_sequence ();
7167 for (; insn
; insn
= NEXT_INSN (insn
))
7169 && GET_CODE (PATTERN (insn
)) != USE
7170 && GET_CODE (PATTERN (insn
)) != CLOBBER
7171 && get_attr_usegp (insn
))
7177 /* Write a version stamp. Don't write anything if we are running as a
7178 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
7185 alpha_write_verstamp (file
)
7186 FILE *file ATTRIBUTE_UNUSED
;
7189 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
7193 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7197 set_frame_related_p ()
7199 rtx seq
= get_insns ();
7210 while (insn
!= NULL_RTX
)
7212 RTX_FRAME_RELATED_P (insn
) = 1;
7213 insn
= NEXT_INSN (insn
);
7215 seq
= emit_insn (seq
);
7219 seq
= emit_insn (seq
);
7220 RTX_FRAME_RELATED_P (seq
) = 1;
7225 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7227 /* Write function prologue. */
7229 /* On vms we have two kinds of functions:
7231 - stack frame (PROC_STACK)
7232 these are 'normal' functions with local vars and which are
7233 calling other functions
7234 - register frame (PROC_REGISTER)
7235 keeps all data in registers, needs no stack
7237 We must pass this to the assembler so it can generate the
7238 proper pdsc (procedure descriptor)
7239 This is done with the '.pdesc' command.
7241 On not-vms, we don't really differentiate between the two, as we can
7242 simply allocate stack without saving registers. */
7245 alpha_expand_prologue ()
7247 /* Registers to save. */
7248 unsigned long imask
= 0;
7249 unsigned long fmask
= 0;
7250 /* Stack space needed for pushing registers clobbered by us. */
7251 HOST_WIDE_INT sa_size
;
7252 /* Complete stack size needed. */
7253 HOST_WIDE_INT frame_size
;
7254 /* Offset from base reg to register save area. */
7255 HOST_WIDE_INT reg_offset
;
7259 sa_size
= alpha_sa_size ();
7261 frame_size
= get_frame_size ();
7262 if (TARGET_ABI_OPEN_VMS
)
7263 frame_size
= ALPHA_ROUND (sa_size
7264 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7266 + current_function_pretend_args_size
);
7267 else if (TARGET_ABI_UNICOSMK
)
7268 /* We have to allocate space for the DSIB if we generate a frame. */
7269 frame_size
= ALPHA_ROUND (sa_size
7270 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7271 + ALPHA_ROUND (frame_size
7272 + current_function_outgoing_args_size
);
7274 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7276 + ALPHA_ROUND (frame_size
7277 + current_function_pretend_args_size
));
7279 if (TARGET_ABI_OPEN_VMS
)
7282 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7284 alpha_sa_mask (&imask
, &fmask
);
7286 /* Emit an insn to reload GP, if needed. */
7289 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7290 if (alpha_function_needs_gp
)
7291 emit_insn (gen_prologue_ldgp ());
7294 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7295 the call to mcount ourselves, rather than having the linker do it
7296 magically in response to -pg. Since _mcount has special linkage,
7297 don't represent the call as a call. */
7298 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7299 emit_insn (gen_prologue_mcount ());
7301 if (TARGET_ABI_UNICOSMK
)
7302 unicosmk_gen_dsib (&imask
);
7304 /* Adjust the stack by the frame size. If the frame size is > 4096
7305 bytes, we need to be sure we probe somewhere in the first and last
7306 4096 bytes (we can probably get away without the latter test) and
7307 every 8192 bytes in between. If the frame size is > 32768, we
7308 do this in a loop. Otherwise, we generate the explicit probe
7311 Note that we are only allowed to adjust sp once in the prologue. */
7313 if (frame_size
<= 32768)
7315 if (frame_size
> 4096)
7320 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7323 while ((probed
+= 8192) < frame_size
);
7325 /* We only have to do this probe if we aren't saving registers. */
7326 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7327 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7330 if (frame_size
!= 0)
7331 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7332 GEN_INT (TARGET_ABI_UNICOSMK
7338 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7339 number of 8192 byte blocks to probe. We then probe each block
7340 in the loop and then set SP to the proper location. If the
7341 amount remaining is > 4096, we have to do one more probe if we
7342 are not saving any registers. */
7344 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7345 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7346 rtx ptr
= gen_rtx_REG (DImode
, 22);
7347 rtx count
= gen_rtx_REG (DImode
, 23);
7350 emit_move_insn (count
, GEN_INT (blocks
));
7351 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7352 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7354 /* Because of the difficulty in emitting a new basic block this
7355 late in the compilation, generate the loop as a single insn. */
7356 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7358 if (leftover
> 4096 && sa_size
== 0)
7360 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7361 MEM_VOLATILE_P (last
) = 1;
7362 emit_move_insn (last
, const0_rtx
);
7365 if (TARGET_ABI_WINDOWS_NT
)
7367 /* For NT stack unwind (done by 'reverse execution'), it's
7368 not OK to take the result of a loop, even though the value
7369 is already in ptr, so we reload it via a single operation
7370 and subtract it to sp.
7372 Yes, that's correct -- we have to reload the whole constant
7373 into a temporary via ldah+lda then subtract from sp. To
7374 ensure we get ldah+lda, we use a special pattern. */
7376 HOST_WIDE_INT lo
, hi
;
7377 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7378 hi
= frame_size
- lo
;
7380 emit_move_insn (ptr
, GEN_INT (hi
));
7381 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7382 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7387 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7388 GEN_INT (-leftover
)));
7391 /* This alternative is special, because the DWARF code cannot
7392 possibly intuit through the loop above. So we invent this
7393 note it looks at instead. */
7394 RTX_FRAME_RELATED_P (seq
) = 1;
7396 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7397 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7398 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7399 GEN_INT (TARGET_ABI_UNICOSMK
7405 if (!TARGET_ABI_UNICOSMK
)
7407 /* Cope with very large offsets to the register save area. */
7408 sa_reg
= stack_pointer_rtx
;
7409 if (reg_offset
+ sa_size
> 0x8000)
7411 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7414 if (low
+ sa_size
<= 0x8000)
7415 bias
= reg_offset
- low
, reg_offset
= low
;
7417 bias
= reg_offset
, reg_offset
= 0;
7419 sa_reg
= gen_rtx_REG (DImode
, 24);
7420 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7424 /* Save regs in stack order. Beginning with VMS PV. */
7425 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7427 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7428 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7429 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7432 /* Save register RA next. */
7433 if (imask
& (1UL << REG_RA
))
7435 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7436 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7437 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7438 imask
&= ~(1UL << REG_RA
);
7442 /* Now save any other registers required to be saved. */
7443 for (i
= 0; i
< 32; i
++)
7444 if (imask
& (1UL << i
))
7446 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7447 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7448 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7452 for (i
= 0; i
< 32; i
++)
7453 if (fmask
& (1UL << i
))
7455 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7456 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7457 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7461 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7463 /* The standard frame on the T3E includes space for saving registers.
7464 We just have to use it. We don't have to save the return address and
7465 the old frame pointer here - they are saved in the DSIB. */
7468 for (i
= 9; i
< 15; i
++)
7469 if (imask
& (1UL << i
))
7471 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7473 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7474 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7477 for (i
= 2; i
< 10; i
++)
7478 if (fmask
& (1UL << i
))
7480 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7482 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7483 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7488 if (TARGET_ABI_OPEN_VMS
)
7490 if (alpha_procedure_type
== PT_REGISTER
)
7491 /* Register frame procedures save the fp.
7492 ?? Ought to have a dwarf2 save for this. */
7493 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7494 hard_frame_pointer_rtx
);
7496 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7497 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7498 gen_rtx_REG (DImode
, REG_PV
)));
7500 if (alpha_procedure_type
!= PT_NULL
7501 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7502 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7504 /* If we have to allocate space for outgoing args, do it now. */
7505 if (current_function_outgoing_args_size
!= 0)
7508 = emit_move_insn (stack_pointer_rtx
,
7510 (hard_frame_pointer_rtx
,
7512 (current_function_outgoing_args_size
))));
7514 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7515 if ! frame_pointer_needed. Setting the bit will change the CFA
7516 computation rule to use sp again, which would be wrong if we had
7517 frame_pointer_needed, as this means sp might move unpredictably
7521 frame_pointer_needed
7522 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7524 current_function_outgoing_args_size != 0
7525 => alpha_procedure_type != PT_NULL,
7527 so when we are not setting the bit here, we are guaranteed to
7528 have emited an FRP frame pointer update just before. */
7529 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7532 else if (!TARGET_ABI_UNICOSMK
)
7534 /* If we need a frame pointer, set it from the stack pointer. */
7535 if (frame_pointer_needed
)
7537 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7538 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7540 /* This must always be the last instruction in the
7541 prologue, thus we emit a special move + clobber. */
7542 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7543 stack_pointer_rtx
, sa_reg
)));
7547 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7548 the prologue, for exception handling reasons, we cannot do this for
7549 any insn that might fault. We could prevent this for mems with a
7550 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7551 have to prevent all such scheduling with a blockage.
7553 Linux, on the other hand, never bothered to implement OSF/1's
7554 exception handling, and so doesn't care about such things. Anyone
7555 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7557 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7558 emit_insn (gen_blockage ());
7561 /* Output the textual info surrounding the prologue. */
7564 alpha_start_function (file
, fnname
, decl
)
7567 tree decl ATTRIBUTE_UNUSED
;
7569 unsigned long imask
= 0;
7570 unsigned long fmask
= 0;
7571 /* Stack space needed for pushing registers clobbered by us. */
7572 HOST_WIDE_INT sa_size
;
7573 /* Complete stack size needed. */
7574 HOST_WIDE_INT frame_size
;
7575 /* Offset from base reg to register save area. */
7576 HOST_WIDE_INT reg_offset
;
7577 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7580 /* Don't emit an extern directive for functions defined in the same file. */
7581 if (TARGET_ABI_UNICOSMK
)
7584 name_tree
= get_identifier (fnname
);
7585 TREE_ASM_WRITTEN (name_tree
) = 1;
7588 alpha_fnname
= fnname
;
7589 sa_size
= alpha_sa_size ();
7591 frame_size
= get_frame_size ();
7592 if (TARGET_ABI_OPEN_VMS
)
7593 frame_size
= ALPHA_ROUND (sa_size
7594 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7596 + current_function_pretend_args_size
);
7597 else if (TARGET_ABI_UNICOSMK
)
7598 frame_size
= ALPHA_ROUND (sa_size
7599 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7600 + ALPHA_ROUND (frame_size
7601 + current_function_outgoing_args_size
);
7603 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7605 + ALPHA_ROUND (frame_size
7606 + current_function_pretend_args_size
));
7608 if (TARGET_ABI_OPEN_VMS
)
7611 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7613 alpha_sa_mask (&imask
, &fmask
);
7615 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7616 We have to do that before the .ent directive as we cannot switch
7617 files within procedures with native ecoff because line numbers are
7618 linked to procedure descriptors.
7619 Outputting the lineno helps debugging of one line functions as they
7620 would otherwise get no line number at all. Please note that we would
7621 like to put out last_linenum from final.c, but it is not accessible. */
7623 if (write_symbols
== SDB_DEBUG
)
7625 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7626 ASM_OUTPUT_SOURCE_FILENAME (file
,
7627 DECL_SOURCE_FILE (current_function_decl
));
7629 #ifdef ASM_OUTPUT_SOURCE_LINE
7630 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7631 ASM_OUTPUT_SOURCE_LINE (file
,
7632 DECL_SOURCE_LINE (current_function_decl
));
7636 /* Issue function start and label. */
7637 if (TARGET_ABI_OPEN_VMS
7638 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7640 fputs ("\t.ent ", file
);
7641 assemble_name (file
, fnname
);
7644 /* If the function needs GP, we'll write the "..ng" label there.
7645 Otherwise, do it here. */
7647 && ! alpha_function_needs_gp
7648 && ! current_function_is_thunk
)
7651 assemble_name (file
, fnname
);
7652 fputs ("..ng:\n", file
);
7656 strcpy (entry_label
, fnname
);
7657 if (TARGET_ABI_OPEN_VMS
)
7658 strcat (entry_label
, "..en");
7660 /* For public functions, the label must be globalized by appending an
7661 additional colon. */
7662 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7663 strcat (entry_label
, ":");
7665 ASM_OUTPUT_LABEL (file
, entry_label
);
7666 inside_function
= TRUE
;
7668 if (TARGET_ABI_OPEN_VMS
)
7669 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7671 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7672 && !flag_inhibit_size_directive
)
7674 /* Set flags in procedure descriptor to request IEEE-conformant
7675 math-library routines. The value we set it to is PDSC_EXC_IEEE
7676 (/usr/include/pdsc.h). */
7677 fputs ("\t.eflag 48\n", file
);
7680 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7681 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7682 alpha_arg_offset
= -frame_size
+ 48;
7684 /* Describe our frame. If the frame size is larger than an integer,
7685 print it as zero to avoid an assembler error. We won't be
7686 properly describing such a frame, but that's the best we can do. */
7687 if (TARGET_ABI_UNICOSMK
)
7689 else if (TARGET_ABI_OPEN_VMS
)
7691 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7692 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7693 frame_size
>= (1UL << 31) ? 0 : frame_size
);
7694 fputs (",$26,", file
);
7695 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7698 else if (!flag_inhibit_size_directive
)
7700 fprintf (file
, "\t.frame $%d,",
7701 (frame_pointer_needed
7702 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7703 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7704 frame_size
>= (1UL << 31) ? 0 : frame_size
);
7705 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7708 /* Describe which registers were spilled. */
7709 if (TARGET_ABI_UNICOSMK
)
7711 else if (TARGET_ABI_OPEN_VMS
)
7714 /* ??? Does VMS care if mask contains ra? The old code didn't
7715 set it, so I don't here. */
7716 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7718 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7719 if (alpha_procedure_type
== PT_REGISTER
)
7720 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7722 else if (!flag_inhibit_size_directive
)
7726 fprintf (file
, "\t.mask 0x%lx,", imask
);
7727 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7728 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7731 for (i
= 0; i
< 32; ++i
)
7732 if (imask
& (1UL << i
))
7738 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7739 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7740 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7745 #if TARGET_ABI_OPEN_VMS
7746 /* Ifdef'ed cause link_section are only available then. */
7747 readonly_data_section ();
7748 fprintf (file
, "\t.align 3\n");
7749 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7750 fputs ("\t.ascii \"", file
);
7751 assemble_name (file
, fnname
);
7752 fputs ("\\0\"\n", file
);
7753 alpha_need_linkage (fnname
, 1);
7758 /* Emit the .prologue note at the scheduled end of the prologue. */
7761 alpha_output_function_end_prologue (file
)
7764 if (TARGET_ABI_UNICOSMK
)
7766 else if (TARGET_ABI_OPEN_VMS
)
7767 fputs ("\t.prologue\n", file
);
7768 else if (TARGET_ABI_WINDOWS_NT
)
7769 fputs ("\t.prologue 0\n", file
);
7770 else if (!flag_inhibit_size_directive
)
7771 fprintf (file
, "\t.prologue %d\n",
7772 alpha_function_needs_gp
|| current_function_is_thunk
);
7775 /* Write function epilogue. */
7777 /* ??? At some point we will want to support full unwind, and so will
7778 need to mark the epilogue as well. At the moment, we just confuse
7781 #define FRP(exp) exp
7784 alpha_expand_epilogue ()
7786 /* Registers to save. */
7787 unsigned long imask
= 0;
7788 unsigned long fmask
= 0;
7789 /* Stack space needed for pushing registers clobbered by us. */
7790 HOST_WIDE_INT sa_size
;
7791 /* Complete stack size needed. */
7792 HOST_WIDE_INT frame_size
;
7793 /* Offset from base reg to register save area. */
7794 HOST_WIDE_INT reg_offset
;
7795 int fp_is_frame_pointer
, fp_offset
;
7796 rtx sa_reg
, sa_reg_exp
= NULL
;
7797 rtx sp_adj1
, sp_adj2
, mem
;
7801 sa_size
= alpha_sa_size ();
7803 frame_size
= get_frame_size ();
7804 if (TARGET_ABI_OPEN_VMS
)
7805 frame_size
= ALPHA_ROUND (sa_size
7806 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7808 + current_function_pretend_args_size
);
7809 else if (TARGET_ABI_UNICOSMK
)
7810 frame_size
= ALPHA_ROUND (sa_size
7811 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7812 + ALPHA_ROUND (frame_size
7813 + current_function_outgoing_args_size
);
7815 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7817 + ALPHA_ROUND (frame_size
7818 + current_function_pretend_args_size
));
7820 if (TARGET_ABI_OPEN_VMS
)
7822 if (alpha_procedure_type
== PT_STACK
)
7828 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7830 alpha_sa_mask (&imask
, &fmask
);
7833 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7834 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7836 sa_reg
= stack_pointer_rtx
;
7838 if (current_function_calls_eh_return
)
7839 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7843 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7845 /* If we have a frame pointer, restore SP from it. */
7846 if ((TARGET_ABI_OPEN_VMS
7847 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7848 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7849 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7851 /* Cope with very large offsets to the register save area. */
7852 if (reg_offset
+ sa_size
> 0x8000)
7854 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7857 if (low
+ sa_size
<= 0x8000)
7858 bias
= reg_offset
- low
, reg_offset
= low
;
7860 bias
= reg_offset
, reg_offset
= 0;
7862 sa_reg
= gen_rtx_REG (DImode
, 22);
7863 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7865 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7868 /* Restore registers in order, excepting a true frame pointer. */
7870 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7872 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7873 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7876 imask
&= ~(1UL << REG_RA
);
7878 for (i
= 0; i
< 32; ++i
)
7879 if (imask
& (1UL << i
))
7881 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7882 fp_offset
= reg_offset
;
7885 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7886 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7887 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7892 for (i
= 0; i
< 32; ++i
)
7893 if (fmask
& (1UL << i
))
7895 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7896 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7897 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7901 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7903 /* Restore callee-saved general-purpose registers. */
7907 for (i
= 9; i
< 15; i
++)
7908 if (imask
& (1UL << i
))
7910 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7912 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7913 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7917 for (i
= 2; i
< 10; i
++)
7918 if (fmask
& (1UL << i
))
7920 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7922 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7923 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7927 /* Restore the return address from the DSIB. */
7929 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7930 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7931 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7934 if (frame_size
|| eh_ofs
)
7936 sp_adj1
= stack_pointer_rtx
;
7940 sp_adj1
= gen_rtx_REG (DImode
, 23);
7941 emit_move_insn (sp_adj1
,
7942 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7945 /* If the stack size is large, begin computation into a temporary
7946 register so as not to interfere with a potential fp restore,
7947 which must be consecutive with an SP restore. */
7948 if (frame_size
< 32768
7949 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7950 sp_adj2
= GEN_INT (frame_size
);
7951 else if (TARGET_ABI_UNICOSMK
)
7953 sp_adj1
= gen_rtx_REG (DImode
, 23);
7954 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7955 sp_adj2
= const0_rtx
;
7957 else if (frame_size
< 0x40007fffL
)
7959 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7961 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7962 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7966 sp_adj1
= gen_rtx_REG (DImode
, 23);
7967 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7969 sp_adj2
= GEN_INT (low
);
7973 rtx tmp
= gen_rtx_REG (DImode
, 23);
7974 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7977 /* We can't drop new things to memory this late, afaik,
7978 so build it up by pieces. */
7979 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7980 -(frame_size
< 0)));
7986 /* From now on, things must be in order. So emit blockages. */
7988 /* Restore the frame pointer. */
7989 if (TARGET_ABI_UNICOSMK
)
7991 emit_insn (gen_blockage ());
7992 mem
= gen_rtx_MEM (DImode
,
7993 plus_constant (hard_frame_pointer_rtx
, -16));
7994 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7995 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7997 else if (fp_is_frame_pointer
)
7999 emit_insn (gen_blockage ());
8000 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
8001 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8002 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8004 else if (TARGET_ABI_OPEN_VMS
)
8006 emit_insn (gen_blockage ());
8007 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8008 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8011 /* Restore the stack pointer. */
8012 emit_insn (gen_blockage ());
8013 if (sp_adj2
== const0_rtx
)
8014 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
8016 FRP (emit_move_insn (stack_pointer_rtx
,
8017 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
8021 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8023 emit_insn (gen_blockage ());
8024 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8025 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8027 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8029 /* Decrement the frame pointer if the function does not have a
8032 emit_insn (gen_blockage ());
8033 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8034 hard_frame_pointer_rtx
, GEN_INT (-1))));
8039 /* Output the rest of the textual info surrounding the epilogue. */
8042 alpha_end_function (file
, fnname
, decl
)
8045 tree decl ATTRIBUTE_UNUSED
;
8047 /* End the function. */
8048 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8050 fputs ("\t.end ", file
);
8051 assemble_name (file
, fnname
);
8054 inside_function
= FALSE
;
8056 #if TARGET_ABI_OPEN_VMS
8057 alpha_write_linkage (file
, fnname
, decl
);
8060 /* Output jump tables and the static subroutine information block. */
8061 if (TARGET_ABI_UNICOSMK
)
8063 unicosmk_output_ssib (file
, fnname
);
8064 unicosmk_output_deferred_case_vectors (file
);
8069 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8071 In order to avoid the hordes of differences between generated code
8072 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8073 lots of code loading up large constants, generate rtl and emit it
8074 instead of going straight to text.
8076 Not sure why this idea hasn't been explored before... */
8079 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
8081 tree thunk_fndecl ATTRIBUTE_UNUSED
;
8082 HOST_WIDE_INT delta
;
8083 HOST_WIDE_INT vcall_offset
;
8086 HOST_WIDE_INT hi
, lo
;
8087 rtx
this, insn
, funexp
;
8089 /* We always require a valid GP. */
8090 emit_insn (gen_prologue_ldgp ());
8091 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
8093 /* Find the "this" pointer. If the function returns a structure,
8094 the structure return pointer is in $16. */
8095 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
8096 this = gen_rtx_REG (Pmode
, 17);
8098 this = gen_rtx_REG (Pmode
, 16);
8100 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8101 entire constant for the add. */
8102 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8103 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8104 if (hi
+ lo
== delta
)
8107 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
8109 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
8113 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8114 delta
, -(delta
< 0));
8115 emit_insn (gen_adddi3 (this, this, tmp
));
8118 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8123 tmp
= gen_rtx_REG (Pmode
, 0);
8124 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8126 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8127 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8128 if (hi
+ lo
== vcall_offset
)
8131 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8135 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8136 vcall_offset
, -(vcall_offset
< 0));
8137 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8141 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8144 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8146 emit_insn (gen_adddi3 (this, this, tmp
));
8149 /* Generate a tail call to the target function. */
8150 if (! TREE_USED (function
))
8152 assemble_external (function
);
8153 TREE_USED (function
) = 1;
8155 funexp
= XEXP (DECL_RTL (function
), 0);
8156 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8157 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8158 SIBLING_CALL_P (insn
) = 1;
8160 /* Run just enough of rest_of_compilation to get the insns emitted.
8161 There's not really enough bulk here to make other passes such as
8162 instruction scheduling worth while. Note that use_thunk calls
8163 assemble_start_function and assemble_end_function. */
8164 insn
= get_insns ();
8165 shorten_branches (insn
);
8166 final_start_function (insn
, file
, 1);
8167 final (insn
, file
, 1, 0);
8168 final_end_function ();
8170 #endif /* TARGET_ABI_OSF */
8172 /* Debugging support. */
8176 /* Count the number of sdb related labels are generated (to find block
8177 start and end boundaries). */
8179 int sdb_label_count
= 0;
8181 /* Next label # for each statement. */
8183 static int sym_lineno
= 0;
8185 /* Count the number of .file directives, so that .loc is up to date. */
8187 static int num_source_filenames
= 0;
8189 /* Name of the file containing the current function. */
8191 static const char *current_function_file
= "";
8193 /* Offsets to alpha virtual arg/local debugging pointers. */
8195 long alpha_arg_offset
;
8196 long alpha_auto_offset
;
8198 /* Emit a new filename to a stream. */
8201 alpha_output_filename (stream
, name
)
8205 static int first_time
= TRUE
;
8206 char ltext_label_name
[100];
8211 ++num_source_filenames
;
8212 current_function_file
= name
;
8213 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8214 output_quoted_string (stream
, name
);
8215 fprintf (stream
, "\n");
8216 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8217 fprintf (stream
, "\t#@stabs\n");
8220 else if (write_symbols
== DBX_DEBUG
)
8222 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
8223 fprintf (stream
, "%s", ASM_STABS_OP
);
8224 output_quoted_string (stream
, name
);
8225 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8228 else if (name
!= current_function_file
8229 && strcmp (name
, current_function_file
) != 0)
8231 if (inside_function
&& ! TARGET_GAS
)
8232 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8235 ++num_source_filenames
;
8236 current_function_file
= name
;
8237 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8240 output_quoted_string (stream
, name
);
8241 fprintf (stream
, "\n");
8245 /* Emit a linenumber to a stream. */
8248 alpha_output_lineno (stream
, line
)
8252 if (write_symbols
== DBX_DEBUG
)
8254 /* mips-tfile doesn't understand .stabd directives. */
8256 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8257 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8260 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8263 /* Structure to show the current status of registers and memory. */
8265 struct shadow_summary
8268 unsigned int i
: 31; /* Mask of int regs */
8269 unsigned int fp
: 31; /* Mask of fp regs */
8270 unsigned int mem
: 1; /* mem == imem | fpmem */
8274 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
8275 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
8277 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8278 to the summary structure. SET is nonzero if the insn is setting the
8279 object, otherwise zero. */
8282 summarize_insn (x
, sum
, set
)
8284 struct shadow_summary
*sum
;
8287 const char *format_ptr
;
8293 switch (GET_CODE (x
))
8295 /* ??? Note that this case would be incorrect if the Alpha had a
8296 ZERO_EXTRACT in SET_DEST. */
8298 summarize_insn (SET_SRC (x
), sum
, 0);
8299 summarize_insn (SET_DEST (x
), sum
, 1);
8303 summarize_insn (XEXP (x
, 0), sum
, 1);
8307 summarize_insn (XEXP (x
, 0), sum
, 0);
8311 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8312 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8316 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8317 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8321 summarize_insn (SUBREG_REG (x
), sum
, 0);
8326 int regno
= REGNO (x
);
8327 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8329 if (regno
== 31 || regno
== 63)
8335 sum
->defd
.i
|= mask
;
8337 sum
->defd
.fp
|= mask
;
8342 sum
->used
.i
|= mask
;
8344 sum
->used
.fp
|= mask
;
8355 /* Find the regs used in memory address computation: */
8356 summarize_insn (XEXP (x
, 0), sum
, 0);
8359 case CONST_INT
: case CONST_DOUBLE
:
8360 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8361 case SCRATCH
: case ASM_INPUT
:
8364 /* Handle common unary and binary ops for efficiency. */
8365 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8366 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8367 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8368 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8369 case NE
: case EQ
: case GE
: case GT
: case LE
:
8370 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8371 summarize_insn (XEXP (x
, 0), sum
, 0);
8372 summarize_insn (XEXP (x
, 1), sum
, 0);
8375 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8376 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8377 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8378 case SQRT
: case FFS
:
8379 summarize_insn (XEXP (x
, 0), sum
, 0);
8383 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8384 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8385 switch (format_ptr
[i
])
8388 summarize_insn (XEXP (x
, i
), sum
, 0);
8392 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8393 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8405 /* Ensure a sufficient number of `trapb' insns are in the code when
8406 the user requests code with a trap precision of functions or
8409 In naive mode, when the user requests a trap-precision of
8410 "instruction", a trapb is needed after every instruction that may
8411 generate a trap. This ensures that the code is resumption safe but
8414 When optimizations are turned on, we delay issuing a trapb as long
8415 as possible. In this context, a trap shadow is the sequence of
8416 instructions that starts with a (potentially) trap generating
8417 instruction and extends to the next trapb or call_pal instruction
8418 (but GCC never generates call_pal by itself). We can delay (and
8419 therefore sometimes omit) a trapb subject to the following
8422 (a) On entry to the trap shadow, if any Alpha register or memory
8423 location contains a value that is used as an operand value by some
8424 instruction in the trap shadow (live on entry), then no instruction
8425 in the trap shadow may modify the register or memory location.
8427 (b) Within the trap shadow, the computation of the base register
8428 for a memory load or store instruction may not involve using the
8429 result of an instruction that might generate an UNPREDICTABLE
8432 (c) Within the trap shadow, no register may be used more than once
8433 as a destination register. (This is to make life easier for the
8436 (d) The trap shadow may not include any branch instructions. */
8439 alpha_handle_trap_shadows (insns
)
8442 struct shadow_summary shadow
;
8443 int trap_pending
, exception_nesting
;
8447 exception_nesting
= 0;
8450 shadow
.used
.mem
= 0;
8451 shadow
.defd
= shadow
.used
;
8453 for (i
= insns
; i
; i
= NEXT_INSN (i
))
8455 if (GET_CODE (i
) == NOTE
)
8457 switch (NOTE_LINE_NUMBER (i
))
8459 case NOTE_INSN_EH_REGION_BEG
:
8460 exception_nesting
++;
8465 case NOTE_INSN_EH_REGION_END
:
8466 exception_nesting
--;
8471 case NOTE_INSN_EPILOGUE_BEG
:
8472 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8477 else if (trap_pending
)
8479 if (alpha_tp
== ALPHA_TP_FUNC
)
8481 if (GET_CODE (i
) == JUMP_INSN
8482 && GET_CODE (PATTERN (i
)) == RETURN
)
8485 else if (alpha_tp
== ALPHA_TP_INSN
)
8489 struct shadow_summary sum
;
8494 sum
.defd
= sum
.used
;
8496 switch (GET_CODE (i
))
8499 /* Annoyingly, get_attr_trap will abort on these. */
8500 if (GET_CODE (PATTERN (i
)) == USE
8501 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8504 summarize_insn (PATTERN (i
), &sum
, 0);
8506 if ((sum
.defd
.i
& shadow
.defd
.i
)
8507 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8509 /* (c) would be violated */
8513 /* Combine shadow with summary of current insn: */
8514 shadow
.used
.i
|= sum
.used
.i
;
8515 shadow
.used
.fp
|= sum
.used
.fp
;
8516 shadow
.used
.mem
|= sum
.used
.mem
;
8517 shadow
.defd
.i
|= sum
.defd
.i
;
8518 shadow
.defd
.fp
|= sum
.defd
.fp
;
8519 shadow
.defd
.mem
|= sum
.defd
.mem
;
8521 if ((sum
.defd
.i
& shadow
.used
.i
)
8522 || (sum
.defd
.fp
& shadow
.used
.fp
)
8523 || (sum
.defd
.mem
& shadow
.used
.mem
))
8525 /* (a) would be violated (also takes care of (b)) */
8526 if (get_attr_trap (i
) == TRAP_YES
8527 && ((sum
.defd
.i
& sum
.used
.i
)
8528 || (sum
.defd
.fp
& sum
.used
.fp
)))
8547 n
= emit_insn_before (gen_trapb (), i
);
8548 PUT_MODE (n
, TImode
);
8549 PUT_MODE (i
, TImode
);
8553 shadow
.used
.mem
= 0;
8554 shadow
.defd
= shadow
.used
;
8559 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8560 && GET_CODE (i
) == INSN
8561 && GET_CODE (PATTERN (i
)) != USE
8562 && GET_CODE (PATTERN (i
)) != CLOBBER
8563 && get_attr_trap (i
) == TRAP_YES
)
8565 if (optimize
&& !trap_pending
)
8566 summarize_insn (PATTERN (i
), &shadow
, 0);
8572 /* Alpha can only issue instruction groups simultaneously if they are
8573 suitibly aligned. This is very processor-specific. */
8575 enum alphaev4_pipe
{
8582 enum alphaev5_pipe
{
8593 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8594 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8595 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8596 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8597 static rtx alphaev4_next_nop
PARAMS ((int *));
8598 static rtx alphaev5_next_nop
PARAMS ((int *));
8600 static void alpha_align_insns
8601 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8603 static enum alphaev4_pipe
8604 alphaev4_insn_pipe (insn
)
8607 if (recog_memoized (insn
) < 0)
8609 if (get_attr_length (insn
) != 4)
8612 switch (get_attr_type (insn
))
8646 static enum alphaev5_pipe
8647 alphaev5_insn_pipe (insn
)
8650 if (recog_memoized (insn
) < 0)
8652 if (get_attr_length (insn
) != 4)
8655 switch (get_attr_type (insn
))
8696 /* IN_USE is a mask of the slots currently filled within the insn group.
8697 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8698 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8700 LEN is, of course, the length of the group in bytes. */
8703 alphaev4_next_group (insn
, pin_use
, plen
)
8705 int *pin_use
, *plen
;
8712 || GET_CODE (PATTERN (insn
)) == CLOBBER
8713 || GET_CODE (PATTERN (insn
)) == USE
)
8718 enum alphaev4_pipe pipe
;
8720 pipe
= alphaev4_insn_pipe (insn
);
8724 /* Force complex instructions to start new groups. */
8728 /* If this is a completely unrecognized insn, its an asm.
8729 We don't know how long it is, so record length as -1 to
8730 signal a needed realignment. */
8731 if (recog_memoized (insn
) < 0)
8734 len
= get_attr_length (insn
);
8738 if (in_use
& EV4_IB0
)
8740 if (in_use
& EV4_IB1
)
8745 in_use
|= EV4_IB0
| EV4_IBX
;
8749 if (in_use
& EV4_IB0
)
8751 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8759 if (in_use
& EV4_IB1
)
8769 /* Haifa doesn't do well scheduling branches. */
8770 if (GET_CODE (insn
) == JUMP_INSN
)
8774 insn
= next_nonnote_insn (insn
);
8776 if (!insn
|| ! INSN_P (insn
))
8779 /* Let Haifa tell us where it thinks insn group boundaries are. */
8780 if (GET_MODE (insn
) == TImode
)
8783 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8788 insn
= next_nonnote_insn (insn
);
8796 /* IN_USE is a mask of the slots currently filled within the insn group.
8797 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8798 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8800 LEN is, of course, the length of the group in bytes. */
8803 alphaev5_next_group (insn
, pin_use
, plen
)
8805 int *pin_use
, *plen
;
8812 || GET_CODE (PATTERN (insn
)) == CLOBBER
8813 || GET_CODE (PATTERN (insn
)) == USE
)
8818 enum alphaev5_pipe pipe
;
8820 pipe
= alphaev5_insn_pipe (insn
);
8824 /* Force complex instructions to start new groups. */
8828 /* If this is a completely unrecognized insn, its an asm.
8829 We don't know how long it is, so record length as -1 to
8830 signal a needed realignment. */
8831 if (recog_memoized (insn
) < 0)
8834 len
= get_attr_length (insn
);
8837 /* ??? Most of the places below, we would like to abort, as
8838 it would indicate an error either in Haifa, or in the
8839 scheduling description. Unfortunately, Haifa never
8840 schedules the last instruction of the BB, so we don't
8841 have an accurate TI bit to go off. */
8843 if (in_use
& EV5_E0
)
8845 if (in_use
& EV5_E1
)
8850 in_use
|= EV5_E0
| EV5_E01
;
8854 if (in_use
& EV5_E0
)
8856 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8864 if (in_use
& EV5_E1
)
8870 if (in_use
& EV5_FA
)
8872 if (in_use
& EV5_FM
)
8877 in_use
|= EV5_FA
| EV5_FAM
;
8881 if (in_use
& EV5_FA
)
8887 if (in_use
& EV5_FM
)
8900 /* Haifa doesn't do well scheduling branches. */
8901 /* ??? If this is predicted not-taken, slotting continues, except
8902 that no more IBR, FBR, or JSR insns may be slotted. */
8903 if (GET_CODE (insn
) == JUMP_INSN
)
8907 insn
= next_nonnote_insn (insn
);
8909 if (!insn
|| ! INSN_P (insn
))
8912 /* Let Haifa tell us where it thinks insn group boundaries are. */
8913 if (GET_MODE (insn
) == TImode
)
8916 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8921 insn
= next_nonnote_insn (insn
);
8930 alphaev4_next_nop (pin_use
)
8933 int in_use
= *pin_use
;
8936 if (!(in_use
& EV4_IB0
))
8941 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8946 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8959 alphaev5_next_nop (pin_use
)
8962 int in_use
= *pin_use
;
8965 if (!(in_use
& EV5_E1
))
8970 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8975 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8987 /* The instruction group alignment main loop. */
8990 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
8992 unsigned int max_align
;
8993 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
8994 rtx (*next_nop
) PARAMS ((int *));
8996 /* ALIGN is the known alignment for the insn group. */
8998 /* OFS is the offset of the current insn in the insn group. */
9000 int prev_in_use
, in_use
, len
;
9003 /* Let shorten branches care for assigning alignments to code labels. */
9004 shorten_branches (insns
);
9006 if (align_functions
< 4)
9008 else if ((unsigned int) align_functions
< max_align
)
9009 align
= align_functions
;
9013 ofs
= prev_in_use
= 0;
9015 if (GET_CODE (i
) == NOTE
)
9016 i
= next_nonnote_insn (i
);
9020 next
= (*next_group
) (i
, &in_use
, &len
);
9022 /* When we see a label, resync alignment etc. */
9023 if (GET_CODE (i
) == CODE_LABEL
)
9025 unsigned int new_align
= 1 << label_to_alignment (i
);
9027 if (new_align
>= align
)
9029 align
= new_align
< max_align
? new_align
: max_align
;
9033 else if (ofs
& (new_align
-1))
9034 ofs
= (ofs
| (new_align
-1)) + 1;
9039 /* Handle complex instructions special. */
9040 else if (in_use
== 0)
9042 /* Asms will have length < 0. This is a signal that we have
9043 lost alignment knowledge. Assume, however, that the asm
9044 will not mis-align instructions. */
9053 /* If the known alignment is smaller than the recognized insn group,
9054 realign the output. */
9055 else if ((int) align
< len
)
9057 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9060 where
= prev
= prev_nonnote_insn (i
);
9061 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
9064 /* Can't realign between a call and its gp reload. */
9065 if (! (TARGET_EXPLICIT_RELOCS
9066 && prev
&& GET_CODE (prev
) == CALL_INSN
))
9068 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9069 align
= 1 << new_log_align
;
9074 /* If the group won't fit in the same INT16 as the previous,
9075 we need to add padding to keep the group together. Rather
9076 than simply leaving the insn filling to the assembler, we
9077 can make use of the knowledge of what sorts of instructions
9078 were issued in the previous group to make sure that all of
9079 the added nops are really free. */
9080 else if (ofs
+ len
> (int) align
)
9082 int nop_count
= (align
- ofs
) / 4;
9085 /* Insert nops before labels, branches, and calls to truely merge
9086 the execution of the nops with the previous instruction group. */
9087 where
= prev_nonnote_insn (i
);
9090 if (GET_CODE (where
) == CODE_LABEL
)
9092 rtx where2
= prev_nonnote_insn (where
);
9093 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
9096 else if (GET_CODE (where
) == INSN
)
9103 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9104 while (--nop_count
);
9108 ofs
= (ofs
+ len
) & (align
- 1);
9109 prev_in_use
= in_use
;
9114 /* Machine dependent reorg pass. */
9120 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9121 alpha_handle_trap_shadows (insns
);
9123 /* Due to the number of extra trapb insns, don't bother fixing up
9124 alignment when trap precision is instruction. Moreover, we can
9125 only do our job when sched2 is run. */
9126 if (optimize
&& !optimize_size
9127 && alpha_tp
!= ALPHA_TP_INSN
9128 && flag_schedule_insns_after_reload
)
9130 if (alpha_cpu
== PROCESSOR_EV4
)
9131 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
9132 else if (alpha_cpu
== PROCESSOR_EV5
)
9133 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
9137 #ifdef OBJECT_FORMAT_ELF
9139 /* Switch to the section to which we should output X. The only thing
9140 special we do here is to honor small data. */
9143 alpha_elf_select_rtx_section (mode
, x
, align
)
9144 enum machine_mode mode
;
9146 unsigned HOST_WIDE_INT align
;
9148 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9149 /* ??? Consider using mergable sdata sections. */
9152 default_elf_select_rtx_section (mode
, x
, align
);
9155 #endif /* OBJECT_FORMAT_ELF */
9157 /* Structure to collect function names for final output in link section. */
9158 /* Note that items marked with GTY can't be ifdef'ed out. */
9160 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9161 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9163 struct alpha_links
GTY(())
9167 enum links_kind lkind
;
9168 enum reloc_kind rkind
;
9171 struct alpha_funcs
GTY(())
9174 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9178 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9179 splay_tree alpha_links_tree
;
9180 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9181 splay_tree alpha_funcs_tree
;
9183 static GTY(()) int alpha_funcs_num
;
9185 #if TARGET_ABI_OPEN_VMS
9187 /* Return the VMS argument type corresponding to MODE. */
9190 alpha_arg_type (mode
)
9191 enum machine_mode mode
;
9196 return TARGET_FLOAT_VAX
? FF
: FS
;
9198 return TARGET_FLOAT_VAX
? FD
: FT
;
9204 /* Return an rtx for an integer representing the VMS Argument Information
9208 alpha_arg_info_reg_val (cum
)
9209 CUMULATIVE_ARGS cum
;
9211 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9214 for (i
= 0; i
< 6; i
++)
9215 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9217 return GEN_INT (regval
);
9220 /* Make (or fake) .linkage entry for function call.
9222 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9224 Return an SYMBOL_REF rtx for the linkage. */
9227 alpha_need_linkage (name
, is_local
)
9231 splay_tree_node node
;
9232 struct alpha_links
*al
;
9239 struct alpha_funcs
*cfaf
;
9241 if (!alpha_funcs_tree
)
9242 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9243 splay_tree_compare_pointers
);
9245 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9248 cfaf
->num
= ++alpha_funcs_num
;
9250 splay_tree_insert (alpha_funcs_tree
,
9251 (splay_tree_key
) current_function_decl
,
9252 (splay_tree_value
) cfaf
);
9255 if (alpha_links_tree
)
9257 /* Is this name already defined? */
9259 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9262 al
= (struct alpha_links
*) node
->value
;
9265 /* Defined here but external assumed. */
9266 if (al
->lkind
== KIND_EXTERN
)
9267 al
->lkind
= KIND_LOCAL
;
9271 /* Used here but unused assumed. */
9272 if (al
->lkind
== KIND_UNUSED
)
9273 al
->lkind
= KIND_LOCAL
;
9279 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9281 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9282 name
= ggc_strdup (name
);
9284 /* Assume external if no definition. */
9285 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9287 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9288 get_identifier (name
);
9290 /* Construct a SYMBOL_REF for us to call. */
9292 size_t name_len
= strlen (name
);
9293 char *linksym
= alloca (name_len
+ 6);
9295 memcpy (linksym
+ 1, name
, name_len
);
9296 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9297 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9298 ggc_alloc_string (linksym
, name_len
+ 5));
9301 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9302 (splay_tree_value
) al
);
9308 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9314 splay_tree_node cfunnode
;
9315 struct alpha_funcs
*cfaf
;
9316 struct alpha_links
*al
;
9317 const char *name
= XSTR (linkage
, 0);
9319 cfaf
= (struct alpha_funcs
*) 0;
9320 al
= (struct alpha_links
*) 0;
9322 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9323 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9327 splay_tree_node lnode
;
9329 /* Is this name already defined? */
9331 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9333 al
= (struct alpha_links
*) lnode
->value
;
9336 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9344 splay_tree_node node
= 0;
9345 struct alpha_links
*anl
;
9350 name_len
= strlen (name
);
9352 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9353 al
->num
= cfaf
->num
;
9355 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9358 anl
= (struct alpha_links
*) node
->value
;
9359 al
->lkind
= anl
->lkind
;
9362 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9363 buflen
= strlen (buf
);
9364 linksym
= alloca (buflen
+ 1);
9365 memcpy (linksym
, buf
, buflen
+ 1);
9367 al
->linkage
= gen_rtx_SYMBOL_REF
9368 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9370 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9371 (splay_tree_value
) al
);
9375 al
->rkind
= KIND_CODEADDR
;
9377 al
->rkind
= KIND_LINKAGE
;
9380 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9386 alpha_write_one_linkage (node
, data
)
9387 splay_tree_node node
;
9390 const char *const name
= (const char *) node
->key
;
9391 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9392 FILE *stream
= (FILE *) data
;
9394 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9395 if (link
->rkind
== KIND_CODEADDR
)
9397 if (link
->lkind
== KIND_LOCAL
)
9399 /* Local and used */
9400 fprintf (stream
, "\t.quad %s..en\n", name
);
9404 /* External and used, request code address. */
9405 fprintf (stream
, "\t.code_address %s\n", name
);
9410 if (link
->lkind
== KIND_LOCAL
)
9412 /* Local and used, build linkage pair. */
9413 fprintf (stream
, "\t.quad %s..en\n", name
);
9414 fprintf (stream
, "\t.quad %s\n", name
);
9418 /* External and used, request linkage pair. */
9419 fprintf (stream
, "\t.linkage %s\n", name
);
9427 alpha_write_linkage (stream
, funname
, fundecl
)
9429 const char *funname
;
9432 splay_tree_node node
;
9433 struct alpha_funcs
*func
;
9436 fprintf (stream
, "\t.align 3\n");
9437 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9438 func
= (struct alpha_funcs
*) node
->value
;
9440 fputs ("\t.name ", stream
);
9441 assemble_name (stream
, funname
);
9442 fputs ("..na\n", stream
);
9443 ASM_OUTPUT_LABEL (stream
, funname
);
9444 fprintf (stream
, "\t.pdesc ");
9445 assemble_name (stream
, funname
);
9446 fprintf (stream
, "..en,%s\n",
9447 alpha_procedure_type
== PT_STACK
? "stack"
9448 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9452 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9453 /* splay_tree_delete (func->links); */
9457 /* Given a decl, a section name, and whether the decl initializer
9458 has relocs, choose attributes for the section. */
9460 #define SECTION_VMS_OVERLAY SECTION_FORGET
9461 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9462 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9465 vms_section_type_flags (decl
, name
, reloc
)
9470 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9472 if (decl
&& DECL_ATTRIBUTES (decl
)
9473 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9474 flags
|= SECTION_VMS_OVERLAY
;
9475 if (decl
&& DECL_ATTRIBUTES (decl
)
9476 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9477 flags
|= SECTION_VMS_GLOBAL
;
9478 if (decl
&& DECL_ATTRIBUTES (decl
)
9479 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9480 flags
|= SECTION_VMS_INITIALIZE
;
9485 /* Switch to an arbitrary section NAME with attributes as specified
9486 by FLAGS. ALIGN specifies any known alignment requirements for
9487 the section; 0 if the default should be used. */
9490 vms_asm_named_section (name
, flags
)
9494 fputc ('\n', asm_out_file
);
9495 fprintf (asm_out_file
, ".section\t%s", name
);
9497 if (flags
& SECTION_VMS_OVERLAY
)
9498 fprintf (asm_out_file
, ",OVR");
9499 if (flags
& SECTION_VMS_GLOBAL
)
9500 fprintf (asm_out_file
, ",GBL");
9501 if (flags
& SECTION_VMS_INITIALIZE
)
9502 fprintf (asm_out_file
, ",NOMOD");
9503 if (flags
& SECTION_DEBUG
)
9504 fprintf (asm_out_file
, ",NOWRT");
9506 fputc ('\n', asm_out_file
);
9509 /* Record an element in the table of global constructors. SYMBOL is
9510 a SYMBOL_REF of the function to be called; PRIORITY is a number
9511 between 0 and MAX_INIT_PRIORITY.
9513 Differs from default_ctors_section_asm_out_constructor in that the
9514 width of the .ctors entry is always 64 bits, rather than the 32 bits
9515 used by a normal pointer. */
9518 vms_asm_out_constructor (symbol
, priority
)
9520 int priority ATTRIBUTE_UNUSED
;
9523 assemble_align (BITS_PER_WORD
);
9524 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9528 vms_asm_out_destructor (symbol
, priority
)
9530 int priority ATTRIBUTE_UNUSED
;
9533 assemble_align (BITS_PER_WORD
);
9534 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9539 alpha_need_linkage (name
, is_local
)
9540 const char *name ATTRIBUTE_UNUSED
;
9541 int is_local ATTRIBUTE_UNUSED
;
9547 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9548 rtx linkage ATTRIBUTE_UNUSED
;
9549 tree cfundecl ATTRIBUTE_UNUSED
;
9550 int lflag ATTRIBUTE_UNUSED
;
9551 int rflag ATTRIBUTE_UNUSED
;
9556 #endif /* TARGET_ABI_OPEN_VMS */
9558 #if TARGET_ABI_UNICOSMK
9560 static void unicosmk_output_module_name
PARAMS ((FILE *));
9561 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9562 static void unicosmk_output_dex
PARAMS ((FILE *));
9563 static void unicosmk_output_externs
PARAMS ((FILE *));
9564 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9565 static const char *unicosmk_ssib_name
PARAMS ((void));
9566 static int unicosmk_special_name
PARAMS ((const char *));
9568 /* Define the offset between two registers, one to be eliminated, and the
9569 other its replacement, at the start of a routine. */
9572 unicosmk_initial_elimination_offset (from
, to
)
9578 fixed_size
= alpha_sa_size();
9579 if (fixed_size
!= 0)
9582 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9584 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9586 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9587 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9588 + ALPHA_ROUND (get_frame_size()));
9589 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9590 return (ALPHA_ROUND (fixed_size
)
9591 + ALPHA_ROUND (get_frame_size()
9592 + current_function_outgoing_args_size
));
9597 /* Output the module name for .ident and .end directives. We have to strip
9598 directories and add make sure that the module name starts with a letter
9602 unicosmk_output_module_name (file
)
9607 /* Strip directories. */
9609 name
= strrchr (main_input_filename
, '/');
9613 name
= main_input_filename
;
9615 /* CAM only accepts module names that start with a letter or '$'. We
9616 prefix the module name with a '$' if necessary. */
9618 if (!ISALPHA (*name
))
9620 output_clean_symbol_name (file
, name
);
9623 /* Output text that to appear at the beginning of an assembler file. */
9626 unicosmk_asm_file_start (file
)
9631 fputs ("\t.ident\t", file
);
9632 unicosmk_output_module_name (file
);
9633 fputs ("\n\n", file
);
9635 /* The Unicos/Mk assembler uses different register names. Instead of trying
9636 to support them, we simply use micro definitions. */
9638 /* CAM has different register names: rN for the integer register N and fN
9639 for the floating-point register N. Instead of trying to use these in
9640 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9643 for (i
= 0; i
< 32; ++i
)
9644 fprintf (file
, "$%d <- r%d\n", i
, i
);
9646 for (i
= 0; i
< 32; ++i
)
9647 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9651 /* The .align directive fill unused space with zeroes which does not work
9652 in code sections. We define the macro 'gcc@code@align' which uses nops
9653 instead. Note that it assumes that code sections always have the
9654 biggest possible alignment since . refers to the current offset from
9655 the beginning of the section. */
9657 fputs ("\t.macro gcc@code@align n\n", file
);
9658 fputs ("gcc@n@bytes = 1 << n\n", file
);
9659 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9660 fputs ("\t.if ne, gcc@here, 0\n", file
);
9661 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9662 fputs ("\tbis r31,r31,r31\n", file
);
9663 fputs ("\t.endr\n", file
);
9664 fputs ("\t.endif\n", file
);
9665 fputs ("\t.endm gcc@code@align\n\n", file
);
9667 /* Output extern declarations which should always be visible. */
9668 unicosmk_output_default_externs (file
);
9670 /* Open a dummy section. We always need to be inside a section for the
9671 section-switching code to work correctly.
9672 ??? This should be a module id or something like that. I still have to
9673 figure out what the rules for those are. */
9674 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9677 /* Output text to appear at the end of an assembler file. This includes all
9678 pending extern declarations and DEX expressions. */
9681 unicosmk_asm_file_end (file
)
9684 fputs ("\t.endp\n\n", file
);
9686 /* Output all pending externs. */
9688 unicosmk_output_externs (file
);
9690 /* Output dex definitions used for functions whose names conflict with
9693 unicosmk_output_dex (file
);
9695 fputs ("\t.end\t", file
);
9696 unicosmk_output_module_name (file
);
9700 /* Output the definition of a common variable. */
9703 unicosmk_output_common (file
, name
, size
, align
)
9710 printf ("T3E__: common %s\n", name
);
9713 fputs("\t.endp\n\n\t.psect ", file
);
9714 assemble_name(file
, name
);
9715 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9716 fprintf(file
, "\t.byte\t0:%d\n", size
);
9718 /* Mark the symbol as defined in this module. */
9719 name_tree
= get_identifier (name
);
9720 TREE_ASM_WRITTEN (name_tree
) = 1;
9723 #define SECTION_PUBLIC SECTION_MACH_DEP
9724 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9725 static int current_section_align
;
9728 unicosmk_section_type_flags (decl
, name
, reloc
)
9731 int reloc ATTRIBUTE_UNUSED
;
9733 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9738 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9740 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9741 if (align_functions_log
> current_section_align
)
9742 current_section_align
= align_functions_log
;
9744 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9745 flags
|= SECTION_MAIN
;
9748 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9750 if (TREE_PUBLIC (decl
))
9751 flags
|= SECTION_PUBLIC
;
9756 /* Generate a section name for decl and associate it with the
9760 unicosmk_unique_section (decl
, reloc
)
9762 int reloc ATTRIBUTE_UNUSED
;
9770 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9771 name
= default_strip_name_encoding (name
);
9772 len
= strlen (name
);
9774 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9778 /* It is essential that we prefix the section name here because
9779 otherwise the section names generated for constructors and
9780 destructors confuse collect2. */
9782 string
= alloca (len
+ 6);
9783 sprintf (string
, "code@%s", name
);
9784 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9786 else if (TREE_PUBLIC (decl
))
9787 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9792 string
= alloca (len
+ 6);
9793 sprintf (string
, "data@%s", name
);
9794 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9798 /* Switch to an arbitrary section NAME with attributes as specified
9799 by FLAGS. ALIGN specifies any known alignment requirements for
9800 the section; 0 if the default should be used. */
9803 unicosmk_asm_named_section (name
, flags
)
9809 /* Close the previous section. */
9811 fputs ("\t.endp\n\n", asm_out_file
);
9813 /* Find out what kind of section we are opening. */
9815 if (flags
& SECTION_MAIN
)
9816 fputs ("\t.start\tmain\n", asm_out_file
);
9818 if (flags
& SECTION_CODE
)
9820 else if (flags
& SECTION_PUBLIC
)
9825 if (current_section_align
!= 0)
9826 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9827 current_section_align
, kind
);
9829 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9833 unicosmk_insert_attributes (decl
, attr_ptr
)
9835 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9838 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9839 unicosmk_unique_section (decl
, 0);
9842 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9843 in code sections because .align fill unused space with zeroes. */
9846 unicosmk_output_align (file
, align
)
9850 if (inside_function
)
9851 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9853 fprintf (file
, "\t.align\t%d\n", align
);
9856 /* Add a case vector to the current function's list of deferred case
9857 vectors. Case vectors have to be put into a separate section because CAM
9858 does not allow data definitions in code sections. */
9861 unicosmk_defer_case_vector (lab
, vec
)
9865 struct machine_function
*machine
= cfun
->machine
;
9867 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9868 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9869 machine
->addr_list
);
9872 /* Output a case vector. */
9875 unicosmk_output_addr_vec (file
, vec
)
9879 rtx lab
= XEXP (vec
, 0);
9880 rtx body
= XEXP (vec
, 1);
9881 int vlen
= XVECLEN (body
, 0);
9884 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9886 for (idx
= 0; idx
< vlen
; idx
++)
9888 ASM_OUTPUT_ADDR_VEC_ELT
9889 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9893 /* Output current function's deferred case vectors. */
9896 unicosmk_output_deferred_case_vectors (file
)
9899 struct machine_function
*machine
= cfun
->machine
;
9902 if (machine
->addr_list
== NULL_RTX
)
9906 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9907 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9910 /* Set up the dynamic subprogram information block (DSIB) and update the
9911 frame pointer register ($15) for subroutines which have a frame. If the
9912 subroutine doesn't have a frame, simply increment $15. */
9915 unicosmk_gen_dsib (imaskP
)
9916 unsigned long * imaskP
;
9918 if (alpha_procedure_type
== PT_STACK
)
9920 const char *ssib_name
;
9923 /* Allocate 64 bytes for the DSIB. */
9925 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9927 emit_insn (gen_blockage ());
9929 /* Save the return address. */
9931 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9932 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9933 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9934 (*imaskP
) &= ~(1UL << REG_RA
);
9936 /* Save the old frame pointer. */
9938 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9939 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9940 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9941 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9943 emit_insn (gen_blockage ());
9945 /* Store the SSIB pointer. */
9947 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9948 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9949 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9951 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9952 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9953 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9955 /* Save the CIW index. */
9957 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9958 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9959 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9961 emit_insn (gen_blockage ());
9963 /* Set the new frame pointer. */
9965 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9966 stack_pointer_rtx
, GEN_INT (64))));
9971 /* Increment the frame pointer register to indicate that we do not
9974 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9975 hard_frame_pointer_rtx
, GEN_INT (1))));
9979 #define SSIB_PREFIX "__SSIB_"
9980 #define SSIB_PREFIX_LEN 7
9982 /* Generate the name of the SSIB section for the current function. */
9985 unicosmk_ssib_name ()
9987 /* This is ok since CAM won't be able to deal with names longer than that
9990 static char name
[256];
9996 x
= DECL_RTL (cfun
->decl
);
9997 if (GET_CODE (x
) != MEM
)
10000 if (GET_CODE (x
) != SYMBOL_REF
)
10002 fnname
= default_name_encoding (XSTR (x
, 0));
10004 len
= strlen (fnname
);
10005 if (len
+ SSIB_PREFIX_LEN
> 255)
10006 len
= 255 - SSIB_PREFIX_LEN
;
10008 strcpy (name
, SSIB_PREFIX
);
10009 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
10010 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10015 /* Output the static subroutine information block for the current
10019 unicosmk_output_ssib (file
, fnname
)
10021 const char *fnname
;
10027 struct machine_function
*machine
= cfun
->machine
;
10030 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10031 unicosmk_ssib_name ());
10033 /* Some required stuff and the function name length. */
10035 len
= strlen (fnname
);
10036 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10039 ??? We don't do that yet. */
10041 fputs ("\t.quad\t0\n", file
);
10043 /* Function address. */
10045 fputs ("\t.quad\t", file
);
10046 assemble_name (file
, fnname
);
10049 fputs ("\t.quad\t0\n", file
);
10050 fputs ("\t.quad\t0\n", file
);
10053 ??? We do it the same way Cray CC does it but this could be
10056 for( i
= 0; i
< len
; i
++ )
10057 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10058 if( (len
% 8) == 0 )
10059 fputs ("\t.quad\t0\n", file
);
10061 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10063 /* All call information words used in the function. */
10065 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10068 fprintf (file
, "\t.quad\t");
10069 #if HOST_BITS_PER_WIDE_INT == 32
10070 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
10071 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10073 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
10075 fprintf (file
, "\n");
10079 /* Add a call information word (CIW) to the list of the current function's
10080 CIWs and return its index.
10082 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10085 unicosmk_add_call_info_word (x
)
10089 struct machine_function
*machine
= cfun
->machine
;
10091 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10092 if (machine
->first_ciw
== NULL_RTX
)
10093 machine
->first_ciw
= node
;
10095 XEXP (machine
->last_ciw
, 1) = node
;
10097 machine
->last_ciw
= node
;
10098 ++machine
->ciw_count
;
10100 return GEN_INT (machine
->ciw_count
10101 + strlen (current_function_name
)/8 + 5);
10104 static char unicosmk_section_buf
[100];
10107 unicosmk_text_section ()
10109 static int count
= 0;
10110 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
10112 return unicosmk_section_buf
;
10116 unicosmk_data_section ()
10118 static int count
= 1;
10119 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
10121 return unicosmk_section_buf
;
10124 /* The Cray assembler doesn't accept extern declarations for symbols which
10125 are defined in the same file. We have to keep track of all global
10126 symbols which are referenced and/or defined in a source file and output
10127 extern declarations for those which are referenced but not defined at
10128 the end of file. */
10130 /* List of identifiers for which an extern declaration might have to be
10132 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10134 struct unicosmk_extern_list
10136 struct unicosmk_extern_list
*next
;
10140 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10142 /* Output extern declarations which are required for every asm file. */
10145 unicosmk_output_default_externs (file
)
10148 static const char *const externs
[] =
10149 { "__T3E_MISMATCH" };
10154 n
= ARRAY_SIZE (externs
);
10156 for (i
= 0; i
< n
; i
++)
10157 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10160 /* Output extern declarations for global symbols which are have been
10161 referenced but not defined. */
10164 unicosmk_output_externs (file
)
10167 struct unicosmk_extern_list
*p
;
10168 const char *real_name
;
10172 len
= strlen (user_label_prefix
);
10173 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10175 /* We have to strip the encoding and possibly remove user_label_prefix
10176 from the identifier in order to handle -fleading-underscore and
10177 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10178 real_name
= default_strip_name_encoding (p
->name
);
10179 if (len
&& p
->name
[0] == '*'
10180 && !memcmp (real_name
, user_label_prefix
, len
))
10183 name_tree
= get_identifier (real_name
);
10184 if (! TREE_ASM_WRITTEN (name_tree
))
10186 TREE_ASM_WRITTEN (name_tree
) = 1;
10187 fputs ("\t.extern\t", file
);
10188 assemble_name (file
, p
->name
);
10194 /* Record an extern. */
10197 unicosmk_add_extern (name
)
10200 struct unicosmk_extern_list
*p
;
10202 p
= (struct unicosmk_extern_list
*)
10203 xmalloc (sizeof (struct unicosmk_extern_list
));
10204 p
->next
= unicosmk_extern_head
;
10206 unicosmk_extern_head
= p
;
10209 /* The Cray assembler generates incorrect code if identifiers which
10210 conflict with register names are used as instruction operands. We have
10211 to replace such identifiers with DEX expressions. */
10213 /* Structure to collect identifiers which have been replaced by DEX
10215 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10217 struct unicosmk_dex
{
10218 struct unicosmk_dex
*next
;
10222 /* List of identifiers which have been replaced by DEX expressions. The DEX
10223 number is determined by the position in the list. */
10225 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10227 /* The number of elements in the DEX list. */
10229 static int unicosmk_dex_count
= 0;
10231 /* Check if NAME must be replaced by a DEX expression. */
10234 unicosmk_special_name (name
)
10237 if (name
[0] == '*')
10240 if (name
[0] == '$')
10243 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10248 case '1': case '2':
10249 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10252 return (name
[2] == '\0'
10253 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10256 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10260 /* Return the DEX number if X must be replaced by a DEX expression and 0
10264 unicosmk_need_dex (x
)
10267 struct unicosmk_dex
*dex
;
10271 if (GET_CODE (x
) != SYMBOL_REF
)
10275 if (! unicosmk_special_name (name
))
10278 i
= unicosmk_dex_count
;
10279 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10281 if (! strcmp (name
, dex
->name
))
10286 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10288 dex
->next
= unicosmk_dex_list
;
10289 unicosmk_dex_list
= dex
;
10291 ++unicosmk_dex_count
;
10292 return unicosmk_dex_count
;
10295 /* Output the DEX definitions for this file. */
10298 unicosmk_output_dex (file
)
10301 struct unicosmk_dex
*dex
;
10304 if (unicosmk_dex_list
== NULL
)
10307 fprintf (file
, "\t.dexstart\n");
10309 i
= unicosmk_dex_count
;
10310 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10312 fprintf (file
, "\tDEX (%d) = ", i
);
10313 assemble_name (file
, dex
->name
);
10318 fprintf (file
, "\t.dexend\n");
10324 unicosmk_output_deferred_case_vectors (file
)
10325 FILE *file ATTRIBUTE_UNUSED
;
10329 unicosmk_gen_dsib (imaskP
)
10330 unsigned long * imaskP ATTRIBUTE_UNUSED
;
10334 unicosmk_output_ssib (file
, fnname
)
10335 FILE * file ATTRIBUTE_UNUSED
;
10336 const char * fnname ATTRIBUTE_UNUSED
;
10340 unicosmk_add_call_info_word (x
)
10341 rtx x ATTRIBUTE_UNUSED
;
10347 unicosmk_need_dex (x
)
10348 rtx x ATTRIBUTE_UNUSED
;
10353 #endif /* TARGET_ABI_UNICOSMK */
10355 #include "gt-alpha.h"