1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
57 /* Specify which cpu to schedule for. */
59 enum processor_type alpha_cpu
;
60 static const char * const alpha_cpu_name
[] =
65 /* Specify how accurate floating-point traps need to be. */
67 enum alpha_trap_precision alpha_tp
;
69 /* Specify the floating-point rounding mode. */
71 enum alpha_fp_rounding_mode alpha_fprm
;
73 /* Specify which things cause traps. */
75 enum alpha_fp_trap_mode alpha_fptm
;
77 /* Specify bit size of immediate TLS offsets. */
79 int alpha_tls_size
= 32;
81 /* Strings decoded into the above options. */
83 const char *alpha_cpu_string
; /* -mcpu= */
84 const char *alpha_tune_string
; /* -mtune= */
85 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
86 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
87 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
88 const char *alpha_mlat_string
; /* -mmemory-latency= */
89 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
91 /* Save information from a "cmpxx" operation until the branch or scc is
94 struct alpha_compare alpha_compare
;
96 /* Nonzero if inside of a function, because the Alpha asm can't
97 handle .files inside of functions. */
99 static int inside_function
= FALSE
;
101 /* The number of cycles of latency we should assume on memory reads. */
103 int alpha_memory_latency
= 3;
105 /* Whether the function needs the GP. */
107 static int alpha_function_needs_gp
;
109 /* The alias set for prologue/epilogue register save/restore. */
111 static GTY(()) int alpha_sr_alias_set
;
113 /* The assembler name of the current function. */
115 static const char *alpha_fnname
;
117 /* The next explicit relocation sequence number. */
118 extern GTY(()) int alpha_next_sequence_number
;
119 int alpha_next_sequence_number
= 1;
121 /* The literal and gpdisp sequence numbers for this insn, as printed
122 by %# and %* respectively. */
123 extern GTY(()) int alpha_this_literal_sequence_number
;
124 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
125 int alpha_this_literal_sequence_number
;
126 int alpha_this_gpdisp_sequence_number
;
128 /* Costs of various operations on the different architectures. */
130 struct alpha_rtx_cost_data
132 unsigned char fp_add
;
133 unsigned char fp_mult
;
134 unsigned char fp_div_sf
;
135 unsigned char fp_div_df
;
136 unsigned char int_mult_si
;
137 unsigned char int_mult_di
;
138 unsigned char int_shift
;
139 unsigned char int_cmov
;
140 unsigned short int_div
;
143 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
146 COSTS_N_INSNS (6), /* fp_add */
147 COSTS_N_INSNS (6), /* fp_mult */
148 COSTS_N_INSNS (34), /* fp_div_sf */
149 COSTS_N_INSNS (63), /* fp_div_df */
150 COSTS_N_INSNS (23), /* int_mult_si */
151 COSTS_N_INSNS (23), /* int_mult_di */
152 COSTS_N_INSNS (2), /* int_shift */
153 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (97), /* int_div */
157 COSTS_N_INSNS (4), /* fp_add */
158 COSTS_N_INSNS (4), /* fp_mult */
159 COSTS_N_INSNS (15), /* fp_div_sf */
160 COSTS_N_INSNS (22), /* fp_div_df */
161 COSTS_N_INSNS (8), /* int_mult_si */
162 COSTS_N_INSNS (12), /* int_mult_di */
163 COSTS_N_INSNS (1) + 1, /* int_shift */
164 COSTS_N_INSNS (1), /* int_cmov */
165 COSTS_N_INSNS (83), /* int_div */
168 COSTS_N_INSNS (4), /* fp_add */
169 COSTS_N_INSNS (4), /* fp_mult */
170 COSTS_N_INSNS (12), /* fp_div_sf */
171 COSTS_N_INSNS (15), /* fp_div_df */
172 COSTS_N_INSNS (7), /* int_mult_si */
173 COSTS_N_INSNS (7), /* int_mult_di */
174 COSTS_N_INSNS (1), /* int_shift */
175 COSTS_N_INSNS (2), /* int_cmov */
176 COSTS_N_INSNS (86), /* int_div */
180 /* Similar but tuned for code size instead of execution latency. The
181 extra +N is fractional cost tuning based on latency. It's used to
182 encourage use of cheaper insns like shift, but only if there's just
185 static struct alpha_rtx_cost_data
const alpha_rtx_cost_size
=
187 COSTS_N_INSNS (1), /* fp_add */
188 COSTS_N_INSNS (1), /* fp_mult */
189 COSTS_N_INSNS (1), /* fp_div_sf */
190 COSTS_N_INSNS (1) + 1, /* fp_div_df */
191 COSTS_N_INSNS (1) + 1, /* int_mult_si */
192 COSTS_N_INSNS (1) + 2, /* int_mult_di */
193 COSTS_N_INSNS (1), /* int_shift */
194 COSTS_N_INSNS (1), /* int_cmov */
195 COSTS_N_INSNS (6), /* int_div */
198 /* Get the number of args of a function in one of two ways. */
199 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
200 #define NUM_ARGS current_function_args_info.num_args
202 #define NUM_ARGS current_function_args_info
208 /* Declarations of static functions. */
209 static struct machine_function
*alpha_init_machine_status (void);
210 static rtx
alpha_emit_xfloating_compare (enum rtx_code
, rtx
, rtx
);
212 #if TARGET_ABI_OPEN_VMS
213 static void alpha_write_linkage (FILE *, const char *, tree
);
216 static void unicosmk_output_deferred_case_vectors (FILE *);
217 static void unicosmk_gen_dsib (unsigned long *);
218 static void unicosmk_output_ssib (FILE *, const char *);
219 static int unicosmk_need_dex (rtx
);
221 /* Parse target option strings. */
224 override_options (void)
227 static const struct cpu_table
{
228 const char *const name
;
229 const enum processor_type processor
;
232 #define EV5_MASK (MASK_CPU_EV5)
233 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
234 { "ev4", PROCESSOR_EV4
, 0 },
235 { "ev45", PROCESSOR_EV4
, 0 },
236 { "21064", PROCESSOR_EV4
, 0 },
237 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
238 { "21164", PROCESSOR_EV5
, EV5_MASK
},
239 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
240 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
241 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
242 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
243 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
244 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
245 { "21264", PROCESSOR_EV6
, EV6_MASK
},
246 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
247 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
251 /* Unicos/Mk doesn't have shared libraries. */
252 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
254 warning ("-f%s ignored for Unicos/Mk (not supported)",
255 (flag_pic
> 1) ? "PIC" : "pic");
259 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
260 floating-point instructions. Make that the default for this target. */
261 if (TARGET_ABI_UNICOSMK
)
262 alpha_fprm
= ALPHA_FPRM_DYN
;
264 alpha_fprm
= ALPHA_FPRM_NORM
;
266 alpha_tp
= ALPHA_TP_PROG
;
267 alpha_fptm
= ALPHA_FPTM_N
;
269 /* We cannot use su and sui qualifiers for conversion instructions on
270 Unicos/Mk. I'm not sure if this is due to assembler or hardware
271 limitations. Right now, we issue a warning if -mieee is specified
272 and then ignore it; eventually, we should either get it right or
273 disable the option altogether. */
277 if (TARGET_ABI_UNICOSMK
)
278 warning ("-mieee not supported on Unicos/Mk");
281 alpha_tp
= ALPHA_TP_INSN
;
282 alpha_fptm
= ALPHA_FPTM_SU
;
286 if (TARGET_IEEE_WITH_INEXACT
)
288 if (TARGET_ABI_UNICOSMK
)
289 warning ("-mieee-with-inexact not supported on Unicos/Mk");
292 alpha_tp
= ALPHA_TP_INSN
;
293 alpha_fptm
= ALPHA_FPTM_SUI
;
299 if (! strcmp (alpha_tp_string
, "p"))
300 alpha_tp
= ALPHA_TP_PROG
;
301 else if (! strcmp (alpha_tp_string
, "f"))
302 alpha_tp
= ALPHA_TP_FUNC
;
303 else if (! strcmp (alpha_tp_string
, "i"))
304 alpha_tp
= ALPHA_TP_INSN
;
306 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string
);
309 if (alpha_fprm_string
)
311 if (! strcmp (alpha_fprm_string
, "n"))
312 alpha_fprm
= ALPHA_FPRM_NORM
;
313 else if (! strcmp (alpha_fprm_string
, "m"))
314 alpha_fprm
= ALPHA_FPRM_MINF
;
315 else if (! strcmp (alpha_fprm_string
, "c"))
316 alpha_fprm
= ALPHA_FPRM_CHOP
;
317 else if (! strcmp (alpha_fprm_string
,"d"))
318 alpha_fprm
= ALPHA_FPRM_DYN
;
320 error ("bad value %qs for -mfp-rounding-mode switch",
324 if (alpha_fptm_string
)
326 if (strcmp (alpha_fptm_string
, "n") == 0)
327 alpha_fptm
= ALPHA_FPTM_N
;
328 else if (strcmp (alpha_fptm_string
, "u") == 0)
329 alpha_fptm
= ALPHA_FPTM_U
;
330 else if (strcmp (alpha_fptm_string
, "su") == 0)
331 alpha_fptm
= ALPHA_FPTM_SU
;
332 else if (strcmp (alpha_fptm_string
, "sui") == 0)
333 alpha_fptm
= ALPHA_FPTM_SUI
;
335 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string
);
338 if (alpha_tls_size_string
)
340 if (strcmp (alpha_tls_size_string
, "16") == 0)
342 else if (strcmp (alpha_tls_size_string
, "32") == 0)
344 else if (strcmp (alpha_tls_size_string
, "64") == 0)
347 error ("bad value %qs for -mtls-size switch", alpha_tls_size_string
);
351 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
352 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
354 if (alpha_cpu_string
)
356 for (i
= 0; cpu_table
[i
].name
; i
++)
357 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
359 alpha_cpu
= cpu_table
[i
].processor
;
360 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
361 | MASK_CPU_EV5
| MASK_CPU_EV6
);
362 target_flags
|= cpu_table
[i
].flags
;
365 if (! cpu_table
[i
].name
)
366 error ("bad value %qs for -mcpu switch", alpha_cpu_string
);
369 if (alpha_tune_string
)
371 for (i
= 0; cpu_table
[i
].name
; i
++)
372 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
374 alpha_cpu
= cpu_table
[i
].processor
;
377 if (! cpu_table
[i
].name
)
378 error ("bad value %qs for -mcpu switch", alpha_tune_string
);
381 /* Do some sanity checks on the above options. */
383 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
385 warning ("trap mode not supported on Unicos/Mk");
386 alpha_fptm
= ALPHA_FPTM_N
;
389 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
390 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
392 warning ("fp software completion requires -mtrap-precision=i");
393 alpha_tp
= ALPHA_TP_INSN
;
398 /* Except for EV6 pass 1 (not released), we always have precise
399 arithmetic traps. Which means we can do software completion
400 without minding trap shadows. */
401 alpha_tp
= ALPHA_TP_PROG
;
404 if (TARGET_FLOAT_VAX
)
406 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
408 warning ("rounding mode not supported for VAX floats");
409 alpha_fprm
= ALPHA_FPRM_NORM
;
411 if (alpha_fptm
== ALPHA_FPTM_SUI
)
413 warning ("trap mode not supported for VAX floats");
414 alpha_fptm
= ALPHA_FPTM_SU
;
416 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
417 warning ("128-bit long double not supported for VAX floats");
418 target_flags
&= ~MASK_LONG_DOUBLE_128
;
425 if (!alpha_mlat_string
)
426 alpha_mlat_string
= "L1";
428 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
429 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
431 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
432 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
433 && alpha_mlat_string
[2] == '\0')
435 static int const cache_latency
[][4] =
437 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
438 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
439 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
442 lat
= alpha_mlat_string
[1] - '0';
443 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
445 warning ("L%d cache latency unknown for %s",
446 lat
, alpha_cpu_name
[alpha_cpu
]);
450 lat
= cache_latency
[alpha_cpu
][lat
-1];
452 else if (! strcmp (alpha_mlat_string
, "main"))
454 /* Most current memories have about 370ns latency. This is
455 a reasonable guess for a fast cpu. */
460 warning ("bad value %qs for -mmemory-latency", alpha_mlat_string
);
464 alpha_memory_latency
= lat
;
467 /* Default the definition of "small data" to 8 bytes. */
471 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
473 target_flags
|= MASK_SMALL_DATA
;
474 else if (flag_pic
== 2)
475 target_flags
&= ~MASK_SMALL_DATA
;
477 /* Align labels and loops for optimal branching. */
478 /* ??? Kludge these by not doing anything if we don't optimize and also if
479 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
480 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
482 if (align_loops
<= 0)
484 if (align_jumps
<= 0)
487 if (align_functions
<= 0)
488 align_functions
= 16;
490 /* Acquire a unique set number for our register saves and restores. */
491 alpha_sr_alias_set
= new_alias_set ();
493 /* Register variables and functions with the garbage collector. */
495 /* Set up function hooks. */
496 init_machine_status
= alpha_init_machine_status
;
498 /* Tell the compiler when we're using VAX floating point. */
499 if (TARGET_FLOAT_VAX
)
501 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
502 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
503 REAL_MODE_FORMAT (TFmode
) = NULL
;
507 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
510 zap_mask (HOST_WIDE_INT value
)
514 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
516 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
522 /* Return true if OP is valid for a particular TLS relocation.
523 We are already guaranteed that OP is a CONST. */
526 tls_symbolic_operand_1 (rtx op
, int size
, int unspec
)
530 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
532 op
= XVECEXP (op
, 0, 0);
534 if (GET_CODE (op
) != SYMBOL_REF
)
537 if (SYMBOL_REF_LOCAL_P (op
))
539 if (alpha_tls_size
> size
)
548 switch (SYMBOL_REF_TLS_MODEL (op
))
550 case TLS_MODEL_LOCAL_DYNAMIC
:
551 return unspec
== UNSPEC_DTPREL
;
552 case TLS_MODEL_INITIAL_EXEC
:
553 return unspec
== UNSPEC_TPREL
&& size
== 64;
554 case TLS_MODEL_LOCAL_EXEC
:
555 return unspec
== UNSPEC_TPREL
;
561 /* Used by aligned_memory_operand and unaligned_memory_operand to
562 resolve what reload is going to do with OP if it's a register. */
565 resolve_reload_operand (rtx op
)
567 if (reload_in_progress
)
570 if (GET_CODE (tmp
) == SUBREG
)
571 tmp
= SUBREG_REG (tmp
);
572 if (GET_CODE (tmp
) == REG
573 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
575 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
583 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
584 the range defined for C in [I-P]. */
587 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
592 /* An unsigned 8 bit constant. */
593 return (unsigned HOST_WIDE_INT
) value
< 0x100;
595 /* The constant zero. */
598 /* A signed 16 bit constant. */
599 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
601 /* A shifted signed 16 bit constant appropriate for LDAH. */
602 return ((value
& 0xffff) == 0
603 && ((value
) >> 31 == -1 || value
>> 31 == 0));
605 /* A constant that can be AND'ed with using a ZAP insn. */
606 return zap_mask (value
);
608 /* A complemented unsigned 8 bit constant. */
609 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
611 /* A negated unsigned 8 bit constant. */
612 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
614 /* The constant 1, 2 or 3. */
615 return value
== 1 || value
== 2 || value
== 3;
622 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
623 matches for C in [GH]. */
626 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
631 /* The floating point zero constant. */
632 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
633 && value
== CONST0_RTX (GET_MODE (value
)));
636 /* A valid operand of a ZAP insn. */
637 return (GET_MODE (value
) == VOIDmode
638 && zap_mask (CONST_DOUBLE_LOW (value
))
639 && zap_mask (CONST_DOUBLE_HIGH (value
)));
646 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
650 alpha_extra_constraint (rtx value
, int c
)
655 return normal_memory_operand (value
, VOIDmode
);
657 return direct_call_operand (value
, Pmode
);
659 return (GET_CODE (value
) == CONST_INT
660 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
662 return GET_CODE (value
) == HIGH
;
664 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
666 return (GET_CODE (value
) == CONST_VECTOR
667 && value
== CONST0_RTX (GET_MODE (value
)));
673 /* The scalar modes supported differs from the default check-what-c-supports
674 version in that sometimes TFmode is available even when long double
675 indicates only DFmode. On unicosmk, we have the situation that HImode
676 doesn't map to any C type, but of course we still support that. */
679 alpha_scalar_mode_supported_p (enum machine_mode mode
)
687 case TImode
: /* via optabs.c */
695 return TARGET_HAS_XFLOATING_LIBS
;
702 /* Alpha implements a couple of integer vector mode operations when
703 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
704 which allows the vectorizer to operate on e.g. move instructions,
705 or when expand_vector_operations can do something useful. */
708 alpha_vector_mode_supported_p (enum machine_mode mode
)
710 return mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
;
713 /* Return 1 if this function can directly return via $26. */
718 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
720 && alpha_sa_size () == 0
721 && get_frame_size () == 0
722 && current_function_outgoing_args_size
== 0
723 && current_function_pretend_args_size
== 0);
726 /* Return the ADDR_VEC associated with a tablejump insn. */
729 alpha_tablejump_addr_vec (rtx insn
)
733 tmp
= JUMP_LABEL (insn
);
736 tmp
= NEXT_INSN (tmp
);
739 if (GET_CODE (tmp
) == JUMP_INSN
740 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
741 return PATTERN (tmp
);
745 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
748 alpha_tablejump_best_label (rtx insn
)
750 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
751 rtx best_label
= NULL_RTX
;
753 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
754 there for edge frequency counts from profile data. */
758 int n_labels
= XVECLEN (jump_table
, 1);
762 for (i
= 0; i
< n_labels
; i
++)
766 for (j
= i
+ 1; j
< n_labels
; j
++)
767 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
768 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
771 if (count
> best_count
)
772 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
776 return best_label
? best_label
: const0_rtx
;
779 /* Return the TLS model to use for SYMBOL. */
781 static enum tls_model
782 tls_symbolic_operand_type (rtx symbol
)
784 enum tls_model model
;
786 if (GET_CODE (symbol
) != SYMBOL_REF
)
788 model
= SYMBOL_REF_TLS_MODEL (symbol
);
790 /* Local-exec with a 64-bit size is the same code as initial-exec. */
791 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
792 model
= TLS_MODEL_INITIAL_EXEC
;
797 /* Return true if the function DECL will share the same GP as any
798 function in the current unit of translation. */
801 decl_has_samegp (tree decl
)
803 /* Functions that are not local can be overridden, and thus may
804 not share the same gp. */
805 if (!(*targetm
.binds_local_p
) (decl
))
808 /* If -msmall-data is in effect, assume that there is only one GP
809 for the module, and so any local symbol has this property. We
810 need explicit relocations to be able to enforce this for symbols
811 not defined in this unit of translation, however. */
812 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
815 /* Functions that are not external are defined in this UoT. */
816 /* ??? Irritatingly, static functions not yet emitted are still
817 marked "external". Apply this to non-static functions only. */
818 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
821 /* Return true if EXP should be placed in the small data section. */
824 alpha_in_small_data_p (tree exp
)
826 /* We want to merge strings, so we never consider them small data. */
827 if (TREE_CODE (exp
) == STRING_CST
)
830 /* Functions are never in the small data area. Duh. */
831 if (TREE_CODE (exp
) == FUNCTION_DECL
)
834 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
836 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
837 if (strcmp (section
, ".sdata") == 0
838 || strcmp (section
, ".sbss") == 0)
843 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
845 /* If this is an incomplete type with size 0, then we can't put it
846 in sdata because it might be too big when completed. */
847 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
854 #if TARGET_ABI_OPEN_VMS
856 alpha_linkage_symbol_p (const char *symname
)
858 int symlen
= strlen (symname
);
861 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
866 #define LINKAGE_SYMBOL_REF_P(X) \
867 ((GET_CODE (X) == SYMBOL_REF \
868 && alpha_linkage_symbol_p (XSTR (X, 0))) \
869 || (GET_CODE (X) == CONST \
870 && GET_CODE (XEXP (X, 0)) == PLUS \
871 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
872 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
875 /* legitimate_address_p recognizes an RTL expression that is a valid
876 memory address for an instruction. The MODE argument is the
877 machine mode for the MEM expression that wants to use this address.
879 For Alpha, we have either a constant address or the sum of a
880 register and a constant address, or just a register. For DImode,
881 any of those forms can be surrounded with an AND that clear the
882 low-order three bits; this is an "unaligned" access. */
885 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
887 /* If this is an ldq_u type address, discard the outer AND. */
889 && GET_CODE (x
) == AND
890 && GET_CODE (XEXP (x
, 1)) == CONST_INT
891 && INTVAL (XEXP (x
, 1)) == -8)
894 /* Discard non-paradoxical subregs. */
895 if (GET_CODE (x
) == SUBREG
896 && (GET_MODE_SIZE (GET_MODE (x
))
897 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
900 /* Unadorned general registers are valid. */
903 ? STRICT_REG_OK_FOR_BASE_P (x
)
904 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
907 /* Constant addresses (i.e. +/- 32k) are valid. */
908 if (CONSTANT_ADDRESS_P (x
))
911 #if TARGET_ABI_OPEN_VMS
912 if (LINKAGE_SYMBOL_REF_P (x
))
916 /* Register plus a small constant offset is valid. */
917 if (GET_CODE (x
) == PLUS
)
919 rtx ofs
= XEXP (x
, 1);
922 /* Discard non-paradoxical subregs. */
923 if (GET_CODE (x
) == SUBREG
924 && (GET_MODE_SIZE (GET_MODE (x
))
925 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
931 && NONSTRICT_REG_OK_FP_BASE_P (x
)
932 && GET_CODE (ofs
) == CONST_INT
)
935 ? STRICT_REG_OK_FOR_BASE_P (x
)
936 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
937 && CONSTANT_ADDRESS_P (ofs
))
942 /* If we're managing explicit relocations, LO_SUM is valid, as
943 are small data symbols. */
944 else if (TARGET_EXPLICIT_RELOCS
)
946 if (small_symbolic_operand (x
, Pmode
))
949 if (GET_CODE (x
) == LO_SUM
)
951 rtx ofs
= XEXP (x
, 1);
954 /* Discard non-paradoxical subregs. */
955 if (GET_CODE (x
) == SUBREG
956 && (GET_MODE_SIZE (GET_MODE (x
))
957 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
960 /* Must have a valid base register. */
963 ? STRICT_REG_OK_FOR_BASE_P (x
)
964 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
967 /* The symbol must be local. */
968 if (local_symbolic_operand (ofs
, Pmode
)
969 || dtp32_symbolic_operand (ofs
, Pmode
)
970 || tp32_symbolic_operand (ofs
, Pmode
))
978 /* Build the SYMBOL_REF for __tls_get_addr. */
980 static GTY(()) rtx tls_get_addr_libfunc
;
983 get_tls_get_addr (void)
985 if (!tls_get_addr_libfunc
)
986 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
987 return tls_get_addr_libfunc
;
990 /* Try machine-dependent ways of modifying an illegitimate address
991 to be legitimate. If we find one, return the new, valid address. */
994 alpha_legitimize_address (rtx x
, rtx scratch
,
995 enum machine_mode mode ATTRIBUTE_UNUSED
)
997 HOST_WIDE_INT addend
;
999 /* If the address is (plus reg const_int) and the CONST_INT is not a
1000 valid offset, compute the high part of the constant and add it to
1001 the register. Then our address is (plus temp low-part-const). */
1002 if (GET_CODE (x
) == PLUS
1003 && GET_CODE (XEXP (x
, 0)) == REG
1004 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1005 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1007 addend
= INTVAL (XEXP (x
, 1));
1012 /* If the address is (const (plus FOO const_int)), find the low-order
1013 part of the CONST_INT. Then load FOO plus any high-order part of the
1014 CONST_INT into a register. Our address is (plus reg low-part-const).
1015 This is done to reduce the number of GOT entries. */
1017 && GET_CODE (x
) == CONST
1018 && GET_CODE (XEXP (x
, 0)) == PLUS
1019 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1021 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1022 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1026 /* If we have a (plus reg const), emit the load as in (2), then add
1027 the two registers, and finally generate (plus reg low-part-const) as
1030 && GET_CODE (x
) == PLUS
1031 && GET_CODE (XEXP (x
, 0)) == REG
1032 && GET_CODE (XEXP (x
, 1)) == CONST
1033 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1034 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1036 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1037 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1038 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1039 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1043 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1044 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1046 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1048 switch (tls_symbolic_operand_type (x
))
1050 case TLS_MODEL_GLOBAL_DYNAMIC
:
1053 r0
= gen_rtx_REG (Pmode
, 0);
1054 r16
= gen_rtx_REG (Pmode
, 16);
1055 tga
= get_tls_get_addr ();
1056 dest
= gen_reg_rtx (Pmode
);
1057 seq
= GEN_INT (alpha_next_sequence_number
++);
1059 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1060 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1061 insn
= emit_call_insn (insn
);
1062 CONST_OR_PURE_CALL_P (insn
) = 1;
1063 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1065 insn
= get_insns ();
1068 emit_libcall_block (insn
, dest
, r0
, x
);
1071 case TLS_MODEL_LOCAL_DYNAMIC
:
1074 r0
= gen_rtx_REG (Pmode
, 0);
1075 r16
= gen_rtx_REG (Pmode
, 16);
1076 tga
= get_tls_get_addr ();
1077 scratch
= gen_reg_rtx (Pmode
);
1078 seq
= GEN_INT (alpha_next_sequence_number
++);
1080 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1081 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1082 insn
= emit_call_insn (insn
);
1083 CONST_OR_PURE_CALL_P (insn
) = 1;
1084 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1086 insn
= get_insns ();
1089 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1090 UNSPEC_TLSLDM_CALL
);
1091 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1093 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1094 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1096 if (alpha_tls_size
== 64)
1098 dest
= gen_reg_rtx (Pmode
);
1099 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1100 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1103 if (alpha_tls_size
== 32)
1105 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1106 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1107 scratch
= gen_reg_rtx (Pmode
);
1108 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1110 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1112 case TLS_MODEL_INITIAL_EXEC
:
1113 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1114 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1115 tp
= gen_reg_rtx (Pmode
);
1116 scratch
= gen_reg_rtx (Pmode
);
1117 dest
= gen_reg_rtx (Pmode
);
1119 emit_insn (gen_load_tp (tp
));
1120 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1121 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1124 case TLS_MODEL_LOCAL_EXEC
:
1125 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1126 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1127 tp
= gen_reg_rtx (Pmode
);
1129 emit_insn (gen_load_tp (tp
));
1130 if (alpha_tls_size
== 32)
1132 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1133 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1134 tp
= gen_reg_rtx (Pmode
);
1135 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1137 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1140 if (local_symbolic_operand (x
, Pmode
))
1142 if (small_symbolic_operand (x
, Pmode
))
1146 if (!no_new_pseudos
)
1147 scratch
= gen_reg_rtx (Pmode
);
1148 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1149 gen_rtx_HIGH (Pmode
, x
)));
1150 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1159 HOST_WIDE_INT low
, high
;
1161 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1163 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1167 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1168 (no_new_pseudos
? scratch
: NULL_RTX
),
1169 1, OPTAB_LIB_WIDEN
);
1171 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1172 (no_new_pseudos
? scratch
: NULL_RTX
),
1173 1, OPTAB_LIB_WIDEN
);
1175 return plus_constant (x
, low
);
1179 /* Primarily this is required for TLS symbols, but given that our move
1180 patterns *ought* to be able to handle any symbol at any time, we
1181 should never be spilling symbolic operands to the constant pool, ever. */
1184 alpha_cannot_force_const_mem (rtx x
)
1186 enum rtx_code code
= GET_CODE (x
);
1187 return code
== SYMBOL_REF
|| code
== LABEL_REF
|| code
== CONST
;
1190 /* We do not allow indirect calls to be optimized into sibling calls, nor
1191 can we allow a call to a function with a different GP to be optimized
1195 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1197 /* Can't do indirect tail calls, since we don't know if the target
1198 uses the same GP. */
1202 /* Otherwise, we can make a tail call if the target function shares
1204 return decl_has_samegp (decl
);
1208 some_small_symbolic_operand_int (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1212 /* Don't re-split. */
1213 if (GET_CODE (x
) == LO_SUM
)
1216 return small_symbolic_operand (x
, Pmode
) != 0;
1220 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1224 /* Don't re-split. */
1225 if (GET_CODE (x
) == LO_SUM
)
1228 if (small_symbolic_operand (x
, Pmode
))
1230 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1239 split_small_symbolic_operand (rtx x
)
1242 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1246 /* Indicate that INSN cannot be duplicated. This is true for any insn
1247 that we've marked with gpdisp relocs, since those have to stay in
1248 1-1 correspondence with one another.
1250 Technically we could copy them if we could set up a mapping from one
1251 sequence number to another, across the set of insns to be duplicated.
1252 This seems overly complicated and error-prone since interblock motion
1253 from sched-ebb could move one of the pair of insns to a different block.
1255 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1256 then they'll be in a different block from their ldgp. Which could lead
1257 the bb reorder code to think that it would be ok to copy just the block
1258 containing the call and branch to the block containing the ldgp. */
1261 alpha_cannot_copy_insn_p (rtx insn
)
1263 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
1265 if (recog_memoized (insn
) >= 0)
1266 return get_attr_cannot_copy (insn
);
1272 /* Try a machine-dependent way of reloading an illegitimate address
1273 operand. If we find one, push the reload and return the new rtx. */
1276 alpha_legitimize_reload_address (rtx x
,
1277 enum machine_mode mode ATTRIBUTE_UNUSED
,
1278 int opnum
, int type
,
1279 int ind_levels ATTRIBUTE_UNUSED
)
1281 /* We must recognize output that we have already generated ourselves. */
1282 if (GET_CODE (x
) == PLUS
1283 && GET_CODE (XEXP (x
, 0)) == PLUS
1284 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1285 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1286 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1288 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1289 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1294 /* We wish to handle large displacements off a base register by
1295 splitting the addend across an ldah and the mem insn. This
1296 cuts number of extra insns needed from 3 to 1. */
1297 if (GET_CODE (x
) == PLUS
1298 && GET_CODE (XEXP (x
, 0)) == REG
1299 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1300 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1301 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1303 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1304 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1306 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1308 /* Check for 32-bit overflow. */
1309 if (high
+ low
!= val
)
1312 /* Reload the high part into a base reg; leave the low part
1313 in the mem directly. */
1314 x
= gen_rtx_PLUS (GET_MODE (x
),
1315 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1319 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1320 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1328 /* Compute a (partial) cost for rtx X. Return true if the complete
1329 cost has been computed, and false if subexpressions should be
1330 scanned. In either case, *TOTAL contains the cost result. */
1333 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1335 enum machine_mode mode
= GET_MODE (x
);
1336 bool float_mode_p
= FLOAT_MODE_P (mode
);
1337 const struct alpha_rtx_cost_data
*cost_data
;
1340 cost_data
= &alpha_rtx_cost_size
;
1342 cost_data
= &alpha_rtx_cost_data
[alpha_cpu
];
1347 /* If this is an 8-bit constant, return zero since it can be used
1348 nearly anywhere with no cost. If it is a valid operand for an
1349 ADD or AND, likewise return 0 if we know it will be used in that
1350 context. Otherwise, return 2 since it might be used there later.
1351 All other constants take at least two insns. */
1352 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
1360 if (x
== CONST0_RTX (mode
))
1362 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
1363 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
1365 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
1368 *total
= COSTS_N_INSNS (2);
1374 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
1375 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
1376 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
1377 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
1378 else if (tls_symbolic_operand_type (x
))
1379 /* Estimate of cost for call_pal rduniq. */
1380 /* ??? How many insns do we emit here? More than one... */
1381 *total
= COSTS_N_INSNS (15);
1383 /* Otherwise we do a load from the GOT. */
1384 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1390 *total
= cost_data
->fp_add
;
1391 else if (GET_CODE (XEXP (x
, 0)) == MULT
1392 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
1394 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
1395 + rtx_cost (XEXP (x
, 1), outer_code
) + COSTS_N_INSNS (1));
1402 *total
= cost_data
->fp_mult
;
1403 else if (mode
== DImode
)
1404 *total
= cost_data
->int_mult_di
;
1406 *total
= cost_data
->int_mult_si
;
1410 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1411 && INTVAL (XEXP (x
, 1)) <= 3)
1413 *total
= COSTS_N_INSNS (1);
1420 *total
= cost_data
->int_shift
;
1425 *total
= cost_data
->fp_add
;
1427 *total
= cost_data
->int_cmov
;
1435 *total
= cost_data
->int_div
;
1436 else if (mode
== SFmode
)
1437 *total
= cost_data
->fp_div_sf
;
1439 *total
= cost_data
->fp_div_df
;
1443 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1449 *total
= COSTS_N_INSNS (1);
1457 *total
= COSTS_N_INSNS (1) + cost_data
->int_cmov
;
1463 case UNSIGNED_FLOAT
:
1467 case FLOAT_TRUNCATE
:
1468 *total
= cost_data
->fp_add
;
1476 /* REF is an alignable memory location. Place an aligned SImode
1477 reference into *PALIGNED_MEM and the number of bits to shift into
1478 *PBITNUM. SCRATCH is a free register for use in reloading out
1479 of range stack slots. */
1482 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
1485 HOST_WIDE_INT offset
= 0;
1487 if (GET_CODE (ref
) != MEM
)
1490 if (reload_in_progress
1491 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1493 base
= find_replacement (&XEXP (ref
, 0));
1495 if (! memory_address_p (GET_MODE (ref
), base
))
1500 base
= XEXP (ref
, 0);
1503 if (GET_CODE (base
) == PLUS
)
1504 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1507 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
1509 if (WORDS_BIG_ENDIAN
)
1510 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
1511 + (offset
& 3) * 8));
1513 *pbitnum
= GEN_INT ((offset
& 3) * 8);
1516 /* Similar, but just get the address. Handle the two reload cases.
1517 Add EXTRA_OFFSET to the address we return. */
1520 get_unaligned_address (rtx ref
, int extra_offset
)
1523 HOST_WIDE_INT offset
= 0;
1525 if (GET_CODE (ref
) != MEM
)
1528 if (reload_in_progress
1529 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1531 base
= find_replacement (&XEXP (ref
, 0));
1533 if (! memory_address_p (GET_MODE (ref
), base
))
1538 base
= XEXP (ref
, 0);
1541 if (GET_CODE (base
) == PLUS
)
1542 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1544 return plus_constant (base
, offset
+ extra_offset
);
1547 /* On the Alpha, all (non-symbolic) constants except zero go into
1548 a floating-point register via memory. Note that we cannot
1549 return anything that is not a subset of CLASS, and that some
1550 symbolic constants cannot be dropped to memory. */
1553 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
1555 /* Zero is present in any register class. */
1556 if (x
== CONST0_RTX (GET_MODE (x
)))
1559 /* These sorts of constants we can easily drop to memory. */
1560 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
1562 if (class == FLOAT_REGS
)
1564 if (class == ALL_REGS
)
1565 return GENERAL_REGS
;
1569 /* All other kinds of constants should not (and in the case of HIGH
1570 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1571 secondary reload. */
1573 return (class == ALL_REGS
? GENERAL_REGS
: class);
1578 /* Loading and storing HImode or QImode values to and from memory
1579 usually requires a scratch register. The exceptions are loading
1580 QImode and HImode from an aligned address to a general register
1581 unless byte instructions are permitted.
1583 We also cannot load an unaligned address or a paradoxical SUBREG
1584 into an FP register.
1586 We also cannot do integral arithmetic into FP regs, as might result
1587 from register elimination into a DImode fp register. */
1590 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
1593 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
1595 if (GET_CODE (x
) == MEM
1596 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
1597 || (GET_CODE (x
) == SUBREG
1598 && (GET_CODE (SUBREG_REG (x
)) == MEM
1599 || (GET_CODE (SUBREG_REG (x
)) == REG
1600 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
1602 if (!in
|| !aligned_memory_operand(x
, mode
))
1603 return GENERAL_REGS
;
1607 if (class == FLOAT_REGS
)
1609 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
1610 return GENERAL_REGS
;
1612 if (GET_CODE (x
) == SUBREG
1613 && (GET_MODE_SIZE (GET_MODE (x
))
1614 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1615 return GENERAL_REGS
;
1617 if (in
&& INTEGRAL_MODE_P (mode
)
1618 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
1619 return GENERAL_REGS
;
1625 /* Subfunction of the following function. Update the flags of any MEM
1626 found in part of X. */
1629 alpha_set_memflags_1 (rtx
*xp
, void *data
)
1631 rtx x
= *xp
, orig
= (rtx
) data
;
1633 if (GET_CODE (x
) != MEM
)
1636 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (orig
);
1637 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (orig
);
1638 MEM_SCALAR_P (x
) = MEM_SCALAR_P (orig
);
1639 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (orig
);
1640 MEM_READONLY_P (x
) = MEM_READONLY_P (orig
);
1642 /* Sadly, we cannot use alias sets because the extra aliasing
1643 produced by the AND interferes. Given that two-byte quantities
1644 are the only thing we would be able to differentiate anyway,
1645 there does not seem to be any point in convoluting the early
1646 out of the alias check. */
1651 /* Given INSN, which is an INSN list or the PATTERN of a single insn
1652 generated to perform a memory operation, look for any MEMs in either
1653 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1654 volatile flags from REF into each of the MEMs found. If REF is not
1655 a MEM, don't do anything. */
1658 alpha_set_memflags (rtx insn
, rtx ref
)
1662 if (GET_CODE (ref
) != MEM
)
1665 /* This is only called from alpha.md, after having had something
1666 generated from one of the insn patterns. So if everything is
1667 zero, the pattern is already up-to-date. */
1668 if (!MEM_VOLATILE_P (ref
)
1669 && !MEM_IN_STRUCT_P (ref
)
1670 && !MEM_SCALAR_P (ref
)
1671 && !MEM_NOTRAP_P (ref
)
1672 && !MEM_READONLY_P (ref
))
1676 base_ptr
= &PATTERN (insn
);
1679 for_each_rtx (base_ptr
, alpha_set_memflags_1
, (void *) ref
);
1682 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
1685 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
1686 HOST_WIDE_INT c
, int n
)
1690 /* Use a pseudo if highly optimizing and still generating RTL. */
1692 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
1695 /* If this is a sign-extended 32-bit constant, we can do this in at most
1696 three insns, so do it if we have enough insns left. We always have
1697 a sign-extended 32-bit constant when compiling on a narrow machine. */
1699 if (HOST_BITS_PER_WIDE_INT
!= 64
1700 || c
>> 31 == -1 || c
>> 31 == 0)
1702 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1703 HOST_WIDE_INT tmp1
= c
- low
;
1704 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
1705 HOST_WIDE_INT extra
= 0;
1707 /* If HIGH will be interpreted as negative but the constant is
1708 positive, we must adjust it to do two ldha insns. */
1710 if ((high
& 0x8000) != 0 && c
>= 0)
1714 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1717 if (c
== low
|| (low
== 0 && extra
== 0))
1719 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1720 but that meant that we can't handle INT_MIN on 32-bit machines
1721 (like NT/Alpha), because we recurse indefinitely through
1722 emit_move_insn to gen_movdi. So instead, since we know exactly
1723 what we want, create it explicitly. */
1726 target
= gen_reg_rtx (mode
);
1727 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
1730 else if (n
>= 2 + (extra
!= 0))
1734 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
1738 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
1741 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1742 This means that if we go through expand_binop, we'll try to
1743 generate extensions, etc, which will require new pseudos, which
1744 will fail during some split phases. The SImode add patterns
1745 still exist, but are not named. So build the insns by hand. */
1750 subtarget
= gen_reg_rtx (mode
);
1751 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
1752 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
1758 target
= gen_reg_rtx (mode
);
1759 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
1760 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
1766 /* If we couldn't do it that way, try some other methods. But if we have
1767 no instructions left, don't bother. Likewise, if this is SImode and
1768 we can't make pseudos, we can't do anything since the expand_binop
1769 and expand_unop calls will widen and try to make pseudos. */
1771 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
1774 /* Next, see if we can load a related constant and then shift and possibly
1775 negate it to get the constant we want. Try this once each increasing
1776 numbers of insns. */
1778 for (i
= 1; i
< n
; i
++)
1780 /* First, see if minus some low bits, we've an easy load of
1783 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
1785 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
1786 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
1787 target
, 0, OPTAB_WIDEN
);
1789 /* Next try complementing. */
1790 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
1791 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
1793 /* Next try to form a constant and do a left shift. We can do this
1794 if some low-order bits are zero; the exact_log2 call below tells
1795 us that information. The bits we are shifting out could be any
1796 value, but here we'll just try the 0- and sign-extended forms of
1797 the constant. To try to increase the chance of having the same
1798 constant in more than one insn, start at the highest number of
1799 bits to shift, but try all possibilities in case a ZAPNOT will
1802 if ((bits
= exact_log2 (c
& - c
)) > 0)
1803 for (; bits
> 0; bits
--)
1804 if ((temp
= (alpha_emit_set_const
1805 (subtarget
, mode
, c
>> bits
, i
))) != 0
1806 || ((temp
= (alpha_emit_set_const
1808 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
1810 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
1811 target
, 0, OPTAB_WIDEN
);
1813 /* Now try high-order zero bits. Here we try the shifted-in bits as
1814 all zero and all ones. Be careful to avoid shifting outside the
1815 mode and to avoid shifting outside the host wide int size. */
1816 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1817 confuse the recursive call and set all of the high 32 bits. */
1819 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1820 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
1821 for (; bits
> 0; bits
--)
1822 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
1824 || ((temp
= (alpha_emit_set_const
1826 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
1829 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
1830 target
, 1, OPTAB_WIDEN
);
1832 /* Now try high-order 1 bits. We get that with a sign-extension.
1833 But one bit isn't enough here. Be careful to avoid shifting outside
1834 the mode and to avoid shifting outside the host wide int size. */
1836 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1837 - floor_log2 (~ c
) - 2)) > 0)
1838 for (; bits
> 0; bits
--)
1839 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
1841 || ((temp
= (alpha_emit_set_const
1843 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
1846 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
1847 target
, 0, OPTAB_WIDEN
);
1850 #if HOST_BITS_PER_WIDE_INT == 64
1851 /* Finally, see if can load a value into the target that is the same as the
1852 constant except that all bytes that are 0 are changed to be 0xff. If we
1853 can, then we can do a ZAPNOT to obtain the desired constant. */
1856 for (i
= 0; i
< 64; i
+= 8)
1857 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
1858 new |= (HOST_WIDE_INT
) 0xff << i
;
1860 /* We are only called for SImode and DImode. If this is SImode, ensure that
1861 we are sign extended to a full word. */
1864 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
1866 if (new != c
&& new != -1
1867 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
1868 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
1869 target
, 0, OPTAB_WIDEN
);
1875 /* Try to output insns to set TARGET equal to the constant C if it can be
1876 done in less than N insns. Do all computations in MODE. Returns the place
1877 where the output has been placed if it can be done and the insns have been
1878 emitted. If it would take more than N insns, zero is returned and no
1879 insns and emitted. */
1882 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
1883 HOST_WIDE_INT c
, int n
)
1886 rtx orig_target
= target
;
1889 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1890 can't load this constant in one insn, do this in DImode. */
1891 if (no_new_pseudos
&& mode
== SImode
1892 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
1893 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
1895 target
= gen_lowpart (DImode
, target
);
1899 /* Try 1 insn, then 2, then up to N. */
1900 for (i
= 1; i
<= n
; i
++)
1902 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
1905 rtx insn
= get_last_insn ();
1906 rtx set
= single_set (insn
);
1907 if (! CONSTANT_P (SET_SRC (set
)))
1908 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
1913 /* Allow for the case where we changed the mode of TARGET. */
1914 if (result
== target
)
1915 result
= orig_target
;
1920 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1921 fall back to a straight forward decomposition. We do this to avoid
1922 exponential run times encountered when looking for longer sequences
1923 with alpha_emit_set_const. */
1926 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
1928 HOST_WIDE_INT d1
, d2
, d3
, d4
;
1930 /* Decompose the entire word */
1931 #if HOST_BITS_PER_WIDE_INT >= 64
1932 if (c2
!= -(c1
< 0))
1934 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1936 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1937 c1
= (c1
- d2
) >> 32;
1938 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1940 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1944 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
1946 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1950 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
1952 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1957 /* Construct the high word */
1960 emit_move_insn (target
, GEN_INT (d4
));
1962 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
1965 emit_move_insn (target
, GEN_INT (d3
));
1967 /* Shift it into place */
1968 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
1970 /* Add in the low bits. */
1972 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
1974 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
1979 /* Expand a move instruction; return true if all work is done.
1980 We don't handle non-bwx subword loads here. */
1983 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
1985 /* If the output is not a register, the input must be. */
1986 if (GET_CODE (operands
[0]) == MEM
1987 && ! reg_or_0_operand (operands
[1], mode
))
1988 operands
[1] = force_reg (mode
, operands
[1]);
1990 /* Allow legitimize_address to perform some simplifications. */
1991 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
1995 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
1998 if (tmp
== operands
[0])
2005 /* Early out for non-constants and valid constants. */
2006 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2009 /* Split large integers. */
2010 if (GET_CODE (operands
[1]) == CONST_INT
2011 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2013 HOST_WIDE_INT i0
, i1
;
2014 rtx temp
= NULL_RTX
;
2016 if (GET_CODE (operands
[1]) == CONST_INT
)
2018 i0
= INTVAL (operands
[1]);
2021 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2023 i0
= CONST_DOUBLE_LOW (operands
[1]);
2028 i0
= CONST_DOUBLE_LOW (operands
[1]);
2029 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2032 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2033 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2035 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2036 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2040 if (rtx_equal_p (operands
[0], temp
))
2047 /* Otherwise we've nothing left but to drop the thing to memory. */
2048 operands
[1] = force_const_mem (mode
, operands
[1]);
2049 if (reload_in_progress
)
2051 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2052 operands
[1] = copy_rtx (operands
[1]);
2053 XEXP (operands
[1], 0) = operands
[0];
2056 operands
[1] = validize_mem (operands
[1]);
2060 /* Expand a non-bwx QImode or HImode move instruction;
2061 return true if all work is done. */
2064 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2066 /* If the output is not a register, the input must be. */
2067 if (GET_CODE (operands
[0]) == MEM
)
2068 operands
[1] = force_reg (mode
, operands
[1]);
2070 /* Handle four memory cases, unaligned and aligned for either the input
2071 or the output. The only case where we can be called during reload is
2072 for aligned loads; all other cases require temporaries. */
2074 if (GET_CODE (operands
[1]) == MEM
2075 || (GET_CODE (operands
[1]) == SUBREG
2076 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2077 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2078 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2079 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2080 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2081 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2083 if (aligned_memory_operand (operands
[1], mode
))
2085 if (reload_in_progress
)
2087 emit_insn ((mode
== QImode
2088 ? gen_reload_inqi_help
2089 : gen_reload_inhi_help
)
2090 (operands
[0], operands
[1],
2091 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2095 rtx aligned_mem
, bitnum
;
2096 rtx scratch
= gen_reg_rtx (SImode
);
2100 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2102 subtarget
= operands
[0];
2103 if (GET_CODE (subtarget
) == REG
)
2104 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2106 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2108 emit_insn ((mode
== QImode
2109 ? gen_aligned_loadqi
2110 : gen_aligned_loadhi
)
2111 (subtarget
, aligned_mem
, bitnum
, scratch
));
2114 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2119 /* Don't pass these as parameters since that makes the generated
2120 code depend on parameter evaluation order which will cause
2121 bootstrap failures. */
2123 rtx temp1
, temp2
, seq
, subtarget
;
2126 temp1
= gen_reg_rtx (DImode
);
2127 temp2
= gen_reg_rtx (DImode
);
2129 subtarget
= operands
[0];
2130 if (GET_CODE (subtarget
) == REG
)
2131 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2133 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2135 seq
= ((mode
== QImode
2136 ? gen_unaligned_loadqi
2137 : gen_unaligned_loadhi
)
2138 (subtarget
, get_unaligned_address (operands
[1], 0),
2140 alpha_set_memflags (seq
, operands
[1]);
2144 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2149 if (GET_CODE (operands
[0]) == MEM
2150 || (GET_CODE (operands
[0]) == SUBREG
2151 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2152 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2153 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2154 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2155 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2156 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2158 if (aligned_memory_operand (operands
[0], mode
))
2160 rtx aligned_mem
, bitnum
;
2161 rtx temp1
= gen_reg_rtx (SImode
);
2162 rtx temp2
= gen_reg_rtx (SImode
);
2164 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2166 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2171 rtx temp1
= gen_reg_rtx (DImode
);
2172 rtx temp2
= gen_reg_rtx (DImode
);
2173 rtx temp3
= gen_reg_rtx (DImode
);
2174 rtx seq
= ((mode
== QImode
2175 ? gen_unaligned_storeqi
2176 : gen_unaligned_storehi
)
2177 (get_unaligned_address (operands
[0], 0),
2178 operands
[1], temp1
, temp2
, temp3
));
2180 alpha_set_memflags (seq
, operands
[0]);
2189 /* Implement the movmisalign patterns. One of the operands is a memory
2190 that is not naturally aligned. Emit instructions to load it. */
2193 alpha_expand_movmisalign (enum machine_mode mode
, rtx
*operands
)
2195 /* Honor misaligned loads, for those we promised to do so. */
2196 if (MEM_P (operands
[1]))
2200 if (register_operand (operands
[0], mode
))
2203 tmp
= gen_reg_rtx (mode
);
2205 alpha_expand_unaligned_load (tmp
, operands
[1], 8, 0, 0);
2206 if (tmp
!= operands
[0])
2207 emit_move_insn (operands
[0], tmp
);
2209 else if (MEM_P (operands
[0]))
2211 if (!reg_or_0_operand (operands
[1], mode
))
2212 operands
[1] = force_reg (mode
, operands
[1]);
2213 alpha_expand_unaligned_store (operands
[0], operands
[1], 8, 0);
2219 /* Generate an unsigned DImode to FP conversion. This is the same code
2220 optabs would emit if we didn't have TFmode patterns.
2222 For SFmode, this is the only construction I've found that can pass
2223 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2224 intermediates will work, because you'll get intermediate rounding
2225 that ruins the end result. Some of this could be fixed by turning
2226 on round-to-positive-infinity, but that requires diddling the fpsr,
2227 which kills performance. I tried turning this around and converting
2228 to a negative number, so that I could turn on /m, but either I did
2229 it wrong or there's something else cause I wound up with the exact
2230 same single-bit error. There is a branch-less form of this same code:
2241 fcmoveq $f10,$f11,$f0
2243 I'm not using it because it's the same number of instructions as
2244 this branch-full form, and it has more serialized long latency
2245 instructions on the critical path.
2247 For DFmode, we can avoid rounding errors by breaking up the word
2248 into two pieces, converting them separately, and adding them back:
2250 LC0: .long 0,0x5f800000
2255 cpyse $f11,$f31,$f10
2256 cpyse $f31,$f11,$f11
2264 This doesn't seem to be a clear-cut win over the optabs form.
2265 It probably all depends on the distribution of numbers being
2266 converted -- in the optabs form, all but high-bit-set has a
2267 much lower minimum execution time. */
2270 alpha_emit_floatuns (rtx operands
[2])
2272 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2273 enum machine_mode mode
;
2276 in
= force_reg (DImode
, operands
[1]);
2277 mode
= GET_MODE (out
);
2278 neglab
= gen_label_rtx ();
2279 donelab
= gen_label_rtx ();
2280 i0
= gen_reg_rtx (DImode
);
2281 i1
= gen_reg_rtx (DImode
);
2282 f0
= gen_reg_rtx (mode
);
2284 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2286 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2287 emit_jump_insn (gen_jump (donelab
));
2290 emit_label (neglab
);
2292 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2293 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2294 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2295 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2296 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2298 emit_label (donelab
);
2301 /* Generate the comparison for a conditional branch. */
2304 alpha_emit_conditional_branch (enum rtx_code code
)
2306 enum rtx_code cmp_code
, branch_code
;
2307 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
2308 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2311 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
2313 if (! TARGET_HAS_XFLOATING_LIBS
)
2316 /* X_floating library comparison functions return
2320 Convert the compare against the raw return value. */
2342 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2344 alpha_compare
.fp_p
= 0;
2347 /* The general case: fold the comparison code to the types of compares
2348 that we have, choosing the branch as necessary. */
2351 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2353 /* We have these compares: */
2354 cmp_code
= code
, branch_code
= NE
;
2359 /* These must be reversed. */
2360 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2363 case GE
: case GT
: case GEU
: case GTU
:
2364 /* For FP, we swap them, for INT, we reverse them. */
2365 if (alpha_compare
.fp_p
)
2367 cmp_code
= swap_condition (code
);
2369 tem
= op0
, op0
= op1
, op1
= tem
;
2373 cmp_code
= reverse_condition (code
);
2382 if (alpha_compare
.fp_p
)
2385 if (flag_unsafe_math_optimizations
)
2387 /* When we are not as concerned about non-finite values, and we
2388 are comparing against zero, we can branch directly. */
2389 if (op1
== CONST0_RTX (DFmode
))
2390 cmp_code
= UNKNOWN
, branch_code
= code
;
2391 else if (op0
== CONST0_RTX (DFmode
))
2393 /* Undo the swap we probably did just above. */
2394 tem
= op0
, op0
= op1
, op1
= tem
;
2395 branch_code
= swap_condition (cmp_code
);
2401 /* ??? We mark the branch mode to be CCmode to prevent the
2402 compare and branch from being combined, since the compare
2403 insn follows IEEE rules that the branch does not. */
2404 branch_mode
= CCmode
;
2411 /* The following optimizations are only for signed compares. */
2412 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2414 /* Whee. Compare and branch against 0 directly. */
2415 if (op1
== const0_rtx
)
2416 cmp_code
= UNKNOWN
, branch_code
= code
;
2418 /* If the constants doesn't fit into an immediate, but can
2419 be generated by lda/ldah, we adjust the argument and
2420 compare against zero, so we can use beq/bne directly. */
2421 /* ??? Don't do this when comparing against symbols, otherwise
2422 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2423 be declared false out of hand (at least for non-weak). */
2424 else if (GET_CODE (op1
) == CONST_INT
2425 && (code
== EQ
|| code
== NE
)
2426 && !(symbolic_operand (op0
, VOIDmode
)
2427 || (GET_CODE (op0
) == REG
&& REG_POINTER (op0
))))
2429 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
2431 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
2432 && (CONST_OK_FOR_LETTER_P (n
, 'K')
2433 || CONST_OK_FOR_LETTER_P (n
, 'L')))
2435 cmp_code
= PLUS
, branch_code
= code
;
2441 if (!reg_or_0_operand (op0
, DImode
))
2442 op0
= force_reg (DImode
, op0
);
2443 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2444 op1
= force_reg (DImode
, op1
);
2447 /* Emit an initial compare instruction, if necessary. */
2449 if (cmp_code
!= UNKNOWN
)
2451 tem
= gen_reg_rtx (cmp_mode
);
2452 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2455 /* Zero the operands. */
2456 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2458 /* Return the branch comparison. */
2459 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
2462 /* Certain simplifications can be done to make invalid setcc operations
2463 valid. Return the final comparison, or NULL if we can't work. */
2466 alpha_emit_setcc (enum rtx_code code
)
2468 enum rtx_code cmp_code
;
2469 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2470 int fp_p
= alpha_compare
.fp_p
;
2473 /* Zero the operands. */
2474 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2476 if (fp_p
&& GET_MODE (op0
) == TFmode
)
2478 if (! TARGET_HAS_XFLOATING_LIBS
)
2481 /* X_floating library comparison functions return
2485 Convert the compare against the raw return value. */
2487 if (code
== UNORDERED
|| code
== ORDERED
)
2492 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2496 if (code
== UNORDERED
)
2498 else if (code
== ORDERED
)
2504 if (fp_p
&& !TARGET_FIX
)
2507 /* The general case: fold the comparison code to the types of compares
2508 that we have, choosing the branch as necessary. */
2513 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2515 /* We have these compares. */
2517 cmp_code
= code
, code
= NE
;
2521 if (!fp_p
&& op1
== const0_rtx
)
2526 cmp_code
= reverse_condition (code
);
2530 case GE
: case GT
: case GEU
: case GTU
:
2531 /* These normally need swapping, but for integer zero we have
2532 special patterns that recognize swapped operands. */
2533 if (!fp_p
&& op1
== const0_rtx
)
2535 code
= swap_condition (code
);
2537 cmp_code
= code
, code
= NE
;
2538 tmp
= op0
, op0
= op1
, op1
= tmp
;
2547 if (!register_operand (op0
, DImode
))
2548 op0
= force_reg (DImode
, op0
);
2549 if (!reg_or_8bit_operand (op1
, DImode
))
2550 op1
= force_reg (DImode
, op1
);
2553 /* Emit an initial compare instruction, if necessary. */
2554 if (cmp_code
!= UNKNOWN
)
2556 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
2558 tmp
= gen_reg_rtx (mode
);
2559 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
2560 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
2562 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
2566 /* Return the setcc comparison. */
2567 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
2571 /* Rewrite a comparison against zero CMP of the form
2572 (CODE (cc0) (const_int 0)) so it can be written validly in
2573 a conditional move (if_then_else CMP ...).
2574 If both of the operands that set cc0 are nonzero we must emit
2575 an insn to perform the compare (it can't be done within
2576 the conditional move). */
2579 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
2581 enum rtx_code code
= GET_CODE (cmp
);
2582 enum rtx_code cmov_code
= NE
;
2583 rtx op0
= alpha_compare
.op0
;
2584 rtx op1
= alpha_compare
.op1
;
2585 int fp_p
= alpha_compare
.fp_p
;
2586 enum machine_mode cmp_mode
2587 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
2588 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
2589 enum machine_mode cmov_mode
= VOIDmode
;
2590 int local_fast_math
= flag_unsafe_math_optimizations
;
2593 /* Zero the operands. */
2594 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2596 if (fp_p
!= FLOAT_MODE_P (mode
))
2598 enum rtx_code cmp_code
;
2603 /* If we have fp<->int register move instructions, do a cmov by
2604 performing the comparison in fp registers, and move the
2605 zero/nonzero value to integer registers, where we can then
2606 use a normal cmov, or vice-versa. */
2610 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2611 /* We have these compares. */
2612 cmp_code
= code
, code
= NE
;
2616 /* This must be reversed. */
2617 cmp_code
= EQ
, code
= EQ
;
2620 case GE
: case GT
: case GEU
: case GTU
:
2621 /* These normally need swapping, but for integer zero we have
2622 special patterns that recognize swapped operands. */
2623 if (!fp_p
&& op1
== const0_rtx
)
2624 cmp_code
= code
, code
= NE
;
2627 cmp_code
= swap_condition (code
);
2629 tem
= op0
, op0
= op1
, op1
= tem
;
2637 tem
= gen_reg_rtx (cmp_op_mode
);
2638 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2639 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
2642 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
2643 op0
= gen_lowpart (cmp_op_mode
, tem
);
2644 op1
= CONST0_RTX (cmp_op_mode
);
2646 local_fast_math
= 1;
2649 /* We may be able to use a conditional move directly.
2650 This avoids emitting spurious compares. */
2651 if (signed_comparison_operator (cmp
, VOIDmode
)
2652 && (!fp_p
|| local_fast_math
)
2653 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
2654 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2656 /* We can't put the comparison inside the conditional move;
2657 emit a compare instruction and put that inside the
2658 conditional move. Make sure we emit only comparisons we have;
2659 swap or reverse as necessary. */
2666 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2667 /* We have these compares: */
2671 /* This must be reversed. */
2672 code
= reverse_condition (code
);
2676 case GE
: case GT
: case GEU
: case GTU
:
2677 /* These must be swapped. */
2678 if (op1
!= CONST0_RTX (cmp_mode
))
2680 code
= swap_condition (code
);
2681 tem
= op0
, op0
= op1
, op1
= tem
;
2691 if (!reg_or_0_operand (op0
, DImode
))
2692 op0
= force_reg (DImode
, op0
);
2693 if (!reg_or_8bit_operand (op1
, DImode
))
2694 op1
= force_reg (DImode
, op1
);
2697 /* ??? We mark the branch mode to be CCmode to prevent the compare
2698 and cmov from being combined, since the compare insn follows IEEE
2699 rules that the cmov does not. */
2700 if (fp_p
&& !local_fast_math
)
2703 tem
= gen_reg_rtx (cmp_op_mode
);
2704 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
2705 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
2708 /* Simplify a conditional move of two constants into a setcc with
2709 arithmetic. This is done with a splitter since combine would
2710 just undo the work if done during code generation. It also catches
2711 cases we wouldn't have before cse. */
2714 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
2715 rtx t_rtx
, rtx f_rtx
)
2717 HOST_WIDE_INT t
, f
, diff
;
2718 enum machine_mode mode
;
2719 rtx target
, subtarget
, tmp
;
2721 mode
= GET_MODE (dest
);
2726 if (((code
== NE
|| code
== EQ
) && diff
< 0)
2727 || (code
== GE
|| code
== GT
))
2729 code
= reverse_condition (code
);
2730 diff
= t
, t
= f
, f
= diff
;
2734 subtarget
= target
= dest
;
2737 target
= gen_lowpart (DImode
, dest
);
2738 if (! no_new_pseudos
)
2739 subtarget
= gen_reg_rtx (DImode
);
2743 /* Below, we must be careful to use copy_rtx on target and subtarget
2744 in intermediate insns, as they may be a subreg rtx, which may not
2747 if (f
== 0 && exact_log2 (diff
) > 0
2748 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2749 viable over a longer latency cmove. On EV5, the E0 slot is a
2750 scarce resource, and on EV4 shift has the same latency as a cmove. */
2751 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
2753 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2754 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2756 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
2757 GEN_INT (exact_log2 (t
)));
2758 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2760 else if (f
== 0 && t
== -1)
2762 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2763 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2765 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
2767 else if (diff
== 1 || diff
== 4 || diff
== 8)
2771 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2772 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2775 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
2778 add_op
= GEN_INT (f
);
2779 if (sext_add_operand (add_op
, mode
))
2781 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
2783 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
2784 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2796 /* Look up the function X_floating library function name for the
2799 struct xfloating_op
GTY(())
2801 const enum rtx_code code
;
2802 const char *const GTY((skip
)) osf_func
;
2803 const char *const GTY((skip
)) vms_func
;
2807 static GTY(()) struct xfloating_op xfloating_ops
[] =
2809 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
2810 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
2811 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
2812 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
2813 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
2814 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
2815 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
2816 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
2817 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
2818 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
2819 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2820 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
2821 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2822 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2823 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2826 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
2828 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2829 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2833 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
2835 struct xfloating_op
*ops
= xfloating_ops
;
2836 long n
= ARRAY_SIZE (xfloating_ops
);
2839 /* How irritating. Nothing to key off for the main table. */
2840 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
2843 n
= ARRAY_SIZE (vax_cvt_ops
);
2846 for (i
= 0; i
< n
; ++i
, ++ops
)
2847 if (ops
->code
== code
)
2849 rtx func
= ops
->libcall
;
2852 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
2853 ? ops
->vms_func
: ops
->osf_func
);
2854 ops
->libcall
= func
;
2862 /* Most X_floating operations take the rounding mode as an argument.
2863 Compute that here. */
2866 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
2867 enum alpha_fp_rounding_mode round
)
2873 case ALPHA_FPRM_NORM
:
2876 case ALPHA_FPRM_MINF
:
2879 case ALPHA_FPRM_CHOP
:
2882 case ALPHA_FPRM_DYN
:
2888 /* XXX For reference, round to +inf is mode = 3. */
2891 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
2897 /* Emit an X_floating library function call.
2899 Note that these functions do not follow normal calling conventions:
2900 TFmode arguments are passed in two integer registers (as opposed to
2901 indirect); TFmode return values appear in R16+R17.
2903 FUNC is the function to call.
2904 TARGET is where the output belongs.
2905 OPERANDS are the inputs.
2906 NOPERANDS is the count of inputs.
2907 EQUIV is the expression equivalent for the function.
2911 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
2912 int noperands
, rtx equiv
)
2914 rtx usage
= NULL_RTX
, tmp
, reg
;
2919 for (i
= 0; i
< noperands
; ++i
)
2921 switch (GET_MODE (operands
[i
]))
2924 reg
= gen_rtx_REG (TFmode
, regno
);
2929 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
2934 if (GET_CODE (operands
[i
]) != CONST_INT
)
2938 reg
= gen_rtx_REG (DImode
, regno
);
2946 emit_move_insn (reg
, operands
[i
]);
2947 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
2950 switch (GET_MODE (target
))
2953 reg
= gen_rtx_REG (TFmode
, 16);
2956 reg
= gen_rtx_REG (DFmode
, 32);
2959 reg
= gen_rtx_REG (DImode
, 0);
2965 tmp
= gen_rtx_MEM (QImode
, func
);
2966 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
2967 const0_rtx
, const0_rtx
));
2968 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
2969 CONST_OR_PURE_CALL_P (tmp
) = 1;
2974 emit_libcall_block (tmp
, target
, reg
, equiv
);
2977 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
2980 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
2984 rtx out_operands
[3];
2986 func
= alpha_lookup_xfloating_lib_func (code
);
2987 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
2989 out_operands
[0] = operands
[1];
2990 out_operands
[1] = operands
[2];
2991 out_operands
[2] = GEN_INT (mode
);
2992 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
2993 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
2997 /* Emit an X_floating library function call for a comparison. */
3000 alpha_emit_xfloating_compare (enum rtx_code code
, rtx op0
, rtx op1
)
3003 rtx out
, operands
[2];
3005 func
= alpha_lookup_xfloating_lib_func (code
);
3009 out
= gen_reg_rtx (DImode
);
3011 /* ??? Strange mode for equiv because what's actually returned
3012 is -1,0,1, not a proper boolean value. */
3013 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3014 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3019 /* Emit an X_floating library function call for a conversion. */
3022 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3024 int noperands
= 1, mode
;
3025 rtx out_operands
[2];
3027 enum rtx_code code
= orig_code
;
3029 if (code
== UNSIGNED_FIX
)
3032 func
= alpha_lookup_xfloating_lib_func (code
);
3034 out_operands
[0] = operands
[1];
3039 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3040 out_operands
[1] = GEN_INT (mode
);
3043 case FLOAT_TRUNCATE
:
3044 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3045 out_operands
[1] = GEN_INT (mode
);
3052 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3053 gen_rtx_fmt_e (orig_code
,
3054 GET_MODE (operands
[0]),
3058 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3059 OP[0] into OP[0,1]. Naturally, output operand ordering is
3063 alpha_split_tfmode_pair (rtx operands
[4])
3065 if (GET_CODE (operands
[1]) == REG
)
3067 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3068 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3070 else if (GET_CODE (operands
[1]) == MEM
)
3072 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3073 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3075 else if (operands
[1] == CONST0_RTX (TFmode
))
3076 operands
[2] = operands
[3] = const0_rtx
;
3080 if (GET_CODE (operands
[0]) == REG
)
3082 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3083 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3085 else if (GET_CODE (operands
[0]) == MEM
)
3087 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3088 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3094 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3095 op2 is a register containing the sign bit, operation is the
3096 logical operation to be performed. */
3099 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3101 rtx high_bit
= operands
[2];
3105 alpha_split_tfmode_pair (operands
);
3107 /* Detect three flavors of operand overlap. */
3109 if (rtx_equal_p (operands
[0], operands
[2]))
3111 else if (rtx_equal_p (operands
[1], operands
[2]))
3113 if (rtx_equal_p (operands
[0], high_bit
))
3120 emit_move_insn (operands
[0], operands
[2]);
3122 /* ??? If the destination overlaps both source tf and high_bit, then
3123 assume source tf is dead in its entirety and use the other half
3124 for a scratch register. Otherwise "scratch" is just the proper
3125 destination register. */
3126 scratch
= operands
[move
< 2 ? 1 : 3];
3128 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3132 emit_move_insn (operands
[0], operands
[2]);
3134 emit_move_insn (operands
[1], scratch
);
3138 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3142 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3143 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3144 lda r3,X(r11) lda r3,X+2(r11)
3145 extwl r1,r3,r1 extql r1,r3,r1
3146 extwh r2,r3,r2 extqh r2,r3,r2
3147 or r1.r2.r1 or r1,r2,r1
3150 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3151 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3152 lda r3,X(r11) lda r3,X(r11)
3153 extll r1,r3,r1 extll r1,r3,r1
3154 extlh r2,r3,r2 extlh r2,r3,r2
3155 or r1.r2.r1 addl r1,r2,r1
3157 quad: ldq_u r1,X(r11)
3166 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3167 HOST_WIDE_INT ofs
, int sign
)
3169 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3170 enum machine_mode mode
;
3172 if (TARGET_BWX
&& size
== 2)
3174 meml
= adjust_address (mem
, QImode
, ofs
);
3175 memh
= adjust_address (mem
, QImode
, ofs
+1);
3176 if (BYTES_BIG_ENDIAN
)
3177 tmp
= meml
, meml
= memh
, memh
= tmp
;
3178 extl
= gen_reg_rtx (DImode
);
3179 exth
= gen_reg_rtx (DImode
);
3180 emit_insn (gen_zero_extendqidi2 (extl
, meml
));
3181 emit_insn (gen_zero_extendqidi2 (exth
, memh
));
3182 exth
= expand_simple_binop (DImode
, ASHIFT
, exth
, GEN_INT (8),
3183 NULL
, 1, OPTAB_LIB_WIDEN
);
3184 addr
= expand_simple_binop (DImode
, IOR
, extl
, exth
,
3185 NULL
, 1, OPTAB_LIB_WIDEN
);
3187 if (sign
&& GET_MODE (tgt
) != HImode
)
3189 addr
= gen_lowpart (HImode
, addr
);
3190 emit_insn (gen_extend_insn (tgt
, addr
, GET_MODE (tgt
), HImode
, 0));
3194 if (GET_MODE (tgt
) != DImode
)
3195 addr
= gen_lowpart (GET_MODE (tgt
), addr
);
3196 emit_move_insn (tgt
, addr
);
3201 meml
= gen_reg_rtx (DImode
);
3202 memh
= gen_reg_rtx (DImode
);
3203 addr
= gen_reg_rtx (DImode
);
3204 extl
= gen_reg_rtx (DImode
);
3205 exth
= gen_reg_rtx (DImode
);
3207 mema
= XEXP (mem
, 0);
3208 if (GET_CODE (mema
) == LO_SUM
)
3209 mema
= force_reg (Pmode
, mema
);
3211 /* AND addresses cannot be in any alias set, since they may implicitly
3212 alias surrounding code. Ideally we'd have some alias set that
3213 covered all types except those with alignment 8 or higher. */
3215 tmp
= change_address (mem
, DImode
,
3216 gen_rtx_AND (DImode
,
3217 plus_constant (mema
, ofs
),
3219 set_mem_alias_set (tmp
, 0);
3220 emit_move_insn (meml
, tmp
);
3222 tmp
= change_address (mem
, DImode
,
3223 gen_rtx_AND (DImode
,
3224 plus_constant (mema
, ofs
+ size
- 1),
3226 set_mem_alias_set (tmp
, 0);
3227 emit_move_insn (memh
, tmp
);
3229 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3231 emit_move_insn (addr
, plus_constant (mema
, -1));
3233 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3234 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3236 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3237 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3238 addr
, 1, OPTAB_WIDEN
);
3240 else if (sign
&& size
== 2)
3242 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3244 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3245 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3247 /* We must use tgt here for the target. Alpha-vms port fails if we use
3248 addr for the target, because addr is marked as a pointer and combine
3249 knows that pointers are always sign-extended 32 bit values. */
3250 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3251 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3252 addr
, 1, OPTAB_WIDEN
);
3256 if (WORDS_BIG_ENDIAN
)
3258 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3262 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3267 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3272 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3279 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3283 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3284 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3288 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3293 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3298 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3307 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3308 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3313 emit_move_insn (tgt
, gen_lowpart (GET_MODE (tgt
), addr
));
3316 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3319 alpha_expand_unaligned_store (rtx dst
, rtx src
,
3320 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
3322 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3324 if (TARGET_BWX
&& size
== 2)
3326 if (src
!= const0_rtx
)
3328 dstl
= gen_lowpart (QImode
, src
);
3329 dsth
= expand_simple_binop (DImode
, LSHIFTRT
, src
, GEN_INT (8),
3330 NULL
, 1, OPTAB_LIB_WIDEN
);
3331 dsth
= gen_lowpart (QImode
, dsth
);
3334 dstl
= dsth
= const0_rtx
;
3336 meml
= adjust_address (dst
, QImode
, ofs
);
3337 memh
= adjust_address (dst
, QImode
, ofs
+1);
3338 if (BYTES_BIG_ENDIAN
)
3339 addr
= meml
, meml
= memh
, memh
= addr
;
3341 emit_move_insn (meml
, dstl
);
3342 emit_move_insn (memh
, dsth
);
3346 dstl
= gen_reg_rtx (DImode
);
3347 dsth
= gen_reg_rtx (DImode
);
3348 insl
= gen_reg_rtx (DImode
);
3349 insh
= gen_reg_rtx (DImode
);
3351 dsta
= XEXP (dst
, 0);
3352 if (GET_CODE (dsta
) == LO_SUM
)
3353 dsta
= force_reg (Pmode
, dsta
);
3355 /* AND addresses cannot be in any alias set, since they may implicitly
3356 alias surrounding code. Ideally we'd have some alias set that
3357 covered all types except those with alignment 8 or higher. */
3359 meml
= change_address (dst
, DImode
,
3360 gen_rtx_AND (DImode
,
3361 plus_constant (dsta
, ofs
),
3363 set_mem_alias_set (meml
, 0);
3365 memh
= change_address (dst
, DImode
,
3366 gen_rtx_AND (DImode
,
3367 plus_constant (dsta
, ofs
+ size
- 1),
3369 set_mem_alias_set (memh
, 0);
3371 emit_move_insn (dsth
, memh
);
3372 emit_move_insn (dstl
, meml
);
3373 if (WORDS_BIG_ENDIAN
)
3375 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3377 if (src
!= const0_rtx
)
3382 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3385 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3388 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3391 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3392 GEN_INT (size
*8), addr
));
3398 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3402 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3403 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3407 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
3411 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3415 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3417 if (src
!= CONST0_RTX (GET_MODE (src
)))
3419 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3420 GEN_INT (size
*8), addr
));
3425 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3428 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3431 emit_insn (gen_insql_le (insl
, src
, addr
));
3436 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3441 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3445 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3446 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3450 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
3455 if (src
!= CONST0_RTX (GET_MODE (src
)))
3457 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3458 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3461 if (WORDS_BIG_ENDIAN
)
3463 emit_move_insn (meml
, dstl
);
3464 emit_move_insn (memh
, dsth
);
3468 /* Must store high before low for degenerate case of aligned. */
3469 emit_move_insn (memh
, dsth
);
3470 emit_move_insn (meml
, dstl
);
3474 /* The block move code tries to maximize speed by separating loads and
3475 stores at the expense of register pressure: we load all of the data
3476 before we store it back out. There are two secondary effects worth
3477 mentioning, that this speeds copying to/from aligned and unaligned
3478 buffers, and that it makes the code significantly easier to write. */
3480 #define MAX_MOVE_WORDS 8
3482 /* Load an integral number of consecutive unaligned quadwords. */
3485 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
3486 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3488 rtx
const im8
= GEN_INT (-8);
3489 rtx
const i64
= GEN_INT (64);
3490 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3491 rtx sreg
, areg
, tmp
, smema
;
3494 smema
= XEXP (smem
, 0);
3495 if (GET_CODE (smema
) == LO_SUM
)
3496 smema
= force_reg (Pmode
, smema
);
3498 /* Generate all the tmp registers we need. */
3499 for (i
= 0; i
< words
; ++i
)
3501 data_regs
[i
] = out_regs
[i
];
3502 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3504 data_regs
[words
] = gen_reg_rtx (DImode
);
3507 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3509 /* Load up all of the source data. */
3510 for (i
= 0; i
< words
; ++i
)
3512 tmp
= change_address (smem
, DImode
,
3513 gen_rtx_AND (DImode
,
3514 plus_constant (smema
, 8*i
),
3516 set_mem_alias_set (tmp
, 0);
3517 emit_move_insn (data_regs
[i
], tmp
);
3520 tmp
= change_address (smem
, DImode
,
3521 gen_rtx_AND (DImode
,
3522 plus_constant (smema
, 8*words
- 1),
3524 set_mem_alias_set (tmp
, 0);
3525 emit_move_insn (data_regs
[words
], tmp
);
3527 /* Extract the half-word fragments. Unfortunately DEC decided to make
3528 extxh with offset zero a noop instead of zeroing the register, so
3529 we must take care of that edge condition ourselves with cmov. */
3531 sreg
= copy_addr_to_reg (smema
);
3532 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3534 if (WORDS_BIG_ENDIAN
)
3535 emit_move_insn (sreg
, plus_constant (sreg
, 7));
3536 for (i
= 0; i
< words
; ++i
)
3538 if (WORDS_BIG_ENDIAN
)
3540 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
3541 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
3545 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
3546 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3548 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3549 gen_rtx_IF_THEN_ELSE (DImode
,
3550 gen_rtx_EQ (DImode
, areg
,
3552 const0_rtx
, ext_tmps
[i
])));
3555 /* Merge the half-words into whole words. */
3556 for (i
= 0; i
< words
; ++i
)
3558 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3559 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
3563 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3564 may be NULL to store zeros. */
3567 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
3568 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3570 rtx
const im8
= GEN_INT (-8);
3571 rtx
const i64
= GEN_INT (64);
3572 rtx ins_tmps
[MAX_MOVE_WORDS
];
3573 rtx st_tmp_1
, st_tmp_2
, dreg
;
3574 rtx st_addr_1
, st_addr_2
, dmema
;
3577 dmema
= XEXP (dmem
, 0);
3578 if (GET_CODE (dmema
) == LO_SUM
)
3579 dmema
= force_reg (Pmode
, dmema
);
3581 /* Generate all the tmp registers we need. */
3582 if (data_regs
!= NULL
)
3583 for (i
= 0; i
< words
; ++i
)
3584 ins_tmps
[i
] = gen_reg_rtx(DImode
);
3585 st_tmp_1
= gen_reg_rtx(DImode
);
3586 st_tmp_2
= gen_reg_rtx(DImode
);
3589 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
3591 st_addr_2
= change_address (dmem
, DImode
,
3592 gen_rtx_AND (DImode
,
3593 plus_constant (dmema
, words
*8 - 1),
3595 set_mem_alias_set (st_addr_2
, 0);
3597 st_addr_1
= change_address (dmem
, DImode
,
3598 gen_rtx_AND (DImode
, dmema
, im8
));
3599 set_mem_alias_set (st_addr_1
, 0);
3601 /* Load up the destination end bits. */
3602 emit_move_insn (st_tmp_2
, st_addr_2
);
3603 emit_move_insn (st_tmp_1
, st_addr_1
);
3605 /* Shift the input data into place. */
3606 dreg
= copy_addr_to_reg (dmema
);
3607 if (WORDS_BIG_ENDIAN
)
3608 emit_move_insn (dreg
, plus_constant (dreg
, 7));
3609 if (data_regs
!= NULL
)
3611 for (i
= words
-1; i
>= 0; --i
)
3613 if (WORDS_BIG_ENDIAN
)
3615 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
3616 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
3620 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
3621 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
3624 for (i
= words
-1; i
> 0; --i
)
3626 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3627 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
3632 /* Split and merge the ends with the destination data. */
3633 if (WORDS_BIG_ENDIAN
)
3635 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
3636 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
3640 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
3641 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
3644 if (data_regs
!= NULL
)
3646 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
3647 st_tmp_2
, 1, OPTAB_WIDEN
);
3648 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
3649 st_tmp_1
, 1, OPTAB_WIDEN
);
3653 if (WORDS_BIG_ENDIAN
)
3654 emit_move_insn (st_addr_1
, st_tmp_1
);
3656 emit_move_insn (st_addr_2
, st_tmp_2
);
3657 for (i
= words
-1; i
> 0; --i
)
3659 rtx tmp
= change_address (dmem
, DImode
,
3660 gen_rtx_AND (DImode
,
3661 plus_constant(dmema
,
3662 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
3664 set_mem_alias_set (tmp
, 0);
3665 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
3667 if (WORDS_BIG_ENDIAN
)
3668 emit_move_insn (st_addr_2
, st_tmp_2
);
3670 emit_move_insn (st_addr_1
, st_tmp_1
);
3674 /* Expand string/block move operations.
3676 operands[0] is the pointer to the destination.
3677 operands[1] is the pointer to the source.
3678 operands[2] is the number of bytes to move.
3679 operands[3] is the alignment. */
3682 alpha_expand_block_move (rtx operands
[])
3684 rtx bytes_rtx
= operands
[2];
3685 rtx align_rtx
= operands
[3];
3686 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3687 HOST_WIDE_INT bytes
= orig_bytes
;
3688 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3689 HOST_WIDE_INT dst_align
= src_align
;
3690 rtx orig_src
= operands
[1];
3691 rtx orig_dst
= operands
[0];
3692 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
3694 unsigned int i
, words
, ofs
, nregs
= 0;
3696 if (orig_bytes
<= 0)
3698 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3701 /* Look for additional alignment information from recorded register info. */
3703 tmp
= XEXP (orig_src
, 0);
3704 if (GET_CODE (tmp
) == REG
)
3705 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3706 else if (GET_CODE (tmp
) == PLUS
3707 && GET_CODE (XEXP (tmp
, 0)) == REG
3708 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3710 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3711 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3715 if (a
>= 64 && c
% 8 == 0)
3717 else if (a
>= 32 && c
% 4 == 0)
3719 else if (a
>= 16 && c
% 2 == 0)
3724 tmp
= XEXP (orig_dst
, 0);
3725 if (GET_CODE (tmp
) == REG
)
3726 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3727 else if (GET_CODE (tmp
) == PLUS
3728 && GET_CODE (XEXP (tmp
, 0)) == REG
3729 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3731 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3732 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3736 if (a
>= 64 && c
% 8 == 0)
3738 else if (a
>= 32 && c
% 4 == 0)
3740 else if (a
>= 16 && c
% 2 == 0)
3746 if (src_align
>= 64 && bytes
>= 8)
3750 for (i
= 0; i
< words
; ++i
)
3751 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3753 for (i
= 0; i
< words
; ++i
)
3754 emit_move_insn (data_regs
[nregs
+ i
],
3755 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
3762 if (src_align
>= 32 && bytes
>= 4)
3766 for (i
= 0; i
< words
; ++i
)
3767 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
3769 for (i
= 0; i
< words
; ++i
)
3770 emit_move_insn (data_regs
[nregs
+ i
],
3771 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
3782 for (i
= 0; i
< words
+1; ++i
)
3783 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3785 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
3793 if (! TARGET_BWX
&& bytes
>= 4)
3795 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
3796 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
3803 if (src_align
>= 16)
3806 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3807 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
3810 } while (bytes
>= 2);
3812 else if (! TARGET_BWX
)
3814 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3815 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
3823 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
3824 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
3829 if (nregs
> ARRAY_SIZE (data_regs
))
3832 /* Now save it back out again. */
3836 /* Write out the data in whatever chunks reading the source allowed. */
3837 if (dst_align
>= 64)
3839 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3841 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
3848 if (dst_align
>= 32)
3850 /* If the source has remaining DImode regs, write them out in
3852 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3854 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
3855 NULL_RTX
, 1, OPTAB_WIDEN
);
3857 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
3858 gen_lowpart (SImode
, data_regs
[i
]));
3859 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
3860 gen_lowpart (SImode
, tmp
));
3865 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
3867 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
3874 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3876 /* Write out a remaining block of words using unaligned methods. */
3878 for (words
= 1; i
+ words
< nregs
; words
++)
3879 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
3883 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
3885 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
3892 /* Due to the above, this won't be aligned. */
3893 /* ??? If we have more than one of these, consider constructing full
3894 words in registers and using alpha_expand_unaligned_store_words. */
3895 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
3897 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
3902 if (dst_align
>= 16)
3903 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
3905 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
3910 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
3912 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
3917 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
3919 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
3931 alpha_expand_block_clear (rtx operands
[])
3933 rtx bytes_rtx
= operands
[1];
3934 rtx align_rtx
= operands
[2];
3935 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3936 HOST_WIDE_INT bytes
= orig_bytes
;
3937 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3938 HOST_WIDE_INT alignofs
= 0;
3939 rtx orig_dst
= operands
[0];
3941 int i
, words
, ofs
= 0;
3943 if (orig_bytes
<= 0)
3945 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3948 /* Look for stricter alignment. */
3949 tmp
= XEXP (orig_dst
, 0);
3950 if (GET_CODE (tmp
) == REG
)
3951 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3952 else if (GET_CODE (tmp
) == PLUS
3953 && GET_CODE (XEXP (tmp
, 0)) == REG
3954 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3956 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3957 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3962 align
= a
, alignofs
= 8 - c
% 8;
3964 align
= a
, alignofs
= 4 - c
% 4;
3966 align
= a
, alignofs
= 2 - c
% 2;
3970 /* Handle an unaligned prefix first. */
3974 #if HOST_BITS_PER_WIDE_INT >= 64
3975 /* Given that alignofs is bounded by align, the only time BWX could
3976 generate three stores is for a 7 byte fill. Prefer two individual
3977 stores over a load/mask/store sequence. */
3978 if ((!TARGET_BWX
|| alignofs
== 7)
3980 && !(alignofs
== 4 && bytes
>= 4))
3982 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
3983 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
3987 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
3988 set_mem_alias_set (mem
, 0);
3990 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
3991 if (bytes
< alignofs
)
3993 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4004 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4005 NULL_RTX
, 1, OPTAB_WIDEN
);
4007 emit_move_insn (mem
, tmp
);
4011 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4013 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4018 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4020 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4025 if (alignofs
== 4 && bytes
>= 4)
4027 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4033 /* If we've not used the extra lead alignment information by now,
4034 we won't be able to. Downgrade align to match what's left over. */
4037 alignofs
= alignofs
& -alignofs
;
4038 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4042 /* Handle a block of contiguous long-words. */
4044 if (align
>= 64 && bytes
>= 8)
4048 for (i
= 0; i
< words
; ++i
)
4049 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4056 /* If the block is large and appropriately aligned, emit a single
4057 store followed by a sequence of stq_u insns. */
4059 if (align
>= 32 && bytes
> 16)
4063 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4067 orig_dsta
= XEXP (orig_dst
, 0);
4068 if (GET_CODE (orig_dsta
) == LO_SUM
)
4069 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4072 for (i
= 0; i
< words
; ++i
)
4075 = change_address (orig_dst
, DImode
,
4076 gen_rtx_AND (DImode
,
4077 plus_constant (orig_dsta
, ofs
+ i
*8),
4079 set_mem_alias_set (mem
, 0);
4080 emit_move_insn (mem
, const0_rtx
);
4083 /* Depending on the alignment, the first stq_u may have overlapped
4084 with the initial stl, which means that the last stq_u didn't
4085 write as much as it would appear. Leave those questionable bytes
4087 bytes
-= words
* 8 - 4;
4088 ofs
+= words
* 8 - 4;
4091 /* Handle a smaller block of aligned words. */
4093 if ((align
>= 64 && bytes
== 4)
4094 || (align
== 32 && bytes
>= 4))
4098 for (i
= 0; i
< words
; ++i
)
4099 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4106 /* An unaligned block uses stq_u stores for as many as possible. */
4112 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4118 /* Next clean up any trailing pieces. */
4120 #if HOST_BITS_PER_WIDE_INT >= 64
4121 /* Count the number of bits in BYTES for which aligned stores could
4124 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4128 /* If we have appropriate alignment (and it wouldn't take too many
4129 instructions otherwise), mask out the bytes we need. */
4130 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4137 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4138 set_mem_alias_set (mem
, 0);
4140 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4142 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4143 NULL_RTX
, 1, OPTAB_WIDEN
);
4145 emit_move_insn (mem
, tmp
);
4148 else if (align
>= 32 && bytes
< 4)
4153 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4154 set_mem_alias_set (mem
, 0);
4156 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4158 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4159 NULL_RTX
, 1, OPTAB_WIDEN
);
4161 emit_move_insn (mem
, tmp
);
4167 if (!TARGET_BWX
&& bytes
>= 4)
4169 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4179 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4183 } while (bytes
>= 2);
4185 else if (! TARGET_BWX
)
4187 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4195 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4203 /* Returns a mask so that zap(x, value) == x & mask. */
4206 alpha_expand_zap_mask (HOST_WIDE_INT value
)
4211 if (HOST_BITS_PER_WIDE_INT
>= 64)
4213 HOST_WIDE_INT mask
= 0;
4215 for (i
= 7; i
>= 0; --i
)
4218 if (!((value
>> i
) & 1))
4222 result
= gen_int_mode (mask
, DImode
);
4224 else if (HOST_BITS_PER_WIDE_INT
== 32)
4226 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
4228 for (i
= 7; i
>= 4; --i
)
4231 if (!((value
>> i
) & 1))
4235 for (i
= 3; i
>= 0; --i
)
4238 if (!((value
>> i
) & 1))
4242 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
4251 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
4252 enum machine_mode mode
,
4253 rtx op0
, rtx op1
, rtx op2
)
4255 op0
= gen_lowpart (mode
, op0
);
4257 if (op1
== const0_rtx
)
4258 op1
= CONST0_RTX (mode
);
4260 op1
= gen_lowpart (mode
, op1
);
4262 if (op2
== const0_rtx
)
4263 op2
= CONST0_RTX (mode
);
4265 op2
= gen_lowpart (mode
, op2
);
4267 emit_insn ((*gen
) (op0
, op1
, op2
));
4270 /* Adjust the cost of a scheduling dependency. Return the new cost of
4271 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4274 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4276 enum attr_type insn_type
, dep_insn_type
;
4278 /* If the dependence is an anti-dependence, there is no cost. For an
4279 output dependence, there is sometimes a cost, but it doesn't seem
4280 worth handling those few cases. */
4281 if (REG_NOTE_KIND (link
) != 0)
4284 /* If we can't recognize the insns, we can't really do anything. */
4285 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4288 insn_type
= get_attr_type (insn
);
4289 dep_insn_type
= get_attr_type (dep_insn
);
4291 /* Bring in the user-defined memory latency. */
4292 if (dep_insn_type
== TYPE_ILD
4293 || dep_insn_type
== TYPE_FLD
4294 || dep_insn_type
== TYPE_LDSYM
)
4295 cost
+= alpha_memory_latency
-1;
4297 /* Everything else handled in DFA bypasses now. */
4302 /* The number of instructions that can be issued per cycle. */
4305 alpha_issue_rate (void)
4307 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
4310 /* How many alternative schedules to try. This should be as wide as the
4311 scheduling freedom in the DFA, but no wider. Making this value too
4312 large results extra work for the scheduler.
4314 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4315 alternative schedules. For EV5, we can choose between E0/E1 and
4316 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4319 alpha_multipass_dfa_lookahead (void)
4321 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
4324 /* Machine-specific function data. */
4326 struct machine_function
GTY(())
4329 /* List of call information words for calls from this function. */
4330 struct rtx_def
*first_ciw
;
4331 struct rtx_def
*last_ciw
;
4334 /* List of deferred case vectors. */
4335 struct rtx_def
*addr_list
;
4338 const char *some_ld_name
;
4340 /* For TARGET_LD_BUGGY_LDGP. */
4341 struct rtx_def
*gp_save_rtx
;
4344 /* How to allocate a 'struct machine_function'. */
4346 static struct machine_function
*
4347 alpha_init_machine_status (void)
4349 return ((struct machine_function
*)
4350 ggc_alloc_cleared (sizeof (struct machine_function
)));
4353 /* Functions to save and restore alpha_return_addr_rtx. */
4355 /* Start the ball rolling with RETURN_ADDR_RTX. */
4358 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
4363 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4366 /* Return or create a memory slot containing the gp value for the current
4367 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4370 alpha_gp_save_rtx (void)
4372 rtx seq
, m
= cfun
->machine
->gp_save_rtx
;
4378 m
= assign_stack_local (DImode
, UNITS_PER_WORD
, BITS_PER_WORD
);
4379 m
= validize_mem (m
);
4380 emit_move_insn (m
, pic_offset_table_rtx
);
4384 emit_insn_after (seq
, entry_of_function ());
4386 cfun
->machine
->gp_save_rtx
= m
;
4393 alpha_ra_ever_killed (void)
4397 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4398 return regs_ever_live
[REG_RA
];
4400 push_topmost_sequence ();
4402 pop_topmost_sequence ();
4404 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
4408 /* Return the trap mode suffix applicable to the current
4409 instruction, or NULL. */
4412 get_trap_mode_suffix (void)
4414 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
4418 case TRAP_SUFFIX_NONE
:
4421 case TRAP_SUFFIX_SU
:
4422 if (alpha_fptm
>= ALPHA_FPTM_SU
)
4426 case TRAP_SUFFIX_SUI
:
4427 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
4431 case TRAP_SUFFIX_V_SV
:
4439 case ALPHA_FPTM_SUI
:
4444 case TRAP_SUFFIX_V_SV_SVI
:
4453 case ALPHA_FPTM_SUI
:
4458 case TRAP_SUFFIX_U_SU_SUI
:
4467 case ALPHA_FPTM_SUI
:
4475 /* Return the rounding mode suffix applicable to the current
4476 instruction, or NULL. */
4479 get_round_mode_suffix (void)
4481 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
4485 case ROUND_SUFFIX_NONE
:
4487 case ROUND_SUFFIX_NORMAL
:
4490 case ALPHA_FPRM_NORM
:
4492 case ALPHA_FPRM_MINF
:
4494 case ALPHA_FPRM_CHOP
:
4496 case ALPHA_FPRM_DYN
:
4501 case ROUND_SUFFIX_C
:
4507 /* Locate some local-dynamic symbol still in use by this function
4508 so that we can print its name in some movdi_er_tlsldm pattern. */
4511 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4515 if (GET_CODE (x
) == SYMBOL_REF
4516 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4518 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4526 get_some_local_dynamic_name (void)
4530 if (cfun
->machine
->some_ld_name
)
4531 return cfun
->machine
->some_ld_name
;
4533 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4535 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4536 return cfun
->machine
->some_ld_name
;
4541 /* Print an operand. Recognize special options, documented below. */
4544 print_operand (FILE *file
, rtx x
, int code
)
4551 /* Print the assembler name of the current function. */
4552 assemble_name (file
, alpha_fnname
);
4556 assemble_name (file
, get_some_local_dynamic_name ());
4561 const char *trap
= get_trap_mode_suffix ();
4562 const char *round
= get_round_mode_suffix ();
4565 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
4566 (trap
? trap
: ""), (round
? round
: ""));
4571 /* Generates single precision instruction suffix. */
4572 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
4576 /* Generates double precision instruction suffix. */
4577 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
4581 /* Generates a nop after a noreturn call at the very end of the
4583 if (next_real_insn (current_output_insn
) == 0)
4584 fprintf (file
, "\n\tnop");
4588 if (alpha_this_literal_sequence_number
== 0)
4589 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
4590 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
4594 if (alpha_this_gpdisp_sequence_number
== 0)
4595 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
4596 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
4600 if (GET_CODE (x
) == HIGH
)
4601 output_addr_const (file
, XEXP (x
, 0));
4603 output_operand_lossage ("invalid %%H value");
4610 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
4612 x
= XVECEXP (x
, 0, 0);
4613 lituse
= "lituse_tlsgd";
4615 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
4617 x
= XVECEXP (x
, 0, 0);
4618 lituse
= "lituse_tlsldm";
4620 else if (GET_CODE (x
) == CONST_INT
)
4621 lituse
= "lituse_jsr";
4624 output_operand_lossage ("invalid %%J value");
4628 if (x
!= const0_rtx
)
4629 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
4634 /* If this operand is the constant zero, write it as "$31". */
4635 if (GET_CODE (x
) == REG
)
4636 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
4637 else if (x
== CONST0_RTX (GET_MODE (x
)))
4638 fprintf (file
, "$31");
4640 output_operand_lossage ("invalid %%r value");
4644 /* Similar, but for floating-point. */
4645 if (GET_CODE (x
) == REG
)
4646 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
4647 else if (x
== CONST0_RTX (GET_MODE (x
)))
4648 fprintf (file
, "$f31");
4650 output_operand_lossage ("invalid %%R value");
4654 /* Write the 1's complement of a constant. */
4655 if (GET_CODE (x
) != CONST_INT
)
4656 output_operand_lossage ("invalid %%N value");
4658 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
4662 /* Write 1 << C, for a constant C. */
4663 if (GET_CODE (x
) != CONST_INT
)
4664 output_operand_lossage ("invalid %%P value");
4666 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
4670 /* Write the high-order 16 bits of a constant, sign-extended. */
4671 if (GET_CODE (x
) != CONST_INT
)
4672 output_operand_lossage ("invalid %%h value");
4674 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
4678 /* Write the low-order 16 bits of a constant, sign-extended. */
4679 if (GET_CODE (x
) != CONST_INT
)
4680 output_operand_lossage ("invalid %%L value");
4682 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4683 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
4687 /* Write mask for ZAP insn. */
4688 if (GET_CODE (x
) == CONST_DOUBLE
)
4690 HOST_WIDE_INT mask
= 0;
4691 HOST_WIDE_INT value
;
4693 value
= CONST_DOUBLE_LOW (x
);
4694 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
4699 value
= CONST_DOUBLE_HIGH (x
);
4700 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
4703 mask
|= (1 << (i
+ sizeof (int)));
4705 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
4708 else if (GET_CODE (x
) == CONST_INT
)
4710 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
4712 for (i
= 0; i
< 8; i
++, value
>>= 8)
4716 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
4719 output_operand_lossage ("invalid %%m value");
4723 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
4724 if (GET_CODE (x
) != CONST_INT
4725 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
4726 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
4727 output_operand_lossage ("invalid %%M value");
4729 fprintf (file
, "%s",
4730 (INTVAL (x
) == 8 ? "b"
4731 : INTVAL (x
) == 16 ? "w"
4732 : INTVAL (x
) == 32 ? "l"
4737 /* Similar, except do it from the mask. */
4738 if (GET_CODE (x
) == CONST_INT
)
4740 HOST_WIDE_INT value
= INTVAL (x
);
4747 if (value
== 0xffff)
4752 if (value
== 0xffffffff)
4763 else if (HOST_BITS_PER_WIDE_INT
== 32
4764 && GET_CODE (x
) == CONST_DOUBLE
4765 && CONST_DOUBLE_LOW (x
) == 0xffffffff
4766 && CONST_DOUBLE_HIGH (x
) == 0)
4771 output_operand_lossage ("invalid %%U value");
4775 /* Write the constant value divided by 8 for little-endian mode or
4776 (56 - value) / 8 for big-endian mode. */
4778 if (GET_CODE (x
) != CONST_INT
4779 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
4782 || (INTVAL (x
) & 7) != 0)
4783 output_operand_lossage ("invalid %%s value");
4785 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4787 ? (56 - INTVAL (x
)) / 8
4792 /* Same, except compute (64 - c) / 8 */
4794 if (GET_CODE (x
) != CONST_INT
4795 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
4796 && (INTVAL (x
) & 7) != 8)
4797 output_operand_lossage ("invalid %%s value");
4799 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
4804 /* On Unicos/Mk systems: use a DEX expression if the symbol
4805 clashes with a register name. */
4806 int dex
= unicosmk_need_dex (x
);
4808 fprintf (file
, "DEX(%d)", dex
);
4810 output_addr_const (file
, x
);
4814 case 'C': case 'D': case 'c': case 'd':
4815 /* Write out comparison name. */
4817 enum rtx_code c
= GET_CODE (x
);
4819 if (!COMPARISON_P (x
))
4820 output_operand_lossage ("invalid %%C value");
4822 else if (code
== 'D')
4823 c
= reverse_condition (c
);
4824 else if (code
== 'c')
4825 c
= swap_condition (c
);
4826 else if (code
== 'd')
4827 c
= swap_condition (reverse_condition (c
));
4830 fprintf (file
, "ule");
4832 fprintf (file
, "ult");
4833 else if (c
== UNORDERED
)
4834 fprintf (file
, "un");
4836 fprintf (file
, "%s", GET_RTX_NAME (c
));
4841 /* Write the divide or modulus operator. */
4842 switch (GET_CODE (x
))
4845 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
4848 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
4851 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
4854 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
4857 output_operand_lossage ("invalid %%E value");
4863 /* Write "_u" for unaligned access. */
4864 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
4865 fprintf (file
, "_u");
4869 if (GET_CODE (x
) == REG
)
4870 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
4871 else if (GET_CODE (x
) == MEM
)
4872 output_address (XEXP (x
, 0));
4873 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
4875 switch (XINT (XEXP (x
, 0), 1))
4879 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
4882 output_operand_lossage ("unknown relocation unspec");
4887 output_addr_const (file
, x
);
4891 output_operand_lossage ("invalid %%xn code");
4896 print_operand_address (FILE *file
, rtx addr
)
4899 HOST_WIDE_INT offset
= 0;
4901 if (GET_CODE (addr
) == AND
)
4902 addr
= XEXP (addr
, 0);
4904 if (GET_CODE (addr
) == PLUS
4905 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4907 offset
= INTVAL (XEXP (addr
, 1));
4908 addr
= XEXP (addr
, 0);
4911 if (GET_CODE (addr
) == LO_SUM
)
4913 const char *reloc16
, *reloclo
;
4914 rtx op1
= XEXP (addr
, 1);
4916 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
4918 op1
= XEXP (op1
, 0);
4919 switch (XINT (op1
, 1))
4923 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
4927 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
4930 output_operand_lossage ("unknown relocation unspec");
4934 output_addr_const (file
, XVECEXP (op1
, 0, 0));
4939 reloclo
= "gprellow";
4940 output_addr_const (file
, op1
);
4944 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
4946 addr
= XEXP (addr
, 0);
4947 if (GET_CODE (addr
) == REG
)
4948 basereg
= REGNO (addr
);
4949 else if (GET_CODE (addr
) == SUBREG
4950 && GET_CODE (SUBREG_REG (addr
)) == REG
)
4951 basereg
= subreg_regno (addr
);
4955 fprintf (file
, "($%d)\t\t!%s", basereg
,
4956 (basereg
== 29 ? reloc16
: reloclo
));
4960 if (GET_CODE (addr
) == REG
)
4961 basereg
= REGNO (addr
);
4962 else if (GET_CODE (addr
) == SUBREG
4963 && GET_CODE (SUBREG_REG (addr
)) == REG
)
4964 basereg
= subreg_regno (addr
);
4965 else if (GET_CODE (addr
) == CONST_INT
)
4966 offset
= INTVAL (addr
);
4968 #if TARGET_ABI_OPEN_VMS
4969 else if (GET_CODE (addr
) == SYMBOL_REF
)
4971 fprintf (file
, "%s", XSTR (addr
, 0));
4974 else if (GET_CODE (addr
) == CONST
4975 && GET_CODE (XEXP (addr
, 0)) == PLUS
4976 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
4978 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
4979 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
4980 INTVAL (XEXP (XEXP (addr
, 0), 1)));
4988 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
4991 /* Emit RTL insns to initialize the variable parts of a trampoline at
4992 TRAMP. FNADDR is an RTX for the address of the function's pure
4993 code. CXT is an RTX for the static chain value for the function.
4995 The three offset parameters are for the individual template's
4996 layout. A JMPOFS < 0 indicates that the trampoline does not
4997 contain instructions at all.
4999 We assume here that a function will be called many more times than
5000 its address is taken (e.g., it might be passed to qsort), so we
5001 take the trouble to initialize the "hint" field in the JMP insn.
5002 Note that the hint field is PC (new) + 4 * bits 13:0. */
5005 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5006 int fnofs
, int cxtofs
, int jmpofs
)
5008 rtx temp
, temp1
, addr
;
5009 /* VMS really uses DImode pointers in memory at this point. */
5010 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5012 #ifdef POINTERS_EXTEND_UNSIGNED
5013 fnaddr
= convert_memory_address (mode
, fnaddr
);
5014 cxt
= convert_memory_address (mode
, cxt
);
5017 /* Store function address and CXT. */
5018 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5019 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5020 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5021 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5023 /* This has been disabled since the hint only has a 32k range, and in
5024 no existing OS is the stack within 32k of the text segment. */
5025 if (0 && jmpofs
>= 0)
5027 /* Compute hint value. */
5028 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5029 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5031 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5032 build_int_cst (NULL_TREE
, 2), NULL_RTX
, 1);
5033 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5034 GEN_INT (0x3fff), 0);
5036 /* Merge in the hint. */
5037 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5038 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5039 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5040 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5042 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5045 #ifdef ENABLE_EXECUTE_STACK
5046 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5047 0, VOIDmode
, 1, tramp
, Pmode
);
5051 emit_insn (gen_imb ());
5054 /* Determine where to put an argument to a function.
5055 Value is zero to push the argument on the stack,
5056 or a hard register in which to store the argument.
5058 MODE is the argument's machine mode.
5059 TYPE is the data type of the argument (as a tree).
5060 This is null for libcalls where that information may
5062 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5063 the preceding args and about the function being called.
5064 NAMED is nonzero if this argument is a named parameter
5065 (otherwise it is an extra parameter matching an ellipsis).
5067 On Alpha the first 6 words of args are normally in registers
5068 and the rest are pushed. */
5071 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5072 int named ATTRIBUTE_UNUSED
)
5077 /* Don't get confused and pass small structures in FP registers. */
5078 if (type
&& AGGREGATE_TYPE_P (type
))
5082 #ifdef ENABLE_CHECKING
5083 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5085 if (COMPLEX_MODE_P (mode
))
5089 /* Set up defaults for FP operands passed in FP registers, and
5090 integral operands passed in integer registers. */
5091 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5097 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5098 the three platforms, so we can't avoid conditional compilation. */
5099 #if TARGET_ABI_OPEN_VMS
5101 if (mode
== VOIDmode
)
5102 return alpha_arg_info_reg_val (cum
);
5104 num_args
= cum
.num_args
;
5106 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5109 #elif TARGET_ABI_UNICOSMK
5113 /* If this is the last argument, generate the call info word (CIW). */
5114 /* ??? We don't include the caller's line number in the CIW because
5115 I don't know how to determine it if debug infos are turned off. */
5116 if (mode
== VOIDmode
)
5125 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5126 if (cum
.reg_args_type
[i
])
5127 lo
|= (1 << (7 - i
));
5129 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5132 lo
|= cum
.num_reg_words
;
5134 #if HOST_BITS_PER_WIDE_INT == 32
5135 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5137 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5138 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5141 ciw
= immed_double_const (lo
, hi
, DImode
);
5143 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5144 UNSPEC_UMK_LOAD_CIW
);
5147 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5148 num_args
= cum
.num_reg_words
;
5150 || cum
.num_reg_words
+ size
> 6
5151 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5153 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5157 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5158 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5160 /* The argument fits in two registers. Note that we still need to
5161 reserve a register for empty structures. */
5165 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5168 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5169 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5170 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5174 #elif TARGET_ABI_OSF
5180 /* VOID is passed as a special flag for "last argument". */
5181 if (type
== void_type_node
)
5183 else if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5187 #error Unhandled ABI
5190 return gen_rtx_REG (mode
, num_args
+ basereg
);
5194 alpha_arg_partial_bytes (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5195 enum machine_mode mode ATTRIBUTE_UNUSED
,
5196 tree type ATTRIBUTE_UNUSED
,
5197 bool named ATTRIBUTE_UNUSED
)
5201 #if TARGET_ABI_OPEN_VMS
5202 if (cum
->num_args
< 6
5203 && 6 < cum
->num_args
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5204 words
= 6 - (CUM
).num_args
;
5205 #elif TARGET_ABI_UNICOSMK
5206 /* Never any split arguments. */
5207 #elif TARGET_ABI_OSF
5208 if (*cum
< 6 && 6 < *cum
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5211 #error Unhandled ABI
5214 return words
* UNITS_PER_WORD
;
5218 /* Return true if TYPE must be returned in memory, instead of in registers. */
5221 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
5223 enum machine_mode mode
= VOIDmode
;
5228 mode
= TYPE_MODE (type
);
5230 /* All aggregates are returned in memory. */
5231 if (AGGREGATE_TYPE_P (type
))
5235 size
= GET_MODE_SIZE (mode
);
5236 switch (GET_MODE_CLASS (mode
))
5238 case MODE_VECTOR_FLOAT
:
5239 /* Pass all float vectors in memory, like an aggregate. */
5242 case MODE_COMPLEX_FLOAT
:
5243 /* We judge complex floats on the size of their element,
5244 not the size of the whole type. */
5245 size
= GET_MODE_UNIT_SIZE (mode
);
5250 case MODE_COMPLEX_INT
:
5251 case MODE_VECTOR_INT
:
5255 /* ??? We get called on all sorts of random stuff from
5256 aggregate_value_p. We can't abort, but it's not clear
5257 what's safe to return. Pretend it's a struct I guess. */
5261 /* Otherwise types must fit in one register. */
5262 return size
> UNITS_PER_WORD
;
5265 /* Return true if TYPE should be passed by invisible reference. */
5268 alpha_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
5269 enum machine_mode mode
,
5270 tree type ATTRIBUTE_UNUSED
,
5271 bool named ATTRIBUTE_UNUSED
)
5273 return mode
== TFmode
|| mode
== TCmode
;
5276 /* Define how to find the value returned by a function. VALTYPE is the
5277 data type of the value (as a tree). If the precise function being
5278 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5279 MODE is set instead of VALTYPE for libcalls.
5281 On Alpha the value is found in $0 for integer functions and
5282 $f0 for floating-point functions. */
5285 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
5286 enum machine_mode mode
)
5288 unsigned int regnum
, dummy
;
5289 enum mode_class
class;
5291 #ifdef ENABLE_CHECKING
5292 if (valtype
&& alpha_return_in_memory (valtype
, func
))
5297 mode
= TYPE_MODE (valtype
);
5299 class = GET_MODE_CLASS (mode
);
5303 PROMOTE_MODE (mode
, dummy
, valtype
);
5306 case MODE_COMPLEX_INT
:
5307 case MODE_VECTOR_INT
:
5315 case MODE_COMPLEX_FLOAT
:
5317 enum machine_mode cmode
= GET_MODE_INNER (mode
);
5319 return gen_rtx_PARALLEL
5322 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
5324 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
5325 GEN_INT (GET_MODE_SIZE (cmode
)))));
5332 return gen_rtx_REG (mode
, regnum
);
5335 /* TCmode complex values are passed by invisible reference. We
5336 should not split these values. */
5339 alpha_split_complex_arg (tree type
)
5341 return TYPE_MODE (type
) != TCmode
;
5345 alpha_build_builtin_va_list (void)
5347 tree base
, ofs
, space
, record
, type_decl
;
5349 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5350 return ptr_type_node
;
5352 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5353 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5354 TREE_CHAIN (record
) = type_decl
;
5355 TYPE_NAME (record
) = type_decl
;
5357 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5359 /* Dummy field to prevent alignment warnings. */
5360 space
= build_decl (FIELD_DECL
, NULL_TREE
, integer_type_node
);
5361 DECL_FIELD_CONTEXT (space
) = record
;
5362 DECL_ARTIFICIAL (space
) = 1;
5363 DECL_IGNORED_P (space
) = 1;
5365 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
5367 DECL_FIELD_CONTEXT (ofs
) = record
;
5368 TREE_CHAIN (ofs
) = space
;
5370 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
5372 DECL_FIELD_CONTEXT (base
) = record
;
5373 TREE_CHAIN (base
) = ofs
;
5375 TYPE_FIELDS (record
) = base
;
5376 layout_type (record
);
5381 /* Perform any needed actions needed for a function that is receiving a
5382 variable number of arguments. */
5385 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
,
5386 enum machine_mode mode ATTRIBUTE_UNUSED
,
5387 tree type ATTRIBUTE_UNUSED
,
5388 int *pretend_size
, int no_rtl
)
5390 #if TARGET_ABI_UNICOSMK
5391 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
5392 arguments on the stack. Unfortunately, it doesn't always store the first
5393 one (i.e. the one that arrives in $16 or $f16). This is not a problem
5394 with stdargs as we always have at least one named argument there. */
5395 int num_reg_words
= pcum
->num_reg_words
;
5396 if (num_reg_words
< 6)
5400 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words
+ 1)));
5401 emit_insn (gen_arg_home_umk ());
5405 #elif TARGET_ABI_OPEN_VMS
5406 /* For VMS, we allocate space for all 6 arg registers plus a count.
5408 However, if NO registers need to be saved, don't allocate any space.
5409 This is not only because we won't need the space, but because AP
5410 includes the current_pretend_args_size and we don't want to mess up
5411 any ap-relative addresses already made. */
5412 if (pcum
->num_args
< 6)
5416 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
5417 emit_insn (gen_arg_home ());
5419 *pretend_size
= 7 * UNITS_PER_WORD
;
5422 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
5423 only push those that are remaining. However, if NO registers need to
5424 be saved, don't allocate any space. This is not only because we won't
5425 need the space, but because AP includes the current_pretend_args_size
5426 and we don't want to mess up any ap-relative addresses already made.
5428 If we are not to use the floating-point registers, save the integer
5429 registers where we would put the floating-point registers. This is
5430 not the most efficient way to implement varargs with just one register
5431 class, but it isn't worth doing anything more efficient in this rare
5433 CUMULATIVE_ARGS cum
= *pcum
;
5440 int set
= get_varargs_alias_set ();
5443 tmp
= gen_rtx_MEM (BLKmode
,
5444 plus_constant (virtual_incoming_args_rtx
,
5445 (cum
+ 6) * UNITS_PER_WORD
));
5446 set_mem_alias_set (tmp
, set
);
5447 move_block_from_reg (16 + cum
, tmp
, 6 - cum
);
5449 tmp
= gen_rtx_MEM (BLKmode
,
5450 plus_constant (virtual_incoming_args_rtx
,
5451 cum
* UNITS_PER_WORD
));
5452 set_mem_alias_set (tmp
, set
);
5453 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
5456 *pretend_size
= 12 * UNITS_PER_WORD
;
5461 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
5463 HOST_WIDE_INT offset
;
5464 tree t
, offset_field
, base_field
;
5466 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
5469 if (TARGET_ABI_UNICOSMK
)
5470 std_expand_builtin_va_start (valist
, nextarg
);
5472 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
5473 up by 48, storing fp arg registers in the first 48 bytes, and the
5474 integer arg registers in the next 48 bytes. This is only done,
5475 however, if any integer registers need to be stored.
5477 If no integer registers need be stored, then we must subtract 48
5478 in order to account for the integer arg registers which are counted
5479 in argsize above, but which are not actually stored on the stack.
5480 Must further be careful here about structures straddling the last
5481 integer argument register; that futzes with pretend_args_size,
5482 which changes the meaning of AP. */
5485 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
5487 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
5489 if (TARGET_ABI_OPEN_VMS
)
5491 nextarg
= plus_constant (nextarg
, offset
);
5492 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
5493 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
5494 make_tree (ptr_type_node
, nextarg
));
5495 TREE_SIDE_EFFECTS (t
) = 1;
5497 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5501 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5502 offset_field
= TREE_CHAIN (base_field
);
5504 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5505 valist
, base_field
, NULL_TREE
);
5506 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5507 valist
, offset_field
, NULL_TREE
);
5509 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
5510 t
= build (PLUS_EXPR
, ptr_type_node
, t
,
5511 build_int_cst (NULL_TREE
, offset
));
5512 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
5513 TREE_SIDE_EFFECTS (t
) = 1;
5514 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5516 t
= build_int_cst (NULL_TREE
, NUM_ARGS
* UNITS_PER_WORD
);
5517 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
5518 TREE_SIDE_EFFECTS (t
) = 1;
5519 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5524 alpha_gimplify_va_arg_1 (tree type
, tree base
, tree offset
, tree
*pre_p
)
5526 tree type_size
, ptr_type
, addend
, t
, addr
, internal_post
;
5528 /* If the type could not be passed in registers, skip the block
5529 reserved for the registers. */
5530 if (targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
5532 t
= build_int_cst (TREE_TYPE (offset
), 6*8);
5533 t
= build (MODIFY_EXPR
, TREE_TYPE (offset
), offset
,
5534 build (MAX_EXPR
, TREE_TYPE (offset
), offset
, t
));
5535 gimplify_and_add (t
, pre_p
);
5539 ptr_type
= build_pointer_type (type
);
5541 if (TREE_CODE (type
) == COMPLEX_TYPE
)
5543 tree real_part
, imag_part
, real_temp
;
5545 real_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
5548 /* Copy the value into a new temporary, lest the formal temporary
5549 be reused out from under us. */
5550 real_temp
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
5552 imag_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
5555 return build (COMPLEX_EXPR
, type
, real_temp
, imag_part
);
5557 else if (TREE_CODE (type
) == REAL_TYPE
)
5559 tree fpaddend
, cond
, fourtyeight
;
5561 fourtyeight
= build_int_cst (TREE_TYPE (addend
), 6*8);
5562 fpaddend
= fold (build (MINUS_EXPR
, TREE_TYPE (addend
),
5563 addend
, fourtyeight
));
5564 cond
= fold (build (LT_EXPR
, boolean_type_node
, addend
, fourtyeight
));
5565 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
5569 /* Build the final address and force that value into a temporary. */
5570 addr
= build (PLUS_EXPR
, ptr_type
, fold_convert (ptr_type
, base
),
5571 fold_convert (ptr_type
, addend
));
5572 internal_post
= NULL
;
5573 gimplify_expr (&addr
, pre_p
, &internal_post
, is_gimple_val
, fb_rvalue
);
5574 append_to_statement_list (internal_post
, pre_p
);
5576 /* Update the offset field. */
5577 type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
));
5578 if (type_size
== NULL
|| TREE_OVERFLOW (type_size
))
5582 t
= size_binop (PLUS_EXPR
, type_size
, size_int (7));
5583 t
= size_binop (TRUNC_DIV_EXPR
, t
, size_int (8));
5584 t
= size_binop (MULT_EXPR
, t
, size_int (8));
5586 t
= fold_convert (TREE_TYPE (offset
), t
);
5587 t
= build (MODIFY_EXPR
, void_type_node
, offset
,
5588 build (PLUS_EXPR
, TREE_TYPE (offset
), offset
, t
));
5589 gimplify_and_add (t
, pre_p
);
5591 return build_fold_indirect_ref (addr
);
5595 alpha_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
5597 tree offset_field
, base_field
, offset
, base
, t
, r
;
5600 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5601 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5603 base_field
= TYPE_FIELDS (va_list_type_node
);
5604 offset_field
= TREE_CHAIN (base_field
);
5605 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5606 valist
, base_field
, NULL_TREE
);
5607 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5608 valist
, offset_field
, NULL_TREE
);
5610 /* Pull the fields of the structure out into temporaries. Since we never
5611 modify the base field, we can use a formal temporary. Sign-extend the
5612 offset field so that it's the proper width for pointer arithmetic. */
5613 base
= get_formal_tmp_var (base_field
, pre_p
);
5615 t
= fold_convert (lang_hooks
.types
.type_for_size (64, 0), offset_field
);
5616 offset
= get_initialized_tmp_var (t
, pre_p
, NULL
);
5618 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5620 type
= build_pointer_type (type
);
5622 /* Find the value. Note that this will be a stable indirection, or
5623 a composite of stable indirections in the case of complex. */
5624 r
= alpha_gimplify_va_arg_1 (type
, base
, offset
, pre_p
);
5626 /* Stuff the offset temporary back into its field. */
5627 t
= build (MODIFY_EXPR
, void_type_node
, offset_field
,
5628 fold_convert (TREE_TYPE (offset_field
), offset
));
5629 gimplify_and_add (t
, pre_p
);
5632 r
= build_fold_indirect_ref (r
);
5641 ALPHA_BUILTIN_CMPBGE
,
5642 ALPHA_BUILTIN_EXTBL
,
5643 ALPHA_BUILTIN_EXTWL
,
5644 ALPHA_BUILTIN_EXTLL
,
5645 ALPHA_BUILTIN_EXTQL
,
5646 ALPHA_BUILTIN_EXTWH
,
5647 ALPHA_BUILTIN_EXTLH
,
5648 ALPHA_BUILTIN_EXTQH
,
5649 ALPHA_BUILTIN_INSBL
,
5650 ALPHA_BUILTIN_INSWL
,
5651 ALPHA_BUILTIN_INSLL
,
5652 ALPHA_BUILTIN_INSQL
,
5653 ALPHA_BUILTIN_INSWH
,
5654 ALPHA_BUILTIN_INSLH
,
5655 ALPHA_BUILTIN_INSQH
,
5656 ALPHA_BUILTIN_MSKBL
,
5657 ALPHA_BUILTIN_MSKWL
,
5658 ALPHA_BUILTIN_MSKLL
,
5659 ALPHA_BUILTIN_MSKQL
,
5660 ALPHA_BUILTIN_MSKWH
,
5661 ALPHA_BUILTIN_MSKLH
,
5662 ALPHA_BUILTIN_MSKQH
,
5663 ALPHA_BUILTIN_UMULH
,
5665 ALPHA_BUILTIN_ZAPNOT
,
5666 ALPHA_BUILTIN_AMASK
,
5667 ALPHA_BUILTIN_IMPLVER
,
5669 ALPHA_BUILTIN_THREAD_POINTER
,
5670 ALPHA_BUILTIN_SET_THREAD_POINTER
,
5673 ALPHA_BUILTIN_MINUB8
,
5674 ALPHA_BUILTIN_MINSB8
,
5675 ALPHA_BUILTIN_MINUW4
,
5676 ALPHA_BUILTIN_MINSW4
,
5677 ALPHA_BUILTIN_MAXUB8
,
5678 ALPHA_BUILTIN_MAXSB8
,
5679 ALPHA_BUILTIN_MAXUW4
,
5680 ALPHA_BUILTIN_MAXSW4
,
5684 ALPHA_BUILTIN_UNPKBL
,
5685 ALPHA_BUILTIN_UNPKBW
,
5690 ALPHA_BUILTIN_CTPOP
,
5695 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
5696 CODE_FOR_builtin_cmpbge
,
5697 CODE_FOR_builtin_extbl
,
5698 CODE_FOR_builtin_extwl
,
5699 CODE_FOR_builtin_extll
,
5700 CODE_FOR_builtin_extql
,
5701 CODE_FOR_builtin_extwh
,
5702 CODE_FOR_builtin_extlh
,
5703 CODE_FOR_builtin_extqh
,
5704 CODE_FOR_builtin_insbl
,
5705 CODE_FOR_builtin_inswl
,
5706 CODE_FOR_builtin_insll
,
5707 CODE_FOR_builtin_insql
,
5708 CODE_FOR_builtin_inswh
,
5709 CODE_FOR_builtin_inslh
,
5710 CODE_FOR_builtin_insqh
,
5711 CODE_FOR_builtin_mskbl
,
5712 CODE_FOR_builtin_mskwl
,
5713 CODE_FOR_builtin_mskll
,
5714 CODE_FOR_builtin_mskql
,
5715 CODE_FOR_builtin_mskwh
,
5716 CODE_FOR_builtin_msklh
,
5717 CODE_FOR_builtin_mskqh
,
5718 CODE_FOR_umuldi3_highpart
,
5719 CODE_FOR_builtin_zap
,
5720 CODE_FOR_builtin_zapnot
,
5721 CODE_FOR_builtin_amask
,
5722 CODE_FOR_builtin_implver
,
5723 CODE_FOR_builtin_rpcc
,
5728 CODE_FOR_builtin_minub8
,
5729 CODE_FOR_builtin_minsb8
,
5730 CODE_FOR_builtin_minuw4
,
5731 CODE_FOR_builtin_minsw4
,
5732 CODE_FOR_builtin_maxub8
,
5733 CODE_FOR_builtin_maxsb8
,
5734 CODE_FOR_builtin_maxuw4
,
5735 CODE_FOR_builtin_maxsw4
,
5736 CODE_FOR_builtin_perr
,
5737 CODE_FOR_builtin_pklb
,
5738 CODE_FOR_builtin_pkwb
,
5739 CODE_FOR_builtin_unpkbl
,
5740 CODE_FOR_builtin_unpkbw
,
5743 CODE_FOR_builtin_cttz
,
5744 CODE_FOR_builtin_ctlz
,
5745 CODE_FOR_builtin_ctpop
5748 struct alpha_builtin_def
5751 enum alpha_builtin code
;
5752 unsigned int target_mask
;
5755 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
5756 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
5757 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
5760 static struct alpha_builtin_def
const one_arg_builtins
[] = {
5761 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
5762 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
5763 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
5764 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
5765 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
5766 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
5767 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
5768 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
5771 static struct alpha_builtin_def
const two_arg_builtins
[] = {
5772 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
5773 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
5774 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
5775 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
5776 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
5777 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
5778 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
5779 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
5780 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
5781 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
5782 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
5783 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
5784 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
5785 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
5786 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
5787 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
5788 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
5789 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
5790 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
5791 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
5792 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
5793 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
5794 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
5795 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
5796 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
5797 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
5798 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
5799 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
5800 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
5801 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
5802 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
5803 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
5804 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
5805 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
5809 alpha_init_builtins (void)
5811 const struct alpha_builtin_def
*p
;
5815 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
5817 p
= zero_arg_builtins
;
5818 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
5819 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
5820 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
5823 ftype
= build_function_type_list (long_integer_type_node
,
5824 long_integer_type_node
, NULL_TREE
);
5826 p
= one_arg_builtins
;
5827 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
5828 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
5829 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
5832 ftype
= build_function_type_list (long_integer_type_node
,
5833 long_integer_type_node
,
5834 long_integer_type_node
, NULL_TREE
);
5836 p
= two_arg_builtins
;
5837 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
5838 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
5839 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
5842 ftype
= build_function_type (ptr_type_node
, void_list_node
);
5843 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
5844 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
5847 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
5848 lang_hooks
.builtin_function ("__builtin_set_thread_pointer", ftype
,
5849 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
5853 /* Expand an expression EXP that calls a built-in function,
5854 with result going to TARGET if that's convenient
5855 (and in mode MODE if that's convenient).
5856 SUBTARGET may be used as the target for computing one of EXP's operands.
5857 IGNORE is nonzero if the value is to be ignored. */
5860 alpha_expand_builtin (tree exp
, rtx target
,
5861 rtx subtarget ATTRIBUTE_UNUSED
,
5862 enum machine_mode mode ATTRIBUTE_UNUSED
,
5863 int ignore ATTRIBUTE_UNUSED
)
5867 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
5868 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
5869 tree arglist
= TREE_OPERAND (exp
, 1);
5870 enum insn_code icode
;
5871 rtx op
[MAX_ARGS
], pat
;
5875 if (fcode
>= ALPHA_BUILTIN_max
)
5876 internal_error ("bad builtin fcode");
5877 icode
= code_for_builtin
[fcode
];
5879 internal_error ("bad builtin fcode");
5881 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
5883 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
5885 arglist
= TREE_CHAIN (arglist
), arity
++)
5887 const struct insn_operand_data
*insn_op
;
5889 tree arg
= TREE_VALUE (arglist
);
5890 if (arg
== error_mark_node
)
5892 if (arity
> MAX_ARGS
)
5895 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
5897 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
5899 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
5900 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
5905 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5907 || GET_MODE (target
) != tmode
5908 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5909 target
= gen_reg_rtx (tmode
);
5915 pat
= GEN_FCN (icode
) (target
);
5919 pat
= GEN_FCN (icode
) (target
, op
[0]);
5921 pat
= GEN_FCN (icode
) (op
[0]);
5924 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
5939 /* This page contains routines that are used to determine what the function
5940 prologue and epilogue code will do and write them out. */
5942 /* Compute the size of the save area in the stack. */
5944 /* These variables are used for communication between the following functions.
5945 They indicate various things about the current function being compiled
5946 that are used to tell what kind of prologue, epilogue and procedure
5947 descriptor to generate. */
5949 /* Nonzero if we need a stack procedure. */
5950 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
5951 static enum alpha_procedure_types alpha_procedure_type
;
5953 /* Register number (either FP or SP) that is used to unwind the frame. */
5954 static int vms_unwind_regno
;
5956 /* Register number used to save FP. We need not have one for RA since
5957 we don't modify it for register procedures. This is only defined
5958 for register frame procedures. */
5959 static int vms_save_fp_regno
;
5961 /* Register number used to reference objects off our PV. */
5962 static int vms_base_regno
;
5964 /* Compute register masks for saved registers. */
5967 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
5969 unsigned long imask
= 0;
5970 unsigned long fmask
= 0;
5973 /* When outputting a thunk, we don't have valid register life info,
5974 but assemble_start_function wants to output .frame and .mask
5976 if (current_function_is_thunk
)
5983 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
5984 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
5986 /* One for every register we have to save. */
5987 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5988 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
5989 && regs_ever_live
[i
] && i
!= REG_RA
5990 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
5993 imask
|= (1UL << i
);
5995 fmask
|= (1UL << (i
- 32));
5998 /* We need to restore these for the handler. */
5999 if (current_function_calls_eh_return
)
6003 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6004 if (regno
== INVALID_REGNUM
)
6006 imask
|= 1UL << regno
;
6010 /* If any register spilled, then spill the return address also. */
6011 /* ??? This is required by the Digital stack unwind specification
6012 and isn't needed if we're doing Dwarf2 unwinding. */
6013 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6014 imask
|= (1UL << REG_RA
);
6021 alpha_sa_size (void)
6023 unsigned long mask
[2];
6027 alpha_sa_mask (&mask
[0], &mask
[1]);
6029 if (TARGET_ABI_UNICOSMK
)
6031 if (mask
[0] || mask
[1])
6036 for (j
= 0; j
< 2; ++j
)
6037 for (i
= 0; i
< 32; ++i
)
6038 if ((mask
[j
] >> i
) & 1)
6042 if (TARGET_ABI_UNICOSMK
)
6044 /* We might not need to generate a frame if we don't make any calls
6045 (including calls to __T3E_MISMATCH if this is a vararg function),
6046 don't have any local variables which require stack slots, don't
6047 use alloca and have not determined that we need a frame for other
6050 alpha_procedure_type
6051 = (sa_size
|| get_frame_size() != 0
6052 || current_function_outgoing_args_size
6053 || current_function_stdarg
|| current_function_calls_alloca
6054 || frame_pointer_needed
)
6055 ? PT_STACK
: PT_REGISTER
;
6057 /* Always reserve space for saving callee-saved registers if we
6058 need a frame as required by the calling convention. */
6059 if (alpha_procedure_type
== PT_STACK
)
6062 else if (TARGET_ABI_OPEN_VMS
)
6064 /* Start by assuming we can use a register procedure if we don't
6065 make any calls (REG_RA not used) or need to save any
6066 registers and a stack procedure if we do. */
6067 if ((mask
[0] >> REG_RA
) & 1)
6068 alpha_procedure_type
= PT_STACK
;
6069 else if (get_frame_size() != 0)
6070 alpha_procedure_type
= PT_REGISTER
;
6072 alpha_procedure_type
= PT_NULL
;
6074 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6075 made the final decision on stack procedure vs register procedure. */
6076 if (alpha_procedure_type
== PT_STACK
)
6079 /* Decide whether to refer to objects off our PV via FP or PV.
6080 If we need FP for something else or if we receive a nonlocal
6081 goto (which expects PV to contain the value), we must use PV.
6082 Otherwise, start by assuming we can use FP. */
6085 = (frame_pointer_needed
6086 || current_function_has_nonlocal_label
6087 || alpha_procedure_type
== PT_STACK
6088 || current_function_outgoing_args_size
)
6089 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6091 /* If we want to copy PV into FP, we need to find some register
6092 in which to save FP. */
6094 vms_save_fp_regno
= -1;
6095 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6096 for (i
= 0; i
< 32; i
++)
6097 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6098 vms_save_fp_regno
= i
;
6100 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6101 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6102 else if (alpha_procedure_type
== PT_NULL
)
6103 vms_base_regno
= REG_PV
;
6105 /* Stack unwinding should be done via FP unless we use it for PV. */
6106 vms_unwind_regno
= (vms_base_regno
== REG_PV
6107 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6109 /* If this is a stack procedure, allow space for saving FP and RA. */
6110 if (alpha_procedure_type
== PT_STACK
)
6115 /* Our size must be even (multiple of 16 bytes). */
6123 /* Define the offset between two registers, one to be eliminated,
6124 and the other its replacement, at the start of a routine. */
6127 alpha_initial_elimination_offset (unsigned int from
,
6128 unsigned int to ATTRIBUTE_UNUSED
)
6132 ret
= alpha_sa_size ();
6133 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
6135 if (from
== FRAME_POINTER_REGNUM
)
6137 else if (from
== ARG_POINTER_REGNUM
)
6138 ret
+= (ALPHA_ROUND (get_frame_size ()
6139 + current_function_pretend_args_size
)
6140 - current_function_pretend_args_size
);
6148 alpha_pv_save_size (void)
6151 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6155 alpha_using_fp (void)
6158 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6161 #if TARGET_ABI_OPEN_VMS
6163 const struct attribute_spec vms_attribute_table
[] =
6165 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6166 { "overlaid", 0, 0, true, false, false, NULL
},
6167 { "global", 0, 0, true, false, false, NULL
},
6168 { "initialize", 0, 0, true, false, false, NULL
},
6169 { NULL
, 0, 0, false, false, false, NULL
}
6175 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6177 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
6181 alpha_find_lo_sum_using_gp (rtx insn
)
6183 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
6187 alpha_does_function_need_gp (void)
6191 /* The GP being variable is an OSF abi thing. */
6192 if (! TARGET_ABI_OSF
)
6195 /* We need the gp to load the address of __mcount. */
6196 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6199 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6200 if (current_function_is_thunk
)
6203 /* The nonlocal receiver pattern assumes that the gp is valid for
6204 the nested function. Reasonable because it's almost always set
6205 correctly already. For the cases where that's wrong, make sure
6206 the nested function loads its gp on entry. */
6207 if (current_function_has_nonlocal_goto
)
6210 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6211 Even if we are a static function, we still need to do this in case
6212 our address is taken and passed to something like qsort. */
6214 push_topmost_sequence ();
6215 insn
= get_insns ();
6216 pop_topmost_sequence ();
6218 for (; insn
; insn
= NEXT_INSN (insn
))
6220 && GET_CODE (PATTERN (insn
)) != USE
6221 && GET_CODE (PATTERN (insn
)) != CLOBBER
6222 && get_attr_usegp (insn
))
6229 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6233 set_frame_related_p (void)
6235 rtx seq
= get_insns ();
6246 while (insn
!= NULL_RTX
)
6248 RTX_FRAME_RELATED_P (insn
) = 1;
6249 insn
= NEXT_INSN (insn
);
6251 seq
= emit_insn (seq
);
6255 seq
= emit_insn (seq
);
6256 RTX_FRAME_RELATED_P (seq
) = 1;
6261 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6263 /* Generates a store with the proper unwind info attached. VALUE is
6264 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
6265 contains SP+FRAME_BIAS, and that is the unwind info that should be
6266 generated. If FRAME_REG != VALUE, then VALUE is being stored on
6267 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
6270 emit_frame_store_1 (rtx value
, rtx base_reg
, HOST_WIDE_INT frame_bias
,
6271 HOST_WIDE_INT base_ofs
, rtx frame_reg
)
6273 rtx addr
, mem
, insn
;
6275 addr
= plus_constant (base_reg
, base_ofs
);
6276 mem
= gen_rtx_MEM (DImode
, addr
);
6277 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6279 insn
= emit_move_insn (mem
, value
);
6280 RTX_FRAME_RELATED_P (insn
) = 1;
6282 if (frame_bias
|| value
!= frame_reg
)
6286 addr
= plus_constant (stack_pointer_rtx
, frame_bias
+ base_ofs
);
6287 mem
= gen_rtx_MEM (DImode
, addr
);
6291 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6292 gen_rtx_SET (VOIDmode
, mem
, frame_reg
),
6298 emit_frame_store (unsigned int regno
, rtx base_reg
,
6299 HOST_WIDE_INT frame_bias
, HOST_WIDE_INT base_ofs
)
6301 rtx reg
= gen_rtx_REG (DImode
, regno
);
6302 emit_frame_store_1 (reg
, base_reg
, frame_bias
, base_ofs
, reg
);
6305 /* Write function prologue. */
6307 /* On vms we have two kinds of functions:
6309 - stack frame (PROC_STACK)
6310 these are 'normal' functions with local vars and which are
6311 calling other functions
6312 - register frame (PROC_REGISTER)
6313 keeps all data in registers, needs no stack
6315 We must pass this to the assembler so it can generate the
6316 proper pdsc (procedure descriptor)
6317 This is done with the '.pdesc' command.
6319 On not-vms, we don't really differentiate between the two, as we can
6320 simply allocate stack without saving registers. */
6323 alpha_expand_prologue (void)
6325 /* Registers to save. */
6326 unsigned long imask
= 0;
6327 unsigned long fmask
= 0;
6328 /* Stack space needed for pushing registers clobbered by us. */
6329 HOST_WIDE_INT sa_size
;
6330 /* Complete stack size needed. */
6331 HOST_WIDE_INT frame_size
;
6332 /* Offset from base reg to register save area. */
6333 HOST_WIDE_INT reg_offset
;
6337 sa_size
= alpha_sa_size ();
6339 frame_size
= get_frame_size ();
6340 if (TARGET_ABI_OPEN_VMS
)
6341 frame_size
= ALPHA_ROUND (sa_size
6342 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6344 + current_function_pretend_args_size
);
6345 else if (TARGET_ABI_UNICOSMK
)
6346 /* We have to allocate space for the DSIB if we generate a frame. */
6347 frame_size
= ALPHA_ROUND (sa_size
6348 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6349 + ALPHA_ROUND (frame_size
6350 + current_function_outgoing_args_size
);
6352 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6354 + ALPHA_ROUND (frame_size
6355 + current_function_pretend_args_size
));
6357 if (TARGET_ABI_OPEN_VMS
)
6360 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6362 alpha_sa_mask (&imask
, &fmask
);
6364 /* Emit an insn to reload GP, if needed. */
6367 alpha_function_needs_gp
= alpha_does_function_need_gp ();
6368 if (alpha_function_needs_gp
)
6369 emit_insn (gen_prologue_ldgp ());
6372 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6373 the call to mcount ourselves, rather than having the linker do it
6374 magically in response to -pg. Since _mcount has special linkage,
6375 don't represent the call as a call. */
6376 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6377 emit_insn (gen_prologue_mcount ());
6379 if (TARGET_ABI_UNICOSMK
)
6380 unicosmk_gen_dsib (&imask
);
6382 /* Adjust the stack by the frame size. If the frame size is > 4096
6383 bytes, we need to be sure we probe somewhere in the first and last
6384 4096 bytes (we can probably get away without the latter test) and
6385 every 8192 bytes in between. If the frame size is > 32768, we
6386 do this in a loop. Otherwise, we generate the explicit probe
6389 Note that we are only allowed to adjust sp once in the prologue. */
6391 if (frame_size
<= 32768)
6393 if (frame_size
> 4096)
6398 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
6401 while ((probed
+= 8192) < frame_size
);
6403 /* We only have to do this probe if we aren't saving registers. */
6404 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
6405 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
6408 if (frame_size
!= 0)
6409 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6410 GEN_INT (TARGET_ABI_UNICOSMK
6416 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6417 number of 8192 byte blocks to probe. We then probe each block
6418 in the loop and then set SP to the proper location. If the
6419 amount remaining is > 4096, we have to do one more probe if we
6420 are not saving any registers. */
6422 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
6423 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
6424 rtx ptr
= gen_rtx_REG (DImode
, 22);
6425 rtx count
= gen_rtx_REG (DImode
, 23);
6428 emit_move_insn (count
, GEN_INT (blocks
));
6429 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
6430 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
6432 /* Because of the difficulty in emitting a new basic block this
6433 late in the compilation, generate the loop as a single insn. */
6434 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
6436 if (leftover
> 4096 && sa_size
== 0)
6438 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
6439 MEM_VOLATILE_P (last
) = 1;
6440 emit_move_insn (last
, const0_rtx
);
6443 if (TARGET_ABI_WINDOWS_NT
)
6445 /* For NT stack unwind (done by 'reverse execution'), it's
6446 not OK to take the result of a loop, even though the value
6447 is already in ptr, so we reload it via a single operation
6448 and subtract it to sp.
6450 Yes, that's correct -- we have to reload the whole constant
6451 into a temporary via ldah+lda then subtract from sp. */
6453 HOST_WIDE_INT lo
, hi
;
6454 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6455 hi
= frame_size
- lo
;
6457 emit_move_insn (ptr
, GEN_INT (hi
));
6458 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
6459 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6464 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
6465 GEN_INT (-leftover
)));
6468 /* This alternative is special, because the DWARF code cannot
6469 possibly intuit through the loop above. So we invent this
6470 note it looks at instead. */
6471 RTX_FRAME_RELATED_P (seq
) = 1;
6473 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6474 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6475 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
6476 GEN_INT (TARGET_ABI_UNICOSMK
6482 if (!TARGET_ABI_UNICOSMK
)
6484 HOST_WIDE_INT sa_bias
= 0;
6486 /* Cope with very large offsets to the register save area. */
6487 sa_reg
= stack_pointer_rtx
;
6488 if (reg_offset
+ sa_size
> 0x8000)
6490 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6493 if (low
+ sa_size
<= 0x8000)
6494 sa_bias
= reg_offset
- low
, reg_offset
= low
;
6496 sa_bias
= reg_offset
, reg_offset
= 0;
6498 sa_reg
= gen_rtx_REG (DImode
, 24);
6499 sa_bias_rtx
= GEN_INT (sa_bias
);
6501 if (add_operand (sa_bias_rtx
, DImode
))
6502 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_bias_rtx
));
6505 emit_move_insn (sa_reg
, sa_bias_rtx
);
6506 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_reg
));
6510 /* Save regs in stack order. Beginning with VMS PV. */
6511 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6512 emit_frame_store (REG_PV
, stack_pointer_rtx
, 0, 0);
6514 /* Save register RA next. */
6515 if (imask
& (1UL << REG_RA
))
6517 emit_frame_store (REG_RA
, sa_reg
, sa_bias
, reg_offset
);
6518 imask
&= ~(1UL << REG_RA
);
6522 /* Now save any other registers required to be saved. */
6523 for (i
= 0; i
< 31; i
++)
6524 if (imask
& (1UL << i
))
6526 emit_frame_store (i
, sa_reg
, sa_bias
, reg_offset
);
6530 for (i
= 0; i
< 31; i
++)
6531 if (fmask
& (1UL << i
))
6533 emit_frame_store (i
+32, sa_reg
, sa_bias
, reg_offset
);
6537 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6539 /* The standard frame on the T3E includes space for saving registers.
6540 We just have to use it. We don't have to save the return address and
6541 the old frame pointer here - they are saved in the DSIB. */
6544 for (i
= 9; i
< 15; i
++)
6545 if (imask
& (1UL << i
))
6547 emit_frame_store (i
, hard_frame_pointer_rtx
, 0, reg_offset
);
6550 for (i
= 2; i
< 10; i
++)
6551 if (fmask
& (1UL << i
))
6553 emit_frame_store (i
+32, hard_frame_pointer_rtx
, 0, reg_offset
);
6558 if (TARGET_ABI_OPEN_VMS
)
6560 if (alpha_procedure_type
== PT_REGISTER
)
6561 /* Register frame procedures save the fp.
6562 ?? Ought to have a dwarf2 save for this. */
6563 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
6564 hard_frame_pointer_rtx
);
6566 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
6567 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
6568 gen_rtx_REG (DImode
, REG_PV
)));
6570 if (alpha_procedure_type
!= PT_NULL
6571 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6572 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6574 /* If we have to allocate space for outgoing args, do it now. */
6575 if (current_function_outgoing_args_size
!= 0)
6578 = emit_move_insn (stack_pointer_rtx
,
6580 (hard_frame_pointer_rtx
,
6582 (current_function_outgoing_args_size
))));
6584 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
6585 if ! frame_pointer_needed. Setting the bit will change the CFA
6586 computation rule to use sp again, which would be wrong if we had
6587 frame_pointer_needed, as this means sp might move unpredictably
6591 frame_pointer_needed
6592 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
6594 current_function_outgoing_args_size != 0
6595 => alpha_procedure_type != PT_NULL,
6597 so when we are not setting the bit here, we are guaranteed to
6598 have emitted an FRP frame pointer update just before. */
6599 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
6602 else if (!TARGET_ABI_UNICOSMK
)
6604 /* If we need a frame pointer, set it from the stack pointer. */
6605 if (frame_pointer_needed
)
6607 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
6608 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6610 /* This must always be the last instruction in the
6611 prologue, thus we emit a special move + clobber. */
6612 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
6613 stack_pointer_rtx
, sa_reg
)));
6617 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
6618 the prologue, for exception handling reasons, we cannot do this for
6619 any insn that might fault. We could prevent this for mems with a
6620 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
6621 have to prevent all such scheduling with a blockage.
6623 Linux, on the other hand, never bothered to implement OSF/1's
6624 exception handling, and so doesn't care about such things. Anyone
6625 planning to use dwarf2 frame-unwind info can also omit the blockage. */
6627 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
6628 emit_insn (gen_blockage ());
6631 /* Count the number of .file directives, so that .loc is up to date. */
6632 int num_source_filenames
= 0;
6634 /* Output the textual info surrounding the prologue. */
6637 alpha_start_function (FILE *file
, const char *fnname
,
6638 tree decl ATTRIBUTE_UNUSED
)
6640 unsigned long imask
= 0;
6641 unsigned long fmask
= 0;
6642 /* Stack space needed for pushing registers clobbered by us. */
6643 HOST_WIDE_INT sa_size
;
6644 /* Complete stack size needed. */
6645 unsigned HOST_WIDE_INT frame_size
;
6646 /* Offset from base reg to register save area. */
6647 HOST_WIDE_INT reg_offset
;
6648 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
6651 /* Don't emit an extern directive for functions defined in the same file. */
6652 if (TARGET_ABI_UNICOSMK
)
6655 name_tree
= get_identifier (fnname
);
6656 TREE_ASM_WRITTEN (name_tree
) = 1;
6659 alpha_fnname
= fnname
;
6660 sa_size
= alpha_sa_size ();
6662 frame_size
= get_frame_size ();
6663 if (TARGET_ABI_OPEN_VMS
)
6664 frame_size
= ALPHA_ROUND (sa_size
6665 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6667 + current_function_pretend_args_size
);
6668 else if (TARGET_ABI_UNICOSMK
)
6669 frame_size
= ALPHA_ROUND (sa_size
6670 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6671 + ALPHA_ROUND (frame_size
6672 + current_function_outgoing_args_size
);
6674 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6676 + ALPHA_ROUND (frame_size
6677 + current_function_pretend_args_size
));
6679 if (TARGET_ABI_OPEN_VMS
)
6682 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6684 alpha_sa_mask (&imask
, &fmask
);
6686 /* Ecoff can handle multiple .file directives, so put out file and lineno.
6687 We have to do that before the .ent directive as we cannot switch
6688 files within procedures with native ecoff because line numbers are
6689 linked to procedure descriptors.
6690 Outputting the lineno helps debugging of one line functions as they
6691 would otherwise get no line number at all. Please note that we would
6692 like to put out last_linenum from final.c, but it is not accessible. */
6694 if (write_symbols
== SDB_DEBUG
)
6696 #ifdef ASM_OUTPUT_SOURCE_FILENAME
6697 ASM_OUTPUT_SOURCE_FILENAME (file
,
6698 DECL_SOURCE_FILE (current_function_decl
));
6700 #ifdef SDB_OUTPUT_SOURCE_LINE
6701 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
6702 SDB_OUTPUT_SOURCE_LINE (file
,
6703 DECL_SOURCE_LINE (current_function_decl
));
6707 /* Issue function start and label. */
6708 if (TARGET_ABI_OPEN_VMS
6709 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
6711 fputs ("\t.ent ", file
);
6712 assemble_name (file
, fnname
);
6715 /* If the function needs GP, we'll write the "..ng" label there.
6716 Otherwise, do it here. */
6718 && ! alpha_function_needs_gp
6719 && ! current_function_is_thunk
)
6722 assemble_name (file
, fnname
);
6723 fputs ("..ng:\n", file
);
6727 strcpy (entry_label
, fnname
);
6728 if (TARGET_ABI_OPEN_VMS
)
6729 strcat (entry_label
, "..en");
6731 /* For public functions, the label must be globalized by appending an
6732 additional colon. */
6733 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
6734 strcat (entry_label
, ":");
6736 ASM_OUTPUT_LABEL (file
, entry_label
);
6737 inside_function
= TRUE
;
6739 if (TARGET_ABI_OPEN_VMS
)
6740 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
6742 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
6743 && !flag_inhibit_size_directive
)
6745 /* Set flags in procedure descriptor to request IEEE-conformant
6746 math-library routines. The value we set it to is PDSC_EXC_IEEE
6747 (/usr/include/pdsc.h). */
6748 fputs ("\t.eflag 48\n", file
);
6751 /* Set up offsets to alpha virtual arg/local debugging pointer. */
6752 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
6753 alpha_arg_offset
= -frame_size
+ 48;
6755 /* Describe our frame. If the frame size is larger than an integer,
6756 print it as zero to avoid an assembler error. We won't be
6757 properly describing such a frame, but that's the best we can do. */
6758 if (TARGET_ABI_UNICOSMK
)
6760 else if (TARGET_ABI_OPEN_VMS
)
6761 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
6762 HOST_WIDE_INT_PRINT_DEC
"\n",
6764 frame_size
>= (1UL << 31) ? 0 : frame_size
,
6766 else if (!flag_inhibit_size_directive
)
6767 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
6768 (frame_pointer_needed
6769 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
6770 frame_size
>= (1UL << 31) ? 0 : frame_size
,
6771 current_function_pretend_args_size
);
6773 /* Describe which registers were spilled. */
6774 if (TARGET_ABI_UNICOSMK
)
6776 else if (TARGET_ABI_OPEN_VMS
)
6779 /* ??? Does VMS care if mask contains ra? The old code didn't
6780 set it, so I don't here. */
6781 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
6783 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
6784 if (alpha_procedure_type
== PT_REGISTER
)
6785 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
6787 else if (!flag_inhibit_size_directive
)
6791 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
6792 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
6794 for (i
= 0; i
< 32; ++i
)
6795 if (imask
& (1UL << i
))
6800 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
6801 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
6804 #if TARGET_ABI_OPEN_VMS
6805 /* Ifdef'ed cause link_section are only available then. */
6806 readonly_data_section ();
6807 fprintf (file
, "\t.align 3\n");
6808 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
6809 fputs ("\t.ascii \"", file
);
6810 assemble_name (file
, fnname
);
6811 fputs ("\\0\"\n", file
);
6812 alpha_need_linkage (fnname
, 1);
6817 /* Emit the .prologue note at the scheduled end of the prologue. */
6820 alpha_output_function_end_prologue (FILE *file
)
6822 if (TARGET_ABI_UNICOSMK
)
6824 else if (TARGET_ABI_OPEN_VMS
)
6825 fputs ("\t.prologue\n", file
);
6826 else if (TARGET_ABI_WINDOWS_NT
)
6827 fputs ("\t.prologue 0\n", file
);
6828 else if (!flag_inhibit_size_directive
)
6829 fprintf (file
, "\t.prologue %d\n",
6830 alpha_function_needs_gp
|| current_function_is_thunk
);
6833 /* Write function epilogue. */
6835 /* ??? At some point we will want to support full unwind, and so will
6836 need to mark the epilogue as well. At the moment, we just confuse
6839 #define FRP(exp) exp
6842 alpha_expand_epilogue (void)
6844 /* Registers to save. */
6845 unsigned long imask
= 0;
6846 unsigned long fmask
= 0;
6847 /* Stack space needed for pushing registers clobbered by us. */
6848 HOST_WIDE_INT sa_size
;
6849 /* Complete stack size needed. */
6850 HOST_WIDE_INT frame_size
;
6851 /* Offset from base reg to register save area. */
6852 HOST_WIDE_INT reg_offset
;
6853 int fp_is_frame_pointer
, fp_offset
;
6854 rtx sa_reg
, sa_reg_exp
= NULL
;
6855 rtx sp_adj1
, sp_adj2
, mem
;
6859 sa_size
= alpha_sa_size ();
6861 frame_size
= get_frame_size ();
6862 if (TARGET_ABI_OPEN_VMS
)
6863 frame_size
= ALPHA_ROUND (sa_size
6864 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6866 + current_function_pretend_args_size
);
6867 else if (TARGET_ABI_UNICOSMK
)
6868 frame_size
= ALPHA_ROUND (sa_size
6869 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6870 + ALPHA_ROUND (frame_size
6871 + current_function_outgoing_args_size
);
6873 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6875 + ALPHA_ROUND (frame_size
6876 + current_function_pretend_args_size
));
6878 if (TARGET_ABI_OPEN_VMS
)
6880 if (alpha_procedure_type
== PT_STACK
)
6886 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6888 alpha_sa_mask (&imask
, &fmask
);
6891 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6892 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
6894 sa_reg
= stack_pointer_rtx
;
6896 if (current_function_calls_eh_return
)
6897 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
6901 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
6903 /* If we have a frame pointer, restore SP from it. */
6904 if ((TARGET_ABI_OPEN_VMS
6905 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6906 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
6907 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
6909 /* Cope with very large offsets to the register save area. */
6910 if (reg_offset
+ sa_size
> 0x8000)
6912 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6915 if (low
+ sa_size
<= 0x8000)
6916 bias
= reg_offset
- low
, reg_offset
= low
;
6918 bias
= reg_offset
, reg_offset
= 0;
6920 sa_reg
= gen_rtx_REG (DImode
, 22);
6921 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
6923 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
6926 /* Restore registers in order, excepting a true frame pointer. */
6928 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6930 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6931 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6934 imask
&= ~(1UL << REG_RA
);
6936 for (i
= 0; i
< 31; ++i
)
6937 if (imask
& (1UL << i
))
6939 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
6940 fp_offset
= reg_offset
;
6943 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
6944 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6945 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6950 for (i
= 0; i
< 31; ++i
)
6951 if (fmask
& (1UL << i
))
6953 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
6954 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6955 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6959 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6961 /* Restore callee-saved general-purpose registers. */
6965 for (i
= 9; i
< 15; i
++)
6966 if (imask
& (1UL << i
))
6968 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6970 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6971 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6975 for (i
= 2; i
< 10; i
++)
6976 if (fmask
& (1UL << i
))
6978 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
6980 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6981 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6985 /* Restore the return address from the DSIB. */
6987 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
6988 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6989 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6992 if (frame_size
|| eh_ofs
)
6994 sp_adj1
= stack_pointer_rtx
;
6998 sp_adj1
= gen_rtx_REG (DImode
, 23);
6999 emit_move_insn (sp_adj1
,
7000 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7003 /* If the stack size is large, begin computation into a temporary
7004 register so as not to interfere with a potential fp restore,
7005 which must be consecutive with an SP restore. */
7006 if (frame_size
< 32768
7007 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7008 sp_adj2
= GEN_INT (frame_size
);
7009 else if (TARGET_ABI_UNICOSMK
)
7011 sp_adj1
= gen_rtx_REG (DImode
, 23);
7012 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7013 sp_adj2
= const0_rtx
;
7015 else if (frame_size
< 0x40007fffL
)
7017 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7019 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7020 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7024 sp_adj1
= gen_rtx_REG (DImode
, 23);
7025 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7027 sp_adj2
= GEN_INT (low
);
7031 rtx tmp
= gen_rtx_REG (DImode
, 23);
7032 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7035 /* We can't drop new things to memory this late, afaik,
7036 so build it up by pieces. */
7037 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7038 -(frame_size
< 0)));
7044 /* From now on, things must be in order. So emit blockages. */
7046 /* Restore the frame pointer. */
7047 if (TARGET_ABI_UNICOSMK
)
7049 emit_insn (gen_blockage ());
7050 mem
= gen_rtx_MEM (DImode
,
7051 plus_constant (hard_frame_pointer_rtx
, -16));
7052 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7053 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7055 else if (fp_is_frame_pointer
)
7057 emit_insn (gen_blockage ());
7058 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7059 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7060 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7062 else if (TARGET_ABI_OPEN_VMS
)
7064 emit_insn (gen_blockage ());
7065 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7066 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7069 /* Restore the stack pointer. */
7070 emit_insn (gen_blockage ());
7071 if (sp_adj2
== const0_rtx
)
7072 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7074 FRP (emit_move_insn (stack_pointer_rtx
,
7075 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7079 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7081 emit_insn (gen_blockage ());
7082 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7083 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7085 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7087 /* Decrement the frame pointer if the function does not have a
7090 emit_insn (gen_blockage ());
7091 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7092 hard_frame_pointer_rtx
, constm1_rtx
)));
7097 /* Output the rest of the textual info surrounding the epilogue. */
7100 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
7102 #if TARGET_ABI_OPEN_VMS
7103 alpha_write_linkage (file
, fnname
, decl
);
7106 /* End the function. */
7107 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7109 fputs ("\t.end ", file
);
7110 assemble_name (file
, fnname
);
7113 inside_function
= FALSE
;
7115 /* Output jump tables and the static subroutine information block. */
7116 if (TARGET_ABI_UNICOSMK
)
7118 unicosmk_output_ssib (file
, fnname
);
7119 unicosmk_output_deferred_case_vectors (file
);
7124 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7126 In order to avoid the hordes of differences between generated code
7127 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7128 lots of code loading up large constants, generate rtl and emit it
7129 instead of going straight to text.
7131 Not sure why this idea hasn't been explored before... */
7134 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7135 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
7138 HOST_WIDE_INT hi
, lo
;
7139 rtx
this, insn
, funexp
;
7141 reset_block_changes ();
7143 /* We always require a valid GP. */
7144 emit_insn (gen_prologue_ldgp ());
7145 emit_note (NOTE_INSN_PROLOGUE_END
);
7147 /* Find the "this" pointer. If the function returns a structure,
7148 the structure return pointer is in $16. */
7149 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7150 this = gen_rtx_REG (Pmode
, 17);
7152 this = gen_rtx_REG (Pmode
, 16);
7154 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7155 entire constant for the add. */
7156 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7157 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7158 if (hi
+ lo
== delta
)
7161 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7163 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7167 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7168 delta
, -(delta
< 0));
7169 emit_insn (gen_adddi3 (this, this, tmp
));
7172 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7177 tmp
= gen_rtx_REG (Pmode
, 0);
7178 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
7180 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
7181 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7182 if (hi
+ lo
== vcall_offset
)
7185 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
7189 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
7190 vcall_offset
, -(vcall_offset
< 0));
7191 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
7195 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
7198 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
7200 emit_insn (gen_adddi3 (this, this, tmp
));
7203 /* Generate a tail call to the target function. */
7204 if (! TREE_USED (function
))
7206 assemble_external (function
);
7207 TREE_USED (function
) = 1;
7209 funexp
= XEXP (DECL_RTL (function
), 0);
7210 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7211 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7212 SIBLING_CALL_P (insn
) = 1;
7214 /* Run just enough of rest_of_compilation to get the insns emitted.
7215 There's not really enough bulk here to make other passes such as
7216 instruction scheduling worth while. Note that use_thunk calls
7217 assemble_start_function and assemble_end_function. */
7218 insn
= get_insns ();
7219 insn_locators_initialize ();
7220 shorten_branches (insn
);
7221 final_start_function (insn
, file
, 1);
7222 final (insn
, file
, 1, 0);
7223 final_end_function ();
7225 #endif /* TARGET_ABI_OSF */
7227 /* Debugging support. */
7231 /* Count the number of sdb related labels are generated (to find block
7232 start and end boundaries). */
7234 int sdb_label_count
= 0;
7236 /* Name of the file containing the current function. */
7238 static const char *current_function_file
= "";
7240 /* Offsets to alpha virtual arg/local debugging pointers. */
7242 long alpha_arg_offset
;
7243 long alpha_auto_offset
;
7245 /* Emit a new filename to a stream. */
7248 alpha_output_filename (FILE *stream
, const char *name
)
7250 static int first_time
= TRUE
;
7255 ++num_source_filenames
;
7256 current_function_file
= name
;
7257 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7258 output_quoted_string (stream
, name
);
7259 fprintf (stream
, "\n");
7260 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7261 fprintf (stream
, "\t#@stabs\n");
7264 else if (write_symbols
== DBX_DEBUG
)
7265 /* dbxout.c will emit an appropriate .stabs directive. */
7268 else if (name
!= current_function_file
7269 && strcmp (name
, current_function_file
) != 0)
7271 if (inside_function
&& ! TARGET_GAS
)
7272 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7275 ++num_source_filenames
;
7276 current_function_file
= name
;
7277 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7280 output_quoted_string (stream
, name
);
7281 fprintf (stream
, "\n");
7285 /* Structure to show the current status of registers and memory. */
7287 struct shadow_summary
7290 unsigned int i
: 31; /* Mask of int regs */
7291 unsigned int fp
: 31; /* Mask of fp regs */
7292 unsigned int mem
: 1; /* mem == imem | fpmem */
7296 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7297 to the summary structure. SET is nonzero if the insn is setting the
7298 object, otherwise zero. */
7301 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
7303 const char *format_ptr
;
7309 switch (GET_CODE (x
))
7311 /* ??? Note that this case would be incorrect if the Alpha had a
7312 ZERO_EXTRACT in SET_DEST. */
7314 summarize_insn (SET_SRC (x
), sum
, 0);
7315 summarize_insn (SET_DEST (x
), sum
, 1);
7319 summarize_insn (XEXP (x
, 0), sum
, 1);
7323 summarize_insn (XEXP (x
, 0), sum
, 0);
7327 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
7328 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
7332 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
7333 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
7337 summarize_insn (SUBREG_REG (x
), sum
, 0);
7342 int regno
= REGNO (x
);
7343 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
7345 if (regno
== 31 || regno
== 63)
7351 sum
->defd
.i
|= mask
;
7353 sum
->defd
.fp
|= mask
;
7358 sum
->used
.i
|= mask
;
7360 sum
->used
.fp
|= mask
;
7371 /* Find the regs used in memory address computation: */
7372 summarize_insn (XEXP (x
, 0), sum
, 0);
7375 case CONST_INT
: case CONST_DOUBLE
:
7376 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
7377 case SCRATCH
: case ASM_INPUT
:
7380 /* Handle common unary and binary ops for efficiency. */
7381 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
7382 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
7383 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
7384 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
7385 case NE
: case EQ
: case GE
: case GT
: case LE
:
7386 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
7387 summarize_insn (XEXP (x
, 0), sum
, 0);
7388 summarize_insn (XEXP (x
, 1), sum
, 0);
7391 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
7392 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
7393 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
7394 case SQRT
: case FFS
:
7395 summarize_insn (XEXP (x
, 0), sum
, 0);
7399 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
7400 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7401 switch (format_ptr
[i
])
7404 summarize_insn (XEXP (x
, i
), sum
, 0);
7408 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7409 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
7421 /* Ensure a sufficient number of `trapb' insns are in the code when
7422 the user requests code with a trap precision of functions or
7425 In naive mode, when the user requests a trap-precision of
7426 "instruction", a trapb is needed after every instruction that may
7427 generate a trap. This ensures that the code is resumption safe but
7430 When optimizations are turned on, we delay issuing a trapb as long
7431 as possible. In this context, a trap shadow is the sequence of
7432 instructions that starts with a (potentially) trap generating
7433 instruction and extends to the next trapb or call_pal instruction
7434 (but GCC never generates call_pal by itself). We can delay (and
7435 therefore sometimes omit) a trapb subject to the following
7438 (a) On entry to the trap shadow, if any Alpha register or memory
7439 location contains a value that is used as an operand value by some
7440 instruction in the trap shadow (live on entry), then no instruction
7441 in the trap shadow may modify the register or memory location.
7443 (b) Within the trap shadow, the computation of the base register
7444 for a memory load or store instruction may not involve using the
7445 result of an instruction that might generate an UNPREDICTABLE
7448 (c) Within the trap shadow, no register may be used more than once
7449 as a destination register. (This is to make life easier for the
7452 (d) The trap shadow may not include any branch instructions. */
7455 alpha_handle_trap_shadows (void)
7457 struct shadow_summary shadow
;
7458 int trap_pending
, exception_nesting
;
7462 exception_nesting
= 0;
7465 shadow
.used
.mem
= 0;
7466 shadow
.defd
= shadow
.used
;
7468 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
7470 if (GET_CODE (i
) == NOTE
)
7472 switch (NOTE_LINE_NUMBER (i
))
7474 case NOTE_INSN_EH_REGION_BEG
:
7475 exception_nesting
++;
7480 case NOTE_INSN_EH_REGION_END
:
7481 exception_nesting
--;
7486 case NOTE_INSN_EPILOGUE_BEG
:
7487 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
7492 else if (trap_pending
)
7494 if (alpha_tp
== ALPHA_TP_FUNC
)
7496 if (GET_CODE (i
) == JUMP_INSN
7497 && GET_CODE (PATTERN (i
)) == RETURN
)
7500 else if (alpha_tp
== ALPHA_TP_INSN
)
7504 struct shadow_summary sum
;
7509 sum
.defd
= sum
.used
;
7511 switch (GET_CODE (i
))
7514 /* Annoyingly, get_attr_trap will abort on these. */
7515 if (GET_CODE (PATTERN (i
)) == USE
7516 || GET_CODE (PATTERN (i
)) == CLOBBER
)
7519 summarize_insn (PATTERN (i
), &sum
, 0);
7521 if ((sum
.defd
.i
& shadow
.defd
.i
)
7522 || (sum
.defd
.fp
& shadow
.defd
.fp
))
7524 /* (c) would be violated */
7528 /* Combine shadow with summary of current insn: */
7529 shadow
.used
.i
|= sum
.used
.i
;
7530 shadow
.used
.fp
|= sum
.used
.fp
;
7531 shadow
.used
.mem
|= sum
.used
.mem
;
7532 shadow
.defd
.i
|= sum
.defd
.i
;
7533 shadow
.defd
.fp
|= sum
.defd
.fp
;
7534 shadow
.defd
.mem
|= sum
.defd
.mem
;
7536 if ((sum
.defd
.i
& shadow
.used
.i
)
7537 || (sum
.defd
.fp
& shadow
.used
.fp
)
7538 || (sum
.defd
.mem
& shadow
.used
.mem
))
7540 /* (a) would be violated (also takes care of (b)) */
7541 if (get_attr_trap (i
) == TRAP_YES
7542 && ((sum
.defd
.i
& sum
.used
.i
)
7543 || (sum
.defd
.fp
& sum
.used
.fp
)))
7562 n
= emit_insn_before (gen_trapb (), i
);
7563 PUT_MODE (n
, TImode
);
7564 PUT_MODE (i
, TImode
);
7568 shadow
.used
.mem
= 0;
7569 shadow
.defd
= shadow
.used
;
7574 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
7575 && GET_CODE (i
) == INSN
7576 && GET_CODE (PATTERN (i
)) != USE
7577 && GET_CODE (PATTERN (i
)) != CLOBBER
7578 && get_attr_trap (i
) == TRAP_YES
)
7580 if (optimize
&& !trap_pending
)
7581 summarize_insn (PATTERN (i
), &shadow
, 0);
7587 /* Alpha can only issue instruction groups simultaneously if they are
7588 suitably aligned. This is very processor-specific. */
7590 enum alphaev4_pipe
{
7597 enum alphaev5_pipe
{
7608 static enum alphaev4_pipe
7609 alphaev4_insn_pipe (rtx insn
)
7611 if (recog_memoized (insn
) < 0)
7613 if (get_attr_length (insn
) != 4)
7616 switch (get_attr_type (insn
))
7650 static enum alphaev5_pipe
7651 alphaev5_insn_pipe (rtx insn
)
7653 if (recog_memoized (insn
) < 0)
7655 if (get_attr_length (insn
) != 4)
7658 switch (get_attr_type (insn
))
7699 /* IN_USE is a mask of the slots currently filled within the insn group.
7700 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
7701 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
7703 LEN is, of course, the length of the group in bytes. */
7706 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
7713 || GET_CODE (PATTERN (insn
)) == CLOBBER
7714 || GET_CODE (PATTERN (insn
)) == USE
)
7719 enum alphaev4_pipe pipe
;
7721 pipe
= alphaev4_insn_pipe (insn
);
7725 /* Force complex instructions to start new groups. */
7729 /* If this is a completely unrecognized insn, its an asm.
7730 We don't know how long it is, so record length as -1 to
7731 signal a needed realignment. */
7732 if (recog_memoized (insn
) < 0)
7735 len
= get_attr_length (insn
);
7739 if (in_use
& EV4_IB0
)
7741 if (in_use
& EV4_IB1
)
7746 in_use
|= EV4_IB0
| EV4_IBX
;
7750 if (in_use
& EV4_IB0
)
7752 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
7760 if (in_use
& EV4_IB1
)
7770 /* Haifa doesn't do well scheduling branches. */
7771 if (GET_CODE (insn
) == JUMP_INSN
)
7775 insn
= next_nonnote_insn (insn
);
7777 if (!insn
|| ! INSN_P (insn
))
7780 /* Let Haifa tell us where it thinks insn group boundaries are. */
7781 if (GET_MODE (insn
) == TImode
)
7784 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7789 insn
= next_nonnote_insn (insn
);
7797 /* IN_USE is a mask of the slots currently filled within the insn group.
7798 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
7799 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
7801 LEN is, of course, the length of the group in bytes. */
7804 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
7811 || GET_CODE (PATTERN (insn
)) == CLOBBER
7812 || GET_CODE (PATTERN (insn
)) == USE
)
7817 enum alphaev5_pipe pipe
;
7819 pipe
= alphaev5_insn_pipe (insn
);
7823 /* Force complex instructions to start new groups. */
7827 /* If this is a completely unrecognized insn, its an asm.
7828 We don't know how long it is, so record length as -1 to
7829 signal a needed realignment. */
7830 if (recog_memoized (insn
) < 0)
7833 len
= get_attr_length (insn
);
7836 /* ??? Most of the places below, we would like to abort, as
7837 it would indicate an error either in Haifa, or in the
7838 scheduling description. Unfortunately, Haifa never
7839 schedules the last instruction of the BB, so we don't
7840 have an accurate TI bit to go off. */
7842 if (in_use
& EV5_E0
)
7844 if (in_use
& EV5_E1
)
7849 in_use
|= EV5_E0
| EV5_E01
;
7853 if (in_use
& EV5_E0
)
7855 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
7863 if (in_use
& EV5_E1
)
7869 if (in_use
& EV5_FA
)
7871 if (in_use
& EV5_FM
)
7876 in_use
|= EV5_FA
| EV5_FAM
;
7880 if (in_use
& EV5_FA
)
7886 if (in_use
& EV5_FM
)
7899 /* Haifa doesn't do well scheduling branches. */
7900 /* ??? If this is predicted not-taken, slotting continues, except
7901 that no more IBR, FBR, or JSR insns may be slotted. */
7902 if (GET_CODE (insn
) == JUMP_INSN
)
7906 insn
= next_nonnote_insn (insn
);
7908 if (!insn
|| ! INSN_P (insn
))
7911 /* Let Haifa tell us where it thinks insn group boundaries are. */
7912 if (GET_MODE (insn
) == TImode
)
7915 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7920 insn
= next_nonnote_insn (insn
);
7929 alphaev4_next_nop (int *pin_use
)
7931 int in_use
= *pin_use
;
7934 if (!(in_use
& EV4_IB0
))
7939 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
7944 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
7957 alphaev5_next_nop (int *pin_use
)
7959 int in_use
= *pin_use
;
7962 if (!(in_use
& EV5_E1
))
7967 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
7972 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
7984 /* The instruction group alignment main loop. */
7987 alpha_align_insns (unsigned int max_align
,
7988 rtx (*next_group
) (rtx
, int *, int *),
7989 rtx (*next_nop
) (int *))
7991 /* ALIGN is the known alignment for the insn group. */
7993 /* OFS is the offset of the current insn in the insn group. */
7995 int prev_in_use
, in_use
, len
;
7998 /* Let shorten branches care for assigning alignments to code labels. */
7999 shorten_branches (get_insns ());
8001 if (align_functions
< 4)
8003 else if ((unsigned int) align_functions
< max_align
)
8004 align
= align_functions
;
8008 ofs
= prev_in_use
= 0;
8010 if (GET_CODE (i
) == NOTE
)
8011 i
= next_nonnote_insn (i
);
8015 next
= (*next_group
) (i
, &in_use
, &len
);
8017 /* When we see a label, resync alignment etc. */
8018 if (GET_CODE (i
) == CODE_LABEL
)
8020 unsigned int new_align
= 1 << label_to_alignment (i
);
8022 if (new_align
>= align
)
8024 align
= new_align
< max_align
? new_align
: max_align
;
8028 else if (ofs
& (new_align
-1))
8029 ofs
= (ofs
| (new_align
-1)) + 1;
8034 /* Handle complex instructions special. */
8035 else if (in_use
== 0)
8037 /* Asms will have length < 0. This is a signal that we have
8038 lost alignment knowledge. Assume, however, that the asm
8039 will not mis-align instructions. */
8048 /* If the known alignment is smaller than the recognized insn group,
8049 realign the output. */
8050 else if ((int) align
< len
)
8052 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8055 where
= prev
= prev_nonnote_insn (i
);
8056 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8059 /* Can't realign between a call and its gp reload. */
8060 if (! (TARGET_EXPLICIT_RELOCS
8061 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8063 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8064 align
= 1 << new_log_align
;
8069 /* If the group won't fit in the same INT16 as the previous,
8070 we need to add padding to keep the group together. Rather
8071 than simply leaving the insn filling to the assembler, we
8072 can make use of the knowledge of what sorts of instructions
8073 were issued in the previous group to make sure that all of
8074 the added nops are really free. */
8075 else if (ofs
+ len
> (int) align
)
8077 int nop_count
= (align
- ofs
) / 4;
8080 /* Insert nops before labels, branches, and calls to truly merge
8081 the execution of the nops with the previous instruction group. */
8082 where
= prev_nonnote_insn (i
);
8085 if (GET_CODE (where
) == CODE_LABEL
)
8087 rtx where2
= prev_nonnote_insn (where
);
8088 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8091 else if (GET_CODE (where
) == INSN
)
8098 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8099 while (--nop_count
);
8103 ofs
= (ofs
+ len
) & (align
- 1);
8104 prev_in_use
= in_use
;
8109 /* Machine dependent reorg pass. */
8114 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8115 alpha_handle_trap_shadows ();
8117 /* Due to the number of extra trapb insns, don't bother fixing up
8118 alignment when trap precision is instruction. Moreover, we can
8119 only do our job when sched2 is run. */
8120 if (optimize
&& !optimize_size
8121 && alpha_tp
!= ALPHA_TP_INSN
8122 && flag_schedule_insns_after_reload
)
8124 if (alpha_cpu
== PROCESSOR_EV4
)
8125 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
8126 else if (alpha_cpu
== PROCESSOR_EV5
)
8127 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
8131 #if !TARGET_ABI_UNICOSMK
8138 alpha_file_start (void)
8140 #ifdef OBJECT_FORMAT_ELF
8141 /* If emitting dwarf2 debug information, we cannot generate a .file
8142 directive to start the file, as it will conflict with dwarf2out
8143 file numbers. So it's only useful when emitting mdebug output. */
8144 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
8147 default_file_start ();
8149 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
8152 fputs ("\t.set noreorder\n", asm_out_file
);
8153 fputs ("\t.set volatile\n", asm_out_file
);
8154 if (!TARGET_ABI_OPEN_VMS
)
8155 fputs ("\t.set noat\n", asm_out_file
);
8156 if (TARGET_EXPLICIT_RELOCS
)
8157 fputs ("\t.set nomacro\n", asm_out_file
);
8158 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
8159 fprintf (asm_out_file
,
8161 TARGET_CPU_EV6
? "ev6"
8163 ? (TARGET_MAX
? "pca56" : TARGET_BWX
? "ev56" : "ev5")
8168 #ifdef OBJECT_FORMAT_ELF
8170 /* Switch to the section to which we should output X. The only thing
8171 special we do here is to honor small data. */
8174 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
8175 unsigned HOST_WIDE_INT align
)
8177 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8178 /* ??? Consider using mergeable sdata sections. */
8181 default_elf_select_rtx_section (mode
, x
, align
);
8184 #endif /* OBJECT_FORMAT_ELF */
8186 /* Structure to collect function names for final output in link section. */
8187 /* Note that items marked with GTY can't be ifdef'ed out. */
8189 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8190 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
8192 struct alpha_links
GTY(())
8196 enum links_kind lkind
;
8197 enum reloc_kind rkind
;
8200 struct alpha_funcs
GTY(())
8203 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8207 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8208 splay_tree alpha_links_tree
;
8209 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
8210 splay_tree alpha_funcs_tree
;
8212 static GTY(()) int alpha_funcs_num
;
8214 #if TARGET_ABI_OPEN_VMS
8216 /* Return the VMS argument type corresponding to MODE. */
8219 alpha_arg_type (enum machine_mode mode
)
8224 return TARGET_FLOAT_VAX
? FF
: FS
;
8226 return TARGET_FLOAT_VAX
? FD
: FT
;
8232 /* Return an rtx for an integer representing the VMS Argument Information
8236 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
8238 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8241 for (i
= 0; i
< 6; i
++)
8242 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8244 return GEN_INT (regval
);
8247 /* Make (or fake) .linkage entry for function call.
8249 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8251 Return an SYMBOL_REF rtx for the linkage. */
8254 alpha_need_linkage (const char *name
, int is_local
)
8256 splay_tree_node node
;
8257 struct alpha_links
*al
;
8264 struct alpha_funcs
*cfaf
;
8266 if (!alpha_funcs_tree
)
8267 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
8268 splay_tree_compare_pointers
);
8270 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
8273 cfaf
->num
= ++alpha_funcs_num
;
8275 splay_tree_insert (alpha_funcs_tree
,
8276 (splay_tree_key
) current_function_decl
,
8277 (splay_tree_value
) cfaf
);
8280 if (alpha_links_tree
)
8282 /* Is this name already defined? */
8284 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
8287 al
= (struct alpha_links
*) node
->value
;
8290 /* Defined here but external assumed. */
8291 if (al
->lkind
== KIND_EXTERN
)
8292 al
->lkind
= KIND_LOCAL
;
8296 /* Used here but unused assumed. */
8297 if (al
->lkind
== KIND_UNUSED
)
8298 al
->lkind
= KIND_LOCAL
;
8304 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
8306 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
8307 name
= ggc_strdup (name
);
8309 /* Assume external if no definition. */
8310 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
8312 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8313 get_identifier (name
);
8315 /* Construct a SYMBOL_REF for us to call. */
8317 size_t name_len
= strlen (name
);
8318 char *linksym
= alloca (name_len
+ 6);
8320 memcpy (linksym
+ 1, name
, name_len
);
8321 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
8322 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
8323 ggc_alloc_string (linksym
, name_len
+ 5));
8326 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
8327 (splay_tree_value
) al
);
8333 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
8335 splay_tree_node cfunnode
;
8336 struct alpha_funcs
*cfaf
;
8337 struct alpha_links
*al
;
8338 const char *name
= XSTR (linkage
, 0);
8340 cfaf
= (struct alpha_funcs
*) 0;
8341 al
= (struct alpha_links
*) 0;
8343 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
8344 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
8348 splay_tree_node lnode
;
8350 /* Is this name already defined? */
8352 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
8354 al
= (struct alpha_links
*) lnode
->value
;
8357 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
8365 splay_tree_node node
= 0;
8366 struct alpha_links
*anl
;
8371 name_len
= strlen (name
);
8373 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
8374 al
->num
= cfaf
->num
;
8376 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
8379 anl
= (struct alpha_links
*) node
->value
;
8380 al
->lkind
= anl
->lkind
;
8383 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
8384 buflen
= strlen (buf
);
8385 linksym
= alloca (buflen
+ 1);
8386 memcpy (linksym
, buf
, buflen
+ 1);
8388 al
->linkage
= gen_rtx_SYMBOL_REF
8389 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
8391 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
8392 (splay_tree_value
) al
);
8396 al
->rkind
= KIND_CODEADDR
;
8398 al
->rkind
= KIND_LINKAGE
;
8401 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
8407 alpha_write_one_linkage (splay_tree_node node
, void *data
)
8409 const char *const name
= (const char *) node
->key
;
8410 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
8411 FILE *stream
= (FILE *) data
;
8413 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
8414 if (link
->rkind
== KIND_CODEADDR
)
8416 if (link
->lkind
== KIND_LOCAL
)
8418 /* Local and used */
8419 fprintf (stream
, "\t.quad %s..en\n", name
);
8423 /* External and used, request code address. */
8424 fprintf (stream
, "\t.code_address %s\n", name
);
8429 if (link
->lkind
== KIND_LOCAL
)
8431 /* Local and used, build linkage pair. */
8432 fprintf (stream
, "\t.quad %s..en\n", name
);
8433 fprintf (stream
, "\t.quad %s\n", name
);
8437 /* External and used, request linkage pair. */
8438 fprintf (stream
, "\t.linkage %s\n", name
);
8446 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
8448 splay_tree_node node
;
8449 struct alpha_funcs
*func
;
8452 fprintf (stream
, "\t.align 3\n");
8453 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
8454 func
= (struct alpha_funcs
*) node
->value
;
8456 fputs ("\t.name ", stream
);
8457 assemble_name (stream
, funname
);
8458 fputs ("..na\n", stream
);
8459 ASM_OUTPUT_LABEL (stream
, funname
);
8460 fprintf (stream
, "\t.pdesc ");
8461 assemble_name (stream
, funname
);
8462 fprintf (stream
, "..en,%s\n",
8463 alpha_procedure_type
== PT_STACK
? "stack"
8464 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
8468 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
8469 /* splay_tree_delete (func->links); */
8473 /* Given a decl, a section name, and whether the decl initializer
8474 has relocs, choose attributes for the section. */
8476 #define SECTION_VMS_OVERLAY SECTION_FORGET
8477 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
8478 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
8481 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
8483 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8485 if (decl
&& DECL_ATTRIBUTES (decl
)
8486 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
8487 flags
|= SECTION_VMS_OVERLAY
;
8488 if (decl
&& DECL_ATTRIBUTES (decl
)
8489 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
8490 flags
|= SECTION_VMS_GLOBAL
;
8491 if (decl
&& DECL_ATTRIBUTES (decl
)
8492 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
8493 flags
|= SECTION_VMS_INITIALIZE
;
8498 /* Switch to an arbitrary section NAME with attributes as specified
8499 by FLAGS. ALIGN specifies any known alignment requirements for
8500 the section; 0 if the default should be used. */
8503 vms_asm_named_section (const char *name
, unsigned int flags
,
8504 tree decl ATTRIBUTE_UNUSED
)
8506 fputc ('\n', asm_out_file
);
8507 fprintf (asm_out_file
, ".section\t%s", name
);
8509 if (flags
& SECTION_VMS_OVERLAY
)
8510 fprintf (asm_out_file
, ",OVR");
8511 if (flags
& SECTION_VMS_GLOBAL
)
8512 fprintf (asm_out_file
, ",GBL");
8513 if (flags
& SECTION_VMS_INITIALIZE
)
8514 fprintf (asm_out_file
, ",NOMOD");
8515 if (flags
& SECTION_DEBUG
)
8516 fprintf (asm_out_file
, ",NOWRT");
8518 fputc ('\n', asm_out_file
);
8521 /* Record an element in the table of global constructors. SYMBOL is
8522 a SYMBOL_REF of the function to be called; PRIORITY is a number
8523 between 0 and MAX_INIT_PRIORITY.
8525 Differs from default_ctors_section_asm_out_constructor in that the
8526 width of the .ctors entry is always 64 bits, rather than the 32 bits
8527 used by a normal pointer. */
8530 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
8533 assemble_align (BITS_PER_WORD
);
8534 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8538 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
8541 assemble_align (BITS_PER_WORD
);
8542 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8547 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
8548 int is_local ATTRIBUTE_UNUSED
)
8554 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
8555 tree cfundecl ATTRIBUTE_UNUSED
,
8556 int lflag ATTRIBUTE_UNUSED
,
8557 int rflag ATTRIBUTE_UNUSED
)
8562 #endif /* TARGET_ABI_OPEN_VMS */
8564 #if TARGET_ABI_UNICOSMK
8566 /* This evaluates to true if we do not know how to pass TYPE solely in
8567 registers. This is the case for all arguments that do not fit in two
8571 unicosmk_must_pass_in_stack (enum machine_mode mode
, tree type
)
8576 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8578 if (TREE_ADDRESSABLE (type
))
8581 return ALPHA_ARG_SIZE (mode
, type
, 0) > 2;
8584 /* Define the offset between two registers, one to be eliminated, and the
8585 other its replacement, at the start of a routine. */
8588 unicosmk_initial_elimination_offset (int from
, int to
)
8592 fixed_size
= alpha_sa_size();
8593 if (fixed_size
!= 0)
8596 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8598 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8600 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8601 return (ALPHA_ROUND (current_function_outgoing_args_size
)
8602 + ALPHA_ROUND (get_frame_size()));
8603 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8604 return (ALPHA_ROUND (fixed_size
)
8605 + ALPHA_ROUND (get_frame_size()
8606 + current_function_outgoing_args_size
));
8611 /* Output the module name for .ident and .end directives. We have to strip
8612 directories and add make sure that the module name starts with a letter
8616 unicosmk_output_module_name (FILE *file
)
8618 const char *name
= lbasename (main_input_filename
);
8619 unsigned len
= strlen (name
);
8620 char *clean_name
= alloca (len
+ 2);
8621 char *ptr
= clean_name
;
8623 /* CAM only accepts module names that start with a letter or '$'. We
8624 prefix the module name with a '$' if necessary. */
8626 if (!ISALPHA (*name
))
8628 memcpy (ptr
, name
, len
+ 1);
8629 clean_symbol_name (clean_name
);
8630 fputs (clean_name
, file
);
8633 /* Output the definition of a common variable. */
8636 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
8639 printf ("T3E__: common %s\n", name
);
8642 fputs("\t.endp\n\n\t.psect ", file
);
8643 assemble_name(file
, name
);
8644 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
8645 fprintf(file
, "\t.byte\t0:%d\n", size
);
8647 /* Mark the symbol as defined in this module. */
8648 name_tree
= get_identifier (name
);
8649 TREE_ASM_WRITTEN (name_tree
) = 1;
8652 #define SECTION_PUBLIC SECTION_MACH_DEP
8653 #define SECTION_MAIN (SECTION_PUBLIC << 1)
8654 static int current_section_align
;
8657 unicosmk_section_type_flags (tree decl
, const char *name
,
8658 int reloc ATTRIBUTE_UNUSED
)
8660 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8665 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8667 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8668 if (align_functions_log
> current_section_align
)
8669 current_section_align
= align_functions_log
;
8671 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
8672 flags
|= SECTION_MAIN
;
8675 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
8677 if (TREE_PUBLIC (decl
))
8678 flags
|= SECTION_PUBLIC
;
8683 /* Generate a section name for decl and associate it with the
8687 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
8695 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
8696 name
= default_strip_name_encoding (name
);
8697 len
= strlen (name
);
8699 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8703 /* It is essential that we prefix the section name here because
8704 otherwise the section names generated for constructors and
8705 destructors confuse collect2. */
8707 string
= alloca (len
+ 6);
8708 sprintf (string
, "code@%s", name
);
8709 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8711 else if (TREE_PUBLIC (decl
))
8712 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
8717 string
= alloca (len
+ 6);
8718 sprintf (string
, "data@%s", name
);
8719 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8723 /* Switch to an arbitrary section NAME with attributes as specified
8724 by FLAGS. ALIGN specifies any known alignment requirements for
8725 the section; 0 if the default should be used. */
8728 unicosmk_asm_named_section (const char *name
, unsigned int flags
,
8729 tree decl ATTRIBUTE_UNUSED
)
8733 /* Close the previous section. */
8735 fputs ("\t.endp\n\n", asm_out_file
);
8737 /* Find out what kind of section we are opening. */
8739 if (flags
& SECTION_MAIN
)
8740 fputs ("\t.start\tmain\n", asm_out_file
);
8742 if (flags
& SECTION_CODE
)
8744 else if (flags
& SECTION_PUBLIC
)
8749 if (current_section_align
!= 0)
8750 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
8751 current_section_align
, kind
);
8753 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
8757 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
8760 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
8761 unicosmk_unique_section (decl
, 0);
8764 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
8765 in code sections because .align fill unused space with zeroes. */
8768 unicosmk_output_align (FILE *file
, int align
)
8770 if (inside_function
)
8771 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
8773 fprintf (file
, "\t.align\t%d\n", align
);
8776 /* Add a case vector to the current function's list of deferred case
8777 vectors. Case vectors have to be put into a separate section because CAM
8778 does not allow data definitions in code sections. */
8781 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
8783 struct machine_function
*machine
= cfun
->machine
;
8785 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8786 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
8787 machine
->addr_list
);
8790 /* Output a case vector. */
8793 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
8795 rtx lab
= XEXP (vec
, 0);
8796 rtx body
= XEXP (vec
, 1);
8797 int vlen
= XVECLEN (body
, 0);
8800 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
8802 for (idx
= 0; idx
< vlen
; idx
++)
8804 ASM_OUTPUT_ADDR_VEC_ELT
8805 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8809 /* Output current function's deferred case vectors. */
8812 unicosmk_output_deferred_case_vectors (FILE *file
)
8814 struct machine_function
*machine
= cfun
->machine
;
8817 if (machine
->addr_list
== NULL_RTX
)
8821 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
8822 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
8825 /* Generate the name of the SSIB section for the current function. */
8827 #define SSIB_PREFIX "__SSIB_"
8828 #define SSIB_PREFIX_LEN 7
8831 unicosmk_ssib_name (void)
8833 /* This is ok since CAM won't be able to deal with names longer than that
8836 static char name
[256];
8842 x
= DECL_RTL (cfun
->decl
);
8843 if (GET_CODE (x
) != MEM
)
8846 if (GET_CODE (x
) != SYMBOL_REF
)
8848 fnname
= XSTR (x
, 0);
8850 len
= strlen (fnname
);
8851 if (len
+ SSIB_PREFIX_LEN
> 255)
8852 len
= 255 - SSIB_PREFIX_LEN
;
8854 strcpy (name
, SSIB_PREFIX
);
8855 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
8856 name
[len
+ SSIB_PREFIX_LEN
] = 0;
8861 /* Set up the dynamic subprogram information block (DSIB) and update the
8862 frame pointer register ($15) for subroutines which have a frame. If the
8863 subroutine doesn't have a frame, simply increment $15. */
8866 unicosmk_gen_dsib (unsigned long *imaskP
)
8868 if (alpha_procedure_type
== PT_STACK
)
8870 const char *ssib_name
;
8873 /* Allocate 64 bytes for the DSIB. */
8875 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8877 emit_insn (gen_blockage ());
8879 /* Save the return address. */
8881 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
8882 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8883 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
8884 (*imaskP
) &= ~(1UL << REG_RA
);
8886 /* Save the old frame pointer. */
8888 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
8889 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8890 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
8891 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
8893 emit_insn (gen_blockage ());
8895 /* Store the SSIB pointer. */
8897 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
8898 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
8899 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8901 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
8902 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
8903 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
8905 /* Save the CIW index. */
8907 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
8908 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8909 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
8911 emit_insn (gen_blockage ());
8913 /* Set the new frame pointer. */
8915 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8916 stack_pointer_rtx
, GEN_INT (64))));
8921 /* Increment the frame pointer register to indicate that we do not
8924 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8925 hard_frame_pointer_rtx
, const1_rtx
)));
8929 /* Output the static subroutine information block for the current
8933 unicosmk_output_ssib (FILE *file
, const char *fnname
)
8939 struct machine_function
*machine
= cfun
->machine
;
8942 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
8943 unicosmk_ssib_name ());
8945 /* Some required stuff and the function name length. */
8947 len
= strlen (fnname
);
8948 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
8951 ??? We don't do that yet. */
8953 fputs ("\t.quad\t0\n", file
);
8955 /* Function address. */
8957 fputs ("\t.quad\t", file
);
8958 assemble_name (file
, fnname
);
8961 fputs ("\t.quad\t0\n", file
);
8962 fputs ("\t.quad\t0\n", file
);
8965 ??? We do it the same way Cray CC does it but this could be
8968 for( i
= 0; i
< len
; i
++ )
8969 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
8970 if( (len
% 8) == 0 )
8971 fputs ("\t.quad\t0\n", file
);
8973 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
8975 /* All call information words used in the function. */
8977 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
8980 #if HOST_BITS_PER_WIDE_INT == 32
8981 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
8982 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
8984 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
8989 /* Add a call information word (CIW) to the list of the current function's
8990 CIWs and return its index.
8992 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
8995 unicosmk_add_call_info_word (rtx x
)
8998 struct machine_function
*machine
= cfun
->machine
;
9000 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9001 if (machine
->first_ciw
== NULL_RTX
)
9002 machine
->first_ciw
= node
;
9004 XEXP (machine
->last_ciw
, 1) = node
;
9006 machine
->last_ciw
= node
;
9007 ++machine
->ciw_count
;
9009 return GEN_INT (machine
->ciw_count
9010 + strlen (current_function_name ())/8 + 5);
9013 static char unicosmk_section_buf
[100];
9016 unicosmk_text_section (void)
9018 static int count
= 0;
9019 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9021 return unicosmk_section_buf
;
9025 unicosmk_data_section (void)
9027 static int count
= 1;
9028 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9030 return unicosmk_section_buf
;
9033 /* The Cray assembler doesn't accept extern declarations for symbols which
9034 are defined in the same file. We have to keep track of all global
9035 symbols which are referenced and/or defined in a source file and output
9036 extern declarations for those which are referenced but not defined at
9039 /* List of identifiers for which an extern declaration might have to be
9041 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9043 struct unicosmk_extern_list
9045 struct unicosmk_extern_list
*next
;
9049 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9051 /* Output extern declarations which are required for every asm file. */
9054 unicosmk_output_default_externs (FILE *file
)
9056 static const char *const externs
[] =
9057 { "__T3E_MISMATCH" };
9062 n
= ARRAY_SIZE (externs
);
9064 for (i
= 0; i
< n
; i
++)
9065 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9068 /* Output extern declarations for global symbols which are have been
9069 referenced but not defined. */
9072 unicosmk_output_externs (FILE *file
)
9074 struct unicosmk_extern_list
*p
;
9075 const char *real_name
;
9079 len
= strlen (user_label_prefix
);
9080 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9082 /* We have to strip the encoding and possibly remove user_label_prefix
9083 from the identifier in order to handle -fleading-underscore and
9084 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9085 real_name
= default_strip_name_encoding (p
->name
);
9086 if (len
&& p
->name
[0] == '*'
9087 && !memcmp (real_name
, user_label_prefix
, len
))
9090 name_tree
= get_identifier (real_name
);
9091 if (! TREE_ASM_WRITTEN (name_tree
))
9093 TREE_ASM_WRITTEN (name_tree
) = 1;
9094 fputs ("\t.extern\t", file
);
9095 assemble_name (file
, p
->name
);
9101 /* Record an extern. */
9104 unicosmk_add_extern (const char *name
)
9106 struct unicosmk_extern_list
*p
;
9108 p
= (struct unicosmk_extern_list
*)
9109 xmalloc (sizeof (struct unicosmk_extern_list
));
9110 p
->next
= unicosmk_extern_head
;
9112 unicosmk_extern_head
= p
;
9115 /* The Cray assembler generates incorrect code if identifiers which
9116 conflict with register names are used as instruction operands. We have
9117 to replace such identifiers with DEX expressions. */
9119 /* Structure to collect identifiers which have been replaced by DEX
9121 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9123 struct unicosmk_dex
{
9124 struct unicosmk_dex
*next
;
9128 /* List of identifiers which have been replaced by DEX expressions. The DEX
9129 number is determined by the position in the list. */
9131 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9133 /* The number of elements in the DEX list. */
9135 static int unicosmk_dex_count
= 0;
9137 /* Check if NAME must be replaced by a DEX expression. */
9140 unicosmk_special_name (const char *name
)
9148 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9154 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9157 return (name
[2] == '\0'
9158 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9161 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9165 /* Return the DEX number if X must be replaced by a DEX expression and 0
9169 unicosmk_need_dex (rtx x
)
9171 struct unicosmk_dex
*dex
;
9175 if (GET_CODE (x
) != SYMBOL_REF
)
9179 if (! unicosmk_special_name (name
))
9182 i
= unicosmk_dex_count
;
9183 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9185 if (! strcmp (name
, dex
->name
))
9190 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
9192 dex
->next
= unicosmk_dex_list
;
9193 unicosmk_dex_list
= dex
;
9195 ++unicosmk_dex_count
;
9196 return unicosmk_dex_count
;
9199 /* Output the DEX definitions for this file. */
9202 unicosmk_output_dex (FILE *file
)
9204 struct unicosmk_dex
*dex
;
9207 if (unicosmk_dex_list
== NULL
)
9210 fprintf (file
, "\t.dexstart\n");
9212 i
= unicosmk_dex_count
;
9213 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9215 fprintf (file
, "\tDEX (%d) = ", i
);
9216 assemble_name (file
, dex
->name
);
9221 fprintf (file
, "\t.dexend\n");
9224 /* Output text that to appear at the beginning of an assembler file. */
9227 unicosmk_file_start (void)
9231 fputs ("\t.ident\t", asm_out_file
);
9232 unicosmk_output_module_name (asm_out_file
);
9233 fputs ("\n\n", asm_out_file
);
9235 /* The Unicos/Mk assembler uses different register names. Instead of trying
9236 to support them, we simply use micro definitions. */
9238 /* CAM has different register names: rN for the integer register N and fN
9239 for the floating-point register N. Instead of trying to use these in
9240 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9243 for (i
= 0; i
< 32; ++i
)
9244 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
9246 for (i
= 0; i
< 32; ++i
)
9247 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
9249 putc ('\n', asm_out_file
);
9251 /* The .align directive fill unused space with zeroes which does not work
9252 in code sections. We define the macro 'gcc@code@align' which uses nops
9253 instead. Note that it assumes that code sections always have the
9254 biggest possible alignment since . refers to the current offset from
9255 the beginning of the section. */
9257 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
9258 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
9259 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
9260 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
9261 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
9262 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
9263 fputs ("\t.endr\n", asm_out_file
);
9264 fputs ("\t.endif\n", asm_out_file
);
9265 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
9267 /* Output extern declarations which should always be visible. */
9268 unicosmk_output_default_externs (asm_out_file
);
9270 /* Open a dummy section. We always need to be inside a section for the
9271 section-switching code to work correctly.
9272 ??? This should be a module id or something like that. I still have to
9273 figure out what the rules for those are. */
9274 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
9277 /* Output text to appear at the end of an assembler file. This includes all
9278 pending extern declarations and DEX expressions. */
9281 unicosmk_file_end (void)
9283 fputs ("\t.endp\n\n", asm_out_file
);
9285 /* Output all pending externs. */
9287 unicosmk_output_externs (asm_out_file
);
9289 /* Output dex definitions used for functions whose names conflict with
9292 unicosmk_output_dex (asm_out_file
);
9294 fputs ("\t.end\t", asm_out_file
);
9295 unicosmk_output_module_name (asm_out_file
);
9296 putc ('\n', asm_out_file
);
9302 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
9306 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
9310 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
9311 const char * fnname ATTRIBUTE_UNUSED
)
9315 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
9321 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
9326 #endif /* TARGET_ABI_UNICOSMK */
9329 alpha_init_libfuncs (void)
9331 if (TARGET_ABI_UNICOSMK
)
9333 /* Prevent gcc from generating calls to __divsi3. */
9334 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9335 set_optab_libfunc (udiv_optab
, SImode
, 0);
9337 /* Use the functions provided by the system library
9338 for DImode integer division. */
9339 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
9340 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
9342 else if (TARGET_ABI_OPEN_VMS
)
9344 /* Use the VMS runtime library functions for division and
9346 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
9347 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
9348 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
9349 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
9350 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
9351 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
9352 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
9353 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
9358 /* Initialize the GCC target structure. */
9359 #if TARGET_ABI_OPEN_VMS
9360 # undef TARGET_ATTRIBUTE_TABLE
9361 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
9362 # undef TARGET_SECTION_TYPE_FLAGS
9363 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
9366 #undef TARGET_IN_SMALL_DATA_P
9367 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
9369 #if TARGET_ABI_UNICOSMK
9370 # undef TARGET_INSERT_ATTRIBUTES
9371 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
9372 # undef TARGET_SECTION_TYPE_FLAGS
9373 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
9374 # undef TARGET_ASM_UNIQUE_SECTION
9375 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
9376 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
9377 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
9378 # undef TARGET_ASM_GLOBALIZE_LABEL
9379 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
9380 # undef TARGET_MUST_PASS_IN_STACK
9381 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
9384 #undef TARGET_ASM_ALIGNED_HI_OP
9385 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9386 #undef TARGET_ASM_ALIGNED_DI_OP
9387 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9389 /* Default unaligned ops are provided for ELF systems. To get unaligned
9390 data for non-ELF systems, we have to turn off auto alignment. */
9391 #ifndef OBJECT_FORMAT_ELF
9392 #undef TARGET_ASM_UNALIGNED_HI_OP
9393 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
9394 #undef TARGET_ASM_UNALIGNED_SI_OP
9395 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
9396 #undef TARGET_ASM_UNALIGNED_DI_OP
9397 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
9400 #ifdef OBJECT_FORMAT_ELF
9401 #undef TARGET_ASM_SELECT_RTX_SECTION
9402 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
9405 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
9406 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
9408 #undef TARGET_INIT_LIBFUNCS
9409 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
9411 #if TARGET_ABI_UNICOSMK
9412 #undef TARGET_ASM_FILE_START
9413 #define TARGET_ASM_FILE_START unicosmk_file_start
9414 #undef TARGET_ASM_FILE_END
9415 #define TARGET_ASM_FILE_END unicosmk_file_end
9417 #undef TARGET_ASM_FILE_START
9418 #define TARGET_ASM_FILE_START alpha_file_start
9419 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
9420 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
9423 #undef TARGET_SCHED_ADJUST_COST
9424 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
9425 #undef TARGET_SCHED_ISSUE_RATE
9426 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
9427 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9428 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
9429 alpha_multipass_dfa_lookahead
9431 #undef TARGET_HAVE_TLS
9432 #define TARGET_HAVE_TLS HAVE_AS_TLS
9434 #undef TARGET_INIT_BUILTINS
9435 #define TARGET_INIT_BUILTINS alpha_init_builtins
9436 #undef TARGET_EXPAND_BUILTIN
9437 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
9439 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9440 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
9441 #undef TARGET_CANNOT_COPY_INSN_P
9442 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
9443 #undef TARGET_CANNOT_FORCE_CONST_MEM
9444 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
9447 #undef TARGET_ASM_OUTPUT_MI_THUNK
9448 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
9449 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9450 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9453 #undef TARGET_RTX_COSTS
9454 #define TARGET_RTX_COSTS alpha_rtx_costs
9455 #undef TARGET_ADDRESS_COST
9456 #define TARGET_ADDRESS_COST hook_int_rtx_0
9458 #undef TARGET_MACHINE_DEPENDENT_REORG
9459 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
9461 #undef TARGET_PROMOTE_FUNCTION_ARGS
9462 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9463 #undef TARGET_PROMOTE_FUNCTION_RETURN
9464 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9465 #undef TARGET_PROMOTE_PROTOTYPES
9466 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
9467 #undef TARGET_RETURN_IN_MEMORY
9468 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
9469 #undef TARGET_PASS_BY_REFERENCE
9470 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
9471 #undef TARGET_SETUP_INCOMING_VARARGS
9472 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
9473 #undef TARGET_STRICT_ARGUMENT_NAMING
9474 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
9475 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
9476 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
9477 #undef TARGET_SPLIT_COMPLEX_ARG
9478 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
9479 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9480 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
9481 #undef TARGET_ARG_PARTIAL_BYTES
9482 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
9484 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9485 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
9486 #undef TARGET_VECTOR_MODE_SUPPORTED_P
9487 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
9489 #undef TARGET_BUILD_BUILTIN_VA_LIST
9490 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
9492 /* The Alpha architecture does not require sequential consistency. See
9493 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
9494 for an example of how it can be violated in practice. */
9495 #undef TARGET_RELAXED_ORDERING
9496 #define TARGET_RELAXED_ORDERING true
9498 struct gcc_target targetm
= TARGET_INITIALIZER
;
9501 #include "gt-alpha.h"