1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 /* Specify which cpu to schedule for. */
58 enum processor_type alpha_cpu
;
59 static const char * const alpha_cpu_name
[] =
64 /* Specify how accurate floating-point traps need to be. */
66 enum alpha_trap_precision alpha_tp
;
68 /* Specify the floating-point rounding mode. */
70 enum alpha_fp_rounding_mode alpha_fprm
;
72 /* Specify which things cause traps. */
74 enum alpha_fp_trap_mode alpha_fptm
;
76 /* Specify bit size of immediate TLS offsets. */
78 int alpha_tls_size
= 32;
80 /* Strings decoded into the above options. */
82 const char *alpha_cpu_string
; /* -mcpu= */
83 const char *alpha_tune_string
; /* -mtune= */
84 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
85 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
86 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
87 const char *alpha_mlat_string
; /* -mmemory-latency= */
88 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
90 /* Save information from a "cmpxx" operation until the branch or scc is
93 struct alpha_compare alpha_compare
;
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
98 static int inside_function
= FALSE
;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency
= 3;
104 /* Whether the function needs the GP. */
106 static int alpha_function_needs_gp
;
108 /* The alias set for prologue/epilogue register save/restore. */
110 static GTY(()) int alpha_sr_alias_set
;
112 /* The assembler name of the current function. */
114 static const char *alpha_fnname
;
116 /* The next explicit relocation sequence number. */
117 extern GTY(()) int alpha_next_sequence_number
;
118 int alpha_next_sequence_number
= 1;
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
122 extern GTY(()) int alpha_this_literal_sequence_number
;
123 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
124 int alpha_this_literal_sequence_number
;
125 int alpha_this_gpdisp_sequence_number
;
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
131 unsigned char fp_add
;
132 unsigned char fp_mult
;
133 unsigned char fp_div_sf
;
134 unsigned char fp_div_df
;
135 unsigned char int_mult_si
;
136 unsigned char int_mult_di
;
137 unsigned char int_shift
;
138 unsigned char int_cmov
;
141 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
144 COSTS_N_INSNS (6), /* fp_add */
145 COSTS_N_INSNS (6), /* fp_mult */
146 COSTS_N_INSNS (34), /* fp_div_sf */
147 COSTS_N_INSNS (63), /* fp_div_df */
148 COSTS_N_INSNS (23), /* int_mult_si */
149 COSTS_N_INSNS (23), /* int_mult_di */
150 COSTS_N_INSNS (2), /* int_shift */
151 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (15), /* fp_div_sf */
157 COSTS_N_INSNS (22), /* fp_div_df */
158 COSTS_N_INSNS (8), /* int_mult_si */
159 COSTS_N_INSNS (12), /* int_mult_di */
160 COSTS_N_INSNS (1) + 1, /* int_shift */
161 COSTS_N_INSNS (1), /* int_cmov */
164 COSTS_N_INSNS (4), /* fp_add */
165 COSTS_N_INSNS (4), /* fp_mult */
166 COSTS_N_INSNS (12), /* fp_div_sf */
167 COSTS_N_INSNS (15), /* fp_div_df */
168 COSTS_N_INSNS (7), /* int_mult_si */
169 COSTS_N_INSNS (7), /* int_mult_di */
170 COSTS_N_INSNS (1), /* int_shift */
171 COSTS_N_INSNS (2), /* int_cmov */
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
179 #define NUM_ARGS current_function_args_info
185 /* Declarations of static functions. */
186 static struct machine_function
*alpha_init_machine_status (void);
187 static rtx
alpha_emit_xfloating_compare (enum rtx_code
, rtx
, rtx
);
189 #if TARGET_ABI_OPEN_VMS
190 static void alpha_write_linkage (FILE *, const char *, tree
);
193 static void unicosmk_output_deferred_case_vectors (FILE *);
194 static void unicosmk_gen_dsib (unsigned long *);
195 static void unicosmk_output_ssib (FILE *, const char *);
196 static int unicosmk_need_dex (rtx
);
198 /* Parse target option strings. */
201 override_options (void)
204 static const struct cpu_table
{
205 const char *const name
;
206 const enum processor_type processor
;
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
211 { "ev4", PROCESSOR_EV4
, 0 },
212 { "ev45", PROCESSOR_EV4
, 0 },
213 { "21064", PROCESSOR_EV4
, 0 },
214 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
215 { "21164", PROCESSOR_EV5
, EV5_MASK
},
216 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
217 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
218 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
219 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
220 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
221 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
222 { "21264", PROCESSOR_EV6
, EV6_MASK
},
223 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
224 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
228 /* Unicos/Mk doesn't have shared libraries. */
229 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
231 warning ("-f%s ignored for Unicos/Mk (not supported)",
232 (flag_pic
> 1) ? "PIC" : "pic");
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
238 if (TARGET_ABI_UNICOSMK
)
239 alpha_fprm
= ALPHA_FPRM_DYN
;
241 alpha_fprm
= ALPHA_FPRM_NORM
;
243 alpha_tp
= ALPHA_TP_PROG
;
244 alpha_fptm
= ALPHA_FPTM_N
;
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
254 if (TARGET_ABI_UNICOSMK
)
255 warning ("-mieee not supported on Unicos/Mk");
258 alpha_tp
= ALPHA_TP_INSN
;
259 alpha_fptm
= ALPHA_FPTM_SU
;
263 if (TARGET_IEEE_WITH_INEXACT
)
265 if (TARGET_ABI_UNICOSMK
)
266 warning ("-mieee-with-inexact not supported on Unicos/Mk");
269 alpha_tp
= ALPHA_TP_INSN
;
270 alpha_fptm
= ALPHA_FPTM_SUI
;
276 if (! strcmp (alpha_tp_string
, "p"))
277 alpha_tp
= ALPHA_TP_PROG
;
278 else if (! strcmp (alpha_tp_string
, "f"))
279 alpha_tp
= ALPHA_TP_FUNC
;
280 else if (! strcmp (alpha_tp_string
, "i"))
281 alpha_tp
= ALPHA_TP_INSN
;
283 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
286 if (alpha_fprm_string
)
288 if (! strcmp (alpha_fprm_string
, "n"))
289 alpha_fprm
= ALPHA_FPRM_NORM
;
290 else if (! strcmp (alpha_fprm_string
, "m"))
291 alpha_fprm
= ALPHA_FPRM_MINF
;
292 else if (! strcmp (alpha_fprm_string
, "c"))
293 alpha_fprm
= ALPHA_FPRM_CHOP
;
294 else if (! strcmp (alpha_fprm_string
,"d"))
295 alpha_fprm
= ALPHA_FPRM_DYN
;
297 error ("bad value `%s' for -mfp-rounding-mode switch",
301 if (alpha_fptm_string
)
303 if (strcmp (alpha_fptm_string
, "n") == 0)
304 alpha_fptm
= ALPHA_FPTM_N
;
305 else if (strcmp (alpha_fptm_string
, "u") == 0)
306 alpha_fptm
= ALPHA_FPTM_U
;
307 else if (strcmp (alpha_fptm_string
, "su") == 0)
308 alpha_fptm
= ALPHA_FPTM_SU
;
309 else if (strcmp (alpha_fptm_string
, "sui") == 0)
310 alpha_fptm
= ALPHA_FPTM_SUI
;
312 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
315 if (alpha_tls_size_string
)
317 if (strcmp (alpha_tls_size_string
, "16") == 0)
319 else if (strcmp (alpha_tls_size_string
, "32") == 0)
321 else if (strcmp (alpha_tls_size_string
, "64") == 0)
324 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
328 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
329 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
331 if (alpha_cpu_string
)
333 for (i
= 0; cpu_table
[i
].name
; i
++)
334 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
336 alpha_cpu
= cpu_table
[i
].processor
;
337 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
338 | MASK_CPU_EV5
| MASK_CPU_EV6
);
339 target_flags
|= cpu_table
[i
].flags
;
342 if (! cpu_table
[i
].name
)
343 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
346 if (alpha_tune_string
)
348 for (i
= 0; cpu_table
[i
].name
; i
++)
349 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
351 alpha_cpu
= cpu_table
[i
].processor
;
354 if (! cpu_table
[i
].name
)
355 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
358 /* Do some sanity checks on the above options. */
360 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
362 warning ("trap mode not supported on Unicos/Mk");
363 alpha_fptm
= ALPHA_FPTM_N
;
366 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
367 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
369 warning ("fp software completion requires -mtrap-precision=i");
370 alpha_tp
= ALPHA_TP_INSN
;
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
378 alpha_tp
= ALPHA_TP_PROG
;
381 if (TARGET_FLOAT_VAX
)
383 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
385 warning ("rounding mode not supported for VAX floats");
386 alpha_fprm
= ALPHA_FPRM_NORM
;
388 if (alpha_fptm
== ALPHA_FPTM_SUI
)
390 warning ("trap mode not supported for VAX floats");
391 alpha_fptm
= ALPHA_FPTM_SU
;
399 if (!alpha_mlat_string
)
400 alpha_mlat_string
= "L1";
402 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
403 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
405 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
406 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
407 && alpha_mlat_string
[2] == '\0')
409 static int const cache_latency
[][4] =
411 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
412 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
413 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
416 lat
= alpha_mlat_string
[1] - '0';
417 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
419 warning ("L%d cache latency unknown for %s",
420 lat
, alpha_cpu_name
[alpha_cpu
]);
424 lat
= cache_latency
[alpha_cpu
][lat
-1];
426 else if (! strcmp (alpha_mlat_string
, "main"))
428 /* Most current memories have about 370ns latency. This is
429 a reasonable guess for a fast cpu. */
434 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
438 alpha_memory_latency
= lat
;
441 /* Default the definition of "small data" to 8 bytes. */
445 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
447 target_flags
|= MASK_SMALL_DATA
;
448 else if (flag_pic
== 2)
449 target_flags
&= ~MASK_SMALL_DATA
;
451 /* Align labels and loops for optimal branching. */
452 /* ??? Kludge these by not doing anything if we don't optimize and also if
453 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
454 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
456 if (align_loops
<= 0)
458 if (align_jumps
<= 0)
461 if (align_functions
<= 0)
462 align_functions
= 16;
464 /* Acquire a unique set number for our register saves and restores. */
465 alpha_sr_alias_set
= new_alias_set ();
467 /* Register variables and functions with the garbage collector. */
469 /* Set up function hooks. */
470 init_machine_status
= alpha_init_machine_status
;
472 /* Tell the compiler when we're using VAX floating point. */
473 if (TARGET_FLOAT_VAX
)
475 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
476 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
477 REAL_MODE_FORMAT (TFmode
) = NULL
;
481 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
484 zap_mask (HOST_WIDE_INT value
)
488 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
490 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
496 /* Returns 1 if OP is either the constant zero or a register. If a
497 register, it must be in the proper mode unless MODE is VOIDmode. */
500 reg_or_0_operand (rtx op
, enum machine_mode mode
)
502 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
505 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
509 reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
511 return ((GET_CODE (op
) == CONST_INT
512 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
513 || register_operand (op
, mode
));
517 /* Return 1 if OP is an 8-bit constant or any register. */
520 reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
522 return ((GET_CODE (op
) == CONST_INT
523 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
524 || register_operand (op
, mode
));
527 /* Return 1 if OP is a constant or any register. */
530 reg_or_const_int_operand (rtx op
, enum machine_mode mode
)
532 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
535 /* Return 1 if OP is an 8-bit constant. */
538 cint8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
540 return ((GET_CODE (op
) == CONST_INT
541 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
544 /* Return 1 if the operand is a valid second operand to an add insn. */
547 add_operand (rtx op
, enum machine_mode mode
)
549 if (GET_CODE (op
) == CONST_INT
)
550 /* Constraints I, J, O and P are covered by K. */
551 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
552 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
554 return register_operand (op
, mode
);
557 /* Return 1 if the operand is a valid second operand to a sign-extending
561 sext_add_operand (rtx op
, enum machine_mode mode
)
563 if (GET_CODE (op
) == CONST_INT
)
564 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
565 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
567 return reg_not_elim_operand (op
, mode
);
570 /* Return 1 if OP is the constant 4 or 8. */
573 const48_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
575 return (GET_CODE (op
) == CONST_INT
576 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
579 /* Return 1 if OP is a valid first operand to an AND insn. */
582 and_operand (rtx op
, enum machine_mode mode
)
584 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
585 return (zap_mask (CONST_DOUBLE_LOW (op
))
586 && zap_mask (CONST_DOUBLE_HIGH (op
)));
588 if (GET_CODE (op
) == CONST_INT
)
589 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
590 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
591 || zap_mask (INTVAL (op
)));
593 return register_operand (op
, mode
);
596 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
599 or_operand (rtx op
, enum machine_mode mode
)
601 if (GET_CODE (op
) == CONST_INT
)
602 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
603 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
605 return register_operand (op
, mode
);
608 /* Return 1 if OP is a constant that is the width, in bits, of an integral
609 mode smaller than DImode. */
612 mode_width_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
614 return (GET_CODE (op
) == CONST_INT
615 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
616 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
619 /* Return 1 if OP is a constant that is the width of an integral machine mode
620 smaller than an integer. */
623 mode_mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
625 if (GET_CODE (op
) == CONST_INT
)
627 HOST_WIDE_INT value
= INTVAL (op
);
633 if (value
== 0xffffffff)
638 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
640 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
647 /* Return 1 if OP is a multiple of 8 less than 64. */
650 mul8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
652 return (GET_CODE (op
) == CONST_INT
653 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
654 && (INTVAL (op
) & 7) == 0);
657 /* Return 1 if OP is the zero constant for MODE. */
660 const0_operand (rtx op
, enum machine_mode mode
)
662 return op
== CONST0_RTX (mode
);
665 /* Return 1 if OP is a hard floating-point register. */
668 hard_fp_register_operand (rtx op
, enum machine_mode mode
)
670 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
673 if (GET_CODE (op
) == SUBREG
)
674 op
= SUBREG_REG (op
);
675 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
678 /* Return 1 if OP is a hard general register. */
681 hard_int_register_operand (rtx op
, enum machine_mode mode
)
683 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
686 if (GET_CODE (op
) == SUBREG
)
687 op
= SUBREG_REG (op
);
688 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
691 /* Return 1 if OP is a register or a constant integer. */
695 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
697 return (GET_CODE (op
) == CONST_INT
698 || register_operand (op
, mode
));
701 /* Return 1 if OP is something that can be reloaded into a register;
702 if it is a MEM, it need not be valid. */
705 some_operand (rtx op
, enum machine_mode mode
)
707 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
710 switch (GET_CODE (op
))
724 return some_operand (SUBREG_REG (op
), VOIDmode
);
733 /* Likewise, but don't accept constants. */
736 some_ni_operand (rtx op
, enum machine_mode mode
)
738 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
741 if (GET_CODE (op
) == SUBREG
)
742 op
= SUBREG_REG (op
);
744 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
747 /* Return 1 if OP is a valid operand for the source of a move insn. */
750 input_operand (rtx op
, enum machine_mode mode
)
752 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
755 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
758 switch (GET_CODE (op
))
763 if (TARGET_EXPLICIT_RELOCS
)
765 /* We don't split symbolic operands into something unintelligable
766 until after reload, but we do not wish non-small, non-global
767 symbolic operands to be reconstructed from their high/lo_sum
769 return (small_symbolic_operand (op
, mode
)
770 || global_symbolic_operand (op
, mode
)
771 || gotdtp_symbolic_operand (op
, mode
)
772 || gottp_symbolic_operand (op
, mode
));
775 /* This handles both the Windows/NT and OSF cases. */
776 return mode
== ptr_mode
|| mode
== DImode
;
779 return (TARGET_EXPLICIT_RELOCS
780 && local_symbolic_operand (XEXP (op
, 0), mode
));
787 if (register_operand (op
, mode
))
789 /* ... fall through ... */
791 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
792 && general_operand (op
, mode
));
796 return op
== CONST0_RTX (mode
);
799 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
811 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
812 file, and in the same section as the current function. */
815 samegp_function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
817 if (GET_CODE (op
) != SYMBOL_REF
)
820 /* Easy test for recursion. */
821 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
824 /* Functions that are not local can be overridden, and thus may
825 not share the same gp. */
826 if (! SYMBOL_REF_LOCAL_P (op
))
829 /* If -msmall-data is in effect, assume that there is only one GP
830 for the module, and so any local symbol has this property. We
831 need explicit relocations to be able to enforce this for symbols
832 not defined in this unit of translation, however. */
833 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
836 /* Functions that are not external are defined in this UoT,
837 and thus must share the same gp. */
838 return ! SYMBOL_REF_EXTERNAL_P (op
);
841 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
844 direct_call_operand (rtx op
, enum machine_mode mode
)
846 tree op_decl
, cfun_sec
, op_sec
;
848 /* Must share the same GP. */
849 if (!samegp_function_operand (op
, mode
))
852 /* If profiling is implemented via linker tricks, we can't jump
853 to the nogp alternate entry point. Note that current_function_profile
854 would not be correct, since that doesn't indicate if the target
855 function uses profiling. */
856 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
857 but is approximately correct for the OSF ABIs. Don't know
858 what to do for VMS, NT, or UMK. */
859 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
862 /* Must be a function. In some cases folks create thunks in static
863 data structures and then make calls to them. If we allow the
864 direct call, we'll get an error from the linker about !samegp reloc
865 against a symbol without a .prologue directive. */
866 if (!SYMBOL_REF_FUNCTION_P (op
))
869 /* Must be "near" so that the branch is assumed to reach. With
870 -msmall-text, this is assumed true of all local symbols. Since
871 we've already checked samegp, locality is already assured. */
872 if (TARGET_SMALL_TEXT
)
875 /* Otherwise, a decl is "near" if it is defined in the same section. */
876 if (flag_function_sections
)
879 op_decl
= SYMBOL_REF_DECL (op
);
880 if (DECL_ONE_ONLY (current_function_decl
)
881 || (op_decl
&& DECL_ONE_ONLY (op_decl
)))
884 cfun_sec
= DECL_SECTION_NAME (current_function_decl
);
885 op_sec
= op_decl
? DECL_SECTION_NAME (op_decl
) : NULL
;
886 return ((!cfun_sec
&& !op_sec
)
887 || (cfun_sec
&& op_sec
888 && strcmp (TREE_STRING_POINTER (cfun_sec
),
889 TREE_STRING_POINTER (op_sec
)) == 0));
892 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
893 a (non-tls) variable known to be defined in this file. */
896 local_symbolic_operand (rtx op
, enum machine_mode mode
)
898 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
901 if (GET_CODE (op
) == LABEL_REF
)
904 if (GET_CODE (op
) == CONST
905 && GET_CODE (XEXP (op
, 0)) == PLUS
906 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
907 op
= XEXP (XEXP (op
, 0), 0);
909 if (GET_CODE (op
) != SYMBOL_REF
)
912 return SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
915 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
916 known to be defined in this file in the small data area. */
919 small_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
921 if (! TARGET_SMALL_DATA
)
924 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
927 if (GET_CODE (op
) == CONST
928 && GET_CODE (XEXP (op
, 0)) == PLUS
929 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
930 op
= XEXP (XEXP (op
, 0), 0);
932 if (GET_CODE (op
) != SYMBOL_REF
)
935 /* ??? There's no encode_section_info equivalent for the rtl
936 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
937 if (CONSTANT_POOL_ADDRESS_P (op
))
938 return GET_MODE_SIZE (get_pool_mode (op
)) <= g_switch_value
;
940 return (SYMBOL_REF_LOCAL_P (op
)
941 && SYMBOL_REF_SMALL_P (op
)
942 && SYMBOL_REF_TLS_MODEL (op
) == 0);
945 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
946 not known (or known not) to be defined in this file. */
949 global_symbolic_operand (rtx op
, enum machine_mode mode
)
951 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
954 if (GET_CODE (op
) == CONST
955 && GET_CODE (XEXP (op
, 0)) == PLUS
956 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
957 op
= XEXP (XEXP (op
, 0), 0);
959 if (GET_CODE (op
) != SYMBOL_REF
)
962 return !SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
965 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
968 call_operand (rtx op
, enum machine_mode mode
)
973 if (GET_CODE (op
) == REG
)
977 /* Disallow virtual registers to cope with pathological test cases
978 such as compile/930117-1.c in which the virtual reg decomposes
979 to the frame pointer. Which is a hard reg that is not $27. */
980 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
985 if (TARGET_ABI_UNICOSMK
)
987 if (GET_CODE (op
) == SYMBOL_REF
)
993 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
994 possibly with an offset. */
997 symbolic_operand (rtx op
, enum machine_mode mode
)
999 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1001 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1003 if (GET_CODE (op
) == CONST
1004 && GET_CODE (XEXP (op
,0)) == PLUS
1005 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1006 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1011 /* Return true if OP is valid for a particular TLS relocation. */
1014 tls_symbolic_operand_1 (rtx op
, enum machine_mode mode
, int size
, int unspec
)
1016 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1019 if (GET_CODE (op
) != CONST
)
1023 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1025 op
= XVECEXP (op
, 0, 0);
1027 if (GET_CODE (op
) != SYMBOL_REF
)
1030 if (SYMBOL_REF_LOCAL_P (op
))
1032 if (alpha_tls_size
> size
)
1041 switch (SYMBOL_REF_TLS_MODEL (op
))
1043 case TLS_MODEL_LOCAL_DYNAMIC
:
1044 return unspec
== UNSPEC_DTPREL
;
1045 case TLS_MODEL_INITIAL_EXEC
:
1046 return unspec
== UNSPEC_TPREL
&& size
== 64;
1047 case TLS_MODEL_LOCAL_EXEC
:
1048 return unspec
== UNSPEC_TPREL
;
1054 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1057 dtp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1059 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1062 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1065 dtp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1067 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1070 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1073 gotdtp_symbolic_operand (rtx op
, enum machine_mode mode
)
1075 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1078 /* Return true if OP is valid for 16-bit TP relative relocations. */
1081 tp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1083 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1086 /* Return true if OP is valid for 32-bit TP relative relocations. */
1089 tp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1091 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1094 /* Return true if OP is valid for 64-bit TP relative relocations. */
1097 gottp_symbolic_operand (rtx op
, enum machine_mode mode
)
1099 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1102 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1103 comparisons are valid in which insn. */
1106 alpha_comparison_operator (rtx op
, enum machine_mode mode
)
1108 enum rtx_code code
= GET_CODE (op
);
1110 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1113 return (code
== EQ
|| code
== LE
|| code
== LT
1114 || code
== LEU
|| code
== LTU
);
1117 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1118 Here we know which comparisons are valid in which insn. */
1121 alpha_zero_comparison_operator (rtx op
, enum machine_mode mode
)
1123 enum rtx_code code
= GET_CODE (op
);
1125 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1128 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1129 || code
== LEU
|| code
== LTU
);
1132 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1135 alpha_swapped_comparison_operator (rtx op
, enum machine_mode mode
)
1137 enum rtx_code code
= GET_CODE (op
);
1139 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1140 || GET_RTX_CLASS (code
) != '<')
1143 code
= swap_condition (code
);
1144 return (code
== EQ
|| code
== LE
|| code
== LT
1145 || code
== LEU
|| code
== LTU
);
1148 /* Return 1 if OP is a signed comparison operation. */
1151 signed_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1153 enum rtx_code code
= GET_CODE (op
);
1155 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1158 return (code
== EQ
|| code
== NE
1159 || code
== LE
|| code
== LT
1160 || code
== GE
|| code
== GT
);
1163 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1164 Here we know which comparisons are valid in which insn. */
1167 alpha_fp_comparison_operator (rtx op
, enum machine_mode mode
)
1169 enum rtx_code code
= GET_CODE (op
);
1171 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1174 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1177 /* Return 1 if this is a divide or modulus operator. */
1180 divmod_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1182 enum rtx_code code
= GET_CODE (op
);
1184 return (code
== DIV
|| code
== MOD
|| code
== UDIV
|| code
== UMOD
);
1187 /* Return 1 if this is a float->int conversion operator. */
1190 fix_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1192 enum rtx_code code
= GET_CODE (op
);
1194 return (code
== FIX
|| code
== UNSIGNED_FIX
);
1197 /* Return 1 if this memory address is a known aligned register plus
1198 a constant. It must be a valid address. This means that we can do
1199 this as an aligned reference plus some offset.
1201 Take into account what reload will do. */
1204 aligned_memory_operand (rtx op
, enum machine_mode mode
)
1208 if (reload_in_progress
)
1211 if (GET_CODE (tmp
) == SUBREG
)
1212 tmp
= SUBREG_REG (tmp
);
1213 if (GET_CODE (tmp
) == REG
1214 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1216 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1222 if (GET_CODE (op
) != MEM
)
1224 if (MEM_ALIGN (op
) >= 32)
1228 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1229 sorts of constructs. Dig for the real base register. */
1230 if (reload_in_progress
1231 && GET_CODE (op
) == PLUS
1232 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1233 base
= XEXP (XEXP (op
, 0), 0);
1236 if (! memory_address_p (mode
, op
))
1238 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1241 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1244 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1247 unaligned_memory_operand (rtx op
, enum machine_mode mode
)
1251 if (reload_in_progress
)
1254 if (GET_CODE (tmp
) == SUBREG
)
1255 tmp
= SUBREG_REG (tmp
);
1256 if (GET_CODE (tmp
) == REG
1257 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1259 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1265 if (GET_CODE (op
) != MEM
)
1267 if (MEM_ALIGN (op
) >= 32)
1271 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1272 sorts of constructs. Dig for the real base register. */
1273 if (reload_in_progress
1274 && GET_CODE (op
) == PLUS
1275 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1276 base
= XEXP (XEXP (op
, 0), 0);
1279 if (! memory_address_p (mode
, op
))
1281 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1284 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1287 /* Return 1 if OP is either a register or an unaligned memory location. */
1290 reg_or_unaligned_mem_operand (rtx op
, enum machine_mode mode
)
1292 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1295 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1298 any_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1300 return (GET_CODE (op
) == MEM
1301 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1302 || (reload_in_progress
&& GET_CODE (op
) == REG
1303 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1304 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1305 && GET_CODE (SUBREG_REG (op
)) == REG
1306 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1309 /* Returns 1 if OP is not an eliminable register.
1311 This exists to cure a pathological abort in the s8addq (et al) patterns,
1313 long foo () { long t; bar(); return (long) &t * 26107; }
1315 which run afoul of a hack in reload to cure a (presumably) similar
1316 problem with lea-type instructions on other targets. But there is
1317 one of us and many of them, so work around the problem by selectively
1318 preventing combine from making the optimization. */
1321 reg_not_elim_operand (rtx op
, enum machine_mode mode
)
1324 if (GET_CODE (op
) == SUBREG
)
1325 inner
= SUBREG_REG (op
);
1326 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1329 return register_operand (op
, mode
);
1332 /* Return 1 is OP is a memory location that is not a reference (using
1333 an AND) to an unaligned location. Take into account what reload
1337 normal_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1339 if (reload_in_progress
)
1342 if (GET_CODE (tmp
) == SUBREG
)
1343 tmp
= SUBREG_REG (tmp
);
1344 if (GET_CODE (tmp
) == REG
1345 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1347 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1349 /* This may not have been assigned an equivalent address if it will
1350 be eliminated. In that case, it doesn't matter what we do. */
1356 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1359 /* Accept a register, but not a subreg of any kind. This allows us to
1360 avoid pathological cases in reload wrt data movement common in
1361 int->fp conversion. */
1364 reg_no_subreg_operand (rtx op
, enum machine_mode mode
)
1366 if (GET_CODE (op
) != REG
)
1368 return register_operand (op
, mode
);
1371 /* Recognize an addition operation that includes a constant. Used to
1372 convince reload to canonize (plus (plus reg c1) c2) during register
1376 addition_operation (rtx op
, enum machine_mode mode
)
1378 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1380 if (GET_CODE (op
) == PLUS
1381 && register_operand (XEXP (op
, 0), mode
)
1382 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1383 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1388 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1389 the range defined for C in [I-P]. */
1392 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
1397 /* An unsigned 8 bit constant. */
1398 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1400 /* The constant zero. */
1403 /* A signed 16 bit constant. */
1404 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1406 /* A shifted signed 16 bit constant appropriate for LDAH. */
1407 return ((value
& 0xffff) == 0
1408 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1410 /* A constant that can be AND'ed with using a ZAP insn. */
1411 return zap_mask (value
);
1413 /* A complemented unsigned 8 bit constant. */
1414 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1416 /* A negated unsigned 8 bit constant. */
1417 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1419 /* The constant 1, 2 or 3. */
1420 return value
== 1 || value
== 2 || value
== 3;
1427 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1428 matches for C in [GH]. */
1431 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
1436 /* The floating point zero constant. */
1437 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1438 && value
== CONST0_RTX (GET_MODE (value
)));
1441 /* A valid operand of a ZAP insn. */
1442 return (GET_MODE (value
) == VOIDmode
1443 && zap_mask (CONST_DOUBLE_LOW (value
))
1444 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1451 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1455 alpha_extra_constraint (rtx value
, int c
)
1460 return normal_memory_operand (value
, VOIDmode
);
1462 return direct_call_operand (value
, Pmode
);
1464 return (GET_CODE (value
) == CONST_INT
1465 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1467 return GET_CODE (value
) == HIGH
;
1469 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1471 return (GET_CODE (value
) == CONST_VECTOR
1472 && value
== CONST0_RTX (GET_MODE (value
)));
1478 /* Return 1 if this function can directly return via $26. */
1481 direct_return (void)
1483 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1485 && alpha_sa_size () == 0
1486 && get_frame_size () == 0
1487 && current_function_outgoing_args_size
== 0
1488 && current_function_pretend_args_size
== 0);
1491 /* Return the ADDR_VEC associated with a tablejump insn. */
1494 alpha_tablejump_addr_vec (rtx insn
)
1498 tmp
= JUMP_LABEL (insn
);
1501 tmp
= NEXT_INSN (tmp
);
1504 if (GET_CODE (tmp
) == JUMP_INSN
1505 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1506 return PATTERN (tmp
);
1510 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1513 alpha_tablejump_best_label (rtx insn
)
1515 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1516 rtx best_label
= NULL_RTX
;
1518 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1519 there for edge frequency counts from profile data. */
1523 int n_labels
= XVECLEN (jump_table
, 1);
1524 int best_count
= -1;
1527 for (i
= 0; i
< n_labels
; i
++)
1531 for (j
= i
+ 1; j
< n_labels
; j
++)
1532 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1533 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1536 if (count
> best_count
)
1537 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1541 return best_label
? best_label
: const0_rtx
;
1544 /* Return the TLS model to use for SYMBOL. */
1546 static enum tls_model
1547 tls_symbolic_operand_type (rtx symbol
)
1549 enum tls_model model
;
1551 if (GET_CODE (symbol
) != SYMBOL_REF
)
1553 model
= SYMBOL_REF_TLS_MODEL (symbol
);
1555 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1556 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
1557 model
= TLS_MODEL_INITIAL_EXEC
;
1562 /* Return true if the function DECL will share the same GP as any
1563 function in the current unit of translation. */
1566 decl_has_samegp (tree decl
)
1568 /* Functions that are not local can be overridden, and thus may
1569 not share the same gp. */
1570 if (!(*targetm
.binds_local_p
) (decl
))
1573 /* If -msmall-data is in effect, assume that there is only one GP
1574 for the module, and so any local symbol has this property. We
1575 need explicit relocations to be able to enforce this for symbols
1576 not defined in this unit of translation, however. */
1577 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1580 /* Functions that are not external are defined in this UoT. */
1581 /* ??? Irritatingly, static functions not yet emitted are still
1582 marked "external". Apply this to non-static functions only. */
1583 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1586 /* Return true if EXP should be placed in the small data section. */
1589 alpha_in_small_data_p (tree exp
)
1591 /* We want to merge strings, so we never consider them small data. */
1592 if (TREE_CODE (exp
) == STRING_CST
)
1595 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1597 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1598 if (strcmp (section
, ".sdata") == 0
1599 || strcmp (section
, ".sbss") == 0)
1604 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1606 /* If this is an incomplete type with size 0, then we can't put it
1607 in sdata because it might be too big when completed. */
1608 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
1615 #if TARGET_ABI_OPEN_VMS
1617 alpha_linkage_symbol_p (const char *symname
)
1619 int symlen
= strlen (symname
);
1622 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1627 #define LINKAGE_SYMBOL_REF_P(X) \
1628 ((GET_CODE (X) == SYMBOL_REF \
1629 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1630 || (GET_CODE (X) == CONST \
1631 && GET_CODE (XEXP (X, 0)) == PLUS \
1632 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1633 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1636 /* legitimate_address_p recognizes an RTL expression that is a valid
1637 memory address for an instruction. The MODE argument is the
1638 machine mode for the MEM expression that wants to use this address.
1640 For Alpha, we have either a constant address or the sum of a
1641 register and a constant address, or just a register. For DImode,
1642 any of those forms can be surrounded with an AND that clear the
1643 low-order three bits; this is an "unaligned" access. */
1646 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1648 /* If this is an ldq_u type address, discard the outer AND. */
1650 && GET_CODE (x
) == AND
1651 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1652 && INTVAL (XEXP (x
, 1)) == -8)
1655 /* Discard non-paradoxical subregs. */
1656 if (GET_CODE (x
) == SUBREG
1657 && (GET_MODE_SIZE (GET_MODE (x
))
1658 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1661 /* Unadorned general registers are valid. */
1664 ? STRICT_REG_OK_FOR_BASE_P (x
)
1665 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1668 /* Constant addresses (i.e. +/- 32k) are valid. */
1669 if (CONSTANT_ADDRESS_P (x
))
1672 #if TARGET_ABI_OPEN_VMS
1673 if (LINKAGE_SYMBOL_REF_P (x
))
1677 /* Register plus a small constant offset is valid. */
1678 if (GET_CODE (x
) == PLUS
)
1680 rtx ofs
= XEXP (x
, 1);
1683 /* Discard non-paradoxical subregs. */
1684 if (GET_CODE (x
) == SUBREG
1685 && (GET_MODE_SIZE (GET_MODE (x
))
1686 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1692 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1693 && GET_CODE (ofs
) == CONST_INT
)
1696 ? STRICT_REG_OK_FOR_BASE_P (x
)
1697 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1698 && CONSTANT_ADDRESS_P (ofs
))
1701 else if (GET_CODE (x
) == ADDRESSOF
1702 && GET_CODE (ofs
) == CONST_INT
)
1706 /* If we're managing explicit relocations, LO_SUM is valid, as
1707 are small data symbols. */
1708 else if (TARGET_EXPLICIT_RELOCS
)
1710 if (small_symbolic_operand (x
, Pmode
))
1713 if (GET_CODE (x
) == LO_SUM
)
1715 rtx ofs
= XEXP (x
, 1);
1718 /* Discard non-paradoxical subregs. */
1719 if (GET_CODE (x
) == SUBREG
1720 && (GET_MODE_SIZE (GET_MODE (x
))
1721 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1724 /* Must have a valid base register. */
1727 ? STRICT_REG_OK_FOR_BASE_P (x
)
1728 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1731 /* The symbol must be local. */
1732 if (local_symbolic_operand (ofs
, Pmode
)
1733 || dtp32_symbolic_operand (ofs
, Pmode
)
1734 || tp32_symbolic_operand (ofs
, Pmode
))
1742 /* Build the SYMBOL_REF for __tls_get_addr. */
1744 static GTY(()) rtx tls_get_addr_libfunc
;
1747 get_tls_get_addr (void)
1749 if (!tls_get_addr_libfunc
)
1750 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
1751 return tls_get_addr_libfunc
;
1754 /* Try machine-dependent ways of modifying an illegitimate address
1755 to be legitimate. If we find one, return the new, valid address. */
1758 alpha_legitimize_address (rtx x
, rtx scratch
,
1759 enum machine_mode mode ATTRIBUTE_UNUSED
)
1761 HOST_WIDE_INT addend
;
1763 /* If the address is (plus reg const_int) and the CONST_INT is not a
1764 valid offset, compute the high part of the constant and add it to
1765 the register. Then our address is (plus temp low-part-const). */
1766 if (GET_CODE (x
) == PLUS
1767 && GET_CODE (XEXP (x
, 0)) == REG
1768 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1769 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1771 addend
= INTVAL (XEXP (x
, 1));
1776 /* If the address is (const (plus FOO const_int)), find the low-order
1777 part of the CONST_INT. Then load FOO plus any high-order part of the
1778 CONST_INT into a register. Our address is (plus reg low-part-const).
1779 This is done to reduce the number of GOT entries. */
1781 && GET_CODE (x
) == CONST
1782 && GET_CODE (XEXP (x
, 0)) == PLUS
1783 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1785 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1786 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1790 /* If we have a (plus reg const), emit the load as in (2), then add
1791 the two registers, and finally generate (plus reg low-part-const) as
1794 && GET_CODE (x
) == PLUS
1795 && GET_CODE (XEXP (x
, 0)) == REG
1796 && GET_CODE (XEXP (x
, 1)) == CONST
1797 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1798 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1800 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1801 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1802 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1803 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1807 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1808 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1810 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1812 switch (tls_symbolic_operand_type (x
))
1814 case TLS_MODEL_GLOBAL_DYNAMIC
:
1817 r0
= gen_rtx_REG (Pmode
, 0);
1818 r16
= gen_rtx_REG (Pmode
, 16);
1819 tga
= get_tls_get_addr ();
1820 dest
= gen_reg_rtx (Pmode
);
1821 seq
= GEN_INT (alpha_next_sequence_number
++);
1823 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1824 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1825 insn
= emit_call_insn (insn
);
1826 CONST_OR_PURE_CALL_P (insn
) = 1;
1827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1829 insn
= get_insns ();
1832 emit_libcall_block (insn
, dest
, r0
, x
);
1835 case TLS_MODEL_LOCAL_DYNAMIC
:
1838 r0
= gen_rtx_REG (Pmode
, 0);
1839 r16
= gen_rtx_REG (Pmode
, 16);
1840 tga
= get_tls_get_addr ();
1841 scratch
= gen_reg_rtx (Pmode
);
1842 seq
= GEN_INT (alpha_next_sequence_number
++);
1844 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1845 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1846 insn
= emit_call_insn (insn
);
1847 CONST_OR_PURE_CALL_P (insn
) = 1;
1848 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1850 insn
= get_insns ();
1853 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1854 UNSPEC_TLSLDM_CALL
);
1855 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1857 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1858 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1860 if (alpha_tls_size
== 64)
1862 dest
= gen_reg_rtx (Pmode
);
1863 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1864 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1867 if (alpha_tls_size
== 32)
1869 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1870 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1871 scratch
= gen_reg_rtx (Pmode
);
1872 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1874 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1876 case TLS_MODEL_INITIAL_EXEC
:
1877 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1878 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1879 tp
= gen_reg_rtx (Pmode
);
1880 scratch
= gen_reg_rtx (Pmode
);
1881 dest
= gen_reg_rtx (Pmode
);
1883 emit_insn (gen_load_tp (tp
));
1884 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1885 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1888 case TLS_MODEL_LOCAL_EXEC
:
1889 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1890 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1891 tp
= gen_reg_rtx (Pmode
);
1893 emit_insn (gen_load_tp (tp
));
1894 if (alpha_tls_size
== 32)
1896 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1897 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1898 tp
= gen_reg_rtx (Pmode
);
1899 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1901 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1904 if (local_symbolic_operand (x
, Pmode
))
1906 if (small_symbolic_operand (x
, Pmode
))
1910 if (!no_new_pseudos
)
1911 scratch
= gen_reg_rtx (Pmode
);
1912 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1913 gen_rtx_HIGH (Pmode
, x
)));
1914 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1923 HOST_WIDE_INT low
, high
;
1925 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1927 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1931 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1932 (no_new_pseudos
? scratch
: NULL_RTX
),
1933 1, OPTAB_LIB_WIDEN
);
1935 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1936 (no_new_pseudos
? scratch
: NULL_RTX
),
1937 1, OPTAB_LIB_WIDEN
);
1939 return plus_constant (x
, low
);
1943 /* We do not allow indirect calls to be optimized into sibling calls, nor
1944 can we allow a call to a function with a different GP to be optimized
1948 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1950 /* Can't do indirect tail calls, since we don't know if the target
1951 uses the same GP. */
1955 /* Otherwise, we can make a tail call if the target function shares
1957 return decl_has_samegp (decl
);
1960 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1961 small symbolic operand until after reload. At which point we need
1962 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1963 so that sched2 has the proper dependency information. */
1966 some_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1970 /* Don't re-split. */
1971 if (GET_CODE (x
) == LO_SUM
)
1974 return small_symbolic_operand (x
, Pmode
) != 0;
1978 some_small_symbolic_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1980 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
1984 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1988 /* Don't re-split. */
1989 if (GET_CODE (x
) == LO_SUM
)
1992 if (small_symbolic_operand (x
, Pmode
))
1994 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2003 split_small_symbolic_operand (rtx x
)
2006 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2010 /* Indicate that INSN cannot be duplicated. This is true for any insn
2011 that we've marked with gpdisp relocs, since those have to stay in
2012 1-1 correspondence with one another.
2014 Technically we could copy them if we could set up a mapping from one
2015 sequence number to another, across the set of insns to be duplicated.
2016 This seems overly complicated and error-prone since interblock motion
2017 from sched-ebb could move one of the pair of insns to a different block.
2019 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2020 then they'll be in a different block from their ldgp. Which could lead
2021 the bb reorder code to think that it would be ok to copy just the block
2022 containing the call and branch to the block containing the ldgp. */
2025 alpha_cannot_copy_insn_p (rtx insn
)
2027 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2029 if (recog_memoized (insn
) >= 0)
2030 return get_attr_cannot_copy (insn
);
2036 /* Try a machine-dependent way of reloading an illegitimate address
2037 operand. If we find one, push the reload and return the new rtx. */
2040 alpha_legitimize_reload_address (rtx x
,
2041 enum machine_mode mode ATTRIBUTE_UNUSED
,
2042 int opnum
, int type
,
2043 int ind_levels ATTRIBUTE_UNUSED
)
2045 /* We must recognize output that we have already generated ourselves. */
2046 if (GET_CODE (x
) == PLUS
2047 && GET_CODE (XEXP (x
, 0)) == PLUS
2048 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2049 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2050 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2052 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2053 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2058 /* We wish to handle large displacements off a base register by
2059 splitting the addend across an ldah and the mem insn. This
2060 cuts number of extra insns needed from 3 to 1. */
2061 if (GET_CODE (x
) == PLUS
2062 && GET_CODE (XEXP (x
, 0)) == REG
2063 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2064 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2065 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2067 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2068 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2070 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2072 /* Check for 32-bit overflow. */
2073 if (high
+ low
!= val
)
2076 /* Reload the high part into a base reg; leave the low part
2077 in the mem directly. */
2078 x
= gen_rtx_PLUS (GET_MODE (x
),
2079 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2083 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2084 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2092 /* Compute a (partial) cost for rtx X. Return true if the complete
2093 cost has been computed, and false if subexpressions should be
2094 scanned. In either case, *TOTAL contains the cost result. */
2097 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2099 enum machine_mode mode
= GET_MODE (x
);
2100 bool float_mode_p
= FLOAT_MODE_P (mode
);
2104 /* If this is an 8-bit constant, return zero since it can be used
2105 nearly anywhere with no cost. If it is a valid operand for an
2106 ADD or AND, likewise return 0 if we know it will be used in that
2107 context. Otherwise, return 2 since it might be used there later.
2108 All other constants take at least two insns. */
2110 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2118 if (x
== CONST0_RTX (mode
))
2120 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2121 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2123 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2126 *total
= COSTS_N_INSNS (2);
2132 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2133 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2134 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2135 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2136 else if (tls_symbolic_operand_type (x
))
2137 /* Estimate of cost for call_pal rduniq. */
2138 *total
= COSTS_N_INSNS (15);
2140 /* Otherwise we do a load from the GOT. */
2141 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2147 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2148 else if (GET_CODE (XEXP (x
, 0)) == MULT
2149 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2151 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2152 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2159 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2160 else if (mode
== DImode
)
2161 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2163 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2167 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2168 && INTVAL (XEXP (x
, 1)) <= 3)
2170 *total
= COSTS_N_INSNS (1);
2177 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2182 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2184 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2192 *total
= COSTS_N_INSNS (70); /* ??? */
2193 else if (mode
== SFmode
)
2194 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2196 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2200 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2206 *total
= COSTS_N_INSNS (1);
2214 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2220 case UNSIGNED_FLOAT
:
2224 case FLOAT_TRUNCATE
:
2225 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2233 /* REF is an alignable memory location. Place an aligned SImode
2234 reference into *PALIGNED_MEM and the number of bits to shift into
2235 *PBITNUM. SCRATCH is a free register for use in reloading out
2236 of range stack slots. */
2239 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
2242 HOST_WIDE_INT offset
= 0;
2244 if (GET_CODE (ref
) != MEM
)
2247 if (reload_in_progress
2248 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2250 base
= find_replacement (&XEXP (ref
, 0));
2252 if (! memory_address_p (GET_MODE (ref
), base
))
2257 base
= XEXP (ref
, 0);
2260 if (GET_CODE (base
) == PLUS
)
2261 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2264 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2266 if (WORDS_BIG_ENDIAN
)
2267 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2268 + (offset
& 3) * 8));
2270 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2273 /* Similar, but just get the address. Handle the two reload cases.
2274 Add EXTRA_OFFSET to the address we return. */
2277 get_unaligned_address (rtx ref
, int extra_offset
)
2280 HOST_WIDE_INT offset
= 0;
2282 if (GET_CODE (ref
) != MEM
)
2285 if (reload_in_progress
2286 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2288 base
= find_replacement (&XEXP (ref
, 0));
2290 if (! memory_address_p (GET_MODE (ref
), base
))
2295 base
= XEXP (ref
, 0);
2298 if (GET_CODE (base
) == PLUS
)
2299 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2301 return plus_constant (base
, offset
+ extra_offset
);
2304 /* On the Alpha, all (non-symbolic) constants except zero go into
2305 a floating-point register via memory. Note that we cannot
2306 return anything that is not a subset of CLASS, and that some
2307 symbolic constants cannot be dropped to memory. */
2310 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
2312 /* Zero is present in any register class. */
2313 if (x
== CONST0_RTX (GET_MODE (x
)))
2316 /* These sorts of constants we can easily drop to memory. */
2317 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2319 if (class == FLOAT_REGS
)
2321 if (class == ALL_REGS
)
2322 return GENERAL_REGS
;
2326 /* All other kinds of constants should not (and in the case of HIGH
2327 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2328 secondary reload. */
2330 return (class == ALL_REGS
? GENERAL_REGS
: class);
2335 /* Loading and storing HImode or QImode values to and from memory
2336 usually requires a scratch register. The exceptions are loading
2337 QImode and HImode from an aligned address to a general register
2338 unless byte instructions are permitted.
2340 We also cannot load an unaligned address or a paradoxical SUBREG
2341 into an FP register.
2343 We also cannot do integral arithmetic into FP regs, as might result
2344 from register elimination into a DImode fp register. */
2347 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
2350 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2352 if (GET_CODE (x
) == MEM
2353 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2354 || (GET_CODE (x
) == SUBREG
2355 && (GET_CODE (SUBREG_REG (x
)) == MEM
2356 || (GET_CODE (SUBREG_REG (x
)) == REG
2357 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2359 if (!in
|| !aligned_memory_operand(x
, mode
))
2360 return GENERAL_REGS
;
2364 if (class == FLOAT_REGS
)
2366 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2367 return GENERAL_REGS
;
2369 if (GET_CODE (x
) == SUBREG
2370 && (GET_MODE_SIZE (GET_MODE (x
))
2371 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2372 return GENERAL_REGS
;
2374 if (in
&& INTEGRAL_MODE_P (mode
)
2375 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2376 return GENERAL_REGS
;
2382 /* Subfunction of the following function. Update the flags of any MEM
2383 found in part of X. */
2386 alpha_set_memflags_1 (rtx x
, int in_struct_p
, int volatile_p
, int unchanging_p
)
2390 switch (GET_CODE (x
))
2396 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2397 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2402 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2407 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2409 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2414 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2415 MEM_VOLATILE_P (x
) = volatile_p
;
2416 RTX_UNCHANGING_P (x
) = unchanging_p
;
2417 /* Sadly, we cannot use alias sets because the extra aliasing
2418 produced by the AND interferes. Given that two-byte quantities
2419 are the only thing we would be able to differentiate anyway,
2420 there does not seem to be any point in convoluting the early
2421 out of the alias check. */
2429 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2430 generated to perform a memory operation, look for any MEMs in either
2431 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2432 volatile flags from REF into each of the MEMs found. If REF is not
2433 a MEM, don't do anything. */
2436 alpha_set_memflags (rtx insn
, rtx ref
)
2438 int in_struct_p
, volatile_p
, unchanging_p
;
2440 if (GET_CODE (ref
) != MEM
)
2443 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2444 volatile_p
= MEM_VOLATILE_P (ref
);
2445 unchanging_p
= RTX_UNCHANGING_P (ref
);
2447 /* This is only called from alpha.md, after having had something
2448 generated from one of the insn patterns. So if everything is
2449 zero, the pattern is already up-to-date. */
2450 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2453 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2456 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2459 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
2460 HOST_WIDE_INT c
, int n
)
2464 /* Use a pseudo if highly optimizing and still generating RTL. */
2466 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2469 /* If this is a sign-extended 32-bit constant, we can do this in at most
2470 three insns, so do it if we have enough insns left. We always have
2471 a sign-extended 32-bit constant when compiling on a narrow machine. */
2473 if (HOST_BITS_PER_WIDE_INT
!= 64
2474 || c
>> 31 == -1 || c
>> 31 == 0)
2476 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2477 HOST_WIDE_INT tmp1
= c
- low
;
2478 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2479 HOST_WIDE_INT extra
= 0;
2481 /* If HIGH will be interpreted as negative but the constant is
2482 positive, we must adjust it to do two ldha insns. */
2484 if ((high
& 0x8000) != 0 && c
>= 0)
2488 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2491 if (c
== low
|| (low
== 0 && extra
== 0))
2493 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2494 but that meant that we can't handle INT_MIN on 32-bit machines
2495 (like NT/Alpha), because we recurse indefinitely through
2496 emit_move_insn to gen_movdi. So instead, since we know exactly
2497 what we want, create it explicitly. */
2500 target
= gen_reg_rtx (mode
);
2501 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2504 else if (n
>= 2 + (extra
!= 0))
2506 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2508 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2509 This means that if we go through expand_binop, we'll try to
2510 generate extensions, etc, which will require new pseudos, which
2511 will fail during some split phases. The SImode add patterns
2512 still exist, but are not named. So build the insns by hand. */
2517 subtarget
= gen_reg_rtx (mode
);
2518 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2519 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2525 target
= gen_reg_rtx (mode
);
2526 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2527 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2533 /* If we couldn't do it that way, try some other methods. But if we have
2534 no instructions left, don't bother. Likewise, if this is SImode and
2535 we can't make pseudos, we can't do anything since the expand_binop
2536 and expand_unop calls will widen and try to make pseudos. */
2538 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2541 /* Next, see if we can load a related constant and then shift and possibly
2542 negate it to get the constant we want. Try this once each increasing
2543 numbers of insns. */
2545 for (i
= 1; i
< n
; i
++)
2547 /* First, see if minus some low bits, we've an easy load of
2550 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2552 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2553 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2554 target
, 0, OPTAB_WIDEN
);
2556 /* Next try complementing. */
2557 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2558 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2560 /* Next try to form a constant and do a left shift. We can do this
2561 if some low-order bits are zero; the exact_log2 call below tells
2562 us that information. The bits we are shifting out could be any
2563 value, but here we'll just try the 0- and sign-extended forms of
2564 the constant. To try to increase the chance of having the same
2565 constant in more than one insn, start at the highest number of
2566 bits to shift, but try all possibilities in case a ZAPNOT will
2569 if ((bits
= exact_log2 (c
& - c
)) > 0)
2570 for (; bits
> 0; bits
--)
2571 if ((temp
= (alpha_emit_set_const
2572 (subtarget
, mode
, c
>> bits
, i
))) != 0
2573 || ((temp
= (alpha_emit_set_const
2575 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2577 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2578 target
, 0, OPTAB_WIDEN
);
2580 /* Now try high-order zero bits. Here we try the shifted-in bits as
2581 all zero and all ones. Be careful to avoid shifting outside the
2582 mode and to avoid shifting outside the host wide int size. */
2583 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2584 confuse the recursive call and set all of the high 32 bits. */
2586 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2587 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2588 for (; bits
> 0; bits
--)
2589 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2591 || ((temp
= (alpha_emit_set_const
2593 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2596 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2597 target
, 1, OPTAB_WIDEN
);
2599 /* Now try high-order 1 bits. We get that with a sign-extension.
2600 But one bit isn't enough here. Be careful to avoid shifting outside
2601 the mode and to avoid shifting outside the host wide int size. */
2603 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2604 - floor_log2 (~ c
) - 2)) > 0)
2605 for (; bits
> 0; bits
--)
2606 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2608 || ((temp
= (alpha_emit_set_const
2610 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2613 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2614 target
, 0, OPTAB_WIDEN
);
2617 #if HOST_BITS_PER_WIDE_INT == 64
2618 /* Finally, see if can load a value into the target that is the same as the
2619 constant except that all bytes that are 0 are changed to be 0xff. If we
2620 can, then we can do a ZAPNOT to obtain the desired constant. */
2623 for (i
= 0; i
< 64; i
+= 8)
2624 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2625 new |= (HOST_WIDE_INT
) 0xff << i
;
2627 /* We are only called for SImode and DImode. If this is SImode, ensure that
2628 we are sign extended to a full word. */
2631 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2633 if (new != c
&& new != -1
2634 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2635 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2636 target
, 0, OPTAB_WIDEN
);
2642 /* Try to output insns to set TARGET equal to the constant C if it can be
2643 done in less than N insns. Do all computations in MODE. Returns the place
2644 where the output has been placed if it can be done and the insns have been
2645 emitted. If it would take more than N insns, zero is returned and no
2646 insns and emitted. */
2649 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
2650 HOST_WIDE_INT c
, int n
)
2653 rtx orig_target
= target
;
2656 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2657 can't load this constant in one insn, do this in DImode. */
2658 if (no_new_pseudos
&& mode
== SImode
2659 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2660 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2662 target
= gen_lowpart (DImode
, target
);
2666 /* Try 1 insn, then 2, then up to N. */
2667 for (i
= 1; i
<= n
; i
++)
2669 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2672 rtx insn
= get_last_insn ();
2673 rtx set
= single_set (insn
);
2674 if (! CONSTANT_P (SET_SRC (set
)))
2675 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2680 /* Allow for the case where we changed the mode of TARGET. */
2681 if (result
== target
)
2682 result
= orig_target
;
2687 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2688 fall back to a straight forward decomposition. We do this to avoid
2689 exponential run times encountered when looking for longer sequences
2690 with alpha_emit_set_const. */
2693 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2695 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2697 /* Decompose the entire word */
2698 #if HOST_BITS_PER_WIDE_INT >= 64
2699 if (c2
!= -(c1
< 0))
2701 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2703 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2704 c1
= (c1
- d2
) >> 32;
2705 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2707 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2711 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2713 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2717 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2719 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2724 /* Construct the high word */
2727 emit_move_insn (target
, GEN_INT (d4
));
2729 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2732 emit_move_insn (target
, GEN_INT (d3
));
2734 /* Shift it into place */
2735 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2737 /* Add in the low bits. */
2739 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2741 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2746 /* Expand a move instruction; return true if all work is done.
2747 We don't handle non-bwx subword loads here. */
2750 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2752 /* If the output is not a register, the input must be. */
2753 if (GET_CODE (operands
[0]) == MEM
2754 && ! reg_or_0_operand (operands
[1], mode
))
2755 operands
[1] = force_reg (mode
, operands
[1]);
2757 /* Allow legitimize_address to perform some simplifications. */
2758 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2762 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2763 compiled at the end of compilation. In the meantime, someone can
2764 re-encode-section-info on some symbol changing it e.g. from global
2765 to local-not-small. If this happens, we'd have emitted a plain
2766 load rather than a high+losum load and not recognize the insn.
2768 So if rtl inlining is in effect, we delay the global/not-global
2769 decision until rest_of_compilation by wrapping it in an
2771 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2772 && rtx_equal_function_value_matters
2773 && global_symbolic_operand (operands
[1], mode
))
2775 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2779 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2782 if (tmp
== operands
[0])
2789 /* Early out for non-constants and valid constants. */
2790 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2793 /* Split large integers. */
2794 if (GET_CODE (operands
[1]) == CONST_INT
2795 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2797 HOST_WIDE_INT i0
, i1
;
2798 rtx temp
= NULL_RTX
;
2800 if (GET_CODE (operands
[1]) == CONST_INT
)
2802 i0
= INTVAL (operands
[1]);
2805 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2807 i0
= CONST_DOUBLE_LOW (operands
[1]);
2812 i0
= CONST_DOUBLE_LOW (operands
[1]);
2813 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2816 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2817 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2819 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2820 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2824 if (rtx_equal_p (operands
[0], temp
))
2831 /* Otherwise we've nothing left but to drop the thing to memory. */
2832 operands
[1] = force_const_mem (mode
, operands
[1]);
2833 if (reload_in_progress
)
2835 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2836 operands
[1] = copy_rtx (operands
[1]);
2837 XEXP (operands
[1], 0) = operands
[0];
2840 operands
[1] = validize_mem (operands
[1]);
2844 /* Expand a non-bwx QImode or HImode move instruction;
2845 return true if all work is done. */
2848 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2850 /* If the output is not a register, the input must be. */
2851 if (GET_CODE (operands
[0]) == MEM
)
2852 operands
[1] = force_reg (mode
, operands
[1]);
2854 /* Handle four memory cases, unaligned and aligned for either the input
2855 or the output. The only case where we can be called during reload is
2856 for aligned loads; all other cases require temporaries. */
2858 if (GET_CODE (operands
[1]) == MEM
2859 || (GET_CODE (operands
[1]) == SUBREG
2860 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2861 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2862 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2863 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2864 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2865 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2867 if (aligned_memory_operand (operands
[1], mode
))
2869 if (reload_in_progress
)
2871 emit_insn ((mode
== QImode
2872 ? gen_reload_inqi_help
2873 : gen_reload_inhi_help
)
2874 (operands
[0], operands
[1],
2875 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2879 rtx aligned_mem
, bitnum
;
2880 rtx scratch
= gen_reg_rtx (SImode
);
2884 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2886 subtarget
= operands
[0];
2887 if (GET_CODE (subtarget
) == REG
)
2888 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2890 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2892 emit_insn ((mode
== QImode
2893 ? gen_aligned_loadqi
2894 : gen_aligned_loadhi
)
2895 (subtarget
, aligned_mem
, bitnum
, scratch
));
2898 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2903 /* Don't pass these as parameters since that makes the generated
2904 code depend on parameter evaluation order which will cause
2905 bootstrap failures. */
2907 rtx temp1
, temp2
, seq
, subtarget
;
2910 temp1
= gen_reg_rtx (DImode
);
2911 temp2
= gen_reg_rtx (DImode
);
2913 subtarget
= operands
[0];
2914 if (GET_CODE (subtarget
) == REG
)
2915 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2917 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2919 seq
= ((mode
== QImode
2920 ? gen_unaligned_loadqi
2921 : gen_unaligned_loadhi
)
2922 (subtarget
, get_unaligned_address (operands
[1], 0),
2924 alpha_set_memflags (seq
, operands
[1]);
2928 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2933 if (GET_CODE (operands
[0]) == MEM
2934 || (GET_CODE (operands
[0]) == SUBREG
2935 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2936 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2937 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2938 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2939 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2940 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2942 if (aligned_memory_operand (operands
[0], mode
))
2944 rtx aligned_mem
, bitnum
;
2945 rtx temp1
= gen_reg_rtx (SImode
);
2946 rtx temp2
= gen_reg_rtx (SImode
);
2948 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2950 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2955 rtx temp1
= gen_reg_rtx (DImode
);
2956 rtx temp2
= gen_reg_rtx (DImode
);
2957 rtx temp3
= gen_reg_rtx (DImode
);
2958 rtx seq
= ((mode
== QImode
2959 ? gen_unaligned_storeqi
2960 : gen_unaligned_storehi
)
2961 (get_unaligned_address (operands
[0], 0),
2962 operands
[1], temp1
, temp2
, temp3
));
2964 alpha_set_memflags (seq
, operands
[0]);
2973 /* Generate an unsigned DImode to FP conversion. This is the same code
2974 optabs would emit if we didn't have TFmode patterns.
2976 For SFmode, this is the only construction I've found that can pass
2977 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2978 intermediates will work, because you'll get intermediate rounding
2979 that ruins the end result. Some of this could be fixed by turning
2980 on round-to-positive-infinity, but that requires diddling the fpsr,
2981 which kills performance. I tried turning this around and converting
2982 to a negative number, so that I could turn on /m, but either I did
2983 it wrong or there's something else cause I wound up with the exact
2984 same single-bit error. There is a branch-less form of this same code:
2995 fcmoveq $f10,$f11,$f0
2997 I'm not using it because it's the same number of instructions as
2998 this branch-full form, and it has more serialized long latency
2999 instructions on the critical path.
3001 For DFmode, we can avoid rounding errors by breaking up the word
3002 into two pieces, converting them separately, and adding them back:
3004 LC0: .long 0,0x5f800000
3009 cpyse $f11,$f31,$f10
3010 cpyse $f31,$f11,$f11
3018 This doesn't seem to be a clear-cut win over the optabs form.
3019 It probably all depends on the distribution of numbers being
3020 converted -- in the optabs form, all but high-bit-set has a
3021 much lower minimum execution time. */
3024 alpha_emit_floatuns (rtx operands
[2])
3026 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3027 enum machine_mode mode
;
3030 in
= force_reg (DImode
, operands
[1]);
3031 mode
= GET_MODE (out
);
3032 neglab
= gen_label_rtx ();
3033 donelab
= gen_label_rtx ();
3034 i0
= gen_reg_rtx (DImode
);
3035 i1
= gen_reg_rtx (DImode
);
3036 f0
= gen_reg_rtx (mode
);
3038 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3040 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3041 emit_jump_insn (gen_jump (donelab
));
3044 emit_label (neglab
);
3046 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3047 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3048 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3049 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3050 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3052 emit_label (donelab
);
3055 /* Generate the comparison for a conditional branch. */
3058 alpha_emit_conditional_branch (enum rtx_code code
)
3060 enum rtx_code cmp_code
, branch_code
;
3061 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3062 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3065 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3067 if (! TARGET_HAS_XFLOATING_LIBS
)
3070 /* X_floating library comparison functions return
3074 Convert the compare against the raw return value. */
3096 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3098 alpha_compare
.fp_p
= 0;
3101 /* The general case: fold the comparison code to the types of compares
3102 that we have, choosing the branch as necessary. */
3105 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3107 /* We have these compares: */
3108 cmp_code
= code
, branch_code
= NE
;
3113 /* These must be reversed. */
3114 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3117 case GE
: case GT
: case GEU
: case GTU
:
3118 /* For FP, we swap them, for INT, we reverse them. */
3119 if (alpha_compare
.fp_p
)
3121 cmp_code
= swap_condition (code
);
3123 tem
= op0
, op0
= op1
, op1
= tem
;
3127 cmp_code
= reverse_condition (code
);
3136 if (alpha_compare
.fp_p
)
3139 if (flag_unsafe_math_optimizations
)
3141 /* When we are not as concerned about non-finite values, and we
3142 are comparing against zero, we can branch directly. */
3143 if (op1
== CONST0_RTX (DFmode
))
3144 cmp_code
= NIL
, branch_code
= code
;
3145 else if (op0
== CONST0_RTX (DFmode
))
3147 /* Undo the swap we probably did just above. */
3148 tem
= op0
, op0
= op1
, op1
= tem
;
3149 branch_code
= swap_condition (cmp_code
);
3155 /* ??? We mark the branch mode to be CCmode to prevent the
3156 compare and branch from being combined, since the compare
3157 insn follows IEEE rules that the branch does not. */
3158 branch_mode
= CCmode
;
3165 /* The following optimizations are only for signed compares. */
3166 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3168 /* Whee. Compare and branch against 0 directly. */
3169 if (op1
== const0_rtx
)
3170 cmp_code
= NIL
, branch_code
= code
;
3172 /* If the constants doesn't fit into an immediate, but can
3173 be generated by lda/ldah, we adjust the argument and
3174 compare against zero, so we can use beq/bne directly. */
3175 else if (GET_CODE (op1
) == CONST_INT
&& (code
== EQ
|| code
== NE
))
3177 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3179 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3180 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3181 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3183 cmp_code
= PLUS
, branch_code
= code
;
3189 if (!reg_or_0_operand (op0
, DImode
))
3190 op0
= force_reg (DImode
, op0
);
3191 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3192 op1
= force_reg (DImode
, op1
);
3195 /* Emit an initial compare instruction, if necessary. */
3197 if (cmp_code
!= NIL
)
3199 tem
= gen_reg_rtx (cmp_mode
);
3200 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3203 /* Zero the operands. */
3204 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3206 /* Return the branch comparison. */
3207 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3210 /* Certain simplifications can be done to make invalid setcc operations
3211 valid. Return the final comparison, or NULL if we can't work. */
3214 alpha_emit_setcc (enum rtx_code code
)
3216 enum rtx_code cmp_code
;
3217 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3218 int fp_p
= alpha_compare
.fp_p
;
3221 /* Zero the operands. */
3222 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3224 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3226 if (! TARGET_HAS_XFLOATING_LIBS
)
3229 /* X_floating library comparison functions return
3233 Convert the compare against the raw return value. */
3235 if (code
== UNORDERED
|| code
== ORDERED
)
3240 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3244 if (code
== UNORDERED
)
3246 else if (code
== ORDERED
)
3252 if (fp_p
&& !TARGET_FIX
)
3255 /* The general case: fold the comparison code to the types of compares
3256 that we have, choosing the branch as necessary. */
3261 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3263 /* We have these compares. */
3265 cmp_code
= code
, code
= NE
;
3269 if (!fp_p
&& op1
== const0_rtx
)
3274 cmp_code
= reverse_condition (code
);
3278 case GE
: case GT
: case GEU
: case GTU
:
3279 /* These normally need swapping, but for integer zero we have
3280 special patterns that recognize swapped operands. */
3281 if (!fp_p
&& op1
== const0_rtx
)
3283 code
= swap_condition (code
);
3285 cmp_code
= code
, code
= NE
;
3286 tmp
= op0
, op0
= op1
, op1
= tmp
;
3295 if (!register_operand (op0
, DImode
))
3296 op0
= force_reg (DImode
, op0
);
3297 if (!reg_or_8bit_operand (op1
, DImode
))
3298 op1
= force_reg (DImode
, op1
);
3301 /* Emit an initial compare instruction, if necessary. */
3302 if (cmp_code
!= NIL
)
3304 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3306 tmp
= gen_reg_rtx (mode
);
3307 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3308 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3310 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3314 /* Return the setcc comparison. */
3315 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3319 /* Rewrite a comparison against zero CMP of the form
3320 (CODE (cc0) (const_int 0)) so it can be written validly in
3321 a conditional move (if_then_else CMP ...).
3322 If both of the operands that set cc0 are nonzero we must emit
3323 an insn to perform the compare (it can't be done within
3324 the conditional move). */
3327 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
3329 enum rtx_code code
= GET_CODE (cmp
);
3330 enum rtx_code cmov_code
= NE
;
3331 rtx op0
= alpha_compare
.op0
;
3332 rtx op1
= alpha_compare
.op1
;
3333 int fp_p
= alpha_compare
.fp_p
;
3334 enum machine_mode cmp_mode
3335 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3336 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3337 enum machine_mode cmov_mode
= VOIDmode
;
3338 int local_fast_math
= flag_unsafe_math_optimizations
;
3341 /* Zero the operands. */
3342 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3344 if (fp_p
!= FLOAT_MODE_P (mode
))
3346 enum rtx_code cmp_code
;
3351 /* If we have fp<->int register move instructions, do a cmov by
3352 performing the comparison in fp registers, and move the
3353 zero/nonzero value to integer registers, where we can then
3354 use a normal cmov, or vice-versa. */
3358 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3359 /* We have these compares. */
3360 cmp_code
= code
, code
= NE
;
3364 /* This must be reversed. */
3365 cmp_code
= EQ
, code
= EQ
;
3368 case GE
: case GT
: case GEU
: case GTU
:
3369 /* These normally need swapping, but for integer zero we have
3370 special patterns that recognize swapped operands. */
3371 if (!fp_p
&& op1
== const0_rtx
)
3372 cmp_code
= code
, code
= NE
;
3375 cmp_code
= swap_condition (code
);
3377 tem
= op0
, op0
= op1
, op1
= tem
;
3385 tem
= gen_reg_rtx (cmp_op_mode
);
3386 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3387 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3390 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3391 op0
= gen_lowpart (cmp_op_mode
, tem
);
3392 op1
= CONST0_RTX (cmp_op_mode
);
3394 local_fast_math
= 1;
3397 /* We may be able to use a conditional move directly.
3398 This avoids emitting spurious compares. */
3399 if (signed_comparison_operator (cmp
, VOIDmode
)
3400 && (!fp_p
|| local_fast_math
)
3401 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3402 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3404 /* We can't put the comparison inside the conditional move;
3405 emit a compare instruction and put that inside the
3406 conditional move. Make sure we emit only comparisons we have;
3407 swap or reverse as necessary. */
3414 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3415 /* We have these compares: */
3419 /* This must be reversed. */
3420 code
= reverse_condition (code
);
3424 case GE
: case GT
: case GEU
: case GTU
:
3425 /* These must be swapped. */
3426 if (op1
!= CONST0_RTX (cmp_mode
))
3428 code
= swap_condition (code
);
3429 tem
= op0
, op0
= op1
, op1
= tem
;
3439 if (!reg_or_0_operand (op0
, DImode
))
3440 op0
= force_reg (DImode
, op0
);
3441 if (!reg_or_8bit_operand (op1
, DImode
))
3442 op1
= force_reg (DImode
, op1
);
3445 /* ??? We mark the branch mode to be CCmode to prevent the compare
3446 and cmov from being combined, since the compare insn follows IEEE
3447 rules that the cmov does not. */
3448 if (fp_p
&& !local_fast_math
)
3451 tem
= gen_reg_rtx (cmp_op_mode
);
3452 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3453 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3456 /* Simplify a conditional move of two constants into a setcc with
3457 arithmetic. This is done with a splitter since combine would
3458 just undo the work if done during code generation. It also catches
3459 cases we wouldn't have before cse. */
3462 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
3463 rtx t_rtx
, rtx f_rtx
)
3465 HOST_WIDE_INT t
, f
, diff
;
3466 enum machine_mode mode
;
3467 rtx target
, subtarget
, tmp
;
3469 mode
= GET_MODE (dest
);
3474 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3475 || (code
== GE
|| code
== GT
))
3477 code
= reverse_condition (code
);
3478 diff
= t
, t
= f
, f
= diff
;
3482 subtarget
= target
= dest
;
3485 target
= gen_lowpart (DImode
, dest
);
3486 if (! no_new_pseudos
)
3487 subtarget
= gen_reg_rtx (DImode
);
3491 /* Below, we must be careful to use copy_rtx on target and subtarget
3492 in intermediate insns, as they may be a subreg rtx, which may not
3495 if (f
== 0 && exact_log2 (diff
) > 0
3496 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3497 viable over a longer latency cmove. On EV5, the E0 slot is a
3498 scarce resource, and on EV4 shift has the same latency as a cmove. */
3499 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3501 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3502 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3504 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3505 GEN_INT (exact_log2 (t
)));
3506 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3508 else if (f
== 0 && t
== -1)
3510 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3511 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3513 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3515 else if (diff
== 1 || diff
== 4 || diff
== 8)
3519 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3520 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3523 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3526 add_op
= GEN_INT (f
);
3527 if (sext_add_operand (add_op
, mode
))
3529 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3531 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3532 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3544 /* Look up the function X_floating library function name for the
3548 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
3552 const enum rtx_code code
;
3553 const char *const func
;
3556 static const struct xfloating_op vms_xfloating_ops
[] =
3558 { PLUS
, "OTS$ADD_X" },
3559 { MINUS
, "OTS$SUB_X" },
3560 { MULT
, "OTS$MUL_X" },
3561 { DIV
, "OTS$DIV_X" },
3562 { EQ
, "OTS$EQL_X" },
3563 { NE
, "OTS$NEQ_X" },
3564 { LT
, "OTS$LSS_X" },
3565 { LE
, "OTS$LEQ_X" },
3566 { GT
, "OTS$GTR_X" },
3567 { GE
, "OTS$GEQ_X" },
3568 { FIX
, "OTS$CVTXQ" },
3569 { FLOAT
, "OTS$CVTQX" },
3570 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3571 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3572 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3575 static const struct xfloating_op osf_xfloating_ops
[] =
3577 { PLUS
, "_OtsAddX" },
3578 { MINUS
, "_OtsSubX" },
3579 { MULT
, "_OtsMulX" },
3580 { DIV
, "_OtsDivX" },
3587 { FIX
, "_OtsCvtXQ" },
3588 { FLOAT
, "_OtsCvtQX" },
3589 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3590 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3591 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3594 const struct xfloating_op
*ops
;
3595 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3598 /* How irritating. Nothing to key off for the table. Hardcode
3599 knowledge of the G_floating routines. */
3600 if (TARGET_FLOAT_VAX
)
3602 if (TARGET_ABI_OPEN_VMS
)
3604 if (code
== FLOAT_EXTEND
)
3605 return "OTS$CVT_FLOAT_G_X";
3606 if (code
== FLOAT_TRUNCATE
)
3607 return "OTS$CVT_FLOAT_X_G";
3611 if (code
== FLOAT_EXTEND
)
3612 return "_OtsConvertFloatGX";
3613 if (code
== FLOAT_TRUNCATE
)
3614 return "_OtsConvertFloatXG";
3618 if (TARGET_ABI_OPEN_VMS
)
3619 ops
= vms_xfloating_ops
;
3621 ops
= osf_xfloating_ops
;
3623 for (i
= 0; i
< n
; ++i
)
3624 if (ops
[i
].code
== code
)
3630 /* Most X_floating operations take the rounding mode as an argument.
3631 Compute that here. */
3634 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
3635 enum alpha_fp_rounding_mode round
)
3641 case ALPHA_FPRM_NORM
:
3644 case ALPHA_FPRM_MINF
:
3647 case ALPHA_FPRM_CHOP
:
3650 case ALPHA_FPRM_DYN
:
3656 /* XXX For reference, round to +inf is mode = 3. */
3659 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3665 /* Emit an X_floating library function call.
3667 Note that these functions do not follow normal calling conventions:
3668 TFmode arguments are passed in two integer registers (as opposed to
3669 indirect); TFmode return values appear in R16+R17.
3671 FUNC is the function name to call.
3672 TARGET is where the output belongs.
3673 OPERANDS are the inputs.
3674 NOPERANDS is the count of inputs.
3675 EQUIV is the expression equivalent for the function.
3679 alpha_emit_xfloating_libcall (const char *func
, rtx target
, rtx operands
[],
3680 int noperands
, rtx equiv
)
3682 rtx usage
= NULL_RTX
, tmp
, reg
;
3687 for (i
= 0; i
< noperands
; ++i
)
3689 switch (GET_MODE (operands
[i
]))
3692 reg
= gen_rtx_REG (TFmode
, regno
);
3697 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3702 if (GET_CODE (operands
[i
]) != CONST_INT
)
3706 reg
= gen_rtx_REG (DImode
, regno
);
3714 emit_move_insn (reg
, operands
[i
]);
3715 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3718 switch (GET_MODE (target
))
3721 reg
= gen_rtx_REG (TFmode
, 16);
3724 reg
= gen_rtx_REG (DFmode
, 32);
3727 reg
= gen_rtx_REG (DImode
, 0);
3733 tmp
= gen_rtx_MEM (QImode
, init_one_libfunc (func
));
3734 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3735 const0_rtx
, const0_rtx
));
3736 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3741 emit_libcall_block (tmp
, target
, reg
, equiv
);
3744 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3747 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3751 rtx out_operands
[3];
3753 func
= alpha_lookup_xfloating_lib_func (code
);
3754 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3756 out_operands
[0] = operands
[1];
3757 out_operands
[1] = operands
[2];
3758 out_operands
[2] = GEN_INT (mode
);
3759 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3760 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3764 /* Emit an X_floating library function call for a comparison. */
3767 alpha_emit_xfloating_compare (enum rtx_code code
, rtx op0
, rtx op1
)
3770 rtx out
, operands
[2];
3772 func
= alpha_lookup_xfloating_lib_func (code
);
3776 out
= gen_reg_rtx (DImode
);
3778 /* ??? Strange mode for equiv because what's actually returned
3779 is -1,0,1, not a proper boolean value. */
3780 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3781 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3786 /* Emit an X_floating library function call for a conversion. */
3789 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3791 int noperands
= 1, mode
;
3792 rtx out_operands
[2];
3794 enum rtx_code code
= orig_code
;
3796 if (code
== UNSIGNED_FIX
)
3799 func
= alpha_lookup_xfloating_lib_func (code
);
3801 out_operands
[0] = operands
[1];
3806 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3807 out_operands
[1] = GEN_INT (mode
);
3810 case FLOAT_TRUNCATE
:
3811 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3812 out_operands
[1] = GEN_INT (mode
);
3819 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3820 gen_rtx_fmt_e (orig_code
,
3821 GET_MODE (operands
[0]),
3825 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3826 OP[0] into OP[0,1]. Naturally, output operand ordering is
3830 alpha_split_tfmode_pair (rtx operands
[4])
3832 if (GET_CODE (operands
[1]) == REG
)
3834 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3835 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3837 else if (GET_CODE (operands
[1]) == MEM
)
3839 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3840 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3842 else if (operands
[1] == CONST0_RTX (TFmode
))
3843 operands
[2] = operands
[3] = const0_rtx
;
3847 if (GET_CODE (operands
[0]) == REG
)
3849 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3850 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3852 else if (GET_CODE (operands
[0]) == MEM
)
3854 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3855 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3861 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3862 op2 is a register containing the sign bit, operation is the
3863 logical operation to be performed. */
3866 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3868 rtx high_bit
= operands
[2];
3872 alpha_split_tfmode_pair (operands
);
3874 /* Detect three flavors of operand overlap. */
3876 if (rtx_equal_p (operands
[0], operands
[2]))
3878 else if (rtx_equal_p (operands
[1], operands
[2]))
3880 if (rtx_equal_p (operands
[0], high_bit
))
3887 emit_move_insn (operands
[0], operands
[2]);
3889 /* ??? If the destination overlaps both source tf and high_bit, then
3890 assume source tf is dead in its entirety and use the other half
3891 for a scratch register. Otherwise "scratch" is just the proper
3892 destination register. */
3893 scratch
= operands
[move
< 2 ? 1 : 3];
3895 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3899 emit_move_insn (operands
[0], operands
[2]);
3901 emit_move_insn (operands
[1], scratch
);
3905 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3909 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3910 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3911 lda r3,X(r11) lda r3,X+2(r11)
3912 extwl r1,r3,r1 extql r1,r3,r1
3913 extwh r2,r3,r2 extqh r2,r3,r2
3914 or r1.r2.r1 or r1,r2,r1
3917 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3918 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3919 lda r3,X(r11) lda r3,X(r11)
3920 extll r1,r3,r1 extll r1,r3,r1
3921 extlh r2,r3,r2 extlh r2,r3,r2
3922 or r1.r2.r1 addl r1,r2,r1
3924 quad: ldq_u r1,X(r11)
3933 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3934 HOST_WIDE_INT ofs
, int sign
)
3936 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3937 enum machine_mode mode
;
3939 meml
= gen_reg_rtx (DImode
);
3940 memh
= gen_reg_rtx (DImode
);
3941 addr
= gen_reg_rtx (DImode
);
3942 extl
= gen_reg_rtx (DImode
);
3943 exth
= gen_reg_rtx (DImode
);
3945 mema
= XEXP (mem
, 0);
3946 if (GET_CODE (mema
) == LO_SUM
)
3947 mema
= force_reg (Pmode
, mema
);
3949 /* AND addresses cannot be in any alias set, since they may implicitly
3950 alias surrounding code. Ideally we'd have some alias set that
3951 covered all types except those with alignment 8 or higher. */
3953 tmp
= change_address (mem
, DImode
,
3954 gen_rtx_AND (DImode
,
3955 plus_constant (mema
, ofs
),
3957 set_mem_alias_set (tmp
, 0);
3958 emit_move_insn (meml
, tmp
);
3960 tmp
= change_address (mem
, DImode
,
3961 gen_rtx_AND (DImode
,
3962 plus_constant (mema
, ofs
+ size
- 1),
3964 set_mem_alias_set (tmp
, 0);
3965 emit_move_insn (memh
, tmp
);
3967 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3969 emit_move_insn (addr
, plus_constant (mema
, -1));
3971 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3972 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3974 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3975 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3976 addr
, 1, OPTAB_WIDEN
);
3978 else if (sign
&& size
== 2)
3980 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3982 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3983 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3985 /* We must use tgt here for the target. Alpha-vms port fails if we use
3986 addr for the target, because addr is marked as a pointer and combine
3987 knows that pointers are always sign-extended 32 bit values. */
3988 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3989 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3990 addr
, 1, OPTAB_WIDEN
);
3994 if (WORDS_BIG_ENDIAN
)
3996 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4000 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4005 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4010 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4017 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4021 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4022 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4026 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4031 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4036 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4045 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4046 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4051 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4054 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4057 alpha_expand_unaligned_store (rtx dst
, rtx src
,
4058 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
4060 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4062 dstl
= gen_reg_rtx (DImode
);
4063 dsth
= gen_reg_rtx (DImode
);
4064 insl
= gen_reg_rtx (DImode
);
4065 insh
= gen_reg_rtx (DImode
);
4067 dsta
= XEXP (dst
, 0);
4068 if (GET_CODE (dsta
) == LO_SUM
)
4069 dsta
= force_reg (Pmode
, dsta
);
4071 /* AND addresses cannot be in any alias set, since they may implicitly
4072 alias surrounding code. Ideally we'd have some alias set that
4073 covered all types except those with alignment 8 or higher. */
4075 meml
= change_address (dst
, DImode
,
4076 gen_rtx_AND (DImode
,
4077 plus_constant (dsta
, ofs
),
4079 set_mem_alias_set (meml
, 0);
4081 memh
= change_address (dst
, DImode
,
4082 gen_rtx_AND (DImode
,
4083 plus_constant (dsta
, ofs
+ size
- 1),
4085 set_mem_alias_set (memh
, 0);
4087 emit_move_insn (dsth
, memh
);
4088 emit_move_insn (dstl
, meml
);
4089 if (WORDS_BIG_ENDIAN
)
4091 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4093 if (src
!= const0_rtx
)
4098 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4101 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4104 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4107 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4108 GEN_INT (size
*8), addr
));
4114 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4118 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4119 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4123 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4127 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4131 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4133 if (src
!= const0_rtx
)
4135 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4136 GEN_INT (size
*8), addr
));
4141 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4144 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4147 emit_insn (gen_insql_le (insl
, src
, addr
));
4152 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4157 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4161 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4162 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4166 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4171 if (src
!= const0_rtx
)
4173 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4174 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4177 if (WORDS_BIG_ENDIAN
)
4179 emit_move_insn (meml
, dstl
);
4180 emit_move_insn (memh
, dsth
);
4184 /* Must store high before low for degenerate case of aligned. */
4185 emit_move_insn (memh
, dsth
);
4186 emit_move_insn (meml
, dstl
);
4190 /* The block move code tries to maximize speed by separating loads and
4191 stores at the expense of register pressure: we load all of the data
4192 before we store it back out. There are two secondary effects worth
4193 mentioning, that this speeds copying to/from aligned and unaligned
4194 buffers, and that it makes the code significantly easier to write. */
4196 #define MAX_MOVE_WORDS 8
4198 /* Load an integral number of consecutive unaligned quadwords. */
4201 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
4202 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4204 rtx
const im8
= GEN_INT (-8);
4205 rtx
const i64
= GEN_INT (64);
4206 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4207 rtx sreg
, areg
, tmp
, smema
;
4210 smema
= XEXP (smem
, 0);
4211 if (GET_CODE (smema
) == LO_SUM
)
4212 smema
= force_reg (Pmode
, smema
);
4214 /* Generate all the tmp registers we need. */
4215 for (i
= 0; i
< words
; ++i
)
4217 data_regs
[i
] = out_regs
[i
];
4218 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4220 data_regs
[words
] = gen_reg_rtx (DImode
);
4223 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4225 /* Load up all of the source data. */
4226 for (i
= 0; i
< words
; ++i
)
4228 tmp
= change_address (smem
, DImode
,
4229 gen_rtx_AND (DImode
,
4230 plus_constant (smema
, 8*i
),
4232 set_mem_alias_set (tmp
, 0);
4233 emit_move_insn (data_regs
[i
], tmp
);
4236 tmp
= change_address (smem
, DImode
,
4237 gen_rtx_AND (DImode
,
4238 plus_constant (smema
, 8*words
- 1),
4240 set_mem_alias_set (tmp
, 0);
4241 emit_move_insn (data_regs
[words
], tmp
);
4243 /* Extract the half-word fragments. Unfortunately DEC decided to make
4244 extxh with offset zero a noop instead of zeroing the register, so
4245 we must take care of that edge condition ourselves with cmov. */
4247 sreg
= copy_addr_to_reg (smema
);
4248 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4250 if (WORDS_BIG_ENDIAN
)
4251 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4252 for (i
= 0; i
< words
; ++i
)
4254 if (WORDS_BIG_ENDIAN
)
4256 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4257 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4261 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4262 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4264 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4265 gen_rtx_IF_THEN_ELSE (DImode
,
4266 gen_rtx_EQ (DImode
, areg
,
4268 const0_rtx
, ext_tmps
[i
])));
4271 /* Merge the half-words into whole words. */
4272 for (i
= 0; i
< words
; ++i
)
4274 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4275 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4279 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4280 may be NULL to store zeros. */
4283 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
4284 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4286 rtx
const im8
= GEN_INT (-8);
4287 rtx
const i64
= GEN_INT (64);
4288 rtx ins_tmps
[MAX_MOVE_WORDS
];
4289 rtx st_tmp_1
, st_tmp_2
, dreg
;
4290 rtx st_addr_1
, st_addr_2
, dmema
;
4293 dmema
= XEXP (dmem
, 0);
4294 if (GET_CODE (dmema
) == LO_SUM
)
4295 dmema
= force_reg (Pmode
, dmema
);
4297 /* Generate all the tmp registers we need. */
4298 if (data_regs
!= NULL
)
4299 for (i
= 0; i
< words
; ++i
)
4300 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4301 st_tmp_1
= gen_reg_rtx(DImode
);
4302 st_tmp_2
= gen_reg_rtx(DImode
);
4305 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4307 st_addr_2
= change_address (dmem
, DImode
,
4308 gen_rtx_AND (DImode
,
4309 plus_constant (dmema
, words
*8 - 1),
4311 set_mem_alias_set (st_addr_2
, 0);
4313 st_addr_1
= change_address (dmem
, DImode
,
4314 gen_rtx_AND (DImode
, dmema
, im8
));
4315 set_mem_alias_set (st_addr_1
, 0);
4317 /* Load up the destination end bits. */
4318 emit_move_insn (st_tmp_2
, st_addr_2
);
4319 emit_move_insn (st_tmp_1
, st_addr_1
);
4321 /* Shift the input data into place. */
4322 dreg
= copy_addr_to_reg (dmema
);
4323 if (WORDS_BIG_ENDIAN
)
4324 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4325 if (data_regs
!= NULL
)
4327 for (i
= words
-1; i
>= 0; --i
)
4329 if (WORDS_BIG_ENDIAN
)
4331 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4332 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4336 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4337 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4340 for (i
= words
-1; i
> 0; --i
)
4342 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4343 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4348 /* Split and merge the ends with the destination data. */
4349 if (WORDS_BIG_ENDIAN
)
4351 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4352 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4356 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4357 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4360 if (data_regs
!= NULL
)
4362 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4363 st_tmp_2
, 1, OPTAB_WIDEN
);
4364 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4365 st_tmp_1
, 1, OPTAB_WIDEN
);
4369 if (WORDS_BIG_ENDIAN
)
4370 emit_move_insn (st_addr_1
, st_tmp_1
);
4372 emit_move_insn (st_addr_2
, st_tmp_2
);
4373 for (i
= words
-1; i
> 0; --i
)
4375 rtx tmp
= change_address (dmem
, DImode
,
4376 gen_rtx_AND (DImode
,
4377 plus_constant(dmema
,
4378 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4380 set_mem_alias_set (tmp
, 0);
4381 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4383 if (WORDS_BIG_ENDIAN
)
4384 emit_move_insn (st_addr_2
, st_tmp_2
);
4386 emit_move_insn (st_addr_1
, st_tmp_1
);
4390 /* Expand string/block move operations.
4392 operands[0] is the pointer to the destination.
4393 operands[1] is the pointer to the source.
4394 operands[2] is the number of bytes to move.
4395 operands[3] is the alignment. */
4398 alpha_expand_block_move (rtx operands
[])
4400 rtx bytes_rtx
= operands
[2];
4401 rtx align_rtx
= operands
[3];
4402 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4403 HOST_WIDE_INT bytes
= orig_bytes
;
4404 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4405 HOST_WIDE_INT dst_align
= src_align
;
4406 rtx orig_src
= operands
[1];
4407 rtx orig_dst
= operands
[0];
4408 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4410 unsigned int i
, words
, ofs
, nregs
= 0;
4412 if (orig_bytes
<= 0)
4414 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4417 /* Look for additional alignment information from recorded register info. */
4419 tmp
= XEXP (orig_src
, 0);
4420 if (GET_CODE (tmp
) == REG
)
4421 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4422 else if (GET_CODE (tmp
) == PLUS
4423 && GET_CODE (XEXP (tmp
, 0)) == REG
4424 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4426 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4427 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4431 if (a
>= 64 && c
% 8 == 0)
4433 else if (a
>= 32 && c
% 4 == 0)
4435 else if (a
>= 16 && c
% 2 == 0)
4440 tmp
= XEXP (orig_dst
, 0);
4441 if (GET_CODE (tmp
) == REG
)
4442 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4443 else if (GET_CODE (tmp
) == PLUS
4444 && GET_CODE (XEXP (tmp
, 0)) == REG
4445 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4447 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4448 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4452 if (a
>= 64 && c
% 8 == 0)
4454 else if (a
>= 32 && c
% 4 == 0)
4456 else if (a
>= 16 && c
% 2 == 0)
4461 /* Load the entire block into registers. */
4462 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4464 enum machine_mode mode
;
4466 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4468 /* Don't use the existing register if we're reading more than
4469 is held in the register. Nor if there is not a mode that
4470 handles the exact size. */
4471 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4472 if (GET_CODE (tmp
) == REG
4474 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4478 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4479 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4483 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4488 /* No appropriate mode; fall back on memory. */
4489 orig_src
= replace_equiv_address (orig_src
,
4490 copy_addr_to_reg (XEXP (orig_src
, 0)));
4491 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4495 if (src_align
>= 64 && bytes
>= 8)
4499 for (i
= 0; i
< words
; ++i
)
4500 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4502 for (i
= 0; i
< words
; ++i
)
4503 emit_move_insn (data_regs
[nregs
+ i
],
4504 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4511 if (src_align
>= 32 && bytes
>= 4)
4515 for (i
= 0; i
< words
; ++i
)
4516 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4518 for (i
= 0; i
< words
; ++i
)
4519 emit_move_insn (data_regs
[nregs
+ i
],
4520 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4531 for (i
= 0; i
< words
+1; ++i
)
4532 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4534 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4542 if (! TARGET_BWX
&& bytes
>= 4)
4544 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4545 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4552 if (src_align
>= 16)
4555 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4556 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4559 } while (bytes
>= 2);
4561 else if (! TARGET_BWX
)
4563 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4564 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4572 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4573 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4580 if (nregs
> ARRAY_SIZE (data_regs
))
4583 /* Now save it back out again. */
4587 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4589 enum machine_mode mode
;
4590 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4592 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4593 if (GET_CODE (tmp
) == REG
&& GET_MODE (tmp
) == mode
)
4597 emit_move_insn (tmp
, data_regs
[0]);
4602 else if (nregs
== 2 && mode
== TImode
)
4604 /* Undo the subregging done above when copying between
4605 two TImode registers. */
4606 if (GET_CODE (data_regs
[0]) == SUBREG
4607 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4608 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4614 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4615 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4619 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4620 data_regs
[1], NULL_RTX
);
4628 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4629 /* ??? Optimize mode < dst_mode with strict_low_part. */
4631 /* No appropriate mode; fall back on memory. We can speed things
4632 up by recognizing extra alignment information. */
4633 orig_dst
= replace_equiv_address (orig_dst
,
4634 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4635 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4638 /* Write out the data in whatever chunks reading the source allowed. */
4639 if (dst_align
>= 64)
4641 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4643 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4650 if (dst_align
>= 32)
4652 /* If the source has remaining DImode regs, write them out in
4654 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4656 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4657 NULL_RTX
, 1, OPTAB_WIDEN
);
4659 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4660 gen_lowpart (SImode
, data_regs
[i
]));
4661 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4662 gen_lowpart (SImode
, tmp
));
4667 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4669 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4676 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4678 /* Write out a remaining block of words using unaligned methods. */
4680 for (words
= 1; i
+ words
< nregs
; words
++)
4681 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4685 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4687 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4694 /* Due to the above, this won't be aligned. */
4695 /* ??? If we have more than one of these, consider constructing full
4696 words in registers and using alpha_expand_unaligned_store_words. */
4697 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4699 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4704 if (dst_align
>= 16)
4705 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4707 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4712 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4714 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4719 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4721 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4735 alpha_expand_block_clear (rtx operands
[])
4737 rtx bytes_rtx
= operands
[1];
4738 rtx align_rtx
= operands
[2];
4739 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4740 HOST_WIDE_INT bytes
= orig_bytes
;
4741 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4742 HOST_WIDE_INT alignofs
= 0;
4743 rtx orig_dst
= operands
[0];
4745 int i
, words
, ofs
= 0;
4747 if (orig_bytes
<= 0)
4749 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4752 /* Look for stricter alignment. */
4753 tmp
= XEXP (orig_dst
, 0);
4754 if (GET_CODE (tmp
) == REG
)
4755 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4756 else if (GET_CODE (tmp
) == PLUS
4757 && GET_CODE (XEXP (tmp
, 0)) == REG
4758 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4760 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4761 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4766 align
= a
, alignofs
= 8 - c
% 8;
4768 align
= a
, alignofs
= 4 - c
% 4;
4770 align
= a
, alignofs
= 2 - c
% 2;
4773 else if (GET_CODE (tmp
) == ADDRESSOF
)
4775 enum machine_mode mode
;
4777 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4778 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4780 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4784 /* No appropriate mode; fall back on memory. */
4785 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4786 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4789 /* Handle an unaligned prefix first. */
4793 #if HOST_BITS_PER_WIDE_INT >= 64
4794 /* Given that alignofs is bounded by align, the only time BWX could
4795 generate three stores is for a 7 byte fill. Prefer two individual
4796 stores over a load/mask/store sequence. */
4797 if ((!TARGET_BWX
|| alignofs
== 7)
4799 && !(alignofs
== 4 && bytes
>= 4))
4801 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4802 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4806 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4807 set_mem_alias_set (mem
, 0);
4809 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4810 if (bytes
< alignofs
)
4812 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4823 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4824 NULL_RTX
, 1, OPTAB_WIDEN
);
4826 emit_move_insn (mem
, tmp
);
4830 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4832 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4837 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4839 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4844 if (alignofs
== 4 && bytes
>= 4)
4846 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4852 /* If we've not used the extra lead alignment information by now,
4853 we won't be able to. Downgrade align to match what's left over. */
4856 alignofs
= alignofs
& -alignofs
;
4857 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4861 /* Handle a block of contiguous long-words. */
4863 if (align
>= 64 && bytes
>= 8)
4867 for (i
= 0; i
< words
; ++i
)
4868 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4875 /* If the block is large and appropriately aligned, emit a single
4876 store followed by a sequence of stq_u insns. */
4878 if (align
>= 32 && bytes
> 16)
4882 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4886 orig_dsta
= XEXP (orig_dst
, 0);
4887 if (GET_CODE (orig_dsta
) == LO_SUM
)
4888 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4891 for (i
= 0; i
< words
; ++i
)
4894 = change_address (orig_dst
, DImode
,
4895 gen_rtx_AND (DImode
,
4896 plus_constant (orig_dsta
, ofs
+ i
*8),
4898 set_mem_alias_set (mem
, 0);
4899 emit_move_insn (mem
, const0_rtx
);
4902 /* Depending on the alignment, the first stq_u may have overlapped
4903 with the initial stl, which means that the last stq_u didn't
4904 write as much as it would appear. Leave those questionable bytes
4906 bytes
-= words
* 8 - 4;
4907 ofs
+= words
* 8 - 4;
4910 /* Handle a smaller block of aligned words. */
4912 if ((align
>= 64 && bytes
== 4)
4913 || (align
== 32 && bytes
>= 4))
4917 for (i
= 0; i
< words
; ++i
)
4918 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4925 /* An unaligned block uses stq_u stores for as many as possible. */
4931 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4937 /* Next clean up any trailing pieces. */
4939 #if HOST_BITS_PER_WIDE_INT >= 64
4940 /* Count the number of bits in BYTES for which aligned stores could
4943 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4947 /* If we have appropriate alignment (and it wouldn't take too many
4948 instructions otherwise), mask out the bytes we need. */
4949 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4956 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4957 set_mem_alias_set (mem
, 0);
4959 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4961 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4962 NULL_RTX
, 1, OPTAB_WIDEN
);
4964 emit_move_insn (mem
, tmp
);
4967 else if (align
>= 32 && bytes
< 4)
4972 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4973 set_mem_alias_set (mem
, 0);
4975 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4977 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4978 NULL_RTX
, 1, OPTAB_WIDEN
);
4980 emit_move_insn (mem
, tmp
);
4986 if (!TARGET_BWX
&& bytes
>= 4)
4988 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4998 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5002 } while (bytes
>= 2);
5004 else if (! TARGET_BWX
)
5006 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5014 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5022 /* Returns a mask so that zap(x, value) == x & mask. */
5025 alpha_expand_zap_mask (HOST_WIDE_INT value
)
5030 if (HOST_BITS_PER_WIDE_INT
>= 64)
5032 HOST_WIDE_INT mask
= 0;
5034 for (i
= 7; i
>= 0; --i
)
5037 if (!((value
>> i
) & 1))
5041 result
= gen_int_mode (mask
, DImode
);
5043 else if (HOST_BITS_PER_WIDE_INT
== 32)
5045 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5047 for (i
= 7; i
>= 4; --i
)
5050 if (!((value
>> i
) & 1))
5054 for (i
= 3; i
>= 0; --i
)
5057 if (!((value
>> i
) & 1))
5061 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5070 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
5071 enum machine_mode mode
,
5072 rtx op0
, rtx op1
, rtx op2
)
5074 op0
= gen_lowpart (mode
, op0
);
5076 if (op1
== const0_rtx
)
5077 op1
= CONST0_RTX (mode
);
5079 op1
= gen_lowpart (mode
, op1
);
5081 if (op2
== const0_rtx
)
5082 op2
= CONST0_RTX (mode
);
5084 op2
= gen_lowpart (mode
, op2
);
5086 emit_insn ((*gen
) (op0
, op1
, op2
));
5089 /* Adjust the cost of a scheduling dependency. Return the new cost of
5090 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5093 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5095 enum attr_type insn_type
, dep_insn_type
;
5097 /* If the dependence is an anti-dependence, there is no cost. For an
5098 output dependence, there is sometimes a cost, but it doesn't seem
5099 worth handling those few cases. */
5100 if (REG_NOTE_KIND (link
) != 0)
5103 /* If we can't recognize the insns, we can't really do anything. */
5104 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5107 insn_type
= get_attr_type (insn
);
5108 dep_insn_type
= get_attr_type (dep_insn
);
5110 /* Bring in the user-defined memory latency. */
5111 if (dep_insn_type
== TYPE_ILD
5112 || dep_insn_type
== TYPE_FLD
5113 || dep_insn_type
== TYPE_LDSYM
)
5114 cost
+= alpha_memory_latency
-1;
5116 /* Everything else handled in DFA bypasses now. */
5121 /* The number of instructions that can be issued per cycle. */
5124 alpha_issue_rate (void)
5126 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5130 alpha_use_dfa_pipeline_interface (void)
5135 /* How many alternative schedules to try. This should be as wide as the
5136 scheduling freedom in the DFA, but no wider. Making this value too
5137 large results extra work for the scheduler.
5139 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5140 alternative schedules. For EV5, we can choose between E0/E1 and
5141 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5144 alpha_multipass_dfa_lookahead (void)
5146 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5149 /* Machine-specific function data. */
5151 struct machine_function
GTY(())
5154 /* List of call information words for calls from this function. */
5155 struct rtx_def
*first_ciw
;
5156 struct rtx_def
*last_ciw
;
5159 /* List of deferred case vectors. */
5160 struct rtx_def
*addr_list
;
5163 const char *some_ld_name
;
5166 /* How to allocate a 'struct machine_function'. */
5168 static struct machine_function
*
5169 alpha_init_machine_status (void)
5171 return ((struct machine_function
*)
5172 ggc_alloc_cleared (sizeof (struct machine_function
)));
5175 /* Functions to save and restore alpha_return_addr_rtx. */
5177 /* Start the ball rolling with RETURN_ADDR_RTX. */
5180 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
5185 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5188 /* Return or create a pseudo containing the gp value for the current
5189 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5192 alpha_gp_save_rtx (void)
5194 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5195 if (GET_CODE (r
) != MEM
)
5196 r
= gen_mem_addressof (r
, NULL_TREE
, /*rescan=*/true);
5201 alpha_ra_ever_killed (void)
5205 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5206 return regs_ever_live
[REG_RA
];
5208 push_topmost_sequence ();
5210 pop_topmost_sequence ();
5212 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5216 /* Return the trap mode suffix applicable to the current
5217 instruction, or NULL. */
5220 get_trap_mode_suffix (void)
5222 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5226 case TRAP_SUFFIX_NONE
:
5229 case TRAP_SUFFIX_SU
:
5230 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5234 case TRAP_SUFFIX_SUI
:
5235 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5239 case TRAP_SUFFIX_V_SV
:
5247 case ALPHA_FPTM_SUI
:
5252 case TRAP_SUFFIX_V_SV_SVI
:
5261 case ALPHA_FPTM_SUI
:
5266 case TRAP_SUFFIX_U_SU_SUI
:
5275 case ALPHA_FPTM_SUI
:
5283 /* Return the rounding mode suffix applicable to the current
5284 instruction, or NULL. */
5287 get_round_mode_suffix (void)
5289 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5293 case ROUND_SUFFIX_NONE
:
5295 case ROUND_SUFFIX_NORMAL
:
5298 case ALPHA_FPRM_NORM
:
5300 case ALPHA_FPRM_MINF
:
5302 case ALPHA_FPRM_CHOP
:
5304 case ALPHA_FPRM_DYN
:
5309 case ROUND_SUFFIX_C
:
5315 /* Locate some local-dynamic symbol still in use by this function
5316 so that we can print its name in some movdi_er_tlsldm pattern. */
5319 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5323 if (GET_CODE (x
) == SYMBOL_REF
5324 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5326 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5334 get_some_local_dynamic_name (void)
5338 if (cfun
->machine
->some_ld_name
)
5339 return cfun
->machine
->some_ld_name
;
5341 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5343 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5344 return cfun
->machine
->some_ld_name
;
5349 /* Print an operand. Recognize special options, documented below. */
5352 print_operand (FILE *file
, rtx x
, int code
)
5359 /* Print the assembler name of the current function. */
5360 assemble_name (file
, alpha_fnname
);
5364 assemble_name (file
, get_some_local_dynamic_name ());
5369 const char *trap
= get_trap_mode_suffix ();
5370 const char *round
= get_round_mode_suffix ();
5373 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5374 (trap
? trap
: ""), (round
? round
: ""));
5379 /* Generates single precision instruction suffix. */
5380 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5384 /* Generates double precision instruction suffix. */
5385 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5389 /* Generates a nop after a noreturn call at the very end of the
5391 if (next_real_insn (current_output_insn
) == 0)
5392 fprintf (file
, "\n\tnop");
5396 if (alpha_this_literal_sequence_number
== 0)
5397 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5398 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5402 if (alpha_this_gpdisp_sequence_number
== 0)
5403 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5404 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5408 if (GET_CODE (x
) == HIGH
)
5409 output_addr_const (file
, XEXP (x
, 0));
5411 output_operand_lossage ("invalid %%H value");
5418 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5420 x
= XVECEXP (x
, 0, 0);
5421 lituse
= "lituse_tlsgd";
5423 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5425 x
= XVECEXP (x
, 0, 0);
5426 lituse
= "lituse_tlsldm";
5428 else if (GET_CODE (x
) == CONST_INT
)
5429 lituse
= "lituse_jsr";
5432 output_operand_lossage ("invalid %%J value");
5436 if (x
!= const0_rtx
)
5437 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5442 /* If this operand is the constant zero, write it as "$31". */
5443 if (GET_CODE (x
) == REG
)
5444 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5445 else if (x
== CONST0_RTX (GET_MODE (x
)))
5446 fprintf (file
, "$31");
5448 output_operand_lossage ("invalid %%r value");
5452 /* Similar, but for floating-point. */
5453 if (GET_CODE (x
) == REG
)
5454 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5455 else if (x
== CONST0_RTX (GET_MODE (x
)))
5456 fprintf (file
, "$f31");
5458 output_operand_lossage ("invalid %%R value");
5462 /* Write the 1's complement of a constant. */
5463 if (GET_CODE (x
) != CONST_INT
)
5464 output_operand_lossage ("invalid %%N value");
5466 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5470 /* Write 1 << C, for a constant C. */
5471 if (GET_CODE (x
) != CONST_INT
)
5472 output_operand_lossage ("invalid %%P value");
5474 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5478 /* Write the high-order 16 bits of a constant, sign-extended. */
5479 if (GET_CODE (x
) != CONST_INT
)
5480 output_operand_lossage ("invalid %%h value");
5482 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5486 /* Write the low-order 16 bits of a constant, sign-extended. */
5487 if (GET_CODE (x
) != CONST_INT
)
5488 output_operand_lossage ("invalid %%L value");
5490 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5491 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5495 /* Write mask for ZAP insn. */
5496 if (GET_CODE (x
) == CONST_DOUBLE
)
5498 HOST_WIDE_INT mask
= 0;
5499 HOST_WIDE_INT value
;
5501 value
= CONST_DOUBLE_LOW (x
);
5502 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5507 value
= CONST_DOUBLE_HIGH (x
);
5508 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5511 mask
|= (1 << (i
+ sizeof (int)));
5513 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5516 else if (GET_CODE (x
) == CONST_INT
)
5518 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5520 for (i
= 0; i
< 8; i
++, value
>>= 8)
5524 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5527 output_operand_lossage ("invalid %%m value");
5531 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5532 if (GET_CODE (x
) != CONST_INT
5533 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5534 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5535 output_operand_lossage ("invalid %%M value");
5537 fprintf (file
, "%s",
5538 (INTVAL (x
) == 8 ? "b"
5539 : INTVAL (x
) == 16 ? "w"
5540 : INTVAL (x
) == 32 ? "l"
5545 /* Similar, except do it from the mask. */
5546 if (GET_CODE (x
) == CONST_INT
)
5548 HOST_WIDE_INT value
= INTVAL (x
);
5555 if (value
== 0xffff)
5560 if (value
== 0xffffffff)
5571 else if (HOST_BITS_PER_WIDE_INT
== 32
5572 && GET_CODE (x
) == CONST_DOUBLE
5573 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5574 && CONST_DOUBLE_HIGH (x
) == 0)
5579 output_operand_lossage ("invalid %%U value");
5583 /* Write the constant value divided by 8 for little-endian mode or
5584 (56 - value) / 8 for big-endian mode. */
5586 if (GET_CODE (x
) != CONST_INT
5587 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5590 || (INTVAL (x
) & 7) != 0)
5591 output_operand_lossage ("invalid %%s value");
5593 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5595 ? (56 - INTVAL (x
)) / 8
5600 /* Same, except compute (64 - c) / 8 */
5602 if (GET_CODE (x
) != CONST_INT
5603 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5604 && (INTVAL (x
) & 7) != 8)
5605 output_operand_lossage ("invalid %%s value");
5607 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5612 /* On Unicos/Mk systems: use a DEX expression if the symbol
5613 clashes with a register name. */
5614 int dex
= unicosmk_need_dex (x
);
5616 fprintf (file
, "DEX(%d)", dex
);
5618 output_addr_const (file
, x
);
5622 case 'C': case 'D': case 'c': case 'd':
5623 /* Write out comparison name. */
5625 enum rtx_code c
= GET_CODE (x
);
5627 if (GET_RTX_CLASS (c
) != '<')
5628 output_operand_lossage ("invalid %%C value");
5630 else if (code
== 'D')
5631 c
= reverse_condition (c
);
5632 else if (code
== 'c')
5633 c
= swap_condition (c
);
5634 else if (code
== 'd')
5635 c
= swap_condition (reverse_condition (c
));
5638 fprintf (file
, "ule");
5640 fprintf (file
, "ult");
5641 else if (c
== UNORDERED
)
5642 fprintf (file
, "un");
5644 fprintf (file
, "%s", GET_RTX_NAME (c
));
5649 /* Write the divide or modulus operator. */
5650 switch (GET_CODE (x
))
5653 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5656 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5659 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5662 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5665 output_operand_lossage ("invalid %%E value");
5671 /* Write "_u" for unaligned access. */
5672 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5673 fprintf (file
, "_u");
5677 if (GET_CODE (x
) == REG
)
5678 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5679 else if (GET_CODE (x
) == MEM
)
5680 output_address (XEXP (x
, 0));
5681 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5683 switch (XINT (XEXP (x
, 0), 1))
5687 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5690 output_operand_lossage ("unknown relocation unspec");
5695 output_addr_const (file
, x
);
5699 output_operand_lossage ("invalid %%xn code");
5704 print_operand_address (FILE *file
, rtx addr
)
5707 HOST_WIDE_INT offset
= 0;
5709 if (GET_CODE (addr
) == AND
)
5710 addr
= XEXP (addr
, 0);
5712 if (GET_CODE (addr
) == PLUS
5713 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5715 offset
= INTVAL (XEXP (addr
, 1));
5716 addr
= XEXP (addr
, 0);
5719 if (GET_CODE (addr
) == LO_SUM
)
5721 const char *reloc16
, *reloclo
;
5722 rtx op1
= XEXP (addr
, 1);
5724 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5726 op1
= XEXP (op1
, 0);
5727 switch (XINT (op1
, 1))
5731 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5735 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5738 output_operand_lossage ("unknown relocation unspec");
5742 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5747 reloclo
= "gprellow";
5748 output_addr_const (file
, op1
);
5752 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5754 addr
= XEXP (addr
, 0);
5755 if (GET_CODE (addr
) == REG
)
5756 basereg
= REGNO (addr
);
5757 else if (GET_CODE (addr
) == SUBREG
5758 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5759 basereg
= subreg_regno (addr
);
5763 fprintf (file
, "($%d)\t\t!%s", basereg
,
5764 (basereg
== 29 ? reloc16
: reloclo
));
5768 if (GET_CODE (addr
) == REG
)
5769 basereg
= REGNO (addr
);
5770 else if (GET_CODE (addr
) == SUBREG
5771 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5772 basereg
= subreg_regno (addr
);
5773 else if (GET_CODE (addr
) == CONST_INT
)
5774 offset
= INTVAL (addr
);
5776 #if TARGET_ABI_OPEN_VMS
5777 else if (GET_CODE (addr
) == SYMBOL_REF
)
5779 fprintf (file
, "%s", XSTR (addr
, 0));
5782 else if (GET_CODE (addr
) == CONST
5783 && GET_CODE (XEXP (addr
, 0)) == PLUS
5784 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5786 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5787 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5788 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5796 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5799 /* Emit RTL insns to initialize the variable parts of a trampoline at
5800 TRAMP. FNADDR is an RTX for the address of the function's pure
5801 code. CXT is an RTX for the static chain value for the function.
5803 The three offset parameters are for the individual template's
5804 layout. A JMPOFS < 0 indicates that the trampoline does not
5805 contain instructions at all.
5807 We assume here that a function will be called many more times than
5808 its address is taken (e.g., it might be passed to qsort), so we
5809 take the trouble to initialize the "hint" field in the JMP insn.
5810 Note that the hint field is PC (new) + 4 * bits 13:0. */
5813 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5814 int fnofs
, int cxtofs
, int jmpofs
)
5816 rtx temp
, temp1
, addr
;
5817 /* VMS really uses DImode pointers in memory at this point. */
5818 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5820 #ifdef POINTERS_EXTEND_UNSIGNED
5821 fnaddr
= convert_memory_address (mode
, fnaddr
);
5822 cxt
= convert_memory_address (mode
, cxt
);
5825 /* Store function address and CXT. */
5826 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5827 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5828 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5829 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5831 /* This has been disabled since the hint only has a 32k range, and in
5832 no existing OS is the stack within 32k of the text segment. */
5833 if (0 && jmpofs
>= 0)
5835 /* Compute hint value. */
5836 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5837 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5839 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5840 build_int_2 (2, 0), NULL_RTX
, 1);
5841 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5842 GEN_INT (0x3fff), 0);
5844 /* Merge in the hint. */
5845 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5846 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5847 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5848 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5850 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5853 #ifdef TRANSFER_FROM_TRAMPOLINE
5854 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5855 0, VOIDmode
, 1, tramp
, Pmode
);
5859 emit_insn (gen_imb ());
5862 /* Determine where to put an argument to a function.
5863 Value is zero to push the argument on the stack,
5864 or a hard register in which to store the argument.
5866 MODE is the argument's machine mode.
5867 TYPE is the data type of the argument (as a tree).
5868 This is null for libcalls where that information may
5870 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5871 the preceding args and about the function being called.
5872 NAMED is nonzero if this argument is a named parameter
5873 (otherwise it is an extra parameter matching an ellipsis).
5875 On Alpha the first 6 words of args are normally in registers
5876 and the rest are pushed. */
5879 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5880 int named ATTRIBUTE_UNUSED
)
5885 /* Don't get confused and pass small structures in FP registers. */
5886 if (type
&& AGGREGATE_TYPE_P (type
))
5890 #ifdef ENABLE_CHECKING
5891 /* With SPLIT_COMPLEX_ARGS, we shouldn't see any raw complex
5893 if (COMPLEX_MODE_P (mode
))
5897 /* Set up defaults for FP operands passed in FP registers, and
5898 integral operands passed in integer registers. */
5899 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5905 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5906 the three platforms, so we can't avoid conditional compilation. */
5907 #if TARGET_ABI_OPEN_VMS
5909 if (mode
== VOIDmode
)
5910 return alpha_arg_info_reg_val (cum
);
5912 num_args
= cum
.num_args
;
5913 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5916 #elif TARGET_ABI_UNICOSMK
5920 /* If this is the last argument, generate the call info word (CIW). */
5921 /* ??? We don't include the caller's line number in the CIW because
5922 I don't know how to determine it if debug infos are turned off. */
5923 if (mode
== VOIDmode
)
5932 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5933 if (cum
.reg_args_type
[i
])
5934 lo
|= (1 << (7 - i
));
5936 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5939 lo
|= cum
.num_reg_words
;
5941 #if HOST_BITS_PER_WIDE_INT == 32
5942 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5944 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5945 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5948 ciw
= immed_double_const (lo
, hi
, DImode
);
5950 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5951 UNSPEC_UMK_LOAD_CIW
);
5954 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5955 num_args
= cum
.num_reg_words
;
5956 if (MUST_PASS_IN_STACK (mode
, type
)
5957 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5959 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5963 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5964 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5966 /* The argument fits in two registers. Note that we still need to
5967 reserve a register for empty structures. */
5971 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5974 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5975 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5976 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5980 #elif TARGET_ABI_OSF
5986 /* VOID is passed as a special flag for "last argument". */
5987 if (type
== void_type_node
)
5989 else if (MUST_PASS_IN_STACK (mode
, type
))
5991 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5995 #error Unhandled ABI
5998 return gen_rtx_REG (mode
, num_args
+ basereg
);
6001 /* Return true if TYPE must be returned in memory, instead of in registers. */
6004 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
6006 enum machine_mode mode
= VOIDmode
;
6011 mode
= TYPE_MODE (type
);
6013 /* All aggregates are returned in memory. */
6014 if (AGGREGATE_TYPE_P (type
))
6018 size
= GET_MODE_SIZE (mode
);
6019 switch (GET_MODE_CLASS (mode
))
6021 case MODE_VECTOR_FLOAT
:
6022 /* Pass all float vectors in memory, like an aggregate. */
6025 case MODE_COMPLEX_FLOAT
:
6026 /* We judge complex floats on the size of their element,
6027 not the size of the whole type. */
6028 size
= GET_MODE_UNIT_SIZE (mode
);
6033 case MODE_COMPLEX_INT
:
6034 case MODE_VECTOR_INT
:
6038 /* ??? We get called on all sorts of random stuff from
6039 aggregate_value_p. We can't abort, but it's not clear
6040 what's safe to return. Pretend it's a struct I guess. */
6044 /* Otherwise types must fit in one register. */
6045 return size
> UNITS_PER_WORD
;
6048 /* Define how to find the value returned by a function. VALTYPE is the
6049 data type of the value (as a tree). If the precise function being
6050 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6051 MODE is set instead of VALTYPE for libcalls.
6053 On Alpha the value is found in $0 for integer functions and
6054 $f0 for floating-point functions. */
6057 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
6058 enum machine_mode mode
)
6060 unsigned int regnum
;
6061 enum mode_class
class;
6063 #ifdef ENABLE_CHECKING
6064 if (valtype
&& alpha_return_in_memory (valtype
, func
))
6069 mode
= TYPE_MODE (valtype
);
6071 class = GET_MODE_CLASS (mode
);
6075 /* Do the same thing as PROMOTE_MODE. */
6079 case MODE_COMPLEX_INT
:
6080 case MODE_VECTOR_INT
:
6088 case MODE_COMPLEX_FLOAT
:
6090 enum machine_mode cmode
= GET_MODE_INNER (mode
);
6092 return gen_rtx_PARALLEL
6095 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
6097 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
6098 GEN_INT (GET_MODE_SIZE (cmode
)))));
6105 return gen_rtx_REG (mode
, regnum
);
6109 alpha_build_builtin_va_list (void)
6111 tree base
, ofs
, space
, record
, type_decl
;
6113 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6114 return ptr_type_node
;
6116 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6117 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6118 TREE_CHAIN (record
) = type_decl
;
6119 TYPE_NAME (record
) = type_decl
;
6121 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6123 /* Dummy field to prevent alignment warnings. */
6124 space
= build_decl (FIELD_DECL
, NULL_TREE
, integer_type_node
);
6125 DECL_FIELD_CONTEXT (space
) = record
;
6126 DECL_ARTIFICIAL (space
) = 1;
6127 DECL_IGNORED_P (space
) = 1;
6129 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6131 DECL_FIELD_CONTEXT (ofs
) = record
;
6132 TREE_CHAIN (ofs
) = space
;
6134 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6136 DECL_FIELD_CONTEXT (base
) = record
;
6137 TREE_CHAIN (base
) = ofs
;
6139 TYPE_FIELDS (record
) = base
;
6140 layout_type (record
);
6145 /* Perform any needed actions needed for a function that is receiving a
6146 variable number of arguments. */
6149 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
,
6150 enum machine_mode mode ATTRIBUTE_UNUSED
,
6151 tree type ATTRIBUTE_UNUSED
,
6152 int *pretend_size
, int no_rtl
)
6154 #if TARGET_ABI_UNICOSMK
6155 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6156 arguments on the stack. Unfortunately, it doesn't always store the first
6157 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6158 with stdargs as we always have at least one named argument there. */
6159 int num_reg_words
= pcum
->num_reg_words
;
6160 if (num_reg_words
< 6)
6164 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words
+ 1)));
6165 emit_insn (gen_arg_home_umk ());
6169 #elif TARGET_ABI_OPEN_VMS
6170 /* For VMS, we allocate space for all 6 arg registers plus a count.
6172 However, if NO registers need to be saved, don't allocate any space.
6173 This is not only because we won't need the space, but because AP
6174 includes the current_pretend_args_size and we don't want to mess up
6175 any ap-relative addresses already made. */
6176 if (pcum
->num_args
< 6)
6180 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6181 emit_insn (gen_arg_home ());
6183 *pretend_size
= 7 * UNITS_PER_WORD
;
6186 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6187 only push those that are remaining. However, if NO registers need to
6188 be saved, don't allocate any space. This is not only because we won't
6189 need the space, but because AP includes the current_pretend_args_size
6190 and we don't want to mess up any ap-relative addresses already made.
6192 If we are not to use the floating-point registers, save the integer
6193 registers where we would put the floating-point registers. This is
6194 not the most efficient way to implement varargs with just one register
6195 class, but it isn't worth doing anything more efficient in this rare
6197 CUMULATIVE_ARGS cum
= *pcum
;
6204 int set
= get_varargs_alias_set ();
6207 tmp
= gen_rtx_MEM (BLKmode
,
6208 plus_constant (virtual_incoming_args_rtx
,
6209 (cum
+ 6) * UNITS_PER_WORD
));
6210 set_mem_alias_set (tmp
, set
);
6211 move_block_from_reg (16 + cum
, tmp
, 6 - cum
);
6213 tmp
= gen_rtx_MEM (BLKmode
,
6214 plus_constant (virtual_incoming_args_rtx
,
6215 cum
* UNITS_PER_WORD
));
6216 set_mem_alias_set (tmp
, set
);
6217 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
6220 *pretend_size
= 12 * UNITS_PER_WORD
;
6225 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6227 HOST_WIDE_INT offset
;
6228 tree t
, offset_field
, base_field
;
6230 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6233 if (TARGET_ABI_UNICOSMK
)
6234 std_expand_builtin_va_start (valist
, nextarg
);
6236 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6237 up by 48, storing fp arg registers in the first 48 bytes, and the
6238 integer arg registers in the next 48 bytes. This is only done,
6239 however, if any integer registers need to be stored.
6241 If no integer registers need be stored, then we must subtract 48
6242 in order to account for the integer arg registers which are counted
6243 in argsize above, but which are not actually stored on the stack.
6244 Must further be careful here about structures straddling the last
6245 integer argument register; that futzes with pretend_args_size,
6246 which changes the meaning of AP. */
6249 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6251 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6253 if (TARGET_ABI_OPEN_VMS
)
6255 nextarg
= plus_constant (nextarg
, offset
);
6256 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6257 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6258 make_tree (ptr_type_node
, nextarg
));
6259 TREE_SIDE_EFFECTS (t
) = 1;
6261 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6265 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6266 offset_field
= TREE_CHAIN (base_field
);
6268 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6269 valist
, base_field
);
6270 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6271 valist
, offset_field
);
6273 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6274 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6275 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6276 TREE_SIDE_EFFECTS (t
) = 1;
6277 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6279 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6280 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6281 TREE_SIDE_EFFECTS (t
) = 1;
6282 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6287 alpha_va_arg (tree valist
, tree type
)
6290 tree t
, type_size
, rounded_size
;
6291 tree offset_field
, base_field
, addr_tree
, addend
;
6292 tree wide_type
, wide_ofs
;
6295 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6296 return std_expand_builtin_va_arg (valist
, type
);
6298 if (type
== error_mark_node
6299 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6300 || TREE_OVERFLOW (type_size
))
6301 rounded_size
= size_zero_node
;
6303 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6304 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6305 fold (build (PLUS_EXPR
, sizetype
,
6311 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6312 offset_field
= TREE_CHAIN (base_field
);
6314 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6315 valist
, base_field
);
6316 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6317 valist
, offset_field
);
6319 /* If the type could not be passed in registers, skip the block
6320 reserved for the registers. */
6321 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6323 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6324 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6325 offset_field
, build_int_2 (6*8, 0)));
6326 TREE_SIDE_EFFECTS (t
) = 1;
6327 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6330 wide_type
= make_signed_type (64);
6331 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6335 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6338 rounded_size
= size_int (UNITS_PER_WORD
);
6340 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
6342 rtx real_part
, imag_part
, value
, tmp
;
6344 real_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6345 imag_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6347 /* ??? Most irritatingly, we're not returning the value here,
6348 but the address. Since real_part and imag_part are not
6349 necessarily contiguous, we must copy to local storage. */
6351 real_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), real_part
);
6352 imag_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), imag_part
);
6353 value
= gen_rtx_CONCAT (TYPE_MODE (type
), real_part
, imag_part
);
6355 tmp
= assign_temp (type
, 0, 1, 0);
6356 emit_move_insn (tmp
, value
);
6358 return XEXP (tmp
, 0);
6360 else if (TREE_CODE (type
) == REAL_TYPE
)
6362 tree fpaddend
, cond
;
6364 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6365 addend
, build_int_2 (-6*8, 0)));
6367 cond
= fold (build (LT_EXPR
, integer_type_node
,
6368 wide_ofs
, build_int_2 (6*8, 0)));
6370 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6374 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6375 base_field
, addend
);
6377 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6378 addr
= copy_to_reg (addr
);
6380 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6381 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6382 offset_field
, rounded_size
));
6383 TREE_SIDE_EFFECTS (t
) = 1;
6384 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6388 addr
= force_reg (Pmode
, addr
);
6389 addr
= gen_rtx_MEM (Pmode
, addr
);
6399 ALPHA_BUILTIN_CMPBGE
,
6400 ALPHA_BUILTIN_EXTBL
,
6401 ALPHA_BUILTIN_EXTWL
,
6402 ALPHA_BUILTIN_EXTLL
,
6403 ALPHA_BUILTIN_EXTQL
,
6404 ALPHA_BUILTIN_EXTWH
,
6405 ALPHA_BUILTIN_EXTLH
,
6406 ALPHA_BUILTIN_EXTQH
,
6407 ALPHA_BUILTIN_INSBL
,
6408 ALPHA_BUILTIN_INSWL
,
6409 ALPHA_BUILTIN_INSLL
,
6410 ALPHA_BUILTIN_INSQL
,
6411 ALPHA_BUILTIN_INSWH
,
6412 ALPHA_BUILTIN_INSLH
,
6413 ALPHA_BUILTIN_INSQH
,
6414 ALPHA_BUILTIN_MSKBL
,
6415 ALPHA_BUILTIN_MSKWL
,
6416 ALPHA_BUILTIN_MSKLL
,
6417 ALPHA_BUILTIN_MSKQL
,
6418 ALPHA_BUILTIN_MSKWH
,
6419 ALPHA_BUILTIN_MSKLH
,
6420 ALPHA_BUILTIN_MSKQH
,
6421 ALPHA_BUILTIN_UMULH
,
6423 ALPHA_BUILTIN_ZAPNOT
,
6424 ALPHA_BUILTIN_AMASK
,
6425 ALPHA_BUILTIN_IMPLVER
,
6427 ALPHA_BUILTIN_THREAD_POINTER
,
6428 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6431 ALPHA_BUILTIN_MINUB8
,
6432 ALPHA_BUILTIN_MINSB8
,
6433 ALPHA_BUILTIN_MINUW4
,
6434 ALPHA_BUILTIN_MINSW4
,
6435 ALPHA_BUILTIN_MAXUB8
,
6436 ALPHA_BUILTIN_MAXSB8
,
6437 ALPHA_BUILTIN_MAXUW4
,
6438 ALPHA_BUILTIN_MAXSW4
,
6442 ALPHA_BUILTIN_UNPKBL
,
6443 ALPHA_BUILTIN_UNPKBW
,
6448 ALPHA_BUILTIN_CTPOP
,
6453 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6454 CODE_FOR_builtin_cmpbge
,
6455 CODE_FOR_builtin_extbl
,
6456 CODE_FOR_builtin_extwl
,
6457 CODE_FOR_builtin_extll
,
6458 CODE_FOR_builtin_extql
,
6459 CODE_FOR_builtin_extwh
,
6460 CODE_FOR_builtin_extlh
,
6461 CODE_FOR_builtin_extqh
,
6462 CODE_FOR_builtin_insbl
,
6463 CODE_FOR_builtin_inswl
,
6464 CODE_FOR_builtin_insll
,
6465 CODE_FOR_builtin_insql
,
6466 CODE_FOR_builtin_inswh
,
6467 CODE_FOR_builtin_inslh
,
6468 CODE_FOR_builtin_insqh
,
6469 CODE_FOR_builtin_mskbl
,
6470 CODE_FOR_builtin_mskwl
,
6471 CODE_FOR_builtin_mskll
,
6472 CODE_FOR_builtin_mskql
,
6473 CODE_FOR_builtin_mskwh
,
6474 CODE_FOR_builtin_msklh
,
6475 CODE_FOR_builtin_mskqh
,
6476 CODE_FOR_umuldi3_highpart
,
6477 CODE_FOR_builtin_zap
,
6478 CODE_FOR_builtin_zapnot
,
6479 CODE_FOR_builtin_amask
,
6480 CODE_FOR_builtin_implver
,
6481 CODE_FOR_builtin_rpcc
,
6486 CODE_FOR_builtin_minub8
,
6487 CODE_FOR_builtin_minsb8
,
6488 CODE_FOR_builtin_minuw4
,
6489 CODE_FOR_builtin_minsw4
,
6490 CODE_FOR_builtin_maxub8
,
6491 CODE_FOR_builtin_maxsb8
,
6492 CODE_FOR_builtin_maxuw4
,
6493 CODE_FOR_builtin_maxsw4
,
6494 CODE_FOR_builtin_perr
,
6495 CODE_FOR_builtin_pklb
,
6496 CODE_FOR_builtin_pkwb
,
6497 CODE_FOR_builtin_unpkbl
,
6498 CODE_FOR_builtin_unpkbw
,
6501 CODE_FOR_builtin_cttz
,
6502 CODE_FOR_builtin_ctlz
,
6503 CODE_FOR_builtin_ctpop
6506 struct alpha_builtin_def
6509 enum alpha_builtin code
;
6510 unsigned int target_mask
;
6513 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6514 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6515 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6518 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6519 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6520 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6521 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6522 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6523 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6524 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6525 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6526 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6529 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6530 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6531 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6532 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6533 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6534 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6535 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6536 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6537 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6538 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6539 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6540 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6541 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6542 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6543 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6544 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6545 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6546 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6547 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6548 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6549 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6550 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6551 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6552 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6553 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6554 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6555 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6556 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6557 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6558 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6559 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6560 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6561 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6562 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6563 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6567 alpha_init_builtins (void)
6569 const struct alpha_builtin_def
*p
;
6573 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6575 p
= zero_arg_builtins
;
6576 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6577 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6578 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6581 ftype
= build_function_type_list (long_integer_type_node
,
6582 long_integer_type_node
, NULL_TREE
);
6584 p
= one_arg_builtins
;
6585 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6586 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6587 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6590 ftype
= build_function_type_list (long_integer_type_node
,
6591 long_integer_type_node
,
6592 long_integer_type_node
, NULL_TREE
);
6594 p
= two_arg_builtins
;
6595 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6596 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6597 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6600 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6601 builtin_function ("__builtin_thread_pointer", ftype
,
6602 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6605 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6606 builtin_function ("__builtin_set_thread_pointer", ftype
,
6607 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6611 /* Expand an expression EXP that calls a built-in function,
6612 with result going to TARGET if that's convenient
6613 (and in mode MODE if that's convenient).
6614 SUBTARGET may be used as the target for computing one of EXP's operands.
6615 IGNORE is nonzero if the value is to be ignored. */
6618 alpha_expand_builtin (tree exp
, rtx target
,
6619 rtx subtarget ATTRIBUTE_UNUSED
,
6620 enum machine_mode mode ATTRIBUTE_UNUSED
,
6621 int ignore ATTRIBUTE_UNUSED
)
6625 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6626 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6627 tree arglist
= TREE_OPERAND (exp
, 1);
6628 enum insn_code icode
;
6629 rtx op
[MAX_ARGS
], pat
;
6633 if (fcode
>= ALPHA_BUILTIN_max
)
6634 internal_error ("bad builtin fcode");
6635 icode
= code_for_builtin
[fcode
];
6637 internal_error ("bad builtin fcode");
6639 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6641 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6643 arglist
= TREE_CHAIN (arglist
), arity
++)
6645 const struct insn_operand_data
*insn_op
;
6647 tree arg
= TREE_VALUE (arglist
);
6648 if (arg
== error_mark_node
)
6650 if (arity
> MAX_ARGS
)
6653 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6655 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6657 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6658 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6663 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6665 || GET_MODE (target
) != tmode
6666 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6667 target
= gen_reg_rtx (tmode
);
6673 pat
= GEN_FCN (icode
) (target
);
6677 pat
= GEN_FCN (icode
) (target
, op
[0]);
6679 pat
= GEN_FCN (icode
) (op
[0]);
6682 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6697 /* This page contains routines that are used to determine what the function
6698 prologue and epilogue code will do and write them out. */
6700 /* Compute the size of the save area in the stack. */
6702 /* These variables are used for communication between the following functions.
6703 They indicate various things about the current function being compiled
6704 that are used to tell what kind of prologue, epilogue and procedure
6705 descriptor to generate. */
6707 /* Nonzero if we need a stack procedure. */
6708 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6709 static enum alpha_procedure_types alpha_procedure_type
;
6711 /* Register number (either FP or SP) that is used to unwind the frame. */
6712 static int vms_unwind_regno
;
6714 /* Register number used to save FP. We need not have one for RA since
6715 we don't modify it for register procedures. This is only defined
6716 for register frame procedures. */
6717 static int vms_save_fp_regno
;
6719 /* Register number used to reference objects off our PV. */
6720 static int vms_base_regno
;
6722 /* Compute register masks for saved registers. */
6725 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
6727 unsigned long imask
= 0;
6728 unsigned long fmask
= 0;
6731 /* Irritatingly, there are two kinds of thunks -- those created with
6732 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6733 through the regular part of the compiler. In the
6734 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6735 info, but assemble_start_function wants to output .frame and
6736 .mask directives. */
6737 if (current_function_is_thunk
&& !no_new_pseudos
)
6744 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6745 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6747 /* One for every register we have to save. */
6748 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6749 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6750 && regs_ever_live
[i
] && i
!= REG_RA
6751 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6754 imask
|= (1UL << i
);
6756 fmask
|= (1UL << (i
- 32));
6759 /* We need to restore these for the handler. */
6760 if (current_function_calls_eh_return
)
6764 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6765 if (regno
== INVALID_REGNUM
)
6767 imask
|= 1UL << regno
;
6770 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6771 avoid hackery in unwind-dw2.c, we need to actively store a
6772 zero in the prologue of _Unwind_RaiseException et al. */
6776 /* If any register spilled, then spill the return address also. */
6777 /* ??? This is required by the Digital stack unwind specification
6778 and isn't needed if we're doing Dwarf2 unwinding. */
6779 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6780 imask
|= (1UL << REG_RA
);
6787 alpha_sa_size (void)
6789 unsigned long mask
[2];
6793 alpha_sa_mask (&mask
[0], &mask
[1]);
6795 if (TARGET_ABI_UNICOSMK
)
6797 if (mask
[0] || mask
[1])
6802 for (j
= 0; j
< 2; ++j
)
6803 for (i
= 0; i
< 32; ++i
)
6804 if ((mask
[j
] >> i
) & 1)
6808 if (TARGET_ABI_UNICOSMK
)
6810 /* We might not need to generate a frame if we don't make any calls
6811 (including calls to __T3E_MISMATCH if this is a vararg function),
6812 don't have any local variables which require stack slots, don't
6813 use alloca and have not determined that we need a frame for other
6816 alpha_procedure_type
6817 = (sa_size
|| get_frame_size() != 0
6818 || current_function_outgoing_args_size
6819 || current_function_stdarg
|| current_function_calls_alloca
6820 || frame_pointer_needed
)
6821 ? PT_STACK
: PT_REGISTER
;
6823 /* Always reserve space for saving callee-saved registers if we
6824 need a frame as required by the calling convention. */
6825 if (alpha_procedure_type
== PT_STACK
)
6828 else if (TARGET_ABI_OPEN_VMS
)
6830 /* Start by assuming we can use a register procedure if we don't
6831 make any calls (REG_RA not used) or need to save any
6832 registers and a stack procedure if we do. */
6833 if ((mask
[0] >> REG_RA
) & 1)
6834 alpha_procedure_type
= PT_STACK
;
6835 else if (get_frame_size() != 0)
6836 alpha_procedure_type
= PT_REGISTER
;
6838 alpha_procedure_type
= PT_NULL
;
6840 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6841 made the final decision on stack procedure vs register procedure. */
6842 if (alpha_procedure_type
== PT_STACK
)
6845 /* Decide whether to refer to objects off our PV via FP or PV.
6846 If we need FP for something else or if we receive a nonlocal
6847 goto (which expects PV to contain the value), we must use PV.
6848 Otherwise, start by assuming we can use FP. */
6851 = (frame_pointer_needed
6852 || current_function_has_nonlocal_label
6853 || alpha_procedure_type
== PT_STACK
6854 || current_function_outgoing_args_size
)
6855 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6857 /* If we want to copy PV into FP, we need to find some register
6858 in which to save FP. */
6860 vms_save_fp_regno
= -1;
6861 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6862 for (i
= 0; i
< 32; i
++)
6863 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6864 vms_save_fp_regno
= i
;
6866 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6867 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6868 else if (alpha_procedure_type
== PT_NULL
)
6869 vms_base_regno
= REG_PV
;
6871 /* Stack unwinding should be done via FP unless we use it for PV. */
6872 vms_unwind_regno
= (vms_base_regno
== REG_PV
6873 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6875 /* If this is a stack procedure, allow space for saving FP and RA. */
6876 if (alpha_procedure_type
== PT_STACK
)
6881 /* Our size must be even (multiple of 16 bytes). */
6889 /* Define the offset between two registers, one to be eliminated,
6890 and the other its replacement, at the start of a routine. */
6893 alpha_initial_elimination_offset (unsigned int from
,
6894 unsigned int to ATTRIBUTE_UNUSED
)
6898 ret
= alpha_sa_size ();
6899 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
6901 if (from
== FRAME_POINTER_REGNUM
)
6903 else if (from
== ARG_POINTER_REGNUM
)
6904 ret
+= (ALPHA_ROUND (get_frame_size ()
6905 + current_function_pretend_args_size
)
6906 - current_function_pretend_args_size
);
6914 alpha_pv_save_size (void)
6917 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6921 alpha_using_fp (void)
6924 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6927 #if TARGET_ABI_OPEN_VMS
6929 const struct attribute_spec vms_attribute_table
[] =
6931 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6932 { "overlaid", 0, 0, true, false, false, NULL
},
6933 { "global", 0, 0, true, false, false, NULL
},
6934 { "initialize", 0, 0, true, false, false, NULL
},
6935 { NULL
, 0, 0, false, false, false, NULL
}
6941 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6943 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
6947 alpha_find_lo_sum_using_gp (rtx insn
)
6949 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
6953 alpha_does_function_need_gp (void)
6957 /* The GP being variable is an OSF abi thing. */
6958 if (! TARGET_ABI_OSF
)
6961 /* We need the gp to load the address of __mcount. */
6962 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6965 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6966 if (current_function_is_thunk
)
6969 /* The nonlocal receiver pattern assumes that the gp is valid for
6970 the nested function. Reasonable because it's almost always set
6971 correctly already. For the cases where that's wrong, make sure
6972 the nested function loads its gp on entry. */
6973 if (current_function_has_nonlocal_goto
)
6976 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6977 Even if we are a static function, we still need to do this in case
6978 our address is taken and passed to something like qsort. */
6980 push_topmost_sequence ();
6981 insn
= get_insns ();
6982 pop_topmost_sequence ();
6984 for (; insn
; insn
= NEXT_INSN (insn
))
6986 && GET_CODE (PATTERN (insn
)) != USE
6987 && GET_CODE (PATTERN (insn
)) != CLOBBER
6988 && get_attr_usegp (insn
))
6995 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6999 set_frame_related_p (void)
7001 rtx seq
= get_insns ();
7012 while (insn
!= NULL_RTX
)
7014 RTX_FRAME_RELATED_P (insn
) = 1;
7015 insn
= NEXT_INSN (insn
);
7017 seq
= emit_insn (seq
);
7021 seq
= emit_insn (seq
);
7022 RTX_FRAME_RELATED_P (seq
) = 1;
7027 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7029 /* Write function prologue. */
7031 /* On vms we have two kinds of functions:
7033 - stack frame (PROC_STACK)
7034 these are 'normal' functions with local vars and which are
7035 calling other functions
7036 - register frame (PROC_REGISTER)
7037 keeps all data in registers, needs no stack
7039 We must pass this to the assembler so it can generate the
7040 proper pdsc (procedure descriptor)
7041 This is done with the '.pdesc' command.
7043 On not-vms, we don't really differentiate between the two, as we can
7044 simply allocate stack without saving registers. */
7047 alpha_expand_prologue (void)
7049 /* Registers to save. */
7050 unsigned long imask
= 0;
7051 unsigned long fmask
= 0;
7052 /* Stack space needed for pushing registers clobbered by us. */
7053 HOST_WIDE_INT sa_size
;
7054 /* Complete stack size needed. */
7055 HOST_WIDE_INT frame_size
;
7056 /* Offset from base reg to register save area. */
7057 HOST_WIDE_INT reg_offset
;
7061 sa_size
= alpha_sa_size ();
7063 frame_size
= get_frame_size ();
7064 if (TARGET_ABI_OPEN_VMS
)
7065 frame_size
= ALPHA_ROUND (sa_size
7066 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7068 + current_function_pretend_args_size
);
7069 else if (TARGET_ABI_UNICOSMK
)
7070 /* We have to allocate space for the DSIB if we generate a frame. */
7071 frame_size
= ALPHA_ROUND (sa_size
7072 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7073 + ALPHA_ROUND (frame_size
7074 + current_function_outgoing_args_size
);
7076 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7078 + ALPHA_ROUND (frame_size
7079 + current_function_pretend_args_size
));
7081 if (TARGET_ABI_OPEN_VMS
)
7084 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7086 alpha_sa_mask (&imask
, &fmask
);
7088 /* Emit an insn to reload GP, if needed. */
7091 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7092 if (alpha_function_needs_gp
)
7093 emit_insn (gen_prologue_ldgp ());
7096 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7097 the call to mcount ourselves, rather than having the linker do it
7098 magically in response to -pg. Since _mcount has special linkage,
7099 don't represent the call as a call. */
7100 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7101 emit_insn (gen_prologue_mcount ());
7103 if (TARGET_ABI_UNICOSMK
)
7104 unicosmk_gen_dsib (&imask
);
7106 /* Adjust the stack by the frame size. If the frame size is > 4096
7107 bytes, we need to be sure we probe somewhere in the first and last
7108 4096 bytes (we can probably get away without the latter test) and
7109 every 8192 bytes in between. If the frame size is > 32768, we
7110 do this in a loop. Otherwise, we generate the explicit probe
7113 Note that we are only allowed to adjust sp once in the prologue. */
7115 if (frame_size
<= 32768)
7117 if (frame_size
> 4096)
7122 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7125 while ((probed
+= 8192) < frame_size
);
7127 /* We only have to do this probe if we aren't saving registers. */
7128 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7129 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7132 if (frame_size
!= 0)
7133 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7134 GEN_INT (TARGET_ABI_UNICOSMK
7140 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7141 number of 8192 byte blocks to probe. We then probe each block
7142 in the loop and then set SP to the proper location. If the
7143 amount remaining is > 4096, we have to do one more probe if we
7144 are not saving any registers. */
7146 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7147 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7148 rtx ptr
= gen_rtx_REG (DImode
, 22);
7149 rtx count
= gen_rtx_REG (DImode
, 23);
7152 emit_move_insn (count
, GEN_INT (blocks
));
7153 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7154 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7156 /* Because of the difficulty in emitting a new basic block this
7157 late in the compilation, generate the loop as a single insn. */
7158 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7160 if (leftover
> 4096 && sa_size
== 0)
7162 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7163 MEM_VOLATILE_P (last
) = 1;
7164 emit_move_insn (last
, const0_rtx
);
7167 if (TARGET_ABI_WINDOWS_NT
)
7169 /* For NT stack unwind (done by 'reverse execution'), it's
7170 not OK to take the result of a loop, even though the value
7171 is already in ptr, so we reload it via a single operation
7172 and subtract it to sp.
7174 Yes, that's correct -- we have to reload the whole constant
7175 into a temporary via ldah+lda then subtract from sp. */
7177 HOST_WIDE_INT lo
, hi
;
7178 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7179 hi
= frame_size
- lo
;
7181 emit_move_insn (ptr
, GEN_INT (hi
));
7182 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7183 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7188 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7189 GEN_INT (-leftover
)));
7192 /* This alternative is special, because the DWARF code cannot
7193 possibly intuit through the loop above. So we invent this
7194 note it looks at instead. */
7195 RTX_FRAME_RELATED_P (seq
) = 1;
7197 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7198 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7199 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7200 GEN_INT (TARGET_ABI_UNICOSMK
7206 if (!TARGET_ABI_UNICOSMK
)
7208 /* Cope with very large offsets to the register save area. */
7209 sa_reg
= stack_pointer_rtx
;
7210 if (reg_offset
+ sa_size
> 0x8000)
7212 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7215 if (low
+ sa_size
<= 0x8000)
7216 bias
= reg_offset
- low
, reg_offset
= low
;
7218 bias
= reg_offset
, reg_offset
= 0;
7220 sa_reg
= gen_rtx_REG (DImode
, 24);
7221 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7225 /* Save regs in stack order. Beginning with VMS PV. */
7226 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7228 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7229 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7230 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7233 /* Save register RA next. */
7234 if (imask
& (1UL << REG_RA
))
7236 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7237 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7238 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7239 imask
&= ~(1UL << REG_RA
);
7243 /* Now save any other registers required to be saved. */
7244 for (i
= 0; i
< 31; i
++)
7245 if (imask
& (1UL << i
))
7247 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7248 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7249 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7253 /* Store a zero if requested for unwinding. */
7254 if (imask
& (1UL << 31))
7258 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7259 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7260 insn
= emit_move_insn (mem
, const0_rtx
);
7262 RTX_FRAME_RELATED_P (insn
) = 1;
7263 t
= gen_rtx_REG (Pmode
, 31);
7264 t
= gen_rtx_SET (VOIDmode
, mem
, t
);
7265 t
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, t
, REG_NOTES (insn
));
7266 REG_NOTES (insn
) = t
;
7271 for (i
= 0; i
< 31; i
++)
7272 if (fmask
& (1UL << i
))
7274 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7275 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7276 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7280 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7282 /* The standard frame on the T3E includes space for saving registers.
7283 We just have to use it. We don't have to save the return address and
7284 the old frame pointer here - they are saved in the DSIB. */
7287 for (i
= 9; i
< 15; i
++)
7288 if (imask
& (1UL << i
))
7290 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7292 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7293 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7296 for (i
= 2; i
< 10; i
++)
7297 if (fmask
& (1UL << i
))
7299 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7301 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7302 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7307 if (TARGET_ABI_OPEN_VMS
)
7309 if (alpha_procedure_type
== PT_REGISTER
)
7310 /* Register frame procedures save the fp.
7311 ?? Ought to have a dwarf2 save for this. */
7312 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7313 hard_frame_pointer_rtx
);
7315 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7316 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7317 gen_rtx_REG (DImode
, REG_PV
)));
7319 if (alpha_procedure_type
!= PT_NULL
7320 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7321 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7323 /* If we have to allocate space for outgoing args, do it now. */
7324 if (current_function_outgoing_args_size
!= 0)
7327 = emit_move_insn (stack_pointer_rtx
,
7329 (hard_frame_pointer_rtx
,
7331 (current_function_outgoing_args_size
))));
7333 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7334 if ! frame_pointer_needed. Setting the bit will change the CFA
7335 computation rule to use sp again, which would be wrong if we had
7336 frame_pointer_needed, as this means sp might move unpredictably
7340 frame_pointer_needed
7341 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7343 current_function_outgoing_args_size != 0
7344 => alpha_procedure_type != PT_NULL,
7346 so when we are not setting the bit here, we are guaranteed to
7347 have emitted an FRP frame pointer update just before. */
7348 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7351 else if (!TARGET_ABI_UNICOSMK
)
7353 /* If we need a frame pointer, set it from the stack pointer. */
7354 if (frame_pointer_needed
)
7356 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7357 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7359 /* This must always be the last instruction in the
7360 prologue, thus we emit a special move + clobber. */
7361 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7362 stack_pointer_rtx
, sa_reg
)));
7366 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7367 the prologue, for exception handling reasons, we cannot do this for
7368 any insn that might fault. We could prevent this for mems with a
7369 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7370 have to prevent all such scheduling with a blockage.
7372 Linux, on the other hand, never bothered to implement OSF/1's
7373 exception handling, and so doesn't care about such things. Anyone
7374 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7376 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7377 emit_insn (gen_blockage ());
7380 /* Output the textual info surrounding the prologue. */
7383 alpha_start_function (FILE *file
, const char *fnname
,
7384 tree decl ATTRIBUTE_UNUSED
)
7386 unsigned long imask
= 0;
7387 unsigned long fmask
= 0;
7388 /* Stack space needed for pushing registers clobbered by us. */
7389 HOST_WIDE_INT sa_size
;
7390 /* Complete stack size needed. */
7391 unsigned HOST_WIDE_INT frame_size
;
7392 /* Offset from base reg to register save area. */
7393 HOST_WIDE_INT reg_offset
;
7394 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7397 /* Don't emit an extern directive for functions defined in the same file. */
7398 if (TARGET_ABI_UNICOSMK
)
7401 name_tree
= get_identifier (fnname
);
7402 TREE_ASM_WRITTEN (name_tree
) = 1;
7405 alpha_fnname
= fnname
;
7406 sa_size
= alpha_sa_size ();
7408 frame_size
= get_frame_size ();
7409 if (TARGET_ABI_OPEN_VMS
)
7410 frame_size
= ALPHA_ROUND (sa_size
7411 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7413 + current_function_pretend_args_size
);
7414 else if (TARGET_ABI_UNICOSMK
)
7415 frame_size
= ALPHA_ROUND (sa_size
7416 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7417 + ALPHA_ROUND (frame_size
7418 + current_function_outgoing_args_size
);
7420 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7422 + ALPHA_ROUND (frame_size
7423 + current_function_pretend_args_size
));
7425 if (TARGET_ABI_OPEN_VMS
)
7428 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7430 alpha_sa_mask (&imask
, &fmask
);
7432 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7433 We have to do that before the .ent directive as we cannot switch
7434 files within procedures with native ecoff because line numbers are
7435 linked to procedure descriptors.
7436 Outputting the lineno helps debugging of one line functions as they
7437 would otherwise get no line number at all. Please note that we would
7438 like to put out last_linenum from final.c, but it is not accessible. */
7440 if (write_symbols
== SDB_DEBUG
)
7442 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7443 ASM_OUTPUT_SOURCE_FILENAME (file
,
7444 DECL_SOURCE_FILE (current_function_decl
));
7446 #ifdef ASM_OUTPUT_SOURCE_LINE
7447 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7448 ASM_OUTPUT_SOURCE_LINE (file
,
7449 DECL_SOURCE_LINE (current_function_decl
), 0);
7453 /* Issue function start and label. */
7454 if (TARGET_ABI_OPEN_VMS
7455 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7457 fputs ("\t.ent ", file
);
7458 assemble_name (file
, fnname
);
7461 /* If the function needs GP, we'll write the "..ng" label there.
7462 Otherwise, do it here. */
7464 && ! alpha_function_needs_gp
7465 && ! current_function_is_thunk
)
7468 assemble_name (file
, fnname
);
7469 fputs ("..ng:\n", file
);
7473 strcpy (entry_label
, fnname
);
7474 if (TARGET_ABI_OPEN_VMS
)
7475 strcat (entry_label
, "..en");
7477 /* For public functions, the label must be globalized by appending an
7478 additional colon. */
7479 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7480 strcat (entry_label
, ":");
7482 ASM_OUTPUT_LABEL (file
, entry_label
);
7483 inside_function
= TRUE
;
7485 if (TARGET_ABI_OPEN_VMS
)
7486 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7488 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7489 && !flag_inhibit_size_directive
)
7491 /* Set flags in procedure descriptor to request IEEE-conformant
7492 math-library routines. The value we set it to is PDSC_EXC_IEEE
7493 (/usr/include/pdsc.h). */
7494 fputs ("\t.eflag 48\n", file
);
7497 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7498 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7499 alpha_arg_offset
= -frame_size
+ 48;
7501 /* Describe our frame. If the frame size is larger than an integer,
7502 print it as zero to avoid an assembler error. We won't be
7503 properly describing such a frame, but that's the best we can do. */
7504 if (TARGET_ABI_UNICOSMK
)
7506 else if (TARGET_ABI_OPEN_VMS
)
7507 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7508 HOST_WIDE_INT_PRINT_DEC
"\n",
7510 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7512 else if (!flag_inhibit_size_directive
)
7513 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7514 (frame_pointer_needed
7515 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7516 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7517 current_function_pretend_args_size
);
7519 /* Describe which registers were spilled. */
7520 if (TARGET_ABI_UNICOSMK
)
7522 else if (TARGET_ABI_OPEN_VMS
)
7525 /* ??? Does VMS care if mask contains ra? The old code didn't
7526 set it, so I don't here. */
7527 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7529 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7530 if (alpha_procedure_type
== PT_REGISTER
)
7531 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7533 else if (!flag_inhibit_size_directive
)
7537 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7538 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7540 for (i
= 0; i
< 32; ++i
)
7541 if (imask
& (1UL << i
))
7546 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7547 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7550 #if TARGET_ABI_OPEN_VMS
7551 /* Ifdef'ed cause link_section are only available then. */
7552 readonly_data_section ();
7553 fprintf (file
, "\t.align 3\n");
7554 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7555 fputs ("\t.ascii \"", file
);
7556 assemble_name (file
, fnname
);
7557 fputs ("\\0\"\n", file
);
7558 alpha_need_linkage (fnname
, 1);
7563 /* Emit the .prologue note at the scheduled end of the prologue. */
7566 alpha_output_function_end_prologue (FILE *file
)
7568 if (TARGET_ABI_UNICOSMK
)
7570 else if (TARGET_ABI_OPEN_VMS
)
7571 fputs ("\t.prologue\n", file
);
7572 else if (TARGET_ABI_WINDOWS_NT
)
7573 fputs ("\t.prologue 0\n", file
);
7574 else if (!flag_inhibit_size_directive
)
7575 fprintf (file
, "\t.prologue %d\n",
7576 alpha_function_needs_gp
|| current_function_is_thunk
);
7579 /* Write function epilogue. */
7581 /* ??? At some point we will want to support full unwind, and so will
7582 need to mark the epilogue as well. At the moment, we just confuse
7585 #define FRP(exp) exp
7588 alpha_expand_epilogue (void)
7590 /* Registers to save. */
7591 unsigned long imask
= 0;
7592 unsigned long fmask
= 0;
7593 /* Stack space needed for pushing registers clobbered by us. */
7594 HOST_WIDE_INT sa_size
;
7595 /* Complete stack size needed. */
7596 HOST_WIDE_INT frame_size
;
7597 /* Offset from base reg to register save area. */
7598 HOST_WIDE_INT reg_offset
;
7599 int fp_is_frame_pointer
, fp_offset
;
7600 rtx sa_reg
, sa_reg_exp
= NULL
;
7601 rtx sp_adj1
, sp_adj2
, mem
;
7605 sa_size
= alpha_sa_size ();
7607 frame_size
= get_frame_size ();
7608 if (TARGET_ABI_OPEN_VMS
)
7609 frame_size
= ALPHA_ROUND (sa_size
7610 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7612 + current_function_pretend_args_size
);
7613 else if (TARGET_ABI_UNICOSMK
)
7614 frame_size
= ALPHA_ROUND (sa_size
7615 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7616 + ALPHA_ROUND (frame_size
7617 + current_function_outgoing_args_size
);
7619 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7621 + ALPHA_ROUND (frame_size
7622 + current_function_pretend_args_size
));
7624 if (TARGET_ABI_OPEN_VMS
)
7626 if (alpha_procedure_type
== PT_STACK
)
7632 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7634 alpha_sa_mask (&imask
, &fmask
);
7637 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7638 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7640 sa_reg
= stack_pointer_rtx
;
7642 if (current_function_calls_eh_return
)
7643 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7647 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7649 /* If we have a frame pointer, restore SP from it. */
7650 if ((TARGET_ABI_OPEN_VMS
7651 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7652 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7653 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7655 /* Cope with very large offsets to the register save area. */
7656 if (reg_offset
+ sa_size
> 0x8000)
7658 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7661 if (low
+ sa_size
<= 0x8000)
7662 bias
= reg_offset
- low
, reg_offset
= low
;
7664 bias
= reg_offset
, reg_offset
= 0;
7666 sa_reg
= gen_rtx_REG (DImode
, 22);
7667 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7669 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7672 /* Restore registers in order, excepting a true frame pointer. */
7674 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7676 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7677 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7680 imask
&= ~(1UL << REG_RA
);
7682 for (i
= 0; i
< 31; ++i
)
7683 if (imask
& (1UL << i
))
7685 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7686 fp_offset
= reg_offset
;
7689 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7690 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7691 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7696 if (imask
& (1UL << 31))
7699 for (i
= 0; i
< 31; ++i
)
7700 if (fmask
& (1UL << i
))
7702 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7703 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7704 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7708 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7710 /* Restore callee-saved general-purpose registers. */
7714 for (i
= 9; i
< 15; i
++)
7715 if (imask
& (1UL << i
))
7717 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7719 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7720 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7724 for (i
= 2; i
< 10; i
++)
7725 if (fmask
& (1UL << i
))
7727 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7729 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7730 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7734 /* Restore the return address from the DSIB. */
7736 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7737 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7738 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7741 if (frame_size
|| eh_ofs
)
7743 sp_adj1
= stack_pointer_rtx
;
7747 sp_adj1
= gen_rtx_REG (DImode
, 23);
7748 emit_move_insn (sp_adj1
,
7749 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7752 /* If the stack size is large, begin computation into a temporary
7753 register so as not to interfere with a potential fp restore,
7754 which must be consecutive with an SP restore. */
7755 if (frame_size
< 32768
7756 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7757 sp_adj2
= GEN_INT (frame_size
);
7758 else if (TARGET_ABI_UNICOSMK
)
7760 sp_adj1
= gen_rtx_REG (DImode
, 23);
7761 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7762 sp_adj2
= const0_rtx
;
7764 else if (frame_size
< 0x40007fffL
)
7766 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7768 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7769 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7773 sp_adj1
= gen_rtx_REG (DImode
, 23);
7774 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7776 sp_adj2
= GEN_INT (low
);
7780 rtx tmp
= gen_rtx_REG (DImode
, 23);
7781 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7784 /* We can't drop new things to memory this late, afaik,
7785 so build it up by pieces. */
7786 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7787 -(frame_size
< 0)));
7793 /* From now on, things must be in order. So emit blockages. */
7795 /* Restore the frame pointer. */
7796 if (TARGET_ABI_UNICOSMK
)
7798 emit_insn (gen_blockage ());
7799 mem
= gen_rtx_MEM (DImode
,
7800 plus_constant (hard_frame_pointer_rtx
, -16));
7801 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7802 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7804 else if (fp_is_frame_pointer
)
7806 emit_insn (gen_blockage ());
7807 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7808 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7809 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7811 else if (TARGET_ABI_OPEN_VMS
)
7813 emit_insn (gen_blockage ());
7814 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7815 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7818 /* Restore the stack pointer. */
7819 emit_insn (gen_blockage ());
7820 if (sp_adj2
== const0_rtx
)
7821 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7823 FRP (emit_move_insn (stack_pointer_rtx
,
7824 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7828 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7830 emit_insn (gen_blockage ());
7831 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7832 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7834 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7836 /* Decrement the frame pointer if the function does not have a
7839 emit_insn (gen_blockage ());
7840 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7841 hard_frame_pointer_rtx
, GEN_INT (-1))));
7846 /* Output the rest of the textual info surrounding the epilogue. */
7849 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
7851 /* End the function. */
7852 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7854 fputs ("\t.end ", file
);
7855 assemble_name (file
, fnname
);
7858 inside_function
= FALSE
;
7860 #if TARGET_ABI_OPEN_VMS
7861 alpha_write_linkage (file
, fnname
, decl
);
7864 /* Output jump tables and the static subroutine information block. */
7865 if (TARGET_ABI_UNICOSMK
)
7867 unicosmk_output_ssib (file
, fnname
);
7868 unicosmk_output_deferred_case_vectors (file
);
7873 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7875 In order to avoid the hordes of differences between generated code
7876 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7877 lots of code loading up large constants, generate rtl and emit it
7878 instead of going straight to text.
7880 Not sure why this idea hasn't been explored before... */
7883 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7884 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
7887 HOST_WIDE_INT hi
, lo
;
7888 rtx
this, insn
, funexp
;
7890 /* We always require a valid GP. */
7891 emit_insn (gen_prologue_ldgp ());
7892 emit_note (NOTE_INSN_PROLOGUE_END
);
7894 /* Find the "this" pointer. If the function returns a structure,
7895 the structure return pointer is in $16. */
7896 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7897 this = gen_rtx_REG (Pmode
, 17);
7899 this = gen_rtx_REG (Pmode
, 16);
7901 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7902 entire constant for the add. */
7903 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7904 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7905 if (hi
+ lo
== delta
)
7908 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7910 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7914 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7915 delta
, -(delta
< 0));
7916 emit_insn (gen_adddi3 (this, this, tmp
));
7919 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7924 tmp
= gen_rtx_REG (Pmode
, 0);
7925 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
7927 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
7928 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7929 if (hi
+ lo
== vcall_offset
)
7932 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
7936 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
7937 vcall_offset
, -(vcall_offset
< 0));
7938 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
7942 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
7945 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
7947 emit_insn (gen_adddi3 (this, this, tmp
));
7950 /* Generate a tail call to the target function. */
7951 if (! TREE_USED (function
))
7953 assemble_external (function
);
7954 TREE_USED (function
) = 1;
7956 funexp
= XEXP (DECL_RTL (function
), 0);
7957 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7958 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7959 SIBLING_CALL_P (insn
) = 1;
7961 /* Run just enough of rest_of_compilation to get the insns emitted.
7962 There's not really enough bulk here to make other passes such as
7963 instruction scheduling worth while. Note that use_thunk calls
7964 assemble_start_function and assemble_end_function. */
7965 insn
= get_insns ();
7966 insn_locators_initialize ();
7967 shorten_branches (insn
);
7968 final_start_function (insn
, file
, 1);
7969 final (insn
, file
, 1, 0);
7970 final_end_function ();
7972 #endif /* TARGET_ABI_OSF */
7974 /* Debugging support. */
7978 /* Count the number of sdb related labels are generated (to find block
7979 start and end boundaries). */
7981 int sdb_label_count
= 0;
7983 /* Next label # for each statement. */
7985 static int sym_lineno
= 0;
7987 /* Count the number of .file directives, so that .loc is up to date. */
7989 static int num_source_filenames
= 0;
7991 /* Name of the file containing the current function. */
7993 static const char *current_function_file
= "";
7995 /* Offsets to alpha virtual arg/local debugging pointers. */
7997 long alpha_arg_offset
;
7998 long alpha_auto_offset
;
8000 /* Emit a new filename to a stream. */
8003 alpha_output_filename (FILE *stream
, const char *name
)
8005 static int first_time
= TRUE
;
8006 char ltext_label_name
[100];
8011 ++num_source_filenames
;
8012 current_function_file
= name
;
8013 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8014 output_quoted_string (stream
, name
);
8015 fprintf (stream
, "\n");
8016 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8017 fprintf (stream
, "\t#@stabs\n");
8020 else if (write_symbols
== DBX_DEBUG
)
8022 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
8023 fprintf (stream
, "%s", ASM_STABS_OP
);
8024 output_quoted_string (stream
, name
);
8025 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8028 else if (name
!= current_function_file
8029 && strcmp (name
, current_function_file
) != 0)
8031 if (inside_function
&& ! TARGET_GAS
)
8032 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8035 ++num_source_filenames
;
8036 current_function_file
= name
;
8037 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8040 output_quoted_string (stream
, name
);
8041 fprintf (stream
, "\n");
8045 /* Emit a linenumber to a stream. */
8048 alpha_output_lineno (FILE *stream
, int line
)
8050 if (write_symbols
== DBX_DEBUG
)
8052 /* mips-tfile doesn't understand .stabd directives. */
8054 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8055 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8058 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8061 /* Structure to show the current status of registers and memory. */
8063 struct shadow_summary
8066 unsigned int i
: 31; /* Mask of int regs */
8067 unsigned int fp
: 31; /* Mask of fp regs */
8068 unsigned int mem
: 1; /* mem == imem | fpmem */
8072 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8073 to the summary structure. SET is nonzero if the insn is setting the
8074 object, otherwise zero. */
8077 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8079 const char *format_ptr
;
8085 switch (GET_CODE (x
))
8087 /* ??? Note that this case would be incorrect if the Alpha had a
8088 ZERO_EXTRACT in SET_DEST. */
8090 summarize_insn (SET_SRC (x
), sum
, 0);
8091 summarize_insn (SET_DEST (x
), sum
, 1);
8095 summarize_insn (XEXP (x
, 0), sum
, 1);
8099 summarize_insn (XEXP (x
, 0), sum
, 0);
8103 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8104 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8108 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8109 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8113 summarize_insn (SUBREG_REG (x
), sum
, 0);
8118 int regno
= REGNO (x
);
8119 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8121 if (regno
== 31 || regno
== 63)
8127 sum
->defd
.i
|= mask
;
8129 sum
->defd
.fp
|= mask
;
8134 sum
->used
.i
|= mask
;
8136 sum
->used
.fp
|= mask
;
8147 /* Find the regs used in memory address computation: */
8148 summarize_insn (XEXP (x
, 0), sum
, 0);
8151 case CONST_INT
: case CONST_DOUBLE
:
8152 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8153 case SCRATCH
: case ASM_INPUT
:
8156 /* Handle common unary and binary ops for efficiency. */
8157 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8158 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8159 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8160 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8161 case NE
: case EQ
: case GE
: case GT
: case LE
:
8162 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8163 summarize_insn (XEXP (x
, 0), sum
, 0);
8164 summarize_insn (XEXP (x
, 1), sum
, 0);
8167 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8168 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8169 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8170 case SQRT
: case FFS
:
8171 summarize_insn (XEXP (x
, 0), sum
, 0);
8175 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8176 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8177 switch (format_ptr
[i
])
8180 summarize_insn (XEXP (x
, i
), sum
, 0);
8184 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8185 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8197 /* Ensure a sufficient number of `trapb' insns are in the code when
8198 the user requests code with a trap precision of functions or
8201 In naive mode, when the user requests a trap-precision of
8202 "instruction", a trapb is needed after every instruction that may
8203 generate a trap. This ensures that the code is resumption safe but
8206 When optimizations are turned on, we delay issuing a trapb as long
8207 as possible. In this context, a trap shadow is the sequence of
8208 instructions that starts with a (potentially) trap generating
8209 instruction and extends to the next trapb or call_pal instruction
8210 (but GCC never generates call_pal by itself). We can delay (and
8211 therefore sometimes omit) a trapb subject to the following
8214 (a) On entry to the trap shadow, if any Alpha register or memory
8215 location contains a value that is used as an operand value by some
8216 instruction in the trap shadow (live on entry), then no instruction
8217 in the trap shadow may modify the register or memory location.
8219 (b) Within the trap shadow, the computation of the base register
8220 for a memory load or store instruction may not involve using the
8221 result of an instruction that might generate an UNPREDICTABLE
8224 (c) Within the trap shadow, no register may be used more than once
8225 as a destination register. (This is to make life easier for the
8228 (d) The trap shadow may not include any branch instructions. */
8231 alpha_handle_trap_shadows (void)
8233 struct shadow_summary shadow
;
8234 int trap_pending
, exception_nesting
;
8238 exception_nesting
= 0;
8241 shadow
.used
.mem
= 0;
8242 shadow
.defd
= shadow
.used
;
8244 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8246 if (GET_CODE (i
) == NOTE
)
8248 switch (NOTE_LINE_NUMBER (i
))
8250 case NOTE_INSN_EH_REGION_BEG
:
8251 exception_nesting
++;
8256 case NOTE_INSN_EH_REGION_END
:
8257 exception_nesting
--;
8262 case NOTE_INSN_EPILOGUE_BEG
:
8263 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8268 else if (trap_pending
)
8270 if (alpha_tp
== ALPHA_TP_FUNC
)
8272 if (GET_CODE (i
) == JUMP_INSN
8273 && GET_CODE (PATTERN (i
)) == RETURN
)
8276 else if (alpha_tp
== ALPHA_TP_INSN
)
8280 struct shadow_summary sum
;
8285 sum
.defd
= sum
.used
;
8287 switch (GET_CODE (i
))
8290 /* Annoyingly, get_attr_trap will abort on these. */
8291 if (GET_CODE (PATTERN (i
)) == USE
8292 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8295 summarize_insn (PATTERN (i
), &sum
, 0);
8297 if ((sum
.defd
.i
& shadow
.defd
.i
)
8298 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8300 /* (c) would be violated */
8304 /* Combine shadow with summary of current insn: */
8305 shadow
.used
.i
|= sum
.used
.i
;
8306 shadow
.used
.fp
|= sum
.used
.fp
;
8307 shadow
.used
.mem
|= sum
.used
.mem
;
8308 shadow
.defd
.i
|= sum
.defd
.i
;
8309 shadow
.defd
.fp
|= sum
.defd
.fp
;
8310 shadow
.defd
.mem
|= sum
.defd
.mem
;
8312 if ((sum
.defd
.i
& shadow
.used
.i
)
8313 || (sum
.defd
.fp
& shadow
.used
.fp
)
8314 || (sum
.defd
.mem
& shadow
.used
.mem
))
8316 /* (a) would be violated (also takes care of (b)) */
8317 if (get_attr_trap (i
) == TRAP_YES
8318 && ((sum
.defd
.i
& sum
.used
.i
)
8319 || (sum
.defd
.fp
& sum
.used
.fp
)))
8338 n
= emit_insn_before (gen_trapb (), i
);
8339 PUT_MODE (n
, TImode
);
8340 PUT_MODE (i
, TImode
);
8344 shadow
.used
.mem
= 0;
8345 shadow
.defd
= shadow
.used
;
8350 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8351 && GET_CODE (i
) == INSN
8352 && GET_CODE (PATTERN (i
)) != USE
8353 && GET_CODE (PATTERN (i
)) != CLOBBER
8354 && get_attr_trap (i
) == TRAP_YES
)
8356 if (optimize
&& !trap_pending
)
8357 summarize_insn (PATTERN (i
), &shadow
, 0);
8363 /* Alpha can only issue instruction groups simultaneously if they are
8364 suitably aligned. This is very processor-specific. */
8366 enum alphaev4_pipe
{
8373 enum alphaev5_pipe
{
8384 static enum alphaev4_pipe
8385 alphaev4_insn_pipe (rtx insn
)
8387 if (recog_memoized (insn
) < 0)
8389 if (get_attr_length (insn
) != 4)
8392 switch (get_attr_type (insn
))
8426 static enum alphaev5_pipe
8427 alphaev5_insn_pipe (rtx insn
)
8429 if (recog_memoized (insn
) < 0)
8431 if (get_attr_length (insn
) != 4)
8434 switch (get_attr_type (insn
))
8475 /* IN_USE is a mask of the slots currently filled within the insn group.
8476 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8477 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8479 LEN is, of course, the length of the group in bytes. */
8482 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8489 || GET_CODE (PATTERN (insn
)) == CLOBBER
8490 || GET_CODE (PATTERN (insn
)) == USE
)
8495 enum alphaev4_pipe pipe
;
8497 pipe
= alphaev4_insn_pipe (insn
);
8501 /* Force complex instructions to start new groups. */
8505 /* If this is a completely unrecognized insn, its an asm.
8506 We don't know how long it is, so record length as -1 to
8507 signal a needed realignment. */
8508 if (recog_memoized (insn
) < 0)
8511 len
= get_attr_length (insn
);
8515 if (in_use
& EV4_IB0
)
8517 if (in_use
& EV4_IB1
)
8522 in_use
|= EV4_IB0
| EV4_IBX
;
8526 if (in_use
& EV4_IB0
)
8528 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8536 if (in_use
& EV4_IB1
)
8546 /* Haifa doesn't do well scheduling branches. */
8547 if (GET_CODE (insn
) == JUMP_INSN
)
8551 insn
= next_nonnote_insn (insn
);
8553 if (!insn
|| ! INSN_P (insn
))
8556 /* Let Haifa tell us where it thinks insn group boundaries are. */
8557 if (GET_MODE (insn
) == TImode
)
8560 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8565 insn
= next_nonnote_insn (insn
);
8573 /* IN_USE is a mask of the slots currently filled within the insn group.
8574 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8575 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8577 LEN is, of course, the length of the group in bytes. */
8580 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8587 || GET_CODE (PATTERN (insn
)) == CLOBBER
8588 || GET_CODE (PATTERN (insn
)) == USE
)
8593 enum alphaev5_pipe pipe
;
8595 pipe
= alphaev5_insn_pipe (insn
);
8599 /* Force complex instructions to start new groups. */
8603 /* If this is a completely unrecognized insn, its an asm.
8604 We don't know how long it is, so record length as -1 to
8605 signal a needed realignment. */
8606 if (recog_memoized (insn
) < 0)
8609 len
= get_attr_length (insn
);
8612 /* ??? Most of the places below, we would like to abort, as
8613 it would indicate an error either in Haifa, or in the
8614 scheduling description. Unfortunately, Haifa never
8615 schedules the last instruction of the BB, so we don't
8616 have an accurate TI bit to go off. */
8618 if (in_use
& EV5_E0
)
8620 if (in_use
& EV5_E1
)
8625 in_use
|= EV5_E0
| EV5_E01
;
8629 if (in_use
& EV5_E0
)
8631 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8639 if (in_use
& EV5_E1
)
8645 if (in_use
& EV5_FA
)
8647 if (in_use
& EV5_FM
)
8652 in_use
|= EV5_FA
| EV5_FAM
;
8656 if (in_use
& EV5_FA
)
8662 if (in_use
& EV5_FM
)
8675 /* Haifa doesn't do well scheduling branches. */
8676 /* ??? If this is predicted not-taken, slotting continues, except
8677 that no more IBR, FBR, or JSR insns may be slotted. */
8678 if (GET_CODE (insn
) == JUMP_INSN
)
8682 insn
= next_nonnote_insn (insn
);
8684 if (!insn
|| ! INSN_P (insn
))
8687 /* Let Haifa tell us where it thinks insn group boundaries are. */
8688 if (GET_MODE (insn
) == TImode
)
8691 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8696 insn
= next_nonnote_insn (insn
);
8705 alphaev4_next_nop (int *pin_use
)
8707 int in_use
= *pin_use
;
8710 if (!(in_use
& EV4_IB0
))
8715 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8720 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8733 alphaev5_next_nop (int *pin_use
)
8735 int in_use
= *pin_use
;
8738 if (!(in_use
& EV5_E1
))
8743 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8748 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8760 /* The instruction group alignment main loop. */
8763 alpha_align_insns (unsigned int max_align
,
8764 rtx (*next_group
) (rtx
, int *, int *),
8765 rtx (*next_nop
) (int *))
8767 /* ALIGN is the known alignment for the insn group. */
8769 /* OFS is the offset of the current insn in the insn group. */
8771 int prev_in_use
, in_use
, len
;
8774 /* Let shorten branches care for assigning alignments to code labels. */
8775 shorten_branches (get_insns ());
8777 if (align_functions
< 4)
8779 else if ((unsigned int) align_functions
< max_align
)
8780 align
= align_functions
;
8784 ofs
= prev_in_use
= 0;
8786 if (GET_CODE (i
) == NOTE
)
8787 i
= next_nonnote_insn (i
);
8791 next
= (*next_group
) (i
, &in_use
, &len
);
8793 /* When we see a label, resync alignment etc. */
8794 if (GET_CODE (i
) == CODE_LABEL
)
8796 unsigned int new_align
= 1 << label_to_alignment (i
);
8798 if (new_align
>= align
)
8800 align
= new_align
< max_align
? new_align
: max_align
;
8804 else if (ofs
& (new_align
-1))
8805 ofs
= (ofs
| (new_align
-1)) + 1;
8810 /* Handle complex instructions special. */
8811 else if (in_use
== 0)
8813 /* Asms will have length < 0. This is a signal that we have
8814 lost alignment knowledge. Assume, however, that the asm
8815 will not mis-align instructions. */
8824 /* If the known alignment is smaller than the recognized insn group,
8825 realign the output. */
8826 else if ((int) align
< len
)
8828 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8831 where
= prev
= prev_nonnote_insn (i
);
8832 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8835 /* Can't realign between a call and its gp reload. */
8836 if (! (TARGET_EXPLICIT_RELOCS
8837 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8839 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8840 align
= 1 << new_log_align
;
8845 /* If the group won't fit in the same INT16 as the previous,
8846 we need to add padding to keep the group together. Rather
8847 than simply leaving the insn filling to the assembler, we
8848 can make use of the knowledge of what sorts of instructions
8849 were issued in the previous group to make sure that all of
8850 the added nops are really free. */
8851 else if (ofs
+ len
> (int) align
)
8853 int nop_count
= (align
- ofs
) / 4;
8856 /* Insert nops before labels, branches, and calls to truly merge
8857 the execution of the nops with the previous instruction group. */
8858 where
= prev_nonnote_insn (i
);
8861 if (GET_CODE (where
) == CODE_LABEL
)
8863 rtx where2
= prev_nonnote_insn (where
);
8864 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8867 else if (GET_CODE (where
) == INSN
)
8874 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8875 while (--nop_count
);
8879 ofs
= (ofs
+ len
) & (align
- 1);
8880 prev_in_use
= in_use
;
8885 /* Machine dependent reorg pass. */
8890 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8891 alpha_handle_trap_shadows ();
8893 /* Due to the number of extra trapb insns, don't bother fixing up
8894 alignment when trap precision is instruction. Moreover, we can
8895 only do our job when sched2 is run. */
8896 if (optimize
&& !optimize_size
8897 && alpha_tp
!= ALPHA_TP_INSN
8898 && flag_schedule_insns_after_reload
)
8900 if (alpha_cpu
== PROCESSOR_EV4
)
8901 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
8902 else if (alpha_cpu
== PROCESSOR_EV5
)
8903 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
8907 #if !TARGET_ABI_UNICOSMK
8914 alpha_file_start (void)
8916 #ifdef OBJECT_FORMAT_ELF
8917 /* If emitting dwarf2 debug information, we cannot generate a .file
8918 directive to start the file, as it will conflict with dwarf2out
8919 file numbers. So it's only useful when emitting mdebug output. */
8920 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
8923 default_file_start ();
8925 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
8928 fputs ("\t.set noreorder\n", asm_out_file
);
8929 fputs ("\t.set volatile\n", asm_out_file
);
8930 if (!TARGET_ABI_OPEN_VMS
)
8931 fputs ("\t.set noat\n", asm_out_file
);
8932 if (TARGET_EXPLICIT_RELOCS
)
8933 fputs ("\t.set nomacro\n", asm_out_file
);
8934 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
8935 fprintf (asm_out_file
,
8937 TARGET_CPU_EV6
? "ev6"
8939 ? (TARGET_MAX
? "pca56" : TARGET_BWX
? "ev56" : "ev5")
8944 #ifdef OBJECT_FORMAT_ELF
8946 /* Switch to the section to which we should output X. The only thing
8947 special we do here is to honor small data. */
8950 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
8951 unsigned HOST_WIDE_INT align
)
8953 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8954 /* ??? Consider using mergeable sdata sections. */
8957 default_elf_select_rtx_section (mode
, x
, align
);
8960 #endif /* OBJECT_FORMAT_ELF */
8962 /* Structure to collect function names for final output in link section. */
8963 /* Note that items marked with GTY can't be ifdef'ed out. */
8965 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8966 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
8968 struct alpha_links
GTY(())
8972 enum links_kind lkind
;
8973 enum reloc_kind rkind
;
8976 struct alpha_funcs
GTY(())
8979 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8983 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8984 splay_tree alpha_links_tree
;
8985 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
8986 splay_tree alpha_funcs_tree
;
8988 static GTY(()) int alpha_funcs_num
;
8990 #if TARGET_ABI_OPEN_VMS
8992 /* Return the VMS argument type corresponding to MODE. */
8995 alpha_arg_type (enum machine_mode mode
)
9000 return TARGET_FLOAT_VAX
? FF
: FS
;
9002 return TARGET_FLOAT_VAX
? FD
: FT
;
9008 /* Return an rtx for an integer representing the VMS Argument Information
9012 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9014 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9017 for (i
= 0; i
< 6; i
++)
9018 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9020 return GEN_INT (regval
);
9023 /* Make (or fake) .linkage entry for function call.
9025 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9027 Return an SYMBOL_REF rtx for the linkage. */
9030 alpha_need_linkage (const char *name
, int is_local
)
9032 splay_tree_node node
;
9033 struct alpha_links
*al
;
9040 struct alpha_funcs
*cfaf
;
9042 if (!alpha_funcs_tree
)
9043 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9044 splay_tree_compare_pointers
);
9046 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9049 cfaf
->num
= ++alpha_funcs_num
;
9051 splay_tree_insert (alpha_funcs_tree
,
9052 (splay_tree_key
) current_function_decl
,
9053 (splay_tree_value
) cfaf
);
9056 if (alpha_links_tree
)
9058 /* Is this name already defined? */
9060 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9063 al
= (struct alpha_links
*) node
->value
;
9066 /* Defined here but external assumed. */
9067 if (al
->lkind
== KIND_EXTERN
)
9068 al
->lkind
= KIND_LOCAL
;
9072 /* Used here but unused assumed. */
9073 if (al
->lkind
== KIND_UNUSED
)
9074 al
->lkind
= KIND_LOCAL
;
9080 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9082 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9083 name
= ggc_strdup (name
);
9085 /* Assume external if no definition. */
9086 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9088 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9089 get_identifier (name
);
9091 /* Construct a SYMBOL_REF for us to call. */
9093 size_t name_len
= strlen (name
);
9094 char *linksym
= alloca (name_len
+ 6);
9096 memcpy (linksym
+ 1, name
, name_len
);
9097 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9098 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9099 ggc_alloc_string (linksym
, name_len
+ 5));
9102 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9103 (splay_tree_value
) al
);
9109 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9111 splay_tree_node cfunnode
;
9112 struct alpha_funcs
*cfaf
;
9113 struct alpha_links
*al
;
9114 const char *name
= XSTR (linkage
, 0);
9116 cfaf
= (struct alpha_funcs
*) 0;
9117 al
= (struct alpha_links
*) 0;
9119 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9120 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9124 splay_tree_node lnode
;
9126 /* Is this name already defined? */
9128 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9130 al
= (struct alpha_links
*) lnode
->value
;
9133 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9141 splay_tree_node node
= 0;
9142 struct alpha_links
*anl
;
9147 name_len
= strlen (name
);
9149 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9150 al
->num
= cfaf
->num
;
9152 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9155 anl
= (struct alpha_links
*) node
->value
;
9156 al
->lkind
= anl
->lkind
;
9159 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9160 buflen
= strlen (buf
);
9161 linksym
= alloca (buflen
+ 1);
9162 memcpy (linksym
, buf
, buflen
+ 1);
9164 al
->linkage
= gen_rtx_SYMBOL_REF
9165 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9167 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9168 (splay_tree_value
) al
);
9172 al
->rkind
= KIND_CODEADDR
;
9174 al
->rkind
= KIND_LINKAGE
;
9177 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9183 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9185 const char *const name
= (const char *) node
->key
;
9186 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9187 FILE *stream
= (FILE *) data
;
9189 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9190 if (link
->rkind
== KIND_CODEADDR
)
9192 if (link
->lkind
== KIND_LOCAL
)
9194 /* Local and used */
9195 fprintf (stream
, "\t.quad %s..en\n", name
);
9199 /* External and used, request code address. */
9200 fprintf (stream
, "\t.code_address %s\n", name
);
9205 if (link
->lkind
== KIND_LOCAL
)
9207 /* Local and used, build linkage pair. */
9208 fprintf (stream
, "\t.quad %s..en\n", name
);
9209 fprintf (stream
, "\t.quad %s\n", name
);
9213 /* External and used, request linkage pair. */
9214 fprintf (stream
, "\t.linkage %s\n", name
);
9222 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9224 splay_tree_node node
;
9225 struct alpha_funcs
*func
;
9228 fprintf (stream
, "\t.align 3\n");
9229 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9230 func
= (struct alpha_funcs
*) node
->value
;
9232 fputs ("\t.name ", stream
);
9233 assemble_name (stream
, funname
);
9234 fputs ("..na\n", stream
);
9235 ASM_OUTPUT_LABEL (stream
, funname
);
9236 fprintf (stream
, "\t.pdesc ");
9237 assemble_name (stream
, funname
);
9238 fprintf (stream
, "..en,%s\n",
9239 alpha_procedure_type
== PT_STACK
? "stack"
9240 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9244 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9245 /* splay_tree_delete (func->links); */
9249 /* Given a decl, a section name, and whether the decl initializer
9250 has relocs, choose attributes for the section. */
9252 #define SECTION_VMS_OVERLAY SECTION_FORGET
9253 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9254 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9257 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9259 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9261 if (decl
&& DECL_ATTRIBUTES (decl
)
9262 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9263 flags
|= SECTION_VMS_OVERLAY
;
9264 if (decl
&& DECL_ATTRIBUTES (decl
)
9265 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9266 flags
|= SECTION_VMS_GLOBAL
;
9267 if (decl
&& DECL_ATTRIBUTES (decl
)
9268 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9269 flags
|= SECTION_VMS_INITIALIZE
;
9274 /* Switch to an arbitrary section NAME with attributes as specified
9275 by FLAGS. ALIGN specifies any known alignment requirements for
9276 the section; 0 if the default should be used. */
9279 vms_asm_named_section (const char *name
, unsigned int flags
)
9281 fputc ('\n', asm_out_file
);
9282 fprintf (asm_out_file
, ".section\t%s", name
);
9284 if (flags
& SECTION_VMS_OVERLAY
)
9285 fprintf (asm_out_file
, ",OVR");
9286 if (flags
& SECTION_VMS_GLOBAL
)
9287 fprintf (asm_out_file
, ",GBL");
9288 if (flags
& SECTION_VMS_INITIALIZE
)
9289 fprintf (asm_out_file
, ",NOMOD");
9290 if (flags
& SECTION_DEBUG
)
9291 fprintf (asm_out_file
, ",NOWRT");
9293 fputc ('\n', asm_out_file
);
9296 /* Record an element in the table of global constructors. SYMBOL is
9297 a SYMBOL_REF of the function to be called; PRIORITY is a number
9298 between 0 and MAX_INIT_PRIORITY.
9300 Differs from default_ctors_section_asm_out_constructor in that the
9301 width of the .ctors entry is always 64 bits, rather than the 32 bits
9302 used by a normal pointer. */
9305 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9308 assemble_align (BITS_PER_WORD
);
9309 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9313 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9316 assemble_align (BITS_PER_WORD
);
9317 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9322 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9323 int is_local ATTRIBUTE_UNUSED
)
9329 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9330 tree cfundecl ATTRIBUTE_UNUSED
,
9331 int lflag ATTRIBUTE_UNUSED
,
9332 int rflag ATTRIBUTE_UNUSED
)
9337 #endif /* TARGET_ABI_OPEN_VMS */
9339 #if TARGET_ABI_UNICOSMK
9341 /* Define the offset between two registers, one to be eliminated, and the
9342 other its replacement, at the start of a routine. */
9345 unicosmk_initial_elimination_offset (int from
, int to
)
9349 fixed_size
= alpha_sa_size();
9350 if (fixed_size
!= 0)
9353 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9355 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9357 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9358 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9359 + ALPHA_ROUND (get_frame_size()));
9360 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9361 return (ALPHA_ROUND (fixed_size
)
9362 + ALPHA_ROUND (get_frame_size()
9363 + current_function_outgoing_args_size
));
9368 /* Output the module name for .ident and .end directives. We have to strip
9369 directories and add make sure that the module name starts with a letter
9373 unicosmk_output_module_name (FILE *file
)
9375 const char *name
= lbasename (main_input_filename
);
9376 unsigned len
= strlen (name
);
9377 char *clean_name
= alloca (len
+ 2);
9378 char *ptr
= clean_name
;
9380 /* CAM only accepts module names that start with a letter or '$'. We
9381 prefix the module name with a '$' if necessary. */
9383 if (!ISALPHA (*name
))
9385 memcpy (ptr
, name
, len
+ 1);
9386 clean_symbol_name (clean_name
);
9387 fputs (clean_name
, file
);
9390 /* Output the definition of a common variable. */
9393 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9396 printf ("T3E__: common %s\n", name
);
9399 fputs("\t.endp\n\n\t.psect ", file
);
9400 assemble_name(file
, name
);
9401 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9402 fprintf(file
, "\t.byte\t0:%d\n", size
);
9404 /* Mark the symbol as defined in this module. */
9405 name_tree
= get_identifier (name
);
9406 TREE_ASM_WRITTEN (name_tree
) = 1;
9409 #define SECTION_PUBLIC SECTION_MACH_DEP
9410 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9411 static int current_section_align
;
9414 unicosmk_section_type_flags (tree decl
, const char *name
,
9415 int reloc ATTRIBUTE_UNUSED
)
9417 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9422 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9424 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9425 if (align_functions_log
> current_section_align
)
9426 current_section_align
= align_functions_log
;
9428 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9429 flags
|= SECTION_MAIN
;
9432 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9434 if (TREE_PUBLIC (decl
))
9435 flags
|= SECTION_PUBLIC
;
9440 /* Generate a section name for decl and associate it with the
9444 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9452 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9453 name
= default_strip_name_encoding (name
);
9454 len
= strlen (name
);
9456 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9460 /* It is essential that we prefix the section name here because
9461 otherwise the section names generated for constructors and
9462 destructors confuse collect2. */
9464 string
= alloca (len
+ 6);
9465 sprintf (string
, "code@%s", name
);
9466 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9468 else if (TREE_PUBLIC (decl
))
9469 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9474 string
= alloca (len
+ 6);
9475 sprintf (string
, "data@%s", name
);
9476 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9480 /* Switch to an arbitrary section NAME with attributes as specified
9481 by FLAGS. ALIGN specifies any known alignment requirements for
9482 the section; 0 if the default should be used. */
9485 unicosmk_asm_named_section (const char *name
, unsigned int flags
)
9489 /* Close the previous section. */
9491 fputs ("\t.endp\n\n", asm_out_file
);
9493 /* Find out what kind of section we are opening. */
9495 if (flags
& SECTION_MAIN
)
9496 fputs ("\t.start\tmain\n", asm_out_file
);
9498 if (flags
& SECTION_CODE
)
9500 else if (flags
& SECTION_PUBLIC
)
9505 if (current_section_align
!= 0)
9506 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9507 current_section_align
, kind
);
9509 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9513 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9516 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9517 unicosmk_unique_section (decl
, 0);
9520 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9521 in code sections because .align fill unused space with zeroes. */
9524 unicosmk_output_align (FILE *file
, int align
)
9526 if (inside_function
)
9527 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9529 fprintf (file
, "\t.align\t%d\n", align
);
9532 /* Add a case vector to the current function's list of deferred case
9533 vectors. Case vectors have to be put into a separate section because CAM
9534 does not allow data definitions in code sections. */
9537 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9539 struct machine_function
*machine
= cfun
->machine
;
9541 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9542 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9543 machine
->addr_list
);
9546 /* Output a case vector. */
9549 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9551 rtx lab
= XEXP (vec
, 0);
9552 rtx body
= XEXP (vec
, 1);
9553 int vlen
= XVECLEN (body
, 0);
9556 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9558 for (idx
= 0; idx
< vlen
; idx
++)
9560 ASM_OUTPUT_ADDR_VEC_ELT
9561 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9565 /* Output current function's deferred case vectors. */
9568 unicosmk_output_deferred_case_vectors (FILE *file
)
9570 struct machine_function
*machine
= cfun
->machine
;
9573 if (machine
->addr_list
== NULL_RTX
)
9577 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9578 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9581 /* Generate the name of the SSIB section for the current function. */
9583 #define SSIB_PREFIX "__SSIB_"
9584 #define SSIB_PREFIX_LEN 7
9587 unicosmk_ssib_name (void)
9589 /* This is ok since CAM won't be able to deal with names longer than that
9592 static char name
[256];
9598 x
= DECL_RTL (cfun
->decl
);
9599 if (GET_CODE (x
) != MEM
)
9602 if (GET_CODE (x
) != SYMBOL_REF
)
9604 fnname
= XSTR (x
, 0);
9606 len
= strlen (fnname
);
9607 if (len
+ SSIB_PREFIX_LEN
> 255)
9608 len
= 255 - SSIB_PREFIX_LEN
;
9610 strcpy (name
, SSIB_PREFIX
);
9611 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9612 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9617 /* Set up the dynamic subprogram information block (DSIB) and update the
9618 frame pointer register ($15) for subroutines which have a frame. If the
9619 subroutine doesn't have a frame, simply increment $15. */
9622 unicosmk_gen_dsib (unsigned long *imaskP
)
9624 if (alpha_procedure_type
== PT_STACK
)
9626 const char *ssib_name
;
9629 /* Allocate 64 bytes for the DSIB. */
9631 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9633 emit_insn (gen_blockage ());
9635 /* Save the return address. */
9637 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9638 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9639 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9640 (*imaskP
) &= ~(1UL << REG_RA
);
9642 /* Save the old frame pointer. */
9644 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9645 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9646 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9647 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9649 emit_insn (gen_blockage ());
9651 /* Store the SSIB pointer. */
9653 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9654 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9655 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9657 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9658 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9659 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9661 /* Save the CIW index. */
9663 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9664 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9665 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9667 emit_insn (gen_blockage ());
9669 /* Set the new frame pointer. */
9671 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9672 stack_pointer_rtx
, GEN_INT (64))));
9677 /* Increment the frame pointer register to indicate that we do not
9680 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9681 hard_frame_pointer_rtx
, GEN_INT (1))));
9685 /* Output the static subroutine information block for the current
9689 unicosmk_output_ssib (FILE *file
, const char *fnname
)
9695 struct machine_function
*machine
= cfun
->machine
;
9698 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9699 unicosmk_ssib_name ());
9701 /* Some required stuff and the function name length. */
9703 len
= strlen (fnname
);
9704 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9707 ??? We don't do that yet. */
9709 fputs ("\t.quad\t0\n", file
);
9711 /* Function address. */
9713 fputs ("\t.quad\t", file
);
9714 assemble_name (file
, fnname
);
9717 fputs ("\t.quad\t0\n", file
);
9718 fputs ("\t.quad\t0\n", file
);
9721 ??? We do it the same way Cray CC does it but this could be
9724 for( i
= 0; i
< len
; i
++ )
9725 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9726 if( (len
% 8) == 0 )
9727 fputs ("\t.quad\t0\n", file
);
9729 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9731 /* All call information words used in the function. */
9733 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9736 #if HOST_BITS_PER_WIDE_INT == 32
9737 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
9738 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9740 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
9745 /* Add a call information word (CIW) to the list of the current function's
9746 CIWs and return its index.
9748 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9751 unicosmk_add_call_info_word (rtx x
)
9754 struct machine_function
*machine
= cfun
->machine
;
9756 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9757 if (machine
->first_ciw
== NULL_RTX
)
9758 machine
->first_ciw
= node
;
9760 XEXP (machine
->last_ciw
, 1) = node
;
9762 machine
->last_ciw
= node
;
9763 ++machine
->ciw_count
;
9765 return GEN_INT (machine
->ciw_count
9766 + strlen (current_function_name ())/8 + 5);
9769 static char unicosmk_section_buf
[100];
9772 unicosmk_text_section (void)
9774 static int count
= 0;
9775 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9777 return unicosmk_section_buf
;
9781 unicosmk_data_section (void)
9783 static int count
= 1;
9784 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9786 return unicosmk_section_buf
;
9789 /* The Cray assembler doesn't accept extern declarations for symbols which
9790 are defined in the same file. We have to keep track of all global
9791 symbols which are referenced and/or defined in a source file and output
9792 extern declarations for those which are referenced but not defined at
9795 /* List of identifiers for which an extern declaration might have to be
9797 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9799 struct unicosmk_extern_list
9801 struct unicosmk_extern_list
*next
;
9805 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9807 /* Output extern declarations which are required for every asm file. */
9810 unicosmk_output_default_externs (FILE *file
)
9812 static const char *const externs
[] =
9813 { "__T3E_MISMATCH" };
9818 n
= ARRAY_SIZE (externs
);
9820 for (i
= 0; i
< n
; i
++)
9821 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9824 /* Output extern declarations for global symbols which are have been
9825 referenced but not defined. */
9828 unicosmk_output_externs (FILE *file
)
9830 struct unicosmk_extern_list
*p
;
9831 const char *real_name
;
9835 len
= strlen (user_label_prefix
);
9836 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9838 /* We have to strip the encoding and possibly remove user_label_prefix
9839 from the identifier in order to handle -fleading-underscore and
9840 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9841 real_name
= default_strip_name_encoding (p
->name
);
9842 if (len
&& p
->name
[0] == '*'
9843 && !memcmp (real_name
, user_label_prefix
, len
))
9846 name_tree
= get_identifier (real_name
);
9847 if (! TREE_ASM_WRITTEN (name_tree
))
9849 TREE_ASM_WRITTEN (name_tree
) = 1;
9850 fputs ("\t.extern\t", file
);
9851 assemble_name (file
, p
->name
);
9857 /* Record an extern. */
9860 unicosmk_add_extern (const char *name
)
9862 struct unicosmk_extern_list
*p
;
9864 p
= (struct unicosmk_extern_list
*)
9865 xmalloc (sizeof (struct unicosmk_extern_list
));
9866 p
->next
= unicosmk_extern_head
;
9868 unicosmk_extern_head
= p
;
9871 /* The Cray assembler generates incorrect code if identifiers which
9872 conflict with register names are used as instruction operands. We have
9873 to replace such identifiers with DEX expressions. */
9875 /* Structure to collect identifiers which have been replaced by DEX
9877 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9879 struct unicosmk_dex
{
9880 struct unicosmk_dex
*next
;
9884 /* List of identifiers which have been replaced by DEX expressions. The DEX
9885 number is determined by the position in the list. */
9887 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9889 /* The number of elements in the DEX list. */
9891 static int unicosmk_dex_count
= 0;
9893 /* Check if NAME must be replaced by a DEX expression. */
9896 unicosmk_special_name (const char *name
)
9904 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9910 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9913 return (name
[2] == '\0'
9914 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9917 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9921 /* Return the DEX number if X must be replaced by a DEX expression and 0
9925 unicosmk_need_dex (rtx x
)
9927 struct unicosmk_dex
*dex
;
9931 if (GET_CODE (x
) != SYMBOL_REF
)
9935 if (! unicosmk_special_name (name
))
9938 i
= unicosmk_dex_count
;
9939 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9941 if (! strcmp (name
, dex
->name
))
9946 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
9948 dex
->next
= unicosmk_dex_list
;
9949 unicosmk_dex_list
= dex
;
9951 ++unicosmk_dex_count
;
9952 return unicosmk_dex_count
;
9955 /* Output the DEX definitions for this file. */
9958 unicosmk_output_dex (FILE *file
)
9960 struct unicosmk_dex
*dex
;
9963 if (unicosmk_dex_list
== NULL
)
9966 fprintf (file
, "\t.dexstart\n");
9968 i
= unicosmk_dex_count
;
9969 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9971 fprintf (file
, "\tDEX (%d) = ", i
);
9972 assemble_name (file
, dex
->name
);
9977 fprintf (file
, "\t.dexend\n");
9980 /* Output text that to appear at the beginning of an assembler file. */
9983 unicosmk_file_start (void)
9987 fputs ("\t.ident\t", asm_out_file
);
9988 unicosmk_output_module_name (asm_out_file
);
9989 fputs ("\n\n", asm_out_file
);
9991 /* The Unicos/Mk assembler uses different register names. Instead of trying
9992 to support them, we simply use micro definitions. */
9994 /* CAM has different register names: rN for the integer register N and fN
9995 for the floating-point register N. Instead of trying to use these in
9996 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9999 for (i
= 0; i
< 32; ++i
)
10000 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
10002 for (i
= 0; i
< 32; ++i
)
10003 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
10005 putc ('\n', asm_out_file
);
10007 /* The .align directive fill unused space with zeroes which does not work
10008 in code sections. We define the macro 'gcc@code@align' which uses nops
10009 instead. Note that it assumes that code sections always have the
10010 biggest possible alignment since . refers to the current offset from
10011 the beginning of the section. */
10013 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
10014 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
10015 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
10016 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
10017 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
10018 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
10019 fputs ("\t.endr\n", asm_out_file
);
10020 fputs ("\t.endif\n", asm_out_file
);
10021 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
10023 /* Output extern declarations which should always be visible. */
10024 unicosmk_output_default_externs (asm_out_file
);
10026 /* Open a dummy section. We always need to be inside a section for the
10027 section-switching code to work correctly.
10028 ??? This should be a module id or something like that. I still have to
10029 figure out what the rules for those are. */
10030 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10033 /* Output text to appear at the end of an assembler file. This includes all
10034 pending extern declarations and DEX expressions. */
10037 unicosmk_file_end (void)
10039 fputs ("\t.endp\n\n", asm_out_file
);
10041 /* Output all pending externs. */
10043 unicosmk_output_externs (asm_out_file
);
10045 /* Output dex definitions used for functions whose names conflict with
10048 unicosmk_output_dex (asm_out_file
);
10050 fputs ("\t.end\t", asm_out_file
);
10051 unicosmk_output_module_name (asm_out_file
);
10052 putc ('\n', asm_out_file
);
10058 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10062 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10066 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10067 const char * fnname ATTRIBUTE_UNUSED
)
10071 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10077 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10082 #endif /* TARGET_ABI_UNICOSMK */
10085 alpha_init_libfuncs (void)
10087 if (TARGET_ABI_UNICOSMK
)
10089 /* Prevent gcc from generating calls to __divsi3. */
10090 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10091 set_optab_libfunc (udiv_optab
, SImode
, 0);
10093 /* Use the functions provided by the system library
10094 for DImode integer division. */
10095 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10096 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10098 else if (TARGET_ABI_OPEN_VMS
)
10100 /* Use the VMS runtime library functions for division and
10102 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10103 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10104 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10105 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10106 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10107 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10108 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10109 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10114 /* Initialize the GCC target structure. */
10115 #if TARGET_ABI_OPEN_VMS
10116 # undef TARGET_ATTRIBUTE_TABLE
10117 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10118 # undef TARGET_SECTION_TYPE_FLAGS
10119 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10122 #undef TARGET_IN_SMALL_DATA_P
10123 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10125 #if TARGET_ABI_UNICOSMK
10126 # undef TARGET_INSERT_ATTRIBUTES
10127 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10128 # undef TARGET_SECTION_TYPE_FLAGS
10129 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10130 # undef TARGET_ASM_UNIQUE_SECTION
10131 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10132 # undef TARGET_ASM_GLOBALIZE_LABEL
10133 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10136 #undef TARGET_ASM_ALIGNED_HI_OP
10137 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10138 #undef TARGET_ASM_ALIGNED_DI_OP
10139 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10141 /* Default unaligned ops are provided for ELF systems. To get unaligned
10142 data for non-ELF systems, we have to turn off auto alignment. */
10143 #ifndef OBJECT_FORMAT_ELF
10144 #undef TARGET_ASM_UNALIGNED_HI_OP
10145 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10146 #undef TARGET_ASM_UNALIGNED_SI_OP
10147 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10148 #undef TARGET_ASM_UNALIGNED_DI_OP
10149 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10152 #ifdef OBJECT_FORMAT_ELF
10153 #undef TARGET_ASM_SELECT_RTX_SECTION
10154 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10157 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10158 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10160 #undef TARGET_INIT_LIBFUNCS
10161 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10163 #if TARGET_ABI_UNICOSMK
10164 #undef TARGET_ASM_FILE_START
10165 #define TARGET_ASM_FILE_START unicosmk_file_start
10166 #undef TARGET_ASM_FILE_END
10167 #define TARGET_ASM_FILE_END unicosmk_file_end
10169 #undef TARGET_ASM_FILE_START
10170 #define TARGET_ASM_FILE_START alpha_file_start
10171 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10172 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10175 #undef TARGET_SCHED_ADJUST_COST
10176 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10177 #undef TARGET_SCHED_ISSUE_RATE
10178 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10179 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10180 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10181 alpha_use_dfa_pipeline_interface
10182 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10183 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10184 alpha_multipass_dfa_lookahead
10186 #undef TARGET_HAVE_TLS
10187 #define TARGET_HAVE_TLS HAVE_AS_TLS
10189 #undef TARGET_INIT_BUILTINS
10190 #define TARGET_INIT_BUILTINS alpha_init_builtins
10191 #undef TARGET_EXPAND_BUILTIN
10192 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10194 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10195 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10196 #undef TARGET_CANNOT_COPY_INSN_P
10197 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10200 #undef TARGET_ASM_OUTPUT_MI_THUNK
10201 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10202 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10203 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10206 #undef TARGET_RTX_COSTS
10207 #define TARGET_RTX_COSTS alpha_rtx_costs
10208 #undef TARGET_ADDRESS_COST
10209 #define TARGET_ADDRESS_COST hook_int_rtx_0
10211 #undef TARGET_MACHINE_DEPENDENT_REORG
10212 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10214 #undef TARGET_PROMOTE_FUNCTION_ARGS
10215 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10216 #undef TARGET_PROMOTE_FUNCTION_RETURN
10217 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10218 #undef TARGET_PROMOTE_PROTOTYPES
10219 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10220 #undef TARGET_STRUCT_VALUE_RTX
10221 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
10222 #undef TARGET_RETURN_IN_MEMORY
10223 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10224 #undef TARGET_SETUP_INCOMING_VARARGS
10225 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10226 #undef TARGET_STRICT_ARGUMENT_NAMING
10227 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10228 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10229 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10231 #undef TARGET_BUILD_BUILTIN_VA_LIST
10232 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10234 struct gcc_target targetm
= TARGET_INITIALIZER
;
10237 #include "gt-alpha.h"