1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 /* Specify which cpu to schedule for. */
58 enum processor_type alpha_cpu
;
59 static const char * const alpha_cpu_name
[] =
64 /* Specify how accurate floating-point traps need to be. */
66 enum alpha_trap_precision alpha_tp
;
68 /* Specify the floating-point rounding mode. */
70 enum alpha_fp_rounding_mode alpha_fprm
;
72 /* Specify which things cause traps. */
74 enum alpha_fp_trap_mode alpha_fptm
;
76 /* Specify bit size of immediate TLS offsets. */
78 int alpha_tls_size
= 32;
80 /* Strings decoded into the above options. */
82 const char *alpha_cpu_string
; /* -mcpu= */
83 const char *alpha_tune_string
; /* -mtune= */
84 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
85 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
86 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
87 const char *alpha_mlat_string
; /* -mmemory-latency= */
88 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
90 /* Save information from a "cmpxx" operation until the branch or scc is
93 struct alpha_compare alpha_compare
;
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
98 static int inside_function
= FALSE
;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency
= 3;
104 /* Whether the function needs the GP. */
106 static int alpha_function_needs_gp
;
108 /* The alias set for prologue/epilogue register save/restore. */
110 static GTY(()) int alpha_sr_alias_set
;
112 /* The assembler name of the current function. */
114 static const char *alpha_fnname
;
116 /* The next explicit relocation sequence number. */
117 extern GTY(()) int alpha_next_sequence_number
;
118 int alpha_next_sequence_number
= 1;
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
122 extern GTY(()) int alpha_this_literal_sequence_number
;
123 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
124 int alpha_this_literal_sequence_number
;
125 int alpha_this_gpdisp_sequence_number
;
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
131 unsigned char fp_add
;
132 unsigned char fp_mult
;
133 unsigned char fp_div_sf
;
134 unsigned char fp_div_df
;
135 unsigned char int_mult_si
;
136 unsigned char int_mult_di
;
137 unsigned char int_shift
;
138 unsigned char int_cmov
;
141 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
144 COSTS_N_INSNS (6), /* fp_add */
145 COSTS_N_INSNS (6), /* fp_mult */
146 COSTS_N_INSNS (34), /* fp_div_sf */
147 COSTS_N_INSNS (63), /* fp_div_df */
148 COSTS_N_INSNS (23), /* int_mult_si */
149 COSTS_N_INSNS (23), /* int_mult_di */
150 COSTS_N_INSNS (2), /* int_shift */
151 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (15), /* fp_div_sf */
157 COSTS_N_INSNS (22), /* fp_div_df */
158 COSTS_N_INSNS (8), /* int_mult_si */
159 COSTS_N_INSNS (12), /* int_mult_di */
160 COSTS_N_INSNS (1) + 1, /* int_shift */
161 COSTS_N_INSNS (1), /* int_cmov */
164 COSTS_N_INSNS (4), /* fp_add */
165 COSTS_N_INSNS (4), /* fp_mult */
166 COSTS_N_INSNS (12), /* fp_div_sf */
167 COSTS_N_INSNS (15), /* fp_div_df */
168 COSTS_N_INSNS (7), /* int_mult_si */
169 COSTS_N_INSNS (7), /* int_mult_di */
170 COSTS_N_INSNS (1), /* int_shift */
171 COSTS_N_INSNS (2), /* int_cmov */
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
179 #define NUM_ARGS current_function_args_info
185 /* Declarations of static functions. */
186 static struct machine_function
*alpha_init_machine_status (void);
187 static rtx
alpha_emit_xfloating_compare (enum rtx_code
, rtx
, rtx
);
189 #if TARGET_ABI_OPEN_VMS
190 static void alpha_write_linkage (FILE *, const char *, tree
);
193 static void unicosmk_output_deferred_case_vectors (FILE *);
194 static void unicosmk_gen_dsib (unsigned long *);
195 static void unicosmk_output_ssib (FILE *, const char *);
196 static int unicosmk_need_dex (rtx
);
198 /* Parse target option strings. */
201 override_options (void)
204 static const struct cpu_table
{
205 const char *const name
;
206 const enum processor_type processor
;
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
211 { "ev4", PROCESSOR_EV4
, 0 },
212 { "ev45", PROCESSOR_EV4
, 0 },
213 { "21064", PROCESSOR_EV4
, 0 },
214 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
215 { "21164", PROCESSOR_EV5
, EV5_MASK
},
216 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
217 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
218 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
219 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
220 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
221 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
222 { "21264", PROCESSOR_EV6
, EV6_MASK
},
223 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
224 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
228 /* Unicos/Mk doesn't have shared libraries. */
229 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
231 warning ("-f%s ignored for Unicos/Mk (not supported)",
232 (flag_pic
> 1) ? "PIC" : "pic");
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
238 if (TARGET_ABI_UNICOSMK
)
239 alpha_fprm
= ALPHA_FPRM_DYN
;
241 alpha_fprm
= ALPHA_FPRM_NORM
;
243 alpha_tp
= ALPHA_TP_PROG
;
244 alpha_fptm
= ALPHA_FPTM_N
;
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
254 if (TARGET_ABI_UNICOSMK
)
255 warning ("-mieee not supported on Unicos/Mk");
258 alpha_tp
= ALPHA_TP_INSN
;
259 alpha_fptm
= ALPHA_FPTM_SU
;
263 if (TARGET_IEEE_WITH_INEXACT
)
265 if (TARGET_ABI_UNICOSMK
)
266 warning ("-mieee-with-inexact not supported on Unicos/Mk");
269 alpha_tp
= ALPHA_TP_INSN
;
270 alpha_fptm
= ALPHA_FPTM_SUI
;
276 if (! strcmp (alpha_tp_string
, "p"))
277 alpha_tp
= ALPHA_TP_PROG
;
278 else if (! strcmp (alpha_tp_string
, "f"))
279 alpha_tp
= ALPHA_TP_FUNC
;
280 else if (! strcmp (alpha_tp_string
, "i"))
281 alpha_tp
= ALPHA_TP_INSN
;
283 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
286 if (alpha_fprm_string
)
288 if (! strcmp (alpha_fprm_string
, "n"))
289 alpha_fprm
= ALPHA_FPRM_NORM
;
290 else if (! strcmp (alpha_fprm_string
, "m"))
291 alpha_fprm
= ALPHA_FPRM_MINF
;
292 else if (! strcmp (alpha_fprm_string
, "c"))
293 alpha_fprm
= ALPHA_FPRM_CHOP
;
294 else if (! strcmp (alpha_fprm_string
,"d"))
295 alpha_fprm
= ALPHA_FPRM_DYN
;
297 error ("bad value `%s' for -mfp-rounding-mode switch",
301 if (alpha_fptm_string
)
303 if (strcmp (alpha_fptm_string
, "n") == 0)
304 alpha_fptm
= ALPHA_FPTM_N
;
305 else if (strcmp (alpha_fptm_string
, "u") == 0)
306 alpha_fptm
= ALPHA_FPTM_U
;
307 else if (strcmp (alpha_fptm_string
, "su") == 0)
308 alpha_fptm
= ALPHA_FPTM_SU
;
309 else if (strcmp (alpha_fptm_string
, "sui") == 0)
310 alpha_fptm
= ALPHA_FPTM_SUI
;
312 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
315 if (alpha_tls_size_string
)
317 if (strcmp (alpha_tls_size_string
, "16") == 0)
319 else if (strcmp (alpha_tls_size_string
, "32") == 0)
321 else if (strcmp (alpha_tls_size_string
, "64") == 0)
324 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
328 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
329 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
331 if (alpha_cpu_string
)
333 for (i
= 0; cpu_table
[i
].name
; i
++)
334 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
336 alpha_cpu
= cpu_table
[i
].processor
;
337 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
338 | MASK_CPU_EV5
| MASK_CPU_EV6
);
339 target_flags
|= cpu_table
[i
].flags
;
342 if (! cpu_table
[i
].name
)
343 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
346 if (alpha_tune_string
)
348 for (i
= 0; cpu_table
[i
].name
; i
++)
349 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
351 alpha_cpu
= cpu_table
[i
].processor
;
354 if (! cpu_table
[i
].name
)
355 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
358 /* Do some sanity checks on the above options. */
360 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
362 warning ("trap mode not supported on Unicos/Mk");
363 alpha_fptm
= ALPHA_FPTM_N
;
366 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
367 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
369 warning ("fp software completion requires -mtrap-precision=i");
370 alpha_tp
= ALPHA_TP_INSN
;
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
378 alpha_tp
= ALPHA_TP_PROG
;
381 if (TARGET_FLOAT_VAX
)
383 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
385 warning ("rounding mode not supported for VAX floats");
386 alpha_fprm
= ALPHA_FPRM_NORM
;
388 if (alpha_fptm
== ALPHA_FPTM_SUI
)
390 warning ("trap mode not supported for VAX floats");
391 alpha_fptm
= ALPHA_FPTM_SU
;
399 if (!alpha_mlat_string
)
400 alpha_mlat_string
= "L1";
402 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
403 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
405 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
406 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
407 && alpha_mlat_string
[2] == '\0')
409 static int const cache_latency
[][4] =
411 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
412 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
413 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
416 lat
= alpha_mlat_string
[1] - '0';
417 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
419 warning ("L%d cache latency unknown for %s",
420 lat
, alpha_cpu_name
[alpha_cpu
]);
424 lat
= cache_latency
[alpha_cpu
][lat
-1];
426 else if (! strcmp (alpha_mlat_string
, "main"))
428 /* Most current memories have about 370ns latency. This is
429 a reasonable guess for a fast cpu. */
434 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
438 alpha_memory_latency
= lat
;
441 /* Default the definition of "small data" to 8 bytes. */
445 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
447 target_flags
|= MASK_SMALL_DATA
;
448 else if (flag_pic
== 2)
449 target_flags
&= ~MASK_SMALL_DATA
;
451 /* Align labels and loops for optimal branching. */
452 /* ??? Kludge these by not doing anything if we don't optimize and also if
453 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
454 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
456 if (align_loops
<= 0)
458 if (align_jumps
<= 0)
461 if (align_functions
<= 0)
462 align_functions
= 16;
464 /* Acquire a unique set number for our register saves and restores. */
465 alpha_sr_alias_set
= new_alias_set ();
467 /* Register variables and functions with the garbage collector. */
469 /* Set up function hooks. */
470 init_machine_status
= alpha_init_machine_status
;
472 /* Tell the compiler when we're using VAX floating point. */
473 if (TARGET_FLOAT_VAX
)
475 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
476 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
477 REAL_MODE_FORMAT (TFmode
) = NULL
;
481 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
484 zap_mask (HOST_WIDE_INT value
)
488 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
490 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
496 /* Returns 1 if OP is either the constant zero or a register. If a
497 register, it must be in the proper mode unless MODE is VOIDmode. */
500 reg_or_0_operand (rtx op
, enum machine_mode mode
)
502 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
505 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
509 reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
511 return ((GET_CODE (op
) == CONST_INT
512 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
513 || register_operand (op
, mode
));
517 /* Return 1 if OP is an 8-bit constant or any register. */
520 reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
522 return ((GET_CODE (op
) == CONST_INT
523 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
524 || register_operand (op
, mode
));
527 /* Return 1 if OP is a constant or any register. */
530 reg_or_const_int_operand (rtx op
, enum machine_mode mode
)
532 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
535 /* Return 1 if OP is an 8-bit constant. */
538 cint8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
540 return ((GET_CODE (op
) == CONST_INT
541 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
544 /* Return 1 if the operand is a valid second operand to an add insn. */
547 add_operand (rtx op
, enum machine_mode mode
)
549 if (GET_CODE (op
) == CONST_INT
)
550 /* Constraints I, J, O and P are covered by K. */
551 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
552 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
554 return register_operand (op
, mode
);
557 /* Return 1 if the operand is a valid second operand to a sign-extending
561 sext_add_operand (rtx op
, enum machine_mode mode
)
563 if (GET_CODE (op
) == CONST_INT
)
564 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
565 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
567 return reg_not_elim_operand (op
, mode
);
570 /* Return 1 if OP is the constant 4 or 8. */
573 const48_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
575 return (GET_CODE (op
) == CONST_INT
576 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
579 /* Return 1 if OP is a valid first operand to an AND insn. */
582 and_operand (rtx op
, enum machine_mode mode
)
584 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
585 return (zap_mask (CONST_DOUBLE_LOW (op
))
586 && zap_mask (CONST_DOUBLE_HIGH (op
)));
588 if (GET_CODE (op
) == CONST_INT
)
589 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
590 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
591 || zap_mask (INTVAL (op
)));
593 return register_operand (op
, mode
);
596 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
599 or_operand (rtx op
, enum machine_mode mode
)
601 if (GET_CODE (op
) == CONST_INT
)
602 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
603 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
605 return register_operand (op
, mode
);
608 /* Return 1 if OP is a constant that is the width, in bits, of an integral
609 mode smaller than DImode. */
612 mode_width_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
614 return (GET_CODE (op
) == CONST_INT
615 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
616 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
619 /* Return 1 if OP is a constant that is the width of an integral machine mode
620 smaller than an integer. */
623 mode_mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
625 if (GET_CODE (op
) == CONST_INT
)
627 HOST_WIDE_INT value
= INTVAL (op
);
633 if (value
== 0xffffffff)
638 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
640 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
647 /* Return 1 if OP is a multiple of 8 less than 64. */
650 mul8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
652 return (GET_CODE (op
) == CONST_INT
653 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
654 && (INTVAL (op
) & 7) == 0);
657 /* Return 1 if OP is the zero constant for MODE. */
660 const0_operand (rtx op
, enum machine_mode mode
)
662 return op
== CONST0_RTX (mode
);
665 /* Return 1 if OP is a hard floating-point register. */
668 hard_fp_register_operand (rtx op
, enum machine_mode mode
)
670 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
673 if (GET_CODE (op
) == SUBREG
)
674 op
= SUBREG_REG (op
);
675 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
678 /* Return 1 if OP is a hard general register. */
681 hard_int_register_operand (rtx op
, enum machine_mode mode
)
683 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
686 if (GET_CODE (op
) == SUBREG
)
687 op
= SUBREG_REG (op
);
688 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
691 /* Return 1 if OP is a register or a constant integer. */
695 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
697 return (GET_CODE (op
) == CONST_INT
698 || register_operand (op
, mode
));
701 /* Return 1 if OP is something that can be reloaded into a register;
702 if it is a MEM, it need not be valid. */
705 some_operand (rtx op
, enum machine_mode mode
)
707 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
710 switch (GET_CODE (op
))
724 return some_operand (SUBREG_REG (op
), VOIDmode
);
733 /* Likewise, but don't accept constants. */
736 some_ni_operand (rtx op
, enum machine_mode mode
)
738 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
741 if (GET_CODE (op
) == SUBREG
)
742 op
= SUBREG_REG (op
);
744 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
747 /* Return 1 if OP is a valid operand for the source of a move insn. */
750 input_operand (rtx op
, enum machine_mode mode
)
752 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
755 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
758 switch (GET_CODE (op
))
763 if (TARGET_EXPLICIT_RELOCS
)
765 /* We don't split symbolic operands into something unintelligable
766 until after reload, but we do not wish non-small, non-global
767 symbolic operands to be reconstructed from their high/lo_sum
769 return (small_symbolic_operand (op
, mode
)
770 || global_symbolic_operand (op
, mode
)
771 || gotdtp_symbolic_operand (op
, mode
)
772 || gottp_symbolic_operand (op
, mode
));
775 /* This handles both the Windows/NT and OSF cases. */
776 return mode
== ptr_mode
|| mode
== DImode
;
779 return (TARGET_EXPLICIT_RELOCS
780 && local_symbolic_operand (XEXP (op
, 0), mode
));
787 if (register_operand (op
, mode
))
789 /* ... fall through ... */
791 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
792 && general_operand (op
, mode
));
796 return op
== CONST0_RTX (mode
);
799 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
811 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
812 file, and in the same section as the current function. */
815 samegp_function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
817 if (GET_CODE (op
) != SYMBOL_REF
)
820 /* Easy test for recursion. */
821 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
824 /* Functions that are not local can be overridden, and thus may
825 not share the same gp. */
826 if (! SYMBOL_REF_LOCAL_P (op
))
829 /* If -msmall-data is in effect, assume that there is only one GP
830 for the module, and so any local symbol has this property. We
831 need explicit relocations to be able to enforce this for symbols
832 not defined in this unit of translation, however. */
833 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
836 /* Functions that are not external are defined in this UoT,
837 and thus must share the same gp. */
838 return ! SYMBOL_REF_EXTERNAL_P (op
);
841 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
844 direct_call_operand (rtx op
, enum machine_mode mode
)
846 tree op_decl
, cfun_sec
, op_sec
;
848 /* Must share the same GP. */
849 if (!samegp_function_operand (op
, mode
))
852 /* If profiling is implemented via linker tricks, we can't jump
853 to the nogp alternate entry point. Note that current_function_profile
854 would not be correct, since that doesn't indicate if the target
855 function uses profiling. */
856 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
857 but is approximately correct for the OSF ABIs. Don't know
858 what to do for VMS, NT, or UMK. */
859 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
862 /* Must be a function. In some cases folks create thunks in static
863 data structures and then make calls to them. If we allow the
864 direct call, we'll get an error from the linker about !samegp reloc
865 against a symbol without a .prologue directive. */
866 if (!SYMBOL_REF_FUNCTION_P (op
))
869 /* Must be "near" so that the branch is assumed to reach. With
870 -msmall-text, this is assumed true of all local symbols. Since
871 we've already checked samegp, locality is already assured. */
872 if (TARGET_SMALL_TEXT
)
875 /* Otherwise, a decl is "near" if it is defined in the same section. */
876 if (flag_function_sections
)
879 op_decl
= SYMBOL_REF_DECL (op
);
880 if (DECL_ONE_ONLY (current_function_decl
)
881 || (op_decl
&& DECL_ONE_ONLY (op_decl
)))
884 cfun_sec
= DECL_SECTION_NAME (current_function_decl
);
885 op_sec
= op_decl
? DECL_SECTION_NAME (op_decl
) : NULL
;
886 return ((!cfun_sec
&& !op_sec
)
887 || (cfun_sec
&& op_sec
888 && strcmp (TREE_STRING_POINTER (cfun_sec
),
889 TREE_STRING_POINTER (op_sec
)) == 0));
892 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
893 a (non-tls) variable known to be defined in this file. */
896 local_symbolic_operand (rtx op
, enum machine_mode mode
)
898 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
901 if (GET_CODE (op
) == LABEL_REF
)
904 if (GET_CODE (op
) == CONST
905 && GET_CODE (XEXP (op
, 0)) == PLUS
906 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
907 op
= XEXP (XEXP (op
, 0), 0);
909 if (GET_CODE (op
) != SYMBOL_REF
)
912 return SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
915 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
916 known to be defined in this file in the small data area. */
919 small_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
921 if (! TARGET_SMALL_DATA
)
924 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
927 if (GET_CODE (op
) == CONST
928 && GET_CODE (XEXP (op
, 0)) == PLUS
929 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
930 op
= XEXP (XEXP (op
, 0), 0);
932 if (GET_CODE (op
) != SYMBOL_REF
)
935 /* ??? There's no encode_section_info equivalent for the rtl
936 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
937 if (CONSTANT_POOL_ADDRESS_P (op
))
938 return GET_MODE_SIZE (get_pool_mode (op
)) <= g_switch_value
;
940 return (SYMBOL_REF_LOCAL_P (op
)
941 && SYMBOL_REF_SMALL_P (op
)
942 && SYMBOL_REF_TLS_MODEL (op
) == 0);
945 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
946 not known (or known not) to be defined in this file. */
949 global_symbolic_operand (rtx op
, enum machine_mode mode
)
951 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
954 if (GET_CODE (op
) == CONST
955 && GET_CODE (XEXP (op
, 0)) == PLUS
956 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
957 op
= XEXP (XEXP (op
, 0), 0);
959 if (GET_CODE (op
) != SYMBOL_REF
)
962 return !SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
965 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
968 call_operand (rtx op
, enum machine_mode mode
)
973 if (GET_CODE (op
) == REG
)
977 /* Disallow virtual registers to cope with pathological test cases
978 such as compile/930117-1.c in which the virtual reg decomposes
979 to the frame pointer. Which is a hard reg that is not $27. */
980 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
985 if (TARGET_ABI_UNICOSMK
)
987 if (GET_CODE (op
) == SYMBOL_REF
)
993 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
994 possibly with an offset. */
997 symbolic_operand (rtx op
, enum machine_mode mode
)
999 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1001 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1003 if (GET_CODE (op
) == CONST
1004 && GET_CODE (XEXP (op
,0)) == PLUS
1005 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1006 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1011 /* Return true if OP is valid for a particular TLS relocation. */
1014 tls_symbolic_operand_1 (rtx op
, enum machine_mode mode
, int size
, int unspec
)
1016 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1019 if (GET_CODE (op
) != CONST
)
1023 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1025 op
= XVECEXP (op
, 0, 0);
1027 if (GET_CODE (op
) != SYMBOL_REF
)
1030 if (SYMBOL_REF_LOCAL_P (op
))
1032 if (alpha_tls_size
> size
)
1041 switch (SYMBOL_REF_TLS_MODEL (op
))
1043 case TLS_MODEL_LOCAL_DYNAMIC
:
1044 return unspec
== UNSPEC_DTPREL
;
1045 case TLS_MODEL_INITIAL_EXEC
:
1046 return unspec
== UNSPEC_TPREL
&& size
== 64;
1047 case TLS_MODEL_LOCAL_EXEC
:
1048 return unspec
== UNSPEC_TPREL
;
1054 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1057 dtp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1059 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1062 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1065 dtp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1067 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1070 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1073 gotdtp_symbolic_operand (rtx op
, enum machine_mode mode
)
1075 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1078 /* Return true if OP is valid for 16-bit TP relative relocations. */
1081 tp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1083 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1086 /* Return true if OP is valid for 32-bit TP relative relocations. */
1089 tp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1091 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1094 /* Return true if OP is valid for 64-bit TP relative relocations. */
1097 gottp_symbolic_operand (rtx op
, enum machine_mode mode
)
1099 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1102 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1103 comparisons are valid in which insn. */
1106 alpha_comparison_operator (rtx op
, enum machine_mode mode
)
1108 enum rtx_code code
= GET_CODE (op
);
1110 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1113 return (code
== EQ
|| code
== LE
|| code
== LT
1114 || code
== LEU
|| code
== LTU
);
1117 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1118 Here we know which comparisons are valid in which insn. */
1121 alpha_zero_comparison_operator (rtx op
, enum machine_mode mode
)
1123 enum rtx_code code
= GET_CODE (op
);
1125 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1128 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1129 || code
== LEU
|| code
== LTU
);
1132 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1135 alpha_swapped_comparison_operator (rtx op
, enum machine_mode mode
)
1137 enum rtx_code code
= GET_CODE (op
);
1139 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1140 || GET_RTX_CLASS (code
) != '<')
1143 code
= swap_condition (code
);
1144 return (code
== EQ
|| code
== LE
|| code
== LT
1145 || code
== LEU
|| code
== LTU
);
1148 /* Return 1 if OP is a signed comparison operation. */
1151 signed_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1153 enum rtx_code code
= GET_CODE (op
);
1155 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1158 return (code
== EQ
|| code
== NE
1159 || code
== LE
|| code
== LT
1160 || code
== GE
|| code
== GT
);
1163 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1164 Here we know which comparisons are valid in which insn. */
1167 alpha_fp_comparison_operator (rtx op
, enum machine_mode mode
)
1169 enum rtx_code code
= GET_CODE (op
);
1171 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1174 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1177 /* Return 1 if this is a divide or modulus operator. */
1180 divmod_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1182 enum rtx_code code
= GET_CODE (op
);
1184 return (code
== DIV
|| code
== MOD
|| code
== UDIV
|| code
== UMOD
);
1187 /* Return 1 if this is a float->int conversion operator. */
1190 fix_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1192 enum rtx_code code
= GET_CODE (op
);
1194 return (code
== FIX
|| code
== UNSIGNED_FIX
);
1197 /* Return 1 if this memory address is a known aligned register plus
1198 a constant. It must be a valid address. This means that we can do
1199 this as an aligned reference plus some offset.
1201 Take into account what reload will do. */
1204 aligned_memory_operand (rtx op
, enum machine_mode mode
)
1208 if (reload_in_progress
)
1211 if (GET_CODE (tmp
) == SUBREG
)
1212 tmp
= SUBREG_REG (tmp
);
1213 if (GET_CODE (tmp
) == REG
1214 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1216 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1222 if (GET_CODE (op
) != MEM
1223 || GET_MODE (op
) != mode
)
1227 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1228 sorts of constructs. Dig for the real base register. */
1229 if (reload_in_progress
1230 && GET_CODE (op
) == PLUS
1231 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1232 base
= XEXP (XEXP (op
, 0), 0);
1235 if (! memory_address_p (mode
, op
))
1237 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1240 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1243 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1246 unaligned_memory_operand (rtx op
, enum machine_mode mode
)
1250 if (reload_in_progress
)
1253 if (GET_CODE (tmp
) == SUBREG
)
1254 tmp
= SUBREG_REG (tmp
);
1255 if (GET_CODE (tmp
) == REG
1256 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1258 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1264 if (GET_CODE (op
) != MEM
1265 || GET_MODE (op
) != mode
)
1269 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1270 sorts of constructs. Dig for the real base register. */
1271 if (reload_in_progress
1272 && GET_CODE (op
) == PLUS
1273 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1274 base
= XEXP (XEXP (op
, 0), 0);
1277 if (! memory_address_p (mode
, op
))
1279 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1282 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1285 /* Return 1 if OP is either a register or an unaligned memory location. */
1288 reg_or_unaligned_mem_operand (rtx op
, enum machine_mode mode
)
1290 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1293 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1296 any_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1298 return (GET_CODE (op
) == MEM
1299 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1300 || (reload_in_progress
&& GET_CODE (op
) == REG
1301 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1302 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1303 && GET_CODE (SUBREG_REG (op
)) == REG
1304 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1307 /* Returns 1 if OP is not an eliminable register.
1309 This exists to cure a pathological abort in the s8addq (et al) patterns,
1311 long foo () { long t; bar(); return (long) &t * 26107; }
1313 which run afoul of a hack in reload to cure a (presumably) similar
1314 problem with lea-type instructions on other targets. But there is
1315 one of us and many of them, so work around the problem by selectively
1316 preventing combine from making the optimization. */
1319 reg_not_elim_operand (rtx op
, enum machine_mode mode
)
1322 if (GET_CODE (op
) == SUBREG
)
1323 inner
= SUBREG_REG (op
);
1324 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1327 return register_operand (op
, mode
);
1330 /* Return 1 is OP is a memory location that is not a reference (using
1331 an AND) to an unaligned location. Take into account what reload
1335 normal_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1337 if (reload_in_progress
)
1340 if (GET_CODE (tmp
) == SUBREG
)
1341 tmp
= SUBREG_REG (tmp
);
1342 if (GET_CODE (tmp
) == REG
1343 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1345 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1347 /* This may not have been assigned an equivalent address if it will
1348 be eliminated. In that case, it doesn't matter what we do. */
1354 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1357 /* Accept a register, but not a subreg of any kind. This allows us to
1358 avoid pathological cases in reload wrt data movement common in
1359 int->fp conversion. */
1362 reg_no_subreg_operand (rtx op
, enum machine_mode mode
)
1364 if (GET_CODE (op
) != REG
)
1366 return register_operand (op
, mode
);
1369 /* Recognize an addition operation that includes a constant. Used to
1370 convince reload to canonize (plus (plus reg c1) c2) during register
1374 addition_operation (rtx op
, enum machine_mode mode
)
1376 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1378 if (GET_CODE (op
) == PLUS
1379 && register_operand (XEXP (op
, 0), mode
)
1380 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1381 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1386 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1387 the range defined for C in [I-P]. */
1390 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
1395 /* An unsigned 8 bit constant. */
1396 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1398 /* The constant zero. */
1401 /* A signed 16 bit constant. */
1402 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1404 /* A shifted signed 16 bit constant appropriate for LDAH. */
1405 return ((value
& 0xffff) == 0
1406 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1408 /* A constant that can be AND'ed with using a ZAP insn. */
1409 return zap_mask (value
);
1411 /* A complemented unsigned 8 bit constant. */
1412 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1414 /* A negated unsigned 8 bit constant. */
1415 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1417 /* The constant 1, 2 or 3. */
1418 return value
== 1 || value
== 2 || value
== 3;
1425 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1426 matches for C in [GH]. */
1429 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
1434 /* The floating point zero constant. */
1435 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1436 && value
== CONST0_RTX (GET_MODE (value
)));
1439 /* A valid operand of a ZAP insn. */
1440 return (GET_MODE (value
) == VOIDmode
1441 && zap_mask (CONST_DOUBLE_LOW (value
))
1442 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1449 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1453 alpha_extra_constraint (rtx value
, int c
)
1458 return normal_memory_operand (value
, VOIDmode
);
1460 return direct_call_operand (value
, Pmode
);
1462 return (GET_CODE (value
) == CONST_INT
1463 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1465 return GET_CODE (value
) == HIGH
;
1467 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1469 return (GET_CODE (value
) == CONST_VECTOR
1470 && value
== CONST0_RTX (GET_MODE (value
)));
1476 /* Return 1 if this function can directly return via $26. */
1479 direct_return (void)
1481 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1483 && alpha_sa_size () == 0
1484 && get_frame_size () == 0
1485 && current_function_outgoing_args_size
== 0
1486 && current_function_pretend_args_size
== 0);
1489 /* Return the ADDR_VEC associated with a tablejump insn. */
1492 alpha_tablejump_addr_vec (rtx insn
)
1496 tmp
= JUMP_LABEL (insn
);
1499 tmp
= NEXT_INSN (tmp
);
1502 if (GET_CODE (tmp
) == JUMP_INSN
1503 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1504 return PATTERN (tmp
);
1508 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1511 alpha_tablejump_best_label (rtx insn
)
1513 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1514 rtx best_label
= NULL_RTX
;
1516 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1517 there for edge frequency counts from profile data. */
1521 int n_labels
= XVECLEN (jump_table
, 1);
1522 int best_count
= -1;
1525 for (i
= 0; i
< n_labels
; i
++)
1529 for (j
= i
+ 1; j
< n_labels
; j
++)
1530 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1531 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1534 if (count
> best_count
)
1535 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1539 return best_label
? best_label
: const0_rtx
;
1542 /* Return the TLS model to use for SYMBOL. */
1544 static enum tls_model
1545 tls_symbolic_operand_type (rtx symbol
)
1547 enum tls_model model
;
1549 if (GET_CODE (symbol
) != SYMBOL_REF
)
1551 model
= SYMBOL_REF_TLS_MODEL (symbol
);
1553 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1554 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
1555 model
= TLS_MODEL_INITIAL_EXEC
;
1560 /* Return true if the function DECL will share the same GP as any
1561 function in the current unit of translation. */
1564 decl_has_samegp (tree decl
)
1566 /* Functions that are not local can be overridden, and thus may
1567 not share the same gp. */
1568 if (!(*targetm
.binds_local_p
) (decl
))
1571 /* If -msmall-data is in effect, assume that there is only one GP
1572 for the module, and so any local symbol has this property. We
1573 need explicit relocations to be able to enforce this for symbols
1574 not defined in this unit of translation, however. */
1575 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1578 /* Functions that are not external are defined in this UoT. */
1579 /* ??? Irritatingly, static functions not yet emitted are still
1580 marked "external". Apply this to non-static functions only. */
1581 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1584 /* Return true if EXP should be placed in the small data section. */
1587 alpha_in_small_data_p (tree exp
)
1589 /* We want to merge strings, so we never consider them small data. */
1590 if (TREE_CODE (exp
) == STRING_CST
)
1593 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1595 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1596 if (strcmp (section
, ".sdata") == 0
1597 || strcmp (section
, ".sbss") == 0)
1602 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1604 /* If this is an incomplete type with size 0, then we can't put it
1605 in sdata because it might be too big when completed. */
1606 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
1613 #if TARGET_ABI_OPEN_VMS
1615 alpha_linkage_symbol_p (const char *symname
)
1617 int symlen
= strlen (symname
);
1620 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1625 #define LINKAGE_SYMBOL_REF_P(X) \
1626 ((GET_CODE (X) == SYMBOL_REF \
1627 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1628 || (GET_CODE (X) == CONST \
1629 && GET_CODE (XEXP (X, 0)) == PLUS \
1630 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1631 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1634 /* legitimate_address_p recognizes an RTL expression that is a valid
1635 memory address for an instruction. The MODE argument is the
1636 machine mode for the MEM expression that wants to use this address.
1638 For Alpha, we have either a constant address or the sum of a
1639 register and a constant address, or just a register. For DImode,
1640 any of those forms can be surrounded with an AND that clear the
1641 low-order three bits; this is an "unaligned" access. */
1644 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1646 /* If this is an ldq_u type address, discard the outer AND. */
1648 && GET_CODE (x
) == AND
1649 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1650 && INTVAL (XEXP (x
, 1)) == -8)
1653 /* Discard non-paradoxical subregs. */
1654 if (GET_CODE (x
) == SUBREG
1655 && (GET_MODE_SIZE (GET_MODE (x
))
1656 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1659 /* Unadorned general registers are valid. */
1662 ? STRICT_REG_OK_FOR_BASE_P (x
)
1663 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1666 /* Constant addresses (i.e. +/- 32k) are valid. */
1667 if (CONSTANT_ADDRESS_P (x
))
1670 #if TARGET_ABI_OPEN_VMS
1671 if (LINKAGE_SYMBOL_REF_P (x
))
1675 /* Register plus a small constant offset is valid. */
1676 if (GET_CODE (x
) == PLUS
)
1678 rtx ofs
= XEXP (x
, 1);
1681 /* Discard non-paradoxical subregs. */
1682 if (GET_CODE (x
) == SUBREG
1683 && (GET_MODE_SIZE (GET_MODE (x
))
1684 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1690 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1691 && GET_CODE (ofs
) == CONST_INT
)
1694 ? STRICT_REG_OK_FOR_BASE_P (x
)
1695 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1696 && CONSTANT_ADDRESS_P (ofs
))
1699 else if (GET_CODE (x
) == ADDRESSOF
1700 && GET_CODE (ofs
) == CONST_INT
)
1704 /* If we're managing explicit relocations, LO_SUM is valid, as
1705 are small data symbols. */
1706 else if (TARGET_EXPLICIT_RELOCS
)
1708 if (small_symbolic_operand (x
, Pmode
))
1711 if (GET_CODE (x
) == LO_SUM
)
1713 rtx ofs
= XEXP (x
, 1);
1716 /* Discard non-paradoxical subregs. */
1717 if (GET_CODE (x
) == SUBREG
1718 && (GET_MODE_SIZE (GET_MODE (x
))
1719 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1722 /* Must have a valid base register. */
1725 ? STRICT_REG_OK_FOR_BASE_P (x
)
1726 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1729 /* The symbol must be local. */
1730 if (local_symbolic_operand (ofs
, Pmode
)
1731 || dtp32_symbolic_operand (ofs
, Pmode
)
1732 || tp32_symbolic_operand (ofs
, Pmode
))
1740 /* Build the SYMBOL_REF for __tls_get_addr. */
1742 static GTY(()) rtx tls_get_addr_libfunc
;
1745 get_tls_get_addr (void)
1747 if (!tls_get_addr_libfunc
)
1748 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
1749 return tls_get_addr_libfunc
;
1752 /* Try machine-dependent ways of modifying an illegitimate address
1753 to be legitimate. If we find one, return the new, valid address. */
1756 alpha_legitimize_address (rtx x
, rtx scratch
,
1757 enum machine_mode mode ATTRIBUTE_UNUSED
)
1759 HOST_WIDE_INT addend
;
1761 /* If the address is (plus reg const_int) and the CONST_INT is not a
1762 valid offset, compute the high part of the constant and add it to
1763 the register. Then our address is (plus temp low-part-const). */
1764 if (GET_CODE (x
) == PLUS
1765 && GET_CODE (XEXP (x
, 0)) == REG
1766 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1767 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1769 addend
= INTVAL (XEXP (x
, 1));
1774 /* If the address is (const (plus FOO const_int)), find the low-order
1775 part of the CONST_INT. Then load FOO plus any high-order part of the
1776 CONST_INT into a register. Our address is (plus reg low-part-const).
1777 This is done to reduce the number of GOT entries. */
1779 && GET_CODE (x
) == CONST
1780 && GET_CODE (XEXP (x
, 0)) == PLUS
1781 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1783 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1784 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1788 /* If we have a (plus reg const), emit the load as in (2), then add
1789 the two registers, and finally generate (plus reg low-part-const) as
1792 && GET_CODE (x
) == PLUS
1793 && GET_CODE (XEXP (x
, 0)) == REG
1794 && GET_CODE (XEXP (x
, 1)) == CONST
1795 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1796 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1798 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1799 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1800 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1801 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1805 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1806 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1808 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1810 switch (tls_symbolic_operand_type (x
))
1812 case TLS_MODEL_GLOBAL_DYNAMIC
:
1815 r0
= gen_rtx_REG (Pmode
, 0);
1816 r16
= gen_rtx_REG (Pmode
, 16);
1817 tga
= get_tls_get_addr ();
1818 dest
= gen_reg_rtx (Pmode
);
1819 seq
= GEN_INT (alpha_next_sequence_number
++);
1821 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1822 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1823 insn
= emit_call_insn (insn
);
1824 CONST_OR_PURE_CALL_P (insn
) = 1;
1825 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1827 insn
= get_insns ();
1830 emit_libcall_block (insn
, dest
, r0
, x
);
1833 case TLS_MODEL_LOCAL_DYNAMIC
:
1836 r0
= gen_rtx_REG (Pmode
, 0);
1837 r16
= gen_rtx_REG (Pmode
, 16);
1838 tga
= get_tls_get_addr ();
1839 scratch
= gen_reg_rtx (Pmode
);
1840 seq
= GEN_INT (alpha_next_sequence_number
++);
1842 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1843 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1844 insn
= emit_call_insn (insn
);
1845 CONST_OR_PURE_CALL_P (insn
) = 1;
1846 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1848 insn
= get_insns ();
1851 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1852 UNSPEC_TLSLDM_CALL
);
1853 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1855 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1856 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1858 if (alpha_tls_size
== 64)
1860 dest
= gen_reg_rtx (Pmode
);
1861 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1862 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1865 if (alpha_tls_size
== 32)
1867 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1868 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1869 scratch
= gen_reg_rtx (Pmode
);
1870 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1872 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1874 case TLS_MODEL_INITIAL_EXEC
:
1875 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1876 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1877 tp
= gen_reg_rtx (Pmode
);
1878 scratch
= gen_reg_rtx (Pmode
);
1879 dest
= gen_reg_rtx (Pmode
);
1881 emit_insn (gen_load_tp (tp
));
1882 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1883 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1886 case TLS_MODEL_LOCAL_EXEC
:
1887 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1888 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1889 tp
= gen_reg_rtx (Pmode
);
1891 emit_insn (gen_load_tp (tp
));
1892 if (alpha_tls_size
== 32)
1894 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1895 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1896 tp
= gen_reg_rtx (Pmode
);
1897 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1899 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1902 if (local_symbolic_operand (x
, Pmode
))
1904 if (small_symbolic_operand (x
, Pmode
))
1908 if (!no_new_pseudos
)
1909 scratch
= gen_reg_rtx (Pmode
);
1910 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1911 gen_rtx_HIGH (Pmode
, x
)));
1912 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1921 HOST_WIDE_INT low
, high
;
1923 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1925 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1929 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1930 (no_new_pseudos
? scratch
: NULL_RTX
),
1931 1, OPTAB_LIB_WIDEN
);
1933 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1934 (no_new_pseudos
? scratch
: NULL_RTX
),
1935 1, OPTAB_LIB_WIDEN
);
1937 return plus_constant (x
, low
);
1941 /* We do not allow indirect calls to be optimized into sibling calls, nor
1942 can we allow a call to a function with a different GP to be optimized
1946 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1948 /* Can't do indirect tail calls, since we don't know if the target
1949 uses the same GP. */
1953 /* Otherwise, we can make a tail call if the target function shares
1955 return decl_has_samegp (decl
);
1958 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1959 small symbolic operand until after reload. At which point we need
1960 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1961 so that sched2 has the proper dependency information. */
1964 some_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1968 /* Don't re-split. */
1969 if (GET_CODE (x
) == LO_SUM
)
1972 return small_symbolic_operand (x
, Pmode
) != 0;
1976 some_small_symbolic_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1978 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
1982 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1986 /* Don't re-split. */
1987 if (GET_CODE (x
) == LO_SUM
)
1990 if (small_symbolic_operand (x
, Pmode
))
1992 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2001 split_small_symbolic_operand (rtx x
)
2004 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2008 /* Indicate that INSN cannot be duplicated. This is true for any insn
2009 that we've marked with gpdisp relocs, since those have to stay in
2010 1-1 correspondence with one another.
2012 Technically we could copy them if we could set up a mapping from one
2013 sequence number to another, across the set of insns to be duplicated.
2014 This seems overly complicated and error-prone since interblock motion
2015 from sched-ebb could move one of the pair of insns to a different block. */
2018 alpha_cannot_copy_insn_p (rtx insn
)
2022 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2025 if (GET_CODE (insn
) != INSN
)
2027 if (asm_noperands (insn
) >= 0)
2030 pat
= PATTERN (insn
);
2031 if (GET_CODE (pat
) != SET
)
2033 pat
= SET_SRC (pat
);
2034 if (GET_CODE (pat
) == UNSPEC_VOLATILE
)
2036 if (XINT (pat
, 1) == UNSPECV_LDGP1
2037 || XINT (pat
, 1) == UNSPECV_PLDGP2
)
2040 else if (GET_CODE (pat
) == UNSPEC
)
2042 if (XINT (pat
, 1) == UNSPEC_LDGP2
)
2050 /* Try a machine-dependent way of reloading an illegitimate address
2051 operand. If we find one, push the reload and return the new rtx. */
2054 alpha_legitimize_reload_address (rtx x
,
2055 enum machine_mode mode ATTRIBUTE_UNUSED
,
2056 int opnum
, int type
,
2057 int ind_levels ATTRIBUTE_UNUSED
)
2059 /* We must recognize output that we have already generated ourselves. */
2060 if (GET_CODE (x
) == PLUS
2061 && GET_CODE (XEXP (x
, 0)) == PLUS
2062 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2063 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2064 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2066 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2067 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2072 /* We wish to handle large displacements off a base register by
2073 splitting the addend across an ldah and the mem insn. This
2074 cuts number of extra insns needed from 3 to 1. */
2075 if (GET_CODE (x
) == PLUS
2076 && GET_CODE (XEXP (x
, 0)) == REG
2077 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2078 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2079 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2081 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2082 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2084 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2086 /* Check for 32-bit overflow. */
2087 if (high
+ low
!= val
)
2090 /* Reload the high part into a base reg; leave the low part
2091 in the mem directly. */
2092 x
= gen_rtx_PLUS (GET_MODE (x
),
2093 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2097 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2098 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2106 /* Compute a (partial) cost for rtx X. Return true if the complete
2107 cost has been computed, and false if subexpressions should be
2108 scanned. In either case, *TOTAL contains the cost result. */
2111 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2113 enum machine_mode mode
= GET_MODE (x
);
2114 bool float_mode_p
= FLOAT_MODE_P (mode
);
2118 /* If this is an 8-bit constant, return zero since it can be used
2119 nearly anywhere with no cost. If it is a valid operand for an
2120 ADD or AND, likewise return 0 if we know it will be used in that
2121 context. Otherwise, return 2 since it might be used there later.
2122 All other constants take at least two insns. */
2124 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2132 if (x
== CONST0_RTX (mode
))
2134 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2135 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2137 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2140 *total
= COSTS_N_INSNS (2);
2146 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2147 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2148 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2149 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2150 else if (tls_symbolic_operand_type (x
))
2151 /* Estimate of cost for call_pal rduniq. */
2152 *total
= COSTS_N_INSNS (15);
2154 /* Otherwise we do a load from the GOT. */
2155 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2161 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2162 else if (GET_CODE (XEXP (x
, 0)) == MULT
2163 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2165 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2166 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2173 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2174 else if (mode
== DImode
)
2175 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2177 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2181 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2182 && INTVAL (XEXP (x
, 1)) <= 3)
2184 *total
= COSTS_N_INSNS (1);
2191 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2196 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2198 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2206 *total
= COSTS_N_INSNS (70); /* ??? */
2207 else if (mode
== SFmode
)
2208 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2210 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2214 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2220 *total
= COSTS_N_INSNS (1);
2228 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2234 case UNSIGNED_FLOAT
:
2238 case FLOAT_TRUNCATE
:
2239 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2247 /* REF is an alignable memory location. Place an aligned SImode
2248 reference into *PALIGNED_MEM and the number of bits to shift into
2249 *PBITNUM. SCRATCH is a free register for use in reloading out
2250 of range stack slots. */
2253 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
2256 HOST_WIDE_INT offset
= 0;
2258 if (GET_CODE (ref
) != MEM
)
2261 if (reload_in_progress
2262 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2264 base
= find_replacement (&XEXP (ref
, 0));
2266 if (! memory_address_p (GET_MODE (ref
), base
))
2271 base
= XEXP (ref
, 0);
2274 if (GET_CODE (base
) == PLUS
)
2275 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2278 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2280 if (WORDS_BIG_ENDIAN
)
2281 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2282 + (offset
& 3) * 8));
2284 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2287 /* Similar, but just get the address. Handle the two reload cases.
2288 Add EXTRA_OFFSET to the address we return. */
2291 get_unaligned_address (rtx ref
, int extra_offset
)
2294 HOST_WIDE_INT offset
= 0;
2296 if (GET_CODE (ref
) != MEM
)
2299 if (reload_in_progress
2300 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2302 base
= find_replacement (&XEXP (ref
, 0));
2304 if (! memory_address_p (GET_MODE (ref
), base
))
2309 base
= XEXP (ref
, 0);
2312 if (GET_CODE (base
) == PLUS
)
2313 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2315 return plus_constant (base
, offset
+ extra_offset
);
2318 /* On the Alpha, all (non-symbolic) constants except zero go into
2319 a floating-point register via memory. Note that we cannot
2320 return anything that is not a subset of CLASS, and that some
2321 symbolic constants cannot be dropped to memory. */
2324 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
2326 /* Zero is present in any register class. */
2327 if (x
== CONST0_RTX (GET_MODE (x
)))
2330 /* These sorts of constants we can easily drop to memory. */
2331 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2333 if (class == FLOAT_REGS
)
2335 if (class == ALL_REGS
)
2336 return GENERAL_REGS
;
2340 /* All other kinds of constants should not (and in the case of HIGH
2341 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2342 secondary reload. */
2344 return (class == ALL_REGS
? GENERAL_REGS
: class);
2349 /* Loading and storing HImode or QImode values to and from memory
2350 usually requires a scratch register. The exceptions are loading
2351 QImode and HImode from an aligned address to a general register
2352 unless byte instructions are permitted.
2354 We also cannot load an unaligned address or a paradoxical SUBREG
2355 into an FP register.
2357 We also cannot do integral arithmetic into FP regs, as might result
2358 from register elimination into a DImode fp register. */
2361 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
2364 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2366 if (GET_CODE (x
) == MEM
2367 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2368 || (GET_CODE (x
) == SUBREG
2369 && (GET_CODE (SUBREG_REG (x
)) == MEM
2370 || (GET_CODE (SUBREG_REG (x
)) == REG
2371 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2373 if (!in
|| !aligned_memory_operand(x
, mode
))
2374 return GENERAL_REGS
;
2378 if (class == FLOAT_REGS
)
2380 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2381 return GENERAL_REGS
;
2383 if (GET_CODE (x
) == SUBREG
2384 && (GET_MODE_SIZE (GET_MODE (x
))
2385 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2386 return GENERAL_REGS
;
2388 if (in
&& INTEGRAL_MODE_P (mode
)
2389 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2390 return GENERAL_REGS
;
2396 /* Subfunction of the following function. Update the flags of any MEM
2397 found in part of X. */
2400 alpha_set_memflags_1 (rtx x
, int in_struct_p
, int volatile_p
, int unchanging_p
)
2404 switch (GET_CODE (x
))
2410 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2411 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2416 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2421 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2423 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2428 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2429 MEM_VOLATILE_P (x
) = volatile_p
;
2430 RTX_UNCHANGING_P (x
) = unchanging_p
;
2431 /* Sadly, we cannot use alias sets because the extra aliasing
2432 produced by the AND interferes. Given that two-byte quantities
2433 are the only thing we would be able to differentiate anyway,
2434 there does not seem to be any point in convoluting the early
2435 out of the alias check. */
2443 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2444 generated to perform a memory operation, look for any MEMs in either
2445 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2446 volatile flags from REF into each of the MEMs found. If REF is not
2447 a MEM, don't do anything. */
2450 alpha_set_memflags (rtx insn
, rtx ref
)
2452 int in_struct_p
, volatile_p
, unchanging_p
;
2454 if (GET_CODE (ref
) != MEM
)
2457 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2458 volatile_p
= MEM_VOLATILE_P (ref
);
2459 unchanging_p
= RTX_UNCHANGING_P (ref
);
2461 /* This is only called from alpha.md, after having had something
2462 generated from one of the insn patterns. So if everything is
2463 zero, the pattern is already up-to-date. */
2464 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2467 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2470 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2473 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
2474 HOST_WIDE_INT c
, int n
)
2478 /* Use a pseudo if highly optimizing and still generating RTL. */
2480 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2483 /* If this is a sign-extended 32-bit constant, we can do this in at most
2484 three insns, so do it if we have enough insns left. We always have
2485 a sign-extended 32-bit constant when compiling on a narrow machine. */
2487 if (HOST_BITS_PER_WIDE_INT
!= 64
2488 || c
>> 31 == -1 || c
>> 31 == 0)
2490 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2491 HOST_WIDE_INT tmp1
= c
- low
;
2492 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2493 HOST_WIDE_INT extra
= 0;
2495 /* If HIGH will be interpreted as negative but the constant is
2496 positive, we must adjust it to do two ldha insns. */
2498 if ((high
& 0x8000) != 0 && c
>= 0)
2502 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2505 if (c
== low
|| (low
== 0 && extra
== 0))
2507 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2508 but that meant that we can't handle INT_MIN on 32-bit machines
2509 (like NT/Alpha), because we recurse indefinitely through
2510 emit_move_insn to gen_movdi. So instead, since we know exactly
2511 what we want, create it explicitly. */
2514 target
= gen_reg_rtx (mode
);
2515 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2518 else if (n
>= 2 + (extra
!= 0))
2520 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2522 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2523 This means that if we go through expand_binop, we'll try to
2524 generate extensions, etc, which will require new pseudos, which
2525 will fail during some split phases. The SImode add patterns
2526 still exist, but are not named. So build the insns by hand. */
2531 subtarget
= gen_reg_rtx (mode
);
2532 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2533 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2539 target
= gen_reg_rtx (mode
);
2540 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2541 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2547 /* If we couldn't do it that way, try some other methods. But if we have
2548 no instructions left, don't bother. Likewise, if this is SImode and
2549 we can't make pseudos, we can't do anything since the expand_binop
2550 and expand_unop calls will widen and try to make pseudos. */
2552 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2555 /* Next, see if we can load a related constant and then shift and possibly
2556 negate it to get the constant we want. Try this once each increasing
2557 numbers of insns. */
2559 for (i
= 1; i
< n
; i
++)
2561 /* First, see if minus some low bits, we've an easy load of
2564 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2566 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2567 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2568 target
, 0, OPTAB_WIDEN
);
2570 /* Next try complementing. */
2571 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2572 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2574 /* Next try to form a constant and do a left shift. We can do this
2575 if some low-order bits are zero; the exact_log2 call below tells
2576 us that information. The bits we are shifting out could be any
2577 value, but here we'll just try the 0- and sign-extended forms of
2578 the constant. To try to increase the chance of having the same
2579 constant in more than one insn, start at the highest number of
2580 bits to shift, but try all possibilities in case a ZAPNOT will
2583 if ((bits
= exact_log2 (c
& - c
)) > 0)
2584 for (; bits
> 0; bits
--)
2585 if ((temp
= (alpha_emit_set_const
2586 (subtarget
, mode
, c
>> bits
, i
))) != 0
2587 || ((temp
= (alpha_emit_set_const
2589 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2591 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2592 target
, 0, OPTAB_WIDEN
);
2594 /* Now try high-order zero bits. Here we try the shifted-in bits as
2595 all zero and all ones. Be careful to avoid shifting outside the
2596 mode and to avoid shifting outside the host wide int size. */
2597 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2598 confuse the recursive call and set all of the high 32 bits. */
2600 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2601 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2602 for (; bits
> 0; bits
--)
2603 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2605 || ((temp
= (alpha_emit_set_const
2607 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2610 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2611 target
, 1, OPTAB_WIDEN
);
2613 /* Now try high-order 1 bits. We get that with a sign-extension.
2614 But one bit isn't enough here. Be careful to avoid shifting outside
2615 the mode and to avoid shifting outside the host wide int size. */
2617 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2618 - floor_log2 (~ c
) - 2)) > 0)
2619 for (; bits
> 0; bits
--)
2620 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2622 || ((temp
= (alpha_emit_set_const
2624 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2627 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2628 target
, 0, OPTAB_WIDEN
);
2631 #if HOST_BITS_PER_WIDE_INT == 64
2632 /* Finally, see if can load a value into the target that is the same as the
2633 constant except that all bytes that are 0 are changed to be 0xff. If we
2634 can, then we can do a ZAPNOT to obtain the desired constant. */
2637 for (i
= 0; i
< 64; i
+= 8)
2638 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2639 new |= (HOST_WIDE_INT
) 0xff << i
;
2641 /* We are only called for SImode and DImode. If this is SImode, ensure that
2642 we are sign extended to a full word. */
2645 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2647 if (new != c
&& new != -1
2648 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2649 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2650 target
, 0, OPTAB_WIDEN
);
2656 /* Try to output insns to set TARGET equal to the constant C if it can be
2657 done in less than N insns. Do all computations in MODE. Returns the place
2658 where the output has been placed if it can be done and the insns have been
2659 emitted. If it would take more than N insns, zero is returned and no
2660 insns and emitted. */
2663 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
2664 HOST_WIDE_INT c
, int n
)
2667 rtx orig_target
= target
;
2670 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2671 can't load this constant in one insn, do this in DImode. */
2672 if (no_new_pseudos
&& mode
== SImode
2673 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2674 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2676 target
= gen_lowpart (DImode
, target
);
2680 /* Try 1 insn, then 2, then up to N. */
2681 for (i
= 1; i
<= n
; i
++)
2683 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2686 rtx insn
= get_last_insn ();
2687 rtx set
= single_set (insn
);
2688 if (! CONSTANT_P (SET_SRC (set
)))
2689 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2694 /* Allow for the case where we changed the mode of TARGET. */
2695 if (result
== target
)
2696 result
= orig_target
;
2701 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2702 fall back to a straight forward decomposition. We do this to avoid
2703 exponential run times encountered when looking for longer sequences
2704 with alpha_emit_set_const. */
2707 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2709 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2711 /* Decompose the entire word */
2712 #if HOST_BITS_PER_WIDE_INT >= 64
2713 if (c2
!= -(c1
< 0))
2715 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2717 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2718 c1
= (c1
- d2
) >> 32;
2719 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2721 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2725 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2727 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2731 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2733 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2738 /* Construct the high word */
2741 emit_move_insn (target
, GEN_INT (d4
));
2743 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2746 emit_move_insn (target
, GEN_INT (d3
));
2748 /* Shift it into place */
2749 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2751 /* Add in the low bits. */
2753 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2755 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2760 /* Expand a move instruction; return true if all work is done.
2761 We don't handle non-bwx subword loads here. */
2764 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2766 /* If the output is not a register, the input must be. */
2767 if (GET_CODE (operands
[0]) == MEM
2768 && ! reg_or_0_operand (operands
[1], mode
))
2769 operands
[1] = force_reg (mode
, operands
[1]);
2771 /* Allow legitimize_address to perform some simplifications. */
2772 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2776 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2777 compiled at the end of compilation. In the meantime, someone can
2778 re-encode-section-info on some symbol changing it e.g. from global
2779 to local-not-small. If this happens, we'd have emitted a plain
2780 load rather than a high+losum load and not recognize the insn.
2782 So if rtl inlining is in effect, we delay the global/not-global
2783 decision until rest_of_compilation by wrapping it in an
2785 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2786 && rtx_equal_function_value_matters
2787 && global_symbolic_operand (operands
[1], mode
))
2789 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2793 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2796 if (tmp
== operands
[0])
2803 /* Early out for non-constants and valid constants. */
2804 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2807 /* Split large integers. */
2808 if (GET_CODE (operands
[1]) == CONST_INT
2809 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2811 HOST_WIDE_INT i0
, i1
;
2812 rtx temp
= NULL_RTX
;
2814 if (GET_CODE (operands
[1]) == CONST_INT
)
2816 i0
= INTVAL (operands
[1]);
2819 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2821 i0
= CONST_DOUBLE_LOW (operands
[1]);
2826 i0
= CONST_DOUBLE_LOW (operands
[1]);
2827 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2830 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2831 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2833 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2834 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2838 if (rtx_equal_p (operands
[0], temp
))
2845 /* Otherwise we've nothing left but to drop the thing to memory. */
2846 operands
[1] = force_const_mem (mode
, operands
[1]);
2847 if (reload_in_progress
)
2849 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2850 operands
[1] = copy_rtx (operands
[1]);
2851 XEXP (operands
[1], 0) = operands
[0];
2854 operands
[1] = validize_mem (operands
[1]);
2858 /* Expand a non-bwx QImode or HImode move instruction;
2859 return true if all work is done. */
2862 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2864 /* If the output is not a register, the input must be. */
2865 if (GET_CODE (operands
[0]) == MEM
)
2866 operands
[1] = force_reg (mode
, operands
[1]);
2868 /* Handle four memory cases, unaligned and aligned for either the input
2869 or the output. The only case where we can be called during reload is
2870 for aligned loads; all other cases require temporaries. */
2872 if (GET_CODE (operands
[1]) == MEM
2873 || (GET_CODE (operands
[1]) == SUBREG
2874 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2875 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2876 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2877 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2878 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2879 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2881 if (aligned_memory_operand (operands
[1], mode
))
2883 if (reload_in_progress
)
2885 emit_insn ((mode
== QImode
2886 ? gen_reload_inqi_help
2887 : gen_reload_inhi_help
)
2888 (operands
[0], operands
[1],
2889 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2893 rtx aligned_mem
, bitnum
;
2894 rtx scratch
= gen_reg_rtx (SImode
);
2896 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2898 emit_insn ((mode
== QImode
2899 ? gen_aligned_loadqi
2900 : gen_aligned_loadhi
)
2901 (operands
[0], aligned_mem
, bitnum
, scratch
));
2906 /* Don't pass these as parameters since that makes the generated
2907 code depend on parameter evaluation order which will cause
2908 bootstrap failures. */
2910 rtx temp1
= gen_reg_rtx (DImode
);
2911 rtx temp2
= gen_reg_rtx (DImode
);
2912 rtx seq
= ((mode
== QImode
2913 ? gen_unaligned_loadqi
2914 : gen_unaligned_loadhi
)
2915 (operands
[0], get_unaligned_address (operands
[1], 0),
2918 alpha_set_memflags (seq
, operands
[1]);
2924 if (GET_CODE (operands
[0]) == MEM
2925 || (GET_CODE (operands
[0]) == SUBREG
2926 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2927 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2928 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2929 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2930 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2931 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2933 if (aligned_memory_operand (operands
[0], mode
))
2935 rtx aligned_mem
, bitnum
;
2936 rtx temp1
= gen_reg_rtx (SImode
);
2937 rtx temp2
= gen_reg_rtx (SImode
);
2939 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2941 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2946 rtx temp1
= gen_reg_rtx (DImode
);
2947 rtx temp2
= gen_reg_rtx (DImode
);
2948 rtx temp3
= gen_reg_rtx (DImode
);
2949 rtx seq
= ((mode
== QImode
2950 ? gen_unaligned_storeqi
2951 : gen_unaligned_storehi
)
2952 (get_unaligned_address (operands
[0], 0),
2953 operands
[1], temp1
, temp2
, temp3
));
2955 alpha_set_memflags (seq
, operands
[0]);
2964 /* Generate an unsigned DImode to FP conversion. This is the same code
2965 optabs would emit if we didn't have TFmode patterns.
2967 For SFmode, this is the only construction I've found that can pass
2968 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2969 intermediates will work, because you'll get intermediate rounding
2970 that ruins the end result. Some of this could be fixed by turning
2971 on round-to-positive-infinity, but that requires diddling the fpsr,
2972 which kills performance. I tried turning this around and converting
2973 to a negative number, so that I could turn on /m, but either I did
2974 it wrong or there's something else cause I wound up with the exact
2975 same single-bit error. There is a branch-less form of this same code:
2986 fcmoveq $f10,$f11,$f0
2988 I'm not using it because it's the same number of instructions as
2989 this branch-full form, and it has more serialized long latency
2990 instructions on the critical path.
2992 For DFmode, we can avoid rounding errors by breaking up the word
2993 into two pieces, converting them separately, and adding them back:
2995 LC0: .long 0,0x5f800000
3000 cpyse $f11,$f31,$f10
3001 cpyse $f31,$f11,$f11
3009 This doesn't seem to be a clear-cut win over the optabs form.
3010 It probably all depends on the distribution of numbers being
3011 converted -- in the optabs form, all but high-bit-set has a
3012 much lower minimum execution time. */
3015 alpha_emit_floatuns (rtx operands
[2])
3017 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3018 enum machine_mode mode
;
3021 in
= force_reg (DImode
, operands
[1]);
3022 mode
= GET_MODE (out
);
3023 neglab
= gen_label_rtx ();
3024 donelab
= gen_label_rtx ();
3025 i0
= gen_reg_rtx (DImode
);
3026 i1
= gen_reg_rtx (DImode
);
3027 f0
= gen_reg_rtx (mode
);
3029 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3031 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3032 emit_jump_insn (gen_jump (donelab
));
3035 emit_label (neglab
);
3037 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3038 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3039 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3040 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3041 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3043 emit_label (donelab
);
3046 /* Generate the comparison for a conditional branch. */
3049 alpha_emit_conditional_branch (enum rtx_code code
)
3051 enum rtx_code cmp_code
, branch_code
;
3052 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3053 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3056 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3058 if (! TARGET_HAS_XFLOATING_LIBS
)
3061 /* X_floating library comparison functions return
3065 Convert the compare against the raw return value. */
3087 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3089 alpha_compare
.fp_p
= 0;
3092 /* The general case: fold the comparison code to the types of compares
3093 that we have, choosing the branch as necessary. */
3096 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3098 /* We have these compares: */
3099 cmp_code
= code
, branch_code
= NE
;
3104 /* These must be reversed. */
3105 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3108 case GE
: case GT
: case GEU
: case GTU
:
3109 /* For FP, we swap them, for INT, we reverse them. */
3110 if (alpha_compare
.fp_p
)
3112 cmp_code
= swap_condition (code
);
3114 tem
= op0
, op0
= op1
, op1
= tem
;
3118 cmp_code
= reverse_condition (code
);
3127 if (alpha_compare
.fp_p
)
3130 if (flag_unsafe_math_optimizations
)
3132 /* When we are not as concerned about non-finite values, and we
3133 are comparing against zero, we can branch directly. */
3134 if (op1
== CONST0_RTX (DFmode
))
3135 cmp_code
= NIL
, branch_code
= code
;
3136 else if (op0
== CONST0_RTX (DFmode
))
3138 /* Undo the swap we probably did just above. */
3139 tem
= op0
, op0
= op1
, op1
= tem
;
3140 branch_code
= swap_condition (cmp_code
);
3146 /* ??? We mark the branch mode to be CCmode to prevent the
3147 compare and branch from being combined, since the compare
3148 insn follows IEEE rules that the branch does not. */
3149 branch_mode
= CCmode
;
3156 /* The following optimizations are only for signed compares. */
3157 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3159 /* Whee. Compare and branch against 0 directly. */
3160 if (op1
== const0_rtx
)
3161 cmp_code
= NIL
, branch_code
= code
;
3163 /* If the constants doesn't fit into an immediate, but can
3164 be generated by lda/ldah, we adjust the argument and
3165 compare against zero, so we can use beq/bne directly. */
3166 else if (GET_CODE (op1
) == CONST_INT
&& (code
== EQ
|| code
== NE
))
3168 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3170 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3171 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3172 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3174 cmp_code
= PLUS
, branch_code
= code
;
3180 if (!reg_or_0_operand (op0
, DImode
))
3181 op0
= force_reg (DImode
, op0
);
3182 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3183 op1
= force_reg (DImode
, op1
);
3186 /* Emit an initial compare instruction, if necessary. */
3188 if (cmp_code
!= NIL
)
3190 tem
= gen_reg_rtx (cmp_mode
);
3191 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3194 /* Zero the operands. */
3195 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3197 /* Return the branch comparison. */
3198 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3201 /* Certain simplifications can be done to make invalid setcc operations
3202 valid. Return the final comparison, or NULL if we can't work. */
3205 alpha_emit_setcc (enum rtx_code code
)
3207 enum rtx_code cmp_code
;
3208 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3209 int fp_p
= alpha_compare
.fp_p
;
3212 /* Zero the operands. */
3213 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3215 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3217 if (! TARGET_HAS_XFLOATING_LIBS
)
3220 /* X_floating library comparison functions return
3224 Convert the compare against the raw return value. */
3226 if (code
== UNORDERED
|| code
== ORDERED
)
3231 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3235 if (code
== UNORDERED
)
3237 else if (code
== ORDERED
)
3243 if (fp_p
&& !TARGET_FIX
)
3246 /* The general case: fold the comparison code to the types of compares
3247 that we have, choosing the branch as necessary. */
3252 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3254 /* We have these compares. */
3256 cmp_code
= code
, code
= NE
;
3260 if (!fp_p
&& op1
== const0_rtx
)
3265 cmp_code
= reverse_condition (code
);
3269 case GE
: case GT
: case GEU
: case GTU
:
3270 /* These normally need swapping, but for integer zero we have
3271 special patterns that recognize swapped operands. */
3272 if (!fp_p
&& op1
== const0_rtx
)
3274 code
= swap_condition (code
);
3276 cmp_code
= code
, code
= NE
;
3277 tmp
= op0
, op0
= op1
, op1
= tmp
;
3286 if (!register_operand (op0
, DImode
))
3287 op0
= force_reg (DImode
, op0
);
3288 if (!reg_or_8bit_operand (op1
, DImode
))
3289 op1
= force_reg (DImode
, op1
);
3292 /* Emit an initial compare instruction, if necessary. */
3293 if (cmp_code
!= NIL
)
3295 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3297 tmp
= gen_reg_rtx (mode
);
3298 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3299 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3301 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3305 /* Return the setcc comparison. */
3306 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3310 /* Rewrite a comparison against zero CMP of the form
3311 (CODE (cc0) (const_int 0)) so it can be written validly in
3312 a conditional move (if_then_else CMP ...).
3313 If both of the operands that set cc0 are nonzero we must emit
3314 an insn to perform the compare (it can't be done within
3315 the conditional move). */
3318 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
3320 enum rtx_code code
= GET_CODE (cmp
);
3321 enum rtx_code cmov_code
= NE
;
3322 rtx op0
= alpha_compare
.op0
;
3323 rtx op1
= alpha_compare
.op1
;
3324 int fp_p
= alpha_compare
.fp_p
;
3325 enum machine_mode cmp_mode
3326 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3327 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3328 enum machine_mode cmov_mode
= VOIDmode
;
3329 int local_fast_math
= flag_unsafe_math_optimizations
;
3332 /* Zero the operands. */
3333 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3335 if (fp_p
!= FLOAT_MODE_P (mode
))
3337 enum rtx_code cmp_code
;
3342 /* If we have fp<->int register move instructions, do a cmov by
3343 performing the comparison in fp registers, and move the
3344 zero/nonzero value to integer registers, where we can then
3345 use a normal cmov, or vice-versa. */
3349 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3350 /* We have these compares. */
3351 cmp_code
= code
, code
= NE
;
3355 /* This must be reversed. */
3356 cmp_code
= EQ
, code
= EQ
;
3359 case GE
: case GT
: case GEU
: case GTU
:
3360 /* These normally need swapping, but for integer zero we have
3361 special patterns that recognize swapped operands. */
3362 if (!fp_p
&& op1
== const0_rtx
)
3363 cmp_code
= code
, code
= NE
;
3366 cmp_code
= swap_condition (code
);
3368 tem
= op0
, op0
= op1
, op1
= tem
;
3376 tem
= gen_reg_rtx (cmp_op_mode
);
3377 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3378 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3381 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3382 op0
= gen_lowpart (cmp_op_mode
, tem
);
3383 op1
= CONST0_RTX (cmp_op_mode
);
3385 local_fast_math
= 1;
3388 /* We may be able to use a conditional move directly.
3389 This avoids emitting spurious compares. */
3390 if (signed_comparison_operator (cmp
, VOIDmode
)
3391 && (!fp_p
|| local_fast_math
)
3392 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3393 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3395 /* We can't put the comparison inside the conditional move;
3396 emit a compare instruction and put that inside the
3397 conditional move. Make sure we emit only comparisons we have;
3398 swap or reverse as necessary. */
3405 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3406 /* We have these compares: */
3410 /* This must be reversed. */
3411 code
= reverse_condition (code
);
3415 case GE
: case GT
: case GEU
: case GTU
:
3416 /* These must be swapped. */
3417 if (op1
!= CONST0_RTX (cmp_mode
))
3419 code
= swap_condition (code
);
3420 tem
= op0
, op0
= op1
, op1
= tem
;
3430 if (!reg_or_0_operand (op0
, DImode
))
3431 op0
= force_reg (DImode
, op0
);
3432 if (!reg_or_8bit_operand (op1
, DImode
))
3433 op1
= force_reg (DImode
, op1
);
3436 /* ??? We mark the branch mode to be CCmode to prevent the compare
3437 and cmov from being combined, since the compare insn follows IEEE
3438 rules that the cmov does not. */
3439 if (fp_p
&& !local_fast_math
)
3442 tem
= gen_reg_rtx (cmp_op_mode
);
3443 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3444 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3447 /* Simplify a conditional move of two constants into a setcc with
3448 arithmetic. This is done with a splitter since combine would
3449 just undo the work if done during code generation. It also catches
3450 cases we wouldn't have before cse. */
3453 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
3454 rtx t_rtx
, rtx f_rtx
)
3456 HOST_WIDE_INT t
, f
, diff
;
3457 enum machine_mode mode
;
3458 rtx target
, subtarget
, tmp
;
3460 mode
= GET_MODE (dest
);
3465 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3466 || (code
== GE
|| code
== GT
))
3468 code
= reverse_condition (code
);
3469 diff
= t
, t
= f
, f
= diff
;
3473 subtarget
= target
= dest
;
3476 target
= gen_lowpart (DImode
, dest
);
3477 if (! no_new_pseudos
)
3478 subtarget
= gen_reg_rtx (DImode
);
3482 /* Below, we must be careful to use copy_rtx on target and subtarget
3483 in intermediate insns, as they may be a subreg rtx, which may not
3486 if (f
== 0 && exact_log2 (diff
) > 0
3487 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3488 viable over a longer latency cmove. On EV5, the E0 slot is a
3489 scarce resource, and on EV4 shift has the same latency as a cmove. */
3490 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3492 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3493 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3495 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3496 GEN_INT (exact_log2 (t
)));
3497 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3499 else if (f
== 0 && t
== -1)
3501 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3502 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3504 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3506 else if (diff
== 1 || diff
== 4 || diff
== 8)
3510 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3511 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3514 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3517 add_op
= GEN_INT (f
);
3518 if (sext_add_operand (add_op
, mode
))
3520 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3522 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3523 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3535 /* Look up the function X_floating library function name for the
3539 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
3543 const enum rtx_code code
;
3544 const char *const func
;
3547 static const struct xfloating_op vms_xfloating_ops
[] =
3549 { PLUS
, "OTS$ADD_X" },
3550 { MINUS
, "OTS$SUB_X" },
3551 { MULT
, "OTS$MUL_X" },
3552 { DIV
, "OTS$DIV_X" },
3553 { EQ
, "OTS$EQL_X" },
3554 { NE
, "OTS$NEQ_X" },
3555 { LT
, "OTS$LSS_X" },
3556 { LE
, "OTS$LEQ_X" },
3557 { GT
, "OTS$GTR_X" },
3558 { GE
, "OTS$GEQ_X" },
3559 { FIX
, "OTS$CVTXQ" },
3560 { FLOAT
, "OTS$CVTQX" },
3561 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3562 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3563 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3566 static const struct xfloating_op osf_xfloating_ops
[] =
3568 { PLUS
, "_OtsAddX" },
3569 { MINUS
, "_OtsSubX" },
3570 { MULT
, "_OtsMulX" },
3571 { DIV
, "_OtsDivX" },
3578 { FIX
, "_OtsCvtXQ" },
3579 { FLOAT
, "_OtsCvtQX" },
3580 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3581 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3582 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3585 const struct xfloating_op
*ops
;
3586 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3589 /* How irritating. Nothing to key off for the table. Hardcode
3590 knowledge of the G_floating routines. */
3591 if (TARGET_FLOAT_VAX
)
3593 if (TARGET_ABI_OPEN_VMS
)
3595 if (code
== FLOAT_EXTEND
)
3596 return "OTS$CVT_FLOAT_G_X";
3597 if (code
== FLOAT_TRUNCATE
)
3598 return "OTS$CVT_FLOAT_X_G";
3602 if (code
== FLOAT_EXTEND
)
3603 return "_OtsConvertFloatGX";
3604 if (code
== FLOAT_TRUNCATE
)
3605 return "_OtsConvertFloatXG";
3609 if (TARGET_ABI_OPEN_VMS
)
3610 ops
= vms_xfloating_ops
;
3612 ops
= osf_xfloating_ops
;
3614 for (i
= 0; i
< n
; ++i
)
3615 if (ops
[i
].code
== code
)
3621 /* Most X_floating operations take the rounding mode as an argument.
3622 Compute that here. */
3625 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
3626 enum alpha_fp_rounding_mode round
)
3632 case ALPHA_FPRM_NORM
:
3635 case ALPHA_FPRM_MINF
:
3638 case ALPHA_FPRM_CHOP
:
3641 case ALPHA_FPRM_DYN
:
3647 /* XXX For reference, round to +inf is mode = 3. */
3650 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3656 /* Emit an X_floating library function call.
3658 Note that these functions do not follow normal calling conventions:
3659 TFmode arguments are passed in two integer registers (as opposed to
3660 indirect); TFmode return values appear in R16+R17.
3662 FUNC is the function name to call.
3663 TARGET is where the output belongs.
3664 OPERANDS are the inputs.
3665 NOPERANDS is the count of inputs.
3666 EQUIV is the expression equivalent for the function.
3670 alpha_emit_xfloating_libcall (const char *func
, rtx target
, rtx operands
[],
3671 int noperands
, rtx equiv
)
3673 rtx usage
= NULL_RTX
, tmp
, reg
;
3678 for (i
= 0; i
< noperands
; ++i
)
3680 switch (GET_MODE (operands
[i
]))
3683 reg
= gen_rtx_REG (TFmode
, regno
);
3688 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3693 if (GET_CODE (operands
[i
]) != CONST_INT
)
3697 reg
= gen_rtx_REG (DImode
, regno
);
3705 emit_move_insn (reg
, operands
[i
]);
3706 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3709 switch (GET_MODE (target
))
3712 reg
= gen_rtx_REG (TFmode
, 16);
3715 reg
= gen_rtx_REG (DFmode
, 32);
3718 reg
= gen_rtx_REG (DImode
, 0);
3724 tmp
= gen_rtx_MEM (QImode
, init_one_libfunc (func
));
3725 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3726 const0_rtx
, const0_rtx
));
3727 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3732 emit_libcall_block (tmp
, target
, reg
, equiv
);
3735 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3738 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3742 rtx out_operands
[3];
3744 func
= alpha_lookup_xfloating_lib_func (code
);
3745 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3747 out_operands
[0] = operands
[1];
3748 out_operands
[1] = operands
[2];
3749 out_operands
[2] = GEN_INT (mode
);
3750 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3751 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3755 /* Emit an X_floating library function call for a comparison. */
3758 alpha_emit_xfloating_compare (enum rtx_code code
, rtx op0
, rtx op1
)
3761 rtx out
, operands
[2];
3763 func
= alpha_lookup_xfloating_lib_func (code
);
3767 out
= gen_reg_rtx (DImode
);
3769 /* ??? Strange mode for equiv because what's actually returned
3770 is -1,0,1, not a proper boolean value. */
3771 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3772 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3777 /* Emit an X_floating library function call for a conversion. */
3780 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3782 int noperands
= 1, mode
;
3783 rtx out_operands
[2];
3785 enum rtx_code code
= orig_code
;
3787 if (code
== UNSIGNED_FIX
)
3790 func
= alpha_lookup_xfloating_lib_func (code
);
3792 out_operands
[0] = operands
[1];
3797 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3798 out_operands
[1] = GEN_INT (mode
);
3801 case FLOAT_TRUNCATE
:
3802 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3803 out_operands
[1] = GEN_INT (mode
);
3810 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3811 gen_rtx_fmt_e (orig_code
,
3812 GET_MODE (operands
[0]),
3816 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3817 OP[0] into OP[0,1]. Naturally, output operand ordering is
3821 alpha_split_tfmode_pair (rtx operands
[4])
3823 if (GET_CODE (operands
[1]) == REG
)
3825 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3826 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3828 else if (GET_CODE (operands
[1]) == MEM
)
3830 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3831 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3833 else if (operands
[1] == CONST0_RTX (TFmode
))
3834 operands
[2] = operands
[3] = const0_rtx
;
3838 if (GET_CODE (operands
[0]) == REG
)
3840 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3841 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3843 else if (GET_CODE (operands
[0]) == MEM
)
3845 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3846 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3852 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3853 op2 is a register containing the sign bit, operation is the
3854 logical operation to be performed. */
3857 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3859 rtx high_bit
= operands
[2];
3863 alpha_split_tfmode_pair (operands
);
3865 /* Detect three flavors of operand overlap. */
3867 if (rtx_equal_p (operands
[0], operands
[2]))
3869 else if (rtx_equal_p (operands
[1], operands
[2]))
3871 if (rtx_equal_p (operands
[0], high_bit
))
3878 emit_move_insn (operands
[0], operands
[2]);
3880 /* ??? If the destination overlaps both source tf and high_bit, then
3881 assume source tf is dead in its entirety and use the other half
3882 for a scratch register. Otherwise "scratch" is just the proper
3883 destination register. */
3884 scratch
= operands
[move
< 2 ? 1 : 3];
3886 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3890 emit_move_insn (operands
[0], operands
[2]);
3892 emit_move_insn (operands
[1], scratch
);
3896 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3900 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3901 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3902 lda r3,X(r11) lda r3,X+2(r11)
3903 extwl r1,r3,r1 extql r1,r3,r1
3904 extwh r2,r3,r2 extqh r2,r3,r2
3905 or r1.r2.r1 or r1,r2,r1
3908 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3909 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3910 lda r3,X(r11) lda r3,X(r11)
3911 extll r1,r3,r1 extll r1,r3,r1
3912 extlh r2,r3,r2 extlh r2,r3,r2
3913 or r1.r2.r1 addl r1,r2,r1
3915 quad: ldq_u r1,X(r11)
3924 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3925 HOST_WIDE_INT ofs
, int sign
)
3927 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3928 enum machine_mode mode
;
3930 meml
= gen_reg_rtx (DImode
);
3931 memh
= gen_reg_rtx (DImode
);
3932 addr
= gen_reg_rtx (DImode
);
3933 extl
= gen_reg_rtx (DImode
);
3934 exth
= gen_reg_rtx (DImode
);
3936 mema
= XEXP (mem
, 0);
3937 if (GET_CODE (mema
) == LO_SUM
)
3938 mema
= force_reg (Pmode
, mema
);
3940 /* AND addresses cannot be in any alias set, since they may implicitly
3941 alias surrounding code. Ideally we'd have some alias set that
3942 covered all types except those with alignment 8 or higher. */
3944 tmp
= change_address (mem
, DImode
,
3945 gen_rtx_AND (DImode
,
3946 plus_constant (mema
, ofs
),
3948 set_mem_alias_set (tmp
, 0);
3949 emit_move_insn (meml
, tmp
);
3951 tmp
= change_address (mem
, DImode
,
3952 gen_rtx_AND (DImode
,
3953 plus_constant (mema
, ofs
+ size
- 1),
3955 set_mem_alias_set (tmp
, 0);
3956 emit_move_insn (memh
, tmp
);
3958 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3960 emit_move_insn (addr
, plus_constant (mema
, -1));
3962 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3963 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3965 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3966 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3967 addr
, 1, OPTAB_WIDEN
);
3969 else if (sign
&& size
== 2)
3971 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3973 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3974 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3976 /* We must use tgt here for the target. Alpha-vms port fails if we use
3977 addr for the target, because addr is marked as a pointer and combine
3978 knows that pointers are always sign-extended 32 bit values. */
3979 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3980 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3981 addr
, 1, OPTAB_WIDEN
);
3985 if (WORDS_BIG_ENDIAN
)
3987 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3991 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3996 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4001 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4008 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4012 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4013 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4017 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4022 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4027 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4036 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4037 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4042 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4045 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4048 alpha_expand_unaligned_store (rtx dst
, rtx src
,
4049 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
4051 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4053 dstl
= gen_reg_rtx (DImode
);
4054 dsth
= gen_reg_rtx (DImode
);
4055 insl
= gen_reg_rtx (DImode
);
4056 insh
= gen_reg_rtx (DImode
);
4058 dsta
= XEXP (dst
, 0);
4059 if (GET_CODE (dsta
) == LO_SUM
)
4060 dsta
= force_reg (Pmode
, dsta
);
4062 /* AND addresses cannot be in any alias set, since they may implicitly
4063 alias surrounding code. Ideally we'd have some alias set that
4064 covered all types except those with alignment 8 or higher. */
4066 meml
= change_address (dst
, DImode
,
4067 gen_rtx_AND (DImode
,
4068 plus_constant (dsta
, ofs
),
4070 set_mem_alias_set (meml
, 0);
4072 memh
= change_address (dst
, DImode
,
4073 gen_rtx_AND (DImode
,
4074 plus_constant (dsta
, ofs
+ size
- 1),
4076 set_mem_alias_set (memh
, 0);
4078 emit_move_insn (dsth
, memh
);
4079 emit_move_insn (dstl
, meml
);
4080 if (WORDS_BIG_ENDIAN
)
4082 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4084 if (src
!= const0_rtx
)
4089 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4092 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4095 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4098 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4099 GEN_INT (size
*8), addr
));
4105 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4109 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4110 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4114 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4118 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4122 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4124 if (src
!= const0_rtx
)
4126 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4127 GEN_INT (size
*8), addr
));
4132 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4135 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4138 emit_insn (gen_insql_le (insl
, src
, addr
));
4143 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4148 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4152 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4153 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4157 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4162 if (src
!= const0_rtx
)
4164 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4165 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4168 if (WORDS_BIG_ENDIAN
)
4170 emit_move_insn (meml
, dstl
);
4171 emit_move_insn (memh
, dsth
);
4175 /* Must store high before low for degenerate case of aligned. */
4176 emit_move_insn (memh
, dsth
);
4177 emit_move_insn (meml
, dstl
);
4181 /* The block move code tries to maximize speed by separating loads and
4182 stores at the expense of register pressure: we load all of the data
4183 before we store it back out. There are two secondary effects worth
4184 mentioning, that this speeds copying to/from aligned and unaligned
4185 buffers, and that it makes the code significantly easier to write. */
4187 #define MAX_MOVE_WORDS 8
4189 /* Load an integral number of consecutive unaligned quadwords. */
4192 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
4193 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4195 rtx
const im8
= GEN_INT (-8);
4196 rtx
const i64
= GEN_INT (64);
4197 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4198 rtx sreg
, areg
, tmp
, smema
;
4201 smema
= XEXP (smem
, 0);
4202 if (GET_CODE (smema
) == LO_SUM
)
4203 smema
= force_reg (Pmode
, smema
);
4205 /* Generate all the tmp registers we need. */
4206 for (i
= 0; i
< words
; ++i
)
4208 data_regs
[i
] = out_regs
[i
];
4209 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4211 data_regs
[words
] = gen_reg_rtx (DImode
);
4214 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4216 /* Load up all of the source data. */
4217 for (i
= 0; i
< words
; ++i
)
4219 tmp
= change_address (smem
, DImode
,
4220 gen_rtx_AND (DImode
,
4221 plus_constant (smema
, 8*i
),
4223 set_mem_alias_set (tmp
, 0);
4224 emit_move_insn (data_regs
[i
], tmp
);
4227 tmp
= change_address (smem
, DImode
,
4228 gen_rtx_AND (DImode
,
4229 plus_constant (smema
, 8*words
- 1),
4231 set_mem_alias_set (tmp
, 0);
4232 emit_move_insn (data_regs
[words
], tmp
);
4234 /* Extract the half-word fragments. Unfortunately DEC decided to make
4235 extxh with offset zero a noop instead of zeroing the register, so
4236 we must take care of that edge condition ourselves with cmov. */
4238 sreg
= copy_addr_to_reg (smema
);
4239 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4241 if (WORDS_BIG_ENDIAN
)
4242 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4243 for (i
= 0; i
< words
; ++i
)
4245 if (WORDS_BIG_ENDIAN
)
4247 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4248 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4252 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4253 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4255 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4256 gen_rtx_IF_THEN_ELSE (DImode
,
4257 gen_rtx_EQ (DImode
, areg
,
4259 const0_rtx
, ext_tmps
[i
])));
4262 /* Merge the half-words into whole words. */
4263 for (i
= 0; i
< words
; ++i
)
4265 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4266 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4270 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4271 may be NULL to store zeros. */
4274 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
4275 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4277 rtx
const im8
= GEN_INT (-8);
4278 rtx
const i64
= GEN_INT (64);
4279 rtx ins_tmps
[MAX_MOVE_WORDS
];
4280 rtx st_tmp_1
, st_tmp_2
, dreg
;
4281 rtx st_addr_1
, st_addr_2
, dmema
;
4284 dmema
= XEXP (dmem
, 0);
4285 if (GET_CODE (dmema
) == LO_SUM
)
4286 dmema
= force_reg (Pmode
, dmema
);
4288 /* Generate all the tmp registers we need. */
4289 if (data_regs
!= NULL
)
4290 for (i
= 0; i
< words
; ++i
)
4291 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4292 st_tmp_1
= gen_reg_rtx(DImode
);
4293 st_tmp_2
= gen_reg_rtx(DImode
);
4296 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4298 st_addr_2
= change_address (dmem
, DImode
,
4299 gen_rtx_AND (DImode
,
4300 plus_constant (dmema
, words
*8 - 1),
4302 set_mem_alias_set (st_addr_2
, 0);
4304 st_addr_1
= change_address (dmem
, DImode
,
4305 gen_rtx_AND (DImode
, dmema
, im8
));
4306 set_mem_alias_set (st_addr_1
, 0);
4308 /* Load up the destination end bits. */
4309 emit_move_insn (st_tmp_2
, st_addr_2
);
4310 emit_move_insn (st_tmp_1
, st_addr_1
);
4312 /* Shift the input data into place. */
4313 dreg
= copy_addr_to_reg (dmema
);
4314 if (WORDS_BIG_ENDIAN
)
4315 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4316 if (data_regs
!= NULL
)
4318 for (i
= words
-1; i
>= 0; --i
)
4320 if (WORDS_BIG_ENDIAN
)
4322 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4323 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4327 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4328 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4331 for (i
= words
-1; i
> 0; --i
)
4333 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4334 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4339 /* Split and merge the ends with the destination data. */
4340 if (WORDS_BIG_ENDIAN
)
4342 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4343 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4347 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4348 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4351 if (data_regs
!= NULL
)
4353 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4354 st_tmp_2
, 1, OPTAB_WIDEN
);
4355 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4356 st_tmp_1
, 1, OPTAB_WIDEN
);
4360 if (WORDS_BIG_ENDIAN
)
4361 emit_move_insn (st_addr_1
, st_tmp_1
);
4363 emit_move_insn (st_addr_2
, st_tmp_2
);
4364 for (i
= words
-1; i
> 0; --i
)
4366 rtx tmp
= change_address (dmem
, DImode
,
4367 gen_rtx_AND (DImode
,
4368 plus_constant(dmema
,
4369 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4371 set_mem_alias_set (tmp
, 0);
4372 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4374 if (WORDS_BIG_ENDIAN
)
4375 emit_move_insn (st_addr_2
, st_tmp_2
);
4377 emit_move_insn (st_addr_1
, st_tmp_1
);
4381 /* Expand string/block move operations.
4383 operands[0] is the pointer to the destination.
4384 operands[1] is the pointer to the source.
4385 operands[2] is the number of bytes to move.
4386 operands[3] is the alignment. */
4389 alpha_expand_block_move (rtx operands
[])
4391 rtx bytes_rtx
= operands
[2];
4392 rtx align_rtx
= operands
[3];
4393 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4394 HOST_WIDE_INT bytes
= orig_bytes
;
4395 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4396 HOST_WIDE_INT dst_align
= src_align
;
4397 rtx orig_src
= operands
[1];
4398 rtx orig_dst
= operands
[0];
4399 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4401 unsigned int i
, words
, ofs
, nregs
= 0;
4403 if (orig_bytes
<= 0)
4405 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4408 /* Look for additional alignment information from recorded register info. */
4410 tmp
= XEXP (orig_src
, 0);
4411 if (GET_CODE (tmp
) == REG
)
4412 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4413 else if (GET_CODE (tmp
) == PLUS
4414 && GET_CODE (XEXP (tmp
, 0)) == REG
4415 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4417 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4418 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4422 if (a
>= 64 && c
% 8 == 0)
4424 else if (a
>= 32 && c
% 4 == 0)
4426 else if (a
>= 16 && c
% 2 == 0)
4431 tmp
= XEXP (orig_dst
, 0);
4432 if (GET_CODE (tmp
) == REG
)
4433 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4434 else if (GET_CODE (tmp
) == PLUS
4435 && GET_CODE (XEXP (tmp
, 0)) == REG
4436 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4438 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4439 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4443 if (a
>= 64 && c
% 8 == 0)
4445 else if (a
>= 32 && c
% 4 == 0)
4447 else if (a
>= 16 && c
% 2 == 0)
4452 /* Load the entire block into registers. */
4453 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4455 enum machine_mode mode
;
4457 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4459 /* Don't use the existing register if we're reading more than
4460 is held in the register. Nor if there is not a mode that
4461 handles the exact size. */
4462 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4463 if (GET_CODE (tmp
) == REG
4465 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4469 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4470 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4474 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4479 /* No appropriate mode; fall back on memory. */
4480 orig_src
= replace_equiv_address (orig_src
,
4481 copy_addr_to_reg (XEXP (orig_src
, 0)));
4482 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4486 if (src_align
>= 64 && bytes
>= 8)
4490 for (i
= 0; i
< words
; ++i
)
4491 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4493 for (i
= 0; i
< words
; ++i
)
4494 emit_move_insn (data_regs
[nregs
+ i
],
4495 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4502 if (src_align
>= 32 && bytes
>= 4)
4506 for (i
= 0; i
< words
; ++i
)
4507 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4509 for (i
= 0; i
< words
; ++i
)
4510 emit_move_insn (data_regs
[nregs
+ i
],
4511 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4522 for (i
= 0; i
< words
+1; ++i
)
4523 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4525 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4533 if (! TARGET_BWX
&& bytes
>= 4)
4535 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4536 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4543 if (src_align
>= 16)
4546 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4547 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4550 } while (bytes
>= 2);
4552 else if (! TARGET_BWX
)
4554 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4555 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4563 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4564 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4571 if (nregs
> ARRAY_SIZE (data_regs
))
4574 /* Now save it back out again. */
4578 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4580 enum machine_mode mode
;
4581 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4583 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4584 if (GET_CODE (tmp
) == REG
&& GET_MODE (tmp
) == mode
)
4588 emit_move_insn (tmp
, data_regs
[0]);
4593 else if (nregs
== 2 && mode
== TImode
)
4595 /* Undo the subregging done above when copying between
4596 two TImode registers. */
4597 if (GET_CODE (data_regs
[0]) == SUBREG
4598 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4599 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4605 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4606 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4610 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4611 data_regs
[1], NULL_RTX
);
4619 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4620 /* ??? Optimize mode < dst_mode with strict_low_part. */
4622 /* No appropriate mode; fall back on memory. We can speed things
4623 up by recognizing extra alignment information. */
4624 orig_dst
= replace_equiv_address (orig_dst
,
4625 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4626 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4629 /* Write out the data in whatever chunks reading the source allowed. */
4630 if (dst_align
>= 64)
4632 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4634 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4641 if (dst_align
>= 32)
4643 /* If the source has remaining DImode regs, write them out in
4645 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4647 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4648 NULL_RTX
, 1, OPTAB_WIDEN
);
4650 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4651 gen_lowpart (SImode
, data_regs
[i
]));
4652 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4653 gen_lowpart (SImode
, tmp
));
4658 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4660 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4667 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4669 /* Write out a remaining block of words using unaligned methods. */
4671 for (words
= 1; i
+ words
< nregs
; words
++)
4672 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4676 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4678 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4685 /* Due to the above, this won't be aligned. */
4686 /* ??? If we have more than one of these, consider constructing full
4687 words in registers and using alpha_expand_unaligned_store_words. */
4688 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4690 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4695 if (dst_align
>= 16)
4696 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4698 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4703 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4705 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4710 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4712 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4726 alpha_expand_block_clear (rtx operands
[])
4728 rtx bytes_rtx
= operands
[1];
4729 rtx align_rtx
= operands
[2];
4730 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4731 HOST_WIDE_INT bytes
= orig_bytes
;
4732 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4733 HOST_WIDE_INT alignofs
= 0;
4734 rtx orig_dst
= operands
[0];
4736 int i
, words
, ofs
= 0;
4738 if (orig_bytes
<= 0)
4740 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4743 /* Look for stricter alignment. */
4744 tmp
= XEXP (orig_dst
, 0);
4745 if (GET_CODE (tmp
) == REG
)
4746 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4747 else if (GET_CODE (tmp
) == PLUS
4748 && GET_CODE (XEXP (tmp
, 0)) == REG
4749 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4751 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4752 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4757 align
= a
, alignofs
= 8 - c
% 8;
4759 align
= a
, alignofs
= 4 - c
% 4;
4761 align
= a
, alignofs
= 2 - c
% 2;
4764 else if (GET_CODE (tmp
) == ADDRESSOF
)
4766 enum machine_mode mode
;
4768 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4769 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4771 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4775 /* No appropriate mode; fall back on memory. */
4776 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4777 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4780 /* Handle an unaligned prefix first. */
4784 #if HOST_BITS_PER_WIDE_INT >= 64
4785 /* Given that alignofs is bounded by align, the only time BWX could
4786 generate three stores is for a 7 byte fill. Prefer two individual
4787 stores over a load/mask/store sequence. */
4788 if ((!TARGET_BWX
|| alignofs
== 7)
4790 && !(alignofs
== 4 && bytes
>= 4))
4792 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4793 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4797 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4798 set_mem_alias_set (mem
, 0);
4800 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4801 if (bytes
< alignofs
)
4803 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4814 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4815 NULL_RTX
, 1, OPTAB_WIDEN
);
4817 emit_move_insn (mem
, tmp
);
4821 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4823 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4828 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4830 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4835 if (alignofs
== 4 && bytes
>= 4)
4837 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4843 /* If we've not used the extra lead alignment information by now,
4844 we won't be able to. Downgrade align to match what's left over. */
4847 alignofs
= alignofs
& -alignofs
;
4848 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4852 /* Handle a block of contiguous long-words. */
4854 if (align
>= 64 && bytes
>= 8)
4858 for (i
= 0; i
< words
; ++i
)
4859 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4866 /* If the block is large and appropriately aligned, emit a single
4867 store followed by a sequence of stq_u insns. */
4869 if (align
>= 32 && bytes
> 16)
4873 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4877 orig_dsta
= XEXP (orig_dst
, 0);
4878 if (GET_CODE (orig_dsta
) == LO_SUM
)
4879 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4882 for (i
= 0; i
< words
; ++i
)
4885 = change_address (orig_dst
, DImode
,
4886 gen_rtx_AND (DImode
,
4887 plus_constant (orig_dsta
, ofs
+ i
*8),
4889 set_mem_alias_set (mem
, 0);
4890 emit_move_insn (mem
, const0_rtx
);
4893 /* Depending on the alignment, the first stq_u may have overlapped
4894 with the initial stl, which means that the last stq_u didn't
4895 write as much as it would appear. Leave those questionable bytes
4897 bytes
-= words
* 8 - 4;
4898 ofs
+= words
* 8 - 4;
4901 /* Handle a smaller block of aligned words. */
4903 if ((align
>= 64 && bytes
== 4)
4904 || (align
== 32 && bytes
>= 4))
4908 for (i
= 0; i
< words
; ++i
)
4909 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4916 /* An unaligned block uses stq_u stores for as many as possible. */
4922 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4928 /* Next clean up any trailing pieces. */
4930 #if HOST_BITS_PER_WIDE_INT >= 64
4931 /* Count the number of bits in BYTES for which aligned stores could
4934 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4938 /* If we have appropriate alignment (and it wouldn't take too many
4939 instructions otherwise), mask out the bytes we need. */
4940 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4947 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4948 set_mem_alias_set (mem
, 0);
4950 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4952 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4953 NULL_RTX
, 1, OPTAB_WIDEN
);
4955 emit_move_insn (mem
, tmp
);
4958 else if (align
>= 32 && bytes
< 4)
4963 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4964 set_mem_alias_set (mem
, 0);
4966 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4968 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4969 NULL_RTX
, 1, OPTAB_WIDEN
);
4971 emit_move_insn (mem
, tmp
);
4977 if (!TARGET_BWX
&& bytes
>= 4)
4979 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4989 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4993 } while (bytes
>= 2);
4995 else if (! TARGET_BWX
)
4997 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5005 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5013 /* Returns a mask so that zap(x, value) == x & mask. */
5016 alpha_expand_zap_mask (HOST_WIDE_INT value
)
5021 if (HOST_BITS_PER_WIDE_INT
>= 64)
5023 HOST_WIDE_INT mask
= 0;
5025 for (i
= 7; i
>= 0; --i
)
5028 if (!((value
>> i
) & 1))
5032 result
= gen_int_mode (mask
, DImode
);
5034 else if (HOST_BITS_PER_WIDE_INT
== 32)
5036 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5038 for (i
= 7; i
>= 4; --i
)
5041 if (!((value
>> i
) & 1))
5045 for (i
= 3; i
>= 0; --i
)
5048 if (!((value
>> i
) & 1))
5052 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5061 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
5062 enum machine_mode mode
,
5063 rtx op0
, rtx op1
, rtx op2
)
5065 op0
= gen_lowpart (mode
, op0
);
5067 if (op1
== const0_rtx
)
5068 op1
= CONST0_RTX (mode
);
5070 op1
= gen_lowpart (mode
, op1
);
5072 if (op2
== const0_rtx
)
5073 op2
= CONST0_RTX (mode
);
5075 op2
= gen_lowpart (mode
, op2
);
5077 emit_insn ((*gen
) (op0
, op1
, op2
));
5080 /* Adjust the cost of a scheduling dependency. Return the new cost of
5081 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5084 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5086 enum attr_type insn_type
, dep_insn_type
;
5088 /* If the dependence is an anti-dependence, there is no cost. For an
5089 output dependence, there is sometimes a cost, but it doesn't seem
5090 worth handling those few cases. */
5091 if (REG_NOTE_KIND (link
) != 0)
5094 /* If we can't recognize the insns, we can't really do anything. */
5095 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5098 insn_type
= get_attr_type (insn
);
5099 dep_insn_type
= get_attr_type (dep_insn
);
5101 /* Bring in the user-defined memory latency. */
5102 if (dep_insn_type
== TYPE_ILD
5103 || dep_insn_type
== TYPE_FLD
5104 || dep_insn_type
== TYPE_LDSYM
)
5105 cost
+= alpha_memory_latency
-1;
5107 /* Everything else handled in DFA bypasses now. */
5112 /* The number of instructions that can be issued per cycle. */
5115 alpha_issue_rate (void)
5117 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5121 alpha_use_dfa_pipeline_interface (void)
5126 /* How many alternative schedules to try. This should be as wide as the
5127 scheduling freedom in the DFA, but no wider. Making this value too
5128 large results extra work for the scheduler.
5130 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5131 alternative schedules. For EV5, we can choose between E0/E1 and
5132 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5135 alpha_multipass_dfa_lookahead (void)
5137 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5140 /* Machine-specific function data. */
5142 struct machine_function
GTY(())
5145 /* List of call information words for calls from this function. */
5146 struct rtx_def
*first_ciw
;
5147 struct rtx_def
*last_ciw
;
5150 /* List of deferred case vectors. */
5151 struct rtx_def
*addr_list
;
5154 const char *some_ld_name
;
5157 /* How to allocate a 'struct machine_function'. */
5159 static struct machine_function
*
5160 alpha_init_machine_status (void)
5162 return ((struct machine_function
*)
5163 ggc_alloc_cleared (sizeof (struct machine_function
)));
5166 /* Functions to save and restore alpha_return_addr_rtx. */
5168 /* Start the ball rolling with RETURN_ADDR_RTX. */
5171 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
5176 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5179 /* Return or create a pseudo containing the gp value for the current
5180 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5183 alpha_gp_save_rtx (void)
5185 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5186 if (GET_CODE (r
) != MEM
)
5187 r
= gen_mem_addressof (r
, NULL_TREE
, /*rescan=*/true);
5192 alpha_ra_ever_killed (void)
5196 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5197 return regs_ever_live
[REG_RA
];
5199 push_topmost_sequence ();
5201 pop_topmost_sequence ();
5203 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5207 /* Return the trap mode suffix applicable to the current
5208 instruction, or NULL. */
5211 get_trap_mode_suffix (void)
5213 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5217 case TRAP_SUFFIX_NONE
:
5220 case TRAP_SUFFIX_SU
:
5221 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5225 case TRAP_SUFFIX_SUI
:
5226 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5230 case TRAP_SUFFIX_V_SV
:
5238 case ALPHA_FPTM_SUI
:
5243 case TRAP_SUFFIX_V_SV_SVI
:
5252 case ALPHA_FPTM_SUI
:
5257 case TRAP_SUFFIX_U_SU_SUI
:
5266 case ALPHA_FPTM_SUI
:
5274 /* Return the rounding mode suffix applicable to the current
5275 instruction, or NULL. */
5278 get_round_mode_suffix (void)
5280 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5284 case ROUND_SUFFIX_NONE
:
5286 case ROUND_SUFFIX_NORMAL
:
5289 case ALPHA_FPRM_NORM
:
5291 case ALPHA_FPRM_MINF
:
5293 case ALPHA_FPRM_CHOP
:
5295 case ALPHA_FPRM_DYN
:
5300 case ROUND_SUFFIX_C
:
5306 /* Locate some local-dynamic symbol still in use by this function
5307 so that we can print its name in some movdi_er_tlsldm pattern. */
5310 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5314 if (GET_CODE (x
) == SYMBOL_REF
5315 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5317 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5325 get_some_local_dynamic_name (void)
5329 if (cfun
->machine
->some_ld_name
)
5330 return cfun
->machine
->some_ld_name
;
5332 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5334 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5335 return cfun
->machine
->some_ld_name
;
5340 /* Print an operand. Recognize special options, documented below. */
5343 print_operand (FILE *file
, rtx x
, int code
)
5350 /* Print the assembler name of the current function. */
5351 assemble_name (file
, alpha_fnname
);
5355 assemble_name (file
, get_some_local_dynamic_name ());
5360 const char *trap
= get_trap_mode_suffix ();
5361 const char *round
= get_round_mode_suffix ();
5364 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5365 (trap
? trap
: ""), (round
? round
: ""));
5370 /* Generates single precision instruction suffix. */
5371 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5375 /* Generates double precision instruction suffix. */
5376 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5380 /* Generates a nop after a noreturn call at the very end of the
5382 if (next_real_insn (current_output_insn
) == 0)
5383 fprintf (file
, "\n\tnop");
5387 if (alpha_this_literal_sequence_number
== 0)
5388 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5389 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5393 if (alpha_this_gpdisp_sequence_number
== 0)
5394 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5395 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5399 if (GET_CODE (x
) == HIGH
)
5400 output_addr_const (file
, XEXP (x
, 0));
5402 output_operand_lossage ("invalid %%H value");
5409 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5411 x
= XVECEXP (x
, 0, 0);
5412 lituse
= "lituse_tlsgd";
5414 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5416 x
= XVECEXP (x
, 0, 0);
5417 lituse
= "lituse_tlsldm";
5419 else if (GET_CODE (x
) == CONST_INT
)
5420 lituse
= "lituse_jsr";
5423 output_operand_lossage ("invalid %%J value");
5427 if (x
!= const0_rtx
)
5428 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5433 /* If this operand is the constant zero, write it as "$31". */
5434 if (GET_CODE (x
) == REG
)
5435 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5436 else if (x
== CONST0_RTX (GET_MODE (x
)))
5437 fprintf (file
, "$31");
5439 output_operand_lossage ("invalid %%r value");
5443 /* Similar, but for floating-point. */
5444 if (GET_CODE (x
) == REG
)
5445 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5446 else if (x
== CONST0_RTX (GET_MODE (x
)))
5447 fprintf (file
, "$f31");
5449 output_operand_lossage ("invalid %%R value");
5453 /* Write the 1's complement of a constant. */
5454 if (GET_CODE (x
) != CONST_INT
)
5455 output_operand_lossage ("invalid %%N value");
5457 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5461 /* Write 1 << C, for a constant C. */
5462 if (GET_CODE (x
) != CONST_INT
)
5463 output_operand_lossage ("invalid %%P value");
5465 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5469 /* Write the high-order 16 bits of a constant, sign-extended. */
5470 if (GET_CODE (x
) != CONST_INT
)
5471 output_operand_lossage ("invalid %%h value");
5473 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5477 /* Write the low-order 16 bits of a constant, sign-extended. */
5478 if (GET_CODE (x
) != CONST_INT
)
5479 output_operand_lossage ("invalid %%L value");
5481 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5482 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5486 /* Write mask for ZAP insn. */
5487 if (GET_CODE (x
) == CONST_DOUBLE
)
5489 HOST_WIDE_INT mask
= 0;
5490 HOST_WIDE_INT value
;
5492 value
= CONST_DOUBLE_LOW (x
);
5493 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5498 value
= CONST_DOUBLE_HIGH (x
);
5499 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5502 mask
|= (1 << (i
+ sizeof (int)));
5504 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5507 else if (GET_CODE (x
) == CONST_INT
)
5509 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5511 for (i
= 0; i
< 8; i
++, value
>>= 8)
5515 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5518 output_operand_lossage ("invalid %%m value");
5522 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5523 if (GET_CODE (x
) != CONST_INT
5524 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5525 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5526 output_operand_lossage ("invalid %%M value");
5528 fprintf (file
, "%s",
5529 (INTVAL (x
) == 8 ? "b"
5530 : INTVAL (x
) == 16 ? "w"
5531 : INTVAL (x
) == 32 ? "l"
5536 /* Similar, except do it from the mask. */
5537 if (GET_CODE (x
) == CONST_INT
)
5539 HOST_WIDE_INT value
= INTVAL (x
);
5546 if (value
== 0xffff)
5551 if (value
== 0xffffffff)
5562 else if (HOST_BITS_PER_WIDE_INT
== 32
5563 && GET_CODE (x
) == CONST_DOUBLE
5564 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5565 && CONST_DOUBLE_HIGH (x
) == 0)
5570 output_operand_lossage ("invalid %%U value");
5574 /* Write the constant value divided by 8 for little-endian mode or
5575 (56 - value) / 8 for big-endian mode. */
5577 if (GET_CODE (x
) != CONST_INT
5578 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5581 || (INTVAL (x
) & 7) != 0)
5582 output_operand_lossage ("invalid %%s value");
5584 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5586 ? (56 - INTVAL (x
)) / 8
5591 /* Same, except compute (64 - c) / 8 */
5593 if (GET_CODE (x
) != CONST_INT
5594 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5595 && (INTVAL (x
) & 7) != 8)
5596 output_operand_lossage ("invalid %%s value");
5598 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5603 /* On Unicos/Mk systems: use a DEX expression if the symbol
5604 clashes with a register name. */
5605 int dex
= unicosmk_need_dex (x
);
5607 fprintf (file
, "DEX(%d)", dex
);
5609 output_addr_const (file
, x
);
5613 case 'C': case 'D': case 'c': case 'd':
5614 /* Write out comparison name. */
5616 enum rtx_code c
= GET_CODE (x
);
5618 if (GET_RTX_CLASS (c
) != '<')
5619 output_operand_lossage ("invalid %%C value");
5621 else if (code
== 'D')
5622 c
= reverse_condition (c
);
5623 else if (code
== 'c')
5624 c
= swap_condition (c
);
5625 else if (code
== 'd')
5626 c
= swap_condition (reverse_condition (c
));
5629 fprintf (file
, "ule");
5631 fprintf (file
, "ult");
5632 else if (c
== UNORDERED
)
5633 fprintf (file
, "un");
5635 fprintf (file
, "%s", GET_RTX_NAME (c
));
5640 /* Write the divide or modulus operator. */
5641 switch (GET_CODE (x
))
5644 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5647 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5650 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5653 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5656 output_operand_lossage ("invalid %%E value");
5662 /* Write "_u" for unaligned access. */
5663 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5664 fprintf (file
, "_u");
5668 if (GET_CODE (x
) == REG
)
5669 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5670 else if (GET_CODE (x
) == MEM
)
5671 output_address (XEXP (x
, 0));
5672 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5674 switch (XINT (XEXP (x
, 0), 1))
5678 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5681 output_operand_lossage ("unknown relocation unspec");
5686 output_addr_const (file
, x
);
5690 output_operand_lossage ("invalid %%xn code");
5695 print_operand_address (FILE *file
, rtx addr
)
5698 HOST_WIDE_INT offset
= 0;
5700 if (GET_CODE (addr
) == AND
)
5701 addr
= XEXP (addr
, 0);
5703 if (GET_CODE (addr
) == PLUS
5704 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5706 offset
= INTVAL (XEXP (addr
, 1));
5707 addr
= XEXP (addr
, 0);
5710 if (GET_CODE (addr
) == LO_SUM
)
5712 const char *reloc16
, *reloclo
;
5713 rtx op1
= XEXP (addr
, 1);
5715 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5717 op1
= XEXP (op1
, 0);
5718 switch (XINT (op1
, 1))
5722 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5726 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5729 output_operand_lossage ("unknown relocation unspec");
5733 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5738 reloclo
= "gprellow";
5739 output_addr_const (file
, op1
);
5743 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5745 addr
= XEXP (addr
, 0);
5746 if (GET_CODE (addr
) == REG
)
5747 basereg
= REGNO (addr
);
5748 else if (GET_CODE (addr
) == SUBREG
5749 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5750 basereg
= subreg_regno (addr
);
5754 fprintf (file
, "($%d)\t\t!%s", basereg
,
5755 (basereg
== 29 ? reloc16
: reloclo
));
5759 if (GET_CODE (addr
) == REG
)
5760 basereg
= REGNO (addr
);
5761 else if (GET_CODE (addr
) == SUBREG
5762 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5763 basereg
= subreg_regno (addr
);
5764 else if (GET_CODE (addr
) == CONST_INT
)
5765 offset
= INTVAL (addr
);
5767 #if TARGET_ABI_OPEN_VMS
5768 else if (GET_CODE (addr
) == SYMBOL_REF
)
5770 fprintf (file
, "%s", XSTR (addr
, 0));
5773 else if (GET_CODE (addr
) == CONST
5774 && GET_CODE (XEXP (addr
, 0)) == PLUS
5775 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5777 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5778 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5779 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5787 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5790 /* Emit RTL insns to initialize the variable parts of a trampoline at
5791 TRAMP. FNADDR is an RTX for the address of the function's pure
5792 code. CXT is an RTX for the static chain value for the function.
5794 The three offset parameters are for the individual template's
5795 layout. A JMPOFS < 0 indicates that the trampoline does not
5796 contain instructions at all.
5798 We assume here that a function will be called many more times than
5799 its address is taken (e.g., it might be passed to qsort), so we
5800 take the trouble to initialize the "hint" field in the JMP insn.
5801 Note that the hint field is PC (new) + 4 * bits 13:0. */
5804 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5805 int fnofs
, int cxtofs
, int jmpofs
)
5807 rtx temp
, temp1
, addr
;
5808 /* VMS really uses DImode pointers in memory at this point. */
5809 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5811 #ifdef POINTERS_EXTEND_UNSIGNED
5812 fnaddr
= convert_memory_address (mode
, fnaddr
);
5813 cxt
= convert_memory_address (mode
, cxt
);
5816 /* Store function address and CXT. */
5817 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5818 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5819 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5820 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5822 /* This has been disabled since the hint only has a 32k range, and in
5823 no existing OS is the stack within 32k of the text segment. */
5824 if (0 && jmpofs
>= 0)
5826 /* Compute hint value. */
5827 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5828 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5830 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5831 build_int_2 (2, 0), NULL_RTX
, 1);
5832 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5833 GEN_INT (0x3fff), 0);
5835 /* Merge in the hint. */
5836 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5837 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5838 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5839 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5841 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5844 #ifdef TRANSFER_FROM_TRAMPOLINE
5845 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5846 0, VOIDmode
, 1, tramp
, Pmode
);
5850 emit_insn (gen_imb ());
5853 /* Determine where to put an argument to a function.
5854 Value is zero to push the argument on the stack,
5855 or a hard register in which to store the argument.
5857 MODE is the argument's machine mode.
5858 TYPE is the data type of the argument (as a tree).
5859 This is null for libcalls where that information may
5861 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5862 the preceding args and about the function being called.
5863 NAMED is nonzero if this argument is a named parameter
5864 (otherwise it is an extra parameter matching an ellipsis).
5866 On Alpha the first 6 words of args are normally in registers
5867 and the rest are pushed. */
5870 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5871 int named ATTRIBUTE_UNUSED
)
5876 /* Don't get confused and pass small structures in FP registers. */
5877 if (type
&& AGGREGATE_TYPE_P (type
))
5881 #ifdef ENABLE_CHECKING
5882 /* With SPLIT_COMPLEX_ARGS, we shouldn't see any raw complex
5884 if (COMPLEX_MODE_P (mode
))
5888 /* Set up defaults for FP operands passed in FP registers, and
5889 integral operands passed in integer registers. */
5890 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5896 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5897 the three platforms, so we can't avoid conditional compilation. */
5898 #if TARGET_ABI_OPEN_VMS
5900 if (mode
== VOIDmode
)
5901 return alpha_arg_info_reg_val (cum
);
5903 num_args
= cum
.num_args
;
5904 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5907 #elif TARGET_ABI_UNICOSMK
5911 /* If this is the last argument, generate the call info word (CIW). */
5912 /* ??? We don't include the caller's line number in the CIW because
5913 I don't know how to determine it if debug infos are turned off. */
5914 if (mode
== VOIDmode
)
5923 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5924 if (cum
.reg_args_type
[i
])
5925 lo
|= (1 << (7 - i
));
5927 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5930 lo
|= cum
.num_reg_words
;
5932 #if HOST_BITS_PER_WIDE_INT == 32
5933 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5935 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5936 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5939 ciw
= immed_double_const (lo
, hi
, DImode
);
5941 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5942 UNSPEC_UMK_LOAD_CIW
);
5945 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5946 num_args
= cum
.num_reg_words
;
5947 if (MUST_PASS_IN_STACK (mode
, type
)
5948 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5950 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5954 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5955 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5957 /* The argument fits in two registers. Note that we still need to
5958 reserve a register for empty structures. */
5962 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5965 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5966 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5967 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5971 #elif TARGET_ABI_OSF
5977 /* VOID is passed as a special flag for "last argument". */
5978 if (type
== void_type_node
)
5980 else if (MUST_PASS_IN_STACK (mode
, type
))
5982 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5986 #error Unhandled ABI
5989 return gen_rtx_REG (mode
, num_args
+ basereg
);
5992 /* Return true if TYPE must be returned in memory, instead of in registers. */
5995 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
5997 enum machine_mode mode
= VOIDmode
;
6002 mode
= TYPE_MODE (type
);
6004 /* All aggregates are returned in memory. */
6005 if (AGGREGATE_TYPE_P (type
))
6009 size
= GET_MODE_SIZE (mode
);
6010 switch (GET_MODE_CLASS (mode
))
6012 case MODE_VECTOR_FLOAT
:
6013 /* Pass all float vectors in memory, like an aggregate. */
6016 case MODE_COMPLEX_FLOAT
:
6017 /* We judge complex floats on the size of their element,
6018 not the size of the whole type. */
6019 size
= GET_MODE_UNIT_SIZE (mode
);
6024 case MODE_COMPLEX_INT
:
6025 case MODE_VECTOR_INT
:
6029 /* ??? We get called on all sorts of random stuff from
6030 aggregate_value_p. We can't abort, but it's not clear
6031 what's safe to return. Pretend it's a struct I guess. */
6035 /* Otherwise types must fit in one register. */
6036 return size
> UNITS_PER_WORD
;
6039 /* Define how to find the value returned by a function. VALTYPE is the
6040 data type of the value (as a tree). If the precise function being
6041 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6042 MODE is set instead of VALTYPE for libcalls.
6044 On Alpha the value is found in $0 for integer functions and
6045 $f0 for floating-point functions. */
6048 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
6049 enum machine_mode mode
)
6051 unsigned int regnum
;
6052 enum mode_class
class;
6054 #ifdef ENABLE_CHECKING
6055 if (valtype
&& alpha_return_in_memory (valtype
, func
))
6060 mode
= TYPE_MODE (valtype
);
6062 class = GET_MODE_CLASS (mode
);
6066 /* Do the same thing as PROMOTE_MODE. */
6070 case MODE_COMPLEX_INT
:
6071 case MODE_VECTOR_INT
:
6079 case MODE_COMPLEX_FLOAT
:
6081 enum machine_mode cmode
= GET_MODE_INNER (mode
);
6083 return gen_rtx_PARALLEL
6086 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
6088 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
6089 GEN_INT (GET_MODE_SIZE (cmode
)))));
6096 return gen_rtx_REG (mode
, regnum
);
6100 alpha_build_va_list (void)
6102 tree base
, ofs
, record
, type_decl
;
6104 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6105 return ptr_type_node
;
6107 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6108 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6109 TREE_CHAIN (record
) = type_decl
;
6110 TYPE_NAME (record
) = type_decl
;
6112 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6114 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6116 DECL_FIELD_CONTEXT (ofs
) = record
;
6118 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6120 DECL_FIELD_CONTEXT (base
) = record
;
6121 TREE_CHAIN (base
) = ofs
;
6123 TYPE_FIELDS (record
) = base
;
6124 layout_type (record
);
6129 /* Perform any needed actions needed for a function that is receiving a
6130 variable number of arguments. */
6133 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
,
6134 enum machine_mode mode ATTRIBUTE_UNUSED
,
6135 tree type ATTRIBUTE_UNUSED
,
6136 int *pretend_size
, int no_rtl
)
6138 #if TARGET_ABI_UNICOSMK
6139 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6140 arguments on the stack. Unfortunately, it doesn't always store the first
6141 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6142 with stdargs as we always have at least one named argument there. */
6143 int num_reg_words
= pcum
->num_reg_words
;
6144 if (num_reg_words
< 6)
6148 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words
+ 1)));
6149 emit_insn (gen_arg_home_umk ());
6153 #elif TARGET_ABI_OPEN_VMS
6154 /* For VMS, we allocate space for all 6 arg registers plus a count.
6156 However, if NO registers need to be saved, don't allocate any space.
6157 This is not only because we won't need the space, but because AP
6158 includes the current_pretend_args_size and we don't want to mess up
6159 any ap-relative addresses already made. */
6160 if (pcum
->num_args
< 6)
6164 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6165 emit_insn (gen_arg_home ());
6167 *pretend_size
= 7 * UNITS_PER_WORD
;
6170 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6171 only push those that are remaining. However, if NO registers need to
6172 be saved, don't allocate any space. This is not only because we won't
6173 need the space, but because AP includes the current_pretend_args_size
6174 and we don't want to mess up any ap-relative addresses already made.
6176 If we are not to use the floating-point registers, save the integer
6177 registers where we would put the floating-point registers. This is
6178 not the most efficient way to implement varargs with just one register
6179 class, but it isn't worth doing anything more efficient in this rare
6181 CUMULATIVE_ARGS cum
= *pcum
;
6188 int set
= get_varargs_alias_set ();
6191 tmp
= gen_rtx_MEM (BLKmode
,
6192 plus_constant (virtual_incoming_args_rtx
,
6193 (cum
+ 6) * UNITS_PER_WORD
));
6194 set_mem_alias_set (tmp
, set
);
6195 move_block_from_reg (16 + cum
, tmp
, 6 - cum
);
6197 tmp
= gen_rtx_MEM (BLKmode
,
6198 plus_constant (virtual_incoming_args_rtx
,
6199 cum
* UNITS_PER_WORD
));
6200 set_mem_alias_set (tmp
, set
);
6201 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
6204 *pretend_size
= 12 * UNITS_PER_WORD
;
6209 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6211 HOST_WIDE_INT offset
;
6212 tree t
, offset_field
, base_field
;
6214 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6217 if (TARGET_ABI_UNICOSMK
)
6218 std_expand_builtin_va_start (valist
, nextarg
);
6220 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6221 up by 48, storing fp arg registers in the first 48 bytes, and the
6222 integer arg registers in the next 48 bytes. This is only done,
6223 however, if any integer registers need to be stored.
6225 If no integer registers need be stored, then we must subtract 48
6226 in order to account for the integer arg registers which are counted
6227 in argsize above, but which are not actually stored on the stack.
6228 Must further be careful here about structures straddling the last
6229 integer argument register; that futzes with pretend_args_size,
6230 which changes the meaning of AP. */
6233 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6235 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6237 if (TARGET_ABI_OPEN_VMS
)
6239 nextarg
= plus_constant (nextarg
, offset
);
6240 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6241 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6242 make_tree (ptr_type_node
, nextarg
));
6243 TREE_SIDE_EFFECTS (t
) = 1;
6245 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6249 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6250 offset_field
= TREE_CHAIN (base_field
);
6252 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6253 valist
, base_field
);
6254 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6255 valist
, offset_field
);
6257 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6258 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6259 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6260 TREE_SIDE_EFFECTS (t
) = 1;
6261 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6263 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6264 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6265 TREE_SIDE_EFFECTS (t
) = 1;
6266 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6271 alpha_va_arg (tree valist
, tree type
)
6274 tree t
, type_size
, rounded_size
;
6275 tree offset_field
, base_field
, addr_tree
, addend
;
6276 tree wide_type
, wide_ofs
;
6279 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6280 return std_expand_builtin_va_arg (valist
, type
);
6282 if (type
== error_mark_node
6283 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6284 || TREE_OVERFLOW (type_size
))
6285 rounded_size
= size_zero_node
;
6287 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6288 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6289 fold (build (PLUS_EXPR
, sizetype
,
6295 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6296 offset_field
= TREE_CHAIN (base_field
);
6298 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6299 valist
, base_field
);
6300 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6301 valist
, offset_field
);
6303 /* If the type could not be passed in registers, skip the block
6304 reserved for the registers. */
6305 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6307 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6308 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6309 offset_field
, build_int_2 (6*8, 0)));
6310 TREE_SIDE_EFFECTS (t
) = 1;
6311 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6314 wide_type
= make_signed_type (64);
6315 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6319 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6322 rounded_size
= size_int (UNITS_PER_WORD
);
6324 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
6326 rtx real_part
, imag_part
, value
, tmp
;
6328 real_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6329 imag_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6331 /* ??? Most irritatingly, we're not returning the value here,
6332 but the address. Since real_part and imag_part are not
6333 necessarily contiguous, we must copy to local storage. */
6335 real_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), real_part
);
6336 imag_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), imag_part
);
6337 value
= gen_rtx_CONCAT (TYPE_MODE (type
), real_part
, imag_part
);
6339 tmp
= assign_temp (type
, 0, 1, 0);
6340 emit_move_insn (tmp
, value
);
6342 return XEXP (tmp
, 0);
6344 else if (TREE_CODE (type
) == REAL_TYPE
)
6346 tree fpaddend
, cond
;
6348 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6349 addend
, build_int_2 (-6*8, 0)));
6351 cond
= fold (build (LT_EXPR
, integer_type_node
,
6352 wide_ofs
, build_int_2 (6*8, 0)));
6354 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6358 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6359 base_field
, addend
);
6361 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6362 addr
= copy_to_reg (addr
);
6364 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6365 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6366 offset_field
, rounded_size
));
6367 TREE_SIDE_EFFECTS (t
) = 1;
6368 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6372 addr
= force_reg (Pmode
, addr
);
6373 addr
= gen_rtx_MEM (Pmode
, addr
);
6383 ALPHA_BUILTIN_CMPBGE
,
6384 ALPHA_BUILTIN_EXTBL
,
6385 ALPHA_BUILTIN_EXTWL
,
6386 ALPHA_BUILTIN_EXTLL
,
6387 ALPHA_BUILTIN_EXTQL
,
6388 ALPHA_BUILTIN_EXTWH
,
6389 ALPHA_BUILTIN_EXTLH
,
6390 ALPHA_BUILTIN_EXTQH
,
6391 ALPHA_BUILTIN_INSBL
,
6392 ALPHA_BUILTIN_INSWL
,
6393 ALPHA_BUILTIN_INSLL
,
6394 ALPHA_BUILTIN_INSQL
,
6395 ALPHA_BUILTIN_INSWH
,
6396 ALPHA_BUILTIN_INSLH
,
6397 ALPHA_BUILTIN_INSQH
,
6398 ALPHA_BUILTIN_MSKBL
,
6399 ALPHA_BUILTIN_MSKWL
,
6400 ALPHA_BUILTIN_MSKLL
,
6401 ALPHA_BUILTIN_MSKQL
,
6402 ALPHA_BUILTIN_MSKWH
,
6403 ALPHA_BUILTIN_MSKLH
,
6404 ALPHA_BUILTIN_MSKQH
,
6405 ALPHA_BUILTIN_UMULH
,
6407 ALPHA_BUILTIN_ZAPNOT
,
6408 ALPHA_BUILTIN_AMASK
,
6409 ALPHA_BUILTIN_IMPLVER
,
6411 ALPHA_BUILTIN_THREAD_POINTER
,
6412 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6415 ALPHA_BUILTIN_MINUB8
,
6416 ALPHA_BUILTIN_MINSB8
,
6417 ALPHA_BUILTIN_MINUW4
,
6418 ALPHA_BUILTIN_MINSW4
,
6419 ALPHA_BUILTIN_MAXUB8
,
6420 ALPHA_BUILTIN_MAXSB8
,
6421 ALPHA_BUILTIN_MAXUW4
,
6422 ALPHA_BUILTIN_MAXSW4
,
6426 ALPHA_BUILTIN_UNPKBL
,
6427 ALPHA_BUILTIN_UNPKBW
,
6432 ALPHA_BUILTIN_CTPOP
,
6437 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6438 CODE_FOR_builtin_cmpbge
,
6439 CODE_FOR_builtin_extbl
,
6440 CODE_FOR_builtin_extwl
,
6441 CODE_FOR_builtin_extll
,
6442 CODE_FOR_builtin_extql
,
6443 CODE_FOR_builtin_extwh
,
6444 CODE_FOR_builtin_extlh
,
6445 CODE_FOR_builtin_extqh
,
6446 CODE_FOR_builtin_insbl
,
6447 CODE_FOR_builtin_inswl
,
6448 CODE_FOR_builtin_insll
,
6449 CODE_FOR_builtin_insql
,
6450 CODE_FOR_builtin_inswh
,
6451 CODE_FOR_builtin_inslh
,
6452 CODE_FOR_builtin_insqh
,
6453 CODE_FOR_builtin_mskbl
,
6454 CODE_FOR_builtin_mskwl
,
6455 CODE_FOR_builtin_mskll
,
6456 CODE_FOR_builtin_mskql
,
6457 CODE_FOR_builtin_mskwh
,
6458 CODE_FOR_builtin_msklh
,
6459 CODE_FOR_builtin_mskqh
,
6460 CODE_FOR_umuldi3_highpart
,
6461 CODE_FOR_builtin_zap
,
6462 CODE_FOR_builtin_zapnot
,
6463 CODE_FOR_builtin_amask
,
6464 CODE_FOR_builtin_implver
,
6465 CODE_FOR_builtin_rpcc
,
6470 CODE_FOR_builtin_minub8
,
6471 CODE_FOR_builtin_minsb8
,
6472 CODE_FOR_builtin_minuw4
,
6473 CODE_FOR_builtin_minsw4
,
6474 CODE_FOR_builtin_maxub8
,
6475 CODE_FOR_builtin_maxsb8
,
6476 CODE_FOR_builtin_maxuw4
,
6477 CODE_FOR_builtin_maxsw4
,
6478 CODE_FOR_builtin_perr
,
6479 CODE_FOR_builtin_pklb
,
6480 CODE_FOR_builtin_pkwb
,
6481 CODE_FOR_builtin_unpkbl
,
6482 CODE_FOR_builtin_unpkbw
,
6485 CODE_FOR_builtin_cttz
,
6486 CODE_FOR_builtin_ctlz
,
6487 CODE_FOR_builtin_ctpop
6490 struct alpha_builtin_def
6493 enum alpha_builtin code
;
6494 unsigned int target_mask
;
6497 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6498 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6499 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6502 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6503 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6504 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6505 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6506 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6507 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6508 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6509 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6510 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6513 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6514 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6515 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6516 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6517 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6518 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6519 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6520 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6521 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6522 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6523 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6524 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6525 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6526 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6527 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6528 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6529 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6530 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6531 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6532 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6533 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6534 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6535 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6536 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6537 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6538 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6539 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6540 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6541 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6542 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6543 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6544 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6545 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6546 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6547 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6551 alpha_init_builtins (void)
6553 const struct alpha_builtin_def
*p
;
6557 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6559 p
= zero_arg_builtins
;
6560 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6561 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6562 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6565 ftype
= build_function_type_list (long_integer_type_node
,
6566 long_integer_type_node
, NULL_TREE
);
6568 p
= one_arg_builtins
;
6569 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6570 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6571 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6574 ftype
= build_function_type_list (long_integer_type_node
,
6575 long_integer_type_node
,
6576 long_integer_type_node
, NULL_TREE
);
6578 p
= two_arg_builtins
;
6579 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6580 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6581 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6584 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6585 builtin_function ("__builtin_thread_pointer", ftype
,
6586 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6589 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6590 builtin_function ("__builtin_set_thread_pointer", ftype
,
6591 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6595 /* Expand an expression EXP that calls a built-in function,
6596 with result going to TARGET if that's convenient
6597 (and in mode MODE if that's convenient).
6598 SUBTARGET may be used as the target for computing one of EXP's operands.
6599 IGNORE is nonzero if the value is to be ignored. */
6602 alpha_expand_builtin (tree exp
, rtx target
,
6603 rtx subtarget ATTRIBUTE_UNUSED
,
6604 enum machine_mode mode ATTRIBUTE_UNUSED
,
6605 int ignore ATTRIBUTE_UNUSED
)
6609 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6610 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6611 tree arglist
= TREE_OPERAND (exp
, 1);
6612 enum insn_code icode
;
6613 rtx op
[MAX_ARGS
], pat
;
6617 if (fcode
>= ALPHA_BUILTIN_max
)
6618 internal_error ("bad builtin fcode");
6619 icode
= code_for_builtin
[fcode
];
6621 internal_error ("bad builtin fcode");
6623 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6625 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6627 arglist
= TREE_CHAIN (arglist
), arity
++)
6629 const struct insn_operand_data
*insn_op
;
6631 tree arg
= TREE_VALUE (arglist
);
6632 if (arg
== error_mark_node
)
6634 if (arity
> MAX_ARGS
)
6637 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6639 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6641 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6642 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6647 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6649 || GET_MODE (target
) != tmode
6650 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6651 target
= gen_reg_rtx (tmode
);
6657 pat
= GEN_FCN (icode
) (target
);
6661 pat
= GEN_FCN (icode
) (target
, op
[0]);
6663 pat
= GEN_FCN (icode
) (op
[0]);
6666 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6681 /* This page contains routines that are used to determine what the function
6682 prologue and epilogue code will do and write them out. */
6684 /* Compute the size of the save area in the stack. */
6686 /* These variables are used for communication between the following functions.
6687 They indicate various things about the current function being compiled
6688 that are used to tell what kind of prologue, epilogue and procedure
6689 descriptior to generate. */
6691 /* Nonzero if we need a stack procedure. */
6692 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6693 static enum alpha_procedure_types alpha_procedure_type
;
6695 /* Register number (either FP or SP) that is used to unwind the frame. */
6696 static int vms_unwind_regno
;
6698 /* Register number used to save FP. We need not have one for RA since
6699 we don't modify it for register procedures. This is only defined
6700 for register frame procedures. */
6701 static int vms_save_fp_regno
;
6703 /* Register number used to reference objects off our PV. */
6704 static int vms_base_regno
;
6706 /* Compute register masks for saved registers. */
6709 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
6711 unsigned long imask
= 0;
6712 unsigned long fmask
= 0;
6715 /* Irritatingly, there are two kinds of thunks -- those created with
6716 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6717 through the regular part of the compiler. In the
6718 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6719 info, but assemble_start_function wants to output .frame and
6720 .mask directives. */
6721 if (current_function_is_thunk
&& !no_new_pseudos
)
6728 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6729 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6731 /* One for every register we have to save. */
6732 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6733 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6734 && regs_ever_live
[i
] && i
!= REG_RA
6735 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6738 imask
|= (1UL << i
);
6740 fmask
|= (1UL << (i
- 32));
6743 /* We need to restore these for the handler. */
6744 if (current_function_calls_eh_return
)
6748 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6749 if (regno
== INVALID_REGNUM
)
6751 imask
|= 1UL << regno
;
6754 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6755 avoid hackery in unwind-dw2.c, we need to actively store a
6756 zero in the prologue of _Unwind_RaiseException et al. */
6760 /* If any register spilled, then spill the return address also. */
6761 /* ??? This is required by the Digital stack unwind specification
6762 and isn't needed if we're doing Dwarf2 unwinding. */
6763 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6764 imask
|= (1UL << REG_RA
);
6771 alpha_sa_size (void)
6773 unsigned long mask
[2];
6777 alpha_sa_mask (&mask
[0], &mask
[1]);
6779 if (TARGET_ABI_UNICOSMK
)
6781 if (mask
[0] || mask
[1])
6786 for (j
= 0; j
< 2; ++j
)
6787 for (i
= 0; i
< 32; ++i
)
6788 if ((mask
[j
] >> i
) & 1)
6792 if (TARGET_ABI_UNICOSMK
)
6794 /* We might not need to generate a frame if we don't make any calls
6795 (including calls to __T3E_MISMATCH if this is a vararg function),
6796 don't have any local variables which require stack slots, don't
6797 use alloca and have not determined that we need a frame for other
6800 alpha_procedure_type
6801 = (sa_size
|| get_frame_size() != 0
6802 || current_function_outgoing_args_size
6803 || current_function_stdarg
|| current_function_calls_alloca
6804 || frame_pointer_needed
)
6805 ? PT_STACK
: PT_REGISTER
;
6807 /* Always reserve space for saving callee-saved registers if we
6808 need a frame as required by the calling convention. */
6809 if (alpha_procedure_type
== PT_STACK
)
6812 else if (TARGET_ABI_OPEN_VMS
)
6814 /* Start by assuming we can use a register procedure if we don't
6815 make any calls (REG_RA not used) or need to save any
6816 registers and a stack procedure if we do. */
6817 if ((mask
[0] >> REG_RA
) & 1)
6818 alpha_procedure_type
= PT_STACK
;
6819 else if (get_frame_size() != 0)
6820 alpha_procedure_type
= PT_REGISTER
;
6822 alpha_procedure_type
= PT_NULL
;
6824 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6825 made the final decision on stack procedure vs register procedure. */
6826 if (alpha_procedure_type
== PT_STACK
)
6829 /* Decide whether to refer to objects off our PV via FP or PV.
6830 If we need FP for something else or if we receive a nonlocal
6831 goto (which expects PV to contain the value), we must use PV.
6832 Otherwise, start by assuming we can use FP. */
6835 = (frame_pointer_needed
6836 || current_function_has_nonlocal_label
6837 || alpha_procedure_type
== PT_STACK
6838 || current_function_outgoing_args_size
)
6839 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6841 /* If we want to copy PV into FP, we need to find some register
6842 in which to save FP. */
6844 vms_save_fp_regno
= -1;
6845 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6846 for (i
= 0; i
< 32; i
++)
6847 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6848 vms_save_fp_regno
= i
;
6850 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6851 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6852 else if (alpha_procedure_type
== PT_NULL
)
6853 vms_base_regno
= REG_PV
;
6855 /* Stack unwinding should be done via FP unless we use it for PV. */
6856 vms_unwind_regno
= (vms_base_regno
== REG_PV
6857 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6859 /* If this is a stack procedure, allow space for saving FP and RA. */
6860 if (alpha_procedure_type
== PT_STACK
)
6865 /* Our size must be even (multiple of 16 bytes). */
6873 /* Define the offset between two registers, one to be eliminated,
6874 and the other its replacement, at the start of a routine. */
6877 alpha_initial_elimination_offset (unsigned int from
,
6878 unsigned int to ATTRIBUTE_UNUSED
)
6882 ret
= alpha_sa_size ();
6883 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
6885 if (from
== FRAME_POINTER_REGNUM
)
6887 else if (from
== ARG_POINTER_REGNUM
)
6888 ret
+= (ALPHA_ROUND (get_frame_size ()
6889 + current_function_pretend_args_size
)
6890 - current_function_pretend_args_size
);
6898 alpha_pv_save_size (void)
6901 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6905 alpha_using_fp (void)
6908 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6911 #if TARGET_ABI_OPEN_VMS
6913 const struct attribute_spec vms_attribute_table
[] =
6915 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6916 { "overlaid", 0, 0, true, false, false, NULL
},
6917 { "global", 0, 0, true, false, false, NULL
},
6918 { "initialize", 0, 0, true, false, false, NULL
},
6919 { NULL
, 0, 0, false, false, false, NULL
}
6925 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6927 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
6931 alpha_find_lo_sum_using_gp (rtx insn
)
6933 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
6937 alpha_does_function_need_gp (void)
6941 /* The GP being variable is an OSF abi thing. */
6942 if (! TARGET_ABI_OSF
)
6945 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6948 if (current_function_is_thunk
)
6951 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6952 Even if we are a static function, we still need to do this in case
6953 our address is taken and passed to something like qsort. */
6955 push_topmost_sequence ();
6956 insn
= get_insns ();
6957 pop_topmost_sequence ();
6959 for (; insn
; insn
= NEXT_INSN (insn
))
6961 && GET_CODE (PATTERN (insn
)) != USE
6962 && GET_CODE (PATTERN (insn
)) != CLOBBER
6963 && get_attr_usegp (insn
))
6970 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6974 set_frame_related_p (void)
6976 rtx seq
= get_insns ();
6987 while (insn
!= NULL_RTX
)
6989 RTX_FRAME_RELATED_P (insn
) = 1;
6990 insn
= NEXT_INSN (insn
);
6992 seq
= emit_insn (seq
);
6996 seq
= emit_insn (seq
);
6997 RTX_FRAME_RELATED_P (seq
) = 1;
7002 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7004 /* Write function prologue. */
7006 /* On vms we have two kinds of functions:
7008 - stack frame (PROC_STACK)
7009 these are 'normal' functions with local vars and which are
7010 calling other functions
7011 - register frame (PROC_REGISTER)
7012 keeps all data in registers, needs no stack
7014 We must pass this to the assembler so it can generate the
7015 proper pdsc (procedure descriptor)
7016 This is done with the '.pdesc' command.
7018 On not-vms, we don't really differentiate between the two, as we can
7019 simply allocate stack without saving registers. */
7022 alpha_expand_prologue (void)
7024 /* Registers to save. */
7025 unsigned long imask
= 0;
7026 unsigned long fmask
= 0;
7027 /* Stack space needed for pushing registers clobbered by us. */
7028 HOST_WIDE_INT sa_size
;
7029 /* Complete stack size needed. */
7030 HOST_WIDE_INT frame_size
;
7031 /* Offset from base reg to register save area. */
7032 HOST_WIDE_INT reg_offset
;
7036 sa_size
= alpha_sa_size ();
7038 frame_size
= get_frame_size ();
7039 if (TARGET_ABI_OPEN_VMS
)
7040 frame_size
= ALPHA_ROUND (sa_size
7041 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7043 + current_function_pretend_args_size
);
7044 else if (TARGET_ABI_UNICOSMK
)
7045 /* We have to allocate space for the DSIB if we generate a frame. */
7046 frame_size
= ALPHA_ROUND (sa_size
7047 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7048 + ALPHA_ROUND (frame_size
7049 + current_function_outgoing_args_size
);
7051 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7053 + ALPHA_ROUND (frame_size
7054 + current_function_pretend_args_size
));
7056 if (TARGET_ABI_OPEN_VMS
)
7059 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7061 alpha_sa_mask (&imask
, &fmask
);
7063 /* Emit an insn to reload GP, if needed. */
7066 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7067 if (alpha_function_needs_gp
)
7068 emit_insn (gen_prologue_ldgp ());
7071 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7072 the call to mcount ourselves, rather than having the linker do it
7073 magically in response to -pg. Since _mcount has special linkage,
7074 don't represent the call as a call. */
7075 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7076 emit_insn (gen_prologue_mcount ());
7078 if (TARGET_ABI_UNICOSMK
)
7079 unicosmk_gen_dsib (&imask
);
7081 /* Adjust the stack by the frame size. If the frame size is > 4096
7082 bytes, we need to be sure we probe somewhere in the first and last
7083 4096 bytes (we can probably get away without the latter test) and
7084 every 8192 bytes in between. If the frame size is > 32768, we
7085 do this in a loop. Otherwise, we generate the explicit probe
7088 Note that we are only allowed to adjust sp once in the prologue. */
7090 if (frame_size
<= 32768)
7092 if (frame_size
> 4096)
7097 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7100 while ((probed
+= 8192) < frame_size
);
7102 /* We only have to do this probe if we aren't saving registers. */
7103 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7104 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7107 if (frame_size
!= 0)
7108 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7109 GEN_INT (TARGET_ABI_UNICOSMK
7115 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7116 number of 8192 byte blocks to probe. We then probe each block
7117 in the loop and then set SP to the proper location. If the
7118 amount remaining is > 4096, we have to do one more probe if we
7119 are not saving any registers. */
7121 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7122 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7123 rtx ptr
= gen_rtx_REG (DImode
, 22);
7124 rtx count
= gen_rtx_REG (DImode
, 23);
7127 emit_move_insn (count
, GEN_INT (blocks
));
7128 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7129 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7131 /* Because of the difficulty in emitting a new basic block this
7132 late in the compilation, generate the loop as a single insn. */
7133 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7135 if (leftover
> 4096 && sa_size
== 0)
7137 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7138 MEM_VOLATILE_P (last
) = 1;
7139 emit_move_insn (last
, const0_rtx
);
7142 if (TARGET_ABI_WINDOWS_NT
)
7144 /* For NT stack unwind (done by 'reverse execution'), it's
7145 not OK to take the result of a loop, even though the value
7146 is already in ptr, so we reload it via a single operation
7147 and subtract it to sp.
7149 Yes, that's correct -- we have to reload the whole constant
7150 into a temporary via ldah+lda then subtract from sp. To
7151 ensure we get ldah+lda, we use a special pattern. */
7153 HOST_WIDE_INT lo
, hi
;
7154 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7155 hi
= frame_size
- lo
;
7157 emit_move_insn (ptr
, GEN_INT (hi
));
7158 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7159 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7164 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7165 GEN_INT (-leftover
)));
7168 /* This alternative is special, because the DWARF code cannot
7169 possibly intuit through the loop above. So we invent this
7170 note it looks at instead. */
7171 RTX_FRAME_RELATED_P (seq
) = 1;
7173 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7174 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7175 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7176 GEN_INT (TARGET_ABI_UNICOSMK
7182 if (!TARGET_ABI_UNICOSMK
)
7184 /* Cope with very large offsets to the register save area. */
7185 sa_reg
= stack_pointer_rtx
;
7186 if (reg_offset
+ sa_size
> 0x8000)
7188 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7191 if (low
+ sa_size
<= 0x8000)
7192 bias
= reg_offset
- low
, reg_offset
= low
;
7194 bias
= reg_offset
, reg_offset
= 0;
7196 sa_reg
= gen_rtx_REG (DImode
, 24);
7197 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7201 /* Save regs in stack order. Beginning with VMS PV. */
7202 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7204 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7205 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7206 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7209 /* Save register RA next. */
7210 if (imask
& (1UL << REG_RA
))
7212 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7213 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7214 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7215 imask
&= ~(1UL << REG_RA
);
7219 /* Now save any other registers required to be saved. */
7220 for (i
= 0; i
< 31; i
++)
7221 if (imask
& (1UL << i
))
7223 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7224 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7225 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7229 /* Store a zero if requested for unwinding. */
7230 if (imask
& (1UL << 31))
7234 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7235 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7236 insn
= emit_move_insn (mem
, const0_rtx
);
7238 RTX_FRAME_RELATED_P (insn
) = 1;
7239 t
= gen_rtx_REG (Pmode
, 31);
7240 t
= gen_rtx_SET (VOIDmode
, mem
, t
);
7241 t
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, t
, REG_NOTES (insn
));
7242 REG_NOTES (insn
) = t
;
7247 for (i
= 0; i
< 31; i
++)
7248 if (fmask
& (1UL << i
))
7250 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7251 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7252 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7256 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7258 /* The standard frame on the T3E includes space for saving registers.
7259 We just have to use it. We don't have to save the return address and
7260 the old frame pointer here - they are saved in the DSIB. */
7263 for (i
= 9; i
< 15; i
++)
7264 if (imask
& (1UL << i
))
7266 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7268 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7269 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7272 for (i
= 2; i
< 10; i
++)
7273 if (fmask
& (1UL << i
))
7275 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7277 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7278 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7283 if (TARGET_ABI_OPEN_VMS
)
7285 if (alpha_procedure_type
== PT_REGISTER
)
7286 /* Register frame procedures save the fp.
7287 ?? Ought to have a dwarf2 save for this. */
7288 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7289 hard_frame_pointer_rtx
);
7291 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7292 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7293 gen_rtx_REG (DImode
, REG_PV
)));
7295 if (alpha_procedure_type
!= PT_NULL
7296 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7297 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7299 /* If we have to allocate space for outgoing args, do it now. */
7300 if (current_function_outgoing_args_size
!= 0)
7303 = emit_move_insn (stack_pointer_rtx
,
7305 (hard_frame_pointer_rtx
,
7307 (current_function_outgoing_args_size
))));
7309 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7310 if ! frame_pointer_needed. Setting the bit will change the CFA
7311 computation rule to use sp again, which would be wrong if we had
7312 frame_pointer_needed, as this means sp might move unpredictably
7316 frame_pointer_needed
7317 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7319 current_function_outgoing_args_size != 0
7320 => alpha_procedure_type != PT_NULL,
7322 so when we are not setting the bit here, we are guaranteed to
7323 have emitted an FRP frame pointer update just before. */
7324 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7327 else if (!TARGET_ABI_UNICOSMK
)
7329 /* If we need a frame pointer, set it from the stack pointer. */
7330 if (frame_pointer_needed
)
7332 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7333 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7335 /* This must always be the last instruction in the
7336 prologue, thus we emit a special move + clobber. */
7337 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7338 stack_pointer_rtx
, sa_reg
)));
7342 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7343 the prologue, for exception handling reasons, we cannot do this for
7344 any insn that might fault. We could prevent this for mems with a
7345 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7346 have to prevent all such scheduling with a blockage.
7348 Linux, on the other hand, never bothered to implement OSF/1's
7349 exception handling, and so doesn't care about such things. Anyone
7350 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7352 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7353 emit_insn (gen_blockage ());
7356 /* Output the textual info surrounding the prologue. */
7359 alpha_start_function (FILE *file
, const char *fnname
,
7360 tree decl ATTRIBUTE_UNUSED
)
7362 unsigned long imask
= 0;
7363 unsigned long fmask
= 0;
7364 /* Stack space needed for pushing registers clobbered by us. */
7365 HOST_WIDE_INT sa_size
;
7366 /* Complete stack size needed. */
7367 unsigned HOST_WIDE_INT frame_size
;
7368 /* Offset from base reg to register save area. */
7369 HOST_WIDE_INT reg_offset
;
7370 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7373 /* Don't emit an extern directive for functions defined in the same file. */
7374 if (TARGET_ABI_UNICOSMK
)
7377 name_tree
= get_identifier (fnname
);
7378 TREE_ASM_WRITTEN (name_tree
) = 1;
7381 alpha_fnname
= fnname
;
7382 sa_size
= alpha_sa_size ();
7384 frame_size
= get_frame_size ();
7385 if (TARGET_ABI_OPEN_VMS
)
7386 frame_size
= ALPHA_ROUND (sa_size
7387 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7389 + current_function_pretend_args_size
);
7390 else if (TARGET_ABI_UNICOSMK
)
7391 frame_size
= ALPHA_ROUND (sa_size
7392 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7393 + ALPHA_ROUND (frame_size
7394 + current_function_outgoing_args_size
);
7396 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7398 + ALPHA_ROUND (frame_size
7399 + current_function_pretend_args_size
));
7401 if (TARGET_ABI_OPEN_VMS
)
7404 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7406 alpha_sa_mask (&imask
, &fmask
);
7408 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7409 We have to do that before the .ent directive as we cannot switch
7410 files within procedures with native ecoff because line numbers are
7411 linked to procedure descriptors.
7412 Outputting the lineno helps debugging of one line functions as they
7413 would otherwise get no line number at all. Please note that we would
7414 like to put out last_linenum from final.c, but it is not accessible. */
7416 if (write_symbols
== SDB_DEBUG
)
7418 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7419 ASM_OUTPUT_SOURCE_FILENAME (file
,
7420 DECL_SOURCE_FILE (current_function_decl
));
7422 #ifdef ASM_OUTPUT_SOURCE_LINE
7423 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7424 ASM_OUTPUT_SOURCE_LINE (file
,
7425 DECL_SOURCE_LINE (current_function_decl
), 0);
7429 /* Issue function start and label. */
7430 if (TARGET_ABI_OPEN_VMS
7431 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7433 fputs ("\t.ent ", file
);
7434 assemble_name (file
, fnname
);
7437 /* If the function needs GP, we'll write the "..ng" label there.
7438 Otherwise, do it here. */
7440 && ! alpha_function_needs_gp
7441 && ! current_function_is_thunk
)
7444 assemble_name (file
, fnname
);
7445 fputs ("..ng:\n", file
);
7449 strcpy (entry_label
, fnname
);
7450 if (TARGET_ABI_OPEN_VMS
)
7451 strcat (entry_label
, "..en");
7453 /* For public functions, the label must be globalized by appending an
7454 additional colon. */
7455 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7456 strcat (entry_label
, ":");
7458 ASM_OUTPUT_LABEL (file
, entry_label
);
7459 inside_function
= TRUE
;
7461 if (TARGET_ABI_OPEN_VMS
)
7462 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7464 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7465 && !flag_inhibit_size_directive
)
7467 /* Set flags in procedure descriptor to request IEEE-conformant
7468 math-library routines. The value we set it to is PDSC_EXC_IEEE
7469 (/usr/include/pdsc.h). */
7470 fputs ("\t.eflag 48\n", file
);
7473 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7474 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7475 alpha_arg_offset
= -frame_size
+ 48;
7477 /* Describe our frame. If the frame size is larger than an integer,
7478 print it as zero to avoid an assembler error. We won't be
7479 properly describing such a frame, but that's the best we can do. */
7480 if (TARGET_ABI_UNICOSMK
)
7482 else if (TARGET_ABI_OPEN_VMS
)
7483 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7484 HOST_WIDE_INT_PRINT_DEC
"\n",
7486 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7488 else if (!flag_inhibit_size_directive
)
7489 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7490 (frame_pointer_needed
7491 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7492 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7493 current_function_pretend_args_size
);
7495 /* Describe which registers were spilled. */
7496 if (TARGET_ABI_UNICOSMK
)
7498 else if (TARGET_ABI_OPEN_VMS
)
7501 /* ??? Does VMS care if mask contains ra? The old code didn't
7502 set it, so I don't here. */
7503 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7505 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7506 if (alpha_procedure_type
== PT_REGISTER
)
7507 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7509 else if (!flag_inhibit_size_directive
)
7513 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7514 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7516 for (i
= 0; i
< 32; ++i
)
7517 if (imask
& (1UL << i
))
7522 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7523 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7526 #if TARGET_ABI_OPEN_VMS
7527 /* Ifdef'ed cause link_section are only available then. */
7528 readonly_data_section ();
7529 fprintf (file
, "\t.align 3\n");
7530 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7531 fputs ("\t.ascii \"", file
);
7532 assemble_name (file
, fnname
);
7533 fputs ("\\0\"\n", file
);
7534 alpha_need_linkage (fnname
, 1);
7539 /* Emit the .prologue note at the scheduled end of the prologue. */
7542 alpha_output_function_end_prologue (FILE *file
)
7544 if (TARGET_ABI_UNICOSMK
)
7546 else if (TARGET_ABI_OPEN_VMS
)
7547 fputs ("\t.prologue\n", file
);
7548 else if (TARGET_ABI_WINDOWS_NT
)
7549 fputs ("\t.prologue 0\n", file
);
7550 else if (!flag_inhibit_size_directive
)
7551 fprintf (file
, "\t.prologue %d\n",
7552 alpha_function_needs_gp
|| current_function_is_thunk
);
7555 /* Write function epilogue. */
7557 /* ??? At some point we will want to support full unwind, and so will
7558 need to mark the epilogue as well. At the moment, we just confuse
7561 #define FRP(exp) exp
7564 alpha_expand_epilogue (void)
7566 /* Registers to save. */
7567 unsigned long imask
= 0;
7568 unsigned long fmask
= 0;
7569 /* Stack space needed for pushing registers clobbered by us. */
7570 HOST_WIDE_INT sa_size
;
7571 /* Complete stack size needed. */
7572 HOST_WIDE_INT frame_size
;
7573 /* Offset from base reg to register save area. */
7574 HOST_WIDE_INT reg_offset
;
7575 int fp_is_frame_pointer
, fp_offset
;
7576 rtx sa_reg
, sa_reg_exp
= NULL
;
7577 rtx sp_adj1
, sp_adj2
, mem
;
7581 sa_size
= alpha_sa_size ();
7583 frame_size
= get_frame_size ();
7584 if (TARGET_ABI_OPEN_VMS
)
7585 frame_size
= ALPHA_ROUND (sa_size
7586 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7588 + current_function_pretend_args_size
);
7589 else if (TARGET_ABI_UNICOSMK
)
7590 frame_size
= ALPHA_ROUND (sa_size
7591 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7592 + ALPHA_ROUND (frame_size
7593 + current_function_outgoing_args_size
);
7595 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7597 + ALPHA_ROUND (frame_size
7598 + current_function_pretend_args_size
));
7600 if (TARGET_ABI_OPEN_VMS
)
7602 if (alpha_procedure_type
== PT_STACK
)
7608 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7610 alpha_sa_mask (&imask
, &fmask
);
7613 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7614 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7616 sa_reg
= stack_pointer_rtx
;
7618 if (current_function_calls_eh_return
)
7619 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7623 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7625 /* If we have a frame pointer, restore SP from it. */
7626 if ((TARGET_ABI_OPEN_VMS
7627 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7628 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7629 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7631 /* Cope with very large offsets to the register save area. */
7632 if (reg_offset
+ sa_size
> 0x8000)
7634 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7637 if (low
+ sa_size
<= 0x8000)
7638 bias
= reg_offset
- low
, reg_offset
= low
;
7640 bias
= reg_offset
, reg_offset
= 0;
7642 sa_reg
= gen_rtx_REG (DImode
, 22);
7643 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7645 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7648 /* Restore registers in order, excepting a true frame pointer. */
7650 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7652 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7653 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7656 imask
&= ~(1UL << REG_RA
);
7658 for (i
= 0; i
< 31; ++i
)
7659 if (imask
& (1UL << i
))
7661 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7662 fp_offset
= reg_offset
;
7665 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7666 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7667 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7672 if (imask
& (1UL << 31))
7675 for (i
= 0; i
< 31; ++i
)
7676 if (fmask
& (1UL << i
))
7678 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7679 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7680 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7684 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7686 /* Restore callee-saved general-purpose registers. */
7690 for (i
= 9; i
< 15; i
++)
7691 if (imask
& (1UL << i
))
7693 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7695 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7696 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7700 for (i
= 2; i
< 10; i
++)
7701 if (fmask
& (1UL << i
))
7703 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7705 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7706 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7710 /* Restore the return address from the DSIB. */
7712 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7713 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7714 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7717 if (frame_size
|| eh_ofs
)
7719 sp_adj1
= stack_pointer_rtx
;
7723 sp_adj1
= gen_rtx_REG (DImode
, 23);
7724 emit_move_insn (sp_adj1
,
7725 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7728 /* If the stack size is large, begin computation into a temporary
7729 register so as not to interfere with a potential fp restore,
7730 which must be consecutive with an SP restore. */
7731 if (frame_size
< 32768
7732 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7733 sp_adj2
= GEN_INT (frame_size
);
7734 else if (TARGET_ABI_UNICOSMK
)
7736 sp_adj1
= gen_rtx_REG (DImode
, 23);
7737 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7738 sp_adj2
= const0_rtx
;
7740 else if (frame_size
< 0x40007fffL
)
7742 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7744 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7745 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7749 sp_adj1
= gen_rtx_REG (DImode
, 23);
7750 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7752 sp_adj2
= GEN_INT (low
);
7756 rtx tmp
= gen_rtx_REG (DImode
, 23);
7757 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7760 /* We can't drop new things to memory this late, afaik,
7761 so build it up by pieces. */
7762 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7763 -(frame_size
< 0)));
7769 /* From now on, things must be in order. So emit blockages. */
7771 /* Restore the frame pointer. */
7772 if (TARGET_ABI_UNICOSMK
)
7774 emit_insn (gen_blockage ());
7775 mem
= gen_rtx_MEM (DImode
,
7776 plus_constant (hard_frame_pointer_rtx
, -16));
7777 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7778 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7780 else if (fp_is_frame_pointer
)
7782 emit_insn (gen_blockage ());
7783 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7784 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7785 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7787 else if (TARGET_ABI_OPEN_VMS
)
7789 emit_insn (gen_blockage ());
7790 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7791 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7794 /* Restore the stack pointer. */
7795 emit_insn (gen_blockage ());
7796 if (sp_adj2
== const0_rtx
)
7797 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7799 FRP (emit_move_insn (stack_pointer_rtx
,
7800 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7804 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7806 emit_insn (gen_blockage ());
7807 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7808 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7810 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7812 /* Decrement the frame pointer if the function does not have a
7815 emit_insn (gen_blockage ());
7816 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7817 hard_frame_pointer_rtx
, GEN_INT (-1))));
7822 /* Output the rest of the textual info surrounding the epilogue. */
7825 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
7827 /* End the function. */
7828 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7830 fputs ("\t.end ", file
);
7831 assemble_name (file
, fnname
);
7834 inside_function
= FALSE
;
7836 #if TARGET_ABI_OPEN_VMS
7837 alpha_write_linkage (file
, fnname
, decl
);
7840 /* Output jump tables and the static subroutine information block. */
7841 if (TARGET_ABI_UNICOSMK
)
7843 unicosmk_output_ssib (file
, fnname
);
7844 unicosmk_output_deferred_case_vectors (file
);
7849 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7851 In order to avoid the hordes of differences between generated code
7852 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7853 lots of code loading up large constants, generate rtl and emit it
7854 instead of going straight to text.
7856 Not sure why this idea hasn't been explored before... */
7859 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7860 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
7863 HOST_WIDE_INT hi
, lo
;
7864 rtx
this, insn
, funexp
;
7866 /* We always require a valid GP. */
7867 emit_insn (gen_prologue_ldgp ());
7868 emit_note (NOTE_INSN_PROLOGUE_END
);
7870 /* Find the "this" pointer. If the function returns a structure,
7871 the structure return pointer is in $16. */
7872 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7873 this = gen_rtx_REG (Pmode
, 17);
7875 this = gen_rtx_REG (Pmode
, 16);
7877 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7878 entire constant for the add. */
7879 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7880 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7881 if (hi
+ lo
== delta
)
7884 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7886 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7890 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7891 delta
, -(delta
< 0));
7892 emit_insn (gen_adddi3 (this, this, tmp
));
7895 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7900 tmp
= gen_rtx_REG (Pmode
, 0);
7901 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
7903 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
7904 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7905 if (hi
+ lo
== vcall_offset
)
7908 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
7912 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
7913 vcall_offset
, -(vcall_offset
< 0));
7914 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
7918 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
7921 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
7923 emit_insn (gen_adddi3 (this, this, tmp
));
7926 /* Generate a tail call to the target function. */
7927 if (! TREE_USED (function
))
7929 assemble_external (function
);
7930 TREE_USED (function
) = 1;
7932 funexp
= XEXP (DECL_RTL (function
), 0);
7933 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7934 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7935 SIBLING_CALL_P (insn
) = 1;
7937 /* Run just enough of rest_of_compilation to get the insns emitted.
7938 There's not really enough bulk here to make other passes such as
7939 instruction scheduling worth while. Note that use_thunk calls
7940 assemble_start_function and assemble_end_function. */
7941 insn
= get_insns ();
7942 insn_locators_initialize ();
7943 shorten_branches (insn
);
7944 final_start_function (insn
, file
, 1);
7945 final (insn
, file
, 1, 0);
7946 final_end_function ();
7948 #endif /* TARGET_ABI_OSF */
7950 /* Debugging support. */
7954 /* Count the number of sdb related labels are generated (to find block
7955 start and end boundaries). */
7957 int sdb_label_count
= 0;
7959 /* Next label # for each statement. */
7961 static int sym_lineno
= 0;
7963 /* Count the number of .file directives, so that .loc is up to date. */
7965 static int num_source_filenames
= 0;
7967 /* Name of the file containing the current function. */
7969 static const char *current_function_file
= "";
7971 /* Offsets to alpha virtual arg/local debugging pointers. */
7973 long alpha_arg_offset
;
7974 long alpha_auto_offset
;
7976 /* Emit a new filename to a stream. */
7979 alpha_output_filename (FILE *stream
, const char *name
)
7981 static int first_time
= TRUE
;
7982 char ltext_label_name
[100];
7987 ++num_source_filenames
;
7988 current_function_file
= name
;
7989 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7990 output_quoted_string (stream
, name
);
7991 fprintf (stream
, "\n");
7992 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7993 fprintf (stream
, "\t#@stabs\n");
7996 else if (write_symbols
== DBX_DEBUG
)
7998 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7999 fprintf (stream
, "%s", ASM_STABS_OP
);
8000 output_quoted_string (stream
, name
);
8001 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8004 else if (name
!= current_function_file
8005 && strcmp (name
, current_function_file
) != 0)
8007 if (inside_function
&& ! TARGET_GAS
)
8008 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8011 ++num_source_filenames
;
8012 current_function_file
= name
;
8013 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8016 output_quoted_string (stream
, name
);
8017 fprintf (stream
, "\n");
8021 /* Emit a linenumber to a stream. */
8024 alpha_output_lineno (FILE *stream
, int line
)
8026 if (write_symbols
== DBX_DEBUG
)
8028 /* mips-tfile doesn't understand .stabd directives. */
8030 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8031 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8034 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8037 /* Structure to show the current status of registers and memory. */
8039 struct shadow_summary
8042 unsigned int i
: 31; /* Mask of int regs */
8043 unsigned int fp
: 31; /* Mask of fp regs */
8044 unsigned int mem
: 1; /* mem == imem | fpmem */
8048 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8049 to the summary structure. SET is nonzero if the insn is setting the
8050 object, otherwise zero. */
8053 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8055 const char *format_ptr
;
8061 switch (GET_CODE (x
))
8063 /* ??? Note that this case would be incorrect if the Alpha had a
8064 ZERO_EXTRACT in SET_DEST. */
8066 summarize_insn (SET_SRC (x
), sum
, 0);
8067 summarize_insn (SET_DEST (x
), sum
, 1);
8071 summarize_insn (XEXP (x
, 0), sum
, 1);
8075 summarize_insn (XEXP (x
, 0), sum
, 0);
8079 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8080 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8084 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8085 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8089 summarize_insn (SUBREG_REG (x
), sum
, 0);
8094 int regno
= REGNO (x
);
8095 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8097 if (regno
== 31 || regno
== 63)
8103 sum
->defd
.i
|= mask
;
8105 sum
->defd
.fp
|= mask
;
8110 sum
->used
.i
|= mask
;
8112 sum
->used
.fp
|= mask
;
8123 /* Find the regs used in memory address computation: */
8124 summarize_insn (XEXP (x
, 0), sum
, 0);
8127 case CONST_INT
: case CONST_DOUBLE
:
8128 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8129 case SCRATCH
: case ASM_INPUT
:
8132 /* Handle common unary and binary ops for efficiency. */
8133 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8134 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8135 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8136 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8137 case NE
: case EQ
: case GE
: case GT
: case LE
:
8138 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8139 summarize_insn (XEXP (x
, 0), sum
, 0);
8140 summarize_insn (XEXP (x
, 1), sum
, 0);
8143 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8144 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8145 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8146 case SQRT
: case FFS
:
8147 summarize_insn (XEXP (x
, 0), sum
, 0);
8151 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8152 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8153 switch (format_ptr
[i
])
8156 summarize_insn (XEXP (x
, i
), sum
, 0);
8160 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8161 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8173 /* Ensure a sufficient number of `trapb' insns are in the code when
8174 the user requests code with a trap precision of functions or
8177 In naive mode, when the user requests a trap-precision of
8178 "instruction", a trapb is needed after every instruction that may
8179 generate a trap. This ensures that the code is resumption safe but
8182 When optimizations are turned on, we delay issuing a trapb as long
8183 as possible. In this context, a trap shadow is the sequence of
8184 instructions that starts with a (potentially) trap generating
8185 instruction and extends to the next trapb or call_pal instruction
8186 (but GCC never generates call_pal by itself). We can delay (and
8187 therefore sometimes omit) a trapb subject to the following
8190 (a) On entry to the trap shadow, if any Alpha register or memory
8191 location contains a value that is used as an operand value by some
8192 instruction in the trap shadow (live on entry), then no instruction
8193 in the trap shadow may modify the register or memory location.
8195 (b) Within the trap shadow, the computation of the base register
8196 for a memory load or store instruction may not involve using the
8197 result of an instruction that might generate an UNPREDICTABLE
8200 (c) Within the trap shadow, no register may be used more than once
8201 as a destination register. (This is to make life easier for the
8204 (d) The trap shadow may not include any branch instructions. */
8207 alpha_handle_trap_shadows (void)
8209 struct shadow_summary shadow
;
8210 int trap_pending
, exception_nesting
;
8214 exception_nesting
= 0;
8217 shadow
.used
.mem
= 0;
8218 shadow
.defd
= shadow
.used
;
8220 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8222 if (GET_CODE (i
) == NOTE
)
8224 switch (NOTE_LINE_NUMBER (i
))
8226 case NOTE_INSN_EH_REGION_BEG
:
8227 exception_nesting
++;
8232 case NOTE_INSN_EH_REGION_END
:
8233 exception_nesting
--;
8238 case NOTE_INSN_EPILOGUE_BEG
:
8239 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8244 else if (trap_pending
)
8246 if (alpha_tp
== ALPHA_TP_FUNC
)
8248 if (GET_CODE (i
) == JUMP_INSN
8249 && GET_CODE (PATTERN (i
)) == RETURN
)
8252 else if (alpha_tp
== ALPHA_TP_INSN
)
8256 struct shadow_summary sum
;
8261 sum
.defd
= sum
.used
;
8263 switch (GET_CODE (i
))
8266 /* Annoyingly, get_attr_trap will abort on these. */
8267 if (GET_CODE (PATTERN (i
)) == USE
8268 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8271 summarize_insn (PATTERN (i
), &sum
, 0);
8273 if ((sum
.defd
.i
& shadow
.defd
.i
)
8274 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8276 /* (c) would be violated */
8280 /* Combine shadow with summary of current insn: */
8281 shadow
.used
.i
|= sum
.used
.i
;
8282 shadow
.used
.fp
|= sum
.used
.fp
;
8283 shadow
.used
.mem
|= sum
.used
.mem
;
8284 shadow
.defd
.i
|= sum
.defd
.i
;
8285 shadow
.defd
.fp
|= sum
.defd
.fp
;
8286 shadow
.defd
.mem
|= sum
.defd
.mem
;
8288 if ((sum
.defd
.i
& shadow
.used
.i
)
8289 || (sum
.defd
.fp
& shadow
.used
.fp
)
8290 || (sum
.defd
.mem
& shadow
.used
.mem
))
8292 /* (a) would be violated (also takes care of (b)) */
8293 if (get_attr_trap (i
) == TRAP_YES
8294 && ((sum
.defd
.i
& sum
.used
.i
)
8295 || (sum
.defd
.fp
& sum
.used
.fp
)))
8314 n
= emit_insn_before (gen_trapb (), i
);
8315 PUT_MODE (n
, TImode
);
8316 PUT_MODE (i
, TImode
);
8320 shadow
.used
.mem
= 0;
8321 shadow
.defd
= shadow
.used
;
8326 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8327 && GET_CODE (i
) == INSN
8328 && GET_CODE (PATTERN (i
)) != USE
8329 && GET_CODE (PATTERN (i
)) != CLOBBER
8330 && get_attr_trap (i
) == TRAP_YES
)
8332 if (optimize
&& !trap_pending
)
8333 summarize_insn (PATTERN (i
), &shadow
, 0);
8339 /* Alpha can only issue instruction groups simultaneously if they are
8340 suitably aligned. This is very processor-specific. */
8342 enum alphaev4_pipe
{
8349 enum alphaev5_pipe
{
8360 static enum alphaev4_pipe
8361 alphaev4_insn_pipe (rtx insn
)
8363 if (recog_memoized (insn
) < 0)
8365 if (get_attr_length (insn
) != 4)
8368 switch (get_attr_type (insn
))
8402 static enum alphaev5_pipe
8403 alphaev5_insn_pipe (rtx insn
)
8405 if (recog_memoized (insn
) < 0)
8407 if (get_attr_length (insn
) != 4)
8410 switch (get_attr_type (insn
))
8451 /* IN_USE is a mask of the slots currently filled within the insn group.
8452 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8453 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8455 LEN is, of course, the length of the group in bytes. */
8458 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8465 || GET_CODE (PATTERN (insn
)) == CLOBBER
8466 || GET_CODE (PATTERN (insn
)) == USE
)
8471 enum alphaev4_pipe pipe
;
8473 pipe
= alphaev4_insn_pipe (insn
);
8477 /* Force complex instructions to start new groups. */
8481 /* If this is a completely unrecognized insn, its an asm.
8482 We don't know how long it is, so record length as -1 to
8483 signal a needed realignment. */
8484 if (recog_memoized (insn
) < 0)
8487 len
= get_attr_length (insn
);
8491 if (in_use
& EV4_IB0
)
8493 if (in_use
& EV4_IB1
)
8498 in_use
|= EV4_IB0
| EV4_IBX
;
8502 if (in_use
& EV4_IB0
)
8504 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8512 if (in_use
& EV4_IB1
)
8522 /* Haifa doesn't do well scheduling branches. */
8523 if (GET_CODE (insn
) == JUMP_INSN
)
8527 insn
= next_nonnote_insn (insn
);
8529 if (!insn
|| ! INSN_P (insn
))
8532 /* Let Haifa tell us where it thinks insn group boundaries are. */
8533 if (GET_MODE (insn
) == TImode
)
8536 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8541 insn
= next_nonnote_insn (insn
);
8549 /* IN_USE is a mask of the slots currently filled within the insn group.
8550 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8551 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8553 LEN is, of course, the length of the group in bytes. */
8556 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8563 || GET_CODE (PATTERN (insn
)) == CLOBBER
8564 || GET_CODE (PATTERN (insn
)) == USE
)
8569 enum alphaev5_pipe pipe
;
8571 pipe
= alphaev5_insn_pipe (insn
);
8575 /* Force complex instructions to start new groups. */
8579 /* If this is a completely unrecognized insn, its an asm.
8580 We don't know how long it is, so record length as -1 to
8581 signal a needed realignment. */
8582 if (recog_memoized (insn
) < 0)
8585 len
= get_attr_length (insn
);
8588 /* ??? Most of the places below, we would like to abort, as
8589 it would indicate an error either in Haifa, or in the
8590 scheduling description. Unfortunately, Haifa never
8591 schedules the last instruction of the BB, so we don't
8592 have an accurate TI bit to go off. */
8594 if (in_use
& EV5_E0
)
8596 if (in_use
& EV5_E1
)
8601 in_use
|= EV5_E0
| EV5_E01
;
8605 if (in_use
& EV5_E0
)
8607 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8615 if (in_use
& EV5_E1
)
8621 if (in_use
& EV5_FA
)
8623 if (in_use
& EV5_FM
)
8628 in_use
|= EV5_FA
| EV5_FAM
;
8632 if (in_use
& EV5_FA
)
8638 if (in_use
& EV5_FM
)
8651 /* Haifa doesn't do well scheduling branches. */
8652 /* ??? If this is predicted not-taken, slotting continues, except
8653 that no more IBR, FBR, or JSR insns may be slotted. */
8654 if (GET_CODE (insn
) == JUMP_INSN
)
8658 insn
= next_nonnote_insn (insn
);
8660 if (!insn
|| ! INSN_P (insn
))
8663 /* Let Haifa tell us where it thinks insn group boundaries are. */
8664 if (GET_MODE (insn
) == TImode
)
8667 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8672 insn
= next_nonnote_insn (insn
);
8681 alphaev4_next_nop (int *pin_use
)
8683 int in_use
= *pin_use
;
8686 if (!(in_use
& EV4_IB0
))
8691 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8696 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8709 alphaev5_next_nop (int *pin_use
)
8711 int in_use
= *pin_use
;
8714 if (!(in_use
& EV5_E1
))
8719 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8724 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8736 /* The instruction group alignment main loop. */
8739 alpha_align_insns (unsigned int max_align
,
8740 rtx (*next_group
) (rtx
, int *, int *),
8741 rtx (*next_nop
) (int *))
8743 /* ALIGN is the known alignment for the insn group. */
8745 /* OFS is the offset of the current insn in the insn group. */
8747 int prev_in_use
, in_use
, len
;
8750 /* Let shorten branches care for assigning alignments to code labels. */
8751 shorten_branches (get_insns ());
8753 if (align_functions
< 4)
8755 else if ((unsigned int) align_functions
< max_align
)
8756 align
= align_functions
;
8760 ofs
= prev_in_use
= 0;
8762 if (GET_CODE (i
) == NOTE
)
8763 i
= next_nonnote_insn (i
);
8767 next
= (*next_group
) (i
, &in_use
, &len
);
8769 /* When we see a label, resync alignment etc. */
8770 if (GET_CODE (i
) == CODE_LABEL
)
8772 unsigned int new_align
= 1 << label_to_alignment (i
);
8774 if (new_align
>= align
)
8776 align
= new_align
< max_align
? new_align
: max_align
;
8780 else if (ofs
& (new_align
-1))
8781 ofs
= (ofs
| (new_align
-1)) + 1;
8786 /* Handle complex instructions special. */
8787 else if (in_use
== 0)
8789 /* Asms will have length < 0. This is a signal that we have
8790 lost alignment knowledge. Assume, however, that the asm
8791 will not mis-align instructions. */
8800 /* If the known alignment is smaller than the recognized insn group,
8801 realign the output. */
8802 else if ((int) align
< len
)
8804 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8807 where
= prev
= prev_nonnote_insn (i
);
8808 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8811 /* Can't realign between a call and its gp reload. */
8812 if (! (TARGET_EXPLICIT_RELOCS
8813 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8815 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8816 align
= 1 << new_log_align
;
8821 /* If the group won't fit in the same INT16 as the previous,
8822 we need to add padding to keep the group together. Rather
8823 than simply leaving the insn filling to the assembler, we
8824 can make use of the knowledge of what sorts of instructions
8825 were issued in the previous group to make sure that all of
8826 the added nops are really free. */
8827 else if (ofs
+ len
> (int) align
)
8829 int nop_count
= (align
- ofs
) / 4;
8832 /* Insert nops before labels, branches, and calls to truely merge
8833 the execution of the nops with the previous instruction group. */
8834 where
= prev_nonnote_insn (i
);
8837 if (GET_CODE (where
) == CODE_LABEL
)
8839 rtx where2
= prev_nonnote_insn (where
);
8840 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8843 else if (GET_CODE (where
) == INSN
)
8850 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8851 while (--nop_count
);
8855 ofs
= (ofs
+ len
) & (align
- 1);
8856 prev_in_use
= in_use
;
8861 /* Machine dependent reorg pass. */
8866 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8867 alpha_handle_trap_shadows ();
8869 /* Due to the number of extra trapb insns, don't bother fixing up
8870 alignment when trap precision is instruction. Moreover, we can
8871 only do our job when sched2 is run. */
8872 if (optimize
&& !optimize_size
8873 && alpha_tp
!= ALPHA_TP_INSN
8874 && flag_schedule_insns_after_reload
)
8876 if (alpha_cpu
== PROCESSOR_EV4
)
8877 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
8878 else if (alpha_cpu
== PROCESSOR_EV5
)
8879 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
8883 #if !TARGET_ABI_UNICOSMK
8890 alpha_file_start (void)
8892 #ifdef OBJECT_FORMAT_ELF
8893 /* If emitting dwarf2 debug information, we cannot generate a .file
8894 directive to start the file, as it will conflict with dwarf2out
8895 file numbers. So it's only useful when emitting mdebug output. */
8896 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
8899 default_file_start ();
8901 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
8904 fputs ("\t.set noreorder\n", asm_out_file
);
8905 fputs ("\t.set volatile\n", asm_out_file
);
8906 if (!TARGET_ABI_OPEN_VMS
)
8907 fputs ("\t.set noat\n", asm_out_file
);
8908 if (TARGET_EXPLICIT_RELOCS
)
8909 fputs ("\t.set nomacro\n", asm_out_file
);
8910 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
8911 fprintf (asm_out_file
,
8913 TARGET_CPU_EV6
? "ev6"
8915 ? (TARGET_MAX
? "pca56" : TARGET_BWX
? "ev56" : "ev5")
8920 #ifdef OBJECT_FORMAT_ELF
8922 /* Switch to the section to which we should output X. The only thing
8923 special we do here is to honor small data. */
8926 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
8927 unsigned HOST_WIDE_INT align
)
8929 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8930 /* ??? Consider using mergeable sdata sections. */
8933 default_elf_select_rtx_section (mode
, x
, align
);
8936 #endif /* OBJECT_FORMAT_ELF */
8938 /* Structure to collect function names for final output in link section. */
8939 /* Note that items marked with GTY can't be ifdef'ed out. */
8941 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8942 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
8944 struct alpha_links
GTY(())
8948 enum links_kind lkind
;
8949 enum reloc_kind rkind
;
8952 struct alpha_funcs
GTY(())
8955 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8959 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8960 splay_tree alpha_links_tree
;
8961 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
8962 splay_tree alpha_funcs_tree
;
8964 static GTY(()) int alpha_funcs_num
;
8966 #if TARGET_ABI_OPEN_VMS
8968 /* Return the VMS argument type corresponding to MODE. */
8971 alpha_arg_type (enum machine_mode mode
)
8976 return TARGET_FLOAT_VAX
? FF
: FS
;
8978 return TARGET_FLOAT_VAX
? FD
: FT
;
8984 /* Return an rtx for an integer representing the VMS Argument Information
8988 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
8990 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8993 for (i
= 0; i
< 6; i
++)
8994 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8996 return GEN_INT (regval
);
8999 /* Make (or fake) .linkage entry for function call.
9001 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9003 Return an SYMBOL_REF rtx for the linkage. */
9006 alpha_need_linkage (const char *name
, int is_local
)
9008 splay_tree_node node
;
9009 struct alpha_links
*al
;
9016 struct alpha_funcs
*cfaf
;
9018 if (!alpha_funcs_tree
)
9019 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9020 splay_tree_compare_pointers
);
9022 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9025 cfaf
->num
= ++alpha_funcs_num
;
9027 splay_tree_insert (alpha_funcs_tree
,
9028 (splay_tree_key
) current_function_decl
,
9029 (splay_tree_value
) cfaf
);
9032 if (alpha_links_tree
)
9034 /* Is this name already defined? */
9036 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9039 al
= (struct alpha_links
*) node
->value
;
9042 /* Defined here but external assumed. */
9043 if (al
->lkind
== KIND_EXTERN
)
9044 al
->lkind
= KIND_LOCAL
;
9048 /* Used here but unused assumed. */
9049 if (al
->lkind
== KIND_UNUSED
)
9050 al
->lkind
= KIND_LOCAL
;
9056 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9058 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9059 name
= ggc_strdup (name
);
9061 /* Assume external if no definition. */
9062 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9064 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9065 get_identifier (name
);
9067 /* Construct a SYMBOL_REF for us to call. */
9069 size_t name_len
= strlen (name
);
9070 char *linksym
= alloca (name_len
+ 6);
9072 memcpy (linksym
+ 1, name
, name_len
);
9073 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9074 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9075 ggc_alloc_string (linksym
, name_len
+ 5));
9078 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9079 (splay_tree_value
) al
);
9085 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9087 splay_tree_node cfunnode
;
9088 struct alpha_funcs
*cfaf
;
9089 struct alpha_links
*al
;
9090 const char *name
= XSTR (linkage
, 0);
9092 cfaf
= (struct alpha_funcs
*) 0;
9093 al
= (struct alpha_links
*) 0;
9095 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9096 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9100 splay_tree_node lnode
;
9102 /* Is this name already defined? */
9104 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9106 al
= (struct alpha_links
*) lnode
->value
;
9109 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9117 splay_tree_node node
= 0;
9118 struct alpha_links
*anl
;
9123 name_len
= strlen (name
);
9125 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9126 al
->num
= cfaf
->num
;
9128 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9131 anl
= (struct alpha_links
*) node
->value
;
9132 al
->lkind
= anl
->lkind
;
9135 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9136 buflen
= strlen (buf
);
9137 linksym
= alloca (buflen
+ 1);
9138 memcpy (linksym
, buf
, buflen
+ 1);
9140 al
->linkage
= gen_rtx_SYMBOL_REF
9141 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9143 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9144 (splay_tree_value
) al
);
9148 al
->rkind
= KIND_CODEADDR
;
9150 al
->rkind
= KIND_LINKAGE
;
9153 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9159 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9161 const char *const name
= (const char *) node
->key
;
9162 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9163 FILE *stream
= (FILE *) data
;
9165 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9166 if (link
->rkind
== KIND_CODEADDR
)
9168 if (link
->lkind
== KIND_LOCAL
)
9170 /* Local and used */
9171 fprintf (stream
, "\t.quad %s..en\n", name
);
9175 /* External and used, request code address. */
9176 fprintf (stream
, "\t.code_address %s\n", name
);
9181 if (link
->lkind
== KIND_LOCAL
)
9183 /* Local and used, build linkage pair. */
9184 fprintf (stream
, "\t.quad %s..en\n", name
);
9185 fprintf (stream
, "\t.quad %s\n", name
);
9189 /* External and used, request linkage pair. */
9190 fprintf (stream
, "\t.linkage %s\n", name
);
9198 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9200 splay_tree_node node
;
9201 struct alpha_funcs
*func
;
9204 fprintf (stream
, "\t.align 3\n");
9205 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9206 func
= (struct alpha_funcs
*) node
->value
;
9208 fputs ("\t.name ", stream
);
9209 assemble_name (stream
, funname
);
9210 fputs ("..na\n", stream
);
9211 ASM_OUTPUT_LABEL (stream
, funname
);
9212 fprintf (stream
, "\t.pdesc ");
9213 assemble_name (stream
, funname
);
9214 fprintf (stream
, "..en,%s\n",
9215 alpha_procedure_type
== PT_STACK
? "stack"
9216 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9220 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9221 /* splay_tree_delete (func->links); */
9225 /* Given a decl, a section name, and whether the decl initializer
9226 has relocs, choose attributes for the section. */
9228 #define SECTION_VMS_OVERLAY SECTION_FORGET
9229 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9230 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9233 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9235 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9237 if (decl
&& DECL_ATTRIBUTES (decl
)
9238 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9239 flags
|= SECTION_VMS_OVERLAY
;
9240 if (decl
&& DECL_ATTRIBUTES (decl
)
9241 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9242 flags
|= SECTION_VMS_GLOBAL
;
9243 if (decl
&& DECL_ATTRIBUTES (decl
)
9244 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9245 flags
|= SECTION_VMS_INITIALIZE
;
9250 /* Switch to an arbitrary section NAME with attributes as specified
9251 by FLAGS. ALIGN specifies any known alignment requirements for
9252 the section; 0 if the default should be used. */
9255 vms_asm_named_section (const char *name
, unsigned int flags
)
9257 fputc ('\n', asm_out_file
);
9258 fprintf (asm_out_file
, ".section\t%s", name
);
9260 if (flags
& SECTION_VMS_OVERLAY
)
9261 fprintf (asm_out_file
, ",OVR");
9262 if (flags
& SECTION_VMS_GLOBAL
)
9263 fprintf (asm_out_file
, ",GBL");
9264 if (flags
& SECTION_VMS_INITIALIZE
)
9265 fprintf (asm_out_file
, ",NOMOD");
9266 if (flags
& SECTION_DEBUG
)
9267 fprintf (asm_out_file
, ",NOWRT");
9269 fputc ('\n', asm_out_file
);
9272 /* Record an element in the table of global constructors. SYMBOL is
9273 a SYMBOL_REF of the function to be called; PRIORITY is a number
9274 between 0 and MAX_INIT_PRIORITY.
9276 Differs from default_ctors_section_asm_out_constructor in that the
9277 width of the .ctors entry is always 64 bits, rather than the 32 bits
9278 used by a normal pointer. */
9281 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9284 assemble_align (BITS_PER_WORD
);
9285 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9289 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9292 assemble_align (BITS_PER_WORD
);
9293 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9298 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9299 int is_local ATTRIBUTE_UNUSED
)
9305 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9306 tree cfundecl ATTRIBUTE_UNUSED
,
9307 int lflag ATTRIBUTE_UNUSED
,
9308 int rflag ATTRIBUTE_UNUSED
)
9313 #endif /* TARGET_ABI_OPEN_VMS */
9315 #if TARGET_ABI_UNICOSMK
9317 /* Define the offset between two registers, one to be eliminated, and the
9318 other its replacement, at the start of a routine. */
9321 unicosmk_initial_elimination_offset (int from
, int to
)
9325 fixed_size
= alpha_sa_size();
9326 if (fixed_size
!= 0)
9329 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9331 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9333 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9334 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9335 + ALPHA_ROUND (get_frame_size()));
9336 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9337 return (ALPHA_ROUND (fixed_size
)
9338 + ALPHA_ROUND (get_frame_size()
9339 + current_function_outgoing_args_size
));
9344 /* Output the module name for .ident and .end directives. We have to strip
9345 directories and add make sure that the module name starts with a letter
9349 unicosmk_output_module_name (FILE *file
)
9351 const char *name
= lbasename (main_input_filename
);
9352 unsigned len
= strlen (name
);
9353 char *clean_name
= alloca (len
+ 2);
9354 char *ptr
= clean_name
;
9356 /* CAM only accepts module names that start with a letter or '$'. We
9357 prefix the module name with a '$' if necessary. */
9359 if (!ISALPHA (*name
))
9361 memcpy (ptr
, name
, len
+ 1);
9362 clean_symbol_name (clean_name
);
9363 fputs (clean_name
, file
);
9366 /* Output the definition of a common variable. */
9369 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9372 printf ("T3E__: common %s\n", name
);
9375 fputs("\t.endp\n\n\t.psect ", file
);
9376 assemble_name(file
, name
);
9377 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9378 fprintf(file
, "\t.byte\t0:%d\n", size
);
9380 /* Mark the symbol as defined in this module. */
9381 name_tree
= get_identifier (name
);
9382 TREE_ASM_WRITTEN (name_tree
) = 1;
9385 #define SECTION_PUBLIC SECTION_MACH_DEP
9386 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9387 static int current_section_align
;
9390 unicosmk_section_type_flags (tree decl
, const char *name
,
9391 int reloc ATTRIBUTE_UNUSED
)
9393 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9398 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9400 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9401 if (align_functions_log
> current_section_align
)
9402 current_section_align
= align_functions_log
;
9404 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9405 flags
|= SECTION_MAIN
;
9408 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9410 if (TREE_PUBLIC (decl
))
9411 flags
|= SECTION_PUBLIC
;
9416 /* Generate a section name for decl and associate it with the
9420 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9428 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9429 name
= default_strip_name_encoding (name
);
9430 len
= strlen (name
);
9432 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9436 /* It is essential that we prefix the section name here because
9437 otherwise the section names generated for constructors and
9438 destructors confuse collect2. */
9440 string
= alloca (len
+ 6);
9441 sprintf (string
, "code@%s", name
);
9442 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9444 else if (TREE_PUBLIC (decl
))
9445 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9450 string
= alloca (len
+ 6);
9451 sprintf (string
, "data@%s", name
);
9452 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9456 /* Switch to an arbitrary section NAME with attributes as specified
9457 by FLAGS. ALIGN specifies any known alignment requirements for
9458 the section; 0 if the default should be used. */
9461 unicosmk_asm_named_section (const char *name
, unsigned int flags
)
9465 /* Close the previous section. */
9467 fputs ("\t.endp\n\n", asm_out_file
);
9469 /* Find out what kind of section we are opening. */
9471 if (flags
& SECTION_MAIN
)
9472 fputs ("\t.start\tmain\n", asm_out_file
);
9474 if (flags
& SECTION_CODE
)
9476 else if (flags
& SECTION_PUBLIC
)
9481 if (current_section_align
!= 0)
9482 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9483 current_section_align
, kind
);
9485 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9489 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9492 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9493 unicosmk_unique_section (decl
, 0);
9496 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9497 in code sections because .align fill unused space with zeroes. */
9500 unicosmk_output_align (FILE *file
, int align
)
9502 if (inside_function
)
9503 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9505 fprintf (file
, "\t.align\t%d\n", align
);
9508 /* Add a case vector to the current function's list of deferred case
9509 vectors. Case vectors have to be put into a separate section because CAM
9510 does not allow data definitions in code sections. */
9513 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9515 struct machine_function
*machine
= cfun
->machine
;
9517 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9518 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9519 machine
->addr_list
);
9522 /* Output a case vector. */
9525 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9527 rtx lab
= XEXP (vec
, 0);
9528 rtx body
= XEXP (vec
, 1);
9529 int vlen
= XVECLEN (body
, 0);
9532 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9534 for (idx
= 0; idx
< vlen
; idx
++)
9536 ASM_OUTPUT_ADDR_VEC_ELT
9537 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9541 /* Output current function's deferred case vectors. */
9544 unicosmk_output_deferred_case_vectors (FILE *file
)
9546 struct machine_function
*machine
= cfun
->machine
;
9549 if (machine
->addr_list
== NULL_RTX
)
9553 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9554 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9557 /* Generate the name of the SSIB section for the current function. */
9559 #define SSIB_PREFIX "__SSIB_"
9560 #define SSIB_PREFIX_LEN 7
9563 unicosmk_ssib_name (void)
9565 /* This is ok since CAM won't be able to deal with names longer than that
9568 static char name
[256];
9574 x
= DECL_RTL (cfun
->decl
);
9575 if (GET_CODE (x
) != MEM
)
9578 if (GET_CODE (x
) != SYMBOL_REF
)
9580 fnname
= XSTR (x
, 0);
9582 len
= strlen (fnname
);
9583 if (len
+ SSIB_PREFIX_LEN
> 255)
9584 len
= 255 - SSIB_PREFIX_LEN
;
9586 strcpy (name
, SSIB_PREFIX
);
9587 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9588 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9593 /* Set up the dynamic subprogram information block (DSIB) and update the
9594 frame pointer register ($15) for subroutines which have a frame. If the
9595 subroutine doesn't have a frame, simply increment $15. */
9598 unicosmk_gen_dsib (unsigned long *imaskP
)
9600 if (alpha_procedure_type
== PT_STACK
)
9602 const char *ssib_name
;
9605 /* Allocate 64 bytes for the DSIB. */
9607 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9609 emit_insn (gen_blockage ());
9611 /* Save the return address. */
9613 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9614 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9615 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9616 (*imaskP
) &= ~(1UL << REG_RA
);
9618 /* Save the old frame pointer. */
9620 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9621 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9622 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9623 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9625 emit_insn (gen_blockage ());
9627 /* Store the SSIB pointer. */
9629 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9630 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9631 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9633 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9634 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9635 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9637 /* Save the CIW index. */
9639 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9640 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9641 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9643 emit_insn (gen_blockage ());
9645 /* Set the new frame pointer. */
9647 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9648 stack_pointer_rtx
, GEN_INT (64))));
9653 /* Increment the frame pointer register to indicate that we do not
9656 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9657 hard_frame_pointer_rtx
, GEN_INT (1))));
9661 /* Output the static subroutine information block for the current
9665 unicosmk_output_ssib (FILE *file
, const char *fnname
)
9671 struct machine_function
*machine
= cfun
->machine
;
9674 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9675 unicosmk_ssib_name ());
9677 /* Some required stuff and the function name length. */
9679 len
= strlen (fnname
);
9680 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9683 ??? We don't do that yet. */
9685 fputs ("\t.quad\t0\n", file
);
9687 /* Function address. */
9689 fputs ("\t.quad\t", file
);
9690 assemble_name (file
, fnname
);
9693 fputs ("\t.quad\t0\n", file
);
9694 fputs ("\t.quad\t0\n", file
);
9697 ??? We do it the same way Cray CC does it but this could be
9700 for( i
= 0; i
< len
; i
++ )
9701 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9702 if( (len
% 8) == 0 )
9703 fputs ("\t.quad\t0\n", file
);
9705 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9707 /* All call information words used in the function. */
9709 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9712 #if HOST_BITS_PER_WIDE_INT == 32
9713 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
9714 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9716 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
9721 /* Add a call information word (CIW) to the list of the current function's
9722 CIWs and return its index.
9724 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9727 unicosmk_add_call_info_word (rtx x
)
9730 struct machine_function
*machine
= cfun
->machine
;
9732 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9733 if (machine
->first_ciw
== NULL_RTX
)
9734 machine
->first_ciw
= node
;
9736 XEXP (machine
->last_ciw
, 1) = node
;
9738 machine
->last_ciw
= node
;
9739 ++machine
->ciw_count
;
9741 return GEN_INT (machine
->ciw_count
9742 + strlen (current_function_name
)/8 + 5);
9745 static char unicosmk_section_buf
[100];
9748 unicosmk_text_section (void)
9750 static int count
= 0;
9751 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9753 return unicosmk_section_buf
;
9757 unicosmk_data_section (void)
9759 static int count
= 1;
9760 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9762 return unicosmk_section_buf
;
9765 /* The Cray assembler doesn't accept extern declarations for symbols which
9766 are defined in the same file. We have to keep track of all global
9767 symbols which are referenced and/or defined in a source file and output
9768 extern declarations for those which are referenced but not defined at
9771 /* List of identifiers for which an extern declaration might have to be
9773 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9775 struct unicosmk_extern_list
9777 struct unicosmk_extern_list
*next
;
9781 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9783 /* Output extern declarations which are required for every asm file. */
9786 unicosmk_output_default_externs (FILE *file
)
9788 static const char *const externs
[] =
9789 { "__T3E_MISMATCH" };
9794 n
= ARRAY_SIZE (externs
);
9796 for (i
= 0; i
< n
; i
++)
9797 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9800 /* Output extern declarations for global symbols which are have been
9801 referenced but not defined. */
9804 unicosmk_output_externs (FILE *file
)
9806 struct unicosmk_extern_list
*p
;
9807 const char *real_name
;
9811 len
= strlen (user_label_prefix
);
9812 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9814 /* We have to strip the encoding and possibly remove user_label_prefix
9815 from the identifier in order to handle -fleading-underscore and
9816 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9817 real_name
= default_strip_name_encoding (p
->name
);
9818 if (len
&& p
->name
[0] == '*'
9819 && !memcmp (real_name
, user_label_prefix
, len
))
9822 name_tree
= get_identifier (real_name
);
9823 if (! TREE_ASM_WRITTEN (name_tree
))
9825 TREE_ASM_WRITTEN (name_tree
) = 1;
9826 fputs ("\t.extern\t", file
);
9827 assemble_name (file
, p
->name
);
9833 /* Record an extern. */
9836 unicosmk_add_extern (const char *name
)
9838 struct unicosmk_extern_list
*p
;
9840 p
= (struct unicosmk_extern_list
*)
9841 xmalloc (sizeof (struct unicosmk_extern_list
));
9842 p
->next
= unicosmk_extern_head
;
9844 unicosmk_extern_head
= p
;
9847 /* The Cray assembler generates incorrect code if identifiers which
9848 conflict with register names are used as instruction operands. We have
9849 to replace such identifiers with DEX expressions. */
9851 /* Structure to collect identifiers which have been replaced by DEX
9853 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9855 struct unicosmk_dex
{
9856 struct unicosmk_dex
*next
;
9860 /* List of identifiers which have been replaced by DEX expressions. The DEX
9861 number is determined by the position in the list. */
9863 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9865 /* The number of elements in the DEX list. */
9867 static int unicosmk_dex_count
= 0;
9869 /* Check if NAME must be replaced by a DEX expression. */
9872 unicosmk_special_name (const char *name
)
9880 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9886 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9889 return (name
[2] == '\0'
9890 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9893 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9897 /* Return the DEX number if X must be replaced by a DEX expression and 0
9901 unicosmk_need_dex (rtx x
)
9903 struct unicosmk_dex
*dex
;
9907 if (GET_CODE (x
) != SYMBOL_REF
)
9911 if (! unicosmk_special_name (name
))
9914 i
= unicosmk_dex_count
;
9915 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9917 if (! strcmp (name
, dex
->name
))
9922 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
9924 dex
->next
= unicosmk_dex_list
;
9925 unicosmk_dex_list
= dex
;
9927 ++unicosmk_dex_count
;
9928 return unicosmk_dex_count
;
9931 /* Output the DEX definitions for this file. */
9934 unicosmk_output_dex (FILE *file
)
9936 struct unicosmk_dex
*dex
;
9939 if (unicosmk_dex_list
== NULL
)
9942 fprintf (file
, "\t.dexstart\n");
9944 i
= unicosmk_dex_count
;
9945 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9947 fprintf (file
, "\tDEX (%d) = ", i
);
9948 assemble_name (file
, dex
->name
);
9953 fprintf (file
, "\t.dexend\n");
9956 /* Output text that to appear at the beginning of an assembler file. */
9959 unicosmk_file_start (void)
9963 fputs ("\t.ident\t", asm_out_file
);
9964 unicosmk_output_module_name (asm_out_file
);
9965 fputs ("\n\n", asm_out_file
);
9967 /* The Unicos/Mk assembler uses different register names. Instead of trying
9968 to support them, we simply use micro definitions. */
9970 /* CAM has different register names: rN for the integer register N and fN
9971 for the floating-point register N. Instead of trying to use these in
9972 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9975 for (i
= 0; i
< 32; ++i
)
9976 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
9978 for (i
= 0; i
< 32; ++i
)
9979 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
9981 putc ('\n', asm_out_file
);
9983 /* The .align directive fill unused space with zeroes which does not work
9984 in code sections. We define the macro 'gcc@code@align' which uses nops
9985 instead. Note that it assumes that code sections always have the
9986 biggest possible alignment since . refers to the current offset from
9987 the beginning of the section. */
9989 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
9990 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
9991 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
9992 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
9993 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
9994 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
9995 fputs ("\t.endr\n", asm_out_file
);
9996 fputs ("\t.endif\n", asm_out_file
);
9997 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
9999 /* Output extern declarations which should always be visible. */
10000 unicosmk_output_default_externs (asm_out_file
);
10002 /* Open a dummy section. We always need to be inside a section for the
10003 section-switching code to work correctly.
10004 ??? This should be a module id or something like that. I still have to
10005 figure out what the rules for those are. */
10006 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10009 /* Output text to appear at the end of an assembler file. This includes all
10010 pending extern declarations and DEX expressions. */
10013 unicosmk_file_end (void)
10015 fputs ("\t.endp\n\n", asm_out_file
);
10017 /* Output all pending externs. */
10019 unicosmk_output_externs (asm_out_file
);
10021 /* Output dex definitions used for functions whose names conflict with
10024 unicosmk_output_dex (asm_out_file
);
10026 fputs ("\t.end\t", asm_out_file
);
10027 unicosmk_output_module_name (asm_out_file
);
10028 putc ('\n', asm_out_file
);
10034 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10038 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10042 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10043 const char * fnname ATTRIBUTE_UNUSED
)
10047 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10053 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10058 #endif /* TARGET_ABI_UNICOSMK */
10061 alpha_init_libfuncs (void)
10063 if (TARGET_ABI_UNICOSMK
)
10065 /* Prevent gcc from generating calls to __divsi3. */
10066 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10067 set_optab_libfunc (udiv_optab
, SImode
, 0);
10069 /* Use the functions provided by the system library
10070 for DImode integer division. */
10071 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10072 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10074 else if (TARGET_ABI_OPEN_VMS
)
10076 /* Use the VMS runtime library functions for division and
10078 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10079 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10080 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10081 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10082 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10083 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10084 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10085 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10090 /* Initialize the GCC target structure. */
10091 #if TARGET_ABI_OPEN_VMS
10092 # undef TARGET_ATTRIBUTE_TABLE
10093 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10094 # undef TARGET_SECTION_TYPE_FLAGS
10095 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10098 #undef TARGET_IN_SMALL_DATA_P
10099 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10101 #if TARGET_ABI_UNICOSMK
10102 # undef TARGET_INSERT_ATTRIBUTES
10103 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10104 # undef TARGET_SECTION_TYPE_FLAGS
10105 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10106 # undef TARGET_ASM_UNIQUE_SECTION
10107 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10108 # undef TARGET_ASM_GLOBALIZE_LABEL
10109 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10112 #undef TARGET_ASM_ALIGNED_HI_OP
10113 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10114 #undef TARGET_ASM_ALIGNED_DI_OP
10115 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10117 /* Default unaligned ops are provided for ELF systems. To get unaligned
10118 data for non-ELF systems, we have to turn off auto alignment. */
10119 #ifndef OBJECT_FORMAT_ELF
10120 #undef TARGET_ASM_UNALIGNED_HI_OP
10121 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10122 #undef TARGET_ASM_UNALIGNED_SI_OP
10123 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10124 #undef TARGET_ASM_UNALIGNED_DI_OP
10125 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10128 #ifdef OBJECT_FORMAT_ELF
10129 #undef TARGET_ASM_SELECT_RTX_SECTION
10130 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10133 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10134 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10136 #undef TARGET_INIT_LIBFUNCS
10137 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10139 #if TARGET_ABI_UNICOSMK
10140 #undef TARGET_ASM_FILE_START
10141 #define TARGET_ASM_FILE_START unicosmk_file_start
10142 #undef TARGET_ASM_FILE_END
10143 #define TARGET_ASM_FILE_END unicosmk_file_end
10145 #undef TARGET_ASM_FILE_START
10146 #define TARGET_ASM_FILE_START alpha_file_start
10147 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10148 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10151 #undef TARGET_SCHED_ADJUST_COST
10152 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10153 #undef TARGET_SCHED_ISSUE_RATE
10154 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10155 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10156 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10157 alpha_use_dfa_pipeline_interface
10158 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10159 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10160 alpha_multipass_dfa_lookahead
10162 #undef TARGET_HAVE_TLS
10163 #define TARGET_HAVE_TLS HAVE_AS_TLS
10165 #undef TARGET_INIT_BUILTINS
10166 #define TARGET_INIT_BUILTINS alpha_init_builtins
10167 #undef TARGET_EXPAND_BUILTIN
10168 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10170 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10171 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10172 #undef TARGET_CANNOT_COPY_INSN_P
10173 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10176 #undef TARGET_ASM_OUTPUT_MI_THUNK
10177 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10178 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10179 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10182 #undef TARGET_RTX_COSTS
10183 #define TARGET_RTX_COSTS alpha_rtx_costs
10184 #undef TARGET_ADDRESS_COST
10185 #define TARGET_ADDRESS_COST hook_int_rtx_0
10187 #undef TARGET_MACHINE_DEPENDENT_REORG
10188 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10190 #undef TARGET_PROMOTE_FUNCTION_ARGS
10191 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10192 #undef TARGET_PROMOTE_FUNCTION_RETURN
10193 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10194 #undef TARGET_PROMOTE_PROTOTYPES
10195 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10196 #undef TARGET_STRUCT_VALUE_RTX
10197 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
10198 #undef TARGET_RETURN_IN_MEMORY
10199 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10200 #undef TARGET_SETUP_INCOMING_VARARGS
10201 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10202 #undef TARGET_STRICT_ARGUMENT_NAMING
10203 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10204 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10205 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10207 struct gcc_target targetm
= TARGET_INITIALIZER
;
10210 #include "gt-alpha.h"