1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 /* Specify which cpu to schedule for. */
58 enum processor_type alpha_cpu
;
59 static const char * const alpha_cpu_name
[] =
64 /* Specify how accurate floating-point traps need to be. */
66 enum alpha_trap_precision alpha_tp
;
68 /* Specify the floating-point rounding mode. */
70 enum alpha_fp_rounding_mode alpha_fprm
;
72 /* Specify which things cause traps. */
74 enum alpha_fp_trap_mode alpha_fptm
;
76 /* Specify bit size of immediate TLS offsets. */
78 int alpha_tls_size
= 32;
80 /* Strings decoded into the above options. */
82 const char *alpha_cpu_string
; /* -mcpu= */
83 const char *alpha_tune_string
; /* -mtune= */
84 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
85 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
86 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
87 const char *alpha_mlat_string
; /* -mmemory-latency= */
88 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
90 /* Save information from a "cmpxx" operation until the branch or scc is
93 struct alpha_compare alpha_compare
;
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
98 static int inside_function
= FALSE
;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency
= 3;
104 /* Whether the function needs the GP. */
106 static int alpha_function_needs_gp
;
108 /* The alias set for prologue/epilogue register save/restore. */
110 static GTY(()) int alpha_sr_alias_set
;
112 /* The assembler name of the current function. */
114 static const char *alpha_fnname
;
116 /* The next explicit relocation sequence number. */
117 extern GTY(()) int alpha_next_sequence_number
;
118 int alpha_next_sequence_number
= 1;
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
122 extern GTY(()) int alpha_this_literal_sequence_number
;
123 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
124 int alpha_this_literal_sequence_number
;
125 int alpha_this_gpdisp_sequence_number
;
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
131 unsigned char fp_add
;
132 unsigned char fp_mult
;
133 unsigned char fp_div_sf
;
134 unsigned char fp_div_df
;
135 unsigned char int_mult_si
;
136 unsigned char int_mult_di
;
137 unsigned char int_shift
;
138 unsigned char int_cmov
;
141 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
144 COSTS_N_INSNS (6), /* fp_add */
145 COSTS_N_INSNS (6), /* fp_mult */
146 COSTS_N_INSNS (34), /* fp_div_sf */
147 COSTS_N_INSNS (63), /* fp_div_df */
148 COSTS_N_INSNS (23), /* int_mult_si */
149 COSTS_N_INSNS (23), /* int_mult_di */
150 COSTS_N_INSNS (2), /* int_shift */
151 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (15), /* fp_div_sf */
157 COSTS_N_INSNS (22), /* fp_div_df */
158 COSTS_N_INSNS (8), /* int_mult_si */
159 COSTS_N_INSNS (12), /* int_mult_di */
160 COSTS_N_INSNS (1) + 1, /* int_shift */
161 COSTS_N_INSNS (1), /* int_cmov */
164 COSTS_N_INSNS (4), /* fp_add */
165 COSTS_N_INSNS (4), /* fp_mult */
166 COSTS_N_INSNS (12), /* fp_div_sf */
167 COSTS_N_INSNS (15), /* fp_div_df */
168 COSTS_N_INSNS (7), /* int_mult_si */
169 COSTS_N_INSNS (7), /* int_mult_di */
170 COSTS_N_INSNS (1), /* int_shift */
171 COSTS_N_INSNS (2), /* int_cmov */
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
179 #define NUM_ARGS current_function_args_info
185 /* Declarations of static functions. */
186 static struct machine_function
*alpha_init_machine_status (void);
187 static rtx
alpha_emit_xfloating_compare (enum rtx_code
, rtx
, rtx
);
189 #if TARGET_ABI_OPEN_VMS
190 static void alpha_write_linkage (FILE *, const char *, tree
);
193 static void unicosmk_output_deferred_case_vectors (FILE *);
194 static void unicosmk_gen_dsib (unsigned long *);
195 static void unicosmk_output_ssib (FILE *, const char *);
196 static int unicosmk_need_dex (rtx
);
198 /* Parse target option strings. */
201 override_options (void)
204 static const struct cpu_table
{
205 const char *const name
;
206 const enum processor_type processor
;
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
211 { "ev4", PROCESSOR_EV4
, 0 },
212 { "ev45", PROCESSOR_EV4
, 0 },
213 { "21064", PROCESSOR_EV4
, 0 },
214 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
215 { "21164", PROCESSOR_EV5
, EV5_MASK
},
216 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
217 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
218 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
219 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
220 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
221 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
222 { "21264", PROCESSOR_EV6
, EV6_MASK
},
223 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
224 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
228 /* Unicos/Mk doesn't have shared libraries. */
229 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
231 warning ("-f%s ignored for Unicos/Mk (not supported)",
232 (flag_pic
> 1) ? "PIC" : "pic");
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
238 if (TARGET_ABI_UNICOSMK
)
239 alpha_fprm
= ALPHA_FPRM_DYN
;
241 alpha_fprm
= ALPHA_FPRM_NORM
;
243 alpha_tp
= ALPHA_TP_PROG
;
244 alpha_fptm
= ALPHA_FPTM_N
;
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
254 if (TARGET_ABI_UNICOSMK
)
255 warning ("-mieee not supported on Unicos/Mk");
258 alpha_tp
= ALPHA_TP_INSN
;
259 alpha_fptm
= ALPHA_FPTM_SU
;
263 if (TARGET_IEEE_WITH_INEXACT
)
265 if (TARGET_ABI_UNICOSMK
)
266 warning ("-mieee-with-inexact not supported on Unicos/Mk");
269 alpha_tp
= ALPHA_TP_INSN
;
270 alpha_fptm
= ALPHA_FPTM_SUI
;
276 if (! strcmp (alpha_tp_string
, "p"))
277 alpha_tp
= ALPHA_TP_PROG
;
278 else if (! strcmp (alpha_tp_string
, "f"))
279 alpha_tp
= ALPHA_TP_FUNC
;
280 else if (! strcmp (alpha_tp_string
, "i"))
281 alpha_tp
= ALPHA_TP_INSN
;
283 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
286 if (alpha_fprm_string
)
288 if (! strcmp (alpha_fprm_string
, "n"))
289 alpha_fprm
= ALPHA_FPRM_NORM
;
290 else if (! strcmp (alpha_fprm_string
, "m"))
291 alpha_fprm
= ALPHA_FPRM_MINF
;
292 else if (! strcmp (alpha_fprm_string
, "c"))
293 alpha_fprm
= ALPHA_FPRM_CHOP
;
294 else if (! strcmp (alpha_fprm_string
,"d"))
295 alpha_fprm
= ALPHA_FPRM_DYN
;
297 error ("bad value `%s' for -mfp-rounding-mode switch",
301 if (alpha_fptm_string
)
303 if (strcmp (alpha_fptm_string
, "n") == 0)
304 alpha_fptm
= ALPHA_FPTM_N
;
305 else if (strcmp (alpha_fptm_string
, "u") == 0)
306 alpha_fptm
= ALPHA_FPTM_U
;
307 else if (strcmp (alpha_fptm_string
, "su") == 0)
308 alpha_fptm
= ALPHA_FPTM_SU
;
309 else if (strcmp (alpha_fptm_string
, "sui") == 0)
310 alpha_fptm
= ALPHA_FPTM_SUI
;
312 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
315 if (alpha_tls_size_string
)
317 if (strcmp (alpha_tls_size_string
, "16") == 0)
319 else if (strcmp (alpha_tls_size_string
, "32") == 0)
321 else if (strcmp (alpha_tls_size_string
, "64") == 0)
324 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
328 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
329 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
331 if (alpha_cpu_string
)
333 for (i
= 0; cpu_table
[i
].name
; i
++)
334 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
336 alpha_cpu
= cpu_table
[i
].processor
;
337 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
338 | MASK_CPU_EV5
| MASK_CPU_EV6
);
339 target_flags
|= cpu_table
[i
].flags
;
342 if (! cpu_table
[i
].name
)
343 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
346 if (alpha_tune_string
)
348 for (i
= 0; cpu_table
[i
].name
; i
++)
349 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
351 alpha_cpu
= cpu_table
[i
].processor
;
354 if (! cpu_table
[i
].name
)
355 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
358 /* Do some sanity checks on the above options. */
360 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
362 warning ("trap mode not supported on Unicos/Mk");
363 alpha_fptm
= ALPHA_FPTM_N
;
366 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
367 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
369 warning ("fp software completion requires -mtrap-precision=i");
370 alpha_tp
= ALPHA_TP_INSN
;
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
378 alpha_tp
= ALPHA_TP_PROG
;
381 if (TARGET_FLOAT_VAX
)
383 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
385 warning ("rounding mode not supported for VAX floats");
386 alpha_fprm
= ALPHA_FPRM_NORM
;
388 if (alpha_fptm
== ALPHA_FPTM_SUI
)
390 warning ("trap mode not supported for VAX floats");
391 alpha_fptm
= ALPHA_FPTM_SU
;
399 if (!alpha_mlat_string
)
400 alpha_mlat_string
= "L1";
402 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
403 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
405 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
406 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
407 && alpha_mlat_string
[2] == '\0')
409 static int const cache_latency
[][4] =
411 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
412 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
413 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
416 lat
= alpha_mlat_string
[1] - '0';
417 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
419 warning ("L%d cache latency unknown for %s",
420 lat
, alpha_cpu_name
[alpha_cpu
]);
424 lat
= cache_latency
[alpha_cpu
][lat
-1];
426 else if (! strcmp (alpha_mlat_string
, "main"))
428 /* Most current memories have about 370ns latency. This is
429 a reasonable guess for a fast cpu. */
434 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
438 alpha_memory_latency
= lat
;
441 /* Default the definition of "small data" to 8 bytes. */
445 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
447 target_flags
|= MASK_SMALL_DATA
;
448 else if (flag_pic
== 2)
449 target_flags
&= ~MASK_SMALL_DATA
;
451 /* Align labels and loops for optimal branching. */
452 /* ??? Kludge these by not doing anything if we don't optimize and also if
453 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
454 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
456 if (align_loops
<= 0)
458 if (align_jumps
<= 0)
461 if (align_functions
<= 0)
462 align_functions
= 16;
464 /* Acquire a unique set number for our register saves and restores. */
465 alpha_sr_alias_set
= new_alias_set ();
467 /* Register variables and functions with the garbage collector. */
469 /* Set up function hooks. */
470 init_machine_status
= alpha_init_machine_status
;
472 /* Tell the compiler when we're using VAX floating point. */
473 if (TARGET_FLOAT_VAX
)
475 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
476 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
477 REAL_MODE_FORMAT (TFmode
) = NULL
;
481 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
484 zap_mask (HOST_WIDE_INT value
)
488 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
490 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
496 /* Returns 1 if OP is either the constant zero or a register. If a
497 register, it must be in the proper mode unless MODE is VOIDmode. */
500 reg_or_0_operand (rtx op
, enum machine_mode mode
)
502 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
505 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
509 reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
511 return ((GET_CODE (op
) == CONST_INT
512 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
513 || register_operand (op
, mode
));
517 /* Return 1 if OP is an 8-bit constant or any register. */
520 reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
522 return ((GET_CODE (op
) == CONST_INT
523 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
524 || register_operand (op
, mode
));
527 /* Return 1 if OP is a constant or any register. */
530 reg_or_const_int_operand (rtx op
, enum machine_mode mode
)
532 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
535 /* Return 1 if OP is an 8-bit constant. */
538 cint8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
540 return ((GET_CODE (op
) == CONST_INT
541 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
544 /* Return 1 if the operand is a valid second operand to an add insn. */
547 add_operand (rtx op
, enum machine_mode mode
)
549 if (GET_CODE (op
) == CONST_INT
)
550 /* Constraints I, J, O and P are covered by K. */
551 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
552 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
554 return register_operand (op
, mode
);
557 /* Return 1 if the operand is a valid second operand to a sign-extending
561 sext_add_operand (rtx op
, enum machine_mode mode
)
563 if (GET_CODE (op
) == CONST_INT
)
564 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
565 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
567 return reg_not_elim_operand (op
, mode
);
570 /* Return 1 if OP is the constant 4 or 8. */
573 const48_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
575 return (GET_CODE (op
) == CONST_INT
576 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
579 /* Return 1 if OP is a valid first operand to an AND insn. */
582 and_operand (rtx op
, enum machine_mode mode
)
584 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
585 return (zap_mask (CONST_DOUBLE_LOW (op
))
586 && zap_mask (CONST_DOUBLE_HIGH (op
)));
588 if (GET_CODE (op
) == CONST_INT
)
589 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
590 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
591 || zap_mask (INTVAL (op
)));
593 return register_operand (op
, mode
);
596 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
599 or_operand (rtx op
, enum machine_mode mode
)
601 if (GET_CODE (op
) == CONST_INT
)
602 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
603 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
605 return register_operand (op
, mode
);
608 /* Return 1 if OP is a constant that is the width, in bits, of an integral
609 mode smaller than DImode. */
612 mode_width_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
614 return (GET_CODE (op
) == CONST_INT
615 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
616 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
619 /* Return 1 if OP is a constant that is the width of an integral machine mode
620 smaller than an integer. */
623 mode_mask_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
625 if (GET_CODE (op
) == CONST_INT
)
627 HOST_WIDE_INT value
= INTVAL (op
);
633 if (value
== 0xffffffff)
638 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
640 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
647 /* Return 1 if OP is a multiple of 8 less than 64. */
650 mul8_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
652 return (GET_CODE (op
) == CONST_INT
653 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
654 && (INTVAL (op
) & 7) == 0);
657 /* Return 1 if OP is the zero constant for MODE. */
660 const0_operand (rtx op
, enum machine_mode mode
)
662 return op
== CONST0_RTX (mode
);
665 /* Return 1 if OP is a hard floating-point register. */
668 hard_fp_register_operand (rtx op
, enum machine_mode mode
)
670 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
673 if (GET_CODE (op
) == SUBREG
)
674 op
= SUBREG_REG (op
);
675 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
678 /* Return 1 if OP is a hard general register. */
681 hard_int_register_operand (rtx op
, enum machine_mode mode
)
683 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
686 if (GET_CODE (op
) == SUBREG
)
687 op
= SUBREG_REG (op
);
688 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
691 /* Return 1 if OP is a register or a constant integer. */
695 reg_or_cint_operand (rtx op
, enum machine_mode mode
)
697 return (GET_CODE (op
) == CONST_INT
698 || register_operand (op
, mode
));
701 /* Return 1 if OP is something that can be reloaded into a register;
702 if it is a MEM, it need not be valid. */
705 some_operand (rtx op
, enum machine_mode mode
)
707 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
710 switch (GET_CODE (op
))
724 return some_operand (SUBREG_REG (op
), VOIDmode
);
733 /* Likewise, but don't accept constants. */
736 some_ni_operand (rtx op
, enum machine_mode mode
)
738 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
741 if (GET_CODE (op
) == SUBREG
)
742 op
= SUBREG_REG (op
);
744 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
747 /* Return 1 if OP is a valid operand for the source of a move insn. */
750 input_operand (rtx op
, enum machine_mode mode
)
752 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
755 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
758 switch (GET_CODE (op
))
763 if (TARGET_EXPLICIT_RELOCS
)
765 /* We don't split symbolic operands into something unintelligable
766 until after reload, but we do not wish non-small, non-global
767 symbolic operands to be reconstructed from their high/lo_sum
769 return (small_symbolic_operand (op
, mode
)
770 || global_symbolic_operand (op
, mode
)
771 || gotdtp_symbolic_operand (op
, mode
)
772 || gottp_symbolic_operand (op
, mode
));
775 /* This handles both the Windows/NT and OSF cases. */
776 return mode
== ptr_mode
|| mode
== DImode
;
779 return (TARGET_EXPLICIT_RELOCS
780 && local_symbolic_operand (XEXP (op
, 0), mode
));
787 if (register_operand (op
, mode
))
789 /* ... fall through ... */
791 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
792 && general_operand (op
, mode
));
796 return op
== CONST0_RTX (mode
);
799 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
811 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
812 file, and in the same section as the current function. */
815 samegp_function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
817 if (GET_CODE (op
) != SYMBOL_REF
)
820 /* Easy test for recursion. */
821 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
824 /* Functions that are not local can be overridden, and thus may
825 not share the same gp. */
826 if (! SYMBOL_REF_LOCAL_P (op
))
829 /* If -msmall-data is in effect, assume that there is only one GP
830 for the module, and so any local symbol has this property. We
831 need explicit relocations to be able to enforce this for symbols
832 not defined in this unit of translation, however. */
833 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
836 /* Functions that are not external are defined in this UoT,
837 and thus must share the same gp. */
838 return ! SYMBOL_REF_EXTERNAL_P (op
);
841 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
844 direct_call_operand (rtx op
, enum machine_mode mode
)
846 tree op_decl
, cfun_sec
, op_sec
;
848 /* Must share the same GP. */
849 if (!samegp_function_operand (op
, mode
))
852 /* If profiling is implemented via linker tricks, we can't jump
853 to the nogp alternate entry point. Note that current_function_profile
854 would not be correct, since that doesn't indicate if the target
855 function uses profiling. */
856 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
857 but is approximately correct for the OSF ABIs. Don't know
858 what to do for VMS, NT, or UMK. */
859 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
862 /* Must be a function. In some cases folks create thunks in static
863 data structures and then make calls to them. If we allow the
864 direct call, we'll get an error from the linker about !samegp reloc
865 against a symbol without a .prologue directive. */
866 if (!SYMBOL_REF_FUNCTION_P (op
))
869 /* Must be "near" so that the branch is assumed to reach. With
870 -msmall-text, this is assumed true of all local symbols. Since
871 we've already checked samegp, locality is already assured. */
872 if (TARGET_SMALL_TEXT
)
875 /* Otherwise, a decl is "near" if it is defined in the same section. */
876 if (flag_function_sections
)
879 op_decl
= SYMBOL_REF_DECL (op
);
880 if (DECL_ONE_ONLY (current_function_decl
)
881 || (op_decl
&& DECL_ONE_ONLY (op_decl
)))
884 cfun_sec
= DECL_SECTION_NAME (current_function_decl
);
885 op_sec
= op_decl
? DECL_SECTION_NAME (op_decl
) : NULL
;
886 return ((!cfun_sec
&& !op_sec
)
887 || (cfun_sec
&& op_sec
888 && strcmp (TREE_STRING_POINTER (cfun_sec
),
889 TREE_STRING_POINTER (op_sec
)) == 0));
892 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
893 a (non-tls) variable known to be defined in this file. */
896 local_symbolic_operand (rtx op
, enum machine_mode mode
)
898 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
901 if (GET_CODE (op
) == LABEL_REF
)
904 if (GET_CODE (op
) == CONST
905 && GET_CODE (XEXP (op
, 0)) == PLUS
906 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
907 op
= XEXP (XEXP (op
, 0), 0);
909 if (GET_CODE (op
) != SYMBOL_REF
)
912 return SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
915 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
916 known to be defined in this file in the small data area. */
919 small_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
921 if (! TARGET_SMALL_DATA
)
924 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
927 if (GET_CODE (op
) == CONST
928 && GET_CODE (XEXP (op
, 0)) == PLUS
929 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
930 op
= XEXP (XEXP (op
, 0), 0);
932 if (GET_CODE (op
) != SYMBOL_REF
)
935 /* ??? There's no encode_section_info equivalent for the rtl
936 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
937 if (CONSTANT_POOL_ADDRESS_P (op
))
938 return GET_MODE_SIZE (get_pool_mode (op
)) <= g_switch_value
;
940 return (SYMBOL_REF_LOCAL_P (op
)
941 && SYMBOL_REF_SMALL_P (op
)
942 && SYMBOL_REF_TLS_MODEL (op
) == 0);
945 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
946 not known (or known not) to be defined in this file. */
949 global_symbolic_operand (rtx op
, enum machine_mode mode
)
951 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
954 if (GET_CODE (op
) == CONST
955 && GET_CODE (XEXP (op
, 0)) == PLUS
956 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
957 op
= XEXP (XEXP (op
, 0), 0);
959 if (GET_CODE (op
) != SYMBOL_REF
)
962 return !SYMBOL_REF_LOCAL_P (op
) && !SYMBOL_REF_TLS_MODEL (op
);
965 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
968 call_operand (rtx op
, enum machine_mode mode
)
973 if (GET_CODE (op
) == REG
)
977 /* Disallow virtual registers to cope with pathological test cases
978 such as compile/930117-1.c in which the virtual reg decomposes
979 to the frame pointer. Which is a hard reg that is not $27. */
980 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
985 if (TARGET_ABI_UNICOSMK
)
987 if (GET_CODE (op
) == SYMBOL_REF
)
993 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
994 possibly with an offset. */
997 symbolic_operand (rtx op
, enum machine_mode mode
)
999 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1001 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1003 if (GET_CODE (op
) == CONST
1004 && GET_CODE (XEXP (op
,0)) == PLUS
1005 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1006 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1011 /* Return true if OP is valid for a particular TLS relocation. */
1014 tls_symbolic_operand_1 (rtx op
, enum machine_mode mode
, int size
, int unspec
)
1016 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1019 if (GET_CODE (op
) != CONST
)
1023 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1025 op
= XVECEXP (op
, 0, 0);
1027 if (GET_CODE (op
) != SYMBOL_REF
)
1030 if (SYMBOL_REF_LOCAL_P (op
))
1032 if (alpha_tls_size
> size
)
1041 switch (SYMBOL_REF_TLS_MODEL (op
))
1043 case TLS_MODEL_LOCAL_DYNAMIC
:
1044 return unspec
== UNSPEC_DTPREL
;
1045 case TLS_MODEL_INITIAL_EXEC
:
1046 return unspec
== UNSPEC_TPREL
&& size
== 64;
1047 case TLS_MODEL_LOCAL_EXEC
:
1048 return unspec
== UNSPEC_TPREL
;
1054 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1057 dtp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1059 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1062 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1065 dtp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1067 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1070 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1073 gotdtp_symbolic_operand (rtx op
, enum machine_mode mode
)
1075 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1078 /* Return true if OP is valid for 16-bit TP relative relocations. */
1081 tp16_symbolic_operand (rtx op
, enum machine_mode mode
)
1083 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1086 /* Return true if OP is valid for 32-bit TP relative relocations. */
1089 tp32_symbolic_operand (rtx op
, enum machine_mode mode
)
1091 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1094 /* Return true if OP is valid for 64-bit TP relative relocations. */
1097 gottp_symbolic_operand (rtx op
, enum machine_mode mode
)
1099 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1102 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1103 comparisons are valid in which insn. */
1106 alpha_comparison_operator (rtx op
, enum machine_mode mode
)
1108 enum rtx_code code
= GET_CODE (op
);
1110 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1113 return (code
== EQ
|| code
== LE
|| code
== LT
1114 || code
== LEU
|| code
== LTU
);
1117 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1118 Here we know which comparisons are valid in which insn. */
1121 alpha_zero_comparison_operator (rtx op
, enum machine_mode mode
)
1123 enum rtx_code code
= GET_CODE (op
);
1125 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1128 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1129 || code
== LEU
|| code
== LTU
);
1132 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1135 alpha_swapped_comparison_operator (rtx op
, enum machine_mode mode
)
1137 enum rtx_code code
= GET_CODE (op
);
1139 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1140 || GET_RTX_CLASS (code
) != '<')
1143 code
= swap_condition (code
);
1144 return (code
== EQ
|| code
== LE
|| code
== LT
1145 || code
== LEU
|| code
== LTU
);
1148 /* Return 1 if OP is a signed comparison operation. */
1151 signed_comparison_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1153 enum rtx_code code
= GET_CODE (op
);
1155 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1158 return (code
== EQ
|| code
== NE
1159 || code
== LE
|| code
== LT
1160 || code
== GE
|| code
== GT
);
1163 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1164 Here we know which comparisons are valid in which insn. */
1167 alpha_fp_comparison_operator (rtx op
, enum machine_mode mode
)
1169 enum rtx_code code
= GET_CODE (op
);
1171 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1174 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1177 /* Return 1 if this is a divide or modulus operator. */
1180 divmod_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1182 enum rtx_code code
= GET_CODE (op
);
1184 return (code
== DIV
|| code
== MOD
|| code
== UDIV
|| code
== UMOD
);
1187 /* Return 1 if this is a float->int conversion operator. */
1190 fix_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1192 enum rtx_code code
= GET_CODE (op
);
1194 return (code
== FIX
|| code
== UNSIGNED_FIX
);
1197 /* Return 1 if this memory address is a known aligned register plus
1198 a constant. It must be a valid address. This means that we can do
1199 this as an aligned reference plus some offset.
1201 Take into account what reload will do. */
1204 aligned_memory_operand (rtx op
, enum machine_mode mode
)
1208 if (reload_in_progress
)
1211 if (GET_CODE (tmp
) == SUBREG
)
1212 tmp
= SUBREG_REG (tmp
);
1213 if (GET_CODE (tmp
) == REG
1214 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1216 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1222 if (GET_CODE (op
) != MEM
1223 || GET_MODE (op
) != mode
)
1227 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1228 sorts of constructs. Dig for the real base register. */
1229 if (reload_in_progress
1230 && GET_CODE (op
) == PLUS
1231 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1232 base
= XEXP (XEXP (op
, 0), 0);
1235 if (! memory_address_p (mode
, op
))
1237 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1240 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1243 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1246 unaligned_memory_operand (rtx op
, enum machine_mode mode
)
1250 if (reload_in_progress
)
1253 if (GET_CODE (tmp
) == SUBREG
)
1254 tmp
= SUBREG_REG (tmp
);
1255 if (GET_CODE (tmp
) == REG
1256 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1258 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1264 if (GET_CODE (op
) != MEM
1265 || GET_MODE (op
) != mode
)
1269 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1270 sorts of constructs. Dig for the real base register. */
1271 if (reload_in_progress
1272 && GET_CODE (op
) == PLUS
1273 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1274 base
= XEXP (XEXP (op
, 0), 0);
1277 if (! memory_address_p (mode
, op
))
1279 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1282 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1285 /* Return 1 if OP is either a register or an unaligned memory location. */
1288 reg_or_unaligned_mem_operand (rtx op
, enum machine_mode mode
)
1290 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1293 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1296 any_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1298 return (GET_CODE (op
) == MEM
1299 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1300 || (reload_in_progress
&& GET_CODE (op
) == REG
1301 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1302 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1303 && GET_CODE (SUBREG_REG (op
)) == REG
1304 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1307 /* Returns 1 if OP is not an eliminable register.
1309 This exists to cure a pathological abort in the s8addq (et al) patterns,
1311 long foo () { long t; bar(); return (long) &t * 26107; }
1313 which run afoul of a hack in reload to cure a (presumably) similar
1314 problem with lea-type instructions on other targets. But there is
1315 one of us and many of them, so work around the problem by selectively
1316 preventing combine from making the optimization. */
1319 reg_not_elim_operand (rtx op
, enum machine_mode mode
)
1322 if (GET_CODE (op
) == SUBREG
)
1323 inner
= SUBREG_REG (op
);
1324 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1327 return register_operand (op
, mode
);
1330 /* Return 1 is OP is a memory location that is not a reference (using
1331 an AND) to an unaligned location. Take into account what reload
1335 normal_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1337 if (reload_in_progress
)
1340 if (GET_CODE (tmp
) == SUBREG
)
1341 tmp
= SUBREG_REG (tmp
);
1342 if (GET_CODE (tmp
) == REG
1343 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1345 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1347 /* This may not have been assigned an equivalent address if it will
1348 be eliminated. In that case, it doesn't matter what we do. */
1354 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1357 /* Accept a register, but not a subreg of any kind. This allows us to
1358 avoid pathological cases in reload wrt data movement common in
1359 int->fp conversion. */
1362 reg_no_subreg_operand (rtx op
, enum machine_mode mode
)
1364 if (GET_CODE (op
) != REG
)
1366 return register_operand (op
, mode
);
1369 /* Recognize an addition operation that includes a constant. Used to
1370 convince reload to canonize (plus (plus reg c1) c2) during register
1374 addition_operation (rtx op
, enum machine_mode mode
)
1376 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1378 if (GET_CODE (op
) == PLUS
1379 && register_operand (XEXP (op
, 0), mode
)
1380 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1381 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1386 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1387 the range defined for C in [I-P]. */
1390 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
1395 /* An unsigned 8 bit constant. */
1396 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1398 /* The constant zero. */
1401 /* A signed 16 bit constant. */
1402 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1404 /* A shifted signed 16 bit constant appropriate for LDAH. */
1405 return ((value
& 0xffff) == 0
1406 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1408 /* A constant that can be AND'ed with using a ZAP insn. */
1409 return zap_mask (value
);
1411 /* A complemented unsigned 8 bit constant. */
1412 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1414 /* A negated unsigned 8 bit constant. */
1415 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1417 /* The constant 1, 2 or 3. */
1418 return value
== 1 || value
== 2 || value
== 3;
1425 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1426 matches for C in [GH]. */
1429 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
1434 /* The floating point zero constant. */
1435 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1436 && value
== CONST0_RTX (GET_MODE (value
)));
1439 /* A valid operand of a ZAP insn. */
1440 return (GET_MODE (value
) == VOIDmode
1441 && zap_mask (CONST_DOUBLE_LOW (value
))
1442 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1449 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1453 alpha_extra_constraint (rtx value
, int c
)
1458 return normal_memory_operand (value
, VOIDmode
);
1460 return direct_call_operand (value
, Pmode
);
1462 return (GET_CODE (value
) == CONST_INT
1463 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1465 return GET_CODE (value
) == HIGH
;
1467 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1469 return (GET_CODE (value
) == CONST_VECTOR
1470 && value
== CONST0_RTX (GET_MODE (value
)));
1476 /* Return 1 if this function can directly return via $26. */
1479 direct_return (void)
1481 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1483 && alpha_sa_size () == 0
1484 && get_frame_size () == 0
1485 && current_function_outgoing_args_size
== 0
1486 && current_function_pretend_args_size
== 0);
1489 /* Return the ADDR_VEC associated with a tablejump insn. */
1492 alpha_tablejump_addr_vec (rtx insn
)
1496 tmp
= JUMP_LABEL (insn
);
1499 tmp
= NEXT_INSN (tmp
);
1502 if (GET_CODE (tmp
) == JUMP_INSN
1503 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1504 return PATTERN (tmp
);
1508 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1511 alpha_tablejump_best_label (rtx insn
)
1513 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1514 rtx best_label
= NULL_RTX
;
1516 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1517 there for edge frequency counts from profile data. */
1521 int n_labels
= XVECLEN (jump_table
, 1);
1522 int best_count
= -1;
1525 for (i
= 0; i
< n_labels
; i
++)
1529 for (j
= i
+ 1; j
< n_labels
; j
++)
1530 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1531 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1534 if (count
> best_count
)
1535 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1539 return best_label
? best_label
: const0_rtx
;
1542 /* Return the TLS model to use for SYMBOL. */
1544 static enum tls_model
1545 tls_symbolic_operand_type (rtx symbol
)
1547 enum tls_model model
;
1549 if (GET_CODE (symbol
) != SYMBOL_REF
)
1551 model
= SYMBOL_REF_TLS_MODEL (symbol
);
1553 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1554 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
1555 model
= TLS_MODEL_INITIAL_EXEC
;
1560 /* Return true if the function DECL will share the same GP as any
1561 function in the current unit of translation. */
1564 decl_has_samegp (tree decl
)
1566 /* Functions that are not local can be overridden, and thus may
1567 not share the same gp. */
1568 if (!(*targetm
.binds_local_p
) (decl
))
1571 /* If -msmall-data is in effect, assume that there is only one GP
1572 for the module, and so any local symbol has this property. We
1573 need explicit relocations to be able to enforce this for symbols
1574 not defined in this unit of translation, however. */
1575 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1578 /* Functions that are not external are defined in this UoT. */
1579 /* ??? Irritatingly, static functions not yet emitted are still
1580 marked "external". Apply this to non-static functions only. */
1581 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1584 /* Return true if EXP should be placed in the small data section. */
1587 alpha_in_small_data_p (tree exp
)
1589 /* We want to merge strings, so we never consider them small data. */
1590 if (TREE_CODE (exp
) == STRING_CST
)
1593 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1595 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1596 if (strcmp (section
, ".sdata") == 0
1597 || strcmp (section
, ".sbss") == 0)
1602 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1604 /* If this is an incomplete type with size 0, then we can't put it
1605 in sdata because it might be too big when completed. */
1606 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
1613 #if TARGET_ABI_OPEN_VMS
1615 alpha_linkage_symbol_p (const char *symname
)
1617 int symlen
= strlen (symname
);
1620 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1625 #define LINKAGE_SYMBOL_REF_P(X) \
1626 ((GET_CODE (X) == SYMBOL_REF \
1627 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1628 || (GET_CODE (X) == CONST \
1629 && GET_CODE (XEXP (X, 0)) == PLUS \
1630 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1631 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1634 /* legitimate_address_p recognizes an RTL expression that is a valid
1635 memory address for an instruction. The MODE argument is the
1636 machine mode for the MEM expression that wants to use this address.
1638 For Alpha, we have either a constant address or the sum of a
1639 register and a constant address, or just a register. For DImode,
1640 any of those forms can be surrounded with an AND that clear the
1641 low-order three bits; this is an "unaligned" access. */
1644 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1646 /* If this is an ldq_u type address, discard the outer AND. */
1648 && GET_CODE (x
) == AND
1649 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1650 && INTVAL (XEXP (x
, 1)) == -8)
1653 /* Discard non-paradoxical subregs. */
1654 if (GET_CODE (x
) == SUBREG
1655 && (GET_MODE_SIZE (GET_MODE (x
))
1656 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1659 /* Unadorned general registers are valid. */
1662 ? STRICT_REG_OK_FOR_BASE_P (x
)
1663 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1666 /* Constant addresses (i.e. +/- 32k) are valid. */
1667 if (CONSTANT_ADDRESS_P (x
))
1670 #if TARGET_ABI_OPEN_VMS
1671 if (LINKAGE_SYMBOL_REF_P (x
))
1675 /* Register plus a small constant offset is valid. */
1676 if (GET_CODE (x
) == PLUS
)
1678 rtx ofs
= XEXP (x
, 1);
1681 /* Discard non-paradoxical subregs. */
1682 if (GET_CODE (x
) == SUBREG
1683 && (GET_MODE_SIZE (GET_MODE (x
))
1684 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1690 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1691 && GET_CODE (ofs
) == CONST_INT
)
1694 ? STRICT_REG_OK_FOR_BASE_P (x
)
1695 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1696 && CONSTANT_ADDRESS_P (ofs
))
1699 else if (GET_CODE (x
) == ADDRESSOF
1700 && GET_CODE (ofs
) == CONST_INT
)
1704 /* If we're managing explicit relocations, LO_SUM is valid, as
1705 are small data symbols. */
1706 else if (TARGET_EXPLICIT_RELOCS
)
1708 if (small_symbolic_operand (x
, Pmode
))
1711 if (GET_CODE (x
) == LO_SUM
)
1713 rtx ofs
= XEXP (x
, 1);
1716 /* Discard non-paradoxical subregs. */
1717 if (GET_CODE (x
) == SUBREG
1718 && (GET_MODE_SIZE (GET_MODE (x
))
1719 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1722 /* Must have a valid base register. */
1725 ? STRICT_REG_OK_FOR_BASE_P (x
)
1726 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1729 /* The symbol must be local. */
1730 if (local_symbolic_operand (ofs
, Pmode
)
1731 || dtp32_symbolic_operand (ofs
, Pmode
)
1732 || tp32_symbolic_operand (ofs
, Pmode
))
1740 /* Build the SYMBOL_REF for __tls_get_addr. */
1742 static GTY(()) rtx tls_get_addr_libfunc
;
1745 get_tls_get_addr (void)
1747 if (!tls_get_addr_libfunc
)
1748 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
1749 return tls_get_addr_libfunc
;
1752 /* Try machine-dependent ways of modifying an illegitimate address
1753 to be legitimate. If we find one, return the new, valid address. */
1756 alpha_legitimize_address (rtx x
, rtx scratch
,
1757 enum machine_mode mode ATTRIBUTE_UNUSED
)
1759 HOST_WIDE_INT addend
;
1761 /* If the address is (plus reg const_int) and the CONST_INT is not a
1762 valid offset, compute the high part of the constant and add it to
1763 the register. Then our address is (plus temp low-part-const). */
1764 if (GET_CODE (x
) == PLUS
1765 && GET_CODE (XEXP (x
, 0)) == REG
1766 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1767 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1769 addend
= INTVAL (XEXP (x
, 1));
1774 /* If the address is (const (plus FOO const_int)), find the low-order
1775 part of the CONST_INT. Then load FOO plus any high-order part of the
1776 CONST_INT into a register. Our address is (plus reg low-part-const).
1777 This is done to reduce the number of GOT entries. */
1779 && GET_CODE (x
) == CONST
1780 && GET_CODE (XEXP (x
, 0)) == PLUS
1781 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1783 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1784 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1788 /* If we have a (plus reg const), emit the load as in (2), then add
1789 the two registers, and finally generate (plus reg low-part-const) as
1792 && GET_CODE (x
) == PLUS
1793 && GET_CODE (XEXP (x
, 0)) == REG
1794 && GET_CODE (XEXP (x
, 1)) == CONST
1795 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1796 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1798 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1799 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1800 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1801 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1805 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1806 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1808 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1810 switch (tls_symbolic_operand_type (x
))
1812 case TLS_MODEL_GLOBAL_DYNAMIC
:
1815 r0
= gen_rtx_REG (Pmode
, 0);
1816 r16
= gen_rtx_REG (Pmode
, 16);
1817 tga
= get_tls_get_addr ();
1818 dest
= gen_reg_rtx (Pmode
);
1819 seq
= GEN_INT (alpha_next_sequence_number
++);
1821 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1822 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1823 insn
= emit_call_insn (insn
);
1824 CONST_OR_PURE_CALL_P (insn
) = 1;
1825 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1827 insn
= get_insns ();
1830 emit_libcall_block (insn
, dest
, r0
, x
);
1833 case TLS_MODEL_LOCAL_DYNAMIC
:
1836 r0
= gen_rtx_REG (Pmode
, 0);
1837 r16
= gen_rtx_REG (Pmode
, 16);
1838 tga
= get_tls_get_addr ();
1839 scratch
= gen_reg_rtx (Pmode
);
1840 seq
= GEN_INT (alpha_next_sequence_number
++);
1842 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1843 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1844 insn
= emit_call_insn (insn
);
1845 CONST_OR_PURE_CALL_P (insn
) = 1;
1846 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1848 insn
= get_insns ();
1851 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1852 UNSPEC_TLSLDM_CALL
);
1853 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1855 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1856 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1858 if (alpha_tls_size
== 64)
1860 dest
= gen_reg_rtx (Pmode
);
1861 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1862 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1865 if (alpha_tls_size
== 32)
1867 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1868 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1869 scratch
= gen_reg_rtx (Pmode
);
1870 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1872 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1874 case TLS_MODEL_INITIAL_EXEC
:
1875 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1876 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1877 tp
= gen_reg_rtx (Pmode
);
1878 scratch
= gen_reg_rtx (Pmode
);
1879 dest
= gen_reg_rtx (Pmode
);
1881 emit_insn (gen_load_tp (tp
));
1882 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1883 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1886 case TLS_MODEL_LOCAL_EXEC
:
1887 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1888 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1889 tp
= gen_reg_rtx (Pmode
);
1891 emit_insn (gen_load_tp (tp
));
1892 if (alpha_tls_size
== 32)
1894 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1895 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1896 tp
= gen_reg_rtx (Pmode
);
1897 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1899 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1902 if (local_symbolic_operand (x
, Pmode
))
1904 if (small_symbolic_operand (x
, Pmode
))
1908 if (!no_new_pseudos
)
1909 scratch
= gen_reg_rtx (Pmode
);
1910 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1911 gen_rtx_HIGH (Pmode
, x
)));
1912 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1921 HOST_WIDE_INT low
, high
;
1923 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1925 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1929 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1930 (no_new_pseudos
? scratch
: NULL_RTX
),
1931 1, OPTAB_LIB_WIDEN
);
1933 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1934 (no_new_pseudos
? scratch
: NULL_RTX
),
1935 1, OPTAB_LIB_WIDEN
);
1937 return plus_constant (x
, low
);
1941 /* We do not allow indirect calls to be optimized into sibling calls, nor
1942 can we allow a call to a function with a different GP to be optimized
1946 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1948 /* Can't do indirect tail calls, since we don't know if the target
1949 uses the same GP. */
1953 /* Otherwise, we can make a tail call if the target function shares
1955 return decl_has_samegp (decl
);
1958 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1959 small symbolic operand until after reload. At which point we need
1960 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1961 so that sched2 has the proper dependency information. */
1964 some_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1968 /* Don't re-split. */
1969 if (GET_CODE (x
) == LO_SUM
)
1972 return small_symbolic_operand (x
, Pmode
) != 0;
1976 some_small_symbolic_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1978 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
1982 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1986 /* Don't re-split. */
1987 if (GET_CODE (x
) == LO_SUM
)
1990 if (small_symbolic_operand (x
, Pmode
))
1992 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2001 split_small_symbolic_operand (rtx x
)
2004 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2008 /* Indicate that INSN cannot be duplicated. This is true for any insn
2009 that we've marked with gpdisp relocs, since those have to stay in
2010 1-1 correspondence with one another.
2012 Technically we could copy them if we could set up a mapping from one
2013 sequence number to another, across the set of insns to be duplicated.
2014 This seems overly complicated and error-prone since interblock motion
2015 from sched-ebb could move one of the pair of insns to a different block.
2017 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2018 then they'll be in a different block from their ldgp. Which could lead
2019 the bb reorder code to think that it would be ok to copy just the block
2020 containing the call and branch to the block containing the ldgp. */
2023 alpha_cannot_copy_insn_p (rtx insn
)
2025 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
2027 if (recog_memoized (insn
) >= 0)
2028 return get_attr_cannot_copy (insn
);
2034 /* Try a machine-dependent way of reloading an illegitimate address
2035 operand. If we find one, push the reload and return the new rtx. */
2038 alpha_legitimize_reload_address (rtx x
,
2039 enum machine_mode mode ATTRIBUTE_UNUSED
,
2040 int opnum
, int type
,
2041 int ind_levels ATTRIBUTE_UNUSED
)
2043 /* We must recognize output that we have already generated ourselves. */
2044 if (GET_CODE (x
) == PLUS
2045 && GET_CODE (XEXP (x
, 0)) == PLUS
2046 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2047 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2048 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2050 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2051 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2056 /* We wish to handle large displacements off a base register by
2057 splitting the addend across an ldah and the mem insn. This
2058 cuts number of extra insns needed from 3 to 1. */
2059 if (GET_CODE (x
) == PLUS
2060 && GET_CODE (XEXP (x
, 0)) == REG
2061 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2062 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2063 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2065 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2066 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2068 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2070 /* Check for 32-bit overflow. */
2071 if (high
+ low
!= val
)
2074 /* Reload the high part into a base reg; leave the low part
2075 in the mem directly. */
2076 x
= gen_rtx_PLUS (GET_MODE (x
),
2077 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2081 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2082 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2090 /* Compute a (partial) cost for rtx X. Return true if the complete
2091 cost has been computed, and false if subexpressions should be
2092 scanned. In either case, *TOTAL contains the cost result. */
2095 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2097 enum machine_mode mode
= GET_MODE (x
);
2098 bool float_mode_p
= FLOAT_MODE_P (mode
);
2102 /* If this is an 8-bit constant, return zero since it can be used
2103 nearly anywhere with no cost. If it is a valid operand for an
2104 ADD or AND, likewise return 0 if we know it will be used in that
2105 context. Otherwise, return 2 since it might be used there later.
2106 All other constants take at least two insns. */
2108 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2116 if (x
== CONST0_RTX (mode
))
2118 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2119 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2121 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2124 *total
= COSTS_N_INSNS (2);
2130 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2131 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2132 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2133 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2134 else if (tls_symbolic_operand_type (x
))
2135 /* Estimate of cost for call_pal rduniq. */
2136 *total
= COSTS_N_INSNS (15);
2138 /* Otherwise we do a load from the GOT. */
2139 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2145 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2146 else if (GET_CODE (XEXP (x
, 0)) == MULT
2147 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2149 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2150 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2157 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2158 else if (mode
== DImode
)
2159 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2161 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2165 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2166 && INTVAL (XEXP (x
, 1)) <= 3)
2168 *total
= COSTS_N_INSNS (1);
2175 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2180 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2182 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2190 *total
= COSTS_N_INSNS (70); /* ??? */
2191 else if (mode
== SFmode
)
2192 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2194 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2198 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2204 *total
= COSTS_N_INSNS (1);
2212 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2218 case UNSIGNED_FLOAT
:
2222 case FLOAT_TRUNCATE
:
2223 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2231 /* REF is an alignable memory location. Place an aligned SImode
2232 reference into *PALIGNED_MEM and the number of bits to shift into
2233 *PBITNUM. SCRATCH is a free register for use in reloading out
2234 of range stack slots. */
2237 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
2240 HOST_WIDE_INT offset
= 0;
2242 if (GET_CODE (ref
) != MEM
)
2245 if (reload_in_progress
2246 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2248 base
= find_replacement (&XEXP (ref
, 0));
2250 if (! memory_address_p (GET_MODE (ref
), base
))
2255 base
= XEXP (ref
, 0);
2258 if (GET_CODE (base
) == PLUS
)
2259 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2262 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2264 if (WORDS_BIG_ENDIAN
)
2265 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2266 + (offset
& 3) * 8));
2268 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2271 /* Similar, but just get the address. Handle the two reload cases.
2272 Add EXTRA_OFFSET to the address we return. */
2275 get_unaligned_address (rtx ref
, int extra_offset
)
2278 HOST_WIDE_INT offset
= 0;
2280 if (GET_CODE (ref
) != MEM
)
2283 if (reload_in_progress
2284 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2286 base
= find_replacement (&XEXP (ref
, 0));
2288 if (! memory_address_p (GET_MODE (ref
), base
))
2293 base
= XEXP (ref
, 0);
2296 if (GET_CODE (base
) == PLUS
)
2297 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2299 return plus_constant (base
, offset
+ extra_offset
);
2302 /* On the Alpha, all (non-symbolic) constants except zero go into
2303 a floating-point register via memory. Note that we cannot
2304 return anything that is not a subset of CLASS, and that some
2305 symbolic constants cannot be dropped to memory. */
2308 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
2310 /* Zero is present in any register class. */
2311 if (x
== CONST0_RTX (GET_MODE (x
)))
2314 /* These sorts of constants we can easily drop to memory. */
2315 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2317 if (class == FLOAT_REGS
)
2319 if (class == ALL_REGS
)
2320 return GENERAL_REGS
;
2324 /* All other kinds of constants should not (and in the case of HIGH
2325 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2326 secondary reload. */
2328 return (class == ALL_REGS
? GENERAL_REGS
: class);
2333 /* Loading and storing HImode or QImode values to and from memory
2334 usually requires a scratch register. The exceptions are loading
2335 QImode and HImode from an aligned address to a general register
2336 unless byte instructions are permitted.
2338 We also cannot load an unaligned address or a paradoxical SUBREG
2339 into an FP register.
2341 We also cannot do integral arithmetic into FP regs, as might result
2342 from register elimination into a DImode fp register. */
2345 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
2348 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2350 if (GET_CODE (x
) == MEM
2351 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2352 || (GET_CODE (x
) == SUBREG
2353 && (GET_CODE (SUBREG_REG (x
)) == MEM
2354 || (GET_CODE (SUBREG_REG (x
)) == REG
2355 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2357 if (!in
|| !aligned_memory_operand(x
, mode
))
2358 return GENERAL_REGS
;
2362 if (class == FLOAT_REGS
)
2364 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2365 return GENERAL_REGS
;
2367 if (GET_CODE (x
) == SUBREG
2368 && (GET_MODE_SIZE (GET_MODE (x
))
2369 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2370 return GENERAL_REGS
;
2372 if (in
&& INTEGRAL_MODE_P (mode
)
2373 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2374 return GENERAL_REGS
;
2380 /* Subfunction of the following function. Update the flags of any MEM
2381 found in part of X. */
2384 alpha_set_memflags_1 (rtx x
, int in_struct_p
, int volatile_p
, int unchanging_p
)
2388 switch (GET_CODE (x
))
2394 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2395 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2400 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2405 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2407 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2412 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2413 MEM_VOLATILE_P (x
) = volatile_p
;
2414 RTX_UNCHANGING_P (x
) = unchanging_p
;
2415 /* Sadly, we cannot use alias sets because the extra aliasing
2416 produced by the AND interferes. Given that two-byte quantities
2417 are the only thing we would be able to differentiate anyway,
2418 there does not seem to be any point in convoluting the early
2419 out of the alias check. */
2427 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2428 generated to perform a memory operation, look for any MEMs in either
2429 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2430 volatile flags from REF into each of the MEMs found. If REF is not
2431 a MEM, don't do anything. */
2434 alpha_set_memflags (rtx insn
, rtx ref
)
2436 int in_struct_p
, volatile_p
, unchanging_p
;
2438 if (GET_CODE (ref
) != MEM
)
2441 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2442 volatile_p
= MEM_VOLATILE_P (ref
);
2443 unchanging_p
= RTX_UNCHANGING_P (ref
);
2445 /* This is only called from alpha.md, after having had something
2446 generated from one of the insn patterns. So if everything is
2447 zero, the pattern is already up-to-date. */
2448 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2451 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2454 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2457 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
2458 HOST_WIDE_INT c
, int n
)
2462 /* Use a pseudo if highly optimizing and still generating RTL. */
2464 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2467 /* If this is a sign-extended 32-bit constant, we can do this in at most
2468 three insns, so do it if we have enough insns left. We always have
2469 a sign-extended 32-bit constant when compiling on a narrow machine. */
2471 if (HOST_BITS_PER_WIDE_INT
!= 64
2472 || c
>> 31 == -1 || c
>> 31 == 0)
2474 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2475 HOST_WIDE_INT tmp1
= c
- low
;
2476 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2477 HOST_WIDE_INT extra
= 0;
2479 /* If HIGH will be interpreted as negative but the constant is
2480 positive, we must adjust it to do two ldha insns. */
2482 if ((high
& 0x8000) != 0 && c
>= 0)
2486 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2489 if (c
== low
|| (low
== 0 && extra
== 0))
2491 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2492 but that meant that we can't handle INT_MIN on 32-bit machines
2493 (like NT/Alpha), because we recurse indefinitely through
2494 emit_move_insn to gen_movdi. So instead, since we know exactly
2495 what we want, create it explicitly. */
2498 target
= gen_reg_rtx (mode
);
2499 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2502 else if (n
>= 2 + (extra
!= 0))
2504 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2506 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2507 This means that if we go through expand_binop, we'll try to
2508 generate extensions, etc, which will require new pseudos, which
2509 will fail during some split phases. The SImode add patterns
2510 still exist, but are not named. So build the insns by hand. */
2515 subtarget
= gen_reg_rtx (mode
);
2516 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2517 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2523 target
= gen_reg_rtx (mode
);
2524 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2525 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2531 /* If we couldn't do it that way, try some other methods. But if we have
2532 no instructions left, don't bother. Likewise, if this is SImode and
2533 we can't make pseudos, we can't do anything since the expand_binop
2534 and expand_unop calls will widen and try to make pseudos. */
2536 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2539 /* Next, see if we can load a related constant and then shift and possibly
2540 negate it to get the constant we want. Try this once each increasing
2541 numbers of insns. */
2543 for (i
= 1; i
< n
; i
++)
2545 /* First, see if minus some low bits, we've an easy load of
2548 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2550 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2551 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2552 target
, 0, OPTAB_WIDEN
);
2554 /* Next try complementing. */
2555 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2556 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2558 /* Next try to form a constant and do a left shift. We can do this
2559 if some low-order bits are zero; the exact_log2 call below tells
2560 us that information. The bits we are shifting out could be any
2561 value, but here we'll just try the 0- and sign-extended forms of
2562 the constant. To try to increase the chance of having the same
2563 constant in more than one insn, start at the highest number of
2564 bits to shift, but try all possibilities in case a ZAPNOT will
2567 if ((bits
= exact_log2 (c
& - c
)) > 0)
2568 for (; bits
> 0; bits
--)
2569 if ((temp
= (alpha_emit_set_const
2570 (subtarget
, mode
, c
>> bits
, i
))) != 0
2571 || ((temp
= (alpha_emit_set_const
2573 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2575 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2576 target
, 0, OPTAB_WIDEN
);
2578 /* Now try high-order zero bits. Here we try the shifted-in bits as
2579 all zero and all ones. Be careful to avoid shifting outside the
2580 mode and to avoid shifting outside the host wide int size. */
2581 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2582 confuse the recursive call and set all of the high 32 bits. */
2584 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2585 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2586 for (; bits
> 0; bits
--)
2587 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2589 || ((temp
= (alpha_emit_set_const
2591 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2594 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2595 target
, 1, OPTAB_WIDEN
);
2597 /* Now try high-order 1 bits. We get that with a sign-extension.
2598 But one bit isn't enough here. Be careful to avoid shifting outside
2599 the mode and to avoid shifting outside the host wide int size. */
2601 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2602 - floor_log2 (~ c
) - 2)) > 0)
2603 for (; bits
> 0; bits
--)
2604 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2606 || ((temp
= (alpha_emit_set_const
2608 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2611 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2612 target
, 0, OPTAB_WIDEN
);
2615 #if HOST_BITS_PER_WIDE_INT == 64
2616 /* Finally, see if can load a value into the target that is the same as the
2617 constant except that all bytes that are 0 are changed to be 0xff. If we
2618 can, then we can do a ZAPNOT to obtain the desired constant. */
2621 for (i
= 0; i
< 64; i
+= 8)
2622 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2623 new |= (HOST_WIDE_INT
) 0xff << i
;
2625 /* We are only called for SImode and DImode. If this is SImode, ensure that
2626 we are sign extended to a full word. */
2629 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2631 if (new != c
&& new != -1
2632 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2633 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2634 target
, 0, OPTAB_WIDEN
);
2640 /* Try to output insns to set TARGET equal to the constant C if it can be
2641 done in less than N insns. Do all computations in MODE. Returns the place
2642 where the output has been placed if it can be done and the insns have been
2643 emitted. If it would take more than N insns, zero is returned and no
2644 insns and emitted. */
2647 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
2648 HOST_WIDE_INT c
, int n
)
2651 rtx orig_target
= target
;
2654 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2655 can't load this constant in one insn, do this in DImode. */
2656 if (no_new_pseudos
&& mode
== SImode
2657 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2658 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2660 target
= gen_lowpart (DImode
, target
);
2664 /* Try 1 insn, then 2, then up to N. */
2665 for (i
= 1; i
<= n
; i
++)
2667 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2670 rtx insn
= get_last_insn ();
2671 rtx set
= single_set (insn
);
2672 if (! CONSTANT_P (SET_SRC (set
)))
2673 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2678 /* Allow for the case where we changed the mode of TARGET. */
2679 if (result
== target
)
2680 result
= orig_target
;
2685 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2686 fall back to a straight forward decomposition. We do this to avoid
2687 exponential run times encountered when looking for longer sequences
2688 with alpha_emit_set_const. */
2691 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2693 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2695 /* Decompose the entire word */
2696 #if HOST_BITS_PER_WIDE_INT >= 64
2697 if (c2
!= -(c1
< 0))
2699 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2701 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2702 c1
= (c1
- d2
) >> 32;
2703 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2705 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2709 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2711 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2715 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2717 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2722 /* Construct the high word */
2725 emit_move_insn (target
, GEN_INT (d4
));
2727 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2730 emit_move_insn (target
, GEN_INT (d3
));
2732 /* Shift it into place */
2733 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2735 /* Add in the low bits. */
2737 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2739 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2744 /* Expand a move instruction; return true if all work is done.
2745 We don't handle non-bwx subword loads here. */
2748 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2750 /* If the output is not a register, the input must be. */
2751 if (GET_CODE (operands
[0]) == MEM
2752 && ! reg_or_0_operand (operands
[1], mode
))
2753 operands
[1] = force_reg (mode
, operands
[1]);
2755 /* Allow legitimize_address to perform some simplifications. */
2756 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2760 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2761 compiled at the end of compilation. In the meantime, someone can
2762 re-encode-section-info on some symbol changing it e.g. from global
2763 to local-not-small. If this happens, we'd have emitted a plain
2764 load rather than a high+losum load and not recognize the insn.
2766 So if rtl inlining is in effect, we delay the global/not-global
2767 decision until rest_of_compilation by wrapping it in an
2769 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2770 && rtx_equal_function_value_matters
2771 && global_symbolic_operand (operands
[1], mode
))
2773 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2777 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2780 if (tmp
== operands
[0])
2787 /* Early out for non-constants and valid constants. */
2788 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2791 /* Split large integers. */
2792 if (GET_CODE (operands
[1]) == CONST_INT
2793 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2795 HOST_WIDE_INT i0
, i1
;
2796 rtx temp
= NULL_RTX
;
2798 if (GET_CODE (operands
[1]) == CONST_INT
)
2800 i0
= INTVAL (operands
[1]);
2803 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2805 i0
= CONST_DOUBLE_LOW (operands
[1]);
2810 i0
= CONST_DOUBLE_LOW (operands
[1]);
2811 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2814 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2815 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2817 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2818 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2822 if (rtx_equal_p (operands
[0], temp
))
2829 /* Otherwise we've nothing left but to drop the thing to memory. */
2830 operands
[1] = force_const_mem (mode
, operands
[1]);
2831 if (reload_in_progress
)
2833 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2834 operands
[1] = copy_rtx (operands
[1]);
2835 XEXP (operands
[1], 0) = operands
[0];
2838 operands
[1] = validize_mem (operands
[1]);
2842 /* Expand a non-bwx QImode or HImode move instruction;
2843 return true if all work is done. */
2846 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2848 /* If the output is not a register, the input must be. */
2849 if (GET_CODE (operands
[0]) == MEM
)
2850 operands
[1] = force_reg (mode
, operands
[1]);
2852 /* Handle four memory cases, unaligned and aligned for either the input
2853 or the output. The only case where we can be called during reload is
2854 for aligned loads; all other cases require temporaries. */
2856 if (GET_CODE (operands
[1]) == MEM
2857 || (GET_CODE (operands
[1]) == SUBREG
2858 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2859 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2860 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2861 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2862 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2863 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2865 if (aligned_memory_operand (operands
[1], mode
))
2867 if (reload_in_progress
)
2869 emit_insn ((mode
== QImode
2870 ? gen_reload_inqi_help
2871 : gen_reload_inhi_help
)
2872 (operands
[0], operands
[1],
2873 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2877 rtx aligned_mem
, bitnum
;
2878 rtx scratch
= gen_reg_rtx (SImode
);
2880 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2882 emit_insn ((mode
== QImode
2883 ? gen_aligned_loadqi
2884 : gen_aligned_loadhi
)
2885 (operands
[0], aligned_mem
, bitnum
, scratch
));
2890 /* Don't pass these as parameters since that makes the generated
2891 code depend on parameter evaluation order which will cause
2892 bootstrap failures. */
2894 rtx temp1
= gen_reg_rtx (DImode
);
2895 rtx temp2
= gen_reg_rtx (DImode
);
2896 rtx seq
= ((mode
== QImode
2897 ? gen_unaligned_loadqi
2898 : gen_unaligned_loadhi
)
2899 (operands
[0], get_unaligned_address (operands
[1], 0),
2902 alpha_set_memflags (seq
, operands
[1]);
2908 if (GET_CODE (operands
[0]) == MEM
2909 || (GET_CODE (operands
[0]) == SUBREG
2910 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2911 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2912 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2913 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2914 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2915 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2917 if (aligned_memory_operand (operands
[0], mode
))
2919 rtx aligned_mem
, bitnum
;
2920 rtx temp1
= gen_reg_rtx (SImode
);
2921 rtx temp2
= gen_reg_rtx (SImode
);
2923 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2925 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2930 rtx temp1
= gen_reg_rtx (DImode
);
2931 rtx temp2
= gen_reg_rtx (DImode
);
2932 rtx temp3
= gen_reg_rtx (DImode
);
2933 rtx seq
= ((mode
== QImode
2934 ? gen_unaligned_storeqi
2935 : gen_unaligned_storehi
)
2936 (get_unaligned_address (operands
[0], 0),
2937 operands
[1], temp1
, temp2
, temp3
));
2939 alpha_set_memflags (seq
, operands
[0]);
2948 /* Generate an unsigned DImode to FP conversion. This is the same code
2949 optabs would emit if we didn't have TFmode patterns.
2951 For SFmode, this is the only construction I've found that can pass
2952 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2953 intermediates will work, because you'll get intermediate rounding
2954 that ruins the end result. Some of this could be fixed by turning
2955 on round-to-positive-infinity, but that requires diddling the fpsr,
2956 which kills performance. I tried turning this around and converting
2957 to a negative number, so that I could turn on /m, but either I did
2958 it wrong or there's something else cause I wound up with the exact
2959 same single-bit error. There is a branch-less form of this same code:
2970 fcmoveq $f10,$f11,$f0
2972 I'm not using it because it's the same number of instructions as
2973 this branch-full form, and it has more serialized long latency
2974 instructions on the critical path.
2976 For DFmode, we can avoid rounding errors by breaking up the word
2977 into two pieces, converting them separately, and adding them back:
2979 LC0: .long 0,0x5f800000
2984 cpyse $f11,$f31,$f10
2985 cpyse $f31,$f11,$f11
2993 This doesn't seem to be a clear-cut win over the optabs form.
2994 It probably all depends on the distribution of numbers being
2995 converted -- in the optabs form, all but high-bit-set has a
2996 much lower minimum execution time. */
2999 alpha_emit_floatuns (rtx operands
[2])
3001 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3002 enum machine_mode mode
;
3005 in
= force_reg (DImode
, operands
[1]);
3006 mode
= GET_MODE (out
);
3007 neglab
= gen_label_rtx ();
3008 donelab
= gen_label_rtx ();
3009 i0
= gen_reg_rtx (DImode
);
3010 i1
= gen_reg_rtx (DImode
);
3011 f0
= gen_reg_rtx (mode
);
3013 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3015 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3016 emit_jump_insn (gen_jump (donelab
));
3019 emit_label (neglab
);
3021 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3022 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3023 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3024 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3025 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3027 emit_label (donelab
);
3030 /* Generate the comparison for a conditional branch. */
3033 alpha_emit_conditional_branch (enum rtx_code code
)
3035 enum rtx_code cmp_code
, branch_code
;
3036 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3037 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3040 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3042 if (! TARGET_HAS_XFLOATING_LIBS
)
3045 /* X_floating library comparison functions return
3049 Convert the compare against the raw return value. */
3071 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3073 alpha_compare
.fp_p
= 0;
3076 /* The general case: fold the comparison code to the types of compares
3077 that we have, choosing the branch as necessary. */
3080 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3082 /* We have these compares: */
3083 cmp_code
= code
, branch_code
= NE
;
3088 /* These must be reversed. */
3089 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3092 case GE
: case GT
: case GEU
: case GTU
:
3093 /* For FP, we swap them, for INT, we reverse them. */
3094 if (alpha_compare
.fp_p
)
3096 cmp_code
= swap_condition (code
);
3098 tem
= op0
, op0
= op1
, op1
= tem
;
3102 cmp_code
= reverse_condition (code
);
3111 if (alpha_compare
.fp_p
)
3114 if (flag_unsafe_math_optimizations
)
3116 /* When we are not as concerned about non-finite values, and we
3117 are comparing against zero, we can branch directly. */
3118 if (op1
== CONST0_RTX (DFmode
))
3119 cmp_code
= NIL
, branch_code
= code
;
3120 else if (op0
== CONST0_RTX (DFmode
))
3122 /* Undo the swap we probably did just above. */
3123 tem
= op0
, op0
= op1
, op1
= tem
;
3124 branch_code
= swap_condition (cmp_code
);
3130 /* ??? We mark the branch mode to be CCmode to prevent the
3131 compare and branch from being combined, since the compare
3132 insn follows IEEE rules that the branch does not. */
3133 branch_mode
= CCmode
;
3140 /* The following optimizations are only for signed compares. */
3141 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3143 /* Whee. Compare and branch against 0 directly. */
3144 if (op1
== const0_rtx
)
3145 cmp_code
= NIL
, branch_code
= code
;
3147 /* If the constants doesn't fit into an immediate, but can
3148 be generated by lda/ldah, we adjust the argument and
3149 compare against zero, so we can use beq/bne directly. */
3150 else if (GET_CODE (op1
) == CONST_INT
&& (code
== EQ
|| code
== NE
))
3152 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3154 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3155 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3156 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3158 cmp_code
= PLUS
, branch_code
= code
;
3164 if (!reg_or_0_operand (op0
, DImode
))
3165 op0
= force_reg (DImode
, op0
);
3166 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3167 op1
= force_reg (DImode
, op1
);
3170 /* Emit an initial compare instruction, if necessary. */
3172 if (cmp_code
!= NIL
)
3174 tem
= gen_reg_rtx (cmp_mode
);
3175 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3178 /* Zero the operands. */
3179 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3181 /* Return the branch comparison. */
3182 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3185 /* Certain simplifications can be done to make invalid setcc operations
3186 valid. Return the final comparison, or NULL if we can't work. */
3189 alpha_emit_setcc (enum rtx_code code
)
3191 enum rtx_code cmp_code
;
3192 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3193 int fp_p
= alpha_compare
.fp_p
;
3196 /* Zero the operands. */
3197 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3199 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3201 if (! TARGET_HAS_XFLOATING_LIBS
)
3204 /* X_floating library comparison functions return
3208 Convert the compare against the raw return value. */
3210 if (code
== UNORDERED
|| code
== ORDERED
)
3215 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3219 if (code
== UNORDERED
)
3221 else if (code
== ORDERED
)
3227 if (fp_p
&& !TARGET_FIX
)
3230 /* The general case: fold the comparison code to the types of compares
3231 that we have, choosing the branch as necessary. */
3236 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3238 /* We have these compares. */
3240 cmp_code
= code
, code
= NE
;
3244 if (!fp_p
&& op1
== const0_rtx
)
3249 cmp_code
= reverse_condition (code
);
3253 case GE
: case GT
: case GEU
: case GTU
:
3254 /* These normally need swapping, but for integer zero we have
3255 special patterns that recognize swapped operands. */
3256 if (!fp_p
&& op1
== const0_rtx
)
3258 code
= swap_condition (code
);
3260 cmp_code
= code
, code
= NE
;
3261 tmp
= op0
, op0
= op1
, op1
= tmp
;
3270 if (!register_operand (op0
, DImode
))
3271 op0
= force_reg (DImode
, op0
);
3272 if (!reg_or_8bit_operand (op1
, DImode
))
3273 op1
= force_reg (DImode
, op1
);
3276 /* Emit an initial compare instruction, if necessary. */
3277 if (cmp_code
!= NIL
)
3279 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3281 tmp
= gen_reg_rtx (mode
);
3282 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3283 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3285 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3289 /* Return the setcc comparison. */
3290 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3294 /* Rewrite a comparison against zero CMP of the form
3295 (CODE (cc0) (const_int 0)) so it can be written validly in
3296 a conditional move (if_then_else CMP ...).
3297 If both of the operands that set cc0 are nonzero we must emit
3298 an insn to perform the compare (it can't be done within
3299 the conditional move). */
3302 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
3304 enum rtx_code code
= GET_CODE (cmp
);
3305 enum rtx_code cmov_code
= NE
;
3306 rtx op0
= alpha_compare
.op0
;
3307 rtx op1
= alpha_compare
.op1
;
3308 int fp_p
= alpha_compare
.fp_p
;
3309 enum machine_mode cmp_mode
3310 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3311 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3312 enum machine_mode cmov_mode
= VOIDmode
;
3313 int local_fast_math
= flag_unsafe_math_optimizations
;
3316 /* Zero the operands. */
3317 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3319 if (fp_p
!= FLOAT_MODE_P (mode
))
3321 enum rtx_code cmp_code
;
3326 /* If we have fp<->int register move instructions, do a cmov by
3327 performing the comparison in fp registers, and move the
3328 zero/nonzero value to integer registers, where we can then
3329 use a normal cmov, or vice-versa. */
3333 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3334 /* We have these compares. */
3335 cmp_code
= code
, code
= NE
;
3339 /* This must be reversed. */
3340 cmp_code
= EQ
, code
= EQ
;
3343 case GE
: case GT
: case GEU
: case GTU
:
3344 /* These normally need swapping, but for integer zero we have
3345 special patterns that recognize swapped operands. */
3346 if (!fp_p
&& op1
== const0_rtx
)
3347 cmp_code
= code
, code
= NE
;
3350 cmp_code
= swap_condition (code
);
3352 tem
= op0
, op0
= op1
, op1
= tem
;
3360 tem
= gen_reg_rtx (cmp_op_mode
);
3361 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3362 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3365 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3366 op0
= gen_lowpart (cmp_op_mode
, tem
);
3367 op1
= CONST0_RTX (cmp_op_mode
);
3369 local_fast_math
= 1;
3372 /* We may be able to use a conditional move directly.
3373 This avoids emitting spurious compares. */
3374 if (signed_comparison_operator (cmp
, VOIDmode
)
3375 && (!fp_p
|| local_fast_math
)
3376 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3377 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3379 /* We can't put the comparison inside the conditional move;
3380 emit a compare instruction and put that inside the
3381 conditional move. Make sure we emit only comparisons we have;
3382 swap or reverse as necessary. */
3389 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3390 /* We have these compares: */
3394 /* This must be reversed. */
3395 code
= reverse_condition (code
);
3399 case GE
: case GT
: case GEU
: case GTU
:
3400 /* These must be swapped. */
3401 if (op1
!= CONST0_RTX (cmp_mode
))
3403 code
= swap_condition (code
);
3404 tem
= op0
, op0
= op1
, op1
= tem
;
3414 if (!reg_or_0_operand (op0
, DImode
))
3415 op0
= force_reg (DImode
, op0
);
3416 if (!reg_or_8bit_operand (op1
, DImode
))
3417 op1
= force_reg (DImode
, op1
);
3420 /* ??? We mark the branch mode to be CCmode to prevent the compare
3421 and cmov from being combined, since the compare insn follows IEEE
3422 rules that the cmov does not. */
3423 if (fp_p
&& !local_fast_math
)
3426 tem
= gen_reg_rtx (cmp_op_mode
);
3427 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3428 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3431 /* Simplify a conditional move of two constants into a setcc with
3432 arithmetic. This is done with a splitter since combine would
3433 just undo the work if done during code generation. It also catches
3434 cases we wouldn't have before cse. */
3437 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
3438 rtx t_rtx
, rtx f_rtx
)
3440 HOST_WIDE_INT t
, f
, diff
;
3441 enum machine_mode mode
;
3442 rtx target
, subtarget
, tmp
;
3444 mode
= GET_MODE (dest
);
3449 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3450 || (code
== GE
|| code
== GT
))
3452 code
= reverse_condition (code
);
3453 diff
= t
, t
= f
, f
= diff
;
3457 subtarget
= target
= dest
;
3460 target
= gen_lowpart (DImode
, dest
);
3461 if (! no_new_pseudos
)
3462 subtarget
= gen_reg_rtx (DImode
);
3466 /* Below, we must be careful to use copy_rtx on target and subtarget
3467 in intermediate insns, as they may be a subreg rtx, which may not
3470 if (f
== 0 && exact_log2 (diff
) > 0
3471 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3472 viable over a longer latency cmove. On EV5, the E0 slot is a
3473 scarce resource, and on EV4 shift has the same latency as a cmove. */
3474 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3476 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3477 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3479 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3480 GEN_INT (exact_log2 (t
)));
3481 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3483 else if (f
== 0 && t
== -1)
3485 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3486 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3488 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3490 else if (diff
== 1 || diff
== 4 || diff
== 8)
3494 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3495 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3498 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3501 add_op
= GEN_INT (f
);
3502 if (sext_add_operand (add_op
, mode
))
3504 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3506 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3507 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3519 /* Look up the function X_floating library function name for the
3523 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
3527 const enum rtx_code code
;
3528 const char *const func
;
3531 static const struct xfloating_op vms_xfloating_ops
[] =
3533 { PLUS
, "OTS$ADD_X" },
3534 { MINUS
, "OTS$SUB_X" },
3535 { MULT
, "OTS$MUL_X" },
3536 { DIV
, "OTS$DIV_X" },
3537 { EQ
, "OTS$EQL_X" },
3538 { NE
, "OTS$NEQ_X" },
3539 { LT
, "OTS$LSS_X" },
3540 { LE
, "OTS$LEQ_X" },
3541 { GT
, "OTS$GTR_X" },
3542 { GE
, "OTS$GEQ_X" },
3543 { FIX
, "OTS$CVTXQ" },
3544 { FLOAT
, "OTS$CVTQX" },
3545 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3546 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3547 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3550 static const struct xfloating_op osf_xfloating_ops
[] =
3552 { PLUS
, "_OtsAddX" },
3553 { MINUS
, "_OtsSubX" },
3554 { MULT
, "_OtsMulX" },
3555 { DIV
, "_OtsDivX" },
3562 { FIX
, "_OtsCvtXQ" },
3563 { FLOAT
, "_OtsCvtQX" },
3564 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3565 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3566 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3569 const struct xfloating_op
*ops
;
3570 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3573 /* How irritating. Nothing to key off for the table. Hardcode
3574 knowledge of the G_floating routines. */
3575 if (TARGET_FLOAT_VAX
)
3577 if (TARGET_ABI_OPEN_VMS
)
3579 if (code
== FLOAT_EXTEND
)
3580 return "OTS$CVT_FLOAT_G_X";
3581 if (code
== FLOAT_TRUNCATE
)
3582 return "OTS$CVT_FLOAT_X_G";
3586 if (code
== FLOAT_EXTEND
)
3587 return "_OtsConvertFloatGX";
3588 if (code
== FLOAT_TRUNCATE
)
3589 return "_OtsConvertFloatXG";
3593 if (TARGET_ABI_OPEN_VMS
)
3594 ops
= vms_xfloating_ops
;
3596 ops
= osf_xfloating_ops
;
3598 for (i
= 0; i
< n
; ++i
)
3599 if (ops
[i
].code
== code
)
3605 /* Most X_floating operations take the rounding mode as an argument.
3606 Compute that here. */
3609 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
3610 enum alpha_fp_rounding_mode round
)
3616 case ALPHA_FPRM_NORM
:
3619 case ALPHA_FPRM_MINF
:
3622 case ALPHA_FPRM_CHOP
:
3625 case ALPHA_FPRM_DYN
:
3631 /* XXX For reference, round to +inf is mode = 3. */
3634 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3640 /* Emit an X_floating library function call.
3642 Note that these functions do not follow normal calling conventions:
3643 TFmode arguments are passed in two integer registers (as opposed to
3644 indirect); TFmode return values appear in R16+R17.
3646 FUNC is the function name to call.
3647 TARGET is where the output belongs.
3648 OPERANDS are the inputs.
3649 NOPERANDS is the count of inputs.
3650 EQUIV is the expression equivalent for the function.
3654 alpha_emit_xfloating_libcall (const char *func
, rtx target
, rtx operands
[],
3655 int noperands
, rtx equiv
)
3657 rtx usage
= NULL_RTX
, tmp
, reg
;
3662 for (i
= 0; i
< noperands
; ++i
)
3664 switch (GET_MODE (operands
[i
]))
3667 reg
= gen_rtx_REG (TFmode
, regno
);
3672 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3677 if (GET_CODE (operands
[i
]) != CONST_INT
)
3681 reg
= gen_rtx_REG (DImode
, regno
);
3689 emit_move_insn (reg
, operands
[i
]);
3690 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3693 switch (GET_MODE (target
))
3696 reg
= gen_rtx_REG (TFmode
, 16);
3699 reg
= gen_rtx_REG (DFmode
, 32);
3702 reg
= gen_rtx_REG (DImode
, 0);
3708 tmp
= gen_rtx_MEM (QImode
, init_one_libfunc (func
));
3709 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3710 const0_rtx
, const0_rtx
));
3711 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3716 emit_libcall_block (tmp
, target
, reg
, equiv
);
3719 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3722 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3726 rtx out_operands
[3];
3728 func
= alpha_lookup_xfloating_lib_func (code
);
3729 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3731 out_operands
[0] = operands
[1];
3732 out_operands
[1] = operands
[2];
3733 out_operands
[2] = GEN_INT (mode
);
3734 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3735 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3739 /* Emit an X_floating library function call for a comparison. */
3742 alpha_emit_xfloating_compare (enum rtx_code code
, rtx op0
, rtx op1
)
3745 rtx out
, operands
[2];
3747 func
= alpha_lookup_xfloating_lib_func (code
);
3751 out
= gen_reg_rtx (DImode
);
3753 /* ??? Strange mode for equiv because what's actually returned
3754 is -1,0,1, not a proper boolean value. */
3755 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3756 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3761 /* Emit an X_floating library function call for a conversion. */
3764 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3766 int noperands
= 1, mode
;
3767 rtx out_operands
[2];
3769 enum rtx_code code
= orig_code
;
3771 if (code
== UNSIGNED_FIX
)
3774 func
= alpha_lookup_xfloating_lib_func (code
);
3776 out_operands
[0] = operands
[1];
3781 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3782 out_operands
[1] = GEN_INT (mode
);
3785 case FLOAT_TRUNCATE
:
3786 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3787 out_operands
[1] = GEN_INT (mode
);
3794 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3795 gen_rtx_fmt_e (orig_code
,
3796 GET_MODE (operands
[0]),
3800 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3801 OP[0] into OP[0,1]. Naturally, output operand ordering is
3805 alpha_split_tfmode_pair (rtx operands
[4])
3807 if (GET_CODE (operands
[1]) == REG
)
3809 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3810 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3812 else if (GET_CODE (operands
[1]) == MEM
)
3814 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3815 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3817 else if (operands
[1] == CONST0_RTX (TFmode
))
3818 operands
[2] = operands
[3] = const0_rtx
;
3822 if (GET_CODE (operands
[0]) == REG
)
3824 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3825 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3827 else if (GET_CODE (operands
[0]) == MEM
)
3829 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3830 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3836 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3837 op2 is a register containing the sign bit, operation is the
3838 logical operation to be performed. */
3841 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3843 rtx high_bit
= operands
[2];
3847 alpha_split_tfmode_pair (operands
);
3849 /* Detect three flavors of operand overlap. */
3851 if (rtx_equal_p (operands
[0], operands
[2]))
3853 else if (rtx_equal_p (operands
[1], operands
[2]))
3855 if (rtx_equal_p (operands
[0], high_bit
))
3862 emit_move_insn (operands
[0], operands
[2]);
3864 /* ??? If the destination overlaps both source tf and high_bit, then
3865 assume source tf is dead in its entirety and use the other half
3866 for a scratch register. Otherwise "scratch" is just the proper
3867 destination register. */
3868 scratch
= operands
[move
< 2 ? 1 : 3];
3870 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3874 emit_move_insn (operands
[0], operands
[2]);
3876 emit_move_insn (operands
[1], scratch
);
3880 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3884 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3885 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3886 lda r3,X(r11) lda r3,X+2(r11)
3887 extwl r1,r3,r1 extql r1,r3,r1
3888 extwh r2,r3,r2 extqh r2,r3,r2
3889 or r1.r2.r1 or r1,r2,r1
3892 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3893 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3894 lda r3,X(r11) lda r3,X(r11)
3895 extll r1,r3,r1 extll r1,r3,r1
3896 extlh r2,r3,r2 extlh r2,r3,r2
3897 or r1.r2.r1 addl r1,r2,r1
3899 quad: ldq_u r1,X(r11)
3908 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3909 HOST_WIDE_INT ofs
, int sign
)
3911 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3912 enum machine_mode mode
;
3914 meml
= gen_reg_rtx (DImode
);
3915 memh
= gen_reg_rtx (DImode
);
3916 addr
= gen_reg_rtx (DImode
);
3917 extl
= gen_reg_rtx (DImode
);
3918 exth
= gen_reg_rtx (DImode
);
3920 mema
= XEXP (mem
, 0);
3921 if (GET_CODE (mema
) == LO_SUM
)
3922 mema
= force_reg (Pmode
, mema
);
3924 /* AND addresses cannot be in any alias set, since they may implicitly
3925 alias surrounding code. Ideally we'd have some alias set that
3926 covered all types except those with alignment 8 or higher. */
3928 tmp
= change_address (mem
, DImode
,
3929 gen_rtx_AND (DImode
,
3930 plus_constant (mema
, ofs
),
3932 set_mem_alias_set (tmp
, 0);
3933 emit_move_insn (meml
, tmp
);
3935 tmp
= change_address (mem
, DImode
,
3936 gen_rtx_AND (DImode
,
3937 plus_constant (mema
, ofs
+ size
- 1),
3939 set_mem_alias_set (tmp
, 0);
3940 emit_move_insn (memh
, tmp
);
3942 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3944 emit_move_insn (addr
, plus_constant (mema
, -1));
3946 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3947 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3949 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3950 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3951 addr
, 1, OPTAB_WIDEN
);
3953 else if (sign
&& size
== 2)
3955 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3957 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3958 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3960 /* We must use tgt here for the target. Alpha-vms port fails if we use
3961 addr for the target, because addr is marked as a pointer and combine
3962 knows that pointers are always sign-extended 32 bit values. */
3963 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3964 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3965 addr
, 1, OPTAB_WIDEN
);
3969 if (WORDS_BIG_ENDIAN
)
3971 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3975 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3980 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3985 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3992 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3996 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3997 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4001 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4006 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4011 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4020 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4021 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4026 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4029 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4032 alpha_expand_unaligned_store (rtx dst
, rtx src
,
4033 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
4035 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4037 dstl
= gen_reg_rtx (DImode
);
4038 dsth
= gen_reg_rtx (DImode
);
4039 insl
= gen_reg_rtx (DImode
);
4040 insh
= gen_reg_rtx (DImode
);
4042 dsta
= XEXP (dst
, 0);
4043 if (GET_CODE (dsta
) == LO_SUM
)
4044 dsta
= force_reg (Pmode
, dsta
);
4046 /* AND addresses cannot be in any alias set, since they may implicitly
4047 alias surrounding code. Ideally we'd have some alias set that
4048 covered all types except those with alignment 8 or higher. */
4050 meml
= change_address (dst
, DImode
,
4051 gen_rtx_AND (DImode
,
4052 plus_constant (dsta
, ofs
),
4054 set_mem_alias_set (meml
, 0);
4056 memh
= change_address (dst
, DImode
,
4057 gen_rtx_AND (DImode
,
4058 plus_constant (dsta
, ofs
+ size
- 1),
4060 set_mem_alias_set (memh
, 0);
4062 emit_move_insn (dsth
, memh
);
4063 emit_move_insn (dstl
, meml
);
4064 if (WORDS_BIG_ENDIAN
)
4066 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4068 if (src
!= const0_rtx
)
4073 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4076 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4079 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4082 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4083 GEN_INT (size
*8), addr
));
4089 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4093 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4094 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4098 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4102 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4106 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4108 if (src
!= const0_rtx
)
4110 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4111 GEN_INT (size
*8), addr
));
4116 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4119 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4122 emit_insn (gen_insql_le (insl
, src
, addr
));
4127 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4132 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4136 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4137 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4141 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4146 if (src
!= const0_rtx
)
4148 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4149 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4152 if (WORDS_BIG_ENDIAN
)
4154 emit_move_insn (meml
, dstl
);
4155 emit_move_insn (memh
, dsth
);
4159 /* Must store high before low for degenerate case of aligned. */
4160 emit_move_insn (memh
, dsth
);
4161 emit_move_insn (meml
, dstl
);
4165 /* The block move code tries to maximize speed by separating loads and
4166 stores at the expense of register pressure: we load all of the data
4167 before we store it back out. There are two secondary effects worth
4168 mentioning, that this speeds copying to/from aligned and unaligned
4169 buffers, and that it makes the code significantly easier to write. */
4171 #define MAX_MOVE_WORDS 8
4173 /* Load an integral number of consecutive unaligned quadwords. */
4176 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
4177 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4179 rtx
const im8
= GEN_INT (-8);
4180 rtx
const i64
= GEN_INT (64);
4181 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4182 rtx sreg
, areg
, tmp
, smema
;
4185 smema
= XEXP (smem
, 0);
4186 if (GET_CODE (smema
) == LO_SUM
)
4187 smema
= force_reg (Pmode
, smema
);
4189 /* Generate all the tmp registers we need. */
4190 for (i
= 0; i
< words
; ++i
)
4192 data_regs
[i
] = out_regs
[i
];
4193 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4195 data_regs
[words
] = gen_reg_rtx (DImode
);
4198 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4200 /* Load up all of the source data. */
4201 for (i
= 0; i
< words
; ++i
)
4203 tmp
= change_address (smem
, DImode
,
4204 gen_rtx_AND (DImode
,
4205 plus_constant (smema
, 8*i
),
4207 set_mem_alias_set (tmp
, 0);
4208 emit_move_insn (data_regs
[i
], tmp
);
4211 tmp
= change_address (smem
, DImode
,
4212 gen_rtx_AND (DImode
,
4213 plus_constant (smema
, 8*words
- 1),
4215 set_mem_alias_set (tmp
, 0);
4216 emit_move_insn (data_regs
[words
], tmp
);
4218 /* Extract the half-word fragments. Unfortunately DEC decided to make
4219 extxh with offset zero a noop instead of zeroing the register, so
4220 we must take care of that edge condition ourselves with cmov. */
4222 sreg
= copy_addr_to_reg (smema
);
4223 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4225 if (WORDS_BIG_ENDIAN
)
4226 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4227 for (i
= 0; i
< words
; ++i
)
4229 if (WORDS_BIG_ENDIAN
)
4231 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4232 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4236 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4237 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4239 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4240 gen_rtx_IF_THEN_ELSE (DImode
,
4241 gen_rtx_EQ (DImode
, areg
,
4243 const0_rtx
, ext_tmps
[i
])));
4246 /* Merge the half-words into whole words. */
4247 for (i
= 0; i
< words
; ++i
)
4249 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4250 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4254 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4255 may be NULL to store zeros. */
4258 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
4259 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
4261 rtx
const im8
= GEN_INT (-8);
4262 rtx
const i64
= GEN_INT (64);
4263 rtx ins_tmps
[MAX_MOVE_WORDS
];
4264 rtx st_tmp_1
, st_tmp_2
, dreg
;
4265 rtx st_addr_1
, st_addr_2
, dmema
;
4268 dmema
= XEXP (dmem
, 0);
4269 if (GET_CODE (dmema
) == LO_SUM
)
4270 dmema
= force_reg (Pmode
, dmema
);
4272 /* Generate all the tmp registers we need. */
4273 if (data_regs
!= NULL
)
4274 for (i
= 0; i
< words
; ++i
)
4275 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4276 st_tmp_1
= gen_reg_rtx(DImode
);
4277 st_tmp_2
= gen_reg_rtx(DImode
);
4280 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4282 st_addr_2
= change_address (dmem
, DImode
,
4283 gen_rtx_AND (DImode
,
4284 plus_constant (dmema
, words
*8 - 1),
4286 set_mem_alias_set (st_addr_2
, 0);
4288 st_addr_1
= change_address (dmem
, DImode
,
4289 gen_rtx_AND (DImode
, dmema
, im8
));
4290 set_mem_alias_set (st_addr_1
, 0);
4292 /* Load up the destination end bits. */
4293 emit_move_insn (st_tmp_2
, st_addr_2
);
4294 emit_move_insn (st_tmp_1
, st_addr_1
);
4296 /* Shift the input data into place. */
4297 dreg
= copy_addr_to_reg (dmema
);
4298 if (WORDS_BIG_ENDIAN
)
4299 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4300 if (data_regs
!= NULL
)
4302 for (i
= words
-1; i
>= 0; --i
)
4304 if (WORDS_BIG_ENDIAN
)
4306 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4307 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4311 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4312 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4315 for (i
= words
-1; i
> 0; --i
)
4317 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4318 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4323 /* Split and merge the ends with the destination data. */
4324 if (WORDS_BIG_ENDIAN
)
4326 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4327 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4331 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4332 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4335 if (data_regs
!= NULL
)
4337 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4338 st_tmp_2
, 1, OPTAB_WIDEN
);
4339 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4340 st_tmp_1
, 1, OPTAB_WIDEN
);
4344 if (WORDS_BIG_ENDIAN
)
4345 emit_move_insn (st_addr_1
, st_tmp_1
);
4347 emit_move_insn (st_addr_2
, st_tmp_2
);
4348 for (i
= words
-1; i
> 0; --i
)
4350 rtx tmp
= change_address (dmem
, DImode
,
4351 gen_rtx_AND (DImode
,
4352 plus_constant(dmema
,
4353 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4355 set_mem_alias_set (tmp
, 0);
4356 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4358 if (WORDS_BIG_ENDIAN
)
4359 emit_move_insn (st_addr_2
, st_tmp_2
);
4361 emit_move_insn (st_addr_1
, st_tmp_1
);
4365 /* Expand string/block move operations.
4367 operands[0] is the pointer to the destination.
4368 operands[1] is the pointer to the source.
4369 operands[2] is the number of bytes to move.
4370 operands[3] is the alignment. */
4373 alpha_expand_block_move (rtx operands
[])
4375 rtx bytes_rtx
= operands
[2];
4376 rtx align_rtx
= operands
[3];
4377 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4378 HOST_WIDE_INT bytes
= orig_bytes
;
4379 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4380 HOST_WIDE_INT dst_align
= src_align
;
4381 rtx orig_src
= operands
[1];
4382 rtx orig_dst
= operands
[0];
4383 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4385 unsigned int i
, words
, ofs
, nregs
= 0;
4387 if (orig_bytes
<= 0)
4389 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4392 /* Look for additional alignment information from recorded register info. */
4394 tmp
= XEXP (orig_src
, 0);
4395 if (GET_CODE (tmp
) == REG
)
4396 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4397 else if (GET_CODE (tmp
) == PLUS
4398 && GET_CODE (XEXP (tmp
, 0)) == REG
4399 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4401 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4402 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4406 if (a
>= 64 && c
% 8 == 0)
4408 else if (a
>= 32 && c
% 4 == 0)
4410 else if (a
>= 16 && c
% 2 == 0)
4415 tmp
= XEXP (orig_dst
, 0);
4416 if (GET_CODE (tmp
) == REG
)
4417 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4418 else if (GET_CODE (tmp
) == PLUS
4419 && GET_CODE (XEXP (tmp
, 0)) == REG
4420 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4422 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4423 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4427 if (a
>= 64 && c
% 8 == 0)
4429 else if (a
>= 32 && c
% 4 == 0)
4431 else if (a
>= 16 && c
% 2 == 0)
4436 /* Load the entire block into registers. */
4437 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4439 enum machine_mode mode
;
4441 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4443 /* Don't use the existing register if we're reading more than
4444 is held in the register. Nor if there is not a mode that
4445 handles the exact size. */
4446 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4447 if (GET_CODE (tmp
) == REG
4449 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4453 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4454 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4458 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4463 /* No appropriate mode; fall back on memory. */
4464 orig_src
= replace_equiv_address (orig_src
,
4465 copy_addr_to_reg (XEXP (orig_src
, 0)));
4466 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4470 if (src_align
>= 64 && bytes
>= 8)
4474 for (i
= 0; i
< words
; ++i
)
4475 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4477 for (i
= 0; i
< words
; ++i
)
4478 emit_move_insn (data_regs
[nregs
+ i
],
4479 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4486 if (src_align
>= 32 && bytes
>= 4)
4490 for (i
= 0; i
< words
; ++i
)
4491 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4493 for (i
= 0; i
< words
; ++i
)
4494 emit_move_insn (data_regs
[nregs
+ i
],
4495 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4506 for (i
= 0; i
< words
+1; ++i
)
4507 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4509 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4517 if (! TARGET_BWX
&& bytes
>= 4)
4519 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4520 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4527 if (src_align
>= 16)
4530 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4531 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4534 } while (bytes
>= 2);
4536 else if (! TARGET_BWX
)
4538 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4539 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4547 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4548 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4555 if (nregs
> ARRAY_SIZE (data_regs
))
4558 /* Now save it back out again. */
4562 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4564 enum machine_mode mode
;
4565 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4567 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4568 if (GET_CODE (tmp
) == REG
&& GET_MODE (tmp
) == mode
)
4572 emit_move_insn (tmp
, data_regs
[0]);
4577 else if (nregs
== 2 && mode
== TImode
)
4579 /* Undo the subregging done above when copying between
4580 two TImode registers. */
4581 if (GET_CODE (data_regs
[0]) == SUBREG
4582 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4583 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4589 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4590 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4594 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4595 data_regs
[1], NULL_RTX
);
4603 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4604 /* ??? Optimize mode < dst_mode with strict_low_part. */
4606 /* No appropriate mode; fall back on memory. We can speed things
4607 up by recognizing extra alignment information. */
4608 orig_dst
= replace_equiv_address (orig_dst
,
4609 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4610 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4613 /* Write out the data in whatever chunks reading the source allowed. */
4614 if (dst_align
>= 64)
4616 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4618 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4625 if (dst_align
>= 32)
4627 /* If the source has remaining DImode regs, write them out in
4629 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4631 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4632 NULL_RTX
, 1, OPTAB_WIDEN
);
4634 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4635 gen_lowpart (SImode
, data_regs
[i
]));
4636 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4637 gen_lowpart (SImode
, tmp
));
4642 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4644 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4651 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4653 /* Write out a remaining block of words using unaligned methods. */
4655 for (words
= 1; i
+ words
< nregs
; words
++)
4656 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4660 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4662 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4669 /* Due to the above, this won't be aligned. */
4670 /* ??? If we have more than one of these, consider constructing full
4671 words in registers and using alpha_expand_unaligned_store_words. */
4672 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4674 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4679 if (dst_align
>= 16)
4680 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4682 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4687 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4689 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4694 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4696 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4710 alpha_expand_block_clear (rtx operands
[])
4712 rtx bytes_rtx
= operands
[1];
4713 rtx align_rtx
= operands
[2];
4714 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4715 HOST_WIDE_INT bytes
= orig_bytes
;
4716 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4717 HOST_WIDE_INT alignofs
= 0;
4718 rtx orig_dst
= operands
[0];
4720 int i
, words
, ofs
= 0;
4722 if (orig_bytes
<= 0)
4724 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4727 /* Look for stricter alignment. */
4728 tmp
= XEXP (orig_dst
, 0);
4729 if (GET_CODE (tmp
) == REG
)
4730 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4731 else if (GET_CODE (tmp
) == PLUS
4732 && GET_CODE (XEXP (tmp
, 0)) == REG
4733 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4735 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4736 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4741 align
= a
, alignofs
= 8 - c
% 8;
4743 align
= a
, alignofs
= 4 - c
% 4;
4745 align
= a
, alignofs
= 2 - c
% 2;
4748 else if (GET_CODE (tmp
) == ADDRESSOF
)
4750 enum machine_mode mode
;
4752 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4753 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4755 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4759 /* No appropriate mode; fall back on memory. */
4760 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4761 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4764 /* Handle an unaligned prefix first. */
4768 #if HOST_BITS_PER_WIDE_INT >= 64
4769 /* Given that alignofs is bounded by align, the only time BWX could
4770 generate three stores is for a 7 byte fill. Prefer two individual
4771 stores over a load/mask/store sequence. */
4772 if ((!TARGET_BWX
|| alignofs
== 7)
4774 && !(alignofs
== 4 && bytes
>= 4))
4776 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4777 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4781 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4782 set_mem_alias_set (mem
, 0);
4784 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4785 if (bytes
< alignofs
)
4787 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4798 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4799 NULL_RTX
, 1, OPTAB_WIDEN
);
4801 emit_move_insn (mem
, tmp
);
4805 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4807 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4812 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4814 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4819 if (alignofs
== 4 && bytes
>= 4)
4821 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4827 /* If we've not used the extra lead alignment information by now,
4828 we won't be able to. Downgrade align to match what's left over. */
4831 alignofs
= alignofs
& -alignofs
;
4832 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4836 /* Handle a block of contiguous long-words. */
4838 if (align
>= 64 && bytes
>= 8)
4842 for (i
= 0; i
< words
; ++i
)
4843 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4850 /* If the block is large and appropriately aligned, emit a single
4851 store followed by a sequence of stq_u insns. */
4853 if (align
>= 32 && bytes
> 16)
4857 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4861 orig_dsta
= XEXP (orig_dst
, 0);
4862 if (GET_CODE (orig_dsta
) == LO_SUM
)
4863 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4866 for (i
= 0; i
< words
; ++i
)
4869 = change_address (orig_dst
, DImode
,
4870 gen_rtx_AND (DImode
,
4871 plus_constant (orig_dsta
, ofs
+ i
*8),
4873 set_mem_alias_set (mem
, 0);
4874 emit_move_insn (mem
, const0_rtx
);
4877 /* Depending on the alignment, the first stq_u may have overlapped
4878 with the initial stl, which means that the last stq_u didn't
4879 write as much as it would appear. Leave those questionable bytes
4881 bytes
-= words
* 8 - 4;
4882 ofs
+= words
* 8 - 4;
4885 /* Handle a smaller block of aligned words. */
4887 if ((align
>= 64 && bytes
== 4)
4888 || (align
== 32 && bytes
>= 4))
4892 for (i
= 0; i
< words
; ++i
)
4893 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4900 /* An unaligned block uses stq_u stores for as many as possible. */
4906 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4912 /* Next clean up any trailing pieces. */
4914 #if HOST_BITS_PER_WIDE_INT >= 64
4915 /* Count the number of bits in BYTES for which aligned stores could
4918 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4922 /* If we have appropriate alignment (and it wouldn't take too many
4923 instructions otherwise), mask out the bytes we need. */
4924 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4931 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4932 set_mem_alias_set (mem
, 0);
4934 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4936 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4937 NULL_RTX
, 1, OPTAB_WIDEN
);
4939 emit_move_insn (mem
, tmp
);
4942 else if (align
>= 32 && bytes
< 4)
4947 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4948 set_mem_alias_set (mem
, 0);
4950 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4952 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4953 NULL_RTX
, 1, OPTAB_WIDEN
);
4955 emit_move_insn (mem
, tmp
);
4961 if (!TARGET_BWX
&& bytes
>= 4)
4963 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4973 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4977 } while (bytes
>= 2);
4979 else if (! TARGET_BWX
)
4981 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4989 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4997 /* Returns a mask so that zap(x, value) == x & mask. */
5000 alpha_expand_zap_mask (HOST_WIDE_INT value
)
5005 if (HOST_BITS_PER_WIDE_INT
>= 64)
5007 HOST_WIDE_INT mask
= 0;
5009 for (i
= 7; i
>= 0; --i
)
5012 if (!((value
>> i
) & 1))
5016 result
= gen_int_mode (mask
, DImode
);
5018 else if (HOST_BITS_PER_WIDE_INT
== 32)
5020 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5022 for (i
= 7; i
>= 4; --i
)
5025 if (!((value
>> i
) & 1))
5029 for (i
= 3; i
>= 0; --i
)
5032 if (!((value
>> i
) & 1))
5036 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5045 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
5046 enum machine_mode mode
,
5047 rtx op0
, rtx op1
, rtx op2
)
5049 op0
= gen_lowpart (mode
, op0
);
5051 if (op1
== const0_rtx
)
5052 op1
= CONST0_RTX (mode
);
5054 op1
= gen_lowpart (mode
, op1
);
5056 if (op2
== const0_rtx
)
5057 op2
= CONST0_RTX (mode
);
5059 op2
= gen_lowpart (mode
, op2
);
5061 emit_insn ((*gen
) (op0
, op1
, op2
));
5064 /* Adjust the cost of a scheduling dependency. Return the new cost of
5065 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5068 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5070 enum attr_type insn_type
, dep_insn_type
;
5072 /* If the dependence is an anti-dependence, there is no cost. For an
5073 output dependence, there is sometimes a cost, but it doesn't seem
5074 worth handling those few cases. */
5075 if (REG_NOTE_KIND (link
) != 0)
5078 /* If we can't recognize the insns, we can't really do anything. */
5079 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5082 insn_type
= get_attr_type (insn
);
5083 dep_insn_type
= get_attr_type (dep_insn
);
5085 /* Bring in the user-defined memory latency. */
5086 if (dep_insn_type
== TYPE_ILD
5087 || dep_insn_type
== TYPE_FLD
5088 || dep_insn_type
== TYPE_LDSYM
)
5089 cost
+= alpha_memory_latency
-1;
5091 /* Everything else handled in DFA bypasses now. */
5096 /* The number of instructions that can be issued per cycle. */
5099 alpha_issue_rate (void)
5101 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5105 alpha_use_dfa_pipeline_interface (void)
5110 /* How many alternative schedules to try. This should be as wide as the
5111 scheduling freedom in the DFA, but no wider. Making this value too
5112 large results extra work for the scheduler.
5114 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5115 alternative schedules. For EV5, we can choose between E0/E1 and
5116 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5119 alpha_multipass_dfa_lookahead (void)
5121 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5124 /* Machine-specific function data. */
5126 struct machine_function
GTY(())
5129 /* List of call information words for calls from this function. */
5130 struct rtx_def
*first_ciw
;
5131 struct rtx_def
*last_ciw
;
5134 /* List of deferred case vectors. */
5135 struct rtx_def
*addr_list
;
5138 const char *some_ld_name
;
5141 /* How to allocate a 'struct machine_function'. */
5143 static struct machine_function
*
5144 alpha_init_machine_status (void)
5146 return ((struct machine_function
*)
5147 ggc_alloc_cleared (sizeof (struct machine_function
)));
5150 /* Functions to save and restore alpha_return_addr_rtx. */
5152 /* Start the ball rolling with RETURN_ADDR_RTX. */
5155 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
5160 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5163 /* Return or create a pseudo containing the gp value for the current
5164 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5167 alpha_gp_save_rtx (void)
5169 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5170 if (GET_CODE (r
) != MEM
)
5171 r
= gen_mem_addressof (r
, NULL_TREE
, /*rescan=*/true);
5176 alpha_ra_ever_killed (void)
5180 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5181 return regs_ever_live
[REG_RA
];
5183 push_topmost_sequence ();
5185 pop_topmost_sequence ();
5187 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5191 /* Return the trap mode suffix applicable to the current
5192 instruction, or NULL. */
5195 get_trap_mode_suffix (void)
5197 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5201 case TRAP_SUFFIX_NONE
:
5204 case TRAP_SUFFIX_SU
:
5205 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5209 case TRAP_SUFFIX_SUI
:
5210 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5214 case TRAP_SUFFIX_V_SV
:
5222 case ALPHA_FPTM_SUI
:
5227 case TRAP_SUFFIX_V_SV_SVI
:
5236 case ALPHA_FPTM_SUI
:
5241 case TRAP_SUFFIX_U_SU_SUI
:
5250 case ALPHA_FPTM_SUI
:
5258 /* Return the rounding mode suffix applicable to the current
5259 instruction, or NULL. */
5262 get_round_mode_suffix (void)
5264 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5268 case ROUND_SUFFIX_NONE
:
5270 case ROUND_SUFFIX_NORMAL
:
5273 case ALPHA_FPRM_NORM
:
5275 case ALPHA_FPRM_MINF
:
5277 case ALPHA_FPRM_CHOP
:
5279 case ALPHA_FPRM_DYN
:
5284 case ROUND_SUFFIX_C
:
5290 /* Locate some local-dynamic symbol still in use by this function
5291 so that we can print its name in some movdi_er_tlsldm pattern. */
5294 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5298 if (GET_CODE (x
) == SYMBOL_REF
5299 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5301 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5309 get_some_local_dynamic_name (void)
5313 if (cfun
->machine
->some_ld_name
)
5314 return cfun
->machine
->some_ld_name
;
5316 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5318 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5319 return cfun
->machine
->some_ld_name
;
5324 /* Print an operand. Recognize special options, documented below. */
5327 print_operand (FILE *file
, rtx x
, int code
)
5334 /* Print the assembler name of the current function. */
5335 assemble_name (file
, alpha_fnname
);
5339 assemble_name (file
, get_some_local_dynamic_name ());
5344 const char *trap
= get_trap_mode_suffix ();
5345 const char *round
= get_round_mode_suffix ();
5348 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5349 (trap
? trap
: ""), (round
? round
: ""));
5354 /* Generates single precision instruction suffix. */
5355 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5359 /* Generates double precision instruction suffix. */
5360 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5364 /* Generates a nop after a noreturn call at the very end of the
5366 if (next_real_insn (current_output_insn
) == 0)
5367 fprintf (file
, "\n\tnop");
5371 if (alpha_this_literal_sequence_number
== 0)
5372 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5373 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5377 if (alpha_this_gpdisp_sequence_number
== 0)
5378 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5379 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5383 if (GET_CODE (x
) == HIGH
)
5384 output_addr_const (file
, XEXP (x
, 0));
5386 output_operand_lossage ("invalid %%H value");
5393 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5395 x
= XVECEXP (x
, 0, 0);
5396 lituse
= "lituse_tlsgd";
5398 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5400 x
= XVECEXP (x
, 0, 0);
5401 lituse
= "lituse_tlsldm";
5403 else if (GET_CODE (x
) == CONST_INT
)
5404 lituse
= "lituse_jsr";
5407 output_operand_lossage ("invalid %%J value");
5411 if (x
!= const0_rtx
)
5412 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5417 /* If this operand is the constant zero, write it as "$31". */
5418 if (GET_CODE (x
) == REG
)
5419 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5420 else if (x
== CONST0_RTX (GET_MODE (x
)))
5421 fprintf (file
, "$31");
5423 output_operand_lossage ("invalid %%r value");
5427 /* Similar, but for floating-point. */
5428 if (GET_CODE (x
) == REG
)
5429 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5430 else if (x
== CONST0_RTX (GET_MODE (x
)))
5431 fprintf (file
, "$f31");
5433 output_operand_lossage ("invalid %%R value");
5437 /* Write the 1's complement of a constant. */
5438 if (GET_CODE (x
) != CONST_INT
)
5439 output_operand_lossage ("invalid %%N value");
5441 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5445 /* Write 1 << C, for a constant C. */
5446 if (GET_CODE (x
) != CONST_INT
)
5447 output_operand_lossage ("invalid %%P value");
5449 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5453 /* Write the high-order 16 bits of a constant, sign-extended. */
5454 if (GET_CODE (x
) != CONST_INT
)
5455 output_operand_lossage ("invalid %%h value");
5457 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5461 /* Write the low-order 16 bits of a constant, sign-extended. */
5462 if (GET_CODE (x
) != CONST_INT
)
5463 output_operand_lossage ("invalid %%L value");
5465 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5466 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5470 /* Write mask for ZAP insn. */
5471 if (GET_CODE (x
) == CONST_DOUBLE
)
5473 HOST_WIDE_INT mask
= 0;
5474 HOST_WIDE_INT value
;
5476 value
= CONST_DOUBLE_LOW (x
);
5477 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5482 value
= CONST_DOUBLE_HIGH (x
);
5483 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5486 mask
|= (1 << (i
+ sizeof (int)));
5488 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5491 else if (GET_CODE (x
) == CONST_INT
)
5493 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5495 for (i
= 0; i
< 8; i
++, value
>>= 8)
5499 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5502 output_operand_lossage ("invalid %%m value");
5506 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5507 if (GET_CODE (x
) != CONST_INT
5508 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5509 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5510 output_operand_lossage ("invalid %%M value");
5512 fprintf (file
, "%s",
5513 (INTVAL (x
) == 8 ? "b"
5514 : INTVAL (x
) == 16 ? "w"
5515 : INTVAL (x
) == 32 ? "l"
5520 /* Similar, except do it from the mask. */
5521 if (GET_CODE (x
) == CONST_INT
)
5523 HOST_WIDE_INT value
= INTVAL (x
);
5530 if (value
== 0xffff)
5535 if (value
== 0xffffffff)
5546 else if (HOST_BITS_PER_WIDE_INT
== 32
5547 && GET_CODE (x
) == CONST_DOUBLE
5548 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5549 && CONST_DOUBLE_HIGH (x
) == 0)
5554 output_operand_lossage ("invalid %%U value");
5558 /* Write the constant value divided by 8 for little-endian mode or
5559 (56 - value) / 8 for big-endian mode. */
5561 if (GET_CODE (x
) != CONST_INT
5562 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5565 || (INTVAL (x
) & 7) != 0)
5566 output_operand_lossage ("invalid %%s value");
5568 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5570 ? (56 - INTVAL (x
)) / 8
5575 /* Same, except compute (64 - c) / 8 */
5577 if (GET_CODE (x
) != CONST_INT
5578 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5579 && (INTVAL (x
) & 7) != 8)
5580 output_operand_lossage ("invalid %%s value");
5582 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5587 /* On Unicos/Mk systems: use a DEX expression if the symbol
5588 clashes with a register name. */
5589 int dex
= unicosmk_need_dex (x
);
5591 fprintf (file
, "DEX(%d)", dex
);
5593 output_addr_const (file
, x
);
5597 case 'C': case 'D': case 'c': case 'd':
5598 /* Write out comparison name. */
5600 enum rtx_code c
= GET_CODE (x
);
5602 if (GET_RTX_CLASS (c
) != '<')
5603 output_operand_lossage ("invalid %%C value");
5605 else if (code
== 'D')
5606 c
= reverse_condition (c
);
5607 else if (code
== 'c')
5608 c
= swap_condition (c
);
5609 else if (code
== 'd')
5610 c
= swap_condition (reverse_condition (c
));
5613 fprintf (file
, "ule");
5615 fprintf (file
, "ult");
5616 else if (c
== UNORDERED
)
5617 fprintf (file
, "un");
5619 fprintf (file
, "%s", GET_RTX_NAME (c
));
5624 /* Write the divide or modulus operator. */
5625 switch (GET_CODE (x
))
5628 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5631 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5634 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5637 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5640 output_operand_lossage ("invalid %%E value");
5646 /* Write "_u" for unaligned access. */
5647 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5648 fprintf (file
, "_u");
5652 if (GET_CODE (x
) == REG
)
5653 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5654 else if (GET_CODE (x
) == MEM
)
5655 output_address (XEXP (x
, 0));
5656 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5658 switch (XINT (XEXP (x
, 0), 1))
5662 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5665 output_operand_lossage ("unknown relocation unspec");
5670 output_addr_const (file
, x
);
5674 output_operand_lossage ("invalid %%xn code");
5679 print_operand_address (FILE *file
, rtx addr
)
5682 HOST_WIDE_INT offset
= 0;
5684 if (GET_CODE (addr
) == AND
)
5685 addr
= XEXP (addr
, 0);
5687 if (GET_CODE (addr
) == PLUS
5688 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5690 offset
= INTVAL (XEXP (addr
, 1));
5691 addr
= XEXP (addr
, 0);
5694 if (GET_CODE (addr
) == LO_SUM
)
5696 const char *reloc16
, *reloclo
;
5697 rtx op1
= XEXP (addr
, 1);
5699 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5701 op1
= XEXP (op1
, 0);
5702 switch (XINT (op1
, 1))
5706 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5710 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5713 output_operand_lossage ("unknown relocation unspec");
5717 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5722 reloclo
= "gprellow";
5723 output_addr_const (file
, op1
);
5727 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5729 addr
= XEXP (addr
, 0);
5730 if (GET_CODE (addr
) == REG
)
5731 basereg
= REGNO (addr
);
5732 else if (GET_CODE (addr
) == SUBREG
5733 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5734 basereg
= subreg_regno (addr
);
5738 fprintf (file
, "($%d)\t\t!%s", basereg
,
5739 (basereg
== 29 ? reloc16
: reloclo
));
5743 if (GET_CODE (addr
) == REG
)
5744 basereg
= REGNO (addr
);
5745 else if (GET_CODE (addr
) == SUBREG
5746 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5747 basereg
= subreg_regno (addr
);
5748 else if (GET_CODE (addr
) == CONST_INT
)
5749 offset
= INTVAL (addr
);
5751 #if TARGET_ABI_OPEN_VMS
5752 else if (GET_CODE (addr
) == SYMBOL_REF
)
5754 fprintf (file
, "%s", XSTR (addr
, 0));
5757 else if (GET_CODE (addr
) == CONST
5758 && GET_CODE (XEXP (addr
, 0)) == PLUS
5759 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5761 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5762 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5763 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5771 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5774 /* Emit RTL insns to initialize the variable parts of a trampoline at
5775 TRAMP. FNADDR is an RTX for the address of the function's pure
5776 code. CXT is an RTX for the static chain value for the function.
5778 The three offset parameters are for the individual template's
5779 layout. A JMPOFS < 0 indicates that the trampoline does not
5780 contain instructions at all.
5782 We assume here that a function will be called many more times than
5783 its address is taken (e.g., it might be passed to qsort), so we
5784 take the trouble to initialize the "hint" field in the JMP insn.
5785 Note that the hint field is PC (new) + 4 * bits 13:0. */
5788 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5789 int fnofs
, int cxtofs
, int jmpofs
)
5791 rtx temp
, temp1
, addr
;
5792 /* VMS really uses DImode pointers in memory at this point. */
5793 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5795 #ifdef POINTERS_EXTEND_UNSIGNED
5796 fnaddr
= convert_memory_address (mode
, fnaddr
);
5797 cxt
= convert_memory_address (mode
, cxt
);
5800 /* Store function address and CXT. */
5801 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5802 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5803 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5804 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5806 /* This has been disabled since the hint only has a 32k range, and in
5807 no existing OS is the stack within 32k of the text segment. */
5808 if (0 && jmpofs
>= 0)
5810 /* Compute hint value. */
5811 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5812 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5814 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5815 build_int_2 (2, 0), NULL_RTX
, 1);
5816 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5817 GEN_INT (0x3fff), 0);
5819 /* Merge in the hint. */
5820 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5821 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5822 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5823 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5825 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5828 #ifdef TRANSFER_FROM_TRAMPOLINE
5829 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5830 0, VOIDmode
, 1, tramp
, Pmode
);
5834 emit_insn (gen_imb ());
5837 /* Determine where to put an argument to a function.
5838 Value is zero to push the argument on the stack,
5839 or a hard register in which to store the argument.
5841 MODE is the argument's machine mode.
5842 TYPE is the data type of the argument (as a tree).
5843 This is null for libcalls where that information may
5845 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5846 the preceding args and about the function being called.
5847 NAMED is nonzero if this argument is a named parameter
5848 (otherwise it is an extra parameter matching an ellipsis).
5850 On Alpha the first 6 words of args are normally in registers
5851 and the rest are pushed. */
5854 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5855 int named ATTRIBUTE_UNUSED
)
5860 /* Don't get confused and pass small structures in FP registers. */
5861 if (type
&& AGGREGATE_TYPE_P (type
))
5865 #ifdef ENABLE_CHECKING
5866 /* With SPLIT_COMPLEX_ARGS, we shouldn't see any raw complex
5868 if (COMPLEX_MODE_P (mode
))
5872 /* Set up defaults for FP operands passed in FP registers, and
5873 integral operands passed in integer registers. */
5874 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5880 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5881 the three platforms, so we can't avoid conditional compilation. */
5882 #if TARGET_ABI_OPEN_VMS
5884 if (mode
== VOIDmode
)
5885 return alpha_arg_info_reg_val (cum
);
5887 num_args
= cum
.num_args
;
5888 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5891 #elif TARGET_ABI_UNICOSMK
5895 /* If this is the last argument, generate the call info word (CIW). */
5896 /* ??? We don't include the caller's line number in the CIW because
5897 I don't know how to determine it if debug infos are turned off. */
5898 if (mode
== VOIDmode
)
5907 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5908 if (cum
.reg_args_type
[i
])
5909 lo
|= (1 << (7 - i
));
5911 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5914 lo
|= cum
.num_reg_words
;
5916 #if HOST_BITS_PER_WIDE_INT == 32
5917 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5919 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5920 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5923 ciw
= immed_double_const (lo
, hi
, DImode
);
5925 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5926 UNSPEC_UMK_LOAD_CIW
);
5929 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5930 num_args
= cum
.num_reg_words
;
5931 if (MUST_PASS_IN_STACK (mode
, type
)
5932 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5934 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5938 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5939 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5941 /* The argument fits in two registers. Note that we still need to
5942 reserve a register for empty structures. */
5946 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5949 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5950 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5951 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5955 #elif TARGET_ABI_OSF
5961 /* VOID is passed as a special flag for "last argument". */
5962 if (type
== void_type_node
)
5964 else if (MUST_PASS_IN_STACK (mode
, type
))
5966 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5970 #error Unhandled ABI
5973 return gen_rtx_REG (mode
, num_args
+ basereg
);
5976 /* Return true if TYPE must be returned in memory, instead of in registers. */
5979 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
5981 enum machine_mode mode
= VOIDmode
;
5986 mode
= TYPE_MODE (type
);
5988 /* All aggregates are returned in memory. */
5989 if (AGGREGATE_TYPE_P (type
))
5993 size
= GET_MODE_SIZE (mode
);
5994 switch (GET_MODE_CLASS (mode
))
5996 case MODE_VECTOR_FLOAT
:
5997 /* Pass all float vectors in memory, like an aggregate. */
6000 case MODE_COMPLEX_FLOAT
:
6001 /* We judge complex floats on the size of their element,
6002 not the size of the whole type. */
6003 size
= GET_MODE_UNIT_SIZE (mode
);
6008 case MODE_COMPLEX_INT
:
6009 case MODE_VECTOR_INT
:
6013 /* ??? We get called on all sorts of random stuff from
6014 aggregate_value_p. We can't abort, but it's not clear
6015 what's safe to return. Pretend it's a struct I guess. */
6019 /* Otherwise types must fit in one register. */
6020 return size
> UNITS_PER_WORD
;
6023 /* Define how to find the value returned by a function. VALTYPE is the
6024 data type of the value (as a tree). If the precise function being
6025 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6026 MODE is set instead of VALTYPE for libcalls.
6028 On Alpha the value is found in $0 for integer functions and
6029 $f0 for floating-point functions. */
6032 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
6033 enum machine_mode mode
)
6035 unsigned int regnum
;
6036 enum mode_class
class;
6038 #ifdef ENABLE_CHECKING
6039 if (valtype
&& alpha_return_in_memory (valtype
, func
))
6044 mode
= TYPE_MODE (valtype
);
6046 class = GET_MODE_CLASS (mode
);
6050 /* Do the same thing as PROMOTE_MODE. */
6054 case MODE_COMPLEX_INT
:
6055 case MODE_VECTOR_INT
:
6063 case MODE_COMPLEX_FLOAT
:
6065 enum machine_mode cmode
= GET_MODE_INNER (mode
);
6067 return gen_rtx_PARALLEL
6070 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
6072 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
6073 GEN_INT (GET_MODE_SIZE (cmode
)))));
6080 return gen_rtx_REG (mode
, regnum
);
6084 alpha_build_builtin_va_list (void)
6086 tree base
, ofs
, record
, type_decl
;
6088 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6089 return ptr_type_node
;
6091 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6092 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6093 TREE_CHAIN (record
) = type_decl
;
6094 TYPE_NAME (record
) = type_decl
;
6096 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6098 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6100 DECL_FIELD_CONTEXT (ofs
) = record
;
6102 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6104 DECL_FIELD_CONTEXT (base
) = record
;
6105 TREE_CHAIN (base
) = ofs
;
6107 TYPE_FIELDS (record
) = base
;
6108 layout_type (record
);
6113 /* Perform any needed actions needed for a function that is receiving a
6114 variable number of arguments. */
6117 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
,
6118 enum machine_mode mode ATTRIBUTE_UNUSED
,
6119 tree type ATTRIBUTE_UNUSED
,
6120 int *pretend_size
, int no_rtl
)
6122 #if TARGET_ABI_UNICOSMK
6123 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6124 arguments on the stack. Unfortunately, it doesn't always store the first
6125 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6126 with stdargs as we always have at least one named argument there. */
6127 int num_reg_words
= pcum
->num_reg_words
;
6128 if (num_reg_words
< 6)
6132 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words
+ 1)));
6133 emit_insn (gen_arg_home_umk ());
6137 #elif TARGET_ABI_OPEN_VMS
6138 /* For VMS, we allocate space for all 6 arg registers plus a count.
6140 However, if NO registers need to be saved, don't allocate any space.
6141 This is not only because we won't need the space, but because AP
6142 includes the current_pretend_args_size and we don't want to mess up
6143 any ap-relative addresses already made. */
6144 if (pcum
->num_args
< 6)
6148 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6149 emit_insn (gen_arg_home ());
6151 *pretend_size
= 7 * UNITS_PER_WORD
;
6154 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6155 only push those that are remaining. However, if NO registers need to
6156 be saved, don't allocate any space. This is not only because we won't
6157 need the space, but because AP includes the current_pretend_args_size
6158 and we don't want to mess up any ap-relative addresses already made.
6160 If we are not to use the floating-point registers, save the integer
6161 registers where we would put the floating-point registers. This is
6162 not the most efficient way to implement varargs with just one register
6163 class, but it isn't worth doing anything more efficient in this rare
6165 CUMULATIVE_ARGS cum
= *pcum
;
6172 int set
= get_varargs_alias_set ();
6175 tmp
= gen_rtx_MEM (BLKmode
,
6176 plus_constant (virtual_incoming_args_rtx
,
6177 (cum
+ 6) * UNITS_PER_WORD
));
6178 set_mem_alias_set (tmp
, set
);
6179 move_block_from_reg (16 + cum
, tmp
, 6 - cum
);
6181 tmp
= gen_rtx_MEM (BLKmode
,
6182 plus_constant (virtual_incoming_args_rtx
,
6183 cum
* UNITS_PER_WORD
));
6184 set_mem_alias_set (tmp
, set
);
6185 move_block_from_reg (16 + (TARGET_FPREGS
? 32 : 0) + cum
, tmp
,
6188 *pretend_size
= 12 * UNITS_PER_WORD
;
6193 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6195 HOST_WIDE_INT offset
;
6196 tree t
, offset_field
, base_field
;
6198 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6201 if (TARGET_ABI_UNICOSMK
)
6202 std_expand_builtin_va_start (valist
, nextarg
);
6204 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6205 up by 48, storing fp arg registers in the first 48 bytes, and the
6206 integer arg registers in the next 48 bytes. This is only done,
6207 however, if any integer registers need to be stored.
6209 If no integer registers need be stored, then we must subtract 48
6210 in order to account for the integer arg registers which are counted
6211 in argsize above, but which are not actually stored on the stack.
6212 Must further be careful here about structures straddling the last
6213 integer argument register; that futzes with pretend_args_size,
6214 which changes the meaning of AP. */
6217 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6219 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6221 if (TARGET_ABI_OPEN_VMS
)
6223 nextarg
= plus_constant (nextarg
, offset
);
6224 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6225 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6226 make_tree (ptr_type_node
, nextarg
));
6227 TREE_SIDE_EFFECTS (t
) = 1;
6229 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6233 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6234 offset_field
= TREE_CHAIN (base_field
);
6236 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6237 valist
, base_field
);
6238 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6239 valist
, offset_field
);
6241 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6242 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6243 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6244 TREE_SIDE_EFFECTS (t
) = 1;
6245 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6247 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6248 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6249 TREE_SIDE_EFFECTS (t
) = 1;
6250 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6255 alpha_va_arg (tree valist
, tree type
)
6258 tree t
, type_size
, rounded_size
;
6259 tree offset_field
, base_field
, addr_tree
, addend
;
6260 tree wide_type
, wide_ofs
;
6263 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6264 return std_expand_builtin_va_arg (valist
, type
);
6266 if (type
== error_mark_node
6267 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6268 || TREE_OVERFLOW (type_size
))
6269 rounded_size
= size_zero_node
;
6271 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6272 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6273 fold (build (PLUS_EXPR
, sizetype
,
6279 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6280 offset_field
= TREE_CHAIN (base_field
);
6282 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6283 valist
, base_field
);
6284 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6285 valist
, offset_field
);
6287 /* If the type could not be passed in registers, skip the block
6288 reserved for the registers. */
6289 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6291 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6292 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6293 offset_field
, build_int_2 (6*8, 0)));
6294 TREE_SIDE_EFFECTS (t
) = 1;
6295 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6298 wide_type
= make_signed_type (64);
6299 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6303 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6306 rounded_size
= size_int (UNITS_PER_WORD
);
6308 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
6310 rtx real_part
, imag_part
, value
, tmp
;
6312 real_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6313 imag_part
= alpha_va_arg (valist
, TREE_TYPE (type
));
6315 /* ??? Most irritatingly, we're not returning the value here,
6316 but the address. Since real_part and imag_part are not
6317 necessarily contiguous, we must copy to local storage. */
6319 real_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), real_part
);
6320 imag_part
= gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type
)), imag_part
);
6321 value
= gen_rtx_CONCAT (TYPE_MODE (type
), real_part
, imag_part
);
6323 tmp
= assign_temp (type
, 0, 1, 0);
6324 emit_move_insn (tmp
, value
);
6326 return XEXP (tmp
, 0);
6328 else if (TREE_CODE (type
) == REAL_TYPE
)
6330 tree fpaddend
, cond
;
6332 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6333 addend
, build_int_2 (-6*8, 0)));
6335 cond
= fold (build (LT_EXPR
, integer_type_node
,
6336 wide_ofs
, build_int_2 (6*8, 0)));
6338 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6342 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6343 base_field
, addend
);
6345 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6346 addr
= copy_to_reg (addr
);
6348 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6349 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6350 offset_field
, rounded_size
));
6351 TREE_SIDE_EFFECTS (t
) = 1;
6352 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6356 addr
= force_reg (Pmode
, addr
);
6357 addr
= gen_rtx_MEM (Pmode
, addr
);
6367 ALPHA_BUILTIN_CMPBGE
,
6368 ALPHA_BUILTIN_EXTBL
,
6369 ALPHA_BUILTIN_EXTWL
,
6370 ALPHA_BUILTIN_EXTLL
,
6371 ALPHA_BUILTIN_EXTQL
,
6372 ALPHA_BUILTIN_EXTWH
,
6373 ALPHA_BUILTIN_EXTLH
,
6374 ALPHA_BUILTIN_EXTQH
,
6375 ALPHA_BUILTIN_INSBL
,
6376 ALPHA_BUILTIN_INSWL
,
6377 ALPHA_BUILTIN_INSLL
,
6378 ALPHA_BUILTIN_INSQL
,
6379 ALPHA_BUILTIN_INSWH
,
6380 ALPHA_BUILTIN_INSLH
,
6381 ALPHA_BUILTIN_INSQH
,
6382 ALPHA_BUILTIN_MSKBL
,
6383 ALPHA_BUILTIN_MSKWL
,
6384 ALPHA_BUILTIN_MSKLL
,
6385 ALPHA_BUILTIN_MSKQL
,
6386 ALPHA_BUILTIN_MSKWH
,
6387 ALPHA_BUILTIN_MSKLH
,
6388 ALPHA_BUILTIN_MSKQH
,
6389 ALPHA_BUILTIN_UMULH
,
6391 ALPHA_BUILTIN_ZAPNOT
,
6392 ALPHA_BUILTIN_AMASK
,
6393 ALPHA_BUILTIN_IMPLVER
,
6395 ALPHA_BUILTIN_THREAD_POINTER
,
6396 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6399 ALPHA_BUILTIN_MINUB8
,
6400 ALPHA_BUILTIN_MINSB8
,
6401 ALPHA_BUILTIN_MINUW4
,
6402 ALPHA_BUILTIN_MINSW4
,
6403 ALPHA_BUILTIN_MAXUB8
,
6404 ALPHA_BUILTIN_MAXSB8
,
6405 ALPHA_BUILTIN_MAXUW4
,
6406 ALPHA_BUILTIN_MAXSW4
,
6410 ALPHA_BUILTIN_UNPKBL
,
6411 ALPHA_BUILTIN_UNPKBW
,
6416 ALPHA_BUILTIN_CTPOP
,
6421 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6422 CODE_FOR_builtin_cmpbge
,
6423 CODE_FOR_builtin_extbl
,
6424 CODE_FOR_builtin_extwl
,
6425 CODE_FOR_builtin_extll
,
6426 CODE_FOR_builtin_extql
,
6427 CODE_FOR_builtin_extwh
,
6428 CODE_FOR_builtin_extlh
,
6429 CODE_FOR_builtin_extqh
,
6430 CODE_FOR_builtin_insbl
,
6431 CODE_FOR_builtin_inswl
,
6432 CODE_FOR_builtin_insll
,
6433 CODE_FOR_builtin_insql
,
6434 CODE_FOR_builtin_inswh
,
6435 CODE_FOR_builtin_inslh
,
6436 CODE_FOR_builtin_insqh
,
6437 CODE_FOR_builtin_mskbl
,
6438 CODE_FOR_builtin_mskwl
,
6439 CODE_FOR_builtin_mskll
,
6440 CODE_FOR_builtin_mskql
,
6441 CODE_FOR_builtin_mskwh
,
6442 CODE_FOR_builtin_msklh
,
6443 CODE_FOR_builtin_mskqh
,
6444 CODE_FOR_umuldi3_highpart
,
6445 CODE_FOR_builtin_zap
,
6446 CODE_FOR_builtin_zapnot
,
6447 CODE_FOR_builtin_amask
,
6448 CODE_FOR_builtin_implver
,
6449 CODE_FOR_builtin_rpcc
,
6454 CODE_FOR_builtin_minub8
,
6455 CODE_FOR_builtin_minsb8
,
6456 CODE_FOR_builtin_minuw4
,
6457 CODE_FOR_builtin_minsw4
,
6458 CODE_FOR_builtin_maxub8
,
6459 CODE_FOR_builtin_maxsb8
,
6460 CODE_FOR_builtin_maxuw4
,
6461 CODE_FOR_builtin_maxsw4
,
6462 CODE_FOR_builtin_perr
,
6463 CODE_FOR_builtin_pklb
,
6464 CODE_FOR_builtin_pkwb
,
6465 CODE_FOR_builtin_unpkbl
,
6466 CODE_FOR_builtin_unpkbw
,
6469 CODE_FOR_builtin_cttz
,
6470 CODE_FOR_builtin_ctlz
,
6471 CODE_FOR_builtin_ctpop
6474 struct alpha_builtin_def
6477 enum alpha_builtin code
;
6478 unsigned int target_mask
;
6481 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6482 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6483 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6486 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6487 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6488 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6489 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6490 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6491 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6492 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6493 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6494 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6497 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6498 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6499 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6500 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6501 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6502 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6503 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6504 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6505 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6506 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6507 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6508 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6509 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6510 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6511 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6512 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6513 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6514 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6515 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6516 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6517 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6518 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6519 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6520 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6521 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6522 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6523 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6524 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6525 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6526 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6527 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6528 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6529 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6530 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6531 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6535 alpha_init_builtins (void)
6537 const struct alpha_builtin_def
*p
;
6541 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6543 p
= zero_arg_builtins
;
6544 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6545 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6546 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6549 ftype
= build_function_type_list (long_integer_type_node
,
6550 long_integer_type_node
, NULL_TREE
);
6552 p
= one_arg_builtins
;
6553 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6554 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6555 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6558 ftype
= build_function_type_list (long_integer_type_node
,
6559 long_integer_type_node
,
6560 long_integer_type_node
, NULL_TREE
);
6562 p
= two_arg_builtins
;
6563 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6564 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6565 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6568 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6569 builtin_function ("__builtin_thread_pointer", ftype
,
6570 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6573 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6574 builtin_function ("__builtin_set_thread_pointer", ftype
,
6575 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6579 /* Expand an expression EXP that calls a built-in function,
6580 with result going to TARGET if that's convenient
6581 (and in mode MODE if that's convenient).
6582 SUBTARGET may be used as the target for computing one of EXP's operands.
6583 IGNORE is nonzero if the value is to be ignored. */
6586 alpha_expand_builtin (tree exp
, rtx target
,
6587 rtx subtarget ATTRIBUTE_UNUSED
,
6588 enum machine_mode mode ATTRIBUTE_UNUSED
,
6589 int ignore ATTRIBUTE_UNUSED
)
6593 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6594 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6595 tree arglist
= TREE_OPERAND (exp
, 1);
6596 enum insn_code icode
;
6597 rtx op
[MAX_ARGS
], pat
;
6601 if (fcode
>= ALPHA_BUILTIN_max
)
6602 internal_error ("bad builtin fcode");
6603 icode
= code_for_builtin
[fcode
];
6605 internal_error ("bad builtin fcode");
6607 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6609 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6611 arglist
= TREE_CHAIN (arglist
), arity
++)
6613 const struct insn_operand_data
*insn_op
;
6615 tree arg
= TREE_VALUE (arglist
);
6616 if (arg
== error_mark_node
)
6618 if (arity
> MAX_ARGS
)
6621 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6623 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6625 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6626 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6631 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6633 || GET_MODE (target
) != tmode
6634 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6635 target
= gen_reg_rtx (tmode
);
6641 pat
= GEN_FCN (icode
) (target
);
6645 pat
= GEN_FCN (icode
) (target
, op
[0]);
6647 pat
= GEN_FCN (icode
) (op
[0]);
6650 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6665 /* This page contains routines that are used to determine what the function
6666 prologue and epilogue code will do and write them out. */
6668 /* Compute the size of the save area in the stack. */
6670 /* These variables are used for communication between the following functions.
6671 They indicate various things about the current function being compiled
6672 that are used to tell what kind of prologue, epilogue and procedure
6673 descriptior to generate. */
6675 /* Nonzero if we need a stack procedure. */
6676 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6677 static enum alpha_procedure_types alpha_procedure_type
;
6679 /* Register number (either FP or SP) that is used to unwind the frame. */
6680 static int vms_unwind_regno
;
6682 /* Register number used to save FP. We need not have one for RA since
6683 we don't modify it for register procedures. This is only defined
6684 for register frame procedures. */
6685 static int vms_save_fp_regno
;
6687 /* Register number used to reference objects off our PV. */
6688 static int vms_base_regno
;
6690 /* Compute register masks for saved registers. */
6693 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
6695 unsigned long imask
= 0;
6696 unsigned long fmask
= 0;
6699 /* Irritatingly, there are two kinds of thunks -- those created with
6700 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6701 through the regular part of the compiler. In the
6702 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6703 info, but assemble_start_function wants to output .frame and
6704 .mask directives. */
6705 if (current_function_is_thunk
&& !no_new_pseudos
)
6712 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6713 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6715 /* One for every register we have to save. */
6716 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6717 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6718 && regs_ever_live
[i
] && i
!= REG_RA
6719 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6722 imask
|= (1UL << i
);
6724 fmask
|= (1UL << (i
- 32));
6727 /* We need to restore these for the handler. */
6728 if (current_function_calls_eh_return
)
6732 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6733 if (regno
== INVALID_REGNUM
)
6735 imask
|= 1UL << regno
;
6738 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6739 avoid hackery in unwind-dw2.c, we need to actively store a
6740 zero in the prologue of _Unwind_RaiseException et al. */
6744 /* If any register spilled, then spill the return address also. */
6745 /* ??? This is required by the Digital stack unwind specification
6746 and isn't needed if we're doing Dwarf2 unwinding. */
6747 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6748 imask
|= (1UL << REG_RA
);
6755 alpha_sa_size (void)
6757 unsigned long mask
[2];
6761 alpha_sa_mask (&mask
[0], &mask
[1]);
6763 if (TARGET_ABI_UNICOSMK
)
6765 if (mask
[0] || mask
[1])
6770 for (j
= 0; j
< 2; ++j
)
6771 for (i
= 0; i
< 32; ++i
)
6772 if ((mask
[j
] >> i
) & 1)
6776 if (TARGET_ABI_UNICOSMK
)
6778 /* We might not need to generate a frame if we don't make any calls
6779 (including calls to __T3E_MISMATCH if this is a vararg function),
6780 don't have any local variables which require stack slots, don't
6781 use alloca and have not determined that we need a frame for other
6784 alpha_procedure_type
6785 = (sa_size
|| get_frame_size() != 0
6786 || current_function_outgoing_args_size
6787 || current_function_stdarg
|| current_function_calls_alloca
6788 || frame_pointer_needed
)
6789 ? PT_STACK
: PT_REGISTER
;
6791 /* Always reserve space for saving callee-saved registers if we
6792 need a frame as required by the calling convention. */
6793 if (alpha_procedure_type
== PT_STACK
)
6796 else if (TARGET_ABI_OPEN_VMS
)
6798 /* Start by assuming we can use a register procedure if we don't
6799 make any calls (REG_RA not used) or need to save any
6800 registers and a stack procedure if we do. */
6801 if ((mask
[0] >> REG_RA
) & 1)
6802 alpha_procedure_type
= PT_STACK
;
6803 else if (get_frame_size() != 0)
6804 alpha_procedure_type
= PT_REGISTER
;
6806 alpha_procedure_type
= PT_NULL
;
6808 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6809 made the final decision on stack procedure vs register procedure. */
6810 if (alpha_procedure_type
== PT_STACK
)
6813 /* Decide whether to refer to objects off our PV via FP or PV.
6814 If we need FP for something else or if we receive a nonlocal
6815 goto (which expects PV to contain the value), we must use PV.
6816 Otherwise, start by assuming we can use FP. */
6819 = (frame_pointer_needed
6820 || current_function_has_nonlocal_label
6821 || alpha_procedure_type
== PT_STACK
6822 || current_function_outgoing_args_size
)
6823 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6825 /* If we want to copy PV into FP, we need to find some register
6826 in which to save FP. */
6828 vms_save_fp_regno
= -1;
6829 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6830 for (i
= 0; i
< 32; i
++)
6831 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6832 vms_save_fp_regno
= i
;
6834 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6835 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6836 else if (alpha_procedure_type
== PT_NULL
)
6837 vms_base_regno
= REG_PV
;
6839 /* Stack unwinding should be done via FP unless we use it for PV. */
6840 vms_unwind_regno
= (vms_base_regno
== REG_PV
6841 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6843 /* If this is a stack procedure, allow space for saving FP and RA. */
6844 if (alpha_procedure_type
== PT_STACK
)
6849 /* Our size must be even (multiple of 16 bytes). */
6857 /* Define the offset between two registers, one to be eliminated,
6858 and the other its replacement, at the start of a routine. */
6861 alpha_initial_elimination_offset (unsigned int from
,
6862 unsigned int to ATTRIBUTE_UNUSED
)
6866 ret
= alpha_sa_size ();
6867 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
6869 if (from
== FRAME_POINTER_REGNUM
)
6871 else if (from
== ARG_POINTER_REGNUM
)
6872 ret
+= (ALPHA_ROUND (get_frame_size ()
6873 + current_function_pretend_args_size
)
6874 - current_function_pretend_args_size
);
6882 alpha_pv_save_size (void)
6885 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6889 alpha_using_fp (void)
6892 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6895 #if TARGET_ABI_OPEN_VMS
6897 const struct attribute_spec vms_attribute_table
[] =
6899 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6900 { "overlaid", 0, 0, true, false, false, NULL
},
6901 { "global", 0, 0, true, false, false, NULL
},
6902 { "initialize", 0, 0, true, false, false, NULL
},
6903 { NULL
, 0, 0, false, false, false, NULL
}
6909 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6911 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
6915 alpha_find_lo_sum_using_gp (rtx insn
)
6917 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
6921 alpha_does_function_need_gp (void)
6925 /* The GP being variable is an OSF abi thing. */
6926 if (! TARGET_ABI_OSF
)
6929 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6932 if (current_function_is_thunk
)
6935 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6936 Even if we are a static function, we still need to do this in case
6937 our address is taken and passed to something like qsort. */
6939 push_topmost_sequence ();
6940 insn
= get_insns ();
6941 pop_topmost_sequence ();
6943 for (; insn
; insn
= NEXT_INSN (insn
))
6945 && GET_CODE (PATTERN (insn
)) != USE
6946 && GET_CODE (PATTERN (insn
)) != CLOBBER
6947 && get_attr_usegp (insn
))
6954 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6958 set_frame_related_p (void)
6960 rtx seq
= get_insns ();
6971 while (insn
!= NULL_RTX
)
6973 RTX_FRAME_RELATED_P (insn
) = 1;
6974 insn
= NEXT_INSN (insn
);
6976 seq
= emit_insn (seq
);
6980 seq
= emit_insn (seq
);
6981 RTX_FRAME_RELATED_P (seq
) = 1;
6986 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6988 /* Write function prologue. */
6990 /* On vms we have two kinds of functions:
6992 - stack frame (PROC_STACK)
6993 these are 'normal' functions with local vars and which are
6994 calling other functions
6995 - register frame (PROC_REGISTER)
6996 keeps all data in registers, needs no stack
6998 We must pass this to the assembler so it can generate the
6999 proper pdsc (procedure descriptor)
7000 This is done with the '.pdesc' command.
7002 On not-vms, we don't really differentiate between the two, as we can
7003 simply allocate stack without saving registers. */
7006 alpha_expand_prologue (void)
7008 /* Registers to save. */
7009 unsigned long imask
= 0;
7010 unsigned long fmask
= 0;
7011 /* Stack space needed for pushing registers clobbered by us. */
7012 HOST_WIDE_INT sa_size
;
7013 /* Complete stack size needed. */
7014 HOST_WIDE_INT frame_size
;
7015 /* Offset from base reg to register save area. */
7016 HOST_WIDE_INT reg_offset
;
7020 sa_size
= alpha_sa_size ();
7022 frame_size
= get_frame_size ();
7023 if (TARGET_ABI_OPEN_VMS
)
7024 frame_size
= ALPHA_ROUND (sa_size
7025 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7027 + current_function_pretend_args_size
);
7028 else if (TARGET_ABI_UNICOSMK
)
7029 /* We have to allocate space for the DSIB if we generate a frame. */
7030 frame_size
= ALPHA_ROUND (sa_size
7031 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7032 + ALPHA_ROUND (frame_size
7033 + current_function_outgoing_args_size
);
7035 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7037 + ALPHA_ROUND (frame_size
7038 + current_function_pretend_args_size
));
7040 if (TARGET_ABI_OPEN_VMS
)
7043 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7045 alpha_sa_mask (&imask
, &fmask
);
7047 /* Emit an insn to reload GP, if needed. */
7050 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7051 if (alpha_function_needs_gp
)
7052 emit_insn (gen_prologue_ldgp ());
7055 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7056 the call to mcount ourselves, rather than having the linker do it
7057 magically in response to -pg. Since _mcount has special linkage,
7058 don't represent the call as a call. */
7059 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7060 emit_insn (gen_prologue_mcount ());
7062 if (TARGET_ABI_UNICOSMK
)
7063 unicosmk_gen_dsib (&imask
);
7065 /* Adjust the stack by the frame size. If the frame size is > 4096
7066 bytes, we need to be sure we probe somewhere in the first and last
7067 4096 bytes (we can probably get away without the latter test) and
7068 every 8192 bytes in between. If the frame size is > 32768, we
7069 do this in a loop. Otherwise, we generate the explicit probe
7072 Note that we are only allowed to adjust sp once in the prologue. */
7074 if (frame_size
<= 32768)
7076 if (frame_size
> 4096)
7081 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7084 while ((probed
+= 8192) < frame_size
);
7086 /* We only have to do this probe if we aren't saving registers. */
7087 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7088 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7091 if (frame_size
!= 0)
7092 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7093 GEN_INT (TARGET_ABI_UNICOSMK
7099 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7100 number of 8192 byte blocks to probe. We then probe each block
7101 in the loop and then set SP to the proper location. If the
7102 amount remaining is > 4096, we have to do one more probe if we
7103 are not saving any registers. */
7105 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7106 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7107 rtx ptr
= gen_rtx_REG (DImode
, 22);
7108 rtx count
= gen_rtx_REG (DImode
, 23);
7111 emit_move_insn (count
, GEN_INT (blocks
));
7112 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7113 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7115 /* Because of the difficulty in emitting a new basic block this
7116 late in the compilation, generate the loop as a single insn. */
7117 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7119 if (leftover
> 4096 && sa_size
== 0)
7121 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7122 MEM_VOLATILE_P (last
) = 1;
7123 emit_move_insn (last
, const0_rtx
);
7126 if (TARGET_ABI_WINDOWS_NT
)
7128 /* For NT stack unwind (done by 'reverse execution'), it's
7129 not OK to take the result of a loop, even though the value
7130 is already in ptr, so we reload it via a single operation
7131 and subtract it to sp.
7133 Yes, that's correct -- we have to reload the whole constant
7134 into a temporary via ldah+lda then subtract from sp. To
7135 ensure we get ldah+lda, we use a special pattern. */
7137 HOST_WIDE_INT lo
, hi
;
7138 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7139 hi
= frame_size
- lo
;
7141 emit_move_insn (ptr
, GEN_INT (hi
));
7142 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7143 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7148 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7149 GEN_INT (-leftover
)));
7152 /* This alternative is special, because the DWARF code cannot
7153 possibly intuit through the loop above. So we invent this
7154 note it looks at instead. */
7155 RTX_FRAME_RELATED_P (seq
) = 1;
7157 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7158 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7159 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7160 GEN_INT (TARGET_ABI_UNICOSMK
7166 if (!TARGET_ABI_UNICOSMK
)
7168 /* Cope with very large offsets to the register save area. */
7169 sa_reg
= stack_pointer_rtx
;
7170 if (reg_offset
+ sa_size
> 0x8000)
7172 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7175 if (low
+ sa_size
<= 0x8000)
7176 bias
= reg_offset
- low
, reg_offset
= low
;
7178 bias
= reg_offset
, reg_offset
= 0;
7180 sa_reg
= gen_rtx_REG (DImode
, 24);
7181 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7185 /* Save regs in stack order. Beginning with VMS PV. */
7186 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7188 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7189 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7190 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7193 /* Save register RA next. */
7194 if (imask
& (1UL << REG_RA
))
7196 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7197 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7198 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7199 imask
&= ~(1UL << REG_RA
);
7203 /* Now save any other registers required to be saved. */
7204 for (i
= 0; i
< 31; i
++)
7205 if (imask
& (1UL << i
))
7207 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7208 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7209 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7213 /* Store a zero if requested for unwinding. */
7214 if (imask
& (1UL << 31))
7218 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7219 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7220 insn
= emit_move_insn (mem
, const0_rtx
);
7222 RTX_FRAME_RELATED_P (insn
) = 1;
7223 t
= gen_rtx_REG (Pmode
, 31);
7224 t
= gen_rtx_SET (VOIDmode
, mem
, t
);
7225 t
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, t
, REG_NOTES (insn
));
7226 REG_NOTES (insn
) = t
;
7231 for (i
= 0; i
< 31; i
++)
7232 if (fmask
& (1UL << i
))
7234 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7235 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7236 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7240 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7242 /* The standard frame on the T3E includes space for saving registers.
7243 We just have to use it. We don't have to save the return address and
7244 the old frame pointer here - they are saved in the DSIB. */
7247 for (i
= 9; i
< 15; i
++)
7248 if (imask
& (1UL << i
))
7250 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7252 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7253 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7256 for (i
= 2; i
< 10; i
++)
7257 if (fmask
& (1UL << i
))
7259 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7261 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7262 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7267 if (TARGET_ABI_OPEN_VMS
)
7269 if (alpha_procedure_type
== PT_REGISTER
)
7270 /* Register frame procedures save the fp.
7271 ?? Ought to have a dwarf2 save for this. */
7272 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7273 hard_frame_pointer_rtx
);
7275 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7276 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7277 gen_rtx_REG (DImode
, REG_PV
)));
7279 if (alpha_procedure_type
!= PT_NULL
7280 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7281 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7283 /* If we have to allocate space for outgoing args, do it now. */
7284 if (current_function_outgoing_args_size
!= 0)
7287 = emit_move_insn (stack_pointer_rtx
,
7289 (hard_frame_pointer_rtx
,
7291 (current_function_outgoing_args_size
))));
7293 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7294 if ! frame_pointer_needed. Setting the bit will change the CFA
7295 computation rule to use sp again, which would be wrong if we had
7296 frame_pointer_needed, as this means sp might move unpredictably
7300 frame_pointer_needed
7301 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7303 current_function_outgoing_args_size != 0
7304 => alpha_procedure_type != PT_NULL,
7306 so when we are not setting the bit here, we are guaranteed to
7307 have emitted an FRP frame pointer update just before. */
7308 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7311 else if (!TARGET_ABI_UNICOSMK
)
7313 /* If we need a frame pointer, set it from the stack pointer. */
7314 if (frame_pointer_needed
)
7316 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7317 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7319 /* This must always be the last instruction in the
7320 prologue, thus we emit a special move + clobber. */
7321 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7322 stack_pointer_rtx
, sa_reg
)));
7326 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7327 the prologue, for exception handling reasons, we cannot do this for
7328 any insn that might fault. We could prevent this for mems with a
7329 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7330 have to prevent all such scheduling with a blockage.
7332 Linux, on the other hand, never bothered to implement OSF/1's
7333 exception handling, and so doesn't care about such things. Anyone
7334 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7336 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7337 emit_insn (gen_blockage ());
7340 /* Output the textual info surrounding the prologue. */
7343 alpha_start_function (FILE *file
, const char *fnname
,
7344 tree decl ATTRIBUTE_UNUSED
)
7346 unsigned long imask
= 0;
7347 unsigned long fmask
= 0;
7348 /* Stack space needed for pushing registers clobbered by us. */
7349 HOST_WIDE_INT sa_size
;
7350 /* Complete stack size needed. */
7351 unsigned HOST_WIDE_INT frame_size
;
7352 /* Offset from base reg to register save area. */
7353 HOST_WIDE_INT reg_offset
;
7354 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7357 /* Don't emit an extern directive for functions defined in the same file. */
7358 if (TARGET_ABI_UNICOSMK
)
7361 name_tree
= get_identifier (fnname
);
7362 TREE_ASM_WRITTEN (name_tree
) = 1;
7365 alpha_fnname
= fnname
;
7366 sa_size
= alpha_sa_size ();
7368 frame_size
= get_frame_size ();
7369 if (TARGET_ABI_OPEN_VMS
)
7370 frame_size
= ALPHA_ROUND (sa_size
7371 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7373 + current_function_pretend_args_size
);
7374 else if (TARGET_ABI_UNICOSMK
)
7375 frame_size
= ALPHA_ROUND (sa_size
7376 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7377 + ALPHA_ROUND (frame_size
7378 + current_function_outgoing_args_size
);
7380 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7382 + ALPHA_ROUND (frame_size
7383 + current_function_pretend_args_size
));
7385 if (TARGET_ABI_OPEN_VMS
)
7388 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7390 alpha_sa_mask (&imask
, &fmask
);
7392 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7393 We have to do that before the .ent directive as we cannot switch
7394 files within procedures with native ecoff because line numbers are
7395 linked to procedure descriptors.
7396 Outputting the lineno helps debugging of one line functions as they
7397 would otherwise get no line number at all. Please note that we would
7398 like to put out last_linenum from final.c, but it is not accessible. */
7400 if (write_symbols
== SDB_DEBUG
)
7402 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7403 ASM_OUTPUT_SOURCE_FILENAME (file
,
7404 DECL_SOURCE_FILE (current_function_decl
));
7406 #ifdef ASM_OUTPUT_SOURCE_LINE
7407 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7408 ASM_OUTPUT_SOURCE_LINE (file
,
7409 DECL_SOURCE_LINE (current_function_decl
), 0);
7413 /* Issue function start and label. */
7414 if (TARGET_ABI_OPEN_VMS
7415 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7417 fputs ("\t.ent ", file
);
7418 assemble_name (file
, fnname
);
7421 /* If the function needs GP, we'll write the "..ng" label there.
7422 Otherwise, do it here. */
7424 && ! alpha_function_needs_gp
7425 && ! current_function_is_thunk
)
7428 assemble_name (file
, fnname
);
7429 fputs ("..ng:\n", file
);
7433 strcpy (entry_label
, fnname
);
7434 if (TARGET_ABI_OPEN_VMS
)
7435 strcat (entry_label
, "..en");
7437 /* For public functions, the label must be globalized by appending an
7438 additional colon. */
7439 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7440 strcat (entry_label
, ":");
7442 ASM_OUTPUT_LABEL (file
, entry_label
);
7443 inside_function
= TRUE
;
7445 if (TARGET_ABI_OPEN_VMS
)
7446 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7448 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7449 && !flag_inhibit_size_directive
)
7451 /* Set flags in procedure descriptor to request IEEE-conformant
7452 math-library routines. The value we set it to is PDSC_EXC_IEEE
7453 (/usr/include/pdsc.h). */
7454 fputs ("\t.eflag 48\n", file
);
7457 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7458 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7459 alpha_arg_offset
= -frame_size
+ 48;
7461 /* Describe our frame. If the frame size is larger than an integer,
7462 print it as zero to avoid an assembler error. We won't be
7463 properly describing such a frame, but that's the best we can do. */
7464 if (TARGET_ABI_UNICOSMK
)
7466 else if (TARGET_ABI_OPEN_VMS
)
7467 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7468 HOST_WIDE_INT_PRINT_DEC
"\n",
7470 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7472 else if (!flag_inhibit_size_directive
)
7473 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7474 (frame_pointer_needed
7475 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7476 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7477 current_function_pretend_args_size
);
7479 /* Describe which registers were spilled. */
7480 if (TARGET_ABI_UNICOSMK
)
7482 else if (TARGET_ABI_OPEN_VMS
)
7485 /* ??? Does VMS care if mask contains ra? The old code didn't
7486 set it, so I don't here. */
7487 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7489 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7490 if (alpha_procedure_type
== PT_REGISTER
)
7491 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7493 else if (!flag_inhibit_size_directive
)
7497 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7498 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7500 for (i
= 0; i
< 32; ++i
)
7501 if (imask
& (1UL << i
))
7506 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7507 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7510 #if TARGET_ABI_OPEN_VMS
7511 /* Ifdef'ed cause link_section are only available then. */
7512 readonly_data_section ();
7513 fprintf (file
, "\t.align 3\n");
7514 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7515 fputs ("\t.ascii \"", file
);
7516 assemble_name (file
, fnname
);
7517 fputs ("\\0\"\n", file
);
7518 alpha_need_linkage (fnname
, 1);
7523 /* Emit the .prologue note at the scheduled end of the prologue. */
7526 alpha_output_function_end_prologue (FILE *file
)
7528 if (TARGET_ABI_UNICOSMK
)
7530 else if (TARGET_ABI_OPEN_VMS
)
7531 fputs ("\t.prologue\n", file
);
7532 else if (TARGET_ABI_WINDOWS_NT
)
7533 fputs ("\t.prologue 0\n", file
);
7534 else if (!flag_inhibit_size_directive
)
7535 fprintf (file
, "\t.prologue %d\n",
7536 alpha_function_needs_gp
|| current_function_is_thunk
);
7539 /* Write function epilogue. */
7541 /* ??? At some point we will want to support full unwind, and so will
7542 need to mark the epilogue as well. At the moment, we just confuse
7545 #define FRP(exp) exp
7548 alpha_expand_epilogue (void)
7550 /* Registers to save. */
7551 unsigned long imask
= 0;
7552 unsigned long fmask
= 0;
7553 /* Stack space needed for pushing registers clobbered by us. */
7554 HOST_WIDE_INT sa_size
;
7555 /* Complete stack size needed. */
7556 HOST_WIDE_INT frame_size
;
7557 /* Offset from base reg to register save area. */
7558 HOST_WIDE_INT reg_offset
;
7559 int fp_is_frame_pointer
, fp_offset
;
7560 rtx sa_reg
, sa_reg_exp
= NULL
;
7561 rtx sp_adj1
, sp_adj2
, mem
;
7565 sa_size
= alpha_sa_size ();
7567 frame_size
= get_frame_size ();
7568 if (TARGET_ABI_OPEN_VMS
)
7569 frame_size
= ALPHA_ROUND (sa_size
7570 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7572 + current_function_pretend_args_size
);
7573 else if (TARGET_ABI_UNICOSMK
)
7574 frame_size
= ALPHA_ROUND (sa_size
7575 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7576 + ALPHA_ROUND (frame_size
7577 + current_function_outgoing_args_size
);
7579 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7581 + ALPHA_ROUND (frame_size
7582 + current_function_pretend_args_size
));
7584 if (TARGET_ABI_OPEN_VMS
)
7586 if (alpha_procedure_type
== PT_STACK
)
7592 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7594 alpha_sa_mask (&imask
, &fmask
);
7597 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7598 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7600 sa_reg
= stack_pointer_rtx
;
7602 if (current_function_calls_eh_return
)
7603 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7607 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7609 /* If we have a frame pointer, restore SP from it. */
7610 if ((TARGET_ABI_OPEN_VMS
7611 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7612 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7613 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7615 /* Cope with very large offsets to the register save area. */
7616 if (reg_offset
+ sa_size
> 0x8000)
7618 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7621 if (low
+ sa_size
<= 0x8000)
7622 bias
= reg_offset
- low
, reg_offset
= low
;
7624 bias
= reg_offset
, reg_offset
= 0;
7626 sa_reg
= gen_rtx_REG (DImode
, 22);
7627 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7629 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7632 /* Restore registers in order, excepting a true frame pointer. */
7634 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7636 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7637 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7640 imask
&= ~(1UL << REG_RA
);
7642 for (i
= 0; i
< 31; ++i
)
7643 if (imask
& (1UL << i
))
7645 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7646 fp_offset
= reg_offset
;
7649 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7650 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7651 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7656 if (imask
& (1UL << 31))
7659 for (i
= 0; i
< 31; ++i
)
7660 if (fmask
& (1UL << i
))
7662 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7663 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7664 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7668 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7670 /* Restore callee-saved general-purpose registers. */
7674 for (i
= 9; i
< 15; i
++)
7675 if (imask
& (1UL << i
))
7677 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7679 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7680 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7684 for (i
= 2; i
< 10; i
++)
7685 if (fmask
& (1UL << i
))
7687 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7689 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7690 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7694 /* Restore the return address from the DSIB. */
7696 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7697 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7698 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7701 if (frame_size
|| eh_ofs
)
7703 sp_adj1
= stack_pointer_rtx
;
7707 sp_adj1
= gen_rtx_REG (DImode
, 23);
7708 emit_move_insn (sp_adj1
,
7709 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7712 /* If the stack size is large, begin computation into a temporary
7713 register so as not to interfere with a potential fp restore,
7714 which must be consecutive with an SP restore. */
7715 if (frame_size
< 32768
7716 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7717 sp_adj2
= GEN_INT (frame_size
);
7718 else if (TARGET_ABI_UNICOSMK
)
7720 sp_adj1
= gen_rtx_REG (DImode
, 23);
7721 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7722 sp_adj2
= const0_rtx
;
7724 else if (frame_size
< 0x40007fffL
)
7726 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7728 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7729 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7733 sp_adj1
= gen_rtx_REG (DImode
, 23);
7734 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7736 sp_adj2
= GEN_INT (low
);
7740 rtx tmp
= gen_rtx_REG (DImode
, 23);
7741 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7744 /* We can't drop new things to memory this late, afaik,
7745 so build it up by pieces. */
7746 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7747 -(frame_size
< 0)));
7753 /* From now on, things must be in order. So emit blockages. */
7755 /* Restore the frame pointer. */
7756 if (TARGET_ABI_UNICOSMK
)
7758 emit_insn (gen_blockage ());
7759 mem
= gen_rtx_MEM (DImode
,
7760 plus_constant (hard_frame_pointer_rtx
, -16));
7761 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7762 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7764 else if (fp_is_frame_pointer
)
7766 emit_insn (gen_blockage ());
7767 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7768 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7769 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7771 else if (TARGET_ABI_OPEN_VMS
)
7773 emit_insn (gen_blockage ());
7774 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7775 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7778 /* Restore the stack pointer. */
7779 emit_insn (gen_blockage ());
7780 if (sp_adj2
== const0_rtx
)
7781 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7783 FRP (emit_move_insn (stack_pointer_rtx
,
7784 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7788 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7790 emit_insn (gen_blockage ());
7791 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7792 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7794 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7796 /* Decrement the frame pointer if the function does not have a
7799 emit_insn (gen_blockage ());
7800 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7801 hard_frame_pointer_rtx
, GEN_INT (-1))));
7806 /* Output the rest of the textual info surrounding the epilogue. */
7809 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
7811 /* End the function. */
7812 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7814 fputs ("\t.end ", file
);
7815 assemble_name (file
, fnname
);
7818 inside_function
= FALSE
;
7820 #if TARGET_ABI_OPEN_VMS
7821 alpha_write_linkage (file
, fnname
, decl
);
7824 /* Output jump tables and the static subroutine information block. */
7825 if (TARGET_ABI_UNICOSMK
)
7827 unicosmk_output_ssib (file
, fnname
);
7828 unicosmk_output_deferred_case_vectors (file
);
7833 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7835 In order to avoid the hordes of differences between generated code
7836 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7837 lots of code loading up large constants, generate rtl and emit it
7838 instead of going straight to text.
7840 Not sure why this idea hasn't been explored before... */
7843 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7844 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
7847 HOST_WIDE_INT hi
, lo
;
7848 rtx
this, insn
, funexp
;
7850 /* We always require a valid GP. */
7851 emit_insn (gen_prologue_ldgp ());
7852 emit_note (NOTE_INSN_PROLOGUE_END
);
7854 /* Find the "this" pointer. If the function returns a structure,
7855 the structure return pointer is in $16. */
7856 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
7857 this = gen_rtx_REG (Pmode
, 17);
7859 this = gen_rtx_REG (Pmode
, 16);
7861 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7862 entire constant for the add. */
7863 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7864 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7865 if (hi
+ lo
== delta
)
7868 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7870 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7874 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7875 delta
, -(delta
< 0));
7876 emit_insn (gen_adddi3 (this, this, tmp
));
7879 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7884 tmp
= gen_rtx_REG (Pmode
, 0);
7885 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
7887 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
7888 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7889 if (hi
+ lo
== vcall_offset
)
7892 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
7896 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
7897 vcall_offset
, -(vcall_offset
< 0));
7898 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
7902 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
7905 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
7907 emit_insn (gen_adddi3 (this, this, tmp
));
7910 /* Generate a tail call to the target function. */
7911 if (! TREE_USED (function
))
7913 assemble_external (function
);
7914 TREE_USED (function
) = 1;
7916 funexp
= XEXP (DECL_RTL (function
), 0);
7917 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7918 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7919 SIBLING_CALL_P (insn
) = 1;
7921 /* Run just enough of rest_of_compilation to get the insns emitted.
7922 There's not really enough bulk here to make other passes such as
7923 instruction scheduling worth while. Note that use_thunk calls
7924 assemble_start_function and assemble_end_function. */
7925 insn
= get_insns ();
7926 insn_locators_initialize ();
7927 shorten_branches (insn
);
7928 final_start_function (insn
, file
, 1);
7929 final (insn
, file
, 1, 0);
7930 final_end_function ();
7932 #endif /* TARGET_ABI_OSF */
7934 /* Debugging support. */
7938 /* Count the number of sdb related labels are generated (to find block
7939 start and end boundaries). */
7941 int sdb_label_count
= 0;
7943 /* Next label # for each statement. */
7945 static int sym_lineno
= 0;
7947 /* Count the number of .file directives, so that .loc is up to date. */
7949 static int num_source_filenames
= 0;
7951 /* Name of the file containing the current function. */
7953 static const char *current_function_file
= "";
7955 /* Offsets to alpha virtual arg/local debugging pointers. */
7957 long alpha_arg_offset
;
7958 long alpha_auto_offset
;
7960 /* Emit a new filename to a stream. */
7963 alpha_output_filename (FILE *stream
, const char *name
)
7965 static int first_time
= TRUE
;
7966 char ltext_label_name
[100];
7971 ++num_source_filenames
;
7972 current_function_file
= name
;
7973 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7974 output_quoted_string (stream
, name
);
7975 fprintf (stream
, "\n");
7976 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7977 fprintf (stream
, "\t#@stabs\n");
7980 else if (write_symbols
== DBX_DEBUG
)
7982 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7983 fprintf (stream
, "%s", ASM_STABS_OP
);
7984 output_quoted_string (stream
, name
);
7985 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7988 else if (name
!= current_function_file
7989 && strcmp (name
, current_function_file
) != 0)
7991 if (inside_function
&& ! TARGET_GAS
)
7992 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7995 ++num_source_filenames
;
7996 current_function_file
= name
;
7997 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8000 output_quoted_string (stream
, name
);
8001 fprintf (stream
, "\n");
8005 /* Emit a linenumber to a stream. */
8008 alpha_output_lineno (FILE *stream
, int line
)
8010 if (write_symbols
== DBX_DEBUG
)
8012 /* mips-tfile doesn't understand .stabd directives. */
8014 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8015 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8018 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8021 /* Structure to show the current status of registers and memory. */
8023 struct shadow_summary
8026 unsigned int i
: 31; /* Mask of int regs */
8027 unsigned int fp
: 31; /* Mask of fp regs */
8028 unsigned int mem
: 1; /* mem == imem | fpmem */
8032 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8033 to the summary structure. SET is nonzero if the insn is setting the
8034 object, otherwise zero. */
8037 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8039 const char *format_ptr
;
8045 switch (GET_CODE (x
))
8047 /* ??? Note that this case would be incorrect if the Alpha had a
8048 ZERO_EXTRACT in SET_DEST. */
8050 summarize_insn (SET_SRC (x
), sum
, 0);
8051 summarize_insn (SET_DEST (x
), sum
, 1);
8055 summarize_insn (XEXP (x
, 0), sum
, 1);
8059 summarize_insn (XEXP (x
, 0), sum
, 0);
8063 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8064 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8068 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8069 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8073 summarize_insn (SUBREG_REG (x
), sum
, 0);
8078 int regno
= REGNO (x
);
8079 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8081 if (regno
== 31 || regno
== 63)
8087 sum
->defd
.i
|= mask
;
8089 sum
->defd
.fp
|= mask
;
8094 sum
->used
.i
|= mask
;
8096 sum
->used
.fp
|= mask
;
8107 /* Find the regs used in memory address computation: */
8108 summarize_insn (XEXP (x
, 0), sum
, 0);
8111 case CONST_INT
: case CONST_DOUBLE
:
8112 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8113 case SCRATCH
: case ASM_INPUT
:
8116 /* Handle common unary and binary ops for efficiency. */
8117 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8118 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8119 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8120 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8121 case NE
: case EQ
: case GE
: case GT
: case LE
:
8122 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8123 summarize_insn (XEXP (x
, 0), sum
, 0);
8124 summarize_insn (XEXP (x
, 1), sum
, 0);
8127 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8128 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8129 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8130 case SQRT
: case FFS
:
8131 summarize_insn (XEXP (x
, 0), sum
, 0);
8135 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8136 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8137 switch (format_ptr
[i
])
8140 summarize_insn (XEXP (x
, i
), sum
, 0);
8144 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8145 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8157 /* Ensure a sufficient number of `trapb' insns are in the code when
8158 the user requests code with a trap precision of functions or
8161 In naive mode, when the user requests a trap-precision of
8162 "instruction", a trapb is needed after every instruction that may
8163 generate a trap. This ensures that the code is resumption safe but
8166 When optimizations are turned on, we delay issuing a trapb as long
8167 as possible. In this context, a trap shadow is the sequence of
8168 instructions that starts with a (potentially) trap generating
8169 instruction and extends to the next trapb or call_pal instruction
8170 (but GCC never generates call_pal by itself). We can delay (and
8171 therefore sometimes omit) a trapb subject to the following
8174 (a) On entry to the trap shadow, if any Alpha register or memory
8175 location contains a value that is used as an operand value by some
8176 instruction in the trap shadow (live on entry), then no instruction
8177 in the trap shadow may modify the register or memory location.
8179 (b) Within the trap shadow, the computation of the base register
8180 for a memory load or store instruction may not involve using the
8181 result of an instruction that might generate an UNPREDICTABLE
8184 (c) Within the trap shadow, no register may be used more than once
8185 as a destination register. (This is to make life easier for the
8188 (d) The trap shadow may not include any branch instructions. */
8191 alpha_handle_trap_shadows (void)
8193 struct shadow_summary shadow
;
8194 int trap_pending
, exception_nesting
;
8198 exception_nesting
= 0;
8201 shadow
.used
.mem
= 0;
8202 shadow
.defd
= shadow
.used
;
8204 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8206 if (GET_CODE (i
) == NOTE
)
8208 switch (NOTE_LINE_NUMBER (i
))
8210 case NOTE_INSN_EH_REGION_BEG
:
8211 exception_nesting
++;
8216 case NOTE_INSN_EH_REGION_END
:
8217 exception_nesting
--;
8222 case NOTE_INSN_EPILOGUE_BEG
:
8223 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8228 else if (trap_pending
)
8230 if (alpha_tp
== ALPHA_TP_FUNC
)
8232 if (GET_CODE (i
) == JUMP_INSN
8233 && GET_CODE (PATTERN (i
)) == RETURN
)
8236 else if (alpha_tp
== ALPHA_TP_INSN
)
8240 struct shadow_summary sum
;
8245 sum
.defd
= sum
.used
;
8247 switch (GET_CODE (i
))
8250 /* Annoyingly, get_attr_trap will abort on these. */
8251 if (GET_CODE (PATTERN (i
)) == USE
8252 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8255 summarize_insn (PATTERN (i
), &sum
, 0);
8257 if ((sum
.defd
.i
& shadow
.defd
.i
)
8258 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8260 /* (c) would be violated */
8264 /* Combine shadow with summary of current insn: */
8265 shadow
.used
.i
|= sum
.used
.i
;
8266 shadow
.used
.fp
|= sum
.used
.fp
;
8267 shadow
.used
.mem
|= sum
.used
.mem
;
8268 shadow
.defd
.i
|= sum
.defd
.i
;
8269 shadow
.defd
.fp
|= sum
.defd
.fp
;
8270 shadow
.defd
.mem
|= sum
.defd
.mem
;
8272 if ((sum
.defd
.i
& shadow
.used
.i
)
8273 || (sum
.defd
.fp
& shadow
.used
.fp
)
8274 || (sum
.defd
.mem
& shadow
.used
.mem
))
8276 /* (a) would be violated (also takes care of (b)) */
8277 if (get_attr_trap (i
) == TRAP_YES
8278 && ((sum
.defd
.i
& sum
.used
.i
)
8279 || (sum
.defd
.fp
& sum
.used
.fp
)))
8298 n
= emit_insn_before (gen_trapb (), i
);
8299 PUT_MODE (n
, TImode
);
8300 PUT_MODE (i
, TImode
);
8304 shadow
.used
.mem
= 0;
8305 shadow
.defd
= shadow
.used
;
8310 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8311 && GET_CODE (i
) == INSN
8312 && GET_CODE (PATTERN (i
)) != USE
8313 && GET_CODE (PATTERN (i
)) != CLOBBER
8314 && get_attr_trap (i
) == TRAP_YES
)
8316 if (optimize
&& !trap_pending
)
8317 summarize_insn (PATTERN (i
), &shadow
, 0);
8323 /* Alpha can only issue instruction groups simultaneously if they are
8324 suitably aligned. This is very processor-specific. */
8326 enum alphaev4_pipe
{
8333 enum alphaev5_pipe
{
8344 static enum alphaev4_pipe
8345 alphaev4_insn_pipe (rtx insn
)
8347 if (recog_memoized (insn
) < 0)
8349 if (get_attr_length (insn
) != 4)
8352 switch (get_attr_type (insn
))
8386 static enum alphaev5_pipe
8387 alphaev5_insn_pipe (rtx insn
)
8389 if (recog_memoized (insn
) < 0)
8391 if (get_attr_length (insn
) != 4)
8394 switch (get_attr_type (insn
))
8435 /* IN_USE is a mask of the slots currently filled within the insn group.
8436 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8437 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8439 LEN is, of course, the length of the group in bytes. */
8442 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8449 || GET_CODE (PATTERN (insn
)) == CLOBBER
8450 || GET_CODE (PATTERN (insn
)) == USE
)
8455 enum alphaev4_pipe pipe
;
8457 pipe
= alphaev4_insn_pipe (insn
);
8461 /* Force complex instructions to start new groups. */
8465 /* If this is a completely unrecognized insn, its an asm.
8466 We don't know how long it is, so record length as -1 to
8467 signal a needed realignment. */
8468 if (recog_memoized (insn
) < 0)
8471 len
= get_attr_length (insn
);
8475 if (in_use
& EV4_IB0
)
8477 if (in_use
& EV4_IB1
)
8482 in_use
|= EV4_IB0
| EV4_IBX
;
8486 if (in_use
& EV4_IB0
)
8488 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8496 if (in_use
& EV4_IB1
)
8506 /* Haifa doesn't do well scheduling branches. */
8507 if (GET_CODE (insn
) == JUMP_INSN
)
8511 insn
= next_nonnote_insn (insn
);
8513 if (!insn
|| ! INSN_P (insn
))
8516 /* Let Haifa tell us where it thinks insn group boundaries are. */
8517 if (GET_MODE (insn
) == TImode
)
8520 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8525 insn
= next_nonnote_insn (insn
);
8533 /* IN_USE is a mask of the slots currently filled within the insn group.
8534 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8535 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8537 LEN is, of course, the length of the group in bytes. */
8540 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8547 || GET_CODE (PATTERN (insn
)) == CLOBBER
8548 || GET_CODE (PATTERN (insn
)) == USE
)
8553 enum alphaev5_pipe pipe
;
8555 pipe
= alphaev5_insn_pipe (insn
);
8559 /* Force complex instructions to start new groups. */
8563 /* If this is a completely unrecognized insn, its an asm.
8564 We don't know how long it is, so record length as -1 to
8565 signal a needed realignment. */
8566 if (recog_memoized (insn
) < 0)
8569 len
= get_attr_length (insn
);
8572 /* ??? Most of the places below, we would like to abort, as
8573 it would indicate an error either in Haifa, or in the
8574 scheduling description. Unfortunately, Haifa never
8575 schedules the last instruction of the BB, so we don't
8576 have an accurate TI bit to go off. */
8578 if (in_use
& EV5_E0
)
8580 if (in_use
& EV5_E1
)
8585 in_use
|= EV5_E0
| EV5_E01
;
8589 if (in_use
& EV5_E0
)
8591 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8599 if (in_use
& EV5_E1
)
8605 if (in_use
& EV5_FA
)
8607 if (in_use
& EV5_FM
)
8612 in_use
|= EV5_FA
| EV5_FAM
;
8616 if (in_use
& EV5_FA
)
8622 if (in_use
& EV5_FM
)
8635 /* Haifa doesn't do well scheduling branches. */
8636 /* ??? If this is predicted not-taken, slotting continues, except
8637 that no more IBR, FBR, or JSR insns may be slotted. */
8638 if (GET_CODE (insn
) == JUMP_INSN
)
8642 insn
= next_nonnote_insn (insn
);
8644 if (!insn
|| ! INSN_P (insn
))
8647 /* Let Haifa tell us where it thinks insn group boundaries are. */
8648 if (GET_MODE (insn
) == TImode
)
8651 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8656 insn
= next_nonnote_insn (insn
);
8665 alphaev4_next_nop (int *pin_use
)
8667 int in_use
= *pin_use
;
8670 if (!(in_use
& EV4_IB0
))
8675 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8680 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8693 alphaev5_next_nop (int *pin_use
)
8695 int in_use
= *pin_use
;
8698 if (!(in_use
& EV5_E1
))
8703 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8708 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8720 /* The instruction group alignment main loop. */
8723 alpha_align_insns (unsigned int max_align
,
8724 rtx (*next_group
) (rtx
, int *, int *),
8725 rtx (*next_nop
) (int *))
8727 /* ALIGN is the known alignment for the insn group. */
8729 /* OFS is the offset of the current insn in the insn group. */
8731 int prev_in_use
, in_use
, len
;
8734 /* Let shorten branches care for assigning alignments to code labels. */
8735 shorten_branches (get_insns ());
8737 if (align_functions
< 4)
8739 else if ((unsigned int) align_functions
< max_align
)
8740 align
= align_functions
;
8744 ofs
= prev_in_use
= 0;
8746 if (GET_CODE (i
) == NOTE
)
8747 i
= next_nonnote_insn (i
);
8751 next
= (*next_group
) (i
, &in_use
, &len
);
8753 /* When we see a label, resync alignment etc. */
8754 if (GET_CODE (i
) == CODE_LABEL
)
8756 unsigned int new_align
= 1 << label_to_alignment (i
);
8758 if (new_align
>= align
)
8760 align
= new_align
< max_align
? new_align
: max_align
;
8764 else if (ofs
& (new_align
-1))
8765 ofs
= (ofs
| (new_align
-1)) + 1;
8770 /* Handle complex instructions special. */
8771 else if (in_use
== 0)
8773 /* Asms will have length < 0. This is a signal that we have
8774 lost alignment knowledge. Assume, however, that the asm
8775 will not mis-align instructions. */
8784 /* If the known alignment is smaller than the recognized insn group,
8785 realign the output. */
8786 else if ((int) align
< len
)
8788 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8791 where
= prev
= prev_nonnote_insn (i
);
8792 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8795 /* Can't realign between a call and its gp reload. */
8796 if (! (TARGET_EXPLICIT_RELOCS
8797 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8799 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8800 align
= 1 << new_log_align
;
8805 /* If the group won't fit in the same INT16 as the previous,
8806 we need to add padding to keep the group together. Rather
8807 than simply leaving the insn filling to the assembler, we
8808 can make use of the knowledge of what sorts of instructions
8809 were issued in the previous group to make sure that all of
8810 the added nops are really free. */
8811 else if (ofs
+ len
> (int) align
)
8813 int nop_count
= (align
- ofs
) / 4;
8816 /* Insert nops before labels, branches, and calls to truely merge
8817 the execution of the nops with the previous instruction group. */
8818 where
= prev_nonnote_insn (i
);
8821 if (GET_CODE (where
) == CODE_LABEL
)
8823 rtx where2
= prev_nonnote_insn (where
);
8824 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8827 else if (GET_CODE (where
) == INSN
)
8834 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8835 while (--nop_count
);
8839 ofs
= (ofs
+ len
) & (align
- 1);
8840 prev_in_use
= in_use
;
8845 /* Machine dependent reorg pass. */
8850 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8851 alpha_handle_trap_shadows ();
8853 /* Due to the number of extra trapb insns, don't bother fixing up
8854 alignment when trap precision is instruction. Moreover, we can
8855 only do our job when sched2 is run. */
8856 if (optimize
&& !optimize_size
8857 && alpha_tp
!= ALPHA_TP_INSN
8858 && flag_schedule_insns_after_reload
)
8860 if (alpha_cpu
== PROCESSOR_EV4
)
8861 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
8862 else if (alpha_cpu
== PROCESSOR_EV5
)
8863 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
8867 #if !TARGET_ABI_UNICOSMK
8874 alpha_file_start (void)
8876 #ifdef OBJECT_FORMAT_ELF
8877 /* If emitting dwarf2 debug information, we cannot generate a .file
8878 directive to start the file, as it will conflict with dwarf2out
8879 file numbers. So it's only useful when emitting mdebug output. */
8880 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
8883 default_file_start ();
8885 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
8888 fputs ("\t.set noreorder\n", asm_out_file
);
8889 fputs ("\t.set volatile\n", asm_out_file
);
8890 if (!TARGET_ABI_OPEN_VMS
)
8891 fputs ("\t.set noat\n", asm_out_file
);
8892 if (TARGET_EXPLICIT_RELOCS
)
8893 fputs ("\t.set nomacro\n", asm_out_file
);
8894 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
8895 fprintf (asm_out_file
,
8897 TARGET_CPU_EV6
? "ev6"
8899 ? (TARGET_MAX
? "pca56" : TARGET_BWX
? "ev56" : "ev5")
8904 #ifdef OBJECT_FORMAT_ELF
8906 /* Switch to the section to which we should output X. The only thing
8907 special we do here is to honor small data. */
8910 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
8911 unsigned HOST_WIDE_INT align
)
8913 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8914 /* ??? Consider using mergeable sdata sections. */
8917 default_elf_select_rtx_section (mode
, x
, align
);
8920 #endif /* OBJECT_FORMAT_ELF */
8922 /* Structure to collect function names for final output in link section. */
8923 /* Note that items marked with GTY can't be ifdef'ed out. */
8925 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8926 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
8928 struct alpha_links
GTY(())
8932 enum links_kind lkind
;
8933 enum reloc_kind rkind
;
8936 struct alpha_funcs
GTY(())
8939 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8943 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
8944 splay_tree alpha_links_tree
;
8945 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
8946 splay_tree alpha_funcs_tree
;
8948 static GTY(()) int alpha_funcs_num
;
8950 #if TARGET_ABI_OPEN_VMS
8952 /* Return the VMS argument type corresponding to MODE. */
8955 alpha_arg_type (enum machine_mode mode
)
8960 return TARGET_FLOAT_VAX
? FF
: FS
;
8962 return TARGET_FLOAT_VAX
? FD
: FT
;
8968 /* Return an rtx for an integer representing the VMS Argument Information
8972 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
8974 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8977 for (i
= 0; i
< 6; i
++)
8978 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8980 return GEN_INT (regval
);
8983 /* Make (or fake) .linkage entry for function call.
8985 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8987 Return an SYMBOL_REF rtx for the linkage. */
8990 alpha_need_linkage (const char *name
, int is_local
)
8992 splay_tree_node node
;
8993 struct alpha_links
*al
;
9000 struct alpha_funcs
*cfaf
;
9002 if (!alpha_funcs_tree
)
9003 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9004 splay_tree_compare_pointers
);
9006 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9009 cfaf
->num
= ++alpha_funcs_num
;
9011 splay_tree_insert (alpha_funcs_tree
,
9012 (splay_tree_key
) current_function_decl
,
9013 (splay_tree_value
) cfaf
);
9016 if (alpha_links_tree
)
9018 /* Is this name already defined? */
9020 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9023 al
= (struct alpha_links
*) node
->value
;
9026 /* Defined here but external assumed. */
9027 if (al
->lkind
== KIND_EXTERN
)
9028 al
->lkind
= KIND_LOCAL
;
9032 /* Used here but unused assumed. */
9033 if (al
->lkind
== KIND_UNUSED
)
9034 al
->lkind
= KIND_LOCAL
;
9040 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9042 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9043 name
= ggc_strdup (name
);
9045 /* Assume external if no definition. */
9046 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9048 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9049 get_identifier (name
);
9051 /* Construct a SYMBOL_REF for us to call. */
9053 size_t name_len
= strlen (name
);
9054 char *linksym
= alloca (name_len
+ 6);
9056 memcpy (linksym
+ 1, name
, name_len
);
9057 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9058 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9059 ggc_alloc_string (linksym
, name_len
+ 5));
9062 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9063 (splay_tree_value
) al
);
9069 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9071 splay_tree_node cfunnode
;
9072 struct alpha_funcs
*cfaf
;
9073 struct alpha_links
*al
;
9074 const char *name
= XSTR (linkage
, 0);
9076 cfaf
= (struct alpha_funcs
*) 0;
9077 al
= (struct alpha_links
*) 0;
9079 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9080 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9084 splay_tree_node lnode
;
9086 /* Is this name already defined? */
9088 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9090 al
= (struct alpha_links
*) lnode
->value
;
9093 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9101 splay_tree_node node
= 0;
9102 struct alpha_links
*anl
;
9107 name_len
= strlen (name
);
9109 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9110 al
->num
= cfaf
->num
;
9112 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9115 anl
= (struct alpha_links
*) node
->value
;
9116 al
->lkind
= anl
->lkind
;
9119 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9120 buflen
= strlen (buf
);
9121 linksym
= alloca (buflen
+ 1);
9122 memcpy (linksym
, buf
, buflen
+ 1);
9124 al
->linkage
= gen_rtx_SYMBOL_REF
9125 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9127 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9128 (splay_tree_value
) al
);
9132 al
->rkind
= KIND_CODEADDR
;
9134 al
->rkind
= KIND_LINKAGE
;
9137 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9143 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9145 const char *const name
= (const char *) node
->key
;
9146 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9147 FILE *stream
= (FILE *) data
;
9149 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9150 if (link
->rkind
== KIND_CODEADDR
)
9152 if (link
->lkind
== KIND_LOCAL
)
9154 /* Local and used */
9155 fprintf (stream
, "\t.quad %s..en\n", name
);
9159 /* External and used, request code address. */
9160 fprintf (stream
, "\t.code_address %s\n", name
);
9165 if (link
->lkind
== KIND_LOCAL
)
9167 /* Local and used, build linkage pair. */
9168 fprintf (stream
, "\t.quad %s..en\n", name
);
9169 fprintf (stream
, "\t.quad %s\n", name
);
9173 /* External and used, request linkage pair. */
9174 fprintf (stream
, "\t.linkage %s\n", name
);
9182 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9184 splay_tree_node node
;
9185 struct alpha_funcs
*func
;
9188 fprintf (stream
, "\t.align 3\n");
9189 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9190 func
= (struct alpha_funcs
*) node
->value
;
9192 fputs ("\t.name ", stream
);
9193 assemble_name (stream
, funname
);
9194 fputs ("..na\n", stream
);
9195 ASM_OUTPUT_LABEL (stream
, funname
);
9196 fprintf (stream
, "\t.pdesc ");
9197 assemble_name (stream
, funname
);
9198 fprintf (stream
, "..en,%s\n",
9199 alpha_procedure_type
== PT_STACK
? "stack"
9200 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9204 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9205 /* splay_tree_delete (func->links); */
9209 /* Given a decl, a section name, and whether the decl initializer
9210 has relocs, choose attributes for the section. */
9212 #define SECTION_VMS_OVERLAY SECTION_FORGET
9213 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9214 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9217 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9219 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9221 if (decl
&& DECL_ATTRIBUTES (decl
)
9222 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9223 flags
|= SECTION_VMS_OVERLAY
;
9224 if (decl
&& DECL_ATTRIBUTES (decl
)
9225 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9226 flags
|= SECTION_VMS_GLOBAL
;
9227 if (decl
&& DECL_ATTRIBUTES (decl
)
9228 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9229 flags
|= SECTION_VMS_INITIALIZE
;
9234 /* Switch to an arbitrary section NAME with attributes as specified
9235 by FLAGS. ALIGN specifies any known alignment requirements for
9236 the section; 0 if the default should be used. */
9239 vms_asm_named_section (const char *name
, unsigned int flags
)
9241 fputc ('\n', asm_out_file
);
9242 fprintf (asm_out_file
, ".section\t%s", name
);
9244 if (flags
& SECTION_VMS_OVERLAY
)
9245 fprintf (asm_out_file
, ",OVR");
9246 if (flags
& SECTION_VMS_GLOBAL
)
9247 fprintf (asm_out_file
, ",GBL");
9248 if (flags
& SECTION_VMS_INITIALIZE
)
9249 fprintf (asm_out_file
, ",NOMOD");
9250 if (flags
& SECTION_DEBUG
)
9251 fprintf (asm_out_file
, ",NOWRT");
9253 fputc ('\n', asm_out_file
);
9256 /* Record an element in the table of global constructors. SYMBOL is
9257 a SYMBOL_REF of the function to be called; PRIORITY is a number
9258 between 0 and MAX_INIT_PRIORITY.
9260 Differs from default_ctors_section_asm_out_constructor in that the
9261 width of the .ctors entry is always 64 bits, rather than the 32 bits
9262 used by a normal pointer. */
9265 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9268 assemble_align (BITS_PER_WORD
);
9269 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9273 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9276 assemble_align (BITS_PER_WORD
);
9277 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9282 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9283 int is_local ATTRIBUTE_UNUSED
)
9289 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9290 tree cfundecl ATTRIBUTE_UNUSED
,
9291 int lflag ATTRIBUTE_UNUSED
,
9292 int rflag ATTRIBUTE_UNUSED
)
9297 #endif /* TARGET_ABI_OPEN_VMS */
9299 #if TARGET_ABI_UNICOSMK
9301 /* Define the offset between two registers, one to be eliminated, and the
9302 other its replacement, at the start of a routine. */
9305 unicosmk_initial_elimination_offset (int from
, int to
)
9309 fixed_size
= alpha_sa_size();
9310 if (fixed_size
!= 0)
9313 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9315 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9317 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9318 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9319 + ALPHA_ROUND (get_frame_size()));
9320 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9321 return (ALPHA_ROUND (fixed_size
)
9322 + ALPHA_ROUND (get_frame_size()
9323 + current_function_outgoing_args_size
));
9328 /* Output the module name for .ident and .end directives. We have to strip
9329 directories and add make sure that the module name starts with a letter
9333 unicosmk_output_module_name (FILE *file
)
9335 const char *name
= lbasename (main_input_filename
);
9336 unsigned len
= strlen (name
);
9337 char *clean_name
= alloca (len
+ 2);
9338 char *ptr
= clean_name
;
9340 /* CAM only accepts module names that start with a letter or '$'. We
9341 prefix the module name with a '$' if necessary. */
9343 if (!ISALPHA (*name
))
9345 memcpy (ptr
, name
, len
+ 1);
9346 clean_symbol_name (clean_name
);
9347 fputs (clean_name
, file
);
9350 /* Output the definition of a common variable. */
9353 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9356 printf ("T3E__: common %s\n", name
);
9359 fputs("\t.endp\n\n\t.psect ", file
);
9360 assemble_name(file
, name
);
9361 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9362 fprintf(file
, "\t.byte\t0:%d\n", size
);
9364 /* Mark the symbol as defined in this module. */
9365 name_tree
= get_identifier (name
);
9366 TREE_ASM_WRITTEN (name_tree
) = 1;
9369 #define SECTION_PUBLIC SECTION_MACH_DEP
9370 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9371 static int current_section_align
;
9374 unicosmk_section_type_flags (tree decl
, const char *name
,
9375 int reloc ATTRIBUTE_UNUSED
)
9377 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9382 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9384 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9385 if (align_functions_log
> current_section_align
)
9386 current_section_align
= align_functions_log
;
9388 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9389 flags
|= SECTION_MAIN
;
9392 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9394 if (TREE_PUBLIC (decl
))
9395 flags
|= SECTION_PUBLIC
;
9400 /* Generate a section name for decl and associate it with the
9404 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9412 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9413 name
= default_strip_name_encoding (name
);
9414 len
= strlen (name
);
9416 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9420 /* It is essential that we prefix the section name here because
9421 otherwise the section names generated for constructors and
9422 destructors confuse collect2. */
9424 string
= alloca (len
+ 6);
9425 sprintf (string
, "code@%s", name
);
9426 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9428 else if (TREE_PUBLIC (decl
))
9429 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9434 string
= alloca (len
+ 6);
9435 sprintf (string
, "data@%s", name
);
9436 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9440 /* Switch to an arbitrary section NAME with attributes as specified
9441 by FLAGS. ALIGN specifies any known alignment requirements for
9442 the section; 0 if the default should be used. */
9445 unicosmk_asm_named_section (const char *name
, unsigned int flags
)
9449 /* Close the previous section. */
9451 fputs ("\t.endp\n\n", asm_out_file
);
9453 /* Find out what kind of section we are opening. */
9455 if (flags
& SECTION_MAIN
)
9456 fputs ("\t.start\tmain\n", asm_out_file
);
9458 if (flags
& SECTION_CODE
)
9460 else if (flags
& SECTION_PUBLIC
)
9465 if (current_section_align
!= 0)
9466 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9467 current_section_align
, kind
);
9469 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9473 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9476 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9477 unicosmk_unique_section (decl
, 0);
9480 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9481 in code sections because .align fill unused space with zeroes. */
9484 unicosmk_output_align (FILE *file
, int align
)
9486 if (inside_function
)
9487 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9489 fprintf (file
, "\t.align\t%d\n", align
);
9492 /* Add a case vector to the current function's list of deferred case
9493 vectors. Case vectors have to be put into a separate section because CAM
9494 does not allow data definitions in code sections. */
9497 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9499 struct machine_function
*machine
= cfun
->machine
;
9501 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9502 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9503 machine
->addr_list
);
9506 /* Output a case vector. */
9509 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9511 rtx lab
= XEXP (vec
, 0);
9512 rtx body
= XEXP (vec
, 1);
9513 int vlen
= XVECLEN (body
, 0);
9516 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9518 for (idx
= 0; idx
< vlen
; idx
++)
9520 ASM_OUTPUT_ADDR_VEC_ELT
9521 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9525 /* Output current function's deferred case vectors. */
9528 unicosmk_output_deferred_case_vectors (FILE *file
)
9530 struct machine_function
*machine
= cfun
->machine
;
9533 if (machine
->addr_list
== NULL_RTX
)
9537 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9538 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9541 /* Generate the name of the SSIB section for the current function. */
9543 #define SSIB_PREFIX "__SSIB_"
9544 #define SSIB_PREFIX_LEN 7
9547 unicosmk_ssib_name (void)
9549 /* This is ok since CAM won't be able to deal with names longer than that
9552 static char name
[256];
9558 x
= DECL_RTL (cfun
->decl
);
9559 if (GET_CODE (x
) != MEM
)
9562 if (GET_CODE (x
) != SYMBOL_REF
)
9564 fnname
= XSTR (x
, 0);
9566 len
= strlen (fnname
);
9567 if (len
+ SSIB_PREFIX_LEN
> 255)
9568 len
= 255 - SSIB_PREFIX_LEN
;
9570 strcpy (name
, SSIB_PREFIX
);
9571 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9572 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9577 /* Set up the dynamic subprogram information block (DSIB) and update the
9578 frame pointer register ($15) for subroutines which have a frame. If the
9579 subroutine doesn't have a frame, simply increment $15. */
9582 unicosmk_gen_dsib (unsigned long *imaskP
)
9584 if (alpha_procedure_type
== PT_STACK
)
9586 const char *ssib_name
;
9589 /* Allocate 64 bytes for the DSIB. */
9591 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9593 emit_insn (gen_blockage ());
9595 /* Save the return address. */
9597 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9598 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9599 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9600 (*imaskP
) &= ~(1UL << REG_RA
);
9602 /* Save the old frame pointer. */
9604 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9605 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9606 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9607 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9609 emit_insn (gen_blockage ());
9611 /* Store the SSIB pointer. */
9613 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9614 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9615 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9617 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9618 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9619 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9621 /* Save the CIW index. */
9623 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9624 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9625 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9627 emit_insn (gen_blockage ());
9629 /* Set the new frame pointer. */
9631 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9632 stack_pointer_rtx
, GEN_INT (64))));
9637 /* Increment the frame pointer register to indicate that we do not
9640 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9641 hard_frame_pointer_rtx
, GEN_INT (1))));
9645 /* Output the static subroutine information block for the current
9649 unicosmk_output_ssib (FILE *file
, const char *fnname
)
9655 struct machine_function
*machine
= cfun
->machine
;
9658 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9659 unicosmk_ssib_name ());
9661 /* Some required stuff and the function name length. */
9663 len
= strlen (fnname
);
9664 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9667 ??? We don't do that yet. */
9669 fputs ("\t.quad\t0\n", file
);
9671 /* Function address. */
9673 fputs ("\t.quad\t", file
);
9674 assemble_name (file
, fnname
);
9677 fputs ("\t.quad\t0\n", file
);
9678 fputs ("\t.quad\t0\n", file
);
9681 ??? We do it the same way Cray CC does it but this could be
9684 for( i
= 0; i
< len
; i
++ )
9685 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9686 if( (len
% 8) == 0 )
9687 fputs ("\t.quad\t0\n", file
);
9689 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9691 /* All call information words used in the function. */
9693 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9696 #if HOST_BITS_PER_WIDE_INT == 32
9697 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
9698 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9700 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
9705 /* Add a call information word (CIW) to the list of the current function's
9706 CIWs and return its index.
9708 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9711 unicosmk_add_call_info_word (rtx x
)
9714 struct machine_function
*machine
= cfun
->machine
;
9716 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9717 if (machine
->first_ciw
== NULL_RTX
)
9718 machine
->first_ciw
= node
;
9720 XEXP (machine
->last_ciw
, 1) = node
;
9722 machine
->last_ciw
= node
;
9723 ++machine
->ciw_count
;
9725 return GEN_INT (machine
->ciw_count
9726 + strlen (current_function_name
)/8 + 5);
9729 static char unicosmk_section_buf
[100];
9732 unicosmk_text_section (void)
9734 static int count
= 0;
9735 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9737 return unicosmk_section_buf
;
9741 unicosmk_data_section (void)
9743 static int count
= 1;
9744 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9746 return unicosmk_section_buf
;
9749 /* The Cray assembler doesn't accept extern declarations for symbols which
9750 are defined in the same file. We have to keep track of all global
9751 symbols which are referenced and/or defined in a source file and output
9752 extern declarations for those which are referenced but not defined at
9755 /* List of identifiers for which an extern declaration might have to be
9757 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9759 struct unicosmk_extern_list
9761 struct unicosmk_extern_list
*next
;
9765 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9767 /* Output extern declarations which are required for every asm file. */
9770 unicosmk_output_default_externs (FILE *file
)
9772 static const char *const externs
[] =
9773 { "__T3E_MISMATCH" };
9778 n
= ARRAY_SIZE (externs
);
9780 for (i
= 0; i
< n
; i
++)
9781 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9784 /* Output extern declarations for global symbols which are have been
9785 referenced but not defined. */
9788 unicosmk_output_externs (FILE *file
)
9790 struct unicosmk_extern_list
*p
;
9791 const char *real_name
;
9795 len
= strlen (user_label_prefix
);
9796 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9798 /* We have to strip the encoding and possibly remove user_label_prefix
9799 from the identifier in order to handle -fleading-underscore and
9800 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9801 real_name
= default_strip_name_encoding (p
->name
);
9802 if (len
&& p
->name
[0] == '*'
9803 && !memcmp (real_name
, user_label_prefix
, len
))
9806 name_tree
= get_identifier (real_name
);
9807 if (! TREE_ASM_WRITTEN (name_tree
))
9809 TREE_ASM_WRITTEN (name_tree
) = 1;
9810 fputs ("\t.extern\t", file
);
9811 assemble_name (file
, p
->name
);
9817 /* Record an extern. */
9820 unicosmk_add_extern (const char *name
)
9822 struct unicosmk_extern_list
*p
;
9824 p
= (struct unicosmk_extern_list
*)
9825 xmalloc (sizeof (struct unicosmk_extern_list
));
9826 p
->next
= unicosmk_extern_head
;
9828 unicosmk_extern_head
= p
;
9831 /* The Cray assembler generates incorrect code if identifiers which
9832 conflict with register names are used as instruction operands. We have
9833 to replace such identifiers with DEX expressions. */
9835 /* Structure to collect identifiers which have been replaced by DEX
9837 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9839 struct unicosmk_dex
{
9840 struct unicosmk_dex
*next
;
9844 /* List of identifiers which have been replaced by DEX expressions. The DEX
9845 number is determined by the position in the list. */
9847 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9849 /* The number of elements in the DEX list. */
9851 static int unicosmk_dex_count
= 0;
9853 /* Check if NAME must be replaced by a DEX expression. */
9856 unicosmk_special_name (const char *name
)
9864 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9870 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9873 return (name
[2] == '\0'
9874 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9877 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9881 /* Return the DEX number if X must be replaced by a DEX expression and 0
9885 unicosmk_need_dex (rtx x
)
9887 struct unicosmk_dex
*dex
;
9891 if (GET_CODE (x
) != SYMBOL_REF
)
9895 if (! unicosmk_special_name (name
))
9898 i
= unicosmk_dex_count
;
9899 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9901 if (! strcmp (name
, dex
->name
))
9906 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
9908 dex
->next
= unicosmk_dex_list
;
9909 unicosmk_dex_list
= dex
;
9911 ++unicosmk_dex_count
;
9912 return unicosmk_dex_count
;
9915 /* Output the DEX definitions for this file. */
9918 unicosmk_output_dex (FILE *file
)
9920 struct unicosmk_dex
*dex
;
9923 if (unicosmk_dex_list
== NULL
)
9926 fprintf (file
, "\t.dexstart\n");
9928 i
= unicosmk_dex_count
;
9929 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9931 fprintf (file
, "\tDEX (%d) = ", i
);
9932 assemble_name (file
, dex
->name
);
9937 fprintf (file
, "\t.dexend\n");
9940 /* Output text that to appear at the beginning of an assembler file. */
9943 unicosmk_file_start (void)
9947 fputs ("\t.ident\t", asm_out_file
);
9948 unicosmk_output_module_name (asm_out_file
);
9949 fputs ("\n\n", asm_out_file
);
9951 /* The Unicos/Mk assembler uses different register names. Instead of trying
9952 to support them, we simply use micro definitions. */
9954 /* CAM has different register names: rN for the integer register N and fN
9955 for the floating-point register N. Instead of trying to use these in
9956 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9959 for (i
= 0; i
< 32; ++i
)
9960 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
9962 for (i
= 0; i
< 32; ++i
)
9963 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
9965 putc ('\n', asm_out_file
);
9967 /* The .align directive fill unused space with zeroes which does not work
9968 in code sections. We define the macro 'gcc@code@align' which uses nops
9969 instead. Note that it assumes that code sections always have the
9970 biggest possible alignment since . refers to the current offset from
9971 the beginning of the section. */
9973 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
9974 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
9975 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
9976 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
9977 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
9978 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
9979 fputs ("\t.endr\n", asm_out_file
);
9980 fputs ("\t.endif\n", asm_out_file
);
9981 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
9983 /* Output extern declarations which should always be visible. */
9984 unicosmk_output_default_externs (asm_out_file
);
9986 /* Open a dummy section. We always need to be inside a section for the
9987 section-switching code to work correctly.
9988 ??? This should be a module id or something like that. I still have to
9989 figure out what the rules for those are. */
9990 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
9993 /* Output text to appear at the end of an assembler file. This includes all
9994 pending extern declarations and DEX expressions. */
9997 unicosmk_file_end (void)
9999 fputs ("\t.endp\n\n", asm_out_file
);
10001 /* Output all pending externs. */
10003 unicosmk_output_externs (asm_out_file
);
10005 /* Output dex definitions used for functions whose names conflict with
10008 unicosmk_output_dex (asm_out_file
);
10010 fputs ("\t.end\t", asm_out_file
);
10011 unicosmk_output_module_name (asm_out_file
);
10012 putc ('\n', asm_out_file
);
10018 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10022 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10026 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10027 const char * fnname ATTRIBUTE_UNUSED
)
10031 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10037 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10042 #endif /* TARGET_ABI_UNICOSMK */
10045 alpha_init_libfuncs (void)
10047 if (TARGET_ABI_UNICOSMK
)
10049 /* Prevent gcc from generating calls to __divsi3. */
10050 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10051 set_optab_libfunc (udiv_optab
, SImode
, 0);
10053 /* Use the functions provided by the system library
10054 for DImode integer division. */
10055 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10056 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10058 else if (TARGET_ABI_OPEN_VMS
)
10060 /* Use the VMS runtime library functions for division and
10062 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10063 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10064 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10065 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10066 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10067 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10068 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10069 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10074 /* Initialize the GCC target structure. */
10075 #if TARGET_ABI_OPEN_VMS
10076 # undef TARGET_ATTRIBUTE_TABLE
10077 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10078 # undef TARGET_SECTION_TYPE_FLAGS
10079 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10082 #undef TARGET_IN_SMALL_DATA_P
10083 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10085 #if TARGET_ABI_UNICOSMK
10086 # undef TARGET_INSERT_ATTRIBUTES
10087 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10088 # undef TARGET_SECTION_TYPE_FLAGS
10089 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10090 # undef TARGET_ASM_UNIQUE_SECTION
10091 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10092 # undef TARGET_ASM_GLOBALIZE_LABEL
10093 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10096 #undef TARGET_ASM_ALIGNED_HI_OP
10097 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10098 #undef TARGET_ASM_ALIGNED_DI_OP
10099 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10101 /* Default unaligned ops are provided for ELF systems. To get unaligned
10102 data for non-ELF systems, we have to turn off auto alignment. */
10103 #ifndef OBJECT_FORMAT_ELF
10104 #undef TARGET_ASM_UNALIGNED_HI_OP
10105 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10106 #undef TARGET_ASM_UNALIGNED_SI_OP
10107 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10108 #undef TARGET_ASM_UNALIGNED_DI_OP
10109 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10112 #ifdef OBJECT_FORMAT_ELF
10113 #undef TARGET_ASM_SELECT_RTX_SECTION
10114 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10117 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10118 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10120 #undef TARGET_INIT_LIBFUNCS
10121 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10123 #if TARGET_ABI_UNICOSMK
10124 #undef TARGET_ASM_FILE_START
10125 #define TARGET_ASM_FILE_START unicosmk_file_start
10126 #undef TARGET_ASM_FILE_END
10127 #define TARGET_ASM_FILE_END unicosmk_file_end
10129 #undef TARGET_ASM_FILE_START
10130 #define TARGET_ASM_FILE_START alpha_file_start
10131 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10132 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10135 #undef TARGET_SCHED_ADJUST_COST
10136 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10137 #undef TARGET_SCHED_ISSUE_RATE
10138 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10139 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10140 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10141 alpha_use_dfa_pipeline_interface
10142 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10143 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10144 alpha_multipass_dfa_lookahead
10146 #undef TARGET_HAVE_TLS
10147 #define TARGET_HAVE_TLS HAVE_AS_TLS
10149 #undef TARGET_INIT_BUILTINS
10150 #define TARGET_INIT_BUILTINS alpha_init_builtins
10151 #undef TARGET_EXPAND_BUILTIN
10152 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10154 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10155 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10156 #undef TARGET_CANNOT_COPY_INSN_P
10157 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10160 #undef TARGET_ASM_OUTPUT_MI_THUNK
10161 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10162 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10163 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10166 #undef TARGET_RTX_COSTS
10167 #define TARGET_RTX_COSTS alpha_rtx_costs
10168 #undef TARGET_ADDRESS_COST
10169 #define TARGET_ADDRESS_COST hook_int_rtx_0
10171 #undef TARGET_MACHINE_DEPENDENT_REORG
10172 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10174 #undef TARGET_PROMOTE_FUNCTION_ARGS
10175 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10176 #undef TARGET_PROMOTE_FUNCTION_RETURN
10177 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10178 #undef TARGET_PROMOTE_PROTOTYPES
10179 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10180 #undef TARGET_STRUCT_VALUE_RTX
10181 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
10182 #undef TARGET_RETURN_IN_MEMORY
10183 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10184 #undef TARGET_SETUP_INCOMING_VARARGS
10185 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10186 #undef TARGET_STRICT_ARGUMENT_NAMING
10187 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10188 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10189 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10191 #undef TARGET_BUILD_BUILTIN_VA_LIST
10192 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10194 struct gcc_target targetm
= TARGET_INITIALIZER
;
10197 #include "gt-alpha.h"