1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
40 /* Save information from a "cmpxx" operation until the branch or scc is
43 rtx alpha_compare_op0
, alpha_compare_op1
;
44 int alpha_compare_fp_p
;
46 /* Save the name of the current function as used by the assembler. This
47 is used by the epilogue. */
49 char *alpha_function_name
;
51 /* Nonzero if the current function needs gp. */
53 int alpha_function_needs_gp
;
55 extern char *version_string
;
57 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
65 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
67 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
73 /* Returns 1 if OP is either the constant zero or a register. If a
74 register, it must be in the proper mode unless MODE is VOIDmode. */
77 reg_or_0_operand (op
, mode
)
79 enum machine_mode mode
;
81 return op
== const0_rtx
|| register_operand (op
, mode
);
84 /* Return 1 if OP is an 8-bit constant or any register. */
87 reg_or_8bit_operand (op
, mode
)
89 enum machine_mode mode
;
91 return ((GET_CODE (op
) == CONST_INT
92 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
93 || register_operand (op
, mode
));
96 /* Return 1 if the operand is a valid second operand to an add insn. */
99 add_operand (op
, mode
)
101 enum machine_mode mode
;
103 if (GET_CODE (op
) == CONST_INT
)
104 return ((unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x8000) < 0x10000
105 || ((INTVAL (op
) & 0xffff) == 0
106 && (INTVAL (op
) >> 31 == -1
107 || INTVAL (op
) >> 31 == 0)));
109 return register_operand (op
, mode
);
112 /* Return 1 if the operand is a valid second operand to a sign-extending
116 sext_add_operand (op
, mode
)
118 enum machine_mode mode
;
120 if (GET_CODE (op
) == CONST_INT
)
121 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 255
122 || (unsigned HOST_WIDE_INT
) (- INTVAL (op
)) < 255);
124 return register_operand (op
, mode
);
127 /* Return 1 if OP is the constant 4 or 8. */
130 const48_operand (op
, mode
)
132 enum machine_mode mode
;
134 return (GET_CODE (op
) == CONST_INT
135 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
138 /* Return 1 if OP is a valid first operand to an AND insn. */
141 and_operand (op
, mode
)
143 enum machine_mode mode
;
145 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
146 return (zap_mask (CONST_DOUBLE_LOW (op
))
147 && zap_mask (CONST_DOUBLE_HIGH (op
)));
149 if (GET_CODE (op
) == CONST_INT
)
150 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
151 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
152 || zap_mask (INTVAL (op
)));
154 return register_operand (op
, mode
);
157 /* Return 1 if OP is a constant that is the width, in bits, of an integral
158 mode smaller than DImode. */
161 mode_width_operand (op
, mode
)
163 enum machine_mode mode
;
165 return (GET_CODE (op
) == CONST_INT
166 && (INTVAL (op
) == 8 || INTVAL (op
) == 16 || INTVAL (op
) == 32));
169 /* Return 1 if OP is a constant that is the width of an integral machine mode
170 smaller than an integer. */
173 mode_mask_operand (op
, mode
)
175 enum machine_mode mode
;
177 #if HOST_BITS_PER_WIDE_INT == 32
178 if (GET_CODE (op
) == CONST_DOUBLE
)
179 return CONST_DOUBLE_HIGH (op
) == 0 && CONST_DOUBLE_LOW (op
) == -1;
182 if (GET_CODE (op
) == CONST_INT
)
183 return (INTVAL (op
) == 0xff
184 || INTVAL (op
) == 0xffff
185 #if HOST_BITS_PER_WIDE_INT == 64
186 || INTVAL (op
) == 0xffffffff
191 /* Return 1 if OP is a multiple of 8 less than 64. */
194 mul8_operand (op
, mode
)
196 enum machine_mode mode
;
198 return (GET_CODE (op
) == CONST_INT
199 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
200 && (INTVAL (op
) & 7) == 0);
203 /* Return 1 if OP is the constant zero in floating-point. */
206 fp0_operand (op
, mode
)
208 enum machine_mode mode
;
210 return (GET_MODE (op
) == mode
211 && GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
));
214 /* Return 1 if OP is the floating-point constant zero or a register. */
217 reg_or_fp0_operand (op
, mode
)
219 enum machine_mode mode
;
221 return fp0_operand (op
, mode
) || register_operand (op
, mode
);
224 /* Return 1 if OP is a register or a constant integer. */
228 reg_or_cint_operand (op
, mode
)
230 enum machine_mode mode
;
232 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
235 /* Return 1 if OP is a valid operand for the source of a move insn. */
238 input_operand (op
, mode
)
240 enum machine_mode mode
;
242 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
245 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
248 switch (GET_CODE (op
))
253 return mode
== DImode
;
259 if (register_operand (op
, mode
))
261 /* ... fall through ... */
263 return mode
!= HImode
&& mode
!= QImode
&& general_operand (op
, mode
);
266 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
269 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
275 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
279 current_file_function_operand (op
, mode
)
281 enum machine_mode mode
;
283 return (GET_CODE (op
) == SYMBOL_REF
284 && (SYMBOL_REF_FLAG (op
)
285 || op
== XEXP (DECL_RTL (current_function_decl
), 0)));
288 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
289 comparisons are valid in which insn. */
292 alpha_comparison_operator (op
, mode
)
294 enum machine_mode mode
;
296 enum rtx_code code
= GET_CODE (op
);
298 if (mode
!= GET_MODE (op
) || GET_RTX_CLASS (code
) != '<')
301 return (code
== EQ
|| code
== LE
|| code
== LT
302 || (mode
== DImode
&& (code
== LEU
|| code
== LTU
)));
305 /* Return 1 if OP is a signed comparison operation. */
308 signed_comparison_operator (op
, mode
)
310 enum machine_mode mode
;
312 switch (GET_CODE (op
))
314 case EQ
: case NE
: case LE
: case LT
: case GE
: case GT
:
321 /* Return 1 if this is a divide or modulus operator. */
324 divmod_operator (op
, mode
)
326 enum machine_mode mode
;
328 switch (GET_CODE (op
))
330 case DIV
: case MOD
: case UDIV
: case UMOD
:
337 /* Return 1 if this memory address is a known aligned register plus
338 a constant. It must be a valid address. This means that we can do
339 this as an aligned reference plus some offset.
341 Take into account what reload will do.
343 We could say that out-of-range stack slots are alignable, but that would
344 complicate get_aligned_mem and it isn't worth the trouble since few
345 functions have large stack space. */
348 aligned_memory_operand (op
, mode
)
350 enum machine_mode mode
;
352 if (GET_CODE (op
) == SUBREG
)
354 if (GET_MODE (op
) != mode
)
356 op
= SUBREG_REG (op
);
357 mode
= GET_MODE (op
);
360 if (reload_in_progress
&& GET_CODE (op
) == REG
361 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
362 op
= reg_equiv_mem
[REGNO (op
)];
364 if (GET_CODE (op
) != MEM
|| GET_MODE (op
) != mode
365 || ! memory_address_p (mode
, XEXP (op
, 0)))
370 if (GET_CODE (op
) == PLUS
)
373 return (GET_CODE (op
) == REG
374 && (REGNO (op
) == STACK_POINTER_REGNUM
|| op
== frame_pointer_rtx
375 || (REGNO (op
) >= FIRST_VIRTUAL_REGISTER
376 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
379 /* Similar, but return 1 if OP is a MEM which is not alignable. */
382 unaligned_memory_operand (op
, mode
)
384 enum machine_mode mode
;
386 if (GET_CODE (op
) == SUBREG
)
388 if (GET_MODE (op
) != mode
)
390 op
= SUBREG_REG (op
);
391 mode
= GET_MODE (op
);
394 if (reload_in_progress
&& GET_CODE (op
) == REG
395 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
396 op
= reg_equiv_mem
[REGNO (op
)];
398 if (GET_CODE (op
) != MEM
|| GET_MODE (op
) != mode
)
403 if (! memory_address_p (mode
, op
))
406 if (GET_CODE (op
) == PLUS
)
409 return (GET_CODE (op
) != REG
410 || (REGNO (op
) != STACK_POINTER_REGNUM
&& op
!= frame_pointer_rtx
411 && (REGNO (op
) < FIRST_VIRTUAL_REGISTER
412 || REGNO (op
) > LAST_VIRTUAL_REGISTER
)));
415 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
418 any_memory_operand (op
, mode
)
420 enum machine_mode mode
;
422 return (GET_CODE (op
) == MEM
423 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
424 || (reload_in_progress
&& GET_CODE (op
) == REG
425 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
426 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
427 && GET_CODE (SUBREG_REG (op
)) == REG
428 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
431 /* REF is an alignable memory location. Place an aligned SImode
432 reference into *PALIGNED_MEM and the number of bits to shift into
436 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
438 rtx
*paligned_mem
, *pbitnum
;
441 HOST_WIDE_INT offset
= 0;
443 if (GET_CODE (ref
) == SUBREG
)
445 offset
= SUBREG_WORD (ref
) * UNITS_PER_WORD
;
446 if (BYTES_BIG_ENDIAN
)
447 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (ref
)))
448 - MIN (UNITS_PER_WORD
,
449 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref
)))));
450 ref
= SUBREG_REG (ref
);
453 if (GET_CODE (ref
) == REG
)
454 ref
= reg_equiv_mem
[REGNO (ref
)];
456 if (reload_in_progress
)
457 base
= find_replacement (&XEXP (ref
, 0));
459 base
= XEXP (ref
, 0);
461 if (GET_CODE (base
) == PLUS
)
462 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
464 *paligned_mem
= gen_rtx (MEM
, SImode
,
465 plus_constant (base
, offset
& ~3));
466 MEM_IN_STRUCT_P (*paligned_mem
) = MEM_IN_STRUCT_P (ref
);
467 MEM_VOLATILE_P (*paligned_mem
) = MEM_VOLATILE_P (ref
);
468 RTX_UNCHANGING_P (*paligned_mem
) = RTX_UNCHANGING_P (ref
);
470 *pbitnum
= GEN_INT ((offset
& 3) * 8);
473 /* Similar, but just get the address. Handle the two reload cases. */
476 get_unaligned_address (ref
)
480 HOST_WIDE_INT offset
= 0;
482 if (GET_CODE (ref
) == SUBREG
)
484 offset
= SUBREG_WORD (ref
) * UNITS_PER_WORD
;
485 if (BYTES_BIG_ENDIAN
)
486 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (ref
)))
487 - MIN (UNITS_PER_WORD
,
488 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref
)))));
489 ref
= SUBREG_REG (ref
);
492 if (GET_CODE (ref
) == REG
)
493 ref
= reg_equiv_mem
[REGNO (ref
)];
495 if (reload_in_progress
)
496 base
= find_replacement (&XEXP (ref
, 0));
498 base
= XEXP (ref
, 0);
500 if (GET_CODE (base
) == PLUS
)
501 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
503 return plus_constant (base
, offset
);
506 /* Subfunction of the following function. Update the flags of any MEM
507 found in part of X. */
510 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
512 int in_struct_p
, volatile_p
, unchanging_p
;
516 switch (GET_CODE (x
))
520 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
521 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
526 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
531 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
533 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
538 MEM_IN_STRUCT_P (x
) = in_struct_p
;
539 MEM_VOLATILE_P (x
) = volatile_p
;
540 RTX_UNCHANGING_P (x
) = unchanging_p
;
545 /* Given INSN, which is either an INSN or a SEQUENCE generated to
546 perform a memory operation, look for any MEMs in either a SET_DEST or
547 a SET_SRC and copy the in-struct, unchanging, and volatile flags from
548 REF into each of the MEMs found. If REF is not a MEM, don't do
552 alpha_set_memflags (insn
, ref
)
556 /* Note that it is always safe to get these flags, though they won't
557 be what we think if REF is not a MEM. */
558 int in_struct_p
= MEM_IN_STRUCT_P (ref
);
559 int volatile_p
= MEM_VOLATILE_P (ref
);
560 int unchanging_p
= RTX_UNCHANGING_P (ref
);
562 if (GET_CODE (ref
) != MEM
563 || (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
))
566 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
569 /* Try to output insns to set TARGET equal to the constant C if it can be
570 done in less than N insns. Returns 1 if it can be done and the
571 insns have been emitted. If it would take more than N insns, zero is
572 returned and no insns and emitted. */
575 alpha_emit_set_const (target
, c
, n
)
580 HOST_WIDE_INT
new = c
;
583 #if HOST_BITS_PER_WIDE_INT == 64
584 /* We are only called for SImode and DImode. If this is SImode, ensure that
585 we are sign extended to a full word. This does not make any sense when
586 cross-compiling on a narrow machine. */
588 if (GET_MODE (target
) == SImode
)
589 c
= (c
& 0xffffffff) - 2 * (c
& 0x80000000);
592 /* If this is a sign-extended 32-bit constant, we can do this in at most
593 three insns, so do it if we have enough insns left. We always have
594 a sign-extended 32-bit constant when compiling on a narrow machine. */
596 if (HOST_BITS_PER_WIDE_INT
!= 64
597 || c
>> 31 == -1 || c
>> 31 == 0)
599 HOST_WIDE_INT low
= (c
& 0xffff) - 2 * (c
& 0x8000);
600 HOST_WIDE_INT tmp1
= c
- low
;
602 = ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
603 HOST_WIDE_INT tmp2
= c
- (high
<< 16) - low
;
604 HOST_WIDE_INT extra
= 0;
610 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
613 if (c
== low
|| (low
== 0 && extra
== 0))
615 emit_move_insn (target
, GEN_INT (c
));
618 else if (n
>= 2 + (extra
!= 0))
620 emit_move_insn (target
, GEN_INT (low
));
622 emit_insn (gen_add2_insn (target
, GEN_INT (extra
<< 16)));
624 emit_insn (gen_add2_insn (target
, GEN_INT (high
<< 16)));
629 /* If we couldn't do it that way, try some other methods (that depend on
630 being able to compute in the target's word size). But if we have no
631 instructions left, don't bother. Also, don't even try if this is
632 SImode (in which case we should have already done something, but
633 do a sanity check here). */
635 if (n
== 1 || HOST_BITS_PER_WIDE_INT
< 64 || GET_MODE (target
) != DImode
)
638 /* First, see if can load a value into the target that is the same as the
639 constant except that all bytes that are 0 are changed to be 0xff. If we
640 can, then we can do a ZAPNOT to obtain the desired constant. */
642 for (i
= 0; i
< 64; i
+= 8)
643 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
644 new |= (HOST_WIDE_INT
) 0xff << i
;
646 if (alpha_emit_set_const (target
, new, n
- 1))
648 emit_insn (gen_anddi3 (target
, target
, GEN_INT (c
| ~ new)));
652 /* Find, see if we can load a related constant and then shift and possibly
653 negate it to get the constant we want. Try this once each increasing
656 for (i
= 1; i
< n
; i
++)
658 /* First try complementing. */
659 if (alpha_emit_set_const (target
, ~ c
, i
))
661 emit_insn (gen_one_cmpldi2 (target
, target
));
665 /* First try to form a constant and do a left shift. We can do this
666 if some low-order bits are zero; the exact_log2 call below tells
667 us that information. The bits we are shifting out could be any
668 value, but here we'll just try the 0- and sign-extended forms of
669 the constant. To try to increase the chance of having the same
670 constant in more than one insn, start at the highest number of
671 bits to shift, but try all possibilities in case a ZAPNOT will
674 if ((bits
= exact_log2 (c
& - c
)) > 0)
675 for (; bits
> 0; bits
--)
676 if (alpha_emit_set_const (target
, c
>> bits
, i
)
677 || alpha_emit_set_const (target
,
678 ((unsigned HOST_WIDE_INT
) c
) >> bits
,
681 emit_insn (gen_ashldi3 (target
, target
, GEN_INT (bits
)));
685 /* Now try high-order zero bits. Here we try the shifted-in bits as
686 all zero and all ones. */
688 if ((bits
= HOST_BITS_PER_WIDE_INT
- floor_log2 (c
) - 1) > 0)
689 for (; bits
> 0; bits
--)
690 if (alpha_emit_set_const (target
, c
<< bits
, i
)
691 || alpha_emit_set_const (target
,
693 | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
696 emit_insn (gen_lshrdi3 (target
, target
, GEN_INT (bits
)));
700 /* Now try high-order 1 bits. We get that with a sign-extension.
701 But one bit isn't enough here. */
703 if ((bits
= HOST_BITS_PER_WIDE_INT
- floor_log2 (~ c
) - 2) > 0)
704 for (; bits
> 0; bits
--)
705 if (alpha_emit_set_const (target
, c
<< bits
, i
)
706 || alpha_emit_set_const (target
,
708 | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
711 emit_insn (gen_ashrdi3 (target
, target
, GEN_INT (bits
)));
719 /* Adjust the cost of a scheduling dependency. Return the new cost of
720 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
723 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
731 /* If the dependence is an anti-dependence, there is no cost. For an
732 output dependence, there is sometimes a cost, but it doesn't seem
733 worth handling those few cases. */
735 if (REG_NOTE_KIND (link
) != 0)
738 /* If INSN is a store insn and DEP_INSN is setting the data being stored,
739 we can sometimes lower the cost. */
741 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) == TYPE_ST
742 && (set
= single_set (dep_insn
)) != 0
743 && GET_CODE (PATTERN (insn
)) == SET
744 && rtx_equal_p (SET_DEST (set
), SET_SRC (PATTERN (insn
))))
745 switch (get_attr_type (dep_insn
))
748 /* No savings here. */
753 /* In these cases, we save one cycle. */
757 /* In all other cases, we save two cycles. */
758 return MAX (0, cost
- 4);
761 /* Another case that needs adjustment is an arithmetic or logical
762 operation. It's cost is usually one cycle, but we default it to
763 two in the MD file. The only case that it is actually two is
764 for the address in loads and stores. */
766 if (recog_memoized (dep_insn
) >= 0
767 && get_attr_type (dep_insn
) == TYPE_IADDLOG
)
768 switch (get_attr_type (insn
))
778 /* The final case is when a compare feeds into an integer branch. The cost
779 is only one cycle in that case. */
781 if (recog_memoized (dep_insn
) >= 0
782 && get_attr_type (dep_insn
) == TYPE_ICMP
783 && recog_memoized (insn
) >= 0
784 && get_attr_type (insn
) == TYPE_IBR
)
787 /* Otherwise, return the default cost. */
792 /* Print an operand. Recognize special options, documented below. */
795 print_operand (file
, x
, code
)
805 /* If this operand is the constant zero, write it as "$31". */
806 if (GET_CODE (x
) == REG
)
807 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
808 else if (x
== CONST0_RTX (GET_MODE (x
)))
809 fprintf (file
, "$31");
811 output_operand_lossage ("invalid %%r value");
816 /* Similar, but for floating-point. */
817 if (GET_CODE (x
) == REG
)
818 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
819 else if (x
== CONST0_RTX (GET_MODE (x
)))
820 fprintf (file
, "$f31");
822 output_operand_lossage ("invalid %%R value");
827 /* Write the 1's complement of a constant. */
828 if (GET_CODE (x
) != CONST_INT
)
829 output_operand_lossage ("invalid %%N value");
831 fprintf (file
, "%ld", ~ INTVAL (x
));
835 /* Write 1 << C, for a constant C. */
836 if (GET_CODE (x
) != CONST_INT
)
837 output_operand_lossage ("invalid %%P value");
839 fprintf (file
, "%ld", (HOST_WIDE_INT
) 1 << INTVAL (x
));
843 /* Write the high-order 16 bits of a constant, sign-extended. */
844 if (GET_CODE (x
) != CONST_INT
)
845 output_operand_lossage ("invalid %%h value");
847 fprintf (file
, "%ld", INTVAL (x
) >> 16);
851 /* Write the low-order 16 bits of a constant, sign-extended. */
852 if (GET_CODE (x
) != CONST_INT
)
853 output_operand_lossage ("invalid %%L value");
855 fprintf (file
, "%ld", (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
859 /* Write mask for ZAP insn. */
860 if (GET_CODE (x
) == CONST_DOUBLE
)
862 HOST_WIDE_INT mask
= 0;
865 value
= CONST_DOUBLE_LOW (x
);
866 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
871 value
= CONST_DOUBLE_HIGH (x
);
872 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
875 mask
|= (1 << (i
+ sizeof (int)));
877 fprintf (file
, "%ld", mask
& 0xff);
880 else if (GET_CODE (x
) == CONST_INT
)
882 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
884 for (i
= 0; i
< 8; i
++, value
>>= 8)
888 fprintf (file
, "%ld", mask
);
891 output_operand_lossage ("invalid %%m value");
895 /* 'b', 'w', or 'l' as the value of the constant. */
896 if (GET_CODE (x
) != CONST_INT
897 || (INTVAL (x
) != 8 && INTVAL (x
) != 16 && INTVAL (x
) != 32))
898 output_operand_lossage ("invalid %%M value");
901 INTVAL (x
) == 8 ? "b" : INTVAL (x
) == 16 ? "w" : "l");
905 /* Similar, except do it from the mask. */
906 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xff)
908 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffff)
910 #if HOST_BITS_PER_WIDE_INT == 32
911 else if (GET_CODE (x
) == CONST_DOUBLE
912 && CONST_DOUBLE_HIGH (x
) == 0
913 && CONST_DOUBLE_LOW (x
) == -1)
916 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffffffff)
920 output_operand_lossage ("invalid %%U value");
924 /* Write the constant value divided by 8. */
925 if (GET_CODE (x
) != CONST_INT
926 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
927 && (INTVAL (x
) & 7) != 8)
928 output_operand_lossage ("invalid %%s value");
930 fprintf (file
, "%ld", INTVAL (x
) / 8);
934 /* Same, except compute (64 - c) / 8 */
936 if (GET_CODE (x
) != CONST_INT
937 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
938 && (INTVAL (x
) & 7) != 8)
939 output_operand_lossage ("invalid %%s value");
941 fprintf (file
, "%ld", (64 - INTVAL (x
)) / 8);
945 /* Write out comparison name. */
946 if (GET_RTX_CLASS (GET_CODE (x
)) != '<')
947 output_operand_lossage ("invalid %%C value");
949 if (GET_CODE (x
) == LEU
)
950 fprintf (file
, "ule");
951 else if (GET_CODE (x
) == LTU
)
952 fprintf (file
, "ult");
954 fprintf (file
, "%s", GET_RTX_NAME (GET_CODE (x
)));
958 /* Similar, but write reversed code. We can't get an unsigned code
960 if (GET_RTX_CLASS (GET_CODE (x
)) != '<')
961 output_operand_lossage ("invalid %%D value");
963 fprintf (file
, "%s", GET_RTX_NAME (reverse_condition (GET_CODE (x
))));
967 /* Write the divide or modulus operator. */
968 switch (GET_CODE (x
))
971 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
974 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
977 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
980 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
983 output_operand_lossage ("invalid %%E value");
989 /* Write "_u" for unaligned access. */
990 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
991 fprintf (file
, "_u");
995 if (GET_CODE (x
) == REG
)
996 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
997 else if (GET_CODE (x
) == MEM
)
998 output_address (XEXP (x
, 0));
1000 output_addr_const (file
, x
);
1004 output_operand_lossage ("invalid %%xn code");
1008 /* Do what is necessary for `va_start'. The argument is ignored;
1009 We look at the current function to determine if stdarg or varargs
1010 is used and fill in an initial va_list. A pointer to this constructor
1014 alpha_builtin_saveregs (arglist
)
1017 rtx block
, addr
, argsize
;
1018 tree fntype
= TREE_TYPE (current_function_decl
);
1019 int stdarg
= (TYPE_ARG_TYPES (fntype
) != 0
1020 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
1021 != void_type_node
));
1023 /* Compute the current position into the args, taking into account
1024 both registers and memory. */
1026 argsize
= plus_constant (current_function_arg_offset_rtx
,
1027 current_function_args_info
* UNITS_PER_WORD
);
1029 /* Allocate the va_list constructor */
1030 block
= assign_stack_local (BLKmode
, 2 * UNITS_PER_WORD
, BITS_PER_WORD
);
1031 RTX_UNCHANGING_P (block
) = 1;
1032 RTX_UNCHANGING_P (XEXP (block
, 0)) = 1;
1034 /* Store the address of the first integer register in the
1035 __va_base member. */
1037 emit_move_insn (change_address (block
, DImode
, XEXP (block
, 0)),
1038 force_operand (plus_constant (virtual_incoming_args_rtx
,
1039 6 * UNITS_PER_WORD
),
1042 /* Store the argsize as the __va_offset member. */
1043 emit_move_insn (change_address (block
, Pmode
,
1044 plus_constant (XEXP (block
, 0),
1046 force_operand (argsize
, NULL_RTX
));
1048 /* Return the address of the va_list constructor, but don't put it in a
1049 register. Doing so would fail when not optimizing and produce worse
1050 code when optimizing. */
1051 return XEXP (block
, 0);
1054 /* This page contains routines that are used to determine what the function
1055 prologue and epilogue code will do and write them out. */
1057 /* Compute the size of the save area in the stack. */
1065 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1066 if (! fixed_regs
[i
] && ! call_used_regs
[i
] && regs_ever_live
[i
])
1069 /* If some registers were saved but not reg 26, reg 26 must also
1070 be saved, so leave space for it. */
1071 if (size
!= 0 && ! regs_ever_live
[26])
1077 /* Return 1 if this function can directly return via $26. */
1082 return (reload_completed
&& alpha_sa_size () == 0
1083 && get_frame_size () == 0
1084 && current_function_pretend_args_size
== 0);
1087 /* Write a version stamp. Don't write anything if we are running as a
1088 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
1090 #ifndef CROSS_COMPILE
1095 alpha_write_verstamp (file
)
1101 fprintf (file
, "\t.verstamp %d %d ", MS_STAMP
, LS_STAMP
);
1102 for (p
= version_string
; *p
!= ' ' && *p
!= 0; p
++)
1103 fprintf (file
, "%c", *p
== '.' ? ' ' : *p
);
1104 fprintf (file
, "\n");
1108 /* Write function prologue. */
1111 output_prolog (file
, size
)
1115 HOST_WIDE_INT frame_size
= ((size
+ current_function_outgoing_args_size
1116 + current_function_pretend_args_size
1117 + alpha_sa_size () + 15) & ~15);
1118 int reg_offset
= size
+ current_function_outgoing_args_size
;
1120 int start_reg_offset
= reg_offset
;
1121 unsigned reg_mask
= 0;
1124 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
1125 Even if we are a static function, we still need to do this in case
1126 our address is taken and passed to something like qsort. */
1128 alpha_function_needs_gp
= 0;
1129 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1130 if ((GET_CODE (insn
) == CALL_INSN
)
1131 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1132 && GET_CODE (PATTERN (insn
)) != USE
1133 && GET_CODE (PATTERN (insn
)) != CLOBBER
1134 && get_attr_type (insn
) == TYPE_LDSYM
))
1136 alpha_function_needs_gp
= 1;
1140 if (alpha_function_needs_gp
)
1141 fprintf (file
, "\tldgp $29,0($27)\n");
1143 /* Put a label after the GP load so we can enter the function at it. */
1144 fprintf (file
, "%s..ng:\n", alpha_function_name
);
1146 /* Adjust the stack by the frame size. If the frame size is > 4096
1147 bytes, we need to be sure we probe somewhere in the first and last
1148 4096 bytes (we can probably get away without the latter test) and
1149 every 8192 bytes in between. If the frame size is > 32768, we
1150 do this in a loop. Otherwise, we generate the explicit probe
1153 Note that we are only allowed to adjust sp once in the prologue. */
1155 if (frame_size
< 32768)
1157 if (frame_size
> 4096)
1162 fprintf (file
, "\tldq $%d,-%d($30)\n", regnum
++, probed
);
1164 while (probed
+ 8192 < frame_size
)
1165 fprintf (file
, "\tldq $%d,-%d($30)\n", regnum
++, probed
+= 8192);
1167 if (probed
+ 4096 < frame_size
)
1168 fprintf (file
, "\tldq $%d,-%d($30)\n", regnum
++, probed
+= 4096);
1174 if (frame_size
!= 0)
1175 fprintf (file
, "\tlda $30,-%d($30)\n", frame_size
);
1179 /* Here we generate code to set R4 to SP + 4096 and set R5 to the
1180 number of 8192 byte blocks to probe. We then probe each block
1181 in the loop and then set SP to the proper location. If the
1182 amount remaining is > 4096, we have to do one more probe.
1184 This is complicated by the code we would generate if
1185 the number of blocks > 32767. */
1187 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
1188 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
1189 HOST_WIDE_INT low
= (blocks
& 0xffff) - 2 * (blocks
& 0x8000);
1190 HOST_WIDE_INT tmp1
= blocks
- low
;
1192 = ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1193 HOST_WIDE_INT tmp2
= blocks
- (high
<< 16) - low
;
1194 HOST_WIDE_INT extra
= 0;
1201 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1207 fprintf (file
, "\tbis $31,%d,$5\n", low
);
1209 fprintf (file
, "\tlda $5,%d($31)\n", low
);
1215 fprintf (file
, "\tldah $5,%d($%d)\n", extra
, in_reg
);
1220 fprintf (file
, "\tldah $5,%d($%d)\n", high
, in_reg
);
1222 fprintf (file
, "\tlda $4,4096($30)\n");
1223 fprintf (file
, "%s..sc:\n", alpha_function_name
);
1224 fprintf (file
, "\tldq $6,-8192($4)\n");
1225 fprintf (file
, "\tsubq $5,1,$5\n");
1226 fprintf (file
, "\tlda $4,-8192($4)\n");
1227 fprintf (file
, "\tbne $5,%s..sc\n", alpha_function_name
);
1228 fprintf (file
, "\tlda $30,-%d($4)\n", leftover
);
1230 if (leftover
> 4096)
1231 fprintf (file
, "\tldq $2,%d(sp)\n", leftover
- 4096);
1234 /* Describe our frame. */
1235 fprintf (file
, "\t.frame $%d,%d,$26,%d\n",
1236 frame_pointer_needed
? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
,
1237 frame_size
, current_function_pretend_args_size
);
1239 /* Save register 26 if it is used or if any other register needs to
1241 if (regs_ever_live
[26] || alpha_sa_size () != 0)
1243 reg_mask
|= 1 << 26;
1244 fprintf (file
, "\tstq $26,%d($30)\n", reg_offset
);
1248 /* Now save any other used integer registers required to be saved. */
1249 for (i
= 0; i
< 32; i
++)
1250 if (! fixed_regs
[i
] && ! call_used_regs
[i
] && regs_ever_live
[i
] && i
!= 26)
1253 fprintf (file
, "\tstq $%d,%d($30)\n", i
, reg_offset
);
1257 /* Print the register mask and do floating-point saves. */
1259 fprintf (file
, "\t.mask 0x%x,%d\n", reg_mask
,
1260 start_reg_offset
- frame_size
);
1262 start_reg_offset
= reg_offset
;
1265 for (i
= 0; i
< 32; i
++)
1266 if (! fixed_regs
[i
+ 32] && ! call_used_regs
[i
+ 32]
1267 && regs_ever_live
[i
+ 32])
1270 fprintf (file
, "\tstt $f%d,%d($30)\n", i
, reg_offset
);
1274 /* Print the floating-point mask, if we've saved any fp register. */
1276 fprintf (file
, "\t.fmask 0x%x,%d\n", reg_mask
, start_reg_offset
);
1278 /* If we need a frame pointer, set it from the stack pointer. Note that
1279 this must always be the last instruction in the prologue. */
1280 if (frame_pointer_needed
)
1281 fprintf (file
, "\tbis $30,$30,$15\n");
1283 /* End the prologue and say if we used gp. */
1284 fprintf (file
, "\t.prologue %d\n", alpha_function_needs_gp
);
1287 /* Write function epilogue. */
1290 output_epilog (file
, size
)
1294 rtx insn
= get_last_insn ();
1295 HOST_WIDE_INT frame_size
= ((size
+ current_function_outgoing_args_size
1296 + current_function_pretend_args_size
1297 + alpha_sa_size () + 15) & ~15);
1298 int reg_offset
= size
+ current_function_outgoing_args_size
;
1301 /* If the last insn was a BARRIER, we don't have to write anything except
1302 the .end pseudo-op. */
1303 if (GET_CODE (insn
) == NOTE
)
1304 insn
= prev_nonnote_insn (insn
);
1305 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
1309 /* If we have a frame pointer, restore SP from it. */
1310 if (frame_pointer_needed
)
1311 fprintf (file
, "\tbis $15,$15,$30\n");
1313 /* Restore all the registers, starting with the return address
1315 if (regs_ever_live
[26] || alpha_sa_size () != 0)
1317 fprintf (file
, "\tldq $26,%d($30)\n", reg_offset
);
1321 /* Now restore any other used integer registers that that we saved,
1322 except for FP if it is being used as FP, since it must be
1325 for (i
= 0; i
< 32; i
++)
1326 if (! fixed_regs
[i
] && ! call_used_regs
[i
] && regs_ever_live
[i
]
1329 if (i
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
1330 fp_offset
= reg_offset
;
1332 fprintf (file
, "\tldq $%d,%d($30)\n", i
, reg_offset
);
1336 for (i
= 0; i
< 32; i
++)
1337 if (! fixed_regs
[i
+ 32] && ! call_used_regs
[i
+ 32]
1338 && regs_ever_live
[i
+ 32])
1340 fprintf (file
, "\tldt $f%d,%d($30)\n", i
, reg_offset
);
1344 /* If the stack size is large, compute the size of the stack into
1345 a register because the old FP restore, stack pointer adjust,
1346 and return are required to be consecutive instructions. */
1347 if (frame_size
> 32767)
1350 = (frame_size
& 0xffff) - 2 * (frame_size
& 0x8000);
1351 HOST_WIDE_INT tmp1
= frame_size
- low
;
1353 = ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1354 HOST_WIDE_INT tmp2
= frame_size
- (high
<< 16) - low
;
1355 HOST_WIDE_INT extra
= 0;
1358 /* We haven't written code to handle frames > 4GB. */
1359 #if HOST_BITS_PER_LONG_INT == 64
1360 if ((unsigned HOST_WIDE_INT
) frame_size
>> 32 != 0)
1368 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1373 fprintf (file
, "\tlda $28,%d($%d)\n", low
, in_reg
);
1379 fprintf (file
, "\tldah $28,%d($%d)\n", extra
, in_reg
);
1383 fprintf (file
, "\tldah $28,%d($%d)\n", high
, in_reg
);
1386 /* If we needed a frame pointer and we have to restore it, do it
1389 if (frame_pointer_needed
&& regs_ever_live
[FRAME_POINTER_REGNUM
])
1390 fprintf (file
, "\tldq $15,%d($30)\n", fp_offset
);
1392 /* Now update the stack pointer, if needed. This must be done in
1393 one, styalized, instruction. */
1394 if (frame_size
> 32768)
1395 fprintf (file
, "\taddq $28,$30,$30\n");
1397 fprintf (file
, "\tlda $30,%d($30)\n", frame_size
);
1399 /* Finally return to the caller. */
1400 fprintf (file
, "\tret $31,($26),1\n");
1403 /* End the function. */
1404 fprintf (file
, "\t.end %s\n", alpha_function_name
);
1406 /* Show that we know this function if it is called again. */
1407 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl
), 0)) = 1;