1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
56 #include "tree-flow.h"
57 #include "tree-stdarg.h"
59 /* Specify which cpu to schedule for. */
60 enum processor_type alpha_tune
;
62 /* Which cpu we're generating code for. */
63 enum processor_type alpha_cpu
;
65 static const char * const alpha_cpu_name
[] =
70 /* Specify how accurate floating-point traps need to be. */
72 enum alpha_trap_precision alpha_tp
;
74 /* Specify the floating-point rounding mode. */
76 enum alpha_fp_rounding_mode alpha_fprm
;
78 /* Specify which things cause traps. */
80 enum alpha_fp_trap_mode alpha_fptm
;
82 /* Save information from a "cmpxx" operation until the branch or scc is
85 struct alpha_compare alpha_compare
;
87 /* Nonzero if inside of a function, because the Alpha asm can't
88 handle .files inside of functions. */
90 static int inside_function
= FALSE
;
92 /* The number of cycles of latency we should assume on memory reads. */
94 int alpha_memory_latency
= 3;
96 /* Whether the function needs the GP. */
98 static int alpha_function_needs_gp
;
100 /* The alias set for prologue/epilogue register save/restore. */
102 static GTY(()) int alpha_sr_alias_set
;
104 /* The assembler name of the current function. */
106 static const char *alpha_fnname
;
108 /* The next explicit relocation sequence number. */
109 extern GTY(()) int alpha_next_sequence_number
;
110 int alpha_next_sequence_number
= 1;
112 /* The literal and gpdisp sequence numbers for this insn, as printed
113 by %# and %* respectively. */
114 extern GTY(()) int alpha_this_literal_sequence_number
;
115 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
116 int alpha_this_literal_sequence_number
;
117 int alpha_this_gpdisp_sequence_number
;
119 /* Costs of various operations on the different architectures. */
121 struct alpha_rtx_cost_data
123 unsigned char fp_add
;
124 unsigned char fp_mult
;
125 unsigned char fp_div_sf
;
126 unsigned char fp_div_df
;
127 unsigned char int_mult_si
;
128 unsigned char int_mult_di
;
129 unsigned char int_shift
;
130 unsigned char int_cmov
;
131 unsigned short int_div
;
134 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
137 COSTS_N_INSNS (6), /* fp_add */
138 COSTS_N_INSNS (6), /* fp_mult */
139 COSTS_N_INSNS (34), /* fp_div_sf */
140 COSTS_N_INSNS (63), /* fp_div_df */
141 COSTS_N_INSNS (23), /* int_mult_si */
142 COSTS_N_INSNS (23), /* int_mult_di */
143 COSTS_N_INSNS (2), /* int_shift */
144 COSTS_N_INSNS (2), /* int_cmov */
145 COSTS_N_INSNS (97), /* int_div */
148 COSTS_N_INSNS (4), /* fp_add */
149 COSTS_N_INSNS (4), /* fp_mult */
150 COSTS_N_INSNS (15), /* fp_div_sf */
151 COSTS_N_INSNS (22), /* fp_div_df */
152 COSTS_N_INSNS (8), /* int_mult_si */
153 COSTS_N_INSNS (12), /* int_mult_di */
154 COSTS_N_INSNS (1) + 1, /* int_shift */
155 COSTS_N_INSNS (1), /* int_cmov */
156 COSTS_N_INSNS (83), /* int_div */
159 COSTS_N_INSNS (4), /* fp_add */
160 COSTS_N_INSNS (4), /* fp_mult */
161 COSTS_N_INSNS (12), /* fp_div_sf */
162 COSTS_N_INSNS (15), /* fp_div_df */
163 COSTS_N_INSNS (7), /* int_mult_si */
164 COSTS_N_INSNS (7), /* int_mult_di */
165 COSTS_N_INSNS (1), /* int_shift */
166 COSTS_N_INSNS (2), /* int_cmov */
167 COSTS_N_INSNS (86), /* int_div */
171 /* Similar but tuned for code size instead of execution latency. The
172 extra +N is fractional cost tuning based on latency. It's used to
173 encourage use of cheaper insns like shift, but only if there's just
176 static struct alpha_rtx_cost_data
const alpha_rtx_cost_size
=
178 COSTS_N_INSNS (1), /* fp_add */
179 COSTS_N_INSNS (1), /* fp_mult */
180 COSTS_N_INSNS (1), /* fp_div_sf */
181 COSTS_N_INSNS (1) + 1, /* fp_div_df */
182 COSTS_N_INSNS (1) + 1, /* int_mult_si */
183 COSTS_N_INSNS (1) + 2, /* int_mult_di */
184 COSTS_N_INSNS (1), /* int_shift */
185 COSTS_N_INSNS (1), /* int_cmov */
186 COSTS_N_INSNS (6), /* int_div */
189 /* Get the number of args of a function in one of two ways. */
190 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
191 #define NUM_ARGS current_function_args_info.num_args
193 #define NUM_ARGS current_function_args_info
199 /* Declarations of static functions. */
200 static struct machine_function
*alpha_init_machine_status (void);
201 static rtx
alpha_emit_xfloating_compare (enum rtx_code
*, rtx
, rtx
);
203 #if TARGET_ABI_OPEN_VMS
204 static void alpha_write_linkage (FILE *, const char *, tree
);
207 static void unicosmk_output_deferred_case_vectors (FILE *);
208 static void unicosmk_gen_dsib (unsigned long *);
209 static void unicosmk_output_ssib (FILE *, const char *);
210 static int unicosmk_need_dex (rtx
);
212 /* Implement TARGET_HANDLE_OPTION. */
215 alpha_handle_option (size_t code
, const char *arg
, int value
)
221 target_flags
|= MASK_SOFT_FP
;
225 case OPT_mieee_with_inexact
:
226 target_flags
|= MASK_IEEE_CONFORMANT
;
230 if (value
!= 16 && value
!= 32 && value
!= 64)
231 error ("bad value %qs for -mtls-size switch", arg
);
238 /* Parse target option strings. */
241 override_options (void)
243 static const struct cpu_table
{
244 const char *const name
;
245 const enum processor_type processor
;
248 { "ev4", PROCESSOR_EV4
, 0 },
249 { "ev45", PROCESSOR_EV4
, 0 },
250 { "21064", PROCESSOR_EV4
, 0 },
251 { "ev5", PROCESSOR_EV5
, 0 },
252 { "21164", PROCESSOR_EV5
, 0 },
253 { "ev56", PROCESSOR_EV5
, MASK_BWX
},
254 { "21164a", PROCESSOR_EV5
, MASK_BWX
},
255 { "pca56", PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
256 { "21164PC",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
257 { "21164pc",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
258 { "ev6", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
259 { "21264", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
260 { "ev67", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
261 { "21264a", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
267 /* Unicos/Mk doesn't have shared libraries. */
268 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
270 warning (0, "-f%s ignored for Unicos/Mk (not supported)",
271 (flag_pic
> 1) ? "PIC" : "pic");
275 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
276 floating-point instructions. Make that the default for this target. */
277 if (TARGET_ABI_UNICOSMK
)
278 alpha_fprm
= ALPHA_FPRM_DYN
;
280 alpha_fprm
= ALPHA_FPRM_NORM
;
282 alpha_tp
= ALPHA_TP_PROG
;
283 alpha_fptm
= ALPHA_FPTM_N
;
285 /* We cannot use su and sui qualifiers for conversion instructions on
286 Unicos/Mk. I'm not sure if this is due to assembler or hardware
287 limitations. Right now, we issue a warning if -mieee is specified
288 and then ignore it; eventually, we should either get it right or
289 disable the option altogether. */
293 if (TARGET_ABI_UNICOSMK
)
294 warning (0, "-mieee not supported on Unicos/Mk");
297 alpha_tp
= ALPHA_TP_INSN
;
298 alpha_fptm
= ALPHA_FPTM_SU
;
302 if (TARGET_IEEE_WITH_INEXACT
)
304 if (TARGET_ABI_UNICOSMK
)
305 warning (0, "-mieee-with-inexact not supported on Unicos/Mk");
308 alpha_tp
= ALPHA_TP_INSN
;
309 alpha_fptm
= ALPHA_FPTM_SUI
;
315 if (! strcmp (alpha_tp_string
, "p"))
316 alpha_tp
= ALPHA_TP_PROG
;
317 else if (! strcmp (alpha_tp_string
, "f"))
318 alpha_tp
= ALPHA_TP_FUNC
;
319 else if (! strcmp (alpha_tp_string
, "i"))
320 alpha_tp
= ALPHA_TP_INSN
;
322 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string
);
325 if (alpha_fprm_string
)
327 if (! strcmp (alpha_fprm_string
, "n"))
328 alpha_fprm
= ALPHA_FPRM_NORM
;
329 else if (! strcmp (alpha_fprm_string
, "m"))
330 alpha_fprm
= ALPHA_FPRM_MINF
;
331 else if (! strcmp (alpha_fprm_string
, "c"))
332 alpha_fprm
= ALPHA_FPRM_CHOP
;
333 else if (! strcmp (alpha_fprm_string
,"d"))
334 alpha_fprm
= ALPHA_FPRM_DYN
;
336 error ("bad value %qs for -mfp-rounding-mode switch",
340 if (alpha_fptm_string
)
342 if (strcmp (alpha_fptm_string
, "n") == 0)
343 alpha_fptm
= ALPHA_FPTM_N
;
344 else if (strcmp (alpha_fptm_string
, "u") == 0)
345 alpha_fptm
= ALPHA_FPTM_U
;
346 else if (strcmp (alpha_fptm_string
, "su") == 0)
347 alpha_fptm
= ALPHA_FPTM_SU
;
348 else if (strcmp (alpha_fptm_string
, "sui") == 0)
349 alpha_fptm
= ALPHA_FPTM_SUI
;
351 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string
);
354 if (alpha_cpu_string
)
356 for (i
= 0; cpu_table
[i
].name
; i
++)
357 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
359 alpha_tune
= alpha_cpu
= cpu_table
[i
].processor
;
360 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
);
361 target_flags
|= cpu_table
[i
].flags
;
364 if (! cpu_table
[i
].name
)
365 error ("bad value %qs for -mcpu switch", alpha_cpu_string
);
368 if (alpha_tune_string
)
370 for (i
= 0; cpu_table
[i
].name
; i
++)
371 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
373 alpha_tune
= cpu_table
[i
].processor
;
376 if (! cpu_table
[i
].name
)
377 error ("bad value %qs for -mcpu switch", alpha_tune_string
);
380 /* Do some sanity checks on the above options. */
382 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
384 warning (0, "trap mode not supported on Unicos/Mk");
385 alpha_fptm
= ALPHA_FPTM_N
;
388 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
389 && alpha_tp
!= ALPHA_TP_INSN
&& alpha_cpu
!= PROCESSOR_EV6
)
391 warning (0, "fp software completion requires -mtrap-precision=i");
392 alpha_tp
= ALPHA_TP_INSN
;
395 if (alpha_cpu
== PROCESSOR_EV6
)
397 /* Except for EV6 pass 1 (not released), we always have precise
398 arithmetic traps. Which means we can do software completion
399 without minding trap shadows. */
400 alpha_tp
= ALPHA_TP_PROG
;
403 if (TARGET_FLOAT_VAX
)
405 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
407 warning (0, "rounding mode not supported for VAX floats");
408 alpha_fprm
= ALPHA_FPRM_NORM
;
410 if (alpha_fptm
== ALPHA_FPTM_SUI
)
412 warning (0, "trap mode not supported for VAX floats");
413 alpha_fptm
= ALPHA_FPTM_SU
;
415 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
416 warning (0, "128-bit long double not supported for VAX floats");
417 target_flags
&= ~MASK_LONG_DOUBLE_128
;
424 if (!alpha_mlat_string
)
425 alpha_mlat_string
= "L1";
427 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
428 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
430 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
431 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
432 && alpha_mlat_string
[2] == '\0')
434 static int const cache_latency
[][4] =
436 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
437 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
438 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
441 lat
= alpha_mlat_string
[1] - '0';
442 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_tune
][lat
-1] == -1)
444 warning (0, "L%d cache latency unknown for %s",
445 lat
, alpha_cpu_name
[alpha_tune
]);
449 lat
= cache_latency
[alpha_tune
][lat
-1];
451 else if (! strcmp (alpha_mlat_string
, "main"))
453 /* Most current memories have about 370ns latency. This is
454 a reasonable guess for a fast cpu. */
459 warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string
);
463 alpha_memory_latency
= lat
;
466 /* Default the definition of "small data" to 8 bytes. */
470 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
472 target_flags
|= MASK_SMALL_DATA
;
473 else if (flag_pic
== 2)
474 target_flags
&= ~MASK_SMALL_DATA
;
476 /* Align labels and loops for optimal branching. */
477 /* ??? Kludge these by not doing anything if we don't optimize and also if
478 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
479 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
481 if (align_loops
<= 0)
483 if (align_jumps
<= 0)
486 if (align_functions
<= 0)
487 align_functions
= 16;
489 /* Acquire a unique set number for our register saves and restores. */
490 alpha_sr_alias_set
= new_alias_set ();
492 /* Register variables and functions with the garbage collector. */
494 /* Set up function hooks. */
495 init_machine_status
= alpha_init_machine_status
;
497 /* Tell the compiler when we're using VAX floating point. */
498 if (TARGET_FLOAT_VAX
)
500 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
501 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
502 REAL_MODE_FORMAT (TFmode
) = NULL
;
506 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
509 zap_mask (HOST_WIDE_INT value
)
513 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
515 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
521 /* Return true if OP is valid for a particular TLS relocation.
522 We are already guaranteed that OP is a CONST. */
525 tls_symbolic_operand_1 (rtx op
, int size
, int unspec
)
529 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
531 op
= XVECEXP (op
, 0, 0);
533 if (GET_CODE (op
) != SYMBOL_REF
)
536 switch (SYMBOL_REF_TLS_MODEL (op
))
538 case TLS_MODEL_LOCAL_DYNAMIC
:
539 return unspec
== UNSPEC_DTPREL
&& size
== alpha_tls_size
;
540 case TLS_MODEL_INITIAL_EXEC
:
541 return unspec
== UNSPEC_TPREL
&& size
== 64;
542 case TLS_MODEL_LOCAL_EXEC
:
543 return unspec
== UNSPEC_TPREL
&& size
== alpha_tls_size
;
549 /* Used by aligned_memory_operand and unaligned_memory_operand to
550 resolve what reload is going to do with OP if it's a register. */
553 resolve_reload_operand (rtx op
)
555 if (reload_in_progress
)
558 if (GET_CODE (tmp
) == SUBREG
)
559 tmp
= SUBREG_REG (tmp
);
560 if (GET_CODE (tmp
) == REG
561 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
563 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
571 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
572 the range defined for C in [I-P]. */
575 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
580 /* An unsigned 8 bit constant. */
581 return (unsigned HOST_WIDE_INT
) value
< 0x100;
583 /* The constant zero. */
586 /* A signed 16 bit constant. */
587 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
589 /* A shifted signed 16 bit constant appropriate for LDAH. */
590 return ((value
& 0xffff) == 0
591 && ((value
) >> 31 == -1 || value
>> 31 == 0));
593 /* A constant that can be AND'ed with using a ZAP insn. */
594 return zap_mask (value
);
596 /* A complemented unsigned 8 bit constant. */
597 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
599 /* A negated unsigned 8 bit constant. */
600 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
602 /* The constant 1, 2 or 3. */
603 return value
== 1 || value
== 2 || value
== 3;
610 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
611 matches for C in [GH]. */
614 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
619 /* The floating point zero constant. */
620 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
621 && value
== CONST0_RTX (GET_MODE (value
)));
624 /* A valid operand of a ZAP insn. */
625 return (GET_MODE (value
) == VOIDmode
626 && zap_mask (CONST_DOUBLE_LOW (value
))
627 && zap_mask (CONST_DOUBLE_HIGH (value
)));
634 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
638 alpha_extra_constraint (rtx value
, int c
)
643 return normal_memory_operand (value
, VOIDmode
);
645 return direct_call_operand (value
, Pmode
);
647 return (GET_CODE (value
) == CONST_INT
648 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
650 return GET_CODE (value
) == HIGH
;
652 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
654 return (GET_CODE (value
) == CONST_VECTOR
655 && value
== CONST0_RTX (GET_MODE (value
)));
661 /* The scalar modes supported differs from the default check-what-c-supports
662 version in that sometimes TFmode is available even when long double
663 indicates only DFmode. On unicosmk, we have the situation that HImode
664 doesn't map to any C type, but of course we still support that. */
667 alpha_scalar_mode_supported_p (enum machine_mode mode
)
675 case TImode
: /* via optabs.c */
683 return TARGET_HAS_XFLOATING_LIBS
;
690 /* Alpha implements a couple of integer vector mode operations when
691 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
692 which allows the vectorizer to operate on e.g. move instructions,
693 or when expand_vector_operations can do something useful. */
696 alpha_vector_mode_supported_p (enum machine_mode mode
)
698 return mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
;
701 /* Return 1 if this function can directly return via $26. */
706 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
708 && alpha_sa_size () == 0
709 && get_frame_size () == 0
710 && current_function_outgoing_args_size
== 0
711 && current_function_pretend_args_size
== 0);
714 /* Return the ADDR_VEC associated with a tablejump insn. */
717 alpha_tablejump_addr_vec (rtx insn
)
721 tmp
= JUMP_LABEL (insn
);
724 tmp
= NEXT_INSN (tmp
);
727 if (GET_CODE (tmp
) == JUMP_INSN
728 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
729 return PATTERN (tmp
);
733 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
736 alpha_tablejump_best_label (rtx insn
)
738 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
739 rtx best_label
= NULL_RTX
;
741 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
742 there for edge frequency counts from profile data. */
746 int n_labels
= XVECLEN (jump_table
, 1);
750 for (i
= 0; i
< n_labels
; i
++)
754 for (j
= i
+ 1; j
< n_labels
; j
++)
755 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
756 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
759 if (count
> best_count
)
760 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
764 return best_label
? best_label
: const0_rtx
;
767 /* Return the TLS model to use for SYMBOL. */
769 static enum tls_model
770 tls_symbolic_operand_type (rtx symbol
)
772 enum tls_model model
;
774 if (GET_CODE (symbol
) != SYMBOL_REF
)
776 model
= SYMBOL_REF_TLS_MODEL (symbol
);
778 /* Local-exec with a 64-bit size is the same code as initial-exec. */
779 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
780 model
= TLS_MODEL_INITIAL_EXEC
;
785 /* Return true if the function DECL will share the same GP as any
786 function in the current unit of translation. */
789 decl_has_samegp (tree decl
)
791 /* Functions that are not local can be overridden, and thus may
792 not share the same gp. */
793 if (!(*targetm
.binds_local_p
) (decl
))
796 /* If -msmall-data is in effect, assume that there is only one GP
797 for the module, and so any local symbol has this property. We
798 need explicit relocations to be able to enforce this for symbols
799 not defined in this unit of translation, however. */
800 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
803 /* Functions that are not external are defined in this UoT. */
804 /* ??? Irritatingly, static functions not yet emitted are still
805 marked "external". Apply this to non-static functions only. */
806 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
809 /* Return true if EXP should be placed in the small data section. */
812 alpha_in_small_data_p (tree exp
)
814 /* We want to merge strings, so we never consider them small data. */
815 if (TREE_CODE (exp
) == STRING_CST
)
818 /* Functions are never in the small data area. Duh. */
819 if (TREE_CODE (exp
) == FUNCTION_DECL
)
822 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
824 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
825 if (strcmp (section
, ".sdata") == 0
826 || strcmp (section
, ".sbss") == 0)
831 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
833 /* If this is an incomplete type with size 0, then we can't put it
834 in sdata because it might be too big when completed. */
835 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
842 #if TARGET_ABI_OPEN_VMS
844 alpha_linkage_symbol_p (const char *symname
)
846 int symlen
= strlen (symname
);
849 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
854 #define LINKAGE_SYMBOL_REF_P(X) \
855 ((GET_CODE (X) == SYMBOL_REF \
856 && alpha_linkage_symbol_p (XSTR (X, 0))) \
857 || (GET_CODE (X) == CONST \
858 && GET_CODE (XEXP (X, 0)) == PLUS \
859 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
860 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
863 /* legitimate_address_p recognizes an RTL expression that is a valid
864 memory address for an instruction. The MODE argument is the
865 machine mode for the MEM expression that wants to use this address.
867 For Alpha, we have either a constant address or the sum of a
868 register and a constant address, or just a register. For DImode,
869 any of those forms can be surrounded with an AND that clear the
870 low-order three bits; this is an "unaligned" access. */
873 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
875 /* If this is an ldq_u type address, discard the outer AND. */
877 && GET_CODE (x
) == AND
878 && GET_CODE (XEXP (x
, 1)) == CONST_INT
879 && INTVAL (XEXP (x
, 1)) == -8)
882 /* Discard non-paradoxical subregs. */
883 if (GET_CODE (x
) == SUBREG
884 && (GET_MODE_SIZE (GET_MODE (x
))
885 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
888 /* Unadorned general registers are valid. */
891 ? STRICT_REG_OK_FOR_BASE_P (x
)
892 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
895 /* Constant addresses (i.e. +/- 32k) are valid. */
896 if (CONSTANT_ADDRESS_P (x
))
899 #if TARGET_ABI_OPEN_VMS
900 if (LINKAGE_SYMBOL_REF_P (x
))
904 /* Register plus a small constant offset is valid. */
905 if (GET_CODE (x
) == PLUS
)
907 rtx ofs
= XEXP (x
, 1);
910 /* Discard non-paradoxical subregs. */
911 if (GET_CODE (x
) == SUBREG
912 && (GET_MODE_SIZE (GET_MODE (x
))
913 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
919 && NONSTRICT_REG_OK_FP_BASE_P (x
)
920 && GET_CODE (ofs
) == CONST_INT
)
923 ? STRICT_REG_OK_FOR_BASE_P (x
)
924 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
925 && CONSTANT_ADDRESS_P (ofs
))
930 /* If we're managing explicit relocations, LO_SUM is valid, as
931 are small data symbols. */
932 else if (TARGET_EXPLICIT_RELOCS
)
934 if (small_symbolic_operand (x
, Pmode
))
937 if (GET_CODE (x
) == LO_SUM
)
939 rtx ofs
= XEXP (x
, 1);
942 /* Discard non-paradoxical subregs. */
943 if (GET_CODE (x
) == SUBREG
944 && (GET_MODE_SIZE (GET_MODE (x
))
945 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
948 /* Must have a valid base register. */
951 ? STRICT_REG_OK_FOR_BASE_P (x
)
952 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
955 /* The symbol must be local. */
956 if (local_symbolic_operand (ofs
, Pmode
)
957 || dtp32_symbolic_operand (ofs
, Pmode
)
958 || tp32_symbolic_operand (ofs
, Pmode
))
966 /* Build the SYMBOL_REF for __tls_get_addr. */
968 static GTY(()) rtx tls_get_addr_libfunc
;
971 get_tls_get_addr (void)
973 if (!tls_get_addr_libfunc
)
974 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
975 return tls_get_addr_libfunc
;
978 /* Try machine-dependent ways of modifying an illegitimate address
979 to be legitimate. If we find one, return the new, valid address. */
982 alpha_legitimize_address (rtx x
, rtx scratch
,
983 enum machine_mode mode ATTRIBUTE_UNUSED
)
985 HOST_WIDE_INT addend
;
987 /* If the address is (plus reg const_int) and the CONST_INT is not a
988 valid offset, compute the high part of the constant and add it to
989 the register. Then our address is (plus temp low-part-const). */
990 if (GET_CODE (x
) == PLUS
991 && GET_CODE (XEXP (x
, 0)) == REG
992 && GET_CODE (XEXP (x
, 1)) == CONST_INT
993 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
995 addend
= INTVAL (XEXP (x
, 1));
1000 /* If the address is (const (plus FOO const_int)), find the low-order
1001 part of the CONST_INT. Then load FOO plus any high-order part of the
1002 CONST_INT into a register. Our address is (plus reg low-part-const).
1003 This is done to reduce the number of GOT entries. */
1005 && GET_CODE (x
) == CONST
1006 && GET_CODE (XEXP (x
, 0)) == PLUS
1007 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1009 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1010 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1014 /* If we have a (plus reg const), emit the load as in (2), then add
1015 the two registers, and finally generate (plus reg low-part-const) as
1018 && GET_CODE (x
) == PLUS
1019 && GET_CODE (XEXP (x
, 0)) == REG
1020 && GET_CODE (XEXP (x
, 1)) == CONST
1021 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1022 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1024 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1025 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1026 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1027 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1031 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1032 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1034 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1036 switch (tls_symbolic_operand_type (x
))
1038 case TLS_MODEL_NONE
:
1041 case TLS_MODEL_GLOBAL_DYNAMIC
:
1044 r0
= gen_rtx_REG (Pmode
, 0);
1045 r16
= gen_rtx_REG (Pmode
, 16);
1046 tga
= get_tls_get_addr ();
1047 dest
= gen_reg_rtx (Pmode
);
1048 seq
= GEN_INT (alpha_next_sequence_number
++);
1050 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1051 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1052 insn
= emit_call_insn (insn
);
1053 CONST_OR_PURE_CALL_P (insn
) = 1;
1054 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1056 insn
= get_insns ();
1059 emit_libcall_block (insn
, dest
, r0
, x
);
1062 case TLS_MODEL_LOCAL_DYNAMIC
:
1065 r0
= gen_rtx_REG (Pmode
, 0);
1066 r16
= gen_rtx_REG (Pmode
, 16);
1067 tga
= get_tls_get_addr ();
1068 scratch
= gen_reg_rtx (Pmode
);
1069 seq
= GEN_INT (alpha_next_sequence_number
++);
1071 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1072 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1073 insn
= emit_call_insn (insn
);
1074 CONST_OR_PURE_CALL_P (insn
) = 1;
1075 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1077 insn
= get_insns ();
1080 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1081 UNSPEC_TLSLDM_CALL
);
1082 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1084 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1085 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1087 if (alpha_tls_size
== 64)
1089 dest
= gen_reg_rtx (Pmode
);
1090 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1091 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1094 if (alpha_tls_size
== 32)
1096 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1097 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1098 scratch
= gen_reg_rtx (Pmode
);
1099 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1101 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1103 case TLS_MODEL_INITIAL_EXEC
:
1104 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1105 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1106 tp
= gen_reg_rtx (Pmode
);
1107 scratch
= gen_reg_rtx (Pmode
);
1108 dest
= gen_reg_rtx (Pmode
);
1110 emit_insn (gen_load_tp (tp
));
1111 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1112 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1115 case TLS_MODEL_LOCAL_EXEC
:
1116 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1117 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1118 tp
= gen_reg_rtx (Pmode
);
1120 emit_insn (gen_load_tp (tp
));
1121 if (alpha_tls_size
== 32)
1123 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1124 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1125 tp
= gen_reg_rtx (Pmode
);
1126 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1128 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1134 if (local_symbolic_operand (x
, Pmode
))
1136 if (small_symbolic_operand (x
, Pmode
))
1140 if (!no_new_pseudos
)
1141 scratch
= gen_reg_rtx (Pmode
);
1142 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1143 gen_rtx_HIGH (Pmode
, x
)));
1144 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1153 HOST_WIDE_INT low
, high
;
1155 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1157 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1161 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1162 (no_new_pseudos
? scratch
: NULL_RTX
),
1163 1, OPTAB_LIB_WIDEN
);
1165 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1166 (no_new_pseudos
? scratch
: NULL_RTX
),
1167 1, OPTAB_LIB_WIDEN
);
1169 return plus_constant (x
, low
);
1173 /* Primarily this is required for TLS symbols, but given that our move
1174 patterns *ought* to be able to handle any symbol at any time, we
1175 should never be spilling symbolic operands to the constant pool, ever. */
1178 alpha_cannot_force_const_mem (rtx x
)
1180 enum rtx_code code
= GET_CODE (x
);
1181 return code
== SYMBOL_REF
|| code
== LABEL_REF
|| code
== CONST
;
1184 /* We do not allow indirect calls to be optimized into sibling calls, nor
1185 can we allow a call to a function with a different GP to be optimized
1189 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1191 /* Can't do indirect tail calls, since we don't know if the target
1192 uses the same GP. */
1196 /* Otherwise, we can make a tail call if the target function shares
1198 return decl_has_samegp (decl
);
1202 some_small_symbolic_operand_int (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1206 /* Don't re-split. */
1207 if (GET_CODE (x
) == LO_SUM
)
1210 return small_symbolic_operand (x
, Pmode
) != 0;
1214 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1218 /* Don't re-split. */
1219 if (GET_CODE (x
) == LO_SUM
)
1222 if (small_symbolic_operand (x
, Pmode
))
1224 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1233 split_small_symbolic_operand (rtx x
)
1236 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1240 /* Indicate that INSN cannot be duplicated. This is true for any insn
1241 that we've marked with gpdisp relocs, since those have to stay in
1242 1-1 correspondence with one another.
1244 Technically we could copy them if we could set up a mapping from one
1245 sequence number to another, across the set of insns to be duplicated.
1246 This seems overly complicated and error-prone since interblock motion
1247 from sched-ebb could move one of the pair of insns to a different block.
1249 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1250 then they'll be in a different block from their ldgp. Which could lead
1251 the bb reorder code to think that it would be ok to copy just the block
1252 containing the call and branch to the block containing the ldgp. */
1255 alpha_cannot_copy_insn_p (rtx insn
)
1257 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
1259 if (recog_memoized (insn
) >= 0)
1260 return get_attr_cannot_copy (insn
);
1266 /* Try a machine-dependent way of reloading an illegitimate address
1267 operand. If we find one, push the reload and return the new rtx. */
1270 alpha_legitimize_reload_address (rtx x
,
1271 enum machine_mode mode ATTRIBUTE_UNUSED
,
1272 int opnum
, int type
,
1273 int ind_levels ATTRIBUTE_UNUSED
)
1275 /* We must recognize output that we have already generated ourselves. */
1276 if (GET_CODE (x
) == PLUS
1277 && GET_CODE (XEXP (x
, 0)) == PLUS
1278 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1279 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1280 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1282 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1283 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1288 /* We wish to handle large displacements off a base register by
1289 splitting the addend across an ldah and the mem insn. This
1290 cuts number of extra insns needed from 3 to 1. */
1291 if (GET_CODE (x
) == PLUS
1292 && GET_CODE (XEXP (x
, 0)) == REG
1293 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1294 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1295 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1297 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1298 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1300 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1302 /* Check for 32-bit overflow. */
1303 if (high
+ low
!= val
)
1306 /* Reload the high part into a base reg; leave the low part
1307 in the mem directly. */
1308 x
= gen_rtx_PLUS (GET_MODE (x
),
1309 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1313 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1314 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1322 /* Compute a (partial) cost for rtx X. Return true if the complete
1323 cost has been computed, and false if subexpressions should be
1324 scanned. In either case, *TOTAL contains the cost result. */
1327 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1329 enum machine_mode mode
= GET_MODE (x
);
1330 bool float_mode_p
= FLOAT_MODE_P (mode
);
1331 const struct alpha_rtx_cost_data
*cost_data
;
1334 cost_data
= &alpha_rtx_cost_size
;
1336 cost_data
= &alpha_rtx_cost_data
[alpha_tune
];
1341 /* If this is an 8-bit constant, return zero since it can be used
1342 nearly anywhere with no cost. If it is a valid operand for an
1343 ADD or AND, likewise return 0 if we know it will be used in that
1344 context. Otherwise, return 2 since it might be used there later.
1345 All other constants take at least two insns. */
1346 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
1354 if (x
== CONST0_RTX (mode
))
1356 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
1357 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
1359 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
1362 *total
= COSTS_N_INSNS (2);
1368 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
1369 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
1370 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
1371 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
1372 else if (tls_symbolic_operand_type (x
))
1373 /* Estimate of cost for call_pal rduniq. */
1374 /* ??? How many insns do we emit here? More than one... */
1375 *total
= COSTS_N_INSNS (15);
1377 /* Otherwise we do a load from the GOT. */
1378 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1382 /* This is effectively an add_operand. */
1389 *total
= cost_data
->fp_add
;
1390 else if (GET_CODE (XEXP (x
, 0)) == MULT
1391 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
1393 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
1394 + rtx_cost (XEXP (x
, 1), outer_code
) + COSTS_N_INSNS (1));
1401 *total
= cost_data
->fp_mult
;
1402 else if (mode
== DImode
)
1403 *total
= cost_data
->int_mult_di
;
1405 *total
= cost_data
->int_mult_si
;
1409 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1410 && INTVAL (XEXP (x
, 1)) <= 3)
1412 *total
= COSTS_N_INSNS (1);
1419 *total
= cost_data
->int_shift
;
1424 *total
= cost_data
->fp_add
;
1426 *total
= cost_data
->int_cmov
;
1434 *total
= cost_data
->int_div
;
1435 else if (mode
== SFmode
)
1436 *total
= cost_data
->fp_div_sf
;
1438 *total
= cost_data
->fp_div_df
;
1442 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1448 *total
= COSTS_N_INSNS (1);
1456 *total
= COSTS_N_INSNS (1) + cost_data
->int_cmov
;
1462 case UNSIGNED_FLOAT
:
1465 case FLOAT_TRUNCATE
:
1466 *total
= cost_data
->fp_add
;
1470 if (GET_CODE (XEXP (x
, 0)) == MEM
)
1473 *total
= cost_data
->fp_add
;
1481 /* REF is an alignable memory location. Place an aligned SImode
1482 reference into *PALIGNED_MEM and the number of bits to shift into
1483 *PBITNUM. SCRATCH is a free register for use in reloading out
1484 of range stack slots. */
1487 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
1490 HOST_WIDE_INT offset
= 0;
1492 gcc_assert (GET_CODE (ref
) == MEM
);
1494 if (reload_in_progress
1495 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1497 base
= find_replacement (&XEXP (ref
, 0));
1499 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1502 base
= XEXP (ref
, 0);
1504 if (GET_CODE (base
) == PLUS
)
1505 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1508 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
1510 if (WORDS_BIG_ENDIAN
)
1511 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
1512 + (offset
& 3) * 8));
1514 *pbitnum
= GEN_INT ((offset
& 3) * 8);
1517 /* Similar, but just get the address. Handle the two reload cases.
1518 Add EXTRA_OFFSET to the address we return. */
1521 get_unaligned_address (rtx ref
, int extra_offset
)
1524 HOST_WIDE_INT offset
= 0;
1526 gcc_assert (GET_CODE (ref
) == MEM
);
1528 if (reload_in_progress
1529 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1531 base
= find_replacement (&XEXP (ref
, 0));
1533 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1536 base
= XEXP (ref
, 0);
1538 if (GET_CODE (base
) == PLUS
)
1539 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1541 return plus_constant (base
, offset
+ extra_offset
);
1544 /* On the Alpha, all (non-symbolic) constants except zero go into
1545 a floating-point register via memory. Note that we cannot
1546 return anything that is not a subset of CLASS, and that some
1547 symbolic constants cannot be dropped to memory. */
1550 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
1552 /* Zero is present in any register class. */
1553 if (x
== CONST0_RTX (GET_MODE (x
)))
1556 /* These sorts of constants we can easily drop to memory. */
1557 if (GET_CODE (x
) == CONST_INT
1558 || GET_CODE (x
) == CONST_DOUBLE
1559 || GET_CODE (x
) == CONST_VECTOR
)
1561 if (class == FLOAT_REGS
)
1563 if (class == ALL_REGS
)
1564 return GENERAL_REGS
;
1568 /* All other kinds of constants should not (and in the case of HIGH
1569 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1570 secondary reload. */
1572 return (class == ALL_REGS
? GENERAL_REGS
: class);
1577 /* Loading and storing HImode or QImode values to and from memory
1578 usually requires a scratch register. The exceptions are loading
1579 QImode and HImode from an aligned address to a general register
1580 unless byte instructions are permitted.
1582 We also cannot load an unaligned address or a paradoxical SUBREG
1583 into an FP register.
1585 We also cannot do integral arithmetic into FP regs, as might result
1586 from register elimination into a DImode fp register. */
1589 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
1592 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
1594 if (GET_CODE (x
) == MEM
1595 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
1596 || (GET_CODE (x
) == SUBREG
1597 && (GET_CODE (SUBREG_REG (x
)) == MEM
1598 || (GET_CODE (SUBREG_REG (x
)) == REG
1599 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
1601 if (!in
|| !aligned_memory_operand(x
, mode
))
1602 return GENERAL_REGS
;
1606 if (class == FLOAT_REGS
)
1608 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
1609 return GENERAL_REGS
;
1611 if (GET_CODE (x
) == SUBREG
1612 && (GET_MODE_SIZE (GET_MODE (x
))
1613 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1614 return GENERAL_REGS
;
1616 if (in
&& INTEGRAL_MODE_P (mode
)
1617 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
1618 return GENERAL_REGS
;
1624 /* Subfunction of the following function. Update the flags of any MEM
1625 found in part of X. */
1628 alpha_set_memflags_1 (rtx
*xp
, void *data
)
1630 rtx x
= *xp
, orig
= (rtx
) data
;
1632 if (GET_CODE (x
) != MEM
)
1635 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (orig
);
1636 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (orig
);
1637 MEM_SCALAR_P (x
) = MEM_SCALAR_P (orig
);
1638 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (orig
);
1639 MEM_READONLY_P (x
) = MEM_READONLY_P (orig
);
1641 /* Sadly, we cannot use alias sets because the extra aliasing
1642 produced by the AND interferes. Given that two-byte quantities
1643 are the only thing we would be able to differentiate anyway,
1644 there does not seem to be any point in convoluting the early
1645 out of the alias check. */
1650 /* Given INSN, which is an INSN list or the PATTERN of a single insn
1651 generated to perform a memory operation, look for any MEMs in either
1652 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1653 volatile flags from REF into each of the MEMs found. If REF is not
1654 a MEM, don't do anything. */
1657 alpha_set_memflags (rtx insn
, rtx ref
)
1661 if (GET_CODE (ref
) != MEM
)
1664 /* This is only called from alpha.md, after having had something
1665 generated from one of the insn patterns. So if everything is
1666 zero, the pattern is already up-to-date. */
1667 if (!MEM_VOLATILE_P (ref
)
1668 && !MEM_IN_STRUCT_P (ref
)
1669 && !MEM_SCALAR_P (ref
)
1670 && !MEM_NOTRAP_P (ref
)
1671 && !MEM_READONLY_P (ref
))
1675 base_ptr
= &PATTERN (insn
);
1678 for_each_rtx (base_ptr
, alpha_set_memflags_1
, (void *) ref
);
1681 static rtx
alpha_emit_set_const (rtx
, enum machine_mode
, HOST_WIDE_INT
,
1684 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1685 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1686 and return pc_rtx if successful. */
1689 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
1690 HOST_WIDE_INT c
, int n
, bool no_output
)
1694 /* Use a pseudo if highly optimizing and still generating RTL. */
1696 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
1699 /* If this is a sign-extended 32-bit constant, we can do this in at most
1700 three insns, so do it if we have enough insns left. We always have
1701 a sign-extended 32-bit constant when compiling on a narrow machine. */
1703 if (HOST_BITS_PER_WIDE_INT
!= 64
1704 || c
>> 31 == -1 || c
>> 31 == 0)
1706 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1707 HOST_WIDE_INT tmp1
= c
- low
;
1708 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
1709 HOST_WIDE_INT extra
= 0;
1711 /* If HIGH will be interpreted as negative but the constant is
1712 positive, we must adjust it to do two ldha insns. */
1714 if ((high
& 0x8000) != 0 && c
>= 0)
1718 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1721 if (c
== low
|| (low
== 0 && extra
== 0))
1723 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1724 but that meant that we can't handle INT_MIN on 32-bit machines
1725 (like NT/Alpha), because we recurse indefinitely through
1726 emit_move_insn to gen_movdi. So instead, since we know exactly
1727 what we want, create it explicitly. */
1732 target
= gen_reg_rtx (mode
);
1733 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
1736 else if (n
>= 2 + (extra
!= 0))
1742 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
1746 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
1749 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1750 This means that if we go through expand_binop, we'll try to
1751 generate extensions, etc, which will require new pseudos, which
1752 will fail during some split phases. The SImode add patterns
1753 still exist, but are not named. So build the insns by hand. */
1758 subtarget
= gen_reg_rtx (mode
);
1759 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
1760 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
1766 target
= gen_reg_rtx (mode
);
1767 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
1768 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
1774 /* If we couldn't do it that way, try some other methods. But if we have
1775 no instructions left, don't bother. Likewise, if this is SImode and
1776 we can't make pseudos, we can't do anything since the expand_binop
1777 and expand_unop calls will widen and try to make pseudos. */
1779 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
1782 /* Next, see if we can load a related constant and then shift and possibly
1783 negate it to get the constant we want. Try this once each increasing
1784 numbers of insns. */
1786 for (i
= 1; i
< n
; i
++)
1788 /* First, see if minus some low bits, we've an easy load of
1791 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
1794 temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
, no_output
);
1799 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
1800 target
, 0, OPTAB_WIDEN
);
1804 /* Next try complementing. */
1805 temp
= alpha_emit_set_const (subtarget
, mode
, ~c
, i
, no_output
);
1810 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
1813 /* Next try to form a constant and do a left shift. We can do this
1814 if some low-order bits are zero; the exact_log2 call below tells
1815 us that information. The bits we are shifting out could be any
1816 value, but here we'll just try the 0- and sign-extended forms of
1817 the constant. To try to increase the chance of having the same
1818 constant in more than one insn, start at the highest number of
1819 bits to shift, but try all possibilities in case a ZAPNOT will
1822 bits
= exact_log2 (c
& -c
);
1824 for (; bits
> 0; bits
--)
1827 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1830 new = (unsigned HOST_WIDE_INT
)c
>> bits
;
1831 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1838 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
1839 target
, 0, OPTAB_WIDEN
);
1843 /* Now try high-order zero bits. Here we try the shifted-in bits as
1844 all zero and all ones. Be careful to avoid shifting outside the
1845 mode and to avoid shifting outside the host wide int size. */
1846 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1847 confuse the recursive call and set all of the high 32 bits. */
1849 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1850 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64));
1852 for (; bits
> 0; bits
--)
1855 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1858 new = (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1859 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1866 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
1867 target
, 1, OPTAB_WIDEN
);
1871 /* Now try high-order 1 bits. We get that with a sign-extension.
1872 But one bit isn't enough here. Be careful to avoid shifting outside
1873 the mode and to avoid shifting outside the host wide int size. */
1875 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1876 - floor_log2 (~ c
) - 2);
1878 for (; bits
> 0; bits
--)
1881 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1884 new = (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1885 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1892 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
1893 target
, 0, OPTAB_WIDEN
);
1898 #if HOST_BITS_PER_WIDE_INT == 64
1899 /* Finally, see if can load a value into the target that is the same as the
1900 constant except that all bytes that are 0 are changed to be 0xff. If we
1901 can, then we can do a ZAPNOT to obtain the desired constant. */
1904 for (i
= 0; i
< 64; i
+= 8)
1905 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
1906 new |= (HOST_WIDE_INT
) 0xff << i
;
1908 /* We are only called for SImode and DImode. If this is SImode, ensure that
1909 we are sign extended to a full word. */
1912 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
1916 temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1, no_output
);
1921 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
1922 target
, 0, OPTAB_WIDEN
);
1930 /* Try to output insns to set TARGET equal to the constant C if it can be
1931 done in less than N insns. Do all computations in MODE. Returns the place
1932 where the output has been placed if it can be done and the insns have been
1933 emitted. If it would take more than N insns, zero is returned and no
1934 insns and emitted. */
1937 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
1938 HOST_WIDE_INT c
, int n
, bool no_output
)
1940 enum machine_mode orig_mode
= mode
;
1941 rtx orig_target
= target
;
1945 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1946 can't load this constant in one insn, do this in DImode. */
1947 if (no_new_pseudos
&& mode
== SImode
1948 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
)
1950 result
= alpha_emit_set_const_1 (target
, mode
, c
, 1, no_output
);
1954 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1957 else if (mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
)
1959 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1963 /* Try 1 insn, then 2, then up to N. */
1964 for (i
= 1; i
<= n
; i
++)
1966 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
, no_output
);
1974 insn
= get_last_insn ();
1975 set
= single_set (insn
);
1976 if (! CONSTANT_P (SET_SRC (set
)))
1977 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
1982 /* Allow for the case where we changed the mode of TARGET. */
1985 if (result
== target
)
1986 result
= orig_target
;
1987 else if (mode
!= orig_mode
)
1988 result
= gen_lowpart (orig_mode
, result
);
1994 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1995 fall back to a straight forward decomposition. We do this to avoid
1996 exponential run times encountered when looking for longer sequences
1997 with alpha_emit_set_const. */
2000 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2002 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2004 /* Decompose the entire word */
2005 #if HOST_BITS_PER_WIDE_INT >= 64
2006 gcc_assert (c2
== -(c1
< 0));
2007 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2009 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2010 c1
= (c1
- d2
) >> 32;
2011 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2013 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2014 gcc_assert (c1
== d4
);
2016 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2018 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2019 gcc_assert (c1
== d2
);
2021 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2023 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2024 gcc_assert (c2
== d4
);
2027 /* Construct the high word */
2030 emit_move_insn (target
, GEN_INT (d4
));
2032 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2035 emit_move_insn (target
, GEN_INT (d3
));
2037 /* Shift it into place */
2038 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2040 /* Add in the low bits. */
2042 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2044 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2049 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
2053 alpha_extract_integer (rtx x
, HOST_WIDE_INT
*p0
, HOST_WIDE_INT
*p1
)
2055 HOST_WIDE_INT i0
, i1
;
2057 if (GET_CODE (x
) == CONST_VECTOR
)
2058 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
2061 if (GET_CODE (x
) == CONST_INT
)
2066 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2068 i0
= CONST_DOUBLE_LOW (x
);
2073 i0
= CONST_DOUBLE_LOW (x
);
2074 i1
= CONST_DOUBLE_HIGH (x
);
2081 /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
2082 are willing to load the value into a register via a move pattern.
2083 Normally this is all symbolic constants, integral constants that
2084 take three or fewer instructions, and floating-point zero. */
2087 alpha_legitimate_constant_p (rtx x
)
2089 enum machine_mode mode
= GET_MODE (x
);
2090 HOST_WIDE_INT i0
, i1
;
2092 switch (GET_CODE (x
))
2101 if (x
== CONST0_RTX (mode
))
2103 if (FLOAT_MODE_P (mode
))
2108 if (x
== CONST0_RTX (mode
))
2110 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2112 if (GET_MODE_SIZE (mode
) != 8)
2118 if (TARGET_BUILD_CONSTANTS
)
2120 alpha_extract_integer (x
, &i0
, &i1
);
2121 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== (-i0
< 0))
2122 return alpha_emit_set_const_1 (x
, mode
, i0
, 3, true) != NULL
;
2130 /* Operand 1 is known to be a constant, and should require more than one
2131 instruction to load. Emit that multi-part load. */
2134 alpha_split_const_mov (enum machine_mode mode
, rtx
*operands
)
2136 HOST_WIDE_INT i0
, i1
;
2137 rtx temp
= NULL_RTX
;
2139 alpha_extract_integer (operands
[1], &i0
, &i1
);
2141 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2142 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3, false);
2144 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2145 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2149 if (!rtx_equal_p (operands
[0], temp
))
2150 emit_move_insn (operands
[0], temp
);
2157 /* Expand a move instruction; return true if all work is done.
2158 We don't handle non-bwx subword loads here. */
2161 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2163 /* If the output is not a register, the input must be. */
2164 if (GET_CODE (operands
[0]) == MEM
2165 && ! reg_or_0_operand (operands
[1], mode
))
2166 operands
[1] = force_reg (mode
, operands
[1]);
2168 /* Allow legitimize_address to perform some simplifications. */
2169 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2173 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2176 if (tmp
== operands
[0])
2183 /* Early out for non-constants and valid constants. */
2184 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2187 /* Split large integers. */
2188 if (GET_CODE (operands
[1]) == CONST_INT
2189 || GET_CODE (operands
[1]) == CONST_DOUBLE
2190 || GET_CODE (operands
[1]) == CONST_VECTOR
)
2192 if (alpha_split_const_mov (mode
, operands
))
2196 /* Otherwise we've nothing left but to drop the thing to memory. */
2197 operands
[1] = force_const_mem (mode
, operands
[1]);
2198 if (reload_in_progress
)
2200 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2201 operands
[1] = copy_rtx (operands
[1]);
2202 XEXP (operands
[1], 0) = operands
[0];
2205 operands
[1] = validize_mem (operands
[1]);
2209 /* Expand a non-bwx QImode or HImode move instruction;
2210 return true if all work is done. */
2213 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2215 /* If the output is not a register, the input must be. */
2216 if (GET_CODE (operands
[0]) == MEM
)
2217 operands
[1] = force_reg (mode
, operands
[1]);
2219 /* Handle four memory cases, unaligned and aligned for either the input
2220 or the output. The only case where we can be called during reload is
2221 for aligned loads; all other cases require temporaries. */
2223 if (GET_CODE (operands
[1]) == MEM
2224 || (GET_CODE (operands
[1]) == SUBREG
2225 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2226 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2227 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2228 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2229 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2230 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2232 if (aligned_memory_operand (operands
[1], mode
))
2234 if (reload_in_progress
)
2236 emit_insn ((mode
== QImode
2237 ? gen_reload_inqi_help
2238 : gen_reload_inhi_help
)
2239 (operands
[0], operands
[1],
2240 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2244 rtx aligned_mem
, bitnum
;
2245 rtx scratch
= gen_reg_rtx (SImode
);
2249 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2251 subtarget
= operands
[0];
2252 if (GET_CODE (subtarget
) == REG
)
2253 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2255 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2257 emit_insn ((mode
== QImode
2258 ? gen_aligned_loadqi
2259 : gen_aligned_loadhi
)
2260 (subtarget
, aligned_mem
, bitnum
, scratch
));
2263 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2268 /* Don't pass these as parameters since that makes the generated
2269 code depend on parameter evaluation order which will cause
2270 bootstrap failures. */
2272 rtx temp1
, temp2
, seq
, subtarget
;
2275 temp1
= gen_reg_rtx (DImode
);
2276 temp2
= gen_reg_rtx (DImode
);
2278 subtarget
= operands
[0];
2279 if (GET_CODE (subtarget
) == REG
)
2280 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2282 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2284 seq
= ((mode
== QImode
2285 ? gen_unaligned_loadqi
2286 : gen_unaligned_loadhi
)
2287 (subtarget
, get_unaligned_address (operands
[1], 0),
2289 alpha_set_memflags (seq
, operands
[1]);
2293 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2298 if (GET_CODE (operands
[0]) == MEM
2299 || (GET_CODE (operands
[0]) == SUBREG
2300 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2301 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2302 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2303 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2304 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2305 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2307 if (aligned_memory_operand (operands
[0], mode
))
2309 rtx aligned_mem
, bitnum
;
2310 rtx temp1
= gen_reg_rtx (SImode
);
2311 rtx temp2
= gen_reg_rtx (SImode
);
2313 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2315 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2320 rtx temp1
= gen_reg_rtx (DImode
);
2321 rtx temp2
= gen_reg_rtx (DImode
);
2322 rtx temp3
= gen_reg_rtx (DImode
);
2323 rtx seq
= ((mode
== QImode
2324 ? gen_unaligned_storeqi
2325 : gen_unaligned_storehi
)
2326 (get_unaligned_address (operands
[0], 0),
2327 operands
[1], temp1
, temp2
, temp3
));
2329 alpha_set_memflags (seq
, operands
[0]);
2338 /* Implement the movmisalign patterns. One of the operands is a memory
2339 that is not naturally aligned. Emit instructions to load it. */
2342 alpha_expand_movmisalign (enum machine_mode mode
, rtx
*operands
)
2344 /* Honor misaligned loads, for those we promised to do so. */
2345 if (MEM_P (operands
[1]))
2349 if (register_operand (operands
[0], mode
))
2352 tmp
= gen_reg_rtx (mode
);
2354 alpha_expand_unaligned_load (tmp
, operands
[1], 8, 0, 0);
2355 if (tmp
!= operands
[0])
2356 emit_move_insn (operands
[0], tmp
);
2358 else if (MEM_P (operands
[0]))
2360 if (!reg_or_0_operand (operands
[1], mode
))
2361 operands
[1] = force_reg (mode
, operands
[1]);
2362 alpha_expand_unaligned_store (operands
[0], operands
[1], 8, 0);
2368 /* Generate an unsigned DImode to FP conversion. This is the same code
2369 optabs would emit if we didn't have TFmode patterns.
2371 For SFmode, this is the only construction I've found that can pass
2372 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2373 intermediates will work, because you'll get intermediate rounding
2374 that ruins the end result. Some of this could be fixed by turning
2375 on round-to-positive-infinity, but that requires diddling the fpsr,
2376 which kills performance. I tried turning this around and converting
2377 to a negative number, so that I could turn on /m, but either I did
2378 it wrong or there's something else cause I wound up with the exact
2379 same single-bit error. There is a branch-less form of this same code:
2390 fcmoveq $f10,$f11,$f0
2392 I'm not using it because it's the same number of instructions as
2393 this branch-full form, and it has more serialized long latency
2394 instructions on the critical path.
2396 For DFmode, we can avoid rounding errors by breaking up the word
2397 into two pieces, converting them separately, and adding them back:
2399 LC0: .long 0,0x5f800000
2404 cpyse $f11,$f31,$f10
2405 cpyse $f31,$f11,$f11
2413 This doesn't seem to be a clear-cut win over the optabs form.
2414 It probably all depends on the distribution of numbers being
2415 converted -- in the optabs form, all but high-bit-set has a
2416 much lower minimum execution time. */
2419 alpha_emit_floatuns (rtx operands
[2])
2421 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2422 enum machine_mode mode
;
2425 in
= force_reg (DImode
, operands
[1]);
2426 mode
= GET_MODE (out
);
2427 neglab
= gen_label_rtx ();
2428 donelab
= gen_label_rtx ();
2429 i0
= gen_reg_rtx (DImode
);
2430 i1
= gen_reg_rtx (DImode
);
2431 f0
= gen_reg_rtx (mode
);
2433 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2435 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2436 emit_jump_insn (gen_jump (donelab
));
2439 emit_label (neglab
);
2441 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2442 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2443 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2444 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2445 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2447 emit_label (donelab
);
2450 /* Generate the comparison for a conditional branch. */
2453 alpha_emit_conditional_branch (enum rtx_code code
)
2455 enum rtx_code cmp_code
, branch_code
;
2456 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
2457 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2460 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
2462 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2464 alpha_compare
.fp_p
= 0;
2467 /* The general case: fold the comparison code to the types of compares
2468 that we have, choosing the branch as necessary. */
2471 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2473 /* We have these compares: */
2474 cmp_code
= code
, branch_code
= NE
;
2479 /* These must be reversed. */
2480 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2483 case GE
: case GT
: case GEU
: case GTU
:
2484 /* For FP, we swap them, for INT, we reverse them. */
2485 if (alpha_compare
.fp_p
)
2487 cmp_code
= swap_condition (code
);
2489 tem
= op0
, op0
= op1
, op1
= tem
;
2493 cmp_code
= reverse_condition (code
);
2502 if (alpha_compare
.fp_p
)
2505 if (flag_unsafe_math_optimizations
)
2507 /* When we are not as concerned about non-finite values, and we
2508 are comparing against zero, we can branch directly. */
2509 if (op1
== CONST0_RTX (DFmode
))
2510 cmp_code
= UNKNOWN
, branch_code
= code
;
2511 else if (op0
== CONST0_RTX (DFmode
))
2513 /* Undo the swap we probably did just above. */
2514 tem
= op0
, op0
= op1
, op1
= tem
;
2515 branch_code
= swap_condition (cmp_code
);
2521 /* ??? We mark the branch mode to be CCmode to prevent the
2522 compare and branch from being combined, since the compare
2523 insn follows IEEE rules that the branch does not. */
2524 branch_mode
= CCmode
;
2531 /* The following optimizations are only for signed compares. */
2532 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2534 /* Whee. Compare and branch against 0 directly. */
2535 if (op1
== const0_rtx
)
2536 cmp_code
= UNKNOWN
, branch_code
= code
;
2538 /* If the constants doesn't fit into an immediate, but can
2539 be generated by lda/ldah, we adjust the argument and
2540 compare against zero, so we can use beq/bne directly. */
2541 /* ??? Don't do this when comparing against symbols, otherwise
2542 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2543 be declared false out of hand (at least for non-weak). */
2544 else if (GET_CODE (op1
) == CONST_INT
2545 && (code
== EQ
|| code
== NE
)
2546 && !(symbolic_operand (op0
, VOIDmode
)
2547 || (GET_CODE (op0
) == REG
&& REG_POINTER (op0
))))
2549 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
2551 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
2552 && (CONST_OK_FOR_LETTER_P (n
, 'K')
2553 || CONST_OK_FOR_LETTER_P (n
, 'L')))
2555 cmp_code
= PLUS
, branch_code
= code
;
2561 if (!reg_or_0_operand (op0
, DImode
))
2562 op0
= force_reg (DImode
, op0
);
2563 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2564 op1
= force_reg (DImode
, op1
);
2567 /* Emit an initial compare instruction, if necessary. */
2569 if (cmp_code
!= UNKNOWN
)
2571 tem
= gen_reg_rtx (cmp_mode
);
2572 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2575 /* Zero the operands. */
2576 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2578 /* Return the branch comparison. */
2579 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
2582 /* Certain simplifications can be done to make invalid setcc operations
2583 valid. Return the final comparison, or NULL if we can't work. */
2586 alpha_emit_setcc (enum rtx_code code
)
2588 enum rtx_code cmp_code
;
2589 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2590 int fp_p
= alpha_compare
.fp_p
;
2593 /* Zero the operands. */
2594 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2596 if (fp_p
&& GET_MODE (op0
) == TFmode
)
2598 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2603 if (fp_p
&& !TARGET_FIX
)
2606 /* The general case: fold the comparison code to the types of compares
2607 that we have, choosing the branch as necessary. */
2612 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2614 /* We have these compares. */
2616 cmp_code
= code
, code
= NE
;
2620 if (!fp_p
&& op1
== const0_rtx
)
2625 cmp_code
= reverse_condition (code
);
2629 case GE
: case GT
: case GEU
: case GTU
:
2630 /* These normally need swapping, but for integer zero we have
2631 special patterns that recognize swapped operands. */
2632 if (!fp_p
&& op1
== const0_rtx
)
2634 code
= swap_condition (code
);
2636 cmp_code
= code
, code
= NE
;
2637 tmp
= op0
, op0
= op1
, op1
= tmp
;
2646 if (!register_operand (op0
, DImode
))
2647 op0
= force_reg (DImode
, op0
);
2648 if (!reg_or_8bit_operand (op1
, DImode
))
2649 op1
= force_reg (DImode
, op1
);
2652 /* Emit an initial compare instruction, if necessary. */
2653 if (cmp_code
!= UNKNOWN
)
2655 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
2657 tmp
= gen_reg_rtx (mode
);
2658 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
2659 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
2661 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
2665 /* Return the setcc comparison. */
2666 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
2670 /* Rewrite a comparison against zero CMP of the form
2671 (CODE (cc0) (const_int 0)) so it can be written validly in
2672 a conditional move (if_then_else CMP ...).
2673 If both of the operands that set cc0 are nonzero we must emit
2674 an insn to perform the compare (it can't be done within
2675 the conditional move). */
2678 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
2680 enum rtx_code code
= GET_CODE (cmp
);
2681 enum rtx_code cmov_code
= NE
;
2682 rtx op0
= alpha_compare
.op0
;
2683 rtx op1
= alpha_compare
.op1
;
2684 int fp_p
= alpha_compare
.fp_p
;
2685 enum machine_mode cmp_mode
2686 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
2687 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
2688 enum machine_mode cmov_mode
= VOIDmode
;
2689 int local_fast_math
= flag_unsafe_math_optimizations
;
2692 /* Zero the operands. */
2693 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2695 if (fp_p
!= FLOAT_MODE_P (mode
))
2697 enum rtx_code cmp_code
;
2702 /* If we have fp<->int register move instructions, do a cmov by
2703 performing the comparison in fp registers, and move the
2704 zero/nonzero value to integer registers, where we can then
2705 use a normal cmov, or vice-versa. */
2709 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2710 /* We have these compares. */
2711 cmp_code
= code
, code
= NE
;
2715 /* This must be reversed. */
2716 cmp_code
= EQ
, code
= EQ
;
2719 case GE
: case GT
: case GEU
: case GTU
:
2720 /* These normally need swapping, but for integer zero we have
2721 special patterns that recognize swapped operands. */
2722 if (!fp_p
&& op1
== const0_rtx
)
2723 cmp_code
= code
, code
= NE
;
2726 cmp_code
= swap_condition (code
);
2728 tem
= op0
, op0
= op1
, op1
= tem
;
2736 tem
= gen_reg_rtx (cmp_op_mode
);
2737 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2738 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
2741 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
2742 op0
= gen_lowpart (cmp_op_mode
, tem
);
2743 op1
= CONST0_RTX (cmp_op_mode
);
2745 local_fast_math
= 1;
2748 /* We may be able to use a conditional move directly.
2749 This avoids emitting spurious compares. */
2750 if (signed_comparison_operator (cmp
, VOIDmode
)
2751 && (!fp_p
|| local_fast_math
)
2752 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
2753 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2755 /* We can't put the comparison inside the conditional move;
2756 emit a compare instruction and put that inside the
2757 conditional move. Make sure we emit only comparisons we have;
2758 swap or reverse as necessary. */
2765 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2766 /* We have these compares: */
2770 /* This must be reversed. */
2771 code
= reverse_condition (code
);
2775 case GE
: case GT
: case GEU
: case GTU
:
2776 /* These must be swapped. */
2777 if (op1
!= CONST0_RTX (cmp_mode
))
2779 code
= swap_condition (code
);
2780 tem
= op0
, op0
= op1
, op1
= tem
;
2790 if (!reg_or_0_operand (op0
, DImode
))
2791 op0
= force_reg (DImode
, op0
);
2792 if (!reg_or_8bit_operand (op1
, DImode
))
2793 op1
= force_reg (DImode
, op1
);
2796 /* ??? We mark the branch mode to be CCmode to prevent the compare
2797 and cmov from being combined, since the compare insn follows IEEE
2798 rules that the cmov does not. */
2799 if (fp_p
&& !local_fast_math
)
2802 tem
= gen_reg_rtx (cmp_op_mode
);
2803 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
2804 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
2807 /* Simplify a conditional move of two constants into a setcc with
2808 arithmetic. This is done with a splitter since combine would
2809 just undo the work if done during code generation. It also catches
2810 cases we wouldn't have before cse. */
2813 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
2814 rtx t_rtx
, rtx f_rtx
)
2816 HOST_WIDE_INT t
, f
, diff
;
2817 enum machine_mode mode
;
2818 rtx target
, subtarget
, tmp
;
2820 mode
= GET_MODE (dest
);
2825 if (((code
== NE
|| code
== EQ
) && diff
< 0)
2826 || (code
== GE
|| code
== GT
))
2828 code
= reverse_condition (code
);
2829 diff
= t
, t
= f
, f
= diff
;
2833 subtarget
= target
= dest
;
2836 target
= gen_lowpart (DImode
, dest
);
2837 if (! no_new_pseudos
)
2838 subtarget
= gen_reg_rtx (DImode
);
2842 /* Below, we must be careful to use copy_rtx on target and subtarget
2843 in intermediate insns, as they may be a subreg rtx, which may not
2846 if (f
== 0 && exact_log2 (diff
) > 0
2847 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2848 viable over a longer latency cmove. On EV5, the E0 slot is a
2849 scarce resource, and on EV4 shift has the same latency as a cmove. */
2850 && (diff
<= 8 || alpha_tune
== PROCESSOR_EV6
))
2852 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2853 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2855 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
2856 GEN_INT (exact_log2 (t
)));
2857 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2859 else if (f
== 0 && t
== -1)
2861 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2862 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2864 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
2866 else if (diff
== 1 || diff
== 4 || diff
== 8)
2870 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2871 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2874 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
2877 add_op
= GEN_INT (f
);
2878 if (sext_add_operand (add_op
, mode
))
2880 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
2882 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
2883 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2895 /* Look up the function X_floating library function name for the
2898 struct xfloating_op
GTY(())
2900 const enum rtx_code code
;
2901 const char *const GTY((skip
)) osf_func
;
2902 const char *const GTY((skip
)) vms_func
;
2906 static GTY(()) struct xfloating_op xfloating_ops
[] =
2908 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
2909 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
2910 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
2911 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
2912 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
2913 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
2914 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
2915 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
2916 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
2917 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
2918 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2919 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
2920 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2921 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2922 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2925 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
2927 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2928 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2932 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
2934 struct xfloating_op
*ops
= xfloating_ops
;
2935 long n
= ARRAY_SIZE (xfloating_ops
);
2938 gcc_assert (TARGET_HAS_XFLOATING_LIBS
);
2940 /* How irritating. Nothing to key off for the main table. */
2941 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
2944 n
= ARRAY_SIZE (vax_cvt_ops
);
2947 for (i
= 0; i
< n
; ++i
, ++ops
)
2948 if (ops
->code
== code
)
2950 rtx func
= ops
->libcall
;
2953 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
2954 ? ops
->vms_func
: ops
->osf_func
);
2955 ops
->libcall
= func
;
2963 /* Most X_floating operations take the rounding mode as an argument.
2964 Compute that here. */
2967 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
2968 enum alpha_fp_rounding_mode round
)
2974 case ALPHA_FPRM_NORM
:
2977 case ALPHA_FPRM_MINF
:
2980 case ALPHA_FPRM_CHOP
:
2983 case ALPHA_FPRM_DYN
:
2989 /* XXX For reference, round to +inf is mode = 3. */
2992 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
2998 /* Emit an X_floating library function call.
3000 Note that these functions do not follow normal calling conventions:
3001 TFmode arguments are passed in two integer registers (as opposed to
3002 indirect); TFmode return values appear in R16+R17.
3004 FUNC is the function to call.
3005 TARGET is where the output belongs.
3006 OPERANDS are the inputs.
3007 NOPERANDS is the count of inputs.
3008 EQUIV is the expression equivalent for the function.
3012 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
3013 int noperands
, rtx equiv
)
3015 rtx usage
= NULL_RTX
, tmp
, reg
;
3020 for (i
= 0; i
< noperands
; ++i
)
3022 switch (GET_MODE (operands
[i
]))
3025 reg
= gen_rtx_REG (TFmode
, regno
);
3030 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3035 gcc_assert (GET_CODE (operands
[i
]) == CONST_INT
);
3038 reg
= gen_rtx_REG (DImode
, regno
);
3046 emit_move_insn (reg
, operands
[i
]);
3047 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3050 switch (GET_MODE (target
))
3053 reg
= gen_rtx_REG (TFmode
, 16);
3056 reg
= gen_rtx_REG (DFmode
, 32);
3059 reg
= gen_rtx_REG (DImode
, 0);
3065 tmp
= gen_rtx_MEM (QImode
, func
);
3066 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3067 const0_rtx
, const0_rtx
));
3068 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3069 CONST_OR_PURE_CALL_P (tmp
) = 1;
3074 emit_libcall_block (tmp
, target
, reg
, equiv
);
3077 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3080 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3084 rtx out_operands
[3];
3086 func
= alpha_lookup_xfloating_lib_func (code
);
3087 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3089 out_operands
[0] = operands
[1];
3090 out_operands
[1] = operands
[2];
3091 out_operands
[2] = GEN_INT (mode
);
3092 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3093 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3097 /* Emit an X_floating library function call for a comparison. */
3100 alpha_emit_xfloating_compare (enum rtx_code
*pcode
, rtx op0
, rtx op1
)
3102 enum rtx_code cmp_code
, res_code
;
3103 rtx func
, out
, operands
[2];
3105 /* X_floating library comparison functions return
3109 Convert the compare against the raw return value. */
3137 func
= alpha_lookup_xfloating_lib_func (cmp_code
);
3141 out
= gen_reg_rtx (DImode
);
3143 /* ??? Strange mode for equiv because what's actually returned
3144 is -1,0,1, not a proper boolean value. */
3145 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3146 gen_rtx_fmt_ee (cmp_code
, CCmode
, op0
, op1
));
3151 /* Emit an X_floating library function call for a conversion. */
3154 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3156 int noperands
= 1, mode
;
3157 rtx out_operands
[2];
3159 enum rtx_code code
= orig_code
;
3161 if (code
== UNSIGNED_FIX
)
3164 func
= alpha_lookup_xfloating_lib_func (code
);
3166 out_operands
[0] = operands
[1];
3171 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3172 out_operands
[1] = GEN_INT (mode
);
3175 case FLOAT_TRUNCATE
:
3176 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3177 out_operands
[1] = GEN_INT (mode
);
3184 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3185 gen_rtx_fmt_e (orig_code
,
3186 GET_MODE (operands
[0]),
3190 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3191 OP[0] into OP[0,1]. Naturally, output operand ordering is
3195 alpha_split_tfmode_pair (rtx operands
[4])
3197 switch (GET_CODE (operands
[1]))
3200 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3201 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3205 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3206 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3210 gcc_assert (operands
[1] == CONST0_RTX (TFmode
));
3211 operands
[2] = operands
[3] = const0_rtx
;
3218 switch (GET_CODE (operands
[0]))
3221 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3222 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3226 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3227 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3235 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3236 op2 is a register containing the sign bit, operation is the
3237 logical operation to be performed. */
3240 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3242 rtx high_bit
= operands
[2];
3246 alpha_split_tfmode_pair (operands
);
3248 /* Detect three flavors of operand overlap. */
3250 if (rtx_equal_p (operands
[0], operands
[2]))
3252 else if (rtx_equal_p (operands
[1], operands
[2]))
3254 if (rtx_equal_p (operands
[0], high_bit
))
3261 emit_move_insn (operands
[0], operands
[2]);
3263 /* ??? If the destination overlaps both source tf and high_bit, then
3264 assume source tf is dead in its entirety and use the other half
3265 for a scratch register. Otherwise "scratch" is just the proper
3266 destination register. */
3267 scratch
= operands
[move
< 2 ? 1 : 3];
3269 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3273 emit_move_insn (operands
[0], operands
[2]);
3275 emit_move_insn (operands
[1], scratch
);
3279 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3283 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3284 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3285 lda r3,X(r11) lda r3,X+2(r11)
3286 extwl r1,r3,r1 extql r1,r3,r1
3287 extwh r2,r3,r2 extqh r2,r3,r2
3288 or r1.r2.r1 or r1,r2,r1
3291 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3292 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3293 lda r3,X(r11) lda r3,X(r11)
3294 extll r1,r3,r1 extll r1,r3,r1
3295 extlh r2,r3,r2 extlh r2,r3,r2
3296 or r1.r2.r1 addl r1,r2,r1
3298 quad: ldq_u r1,X(r11)
3307 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3308 HOST_WIDE_INT ofs
, int sign
)
3310 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3311 enum machine_mode mode
;
3313 if (TARGET_BWX
&& size
== 2)
3315 meml
= adjust_address (mem
, QImode
, ofs
);
3316 memh
= adjust_address (mem
, QImode
, ofs
+1);
3317 if (BYTES_BIG_ENDIAN
)
3318 tmp
= meml
, meml
= memh
, memh
= tmp
;
3319 extl
= gen_reg_rtx (DImode
);
3320 exth
= gen_reg_rtx (DImode
);
3321 emit_insn (gen_zero_extendqidi2 (extl
, meml
));
3322 emit_insn (gen_zero_extendqidi2 (exth
, memh
));
3323 exth
= expand_simple_binop (DImode
, ASHIFT
, exth
, GEN_INT (8),
3324 NULL
, 1, OPTAB_LIB_WIDEN
);
3325 addr
= expand_simple_binop (DImode
, IOR
, extl
, exth
,
3326 NULL
, 1, OPTAB_LIB_WIDEN
);
3328 if (sign
&& GET_MODE (tgt
) != HImode
)
3330 addr
= gen_lowpart (HImode
, addr
);
3331 emit_insn (gen_extend_insn (tgt
, addr
, GET_MODE (tgt
), HImode
, 0));
3335 if (GET_MODE (tgt
) != DImode
)
3336 addr
= gen_lowpart (GET_MODE (tgt
), addr
);
3337 emit_move_insn (tgt
, addr
);
3342 meml
= gen_reg_rtx (DImode
);
3343 memh
= gen_reg_rtx (DImode
);
3344 addr
= gen_reg_rtx (DImode
);
3345 extl
= gen_reg_rtx (DImode
);
3346 exth
= gen_reg_rtx (DImode
);
3348 mema
= XEXP (mem
, 0);
3349 if (GET_CODE (mema
) == LO_SUM
)
3350 mema
= force_reg (Pmode
, mema
);
3352 /* AND addresses cannot be in any alias set, since they may implicitly
3353 alias surrounding code. Ideally we'd have some alias set that
3354 covered all types except those with alignment 8 or higher. */
3356 tmp
= change_address (mem
, DImode
,
3357 gen_rtx_AND (DImode
,
3358 plus_constant (mema
, ofs
),
3360 set_mem_alias_set (tmp
, 0);
3361 emit_move_insn (meml
, tmp
);
3363 tmp
= change_address (mem
, DImode
,
3364 gen_rtx_AND (DImode
,
3365 plus_constant (mema
, ofs
+ size
- 1),
3367 set_mem_alias_set (tmp
, 0);
3368 emit_move_insn (memh
, tmp
);
3370 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3372 emit_move_insn (addr
, plus_constant (mema
, -1));
3374 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3375 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3377 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3378 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3379 addr
, 1, OPTAB_WIDEN
);
3381 else if (sign
&& size
== 2)
3383 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3385 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3386 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3388 /* We must use tgt here for the target. Alpha-vms port fails if we use
3389 addr for the target, because addr is marked as a pointer and combine
3390 knows that pointers are always sign-extended 32 bit values. */
3391 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3392 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3393 addr
, 1, OPTAB_WIDEN
);
3397 if (WORDS_BIG_ENDIAN
)
3399 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3403 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3408 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3413 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3420 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3424 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3425 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3429 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3434 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3439 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3448 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3449 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3454 emit_move_insn (tgt
, gen_lowpart (GET_MODE (tgt
), addr
));
3457 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3460 alpha_expand_unaligned_store (rtx dst
, rtx src
,
3461 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
3463 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3465 if (TARGET_BWX
&& size
== 2)
3467 if (src
!= const0_rtx
)
3469 dstl
= gen_lowpart (QImode
, src
);
3470 dsth
= expand_simple_binop (DImode
, LSHIFTRT
, src
, GEN_INT (8),
3471 NULL
, 1, OPTAB_LIB_WIDEN
);
3472 dsth
= gen_lowpart (QImode
, dsth
);
3475 dstl
= dsth
= const0_rtx
;
3477 meml
= adjust_address (dst
, QImode
, ofs
);
3478 memh
= adjust_address (dst
, QImode
, ofs
+1);
3479 if (BYTES_BIG_ENDIAN
)
3480 addr
= meml
, meml
= memh
, memh
= addr
;
3482 emit_move_insn (meml
, dstl
);
3483 emit_move_insn (memh
, dsth
);
3487 dstl
= gen_reg_rtx (DImode
);
3488 dsth
= gen_reg_rtx (DImode
);
3489 insl
= gen_reg_rtx (DImode
);
3490 insh
= gen_reg_rtx (DImode
);
3492 dsta
= XEXP (dst
, 0);
3493 if (GET_CODE (dsta
) == LO_SUM
)
3494 dsta
= force_reg (Pmode
, dsta
);
3496 /* AND addresses cannot be in any alias set, since they may implicitly
3497 alias surrounding code. Ideally we'd have some alias set that
3498 covered all types except those with alignment 8 or higher. */
3500 meml
= change_address (dst
, DImode
,
3501 gen_rtx_AND (DImode
,
3502 plus_constant (dsta
, ofs
),
3504 set_mem_alias_set (meml
, 0);
3506 memh
= change_address (dst
, DImode
,
3507 gen_rtx_AND (DImode
,
3508 plus_constant (dsta
, ofs
+ size
- 1),
3510 set_mem_alias_set (memh
, 0);
3512 emit_move_insn (dsth
, memh
);
3513 emit_move_insn (dstl
, meml
);
3514 if (WORDS_BIG_ENDIAN
)
3516 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3518 if (src
!= const0_rtx
)
3523 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3526 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3529 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3532 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3533 GEN_INT (size
*8), addr
));
3539 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3543 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3544 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3548 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
3552 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3556 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3558 if (src
!= CONST0_RTX (GET_MODE (src
)))
3560 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3561 GEN_INT (size
*8), addr
));
3566 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3569 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3572 emit_insn (gen_insql_le (insl
, src
, addr
));
3577 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3582 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3586 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3587 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3591 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
3596 if (src
!= CONST0_RTX (GET_MODE (src
)))
3598 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3599 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3602 if (WORDS_BIG_ENDIAN
)
3604 emit_move_insn (meml
, dstl
);
3605 emit_move_insn (memh
, dsth
);
3609 /* Must store high before low for degenerate case of aligned. */
3610 emit_move_insn (memh
, dsth
);
3611 emit_move_insn (meml
, dstl
);
3615 /* The block move code tries to maximize speed by separating loads and
3616 stores at the expense of register pressure: we load all of the data
3617 before we store it back out. There are two secondary effects worth
3618 mentioning, that this speeds copying to/from aligned and unaligned
3619 buffers, and that it makes the code significantly easier to write. */
3621 #define MAX_MOVE_WORDS 8
3623 /* Load an integral number of consecutive unaligned quadwords. */
3626 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
3627 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3629 rtx
const im8
= GEN_INT (-8);
3630 rtx
const i64
= GEN_INT (64);
3631 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3632 rtx sreg
, areg
, tmp
, smema
;
3635 smema
= XEXP (smem
, 0);
3636 if (GET_CODE (smema
) == LO_SUM
)
3637 smema
= force_reg (Pmode
, smema
);
3639 /* Generate all the tmp registers we need. */
3640 for (i
= 0; i
< words
; ++i
)
3642 data_regs
[i
] = out_regs
[i
];
3643 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3645 data_regs
[words
] = gen_reg_rtx (DImode
);
3648 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3650 /* Load up all of the source data. */
3651 for (i
= 0; i
< words
; ++i
)
3653 tmp
= change_address (smem
, DImode
,
3654 gen_rtx_AND (DImode
,
3655 plus_constant (smema
, 8*i
),
3657 set_mem_alias_set (tmp
, 0);
3658 emit_move_insn (data_regs
[i
], tmp
);
3661 tmp
= change_address (smem
, DImode
,
3662 gen_rtx_AND (DImode
,
3663 plus_constant (smema
, 8*words
- 1),
3665 set_mem_alias_set (tmp
, 0);
3666 emit_move_insn (data_regs
[words
], tmp
);
3668 /* Extract the half-word fragments. Unfortunately DEC decided to make
3669 extxh with offset zero a noop instead of zeroing the register, so
3670 we must take care of that edge condition ourselves with cmov. */
3672 sreg
= copy_addr_to_reg (smema
);
3673 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3675 if (WORDS_BIG_ENDIAN
)
3676 emit_move_insn (sreg
, plus_constant (sreg
, 7));
3677 for (i
= 0; i
< words
; ++i
)
3679 if (WORDS_BIG_ENDIAN
)
3681 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
3682 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
3686 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
3687 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3689 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3690 gen_rtx_IF_THEN_ELSE (DImode
,
3691 gen_rtx_EQ (DImode
, areg
,
3693 const0_rtx
, ext_tmps
[i
])));
3696 /* Merge the half-words into whole words. */
3697 for (i
= 0; i
< words
; ++i
)
3699 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3700 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
3704 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3705 may be NULL to store zeros. */
3708 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
3709 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3711 rtx
const im8
= GEN_INT (-8);
3712 rtx
const i64
= GEN_INT (64);
3713 rtx ins_tmps
[MAX_MOVE_WORDS
];
3714 rtx st_tmp_1
, st_tmp_2
, dreg
;
3715 rtx st_addr_1
, st_addr_2
, dmema
;
3718 dmema
= XEXP (dmem
, 0);
3719 if (GET_CODE (dmema
) == LO_SUM
)
3720 dmema
= force_reg (Pmode
, dmema
);
3722 /* Generate all the tmp registers we need. */
3723 if (data_regs
!= NULL
)
3724 for (i
= 0; i
< words
; ++i
)
3725 ins_tmps
[i
] = gen_reg_rtx(DImode
);
3726 st_tmp_1
= gen_reg_rtx(DImode
);
3727 st_tmp_2
= gen_reg_rtx(DImode
);
3730 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
3732 st_addr_2
= change_address (dmem
, DImode
,
3733 gen_rtx_AND (DImode
,
3734 plus_constant (dmema
, words
*8 - 1),
3736 set_mem_alias_set (st_addr_2
, 0);
3738 st_addr_1
= change_address (dmem
, DImode
,
3739 gen_rtx_AND (DImode
, dmema
, im8
));
3740 set_mem_alias_set (st_addr_1
, 0);
3742 /* Load up the destination end bits. */
3743 emit_move_insn (st_tmp_2
, st_addr_2
);
3744 emit_move_insn (st_tmp_1
, st_addr_1
);
3746 /* Shift the input data into place. */
3747 dreg
= copy_addr_to_reg (dmema
);
3748 if (WORDS_BIG_ENDIAN
)
3749 emit_move_insn (dreg
, plus_constant (dreg
, 7));
3750 if (data_regs
!= NULL
)
3752 for (i
= words
-1; i
>= 0; --i
)
3754 if (WORDS_BIG_ENDIAN
)
3756 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
3757 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
3761 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
3762 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
3765 for (i
= words
-1; i
> 0; --i
)
3767 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3768 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
3773 /* Split and merge the ends with the destination data. */
3774 if (WORDS_BIG_ENDIAN
)
3776 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
3777 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
3781 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
3782 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
3785 if (data_regs
!= NULL
)
3787 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
3788 st_tmp_2
, 1, OPTAB_WIDEN
);
3789 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
3790 st_tmp_1
, 1, OPTAB_WIDEN
);
3794 if (WORDS_BIG_ENDIAN
)
3795 emit_move_insn (st_addr_1
, st_tmp_1
);
3797 emit_move_insn (st_addr_2
, st_tmp_2
);
3798 for (i
= words
-1; i
> 0; --i
)
3800 rtx tmp
= change_address (dmem
, DImode
,
3801 gen_rtx_AND (DImode
,
3802 plus_constant(dmema
,
3803 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
3805 set_mem_alias_set (tmp
, 0);
3806 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
3808 if (WORDS_BIG_ENDIAN
)
3809 emit_move_insn (st_addr_2
, st_tmp_2
);
3811 emit_move_insn (st_addr_1
, st_tmp_1
);
3815 /* Expand string/block move operations.
3817 operands[0] is the pointer to the destination.
3818 operands[1] is the pointer to the source.
3819 operands[2] is the number of bytes to move.
3820 operands[3] is the alignment. */
3823 alpha_expand_block_move (rtx operands
[])
3825 rtx bytes_rtx
= operands
[2];
3826 rtx align_rtx
= operands
[3];
3827 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3828 HOST_WIDE_INT bytes
= orig_bytes
;
3829 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3830 HOST_WIDE_INT dst_align
= src_align
;
3831 rtx orig_src
= operands
[1];
3832 rtx orig_dst
= operands
[0];
3833 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
3835 unsigned int i
, words
, ofs
, nregs
= 0;
3837 if (orig_bytes
<= 0)
3839 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3842 /* Look for additional alignment information from recorded register info. */
3844 tmp
= XEXP (orig_src
, 0);
3845 if (GET_CODE (tmp
) == REG
)
3846 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3847 else if (GET_CODE (tmp
) == PLUS
3848 && GET_CODE (XEXP (tmp
, 0)) == REG
3849 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3851 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3852 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3856 if (a
>= 64 && c
% 8 == 0)
3858 else if (a
>= 32 && c
% 4 == 0)
3860 else if (a
>= 16 && c
% 2 == 0)
3865 tmp
= XEXP (orig_dst
, 0);
3866 if (GET_CODE (tmp
) == REG
)
3867 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3868 else if (GET_CODE (tmp
) == PLUS
3869 && GET_CODE (XEXP (tmp
, 0)) == REG
3870 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3872 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3873 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3877 if (a
>= 64 && c
% 8 == 0)
3879 else if (a
>= 32 && c
% 4 == 0)
3881 else if (a
>= 16 && c
% 2 == 0)
3887 if (src_align
>= 64 && bytes
>= 8)
3891 for (i
= 0; i
< words
; ++i
)
3892 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3894 for (i
= 0; i
< words
; ++i
)
3895 emit_move_insn (data_regs
[nregs
+ i
],
3896 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
3903 if (src_align
>= 32 && bytes
>= 4)
3907 for (i
= 0; i
< words
; ++i
)
3908 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
3910 for (i
= 0; i
< words
; ++i
)
3911 emit_move_insn (data_regs
[nregs
+ i
],
3912 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
3923 for (i
= 0; i
< words
+1; ++i
)
3924 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3926 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
3934 if (! TARGET_BWX
&& bytes
>= 4)
3936 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
3937 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
3944 if (src_align
>= 16)
3947 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3948 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
3951 } while (bytes
>= 2);
3953 else if (! TARGET_BWX
)
3955 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3956 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
3964 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
3965 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
3970 gcc_assert (nregs
<= ARRAY_SIZE (data_regs
));
3972 /* Now save it back out again. */
3976 /* Write out the data in whatever chunks reading the source allowed. */
3977 if (dst_align
>= 64)
3979 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3981 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
3988 if (dst_align
>= 32)
3990 /* If the source has remaining DImode regs, write them out in
3992 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
3994 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
3995 NULL_RTX
, 1, OPTAB_WIDEN
);
3997 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
3998 gen_lowpart (SImode
, data_regs
[i
]));
3999 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4000 gen_lowpart (SImode
, tmp
));
4005 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4007 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4014 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4016 /* Write out a remaining block of words using unaligned methods. */
4018 for (words
= 1; i
+ words
< nregs
; words
++)
4019 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4023 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4025 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4032 /* Due to the above, this won't be aligned. */
4033 /* ??? If we have more than one of these, consider constructing full
4034 words in registers and using alpha_expand_unaligned_store_words. */
4035 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4037 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4042 if (dst_align
>= 16)
4043 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4045 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4050 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4052 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4057 /* The remainder must be byte copies. */
4060 gcc_assert (GET_MODE (data_regs
[i
]) == QImode
);
4061 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4070 alpha_expand_block_clear (rtx operands
[])
4072 rtx bytes_rtx
= operands
[1];
4073 rtx align_rtx
= operands
[3];
4074 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4075 HOST_WIDE_INT bytes
= orig_bytes
;
4076 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4077 HOST_WIDE_INT alignofs
= 0;
4078 rtx orig_dst
= operands
[0];
4080 int i
, words
, ofs
= 0;
4082 if (orig_bytes
<= 0)
4084 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4087 /* Look for stricter alignment. */
4088 tmp
= XEXP (orig_dst
, 0);
4089 if (GET_CODE (tmp
) == REG
)
4090 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4091 else if (GET_CODE (tmp
) == PLUS
4092 && GET_CODE (XEXP (tmp
, 0)) == REG
4093 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4095 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4096 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4101 align
= a
, alignofs
= 8 - c
% 8;
4103 align
= a
, alignofs
= 4 - c
% 4;
4105 align
= a
, alignofs
= 2 - c
% 2;
4109 /* Handle an unaligned prefix first. */
4113 #if HOST_BITS_PER_WIDE_INT >= 64
4114 /* Given that alignofs is bounded by align, the only time BWX could
4115 generate three stores is for a 7 byte fill. Prefer two individual
4116 stores over a load/mask/store sequence. */
4117 if ((!TARGET_BWX
|| alignofs
== 7)
4119 && !(alignofs
== 4 && bytes
>= 4))
4121 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4122 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4126 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4127 set_mem_alias_set (mem
, 0);
4129 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4130 if (bytes
< alignofs
)
4132 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4143 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4144 NULL_RTX
, 1, OPTAB_WIDEN
);
4146 emit_move_insn (mem
, tmp
);
4150 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4152 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4157 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4159 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4164 if (alignofs
== 4 && bytes
>= 4)
4166 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4172 /* If we've not used the extra lead alignment information by now,
4173 we won't be able to. Downgrade align to match what's left over. */
4176 alignofs
= alignofs
& -alignofs
;
4177 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4181 /* Handle a block of contiguous long-words. */
4183 if (align
>= 64 && bytes
>= 8)
4187 for (i
= 0; i
< words
; ++i
)
4188 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4195 /* If the block is large and appropriately aligned, emit a single
4196 store followed by a sequence of stq_u insns. */
4198 if (align
>= 32 && bytes
> 16)
4202 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4206 orig_dsta
= XEXP (orig_dst
, 0);
4207 if (GET_CODE (orig_dsta
) == LO_SUM
)
4208 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4211 for (i
= 0; i
< words
; ++i
)
4214 = change_address (orig_dst
, DImode
,
4215 gen_rtx_AND (DImode
,
4216 plus_constant (orig_dsta
, ofs
+ i
*8),
4218 set_mem_alias_set (mem
, 0);
4219 emit_move_insn (mem
, const0_rtx
);
4222 /* Depending on the alignment, the first stq_u may have overlapped
4223 with the initial stl, which means that the last stq_u didn't
4224 write as much as it would appear. Leave those questionable bytes
4226 bytes
-= words
* 8 - 4;
4227 ofs
+= words
* 8 - 4;
4230 /* Handle a smaller block of aligned words. */
4232 if ((align
>= 64 && bytes
== 4)
4233 || (align
== 32 && bytes
>= 4))
4237 for (i
= 0; i
< words
; ++i
)
4238 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4245 /* An unaligned block uses stq_u stores for as many as possible. */
4251 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4257 /* Next clean up any trailing pieces. */
4259 #if HOST_BITS_PER_WIDE_INT >= 64
4260 /* Count the number of bits in BYTES for which aligned stores could
4263 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4267 /* If we have appropriate alignment (and it wouldn't take too many
4268 instructions otherwise), mask out the bytes we need. */
4269 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4276 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4277 set_mem_alias_set (mem
, 0);
4279 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4281 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4282 NULL_RTX
, 1, OPTAB_WIDEN
);
4284 emit_move_insn (mem
, tmp
);
4287 else if (align
>= 32 && bytes
< 4)
4292 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4293 set_mem_alias_set (mem
, 0);
4295 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4297 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4298 NULL_RTX
, 1, OPTAB_WIDEN
);
4300 emit_move_insn (mem
, tmp
);
4306 if (!TARGET_BWX
&& bytes
>= 4)
4308 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4318 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4322 } while (bytes
>= 2);
4324 else if (! TARGET_BWX
)
4326 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4334 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4342 /* Returns a mask so that zap(x, value) == x & mask. */
4345 alpha_expand_zap_mask (HOST_WIDE_INT value
)
4350 if (HOST_BITS_PER_WIDE_INT
>= 64)
4352 HOST_WIDE_INT mask
= 0;
4354 for (i
= 7; i
>= 0; --i
)
4357 if (!((value
>> i
) & 1))
4361 result
= gen_int_mode (mask
, DImode
);
4365 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
4367 gcc_assert (HOST_BITS_PER_WIDE_INT
== 32);
4369 for (i
= 7; i
>= 4; --i
)
4372 if (!((value
>> i
) & 1))
4376 for (i
= 3; i
>= 0; --i
)
4379 if (!((value
>> i
) & 1))
4383 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
4390 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
4391 enum machine_mode mode
,
4392 rtx op0
, rtx op1
, rtx op2
)
4394 op0
= gen_lowpart (mode
, op0
);
4396 if (op1
== const0_rtx
)
4397 op1
= CONST0_RTX (mode
);
4399 op1
= gen_lowpart (mode
, op1
);
4401 if (op2
== const0_rtx
)
4402 op2
= CONST0_RTX (mode
);
4404 op2
= gen_lowpart (mode
, op2
);
4406 emit_insn ((*gen
) (op0
, op1
, op2
));
4409 /* A subroutine of the atomic operation splitters. Jump to LABEL if
4410 COND is true. Mark the jump as unlikely to be taken. */
4413 emit_unlikely_jump (rtx cond
, rtx label
)
4415 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
4418 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
4419 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
4420 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_BR_PROB
, very_unlikely
, NULL_RTX
);
4423 /* A subroutine of the atomic operation splitters. Emit a load-locked
4424 instruction in MODE. */
4427 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
4429 rtx (*fn
) (rtx
, rtx
) = NULL
;
4431 fn
= gen_load_locked_si
;
4432 else if (mode
== DImode
)
4433 fn
= gen_load_locked_di
;
4434 emit_insn (fn (reg
, mem
));
4437 /* A subroutine of the atomic operation splitters. Emit a store-conditional
4438 instruction in MODE. */
4441 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
4443 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
4445 fn
= gen_store_conditional_si
;
4446 else if (mode
== DImode
)
4447 fn
= gen_store_conditional_di
;
4448 emit_insn (fn (res
, mem
, val
));
4451 /* A subroutine of the atomic operation splitters. Emit an insxl
4452 instruction in MODE. */
4455 emit_insxl (enum machine_mode mode
, rtx op1
, rtx op2
)
4457 rtx ret
= gen_reg_rtx (DImode
);
4458 rtx (*fn
) (rtx
, rtx
, rtx
);
4460 if (WORDS_BIG_ENDIAN
)
4474 emit_insn (fn (ret
, op1
, op2
));
4479 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
4480 to perform. MEM is the memory on which to operate. VAL is the second
4481 operand of the binary operator. BEFORE and AFTER are optional locations to
4482 return the value of MEM either before of after the operation. SCRATCH is
4483 a scratch register. */
4486 alpha_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
4487 rtx before
, rtx after
, rtx scratch
)
4489 enum machine_mode mode
= GET_MODE (mem
);
4490 rtx label
, x
, cond
= gen_rtx_REG (DImode
, REGNO (scratch
));
4492 emit_insn (gen_memory_barrier ());
4494 label
= gen_label_rtx ();
4496 label
= gen_rtx_LABEL_REF (DImode
, label
);
4500 emit_load_locked (mode
, before
, mem
);
4503 x
= gen_rtx_AND (mode
, gen_rtx_NOT (mode
, before
), val
);
4505 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
4507 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
4508 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
4510 emit_store_conditional (mode
, cond
, mem
, scratch
);
4512 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4513 emit_unlikely_jump (x
, label
);
4515 emit_insn (gen_memory_barrier ());
4518 /* Expand a compare and swap operation. */
4521 alpha_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
4524 enum machine_mode mode
= GET_MODE (mem
);
4525 rtx label1
, label2
, x
, cond
= gen_lowpart (DImode
, scratch
);
4527 emit_insn (gen_memory_barrier ());
4529 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4530 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4531 emit_label (XEXP (label1
, 0));
4533 emit_load_locked (mode
, retval
, mem
);
4535 x
= gen_lowpart (DImode
, retval
);
4536 if (oldval
== const0_rtx
)
4537 x
= gen_rtx_NE (DImode
, x
, const0_rtx
);
4540 x
= gen_rtx_EQ (DImode
, x
, oldval
);
4541 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4542 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4544 emit_unlikely_jump (x
, label2
);
4546 emit_move_insn (scratch
, newval
);
4547 emit_store_conditional (mode
, cond
, mem
, scratch
);
4549 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4550 emit_unlikely_jump (x
, label1
);
4552 emit_insn (gen_memory_barrier ());
4553 emit_label (XEXP (label2
, 0));
4557 alpha_expand_compare_and_swap_12 (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
4559 enum machine_mode mode
= GET_MODE (mem
);
4560 rtx addr
, align
, wdst
;
4561 rtx (*fn5
) (rtx
, rtx
, rtx
, rtx
, rtx
);
4563 addr
= force_reg (DImode
, XEXP (mem
, 0));
4564 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4565 NULL_RTX
, 1, OPTAB_DIRECT
);
4567 oldval
= convert_modes (DImode
, mode
, oldval
, 1);
4568 newval
= emit_insxl (mode
, newval
, addr
);
4570 wdst
= gen_reg_rtx (DImode
);
4572 fn5
= gen_sync_compare_and_swapqi_1
;
4574 fn5
= gen_sync_compare_and_swaphi_1
;
4575 emit_insn (fn5 (wdst
, addr
, oldval
, newval
, align
));
4577 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4581 alpha_split_compare_and_swap_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4582 rtx oldval
, rtx newval
, rtx align
,
4583 rtx scratch
, rtx cond
)
4585 rtx label1
, label2
, mem
, width
, mask
, x
;
4587 mem
= gen_rtx_MEM (DImode
, align
);
4588 MEM_VOLATILE_P (mem
) = 1;
4590 emit_insn (gen_memory_barrier ());
4591 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4592 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4593 emit_label (XEXP (label1
, 0));
4595 emit_load_locked (DImode
, scratch
, mem
);
4597 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4598 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4599 if (WORDS_BIG_ENDIAN
)
4600 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4602 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4604 if (oldval
== const0_rtx
)
4605 x
= gen_rtx_NE (DImode
, dest
, const0_rtx
);
4608 x
= gen_rtx_EQ (DImode
, dest
, oldval
);
4609 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4610 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4612 emit_unlikely_jump (x
, label2
);
4614 if (WORDS_BIG_ENDIAN
)
4615 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4617 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4618 emit_insn (gen_iordi3 (scratch
, scratch
, newval
));
4620 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4622 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4623 emit_unlikely_jump (x
, label1
);
4625 emit_insn (gen_memory_barrier ());
4626 emit_label (XEXP (label2
, 0));
4629 /* Expand an atomic exchange operation. */
4632 alpha_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
4634 enum machine_mode mode
= GET_MODE (mem
);
4635 rtx label
, x
, cond
= gen_lowpart (DImode
, scratch
);
4637 emit_insn (gen_memory_barrier ());
4639 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4640 emit_label (XEXP (label
, 0));
4642 emit_load_locked (mode
, retval
, mem
);
4643 emit_move_insn (scratch
, val
);
4644 emit_store_conditional (mode
, cond
, mem
, scratch
);
4646 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4647 emit_unlikely_jump (x
, label
);
4651 alpha_expand_lock_test_and_set_12 (rtx dst
, rtx mem
, rtx val
)
4653 enum machine_mode mode
= GET_MODE (mem
);
4654 rtx addr
, align
, wdst
;
4655 rtx (*fn4
) (rtx
, rtx
, rtx
, rtx
);
4657 /* Force the address into a register. */
4658 addr
= force_reg (DImode
, XEXP (mem
, 0));
4660 /* Align it to a multiple of 8. */
4661 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4662 NULL_RTX
, 1, OPTAB_DIRECT
);
4664 /* Insert val into the correct byte location within the word. */
4665 val
= emit_insxl (mode
, val
, addr
);
4667 wdst
= gen_reg_rtx (DImode
);
4669 fn4
= gen_sync_lock_test_and_setqi_1
;
4671 fn4
= gen_sync_lock_test_and_sethi_1
;
4672 emit_insn (fn4 (wdst
, addr
, val
, align
));
4674 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4678 alpha_split_lock_test_and_set_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4679 rtx val
, rtx align
, rtx scratch
)
4681 rtx label
, mem
, width
, mask
, x
;
4683 mem
= gen_rtx_MEM (DImode
, align
);
4684 MEM_VOLATILE_P (mem
) = 1;
4686 emit_insn (gen_memory_barrier ());
4687 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4688 emit_label (XEXP (label
, 0));
4690 emit_load_locked (DImode
, scratch
, mem
);
4692 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4693 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4694 if (WORDS_BIG_ENDIAN
)
4696 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4697 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4701 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4702 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4704 emit_insn (gen_iordi3 (scratch
, scratch
, val
));
4706 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4708 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4709 emit_unlikely_jump (x
, label
);
4712 /* Adjust the cost of a scheduling dependency. Return the new cost of
4713 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4716 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4718 enum attr_type insn_type
, dep_insn_type
;
4720 /* If the dependence is an anti-dependence, there is no cost. For an
4721 output dependence, there is sometimes a cost, but it doesn't seem
4722 worth handling those few cases. */
4723 if (REG_NOTE_KIND (link
) != 0)
4726 /* If we can't recognize the insns, we can't really do anything. */
4727 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4730 insn_type
= get_attr_type (insn
);
4731 dep_insn_type
= get_attr_type (dep_insn
);
4733 /* Bring in the user-defined memory latency. */
4734 if (dep_insn_type
== TYPE_ILD
4735 || dep_insn_type
== TYPE_FLD
4736 || dep_insn_type
== TYPE_LDSYM
)
4737 cost
+= alpha_memory_latency
-1;
4739 /* Everything else handled in DFA bypasses now. */
4744 /* The number of instructions that can be issued per cycle. */
4747 alpha_issue_rate (void)
4749 return (alpha_tune
== PROCESSOR_EV4
? 2 : 4);
4752 /* How many alternative schedules to try. This should be as wide as the
4753 scheduling freedom in the DFA, but no wider. Making this value too
4754 large results extra work for the scheduler.
4756 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4757 alternative schedules. For EV5, we can choose between E0/E1 and
4758 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4761 alpha_multipass_dfa_lookahead (void)
4763 return (alpha_tune
== PROCESSOR_EV6
? 4 : 2);
4766 /* Machine-specific function data. */
4768 struct machine_function
GTY(())
4771 /* List of call information words for calls from this function. */
4772 struct rtx_def
*first_ciw
;
4773 struct rtx_def
*last_ciw
;
4776 /* List of deferred case vectors. */
4777 struct rtx_def
*addr_list
;
4780 const char *some_ld_name
;
4782 /* For TARGET_LD_BUGGY_LDGP. */
4783 struct rtx_def
*gp_save_rtx
;
4786 /* How to allocate a 'struct machine_function'. */
4788 static struct machine_function
*
4789 alpha_init_machine_status (void)
4791 return ((struct machine_function
*)
4792 ggc_alloc_cleared (sizeof (struct machine_function
)));
4795 /* Functions to save and restore alpha_return_addr_rtx. */
4797 /* Start the ball rolling with RETURN_ADDR_RTX. */
4800 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
4805 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4808 /* Return or create a memory slot containing the gp value for the current
4809 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4812 alpha_gp_save_rtx (void)
4814 rtx seq
, m
= cfun
->machine
->gp_save_rtx
;
4820 m
= assign_stack_local (DImode
, UNITS_PER_WORD
, BITS_PER_WORD
);
4821 m
= validize_mem (m
);
4822 emit_move_insn (m
, pic_offset_table_rtx
);
4826 emit_insn_after (seq
, entry_of_function ());
4828 cfun
->machine
->gp_save_rtx
= m
;
4835 alpha_ra_ever_killed (void)
4839 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4840 return regs_ever_live
[REG_RA
];
4842 push_topmost_sequence ();
4844 pop_topmost_sequence ();
4846 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
4850 /* Return the trap mode suffix applicable to the current
4851 instruction, or NULL. */
4854 get_trap_mode_suffix (void)
4856 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
4860 case TRAP_SUFFIX_NONE
:
4863 case TRAP_SUFFIX_SU
:
4864 if (alpha_fptm
>= ALPHA_FPTM_SU
)
4868 case TRAP_SUFFIX_SUI
:
4869 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
4873 case TRAP_SUFFIX_V_SV
:
4881 case ALPHA_FPTM_SUI
:
4887 case TRAP_SUFFIX_V_SV_SVI
:
4896 case ALPHA_FPTM_SUI
:
4903 case TRAP_SUFFIX_U_SU_SUI
:
4912 case ALPHA_FPTM_SUI
:
4925 /* Return the rounding mode suffix applicable to the current
4926 instruction, or NULL. */
4929 get_round_mode_suffix (void)
4931 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
4935 case ROUND_SUFFIX_NONE
:
4937 case ROUND_SUFFIX_NORMAL
:
4940 case ALPHA_FPRM_NORM
:
4942 case ALPHA_FPRM_MINF
:
4944 case ALPHA_FPRM_CHOP
:
4946 case ALPHA_FPRM_DYN
:
4953 case ROUND_SUFFIX_C
:
4962 /* Locate some local-dynamic symbol still in use by this function
4963 so that we can print its name in some movdi_er_tlsldm pattern. */
4966 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4970 if (GET_CODE (x
) == SYMBOL_REF
4971 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4973 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4981 get_some_local_dynamic_name (void)
4985 if (cfun
->machine
->some_ld_name
)
4986 return cfun
->machine
->some_ld_name
;
4988 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4990 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4991 return cfun
->machine
->some_ld_name
;
4996 /* Print an operand. Recognize special options, documented below. */
4999 print_operand (FILE *file
, rtx x
, int code
)
5006 /* Print the assembler name of the current function. */
5007 assemble_name (file
, alpha_fnname
);
5011 assemble_name (file
, get_some_local_dynamic_name ());
5016 const char *trap
= get_trap_mode_suffix ();
5017 const char *round
= get_round_mode_suffix ();
5020 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5021 (trap
? trap
: ""), (round
? round
: ""));
5026 /* Generates single precision instruction suffix. */
5027 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5031 /* Generates double precision instruction suffix. */
5032 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5036 /* Generates a nop after a noreturn call at the very end of the
5038 if (next_real_insn (current_output_insn
) == 0)
5039 fprintf (file
, "\n\tnop");
5043 if (alpha_this_literal_sequence_number
== 0)
5044 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5045 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5049 if (alpha_this_gpdisp_sequence_number
== 0)
5050 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5051 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5055 if (GET_CODE (x
) == HIGH
)
5056 output_addr_const (file
, XEXP (x
, 0));
5058 output_operand_lossage ("invalid %%H value");
5065 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5067 x
= XVECEXP (x
, 0, 0);
5068 lituse
= "lituse_tlsgd";
5070 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5072 x
= XVECEXP (x
, 0, 0);
5073 lituse
= "lituse_tlsldm";
5075 else if (GET_CODE (x
) == CONST_INT
)
5076 lituse
= "lituse_jsr";
5079 output_operand_lossage ("invalid %%J value");
5083 if (x
!= const0_rtx
)
5084 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5092 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5093 lituse
= "lituse_jsrdirect";
5095 lituse
= "lituse_jsr";
5098 gcc_assert (INTVAL (x
) != 0);
5099 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5103 /* If this operand is the constant zero, write it as "$31". */
5104 if (GET_CODE (x
) == REG
)
5105 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5106 else if (x
== CONST0_RTX (GET_MODE (x
)))
5107 fprintf (file
, "$31");
5109 output_operand_lossage ("invalid %%r value");
5113 /* Similar, but for floating-point. */
5114 if (GET_CODE (x
) == REG
)
5115 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5116 else if (x
== CONST0_RTX (GET_MODE (x
)))
5117 fprintf (file
, "$f31");
5119 output_operand_lossage ("invalid %%R value");
5123 /* Write the 1's complement of a constant. */
5124 if (GET_CODE (x
) != CONST_INT
)
5125 output_operand_lossage ("invalid %%N value");
5127 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5131 /* Write 1 << C, for a constant C. */
5132 if (GET_CODE (x
) != CONST_INT
)
5133 output_operand_lossage ("invalid %%P value");
5135 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5139 /* Write the high-order 16 bits of a constant, sign-extended. */
5140 if (GET_CODE (x
) != CONST_INT
)
5141 output_operand_lossage ("invalid %%h value");
5143 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5147 /* Write the low-order 16 bits of a constant, sign-extended. */
5148 if (GET_CODE (x
) != CONST_INT
)
5149 output_operand_lossage ("invalid %%L value");
5151 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5152 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5156 /* Write mask for ZAP insn. */
5157 if (GET_CODE (x
) == CONST_DOUBLE
)
5159 HOST_WIDE_INT mask
= 0;
5160 HOST_WIDE_INT value
;
5162 value
= CONST_DOUBLE_LOW (x
);
5163 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5168 value
= CONST_DOUBLE_HIGH (x
);
5169 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5172 mask
|= (1 << (i
+ sizeof (int)));
5174 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5177 else if (GET_CODE (x
) == CONST_INT
)
5179 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5181 for (i
= 0; i
< 8; i
++, value
>>= 8)
5185 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5188 output_operand_lossage ("invalid %%m value");
5192 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5193 if (GET_CODE (x
) != CONST_INT
5194 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5195 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5196 output_operand_lossage ("invalid %%M value");
5198 fprintf (file
, "%s",
5199 (INTVAL (x
) == 8 ? "b"
5200 : INTVAL (x
) == 16 ? "w"
5201 : INTVAL (x
) == 32 ? "l"
5206 /* Similar, except do it from the mask. */
5207 if (GET_CODE (x
) == CONST_INT
)
5209 HOST_WIDE_INT value
= INTVAL (x
);
5216 if (value
== 0xffff)
5221 if (value
== 0xffffffff)
5232 else if (HOST_BITS_PER_WIDE_INT
== 32
5233 && GET_CODE (x
) == CONST_DOUBLE
5234 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5235 && CONST_DOUBLE_HIGH (x
) == 0)
5240 output_operand_lossage ("invalid %%U value");
5244 /* Write the constant value divided by 8 for little-endian mode or
5245 (56 - value) / 8 for big-endian mode. */
5247 if (GET_CODE (x
) != CONST_INT
5248 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5251 || (INTVAL (x
) & 7) != 0)
5252 output_operand_lossage ("invalid %%s value");
5254 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5256 ? (56 - INTVAL (x
)) / 8
5261 /* Same, except compute (64 - c) / 8 */
5263 if (GET_CODE (x
) != CONST_INT
5264 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5265 && (INTVAL (x
) & 7) != 8)
5266 output_operand_lossage ("invalid %%s value");
5268 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5273 /* On Unicos/Mk systems: use a DEX expression if the symbol
5274 clashes with a register name. */
5275 int dex
= unicosmk_need_dex (x
);
5277 fprintf (file
, "DEX(%d)", dex
);
5279 output_addr_const (file
, x
);
5283 case 'C': case 'D': case 'c': case 'd':
5284 /* Write out comparison name. */
5286 enum rtx_code c
= GET_CODE (x
);
5288 if (!COMPARISON_P (x
))
5289 output_operand_lossage ("invalid %%C value");
5291 else if (code
== 'D')
5292 c
= reverse_condition (c
);
5293 else if (code
== 'c')
5294 c
= swap_condition (c
);
5295 else if (code
== 'd')
5296 c
= swap_condition (reverse_condition (c
));
5299 fprintf (file
, "ule");
5301 fprintf (file
, "ult");
5302 else if (c
== UNORDERED
)
5303 fprintf (file
, "un");
5305 fprintf (file
, "%s", GET_RTX_NAME (c
));
5310 /* Write the divide or modulus operator. */
5311 switch (GET_CODE (x
))
5314 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5317 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5320 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5323 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5326 output_operand_lossage ("invalid %%E value");
5332 /* Write "_u" for unaligned access. */
5333 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5334 fprintf (file
, "_u");
5338 if (GET_CODE (x
) == REG
)
5339 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5340 else if (GET_CODE (x
) == MEM
)
5341 output_address (XEXP (x
, 0));
5342 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5344 switch (XINT (XEXP (x
, 0), 1))
5348 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5351 output_operand_lossage ("unknown relocation unspec");
5356 output_addr_const (file
, x
);
5360 output_operand_lossage ("invalid %%xn code");
5365 print_operand_address (FILE *file
, rtx addr
)
5368 HOST_WIDE_INT offset
= 0;
5370 if (GET_CODE (addr
) == AND
)
5371 addr
= XEXP (addr
, 0);
5373 if (GET_CODE (addr
) == PLUS
5374 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5376 offset
= INTVAL (XEXP (addr
, 1));
5377 addr
= XEXP (addr
, 0);
5380 if (GET_CODE (addr
) == LO_SUM
)
5382 const char *reloc16
, *reloclo
;
5383 rtx op1
= XEXP (addr
, 1);
5385 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5387 op1
= XEXP (op1
, 0);
5388 switch (XINT (op1
, 1))
5392 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5396 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5399 output_operand_lossage ("unknown relocation unspec");
5403 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5408 reloclo
= "gprellow";
5409 output_addr_const (file
, op1
);
5413 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5415 addr
= XEXP (addr
, 0);
5416 switch (GET_CODE (addr
))
5419 basereg
= REGNO (addr
);
5423 basereg
= subreg_regno (addr
);
5430 fprintf (file
, "($%d)\t\t!%s", basereg
,
5431 (basereg
== 29 ? reloc16
: reloclo
));
5435 switch (GET_CODE (addr
))
5438 basereg
= REGNO (addr
);
5442 basereg
= subreg_regno (addr
);
5446 offset
= INTVAL (addr
);
5449 #if TARGET_ABI_OPEN_VMS
5451 fprintf (file
, "%s", XSTR (addr
, 0));
5455 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
5456 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
);
5457 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5458 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5459 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5467 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5470 /* Emit RTL insns to initialize the variable parts of a trampoline at
5471 TRAMP. FNADDR is an RTX for the address of the function's pure
5472 code. CXT is an RTX for the static chain value for the function.
5474 The three offset parameters are for the individual template's
5475 layout. A JMPOFS < 0 indicates that the trampoline does not
5476 contain instructions at all.
5478 We assume here that a function will be called many more times than
5479 its address is taken (e.g., it might be passed to qsort), so we
5480 take the trouble to initialize the "hint" field in the JMP insn.
5481 Note that the hint field is PC (new) + 4 * bits 13:0. */
5484 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5485 int fnofs
, int cxtofs
, int jmpofs
)
5487 rtx temp
, temp1
, addr
;
5488 /* VMS really uses DImode pointers in memory at this point. */
5489 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5491 #ifdef POINTERS_EXTEND_UNSIGNED
5492 fnaddr
= convert_memory_address (mode
, fnaddr
);
5493 cxt
= convert_memory_address (mode
, cxt
);
5496 /* Store function address and CXT. */
5497 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5498 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5499 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5500 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5502 /* This has been disabled since the hint only has a 32k range, and in
5503 no existing OS is the stack within 32k of the text segment. */
5504 if (0 && jmpofs
>= 0)
5506 /* Compute hint value. */
5507 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5508 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5510 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5511 build_int_cst (NULL_TREE
, 2), NULL_RTX
, 1);
5512 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5513 GEN_INT (0x3fff), 0);
5515 /* Merge in the hint. */
5516 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5517 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5518 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5519 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5521 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5524 #ifdef ENABLE_EXECUTE_STACK
5525 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5526 0, VOIDmode
, 1, tramp
, Pmode
);
5530 emit_insn (gen_imb ());
5533 /* Determine where to put an argument to a function.
5534 Value is zero to push the argument on the stack,
5535 or a hard register in which to store the argument.
5537 MODE is the argument's machine mode.
5538 TYPE is the data type of the argument (as a tree).
5539 This is null for libcalls where that information may
5541 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5542 the preceding args and about the function being called.
5543 NAMED is nonzero if this argument is a named parameter
5544 (otherwise it is an extra parameter matching an ellipsis).
5546 On Alpha the first 6 words of args are normally in registers
5547 and the rest are pushed. */
5550 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5551 int named ATTRIBUTE_UNUSED
)
5556 /* Don't get confused and pass small structures in FP registers. */
5557 if (type
&& AGGREGATE_TYPE_P (type
))
5561 #ifdef ENABLE_CHECKING
5562 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5564 gcc_assert (!COMPLEX_MODE_P (mode
));
5567 /* Set up defaults for FP operands passed in FP registers, and
5568 integral operands passed in integer registers. */
5569 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5575 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5576 the three platforms, so we can't avoid conditional compilation. */
5577 #if TARGET_ABI_OPEN_VMS
5579 if (mode
== VOIDmode
)
5580 return alpha_arg_info_reg_val (cum
);
5582 num_args
= cum
.num_args
;
5584 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5587 #elif TARGET_ABI_UNICOSMK
5591 /* If this is the last argument, generate the call info word (CIW). */
5592 /* ??? We don't include the caller's line number in the CIW because
5593 I don't know how to determine it if debug infos are turned off. */
5594 if (mode
== VOIDmode
)
5603 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5604 if (cum
.reg_args_type
[i
])
5605 lo
|= (1 << (7 - i
));
5607 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5610 lo
|= cum
.num_reg_words
;
5612 #if HOST_BITS_PER_WIDE_INT == 32
5613 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5615 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5616 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5619 ciw
= immed_double_const (lo
, hi
, DImode
);
5621 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5622 UNSPEC_UMK_LOAD_CIW
);
5625 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5626 num_args
= cum
.num_reg_words
;
5628 || cum
.num_reg_words
+ size
> 6
5629 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5631 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5635 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5636 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5638 /* The argument fits in two registers. Note that we still need to
5639 reserve a register for empty structures. */
5643 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5646 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5647 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5648 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5652 #elif TARGET_ABI_OSF
5658 /* VOID is passed as a special flag for "last argument". */
5659 if (type
== void_type_node
)
5661 else if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5665 #error Unhandled ABI
5668 return gen_rtx_REG (mode
, num_args
+ basereg
);
5672 alpha_arg_partial_bytes (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5673 enum machine_mode mode ATTRIBUTE_UNUSED
,
5674 tree type ATTRIBUTE_UNUSED
,
5675 bool named ATTRIBUTE_UNUSED
)
5679 #if TARGET_ABI_OPEN_VMS
5680 if (cum
->num_args
< 6
5681 && 6 < cum
->num_args
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5682 words
= 6 - cum
->num_args
;
5683 #elif TARGET_ABI_UNICOSMK
5684 /* Never any split arguments. */
5685 #elif TARGET_ABI_OSF
5686 if (*cum
< 6 && 6 < *cum
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5689 #error Unhandled ABI
5692 return words
* UNITS_PER_WORD
;
5696 /* Return true if TYPE must be returned in memory, instead of in registers. */
5699 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
5701 enum machine_mode mode
= VOIDmode
;
5706 mode
= TYPE_MODE (type
);
5708 /* All aggregates are returned in memory. */
5709 if (AGGREGATE_TYPE_P (type
))
5713 size
= GET_MODE_SIZE (mode
);
5714 switch (GET_MODE_CLASS (mode
))
5716 case MODE_VECTOR_FLOAT
:
5717 /* Pass all float vectors in memory, like an aggregate. */
5720 case MODE_COMPLEX_FLOAT
:
5721 /* We judge complex floats on the size of their element,
5722 not the size of the whole type. */
5723 size
= GET_MODE_UNIT_SIZE (mode
);
5728 case MODE_COMPLEX_INT
:
5729 case MODE_VECTOR_INT
:
5733 /* ??? We get called on all sorts of random stuff from
5734 aggregate_value_p. We must return something, but it's not
5735 clear what's safe to return. Pretend it's a struct I
5740 /* Otherwise types must fit in one register. */
5741 return size
> UNITS_PER_WORD
;
5744 /* Return true if TYPE should be passed by invisible reference. */
5747 alpha_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
5748 enum machine_mode mode
,
5749 tree type ATTRIBUTE_UNUSED
,
5750 bool named ATTRIBUTE_UNUSED
)
5752 return mode
== TFmode
|| mode
== TCmode
;
5755 /* Define how to find the value returned by a function. VALTYPE is the
5756 data type of the value (as a tree). If the precise function being
5757 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5758 MODE is set instead of VALTYPE for libcalls.
5760 On Alpha the value is found in $0 for integer functions and
5761 $f0 for floating-point functions. */
5764 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
5765 enum machine_mode mode
)
5767 unsigned int regnum
, dummy
;
5768 enum mode_class
class;
5770 gcc_assert (!valtype
|| !alpha_return_in_memory (valtype
, func
));
5773 mode
= TYPE_MODE (valtype
);
5775 class = GET_MODE_CLASS (mode
);
5779 PROMOTE_MODE (mode
, dummy
, valtype
);
5782 case MODE_COMPLEX_INT
:
5783 case MODE_VECTOR_INT
:
5791 case MODE_COMPLEX_FLOAT
:
5793 enum machine_mode cmode
= GET_MODE_INNER (mode
);
5795 return gen_rtx_PARALLEL
5798 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
5800 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
5801 GEN_INT (GET_MODE_SIZE (cmode
)))));
5808 return gen_rtx_REG (mode
, regnum
);
5811 /* TCmode complex values are passed by invisible reference. We
5812 should not split these values. */
5815 alpha_split_complex_arg (tree type
)
5817 return TYPE_MODE (type
) != TCmode
;
5821 alpha_build_builtin_va_list (void)
5823 tree base
, ofs
, space
, record
, type_decl
;
5825 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5826 return ptr_type_node
;
5828 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5829 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5830 TREE_CHAIN (record
) = type_decl
;
5831 TYPE_NAME (record
) = type_decl
;
5833 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5835 /* Dummy field to prevent alignment warnings. */
5836 space
= build_decl (FIELD_DECL
, NULL_TREE
, integer_type_node
);
5837 DECL_FIELD_CONTEXT (space
) = record
;
5838 DECL_ARTIFICIAL (space
) = 1;
5839 DECL_IGNORED_P (space
) = 1;
5841 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
5843 DECL_FIELD_CONTEXT (ofs
) = record
;
5844 TREE_CHAIN (ofs
) = space
;
5846 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
5848 DECL_FIELD_CONTEXT (base
) = record
;
5849 TREE_CHAIN (base
) = ofs
;
5851 TYPE_FIELDS (record
) = base
;
5852 layout_type (record
);
5854 va_list_gpr_counter_field
= ofs
;
5859 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5860 and constant additions. */
5863 va_list_skip_additions (tree lhs
)
5867 if (TREE_CODE (lhs
) != SSA_NAME
)
5872 stmt
= SSA_NAME_DEF_STMT (lhs
);
5874 if (TREE_CODE (stmt
) == PHI_NODE
)
5877 if (TREE_CODE (stmt
) != MODIFY_EXPR
5878 || TREE_OPERAND (stmt
, 0) != lhs
)
5881 rhs
= TREE_OPERAND (stmt
, 1);
5882 if (TREE_CODE (rhs
) == WITH_SIZE_EXPR
)
5883 rhs
= TREE_OPERAND (rhs
, 0);
5885 if ((TREE_CODE (rhs
) != NOP_EXPR
5886 && TREE_CODE (rhs
) != CONVERT_EXPR
5887 && (TREE_CODE (rhs
) != PLUS_EXPR
5888 || TREE_CODE (TREE_OPERAND (rhs
, 1)) != INTEGER_CST
5889 || !host_integerp (TREE_OPERAND (rhs
, 1), 1)))
5890 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5893 lhs
= TREE_OPERAND (rhs
, 0);
5897 /* Check if LHS = RHS statement is
5898 LHS = *(ap.__base + ap.__offset + cst)
5901 + ((ap.__offset + cst <= 47)
5902 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
5903 If the former, indicate that GPR registers are needed,
5904 if the latter, indicate that FPR registers are needed.
5905 On alpha, cfun->va_list_gpr_size is used as size of the needed
5906 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if
5907 GPR registers are needed and bit 1 set if FPR registers are needed.
5908 Return true if va_list references should not be scanned for the current
5912 alpha_stdarg_optimize_hook (struct stdarg_info
*si
, tree lhs
, tree rhs
)
5914 tree base
, offset
, arg1
, arg2
;
5917 if (TREE_CODE (rhs
) != INDIRECT_REF
5918 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5921 lhs
= va_list_skip_additions (TREE_OPERAND (rhs
, 0));
5922 if (lhs
== NULL_TREE
5923 || TREE_CODE (lhs
) != PLUS_EXPR
)
5926 base
= TREE_OPERAND (lhs
, 0);
5927 if (TREE_CODE (base
) == SSA_NAME
)
5928 base
= va_list_skip_additions (base
);
5930 if (TREE_CODE (base
) != COMPONENT_REF
5931 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5933 base
= TREE_OPERAND (lhs
, 0);
5934 if (TREE_CODE (base
) == SSA_NAME
)
5935 base
= va_list_skip_additions (base
);
5937 if (TREE_CODE (base
) != COMPONENT_REF
5938 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5944 base
= get_base_address (base
);
5945 if (TREE_CODE (base
) != VAR_DECL
5946 || !bitmap_bit_p (si
->va_list_vars
, DECL_UID (base
)))
5949 offset
= TREE_OPERAND (lhs
, offset_arg
);
5950 if (TREE_CODE (offset
) == SSA_NAME
)
5951 offset
= va_list_skip_additions (offset
);
5953 if (TREE_CODE (offset
) == PHI_NODE
)
5957 if (PHI_NUM_ARGS (offset
) != 2)
5960 arg1
= va_list_skip_additions (PHI_ARG_DEF (offset
, 0));
5961 arg2
= va_list_skip_additions (PHI_ARG_DEF (offset
, 1));
5962 if (TREE_CODE (arg2
) != MINUS_EXPR
&& TREE_CODE (arg2
) != PLUS_EXPR
)
5968 if (TREE_CODE (arg2
) != MINUS_EXPR
&& TREE_CODE (arg2
) != PLUS_EXPR
)
5971 if (!host_integerp (TREE_OPERAND (arg2
, 1), 0))
5974 sub
= tree_low_cst (TREE_OPERAND (arg2
, 1), 0);
5975 if (TREE_CODE (arg2
) == MINUS_EXPR
)
5977 if (sub
< -48 || sub
> -32)
5980 arg2
= va_list_skip_additions (TREE_OPERAND (arg2
, 0));
5984 if (TREE_CODE (arg1
) == SSA_NAME
)
5985 arg1
= va_list_skip_additions (arg1
);
5987 if (TREE_CODE (arg1
) != COMPONENT_REF
5988 || TREE_OPERAND (arg1
, 1) != va_list_gpr_counter_field
5989 || get_base_address (arg1
) != base
)
5992 /* Need floating point regs. */
5993 cfun
->va_list_fpr_size
|= 2;
5995 else if (TREE_CODE (offset
) != COMPONENT_REF
5996 || TREE_OPERAND (offset
, 1) != va_list_gpr_counter_field
5997 || get_base_address (offset
) != base
)
6000 /* Need general regs. */
6001 cfun
->va_list_fpr_size
|= 1;
6005 si
->va_list_escapes
= true;
6010 /* Perform any needed actions needed for a function that is receiving a
6011 variable number of arguments. */
6014 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
6015 tree type
, int *pretend_size
, int no_rtl
)
6017 CUMULATIVE_ARGS cum
= *pcum
;
6019 /* Skip the current argument. */
6020 FUNCTION_ARG_ADVANCE (cum
, mode
, type
, 1);
6022 #if TARGET_ABI_UNICOSMK
6023 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6024 arguments on the stack. Unfortunately, it doesn't always store the first
6025 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6026 with stdargs as we always have at least one named argument there. */
6027 if (cum
.num_reg_words
< 6)
6031 emit_insn (gen_umk_mismatch_args (GEN_INT (cum
.num_reg_words
)));
6032 emit_insn (gen_arg_home_umk ());
6036 #elif TARGET_ABI_OPEN_VMS
6037 /* For VMS, we allocate space for all 6 arg registers plus a count.
6039 However, if NO registers need to be saved, don't allocate any space.
6040 This is not only because we won't need the space, but because AP
6041 includes the current_pretend_args_size and we don't want to mess up
6042 any ap-relative addresses already made. */
6043 if (cum
.num_args
< 6)
6047 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6048 emit_insn (gen_arg_home ());
6050 *pretend_size
= 7 * UNITS_PER_WORD
;
6053 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6054 only push those that are remaining. However, if NO registers need to
6055 be saved, don't allocate any space. This is not only because we won't
6056 need the space, but because AP includes the current_pretend_args_size
6057 and we don't want to mess up any ap-relative addresses already made.
6059 If we are not to use the floating-point registers, save the integer
6060 registers where we would put the floating-point registers. This is
6061 not the most efficient way to implement varargs with just one register
6062 class, but it isn't worth doing anything more efficient in this rare
6069 int count
, set
= get_varargs_alias_set ();
6072 count
= cfun
->va_list_gpr_size
/ UNITS_PER_WORD
;
6073 if (count
> 6 - cum
)
6076 /* Detect whether integer registers or floating-point registers
6077 are needed by the detected va_arg statements. See above for
6078 how these values are computed. Note that the "escape" value
6079 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
6081 gcc_assert ((VA_LIST_MAX_FPR_SIZE
& 3) == 3);
6083 if (cfun
->va_list_fpr_size
& 1)
6085 tmp
= gen_rtx_MEM (BLKmode
,
6086 plus_constant (virtual_incoming_args_rtx
,
6087 (cum
+ 6) * UNITS_PER_WORD
));
6088 MEM_NOTRAP_P (tmp
) = 1;
6089 set_mem_alias_set (tmp
, set
);
6090 move_block_from_reg (16 + cum
, tmp
, count
);
6093 if (cfun
->va_list_fpr_size
& 2)
6095 tmp
= gen_rtx_MEM (BLKmode
,
6096 plus_constant (virtual_incoming_args_rtx
,
6097 cum
* UNITS_PER_WORD
));
6098 MEM_NOTRAP_P (tmp
) = 1;
6099 set_mem_alias_set (tmp
, set
);
6100 move_block_from_reg (16 + cum
+ TARGET_FPREGS
*32, tmp
, count
);
6103 *pretend_size
= 12 * UNITS_PER_WORD
;
6108 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6110 HOST_WIDE_INT offset
;
6111 tree t
, offset_field
, base_field
;
6113 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6116 if (TARGET_ABI_UNICOSMK
)
6117 std_expand_builtin_va_start (valist
, nextarg
);
6119 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6120 up by 48, storing fp arg registers in the first 48 bytes, and the
6121 integer arg registers in the next 48 bytes. This is only done,
6122 however, if any integer registers need to be stored.
6124 If no integer registers need be stored, then we must subtract 48
6125 in order to account for the integer arg registers which are counted
6126 in argsize above, but which are not actually stored on the stack.
6127 Must further be careful here about structures straddling the last
6128 integer argument register; that futzes with pretend_args_size,
6129 which changes the meaning of AP. */
6132 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6134 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
6136 if (TARGET_ABI_OPEN_VMS
)
6138 nextarg
= plus_constant (nextarg
, offset
);
6139 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6140 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6141 make_tree (ptr_type_node
, nextarg
));
6142 TREE_SIDE_EFFECTS (t
) = 1;
6144 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6148 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6149 offset_field
= TREE_CHAIN (base_field
);
6151 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6152 valist
, base_field
, NULL_TREE
);
6153 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6154 valist
, offset_field
, NULL_TREE
);
6156 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6157 t
= build (PLUS_EXPR
, ptr_type_node
, t
,
6158 build_int_cst (NULL_TREE
, offset
));
6159 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6160 TREE_SIDE_EFFECTS (t
) = 1;
6161 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6163 t
= build_int_cst (NULL_TREE
, NUM_ARGS
* UNITS_PER_WORD
);
6164 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6165 TREE_SIDE_EFFECTS (t
) = 1;
6166 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6171 alpha_gimplify_va_arg_1 (tree type
, tree base
, tree offset
, tree
*pre_p
)
6173 tree type_size
, ptr_type
, addend
, t
, addr
, internal_post
;
6175 /* If the type could not be passed in registers, skip the block
6176 reserved for the registers. */
6177 if (targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
6179 t
= build_int_cst (TREE_TYPE (offset
), 6*8);
6180 t
= build (MODIFY_EXPR
, TREE_TYPE (offset
), offset
,
6181 build (MAX_EXPR
, TREE_TYPE (offset
), offset
, t
));
6182 gimplify_and_add (t
, pre_p
);
6186 ptr_type
= build_pointer_type (type
);
6188 if (TREE_CODE (type
) == COMPLEX_TYPE
)
6190 tree real_part
, imag_part
, real_temp
;
6192 real_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6195 /* Copy the value into a new temporary, lest the formal temporary
6196 be reused out from under us. */
6197 real_temp
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
6199 imag_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6202 return build (COMPLEX_EXPR
, type
, real_temp
, imag_part
);
6204 else if (TREE_CODE (type
) == REAL_TYPE
)
6206 tree fpaddend
, cond
, fourtyeight
;
6208 fourtyeight
= build_int_cst (TREE_TYPE (addend
), 6*8);
6209 fpaddend
= fold (build (MINUS_EXPR
, TREE_TYPE (addend
),
6210 addend
, fourtyeight
));
6211 cond
= fold (build (LT_EXPR
, boolean_type_node
, addend
, fourtyeight
));
6212 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6216 /* Build the final address and force that value into a temporary. */
6217 addr
= build (PLUS_EXPR
, ptr_type
, fold_convert (ptr_type
, base
),
6218 fold_convert (ptr_type
, addend
));
6219 internal_post
= NULL
;
6220 gimplify_expr (&addr
, pre_p
, &internal_post
, is_gimple_val
, fb_rvalue
);
6221 append_to_statement_list (internal_post
, pre_p
);
6223 /* Update the offset field. */
6224 type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
));
6225 if (type_size
== NULL
|| TREE_OVERFLOW (type_size
))
6229 t
= size_binop (PLUS_EXPR
, type_size
, size_int (7));
6230 t
= size_binop (TRUNC_DIV_EXPR
, t
, size_int (8));
6231 t
= size_binop (MULT_EXPR
, t
, size_int (8));
6233 t
= fold_convert (TREE_TYPE (offset
), t
);
6234 t
= build (MODIFY_EXPR
, void_type_node
, offset
,
6235 build (PLUS_EXPR
, TREE_TYPE (offset
), offset
, t
));
6236 gimplify_and_add (t
, pre_p
);
6238 return build_va_arg_indirect_ref (addr
);
6242 alpha_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
6244 tree offset_field
, base_field
, offset
, base
, t
, r
;
6247 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6248 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6250 base_field
= TYPE_FIELDS (va_list_type_node
);
6251 offset_field
= TREE_CHAIN (base_field
);
6252 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6253 valist
, base_field
, NULL_TREE
);
6254 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6255 valist
, offset_field
, NULL_TREE
);
6257 /* Pull the fields of the structure out into temporaries. Since we never
6258 modify the base field, we can use a formal temporary. Sign-extend the
6259 offset field so that it's the proper width for pointer arithmetic. */
6260 base
= get_formal_tmp_var (base_field
, pre_p
);
6262 t
= fold_convert (lang_hooks
.types
.type_for_size (64, 0), offset_field
);
6263 offset
= get_initialized_tmp_var (t
, pre_p
, NULL
);
6265 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6267 type
= build_pointer_type (type
);
6269 /* Find the value. Note that this will be a stable indirection, or
6270 a composite of stable indirections in the case of complex. */
6271 r
= alpha_gimplify_va_arg_1 (type
, base
, offset
, pre_p
);
6273 /* Stuff the offset temporary back into its field. */
6274 t
= build (MODIFY_EXPR
, void_type_node
, offset_field
,
6275 fold_convert (TREE_TYPE (offset_field
), offset
));
6276 gimplify_and_add (t
, pre_p
);
6279 r
= build_va_arg_indirect_ref (r
);
6288 ALPHA_BUILTIN_CMPBGE
,
6289 ALPHA_BUILTIN_EXTBL
,
6290 ALPHA_BUILTIN_EXTWL
,
6291 ALPHA_BUILTIN_EXTLL
,
6292 ALPHA_BUILTIN_EXTQL
,
6293 ALPHA_BUILTIN_EXTWH
,
6294 ALPHA_BUILTIN_EXTLH
,
6295 ALPHA_BUILTIN_EXTQH
,
6296 ALPHA_BUILTIN_INSBL
,
6297 ALPHA_BUILTIN_INSWL
,
6298 ALPHA_BUILTIN_INSLL
,
6299 ALPHA_BUILTIN_INSQL
,
6300 ALPHA_BUILTIN_INSWH
,
6301 ALPHA_BUILTIN_INSLH
,
6302 ALPHA_BUILTIN_INSQH
,
6303 ALPHA_BUILTIN_MSKBL
,
6304 ALPHA_BUILTIN_MSKWL
,
6305 ALPHA_BUILTIN_MSKLL
,
6306 ALPHA_BUILTIN_MSKQL
,
6307 ALPHA_BUILTIN_MSKWH
,
6308 ALPHA_BUILTIN_MSKLH
,
6309 ALPHA_BUILTIN_MSKQH
,
6310 ALPHA_BUILTIN_UMULH
,
6312 ALPHA_BUILTIN_ZAPNOT
,
6313 ALPHA_BUILTIN_AMASK
,
6314 ALPHA_BUILTIN_IMPLVER
,
6316 ALPHA_BUILTIN_THREAD_POINTER
,
6317 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6320 ALPHA_BUILTIN_MINUB8
,
6321 ALPHA_BUILTIN_MINSB8
,
6322 ALPHA_BUILTIN_MINUW4
,
6323 ALPHA_BUILTIN_MINSW4
,
6324 ALPHA_BUILTIN_MAXUB8
,
6325 ALPHA_BUILTIN_MAXSB8
,
6326 ALPHA_BUILTIN_MAXUW4
,
6327 ALPHA_BUILTIN_MAXSW4
,
6331 ALPHA_BUILTIN_UNPKBL
,
6332 ALPHA_BUILTIN_UNPKBW
,
6337 ALPHA_BUILTIN_CTPOP
,
6342 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6343 CODE_FOR_builtin_cmpbge
,
6344 CODE_FOR_builtin_extbl
,
6345 CODE_FOR_builtin_extwl
,
6346 CODE_FOR_builtin_extll
,
6347 CODE_FOR_builtin_extql
,
6348 CODE_FOR_builtin_extwh
,
6349 CODE_FOR_builtin_extlh
,
6350 CODE_FOR_builtin_extqh
,
6351 CODE_FOR_builtin_insbl
,
6352 CODE_FOR_builtin_inswl
,
6353 CODE_FOR_builtin_insll
,
6354 CODE_FOR_builtin_insql
,
6355 CODE_FOR_builtin_inswh
,
6356 CODE_FOR_builtin_inslh
,
6357 CODE_FOR_builtin_insqh
,
6358 CODE_FOR_builtin_mskbl
,
6359 CODE_FOR_builtin_mskwl
,
6360 CODE_FOR_builtin_mskll
,
6361 CODE_FOR_builtin_mskql
,
6362 CODE_FOR_builtin_mskwh
,
6363 CODE_FOR_builtin_msklh
,
6364 CODE_FOR_builtin_mskqh
,
6365 CODE_FOR_umuldi3_highpart
,
6366 CODE_FOR_builtin_zap
,
6367 CODE_FOR_builtin_zapnot
,
6368 CODE_FOR_builtin_amask
,
6369 CODE_FOR_builtin_implver
,
6370 CODE_FOR_builtin_rpcc
,
6375 CODE_FOR_builtin_minub8
,
6376 CODE_FOR_builtin_minsb8
,
6377 CODE_FOR_builtin_minuw4
,
6378 CODE_FOR_builtin_minsw4
,
6379 CODE_FOR_builtin_maxub8
,
6380 CODE_FOR_builtin_maxsb8
,
6381 CODE_FOR_builtin_maxuw4
,
6382 CODE_FOR_builtin_maxsw4
,
6383 CODE_FOR_builtin_perr
,
6384 CODE_FOR_builtin_pklb
,
6385 CODE_FOR_builtin_pkwb
,
6386 CODE_FOR_builtin_unpkbl
,
6387 CODE_FOR_builtin_unpkbw
,
6392 CODE_FOR_popcountdi2
6395 struct alpha_builtin_def
6398 enum alpha_builtin code
;
6399 unsigned int target_mask
;
6403 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6404 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0, true },
6405 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0, false }
6408 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6409 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0, true },
6410 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
, true },
6411 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
, true },
6412 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
, true },
6413 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
, true },
6414 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
, true },
6415 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
, true },
6416 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
, true }
6419 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6420 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0, true },
6421 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0, true },
6422 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0, true },
6423 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0, true },
6424 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0, true },
6425 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0, true },
6426 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0, true },
6427 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0, true },
6428 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0, true },
6429 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0, true },
6430 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0, true },
6431 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0, true },
6432 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0, true },
6433 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0, true },
6434 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0, true },
6435 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0, true },
6436 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0, true },
6437 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0, true },
6438 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0, true },
6439 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0, true },
6440 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0, true },
6441 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0, true },
6442 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0, true },
6443 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0, true },
6444 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0, true },
6445 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
, true },
6446 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
, true },
6447 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
, true },
6448 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
, true },
6449 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
, true },
6450 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
, true },
6451 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
, true },
6452 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
, true },
6453 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
, true }
6456 static GTY(()) tree alpha_v8qi_u
;
6457 static GTY(()) tree alpha_v8qi_s
;
6458 static GTY(()) tree alpha_v4hi_u
;
6459 static GTY(()) tree alpha_v4hi_s
;
6462 alpha_init_builtins (void)
6464 const struct alpha_builtin_def
*p
;
6465 tree ftype
, attrs
[2];
6468 attrs
[0] = tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
6469 attrs
[1] = tree_cons (get_identifier ("const"), NULL
, attrs
[0]);
6471 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6473 p
= zero_arg_builtins
;
6474 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6475 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6476 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6477 NULL
, attrs
[p
->is_const
]);
6479 ftype
= build_function_type_list (long_integer_type_node
,
6480 long_integer_type_node
, NULL_TREE
);
6482 p
= one_arg_builtins
;
6483 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6484 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6485 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6486 NULL
, attrs
[p
->is_const
]);
6488 ftype
= build_function_type_list (long_integer_type_node
,
6489 long_integer_type_node
,
6490 long_integer_type_node
, NULL_TREE
);
6492 p
= two_arg_builtins
;
6493 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6494 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6495 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6496 NULL
, attrs
[p
->is_const
]);
6498 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6499 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
6500 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6503 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6504 lang_hooks
.builtin_function ("__builtin_set_thread_pointer", ftype
,
6505 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6508 alpha_v8qi_u
= build_vector_type (unsigned_intQI_type_node
, 8);
6509 alpha_v8qi_s
= build_vector_type (intQI_type_node
, 8);
6510 alpha_v4hi_u
= build_vector_type (unsigned_intHI_type_node
, 4);
6511 alpha_v4hi_s
= build_vector_type (intHI_type_node
, 4);
6514 /* Expand an expression EXP that calls a built-in function,
6515 with result going to TARGET if that's convenient
6516 (and in mode MODE if that's convenient).
6517 SUBTARGET may be used as the target for computing one of EXP's operands.
6518 IGNORE is nonzero if the value is to be ignored. */
6521 alpha_expand_builtin (tree exp
, rtx target
,
6522 rtx subtarget ATTRIBUTE_UNUSED
,
6523 enum machine_mode mode ATTRIBUTE_UNUSED
,
6524 int ignore ATTRIBUTE_UNUSED
)
6528 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6529 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6530 tree arglist
= TREE_OPERAND (exp
, 1);
6531 enum insn_code icode
;
6532 rtx op
[MAX_ARGS
], pat
;
6536 if (fcode
>= ALPHA_BUILTIN_max
)
6537 internal_error ("bad builtin fcode");
6538 icode
= code_for_builtin
[fcode
];
6540 internal_error ("bad builtin fcode");
6542 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6544 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6546 arglist
= TREE_CHAIN (arglist
), arity
++)
6548 const struct insn_operand_data
*insn_op
;
6550 tree arg
= TREE_VALUE (arglist
);
6551 if (arg
== error_mark_node
)
6553 if (arity
> MAX_ARGS
)
6556 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6558 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6560 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6561 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6566 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6568 || GET_MODE (target
) != tmode
6569 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6570 target
= gen_reg_rtx (tmode
);
6576 pat
= GEN_FCN (icode
) (target
);
6580 pat
= GEN_FCN (icode
) (target
, op
[0]);
6582 pat
= GEN_FCN (icode
) (op
[0]);
6585 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6601 /* Several bits below assume HWI >= 64 bits. This should be enforced
6603 #if HOST_BITS_PER_WIDE_INT < 64
6604 # error "HOST_WIDE_INT too small"
6607 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6608 with an 8 bit output vector. OPINT contains the integer operands; bit N
6609 of OP_CONST is set if OPINT[N] is valid. */
6612 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint
[], long op_const
)
6617 for (i
= 0, val
= 0; i
< 8; ++i
)
6619 unsigned HOST_WIDE_INT c0
= (opint
[0] >> (i
* 8)) & 0xff;
6620 unsigned HOST_WIDE_INT c1
= (opint
[1] >> (i
* 8)) & 0xff;
6624 return build_int_cst (long_integer_type_node
, val
);
6626 else if (op_const
== 2 && opint
[1] == 0)
6627 return build_int_cst (long_integer_type_node
, 0xff);
6631 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6632 specialized form of an AND operation. Other byte manipulation instructions
6633 are defined in terms of this instruction, so this is also used as a
6634 subroutine for other builtins.
6636 OP contains the tree operands; OPINT contains the extracted integer values.
6637 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6638 OPINT may be considered. */
6641 alpha_fold_builtin_zapnot (tree
*op
, unsigned HOST_WIDE_INT opint
[],
6646 unsigned HOST_WIDE_INT mask
= 0;
6649 for (i
= 0; i
< 8; ++i
)
6650 if ((opint
[1] >> i
) & 1)
6651 mask
|= (unsigned HOST_WIDE_INT
)0xff << (i
* 8);
6654 return build_int_cst (long_integer_type_node
, opint
[0] & mask
);
6657 return fold (build2 (BIT_AND_EXPR
, long_integer_type_node
, op
[0],
6658 build_int_cst (long_integer_type_node
, mask
)));
6660 else if ((op_const
& 1) && opint
[0] == 0)
6661 return build_int_cst (long_integer_type_node
, 0);
6665 /* Fold the builtins for the EXT family of instructions. */
6668 alpha_fold_builtin_extxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6669 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6673 tree
*zap_op
= NULL
;
6677 unsigned HOST_WIDE_INT loc
;
6680 if (BYTES_BIG_ENDIAN
)
6688 unsigned HOST_WIDE_INT temp
= opint
[0];
6701 opint
[1] = bytemask
;
6702 return alpha_fold_builtin_zapnot (zap_op
, opint
, zap_const
);
6705 /* Fold the builtins for the INS family of instructions. */
6708 alpha_fold_builtin_insxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6709 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6712 if ((op_const
& 1) && opint
[0] == 0)
6713 return build_int_cst (long_integer_type_node
, 0);
6717 unsigned HOST_WIDE_INT temp
, loc
, byteloc
;
6718 tree
*zap_op
= NULL
;
6721 if (BYTES_BIG_ENDIAN
)
6728 byteloc
= (64 - (loc
* 8)) & 0x3f;
6745 opint
[1] = bytemask
;
6746 return alpha_fold_builtin_zapnot (zap_op
, opint
, op_const
);
6753 alpha_fold_builtin_mskxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6754 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6759 unsigned HOST_WIDE_INT loc
;
6762 if (BYTES_BIG_ENDIAN
)
6769 opint
[1] = bytemask
^ 0xff;
6772 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
6776 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint
[], long op_const
)
6782 unsigned HOST_WIDE_INT l
;
6785 mul_double (opint
[0], 0, opint
[1], 0, &l
, &h
);
6787 #if HOST_BITS_PER_WIDE_INT > 64
6791 return build_int_cst (long_integer_type_node
, h
);
6795 opint
[1] = opint
[0];
6798 /* Note that (X*1) >> 64 == 0. */
6799 if (opint
[1] == 0 || opint
[1] == 1)
6800 return build_int_cst (long_integer_type_node
, 0);
6807 alpha_fold_vector_minmax (enum tree_code code
, tree op
[], tree vtype
)
6809 tree op0
= fold_convert (vtype
, op
[0]);
6810 tree op1
= fold_convert (vtype
, op
[1]);
6811 tree val
= fold (build2 (code
, vtype
, op0
, op1
));
6812 return fold_convert (long_integer_type_node
, val
);
6816 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint
[], long op_const
)
6818 unsigned HOST_WIDE_INT temp
= 0;
6824 for (i
= 0; i
< 8; ++i
)
6826 unsigned HOST_WIDE_INT a
= (opint
[0] >> (i
* 8)) & 0xff;
6827 unsigned HOST_WIDE_INT b
= (opint
[1] >> (i
* 8)) & 0xff;
6834 return build_int_cst (long_integer_type_node
, temp
);
6838 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6840 unsigned HOST_WIDE_INT temp
;
6845 temp
= opint
[0] & 0xff;
6846 temp
|= (opint
[0] >> 24) & 0xff00;
6848 return build_int_cst (long_integer_type_node
, temp
);
6852 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6854 unsigned HOST_WIDE_INT temp
;
6859 temp
= opint
[0] & 0xff;
6860 temp
|= (opint
[0] >> 8) & 0xff00;
6861 temp
|= (opint
[0] >> 16) & 0xff0000;
6862 temp
|= (opint
[0] >> 24) & 0xff000000;
6864 return build_int_cst (long_integer_type_node
, temp
);
6868 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint
[], long op_const
)
6870 unsigned HOST_WIDE_INT temp
;
6875 temp
= opint
[0] & 0xff;
6876 temp
|= (opint
[0] & 0xff00) << 24;
6878 return build_int_cst (long_integer_type_node
, temp
);
6882 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint
[], long op_const
)
6884 unsigned HOST_WIDE_INT temp
;
6889 temp
= opint
[0] & 0xff;
6890 temp
|= (opint
[0] & 0x0000ff00) << 8;
6891 temp
|= (opint
[0] & 0x00ff0000) << 16;
6892 temp
|= (opint
[0] & 0xff000000) << 24;
6894 return build_int_cst (long_integer_type_node
, temp
);
6898 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6900 unsigned HOST_WIDE_INT temp
;
6908 temp
= exact_log2 (opint
[0] & -opint
[0]);
6910 return build_int_cst (long_integer_type_node
, temp
);
6914 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6916 unsigned HOST_WIDE_INT temp
;
6924 temp
= 64 - floor_log2 (opint
[0]) - 1;
6926 return build_int_cst (long_integer_type_node
, temp
);
6930 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint
[], long op_const
)
6932 unsigned HOST_WIDE_INT temp
, op
;
6940 temp
++, op
&= op
- 1;
6942 return build_int_cst (long_integer_type_node
, temp
);
6945 /* Fold one of our builtin functions. */
6948 alpha_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
6950 tree op
[MAX_ARGS
], t
;
6951 unsigned HOST_WIDE_INT opint
[MAX_ARGS
];
6952 long op_const
= 0, arity
= 0;
6954 for (t
= arglist
; t
; t
= TREE_CHAIN (t
), ++arity
)
6956 tree arg
= TREE_VALUE (t
);
6957 if (arg
== error_mark_node
)
6959 if (arity
>= MAX_ARGS
)
6964 if (TREE_CODE (arg
) == INTEGER_CST
)
6966 op_const
|= 1L << arity
;
6967 opint
[arity
] = int_cst_value (arg
);
6971 switch (DECL_FUNCTION_CODE (fndecl
))
6973 case ALPHA_BUILTIN_CMPBGE
:
6974 return alpha_fold_builtin_cmpbge (opint
, op_const
);
6976 case ALPHA_BUILTIN_EXTBL
:
6977 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x01, false);
6978 case ALPHA_BUILTIN_EXTWL
:
6979 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, false);
6980 case ALPHA_BUILTIN_EXTLL
:
6981 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, false);
6982 case ALPHA_BUILTIN_EXTQL
:
6983 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, false);
6984 case ALPHA_BUILTIN_EXTWH
:
6985 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, true);
6986 case ALPHA_BUILTIN_EXTLH
:
6987 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, true);
6988 case ALPHA_BUILTIN_EXTQH
:
6989 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, true);
6991 case ALPHA_BUILTIN_INSBL
:
6992 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x01, false);
6993 case ALPHA_BUILTIN_INSWL
:
6994 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, false);
6995 case ALPHA_BUILTIN_INSLL
:
6996 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, false);
6997 case ALPHA_BUILTIN_INSQL
:
6998 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, false);
6999 case ALPHA_BUILTIN_INSWH
:
7000 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, true);
7001 case ALPHA_BUILTIN_INSLH
:
7002 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, true);
7003 case ALPHA_BUILTIN_INSQH
:
7004 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, true);
7006 case ALPHA_BUILTIN_MSKBL
:
7007 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x01, false);
7008 case ALPHA_BUILTIN_MSKWL
:
7009 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, false);
7010 case ALPHA_BUILTIN_MSKLL
:
7011 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, false);
7012 case ALPHA_BUILTIN_MSKQL
:
7013 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, false);
7014 case ALPHA_BUILTIN_MSKWH
:
7015 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, true);
7016 case ALPHA_BUILTIN_MSKLH
:
7017 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, true);
7018 case ALPHA_BUILTIN_MSKQH
:
7019 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, true);
7021 case ALPHA_BUILTIN_UMULH
:
7022 return alpha_fold_builtin_umulh (opint
, op_const
);
7024 case ALPHA_BUILTIN_ZAP
:
7027 case ALPHA_BUILTIN_ZAPNOT
:
7028 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
7030 case ALPHA_BUILTIN_MINUB8
:
7031 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_u
);
7032 case ALPHA_BUILTIN_MINSB8
:
7033 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_s
);
7034 case ALPHA_BUILTIN_MINUW4
:
7035 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_u
);
7036 case ALPHA_BUILTIN_MINSW4
:
7037 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_s
);
7038 case ALPHA_BUILTIN_MAXUB8
:
7039 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_u
);
7040 case ALPHA_BUILTIN_MAXSB8
:
7041 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_s
);
7042 case ALPHA_BUILTIN_MAXUW4
:
7043 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_u
);
7044 case ALPHA_BUILTIN_MAXSW4
:
7045 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_s
);
7047 case ALPHA_BUILTIN_PERR
:
7048 return alpha_fold_builtin_perr (opint
, op_const
);
7049 case ALPHA_BUILTIN_PKLB
:
7050 return alpha_fold_builtin_pklb (opint
, op_const
);
7051 case ALPHA_BUILTIN_PKWB
:
7052 return alpha_fold_builtin_pkwb (opint
, op_const
);
7053 case ALPHA_BUILTIN_UNPKBL
:
7054 return alpha_fold_builtin_unpkbl (opint
, op_const
);
7055 case ALPHA_BUILTIN_UNPKBW
:
7056 return alpha_fold_builtin_unpkbw (opint
, op_const
);
7058 case ALPHA_BUILTIN_CTTZ
:
7059 return alpha_fold_builtin_cttz (opint
, op_const
);
7060 case ALPHA_BUILTIN_CTLZ
:
7061 return alpha_fold_builtin_ctlz (opint
, op_const
);
7062 case ALPHA_BUILTIN_CTPOP
:
7063 return alpha_fold_builtin_ctpop (opint
, op_const
);
7065 case ALPHA_BUILTIN_AMASK
:
7066 case ALPHA_BUILTIN_IMPLVER
:
7067 case ALPHA_BUILTIN_RPCC
:
7068 case ALPHA_BUILTIN_THREAD_POINTER
:
7069 case ALPHA_BUILTIN_SET_THREAD_POINTER
:
7070 /* None of these are foldable at compile-time. */
7076 /* This page contains routines that are used to determine what the function
7077 prologue and epilogue code will do and write them out. */
7079 /* Compute the size of the save area in the stack. */
7081 /* These variables are used for communication between the following functions.
7082 They indicate various things about the current function being compiled
7083 that are used to tell what kind of prologue, epilogue and procedure
7084 descriptor to generate. */
7086 /* Nonzero if we need a stack procedure. */
7087 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
7088 static enum alpha_procedure_types alpha_procedure_type
;
7090 /* Register number (either FP or SP) that is used to unwind the frame. */
7091 static int vms_unwind_regno
;
7093 /* Register number used to save FP. We need not have one for RA since
7094 we don't modify it for register procedures. This is only defined
7095 for register frame procedures. */
7096 static int vms_save_fp_regno
;
7098 /* Register number used to reference objects off our PV. */
7099 static int vms_base_regno
;
7101 /* Compute register masks for saved registers. */
7104 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
7106 unsigned long imask
= 0;
7107 unsigned long fmask
= 0;
7110 /* When outputting a thunk, we don't have valid register life info,
7111 but assemble_start_function wants to output .frame and .mask
7113 if (current_function_is_thunk
)
7120 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7121 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
7123 /* One for every register we have to save. */
7124 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7125 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
7126 && regs_ever_live
[i
] && i
!= REG_RA
7127 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
7130 imask
|= (1UL << i
);
7132 fmask
|= (1UL << (i
- 32));
7135 /* We need to restore these for the handler. */
7136 if (current_function_calls_eh_return
)
7140 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
7141 if (regno
== INVALID_REGNUM
)
7143 imask
|= 1UL << regno
;
7147 /* If any register spilled, then spill the return address also. */
7148 /* ??? This is required by the Digital stack unwind specification
7149 and isn't needed if we're doing Dwarf2 unwinding. */
7150 if (imask
|| fmask
|| alpha_ra_ever_killed ())
7151 imask
|= (1UL << REG_RA
);
7158 alpha_sa_size (void)
7160 unsigned long mask
[2];
7164 alpha_sa_mask (&mask
[0], &mask
[1]);
7166 if (TARGET_ABI_UNICOSMK
)
7168 if (mask
[0] || mask
[1])
7173 for (j
= 0; j
< 2; ++j
)
7174 for (i
= 0; i
< 32; ++i
)
7175 if ((mask
[j
] >> i
) & 1)
7179 if (TARGET_ABI_UNICOSMK
)
7181 /* We might not need to generate a frame if we don't make any calls
7182 (including calls to __T3E_MISMATCH if this is a vararg function),
7183 don't have any local variables which require stack slots, don't
7184 use alloca and have not determined that we need a frame for other
7187 alpha_procedure_type
7188 = (sa_size
|| get_frame_size() != 0
7189 || current_function_outgoing_args_size
7190 || current_function_stdarg
|| current_function_calls_alloca
7191 || frame_pointer_needed
)
7192 ? PT_STACK
: PT_REGISTER
;
7194 /* Always reserve space for saving callee-saved registers if we
7195 need a frame as required by the calling convention. */
7196 if (alpha_procedure_type
== PT_STACK
)
7199 else if (TARGET_ABI_OPEN_VMS
)
7201 /* Start by assuming we can use a register procedure if we don't
7202 make any calls (REG_RA not used) or need to save any
7203 registers and a stack procedure if we do. */
7204 if ((mask
[0] >> REG_RA
) & 1)
7205 alpha_procedure_type
= PT_STACK
;
7206 else if (get_frame_size() != 0)
7207 alpha_procedure_type
= PT_REGISTER
;
7209 alpha_procedure_type
= PT_NULL
;
7211 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7212 made the final decision on stack procedure vs register procedure. */
7213 if (alpha_procedure_type
== PT_STACK
)
7216 /* Decide whether to refer to objects off our PV via FP or PV.
7217 If we need FP for something else or if we receive a nonlocal
7218 goto (which expects PV to contain the value), we must use PV.
7219 Otherwise, start by assuming we can use FP. */
7222 = (frame_pointer_needed
7223 || current_function_has_nonlocal_label
7224 || alpha_procedure_type
== PT_STACK
7225 || current_function_outgoing_args_size
)
7226 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7228 /* If we want to copy PV into FP, we need to find some register
7229 in which to save FP. */
7231 vms_save_fp_regno
= -1;
7232 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7233 for (i
= 0; i
< 32; i
++)
7234 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
7235 vms_save_fp_regno
= i
;
7237 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7238 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7239 else if (alpha_procedure_type
== PT_NULL
)
7240 vms_base_regno
= REG_PV
;
7242 /* Stack unwinding should be done via FP unless we use it for PV. */
7243 vms_unwind_regno
= (vms_base_regno
== REG_PV
7244 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7246 /* If this is a stack procedure, allow space for saving FP and RA. */
7247 if (alpha_procedure_type
== PT_STACK
)
7252 /* Our size must be even (multiple of 16 bytes). */
7260 /* Define the offset between two registers, one to be eliminated,
7261 and the other its replacement, at the start of a routine. */
7264 alpha_initial_elimination_offset (unsigned int from
,
7265 unsigned int to ATTRIBUTE_UNUSED
)
7269 ret
= alpha_sa_size ();
7270 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
7274 case FRAME_POINTER_REGNUM
:
7277 case ARG_POINTER_REGNUM
:
7278 ret
+= (ALPHA_ROUND (get_frame_size ()
7279 + current_function_pretend_args_size
)
7280 - current_function_pretend_args_size
);
7291 alpha_pv_save_size (void)
7294 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7298 alpha_using_fp (void)
7301 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7304 #if TARGET_ABI_OPEN_VMS
7306 const struct attribute_spec vms_attribute_table
[] =
7308 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7309 { "overlaid", 0, 0, true, false, false, NULL
},
7310 { "global", 0, 0, true, false, false, NULL
},
7311 { "initialize", 0, 0, true, false, false, NULL
},
7312 { NULL
, 0, 0, false, false, false, NULL
}
7318 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
7320 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7324 alpha_find_lo_sum_using_gp (rtx insn
)
7326 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7330 alpha_does_function_need_gp (void)
7334 /* The GP being variable is an OSF abi thing. */
7335 if (! TARGET_ABI_OSF
)
7338 /* We need the gp to load the address of __mcount. */
7339 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7342 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7343 if (current_function_is_thunk
)
7346 /* The nonlocal receiver pattern assumes that the gp is valid for
7347 the nested function. Reasonable because it's almost always set
7348 correctly already. For the cases where that's wrong, make sure
7349 the nested function loads its gp on entry. */
7350 if (current_function_has_nonlocal_goto
)
7353 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7354 Even if we are a static function, we still need to do this in case
7355 our address is taken and passed to something like qsort. */
7357 push_topmost_sequence ();
7358 insn
= get_insns ();
7359 pop_topmost_sequence ();
7361 for (; insn
; insn
= NEXT_INSN (insn
))
7363 && GET_CODE (PATTERN (insn
)) != USE
7364 && GET_CODE (PATTERN (insn
)) != CLOBBER
7365 && get_attr_usegp (insn
))
7372 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7376 set_frame_related_p (void)
7378 rtx seq
= get_insns ();
7389 while (insn
!= NULL_RTX
)
7391 RTX_FRAME_RELATED_P (insn
) = 1;
7392 insn
= NEXT_INSN (insn
);
7394 seq
= emit_insn (seq
);
7398 seq
= emit_insn (seq
);
7399 RTX_FRAME_RELATED_P (seq
) = 1;
7404 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7406 /* Generates a store with the proper unwind info attached. VALUE is
7407 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7408 contains SP+FRAME_BIAS, and that is the unwind info that should be
7409 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7410 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7413 emit_frame_store_1 (rtx value
, rtx base_reg
, HOST_WIDE_INT frame_bias
,
7414 HOST_WIDE_INT base_ofs
, rtx frame_reg
)
7416 rtx addr
, mem
, insn
;
7418 addr
= plus_constant (base_reg
, base_ofs
);
7419 mem
= gen_rtx_MEM (DImode
, addr
);
7420 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7422 insn
= emit_move_insn (mem
, value
);
7423 RTX_FRAME_RELATED_P (insn
) = 1;
7425 if (frame_bias
|| value
!= frame_reg
)
7429 addr
= plus_constant (stack_pointer_rtx
, frame_bias
+ base_ofs
);
7430 mem
= gen_rtx_MEM (DImode
, addr
);
7434 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7435 gen_rtx_SET (VOIDmode
, mem
, frame_reg
),
7441 emit_frame_store (unsigned int regno
, rtx base_reg
,
7442 HOST_WIDE_INT frame_bias
, HOST_WIDE_INT base_ofs
)
7444 rtx reg
= gen_rtx_REG (DImode
, regno
);
7445 emit_frame_store_1 (reg
, base_reg
, frame_bias
, base_ofs
, reg
);
7448 /* Write function prologue. */
7450 /* On vms we have two kinds of functions:
7452 - stack frame (PROC_STACK)
7453 these are 'normal' functions with local vars and which are
7454 calling other functions
7455 - register frame (PROC_REGISTER)
7456 keeps all data in registers, needs no stack
7458 We must pass this to the assembler so it can generate the
7459 proper pdsc (procedure descriptor)
7460 This is done with the '.pdesc' command.
7462 On not-vms, we don't really differentiate between the two, as we can
7463 simply allocate stack without saving registers. */
7466 alpha_expand_prologue (void)
7468 /* Registers to save. */
7469 unsigned long imask
= 0;
7470 unsigned long fmask
= 0;
7471 /* Stack space needed for pushing registers clobbered by us. */
7472 HOST_WIDE_INT sa_size
;
7473 /* Complete stack size needed. */
7474 HOST_WIDE_INT frame_size
;
7475 /* Offset from base reg to register save area. */
7476 HOST_WIDE_INT reg_offset
;
7480 sa_size
= alpha_sa_size ();
7482 frame_size
= get_frame_size ();
7483 if (TARGET_ABI_OPEN_VMS
)
7484 frame_size
= ALPHA_ROUND (sa_size
7485 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7487 + current_function_pretend_args_size
);
7488 else if (TARGET_ABI_UNICOSMK
)
7489 /* We have to allocate space for the DSIB if we generate a frame. */
7490 frame_size
= ALPHA_ROUND (sa_size
7491 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7492 + ALPHA_ROUND (frame_size
7493 + current_function_outgoing_args_size
);
7495 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7497 + ALPHA_ROUND (frame_size
7498 + current_function_pretend_args_size
));
7500 if (TARGET_ABI_OPEN_VMS
)
7503 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7505 alpha_sa_mask (&imask
, &fmask
);
7507 /* Emit an insn to reload GP, if needed. */
7510 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7511 if (alpha_function_needs_gp
)
7512 emit_insn (gen_prologue_ldgp ());
7515 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7516 the call to mcount ourselves, rather than having the linker do it
7517 magically in response to -pg. Since _mcount has special linkage,
7518 don't represent the call as a call. */
7519 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7520 emit_insn (gen_prologue_mcount ());
7522 if (TARGET_ABI_UNICOSMK
)
7523 unicosmk_gen_dsib (&imask
);
7525 /* Adjust the stack by the frame size. If the frame size is > 4096
7526 bytes, we need to be sure we probe somewhere in the first and last
7527 4096 bytes (we can probably get away without the latter test) and
7528 every 8192 bytes in between. If the frame size is > 32768, we
7529 do this in a loop. Otherwise, we generate the explicit probe
7532 Note that we are only allowed to adjust sp once in the prologue. */
7534 if (frame_size
<= 32768)
7536 if (frame_size
> 4096)
7541 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7544 while ((probed
+= 8192) < frame_size
);
7546 /* We only have to do this probe if we aren't saving registers. */
7547 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7548 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7551 if (frame_size
!= 0)
7552 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7553 GEN_INT (TARGET_ABI_UNICOSMK
7559 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7560 number of 8192 byte blocks to probe. We then probe each block
7561 in the loop and then set SP to the proper location. If the
7562 amount remaining is > 4096, we have to do one more probe if we
7563 are not saving any registers. */
7565 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7566 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7567 rtx ptr
= gen_rtx_REG (DImode
, 22);
7568 rtx count
= gen_rtx_REG (DImode
, 23);
7571 emit_move_insn (count
, GEN_INT (blocks
));
7572 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7573 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7575 /* Because of the difficulty in emitting a new basic block this
7576 late in the compilation, generate the loop as a single insn. */
7577 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7579 if (leftover
> 4096 && sa_size
== 0)
7581 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7582 MEM_VOLATILE_P (last
) = 1;
7583 emit_move_insn (last
, const0_rtx
);
7586 if (TARGET_ABI_WINDOWS_NT
)
7588 /* For NT stack unwind (done by 'reverse execution'), it's
7589 not OK to take the result of a loop, even though the value
7590 is already in ptr, so we reload it via a single operation
7591 and subtract it to sp.
7593 Yes, that's correct -- we have to reload the whole constant
7594 into a temporary via ldah+lda then subtract from sp. */
7596 HOST_WIDE_INT lo
, hi
;
7597 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7598 hi
= frame_size
- lo
;
7600 emit_move_insn (ptr
, GEN_INT (hi
));
7601 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7602 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7607 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7608 GEN_INT (-leftover
)));
7611 /* This alternative is special, because the DWARF code cannot
7612 possibly intuit through the loop above. So we invent this
7613 note it looks at instead. */
7614 RTX_FRAME_RELATED_P (seq
) = 1;
7616 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7617 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7618 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7619 GEN_INT (TARGET_ABI_UNICOSMK
7625 if (!TARGET_ABI_UNICOSMK
)
7627 HOST_WIDE_INT sa_bias
= 0;
7629 /* Cope with very large offsets to the register save area. */
7630 sa_reg
= stack_pointer_rtx
;
7631 if (reg_offset
+ sa_size
> 0x8000)
7633 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7636 if (low
+ sa_size
<= 0x8000)
7637 sa_bias
= reg_offset
- low
, reg_offset
= low
;
7639 sa_bias
= reg_offset
, reg_offset
= 0;
7641 sa_reg
= gen_rtx_REG (DImode
, 24);
7642 sa_bias_rtx
= GEN_INT (sa_bias
);
7644 if (add_operand (sa_bias_rtx
, DImode
))
7645 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_bias_rtx
));
7648 emit_move_insn (sa_reg
, sa_bias_rtx
);
7649 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_reg
));
7653 /* Save regs in stack order. Beginning with VMS PV. */
7654 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7655 emit_frame_store (REG_PV
, stack_pointer_rtx
, 0, 0);
7657 /* Save register RA next. */
7658 if (imask
& (1UL << REG_RA
))
7660 emit_frame_store (REG_RA
, sa_reg
, sa_bias
, reg_offset
);
7661 imask
&= ~(1UL << REG_RA
);
7665 /* Now save any other registers required to be saved. */
7666 for (i
= 0; i
< 31; i
++)
7667 if (imask
& (1UL << i
))
7669 emit_frame_store (i
, sa_reg
, sa_bias
, reg_offset
);
7673 for (i
= 0; i
< 31; i
++)
7674 if (fmask
& (1UL << i
))
7676 emit_frame_store (i
+32, sa_reg
, sa_bias
, reg_offset
);
7680 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7682 /* The standard frame on the T3E includes space for saving registers.
7683 We just have to use it. We don't have to save the return address and
7684 the old frame pointer here - they are saved in the DSIB. */
7687 for (i
= 9; i
< 15; i
++)
7688 if (imask
& (1UL << i
))
7690 emit_frame_store (i
, hard_frame_pointer_rtx
, 0, reg_offset
);
7693 for (i
= 2; i
< 10; i
++)
7694 if (fmask
& (1UL << i
))
7696 emit_frame_store (i
+32, hard_frame_pointer_rtx
, 0, reg_offset
);
7701 if (TARGET_ABI_OPEN_VMS
)
7703 if (alpha_procedure_type
== PT_REGISTER
)
7704 /* Register frame procedures save the fp.
7705 ?? Ought to have a dwarf2 save for this. */
7706 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7707 hard_frame_pointer_rtx
);
7709 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7710 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7711 gen_rtx_REG (DImode
, REG_PV
)));
7713 if (alpha_procedure_type
!= PT_NULL
7714 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7715 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7717 /* If we have to allocate space for outgoing args, do it now. */
7718 if (current_function_outgoing_args_size
!= 0)
7721 = emit_move_insn (stack_pointer_rtx
,
7723 (hard_frame_pointer_rtx
,
7725 (current_function_outgoing_args_size
))));
7727 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7728 if ! frame_pointer_needed. Setting the bit will change the CFA
7729 computation rule to use sp again, which would be wrong if we had
7730 frame_pointer_needed, as this means sp might move unpredictably
7734 frame_pointer_needed
7735 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7737 current_function_outgoing_args_size != 0
7738 => alpha_procedure_type != PT_NULL,
7740 so when we are not setting the bit here, we are guaranteed to
7741 have emitted an FRP frame pointer update just before. */
7742 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7745 else if (!TARGET_ABI_UNICOSMK
)
7747 /* If we need a frame pointer, set it from the stack pointer. */
7748 if (frame_pointer_needed
)
7750 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7751 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7753 /* This must always be the last instruction in the
7754 prologue, thus we emit a special move + clobber. */
7755 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7756 stack_pointer_rtx
, sa_reg
)));
7760 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7761 the prologue, for exception handling reasons, we cannot do this for
7762 any insn that might fault. We could prevent this for mems with a
7763 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7764 have to prevent all such scheduling with a blockage.
7766 Linux, on the other hand, never bothered to implement OSF/1's
7767 exception handling, and so doesn't care about such things. Anyone
7768 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7770 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7771 emit_insn (gen_blockage ());
7774 /* Count the number of .file directives, so that .loc is up to date. */
7775 int num_source_filenames
= 0;
7777 /* Output the textual info surrounding the prologue. */
7780 alpha_start_function (FILE *file
, const char *fnname
,
7781 tree decl ATTRIBUTE_UNUSED
)
7783 unsigned long imask
= 0;
7784 unsigned long fmask
= 0;
7785 /* Stack space needed for pushing registers clobbered by us. */
7786 HOST_WIDE_INT sa_size
;
7787 /* Complete stack size needed. */
7788 unsigned HOST_WIDE_INT frame_size
;
7789 /* Offset from base reg to register save area. */
7790 HOST_WIDE_INT reg_offset
;
7791 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7794 /* Don't emit an extern directive for functions defined in the same file. */
7795 if (TARGET_ABI_UNICOSMK
)
7798 name_tree
= get_identifier (fnname
);
7799 TREE_ASM_WRITTEN (name_tree
) = 1;
7802 alpha_fnname
= fnname
;
7803 sa_size
= alpha_sa_size ();
7805 frame_size
= get_frame_size ();
7806 if (TARGET_ABI_OPEN_VMS
)
7807 frame_size
= ALPHA_ROUND (sa_size
7808 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7810 + current_function_pretend_args_size
);
7811 else if (TARGET_ABI_UNICOSMK
)
7812 frame_size
= ALPHA_ROUND (sa_size
7813 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7814 + ALPHA_ROUND (frame_size
7815 + current_function_outgoing_args_size
);
7817 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7819 + ALPHA_ROUND (frame_size
7820 + current_function_pretend_args_size
));
7822 if (TARGET_ABI_OPEN_VMS
)
7825 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7827 alpha_sa_mask (&imask
, &fmask
);
7829 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7830 We have to do that before the .ent directive as we cannot switch
7831 files within procedures with native ecoff because line numbers are
7832 linked to procedure descriptors.
7833 Outputting the lineno helps debugging of one line functions as they
7834 would otherwise get no line number at all. Please note that we would
7835 like to put out last_linenum from final.c, but it is not accessible. */
7837 if (write_symbols
== SDB_DEBUG
)
7839 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7840 ASM_OUTPUT_SOURCE_FILENAME (file
,
7841 DECL_SOURCE_FILE (current_function_decl
));
7843 #ifdef SDB_OUTPUT_SOURCE_LINE
7844 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7845 SDB_OUTPUT_SOURCE_LINE (file
,
7846 DECL_SOURCE_LINE (current_function_decl
));
7850 /* Issue function start and label. */
7851 if (TARGET_ABI_OPEN_VMS
7852 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7854 fputs ("\t.ent ", file
);
7855 assemble_name (file
, fnname
);
7858 /* If the function needs GP, we'll write the "..ng" label there.
7859 Otherwise, do it here. */
7861 && ! alpha_function_needs_gp
7862 && ! current_function_is_thunk
)
7865 assemble_name (file
, fnname
);
7866 fputs ("..ng:\n", file
);
7870 strcpy (entry_label
, fnname
);
7871 if (TARGET_ABI_OPEN_VMS
)
7872 strcat (entry_label
, "..en");
7874 /* For public functions, the label must be globalized by appending an
7875 additional colon. */
7876 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7877 strcat (entry_label
, ":");
7879 ASM_OUTPUT_LABEL (file
, entry_label
);
7880 inside_function
= TRUE
;
7882 if (TARGET_ABI_OPEN_VMS
)
7883 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7885 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7886 && !flag_inhibit_size_directive
)
7888 /* Set flags in procedure descriptor to request IEEE-conformant
7889 math-library routines. The value we set it to is PDSC_EXC_IEEE
7890 (/usr/include/pdsc.h). */
7891 fputs ("\t.eflag 48\n", file
);
7894 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7895 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7896 alpha_arg_offset
= -frame_size
+ 48;
7898 /* Describe our frame. If the frame size is larger than an integer,
7899 print it as zero to avoid an assembler error. We won't be
7900 properly describing such a frame, but that's the best we can do. */
7901 if (TARGET_ABI_UNICOSMK
)
7903 else if (TARGET_ABI_OPEN_VMS
)
7904 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7905 HOST_WIDE_INT_PRINT_DEC
"\n",
7907 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7909 else if (!flag_inhibit_size_directive
)
7910 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7911 (frame_pointer_needed
7912 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7913 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7914 current_function_pretend_args_size
);
7916 /* Describe which registers were spilled. */
7917 if (TARGET_ABI_UNICOSMK
)
7919 else if (TARGET_ABI_OPEN_VMS
)
7922 /* ??? Does VMS care if mask contains ra? The old code didn't
7923 set it, so I don't here. */
7924 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7926 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7927 if (alpha_procedure_type
== PT_REGISTER
)
7928 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7930 else if (!flag_inhibit_size_directive
)
7934 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7935 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7937 for (i
= 0; i
< 32; ++i
)
7938 if (imask
& (1UL << i
))
7943 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7944 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7947 #if TARGET_ABI_OPEN_VMS
7948 /* Ifdef'ed cause link_section are only available then. */
7949 readonly_data_section ();
7950 fprintf (file
, "\t.align 3\n");
7951 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7952 fputs ("\t.ascii \"", file
);
7953 assemble_name (file
, fnname
);
7954 fputs ("\\0\"\n", file
);
7955 alpha_need_linkage (fnname
, 1);
7960 /* Emit the .prologue note at the scheduled end of the prologue. */
7963 alpha_output_function_end_prologue (FILE *file
)
7965 if (TARGET_ABI_UNICOSMK
)
7967 else if (TARGET_ABI_OPEN_VMS
)
7968 fputs ("\t.prologue\n", file
);
7969 else if (TARGET_ABI_WINDOWS_NT
)
7970 fputs ("\t.prologue 0\n", file
);
7971 else if (!flag_inhibit_size_directive
)
7972 fprintf (file
, "\t.prologue %d\n",
7973 alpha_function_needs_gp
|| current_function_is_thunk
);
7976 /* Write function epilogue. */
7978 /* ??? At some point we will want to support full unwind, and so will
7979 need to mark the epilogue as well. At the moment, we just confuse
7982 #define FRP(exp) exp
7985 alpha_expand_epilogue (void)
7987 /* Registers to save. */
7988 unsigned long imask
= 0;
7989 unsigned long fmask
= 0;
7990 /* Stack space needed for pushing registers clobbered by us. */
7991 HOST_WIDE_INT sa_size
;
7992 /* Complete stack size needed. */
7993 HOST_WIDE_INT frame_size
;
7994 /* Offset from base reg to register save area. */
7995 HOST_WIDE_INT reg_offset
;
7996 int fp_is_frame_pointer
, fp_offset
;
7997 rtx sa_reg
, sa_reg_exp
= NULL
;
7998 rtx sp_adj1
, sp_adj2
, mem
;
8002 sa_size
= alpha_sa_size ();
8004 frame_size
= get_frame_size ();
8005 if (TARGET_ABI_OPEN_VMS
)
8006 frame_size
= ALPHA_ROUND (sa_size
8007 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
8009 + current_function_pretend_args_size
);
8010 else if (TARGET_ABI_UNICOSMK
)
8011 frame_size
= ALPHA_ROUND (sa_size
8012 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
8013 + ALPHA_ROUND (frame_size
8014 + current_function_outgoing_args_size
);
8016 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
8018 + ALPHA_ROUND (frame_size
8019 + current_function_pretend_args_size
));
8021 if (TARGET_ABI_OPEN_VMS
)
8023 if (alpha_procedure_type
== PT_STACK
)
8029 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
8031 alpha_sa_mask (&imask
, &fmask
);
8034 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
8035 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
8037 sa_reg
= stack_pointer_rtx
;
8039 if (current_function_calls_eh_return
)
8040 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
8044 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
8046 /* If we have a frame pointer, restore SP from it. */
8047 if ((TARGET_ABI_OPEN_VMS
8048 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
8049 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
8050 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
8052 /* Cope with very large offsets to the register save area. */
8053 if (reg_offset
+ sa_size
> 0x8000)
8055 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
8058 if (low
+ sa_size
<= 0x8000)
8059 bias
= reg_offset
- low
, reg_offset
= low
;
8061 bias
= reg_offset
, reg_offset
= 0;
8063 sa_reg
= gen_rtx_REG (DImode
, 22);
8064 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
8066 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
8069 /* Restore registers in order, excepting a true frame pointer. */
8071 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
8073 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8074 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
8077 imask
&= ~(1UL << REG_RA
);
8079 for (i
= 0; i
< 31; ++i
)
8080 if (imask
& (1UL << i
))
8082 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
8083 fp_offset
= reg_offset
;
8086 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
8087 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8088 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
8093 for (i
= 0; i
< 31; ++i
)
8094 if (fmask
& (1UL << i
))
8096 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
8097 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8098 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
8102 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
8104 /* Restore callee-saved general-purpose registers. */
8108 for (i
= 9; i
< 15; i
++)
8109 if (imask
& (1UL << i
))
8111 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
8113 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8114 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
8118 for (i
= 2; i
< 10; i
++)
8119 if (fmask
& (1UL << i
))
8121 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
8123 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8124 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
8128 /* Restore the return address from the DSIB. */
8130 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
8131 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8132 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
8135 if (frame_size
|| eh_ofs
)
8137 sp_adj1
= stack_pointer_rtx
;
8141 sp_adj1
= gen_rtx_REG (DImode
, 23);
8142 emit_move_insn (sp_adj1
,
8143 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
8146 /* If the stack size is large, begin computation into a temporary
8147 register so as not to interfere with a potential fp restore,
8148 which must be consecutive with an SP restore. */
8149 if (frame_size
< 32768
8150 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
8151 sp_adj2
= GEN_INT (frame_size
);
8152 else if (TARGET_ABI_UNICOSMK
)
8154 sp_adj1
= gen_rtx_REG (DImode
, 23);
8155 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
8156 sp_adj2
= const0_rtx
;
8158 else if (frame_size
< 0x40007fffL
)
8160 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
8162 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
8163 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
8167 sp_adj1
= gen_rtx_REG (DImode
, 23);
8168 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
8170 sp_adj2
= GEN_INT (low
);
8174 rtx tmp
= gen_rtx_REG (DImode
, 23);
8175 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
,
8179 /* We can't drop new things to memory this late, afaik,
8180 so build it up by pieces. */
8181 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
8182 -(frame_size
< 0)));
8183 gcc_assert (sp_adj2
);
8187 /* From now on, things must be in order. So emit blockages. */
8189 /* Restore the frame pointer. */
8190 if (TARGET_ABI_UNICOSMK
)
8192 emit_insn (gen_blockage ());
8193 mem
= gen_rtx_MEM (DImode
,
8194 plus_constant (hard_frame_pointer_rtx
, -16));
8195 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8196 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8198 else if (fp_is_frame_pointer
)
8200 emit_insn (gen_blockage ());
8201 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
8202 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8203 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8205 else if (TARGET_ABI_OPEN_VMS
)
8207 emit_insn (gen_blockage ());
8208 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8209 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8212 /* Restore the stack pointer. */
8213 emit_insn (gen_blockage ());
8214 if (sp_adj2
== const0_rtx
)
8215 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
8217 FRP (emit_move_insn (stack_pointer_rtx
,
8218 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
8222 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8224 emit_insn (gen_blockage ());
8225 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8226 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8228 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8230 /* Decrement the frame pointer if the function does not have a
8233 emit_insn (gen_blockage ());
8234 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8235 hard_frame_pointer_rtx
, constm1_rtx
)));
8240 /* Output the rest of the textual info surrounding the epilogue. */
8243 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
8245 #if TARGET_ABI_OPEN_VMS
8246 alpha_write_linkage (file
, fnname
, decl
);
8249 /* End the function. */
8250 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8252 fputs ("\t.end ", file
);
8253 assemble_name (file
, fnname
);
8256 inside_function
= FALSE
;
8258 /* Output jump tables and the static subroutine information block. */
8259 if (TARGET_ABI_UNICOSMK
)
8261 unicosmk_output_ssib (file
, fnname
);
8262 unicosmk_output_deferred_case_vectors (file
);
8267 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8269 In order to avoid the hordes of differences between generated code
8270 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8271 lots of code loading up large constants, generate rtl and emit it
8272 instead of going straight to text.
8274 Not sure why this idea hasn't been explored before... */
8277 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8278 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8281 HOST_WIDE_INT hi
, lo
;
8282 rtx
this, insn
, funexp
;
8284 reset_block_changes ();
8286 /* We always require a valid GP. */
8287 emit_insn (gen_prologue_ldgp ());
8288 emit_note (NOTE_INSN_PROLOGUE_END
);
8290 /* Find the "this" pointer. If the function returns a structure,
8291 the structure return pointer is in $16. */
8292 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8293 this = gen_rtx_REG (Pmode
, 17);
8295 this = gen_rtx_REG (Pmode
, 16);
8297 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8298 entire constant for the add. */
8299 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8300 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8301 if (hi
+ lo
== delta
)
8304 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
8306 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
8310 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8311 delta
, -(delta
< 0));
8312 emit_insn (gen_adddi3 (this, this, tmp
));
8315 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8320 tmp
= gen_rtx_REG (Pmode
, 0);
8321 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8323 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8324 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8325 if (hi
+ lo
== vcall_offset
)
8328 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8332 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8333 vcall_offset
, -(vcall_offset
< 0));
8334 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8338 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8341 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8343 emit_insn (gen_adddi3 (this, this, tmp
));
8346 /* Generate a tail call to the target function. */
8347 if (! TREE_USED (function
))
8349 assemble_external (function
);
8350 TREE_USED (function
) = 1;
8352 funexp
= XEXP (DECL_RTL (function
), 0);
8353 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8354 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8355 SIBLING_CALL_P (insn
) = 1;
8357 /* Run just enough of rest_of_compilation to get the insns emitted.
8358 There's not really enough bulk here to make other passes such as
8359 instruction scheduling worth while. Note that use_thunk calls
8360 assemble_start_function and assemble_end_function. */
8361 insn
= get_insns ();
8362 insn_locators_initialize ();
8363 shorten_branches (insn
);
8364 final_start_function (insn
, file
, 1);
8365 final (insn
, file
, 1);
8366 final_end_function ();
8368 #endif /* TARGET_ABI_OSF */
8370 /* Debugging support. */
8374 /* Count the number of sdb related labels are generated (to find block
8375 start and end boundaries). */
8377 int sdb_label_count
= 0;
8379 /* Name of the file containing the current function. */
8381 static const char *current_function_file
= "";
8383 /* Offsets to alpha virtual arg/local debugging pointers. */
8385 long alpha_arg_offset
;
8386 long alpha_auto_offset
;
8388 /* Emit a new filename to a stream. */
8391 alpha_output_filename (FILE *stream
, const char *name
)
8393 static int first_time
= TRUE
;
8398 ++num_source_filenames
;
8399 current_function_file
= name
;
8400 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8401 output_quoted_string (stream
, name
);
8402 fprintf (stream
, "\n");
8403 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8404 fprintf (stream
, "\t#@stabs\n");
8407 else if (write_symbols
== DBX_DEBUG
)
8408 /* dbxout.c will emit an appropriate .stabs directive. */
8411 else if (name
!= current_function_file
8412 && strcmp (name
, current_function_file
) != 0)
8414 if (inside_function
&& ! TARGET_GAS
)
8415 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8418 ++num_source_filenames
;
8419 current_function_file
= name
;
8420 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8423 output_quoted_string (stream
, name
);
8424 fprintf (stream
, "\n");
8428 /* Structure to show the current status of registers and memory. */
8430 struct shadow_summary
8433 unsigned int i
: 31; /* Mask of int regs */
8434 unsigned int fp
: 31; /* Mask of fp regs */
8435 unsigned int mem
: 1; /* mem == imem | fpmem */
8439 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8440 to the summary structure. SET is nonzero if the insn is setting the
8441 object, otherwise zero. */
8444 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8446 const char *format_ptr
;
8452 switch (GET_CODE (x
))
8454 /* ??? Note that this case would be incorrect if the Alpha had a
8455 ZERO_EXTRACT in SET_DEST. */
8457 summarize_insn (SET_SRC (x
), sum
, 0);
8458 summarize_insn (SET_DEST (x
), sum
, 1);
8462 summarize_insn (XEXP (x
, 0), sum
, 1);
8466 summarize_insn (XEXP (x
, 0), sum
, 0);
8470 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8471 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8475 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8476 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8480 summarize_insn (SUBREG_REG (x
), sum
, 0);
8485 int regno
= REGNO (x
);
8486 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8488 if (regno
== 31 || regno
== 63)
8494 sum
->defd
.i
|= mask
;
8496 sum
->defd
.fp
|= mask
;
8501 sum
->used
.i
|= mask
;
8503 sum
->used
.fp
|= mask
;
8514 /* Find the regs used in memory address computation: */
8515 summarize_insn (XEXP (x
, 0), sum
, 0);
8518 case CONST_INT
: case CONST_DOUBLE
:
8519 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8520 case SCRATCH
: case ASM_INPUT
:
8523 /* Handle common unary and binary ops for efficiency. */
8524 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8525 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8526 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8527 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8528 case NE
: case EQ
: case GE
: case GT
: case LE
:
8529 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8530 summarize_insn (XEXP (x
, 0), sum
, 0);
8531 summarize_insn (XEXP (x
, 1), sum
, 0);
8534 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8535 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8536 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8537 case SQRT
: case FFS
:
8538 summarize_insn (XEXP (x
, 0), sum
, 0);
8542 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8543 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8544 switch (format_ptr
[i
])
8547 summarize_insn (XEXP (x
, i
), sum
, 0);
8551 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8552 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8564 /* Ensure a sufficient number of `trapb' insns are in the code when
8565 the user requests code with a trap precision of functions or
8568 In naive mode, when the user requests a trap-precision of
8569 "instruction", a trapb is needed after every instruction that may
8570 generate a trap. This ensures that the code is resumption safe but
8573 When optimizations are turned on, we delay issuing a trapb as long
8574 as possible. In this context, a trap shadow is the sequence of
8575 instructions that starts with a (potentially) trap generating
8576 instruction and extends to the next trapb or call_pal instruction
8577 (but GCC never generates call_pal by itself). We can delay (and
8578 therefore sometimes omit) a trapb subject to the following
8581 (a) On entry to the trap shadow, if any Alpha register or memory
8582 location contains a value that is used as an operand value by some
8583 instruction in the trap shadow (live on entry), then no instruction
8584 in the trap shadow may modify the register or memory location.
8586 (b) Within the trap shadow, the computation of the base register
8587 for a memory load or store instruction may not involve using the
8588 result of an instruction that might generate an UNPREDICTABLE
8591 (c) Within the trap shadow, no register may be used more than once
8592 as a destination register. (This is to make life easier for the
8595 (d) The trap shadow may not include any branch instructions. */
8598 alpha_handle_trap_shadows (void)
8600 struct shadow_summary shadow
;
8601 int trap_pending
, exception_nesting
;
8605 exception_nesting
= 0;
8608 shadow
.used
.mem
= 0;
8609 shadow
.defd
= shadow
.used
;
8611 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8613 if (GET_CODE (i
) == NOTE
)
8615 switch (NOTE_LINE_NUMBER (i
))
8617 case NOTE_INSN_EH_REGION_BEG
:
8618 exception_nesting
++;
8623 case NOTE_INSN_EH_REGION_END
:
8624 exception_nesting
--;
8629 case NOTE_INSN_EPILOGUE_BEG
:
8630 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8635 else if (trap_pending
)
8637 if (alpha_tp
== ALPHA_TP_FUNC
)
8639 if (GET_CODE (i
) == JUMP_INSN
8640 && GET_CODE (PATTERN (i
)) == RETURN
)
8643 else if (alpha_tp
== ALPHA_TP_INSN
)
8647 struct shadow_summary sum
;
8652 sum
.defd
= sum
.used
;
8654 switch (GET_CODE (i
))
8657 /* Annoyingly, get_attr_trap will die on these. */
8658 if (GET_CODE (PATTERN (i
)) == USE
8659 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8662 summarize_insn (PATTERN (i
), &sum
, 0);
8664 if ((sum
.defd
.i
& shadow
.defd
.i
)
8665 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8667 /* (c) would be violated */
8671 /* Combine shadow with summary of current insn: */
8672 shadow
.used
.i
|= sum
.used
.i
;
8673 shadow
.used
.fp
|= sum
.used
.fp
;
8674 shadow
.used
.mem
|= sum
.used
.mem
;
8675 shadow
.defd
.i
|= sum
.defd
.i
;
8676 shadow
.defd
.fp
|= sum
.defd
.fp
;
8677 shadow
.defd
.mem
|= sum
.defd
.mem
;
8679 if ((sum
.defd
.i
& shadow
.used
.i
)
8680 || (sum
.defd
.fp
& shadow
.used
.fp
)
8681 || (sum
.defd
.mem
& shadow
.used
.mem
))
8683 /* (a) would be violated (also takes care of (b)) */
8684 gcc_assert (get_attr_trap (i
) != TRAP_YES
8685 || (!(sum
.defd
.i
& sum
.used
.i
)
8686 && !(sum
.defd
.fp
& sum
.used
.fp
)));
8704 n
= emit_insn_before (gen_trapb (), i
);
8705 PUT_MODE (n
, TImode
);
8706 PUT_MODE (i
, TImode
);
8710 shadow
.used
.mem
= 0;
8711 shadow
.defd
= shadow
.used
;
8716 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8717 && GET_CODE (i
) == INSN
8718 && GET_CODE (PATTERN (i
)) != USE
8719 && GET_CODE (PATTERN (i
)) != CLOBBER
8720 && get_attr_trap (i
) == TRAP_YES
)
8722 if (optimize
&& !trap_pending
)
8723 summarize_insn (PATTERN (i
), &shadow
, 0);
8729 /* Alpha can only issue instruction groups simultaneously if they are
8730 suitably aligned. This is very processor-specific. */
8731 /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe
8732 that are marked "fake". These instructions do not exist on that target,
8733 but it is possible to see these insns with deranged combinations of
8734 command-line options, such as "-mtune=ev4 -mmax". Instead of aborting,
8735 choose a result at random. */
8737 enum alphaev4_pipe
{
8744 enum alphaev5_pipe
{
8755 static enum alphaev4_pipe
8756 alphaev4_insn_pipe (rtx insn
)
8758 if (recog_memoized (insn
) < 0)
8760 if (get_attr_length (insn
) != 4)
8763 switch (get_attr_type (insn
))
8779 case TYPE_MVI
: /* fake */
8794 case TYPE_FSQRT
: /* fake */
8795 case TYPE_FTOI
: /* fake */
8796 case TYPE_ITOF
: /* fake */
8804 static enum alphaev5_pipe
8805 alphaev5_insn_pipe (rtx insn
)
8807 if (recog_memoized (insn
) < 0)
8809 if (get_attr_length (insn
) != 4)
8812 switch (get_attr_type (insn
))
8832 case TYPE_FTOI
: /* fake */
8833 case TYPE_ITOF
: /* fake */
8848 case TYPE_FSQRT
: /* fake */
8859 /* IN_USE is a mask of the slots currently filled within the insn group.
8860 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8861 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8863 LEN is, of course, the length of the group in bytes. */
8866 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8873 || GET_CODE (PATTERN (insn
)) == CLOBBER
8874 || GET_CODE (PATTERN (insn
)) == USE
)
8879 enum alphaev4_pipe pipe
;
8881 pipe
= alphaev4_insn_pipe (insn
);
8885 /* Force complex instructions to start new groups. */
8889 /* If this is a completely unrecognized insn, it's an asm.
8890 We don't know how long it is, so record length as -1 to
8891 signal a needed realignment. */
8892 if (recog_memoized (insn
) < 0)
8895 len
= get_attr_length (insn
);
8899 if (in_use
& EV4_IB0
)
8901 if (in_use
& EV4_IB1
)
8906 in_use
|= EV4_IB0
| EV4_IBX
;
8910 if (in_use
& EV4_IB0
)
8912 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8920 if (in_use
& EV4_IB1
)
8930 /* Haifa doesn't do well scheduling branches. */
8931 if (GET_CODE (insn
) == JUMP_INSN
)
8935 insn
= next_nonnote_insn (insn
);
8937 if (!insn
|| ! INSN_P (insn
))
8940 /* Let Haifa tell us where it thinks insn group boundaries are. */
8941 if (GET_MODE (insn
) == TImode
)
8944 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8949 insn
= next_nonnote_insn (insn
);
8957 /* IN_USE is a mask of the slots currently filled within the insn group.
8958 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8959 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8961 LEN is, of course, the length of the group in bytes. */
8964 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8971 || GET_CODE (PATTERN (insn
)) == CLOBBER
8972 || GET_CODE (PATTERN (insn
)) == USE
)
8977 enum alphaev5_pipe pipe
;
8979 pipe
= alphaev5_insn_pipe (insn
);
8983 /* Force complex instructions to start new groups. */
8987 /* If this is a completely unrecognized insn, it's an asm.
8988 We don't know how long it is, so record length as -1 to
8989 signal a needed realignment. */
8990 if (recog_memoized (insn
) < 0)
8993 len
= get_attr_length (insn
);
8996 /* ??? Most of the places below, we would like to assert never
8997 happen, as it would indicate an error either in Haifa, or
8998 in the scheduling description. Unfortunately, Haifa never
8999 schedules the last instruction of the BB, so we don't have
9000 an accurate TI bit to go off. */
9002 if (in_use
& EV5_E0
)
9004 if (in_use
& EV5_E1
)
9009 in_use
|= EV5_E0
| EV5_E01
;
9013 if (in_use
& EV5_E0
)
9015 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
9023 if (in_use
& EV5_E1
)
9029 if (in_use
& EV5_FA
)
9031 if (in_use
& EV5_FM
)
9036 in_use
|= EV5_FA
| EV5_FAM
;
9040 if (in_use
& EV5_FA
)
9046 if (in_use
& EV5_FM
)
9059 /* Haifa doesn't do well scheduling branches. */
9060 /* ??? If this is predicted not-taken, slotting continues, except
9061 that no more IBR, FBR, or JSR insns may be slotted. */
9062 if (GET_CODE (insn
) == JUMP_INSN
)
9066 insn
= next_nonnote_insn (insn
);
9068 if (!insn
|| ! INSN_P (insn
))
9071 /* Let Haifa tell us where it thinks insn group boundaries are. */
9072 if (GET_MODE (insn
) == TImode
)
9075 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9080 insn
= next_nonnote_insn (insn
);
9089 alphaev4_next_nop (int *pin_use
)
9091 int in_use
= *pin_use
;
9094 if (!(in_use
& EV4_IB0
))
9099 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
9104 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
9117 alphaev5_next_nop (int *pin_use
)
9119 int in_use
= *pin_use
;
9122 if (!(in_use
& EV5_E1
))
9127 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
9132 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
9144 /* The instruction group alignment main loop. */
9147 alpha_align_insns (unsigned int max_align
,
9148 rtx (*next_group
) (rtx
, int *, int *),
9149 rtx (*next_nop
) (int *))
9151 /* ALIGN is the known alignment for the insn group. */
9153 /* OFS is the offset of the current insn in the insn group. */
9155 int prev_in_use
, in_use
, len
, ldgp
;
9158 /* Let shorten branches care for assigning alignments to code labels. */
9159 shorten_branches (get_insns ());
9161 if (align_functions
< 4)
9163 else if ((unsigned int) align_functions
< max_align
)
9164 align
= align_functions
;
9168 ofs
= prev_in_use
= 0;
9170 if (GET_CODE (i
) == NOTE
)
9171 i
= next_nonnote_insn (i
);
9173 ldgp
= alpha_function_needs_gp
? 8 : 0;
9177 next
= (*next_group
) (i
, &in_use
, &len
);
9179 /* When we see a label, resync alignment etc. */
9180 if (GET_CODE (i
) == CODE_LABEL
)
9182 unsigned int new_align
= 1 << label_to_alignment (i
);
9184 if (new_align
>= align
)
9186 align
= new_align
< max_align
? new_align
: max_align
;
9190 else if (ofs
& (new_align
-1))
9191 ofs
= (ofs
| (new_align
-1)) + 1;
9195 /* Handle complex instructions special. */
9196 else if (in_use
== 0)
9198 /* Asms will have length < 0. This is a signal that we have
9199 lost alignment knowledge. Assume, however, that the asm
9200 will not mis-align instructions. */
9209 /* If the known alignment is smaller than the recognized insn group,
9210 realign the output. */
9211 else if ((int) align
< len
)
9213 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9216 where
= prev
= prev_nonnote_insn (i
);
9217 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
9220 /* Can't realign between a call and its gp reload. */
9221 if (! (TARGET_EXPLICIT_RELOCS
9222 && prev
&& GET_CODE (prev
) == CALL_INSN
))
9224 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9225 align
= 1 << new_log_align
;
9230 /* We may not insert padding inside the initial ldgp sequence. */
9234 /* If the group won't fit in the same INT16 as the previous,
9235 we need to add padding to keep the group together. Rather
9236 than simply leaving the insn filling to the assembler, we
9237 can make use of the knowledge of what sorts of instructions
9238 were issued in the previous group to make sure that all of
9239 the added nops are really free. */
9240 else if (ofs
+ len
> (int) align
)
9242 int nop_count
= (align
- ofs
) / 4;
9245 /* Insert nops before labels, branches, and calls to truly merge
9246 the execution of the nops with the previous instruction group. */
9247 where
= prev_nonnote_insn (i
);
9250 if (GET_CODE (where
) == CODE_LABEL
)
9252 rtx where2
= prev_nonnote_insn (where
);
9253 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
9256 else if (GET_CODE (where
) == INSN
)
9263 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9264 while (--nop_count
);
9268 ofs
= (ofs
+ len
) & (align
- 1);
9269 prev_in_use
= in_use
;
9274 /* Machine dependent reorg pass. */
9279 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9280 alpha_handle_trap_shadows ();
9282 /* Due to the number of extra trapb insns, don't bother fixing up
9283 alignment when trap precision is instruction. Moreover, we can
9284 only do our job when sched2 is run. */
9285 if (optimize
&& !optimize_size
9286 && alpha_tp
!= ALPHA_TP_INSN
9287 && flag_schedule_insns_after_reload
)
9289 if (alpha_tune
== PROCESSOR_EV4
)
9290 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
9291 else if (alpha_tune
== PROCESSOR_EV5
)
9292 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
9296 #if !TARGET_ABI_UNICOSMK
9303 alpha_file_start (void)
9305 #ifdef OBJECT_FORMAT_ELF
9306 /* If emitting dwarf2 debug information, we cannot generate a .file
9307 directive to start the file, as it will conflict with dwarf2out
9308 file numbers. So it's only useful when emitting mdebug output. */
9309 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
9312 default_file_start ();
9314 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
9317 fputs ("\t.set noreorder\n", asm_out_file
);
9318 fputs ("\t.set volatile\n", asm_out_file
);
9319 if (!TARGET_ABI_OPEN_VMS
)
9320 fputs ("\t.set noat\n", asm_out_file
);
9321 if (TARGET_EXPLICIT_RELOCS
)
9322 fputs ("\t.set nomacro\n", asm_out_file
);
9323 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
9327 if (alpha_cpu
== PROCESSOR_EV6
|| TARGET_FIX
|| TARGET_CIX
)
9329 else if (TARGET_MAX
)
9331 else if (TARGET_BWX
)
9333 else if (alpha_cpu
== PROCESSOR_EV5
)
9338 fprintf (asm_out_file
, "\t.arch %s\n", arch
);
9343 #ifdef OBJECT_FORMAT_ELF
9345 /* Switch to the section to which we should output X. The only thing
9346 special we do here is to honor small data. */
9349 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
9350 unsigned HOST_WIDE_INT align
)
9352 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9353 /* ??? Consider using mergeable sdata sections. */
9356 default_elf_select_rtx_section (mode
, x
, align
);
9359 #endif /* OBJECT_FORMAT_ELF */
9361 /* Structure to collect function names for final output in link section. */
9362 /* Note that items marked with GTY can't be ifdef'ed out. */
9364 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9365 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9367 struct alpha_links
GTY(())
9371 enum links_kind lkind
;
9372 enum reloc_kind rkind
;
9375 struct alpha_funcs
GTY(())
9378 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9382 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9383 splay_tree alpha_links_tree
;
9384 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9385 splay_tree alpha_funcs_tree
;
9387 static GTY(()) int alpha_funcs_num
;
9389 #if TARGET_ABI_OPEN_VMS
9391 /* Return the VMS argument type corresponding to MODE. */
9394 alpha_arg_type (enum machine_mode mode
)
9399 return TARGET_FLOAT_VAX
? FF
: FS
;
9401 return TARGET_FLOAT_VAX
? FD
: FT
;
9407 /* Return an rtx for an integer representing the VMS Argument Information
9411 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9413 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9416 for (i
= 0; i
< 6; i
++)
9417 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9419 return GEN_INT (regval
);
9422 /* Make (or fake) .linkage entry for function call.
9424 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9426 Return an SYMBOL_REF rtx for the linkage. */
9429 alpha_need_linkage (const char *name
, int is_local
)
9431 splay_tree_node node
;
9432 struct alpha_links
*al
;
9439 struct alpha_funcs
*cfaf
;
9441 if (!alpha_funcs_tree
)
9442 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9443 splay_tree_compare_pointers
);
9445 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9448 cfaf
->num
= ++alpha_funcs_num
;
9450 splay_tree_insert (alpha_funcs_tree
,
9451 (splay_tree_key
) current_function_decl
,
9452 (splay_tree_value
) cfaf
);
9455 if (alpha_links_tree
)
9457 /* Is this name already defined? */
9459 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9462 al
= (struct alpha_links
*) node
->value
;
9465 /* Defined here but external assumed. */
9466 if (al
->lkind
== KIND_EXTERN
)
9467 al
->lkind
= KIND_LOCAL
;
9471 /* Used here but unused assumed. */
9472 if (al
->lkind
== KIND_UNUSED
)
9473 al
->lkind
= KIND_LOCAL
;
9479 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9481 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9482 name
= ggc_strdup (name
);
9484 /* Assume external if no definition. */
9485 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9487 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9488 get_identifier (name
);
9490 /* Construct a SYMBOL_REF for us to call. */
9492 size_t name_len
= strlen (name
);
9493 char *linksym
= alloca (name_len
+ 6);
9495 memcpy (linksym
+ 1, name
, name_len
);
9496 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9497 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9498 ggc_alloc_string (linksym
, name_len
+ 5));
9501 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9502 (splay_tree_value
) al
);
9508 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9510 splay_tree_node cfunnode
;
9511 struct alpha_funcs
*cfaf
;
9512 struct alpha_links
*al
;
9513 const char *name
= XSTR (linkage
, 0);
9515 cfaf
= (struct alpha_funcs
*) 0;
9516 al
= (struct alpha_links
*) 0;
9518 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9519 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9523 splay_tree_node lnode
;
9525 /* Is this name already defined? */
9527 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9529 al
= (struct alpha_links
*) lnode
->value
;
9532 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9540 splay_tree_node node
= 0;
9541 struct alpha_links
*anl
;
9546 name_len
= strlen (name
);
9548 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9549 al
->num
= cfaf
->num
;
9551 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9554 anl
= (struct alpha_links
*) node
->value
;
9555 al
->lkind
= anl
->lkind
;
9558 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9559 buflen
= strlen (buf
);
9560 linksym
= alloca (buflen
+ 1);
9561 memcpy (linksym
, buf
, buflen
+ 1);
9563 al
->linkage
= gen_rtx_SYMBOL_REF
9564 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9566 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9567 (splay_tree_value
) al
);
9571 al
->rkind
= KIND_CODEADDR
;
9573 al
->rkind
= KIND_LINKAGE
;
9576 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9582 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9584 const char *const name
= (const char *) node
->key
;
9585 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9586 FILE *stream
= (FILE *) data
;
9588 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9589 if (link
->rkind
== KIND_CODEADDR
)
9591 if (link
->lkind
== KIND_LOCAL
)
9593 /* Local and used */
9594 fprintf (stream
, "\t.quad %s..en\n", name
);
9598 /* External and used, request code address. */
9599 fprintf (stream
, "\t.code_address %s\n", name
);
9604 if (link
->lkind
== KIND_LOCAL
)
9606 /* Local and used, build linkage pair. */
9607 fprintf (stream
, "\t.quad %s..en\n", name
);
9608 fprintf (stream
, "\t.quad %s\n", name
);
9612 /* External and used, request linkage pair. */
9613 fprintf (stream
, "\t.linkage %s\n", name
);
9621 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9623 splay_tree_node node
;
9624 struct alpha_funcs
*func
;
9627 fprintf (stream
, "\t.align 3\n");
9628 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9629 func
= (struct alpha_funcs
*) node
->value
;
9631 fputs ("\t.name ", stream
);
9632 assemble_name (stream
, funname
);
9633 fputs ("..na\n", stream
);
9634 ASM_OUTPUT_LABEL (stream
, funname
);
9635 fprintf (stream
, "\t.pdesc ");
9636 assemble_name (stream
, funname
);
9637 fprintf (stream
, "..en,%s\n",
9638 alpha_procedure_type
== PT_STACK
? "stack"
9639 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9643 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9644 /* splay_tree_delete (func->links); */
9648 /* Given a decl, a section name, and whether the decl initializer
9649 has relocs, choose attributes for the section. */
9651 #define SECTION_VMS_OVERLAY SECTION_FORGET
9652 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9653 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9656 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9658 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9660 if (decl
&& DECL_ATTRIBUTES (decl
)
9661 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9662 flags
|= SECTION_VMS_OVERLAY
;
9663 if (decl
&& DECL_ATTRIBUTES (decl
)
9664 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9665 flags
|= SECTION_VMS_GLOBAL
;
9666 if (decl
&& DECL_ATTRIBUTES (decl
)
9667 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9668 flags
|= SECTION_VMS_INITIALIZE
;
9673 /* Switch to an arbitrary section NAME with attributes as specified
9674 by FLAGS. ALIGN specifies any known alignment requirements for
9675 the section; 0 if the default should be used. */
9678 vms_asm_named_section (const char *name
, unsigned int flags
,
9679 tree decl ATTRIBUTE_UNUSED
)
9681 fputc ('\n', asm_out_file
);
9682 fprintf (asm_out_file
, ".section\t%s", name
);
9684 if (flags
& SECTION_VMS_OVERLAY
)
9685 fprintf (asm_out_file
, ",OVR");
9686 if (flags
& SECTION_VMS_GLOBAL
)
9687 fprintf (asm_out_file
, ",GBL");
9688 if (flags
& SECTION_VMS_INITIALIZE
)
9689 fprintf (asm_out_file
, ",NOMOD");
9690 if (flags
& SECTION_DEBUG
)
9691 fprintf (asm_out_file
, ",NOWRT");
9693 fputc ('\n', asm_out_file
);
9696 /* Record an element in the table of global constructors. SYMBOL is
9697 a SYMBOL_REF of the function to be called; PRIORITY is a number
9698 between 0 and MAX_INIT_PRIORITY.
9700 Differs from default_ctors_section_asm_out_constructor in that the
9701 width of the .ctors entry is always 64 bits, rather than the 32 bits
9702 used by a normal pointer. */
9705 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9708 assemble_align (BITS_PER_WORD
);
9709 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9713 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9716 assemble_align (BITS_PER_WORD
);
9717 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9722 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9723 int is_local ATTRIBUTE_UNUSED
)
9729 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9730 tree cfundecl ATTRIBUTE_UNUSED
,
9731 int lflag ATTRIBUTE_UNUSED
,
9732 int rflag ATTRIBUTE_UNUSED
)
9737 #endif /* TARGET_ABI_OPEN_VMS */
9739 #if TARGET_ABI_UNICOSMK
9741 /* This evaluates to true if we do not know how to pass TYPE solely in
9742 registers. This is the case for all arguments that do not fit in two
9746 unicosmk_must_pass_in_stack (enum machine_mode mode
, tree type
)
9751 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9753 if (TREE_ADDRESSABLE (type
))
9756 return ALPHA_ARG_SIZE (mode
, type
, 0) > 2;
9759 /* Define the offset between two registers, one to be eliminated, and the
9760 other its replacement, at the start of a routine. */
9763 unicosmk_initial_elimination_offset (int from
, int to
)
9767 fixed_size
= alpha_sa_size();
9768 if (fixed_size
!= 0)
9771 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9773 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9775 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9776 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9777 + ALPHA_ROUND (get_frame_size()));
9778 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9779 return (ALPHA_ROUND (fixed_size
)
9780 + ALPHA_ROUND (get_frame_size()
9781 + current_function_outgoing_args_size
));
9786 /* Output the module name for .ident and .end directives. We have to strip
9787 directories and add make sure that the module name starts with a letter
9791 unicosmk_output_module_name (FILE *file
)
9793 const char *name
= lbasename (main_input_filename
);
9794 unsigned len
= strlen (name
);
9795 char *clean_name
= alloca (len
+ 2);
9796 char *ptr
= clean_name
;
9798 /* CAM only accepts module names that start with a letter or '$'. We
9799 prefix the module name with a '$' if necessary. */
9801 if (!ISALPHA (*name
))
9803 memcpy (ptr
, name
, len
+ 1);
9804 clean_symbol_name (clean_name
);
9805 fputs (clean_name
, file
);
9808 /* Output the definition of a common variable. */
9811 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9814 printf ("T3E__: common %s\n", name
);
9817 fputs("\t.endp\n\n\t.psect ", file
);
9818 assemble_name(file
, name
);
9819 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9820 fprintf(file
, "\t.byte\t0:%d\n", size
);
9822 /* Mark the symbol as defined in this module. */
9823 name_tree
= get_identifier (name
);
9824 TREE_ASM_WRITTEN (name_tree
) = 1;
9827 #define SECTION_PUBLIC SECTION_MACH_DEP
9828 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9829 static int current_section_align
;
9832 unicosmk_section_type_flags (tree decl
, const char *name
,
9833 int reloc ATTRIBUTE_UNUSED
)
9835 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9840 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9842 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9843 if (align_functions_log
> current_section_align
)
9844 current_section_align
= align_functions_log
;
9846 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9847 flags
|= SECTION_MAIN
;
9850 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9852 if (TREE_PUBLIC (decl
))
9853 flags
|= SECTION_PUBLIC
;
9858 /* Generate a section name for decl and associate it with the
9862 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9869 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9870 name
= default_strip_name_encoding (name
);
9871 len
= strlen (name
);
9873 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9877 /* It is essential that we prefix the section name here because
9878 otherwise the section names generated for constructors and
9879 destructors confuse collect2. */
9881 string
= alloca (len
+ 6);
9882 sprintf (string
, "code@%s", name
);
9883 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9885 else if (TREE_PUBLIC (decl
))
9886 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9891 string
= alloca (len
+ 6);
9892 sprintf (string
, "data@%s", name
);
9893 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9897 /* Switch to an arbitrary section NAME with attributes as specified
9898 by FLAGS. ALIGN specifies any known alignment requirements for
9899 the section; 0 if the default should be used. */
9902 unicosmk_asm_named_section (const char *name
, unsigned int flags
,
9903 tree decl ATTRIBUTE_UNUSED
)
9907 /* Close the previous section. */
9909 fputs ("\t.endp\n\n", asm_out_file
);
9911 /* Find out what kind of section we are opening. */
9913 if (flags
& SECTION_MAIN
)
9914 fputs ("\t.start\tmain\n", asm_out_file
);
9916 if (flags
& SECTION_CODE
)
9918 else if (flags
& SECTION_PUBLIC
)
9923 if (current_section_align
!= 0)
9924 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9925 current_section_align
, kind
);
9927 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9931 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9934 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9935 unicosmk_unique_section (decl
, 0);
9938 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9939 in code sections because .align fill unused space with zeroes. */
9942 unicosmk_output_align (FILE *file
, int align
)
9944 if (inside_function
)
9945 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9947 fprintf (file
, "\t.align\t%d\n", align
);
9950 /* Add a case vector to the current function's list of deferred case
9951 vectors. Case vectors have to be put into a separate section because CAM
9952 does not allow data definitions in code sections. */
9955 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9957 struct machine_function
*machine
= cfun
->machine
;
9959 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9960 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9961 machine
->addr_list
);
9964 /* Output a case vector. */
9967 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9969 rtx lab
= XEXP (vec
, 0);
9970 rtx body
= XEXP (vec
, 1);
9971 int vlen
= XVECLEN (body
, 0);
9974 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9976 for (idx
= 0; idx
< vlen
; idx
++)
9978 ASM_OUTPUT_ADDR_VEC_ELT
9979 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9983 /* Output current function's deferred case vectors. */
9986 unicosmk_output_deferred_case_vectors (FILE *file
)
9988 struct machine_function
*machine
= cfun
->machine
;
9991 if (machine
->addr_list
== NULL_RTX
)
9995 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9996 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9999 /* Generate the name of the SSIB section for the current function. */
10001 #define SSIB_PREFIX "__SSIB_"
10002 #define SSIB_PREFIX_LEN 7
10004 static const char *
10005 unicosmk_ssib_name (void)
10007 /* This is ok since CAM won't be able to deal with names longer than that
10010 static char name
[256];
10013 const char *fnname
;
10016 x
= DECL_RTL (cfun
->decl
);
10017 gcc_assert (GET_CODE (x
) == MEM
);
10019 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
10020 fnname
= XSTR (x
, 0);
10022 len
= strlen (fnname
);
10023 if (len
+ SSIB_PREFIX_LEN
> 255)
10024 len
= 255 - SSIB_PREFIX_LEN
;
10026 strcpy (name
, SSIB_PREFIX
);
10027 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
10028 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10033 /* Set up the dynamic subprogram information block (DSIB) and update the
10034 frame pointer register ($15) for subroutines which have a frame. If the
10035 subroutine doesn't have a frame, simply increment $15. */
10038 unicosmk_gen_dsib (unsigned long *imaskP
)
10040 if (alpha_procedure_type
== PT_STACK
)
10042 const char *ssib_name
;
10045 /* Allocate 64 bytes for the DSIB. */
10047 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10049 emit_insn (gen_blockage ());
10051 /* Save the return address. */
10053 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
10054 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10055 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
10056 (*imaskP
) &= ~(1UL << REG_RA
);
10058 /* Save the old frame pointer. */
10060 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
10061 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10062 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
10063 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
10065 emit_insn (gen_blockage ());
10067 /* Store the SSIB pointer. */
10069 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
10070 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
10071 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10073 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
10074 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
10075 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
10077 /* Save the CIW index. */
10079 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
10080 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10081 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
10083 emit_insn (gen_blockage ());
10085 /* Set the new frame pointer. */
10087 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10088 stack_pointer_rtx
, GEN_INT (64))));
10093 /* Increment the frame pointer register to indicate that we do not
10096 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10097 hard_frame_pointer_rtx
, const1_rtx
)));
10101 /* Output the static subroutine information block for the current
10105 unicosmk_output_ssib (FILE *file
, const char *fnname
)
10111 struct machine_function
*machine
= cfun
->machine
;
10114 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10115 unicosmk_ssib_name ());
10117 /* Some required stuff and the function name length. */
10119 len
= strlen (fnname
);
10120 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10123 ??? We don't do that yet. */
10125 fputs ("\t.quad\t0\n", file
);
10127 /* Function address. */
10129 fputs ("\t.quad\t", file
);
10130 assemble_name (file
, fnname
);
10133 fputs ("\t.quad\t0\n", file
);
10134 fputs ("\t.quad\t0\n", file
);
10137 ??? We do it the same way Cray CC does it but this could be
10140 for( i
= 0; i
< len
; i
++ )
10141 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10142 if( (len
% 8) == 0 )
10143 fputs ("\t.quad\t0\n", file
);
10145 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10147 /* All call information words used in the function. */
10149 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10152 #if HOST_BITS_PER_WIDE_INT == 32
10153 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
10154 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10156 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
10161 /* Add a call information word (CIW) to the list of the current function's
10162 CIWs and return its index.
10164 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10167 unicosmk_add_call_info_word (rtx x
)
10170 struct machine_function
*machine
= cfun
->machine
;
10172 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10173 if (machine
->first_ciw
== NULL_RTX
)
10174 machine
->first_ciw
= node
;
10176 XEXP (machine
->last_ciw
, 1) = node
;
10178 machine
->last_ciw
= node
;
10179 ++machine
->ciw_count
;
10181 return GEN_INT (machine
->ciw_count
10182 + strlen (current_function_name ())/8 + 5);
10185 static char unicosmk_section_buf
[100];
10188 unicosmk_text_section (void)
10190 static int count
= 0;
10191 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
10193 return unicosmk_section_buf
;
10197 unicosmk_data_section (void)
10199 static int count
= 1;
10200 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
10202 return unicosmk_section_buf
;
10205 /* The Cray assembler doesn't accept extern declarations for symbols which
10206 are defined in the same file. We have to keep track of all global
10207 symbols which are referenced and/or defined in a source file and output
10208 extern declarations for those which are referenced but not defined at
10209 the end of file. */
10211 /* List of identifiers for which an extern declaration might have to be
10213 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10215 struct unicosmk_extern_list
10217 struct unicosmk_extern_list
*next
;
10221 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10223 /* Output extern declarations which are required for every asm file. */
10226 unicosmk_output_default_externs (FILE *file
)
10228 static const char *const externs
[] =
10229 { "__T3E_MISMATCH" };
10234 n
= ARRAY_SIZE (externs
);
10236 for (i
= 0; i
< n
; i
++)
10237 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10240 /* Output extern declarations for global symbols which are have been
10241 referenced but not defined. */
10244 unicosmk_output_externs (FILE *file
)
10246 struct unicosmk_extern_list
*p
;
10247 const char *real_name
;
10251 len
= strlen (user_label_prefix
);
10252 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10254 /* We have to strip the encoding and possibly remove user_label_prefix
10255 from the identifier in order to handle -fleading-underscore and
10256 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10257 real_name
= default_strip_name_encoding (p
->name
);
10258 if (len
&& p
->name
[0] == '*'
10259 && !memcmp (real_name
, user_label_prefix
, len
))
10262 name_tree
= get_identifier (real_name
);
10263 if (! TREE_ASM_WRITTEN (name_tree
))
10265 TREE_ASM_WRITTEN (name_tree
) = 1;
10266 fputs ("\t.extern\t", file
);
10267 assemble_name (file
, p
->name
);
10273 /* Record an extern. */
10276 unicosmk_add_extern (const char *name
)
10278 struct unicosmk_extern_list
*p
;
10280 p
= (struct unicosmk_extern_list
*)
10281 xmalloc (sizeof (struct unicosmk_extern_list
));
10282 p
->next
= unicosmk_extern_head
;
10284 unicosmk_extern_head
= p
;
10287 /* The Cray assembler generates incorrect code if identifiers which
10288 conflict with register names are used as instruction operands. We have
10289 to replace such identifiers with DEX expressions. */
10291 /* Structure to collect identifiers which have been replaced by DEX
10293 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10295 struct unicosmk_dex
{
10296 struct unicosmk_dex
*next
;
10300 /* List of identifiers which have been replaced by DEX expressions. The DEX
10301 number is determined by the position in the list. */
10303 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10305 /* The number of elements in the DEX list. */
10307 static int unicosmk_dex_count
= 0;
10309 /* Check if NAME must be replaced by a DEX expression. */
10312 unicosmk_special_name (const char *name
)
10314 if (name
[0] == '*')
10317 if (name
[0] == '$')
10320 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10325 case '1': case '2':
10326 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10329 return (name
[2] == '\0'
10330 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10333 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10337 /* Return the DEX number if X must be replaced by a DEX expression and 0
10341 unicosmk_need_dex (rtx x
)
10343 struct unicosmk_dex
*dex
;
10347 if (GET_CODE (x
) != SYMBOL_REF
)
10351 if (! unicosmk_special_name (name
))
10354 i
= unicosmk_dex_count
;
10355 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10357 if (! strcmp (name
, dex
->name
))
10362 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10364 dex
->next
= unicosmk_dex_list
;
10365 unicosmk_dex_list
= dex
;
10367 ++unicosmk_dex_count
;
10368 return unicosmk_dex_count
;
10371 /* Output the DEX definitions for this file. */
10374 unicosmk_output_dex (FILE *file
)
10376 struct unicosmk_dex
*dex
;
10379 if (unicosmk_dex_list
== NULL
)
10382 fprintf (file
, "\t.dexstart\n");
10384 i
= unicosmk_dex_count
;
10385 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10387 fprintf (file
, "\tDEX (%d) = ", i
);
10388 assemble_name (file
, dex
->name
);
10393 fprintf (file
, "\t.dexend\n");
10396 /* Output text that to appear at the beginning of an assembler file. */
10399 unicosmk_file_start (void)
10403 fputs ("\t.ident\t", asm_out_file
);
10404 unicosmk_output_module_name (asm_out_file
);
10405 fputs ("\n\n", asm_out_file
);
10407 /* The Unicos/Mk assembler uses different register names. Instead of trying
10408 to support them, we simply use micro definitions. */
10410 /* CAM has different register names: rN for the integer register N and fN
10411 for the floating-point register N. Instead of trying to use these in
10412 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10415 for (i
= 0; i
< 32; ++i
)
10416 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
10418 for (i
= 0; i
< 32; ++i
)
10419 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
10421 putc ('\n', asm_out_file
);
10423 /* The .align directive fill unused space with zeroes which does not work
10424 in code sections. We define the macro 'gcc@code@align' which uses nops
10425 instead. Note that it assumes that code sections always have the
10426 biggest possible alignment since . refers to the current offset from
10427 the beginning of the section. */
10429 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
10430 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
10431 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
10432 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
10433 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
10434 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
10435 fputs ("\t.endr\n", asm_out_file
);
10436 fputs ("\t.endif\n", asm_out_file
);
10437 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
10439 /* Output extern declarations which should always be visible. */
10440 unicosmk_output_default_externs (asm_out_file
);
10442 /* Open a dummy section. We always need to be inside a section for the
10443 section-switching code to work correctly.
10444 ??? This should be a module id or something like that. I still have to
10445 figure out what the rules for those are. */
10446 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10449 /* Output text to appear at the end of an assembler file. This includes all
10450 pending extern declarations and DEX expressions. */
10453 unicosmk_file_end (void)
10455 fputs ("\t.endp\n\n", asm_out_file
);
10457 /* Output all pending externs. */
10459 unicosmk_output_externs (asm_out_file
);
10461 /* Output dex definitions used for functions whose names conflict with
10464 unicosmk_output_dex (asm_out_file
);
10466 fputs ("\t.end\t", asm_out_file
);
10467 unicosmk_output_module_name (asm_out_file
);
10468 putc ('\n', asm_out_file
);
10474 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10478 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10482 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10483 const char * fnname ATTRIBUTE_UNUSED
)
10487 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10493 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10498 #endif /* TARGET_ABI_UNICOSMK */
10501 alpha_init_libfuncs (void)
10503 if (TARGET_ABI_UNICOSMK
)
10505 /* Prevent gcc from generating calls to __divsi3. */
10506 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10507 set_optab_libfunc (udiv_optab
, SImode
, 0);
10509 /* Use the functions provided by the system library
10510 for DImode integer division. */
10511 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10512 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10514 else if (TARGET_ABI_OPEN_VMS
)
10516 /* Use the VMS runtime library functions for division and
10518 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10519 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10520 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10521 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10522 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10523 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10524 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10525 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10530 /* Initialize the GCC target structure. */
10531 #if TARGET_ABI_OPEN_VMS
10532 # undef TARGET_ATTRIBUTE_TABLE
10533 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10534 # undef TARGET_SECTION_TYPE_FLAGS
10535 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10538 #undef TARGET_IN_SMALL_DATA_P
10539 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10541 #if TARGET_ABI_UNICOSMK
10542 # undef TARGET_INSERT_ATTRIBUTES
10543 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10544 # undef TARGET_SECTION_TYPE_FLAGS
10545 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10546 # undef TARGET_ASM_UNIQUE_SECTION
10547 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10548 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
10549 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
10550 # undef TARGET_ASM_GLOBALIZE_LABEL
10551 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10552 # undef TARGET_MUST_PASS_IN_STACK
10553 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
10556 #undef TARGET_ASM_ALIGNED_HI_OP
10557 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10558 #undef TARGET_ASM_ALIGNED_DI_OP
10559 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10561 /* Default unaligned ops are provided for ELF systems. To get unaligned
10562 data for non-ELF systems, we have to turn off auto alignment. */
10563 #ifndef OBJECT_FORMAT_ELF
10564 #undef TARGET_ASM_UNALIGNED_HI_OP
10565 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10566 #undef TARGET_ASM_UNALIGNED_SI_OP
10567 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10568 #undef TARGET_ASM_UNALIGNED_DI_OP
10569 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10572 #ifdef OBJECT_FORMAT_ELF
10573 #undef TARGET_ASM_SELECT_RTX_SECTION
10574 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10577 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10578 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10580 #undef TARGET_INIT_LIBFUNCS
10581 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10583 #if TARGET_ABI_UNICOSMK
10584 #undef TARGET_ASM_FILE_START
10585 #define TARGET_ASM_FILE_START unicosmk_file_start
10586 #undef TARGET_ASM_FILE_END
10587 #define TARGET_ASM_FILE_END unicosmk_file_end
10589 #undef TARGET_ASM_FILE_START
10590 #define TARGET_ASM_FILE_START alpha_file_start
10591 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10592 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10595 #undef TARGET_SCHED_ADJUST_COST
10596 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10597 #undef TARGET_SCHED_ISSUE_RATE
10598 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10599 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10600 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10601 alpha_multipass_dfa_lookahead
10603 #undef TARGET_HAVE_TLS
10604 #define TARGET_HAVE_TLS HAVE_AS_TLS
10606 #undef TARGET_INIT_BUILTINS
10607 #define TARGET_INIT_BUILTINS alpha_init_builtins
10608 #undef TARGET_EXPAND_BUILTIN
10609 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10610 #undef TARGET_FOLD_BUILTIN
10611 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
10613 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10614 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10615 #undef TARGET_CANNOT_COPY_INSN_P
10616 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10617 #undef TARGET_CANNOT_FORCE_CONST_MEM
10618 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
10621 #undef TARGET_ASM_OUTPUT_MI_THUNK
10622 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10623 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10624 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10625 #undef TARGET_STDARG_OPTIMIZE_HOOK
10626 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
10629 #undef TARGET_RTX_COSTS
10630 #define TARGET_RTX_COSTS alpha_rtx_costs
10631 #undef TARGET_ADDRESS_COST
10632 #define TARGET_ADDRESS_COST hook_int_rtx_0
10634 #undef TARGET_MACHINE_DEPENDENT_REORG
10635 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10637 #undef TARGET_PROMOTE_FUNCTION_ARGS
10638 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10639 #undef TARGET_PROMOTE_FUNCTION_RETURN
10640 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10641 #undef TARGET_PROMOTE_PROTOTYPES
10642 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10643 #undef TARGET_RETURN_IN_MEMORY
10644 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10645 #undef TARGET_PASS_BY_REFERENCE
10646 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
10647 #undef TARGET_SETUP_INCOMING_VARARGS
10648 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10649 #undef TARGET_STRICT_ARGUMENT_NAMING
10650 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10651 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10652 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10653 #undef TARGET_SPLIT_COMPLEX_ARG
10654 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10655 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10656 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10657 #undef TARGET_ARG_PARTIAL_BYTES
10658 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
10660 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10661 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
10662 #undef TARGET_VECTOR_MODE_SUPPORTED_P
10663 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
10665 #undef TARGET_BUILD_BUILTIN_VA_LIST
10666 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10668 /* The Alpha architecture does not require sequential consistency. See
10669 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
10670 for an example of how it can be violated in practice. */
10671 #undef TARGET_RELAXED_ORDERING
10672 #define TARGET_RELAXED_ORDERING true
10674 #undef TARGET_DEFAULT_TARGET_FLAGS
10675 #define TARGET_DEFAULT_TARGET_FLAGS \
10676 (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
10677 #undef TARGET_HANDLE_OPTION
10678 #define TARGET_HANDLE_OPTION alpha_handle_option
10680 struct gcc_target targetm
= TARGET_INITIALIZER
;
10683 #include "gt-alpha.h"