594b9ffc66227620291ff8b6bc2f598db77e3e18
1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Names to predefine in the preprocessor for this target machine. */
24 #define CPP_PREDEFINES "\
25 -Dunix -D__osf__ -D__alpha -D__alpha__ -D_LONGLONG -DSYSTYPE_BSD \
28 /* Write out the correct language type definition for the header files. */
30 %{.c: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}} \
31 %{.h: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}} \
32 %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
33 %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \
34 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \
35 %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \
36 %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C}"
38 /* Set the spec to use for signed char. The default tests the above macro
39 but DEC's compiler can't handle the conditional in a "constant"
42 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
44 /* No point in running CPP on our assembler output. */
45 #define ASM_SPEC "-nocpp"
47 /* Right now Alpha OSF/1 doesn't seem to have debugging or profiled
50 #define LIB_SPEC "-lc"
52 /* Pass "-G 8" to ld because Alpha's CC does. Pass -O2 if we are optimizing,
53 -O1 if we are not. Pass -non_shared or -call_shared as appropriate. */
54 /* Disable -O2 to ld; it seems to have problems. */
56 "-G 8 %{O*:-O1} %{!O*:-O1} %{static:-non_shared} %{!static:-call_shared}"
58 /* Print subsidiary information on the compiler version in use. */
59 #define TARGET_VERSION
61 /* Define the location for the startup file on OSF/1 for Alpha. */
63 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
65 /* Run-time compilation parameters selecting different hardware subsets. */
67 extern int target_flags
;
69 /* This means that floating-point support exists in the target implementation
70 of the Alpha architecture. This is usually the default. */
72 #define TARGET_FP (target_flags & 1)
74 /* This means that floating-point registers are allowed to be used. Note
75 that Alpha implementations without FP operations are required to
76 provide the FP registers. */
78 #define TARGET_FPREGS (target_flags & 2)
80 /* Macro to define tables used to set the flags.
81 This is a list in braces of pairs in braces,
82 each pair being { "NAME", VALUE }
83 where VALUE is the bits to set or minus the bits to clear.
84 An empty string NAME is used to identify the default VALUE. */
86 #define TARGET_SWITCHES \
87 { {"no-soft-float", 1}, \
91 {"", TARGET_DEFAULT} }
93 #define TARGET_DEFAULT 3
95 /* Define this macro to change register usage conditional on target flags.
97 On the Alpha, we use this to disable the floating-point registers when
100 #define CONDITIONAL_REGISTER_USAGE \
101 if (! TARGET_FPREGS) \
102 for (i = 32; i < 64; i++) \
103 fixed_regs[i] = call_used_regs[i] = 1;
105 /* Define this to change the optimizations performed by default. */
107 #define OPTIMIZATION_OPTIONS(LEVEL) \
111 flag_force_addr = 1; \
112 flag_force_mem = 1; \
113 flag_omit_frame_pointer = 1; \
117 /* target machine storage layout */
119 /* Define to enable software floating point emulation. */
120 #define REAL_ARITHMETIC
122 /* Define the size of `int'. The default is the same as the word size. */
123 #define INT_TYPE_SIZE 32
125 /* Define the size of `long long'. The default is the twice the word size. */
126 #define LONG_LONG_TYPE_SIZE 64
128 /* The two floating-point formats we support are S-floating, which is
129 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
130 and `long double' are T. */
132 #define FLOAT_TYPE_SIZE 32
133 #define DOUBLE_TYPE_SIZE 64
134 #define LONG_DOUBLE_TYPE_SIZE 64
136 #define WCHAR_TYPE "short unsigned int"
137 #define WCHAR_TYPE_SIZE 16
139 /* Define this macro if it is advisable to hold scalars in registers
140 in a wider mode than that declared by the program. In such cases,
141 the value is constrained to be within the bounds of the declared
142 type, but kept valid in the wider mode. The signedness of the
143 extension may differ from that of the type.
145 For Alpha, we always store objects in a full register. 32-bit objects
146 are always sign-extended, but smaller objects retain their signedness. */
148 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
149 if (GET_MODE_CLASS (MODE) == MODE_INT \
150 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
152 if ((MODE) == SImode) \
157 /* Define this if function arguments should also be promoted using the above
160 #define PROMOTE_FUNCTION_ARGS
162 /* Likewise, if the function return value is promoted. */
164 #define PROMOTE_FUNCTION_RETURN
166 /* Define this if most significant bit is lowest numbered
167 in instructions that operate on numbered bit-fields.
169 There are no such instructions on the Alpha, but the documentation
171 #define BITS_BIG_ENDIAN 0
173 /* Define this if most significant byte of a word is the lowest numbered.
174 This is false on the Alpha. */
175 #define BYTES_BIG_ENDIAN 0
177 /* Define this if most significant word of a multiword number is lowest
180 For Alpha we can decide arbitrarily since there are no machine instructions
181 for them. Might as well be consistent with bytes. */
182 #define WORDS_BIG_ENDIAN 0
184 /* number of bits in an addressable storage unit */
185 #define BITS_PER_UNIT 8
187 /* Width in bits of a "word", which is the contents of a machine register.
188 Note that this is not necessarily the width of data type `int';
189 if using 16-bit ints on a 68000, this would still be 32.
190 But on a machine with 16-bit registers, this would be 16. */
191 #define BITS_PER_WORD 64
193 /* Width of a word, in units (bytes). */
194 #define UNITS_PER_WORD 8
196 /* Width in bits of a pointer.
197 See also the macro `Pmode' defined below. */
198 #define POINTER_SIZE 64
200 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
201 #define PARM_BOUNDARY 64
203 /* Boundary (in *bits*) on which stack pointer should be aligned. */
204 #define STACK_BOUNDARY 64
206 /* Allocation boundary (in *bits*) for the code of a function. */
207 #define FUNCTION_BOUNDARY 64
209 /* Alignment of field after `int : 0' in a structure. */
210 #define EMPTY_FIELD_BOUNDARY 64
212 /* Every structure's size must be a multiple of this. */
213 #define STRUCTURE_SIZE_BOUNDARY 8
215 /* A bitfield declared as `int' forces `int' alignment for the struct. */
216 #define PCC_BITFIELD_TYPE_MATTERS 1
218 /* Align loop starts for optimal branching. */
220 #define ASM_OUTPUT_LOOP_ALIGN(FILE) \
221 ASM_OUTPUT_ALIGN (FILE, 5)
223 /* This is how to align an instruction for optimal branching.
224 On Alpha we'll get better performance by aligning on a quadword
227 #define ASM_OUTPUT_ALIGN_CODE(FILE) \
228 ASM_OUTPUT_ALIGN ((FILE), 4)
230 /* No data type wants to be aligned rounder than this. */
231 #define BIGGEST_ALIGNMENT 64
233 /* Make strings word-aligned so strcpy from constants will be faster. */
234 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
235 (TREE_CODE (EXP) == STRING_CST \
236 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
238 /* Make arrays of chars word-aligned for the same reasons. */
239 #define DATA_ALIGNMENT(TYPE, ALIGN) \
240 (TREE_CODE (TYPE) == ARRAY_TYPE \
241 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
242 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
244 /* Set this non-zero if move instructions will actually fail to work
245 when given unaligned data.
247 Since we get an error message when we do one, call them invalid. */
249 #define STRICT_ALIGNMENT 1
251 /* Set this non-zero if unaligned move instructions are extremely slow.
253 On the Alpha, they trap. */
255 #define SLOW_UNALIGNED_ACCESS 1
257 /* Standard register usage. */
259 /* Number of actual hardware registers.
260 The hardware registers are assigned numbers for the compiler
261 from 0 to just below FIRST_PSEUDO_REGISTER.
262 All registers that the compiler knows about must be given numbers,
263 even those that are not normally considered general registers.
265 We define all 32 integer registers, even though $31 is always zero,
266 and all 32 floating-point registers, even though $f31 is also
267 always zero. We do not bother defining the FP status register and
268 there are no other registers.
270 Since $31 is always zero, we will use register number 31 as the
271 argument pointer. It will never appear in the generated code
272 because we will always be eliminating it in favor of the stack
273 poointer or frame pointer. */
275 #define FIRST_PSEUDO_REGISTER 64
277 /* 1 for registers that have pervasive standard uses
278 and are not available for the register allocator. */
280 #define FIXED_REGISTERS \
281 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
283 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
284 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
286 /* 1 for registers not available across function calls.
287 These must include the FIXED_REGISTERS and also any
288 registers that can be used without being saved.
289 The latter must include the registers where values are returned
290 and the register where structure-value addresses are passed.
291 Aside from that, you can include as many other registers as you like. */
292 #define CALL_USED_REGISTERS \
293 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
294 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
295 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
296 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
298 /* List the order in which to allocate registers. Each register must be
299 listed once, even those in FIXED_REGISTERS.
301 We allocate in the following order:
302 $f1 (nonsaved floating-point register)
305 $f21-$f16 (likewise, but input args)
306 $f0 (nonsaved, but return value)
307 $f2-$f9 (saved floating-point registers)
308 $1-$8 (nonsaved integer registers)
311 $0 (likewise, but return value)
312 $21-$16 (likewise, but input args)
313 $27 (procedure value)
314 $9-$14 (saved integer registers)
318 $30, $31, $f31 (stack pointer and always zero/ap) */
320 #define REG_ALLOC_ORDER \
323 54, 55, 56, 57, 58, 59, 60, 61, 62, \
324 53, 52, 51, 50, 49, 48, \
326 34, 35, 36, 37, 38, 39, 40, 41, \
327 1, 2, 3, 4, 5, 6, 7, 8, \
331 21, 20, 19, 18, 17, 16, \
333 9, 10, 11, 12, 13, 14, \
339 /* Return number of consecutive hard regs needed starting at reg REGNO
340 to hold something of mode MODE.
341 This is ordinarily the length in words of a value of mode MODE
342 but can be less for certain modes in special long registers. */
344 #define HARD_REGNO_NREGS(REGNO, MODE) \
345 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
347 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
348 On Alpha, the integer registers can hold any mode. The floating-point
349 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
350 or 8-bit values. If we only allowed the larger integers into FP registers,
351 we'd have to say that QImode and SImode aren't tiable, which is a
352 pain. So say all registers can hold everything and see how that works. */
354 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
356 /* Value is 1 if it is a good idea to tie two pseudo registers
357 when one has mode MODE1 and one has mode MODE2.
358 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
359 for any hard reg, then this must be 0 for correct output. */
361 #define MODES_TIEABLE_P(MODE1, MODE2) 1
363 /* Specify the registers used for certain standard purposes.
364 The values of these macros are register numbers. */
366 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
367 /* #define PC_REGNUM */
369 /* Register to use for pushing function arguments. */
370 #define STACK_POINTER_REGNUM 30
372 /* Base register for access to local variables of the function. */
373 #define FRAME_POINTER_REGNUM 15
375 /* Value should be nonzero if functions must have frame pointers.
376 Zero means the frame pointer need not be set up (and parms
377 may be accessed via the stack pointer) in functions that seem suitable.
378 This is computed in `reload', in reload1.c. */
379 #define FRAME_POINTER_REQUIRED 0
381 /* Base register for access to arguments of the function. */
382 #define ARG_POINTER_REGNUM 31
384 /* Register in which static-chain is passed to a function.
386 For the Alpha, this is based on an example; the calling sequence
387 doesn't seem to specify this. */
388 #define STATIC_CHAIN_REGNUM 1
390 /* Register in which address to store a structure value
391 arrives in the function. On the Alpha, the address is passed
392 as a hidden argument. */
393 #define STRUCT_VALUE 0
395 /* Define the classes of registers for register constraints in the
396 machine description. Also define ranges of constants.
398 One of the classes must always be named ALL_REGS and include all hard regs.
399 If there is more than one class, another class must be named NO_REGS
400 and contain no registers.
402 The name GENERAL_REGS must be the name of a class (or an alias for
403 another name such as ALL_REGS). This is the class of registers
404 that is allowed by "g" or "r" in a register constraint.
405 Also, registers outside this class are allocated only when
406 instructions express preferences for them.
408 The classes must be numbered in nondecreasing order; that is,
409 a larger-numbered class must never be contained completely
410 in a smaller-numbered class.
412 For any two classes, it is very desirable that there be another
413 class that represents their union. */
415 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FLOAT_REGS
, ALL_REGS
,
418 #define N_REG_CLASSES (int) LIM_REG_CLASSES
420 /* Give names of register classes as strings for dump file. */
422 #define REG_CLASS_NAMES \
423 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
425 /* Define which registers fit in which classes.
426 This is an initializer for a vector of HARD_REG_SET
427 of length N_REG_CLASSES. */
429 #define REG_CLASS_CONTENTS \
430 { {0, 0}, {~0, 0}, {0, ~0}, {~0, ~0} }
432 /* The same information, inverted:
433 Return the class number of the smallest class containing
434 reg number REGNO. This could be a conditional expression
435 or could index an array. */
437 #define REGNO_REG_CLASS(REGNO) ((REGNO) >= 32 ? FLOAT_REGS : GENERAL_REGS)
439 /* The class value for index registers, and the one for base regs. */
440 #define INDEX_REG_CLASS NO_REGS
441 #define BASE_REG_CLASS GENERAL_REGS
443 /* Get reg_class from a letter such as appears in the machine description. */
445 #define REG_CLASS_FROM_LETTER(C) \
446 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
448 /* Define this macro to change register usage conditional on target flags. */
449 /* #define CONDITIONAL_REGISTER_USAGE */
451 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
452 can be used to stand for particular ranges of immediate operands.
453 This macro defines what the ranges are.
454 C is the letter, and VALUE is a constant value.
455 Return 1 if VALUE is in the range specified by C.
458 `I' is used for the range of constants most insns can contain.
459 `J' is the constant zero.
460 `K' is used for the constant in an LDA insn.
461 `L' is used for the constant in a LDAH insn.
462 `M' is used for the constants that can be AND'ed with using a ZAP insn.
463 `N' is used for complemented 8-bit constants.
464 `O' is used for negated 8-bit constants.
465 `P' is used for the constants 1, 2 and 3. */
467 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
468 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
469 : (C) == 'J' ? (VALUE) == 0 \
470 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
471 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
472 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
473 : (C) == 'M' ? zap_mask (VALUE) \
474 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
475 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
476 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
479 /* Similar, but for floating or large integer constants, and defining letters
480 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
482 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
483 that is the operand of a ZAP insn. */
485 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
486 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
487 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
488 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
489 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
490 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
493 /* Given an rtx X being reloaded into a reg required to be
494 in class CLASS, return the class of reg to actually use.
495 In general this is just CLASS; but on some machines
496 in some cases it is preferable to use a more restrictive class.
498 On the Alpha, all constants except zero go into a floating-point
499 register via memory. */
501 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
502 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
503 ? ((CLASS) == FLOAT_REGS ? NO_REGS : GENERAL_REGS) \
506 /* Loading and storing HImode or QImode values to and from memory
507 usually requires a scratch register. The exceptions are loading
508 QImode and HImode from an aligned address to a general register. */
510 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
511 (((GET_CODE (IN) == MEM \
512 || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \
513 || (GET_CODE (IN) == SUBREG \
514 && (GET_CODE (SUBREG_REG (IN)) == MEM \
515 || (GET_CODE (SUBREG_REG (IN)) == REG \
516 && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \
517 && (((CLASS) == FLOAT_REGS \
518 && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \
519 || (((MODE) == QImode || (MODE) == HImode) \
520 && unaligned_memory_operand (IN, MODE)))) \
521 ? GENERAL_REGS : NO_REGS)
523 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
524 (((GET_CODE (OUT) == MEM \
525 || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \
526 || (GET_CODE (OUT) == SUBREG \
527 && (GET_CODE (SUBREG_REG (OUT)) == MEM \
528 || (GET_CODE (SUBREG_REG (OUT)) == REG \
529 && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
530 && (((MODE) == HImode || (MODE) == QImode \
531 || ((MODE) == SImode && (CLASS) == FLOAT_REGS)))) \
532 ? GENERAL_REGS : NO_REGS)
534 /* If we are copying between general and FP registers, we need a memory
537 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) ((CLASS1) != (CLASS2))
539 /* Return the maximum number of consecutive registers
540 needed to represent mode MODE in a register of class CLASS. */
542 #define CLASS_MAX_NREGS(CLASS, MODE) \
543 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
545 /* Define the cost of moving between registers of various classes. Moving
546 between FLOAT_REGS and anything else except float regs is expensive.
547 In fact, we make it quite expensive because we really don't want to
548 do these moves unless it is clearly worth it. Optimizations may
549 reduce the impact of not being able to allocate a pseudo to a
552 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
553 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 : 20)
555 /* A C expressions returning the cost of moving data of MODE from a register to
558 On the Alpha, bump this up a bit. */
560 #define MEMORY_MOVE_COST(MODE) 6
562 /* Provide the cost of a branch. Exact meaning under development. */
563 #define BRANCH_COST 5
565 /* Adjust the cost of dependencies. */
567 #define ADJUST_COST(INSN,LINK,DEP,COST) \
568 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
570 /* Stack layout; function entry, exit and calling. */
572 /* Define this if pushing a word on the stack
573 makes the stack pointer a smaller address. */
574 #define STACK_GROWS_DOWNWARD
576 /* Define this if the nominal address of the stack frame
577 is at the high-address end of the local variables;
578 that is, each additional local variable allocated
579 goes at a more negative offset in the frame. */
580 /* #define FRAME_GROWS_DOWNWARD */
582 /* Offset within stack frame to start allocating local variables at.
583 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
584 first local allocated. Otherwise, it is the offset to the BEGINNING
585 of the first local allocated. */
587 #define STARTING_FRAME_OFFSET current_function_outgoing_args_size
589 /* If we generate an insn to push BYTES bytes,
590 this says how many the stack pointer really advances by.
591 On Alpha, don't define this because there are no push insns. */
592 /* #define PUSH_ROUNDING(BYTES) */
594 /* Define this if the maximum size of all the outgoing args is to be
595 accumulated and pushed during the prologue. The amount can be
596 found in the variable current_function_outgoing_args_size. */
597 #define ACCUMULATE_OUTGOING_ARGS
599 /* Offset of first parameter from the argument pointer register value. */
601 #define FIRST_PARM_OFFSET(FNDECL) 0
603 /* Definitions for register eliminations.
605 We have two registers that can be eliminated on the Alpha. First, the
606 frame pointer register can often be eliminated in favor of the stack
607 pointer register. Secondly, the argument pointer register can always be
608 eliminated; it is replaced with either the stack or frame pointer. */
610 /* This is an array of structures. Each structure initializes one pair
611 of eliminable registers. The "from" register number is given first,
612 followed by "to". Eliminations of the same "from" register are listed
613 in order of preference. */
615 #define ELIMINABLE_REGS \
616 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
617 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
618 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
620 /* Given FROM and TO register numbers, say whether this elimination is allowed.
621 Frame pointer elimination is automatically handled.
623 All eliminations are valid since the cases where FP can't be
624 eliminated are already handled. */
626 #define CAN_ELIMINATE(FROM, TO) 1
628 /* Define the offset between two registers, one to be eliminated, and the other
629 its replacement, at the start of a routine. */
630 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
631 { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
635 (OFFSET) = ((get_frame_size () + current_function_outgoing_args_size \
636 + current_function_pretend_args_size \
637 + alpha_sa_size () + 15) \
639 if ((FROM) == ARG_POINTER_REGNUM) \
640 (OFFSET) -= current_function_pretend_args_size; \
644 /* Define this if stack space is still allocated for a parameter passed
646 /* #define REG_PARM_STACK_SPACE */
648 /* Value is the number of bytes of arguments automatically
649 popped when returning from a subroutine call.
650 FUNTYPE is the data type of the function (as a tree),
651 or for a library call it is an identifier node for the subroutine name.
652 SIZE is the number of bytes of arguments passed on the stack. */
654 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
656 /* Define how to find the value returned by a function.
657 VALTYPE is the data type of the value (as a tree).
658 If the precise function being called is known, FUNC is its FUNCTION_DECL;
659 otherwise, FUNC is 0.
661 On Alpha the value is found in $0 for integer functions and
662 $f0 for floating-point functions. */
664 #define FUNCTION_VALUE(VALTYPE, FUNC) \
666 ((TREE_CODE (VALTYPE) == INTEGER_TYPE \
667 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
668 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
669 || TREE_CODE (VALTYPE) == CHAR_TYPE \
670 || TREE_CODE (VALTYPE) == POINTER_TYPE \
671 || TREE_CODE (VALTYPE) == OFFSET_TYPE) \
672 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
673 ? word_mode : TYPE_MODE (VALTYPE), \
674 TARGET_FPREGS && TREE_CODE (VALTYPE) == REAL_TYPE ? 32 : 0)
676 /* Define how to find the value returned by a library function
677 assuming the value has mode MODE. */
679 #define LIBCALL_VALUE(MODE) \
680 gen_rtx (REG, MODE, \
681 TARGET_FPREGS && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 0)
683 /* The definition of this macro implies that there are cases where
684 a scalar value cannot be returned in registers.
686 For the Alpha, any structure or union type is returned in memory, as
687 are integers whose size is larger than 64 bits. */
689 #define RETURN_IN_MEMORY(TYPE) \
690 (TYPE_MODE (TYPE) == BLKmode \
691 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
693 /* 1 if N is a possible register number for a function value
694 as seen by the caller. */
696 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 32)
698 /* 1 if N is a possible register number for function argument passing.
699 On Alpha, these are $16-$21 and $f16-$f21. */
701 #define FUNCTION_ARG_REGNO_P(N) \
702 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
704 /* Define a data type for recording info about an argument list
705 during the scan of that argument list. This data type should
706 hold all necessary information about the function itself
707 and about the args processed so far, enough to enable macros
708 such as FUNCTION_ARG to determine where the next arg should go.
710 On Alpha, this is a single integer, which is a number of words
711 of arguments scanned so far.
712 Thus 6 or more means all following args should go on the stack. */
714 #define CUMULATIVE_ARGS int
716 /* Initialize a variable CUM of type CUMULATIVE_ARGS
717 for a call to a function whose data type is FNTYPE.
718 For a library call, FNTYPE is 0. */
720 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) (CUM) = 0
722 /* Define intermediate macro to compute the size (in registers) of an argument
725 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
727 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
728 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
730 /* Update the data in CUM to advance over an argument
731 of mode MODE and data type TYPE.
732 (TYPE is null for libcalls where that information may not be available.) */
734 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
735 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
738 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
740 /* Determine where to put an argument to a function.
741 Value is zero to push the argument on the stack,
742 or a hard register in which to store the argument.
744 MODE is the argument's machine mode.
745 TYPE is the data type of the argument (as a tree).
746 This is null for libcalls where that information may
748 CUM is a variable of type CUMULATIVE_ARGS which gives info about
749 the preceding args and about the function being called.
750 NAMED is nonzero if this argument is a named parameter
751 (otherwise it is an extra parameter matching an ellipsis).
753 On Alpha the first 6 words of args are normally in registers
754 and the rest are pushed. */
756 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
757 ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \
758 ? gen_rtx(REG, (MODE), \
759 (CUM) + 16 + (TARGET_FPREGS \
760 && GET_MODE_CLASS (MODE) == MODE_FLOAT) * 32) : 0)
762 /* Specify the padding direction of arguments.
764 On the Alpha, we must pad upwards in order to be able to pass args in
767 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
769 /* For an arg passed partly in registers and partly in memory,
770 this is the number of registers used.
771 For args passed entirely in registers or entirely in memory, zero. */
773 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
774 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
777 /* Perform any needed actions needed for a function that is receiving a
778 variable number of arguments.
782 MODE and TYPE are the mode and type of the current parameter.
784 PRETEND_SIZE is a variable that should be set to the amount of stack
785 that must be pushed by the prolog to pretend that our caller pushed
788 Normally, this macro will push all remaining incoming registers on the
789 stack and set PRETEND_SIZE to the length of the registers pushed.
791 On the Alpha, we allocate space for all 12 arg registers, but only
792 push those that are remaining.
794 However, if NO registers need to be saved, don't allocate any space.
795 This is not only because we won't need the space, but because AP includes
796 the current_pretend_args_size and we don't want to mess up any
797 ap-relative addresses already made. */
799 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
804 move_block_from_reg \
806 gen_rtx (MEM, BLKmode, \
807 plus_constant (virtual_incoming_args_rtx, \
808 ((CUM) + 6)* UNITS_PER_WORD)), \
810 move_block_from_reg \
812 gen_rtx (MEM, BLKmode, \
813 plus_constant (virtual_incoming_args_rtx, \
814 (CUM) * UNITS_PER_WORD)), \
817 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
821 /* Generate necessary RTL for __builtin_saveregs().
822 ARGLIST is the argument list; see expr.c. */
823 extern struct rtx_def
*alpha_builtin_saveregs ();
824 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST)
826 /* Define the information needed to generate branch and scc insns. This is
827 stored from the compare operation. Note that we can't use "rtx" here
828 since it hasn't been defined! */
830 extern struct rtx_def
*alpha_compare_op0
, *alpha_compare_op1
;
831 extern int alpha_compare_fp_p
;
833 /* This macro produces the initial definition of a function name. On the
834 Alpha, we need to save the function name for the epilogue. */
836 extern char *alpha_function_name
;
838 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
841 for (_level = -1, _context = (DECL); _context; \
842 _context = DECL_CONTEXT (_context), _level++) \
844 fprintf (FILE, "\t.ent %s %d\n", NAME, _level); \
845 ASM_OUTPUT_LABEL (FILE, NAME); \
846 alpha_function_name = NAME; \
849 /* This macro generates the assembly code for function entry.
850 FILE is a stdio stream to output the code to.
851 SIZE is an int: how many units of temporary storage to allocate.
852 Refer to the array `regs_ever_live' to determine which registers
853 to save; `regs_ever_live[I]' is nonzero if register number I
854 is ever used in the function. This macro is responsible for
855 knowing which registers should not be saved even if used. */
857 #define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE)
859 /* Output assembler code to FILE to increment profiler label # LABELNO
860 for profiling a function entry. */
862 #define FUNCTION_PROFILER(FILE, LABELNO)
864 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
865 the stack pointer does not matter. The value is tested only in
866 functions that have frame pointers.
867 No definition is equivalent to always zero. */
869 #define EXIT_IGNORE_STACK 1
871 /* This macro generates the assembly code for function exit,
872 on machines that need it. If FUNCTION_EPILOGUE is not defined
873 then individual return instructions are generated for each
874 return statement. Args are same as for FUNCTION_PROLOGUE.
876 The function epilogue should not depend on the current stack pointer!
877 It should use the frame pointer only. This is mandatory because
878 of alloca; we also take advantage of it to omit stack adjustments
881 #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE)
884 /* Output assembler code for a block containing the constant parts
885 of a trampoline, leaving space for the variable parts.
887 The trampoline should set the static chain pointer to value placed
888 into the trampoline and should branch to the specified routine.
889 Note that $27 has been set to the address of the trampoline, so we can
890 use it for addressability of the two data items. Trampolines are always
891 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
893 #define TRAMPOLINE_TEMPLATE(FILE) \
895 fprintf (FILE, "\tldq $1,24($27)\n"); \
896 fprintf (FILE, "\tldq $27,16($27)\n"); \
897 fprintf (FILE, "\tjmp $31,($27),0\n"); \
898 fprintf (FILE, "\tnop\n"); \
899 fprintf (FILE, "\t.quad 0,0\n"); \
902 /* Section in which to place the trampoline. On Alpha, instructions
903 may only be placed in a text segment. */
905 #define TRAMPOLINE_SECTION text_section
907 /* Length in units of the trampoline for entering a nested function. */
909 #define TRAMPOLINE_SIZE 32
911 /* Emit RTL insns to initialize the variable parts of a trampoline.
912 FNADDR is an RTX for the address of the function's pure code.
913 CXT is an RTX for the static chain value for the function. We assume
914 here that a function will be called many more times than its address
915 is taken (e.g., it might be passed to qsort), so we take the trouble
916 to initialize the "hint" field in the JMP insn. Note that the hint
917 field is PC (new) + 4 * bits 13:0. */
919 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
921 rtx _temp, _temp1, _addr; \
923 _addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
924 emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR)); \
925 _addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
926 emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT)); \
928 _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX); \
929 _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1, \
931 _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp, \
932 build_int_2 (2, 0), NULL_RTX, 1); \
933 _temp = expand_and (gen_lowpart (SImode, _temp), \
934 GEN_INT (0x3fff), 0); \
936 _addr = memory_address (SImode, plus_constant ((TRAMP), 8)); \
937 _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr)); \
938 _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX); \
939 _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1, \
942 emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1); \
944 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \
945 "__enable_execute_stack"), \
946 0, VOIDmode, 1,_addr, Pmode); \
948 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
949 gen_rtvec (1, const0_rtx), 0)); \
952 /* Attempt to turn on access permissions for the stack. */
954 #define TRANSFER_FROM_TRAMPOLINE \
957 __enable_execute_stack (addr) \
960 long size = getpagesize (); \
961 long mask = ~(size-1); \
962 char *page = (char *) (((long) addr) & mask); \
963 char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
965 /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \
966 if (mprotect (page, end - page, 7) < 0) \
967 perror ("mprotect of trampoline code"); \
970 /* Addressing modes, and classification of registers for them. */
972 /* #define HAVE_POST_INCREMENT */
973 /* #define HAVE_POST_DECREMENT */
975 /* #define HAVE_PRE_DECREMENT */
976 /* #define HAVE_PRE_INCREMENT */
978 /* Macros to check register numbers against specific register classes. */
980 /* These assume that REGNO is a hard or pseudo reg number.
981 They give nonzero only if REGNO is a hard reg of the suitable class
982 or a pseudo reg currently allocated to a suitable hard reg.
983 Since they use reg_renumber, they are safe only once reg_renumber
984 has been allocated, which happens in local-alloc.c. */
986 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
987 #define REGNO_OK_FOR_BASE_P(REGNO) \
988 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
990 /* Maximum number of registers that can appear in a valid memory address. */
991 #define MAX_REGS_PER_ADDRESS 1
993 /* Recognize any constant value that is a valid address. For the Alpha,
994 there are only constants none since we want to use LDA to load any
995 symbolic addresses into registers. */
997 #define CONSTANT_ADDRESS_P(X) \
998 (GET_CODE (X) == CONST_INT \
999 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1001 /* Include all constant integers and constant doubles, but not
1002 floating-point, except for floating-point zero. */
1004 #define LEGITIMATE_CONSTANT_P(X) \
1005 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1006 || (X) == CONST0_RTX (GET_MODE (X)))
1008 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1009 and check its validity for a certain class.
1010 We have two alternate definitions for each of them.
1011 The usual definition accepts all pseudo regs; the other rejects
1012 them unless they have been allocated suitable hard regs.
1013 The symbol REG_OK_STRICT causes the latter definition to be used.
1015 Most source files want to accept pseudo regs in the hope that
1016 they will get allocated to the class that the insn wants them to be in.
1017 Source files for reload pass need to be strict.
1018 After reload, it makes no difference, since pseudo regs have
1019 been eliminated by then. */
1021 #ifndef REG_OK_STRICT
1023 /* Nonzero if X is a hard reg that can be used as an index
1024 or if it is a pseudo reg. */
1025 #define REG_OK_FOR_INDEX_P(X) 0
1026 /* Nonzero if X is a hard reg that can be used as a base reg
1027 or if it is a pseudo reg. */
1028 #define REG_OK_FOR_BASE_P(X) \
1029 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1033 /* Nonzero if X is a hard reg that can be used as an index. */
1034 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1035 /* Nonzero if X is a hard reg that can be used as a base reg. */
1036 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1040 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1041 that is a valid memory address for an instruction.
1042 The MODE argument is the machine mode for the MEM expression
1043 that wants to use this address.
1045 For Alpha, we have either a constant address or the sum of a register
1046 and a constant address, or just a register. For DImode, any of those
1047 forms can be surrounded with an AND that clear the low-order three bits;
1048 this is an "unaligned" access.
1050 We also allow a SYMBOL_REF that is the name of the current function as
1051 valid address. This is for CALL_INSNs. It cannot be used in any other
1054 First define the basic valid address. */
1056 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1057 { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1059 if (CONSTANT_ADDRESS_P (X)) \
1061 if (GET_CODE (X) == PLUS \
1062 && REG_P (XEXP (X, 0)) \
1063 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1064 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1068 /* Now accept the simple address, or, for DImode only, an AND of a simple
1069 address that turns off the low three bits. */
1071 extern char *current_function_name
;
1073 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1074 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1075 if ((MODE) == DImode \
1076 && GET_CODE (X) == AND \
1077 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1078 && INTVAL (XEXP (X, 1)) == -8) \
1079 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1080 if ((MODE) == Pmode && GET_CODE (X) == SYMBOL_REF \
1081 && ! strcmp (XSTR (X, 0), current_function_name)) \
1085 /* Try machine-dependent ways of modifying an illegitimate address
1086 to be legitimate. If we find one, return the new, valid address.
1087 This macro is used in only one place: `memory_address' in explow.c.
1089 OLDX is the address as it was before break_out_memory_refs was called.
1090 In some cases it is useful to look at this to decide what needs to be done.
1092 MODE and WIN are passed so that this macro can use
1093 GO_IF_LEGITIMATE_ADDRESS.
1095 It is always safe for this macro to do nothing. It exists to recognize
1096 opportunities to optimize the output.
1098 For the Alpha, there are three cases we handle:
1100 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1101 valid offset, compute the high part of the constant and add it to the
1102 register. Then our address is (plus temp low-part-const).
1103 (2) If the address is (const (plus FOO const_int)), find the low-order
1104 part of the CONST_INT. Then load FOO plus any high-order part of the
1105 CONST_INT into a register. Our address is (plus reg low-part-const).
1106 This is done to reduce the number of GOT entries.
1107 (3) If we have a (plus reg const), emit the load as in (2), then add
1108 the two registers, and finally generate (plus reg low-part-const) as
1111 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1112 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1113 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1114 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1116 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1117 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1118 HOST_WIDE_INT highpart = val - lowpart; \
1119 rtx high = GEN_INT (highpart); \
1120 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1121 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1123 (X) = plus_constant (temp, lowpart); \
1126 else if (GET_CODE (X) == CONST \
1127 && GET_CODE (XEXP (X, 0)) == PLUS \
1128 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1130 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1131 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1132 HOST_WIDE_INT highpart = val - lowpart; \
1133 rtx high = XEXP (XEXP (X, 0), 0); \
1136 high = plus_constant (high, highpart); \
1138 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1141 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1142 && GET_CODE (XEXP (X, 1)) == CONST \
1143 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1144 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1146 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1147 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1148 HOST_WIDE_INT highpart = val - lowpart; \
1149 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1152 high = plus_constant (high, highpart); \
1154 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1155 force_reg (Pmode, high), \
1156 high, 1, OPTAB_LIB_WIDEN); \
1157 (X) = plus_constant (high, lowpart); \
1162 /* Go to LABEL if ADDR (a legitimate address expression)
1163 has an effect that depends on the machine mode it is used for.
1164 On the Alpha this is true only for the unaligned modes. We can
1165 simplify this test since we know that the address must be valid. */
1167 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1168 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1170 /* Compute the cost of an address. For the Alpha, all valid addresses are
1173 #define ADDRESS_COST(X) 0
1175 /* Define this if some processing needs to be done immediately before
1176 emitting code for an insn. */
1178 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1180 /* Specify the machine mode that this machine uses
1181 for the index in the tablejump instruction. */
1182 #define CASE_VECTOR_MODE SImode
1184 /* Define this if the tablejump instruction expects the table
1185 to contain offsets from the address of the table.
1186 Do not define this if the table should contain absolute addresses. */
1187 /* #define CASE_VECTOR_PC_RELATIVE */
1189 /* Specify the tree operation to be used to convert reals to integers. */
1190 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1192 /* This is the kind of divide that is easiest to do in the general case. */
1193 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1195 /* Define this as 1 if `char' should by default be signed; else as 0. */
1196 #define DEFAULT_SIGNED_CHAR 1
1198 /* This flag, if defined, says the same insns that convert to a signed fixnum
1199 also convert validly to an unsigned one.
1201 We actually lie a bit here as overflow conditions are different. But
1202 they aren't being checked anyway. */
1204 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1206 /* Max number of bytes we can move to or from memory
1207 in one reasonably fast instruction. */
1211 /* Largest number of bytes of an object that can be placed in a register.
1212 On the Alpha we have plenty of registers, so use TImode. */
1213 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1215 /* Nonzero if access to memory by bytes is no faster than for words.
1216 Also non-zero if doing byte operations (specifically shifts) in registers
1219 On the Alpha, we want to not use the byte operation and instead use
1220 masking operations to access fields; these will save instructions. */
1222 #define SLOW_BYTE_ACCESS 1
1224 /* Define if normal loads of shorter-than-word items from memory clears
1225 the rest of the bits in the register. */
1226 /* #define BYTE_LOADS_ZERO_EXTEND */
1228 /* Define if normal loads of shorter-than-word items from memory sign-extends
1229 the rest of the bits in the register. */
1230 #define BYTE_LOADS_SIGN_EXTEND
1232 /* Define if loading short immediate values into registers sign extends. */
1233 #define SHORT_IMMEDIATES_SIGN_EXTEND
1235 /* We aren't doing ANYTHING about debugging for now. */
1236 /* #define SDB_DEBUGGING_INFO */
1238 /* Do not break .stabs pseudos into continuations. */
1239 #define DBX_CONTIN_LENGTH 0
1241 /* Don't try to use the `x' type-cross-reference character in DBX data.
1242 Also has the consequence of putting each struct, union or enum
1243 into a separate .stabs, containing only cross-refs to the others. */
1244 #define DBX_NO_XREFS
1246 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1247 is done just by pretending it is already truncated. */
1248 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1250 /* We assume that the store-condition-codes instructions store 0 for false
1251 and some other value for true. This is the value stored for true. */
1253 #define STORE_FLAG_VALUE 1
1255 /* Define the value returned by a floating-point comparison instruction. */
1257 #define FLOAT_STORE_FLAG_VALUE 0.5
1259 /* Specify the machine mode that pointers have.
1260 After generation of rtl, the compiler makes no further distinction
1261 between pointers and any other objects of this machine mode. */
1262 #define Pmode DImode
1264 /* Mode of a function address in a call instruction (for indexing purposes). */
1266 #define FUNCTION_MODE Pmode
1268 /* Define this if addresses of constant functions
1269 shouldn't be put through pseudo regs where they can be cse'd.
1270 Desirable on machines where ordinary constants are expensive
1271 but a CALL with constant address is cheap.
1273 We define this on the Alpha so that gen_call and gen_call_value
1274 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1275 then copy it into a register, thus actually letting the address be
1278 #define NO_FUNCTION_CSE
1280 /* Define this if shift instructions ignore all but the low-order
1282 #define SHIFT_COUNT_TRUNCATED
1284 /* Compute the cost of computing a constant rtl expression RTX
1285 whose rtx-code is CODE. The body of this macro is a portion
1286 of a switch statement. If the code is computed here,
1287 return it with a return statement. Otherwise, break from the switch.
1289 We only care about the cost if it is valid in an insn, so all constants
1292 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1294 case CONST_DOUBLE: \
1301 /* Provide the costs of a rtl expression. This is in the body of a
1304 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1307 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1308 return COSTS_N_INSNS (6); \
1309 else if (GET_CODE (XEXP (X, 0)) == MULT \
1310 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1311 return 2 + rtx_cost (XEXP (XEXP (X, 0), 0)) + rtx_cost (XEXP (X, 1)); \
1314 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1315 return COSTS_N_INSNS (6); \
1316 else if (GET_CODE (XEXP (X, 1)) != CONST_INT \
1317 || exact_log2 (INTVAL (XEXP (X, 1))) < 0) \
1318 return COSTS_N_INSNS (21); \
1319 else if (const48_operand (XEXP (X, 1), VOIDmode)) \
1321 return COSTS_N_INSNS (2); \
1323 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1324 && INTVAL (XEXP (X, 1)) <= 3) \
1326 /* ... fall through ... */ \
1327 case ASHIFTRT: case LSHIFTRT: case IF_THEN_ELSE: \
1328 return COSTS_N_INSNS (2); \
1333 if (GET_MODE (X) == SFmode) \
1334 return COSTS_N_INSNS (34); \
1335 else if (GET_MODE (X) == DFmode) \
1336 return COSTS_N_INSNS (63); \
1338 return COSTS_N_INSNS (70); \
1340 return COSTS_N_INSNS (3);
1342 /* Control the assembler format that we output. */
1344 /* Output at beginning of assembler file. */
1346 #define ASM_FILE_START(FILE) \
1347 { char *p, *after_dir = main_input_filename; \
1349 alpha_write_verstamp (FILE); \
1350 fprintf (FILE, "\t.set noreorder\n"); \
1351 fprintf (FILE, "\t.set noat\n"); \
1352 for (p = main_input_filename; *p; p++) \
1354 after_dir = p + 1; \
1355 fprintf (FILE, "\n\t.file 2 \"%s\"\n", after_dir); \
1358 /* Output to assembler file text saying following lines
1359 may contain character constants, extra white space, comments, etc. */
1361 #define ASM_APP_ON ""
1363 /* Output to assembler file text saying following lines
1364 no longer contain unusual constructs. */
1366 #define ASM_APP_OFF ""
1368 #define TEXT_SECTION_ASM_OP ".text"
1370 /* Output before read-only data. */
1372 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1374 /* Output before writable data. */
1376 #define DATA_SECTION_ASM_OP ".data"
1378 /* Define an extra section for read-only data, a routine to enter it, and
1379 indicate that it is for read-only data. */
1381 #define EXTRA_SECTIONS readonly_data
1383 #define EXTRA_SECTION_FUNCTIONS \
1385 literal_section () \
1387 if (in_section != readonly_data) \
1389 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1390 in_section = readonly_data; \
1394 #define READONLY_DATA_SECTION literal_section
1396 /* If we are referencing a function that is static or is known to be
1397 in this file, make the SYMBOL_REF special. We can use this to see
1398 indicate that we can branch to this function without setting PV or
1401 #define ENCODE_SECTION_INFO(DECL) \
1402 if (TREE_CODE (DECL) == FUNCTION_DECL \
1403 && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL))) \
1404 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1406 /* How to refer to registers in assembler output.
1407 This sequence is indexed by compiler's hard-register-number (see above). */
1409 #define REGISTER_NAMES \
1410 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1411 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1412 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1413 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1414 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1415 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1416 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1417 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"}
1419 /* How to renumber registers for dbx and gdb. */
1421 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1423 /* This is how to output the definition of a user-level label named NAME,
1424 such as the label on a static function or variable NAME. */
1426 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1427 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1429 /* This is how to output a command to make the user-level label named NAME
1430 defined for reference from other files. */
1432 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1433 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1435 /* This is how to output a reference to a user-level label named NAME.
1436 `assemble_name' uses this. */
1438 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1439 fprintf (FILE, "%s", NAME)
1441 /* This is how to output an internal numbered label where
1442 PREFIX is the class of label and NUM is the number within the class. */
1444 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1445 if ((PREFIX)[0] == 'L') \
1446 fprintf (FILE, "$%s%d:\n", & (PREFIX)[1], NUM + 32); \
1448 fprintf (FILE, "%s%d:\n", PREFIX, NUM);
1450 /* This is how to output a label for a jump table. Arguments are the same as
1451 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1454 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1455 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1457 /* This is how to store into the string LABEL
1458 the symbol_ref name of an internal numbered label where
1459 PREFIX is the class of label and NUM is the number within the class.
1460 This is suitable for output with `assemble_name'. */
1462 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1463 if ((PREFIX)[0] == 'L') \
1464 sprintf (LABEL, "*$%s%d", & (PREFIX)[1], NUM + 32); \
1466 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1468 /* This is how to output an assembler line defining a `double' constant. */
1470 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1472 if (REAL_VALUE_ISINF (VALUE) \
1473 || REAL_VALUE_ISNAN (VALUE) \
1474 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1477 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1478 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
1479 t[1] & 0xffffffff, t[0] & 0xffffffff); \
1484 REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
1485 fprintf (FILE, "\t.t_floating %s\n", str); \
1489 /* This is how to output an assembler line defining a `float' constant. */
1491 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1493 if (REAL_VALUE_ISINF (VALUE) \
1494 || REAL_VALUE_ISNAN (VALUE) \
1495 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1498 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1499 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
1504 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1505 fprintf (FILE, "\t.s_floating %s\n", str); \
1509 /* This is how to output an assembler line defining an `int' constant. */
1511 #define ASM_OUTPUT_INT(FILE,VALUE) \
1512 fprintf (FILE, "\t.long %d\n", \
1513 (GET_CODE (VALUE) == CONST_INT \
1514 ? INTVAL (VALUE) & 0xffffffff : (abort (), 0)))
1516 /* This is how to output an assembler line defining a `long' constant. */
1518 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1519 ( fprintf (FILE, "\t.quad "), \
1520 output_addr_const (FILE, (VALUE)), \
1521 fprintf (FILE, "\n"))
1523 /* Likewise for `char' and `short' constants. */
1525 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1526 fprintf (FILE, "\t.word %d\n", \
1527 (GET_CODE (VALUE) == CONST_INT \
1528 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
1530 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1531 fprintf (FILE, "\t.byte %d\n", \
1532 (GET_CODE (VALUE) == CONST_INT \
1533 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
1535 /* We use the default ASCII-output routine, except that we don't write more
1536 than 50 characters since the assembler doesn't support very long lines. */
1538 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
1540 FILE *_hide_asm_out_file = (MYFILE); \
1541 unsigned char *_hide_p = (unsigned char *) (MYSTRING); \
1542 int _hide_thissize = (MYLENGTH); \
1543 int _size_so_far = 0; \
1545 FILE *asm_out_file = _hide_asm_out_file; \
1546 unsigned char *p = _hide_p; \
1547 int thissize = _hide_thissize; \
1549 fprintf (asm_out_file, "\t.ascii \""); \
1551 for (i = 0; i < thissize; i++) \
1553 register int c = p[i]; \
1555 if (_size_so_far ++ > 50 && i < thissize - 4) \
1556 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
1558 if (c == '\"' || c == '\\') \
1559 putc ('\\', asm_out_file); \
1560 if (c >= ' ' && c < 0177) \
1561 putc (c, asm_out_file); \
1564 fprintf (asm_out_file, "\\%o", c); \
1565 /* After an octal-escape, if a digit follows, \
1566 terminate one string constant and start another. \
1567 The Vax assembler fails to stop reading the escape \
1568 after three digits, so this is the only way we \
1569 can get it to parse the data properly. */ \
1570 if (i < thissize - 1 \
1571 && p[i + 1] >= '0' && p[i + 1] <= '9') \
1572 fprintf (asm_out_file, "\"\n\t.ascii \""); \
1575 fprintf (asm_out_file, "\"\n"); \
1579 /* This is how to output an insn to push a register on the stack.
1580 It need not be very fast code. */
1582 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1583 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
1584 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1587 /* This is how to output an insn to pop a register from the stack.
1588 It need not be very fast code. */
1590 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1591 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
1592 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1595 /* This is how to output an assembler line for a numeric constant byte. */
1597 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1598 fprintf (FILE, "\t.byte 0x%x\n", (VALUE) & 0xff)
1600 /* This is how to output an element of a case-vector that is absolute. */
1602 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1603 fprintf (FILE, "\t.gprel32 $%d\n", (VALUE) + 32)
1605 /* This is how to output an element of a case-vector that is relative.
1606 (Alpha does not use such vectors, but we must define this macro anyway.) */
1608 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) abort ()
1610 /* This is how to output an assembler line
1611 that says to advance the location counter
1612 to a multiple of 2**LOG bytes. */
1614 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1616 fprintf (FILE, "\t.align %d\n", LOG);
1618 /* This is how to advance the location counter by SIZE bytes. */
1620 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1621 fprintf (FILE, "\t.space %d\n", (SIZE))
1623 /* This says how to output an assembler line
1624 to define a global common symbol. */
1626 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1627 ( fputs ("\t.comm ", (FILE)), \
1628 assemble_name ((FILE), (NAME)), \
1629 fprintf ((FILE), ",%d\n", (SIZE)))
1631 /* This says how to output an assembler line
1632 to define a local common symbol. */
1634 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1635 ( fputs ("\t.lcomm ", (FILE)), \
1636 assemble_name ((FILE), (NAME)), \
1637 fprintf ((FILE), ",%d\n", (SIZE)))
1639 /* Store in OUTPUT a string (made with alloca) containing
1640 an assembler-name for a local static variable named NAME.
1641 LABELNO is an integer which is different for each call. */
1643 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1644 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1645 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1647 /* Define the parentheses used to group arithmetic operations
1648 in assembler code. */
1650 #define ASM_OPEN_PAREN "("
1651 #define ASM_CLOSE_PAREN ")"
1653 /* Define results of standard character escape sequences. */
1654 #define TARGET_BELL 007
1655 #define TARGET_BS 010
1656 #define TARGET_TAB 011
1657 #define TARGET_NEWLINE 012
1658 #define TARGET_VT 013
1659 #define TARGET_FF 014
1660 #define TARGET_CR 015
1662 /* Print operand X (an rtx) in assembler syntax to file FILE.
1663 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1664 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1666 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1668 /* Determine which codes are valid without a following integer. These must
1669 not be alphabetic. */
1671 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) 0
1673 /* Print a memory address as an operand to reference that memory location. */
1675 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1676 { rtx addr = (ADDR); \
1678 HOST_WIDE_INT offset = 0; \
1680 if (GET_CODE (addr) == AND) \
1681 addr = XEXP (addr, 0); \
1683 if (GET_CODE (addr) == REG) \
1684 basereg = REGNO (addr); \
1685 else if (GET_CODE (addr) == CONST_INT) \
1686 offset = INTVAL (addr); \
1687 else if (GET_CODE (addr) == PLUS \
1688 && GET_CODE (XEXP (addr, 0)) == REG \
1689 && GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1690 basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \
1694 fprintf (FILE, "%d($%d)", offset, basereg); \
1696 /* Define the codes that are matched by predicates in alpha.c. */
1698 #define PREDICATE_CODES \
1699 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1700 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
1701 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
1702 {"add_operand", {SUBREG, REG, CONST_INT}}, \
1703 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
1704 {"const48_operand", {CONST_INT}}, \
1705 {"and_operand", {SUBREG, REG, CONST_INT}}, \
1706 {"mode_mask_operand", {CONST_INT}}, \
1707 {"mul8_operand", {CONST_INT}}, \
1708 {"mode_width_operand", {CONST_INT}}, \
1709 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1710 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
1711 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
1712 {"fp0_operand", {CONST_DOUBLE}}, \
1713 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
1714 SYMBOL_REF, CONST, LABEL_REF}}, \
1715 {"aligned_memory_operand", {MEM}}, \
1716 {"unaligned_memory_operand", {MEM}}, \
1717 {"any_memory_operand", {MEM}},