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[gcc.git] / gcc / config / alpha / alpha.h
1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 /* Target CPU builtins. */
24 #define TARGET_CPU_CPP_BUILTINS() \
25 do \
26 { \
27 builtin_define ("__alpha"); \
28 builtin_define ("__alpha__"); \
29 builtin_assert ("cpu=alpha"); \
30 builtin_assert ("machine=alpha"); \
31 if (TARGET_CIX) \
32 { \
33 builtin_define ("__alpha_cix__"); \
34 builtin_assert ("cpu=cix"); \
35 } \
36 if (TARGET_FIX) \
37 { \
38 builtin_define ("__alpha_fix__"); \
39 builtin_assert ("cpu=fix"); \
40 } \
41 if (TARGET_BWX) \
42 { \
43 builtin_define ("__alpha_bwx__"); \
44 builtin_assert ("cpu=bwx"); \
45 } \
46 if (TARGET_MAX) \
47 { \
48 builtin_define ("__alpha_max__"); \
49 builtin_assert ("cpu=max"); \
50 } \
51 if (TARGET_CPU_EV6) \
52 { \
53 builtin_define ("__alpha_ev6__"); \
54 builtin_assert ("cpu=ev6"); \
55 } \
56 else if (TARGET_CPU_EV5) \
57 { \
58 builtin_define ("__alpha_ev5__"); \
59 builtin_assert ("cpu=ev5"); \
60 } \
61 else /* Presumably ev4. */ \
62 { \
63 builtin_define ("__alpha_ev4__"); \
64 builtin_assert ("cpu=ev4"); \
65 } \
66 if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \
67 builtin_define ("__IEEE_FP"); \
68 if (TARGET_IEEE_WITH_INEXACT) \
69 builtin_define ("__IEEE_FP_INEXACT"); \
70 \
71 /* Macros dependent on the C dialect. */ \
72 if (preprocessing_asm_p ()) \
73 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
74 else if (c_language == clk_c) \
75 builtin_define_std ("LANGUAGE_C"); \
76 else if (c_language == clk_cplusplus) \
77 { \
78 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
79 builtin_define ("__LANGUAGE_C_PLUS_PLUS__");\
80 } \
81 else if (c_language == clk_objective_c) \
82 { \
83 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
84 builtin_define ("__LANGUAGE_OBJECTIVE_C__");\
85 } \
86 } while (0)
87
88 #define CPP_SPEC "%(cpp_subtarget)"
89
90 #ifndef CPP_SUBTARGET_SPEC
91 #define CPP_SUBTARGET_SPEC ""
92 #endif
93
94 #define WORD_SWITCH_TAKES_ARG(STR) \
95 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
96
97 /* Print subsidiary information on the compiler version in use. */
98 #define TARGET_VERSION
99
100 /* Run-time compilation parameters selecting different hardware subsets. */
101
102 /* Which processor to schedule for. The cpu attribute defines a list that
103 mirrors this list, so changes to alpha.md must be made at the same time. */
104
105 enum processor_type
106 {PROCESSOR_EV4, /* 2106[46]{a,} */
107 PROCESSOR_EV5, /* 21164{a,pc,} */
108 PROCESSOR_EV6}; /* 21264 */
109
110 extern enum processor_type alpha_cpu;
111
112 enum alpha_trap_precision
113 {
114 ALPHA_TP_PROG, /* No precision (default). */
115 ALPHA_TP_FUNC, /* Trap contained within originating function. */
116 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
117 };
118
119 enum alpha_fp_rounding_mode
120 {
121 ALPHA_FPRM_NORM, /* Normal rounding mode. */
122 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
123 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
124 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
125 };
126
127 enum alpha_fp_trap_mode
128 {
129 ALPHA_FPTM_N, /* Normal trap mode. */
130 ALPHA_FPTM_U, /* Underflow traps enabled. */
131 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
132 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
133 };
134
135 extern int target_flags;
136
137 extern enum alpha_trap_precision alpha_tp;
138 extern enum alpha_fp_rounding_mode alpha_fprm;
139 extern enum alpha_fp_trap_mode alpha_fptm;
140 extern int alpha_tls_size;
141
142 /* This means that floating-point support exists in the target implementation
143 of the Alpha architecture. This is usually the default. */
144 #define MASK_FP (1 << 0)
145 #define TARGET_FP (target_flags & MASK_FP)
146
147 /* This means that floating-point registers are allowed to be used. Note
148 that Alpha implementations without FP operations are required to
149 provide the FP registers. */
150
151 #define MASK_FPREGS (1 << 1)
152 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
153
154 /* This means that gas is used to process the assembler file. */
155
156 #define MASK_GAS (1 << 2)
157 #define TARGET_GAS (target_flags & MASK_GAS)
158
159 /* This means that we should mark procedures as IEEE conformant. */
160
161 #define MASK_IEEE_CONFORMANT (1 << 3)
162 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
163
164 /* This means we should be IEEE-compliant except for inexact. */
165
166 #define MASK_IEEE (1 << 4)
167 #define TARGET_IEEE (target_flags & MASK_IEEE)
168
169 /* This means we should be fully IEEE-compliant. */
170
171 #define MASK_IEEE_WITH_INEXACT (1 << 5)
172 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
173
174 /* This means we must construct all constants rather than emitting
175 them as literal data. */
176
177 #define MASK_BUILD_CONSTANTS (1 << 6)
178 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
179
180 /* This means we handle floating points in VAX F- (float)
181 or G- (double) Format. */
182
183 #define MASK_FLOAT_VAX (1 << 7)
184 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
185
186 /* This means that the processor has byte and half word loads and stores
187 (the BWX extension). */
188
189 #define MASK_BWX (1 << 8)
190 #define TARGET_BWX (target_flags & MASK_BWX)
191
192 /* This means that the processor has the MAX extension. */
193 #define MASK_MAX (1 << 9)
194 #define TARGET_MAX (target_flags & MASK_MAX)
195
196 /* This means that the processor has the FIX extension. */
197 #define MASK_FIX (1 << 10)
198 #define TARGET_FIX (target_flags & MASK_FIX)
199
200 /* This means that the processor has the CIX extension. */
201 #define MASK_CIX (1 << 11)
202 #define TARGET_CIX (target_flags & MASK_CIX)
203
204 /* This means use !literal style explicit relocations. */
205 #define MASK_EXPLICIT_RELOCS (1 << 12)
206 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
207
208 /* This means use 16-bit relocations to .sdata/.sbss. */
209 #define MASK_SMALL_DATA (1 << 13)
210 #define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)
211
212 /* This means emit thread pointer loads for kernel not user. */
213 #define MASK_TLS_KERNEL (1 << 14)
214 #define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL)
215
216 /* This means that the processor is an EV5, EV56, or PCA56.
217 Unlike alpha_cpu this is not affected by -mtune= setting. */
218 #define MASK_CPU_EV5 (1 << 28)
219 #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
220
221 /* Likewise for EV6. */
222 #define MASK_CPU_EV6 (1 << 29)
223 #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
224
225 /* This means we support the .arch directive in the assembler. Only
226 defined in TARGET_CPU_DEFAULT. */
227 #define MASK_SUPPORT_ARCH (1 << 30)
228 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
229
230 /* These are for target os support and cannot be changed at runtime. */
231 #define TARGET_ABI_WINDOWS_NT 0
232 #define TARGET_ABI_OPEN_VMS 0
233 #define TARGET_ABI_UNICOSMK 0
234 #define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT \
235 && !TARGET_ABI_OPEN_VMS \
236 && !TARGET_ABI_UNICOSMK)
237
238 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
239 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
240 #endif
241 #ifndef TARGET_AS_SLASH_BEFORE_SUFFIX
242 #define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS
243 #endif
244 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
245 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
246 #endif
247 #ifndef TARGET_HAS_XFLOATING_LIBS
248 #define TARGET_HAS_XFLOATING_LIBS 0
249 #endif
250 #ifndef TARGET_PROFILING_NEEDS_GP
251 #define TARGET_PROFILING_NEEDS_GP 0
252 #endif
253 #ifndef TARGET_LD_BUGGY_LDGP
254 #define TARGET_LD_BUGGY_LDGP 0
255 #endif
256 #ifndef TARGET_FIXUP_EV5_PREFETCH
257 #define TARGET_FIXUP_EV5_PREFETCH 0
258 #endif
259 #ifndef HAVE_AS_TLS
260 #define HAVE_AS_TLS 0
261 #endif
262
263 /* Macro to define tables used to set the flags.
264 This is a list in braces of pairs in braces,
265 each pair being { "NAME", VALUE }
266 where VALUE is the bits to set or minus the bits to clear.
267 An empty string NAME is used to identify the default VALUE. */
268
269 #define TARGET_SWITCHES \
270 { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
271 {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
272 {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
273 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
274 N_("Do not use fp registers")}, \
275 {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
276 {"gas", MASK_GAS, N_("Assume GAS")}, \
277 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
278 N_("Request IEEE-conformant math library routines (OSF/1)")}, \
279 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
280 N_("Emit IEEE-conformant code, without inexact exceptions")}, \
281 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
282 N_("Emit IEEE-conformant code, with inexact exceptions")}, \
283 {"build-constants", MASK_BUILD_CONSTANTS, \
284 N_("Do not emit complex integer constants to read-only memory")}, \
285 {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
286 {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
287 {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
288 {"no-bwx", -MASK_BWX, ""}, \
289 {"max", MASK_MAX, \
290 N_("Emit code for the motion video ISA extension")}, \
291 {"no-max", -MASK_MAX, ""}, \
292 {"fix", MASK_FIX, \
293 N_("Emit code for the fp move and sqrt ISA extension")}, \
294 {"no-fix", -MASK_FIX, ""}, \
295 {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
296 {"no-cix", -MASK_CIX, ""}, \
297 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
298 N_("Emit code using explicit relocation directives")}, \
299 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \
300 {"small-data", MASK_SMALL_DATA, \
301 N_("Emit 16-bit relocations to the small data areas")}, \
302 {"large-data", -MASK_SMALL_DATA, \
303 N_("Emit 32-bit relocations to the small data areas")}, \
304 {"tls-kernel", MASK_TLS_KERNEL, \
305 N_("Emit rdval instead of rduniq for thread pointer")}, \
306 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \
307 | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} }
308
309 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
310
311 #ifndef TARGET_CPU_DEFAULT
312 #define TARGET_CPU_DEFAULT 0
313 #endif
314
315 #ifndef TARGET_DEFAULT_EXPLICIT_RELOCS
316 #ifdef HAVE_AS_EXPLICIT_RELOCS
317 #define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS
318 #else
319 #define TARGET_DEFAULT_EXPLICIT_RELOCS 0
320 #endif
321 #endif
322
323 extern const char *alpha_cpu_string; /* For -mcpu= */
324 extern const char *alpha_tune_string; /* For -mtune= */
325 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
326 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
327 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
328 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
329 extern const char *alpha_tls_size_string; /* For -mtls-size= */
330
331 #define TARGET_OPTIONS \
332 { \
333 {"cpu=", &alpha_cpu_string, \
334 N_("Use features of and schedule given CPU")}, \
335 {"tune=", &alpha_tune_string, \
336 N_("Schedule given CPU")}, \
337 {"fp-rounding-mode=", &alpha_fprm_string, \
338 N_("Control the generated fp rounding mode")}, \
339 {"fp-trap-mode=", &alpha_fptm_string, \
340 N_("Control the IEEE trap mode")}, \
341 {"trap-precision=", &alpha_tp_string, \
342 N_("Control the precision given to fp exceptions")}, \
343 {"memory-latency=", &alpha_mlat_string, \
344 N_("Tune expected memory latency")}, \
345 {"tls-size=", &alpha_tls_size_string, \
346 N_("Specify bit size of immediate TLS offsets")}, \
347 }
348
349 /* This macro defines names of additional specifications to put in the
350 specs that can be used in various specifications like CC1_SPEC. Its
351 definition is an initializer with a subgrouping for each command option.
352
353 Each subgrouping contains a string constant, that defines the
354 specification name, and a string constant that used by the GNU CC driver
355 program.
356
357 Do not define this macro if it does not need to do anything. */
358
359 #ifndef SUBTARGET_EXTRA_SPECS
360 #define SUBTARGET_EXTRA_SPECS
361 #endif
362
363 #define EXTRA_SPECS \
364 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
365 SUBTARGET_EXTRA_SPECS
366
367
368 /* Sometimes certain combinations of command options do not make sense
369 on a particular target machine. You can define a macro
370 `OVERRIDE_OPTIONS' to take account of this. This macro, if
371 defined, is executed once just after all the command options have
372 been parsed.
373
374 On the Alpha, it is used to translate target-option strings into
375 numeric values. */
376
377 #define OVERRIDE_OPTIONS override_options ()
378
379
380 /* Define this macro to change register usage conditional on target flags.
381
382 On the Alpha, we use this to disable the floating-point registers when
383 they don't exist. */
384
385 #define CONDITIONAL_REGISTER_USAGE \
386 { \
387 int i; \
388 if (! TARGET_FPREGS) \
389 for (i = 32; i < 63; i++) \
390 fixed_regs[i] = call_used_regs[i] = 1; \
391 }
392
393
394 /* Show we can debug even without a frame pointer. */
395 #define CAN_DEBUG_WITHOUT_FP
396 \f
397 /* target machine storage layout */
398
399 /* Define the size of `int'. The default is the same as the word size. */
400 #define INT_TYPE_SIZE 32
401
402 /* Define the size of `long long'. The default is the twice the word size. */
403 #define LONG_LONG_TYPE_SIZE 64
404
405 /* The two floating-point formats we support are S-floating, which is
406 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
407 and `long double' are T. */
408
409 #define FLOAT_TYPE_SIZE 32
410 #define DOUBLE_TYPE_SIZE 64
411 #define LONG_DOUBLE_TYPE_SIZE 64
412
413 #define WCHAR_TYPE "unsigned int"
414 #define WCHAR_TYPE_SIZE 32
415
416 /* Define this macro if it is advisable to hold scalars in registers
417 in a wider mode than that declared by the program. In such cases,
418 the value is constrained to be within the bounds of the declared
419 type, but kept valid in the wider mode. The signedness of the
420 extension may differ from that of the type.
421
422 For Alpha, we always store objects in a full register. 32-bit objects
423 are always sign-extended, but smaller objects retain their signedness. */
424
425 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
426 if (GET_MODE_CLASS (MODE) == MODE_INT \
427 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
428 { \
429 if ((MODE) == SImode) \
430 (UNSIGNEDP) = 0; \
431 (MODE) = DImode; \
432 }
433
434 /* Define this if function arguments should also be promoted using the above
435 procedure. */
436
437 #define PROMOTE_FUNCTION_ARGS
438
439 /* Likewise, if the function return value is promoted. */
440
441 #define PROMOTE_FUNCTION_RETURN
442
443 /* Define this if most significant bit is lowest numbered
444 in instructions that operate on numbered bit-fields.
445
446 There are no such instructions on the Alpha, but the documentation
447 is little endian. */
448 #define BITS_BIG_ENDIAN 0
449
450 /* Define this if most significant byte of a word is the lowest numbered.
451 This is false on the Alpha. */
452 #define BYTES_BIG_ENDIAN 0
453
454 /* Define this if most significant word of a multiword number is lowest
455 numbered.
456
457 For Alpha we can decide arbitrarily since there are no machine instructions
458 for them. Might as well be consistent with bytes. */
459 #define WORDS_BIG_ENDIAN 0
460
461 /* Width of a word, in units (bytes). */
462 #define UNITS_PER_WORD 8
463
464 /* Width in bits of a pointer.
465 See also the macro `Pmode' defined below. */
466 #define POINTER_SIZE 64
467
468 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
469 #define PARM_BOUNDARY 64
470
471 /* Boundary (in *bits*) on which stack pointer should be aligned. */
472 #define STACK_BOUNDARY 64
473
474 /* Allocation boundary (in *bits*) for the code of a function. */
475 #define FUNCTION_BOUNDARY 32
476
477 /* Alignment of field after `int : 0' in a structure. */
478 #define EMPTY_FIELD_BOUNDARY 64
479
480 /* Every structure's size must be a multiple of this. */
481 #define STRUCTURE_SIZE_BOUNDARY 8
482
483 /* A bitfield declared as `int' forces `int' alignment for the struct. */
484 #define PCC_BITFIELD_TYPE_MATTERS 1
485
486 /* No data type wants to be aligned rounder than this. */
487 #define BIGGEST_ALIGNMENT 128
488
489 /* For atomic access to objects, must have at least 32-bit alignment
490 unless the machine has byte operations. */
491 #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
492
493 /* Align all constants and variables to at least a word boundary so
494 we can pick up pieces of them faster. */
495 /* ??? Only if block-move stuff knows about different source/destination
496 alignment. */
497 #if 0
498 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
499 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
500 #endif
501
502 /* Set this non-zero if move instructions will actually fail to work
503 when given unaligned data.
504
505 Since we get an error message when we do one, call them invalid. */
506
507 #define STRICT_ALIGNMENT 1
508
509 /* Set this non-zero if unaligned move instructions are extremely slow.
510
511 On the Alpha, they trap. */
512
513 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
514 \f
515 /* Standard register usage. */
516
517 /* Number of actual hardware registers.
518 The hardware registers are assigned numbers for the compiler
519 from 0 to just below FIRST_PSEUDO_REGISTER.
520 All registers that the compiler knows about must be given numbers,
521 even those that are not normally considered general registers.
522
523 We define all 32 integer registers, even though $31 is always zero,
524 and all 32 floating-point registers, even though $f31 is also
525 always zero. We do not bother defining the FP status register and
526 there are no other registers.
527
528 Since $31 is always zero, we will use register number 31 as the
529 argument pointer. It will never appear in the generated code
530 because we will always be eliminating it in favor of the stack
531 pointer or hardware frame pointer.
532
533 Likewise, we use $f31 for the frame pointer, which will always
534 be eliminated in favor of the hardware frame pointer or the
535 stack pointer. */
536
537 #define FIRST_PSEUDO_REGISTER 64
538
539 /* 1 for registers that have pervasive standard uses
540 and are not available for the register allocator. */
541
542 #define FIXED_REGISTERS \
543 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
545 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
547
548 /* 1 for registers not available across function calls.
549 These must include the FIXED_REGISTERS and also any
550 registers that can be used without being saved.
551 The latter must include the registers where values are returned
552 and the register where structure-value addresses are passed.
553 Aside from that, you can include as many other registers as you like. */
554 #define CALL_USED_REGISTERS \
555 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
557 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
559
560 /* List the order in which to allocate registers. Each register must be
561 listed once, even those in FIXED_REGISTERS.
562
563 We allocate in the following order:
564 $f10-$f15 (nonsaved floating-point register)
565 $f22-$f30 (likewise)
566 $f21-$f16 (likewise, but input args)
567 $f0 (nonsaved, but return value)
568 $f1 (nonsaved, but immediate before saved)
569 $f2-$f9 (saved floating-point registers)
570 $1-$8 (nonsaved integer registers)
571 $22-$25 (likewise)
572 $28 (likewise)
573 $0 (likewise, but return value)
574 $21-$16 (likewise, but input args)
575 $27 (procedure value in OSF, nonsaved in NT)
576 $9-$14 (saved integer registers)
577 $26 (return PC)
578 $15 (frame pointer)
579 $29 (global pointer)
580 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
581
582 #define REG_ALLOC_ORDER \
583 {42, 43, 44, 45, 46, 47, \
584 54, 55, 56, 57, 58, 59, 60, 61, 62, \
585 53, 52, 51, 50, 49, 48, \
586 32, 33, \
587 34, 35, 36, 37, 38, 39, 40, 41, \
588 1, 2, 3, 4, 5, 6, 7, 8, \
589 22, 23, 24, 25, \
590 28, \
591 0, \
592 21, 20, 19, 18, 17, 16, \
593 27, \
594 9, 10, 11, 12, 13, 14, \
595 26, \
596 15, \
597 29, \
598 30, 31, 63 }
599
600 /* Return number of consecutive hard regs needed starting at reg REGNO
601 to hold something of mode MODE.
602 This is ordinarily the length in words of a value of mode MODE
603 but can be less for certain modes in special long registers. */
604
605 #define HARD_REGNO_NREGS(REGNO, MODE) \
606 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
607
608 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
609 On Alpha, the integer registers can hold any mode. The floating-point
610 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
611 or 8-bit values. */
612
613 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
614 ((REGNO) >= 32 && (REGNO) <= 62 \
615 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
616 : 1)
617
618 /* A C expression that is nonzero if a value of mode
619 MODE1 is accessible in mode MODE2 without copying.
620
621 This asymmetric test is true when MODE1 could be put
622 in an FP register but MODE2 could not. */
623
624 #define MODES_TIEABLE_P(MODE1, MODE2) \
625 (HARD_REGNO_MODE_OK (32, (MODE1)) \
626 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
627 : 1)
628
629 /* Specify the registers used for certain standard purposes.
630 The values of these macros are register numbers. */
631
632 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
633 /* #define PC_REGNUM */
634
635 /* Register to use for pushing function arguments. */
636 #define STACK_POINTER_REGNUM 30
637
638 /* Base register for access to local variables of the function. */
639 #define HARD_FRAME_POINTER_REGNUM 15
640
641 /* Value should be nonzero if functions must have frame pointers.
642 Zero means the frame pointer need not be set up (and parms
643 may be accessed via the stack pointer) in functions that seem suitable.
644 This is computed in `reload', in reload1.c. */
645 #define FRAME_POINTER_REQUIRED 0
646
647 /* Base register for access to arguments of the function. */
648 #define ARG_POINTER_REGNUM 31
649
650 /* Base register for access to local variables of function. */
651 #define FRAME_POINTER_REGNUM 63
652
653 /* Register in which static-chain is passed to a function.
654
655 For the Alpha, this is based on an example; the calling sequence
656 doesn't seem to specify this. */
657 #define STATIC_CHAIN_REGNUM 1
658
659 /* The register number of the register used to address a table of
660 static data addresses in memory. */
661 #define PIC_OFFSET_TABLE_REGNUM 29
662
663 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM'
664 is clobbered by calls. */
665 /* ??? It is and it isn't. It's required to be valid for a given
666 function when the function returns. It isn't clobbered by
667 current_file functions. Moreover, we do not expose the ldgp
668 until after reload, so we're probably safe. */
669 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
670
671 /* Register in which address to store a structure value
672 arrives in the function. On the Alpha, the address is passed
673 as a hidden argument. */
674 #define STRUCT_VALUE 0
675 \f
676 /* Define the classes of registers for register constraints in the
677 machine description. Also define ranges of constants.
678
679 One of the classes must always be named ALL_REGS and include all hard regs.
680 If there is more than one class, another class must be named NO_REGS
681 and contain no registers.
682
683 The name GENERAL_REGS must be the name of a class (or an alias for
684 another name such as ALL_REGS). This is the class of registers
685 that is allowed by "g" or "r" in a register constraint.
686 Also, registers outside this class are allocated only when
687 instructions express preferences for them.
688
689 The classes must be numbered in nondecreasing order; that is,
690 a larger-numbered class must never be contained completely
691 in a smaller-numbered class.
692
693 For any two classes, it is very desirable that there be another
694 class that represents their union. */
695
696 enum reg_class {
697 NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG,
698 GENERAL_REGS, FLOAT_REGS, ALL_REGS,
699 LIM_REG_CLASSES
700 };
701
702 #define N_REG_CLASSES (int) LIM_REG_CLASSES
703
704 /* Give names of register classes as strings for dump file. */
705
706 #define REG_CLASS_NAMES \
707 {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \
708 "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
709
710 /* Define which registers fit in which classes.
711 This is an initializer for a vector of HARD_REG_SET
712 of length N_REG_CLASSES. */
713
714 #define REG_CLASS_CONTENTS \
715 { {0x00000000, 0x00000000}, /* NO_REGS */ \
716 {0x00000001, 0x00000000}, /* R0_REG */ \
717 {0x01000000, 0x00000000}, /* R24_REG */ \
718 {0x02000000, 0x00000000}, /* R25_REG */ \
719 {0x08000000, 0x00000000}, /* R27_REG */ \
720 {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \
721 {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \
722 {0xffffffff, 0xffffffff} }
723
724 /* The same information, inverted:
725 Return the class number of the smallest class containing
726 reg number REGNO. This could be a conditional expression
727 or could index an array. */
728
729 #define REGNO_REG_CLASS(REGNO) \
730 ((REGNO) == 0 ? R0_REG \
731 : (REGNO) == 24 ? R24_REG \
732 : (REGNO) == 25 ? R25_REG \
733 : (REGNO) == 27 ? R27_REG \
734 : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
735 : GENERAL_REGS)
736
737 /* The class value for index registers, and the one for base regs. */
738 #define INDEX_REG_CLASS NO_REGS
739 #define BASE_REG_CLASS GENERAL_REGS
740
741 /* Get reg_class from a letter such as appears in the machine description. */
742
743 #define REG_CLASS_FROM_LETTER(C) \
744 ((C) == 'a' ? R24_REG \
745 : (C) == 'b' ? R25_REG \
746 : (C) == 'c' ? R27_REG \
747 : (C) == 'f' ? FLOAT_REGS \
748 : (C) == 'v' ? R0_REG \
749 : NO_REGS)
750
751 /* Define this macro to change register usage conditional on target flags. */
752 /* #define CONDITIONAL_REGISTER_USAGE */
753
754 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
755 can be used to stand for particular ranges of immediate operands.
756 This macro defines what the ranges are.
757 C is the letter, and VALUE is a constant value.
758 Return 1 if VALUE is in the range specified by C.
759
760 For Alpha:
761 `I' is used for the range of constants most insns can contain.
762 `J' is the constant zero.
763 `K' is used for the constant in an LDA insn.
764 `L' is used for the constant in a LDAH insn.
765 `M' is used for the constants that can be AND'ed with using a ZAP insn.
766 `N' is used for complemented 8-bit constants.
767 `O' is used for negated 8-bit constants.
768 `P' is used for the constants 1, 2 and 3. */
769
770 #define CONST_OK_FOR_LETTER_P alpha_const_ok_for_letter_p
771
772 /* Similar, but for floating or large integer constants, and defining letters
773 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
774
775 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
776 that is the operand of a ZAP insn. */
777
778 #define CONST_DOUBLE_OK_FOR_LETTER_P alpha_const_double_ok_for_letter_p
779
780 /* Optional extra constraints for this machine.
781
782 For the Alpha, `Q' means that this is a memory operand but not a
783 reference to an unaligned location.
784
785 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
786 function.
787
788 'S' is a 6-bit constant (valid for a shift insn).
789
790 'T' is a HIGH.
791
792 'U' is a symbolic operand. */
793
794 #define EXTRA_CONSTRAINT alpha_extra_constraint
795
796 /* Given an rtx X being reloaded into a reg required to be
797 in class CLASS, return the class of reg to actually use.
798 In general this is just CLASS; but on some machines
799 in some cases it is preferable to use a more restrictive class. */
800
801 #define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class
802
803 /* Loading and storing HImode or QImode values to and from memory
804 usually requires a scratch register. The exceptions are loading
805 QImode and HImode from an aligned address to a general register
806 unless byte instructions are permitted.
807 We also cannot load an unaligned address or a paradoxical SUBREG into an
808 FP register. */
809
810 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
811 secondary_reload_class((CLASS), (MODE), (IN), 1)
812
813 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
814 secondary_reload_class((CLASS), (MODE), (OUT), 0)
815
816 /* If we are copying between general and FP registers, we need a memory
817 location unless the FIX extension is available. */
818
819 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
820 (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \
821 || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS)))
822
823 /* Specify the mode to be used for memory when a secondary memory
824 location is needed. If MODE is floating-point, use it. Otherwise,
825 widen to a word like the default. This is needed because we always
826 store integers in FP registers in quadword format. This whole
827 area is very tricky! */
828 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
829 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
830 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
831 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
832
833 /* Return the maximum number of consecutive registers
834 needed to represent mode MODE in a register of class CLASS. */
835
836 #define CLASS_MAX_NREGS(CLASS, MODE) \
837 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
838
839 /* If defined, gives a class of registers that cannot be used as the
840 operand of a SUBREG that changes the mode of the object illegally. */
841
842 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
843
844 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
845
846 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
847 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
848
849 /* Define the cost of moving between registers of various classes. Moving
850 between FLOAT_REGS and anything else except float regs is expensive.
851 In fact, we make it quite expensive because we really don't want to
852 do these moves unless it is clearly worth it. Optimizations may
853 reduce the impact of not being able to allocate a pseudo to a
854 hard register. */
855
856 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
857 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
858 ? 2 \
859 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
860
861 /* A C expressions returning the cost of moving data of MODE from a register to
862 or from memory.
863
864 On the Alpha, bump this up a bit. */
865
866 extern int alpha_memory_latency;
867 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
868
869 /* Provide the cost of a branch. Exact meaning under development. */
870 #define BRANCH_COST 5
871 \f
872 /* Stack layout; function entry, exit and calling. */
873
874 /* Define this if pushing a word on the stack
875 makes the stack pointer a smaller address. */
876 #define STACK_GROWS_DOWNWARD
877
878 /* Define this if the nominal address of the stack frame
879 is at the high-address end of the local variables;
880 that is, each additional local variable allocated
881 goes at a more negative offset in the frame. */
882 /* #define FRAME_GROWS_DOWNWARD */
883
884 /* Offset within stack frame to start allocating local variables at.
885 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
886 first local allocated. Otherwise, it is the offset to the BEGINNING
887 of the first local allocated. */
888
889 #define STARTING_FRAME_OFFSET 0
890
891 /* If we generate an insn to push BYTES bytes,
892 this says how many the stack pointer really advances by.
893 On Alpha, don't define this because there are no push insns. */
894 /* #define PUSH_ROUNDING(BYTES) */
895
896 /* Define this to be nonzero if stack checking is built into the ABI. */
897 #define STACK_CHECK_BUILTIN 1
898
899 /* Define this if the maximum size of all the outgoing args is to be
900 accumulated and pushed during the prologue. The amount can be
901 found in the variable current_function_outgoing_args_size. */
902 #define ACCUMULATE_OUTGOING_ARGS 1
903
904 /* Offset of first parameter from the argument pointer register value. */
905
906 #define FIRST_PARM_OFFSET(FNDECL) 0
907
908 /* Definitions for register eliminations.
909
910 We have two registers that can be eliminated on the Alpha. First, the
911 frame pointer register can often be eliminated in favor of the stack
912 pointer register. Secondly, the argument pointer register can always be
913 eliminated; it is replaced with either the stack or frame pointer. */
914
915 /* This is an array of structures. Each structure initializes one pair
916 of eliminable registers. The "from" register number is given first,
917 followed by "to". Eliminations of the same "from" register are listed
918 in order of preference. */
919
920 #define ELIMINABLE_REGS \
921 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
922 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
923 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
924 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
925
926 /* Given FROM and TO register numbers, say whether this elimination is allowed.
927 Frame pointer elimination is automatically handled.
928
929 All eliminations are valid since the cases where FP can't be
930 eliminated are already handled. */
931
932 #define CAN_ELIMINATE(FROM, TO) 1
933
934 /* Round up to a multiple of 16 bytes. */
935 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
936
937 /* Define the offset between two registers, one to be eliminated, and the other
938 its replacement, at the start of a routine. */
939 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
940 { if ((FROM) == FRAME_POINTER_REGNUM) \
941 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
942 + alpha_sa_size ()); \
943 else if ((FROM) == ARG_POINTER_REGNUM) \
944 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
945 + alpha_sa_size () \
946 + (ALPHA_ROUND (get_frame_size () \
947 + current_function_pretend_args_size) \
948 - current_function_pretend_args_size)); \
949 else \
950 abort (); \
951 }
952
953 /* Define this if stack space is still allocated for a parameter passed
954 in a register. */
955 /* #define REG_PARM_STACK_SPACE */
956
957 /* Value is the number of bytes of arguments automatically
958 popped when returning from a subroutine call.
959 FUNDECL is the declaration node of the function (as a tree),
960 FUNTYPE is the data type of the function (as a tree),
961 or for a library call it is an identifier node for the subroutine name.
962 SIZE is the number of bytes of arguments passed on the stack. */
963
964 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
965
966 /* Define how to find the value returned by a function.
967 VALTYPE is the data type of the value (as a tree).
968 If the precise function being called is known, FUNC is its FUNCTION_DECL;
969 otherwise, FUNC is 0.
970
971 On Alpha the value is found in $0 for integer functions and
972 $f0 for floating-point functions. */
973
974 #define FUNCTION_VALUE(VALTYPE, FUNC) \
975 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
976 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
977 || POINTER_TYPE_P (VALTYPE)) \
978 ? word_mode : TYPE_MODE (VALTYPE), \
979 ((TARGET_FPREGS \
980 && (TREE_CODE (VALTYPE) == REAL_TYPE \
981 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
982 ? 32 : 0))
983
984 /* Define how to find the value returned by a library function
985 assuming the value has mode MODE. */
986
987 #define LIBCALL_VALUE(MODE) \
988 gen_rtx_REG (MODE, \
989 (TARGET_FPREGS \
990 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
991 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
992 ? 32 : 0))
993
994 /* The definition of this macro implies that there are cases where
995 a scalar value cannot be returned in registers.
996
997 For the Alpha, any structure or union type is returned in memory, as
998 are integers whose size is larger than 64 bits. */
999
1000 #define RETURN_IN_MEMORY(TYPE) \
1001 (TYPE_MODE (TYPE) == BLKmode \
1002 || TYPE_MODE (TYPE) == TFmode \
1003 || TYPE_MODE (TYPE) == TCmode \
1004 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1005
1006 /* 1 if N is a possible register number for a function value
1007 as seen by the caller. */
1008
1009 #define FUNCTION_VALUE_REGNO_P(N) \
1010 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1011
1012 /* 1 if N is a possible register number for function argument passing.
1013 On Alpha, these are $16-$21 and $f16-$f21. */
1014
1015 #define FUNCTION_ARG_REGNO_P(N) \
1016 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1017 \f
1018 /* Define a data type for recording info about an argument list
1019 during the scan of that argument list. This data type should
1020 hold all necessary information about the function itself
1021 and about the args processed so far, enough to enable macros
1022 such as FUNCTION_ARG to determine where the next arg should go.
1023
1024 On Alpha, this is a single integer, which is a number of words
1025 of arguments scanned so far.
1026 Thus 6 or more means all following args should go on the stack. */
1027
1028 #define CUMULATIVE_ARGS int
1029
1030 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1031 for a call to a function whose data type is FNTYPE.
1032 For a library call, FNTYPE is 0. */
1033
1034 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1035
1036 /* Define intermediate macro to compute the size (in registers) of an argument
1037 for the Alpha. */
1038
1039 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1040 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1041 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1042 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1043
1044 /* Update the data in CUM to advance over an argument
1045 of mode MODE and data type TYPE.
1046 (TYPE is null for libcalls where that information may not be available.) */
1047
1048 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1049 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1050 (CUM) = 6; \
1051 else \
1052 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1053
1054 /* Determine where to put an argument to a function.
1055 Value is zero to push the argument on the stack,
1056 or a hard register in which to store the argument.
1057
1058 MODE is the argument's machine mode.
1059 TYPE is the data type of the argument (as a tree).
1060 This is null for libcalls where that information may
1061 not be available.
1062 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1063 the preceding args and about the function being called.
1064 NAMED is nonzero if this argument is a named parameter
1065 (otherwise it is an extra parameter matching an ellipsis).
1066
1067 On Alpha the first 6 words of args are normally in registers
1068 and the rest are pushed. */
1069
1070 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1071 function_arg((CUM), (MODE), (TYPE), (NAMED))
1072
1073 /* A C expression that indicates when an argument must be passed by
1074 reference. If nonzero for an argument, a copy of that argument is
1075 made in memory and a pointer to the argument is passed instead of
1076 the argument itself. The pointer is passed in whatever way is
1077 appropriate for passing a pointer to that type. */
1078
1079 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1080 ((MODE) == TFmode || (MODE) == TCmode)
1081
1082 /* Specify the padding direction of arguments.
1083
1084 On the Alpha, we must pad upwards in order to be able to pass args in
1085 registers. */
1086
1087 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1088
1089 /* For an arg passed partly in registers and partly in memory,
1090 this is the number of registers used.
1091 For args passed entirely in registers or entirely in memory, zero. */
1092
1093 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1094 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1095 ? 6 - (CUM) : 0)
1096
1097 /* Perform any needed actions needed for a function that is receiving a
1098 variable number of arguments.
1099
1100 CUM is as above.
1101
1102 MODE and TYPE are the mode and type of the current parameter.
1103
1104 PRETEND_SIZE is a variable that should be set to the amount of stack
1105 that must be pushed by the prolog to pretend that our caller pushed
1106 it.
1107
1108 Normally, this macro will push all remaining incoming registers on the
1109 stack and set PRETEND_SIZE to the length of the registers pushed.
1110
1111 On the Alpha, we allocate space for all 12 arg registers, but only
1112 push those that are remaining.
1113
1114 However, if NO registers need to be saved, don't allocate any space.
1115 This is not only because we won't need the space, but because AP includes
1116 the current_pretend_args_size and we don't want to mess up any
1117 ap-relative addresses already made.
1118
1119 If we are not to use the floating-point registers, save the integer
1120 registers where we would put the floating-point registers. This is
1121 not the most efficient way to implement varargs with just one register
1122 class, but it isn't worth doing anything more efficient in this rare
1123 case. */
1124
1125 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1126 { if ((CUM) < 6) \
1127 { \
1128 if (! (NO_RTL)) \
1129 { \
1130 rtx tmp; int set = get_varargs_alias_set (); \
1131 tmp = gen_rtx_MEM (BLKmode, \
1132 plus_constant (virtual_incoming_args_rtx, \
1133 ((CUM) + 6)* UNITS_PER_WORD)); \
1134 set_mem_alias_set (tmp, set); \
1135 move_block_from_reg \
1136 (16 + CUM, tmp, \
1137 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1138 \
1139 tmp = gen_rtx_MEM (BLKmode, \
1140 plus_constant (virtual_incoming_args_rtx, \
1141 (CUM) * UNITS_PER_WORD)); \
1142 set_mem_alias_set (tmp, set); \
1143 move_block_from_reg \
1144 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1145 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1146 } \
1147 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1148 } \
1149 }
1150
1151 /* We do not allow indirect calls to be optimized into sibling calls, nor
1152 can we allow a call to a function in a different compilation unit to
1153 be optimized into a sibcall. Except if the function is known not to
1154 return, in which case our caller doesn't care what the gp is. */
1155 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1156 (DECL \
1157 && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \
1158 || ! TREE_PUBLIC (DECL)))
1159
1160 /* Try to output insns to set TARGET equal to the constant C if it can be
1161 done in less than N insns. Do all computations in MODE. Returns the place
1162 where the output has been placed if it can be done and the insns have been
1163 emitted. If it would take more than N insns, zero is returned and no
1164 insns and emitted. */
1165
1166 /* Define the information needed to generate branch and scc insns. This is
1167 stored from the compare operation. Note that we can't use "rtx" here
1168 since it hasn't been defined! */
1169
1170 struct alpha_compare
1171 {
1172 struct rtx_def *op0, *op1;
1173 int fp_p;
1174 };
1175
1176 extern struct alpha_compare alpha_compare;
1177
1178 /* Make (or fake) .linkage entry for function call.
1179 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1180
1181 /* This macro defines the start of an assembly comment. */
1182
1183 #define ASM_COMMENT_START " #"
1184
1185 /* This macro produces the initial definition of a function. */
1186
1187 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1188 alpha_start_function(FILE,NAME,DECL);
1189
1190 /* This macro closes up a function definition for the assembler. */
1191
1192 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1193 alpha_end_function(FILE,NAME,DECL)
1194
1195 /* Output any profiling code before the prologue. */
1196
1197 #define PROFILE_BEFORE_PROLOGUE 1
1198
1199 /* Output assembler code to FILE to increment profiler label # LABELNO
1200 for profiling a function entry. Under OSF/1, profiling is enabled
1201 by simply passing -pg to the assembler and linker. */
1202
1203 #define FUNCTION_PROFILER(FILE, LABELNO)
1204
1205 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1206 the stack pointer does not matter. The value is tested only in
1207 functions that have frame pointers.
1208 No definition is equivalent to always zero. */
1209
1210 #define EXIT_IGNORE_STACK 1
1211
1212 /* Define registers used by the epilogue and return instruction. */
1213
1214 #define EPILOGUE_USES(REGNO) ((REGNO) == 26)
1215 \f
1216 /* Output assembler code for a block containing the constant parts
1217 of a trampoline, leaving space for the variable parts.
1218
1219 The trampoline should set the static chain pointer to value placed
1220 into the trampoline and should branch to the specified routine.
1221 Note that $27 has been set to the address of the trampoline, so we can
1222 use it for addressability of the two data items. */
1223
1224 #define TRAMPOLINE_TEMPLATE(FILE) \
1225 do { \
1226 fprintf (FILE, "\tldq $1,24($27)\n"); \
1227 fprintf (FILE, "\tldq $27,16($27)\n"); \
1228 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1229 fprintf (FILE, "\tnop\n"); \
1230 fprintf (FILE, "\t.quad 0,0\n"); \
1231 } while (0)
1232
1233 /* Section in which to place the trampoline. On Alpha, instructions
1234 may only be placed in a text segment. */
1235
1236 #define TRAMPOLINE_SECTION text_section
1237
1238 /* Length in units of the trampoline for entering a nested function. */
1239
1240 #define TRAMPOLINE_SIZE 32
1241
1242 /* The alignment of a trampoline, in bits. */
1243
1244 #define TRAMPOLINE_ALIGNMENT 64
1245
1246 /* Emit RTL insns to initialize the variable parts of a trampoline.
1247 FNADDR is an RTX for the address of the function's pure code.
1248 CXT is an RTX for the static chain value for the function. */
1249
1250 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1251 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1252
1253 /* A C expression whose value is RTL representing the value of the return
1254 address for the frame COUNT steps up from the current frame.
1255 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1256 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1257
1258 #define RETURN_ADDR_RTX alpha_return_addr
1259
1260 /* Before the prologue, RA lives in $26. */
1261 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1262 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
1263
1264 /* Describe how we implement __builtin_eh_return. */
1265 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM)
1266 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28)
1267 #define EH_RETURN_HANDLER_RTX \
1268 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1269 current_function_outgoing_args_size))
1270 \f
1271 /* Addressing modes, and classification of registers for them. */
1272
1273 /* #define HAVE_POST_INCREMENT 0 */
1274 /* #define HAVE_POST_DECREMENT 0 */
1275
1276 /* #define HAVE_PRE_DECREMENT 0 */
1277 /* #define HAVE_PRE_INCREMENT 0 */
1278
1279 /* Macros to check register numbers against specific register classes. */
1280
1281 /* These assume that REGNO is a hard or pseudo reg number.
1282 They give nonzero only if REGNO is a hard reg of the suitable class
1283 or a pseudo reg currently allocated to a suitable hard reg.
1284 Since they use reg_renumber, they are safe only once reg_renumber
1285 has been allocated, which happens in local-alloc.c. */
1286
1287 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1288 #define REGNO_OK_FOR_BASE_P(REGNO) \
1289 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1290 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1291 \f
1292 /* Maximum number of registers that can appear in a valid memory address. */
1293 #define MAX_REGS_PER_ADDRESS 1
1294
1295 /* Recognize any constant value that is a valid address. For the Alpha,
1296 there are only constants none since we want to use LDA to load any
1297 symbolic addresses into registers. */
1298
1299 #define CONSTANT_ADDRESS_P(X) \
1300 (GET_CODE (X) == CONST_INT \
1301 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1302
1303 /* Include all constant integers and constant doubles, but not
1304 floating-point, except for floating-point zero. */
1305
1306 #define LEGITIMATE_CONSTANT_P(X) \
1307 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1308 || (X) == CONST0_RTX (GET_MODE (X)))
1309
1310 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1311 and check its validity for a certain class.
1312 We have two alternate definitions for each of them.
1313 The usual definition accepts all pseudo regs; the other rejects
1314 them unless they have been allocated suitable hard regs.
1315 The symbol REG_OK_STRICT causes the latter definition to be used.
1316
1317 Most source files want to accept pseudo regs in the hope that
1318 they will get allocated to the class that the insn wants them to be in.
1319 Source files for reload pass need to be strict.
1320 After reload, it makes no difference, since pseudo regs have
1321 been eliminated by then. */
1322
1323 /* Nonzero if X is a hard reg that can be used as an index
1324 or if it is a pseudo reg. */
1325 #define REG_OK_FOR_INDEX_P(X) 0
1326
1327 /* Nonzero if X is a hard reg that can be used as a base reg
1328 or if it is a pseudo reg. */
1329 #define NONSTRICT_REG_OK_FOR_BASE_P(X) \
1330 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1331
1332 /* ??? Nonzero if X is the frame pointer, or some virtual register
1333 that may eliminate to the frame pointer. These will be allowed to
1334 have offsets greater than 32K. This is done because register
1335 elimination offsets will change the hi/lo split, and if we split
1336 before reload, we will require additional instructions. */
1337 #define NONSTRICT_REG_OK_FP_BASE_P(X) \
1338 (REGNO (X) == 31 || REGNO (X) == 63 \
1339 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1340 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1341
1342 /* Nonzero if X is a hard reg that can be used as a base reg. */
1343 #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1344
1345 #ifdef REG_OK_STRICT
1346 #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X)
1347 #else
1348 #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X)
1349 #endif
1350 \f
1351 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1352 valid memory address for an instruction. */
1353
1354 #ifdef REG_OK_STRICT
1355 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1356 do { \
1357 if (alpha_legitimate_address_p (MODE, X, 1)) \
1358 goto WIN; \
1359 } while (0)
1360 #else
1361 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1362 do { \
1363 if (alpha_legitimate_address_p (MODE, X, 0)) \
1364 goto WIN; \
1365 } while (0)
1366 #endif
1367
1368 /* Try machine-dependent ways of modifying an illegitimate address
1369 to be legitimate. If we find one, return the new, valid address.
1370 This macro is used in only one place: `memory_address' in explow.c. */
1371
1372 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1373 do { \
1374 rtx new_x = alpha_legitimize_address (X, NULL_RTX, MODE); \
1375 if (new_x) \
1376 { \
1377 X = new_x; \
1378 goto WIN; \
1379 } \
1380 } while (0)
1381
1382 /* Try a machine-dependent way of reloading an illegitimate address
1383 operand. If we find one, push the reload and jump to WIN. This
1384 macro is used in only one place: `find_reloads_address' in reload.c. */
1385
1386 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
1387 do { \
1388 rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
1389 if (new_x) \
1390 { \
1391 X = new_x; \
1392 goto WIN; \
1393 } \
1394 } while (0)
1395
1396 /* Go to LABEL if ADDR (a legitimate address expression)
1397 has an effect that depends on the machine mode it is used for.
1398 On the Alpha this is true only for the unaligned modes. We can
1399 simplify this test since we know that the address must be valid. */
1400
1401 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1402 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1403
1404 /* Compute the cost of an address. For the Alpha, all valid addresses are
1405 the same cost. */
1406
1407 #define ADDRESS_COST(X) 0
1408
1409 /* Machine-dependent reorg pass. */
1410 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1411 \f
1412 /* Specify the machine mode that this machine uses
1413 for the index in the tablejump instruction. */
1414 #define CASE_VECTOR_MODE SImode
1415
1416 /* Define as C expression which evaluates to nonzero if the tablejump
1417 instruction expects the table to contain offsets from the address of the
1418 table.
1419
1420 Do not define this if the table should contain absolute addresses.
1421 On the Alpha, the table is really GP-relative, not relative to the PC
1422 of the table, but we pretend that it is PC-relative; this should be OK,
1423 but we should try to find some better way sometime. */
1424 #define CASE_VECTOR_PC_RELATIVE 1
1425
1426 /* Define this as 1 if `char' should by default be signed; else as 0. */
1427 #define DEFAULT_SIGNED_CHAR 1
1428
1429 /* This flag, if defined, says the same insns that convert to a signed fixnum
1430 also convert validly to an unsigned one.
1431
1432 We actually lie a bit here as overflow conditions are different. But
1433 they aren't being checked anyway. */
1434
1435 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1436
1437 /* Max number of bytes we can move to or from memory
1438 in one reasonably fast instruction. */
1439
1440 #define MOVE_MAX 8
1441
1442 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1443 move-instruction pairs, we will do a movstr or libcall instead.
1444
1445 Without byte/word accesses, we want no more than four instructions;
1446 with, several single byte accesses are better. */
1447
1448 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1449
1450 /* Largest number of bytes of an object that can be placed in a register.
1451 On the Alpha we have plenty of registers, so use TImode. */
1452 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1453
1454 /* Nonzero if access to memory by bytes is no faster than for words.
1455 Also non-zero if doing byte operations (specifically shifts) in registers
1456 is undesirable.
1457
1458 On the Alpha, we want to not use the byte operation and instead use
1459 masking operations to access fields; these will save instructions. */
1460
1461 #define SLOW_BYTE_ACCESS 1
1462
1463 /* Define if operations between registers always perform the operation
1464 on the full register even if a narrower mode is specified. */
1465 #define WORD_REGISTER_OPERATIONS
1466
1467 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1468 will either zero-extend or sign-extend. The value of this macro should
1469 be the code that says which one of the two operations is implicitly
1470 done, NIL if none. */
1471 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1472
1473 /* Define if loading short immediate values into registers sign extends. */
1474 #define SHORT_IMMEDIATES_SIGN_EXTEND
1475
1476 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1477 is done just by pretending it is already truncated. */
1478 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1479
1480 /* We assume that the store-condition-codes instructions store 0 for false
1481 and some other value for true. This is the value stored for true. */
1482
1483 #define STORE_FLAG_VALUE 1
1484
1485 /* Define the value returned by a floating-point comparison instruction. */
1486
1487 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1488 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1489
1490 /* Canonicalize a comparison from one we don't have to one we do have. */
1491
1492 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1493 do { \
1494 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1495 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1496 { \
1497 rtx tem = (OP0); \
1498 (OP0) = (OP1); \
1499 (OP1) = tem; \
1500 (CODE) = swap_condition (CODE); \
1501 } \
1502 if (((CODE) == LT || (CODE) == LTU) \
1503 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1504 { \
1505 (CODE) = (CODE) == LT ? LE : LEU; \
1506 (OP1) = GEN_INT (255); \
1507 } \
1508 } while (0)
1509
1510 /* Specify the machine mode that pointers have.
1511 After generation of rtl, the compiler makes no further distinction
1512 between pointers and any other objects of this machine mode. */
1513 #define Pmode DImode
1514
1515 /* Mode of a function address in a call instruction (for indexing purposes). */
1516
1517 #define FUNCTION_MODE Pmode
1518
1519 /* Define this if addresses of constant functions
1520 shouldn't be put through pseudo regs where they can be cse'd.
1521 Desirable on machines where ordinary constants are expensive
1522 but a CALL with constant address is cheap.
1523
1524 We define this on the Alpha so that gen_call and gen_call_value
1525 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1526 then copy it into a register, thus actually letting the address be
1527 cse'ed. */
1528
1529 #define NO_FUNCTION_CSE
1530
1531 /* Define this to be nonzero if shift instructions ignore all but the low-order
1532 few bits. */
1533 #define SHIFT_COUNT_TRUNCATED 1
1534
1535 /* Compute the cost of computing a constant rtl expression RTX
1536 whose rtx-code is CODE. The body of this macro is a portion
1537 of a switch statement. If the code is computed here,
1538 return it with a return statement. Otherwise, break from the switch.
1539
1540 If this is an 8-bit constant, return zero since it can be used
1541 nearly anywhere with no cost. If it is a valid operand for an
1542 ADD or AND, likewise return 0 if we know it will be used in that
1543 context. Otherwise, return 2 since it might be used there later.
1544 All other constants take at least two insns. */
1545
1546 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1547 case CONST_INT: \
1548 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1549 return 0; \
1550 case CONST_DOUBLE: \
1551 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1552 return 0; \
1553 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1554 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1555 return 0; \
1556 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1557 return 2; \
1558 else \
1559 return COSTS_N_INSNS (2); \
1560 case CONST: \
1561 case SYMBOL_REF: \
1562 case LABEL_REF: \
1563 switch (alpha_cpu) \
1564 { \
1565 case PROCESSOR_EV4: \
1566 return COSTS_N_INSNS (3); \
1567 case PROCESSOR_EV5: \
1568 case PROCESSOR_EV6: \
1569 return COSTS_N_INSNS (2); \
1570 default: abort(); \
1571 }
1572
1573 /* Provide the costs of a rtl expression. This is in the body of a
1574 switch on CODE. */
1575
1576 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1577 case PLUS: case MINUS: \
1578 if (FLOAT_MODE_P (GET_MODE (X))) \
1579 switch (alpha_cpu) \
1580 { \
1581 case PROCESSOR_EV4: \
1582 return COSTS_N_INSNS (6); \
1583 case PROCESSOR_EV5: \
1584 case PROCESSOR_EV6: \
1585 return COSTS_N_INSNS (4); \
1586 default: abort(); \
1587 } \
1588 else if (GET_CODE (XEXP (X, 0)) == MULT \
1589 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1590 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1591 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1592 break; \
1593 case MULT: \
1594 switch (alpha_cpu) \
1595 { \
1596 case PROCESSOR_EV4: \
1597 if (FLOAT_MODE_P (GET_MODE (X))) \
1598 return COSTS_N_INSNS (6); \
1599 return COSTS_N_INSNS (23); \
1600 case PROCESSOR_EV5: \
1601 if (FLOAT_MODE_P (GET_MODE (X))) \
1602 return COSTS_N_INSNS (4); \
1603 else if (GET_MODE (X) == DImode) \
1604 return COSTS_N_INSNS (12); \
1605 else \
1606 return COSTS_N_INSNS (8); \
1607 case PROCESSOR_EV6: \
1608 if (FLOAT_MODE_P (GET_MODE (X))) \
1609 return COSTS_N_INSNS (4); \
1610 else \
1611 return COSTS_N_INSNS (7); \
1612 default: abort(); \
1613 } \
1614 case ASHIFT: \
1615 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1616 && INTVAL (XEXP (X, 1)) <= 3) \
1617 break; \
1618 /* ... fall through ... */ \
1619 case ASHIFTRT: case LSHIFTRT: \
1620 switch (alpha_cpu) \
1621 { \
1622 case PROCESSOR_EV4: \
1623 return COSTS_N_INSNS (2); \
1624 case PROCESSOR_EV5: \
1625 case PROCESSOR_EV6: \
1626 return COSTS_N_INSNS (1); \
1627 default: abort(); \
1628 } \
1629 case IF_THEN_ELSE: \
1630 switch (alpha_cpu) \
1631 { \
1632 case PROCESSOR_EV4: \
1633 case PROCESSOR_EV6: \
1634 return COSTS_N_INSNS (2); \
1635 case PROCESSOR_EV5: \
1636 return COSTS_N_INSNS (1); \
1637 default: abort(); \
1638 } \
1639 case DIV: case UDIV: case MOD: case UMOD: \
1640 switch (alpha_cpu) \
1641 { \
1642 case PROCESSOR_EV4: \
1643 if (GET_MODE (X) == SFmode) \
1644 return COSTS_N_INSNS (34); \
1645 else if (GET_MODE (X) == DFmode) \
1646 return COSTS_N_INSNS (63); \
1647 else \
1648 return COSTS_N_INSNS (70); \
1649 case PROCESSOR_EV5: \
1650 if (GET_MODE (X) == SFmode) \
1651 return COSTS_N_INSNS (15); \
1652 else if (GET_MODE (X) == DFmode) \
1653 return COSTS_N_INSNS (22); \
1654 else \
1655 return COSTS_N_INSNS (70); /* ??? */ \
1656 case PROCESSOR_EV6: \
1657 if (GET_MODE (X) == SFmode) \
1658 return COSTS_N_INSNS (12); \
1659 else if (GET_MODE (X) == DFmode) \
1660 return COSTS_N_INSNS (15); \
1661 else \
1662 return COSTS_N_INSNS (70); /* ??? */ \
1663 default: abort(); \
1664 } \
1665 case MEM: \
1666 switch (alpha_cpu) \
1667 { \
1668 case PROCESSOR_EV4: \
1669 case PROCESSOR_EV6: \
1670 return COSTS_N_INSNS (3); \
1671 case PROCESSOR_EV5: \
1672 return COSTS_N_INSNS (2); \
1673 default: abort(); \
1674 } \
1675 case NEG: case ABS: \
1676 if (! FLOAT_MODE_P (GET_MODE (X))) \
1677 break; \
1678 /* ... fall through ... */ \
1679 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1680 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1681 switch (alpha_cpu) \
1682 { \
1683 case PROCESSOR_EV4: \
1684 return COSTS_N_INSNS (6); \
1685 case PROCESSOR_EV5: \
1686 case PROCESSOR_EV6: \
1687 return COSTS_N_INSNS (4); \
1688 default: abort(); \
1689 }
1690 \f
1691 /* Control the assembler format that we output. */
1692
1693 /* Output to assembler file text saying following lines
1694 may contain character constants, extra white space, comments, etc. */
1695 #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "")
1696
1697 /* Output to assembler file text saying following lines
1698 no longer contain unusual constructs. */
1699 #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "")
1700
1701 #define TEXT_SECTION_ASM_OP "\t.text"
1702
1703 /* Output before read-only data. */
1704
1705 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
1706
1707 /* Output before writable data. */
1708
1709 #define DATA_SECTION_ASM_OP "\t.data"
1710
1711 /* How to refer to registers in assembler output.
1712 This sequence is indexed by compiler's hard-register-number (see above). */
1713
1714 #define REGISTER_NAMES \
1715 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1716 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1717 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1718 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1719 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1720 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1721 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1722 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1723
1724 /* Strip name encoding when emitting labels. */
1725
1726 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1727 do { \
1728 const char *name_ = NAME; \
1729 if (*name_ == '@' || *name == '%') \
1730 name_ += 2; \
1731 if (*name_ == '*') \
1732 name_++; \
1733 else \
1734 fputs (user_label_prefix, STREAM); \
1735 fputs (name_, STREAM); \
1736 } while (0)
1737
1738 /* This is how to output the definition of a user-level label named NAME,
1739 such as the label on a static function or variable NAME. */
1740
1741 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1742 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1743
1744 /* This is how to output a command to make the user-level label named NAME
1745 defined for reference from other files. */
1746
1747 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1748 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1749
1750 /* The prefix to add to user-visible assembler symbols. */
1751
1752 #define USER_LABEL_PREFIX ""
1753
1754 /* This is how to output an internal numbered label where
1755 PREFIX is the class of label and NUM is the number within the class. */
1756
1757 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1758 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1759
1760 /* This is how to output a label for a jump table. Arguments are the same as
1761 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1762 passed. */
1763
1764 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1765 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1766
1767 /* This is how to store into the string LABEL
1768 the symbol_ref name of an internal numbered label where
1769 PREFIX is the class of label and NUM is the number within the class.
1770 This is suitable for output with `assemble_name'. */
1771
1772 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1773 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
1774
1775 /* Check a floating-point value for validity for a particular machine mode. */
1776
1777 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1778 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
1779
1780 /* We use the default ASCII-output routine, except that we don't write more
1781 than 50 characters since the assembler doesn't support very long lines. */
1782
1783 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
1784 do { \
1785 FILE *_hide_asm_out_file = (MYFILE); \
1786 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
1787 int _hide_thissize = (MYLENGTH); \
1788 int _size_so_far = 0; \
1789 { \
1790 FILE *asm_out_file = _hide_asm_out_file; \
1791 const unsigned char *p = _hide_p; \
1792 int thissize = _hide_thissize; \
1793 int i; \
1794 fprintf (asm_out_file, "\t.ascii \""); \
1795 \
1796 for (i = 0; i < thissize; i++) \
1797 { \
1798 register int c = p[i]; \
1799 \
1800 if (_size_so_far ++ > 50 && i < thissize - 4) \
1801 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
1802 \
1803 if (c == '\"' || c == '\\') \
1804 putc ('\\', asm_out_file); \
1805 if (c >= ' ' && c < 0177) \
1806 putc (c, asm_out_file); \
1807 else \
1808 { \
1809 fprintf (asm_out_file, "\\%o", c); \
1810 /* After an octal-escape, if a digit follows, \
1811 terminate one string constant and start another. \
1812 The VAX assembler fails to stop reading the escape \
1813 after three digits, so this is the only way we \
1814 can get it to parse the data properly. */ \
1815 if (i < thissize - 1 && ISDIGIT (p[i + 1])) \
1816 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
1817 } \
1818 } \
1819 fprintf (asm_out_file, "\"\n"); \
1820 } \
1821 } \
1822 while (0)
1823
1824 /* This is how to output an insn to push a register on the stack.
1825 It need not be very fast code. */
1826
1827 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1828 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
1829 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1830 (REGNO) & 31);
1831
1832 /* This is how to output an insn to pop a register from the stack.
1833 It need not be very fast code. */
1834
1835 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1836 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
1837 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1838 (REGNO) & 31);
1839
1840 /* This is how to output an element of a case-vector that is absolute.
1841 (Alpha does not use such vectors, but we must define this macro anyway.) */
1842
1843 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
1844
1845 /* This is how to output an element of a case-vector that is relative. */
1846
1847 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1848 fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \
1849 (VALUE))
1850
1851 /* This is how to output an assembler line
1852 that says to advance the location counter
1853 to a multiple of 2**LOG bytes. */
1854
1855 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1856 if ((LOG) != 0) \
1857 fprintf (FILE, "\t.align %d\n", LOG);
1858
1859 /* This is how to advance the location counter by SIZE bytes. */
1860
1861 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1862 fprintf (FILE, "\t.space %d\n", (SIZE))
1863
1864 /* This says how to output an assembler line
1865 to define a global common symbol. */
1866
1867 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1868 ( fputs ("\t.comm ", (FILE)), \
1869 assemble_name ((FILE), (NAME)), \
1870 fprintf ((FILE), ",%d\n", (SIZE)))
1871
1872 /* This says how to output an assembler line
1873 to define a local common symbol. */
1874
1875 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1876 ( fputs ("\t.lcomm ", (FILE)), \
1877 assemble_name ((FILE), (NAME)), \
1878 fprintf ((FILE), ",%d\n", (SIZE)))
1879
1880 /* Store in OUTPUT a string (made with alloca) containing
1881 an assembler-name for a local static variable named NAME.
1882 LABELNO is an integer which is different for each call. */
1883
1884 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1885 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1886 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1887 \f
1888
1889 /* Print operand X (an rtx) in assembler syntax to file FILE.
1890 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1891 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1892
1893 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1894
1895 /* Determine which codes are valid without a following integer. These must
1896 not be alphabetic.
1897
1898 ~ Generates the name of the current function.
1899
1900 / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX
1901 attributes are examined to determine what is appropriate.
1902
1903 , Generates single precision suffix for floating point
1904 instructions (s for IEEE, f for VAX)
1905
1906 - Generates double precision suffix for floating point
1907 instructions (t for IEEE, g for VAX)
1908 */
1909
1910 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1911 ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \
1912 || (CODE) == '#' || (CODE) == '*' || (CODE) == '&')
1913 \f
1914 /* Print a memory address as an operand to reference that memory location. */
1915
1916 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1917 print_operand_address((FILE), (ADDR))
1918
1919 /* Define the codes that are matched by predicates in alpha.c. */
1920
1921 #define PREDICATE_CODES \
1922 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1923 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
1924 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
1925 {"cint8_operand", {CONST_INT}}, \
1926 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
1927 {"add_operand", {SUBREG, REG, CONST_INT}}, \
1928 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
1929 {"const48_operand", {CONST_INT}}, \
1930 {"and_operand", {SUBREG, REG, CONST_INT}}, \
1931 {"or_operand", {SUBREG, REG, CONST_INT}}, \
1932 {"mode_mask_operand", {CONST_INT}}, \
1933 {"mul8_operand", {CONST_INT}}, \
1934 {"mode_width_operand", {CONST_INT}}, \
1935 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1936 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
1937 {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \
1938 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
1939 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
1940 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
1941 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
1942 {"fp0_operand", {CONST_DOUBLE}}, \
1943 {"current_file_function_operand", {SYMBOL_REF}}, \
1944 {"direct_call_operand", {SYMBOL_REF}}, \
1945 {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
1946 {"small_symbolic_operand", {SYMBOL_REF, CONST}}, \
1947 {"global_symbolic_operand", {SYMBOL_REF, CONST}}, \
1948 {"dtp16_symbolic_operand", {CONST}}, \
1949 {"dtp32_symbolic_operand", {CONST}}, \
1950 {"gotdtp_symbolic_operand", {CONST}}, \
1951 {"tp16_symbolic_operand", {CONST}}, \
1952 {"tp32_symbolic_operand", {CONST}}, \
1953 {"gottp_symbolic_operand", {CONST}}, \
1954 {"call_operand", {REG, SYMBOL_REF}}, \
1955 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
1956 SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \
1957 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
1958 SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \
1959 {"some_ni_operand", {SUBREG, REG, MEM}}, \
1960 {"aligned_memory_operand", {MEM}}, \
1961 {"unaligned_memory_operand", {MEM}}, \
1962 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
1963 {"any_memory_operand", {MEM}}, \
1964 {"hard_fp_register_operand", {SUBREG, REG}}, \
1965 {"hard_int_register_operand", {SUBREG, REG}}, \
1966 {"reg_not_elim_operand", {SUBREG, REG}}, \
1967 {"reg_no_subreg_operand", {REG}}, \
1968 {"addition_operation", {PLUS}}, \
1969 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
1970 {"some_small_symbolic_operand", {SET, PARALLEL, PREFETCH, UNSPEC, \
1971 UNSPEC_VOLATILE}},
1972 \f
1973 /* Define the `__builtin_va_list' type for the ABI. */
1974 #define BUILD_VA_LIST_TYPE(VALIST) \
1975 (VALIST) = alpha_build_va_list ()
1976
1977 /* Implement `va_start' for varargs and stdarg. */
1978 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1979 alpha_va_start (stdarg, valist, nextarg)
1980
1981 /* Implement `va_arg'. */
1982 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1983 alpha_va_arg (valist, type)
1984 \f
1985 /* Tell collect that the object format is ECOFF. */
1986 #define OBJECT_FORMAT_COFF
1987 #define EXTENDED_COFF
1988
1989 /* If we use NM, pass -g to it so it only lists globals. */
1990 #define NM_FLAGS "-pg"
1991
1992 /* Definitions for debugging. */
1993
1994 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1995 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
1996 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1997
1998 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1999 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2000 #endif
2001
2002
2003 /* Correct the offset of automatic variables and arguments. Note that
2004 the Alpha debug format wants all automatic variables and arguments
2005 to be in terms of two different offsets from the virtual frame pointer,
2006 which is the stack pointer before any adjustment in the function.
2007 The offset for the argument pointer is fixed for the native compiler,
2008 it is either zero (for the no arguments case) or large enough to hold
2009 all argument registers.
2010 The offset for the auto pointer is the fourth argument to the .frame
2011 directive (local_offset).
2012 To stay compatible with the native tools we use the same offsets
2013 from the virtual frame pointer and adjust the debugger arg/auto offsets
2014 accordingly. These debugger offsets are set up in output_prolog. */
2015
2016 extern long alpha_arg_offset;
2017 extern long alpha_auto_offset;
2018 #define DEBUGGER_AUTO_OFFSET(X) \
2019 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2020 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2021
2022
2023 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2024 alpha_output_lineno (STREAM, LINE)
2025
2026 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2027 alpha_output_filename (STREAM, NAME)
2028
2029 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2030 number, because the real length runs past this up to the next
2031 continuation point. This is really a dbxout.c bug. */
2032 #define DBX_CONTIN_LENGTH 3000
2033
2034 /* By default, turn on GDB extensions. */
2035 #define DEFAULT_GDB_EXTENSIONS 1
2036
2037 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2038 #define NO_DBX_FUNCTION_END 1
2039
2040 /* If we are smuggling stabs through the ALPHA ECOFF object
2041 format, put a comment in front of the .stab<x> operation so
2042 that the ALPHA assembler does not choke. The mips-tfile program
2043 will correctly put the stab into the object file. */
2044
2045 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
2046 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
2047 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
2048
2049 /* Forward references to tags are allowed. */
2050 #define SDB_ALLOW_FORWARD_REFERENCES
2051
2052 /* Unknown tags are also allowed. */
2053 #define SDB_ALLOW_UNKNOWN_REFERENCES
2054
2055 #define PUT_SDB_DEF(a) \
2056 do { \
2057 fprintf (asm_out_file, "\t%s.def\t", \
2058 (TARGET_GAS) ? "" : "#"); \
2059 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2060 fputc (';', asm_out_file); \
2061 } while (0)
2062
2063 #define PUT_SDB_PLAIN_DEF(a) \
2064 do { \
2065 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2066 (TARGET_GAS) ? "" : "#", (a)); \
2067 } while (0)
2068
2069 #define PUT_SDB_TYPE(a) \
2070 do { \
2071 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2072 } while (0)
2073
2074 /* For block start and end, we create labels, so that
2075 later we can figure out where the correct offset is.
2076 The normal .ent/.end serve well enough for functions,
2077 so those are just commented out. */
2078
2079 extern int sdb_label_count; /* block start/end next label # */
2080
2081 #define PUT_SDB_BLOCK_START(LINE) \
2082 do { \
2083 fprintf (asm_out_file, \
2084 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2085 sdb_label_count, \
2086 (TARGET_GAS) ? "" : "#", \
2087 sdb_label_count, \
2088 (LINE)); \
2089 sdb_label_count++; \
2090 } while (0)
2091
2092 #define PUT_SDB_BLOCK_END(LINE) \
2093 do { \
2094 fprintf (asm_out_file, \
2095 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2096 sdb_label_count, \
2097 (TARGET_GAS) ? "" : "#", \
2098 sdb_label_count, \
2099 (LINE)); \
2100 sdb_label_count++; \
2101 } while (0)
2102
2103 #define PUT_SDB_FUNCTION_START(LINE)
2104
2105 #define PUT_SDB_FUNCTION_END(LINE)
2106
2107 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2108
2109 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2110 mips-tdump.c to print them out.
2111
2112 These must match the corresponding definitions in gdb/mipsread.c.
2113 Unfortunately, gcc and gdb do not currently share any directories. */
2114
2115 #define CODE_MASK 0x8F300
2116 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2117 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2118 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2119
2120 /* Override some mips-tfile definitions. */
2121
2122 #define SHASH_SIZE 511
2123 #define THASH_SIZE 55
2124
2125 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2126
2127 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2128
2129 /* The system headers under Alpha systems are generally C++-aware. */
2130 #define NO_IMPLICIT_EXTERN_C
2131
2132 /* Generate calls to memcpy, etc., not bcopy, etc. */
2133 #define TARGET_MEM_FUNCTIONS 1
2134
2135 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2136 Used for C++ multiple inheritance. */
2137 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2138 alpha_output_mi_thunk_osf (FILE, THUNK_FNDECL, DELTA, FUNCTION)