1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
48 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
49 (UNSPECV_LONGJMP 3) ; builtin_longjmp
51 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
53 (UNSPECV_EHR 7) ; exception_receiver
57 (UNSPECV_PLDGP2 11) ; prologue ldgp
60 ;; Where necessary, the suffixes _le and _be are used to distinguish between
61 ;; little-endian and big-endian patterns.
63 ;; Note that the Unicos/Mk assembler does not support the following
64 ;; opcodes: mov, fmov, nop, fnop, unop.
66 ;; Processor type -- this attribute must exactly match the processor_type
67 ;; enumeration in alpha.h.
69 (define_attr "cpu" "ev4,ev5,ev6"
70 (const (symbol_ref "alpha_cpu")))
72 ;; Define an insn type attribute. This is used in function unit delay
73 ;; computations, among other purposes. For the most part, we use the names
74 ;; defined in the EV4 documentation, but add a few that we have to know about
78 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
79 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
80 (const_string "iadd"))
82 ;; Describe a user's asm statement.
83 (define_asm_attributes
84 [(set_attr "type" "multi")])
86 ;; Define the operand size an insn operates on. Used primarily by mul
87 ;; and div operations that have size dependent timings.
89 (define_attr "opsize" "si,di,udi"
92 ;; The TRAP attribute marks instructions that may generate traps
93 ;; (which are imprecise and may need a trapb if software completion
96 (define_attr "trap" "no,yes"
99 ;; The ROUND_SUFFIX attribute marks which instructions require a
100 ;; rounding-mode suffix. The value NONE indicates no suffix,
101 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
103 (define_attr "round_suffix" "none,normal,c"
104 (const_string "none"))
106 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
108 ;; SU accepts only /su (cmpt et al)
109 ;; SUI accepts only /sui (cvtqt and cvtqs)
110 ;; V_SV accepts /v and /sv (cvtql only)
111 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
112 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
114 ;; The actual suffix emitted is controled by alpha_fptm.
116 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
117 (const_string "none"))
119 ;; The length of an instruction sequence in bytes.
121 (define_attr "length" ""
124 ;; On EV4 there are two classes of resources to consider: resources needed
125 ;; to issue, and resources needed to execute. IBUS[01] are in the first
126 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
127 ;; (There are a few other register-like resources, but ...)
129 ; First, describe all of the issue constraints with single cycle delays.
130 ; All insns need a bus, but all except loads require one or the other.
131 (define_function_unit "ev4_ibus0" 1 0
132 (and (eq_attr "cpu" "ev4")
133 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
136 (define_function_unit "ev4_ibus1" 1 0
137 (and (eq_attr "cpu" "ev4")
138 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
141 ; Memory delivers its result in three cycles. Actually return one and
142 ; take care of this in adjust_cost, since we want to handle user-defined
144 (define_function_unit "ev4_abox" 1 0
145 (and (eq_attr "cpu" "ev4")
146 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
149 ; Branches have no delay cost, but do tie up the unit for two cycles.
150 (define_function_unit "ev4_bbox" 1 1
151 (and (eq_attr "cpu" "ev4")
152 (eq_attr "type" "ibr,fbr,jsr"))
155 ; Arithmetic insns are normally have their results available after
156 ; two cycles. There are a number of exceptions. They are encoded in
157 ; ADJUST_COST. Some of the other insns have similar exceptions.
158 (define_function_unit "ev4_ebox" 1 0
159 (and (eq_attr "cpu" "ev4")
160 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
163 (define_function_unit "imul" 1 0
164 (and (eq_attr "cpu" "ev4")
165 (and (eq_attr "type" "imul")
166 (eq_attr "opsize" "si")))
169 (define_function_unit "imul" 1 0
170 (and (eq_attr "cpu" "ev4")
171 (and (eq_attr "type" "imul")
172 (eq_attr "opsize" "!si")))
175 (define_function_unit "ev4_fbox" 1 0
176 (and (eq_attr "cpu" "ev4")
177 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
180 (define_function_unit "fdiv" 1 0
181 (and (eq_attr "cpu" "ev4")
182 (and (eq_attr "type" "fdiv")
183 (eq_attr "opsize" "si")))
186 (define_function_unit "fdiv" 1 0
187 (and (eq_attr "cpu" "ev4")
188 (and (eq_attr "type" "fdiv")
189 (eq_attr "opsize" "di")))
192 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
194 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
195 ;; with the combined resource EBOX.
197 (define_function_unit "ev5_ebox" 2 0
198 (and (eq_attr "cpu" "ev5")
199 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
202 ; Memory takes at least 2 clocks. Return one from here and fix up with
203 ; user-defined latencies in adjust_cost.
204 (define_function_unit "ev5_ebox" 2 0
205 (and (eq_attr "cpu" "ev5")
206 (eq_attr "type" "ild,fld,ldsym"))
209 ; Loads can dual issue with one another, but loads and stores do not mix.
210 (define_function_unit "ev5_e0" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (eq_attr "type" "ild,fld,ldsym"))
214 [(eq_attr "type" "ist,fst")])
216 ; Stores, shifts, multiplies can only issue to E0
217 (define_function_unit "ev5_e0" 1 0
218 (and (eq_attr "cpu" "ev5")
219 (eq_attr "type" "ist,fst,shift,imul"))
222 ; Motion video insns also issue only to E0, and take two ticks.
223 (define_function_unit "ev5_e0" 1 0
224 (and (eq_attr "cpu" "ev5")
225 (eq_attr "type" "mvi"))
228 ; Conditional moves always take 2 ticks.
229 (define_function_unit "ev5_ebox" 2 0
230 (and (eq_attr "cpu" "ev5")
231 (eq_attr "type" "icmov"))
234 ; Branches can only issue to E1
235 (define_function_unit "ev5_e1" 1 0
236 (and (eq_attr "cpu" "ev5")
237 (eq_attr "type" "ibr,jsr"))
240 ; Multiplies also use the integer multiplier.
241 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
242 ; cycles before an integer multiplication completes."
243 (define_function_unit "imul" 1 0
244 (and (eq_attr "cpu" "ev5")
245 (and (eq_attr "type" "imul")
246 (eq_attr "opsize" "si")))
249 (define_function_unit "imul" 1 0
250 (and (eq_attr "cpu" "ev5")
251 (and (eq_attr "type" "imul")
252 (eq_attr "opsize" "di")))
255 (define_function_unit "imul" 1 0
256 (and (eq_attr "cpu" "ev5")
257 (and (eq_attr "type" "imul")
258 (eq_attr "opsize" "udi")))
261 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
262 ;; on either so we have to play the game again.
264 (define_function_unit "ev5_fbox" 2 0
265 (and (eq_attr "cpu" "ev5")
266 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
269 (define_function_unit "ev5_fm" 1 0
270 (and (eq_attr "cpu" "ev5")
271 (eq_attr "type" "fmul"))
274 ; Add and cmov as you would expect; fbr never produces a result;
275 ; fdiv issues through fa to the divider,
276 (define_function_unit "ev5_fa" 1 0
277 (and (eq_attr "cpu" "ev5")
278 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
281 ; ??? How to: "No instruction can be issued to pipe FA exactly five
282 ; cycles before a floating point divide completes."
283 (define_function_unit "fdiv" 1 0
284 (and (eq_attr "cpu" "ev5")
285 (and (eq_attr "type" "fdiv")
286 (eq_attr "opsize" "si")))
287 15 15) ; 15 to 31 data dependent
289 (define_function_unit "fdiv" 1 0
290 (and (eq_attr "cpu" "ev5")
291 (and (eq_attr "type" "fdiv")
292 (eq_attr "opsize" "di")))
293 22 22) ; 22 to 60 data dependent
295 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
297 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
298 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
300 ;; Conditional moves decompose into two independent primitives, each
301 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
303 (define_function_unit "ev6_ebox" 4 0
304 (and (eq_attr "cpu" "ev6")
305 (eq_attr "type" "icmov"))
308 (define_function_unit "ev6_ebox" 4 0
309 (and (eq_attr "cpu" "ev6")
310 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
313 ;; Integer loads take at least 3 clocks, and only issue to lower units.
314 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
315 (define_function_unit "ev6_l" 2 0
316 (and (eq_attr "cpu" "ev6")
317 (eq_attr "type" "ild,ldsym,ist,fst"))
320 ;; FP loads take at least 4 clocks. Return two from here...
321 (define_function_unit "ev6_l" 2 0
322 (and (eq_attr "cpu" "ev6")
323 (eq_attr "type" "fld"))
326 ;; Motion video insns also issue only to U0, and take three ticks.
327 (define_function_unit "ev6_u0" 1 0
328 (and (eq_attr "cpu" "ev6")
329 (eq_attr "type" "mvi"))
332 (define_function_unit "ev6_u" 2 0
333 (and (eq_attr "cpu" "ev6")
334 (eq_attr "type" "mvi"))
337 ;; Shifts issue to either upper pipe.
338 (define_function_unit "ev6_u" 2 0
339 (and (eq_attr "cpu" "ev6")
340 (eq_attr "type" "shift"))
343 ;; Multiplies issue only to U1, and all take 7 ticks.
344 ;; Rather than create a new function unit just for U1, reuse IMUL
345 (define_function_unit "imul" 1 0
346 (and (eq_attr "cpu" "ev6")
347 (eq_attr "type" "imul"))
350 (define_function_unit "ev6_u" 2 0
351 (and (eq_attr "cpu" "ev6")
352 (eq_attr "type" "imul"))
355 ;; Branches issue to either upper pipe
356 (define_function_unit "ev6_u" 2 0
357 (and (eq_attr "cpu" "ev6")
358 (eq_attr "type" "ibr"))
361 ;; Calls only issue to L0.
362 (define_function_unit "ev6_l0" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (eq_attr "type" "jsr"))
367 (define_function_unit "ev6_l" 2 0
368 (and (eq_attr "cpu" "ev6")
369 (eq_attr "type" "jsr"))
372 ;; Ftoi/itof only issue to lower pipes
373 (define_function_unit "ev6_l" 2 0
374 (and (eq_attr "cpu" "ev6")
375 (eq_attr "type" "ftoi"))
378 (define_function_unit "ev6_l" 2 0
379 (and (eq_attr "cpu" "ev6")
380 (eq_attr "type" "itof"))
383 ;; For the FPU we are very similar to EV5, except there's no insn that
384 ;; can issue to fm & fa, so we get to leave that out.
386 (define_function_unit "ev6_fm" 1 0
387 (and (eq_attr "cpu" "ev6")
388 (eq_attr "type" "fmul"))
391 (define_function_unit "ev6_fa" 1 0
392 (and (eq_attr "cpu" "ev6")
393 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
396 (define_function_unit "ev6_fa" 1 0
397 (and (eq_attr "cpu" "ev6")
398 (eq_attr "type" "fcmov"))
401 (define_function_unit "fdiv" 1 0
402 (and (eq_attr "cpu" "ev6")
403 (and (eq_attr "type" "fdiv")
404 (eq_attr "opsize" "si")))
407 (define_function_unit "fdiv" 1 0
408 (and (eq_attr "cpu" "ev6")
409 (and (eq_attr "type" "fdiv")
410 (eq_attr "opsize" "di")))
413 (define_function_unit "fsqrt" 1 0
414 (and (eq_attr "cpu" "ev6")
415 (and (eq_attr "type" "fsqrt")
416 (eq_attr "opsize" "si")))
419 (define_function_unit "fsqrt" 1 0
420 (and (eq_attr "cpu" "ev6")
421 (and (eq_attr "type" "fsqrt")
422 (eq_attr "opsize" "di")))
425 ; ??? The FPU communicates with memory and the integer register file
426 ; via two fp store units. We need a slot in the fst immediately, and
427 ; a slot in LOW after the operand data is ready. At which point the
428 ; data may be moved either to the store queue or the integer register
429 ; file and the insn retired.
432 ;; First define the arithmetic insns. Note that the 32-bit forms also
435 ;; Handle 32-64 bit extension from memory to a floating point register
436 ;; specially, since this occurs frequently in int->double conversions.
438 ;; Note that while we must retain the =f case in the insn for reload's
439 ;; benefit, it should be eliminated after reload, so we should never emit
440 ;; code for that case. But we don't reject the possibility.
442 (define_expand "extendsidi2"
443 [(set (match_operand:DI 0 "register_operand" "")
444 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
448 (define_insn "*extendsidi2_nofix"
449 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
451 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
457 lds %0,%1\;cvtlq %0,%0"
458 [(set_attr "type" "iadd,ild,fadd,fld")
459 (set_attr "length" "*,*,*,8")])
461 (define_insn "*extendsidi2_fix"
462 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
464 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
471 lds %0,%1\;cvtlq %0,%0"
472 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
473 (set_attr "length" "*,*,*,*,8")])
475 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
477 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
478 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
480 [(set (match_dup 2) (match_dup 1))
481 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
482 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
484 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
485 ;; reload when converting fp->int.
488 [(set (match_operand:SI 0 "hard_int_register_operand" "")
489 (match_operand:SI 1 "memory_operand" ""))
490 (set (match_operand:DI 2 "hard_int_register_operand" "")
491 (sign_extend:DI (match_dup 0)))]
492 "true_regnum (operands[0]) == true_regnum (operands[2])
493 || peep2_reg_dead_p (2, operands[0])"
495 (sign_extend:DI (match_dup 1)))]
499 [(set (match_operand:SI 0 "hard_int_register_operand" "")
500 (match_operand:SI 1 "hard_fp_register_operand" ""))
501 (set (match_operand:DI 2 "hard_int_register_operand" "")
502 (sign_extend:DI (match_dup 0)))]
504 && (true_regnum (operands[0]) == true_regnum (operands[2])
505 || peep2_reg_dead_p (2, operands[0]))"
507 (sign_extend:DI (match_dup 1)))]
511 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
512 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
513 (set (match_operand:DI 2 "hard_int_register_operand" "")
515 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
517 (sign_extend:DI (match_dup 1)))]
520 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
521 ;; generates better code. We have the anonymous addsi3 pattern below in
522 ;; case combine wants to make it.
523 (define_expand "addsi3"
524 [(set (match_operand:SI 0 "register_operand" "")
525 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
526 (match_operand:SI 2 "add_operand" "")))]
531 rtx op1 = gen_lowpart (DImode, operands[1]);
532 rtx op2 = gen_lowpart (DImode, operands[2]);
534 if (! cse_not_expected)
536 rtx tmp = gen_reg_rtx (DImode);
537 emit_insn (gen_adddi3 (tmp, op1, op2));
538 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
541 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
546 (define_insn "*addsi_internal"
547 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
548 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
549 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
558 [(set (match_operand:SI 0 "register_operand" "")
559 (plus:SI (match_operand:SI 1 "register_operand" "")
560 (match_operand:SI 2 "const_int_operand" "")))]
561 "! add_operand (operands[2], SImode)"
562 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
563 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
565 HOST_WIDE_INT val = INTVAL (operands[2]);
566 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
567 HOST_WIDE_INT rest = val - low;
569 operands[3] = GEN_INT (rest);
570 operands[4] = GEN_INT (low);
573 (define_insn "*addsi_se"
574 [(set (match_operand:DI 0 "register_operand" "=r,r")
576 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
577 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
584 [(set (match_operand:DI 0 "register_operand" "")
586 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
587 (match_operand:SI 2 "const_int_operand" ""))))
588 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
589 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
590 && INTVAL (operands[2]) % 4 == 0"
591 [(set (match_dup 3) (match_dup 4))
592 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
596 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
602 operands[4] = GEN_INT (val);
603 operands[5] = GEN_INT (mult);
607 [(set (match_operand:DI 0 "register_operand" "")
609 (plus:SI (match_operator:SI 1 "comparison_operator"
610 [(match_operand 2 "" "")
611 (match_operand 3 "" "")])
612 (match_operand:SI 4 "add_operand" ""))))
613 (clobber (match_operand:DI 5 "register_operand" ""))]
615 [(set (match_dup 5) (match_dup 6))
616 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
618 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
619 operands[2], operands[3]);
620 operands[7] = gen_lowpart (SImode, operands[5]);
623 (define_insn "addvsi3"
624 [(set (match_operand:SI 0 "register_operand" "=r,r")
625 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
626 (match_operand:SI 2 "sext_add_operand" "rI,O")))
627 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
628 (sign_extend:DI (match_dup 2)))
629 (sign_extend:DI (plus:SI (match_dup 1)
637 (define_expand "adddi3"
638 [(set (match_operand:DI 0 "register_operand" "")
639 (plus:DI (match_operand:DI 1 "register_operand" "")
640 (match_operand:DI 2 "add_operand" "")))]
644 (define_insn "*adddi_er_high_l"
645 [(set (match_operand:DI 0 "register_operand" "=r")
646 (plus:DI (match_operand:DI 1 "register_operand" "r")
647 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
648 "TARGET_EXPLICIT_RELOCS"
649 "ldah %0,%2(%1)\t\t!gprelhigh")
651 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
652 ;; With complications like
654 ;; The NT stack unwind code can't handle a subq to adjust the stack
655 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
656 ;; the exception handling code will loop if a subq is used and an
659 ;; The 19980616 change to emit prologues as RTL also confused some
660 ;; versions of GDB, which also interprets prologues. This has been
661 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
664 ;; and the fact that the three insns schedule exactly the same, it's
665 ;; just not worth the effort.
667 (define_insn "*adddi_internal"
668 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
669 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
670 (match_operand:DI 2 "add_operand" "r,K,L")))]
677 ;; ??? Allow large constants when basing off the frame pointer or some
678 ;; virtual register that may eliminate to the frame pointer. This is
679 ;; done because register elimination offsets will change the hi/lo split,
680 ;; and if we split before reload, we will require additional instructions.
682 (define_insn "*adddi_fp_hack"
683 [(set (match_operand:DI 0 "register_operand" "=r")
684 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
685 (match_operand:DI 2 "const_int_operand" "n")))]
686 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
687 && INTVAL (operands[2]) >= 0
688 /* This is the largest constant an lda+ldah pair can add, minus
689 an upper bound on the displacement between SP and AP during
690 register elimination. See INITIAL_ELIMINATION_OFFSET. */
691 && INTVAL (operands[2])
693 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
694 - ALPHA_ROUND(current_function_outgoing_args_size)
695 - (ALPHA_ROUND (get_frame_size ()
696 + max_reg_num () * UNITS_PER_WORD
697 + current_function_pretend_args_size)
698 - current_function_pretend_args_size))"
701 ;; Don't do this if we are adjusting SP since we don't want to do it
702 ;; in two steps. Don't split FP sources for the reason listed above.
704 [(set (match_operand:DI 0 "register_operand" "")
705 (plus:DI (match_operand:DI 1 "register_operand" "")
706 (match_operand:DI 2 "const_int_operand" "")))]
707 "! add_operand (operands[2], DImode)
708 && operands[0] != stack_pointer_rtx
709 && operands[1] != frame_pointer_rtx
710 && operands[1] != arg_pointer_rtx"
711 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
712 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
714 HOST_WIDE_INT val = INTVAL (operands[2]);
715 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
716 HOST_WIDE_INT rest = val - low;
718 operands[4] = GEN_INT (low);
719 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
720 operands[3] = GEN_INT (rest);
721 else if (! no_new_pseudos)
723 operands[3] = gen_reg_rtx (DImode);
724 emit_move_insn (operands[3], operands[2]);
725 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
732 (define_insn "*saddl"
733 [(set (match_operand:SI 0 "register_operand" "=r,r")
734 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
735 (match_operand:SI 2 "const48_operand" "I,I"))
736 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
742 (define_insn "*saddl_se"
743 [(set (match_operand:DI 0 "register_operand" "=r,r")
745 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
746 (match_operand:SI 2 "const48_operand" "I,I"))
747 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
754 [(set (match_operand:DI 0 "register_operand" "")
756 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
757 [(match_operand 2 "" "")
758 (match_operand 3 "" "")])
759 (match_operand:SI 4 "const48_operand" ""))
760 (match_operand:SI 5 "sext_add_operand" ""))))
761 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
763 [(set (match_dup 6) (match_dup 7))
765 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
768 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
769 operands[2], operands[3]);
770 operands[8] = gen_lowpart (SImode, operands[6]);
773 (define_insn "*saddq"
774 [(set (match_operand:DI 0 "register_operand" "=r,r")
775 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
776 (match_operand:DI 2 "const48_operand" "I,I"))
777 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
783 (define_insn "addvdi3"
784 [(set (match_operand:DI 0 "register_operand" "=r,r")
785 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
786 (match_operand:DI 2 "sext_add_operand" "rI,O")))
787 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
788 (sign_extend:TI (match_dup 2)))
789 (sign_extend:TI (plus:DI (match_dup 1)
797 (define_insn "negsi2"
798 [(set (match_operand:SI 0 "register_operand" "=r")
799 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
803 (define_insn "*negsi_se"
804 [(set (match_operand:DI 0 "register_operand" "=r")
805 (sign_extend:DI (neg:SI
806 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
810 (define_insn "negvsi2"
811 [(set (match_operand:SI 0 "register_operand" "=r")
812 (neg:SI (match_operand:SI 1 "register_operand" "r")))
813 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
814 (sign_extend:DI (neg:SI (match_dup 1))))
819 (define_insn "negdi2"
820 [(set (match_operand:DI 0 "register_operand" "=r")
821 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
825 (define_insn "negvdi2"
826 [(set (match_operand:DI 0 "register_operand" "=r")
827 (neg:DI (match_operand:DI 1 "register_operand" "r")))
828 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
829 (sign_extend:TI (neg:DI (match_dup 1))))
834 (define_expand "subsi3"
835 [(set (match_operand:SI 0 "register_operand" "")
836 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
837 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
842 rtx op1 = gen_lowpart (DImode, operands[1]);
843 rtx op2 = gen_lowpart (DImode, operands[2]);
845 if (! cse_not_expected)
847 rtx tmp = gen_reg_rtx (DImode);
848 emit_insn (gen_subdi3 (tmp, op1, op2));
849 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
852 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
857 (define_insn "*subsi_internal"
858 [(set (match_operand:SI 0 "register_operand" "=r")
859 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
860 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
864 (define_insn "*subsi_se"
865 [(set (match_operand:DI 0 "register_operand" "=r")
866 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
867 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
871 (define_insn "subvsi3"
872 [(set (match_operand:SI 0 "register_operand" "=r")
873 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
874 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
875 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
876 (sign_extend:DI (match_dup 2)))
877 (sign_extend:DI (minus:SI (match_dup 1)
883 (define_insn "subdi3"
884 [(set (match_operand:DI 0 "register_operand" "=r")
885 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
886 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
890 (define_insn "*ssubl"
891 [(set (match_operand:SI 0 "register_operand" "=r")
892 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
893 (match_operand:SI 2 "const48_operand" "I"))
894 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
898 (define_insn "*ssubl_se"
899 [(set (match_operand:DI 0 "register_operand" "=r")
901 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
902 (match_operand:SI 2 "const48_operand" "I"))
903 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
907 (define_insn "*ssubq"
908 [(set (match_operand:DI 0 "register_operand" "=r")
909 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
910 (match_operand:DI 2 "const48_operand" "I"))
911 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
915 (define_insn "subvdi3"
916 [(set (match_operand:DI 0 "register_operand" "=r")
917 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
918 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
919 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
920 (sign_extend:TI (match_dup 2)))
921 (sign_extend:TI (minus:DI (match_dup 1)
927 ;; The Unicos/Mk assembler doesn't support mull.
929 (define_insn "mulsi3"
930 [(set (match_operand:SI 0 "register_operand" "=r")
931 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
932 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
933 "!TARGET_ABI_UNICOSMK"
935 [(set_attr "type" "imul")
936 (set_attr "opsize" "si")])
938 (define_insn "*mulsi_se"
939 [(set (match_operand:DI 0 "register_operand" "=r")
941 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
942 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
943 "!TARGET_ABI_UNICOSMK"
945 [(set_attr "type" "imul")
946 (set_attr "opsize" "si")])
948 (define_insn "mulvsi3"
949 [(set (match_operand:SI 0 "register_operand" "=r")
950 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
951 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
952 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
953 (sign_extend:DI (match_dup 2)))
954 (sign_extend:DI (mult:SI (match_dup 1)
957 "!TARGET_ABI_UNICOSMK"
959 [(set_attr "type" "imul")
960 (set_attr "opsize" "si")])
962 (define_insn "muldi3"
963 [(set (match_operand:DI 0 "register_operand" "=r")
964 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
965 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
968 [(set_attr "type" "imul")])
970 (define_insn "mulvdi3"
971 [(set (match_operand:DI 0 "register_operand" "=r")
972 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
973 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
974 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
975 (sign_extend:TI (match_dup 2)))
976 (sign_extend:TI (mult:DI (match_dup 1)
981 [(set_attr "type" "imul")])
983 (define_insn "umuldi3_highpart"
984 [(set (match_operand:DI 0 "register_operand" "=r")
987 (mult:TI (zero_extend:TI
988 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
990 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
994 [(set_attr "type" "imul")
995 (set_attr "opsize" "udi")])
997 (define_insn "*umuldi3_highpart_const"
998 [(set (match_operand:DI 0 "register_operand" "=r")
1001 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
1002 (match_operand:TI 2 "cint8_operand" "I"))
1006 [(set_attr "type" "imul")
1007 (set_attr "opsize" "udi")])
1009 ;; The divide and remainder operations take their inputs from r24 and
1010 ;; r25, put their output in r27, and clobber r23 and r28 on all
1011 ;; systems except Unicos/Mk. On Unicos, the standard library provides
1012 ;; subroutines which use the standard calling convention and work on
1015 ;; ??? Force sign-extension here because some versions of OSF/1 and
1016 ;; Interix/NT don't do the right thing if the inputs are not properly
1017 ;; sign-extended. But Linux, for instance, does not have this
1018 ;; problem. Is it worth the complication here to eliminate the sign
1021 (define_expand "divsi3"
1023 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1025 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1026 (parallel [(set (match_dup 5)
1027 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
1028 (clobber (reg:DI 23))
1029 (clobber (reg:DI 28))])
1030 (set (match_operand:SI 0 "nonimmediate_operand" "")
1031 (subreg:SI (match_dup 5) 0))]
1032 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1034 operands[3] = gen_reg_rtx (DImode);
1035 operands[4] = gen_reg_rtx (DImode);
1036 operands[5] = gen_reg_rtx (DImode);
1039 (define_expand "udivsi3"
1041 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1043 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1044 (parallel [(set (match_dup 5)
1045 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
1046 (clobber (reg:DI 23))
1047 (clobber (reg:DI 28))])
1048 (set (match_operand:SI 0 "nonimmediate_operand" "")
1049 (subreg:SI (match_dup 5) 0))]
1050 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1052 operands[3] = gen_reg_rtx (DImode);
1053 operands[4] = gen_reg_rtx (DImode);
1054 operands[5] = gen_reg_rtx (DImode);
1057 (define_expand "modsi3"
1059 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1061 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1062 (parallel [(set (match_dup 5)
1063 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
1064 (clobber (reg:DI 23))
1065 (clobber (reg:DI 28))])
1066 (set (match_operand:SI 0 "nonimmediate_operand" "")
1067 (subreg:SI (match_dup 5) 0))]
1068 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1070 operands[3] = gen_reg_rtx (DImode);
1071 operands[4] = gen_reg_rtx (DImode);
1072 operands[5] = gen_reg_rtx (DImode);
1075 (define_expand "umodsi3"
1077 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1079 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1080 (parallel [(set (match_dup 5)
1081 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
1082 (clobber (reg:DI 23))
1083 (clobber (reg:DI 28))])
1084 (set (match_operand:SI 0 "nonimmediate_operand" "")
1085 (subreg:SI (match_dup 5) 0))]
1086 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1088 operands[3] = gen_reg_rtx (DImode);
1089 operands[4] = gen_reg_rtx (DImode);
1090 operands[5] = gen_reg_rtx (DImode);
1093 (define_expand "divdi3"
1094 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1095 (div:DI (match_operand:DI 1 "register_operand" "")
1096 (match_operand:DI 2 "register_operand" "")))
1097 (clobber (reg:DI 23))
1098 (clobber (reg:DI 28))])]
1099 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1102 (define_expand "udivdi3"
1103 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1104 (udiv:DI (match_operand:DI 1 "register_operand" "")
1105 (match_operand:DI 2 "register_operand" "")))
1106 (clobber (reg:DI 23))
1107 (clobber (reg:DI 28))])]
1108 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1111 (define_expand "moddi3"
1112 [(use (match_operand:DI 0 "register_operand" ""))
1113 (use (match_operand:DI 1 "register_operand" ""))
1114 (use (match_operand:DI 2 "register_operand" ""))]
1115 "!TARGET_ABI_OPEN_VMS"
1117 if (TARGET_ABI_UNICOSMK)
1118 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
1120 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
1124 (define_expand "moddi3_dft"
1125 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1126 (mod:DI (match_operand:DI 1 "register_operand" "")
1127 (match_operand:DI 2 "register_operand" "")))
1128 (clobber (reg:DI 23))
1129 (clobber (reg:DI 28))])]
1130 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1133 ;; On Unicos/Mk, we do as the system's C compiler does:
1134 ;; compute the quotient, multiply and subtract.
1136 (define_expand "moddi3_umk"
1137 [(use (match_operand:DI 0 "register_operand" ""))
1138 (use (match_operand:DI 1 "register_operand" ""))
1139 (use (match_operand:DI 2 "register_operand" ""))]
1140 "TARGET_ABI_UNICOSMK"
1142 rtx div, mul = gen_reg_rtx (DImode);
1144 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
1145 NULL_RTX, 0, OPTAB_LIB);
1146 div = force_reg (DImode, div);
1147 emit_insn (gen_muldi3 (mul, operands[2], div));
1148 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1152 (define_expand "umoddi3"
1153 [(use (match_operand:DI 0 "register_operand" ""))
1154 (use (match_operand:DI 1 "register_operand" ""))
1155 (use (match_operand:DI 2 "register_operand" ""))]
1156 "! TARGET_ABI_OPEN_VMS"
1158 if (TARGET_ABI_UNICOSMK)
1159 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
1161 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
1165 (define_expand "umoddi3_dft"
1166 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1167 (umod:DI (match_operand:DI 1 "register_operand" "")
1168 (match_operand:DI 2 "register_operand" "")))
1169 (clobber (reg:DI 23))
1170 (clobber (reg:DI 28))])]
1171 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1174 (define_expand "umoddi3_umk"
1175 [(use (match_operand:DI 0 "register_operand" ""))
1176 (use (match_operand:DI 1 "register_operand" ""))
1177 (use (match_operand:DI 2 "register_operand" ""))]
1178 "TARGET_ABI_UNICOSMK"
1180 rtx div, mul = gen_reg_rtx (DImode);
1182 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
1183 NULL_RTX, 1, OPTAB_LIB);
1184 div = force_reg (DImode, div);
1185 emit_insn (gen_muldi3 (mul, operands[2], div));
1186 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1190 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1191 ;; expanded by the assembler.
1193 (define_insn_and_split "*divmodsi_internal_er"
1194 [(set (match_operand:DI 0 "register_operand" "=c")
1195 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1196 [(match_operand:DI 1 "register_operand" "a")
1197 (match_operand:DI 2 "register_operand" "b")])))
1198 (clobber (reg:DI 23))
1199 (clobber (reg:DI 28))]
1200 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1201 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1202 "&& reload_completed"
1203 [(parallel [(set (match_dup 0)
1204 (sign_extend:DI (match_dup 3)))
1206 (clobber (reg:DI 23))
1207 (clobber (reg:DI 28))])]
1210 switch (GET_CODE (operands[3]))
1227 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1228 gen_rtx_SYMBOL_REF (DImode, str),
1231 [(set_attr "type" "jsr")
1232 (set_attr "length" "8")])
1234 (define_insn "*divmodsi_internal_er_1"
1235 [(set (match_operand:DI 0 "register_operand" "=c")
1236 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1237 [(match_operand:DI 1 "register_operand" "a")
1238 (match_operand:DI 2 "register_operand" "b")])))
1239 (use (match_operand:DI 4 "register_operand" "c"))
1240 (clobber (reg:DI 23))
1241 (clobber (reg:DI 28))]
1242 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1243 "jsr $23,($27),__%E3"
1244 [(set_attr "type" "jsr")
1245 (set_attr "length" "4")])
1247 (define_insn "*divmodsi_internal"
1248 [(set (match_operand:DI 0 "register_operand" "=c")
1249 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1250 [(match_operand:DI 1 "register_operand" "a")
1251 (match_operand:DI 2 "register_operand" "b")])))
1252 (clobber (reg:DI 23))
1253 (clobber (reg:DI 28))]
1254 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1256 [(set_attr "type" "jsr")
1257 (set_attr "length" "8")])
1259 (define_insn_and_split "*divmoddi_internal_er"
1260 [(set (match_operand:DI 0 "register_operand" "=c")
1261 (match_operator:DI 3 "divmod_operator"
1262 [(match_operand:DI 1 "register_operand" "a")
1263 (match_operand:DI 2 "register_operand" "b")]))
1264 (clobber (reg:DI 23))
1265 (clobber (reg:DI 28))]
1266 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1267 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1268 "&& reload_completed"
1269 [(parallel [(set (match_dup 0) (match_dup 3))
1271 (clobber (reg:DI 23))
1272 (clobber (reg:DI 28))])]
1275 switch (GET_CODE (operands[3]))
1292 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1293 gen_rtx_SYMBOL_REF (DImode, str),
1296 [(set_attr "type" "jsr")
1297 (set_attr "length" "8")])
1299 (define_insn "*divmoddi_internal_er_1"
1300 [(set (match_operand:DI 0 "register_operand" "=c")
1301 (match_operator:DI 3 "divmod_operator"
1302 [(match_operand:DI 1 "register_operand" "a")
1303 (match_operand:DI 2 "register_operand" "b")]))
1304 (use (match_operand:DI 4 "register_operand" "c"))
1305 (clobber (reg:DI 23))
1306 (clobber (reg:DI 28))]
1307 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1308 "jsr $23,($27),__%E3"
1309 [(set_attr "type" "jsr")
1310 (set_attr "length" "4")])
1312 (define_insn "*divmoddi_internal"
1313 [(set (match_operand:DI 0 "register_operand" "=c")
1314 (match_operator:DI 3 "divmod_operator"
1315 [(match_operand:DI 1 "register_operand" "a")
1316 (match_operand:DI 2 "register_operand" "b")]))
1317 (clobber (reg:DI 23))
1318 (clobber (reg:DI 28))]
1319 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1321 [(set_attr "type" "jsr")
1322 (set_attr "length" "8")])
1324 ;; Next are the basic logical operations. These only exist in DImode.
1326 (define_insn "anddi3"
1327 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1328 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1329 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1335 [(set_attr "type" "ilog,ilog,shift")])
1337 ;; There are times when we can split an AND into two AND insns. This occurs
1338 ;; when we can first clear any bytes and then clear anything else. For
1339 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1340 ;; Only do this when running on 64-bit host since the computations are
1341 ;; too messy otherwise.
1344 [(set (match_operand:DI 0 "register_operand" "")
1345 (and:DI (match_operand:DI 1 "register_operand" "")
1346 (match_operand:DI 2 "const_int_operand" "")))]
1347 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1348 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1349 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1351 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1352 unsigned HOST_WIDE_INT mask2 = mask1;
1355 /* For each byte that isn't all zeros, make it all ones. */
1356 for (i = 0; i < 64; i += 8)
1357 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1358 mask1 |= (HOST_WIDE_INT) 0xff << i;
1360 /* Now turn on any bits we've just turned off. */
1363 operands[3] = GEN_INT (mask1);
1364 operands[4] = GEN_INT (mask2);
1367 (define_expand "zero_extendqihi2"
1368 [(set (match_operand:HI 0 "register_operand" "")
1369 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1373 operands[1] = force_reg (QImode, operands[1]);
1376 (define_insn "*zero_extendqihi2_bwx"
1377 [(set (match_operand:HI 0 "register_operand" "=r,r")
1378 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1383 [(set_attr "type" "ilog,ild")])
1385 (define_insn "*zero_extendqihi2_nobwx"
1386 [(set (match_operand:HI 0 "register_operand" "=r")
1387 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1390 [(set_attr "type" "ilog")])
1392 (define_expand "zero_extendqisi2"
1393 [(set (match_operand:SI 0 "register_operand" "")
1394 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1398 operands[1] = force_reg (QImode, operands[1]);
1401 (define_insn "*zero_extendqisi2_bwx"
1402 [(set (match_operand:SI 0 "register_operand" "=r,r")
1403 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1408 [(set_attr "type" "ilog,ild")])
1410 (define_insn "*zero_extendqisi2_nobwx"
1411 [(set (match_operand:SI 0 "register_operand" "=r")
1412 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1415 [(set_attr "type" "ilog")])
1417 (define_expand "zero_extendqidi2"
1418 [(set (match_operand:DI 0 "register_operand" "")
1419 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1423 operands[1] = force_reg (QImode, operands[1]);
1426 (define_insn "*zero_extendqidi2_bwx"
1427 [(set (match_operand:DI 0 "register_operand" "=r,r")
1428 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1433 [(set_attr "type" "ilog,ild")])
1435 (define_insn "*zero_extendqidi2_nobwx"
1436 [(set (match_operand:DI 0 "register_operand" "=r")
1437 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1440 [(set_attr "type" "ilog")])
1442 (define_expand "zero_extendhisi2"
1443 [(set (match_operand:SI 0 "register_operand" "")
1444 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1448 operands[1] = force_reg (HImode, operands[1]);
1451 (define_insn "*zero_extendhisi2_bwx"
1452 [(set (match_operand:SI 0 "register_operand" "=r,r")
1453 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1458 [(set_attr "type" "shift,ild")])
1460 (define_insn "*zero_extendhisi2_nobwx"
1461 [(set (match_operand:SI 0 "register_operand" "=r")
1462 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1465 [(set_attr "type" "shift")])
1467 (define_expand "zero_extendhidi2"
1468 [(set (match_operand:DI 0 "register_operand" "")
1469 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1473 operands[1] = force_reg (HImode, operands[1]);
1476 (define_insn "*zero_extendhidi2_bwx"
1477 [(set (match_operand:DI 0 "register_operand" "=r,r")
1478 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1483 [(set_attr "type" "shift,ild")])
1485 (define_insn "*zero_extendhidi2_nobwx"
1486 [(set (match_operand:DI 0 "register_operand" "=r")
1487 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1490 [(set_attr "type" "shift")])
1492 (define_insn "zero_extendsidi2"
1493 [(set (match_operand:DI 0 "register_operand" "=r")
1494 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1497 [(set_attr "type" "shift")])
1499 (define_insn "andnotdi3"
1500 [(set (match_operand:DI 0 "register_operand" "=r")
1501 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1502 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1505 [(set_attr "type" "ilog")])
1507 (define_insn "iordi3"
1508 [(set (match_operand:DI 0 "register_operand" "=r,r")
1509 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1510 (match_operand:DI 2 "or_operand" "rI,N")))]
1515 [(set_attr "type" "ilog")])
1517 (define_insn "one_cmpldi2"
1518 [(set (match_operand:DI 0 "register_operand" "=r")
1519 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1522 [(set_attr "type" "ilog")])
1524 (define_insn "*iornot"
1525 [(set (match_operand:DI 0 "register_operand" "=r")
1526 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1527 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1530 [(set_attr "type" "ilog")])
1532 (define_insn "xordi3"
1533 [(set (match_operand:DI 0 "register_operand" "=r,r")
1534 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1535 (match_operand:DI 2 "or_operand" "rI,N")))]
1540 [(set_attr "type" "ilog")])
1542 (define_insn "*xornot"
1543 [(set (match_operand:DI 0 "register_operand" "=r")
1544 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1545 (match_operand:DI 2 "register_operand" "rI"))))]
1548 [(set_attr "type" "ilog")])
1550 ;; Handle the FFS insn iff we support CIX.
1552 (define_expand "ffsdi2"
1554 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1556 (plus:DI (match_dup 2) (const_int 1)))
1557 (set (match_operand:DI 0 "register_operand" "")
1558 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1559 (const_int 0) (match_dup 3)))]
1562 operands[2] = gen_reg_rtx (DImode);
1563 operands[3] = gen_reg_rtx (DImode);
1566 (define_insn "*cttz"
1567 [(set (match_operand:DI 0 "register_operand" "=r")
1568 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1571 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1572 ; reuse the existing type name.
1573 [(set_attr "type" "mvi")])
1575 ;; Next come the shifts and the various extract and insert operations.
1577 (define_insn "ashldi3"
1578 [(set (match_operand:DI 0 "register_operand" "=r,r")
1579 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1580 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1583 switch (which_alternative)
1586 if (operands[2] == const1_rtx)
1587 return "addq %r1,%r1,%0";
1589 return "s%P2addq %r1,0,%0";
1591 return "sll %r1,%2,%0";
1596 [(set_attr "type" "iadd,shift")])
1598 ;; ??? The following pattern is made by combine, but earlier phases
1599 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1600 ;; with this in a better way at some point.
1602 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1604 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1605 ;; (match_operand:DI 2 "const_int_operand" "P"))
1607 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1609 ;; if (operands[2] == const1_rtx)
1610 ;; return "addl %r1,%r1,%0";
1612 ;; return "s%P2addl %r1,0,%0";
1614 ;; [(set_attr "type" "iadd")])
1616 (define_insn "lshrdi3"
1617 [(set (match_operand:DI 0 "register_operand" "=r")
1618 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1619 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1622 [(set_attr "type" "shift")])
1624 (define_insn "ashrdi3"
1625 [(set (match_operand:DI 0 "register_operand" "=r")
1626 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1627 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1630 [(set_attr "type" "shift")])
1632 (define_expand "extendqihi2"
1634 (ashift:DI (match_operand:QI 1 "some_operand" "")
1636 (set (match_operand:HI 0 "register_operand" "")
1637 (ashiftrt:DI (match_dup 2)
1643 emit_insn (gen_extendqihi2x (operands[0],
1644 force_reg (QImode, operands[1])));
1648 /* If we have an unaligned MEM, extend to DImode (which we do
1649 specially) and then copy to the result. */
1650 if (unaligned_memory_operand (operands[1], HImode))
1652 rtx temp = gen_reg_rtx (DImode);
1654 emit_insn (gen_extendqidi2 (temp, operands[1]));
1655 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1659 operands[0] = gen_lowpart (DImode, operands[0]);
1660 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1661 operands[2] = gen_reg_rtx (DImode);
1664 (define_insn "extendqidi2x"
1665 [(set (match_operand:DI 0 "register_operand" "=r")
1666 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1669 [(set_attr "type" "shift")])
1671 (define_insn "extendhidi2x"
1672 [(set (match_operand:DI 0 "register_operand" "=r")
1673 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1676 [(set_attr "type" "shift")])
1678 (define_insn "extendqisi2x"
1679 [(set (match_operand:SI 0 "register_operand" "=r")
1680 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1683 [(set_attr "type" "shift")])
1685 (define_insn "extendhisi2x"
1686 [(set (match_operand:SI 0 "register_operand" "=r")
1687 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1690 [(set_attr "type" "shift")])
1692 (define_insn "extendqihi2x"
1693 [(set (match_operand:HI 0 "register_operand" "=r")
1694 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1697 [(set_attr "type" "shift")])
1699 (define_expand "extendqisi2"
1701 (ashift:DI (match_operand:QI 1 "some_operand" "")
1703 (set (match_operand:SI 0 "register_operand" "")
1704 (ashiftrt:DI (match_dup 2)
1710 emit_insn (gen_extendqisi2x (operands[0],
1711 force_reg (QImode, operands[1])));
1715 /* If we have an unaligned MEM, extend to a DImode form of
1716 the result (which we do specially). */
1717 if (unaligned_memory_operand (operands[1], QImode))
1719 rtx temp = gen_reg_rtx (DImode);
1721 emit_insn (gen_extendqidi2 (temp, operands[1]));
1722 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1726 operands[0] = gen_lowpart (DImode, operands[0]);
1727 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1728 operands[2] = gen_reg_rtx (DImode);
1731 (define_expand "extendqidi2"
1733 (ashift:DI (match_operand:QI 1 "some_operand" "")
1735 (set (match_operand:DI 0 "register_operand" "")
1736 (ashiftrt:DI (match_dup 2)
1742 emit_insn (gen_extendqidi2x (operands[0],
1743 force_reg (QImode, operands[1])));
1747 if (unaligned_memory_operand (operands[1], QImode))
1750 = gen_unaligned_extendqidi (operands[0],
1751 get_unaligned_address (operands[1], 1));
1753 alpha_set_memflags (seq, operands[1]);
1758 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1759 operands[2] = gen_reg_rtx (DImode);
1762 (define_expand "extendhisi2"
1764 (ashift:DI (match_operand:HI 1 "some_operand" "")
1766 (set (match_operand:SI 0 "register_operand" "")
1767 (ashiftrt:DI (match_dup 2)
1773 emit_insn (gen_extendhisi2x (operands[0],
1774 force_reg (HImode, operands[1])));
1778 /* If we have an unaligned MEM, extend to a DImode form of
1779 the result (which we do specially). */
1780 if (unaligned_memory_operand (operands[1], HImode))
1782 rtx temp = gen_reg_rtx (DImode);
1784 emit_insn (gen_extendhidi2 (temp, operands[1]));
1785 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1789 operands[0] = gen_lowpart (DImode, operands[0]);
1790 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1791 operands[2] = gen_reg_rtx (DImode);
1794 (define_expand "extendhidi2"
1796 (ashift:DI (match_operand:HI 1 "some_operand" "")
1798 (set (match_operand:DI 0 "register_operand" "")
1799 (ashiftrt:DI (match_dup 2)
1805 emit_insn (gen_extendhidi2x (operands[0],
1806 force_reg (HImode, operands[1])));
1810 if (unaligned_memory_operand (operands[1], HImode))
1813 = gen_unaligned_extendhidi (operands[0],
1814 get_unaligned_address (operands[1], 2));
1816 alpha_set_memflags (seq, operands[1]);
1821 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1822 operands[2] = gen_reg_rtx (DImode);
1825 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1826 ;; as a pattern saves one instruction. The code is similar to that for
1827 ;; the unaligned loads (see below).
1829 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1830 (define_expand "unaligned_extendqidi"
1831 [(use (match_operand:QI 0 "register_operand" ""))
1832 (use (match_operand:DI 1 "address_operand" ""))]
1835 if (WORDS_BIG_ENDIAN)
1836 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1838 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1842 (define_expand "unaligned_extendqidi_le"
1843 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1845 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1848 (ashift:DI (match_dup 3)
1849 (minus:DI (const_int 64)
1851 (and:DI (match_dup 2) (const_int 7))
1853 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1854 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1855 "! WORDS_BIG_ENDIAN"
1857 operands[2] = gen_reg_rtx (DImode);
1858 operands[3] = gen_reg_rtx (DImode);
1859 operands[4] = gen_reg_rtx (DImode);
1862 (define_expand "unaligned_extendqidi_be"
1863 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1864 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1866 (mem:DI (and:DI (match_dup 3)
1868 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1870 (ashift:DI (match_dup 4)
1873 (plus:DI (match_dup 5) (const_int 1))
1876 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1877 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1880 operands[2] = gen_reg_rtx (DImode);
1881 operands[3] = gen_reg_rtx (DImode);
1882 operands[4] = gen_reg_rtx (DImode);
1883 operands[5] = gen_reg_rtx (DImode);
1884 operands[6] = gen_reg_rtx (DImode);
1887 (define_expand "unaligned_extendhidi"
1888 [(use (match_operand:QI 0 "register_operand" ""))
1889 (use (match_operand:DI 1 "address_operand" ""))]
1892 operands[0] = gen_lowpart (DImode, operands[0]);
1893 emit_insn ((WORDS_BIG_ENDIAN
1894 ? gen_unaligned_extendhidi_be
1895 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1899 (define_expand "unaligned_extendhidi_le"
1900 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1902 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1905 (ashift:DI (match_dup 3)
1906 (minus:DI (const_int 64)
1908 (and:DI (match_dup 2) (const_int 7))
1910 (set (match_operand:DI 0 "register_operand" "")
1911 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1912 "! WORDS_BIG_ENDIAN"
1914 operands[2] = gen_reg_rtx (DImode);
1915 operands[3] = gen_reg_rtx (DImode);
1916 operands[4] = gen_reg_rtx (DImode);
1919 (define_expand "unaligned_extendhidi_be"
1920 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1921 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1923 (mem:DI (and:DI (match_dup 3)
1925 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1927 (ashift:DI (match_dup 4)
1930 (plus:DI (match_dup 5) (const_int 1))
1933 (set (match_operand:DI 0 "register_operand" "")
1934 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1937 operands[2] = gen_reg_rtx (DImode);
1938 operands[3] = gen_reg_rtx (DImode);
1939 operands[4] = gen_reg_rtx (DImode);
1940 operands[5] = gen_reg_rtx (DImode);
1941 operands[6] = gen_reg_rtx (DImode);
1944 (define_insn "*extxl_const"
1945 [(set (match_operand:DI 0 "register_operand" "=r")
1946 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1947 (match_operand:DI 2 "mode_width_operand" "n")
1948 (match_operand:DI 3 "mul8_operand" "I")))]
1950 "ext%M2l %r1,%s3,%0"
1951 [(set_attr "type" "shift")])
1953 (define_insn "extxl_le"
1954 [(set (match_operand:DI 0 "register_operand" "=r")
1955 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1956 (match_operand:DI 2 "mode_width_operand" "n")
1957 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1959 "! WORDS_BIG_ENDIAN"
1961 [(set_attr "type" "shift")])
1963 (define_insn "extxl_be"
1964 [(set (match_operand:DI 0 "register_operand" "=r")
1965 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1966 (match_operand:DI 2 "mode_width_operand" "n")
1970 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1974 [(set_attr "type" "shift")])
1976 ;; Combine has some strange notion of preserving existing undefined behaviour
1977 ;; in shifts larger than a word size. So capture these patterns that it
1978 ;; should have turned into zero_extracts.
1980 (define_insn "*extxl_1_le"
1981 [(set (match_operand:DI 0 "register_operand" "=r")
1982 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1983 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1985 (match_operand:DI 3 "mode_mask_operand" "n")))]
1986 "! WORDS_BIG_ENDIAN"
1988 [(set_attr "type" "shift")])
1990 (define_insn "*extxl_1_be"
1991 [(set (match_operand:DI 0 "register_operand" "=r")
1992 (and:DI (lshiftrt:DI
1993 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1994 (minus:DI (const_int 56)
1995 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1997 (match_operand:DI 3 "mode_mask_operand" "n")))]
2000 [(set_attr "type" "shift")])
2002 (define_insn "*extql_2_le"
2003 [(set (match_operand:DI 0 "register_operand" "=r")
2004 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2005 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2007 "! WORDS_BIG_ENDIAN"
2009 [(set_attr "type" "shift")])
2011 (define_insn "*extql_2_be"
2012 [(set (match_operand:DI 0 "register_operand" "=r")
2014 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2015 (minus:DI (const_int 56)
2017 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2021 [(set_attr "type" "shift")])
2023 (define_insn "extqh_le"
2024 [(set (match_operand:DI 0 "register_operand" "=r")
2026 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2027 (minus:DI (const_int 64)
2030 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2033 "! WORDS_BIG_ENDIAN"
2035 [(set_attr "type" "shift")])
2037 (define_insn "extqh_be"
2038 [(set (match_operand:DI 0 "register_operand" "=r")
2040 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2043 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2049 [(set_attr "type" "shift")])
2051 (define_insn "extlh_le"
2052 [(set (match_operand:DI 0 "register_operand" "=r")
2054 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2055 (const_int 2147483647))
2056 (minus:DI (const_int 64)
2059 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2062 "! WORDS_BIG_ENDIAN"
2064 [(set_attr "type" "shift")])
2066 (define_insn "extlh_be"
2067 [(set (match_operand:DI 0 "register_operand" "=r")
2070 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2074 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2078 (const_int 2147483647)))]
2081 [(set_attr "type" "shift")])
2083 (define_insn "extwh_le"
2084 [(set (match_operand:DI 0 "register_operand" "=r")
2086 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2088 (minus:DI (const_int 64)
2091 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2094 "! WORDS_BIG_ENDIAN"
2096 [(set_attr "type" "shift")])
2098 (define_insn "extwh_be"
2099 [(set (match_operand:DI 0 "register_operand" "=r")
2101 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2105 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2109 (const_int 65535)))]
2112 [(set_attr "type" "shift")])
2114 ;; This converts an extXl into an extXh with an appropriate adjustment
2115 ;; to the address calculation.
2118 ;; [(set (match_operand:DI 0 "register_operand" "")
2119 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2120 ;; (match_operand:DI 2 "mode_width_operand" "")
2121 ;; (ashift:DI (match_operand:DI 3 "" "")
2123 ;; (match_operand:DI 4 "const_int_operand" "")))
2124 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2125 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2126 ;; [(set (match_dup 5) (match_dup 6))
2127 ;; (set (match_dup 0)
2128 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2129 ;; (ashift:DI (plus:DI (match_dup 5)
2135 ;; operands[6] = plus_constant (operands[3],
2136 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2137 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2140 (define_insn "*insbl_const"
2141 [(set (match_operand:DI 0 "register_operand" "=r")
2142 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2143 (match_operand:DI 2 "mul8_operand" "I")))]
2146 [(set_attr "type" "shift")])
2148 (define_insn "*inswl_const"
2149 [(set (match_operand:DI 0 "register_operand" "=r")
2150 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2151 (match_operand:DI 2 "mul8_operand" "I")))]
2154 [(set_attr "type" "shift")])
2156 (define_insn "*insll_const"
2157 [(set (match_operand:DI 0 "register_operand" "=r")
2158 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2159 (match_operand:DI 2 "mul8_operand" "I")))]
2162 [(set_attr "type" "shift")])
2164 (define_insn "insbl_le"
2165 [(set (match_operand:DI 0 "register_operand" "=r")
2166 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2167 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2169 "! WORDS_BIG_ENDIAN"
2171 [(set_attr "type" "shift")])
2173 (define_insn "insbl_be"
2174 [(set (match_operand:DI 0 "register_operand" "=r")
2175 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2176 (minus:DI (const_int 56)
2177 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2181 [(set_attr "type" "shift")])
2183 (define_insn "inswl_le"
2184 [(set (match_operand:DI 0 "register_operand" "=r")
2185 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2186 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2188 "! WORDS_BIG_ENDIAN"
2190 [(set_attr "type" "shift")])
2192 (define_insn "inswl_be"
2193 [(set (match_operand:DI 0 "register_operand" "=r")
2194 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2195 (minus:DI (const_int 56)
2196 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2200 [(set_attr "type" "shift")])
2202 (define_insn "insll_le"
2203 [(set (match_operand:DI 0 "register_operand" "=r")
2204 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2205 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2207 "! WORDS_BIG_ENDIAN"
2209 [(set_attr "type" "shift")])
2211 (define_insn "insll_be"
2212 [(set (match_operand:DI 0 "register_operand" "=r")
2213 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2214 (minus:DI (const_int 56)
2215 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2219 [(set_attr "type" "shift")])
2221 (define_insn "insql_le"
2222 [(set (match_operand:DI 0 "register_operand" "=r")
2223 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2224 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2226 "! WORDS_BIG_ENDIAN"
2228 [(set_attr "type" "shift")])
2230 (define_insn "insql_be"
2231 [(set (match_operand:DI 0 "register_operand" "=r")
2232 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2233 (minus:DI (const_int 56)
2234 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2238 [(set_attr "type" "shift")])
2240 ;; Combine has this sometimes habit of moving the and outside of the
2241 ;; shift, making life more interesting.
2243 (define_insn "*insxl"
2244 [(set (match_operand:DI 0 "register_operand" "=r")
2245 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2246 (match_operand:DI 2 "mul8_operand" "I"))
2247 (match_operand:DI 3 "immediate_operand" "i")))]
2248 "HOST_BITS_PER_WIDE_INT == 64
2249 && GET_CODE (operands[3]) == CONST_INT
2250 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2251 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2252 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2253 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2254 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2255 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2257 #if HOST_BITS_PER_WIDE_INT == 64
2258 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2259 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2260 return "insbl %1,%s2,%0";
2261 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2262 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2263 return "inswl %1,%s2,%0";
2264 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2265 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2266 return "insll %1,%s2,%0";
2270 [(set_attr "type" "shift")])
2272 ;; We do not include the insXh insns because they are complex to express
2273 ;; and it does not appear that we would ever want to generate them.
2275 ;; Since we need them for block moves, though, cop out and use unspec.
2277 (define_insn "insxh"
2278 [(set (match_operand:DI 0 "register_operand" "=r")
2279 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2280 (match_operand:DI 2 "mode_width_operand" "n")
2281 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2285 [(set_attr "type" "shift")])
2287 (define_insn "mskxl_le"
2288 [(set (match_operand:DI 0 "register_operand" "=r")
2289 (and:DI (not:DI (ashift:DI
2290 (match_operand:DI 2 "mode_mask_operand" "n")
2292 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2294 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2295 "! WORDS_BIG_ENDIAN"
2297 [(set_attr "type" "shift")])
2299 (define_insn "mskxl_be"
2300 [(set (match_operand:DI 0 "register_operand" "=r")
2301 (and:DI (not:DI (ashift:DI
2302 (match_operand:DI 2 "mode_mask_operand" "n")
2303 (minus:DI (const_int 56)
2305 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2307 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2310 [(set_attr "type" "shift")])
2312 ;; We do not include the mskXh insns because it does not appear we would
2313 ;; ever generate one.
2315 ;; Again, we do for block moves and we use unspec again.
2317 (define_insn "mskxh"
2318 [(set (match_operand:DI 0 "register_operand" "=r")
2319 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2320 (match_operand:DI 2 "mode_width_operand" "n")
2321 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2325 [(set_attr "type" "shift")])
2327 ;; Prefer AND + NE over LSHIFTRT + AND.
2329 (define_insn_and_split "*ze_and_ne"
2330 [(set (match_operand:DI 0 "register_operand" "=r")
2331 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2333 (match_operand 2 "const_int_operand" "I")))]
2334 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2336 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2338 (and:DI (match_dup 1) (match_dup 3)))
2340 (ne:DI (match_dup 0) (const_int 0)))]
2341 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2343 ;; Floating-point operations. All the double-precision insns can extend
2344 ;; from single, so indicate that. The exception are the ones that simply
2345 ;; play with the sign bits; it's not clear what to do there.
2347 (define_insn "abssf2"
2348 [(set (match_operand:SF 0 "register_operand" "=f")
2349 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2352 [(set_attr "type" "fcpys")])
2354 (define_insn "*nabssf2"
2355 [(set (match_operand:SF 0 "register_operand" "=f")
2356 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2359 [(set_attr "type" "fadd")])
2361 (define_insn "absdf2"
2362 [(set (match_operand:DF 0 "register_operand" "=f")
2363 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2366 [(set_attr "type" "fcpys")])
2368 (define_insn "*nabsdf2"
2369 [(set (match_operand:DF 0 "register_operand" "=f")
2370 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2373 [(set_attr "type" "fadd")])
2375 (define_expand "abstf2"
2376 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2377 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2378 (use (match_dup 2))])]
2379 "TARGET_HAS_XFLOATING_LIBS"
2381 #if HOST_BITS_PER_WIDE_INT >= 64
2382 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2384 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2388 (define_insn_and_split "*abstf_internal"
2389 [(set (match_operand:TF 0 "register_operand" "=r")
2390 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2391 (use (match_operand:DI 2 "register_operand" "r"))]
2392 "TARGET_HAS_XFLOATING_LIBS"
2394 "&& reload_completed"
2396 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2398 (define_insn "negsf2"
2399 [(set (match_operand:SF 0 "register_operand" "=f")
2400 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2403 [(set_attr "type" "fadd")])
2405 (define_insn "negdf2"
2406 [(set (match_operand:DF 0 "register_operand" "=f")
2407 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2410 [(set_attr "type" "fadd")])
2412 (define_expand "negtf2"
2413 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2414 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2415 (use (match_dup 2))])]
2416 "TARGET_HAS_XFLOATING_LIBS"
2418 #if HOST_BITS_PER_WIDE_INT >= 64
2419 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2421 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2425 (define_insn_and_split "*negtf_internal"
2426 [(set (match_operand:TF 0 "register_operand" "=r")
2427 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2428 (use (match_operand:DI 2 "register_operand" "r"))]
2429 "TARGET_HAS_XFLOATING_LIBS"
2431 "&& reload_completed"
2433 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2435 (define_insn "*addsf_ieee"
2436 [(set (match_operand:SF 0 "register_operand" "=&f")
2437 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2438 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2439 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2440 "add%,%/ %R1,%R2,%0"
2441 [(set_attr "type" "fadd")
2442 (set_attr "trap" "yes")
2443 (set_attr "round_suffix" "normal")
2444 (set_attr "trap_suffix" "u_su_sui")])
2446 (define_insn "addsf3"
2447 [(set (match_operand:SF 0 "register_operand" "=f")
2448 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2449 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2451 "add%,%/ %R1,%R2,%0"
2452 [(set_attr "type" "fadd")
2453 (set_attr "trap" "yes")
2454 (set_attr "round_suffix" "normal")
2455 (set_attr "trap_suffix" "u_su_sui")])
2457 (define_insn "*adddf_ieee"
2458 [(set (match_operand:DF 0 "register_operand" "=&f")
2459 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2460 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2461 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2462 "add%-%/ %R1,%R2,%0"
2463 [(set_attr "type" "fadd")
2464 (set_attr "trap" "yes")
2465 (set_attr "round_suffix" "normal")
2466 (set_attr "trap_suffix" "u_su_sui")])
2468 (define_insn "adddf3"
2469 [(set (match_operand:DF 0 "register_operand" "=f")
2470 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2471 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2473 "add%-%/ %R1,%R2,%0"
2474 [(set_attr "type" "fadd")
2475 (set_attr "trap" "yes")
2476 (set_attr "round_suffix" "normal")
2477 (set_attr "trap_suffix" "u_su_sui")])
2479 (define_insn "*adddf_ext1"
2480 [(set (match_operand:DF 0 "register_operand" "=f")
2481 (plus:DF (float_extend:DF
2482 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2483 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2484 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2485 "add%-%/ %R1,%R2,%0"
2486 [(set_attr "type" "fadd")
2487 (set_attr "trap" "yes")
2488 (set_attr "round_suffix" "normal")
2489 (set_attr "trap_suffix" "u_su_sui")])
2491 (define_insn "*adddf_ext2"
2492 [(set (match_operand:DF 0 "register_operand" "=f")
2493 (plus:DF (float_extend:DF
2494 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2496 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2497 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2498 "add%-%/ %R1,%R2,%0"
2499 [(set_attr "type" "fadd")
2500 (set_attr "trap" "yes")
2501 (set_attr "round_suffix" "normal")
2502 (set_attr "trap_suffix" "u_su_sui")])
2504 (define_expand "addtf3"
2505 [(use (match_operand 0 "register_operand" ""))
2506 (use (match_operand 1 "general_operand" ""))
2507 (use (match_operand 2 "general_operand" ""))]
2508 "TARGET_HAS_XFLOATING_LIBS"
2509 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2511 ;; Define conversion operators between DFmode and SImode, using the cvtql
2512 ;; instruction. To allow combine et al to do useful things, we keep the
2513 ;; operation as a unit until after reload, at which point we split the
2516 ;; Note that we (attempt to) only consider this optimization when the
2517 ;; ultimate destination is memory. If we will be doing further integer
2518 ;; processing, it is cheaper to do the truncation in the int regs.
2520 (define_insn "*cvtql"
2521 [(set (match_operand:SI 0 "register_operand" "=f")
2522 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2526 [(set_attr "type" "fadd")
2527 (set_attr "trap" "yes")
2528 (set_attr "trap_suffix" "v_sv")])
2530 (define_insn_and_split "*fix_truncdfsi_ieee"
2531 [(set (match_operand:SI 0 "memory_operand" "=m")
2532 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2533 (clobber (match_scratch:DI 2 "=&f"))
2534 (clobber (match_scratch:SI 3 "=&f"))]
2535 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2537 "&& reload_completed"
2538 [(set (match_dup 2) (fix:DI (match_dup 1)))
2539 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2540 (set (match_dup 0) (match_dup 3))]
2542 [(set_attr "type" "fadd")
2543 (set_attr "trap" "yes")])
2545 (define_insn_and_split "*fix_truncdfsi_internal"
2546 [(set (match_operand:SI 0 "memory_operand" "=m")
2547 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2548 (clobber (match_scratch:DI 2 "=f"))]
2549 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2551 "&& reload_completed"
2552 [(set (match_dup 2) (fix:DI (match_dup 1)))
2553 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2554 (set (match_dup 0) (match_dup 3))]
2555 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2556 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2557 [(set_attr "type" "fadd")
2558 (set_attr "trap" "yes")])
2560 (define_insn "*fix_truncdfdi_ieee"
2561 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2562 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2563 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2565 [(set_attr "type" "fadd")
2566 (set_attr "trap" "yes")
2567 (set_attr "round_suffix" "c")
2568 (set_attr "trap_suffix" "v_sv_svi")])
2570 (define_insn "fix_truncdfdi2"
2571 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2572 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2575 [(set_attr "type" "fadd")
2576 (set_attr "trap" "yes")
2577 (set_attr "round_suffix" "c")
2578 (set_attr "trap_suffix" "v_sv_svi")])
2580 ;; Likewise between SFmode and SImode.
2582 (define_insn_and_split "*fix_truncsfsi_ieee"
2583 [(set (match_operand:SI 0 "memory_operand" "=m")
2584 (subreg:SI (fix:DI (float_extend:DF
2585 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2586 (clobber (match_scratch:DI 2 "=&f"))
2587 (clobber (match_scratch:SI 3 "=&f"))]
2588 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2590 "&& reload_completed"
2591 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2592 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2593 (set (match_dup 0) (match_dup 3))]
2595 [(set_attr "type" "fadd")
2596 (set_attr "trap" "yes")])
2598 (define_insn_and_split "*fix_truncsfsi_internal"
2599 [(set (match_operand:SI 0 "memory_operand" "=m")
2600 (subreg:SI (fix:DI (float_extend:DF
2601 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2602 (clobber (match_scratch:DI 2 "=f"))]
2603 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2605 "&& reload_completed"
2606 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2607 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2608 (set (match_dup 0) (match_dup 3))]
2609 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2610 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2611 [(set_attr "type" "fadd")
2612 (set_attr "trap" "yes")])
2614 (define_insn "*fix_truncsfdi_ieee"
2615 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2616 (fix:DI (float_extend:DF
2617 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2618 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2620 [(set_attr "type" "fadd")
2621 (set_attr "trap" "yes")
2622 (set_attr "round_suffix" "c")
2623 (set_attr "trap_suffix" "v_sv_svi")])
2625 (define_insn "fix_truncsfdi2"
2626 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2627 (fix:DI (float_extend:DF
2628 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2631 [(set_attr "type" "fadd")
2632 (set_attr "trap" "yes")
2633 (set_attr "round_suffix" "c")
2634 (set_attr "trap_suffix" "v_sv_svi")])
2636 (define_expand "fix_trunctfdi2"
2637 [(use (match_operand:DI 0 "register_operand" ""))
2638 (use (match_operand:TF 1 "general_operand" ""))]
2639 "TARGET_HAS_XFLOATING_LIBS"
2640 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2642 (define_insn "*floatdisf_ieee"
2643 [(set (match_operand:SF 0 "register_operand" "=&f")
2644 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2645 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2647 [(set_attr "type" "fadd")
2648 (set_attr "trap" "yes")
2649 (set_attr "round_suffix" "normal")
2650 (set_attr "trap_suffix" "sui")])
2652 (define_insn "floatdisf2"
2653 [(set (match_operand:SF 0 "register_operand" "=f")
2654 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2657 [(set_attr "type" "fadd")
2658 (set_attr "trap" "yes")
2659 (set_attr "round_suffix" "normal")
2660 (set_attr "trap_suffix" "sui")])
2662 (define_insn "*floatdidf_ieee"
2663 [(set (match_operand:DF 0 "register_operand" "=&f")
2664 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2665 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2667 [(set_attr "type" "fadd")
2668 (set_attr "trap" "yes")
2669 (set_attr "round_suffix" "normal")
2670 (set_attr "trap_suffix" "sui")])
2672 (define_insn "floatdidf2"
2673 [(set (match_operand:DF 0 "register_operand" "=f")
2674 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2677 [(set_attr "type" "fadd")
2678 (set_attr "trap" "yes")
2679 (set_attr "round_suffix" "normal")
2680 (set_attr "trap_suffix" "sui")])
2682 (define_expand "floatditf2"
2683 [(use (match_operand:TF 0 "register_operand" ""))
2684 (use (match_operand:DI 1 "general_operand" ""))]
2685 "TARGET_HAS_XFLOATING_LIBS"
2686 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2688 (define_expand "floatunsdisf2"
2689 [(use (match_operand:SF 0 "register_operand" ""))
2690 (use (match_operand:DI 1 "register_operand" ""))]
2692 "alpha_emit_floatuns (operands); DONE;")
2694 (define_expand "floatunsdidf2"
2695 [(use (match_operand:DF 0 "register_operand" ""))
2696 (use (match_operand:DI 1 "register_operand" ""))]
2698 "alpha_emit_floatuns (operands); DONE;")
2700 (define_expand "floatunsditf2"
2701 [(use (match_operand:TF 0 "register_operand" ""))
2702 (use (match_operand:DI 1 "general_operand" ""))]
2703 "TARGET_HAS_XFLOATING_LIBS"
2704 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2706 (define_expand "extendsfdf2"
2707 [(set (match_operand:DF 0 "register_operand" "")
2708 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2711 if (alpha_fptm >= ALPHA_FPTM_SU)
2712 operands[1] = force_reg (SFmode, operands[1]);
2715 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2716 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2718 (define_insn "*extendsfdf2_ieee"
2719 [(set (match_operand:DF 0 "register_operand" "=&f")
2720 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2721 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2723 [(set_attr "type" "fadd")
2724 (set_attr "trap" "yes")])
2726 (define_insn "*extendsfdf2_internal"
2727 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2728 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2729 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2734 [(set_attr "type" "fcpys,fld,fst")])
2736 (define_expand "extendsftf2"
2737 [(use (match_operand:TF 0 "register_operand" ""))
2738 (use (match_operand:SF 1 "general_operand" ""))]
2739 "TARGET_HAS_XFLOATING_LIBS"
2741 rtx tmp = gen_reg_rtx (DFmode);
2742 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2743 emit_insn (gen_extenddftf2 (operands[0], tmp));
2747 (define_expand "extenddftf2"
2748 [(use (match_operand:TF 0 "register_operand" ""))
2749 (use (match_operand:DF 1 "general_operand" ""))]
2750 "TARGET_HAS_XFLOATING_LIBS"
2751 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2753 (define_insn "*truncdfsf2_ieee"
2754 [(set (match_operand:SF 0 "register_operand" "=&f")
2755 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2756 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2758 [(set_attr "type" "fadd")
2759 (set_attr "trap" "yes")
2760 (set_attr "round_suffix" "normal")
2761 (set_attr "trap_suffix" "u_su_sui")])
2763 (define_insn "truncdfsf2"
2764 [(set (match_operand:SF 0 "register_operand" "=f")
2765 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2768 [(set_attr "type" "fadd")
2769 (set_attr "trap" "yes")
2770 (set_attr "round_suffix" "normal")
2771 (set_attr "trap_suffix" "u_su_sui")])
2773 (define_expand "trunctfdf2"
2774 [(use (match_operand:DF 0 "register_operand" ""))
2775 (use (match_operand:TF 1 "general_operand" ""))]
2776 "TARGET_HAS_XFLOATING_LIBS"
2777 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2779 (define_expand "trunctfsf2"
2780 [(use (match_operand:SF 0 "register_operand" ""))
2781 (use (match_operand:TF 1 "general_operand" ""))]
2782 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2784 rtx tmpf, sticky, arg, lo, hi;
2786 tmpf = gen_reg_rtx (DFmode);
2787 sticky = gen_reg_rtx (DImode);
2788 arg = copy_to_mode_reg (TFmode, operands[1]);
2789 lo = gen_lowpart (DImode, arg);
2790 hi = gen_highpart (DImode, arg);
2792 /* Convert the low word of the TFmode value into a sticky rounding bit,
2793 then or it into the low bit of the high word. This leaves the sticky
2794 bit at bit 48 of the fraction, which is representable in DFmode,
2795 which prevents rounding error in the final conversion to SFmode. */
2797 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2798 gen_rtx_NE (DImode, lo, const0_rtx)));
2799 emit_insn (gen_iordi3 (hi, hi, sticky));
2800 emit_insn (gen_trunctfdf2 (tmpf, arg));
2801 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2805 (define_insn "*divsf3_ieee"
2806 [(set (match_operand:SF 0 "register_operand" "=&f")
2807 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2808 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2809 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2810 "div%,%/ %R1,%R2,%0"
2811 [(set_attr "type" "fdiv")
2812 (set_attr "opsize" "si")
2813 (set_attr "trap" "yes")
2814 (set_attr "round_suffix" "normal")
2815 (set_attr "trap_suffix" "u_su_sui")])
2817 (define_insn "divsf3"
2818 [(set (match_operand:SF 0 "register_operand" "=f")
2819 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2820 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2822 "div%,%/ %R1,%R2,%0"
2823 [(set_attr "type" "fdiv")
2824 (set_attr "opsize" "si")
2825 (set_attr "trap" "yes")
2826 (set_attr "round_suffix" "normal")
2827 (set_attr "trap_suffix" "u_su_sui")])
2829 (define_insn "*divdf3_ieee"
2830 [(set (match_operand:DF 0 "register_operand" "=&f")
2831 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2832 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2833 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2834 "div%-%/ %R1,%R2,%0"
2835 [(set_attr "type" "fdiv")
2836 (set_attr "trap" "yes")
2837 (set_attr "round_suffix" "normal")
2838 (set_attr "trap_suffix" "u_su_sui")])
2840 (define_insn "divdf3"
2841 [(set (match_operand:DF 0 "register_operand" "=f")
2842 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2843 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2845 "div%-%/ %R1,%R2,%0"
2846 [(set_attr "type" "fdiv")
2847 (set_attr "trap" "yes")
2848 (set_attr "round_suffix" "normal")
2849 (set_attr "trap_suffix" "u_su_sui")])
2851 (define_insn "*divdf_ext1"
2852 [(set (match_operand:DF 0 "register_operand" "=f")
2853 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2854 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2855 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2856 "div%-%/ %R1,%R2,%0"
2857 [(set_attr "type" "fdiv")
2858 (set_attr "trap" "yes")
2859 (set_attr "round_suffix" "normal")
2860 (set_attr "trap_suffix" "u_su_sui")])
2862 (define_insn "*divdf_ext2"
2863 [(set (match_operand:DF 0 "register_operand" "=f")
2864 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2866 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2867 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2868 "div%-%/ %R1,%R2,%0"
2869 [(set_attr "type" "fdiv")
2870 (set_attr "trap" "yes")
2871 (set_attr "round_suffix" "normal")
2872 (set_attr "trap_suffix" "u_su_sui")])
2874 (define_insn "*divdf_ext3"
2875 [(set (match_operand:DF 0 "register_operand" "=f")
2876 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2877 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2878 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2879 "div%-%/ %R1,%R2,%0"
2880 [(set_attr "type" "fdiv")
2881 (set_attr "trap" "yes")
2882 (set_attr "round_suffix" "normal")
2883 (set_attr "trap_suffix" "u_su_sui")])
2885 (define_expand "divtf3"
2886 [(use (match_operand 0 "register_operand" ""))
2887 (use (match_operand 1 "general_operand" ""))
2888 (use (match_operand 2 "general_operand" ""))]
2889 "TARGET_HAS_XFLOATING_LIBS"
2890 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2892 (define_insn "*mulsf3_ieee"
2893 [(set (match_operand:SF 0 "register_operand" "=&f")
2894 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2895 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2896 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2897 "mul%,%/ %R1,%R2,%0"
2898 [(set_attr "type" "fmul")
2899 (set_attr "trap" "yes")
2900 (set_attr "round_suffix" "normal")
2901 (set_attr "trap_suffix" "u_su_sui")])
2903 (define_insn "mulsf3"
2904 [(set (match_operand:SF 0 "register_operand" "=f")
2905 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2906 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2908 "mul%,%/ %R1,%R2,%0"
2909 [(set_attr "type" "fmul")
2910 (set_attr "trap" "yes")
2911 (set_attr "round_suffix" "normal")
2912 (set_attr "trap_suffix" "u_su_sui")])
2914 (define_insn "*muldf3_ieee"
2915 [(set (match_operand:DF 0 "register_operand" "=&f")
2916 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2917 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2918 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2919 "mul%-%/ %R1,%R2,%0"
2920 [(set_attr "type" "fmul")
2921 (set_attr "trap" "yes")
2922 (set_attr "round_suffix" "normal")
2923 (set_attr "trap_suffix" "u_su_sui")])
2925 (define_insn "muldf3"
2926 [(set (match_operand:DF 0 "register_operand" "=f")
2927 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2928 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2930 "mul%-%/ %R1,%R2,%0"
2931 [(set_attr "type" "fmul")
2932 (set_attr "trap" "yes")
2933 (set_attr "round_suffix" "normal")
2934 (set_attr "trap_suffix" "u_su_sui")])
2936 (define_insn "*muldf_ext1"
2937 [(set (match_operand:DF 0 "register_operand" "=f")
2938 (mult:DF (float_extend:DF
2939 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2940 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2941 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2942 "mul%-%/ %R1,%R2,%0"
2943 [(set_attr "type" "fmul")
2944 (set_attr "trap" "yes")
2945 (set_attr "round_suffix" "normal")
2946 (set_attr "trap_suffix" "u_su_sui")])
2948 (define_insn "*muldf_ext2"
2949 [(set (match_operand:DF 0 "register_operand" "=f")
2950 (mult:DF (float_extend:DF
2951 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2953 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2954 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2955 "mul%-%/ %R1,%R2,%0"
2956 [(set_attr "type" "fmul")
2957 (set_attr "trap" "yes")
2958 (set_attr "round_suffix" "normal")
2959 (set_attr "trap_suffix" "u_su_sui")])
2961 (define_expand "multf3"
2962 [(use (match_operand 0 "register_operand" ""))
2963 (use (match_operand 1 "general_operand" ""))
2964 (use (match_operand 2 "general_operand" ""))]
2965 "TARGET_HAS_XFLOATING_LIBS"
2966 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2968 (define_insn "*subsf3_ieee"
2969 [(set (match_operand:SF 0 "register_operand" "=&f")
2970 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2971 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2972 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2973 "sub%,%/ %R1,%R2,%0"
2974 [(set_attr "type" "fadd")
2975 (set_attr "trap" "yes")
2976 (set_attr "round_suffix" "normal")
2977 (set_attr "trap_suffix" "u_su_sui")])
2979 (define_insn "subsf3"
2980 [(set (match_operand:SF 0 "register_operand" "=f")
2981 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2982 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2984 "sub%,%/ %R1,%R2,%0"
2985 [(set_attr "type" "fadd")
2986 (set_attr "trap" "yes")
2987 (set_attr "round_suffix" "normal")
2988 (set_attr "trap_suffix" "u_su_sui")])
2990 (define_insn "*subdf3_ieee"
2991 [(set (match_operand:DF 0 "register_operand" "=&f")
2992 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2993 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2994 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2995 "sub%-%/ %R1,%R2,%0"
2996 [(set_attr "type" "fadd")
2997 (set_attr "trap" "yes")
2998 (set_attr "round_suffix" "normal")
2999 (set_attr "trap_suffix" "u_su_sui")])
3001 (define_insn "subdf3"
3002 [(set (match_operand:DF 0 "register_operand" "=f")
3003 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3004 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
3006 "sub%-%/ %R1,%R2,%0"
3007 [(set_attr "type" "fadd")
3008 (set_attr "trap" "yes")
3009 (set_attr "round_suffix" "normal")
3010 (set_attr "trap_suffix" "u_su_sui")])
3012 (define_insn "*subdf_ext1"
3013 [(set (match_operand:DF 0 "register_operand" "=f")
3014 (minus:DF (float_extend:DF
3015 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
3016 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
3017 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3018 "sub%-%/ %R1,%R2,%0"
3019 [(set_attr "type" "fadd")
3020 (set_attr "trap" "yes")
3021 (set_attr "round_suffix" "normal")
3022 (set_attr "trap_suffix" "u_su_sui")])
3024 (define_insn "*subdf_ext2"
3025 [(set (match_operand:DF 0 "register_operand" "=f")
3026 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3028 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3029 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3030 "sub%-%/ %R1,%R2,%0"
3031 [(set_attr "type" "fadd")
3032 (set_attr "trap" "yes")
3033 (set_attr "round_suffix" "normal")
3034 (set_attr "trap_suffix" "u_su_sui")])
3036 (define_insn "*subdf_ext3"
3037 [(set (match_operand:DF 0 "register_operand" "=f")
3038 (minus:DF (float_extend:DF
3039 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
3041 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3042 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3043 "sub%-%/ %R1,%R2,%0"
3044 [(set_attr "type" "fadd")
3045 (set_attr "trap" "yes")
3046 (set_attr "round_suffix" "normal")
3047 (set_attr "trap_suffix" "u_su_sui")])
3049 (define_expand "subtf3"
3050 [(use (match_operand 0 "register_operand" ""))
3051 (use (match_operand 1 "general_operand" ""))
3052 (use (match_operand 2 "general_operand" ""))]
3053 "TARGET_HAS_XFLOATING_LIBS"
3054 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3056 (define_insn "*sqrtsf2_ieee"
3057 [(set (match_operand:SF 0 "register_operand" "=&f")
3058 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3059 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3061 [(set_attr "type" "fsqrt")
3062 (set_attr "opsize" "si")
3063 (set_attr "trap" "yes")
3064 (set_attr "round_suffix" "normal")
3065 (set_attr "trap_suffix" "u_su_sui")])
3067 (define_insn "sqrtsf2"
3068 [(set (match_operand:SF 0 "register_operand" "=f")
3069 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3070 "TARGET_FP && TARGET_FIX"
3072 [(set_attr "type" "fsqrt")
3073 (set_attr "opsize" "si")
3074 (set_attr "trap" "yes")
3075 (set_attr "round_suffix" "normal")
3076 (set_attr "trap_suffix" "u_su_sui")])
3078 (define_insn "*sqrtdf2_ieee"
3079 [(set (match_operand:DF 0 "register_operand" "=&f")
3080 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3081 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3083 [(set_attr "type" "fsqrt")
3084 (set_attr "trap" "yes")
3085 (set_attr "round_suffix" "normal")
3086 (set_attr "trap_suffix" "u_su_sui")])
3088 (define_insn "sqrtdf2"
3089 [(set (match_operand:DF 0 "register_operand" "=f")
3090 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3091 "TARGET_FP && TARGET_FIX"
3093 [(set_attr "type" "fsqrt")
3094 (set_attr "trap" "yes")
3095 (set_attr "round_suffix" "normal")
3096 (set_attr "trap_suffix" "u_su_sui")])
3098 ;; Next are all the integer comparisons, and conditional moves and branches
3099 ;; and some of the related define_expand's and define_split's.
3101 (define_insn "*setcc_internal"
3102 [(set (match_operand 0 "register_operand" "=r")
3103 (match_operator 1 "alpha_comparison_operator"
3104 [(match_operand:DI 2 "register_operand" "r")
3105 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3106 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3107 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3108 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3110 [(set_attr "type" "icmp")])
3112 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3113 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3115 (define_insn "*setcc_swapped_internal"
3116 [(set (match_operand 0 "register_operand" "=r")
3117 (match_operator 1 "alpha_swapped_comparison_operator"
3118 [(match_operand:DI 2 "register_operand" "r")
3119 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3120 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3121 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3122 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3124 [(set_attr "type" "icmp")])
3126 ;; Use match_operator rather than ne directly so that we can match
3127 ;; multiple integer modes.
3128 (define_insn "*setne_internal"
3129 [(set (match_operand 0 "register_operand" "=r")
3130 (match_operator 1 "signed_comparison_operator"
3131 [(match_operand:DI 2 "register_operand" "r")
3133 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3134 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3135 && GET_CODE (operands[1]) == NE
3136 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3138 [(set_attr "type" "icmp")])
3140 ;; The mode folding trick can't be used with const_int operands, since
3141 ;; reload needs to know the proper mode.
3143 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3144 ;; in order to create more pairs of constants. As long as we're allowing
3145 ;; two constants at the same time, and will have to reload one of them...
3147 (define_insn "*movqicc_internal"
3148 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3150 (match_operator 2 "signed_comparison_operator"
3151 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3152 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3153 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3154 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3155 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3161 [(set_attr "type" "icmov")])
3163 (define_insn "*movhicc_internal"
3164 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3166 (match_operator 2 "signed_comparison_operator"
3167 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3168 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3169 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3170 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3171 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3177 [(set_attr "type" "icmov")])
3179 (define_insn "*movsicc_internal"
3180 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3182 (match_operator 2 "signed_comparison_operator"
3183 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3184 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3185 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3186 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3187 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3193 [(set_attr "type" "icmov")])
3195 (define_insn "*movdicc_internal"
3196 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3198 (match_operator 2 "signed_comparison_operator"
3199 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3200 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3201 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3202 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3203 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3209 [(set_attr "type" "icmov")])
3211 (define_insn "*movqicc_lbc"
3212 [(set (match_operand:QI 0 "register_operand" "=r,r")
3214 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3218 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3219 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3224 [(set_attr "type" "icmov")])
3226 (define_insn "*movhicc_lbc"
3227 [(set (match_operand:HI 0 "register_operand" "=r,r")
3229 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3233 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3234 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3239 [(set_attr "type" "icmov")])
3241 (define_insn "*movsicc_lbc"
3242 [(set (match_operand:SI 0 "register_operand" "=r,r")
3244 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3248 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3249 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3254 [(set_attr "type" "icmov")])
3256 (define_insn "*movdicc_lbc"
3257 [(set (match_operand:DI 0 "register_operand" "=r,r")
3259 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3263 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3264 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3269 [(set_attr "type" "icmov")])
3271 (define_insn "*movqicc_lbs"
3272 [(set (match_operand:QI 0 "register_operand" "=r,r")
3274 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3278 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3279 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3284 [(set_attr "type" "icmov")])
3286 (define_insn "*movhicc_lbs"
3287 [(set (match_operand:HI 0 "register_operand" "=r,r")
3289 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3293 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3294 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3299 [(set_attr "type" "icmov")])
3301 (define_insn "*movsicc_lbs"
3302 [(set (match_operand:SI 0 "register_operand" "=r,r")
3304 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3308 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3309 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3314 [(set_attr "type" "icmov")])
3316 (define_insn "*movdicc_lbs"
3317 [(set (match_operand:DI 0 "register_operand" "=r,r")
3319 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3323 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3324 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3329 [(set_attr "type" "icmov")])
3331 ;; For ABS, we have two choices, depending on whether the input and output
3332 ;; registers are the same or not.
3333 (define_expand "absdi2"
3334 [(set (match_operand:DI 0 "register_operand" "")
3335 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3338 if (rtx_equal_p (operands[0], operands[1]))
3339 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3341 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3345 (define_expand "absdi2_same"
3346 [(set (match_operand:DI 1 "register_operand" "")
3347 (neg:DI (match_operand:DI 0 "register_operand" "")))
3349 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3355 (define_expand "absdi2_diff"
3356 [(set (match_operand:DI 0 "register_operand" "")
3357 (neg:DI (match_operand:DI 1 "register_operand" "")))
3359 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3366 [(set (match_operand:DI 0 "register_operand" "")
3367 (abs:DI (match_dup 0)))
3368 (clobber (match_operand:DI 1 "register_operand" ""))]
3370 [(set (match_dup 1) (neg:DI (match_dup 0)))
3371 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3372 (match_dup 0) (match_dup 1)))]
3376 [(set (match_operand:DI 0 "register_operand" "")
3377 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3378 "! rtx_equal_p (operands[0], operands[1])"
3379 [(set (match_dup 0) (neg:DI (match_dup 1)))
3380 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3381 (match_dup 0) (match_dup 1)))]
3385 [(set (match_operand:DI 0 "register_operand" "")
3386 (neg:DI (abs:DI (match_dup 0))))
3387 (clobber (match_operand:DI 1 "register_operand" ""))]
3389 [(set (match_dup 1) (neg:DI (match_dup 0)))
3390 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3391 (match_dup 0) (match_dup 1)))]
3395 [(set (match_operand:DI 0 "register_operand" "")
3396 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3397 "! rtx_equal_p (operands[0], operands[1])"
3398 [(set (match_dup 0) (neg:DI (match_dup 1)))
3399 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3400 (match_dup 0) (match_dup 1)))]
3403 (define_insn "sminqi3"
3404 [(set (match_operand:QI 0 "register_operand" "=r")
3405 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3406 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3409 [(set_attr "type" "mvi")])
3411 (define_insn "uminqi3"
3412 [(set (match_operand:QI 0 "register_operand" "=r")
3413 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3414 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3417 [(set_attr "type" "mvi")])
3419 (define_insn "smaxqi3"
3420 [(set (match_operand:QI 0 "register_operand" "=r")
3421 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3422 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3425 [(set_attr "type" "mvi")])
3427 (define_insn "umaxqi3"
3428 [(set (match_operand:QI 0 "register_operand" "=r")
3429 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3430 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3433 [(set_attr "type" "mvi")])
3435 (define_insn "sminhi3"
3436 [(set (match_operand:HI 0 "register_operand" "=r")
3437 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3438 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3441 [(set_attr "type" "mvi")])
3443 (define_insn "uminhi3"
3444 [(set (match_operand:HI 0 "register_operand" "=r")
3445 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3446 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3449 [(set_attr "type" "mvi")])
3451 (define_insn "smaxhi3"
3452 [(set (match_operand:HI 0 "register_operand" "=r")
3453 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3454 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3457 [(set_attr "type" "mvi")])
3459 (define_insn "umaxhi3"
3460 [(set (match_operand:HI 0 "register_operand" "=r")
3461 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3462 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3465 [(set_attr "type" "shift")])
3467 (define_expand "smaxdi3"
3469 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3470 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3471 (set (match_operand:DI 0 "register_operand" "")
3472 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3473 (match_dup 1) (match_dup 2)))]
3475 { operands[3] = gen_reg_rtx (DImode); })
3478 [(set (match_operand:DI 0 "register_operand" "")
3479 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3480 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3481 (clobber (match_operand:DI 3 "register_operand" ""))]
3482 "operands[2] != const0_rtx"
3483 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3484 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3485 (match_dup 1) (match_dup 2)))]
3488 (define_insn "*smax_const0"
3489 [(set (match_operand:DI 0 "register_operand" "=r")
3490 (smax:DI (match_operand:DI 1 "register_operand" "0")
3494 [(set_attr "type" "icmov")])
3496 (define_expand "smindi3"
3498 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3499 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3500 (set (match_operand:DI 0 "register_operand" "")
3501 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3502 (match_dup 1) (match_dup 2)))]
3504 { operands[3] = gen_reg_rtx (DImode); })
3507 [(set (match_operand:DI 0 "register_operand" "")
3508 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3509 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3510 (clobber (match_operand:DI 3 "register_operand" ""))]
3511 "operands[2] != const0_rtx"
3512 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3513 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3514 (match_dup 1) (match_dup 2)))]
3517 (define_insn "*smin_const0"
3518 [(set (match_operand:DI 0 "register_operand" "=r")
3519 (smin:DI (match_operand:DI 1 "register_operand" "0")
3523 [(set_attr "type" "icmov")])
3525 (define_expand "umaxdi3"
3527 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3528 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3529 (set (match_operand:DI 0 "register_operand" "")
3530 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3531 (match_dup 1) (match_dup 2)))]
3533 "operands[3] = gen_reg_rtx (DImode);")
3536 [(set (match_operand:DI 0 "register_operand" "")
3537 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3538 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3539 (clobber (match_operand:DI 3 "register_operand" ""))]
3540 "operands[2] != const0_rtx"
3541 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3542 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3543 (match_dup 1) (match_dup 2)))]
3546 (define_expand "umindi3"
3548 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3549 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3550 (set (match_operand:DI 0 "register_operand" "")
3551 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3552 (match_dup 1) (match_dup 2)))]
3554 "operands[3] = gen_reg_rtx (DImode);")
3557 [(set (match_operand:DI 0 "register_operand" "")
3558 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3559 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3560 (clobber (match_operand:DI 3 "register_operand" ""))]
3561 "operands[2] != const0_rtx"
3562 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3563 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3564 (match_dup 1) (match_dup 2)))]
3567 (define_insn "*bcc_normal"
3570 (match_operator 1 "signed_comparison_operator"
3571 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3573 (label_ref (match_operand 0 "" ""))
3577 [(set_attr "type" "ibr")])
3579 (define_insn "*bcc_reverse"
3582 (match_operator 1 "signed_comparison_operator"
3583 [(match_operand:DI 2 "register_operand" "r")
3587 (label_ref (match_operand 0 "" ""))))]
3590 [(set_attr "type" "ibr")])
3592 (define_insn "*blbs_normal"
3595 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3599 (label_ref (match_operand 0 "" ""))
3603 [(set_attr "type" "ibr")])
3605 (define_insn "*blbc_normal"
3608 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3612 (label_ref (match_operand 0 "" ""))
3616 [(set_attr "type" "ibr")])
3622 (match_operator 1 "comparison_operator"
3623 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3625 (match_operand:DI 3 "const_int_operand" ""))
3627 (label_ref (match_operand 0 "" ""))
3629 (clobber (match_operand:DI 4 "register_operand" ""))])]
3630 "INTVAL (operands[3]) != 0"
3632 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3634 (if_then_else (match_op_dup 1
3635 [(zero_extract:DI (match_dup 4)
3639 (label_ref (match_dup 0))
3643 ;; The following are the corresponding floating-point insns. Recall
3644 ;; we need to have variants that expand the arguments from SFmode
3647 (define_insn "*cmpdf_ieee"
3648 [(set (match_operand:DF 0 "register_operand" "=&f")
3649 (match_operator:DF 1 "alpha_fp_comparison_operator"
3650 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3651 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3652 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3653 "cmp%-%C1%/ %R2,%R3,%0"
3654 [(set_attr "type" "fadd")
3655 (set_attr "trap" "yes")
3656 (set_attr "trap_suffix" "su")])
3658 (define_insn "*cmpdf_internal"
3659 [(set (match_operand:DF 0 "register_operand" "=f")
3660 (match_operator:DF 1 "alpha_fp_comparison_operator"
3661 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3662 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3663 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3664 "cmp%-%C1%/ %R2,%R3,%0"
3665 [(set_attr "type" "fadd")
3666 (set_attr "trap" "yes")
3667 (set_attr "trap_suffix" "su")])
3669 (define_insn "*cmpdf_ieee_ext1"
3670 [(set (match_operand:DF 0 "register_operand" "=&f")
3671 (match_operator:DF 1 "alpha_fp_comparison_operator"
3673 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3674 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3675 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3676 "cmp%-%C1%/ %R2,%R3,%0"
3677 [(set_attr "type" "fadd")
3678 (set_attr "trap" "yes")
3679 (set_attr "trap_suffix" "su")])
3681 (define_insn "*cmpdf_ext1"
3682 [(set (match_operand:DF 0 "register_operand" "=f")
3683 (match_operator:DF 1 "alpha_fp_comparison_operator"
3685 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3686 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3687 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3688 "cmp%-%C1%/ %R2,%R3,%0"
3689 [(set_attr "type" "fadd")
3690 (set_attr "trap" "yes")
3691 (set_attr "trap_suffix" "su")])
3693 (define_insn "*cmpdf_ieee_ext2"
3694 [(set (match_operand:DF 0 "register_operand" "=&f")
3695 (match_operator:DF 1 "alpha_fp_comparison_operator"
3696 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3698 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3699 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3700 "cmp%-%C1%/ %R2,%R3,%0"
3701 [(set_attr "type" "fadd")
3702 (set_attr "trap" "yes")
3703 (set_attr "trap_suffix" "su")])
3705 (define_insn "*cmpdf_ext2"
3706 [(set (match_operand:DF 0 "register_operand" "=f")
3707 (match_operator:DF 1 "alpha_fp_comparison_operator"
3708 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3710 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3711 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3712 "cmp%-%C1%/ %R2,%R3,%0"
3713 [(set_attr "type" "fadd")
3714 (set_attr "trap" "yes")
3715 (set_attr "trap_suffix" "su")])
3717 (define_insn "*cmpdf_ieee_ext3"
3718 [(set (match_operand:DF 0 "register_operand" "=&f")
3719 (match_operator:DF 1 "alpha_fp_comparison_operator"
3721 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3723 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3724 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3725 "cmp%-%C1%/ %R2,%R3,%0"
3726 [(set_attr "type" "fadd")
3727 (set_attr "trap" "yes")
3728 (set_attr "trap_suffix" "su")])
3730 (define_insn "*cmpdf_ext3"
3731 [(set (match_operand:DF 0 "register_operand" "=f")
3732 (match_operator:DF 1 "alpha_fp_comparison_operator"
3734 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3736 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3737 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3738 "cmp%-%C1%/ %R2,%R3,%0"
3739 [(set_attr "type" "fadd")
3740 (set_attr "trap" "yes")
3741 (set_attr "trap_suffix" "su")])
3743 (define_insn "*movdfcc_internal"
3744 [(set (match_operand:DF 0 "register_operand" "=f,f")
3746 (match_operator 3 "signed_comparison_operator"
3747 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3748 (match_operand:DF 2 "fp0_operand" "G,G")])
3749 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3750 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3754 fcmov%D3 %R4,%R5,%0"
3755 [(set_attr "type" "fcmov")])
3757 (define_insn "*movsfcc_internal"
3758 [(set (match_operand:SF 0 "register_operand" "=f,f")
3760 (match_operator 3 "signed_comparison_operator"
3761 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3762 (match_operand:DF 2 "fp0_operand" "G,G")])
3763 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3764 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3768 fcmov%D3 %R4,%R5,%0"
3769 [(set_attr "type" "fcmov")])
3771 (define_insn "*movdfcc_ext1"
3772 [(set (match_operand:DF 0 "register_operand" "=f,f")
3774 (match_operator 3 "signed_comparison_operator"
3775 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3776 (match_operand:DF 2 "fp0_operand" "G,G")])
3777 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3778 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3782 fcmov%D3 %R4,%R5,%0"
3783 [(set_attr "type" "fcmov")])
3785 (define_insn "*movdfcc_ext2"
3786 [(set (match_operand:DF 0 "register_operand" "=f,f")
3788 (match_operator 3 "signed_comparison_operator"
3790 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3791 (match_operand:DF 2 "fp0_operand" "G,G")])
3792 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3793 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3797 fcmov%D3 %R4,%R5,%0"
3798 [(set_attr "type" "fcmov")])
3800 (define_insn "*movdfcc_ext3"
3801 [(set (match_operand:SF 0 "register_operand" "=f,f")
3803 (match_operator 3 "signed_comparison_operator"
3805 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3806 (match_operand:DF 2 "fp0_operand" "G,G")])
3807 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3808 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3812 fcmov%D3 %R4,%R5,%0"
3813 [(set_attr "type" "fcmov")])
3815 (define_insn "*movdfcc_ext4"
3816 [(set (match_operand:DF 0 "register_operand" "=f,f")
3818 (match_operator 3 "signed_comparison_operator"
3820 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3821 (match_operand:DF 2 "fp0_operand" "G,G")])
3822 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3823 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3827 fcmov%D3 %R4,%R5,%0"
3828 [(set_attr "type" "fcmov")])
3830 (define_expand "maxdf3"
3832 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3833 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3834 (set (match_operand:DF 0 "register_operand" "")
3835 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3836 (match_dup 1) (match_dup 2)))]
3839 operands[3] = gen_reg_rtx (DFmode);
3840 operands[4] = CONST0_RTX (DFmode);
3843 (define_expand "mindf3"
3845 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3846 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3847 (set (match_operand:DF 0 "register_operand" "")
3848 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3849 (match_dup 1) (match_dup 2)))]
3852 operands[3] = gen_reg_rtx (DFmode);
3853 operands[4] = CONST0_RTX (DFmode);
3856 (define_expand "maxsf3"
3858 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3859 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3860 (set (match_operand:SF 0 "register_operand" "")
3861 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3862 (match_dup 1) (match_dup 2)))]
3865 operands[3] = gen_reg_rtx (DFmode);
3866 operands[4] = CONST0_RTX (DFmode);
3869 (define_expand "minsf3"
3871 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3872 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3873 (set (match_operand:SF 0 "register_operand" "")
3874 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3875 (match_dup 1) (match_dup 2)))]
3878 operands[3] = gen_reg_rtx (DFmode);
3879 operands[4] = CONST0_RTX (DFmode);
3882 (define_insn "*fbcc_normal"
3885 (match_operator 1 "signed_comparison_operator"
3886 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3887 (match_operand:DF 3 "fp0_operand" "G")])
3888 (label_ref (match_operand 0 "" ""))
3892 [(set_attr "type" "fbr")])
3894 (define_insn "*fbcc_ext_normal"
3897 (match_operator 1 "signed_comparison_operator"
3899 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3900 (match_operand:DF 3 "fp0_operand" "G")])
3901 (label_ref (match_operand 0 "" ""))
3905 [(set_attr "type" "fbr")])
3907 ;; These are the main define_expand's used to make conditional branches
3910 (define_expand "cmpdf"
3911 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3912 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3915 alpha_compare.op0 = operands[0];
3916 alpha_compare.op1 = operands[1];
3917 alpha_compare.fp_p = 1;
3921 (define_expand "cmptf"
3922 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3923 (match_operand:TF 1 "general_operand" "")))]
3924 "TARGET_HAS_XFLOATING_LIBS"
3926 alpha_compare.op0 = operands[0];
3927 alpha_compare.op1 = operands[1];
3928 alpha_compare.fp_p = 1;
3932 (define_expand "cmpdi"
3933 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3934 (match_operand:DI 1 "general_operand" "")))]
3937 alpha_compare.op0 = operands[0];
3938 alpha_compare.op1 = operands[1];
3939 alpha_compare.fp_p = 0;
3943 (define_expand "beq"
3945 (if_then_else (match_dup 1)
3946 (label_ref (match_operand 0 "" ""))
3949 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3951 (define_expand "bne"
3953 (if_then_else (match_dup 1)
3954 (label_ref (match_operand 0 "" ""))
3957 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3959 (define_expand "blt"
3961 (if_then_else (match_dup 1)
3962 (label_ref (match_operand 0 "" ""))
3965 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3967 (define_expand "ble"
3969 (if_then_else (match_dup 1)
3970 (label_ref (match_operand 0 "" ""))
3973 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3975 (define_expand "bgt"
3977 (if_then_else (match_dup 1)
3978 (label_ref (match_operand 0 "" ""))
3981 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3983 (define_expand "bge"
3985 (if_then_else (match_dup 1)
3986 (label_ref (match_operand 0 "" ""))
3989 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3991 (define_expand "bltu"
3993 (if_then_else (match_dup 1)
3994 (label_ref (match_operand 0 "" ""))
3997 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3999 (define_expand "bleu"
4001 (if_then_else (match_dup 1)
4002 (label_ref (match_operand 0 "" ""))
4005 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4007 (define_expand "bgtu"
4009 (if_then_else (match_dup 1)
4010 (label_ref (match_operand 0 "" ""))
4013 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4015 (define_expand "bgeu"
4017 (if_then_else (match_dup 1)
4018 (label_ref (match_operand 0 "" ""))
4021 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4023 (define_expand "bunordered"
4025 (if_then_else (match_dup 1)
4026 (label_ref (match_operand 0 "" ""))
4029 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4031 (define_expand "bordered"
4033 (if_then_else (match_dup 1)
4034 (label_ref (match_operand 0 "" ""))
4037 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4039 (define_expand "seq"
4040 [(set (match_operand:DI 0 "register_operand" "")
4043 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4045 (define_expand "sne"
4046 [(set (match_operand:DI 0 "register_operand" "")
4049 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4051 (define_expand "slt"
4052 [(set (match_operand:DI 0 "register_operand" "")
4055 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4057 (define_expand "sle"
4058 [(set (match_operand:DI 0 "register_operand" "")
4061 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4063 (define_expand "sgt"
4064 [(set (match_operand:DI 0 "register_operand" "")
4067 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4069 (define_expand "sge"
4070 [(set (match_operand:DI 0 "register_operand" "")
4073 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4075 (define_expand "sltu"
4076 [(set (match_operand:DI 0 "register_operand" "")
4079 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4081 (define_expand "sleu"
4082 [(set (match_operand:DI 0 "register_operand" "")
4085 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4087 (define_expand "sgtu"
4088 [(set (match_operand:DI 0 "register_operand" "")
4091 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4093 (define_expand "sgeu"
4094 [(set (match_operand:DI 0 "register_operand" "")
4097 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4099 (define_expand "sunordered"
4100 [(set (match_operand:DI 0 "register_operand" "")
4103 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4105 (define_expand "sordered"
4106 [(set (match_operand:DI 0 "register_operand" "")
4109 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4111 ;; These are the main define_expand's used to make conditional moves.
4113 (define_expand "movsicc"
4114 [(set (match_operand:SI 0 "register_operand" "")
4115 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4116 (match_operand:SI 2 "reg_or_8bit_operand" "")
4117 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4120 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4124 (define_expand "movdicc"
4125 [(set (match_operand:DI 0 "register_operand" "")
4126 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4127 (match_operand:DI 2 "reg_or_8bit_operand" "")
4128 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4131 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4135 (define_expand "movsfcc"
4136 [(set (match_operand:SF 0 "register_operand" "")
4137 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4138 (match_operand:SF 2 "reg_or_8bit_operand" "")
4139 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4142 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4146 (define_expand "movdfcc"
4147 [(set (match_operand:DF 0 "register_operand" "")
4148 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4149 (match_operand:DF 2 "reg_or_8bit_operand" "")
4150 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4153 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4157 ;; These define_split definitions are used in cases when comparisons have
4158 ;; not be stated in the correct way and we need to reverse the second
4159 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4160 ;; comparison that tests the result being reversed. We have one define_split
4161 ;; for each use of a comparison. They do not match valid insns and need
4162 ;; not generate valid insns.
4164 ;; We can also handle equality comparisons (and inequality comparisons in
4165 ;; cases where the resulting add cannot overflow) by doing an add followed by
4166 ;; a comparison with zero. This is faster since the addition takes one
4167 ;; less cycle than a compare when feeding into a conditional move.
4168 ;; For this case, we also have an SImode pattern since we can merge the add
4169 ;; and sign extend and the order doesn't matter.
4171 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4172 ;; operation could have been generated.
4175 [(set (match_operand:DI 0 "register_operand" "")
4177 (match_operator 1 "comparison_operator"
4178 [(match_operand:DI 2 "reg_or_0_operand" "")
4179 (match_operand:DI 3 "reg_or_cint_operand" "")])
4180 (match_operand:DI 4 "reg_or_cint_operand" "")
4181 (match_operand:DI 5 "reg_or_cint_operand" "")))
4182 (clobber (match_operand:DI 6 "register_operand" ""))]
4183 "operands[3] != const0_rtx"
4184 [(set (match_dup 6) (match_dup 7))
4186 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4188 enum rtx_code code = GET_CODE (operands[1]);
4189 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4191 /* If we are comparing for equality with a constant and that constant
4192 appears in the arm when the register equals the constant, use the
4193 register since that is more likely to match (and to produce better code
4196 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4197 && rtx_equal_p (operands[4], operands[3]))
4198 operands[4] = operands[2];
4200 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4201 && rtx_equal_p (operands[5], operands[3]))
4202 operands[5] = operands[2];
4204 if (code == NE || code == EQ
4205 || (extended_count (operands[2], DImode, unsignedp) >= 1
4206 && extended_count (operands[3], DImode, unsignedp) >= 1))
4208 if (GET_CODE (operands[3]) == CONST_INT)
4209 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4210 GEN_INT (- INTVAL (operands[3])));
4212 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4214 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4217 else if (code == EQ || code == LE || code == LT
4218 || code == LEU || code == LTU)
4220 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4221 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4225 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4226 operands[2], operands[3]);
4227 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4232 [(set (match_operand:DI 0 "register_operand" "")
4234 (match_operator 1 "comparison_operator"
4235 [(match_operand:SI 2 "reg_or_0_operand" "")
4236 (match_operand:SI 3 "reg_or_cint_operand" "")])
4237 (match_operand:DI 4 "reg_or_8bit_operand" "")
4238 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4239 (clobber (match_operand:DI 6 "register_operand" ""))]
4240 "operands[3] != const0_rtx
4241 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4242 [(set (match_dup 6) (match_dup 7))
4244 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4246 enum rtx_code code = GET_CODE (operands[1]);
4247 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4250 if ((code != NE && code != EQ
4251 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4252 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4255 if (GET_CODE (operands[3]) == CONST_INT)
4256 tem = gen_rtx_PLUS (SImode, operands[2],
4257 GEN_INT (- INTVAL (operands[3])));
4259 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4261 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4262 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4263 operands[6], const0_rtx);
4269 (match_operator 1 "comparison_operator"
4270 [(match_operand:DI 2 "reg_or_0_operand" "")
4271 (match_operand:DI 3 "reg_or_cint_operand" "")])
4272 (label_ref (match_operand 0 "" ""))
4274 (clobber (match_operand:DI 4 "register_operand" ""))]
4275 "operands[3] != const0_rtx"
4276 [(set (match_dup 4) (match_dup 5))
4277 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4279 enum rtx_code code = GET_CODE (operands[1]);
4280 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4282 if (code == NE || code == EQ
4283 || (extended_count (operands[2], DImode, unsignedp) >= 1
4284 && extended_count (operands[3], DImode, unsignedp) >= 1))
4286 if (GET_CODE (operands[3]) == CONST_INT)
4287 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4288 GEN_INT (- INTVAL (operands[3])));
4290 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4292 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4295 else if (code == EQ || code == LE || code == LT
4296 || code == LEU || code == LTU)
4298 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4299 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4303 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4304 operands[2], operands[3]);
4305 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4312 (match_operator 1 "comparison_operator"
4313 [(match_operand:SI 2 "reg_or_0_operand" "")
4314 (match_operand:SI 3 "const_int_operand" "")])
4315 (label_ref (match_operand 0 "" ""))
4317 (clobber (match_operand:DI 4 "register_operand" ""))]
4318 "operands[3] != const0_rtx
4319 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4320 [(set (match_dup 4) (match_dup 5))
4321 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4325 if (GET_CODE (operands[3]) == CONST_INT)
4326 tem = gen_rtx_PLUS (SImode, operands[2],
4327 GEN_INT (- INTVAL (operands[3])));
4329 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4331 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4332 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4333 operands[4], const0_rtx);
4336 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4337 ;; This eliminates one, and sometimes two, insns when the AND can be done
4340 [(set (match_operand:DI 0 "register_operand" "")
4341 (match_operator:DI 1 "comparison_operator"
4342 [(match_operand:DI 2 "register_operand" "")
4343 (match_operand:DI 3 "const_int_operand" "")]))
4344 (clobber (match_operand:DI 4 "register_operand" ""))]
4345 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4346 && (GET_CODE (operands[1]) == GTU
4347 || GET_CODE (operands[1]) == LEU
4348 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4349 && extended_count (operands[2], DImode, 1) > 0))"
4350 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4351 (set (match_dup 0) (match_dup 6))]
4353 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4354 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4355 || GET_CODE (operands[1]) == GT)
4357 DImode, operands[4], const0_rtx);
4360 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4363 [(set (match_operand 0 "register_operand" "")
4364 (if_then_else (match_operator 1 "signed_comparison_operator"
4365 [(match_operand:DI 2 "reg_or_0_operand" "")
4367 (match_operand 3 "const_int_operand" "")
4368 (match_operand 4 "const_int_operand" "")))]
4372 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4373 operands[2], operands[3], operands[4]))
4379 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4380 ;; Oh well, we match it in movcc, so it must be partially our fault.
4382 [(set (match_operand 0 "register_operand" "")
4383 (if_then_else (match_operator 1 "signed_comparison_operator"
4385 (match_operand:DI 2 "reg_or_0_operand" "")])
4386 (match_operand 3 "const_int_operand" "")
4387 (match_operand 4 "const_int_operand" "")))]
4391 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4392 operands[0], operands[2], operands[3],
4399 (define_insn_and_split "*cmp_sadd_di"
4400 [(set (match_operand:DI 0 "register_operand" "=r")
4401 (plus:DI (if_then_else:DI
4402 (match_operator 1 "alpha_zero_comparison_operator"
4403 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4405 (match_operand:DI 3 "const48_operand" "I")
4407 (match_operand:DI 4 "sext_add_operand" "rIO")))
4408 (clobber (match_scratch:DI 5 "=r"))]
4411 "! no_new_pseudos || reload_completed"
4413 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4415 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4418 if (! no_new_pseudos)
4419 operands[5] = gen_reg_rtx (DImode);
4420 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4421 operands[5] = operands[0];
4424 (define_insn_and_split "*cmp_sadd_si"
4425 [(set (match_operand:SI 0 "register_operand" "=r")
4426 (plus:SI (if_then_else:SI
4427 (match_operator 1 "alpha_zero_comparison_operator"
4428 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4430 (match_operand:SI 3 "const48_operand" "I")
4432 (match_operand:SI 4 "sext_add_operand" "rIO")))
4433 (clobber (match_scratch:SI 5 "=r"))]
4436 "! no_new_pseudos || reload_completed"
4438 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4440 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4443 if (! no_new_pseudos)
4444 operands[5] = gen_reg_rtx (DImode);
4445 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4446 operands[5] = operands[0];
4449 (define_insn_and_split "*cmp_sadd_sidi"
4450 [(set (match_operand:DI 0 "register_operand" "=r")
4452 (plus:SI (if_then_else:SI
4453 (match_operator 1 "alpha_zero_comparison_operator"
4454 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4456 (match_operand:SI 3 "const48_operand" "I")
4458 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4459 (clobber (match_scratch:SI 5 "=r"))]
4462 "! no_new_pseudos || reload_completed"
4464 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4466 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4469 if (! no_new_pseudos)
4470 operands[5] = gen_reg_rtx (DImode);
4471 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4472 operands[5] = operands[0];
4475 (define_insn_and_split "*cmp_ssub_di"
4476 [(set (match_operand:DI 0 "register_operand" "=r")
4477 (minus:DI (if_then_else:DI
4478 (match_operator 1 "alpha_zero_comparison_operator"
4479 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4481 (match_operand:DI 3 "const48_operand" "I")
4483 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4484 (clobber (match_scratch:DI 5 "=r"))]
4487 "! no_new_pseudos || reload_completed"
4489 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4491 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4494 if (! no_new_pseudos)
4495 operands[5] = gen_reg_rtx (DImode);
4496 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4497 operands[5] = operands[0];
4500 (define_insn_and_split "*cmp_ssub_si"
4501 [(set (match_operand:SI 0 "register_operand" "=r")
4502 (minus:SI (if_then_else:SI
4503 (match_operator 1 "alpha_zero_comparison_operator"
4504 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4506 (match_operand:SI 3 "const48_operand" "I")
4508 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4509 (clobber (match_scratch:SI 5 "=r"))]
4512 "! no_new_pseudos || reload_completed"
4514 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4516 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4519 if (! no_new_pseudos)
4520 operands[5] = gen_reg_rtx (DImode);
4521 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4522 operands[5] = operands[0];
4525 (define_insn_and_split "*cmp_ssub_sidi"
4526 [(set (match_operand:DI 0 "register_operand" "=r")
4528 (minus:SI (if_then_else:SI
4529 (match_operator 1 "alpha_zero_comparison_operator"
4530 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4532 (match_operand:SI 3 "const48_operand" "I")
4534 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4535 (clobber (match_scratch:SI 5 "=r"))]
4538 "! no_new_pseudos || reload_completed"
4540 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4542 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4545 if (! no_new_pseudos)
4546 operands[5] = gen_reg_rtx (DImode);
4547 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4548 operands[5] = operands[0];
4551 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4552 ;; work differently, so we have different patterns for each.
4554 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4555 ;; call. The CIW contains information about arguments passed in registers
4556 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4557 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4558 ;; in the presence of inlining since the CIWs for calls performed by the
4559 ;; inlined function must be stored in the SSIB of the function it is inlined
4560 ;; into as well. We encode the CIW in an unspec and append it to the list
4561 ;; of the CIWs for the current function only when the instruction for loading
4562 ;; $25 is generated.
4564 (define_expand "call"
4565 [(use (match_operand:DI 0 "" ""))
4566 (use (match_operand 1 "" ""))
4567 (use (match_operand 2 "" ""))
4568 (use (match_operand 3 "" ""))]
4571 if (TARGET_ABI_WINDOWS_NT)
4572 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4573 else if (TARGET_ABI_OPEN_VMS)
4574 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4575 else if (TARGET_ABI_UNICOSMK)
4576 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4578 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4582 (define_expand "sibcall"
4583 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4584 (match_operand 1 "" ""))
4585 (use (reg:DI 29))])]
4588 if (GET_CODE (operands[0]) != MEM)
4590 operands[0] = XEXP (operands[0], 0);
4593 (define_expand "call_osf"
4594 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4595 (match_operand 1 "" ""))
4597 (clobber (reg:DI 26))])]
4600 if (GET_CODE (operands[0]) != MEM)
4603 operands[0] = XEXP (operands[0], 0);
4604 if (! call_operand (operands[0], Pmode))
4606 rtx pv = gen_rtx_REG (Pmode, 27);
4607 emit_move_insn (pv, operands[0]);
4612 (define_expand "call_nt"
4613 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4614 (match_operand 1 "" ""))
4615 (clobber (reg:DI 26))])]
4618 if (GET_CODE (operands[0]) != MEM)
4621 operands[0] = XEXP (operands[0], 0);
4622 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4623 operands[0] = force_reg (DImode, operands[0]);
4626 ;; Calls on Unicos/Mk are always indirect.
4627 ;; op 0: symbol ref for called function
4628 ;; op 1: CIW for $25 represented by an unspec
4630 (define_expand "call_umk"
4631 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4632 (match_operand 1 "" ""))
4634 (clobber (reg:DI 26))])]
4637 if (GET_CODE (operands[0]) != MEM)
4640 /* Always load the address of the called function into a register;
4641 load the CIW in $25. */
4643 operands[0] = XEXP (operands[0], 0);
4644 if (GET_CODE (operands[0]) != REG)
4645 operands[0] = force_reg (DImode, operands[0]);
4647 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4651 ;; call openvms/alpha
4652 ;; op 0: symbol ref for called function
4653 ;; op 1: next_arg_reg (argument information value for R25)
4655 (define_expand "call_vms"
4656 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4657 (match_operand 1 "" ""))
4661 (clobber (reg:DI 27))])]
4664 if (GET_CODE (operands[0]) != MEM)
4667 operands[0] = XEXP (operands[0], 0);
4669 /* Always load AI with argument information, then handle symbolic and
4670 indirect call differently. Load RA and set operands[2] to PV in
4673 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4674 if (GET_CODE (operands[0]) == SYMBOL_REF)
4676 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4678 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4680 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4684 emit_move_insn (gen_rtx_REG (Pmode, 26),
4685 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4686 operands[2] = operands[0];
4691 (define_expand "call_value"
4692 [(use (match_operand 0 "" ""))
4693 (use (match_operand:DI 1 "" ""))
4694 (use (match_operand 2 "" ""))
4695 (use (match_operand 3 "" ""))
4696 (use (match_operand 4 "" ""))]
4699 if (TARGET_ABI_WINDOWS_NT)
4700 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4701 else if (TARGET_ABI_OPEN_VMS)
4702 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4704 else if (TARGET_ABI_UNICOSMK)
4705 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4708 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4713 (define_expand "sibcall_value"
4714 [(parallel [(set (match_operand 0 "" "")
4715 (call (mem:DI (match_operand 1 "" ""))
4716 (match_operand 2 "" "")))
4717 (use (reg:DI 29))])]
4720 if (GET_CODE (operands[1]) != MEM)
4722 operands[1] = XEXP (operands[1], 0);
4725 (define_expand "call_value_osf"
4726 [(parallel [(set (match_operand 0 "" "")
4727 (call (mem:DI (match_operand 1 "" ""))
4728 (match_operand 2 "" "")))
4730 (clobber (reg:DI 26))])]
4733 if (GET_CODE (operands[1]) != MEM)
4736 operands[1] = XEXP (operands[1], 0);
4737 if (! call_operand (operands[1], Pmode))
4739 rtx pv = gen_rtx_REG (Pmode, 27);
4740 emit_move_insn (pv, operands[1]);
4745 (define_expand "call_value_nt"
4746 [(parallel [(set (match_operand 0 "" "")
4747 (call (mem:DI (match_operand 1 "" ""))
4748 (match_operand 2 "" "")))
4749 (clobber (reg:DI 26))])]
4752 if (GET_CODE (operands[1]) != MEM)
4755 operands[1] = XEXP (operands[1], 0);
4756 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4757 operands[1] = force_reg (DImode, operands[1]);
4760 (define_expand "call_value_vms"
4761 [(parallel [(set (match_operand 0 "" "")
4762 (call (mem:DI (match_operand:DI 1 "" ""))
4763 (match_operand 2 "" "")))
4767 (clobber (reg:DI 27))])]
4770 if (GET_CODE (operands[1]) != MEM)
4773 operands[1] = XEXP (operands[1], 0);
4775 /* Always load AI with argument information, then handle symbolic and
4776 indirect call differently. Load RA and set operands[3] to PV in
4779 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4780 if (GET_CODE (operands[1]) == SYMBOL_REF)
4782 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4784 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4786 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4790 emit_move_insn (gen_rtx_REG (Pmode, 26),
4791 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4792 operands[3] = operands[1];
4796 (define_expand "call_value_umk"
4797 [(parallel [(set (match_operand 0 "" "")
4798 (call (mem:DI (match_operand 1 "" ""))
4799 (match_operand 2 "" "")))
4801 (clobber (reg:DI 26))])]
4804 if (GET_CODE (operands[1]) != MEM)
4807 operands[1] = XEXP (operands[1], 0);
4808 if (GET_CODE (operands[1]) != REG)
4809 operands[1] = force_reg (DImode, operands[1]);
4811 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4814 (define_insn "*call_osf_1_er"
4815 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4816 (match_operand 1 "" ""))
4818 (clobber (reg:DI 26))]
4819 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4821 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4823 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4824 [(set_attr "type" "jsr")
4825 (set_attr "length" "12,*,16")])
4827 ;; We must use peep2 instead of a split because we need accurate life
4828 ;; information for $gp. Consider the case of { bar(); while (1); }.
4830 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4831 (match_operand 1 "" ""))
4833 (clobber (reg:DI 26))])]
4834 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4835 && ! current_file_function_operand (operands[0], Pmode)
4836 && peep2_regno_dead_p (1, 29)"
4837 [(parallel [(call (mem:DI (match_dup 2))
4839 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4840 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4841 (use (match_dup 0))])]
4843 if (CONSTANT_P (operands[0]))
4845 operands[2] = gen_rtx_REG (Pmode, 27);
4846 emit_move_insn (operands[2], operands[0]);
4850 operands[2] = operands[0];
4851 operands[0] = const0_rtx;
4856 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4857 (match_operand 1 "" ""))
4859 (clobber (reg:DI 26))])]
4860 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4861 && ! current_file_function_operand (operands[0], Pmode)
4862 && ! peep2_regno_dead_p (1, 29)"
4863 [(parallel [(call (mem:DI (match_dup 2))
4865 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4866 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4867 (use (match_dup 0))])
4869 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4871 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4873 if (CONSTANT_P (operands[0]))
4875 operands[2] = gen_rtx_REG (Pmode, 27);
4876 emit_move_insn (operands[2], operands[0]);
4880 operands[2] = operands[0];
4881 operands[0] = const0_rtx;
4883 operands[3] = GEN_INT (alpha_next_sequence_number++);
4886 ;; We add a blockage unspec_volatile to prevent insns from moving down
4887 ;; from above the call to in between the call and the ldah gpdisp.
4889 (define_insn "*call_osf_2_er"
4890 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4891 (match_operand 1 "" ""))
4892 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4893 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4894 (use (match_operand 2 "" ""))]
4895 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4897 [(set_attr "type" "jsr")])
4899 (define_insn "*call_osf_1_noreturn"
4900 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4901 (match_operand 1 "" ""))
4903 (clobber (reg:DI 26))]
4904 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4905 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4910 [(set_attr "type" "jsr")
4911 (set_attr "length" "*,*,8")])
4913 (define_insn "*call_osf_1"
4914 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4915 (match_operand 1 "" ""))
4917 (clobber (reg:DI 26))]
4918 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4920 jsr $26,($27),0\;ldgp $29,0($26)
4922 jsr $26,%0\;ldgp $29,0($26)"
4923 [(set_attr "type" "jsr")
4924 (set_attr "length" "12,*,16")])
4926 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4927 ;; doesn't do what we want.
4928 (define_insn "*sibcall_osf_1"
4929 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4930 (match_operand 1 "" ""))
4935 lda $27,%0\;jmp $31,($27),%0"
4936 [(set_attr "type" "jsr")
4937 (set_attr "length" "*,8")])
4939 (define_insn "*call_nt_1"
4940 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4941 (match_operand 1 "" ""))
4942 (clobber (reg:DI 26))]
4943 "TARGET_ABI_WINDOWS_NT"
4948 [(set_attr "type" "jsr")
4949 (set_attr "length" "*,*,12")])
4951 (define_insn "*call_vms_1"
4952 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4953 (match_operand 1 "" ""))
4954 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4957 (clobber (reg:DI 27))]
4958 "TARGET_ABI_OPEN_VMS"
4960 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4961 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4962 [(set_attr "type" "jsr")
4963 (set_attr "length" "12,16")])
4965 (define_insn "*call_umk_1"
4966 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4967 (match_operand 1 "" ""))
4969 (clobber (reg:DI 26))]
4970 "TARGET_ABI_UNICOSMK"
4972 [(set_attr "type" "jsr")])
4974 ;; Call subroutine returning any type.
4976 (define_expand "untyped_call"
4977 [(parallel [(call (match_operand 0 "" "")
4979 (match_operand 1 "" "")
4980 (match_operand 2 "" "")])]
4985 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4987 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4989 rtx set = XVECEXP (operands[2], 0, i);
4990 emit_move_insn (SET_DEST (set), SET_SRC (set));
4993 /* The optimizer does not know that the call sets the function value
4994 registers we stored in the result block. We avoid problems by
4995 claiming that all hard registers are used and clobbered at this
4997 emit_insn (gen_blockage ());
5002 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5003 ;; all of memory. This blocks insns from being moved across this point.
5005 (define_insn "blockage"
5006 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5009 [(set_attr "length" "0")])
5013 (label_ref (match_operand 0 "" "")))]
5016 [(set_attr "type" "ibr")])
5018 (define_expand "return"
5023 (define_insn "*return_internal"
5027 [(set_attr "type" "ibr")])
5029 (define_insn "indirect_jump"
5030 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
5033 [(set_attr "type" "ibr")])
5035 (define_expand "tablejump"
5036 [(parallel [(set (pc)
5037 (match_operand 0 "register_operand" ""))
5038 (use (label_ref:DI (match_operand 1 "" "")))])]
5041 if (TARGET_ABI_WINDOWS_NT)
5043 rtx dest = gen_reg_rtx (DImode);
5044 emit_insn (gen_extendsidi2 (dest, operands[0]));
5047 else if (TARGET_ABI_OSF)
5049 rtx dest = gen_reg_rtx (DImode);
5050 emit_insn (gen_extendsidi2 (dest, operands[0]));
5051 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
5056 (define_insn "*tablejump_osf_nt_internal"
5058 (match_operand:DI 0 "register_operand" "r"))
5059 (use (label_ref:DI (match_operand 1 "" "")))]
5060 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5061 && alpha_tablejump_addr_vec (insn)"
5063 operands[2] = alpha_tablejump_best_label (insn);
5064 return "jmp $31,(%0),%2";
5066 [(set_attr "type" "ibr")])
5068 (define_insn "*tablejump_internal"
5070 (match_operand:DI 0 "register_operand" "r"))
5071 (use (label_ref (match_operand 1 "" "")))]
5074 [(set_attr "type" "ibr")])
5076 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5077 ;; want to have to include pal.h in our .s file.
5079 ;; Technically the type for call_pal is jsr, but we use that for determining
5080 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5083 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5086 [(set_attr "type" "ibr")])
5088 ;; Finally, we have the basic data motion insns. The byte and word insns
5089 ;; are done via define_expand. Start with the floating-point insns, since
5090 ;; they are simpler.
5092 (define_insn "*movsf_nofix"
5093 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5094 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5095 "TARGET_FPREGS && ! TARGET_FIX
5096 && (register_operand (operands[0], SFmode)
5097 || reg_or_fp0_operand (operands[1], SFmode))"
5105 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5107 (define_insn "*movsf_fix"
5108 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5109 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5110 "TARGET_FPREGS && TARGET_FIX
5111 && (register_operand (operands[0], SFmode)
5112 || reg_or_fp0_operand (operands[1], SFmode))"
5122 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5124 (define_insn "*movsf_nofp"
5125 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5126 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5128 && (register_operand (operands[0], SFmode)
5129 || reg_or_fp0_operand (operands[1], SFmode))"
5134 [(set_attr "type" "ilog,ild,ist")])
5136 (define_insn "*movdf_nofix"
5137 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5138 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5139 "TARGET_FPREGS && ! TARGET_FIX
5140 && (register_operand (operands[0], DFmode)
5141 || reg_or_fp0_operand (operands[1], DFmode))"
5149 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5151 (define_insn "*movdf_fix"
5152 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5153 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5154 "TARGET_FPREGS && TARGET_FIX
5155 && (register_operand (operands[0], DFmode)
5156 || reg_or_fp0_operand (operands[1], DFmode))"
5166 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5168 (define_insn "*movdf_nofp"
5169 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5170 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5172 && (register_operand (operands[0], DFmode)
5173 || reg_or_fp0_operand (operands[1], DFmode))"
5178 [(set_attr "type" "ilog,ild,ist")])
5180 ;; Subregs suck for register allocation. Pretend we can move TFmode
5181 ;; data between general registers until after reload.
5183 (define_insn_and_split "*movtf_internal"
5184 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5185 (match_operand:TF 1 "input_operand" "roG,rG"))]
5186 "register_operand (operands[0], TFmode)
5187 || reg_or_fp0_operand (operands[1], TFmode)"
5190 [(set (match_dup 0) (match_dup 2))
5191 (set (match_dup 1) (match_dup 3))]
5193 alpha_split_tfmode_pair (operands);
5194 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5197 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5198 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5202 (define_expand "movsf"
5203 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5204 (match_operand:SF 1 "general_operand" ""))]
5207 if (GET_CODE (operands[0]) == MEM
5208 && ! reg_or_fp0_operand (operands[1], SFmode))
5209 operands[1] = force_reg (SFmode, operands[1]);
5212 (define_expand "movdf"
5213 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5214 (match_operand:DF 1 "general_operand" ""))]
5217 if (GET_CODE (operands[0]) == MEM
5218 && ! reg_or_fp0_operand (operands[1], DFmode))
5219 operands[1] = force_reg (DFmode, operands[1]);
5222 (define_expand "movtf"
5223 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5224 (match_operand:TF 1 "general_operand" ""))]
5227 if (GET_CODE (operands[0]) == MEM
5228 && ! reg_or_fp0_operand (operands[1], TFmode))
5229 operands[1] = force_reg (TFmode, operands[1]);
5232 (define_insn "*movsi_nofix"
5233 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5234 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5235 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5236 && (register_operand (operands[0], SImode)
5237 || reg_or_0_operand (operands[1], SImode))"
5247 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5249 (define_insn "*movsi_fix"
5250 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5251 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5252 "TARGET_ABI_OSF && TARGET_FIX
5253 && (register_operand (operands[0], SImode)
5254 || reg_or_0_operand (operands[1], SImode))"
5266 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5268 (define_insn "*movsi_nt_vms"
5269 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5270 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5271 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5272 && (register_operand (operands[0], SImode)
5273 || reg_or_0_operand (operands[1], SImode))"
5284 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5286 (define_insn "*movhi_nobwx"
5287 [(set (match_operand:HI 0 "register_operand" "=r,r")
5288 (match_operand:HI 1 "input_operand" "rJ,n"))]
5290 && (register_operand (operands[0], HImode)
5291 || register_operand (operands[1], HImode))"
5295 [(set_attr "type" "ilog,iadd")])
5297 (define_insn "*movhi_bwx"
5298 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5299 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5301 && (register_operand (operands[0], HImode)
5302 || reg_or_0_operand (operands[1], HImode))"
5308 [(set_attr "type" "ilog,iadd,ild,ist")])
5310 (define_insn "*movqi_nobwx"
5311 [(set (match_operand:QI 0 "register_operand" "=r,r")
5312 (match_operand:QI 1 "input_operand" "rJ,n"))]
5314 && (register_operand (operands[0], QImode)
5315 || register_operand (operands[1], QImode))"
5319 [(set_attr "type" "ilog,iadd")])
5321 (define_insn "*movqi_bwx"
5322 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5323 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5325 && (register_operand (operands[0], QImode)
5326 || reg_or_0_operand (operands[1], QImode))"
5332 [(set_attr "type" "ilog,iadd,ild,ist")])
5334 ;; We do two major things here: handle mem->mem and construct long
5337 (define_expand "movsi"
5338 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5339 (match_operand:SI 1 "general_operand" ""))]
5342 if (alpha_expand_mov (SImode, operands))
5346 ;; Split a load of a large constant into the appropriate two-insn
5350 [(set (match_operand:SI 0 "register_operand" "")
5351 (match_operand:SI 1 "const_int_operand" ""))]
5352 "! add_operand (operands[1], SImode)"
5353 [(set (match_dup 0) (match_dup 2))
5354 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5357 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5359 if (tem == operands[0])
5365 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5366 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5367 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5368 ;; notes and update LABEL_NUSES because this is not done automatically.
5369 ;; Labels may be incorrectly deleted if we don't do this.
5371 ;; Describing what the individual instructions do correctly is too complicated
5372 ;; so use UNSPECs for each of the three parts of an address.
5375 [(set (match_operand:DI 0 "register_operand" "")
5376 (match_operand:DI 1 "symbolic_operand" ""))]
5377 "TARGET_ABI_UNICOSMK && reload_completed"
5380 rtx insn1, insn2, insn3;
5382 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5383 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5384 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5385 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5386 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5388 if (GET_CODE (operands[1]) == LABEL_REF)
5392 label = XEXP (operands[1], 0);
5393 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5395 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5397 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5399 LABEL_NUSES (label) += 3;
5404 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5406 (define_insn "umk_laum"
5407 [(set (match_operand:DI 0 "register_operand" "=r")
5408 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5410 "TARGET_ABI_UNICOSMK"
5412 [(set_attr "type" "iadd")])
5414 (define_insn "umk_lalm"
5415 [(set (match_operand:DI 0 "register_operand" "=r")
5416 (plus:DI (match_operand:DI 1 "register_operand" "r")
5417 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5419 "TARGET_ABI_UNICOSMK"
5421 [(set_attr "type" "iadd")])
5423 (define_insn "umk_lal"
5424 [(set (match_operand:DI 0 "register_operand" "=r")
5425 (plus:DI (match_operand:DI 1 "register_operand" "r")
5426 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5428 "TARGET_ABI_UNICOSMK"
5430 [(set_attr "type" "iadd")])
5432 ;; Add a new call information word to the current function's list of CIWs
5433 ;; and load its index into $25. Doing it here ensures that the CIW will be
5434 ;; associated with the correct function even in the presence of inlining.
5436 (define_insn "*umk_load_ciw"
5438 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5439 "TARGET_ABI_UNICOSMK"
5441 operands[0] = unicosmk_add_call_info_word (operands[0]);
5442 return "lda $25,%0";
5444 [(set_attr "type" "iadd")])
5446 (define_insn "*movdi_er_low_l"
5447 [(set (match_operand:DI 0 "register_operand" "=r")
5448 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5449 (match_operand:DI 2 "local_symbolic_operand" "")))]
5450 "TARGET_EXPLICIT_RELOCS"
5452 if (true_regnum (operands[1]) == 29)
5453 return "lda %0,%2(%1)\t\t!gprel";
5455 return "lda %0,%2(%1)\t\t!gprellow";
5458 (define_insn "movdi_er_high_g"
5459 [(set (match_operand:DI 0 "register_operand" "=r")
5460 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5461 (match_operand:DI 2 "global_symbolic_operand" "")
5462 (match_operand 3 "const_int_operand" "")]
5464 "TARGET_EXPLICIT_RELOCS"
5465 "ldq %0,%2(%1)\t\t!literal"
5466 [(set_attr "type" "ldsym")])
5468 (define_insn "*movdi_er_nofix"
5469 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
5470 (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f"))]
5471 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5472 && (register_operand (operands[0], DImode)
5473 || reg_or_0_operand (operands[1], DImode))"
5484 [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst")])
5486 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5487 ;; have been split up by the rules above but we shouldn't reject the
5488 ;; possibility of them getting through.
5490 (define_insn "*movdi_nofix"
5491 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5492 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5494 && (register_operand (operands[0], DImode)
5495 || reg_or_0_operand (operands[1], DImode))"
5500 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5507 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5508 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5510 (define_insn "*movdi_er_fix"
5511 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5512 (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f,*f,r"))]
5513 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5514 && (register_operand (operands[0], DImode)
5515 || reg_or_0_operand (operands[1], DImode))"
5528 [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5530 (define_insn "*movdi_fix"
5531 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5532 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5533 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5534 && (register_operand (operands[0], DImode)
5535 || reg_or_0_operand (operands[1], DImode))"
5548 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5550 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5551 ;; often appears dead to the life analysis code, at which point we
5552 ;; abort for emitting dead prologue instructions. Force this live.
5554 (define_insn "force_movdi"
5555 [(set (match_operand:DI 0 "register_operand" "=r")
5556 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5557 UNSPECV_FORCE_MOV))]
5560 [(set_attr "type" "ilog")])
5562 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5563 ;; memory, and construct long 32-bit constants.
5565 (define_expand "movdi"
5566 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5567 (match_operand:DI 1 "general_operand" ""))]
5570 if (alpha_expand_mov (DImode, operands))
5574 ;; Split a load of a large constant into the appropriate two-insn
5578 [(set (match_operand:DI 0 "register_operand" "")
5579 (match_operand:DI 1 "const_int_operand" ""))]
5580 "! add_operand (operands[1], DImode)"
5581 [(set (match_dup 0) (match_dup 2))
5582 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5585 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5587 if (tem == operands[0])
5593 ;; These are the partial-word cases.
5595 ;; First we have the code to load an aligned word. Operand 0 is the register
5596 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5597 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5598 ;; number of bits within the word that the value is. Operand 3 is an SImode
5599 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5600 ;; same register. It is allowed to conflict with operand 1 as well.
5602 (define_expand "aligned_loadqi"
5603 [(set (match_operand:SI 3 "register_operand" "")
5604 (match_operand:SI 1 "memory_operand" ""))
5605 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5606 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5608 (match_operand:DI 2 "const_int_operand" "")))]
5613 (define_expand "aligned_loadhi"
5614 [(set (match_operand:SI 3 "register_operand" "")
5615 (match_operand:SI 1 "memory_operand" ""))
5616 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5617 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5619 (match_operand:DI 2 "const_int_operand" "")))]
5624 ;; Similar for unaligned loads, where we use the sequence from the
5625 ;; Alpha Architecture manual. We have to distinguish between little-endian
5626 ;; and big-endian systems as the sequences are different.
5628 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5629 ;; operand 3 can overlap the input and output registers.
5631 (define_expand "unaligned_loadqi"
5632 [(use (match_operand:QI 0 "register_operand" ""))
5633 (use (match_operand:DI 1 "address_operand" ""))
5634 (use (match_operand:DI 2 "register_operand" ""))
5635 (use (match_operand:DI 3 "register_operand" ""))]
5638 if (WORDS_BIG_ENDIAN)
5639 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5640 operands[2], operands[3]));
5642 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5643 operands[2], operands[3]));
5647 (define_expand "unaligned_loadqi_le"
5648 [(set (match_operand:DI 2 "register_operand" "")
5649 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5651 (set (match_operand:DI 3 "register_operand" "")
5653 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5654 (zero_extract:DI (match_dup 2)
5656 (ashift:DI (match_dup 3) (const_int 3))))]
5657 "! WORDS_BIG_ENDIAN"
5660 (define_expand "unaligned_loadqi_be"
5661 [(set (match_operand:DI 2 "register_operand" "")
5662 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5664 (set (match_operand:DI 3 "register_operand" "")
5666 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5667 (zero_extract:DI (match_dup 2)
5671 (ashift:DI (match_dup 3) (const_int 3)))))]
5675 (define_expand "unaligned_loadhi"
5676 [(use (match_operand:QI 0 "register_operand" ""))
5677 (use (match_operand:DI 1 "address_operand" ""))
5678 (use (match_operand:DI 2 "register_operand" ""))
5679 (use (match_operand:DI 3 "register_operand" ""))]
5682 if (WORDS_BIG_ENDIAN)
5683 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5684 operands[2], operands[3]));
5686 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5687 operands[2], operands[3]));
5691 (define_expand "unaligned_loadhi_le"
5692 [(set (match_operand:DI 2 "register_operand" "")
5693 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5695 (set (match_operand:DI 3 "register_operand" "")
5697 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5698 (zero_extract:DI (match_dup 2)
5700 (ashift:DI (match_dup 3) (const_int 3))))]
5701 "! WORDS_BIG_ENDIAN"
5704 (define_expand "unaligned_loadhi_be"
5705 [(set (match_operand:DI 2 "register_operand" "")
5706 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5708 (set (match_operand:DI 3 "register_operand" "")
5709 (plus:DI (match_dup 1) (const_int 1)))
5710 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5711 (zero_extract:DI (match_dup 2)
5715 (ashift:DI (match_dup 3) (const_int 3)))))]
5719 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5720 ;; aligned SImode MEM. Operand 1 is the register containing the
5721 ;; byte or word to store. Operand 2 is the number of bits within the word that
5722 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5724 (define_expand "aligned_store"
5725 [(set (match_operand:SI 3 "register_operand" "")
5726 (match_operand:SI 0 "memory_operand" ""))
5727 (set (subreg:DI (match_dup 3) 0)
5728 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5729 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5730 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5731 (match_operand:DI 2 "const_int_operand" "")))
5732 (set (subreg:DI (match_dup 4) 0)
5733 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5734 (set (match_dup 0) (match_dup 4))]
5737 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5738 << INTVAL (operands[2])));
5741 ;; For the unaligned byte and halfword cases, we use code similar to that
5742 ;; in the ;; Architecture book, but reordered to lower the number of registers
5743 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5744 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5745 ;; be the same temporary, if desired. If the address is in a register,
5746 ;; operand 2 can be that register.
5748 (define_expand "unaligned_storeqi"
5749 [(use (match_operand:DI 0 "address_operand" ""))
5750 (use (match_operand:QI 1 "register_operand" ""))
5751 (use (match_operand:DI 2 "register_operand" ""))
5752 (use (match_operand:DI 3 "register_operand" ""))
5753 (use (match_operand:DI 4 "register_operand" ""))]
5756 if (WORDS_BIG_ENDIAN)
5757 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5758 operands[2], operands[3],
5761 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5762 operands[2], operands[3],
5767 (define_expand "unaligned_storeqi_le"
5768 [(set (match_operand:DI 3 "register_operand" "")
5769 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5771 (set (match_operand:DI 2 "register_operand" "")
5774 (and:DI (not:DI (ashift:DI (const_int 255)
5775 (ashift:DI (match_dup 2) (const_int 3))))
5777 (set (match_operand:DI 4 "register_operand" "")
5778 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5779 (ashift:DI (match_dup 2) (const_int 3))))
5780 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5781 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5783 "! WORDS_BIG_ENDIAN"
5786 (define_expand "unaligned_storeqi_be"
5787 [(set (match_operand:DI 3 "register_operand" "")
5788 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5790 (set (match_operand:DI 2 "register_operand" "")
5793 (and:DI (not:DI (ashift:DI (const_int 255)
5794 (minus:DI (const_int 56)
5795 (ashift:DI (match_dup 2) (const_int 3)))))
5797 (set (match_operand:DI 4 "register_operand" "")
5798 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5799 (minus:DI (const_int 56)
5800 (ashift:DI (match_dup 2) (const_int 3)))))
5801 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5802 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5807 (define_expand "unaligned_storehi"
5808 [(use (match_operand:DI 0 "address_operand" ""))
5809 (use (match_operand:HI 1 "register_operand" ""))
5810 (use (match_operand:DI 2 "register_operand" ""))
5811 (use (match_operand:DI 3 "register_operand" ""))
5812 (use (match_operand:DI 4 "register_operand" ""))]
5815 if (WORDS_BIG_ENDIAN)
5816 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5817 operands[2], operands[3],
5820 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5821 operands[2], operands[3],
5826 (define_expand "unaligned_storehi_le"
5827 [(set (match_operand:DI 3 "register_operand" "")
5828 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5830 (set (match_operand:DI 2 "register_operand" "")
5833 (and:DI (not:DI (ashift:DI (const_int 65535)
5834 (ashift:DI (match_dup 2) (const_int 3))))
5836 (set (match_operand:DI 4 "register_operand" "")
5837 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5838 (ashift:DI (match_dup 2) (const_int 3))))
5839 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5840 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5842 "! WORDS_BIG_ENDIAN"
5845 (define_expand "unaligned_storehi_be"
5846 [(set (match_operand:DI 3 "register_operand" "")
5847 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5849 (set (match_operand:DI 2 "register_operand" "")
5850 (plus:DI (match_dup 0) (const_int 1)))
5852 (and:DI (not:DI (ashift:DI
5854 (minus:DI (const_int 56)
5855 (ashift:DI (match_dup 2) (const_int 3)))))
5857 (set (match_operand:DI 4 "register_operand" "")
5858 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5859 (minus:DI (const_int 56)
5860 (ashift:DI (match_dup 2) (const_int 3)))))
5861 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5862 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5867 ;; Here are the define_expand's for QI and HI moves that use the above
5868 ;; patterns. We have the normal sets, plus the ones that need scratch
5869 ;; registers for reload.
5871 (define_expand "movqi"
5872 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5873 (match_operand:QI 1 "general_operand" ""))]
5877 ? alpha_expand_mov (QImode, operands)
5878 : alpha_expand_mov_nobwx (QImode, operands))
5882 (define_expand "movhi"
5883 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5884 (match_operand:HI 1 "general_operand" ""))]
5888 ? alpha_expand_mov (HImode, operands)
5889 : alpha_expand_mov_nobwx (HImode, operands))
5893 ;; Here are the versions for reload. Note that in the unaligned cases
5894 ;; we know that the operand must not be a pseudo-register because stack
5895 ;; slots are always aligned references.
5897 (define_expand "reload_inqi"
5898 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5899 (match_operand:QI 1 "any_memory_operand" "m")
5900 (match_operand:TI 2 "register_operand" "=&r")])]
5905 if (GET_CODE (operands[1]) != MEM)
5908 if (aligned_memory_operand (operands[1], QImode))
5910 seq = gen_reload_inqi_help (operands[0], operands[1],
5911 gen_rtx_REG (SImode, REGNO (operands[2])));
5917 /* It is possible that one of the registers we got for operands[2]
5918 might coincide with that of operands[0] (which is why we made
5919 it TImode). Pick the other one to use as our scratch. */
5920 if (REGNO (operands[0]) == REGNO (operands[2]))
5921 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5923 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5925 addr = get_unaligned_address (operands[1], 0);
5926 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5927 gen_rtx_REG (DImode, REGNO (operands[0])));
5928 alpha_set_memflags (seq, operands[1]);
5934 (define_expand "reload_inhi"
5935 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5936 (match_operand:HI 1 "any_memory_operand" "m")
5937 (match_operand:TI 2 "register_operand" "=&r")])]
5942 if (GET_CODE (operands[1]) != MEM)
5945 if (aligned_memory_operand (operands[1], HImode))
5947 seq = gen_reload_inhi_help (operands[0], operands[1],
5948 gen_rtx_REG (SImode, REGNO (operands[2])));
5954 /* It is possible that one of the registers we got for operands[2]
5955 might coincide with that of operands[0] (which is why we made
5956 it TImode). Pick the other one to use as our scratch. */
5957 if (REGNO (operands[0]) == REGNO (operands[2]))
5958 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5960 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5962 addr = get_unaligned_address (operands[1], 0);
5963 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5964 gen_rtx_REG (DImode, REGNO (operands[0])));
5965 alpha_set_memflags (seq, operands[1]);
5971 (define_expand "reload_outqi"
5972 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5973 (match_operand:QI 1 "register_operand" "r")
5974 (match_operand:TI 2 "register_operand" "=&r")])]
5977 if (GET_CODE (operands[0]) != MEM)
5980 if (aligned_memory_operand (operands[0], QImode))
5982 emit_insn (gen_reload_outqi_help
5983 (operands[0], operands[1],
5984 gen_rtx_REG (SImode, REGNO (operands[2])),
5985 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5989 rtx addr = get_unaligned_address (operands[0], 0);
5990 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5991 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5992 rtx scratch3 = scratch1;
5995 if (GET_CODE (addr) == REG)
5998 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5999 scratch2, scratch3);
6000 alpha_set_memflags (seq, operands[0]);
6006 (define_expand "reload_outhi"
6007 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6008 (match_operand:HI 1 "register_operand" "r")
6009 (match_operand:TI 2 "register_operand" "=&r")])]
6012 if (GET_CODE (operands[0]) != MEM)
6015 if (aligned_memory_operand (operands[0], HImode))
6017 emit_insn (gen_reload_outhi_help
6018 (operands[0], operands[1],
6019 gen_rtx_REG (SImode, REGNO (operands[2])),
6020 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6024 rtx addr = get_unaligned_address (operands[0], 0);
6025 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6026 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6027 rtx scratch3 = scratch1;
6030 if (GET_CODE (addr) == REG)
6033 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6034 scratch2, scratch3);
6035 alpha_set_memflags (seq, operands[0]);
6041 ;; Helpers for the above. The way reload is structured, we can't
6042 ;; always get a proper address for a stack slot during reload_foo
6043 ;; expansion, so we must delay our address manipulations until after.
6045 (define_insn "reload_inqi_help"
6046 [(set (match_operand:QI 0 "register_operand" "=r")
6047 (match_operand:QI 1 "memory_operand" "m"))
6048 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6049 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6052 (define_insn "reload_inhi_help"
6053 [(set (match_operand:HI 0 "register_operand" "=r")
6054 (match_operand:HI 1 "memory_operand" "m"))
6055 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6056 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6059 (define_insn "reload_outqi_help"
6060 [(set (match_operand:QI 0 "memory_operand" "=m")
6061 (match_operand:QI 1 "register_operand" "r"))
6062 (clobber (match_operand:SI 2 "register_operand" "=r"))
6063 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6064 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6067 (define_insn "reload_outhi_help"
6068 [(set (match_operand:HI 0 "memory_operand" "=m")
6069 (match_operand:HI 1 "register_operand" "r"))
6070 (clobber (match_operand:SI 2 "register_operand" "=r"))
6071 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6072 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6076 [(set (match_operand:QI 0 "register_operand" "")
6077 (match_operand:QI 1 "memory_operand" ""))
6078 (clobber (match_operand:SI 2 "register_operand" ""))]
6079 "! TARGET_BWX && reload_completed"
6082 rtx aligned_mem, bitnum;
6083 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6085 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6091 [(set (match_operand:HI 0 "register_operand" "")
6092 (match_operand:HI 1 "memory_operand" ""))
6093 (clobber (match_operand:SI 2 "register_operand" ""))]
6094 "! TARGET_BWX && reload_completed"
6097 rtx aligned_mem, bitnum;
6098 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6100 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6106 [(set (match_operand:QI 0 "memory_operand" "")
6107 (match_operand:QI 1 "register_operand" ""))
6108 (clobber (match_operand:SI 2 "register_operand" ""))
6109 (clobber (match_operand:SI 3 "register_operand" ""))]
6110 "! TARGET_BWX && reload_completed"
6113 rtx aligned_mem, bitnum;
6114 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6115 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6116 operands[2], operands[3]));
6121 [(set (match_operand:HI 0 "memory_operand" "")
6122 (match_operand:HI 1 "register_operand" ""))
6123 (clobber (match_operand:SI 2 "register_operand" ""))
6124 (clobber (match_operand:SI 3 "register_operand" ""))]
6125 "! TARGET_BWX && reload_completed"
6128 rtx aligned_mem, bitnum;
6129 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6130 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6131 operands[2], operands[3]));
6135 ;; Bit field extract patterns which use ext[wlq][lh]
6137 (define_expand "extv"
6138 [(set (match_operand:DI 0 "register_operand" "")
6139 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6140 (match_operand:DI 2 "immediate_operand" "")
6141 (match_operand:DI 3 "immediate_operand" "")))]
6146 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6147 if (INTVAL (operands[3]) % 8 != 0
6148 || (INTVAL (operands[2]) != 16
6149 && INTVAL (operands[2]) != 32
6150 && INTVAL (operands[2]) != 64))
6153 /* From mips.md: extract_bit_field doesn't verify that our source
6154 matches the predicate, so we force it to be a MEM here. */
6155 if (GET_CODE (operands[1]) != MEM)
6158 /* The bit number is relative to the mode of operand 1 which is
6159 usually QImode (this might actually be a bug in expmed.c). Note
6160 that the bit number is negative in big-endian mode in this case.
6161 We have to convert that to the offset. */
6162 if (WORDS_BIG_ENDIAN)
6163 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6164 - INTVAL (operands[2]) - INTVAL (operands[3]);
6166 ofs = INTVAL (operands[3]);
6170 alpha_expand_unaligned_load (operands[0], operands[1],
6171 INTVAL (operands[2]) / 8,
6176 (define_expand "extzv"
6177 [(set (match_operand:DI 0 "register_operand" "")
6178 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6179 (match_operand:DI 2 "immediate_operand" "")
6180 (match_operand:DI 3 "immediate_operand" "")))]
6183 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6184 if (INTVAL (operands[3]) % 8 != 0
6185 || (INTVAL (operands[2]) != 8
6186 && INTVAL (operands[2]) != 16
6187 && INTVAL (operands[2]) != 32
6188 && INTVAL (operands[2]) != 64))
6191 if (GET_CODE (operands[1]) == MEM)
6195 /* Fail 8 bit fields, falling back on a simple byte load. */
6196 if (INTVAL (operands[2]) == 8)
6199 /* The bit number is relative to the mode of operand 1 which is
6200 usually QImode (this might actually be a bug in expmed.c). Note
6201 that the bit number is negative in big-endian mode in this case.
6202 We have to convert that to the offset. */
6203 if (WORDS_BIG_ENDIAN)
6204 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6205 - INTVAL (operands[2]) - INTVAL (operands[3]);
6207 ofs = INTVAL (operands[3]);
6211 alpha_expand_unaligned_load (operands[0], operands[1],
6212 INTVAL (operands[2]) / 8,
6218 (define_expand "insv"
6219 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6220 (match_operand:DI 1 "immediate_operand" "")
6221 (match_operand:DI 2 "immediate_operand" ""))
6222 (match_operand:DI 3 "register_operand" ""))]
6227 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6228 if (INTVAL (operands[2]) % 8 != 0
6229 || (INTVAL (operands[1]) != 16
6230 && INTVAL (operands[1]) != 32
6231 && INTVAL (operands[1]) != 64))
6234 /* From mips.md: store_bit_field doesn't verify that our source
6235 matches the predicate, so we force it to be a MEM here. */
6236 if (GET_CODE (operands[0]) != MEM)
6239 /* The bit number is relative to the mode of operand 1 which is
6240 usually QImode (this might actually be a bug in expmed.c). Note
6241 that the bit number is negative in big-endian mode in this case.
6242 We have to convert that to the offset. */
6243 if (WORDS_BIG_ENDIAN)
6244 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6245 - INTVAL (operands[1]) - INTVAL (operands[2]);
6247 ofs = INTVAL (operands[2]);
6251 alpha_expand_unaligned_store (operands[0], operands[3],
6252 INTVAL (operands[1]) / 8, ofs);
6256 ;; Block move/clear, see alpha.c for more details.
6257 ;; Argument 0 is the destination
6258 ;; Argument 1 is the source
6259 ;; Argument 2 is the length
6260 ;; Argument 3 is the alignment
6262 (define_expand "movstrqi"
6263 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6264 (match_operand:BLK 1 "memory_operand" ""))
6265 (use (match_operand:DI 2 "immediate_operand" ""))
6266 (use (match_operand:DI 3 "immediate_operand" ""))])]
6269 if (alpha_expand_block_move (operands))
6275 (define_expand "clrstrqi"
6276 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6278 (use (match_operand:DI 1 "immediate_operand" ""))
6279 (use (match_operand:DI 2 "immediate_operand" ""))])]
6282 if (alpha_expand_block_clear (operands))
6288 ;; Subroutine of stack space allocation. Perform a stack probe.
6289 (define_expand "probe_stack"
6290 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6293 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6294 INTVAL (operands[0])));
6295 MEM_VOLATILE_P (operands[1]) = 1;
6297 operands[0] = const0_rtx;
6300 ;; This is how we allocate stack space. If we are allocating a
6301 ;; constant amount of space and we know it is less than 4096
6302 ;; bytes, we need do nothing.
6304 ;; If it is more than 4096 bytes, we need to probe the stack
6306 (define_expand "allocate_stack"
6308 (plus:DI (reg:DI 30)
6309 (match_operand:DI 1 "reg_or_cint_operand" "")))
6310 (set (match_operand:DI 0 "register_operand" "=r")
6314 if (GET_CODE (operands[1]) == CONST_INT
6315 && INTVAL (operands[1]) < 32768)
6317 if (INTVAL (operands[1]) >= 4096)
6319 /* We do this the same way as in the prologue and generate explicit
6320 probes. Then we update the stack by the constant. */
6324 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6325 while (probed + 8192 < INTVAL (operands[1]))
6326 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6328 if (probed + 4096 < INTVAL (operands[1]))
6329 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6332 operands[1] = GEN_INT (- INTVAL (operands[1]));
6333 operands[2] = virtual_stack_dynamic_rtx;
6338 rtx loop_label = gen_label_rtx ();
6339 rtx want = gen_reg_rtx (Pmode);
6340 rtx tmp = gen_reg_rtx (Pmode);
6343 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6344 force_reg (Pmode, operands[1])));
6345 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6347 if (GET_CODE (operands[1]) != CONST_INT)
6349 out_label = gen_label_rtx ();
6350 emit_insn (gen_cmpdi (want, tmp));
6351 emit_jump_insn (gen_bgeu (out_label));
6354 emit_label (loop_label);
6355 memref = gen_rtx_MEM (DImode, tmp);
6356 MEM_VOLATILE_P (memref) = 1;
6357 emit_move_insn (memref, const0_rtx);
6358 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6359 emit_insn (gen_cmpdi (tmp, want));
6360 emit_jump_insn (gen_bgtu (loop_label));
6362 memref = gen_rtx_MEM (DImode, want);
6363 MEM_VOLATILE_P (memref) = 1;
6364 emit_move_insn (memref, const0_rtx);
6367 emit_label (out_label);
6369 emit_move_insn (stack_pointer_rtx, want);
6370 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6375 ;; This is used by alpha_expand_prolog to do the same thing as above,
6376 ;; except we cannot at that time generate new basic blocks, so we hide
6377 ;; the loop in this one insn.
6379 (define_insn "prologue_stack_probe_loop"
6380 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6381 (match_operand:DI 1 "register_operand" "r")]
6385 operands[2] = gen_label_rtx ();
6386 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6387 CODE_LABEL_NUMBER (operands[2]));
6389 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6391 [(set_attr "length" "16")
6392 (set_attr "type" "multi")])
6394 (define_expand "prologue"
6395 [(clobber (const_int 0))]
6398 alpha_expand_prologue ();
6402 ;; These take care of emitting the ldgp insn in the prologue. This will be
6403 ;; an lda/ldah pair and we want to align them properly. So we have two
6404 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6405 ;; and the second of which emits nothing. However, both are marked as type
6406 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6409 (define_expand "prologue_ldgp"
6411 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6413 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6416 operands[0] = pic_offset_table_rtx;
6417 operands[1] = gen_rtx_REG (Pmode, 27);
6418 operands[2] = (TARGET_EXPLICIT_RELOCS
6419 ? GEN_INT (alpha_next_sequence_number++)
6423 (define_insn "*ldgp_er_1"
6424 [(set (match_operand:DI 0 "register_operand" "=r")
6425 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6426 (match_operand 2 "const_int_operand" "")]
6428 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6429 "ldah %0,0(%1)\t\t!gpdisp!%2")
6431 (define_insn "*ldgp_er_2"
6432 [(set (match_operand:DI 0 "register_operand" "=r")
6433 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6434 (match_operand 2 "const_int_operand" "")]
6436 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6437 "lda %0,0(%1)\t\t!gpdisp!%2")
6439 (define_insn "*prologue_ldgp_er_2"
6440 [(set (match_operand:DI 0 "register_operand" "=r")
6441 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6442 (match_operand 2 "const_int_operand" "")]
6444 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6445 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6447 (define_insn "*prologue_ldgp_1"
6448 [(set (match_operand:DI 0 "register_operand" "=r")
6449 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6450 (match_operand 2 "const_int_operand" "")]
6453 "ldgp %0,0(%1)\n$%~..ng:")
6455 (define_insn "*prologue_ldgp_2"
6456 [(set (match_operand:DI 0 "register_operand" "=r")
6457 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6458 (match_operand 2 "const_int_operand" "")]
6463 ;; The _mcount profiling hook has special calling conventions, and
6464 ;; does not clobber all the registers that a normal call would. So
6465 ;; hide the fact this is a call at all.
6467 (define_insn "prologue_mcount"
6468 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6470 "lda $28,_mcount\;jsr $28,($28),_mcount"
6471 [(set_attr "type" "multi")
6472 (set_attr "length" "8")])
6474 (define_insn "init_fp"
6475 [(set (match_operand:DI 0 "register_operand" "=r")
6476 (match_operand:DI 1 "register_operand" "r"))
6477 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6481 (define_expand "epilogue"
6485 alpha_expand_epilogue ();
6488 (define_expand "sibcall_epilogue"
6492 alpha_expand_epilogue ();
6496 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6497 ;; the frame size into a register. We use this pattern to ensure
6498 ;; we get lda instead of addq.
6499 (define_insn "nt_lda"
6500 [(set (match_operand:DI 0 "register_operand" "=r")
6501 (unspec:DI [(match_dup 0)
6502 (match_operand:DI 1 "const_int_operand" "n")]
6507 (define_expand "builtin_longjmp"
6508 [(use (match_operand:DI 0 "register_operand" "r"))]
6511 /* The elements of the buffer are, in order: */
6512 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6513 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6514 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6515 rtx pv = gen_rtx_REG (Pmode, 27);
6517 /* This bit is the same as expand_builtin_longjmp. */
6518 emit_move_insn (hard_frame_pointer_rtx, fp);
6519 emit_move_insn (pv, lab);
6520 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6521 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6522 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6524 /* Load the label we are jumping through into $27 so that we know
6525 where to look for it when we get back to setjmp's function for
6526 restoring the gp. */
6527 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6532 ;; This is effectively a copy of indirect_jump, but constrained such
6533 ;; that register renaming cannot foil our cunning plan with $27.
6534 (define_insn "builtin_longjmp_internal"
6536 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6540 [(set_attr "type" "ibr")])
6542 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6543 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6544 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6545 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6547 (define_insn "*builtin_setjmp_receiver_er_1"
6548 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6549 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6550 "br $27,$LSJ%=\n$LSJ%=:"
6551 [(set_attr "type" "ibr")])
6554 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6555 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6556 && prev_nonnote_insn (insn) == operands[0]"
6560 (define_insn "*builtin_setjmp_receiver_1"
6561 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6563 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6564 [(set_attr "length" "12")
6565 (set_attr "type" "multi")])
6567 (define_expand "builtin_setjmp_receiver_er"
6568 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6570 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6572 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6575 operands[1] = pic_offset_table_rtx;
6576 operands[2] = gen_rtx_REG (Pmode, 27);
6577 operands[3] = GEN_INT (alpha_next_sequence_number++);
6580 (define_expand "builtin_setjmp_receiver"
6581 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6584 if (TARGET_EXPLICIT_RELOCS)
6586 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6591 (define_expand "exception_receiver_er"
6593 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6595 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6598 operands[0] = pic_offset_table_rtx;
6599 operands[1] = gen_rtx_REG (Pmode, 26);
6600 operands[2] = GEN_INT (alpha_next_sequence_number++);
6603 (define_expand "exception_receiver"
6604 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6607 if (TARGET_LD_BUGGY_LDGP)
6608 operands[0] = alpha_gp_save_rtx ();
6609 else if (TARGET_EXPLICIT_RELOCS)
6611 emit_insn (gen_exception_receiver_er ());
6615 operands[0] = const0_rtx;
6618 (define_insn "*exception_receiver_1"
6619 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6620 "! TARGET_LD_BUGGY_LDGP"
6622 [(set_attr "length" "8")
6623 (set_attr "type" "multi")])
6625 (define_insn "*exception_receiver_2"
6626 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
6628 "TARGET_LD_BUGGY_LDGP"
6632 [(set_attr "type" "ilog,ild")])
6634 (define_expand "nonlocal_goto_receiver"
6635 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6636 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6637 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6639 "TARGET_ABI_OPEN_VMS"
6642 (define_insn "arg_home"
6643 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6658 (clobber (mem:BLK (const_int 0)))
6659 (clobber (reg:DI 24))
6660 (clobber (reg:DI 25))
6661 (clobber (reg:DI 0))]
6662 "TARGET_ABI_OPEN_VMS"
6663 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6664 [(set_attr "length" "16")
6665 (set_attr "type" "multi")])
6667 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6669 (define_expand "umk_mismatch_args"
6670 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6671 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6672 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6673 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6676 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6677 "TARGET_ABI_UNICOSMK"
6679 operands[1] = gen_reg_rtx (DImode);
6680 operands[2] = gen_reg_rtx (DImode);
6681 operands[3] = gen_reg_rtx (DImode);
6684 (define_insn "arg_home_umk"
6685 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6700 (clobber (mem:BLK (const_int 0)))
6702 (clobber (reg:DI 22))
6703 (clobber (reg:DI 23))
6704 (clobber (reg:DI 24))
6705 (clobber (reg:DI 0))
6706 (clobber (reg:DI 1))
6707 (clobber (reg:DI 2))
6708 (clobber (reg:DI 3))
6709 (clobber (reg:DI 4))
6710 (clobber (reg:DI 5))
6711 (clobber (reg:DI 6))
6712 (clobber (reg:DI 7))
6713 (clobber (reg:DI 8))])]
6714 "TARGET_ABI_UNICOSMK"
6715 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6716 [(set_attr "length" "16")
6717 (set_attr "type" "multi")])
6721 ;; On EV4, these instructions are nops -- no load occurs.
6723 ;; On EV5, these instructions act as a normal load, and thus can trap
6724 ;; if the address is invalid. The OS may (or may not) handle this in
6725 ;; the entMM fault handler and suppress the fault. If so, then this
6726 ;; has the effect of a read prefetch instruction.
6728 ;; On EV6, these become official prefetch instructions.
6730 (define_insn "prefetch"
6731 [(prefetch (match_operand:DI 0 "address_operand" "p")
6732 (match_operand:DI 1 "const_int_operand" "n")
6733 (match_operand:DI 2 "const_int_operand" "n"))]
6734 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6736 /* Interpret "no temporal locality" as this data should be evicted once
6737 it is used. The "evict next" alternatives load the data into the cache
6738 and leave the LRU eviction counter pointing to that block. */
6739 static const char * const alt[2][2] = {
6741 "lds $f31,%a0", /* read, evict next */
6742 "ldl $31,%a0", /* read, evict last */
6745 "ldt $f31,%a0", /* write, evict next */
6746 "ldq $31,%a0", /* write, evict last */
6750 bool write = INTVAL (operands[1]) != 0;
6751 bool lru = INTVAL (operands[2]) != 0;
6753 return alt[write][lru];
6755 [(set_attr "type" "ild")])
6757 ;; Close the trap shadow of preceding instructions. This is generated
6760 (define_insn "trapb"
6761 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6764 [(set_attr "type" "misc")])
6766 ;; No-op instructions used by machine-dependent reorg to preserve
6767 ;; alignment for instruction issue.
6768 ;; The Unicos/Mk assembler does not support these opcodes.
6774 [(set_attr "type" "ilog")])
6779 "cpys $f31,$f31,$f31"
6780 [(set_attr "type" "fcpys")])
6787 ;; On Unicos/Mk we use a macro for aligning code.
6789 (define_insn "realign"
6790 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6794 if (TARGET_ABI_UNICOSMK)
6795 return "gcc@code@align %0";
6797 return ".align %0 #realign";
6800 ;; The call patterns are at the end of the file because their
6801 ;; wildcard operand0 interferes with nice recognition.
6803 (define_insn "*call_value_osf_1_er"
6804 [(set (match_operand 0 "" "")
6805 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6806 (match_operand 2 "" "")))
6808 (clobber (reg:DI 26))]
6809 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6811 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6813 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6814 [(set_attr "type" "jsr")
6815 (set_attr "length" "12,*,16")])
6817 ;; We must use peep2 instead of a split because we need accurate life
6818 ;; information for $gp. Consider the case of { bar(); while (1); }.
6820 [(parallel [(set (match_operand 0 "" "")
6821 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6822 (match_operand 2 "" "")))
6824 (clobber (reg:DI 26))])]
6825 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6826 && ! current_file_function_operand (operands[0], Pmode)
6827 && peep2_regno_dead_p (1, 29)"
6828 [(parallel [(set (match_dup 0)
6829 (call (mem:DI (match_dup 3))
6831 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6832 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6833 (use (match_dup 1))])]
6835 if (CONSTANT_P (operands[1]))
6837 operands[3] = gen_rtx_REG (Pmode, 27);
6838 emit_move_insn (operands[3], operands[1]);
6842 operands[3] = operands[1];
6843 operands[1] = const0_rtx;
6848 [(parallel [(set (match_operand 0 "" "")
6849 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6850 (match_operand 2 "" "")))
6852 (clobber (reg:DI 26))])]
6853 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6854 && ! current_file_function_operand (operands[0], Pmode)
6855 && ! peep2_regno_dead_p (1, 29)"
6856 [(parallel [(set (match_dup 0)
6857 (call (mem:DI (match_dup 3))
6859 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6860 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6861 (use (match_dup 1))])
6863 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6865 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6867 if (CONSTANT_P (operands[1]))
6869 operands[3] = gen_rtx_REG (Pmode, 27);
6870 emit_move_insn (operands[3], operands[1]);
6874 operands[3] = operands[1];
6875 operands[1] = const0_rtx;
6877 operands[4] = GEN_INT (alpha_next_sequence_number++);
6880 ;; We add a blockage unspec_volatile to prevent insns from moving down
6881 ;; from above the call to in between the call and the ldah gpdisp.
6882 (define_insn "*call_value_osf_2_er"
6883 [(set (match_operand 0 "" "")
6884 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6885 (match_operand 2 "" "")))
6887 (plus:DI (pc) (const_int 4)))
6888 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6889 (use (match_operand 3 "" ""))]
6890 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6892 [(set_attr "type" "jsr")])
6894 (define_insn "*call_value_osf_1_noreturn"
6895 [(set (match_operand 0 "" "")
6896 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6897 (match_operand 2 "" "")))
6899 (clobber (reg:DI 26))]
6900 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6901 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6906 [(set_attr "type" "jsr")
6907 (set_attr "length" "*,*,8")])
6909 (define_insn "*call_value_osf_1"
6910 [(set (match_operand 0 "" "")
6911 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6912 (match_operand 2 "" "")))
6914 (clobber (reg:DI 26))]
6915 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6917 jsr $26,($27),0\;ldgp $29,0($26)
6919 jsr $26,%1\;ldgp $29,0($26)"
6920 [(set_attr "type" "jsr")
6921 (set_attr "length" "12,*,16")])
6923 (define_insn "*sibcall_value_osf_1"
6924 [(set (match_operand 0 "" "")
6925 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
6926 (match_operand 2 "" "")))
6931 lda $27,%1\;jmp $31,($27),%1"
6932 [(set_attr "type" "jsr")
6933 (set_attr "length" "*,8")])
6935 (define_insn "*call_value_nt_1"
6936 [(set (match_operand 0 "" "")
6937 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
6938 (match_operand 2 "" "")))
6939 (clobber (reg:DI 26))]
6940 "TARGET_ABI_WINDOWS_NT"
6945 [(set_attr "type" "jsr")
6946 (set_attr "length" "*,*,12")])
6948 (define_insn "*call_value_vms_1"
6949 [(set (match_operand 0 "" "")
6950 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
6951 (match_operand 2 "" "")))
6952 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6955 (clobber (reg:DI 27))]
6956 "TARGET_ABI_OPEN_VMS"
6958 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6959 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6960 [(set_attr "type" "jsr")
6961 (set_attr "length" "12,16")])
6963 (define_insn "*call_value_umk"
6964 [(set (match_operand 0 "" "")
6965 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
6966 (match_operand 2 "" "")))
6968 (clobber (reg:DI 26))]
6969 "TARGET_ABI_UNICOSMK"
6971 [(set_attr "type" "jsr")])