1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
49 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
50 (UNSPECV_LONGJMP 3) ; builtin_longjmp
52 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
54 (UNSPECV_EHR 7) ; exception_receiver
58 (UNSPECV_PLDGP2 11) ; prologue ldgp
61 ;; Where necessary, the suffixes _le and _be are used to distinguish between
62 ;; little-endian and big-endian patterns.
64 ;; Note that the Unicos/Mk assembler does not support the following
65 ;; opcodes: mov, fmov, nop, fnop, unop.
67 ;; Processor type -- this attribute must exactly match the processor_type
68 ;; enumeration in alpha.h.
70 (define_attr "cpu" "ev4,ev5,ev6"
71 (const (symbol_ref "alpha_cpu")))
73 ;; Define an insn type attribute. This is used in function unit delay
74 ;; computations, among other purposes. For the most part, we use the names
75 ;; defined in the EV4 documentation, but add a few that we have to know about
79 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
80 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
81 (const_string "iadd"))
83 ;; Describe a user's asm statement.
84 (define_asm_attributes
85 [(set_attr "type" "multi")])
87 ;; Define the operand size an insn operates on. Used primarily by mul
88 ;; and div operations that have size dependent timings.
90 (define_attr "opsize" "si,di,udi"
93 ;; The TRAP attribute marks instructions that may generate traps
94 ;; (which are imprecise and may need a trapb if software completion
97 (define_attr "trap" "no,yes"
100 ;; The ROUND_SUFFIX attribute marks which instructions require a
101 ;; rounding-mode suffix. The value NONE indicates no suffix,
102 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
104 (define_attr "round_suffix" "none,normal,c"
105 (const_string "none"))
107 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
109 ;; SU accepts only /su (cmpt et al)
110 ;; SUI accepts only /sui (cvtqt and cvtqs)
111 ;; V_SV accepts /v and /sv (cvtql only)
112 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
113 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
115 ;; The actual suffix emitted is controled by alpha_fptm.
117 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
118 (const_string "none"))
120 ;; The length of an instruction sequence in bytes.
122 (define_attr "length" ""
125 ;; On EV4 there are two classes of resources to consider: resources needed
126 ;; to issue, and resources needed to execute. IBUS[01] are in the first
127 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
128 ;; (There are a few other register-like resources, but ...)
130 ; First, describe all of the issue constraints with single cycle delays.
131 ; All insns need a bus, but all except loads require one or the other.
132 (define_function_unit "ev4_ibus0" 1 0
133 (and (eq_attr "cpu" "ev4")
134 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
137 (define_function_unit "ev4_ibus1" 1 0
138 (and (eq_attr "cpu" "ev4")
139 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
142 ; Memory delivers its result in three cycles. Actually return one and
143 ; take care of this in adjust_cost, since we want to handle user-defined
145 (define_function_unit "ev4_abox" 1 0
146 (and (eq_attr "cpu" "ev4")
147 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
150 ; Branches have no delay cost, but do tie up the unit for two cycles.
151 (define_function_unit "ev4_bbox" 1 1
152 (and (eq_attr "cpu" "ev4")
153 (eq_attr "type" "ibr,fbr,jsr"))
156 ; Arithmetic insns are normally have their results available after
157 ; two cycles. There are a number of exceptions. They are encoded in
158 ; ADJUST_COST. Some of the other insns have similar exceptions.
159 (define_function_unit "ev4_ebox" 1 0
160 (and (eq_attr "cpu" "ev4")
161 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
164 (define_function_unit "imul" 1 0
165 (and (eq_attr "cpu" "ev4")
166 (and (eq_attr "type" "imul")
167 (eq_attr "opsize" "si")))
170 (define_function_unit "imul" 1 0
171 (and (eq_attr "cpu" "ev4")
172 (and (eq_attr "type" "imul")
173 (eq_attr "opsize" "!si")))
176 (define_function_unit "ev4_fbox" 1 0
177 (and (eq_attr "cpu" "ev4")
178 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
181 (define_function_unit "fdiv" 1 0
182 (and (eq_attr "cpu" "ev4")
183 (and (eq_attr "type" "fdiv")
184 (eq_attr "opsize" "si")))
187 (define_function_unit "fdiv" 1 0
188 (and (eq_attr "cpu" "ev4")
189 (and (eq_attr "type" "fdiv")
190 (eq_attr "opsize" "di")))
193 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
195 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
196 ;; with the combined resource EBOX.
198 (define_function_unit "ev5_ebox" 2 0
199 (and (eq_attr "cpu" "ev5")
200 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
203 ; Memory takes at least 2 clocks. Return one from here and fix up with
204 ; user-defined latencies in adjust_cost.
205 (define_function_unit "ev5_ebox" 2 0
206 (and (eq_attr "cpu" "ev5")
207 (eq_attr "type" "ild,fld,ldsym"))
210 ; Loads can dual issue with one another, but loads and stores do not mix.
211 (define_function_unit "ev5_e0" 1 0
212 (and (eq_attr "cpu" "ev5")
213 (eq_attr "type" "ild,fld,ldsym"))
215 [(eq_attr "type" "ist,fst")])
217 ; Stores, shifts, multiplies can only issue to E0
218 (define_function_unit "ev5_e0" 1 0
219 (and (eq_attr "cpu" "ev5")
220 (eq_attr "type" "ist,fst,shift,imul"))
223 ; Motion video insns also issue only to E0, and take two ticks.
224 (define_function_unit "ev5_e0" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "mvi"))
229 ; Conditional moves always take 2 ticks.
230 (define_function_unit "ev5_ebox" 2 0
231 (and (eq_attr "cpu" "ev5")
232 (eq_attr "type" "icmov"))
235 ; Branches can only issue to E1
236 (define_function_unit "ev5_e1" 1 0
237 (and (eq_attr "cpu" "ev5")
238 (eq_attr "type" "ibr,jsr"))
241 ; Multiplies also use the integer multiplier.
242 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
243 ; cycles before an integer multiplication completes."
244 (define_function_unit "imul" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "imul")
247 (eq_attr "opsize" "si")))
250 (define_function_unit "imul" 1 0
251 (and (eq_attr "cpu" "ev5")
252 (and (eq_attr "type" "imul")
253 (eq_attr "opsize" "di")))
256 (define_function_unit "imul" 1 0
257 (and (eq_attr "cpu" "ev5")
258 (and (eq_attr "type" "imul")
259 (eq_attr "opsize" "udi")))
262 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
263 ;; on either so we have to play the game again.
265 (define_function_unit "ev5_fbox" 2 0
266 (and (eq_attr "cpu" "ev5")
267 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
270 (define_function_unit "ev5_fm" 1 0
271 (and (eq_attr "cpu" "ev5")
272 (eq_attr "type" "fmul"))
275 ; Add and cmov as you would expect; fbr never produces a result;
276 ; fdiv issues through fa to the divider,
277 (define_function_unit "ev5_fa" 1 0
278 (and (eq_attr "cpu" "ev5")
279 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
282 ; ??? How to: "No instruction can be issued to pipe FA exactly five
283 ; cycles before a floating point divide completes."
284 (define_function_unit "fdiv" 1 0
285 (and (eq_attr "cpu" "ev5")
286 (and (eq_attr "type" "fdiv")
287 (eq_attr "opsize" "si")))
288 15 15) ; 15 to 31 data dependent
290 (define_function_unit "fdiv" 1 0
291 (and (eq_attr "cpu" "ev5")
292 (and (eq_attr "type" "fdiv")
293 (eq_attr "opsize" "di")))
294 22 22) ; 22 to 60 data dependent
296 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
298 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
299 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
301 ;; Conditional moves decompose into two independent primitives, each
302 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
304 (define_function_unit "ev6_ebox" 4 0
305 (and (eq_attr "cpu" "ev6")
306 (eq_attr "type" "icmov"))
309 (define_function_unit "ev6_ebox" 4 0
310 (and (eq_attr "cpu" "ev6")
311 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
314 ;; Integer loads take at least 3 clocks, and only issue to lower units.
315 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
316 (define_function_unit "ev6_l" 2 0
317 (and (eq_attr "cpu" "ev6")
318 (eq_attr "type" "ild,ldsym,ist,fst"))
321 ;; FP loads take at least 4 clocks. Return two from here...
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "fld"))
327 ;; Motion video insns also issue only to U0, and take three ticks.
328 (define_function_unit "ev6_u0" 1 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "mvi"))
333 (define_function_unit "ev6_u" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "mvi"))
338 ;; Shifts issue to either upper pipe.
339 (define_function_unit "ev6_u" 2 0
340 (and (eq_attr "cpu" "ev6")
341 (eq_attr "type" "shift"))
344 ;; Multiplies issue only to U1, and all take 7 ticks.
345 ;; Rather than create a new function unit just for U1, reuse IMUL
346 (define_function_unit "imul" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "imul"))
351 (define_function_unit "ev6_u" 2 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "imul"))
356 ;; Branches issue to either upper pipe
357 (define_function_unit "ev6_u" 2 0
358 (and (eq_attr "cpu" "ev6")
359 (eq_attr "type" "ibr"))
362 ;; Calls only issue to L0.
363 (define_function_unit "ev6_l0" 1 0
364 (and (eq_attr "cpu" "ev6")
365 (eq_attr "type" "jsr"))
368 (define_function_unit "ev6_l" 2 0
369 (and (eq_attr "cpu" "ev6")
370 (eq_attr "type" "jsr"))
373 ;; Ftoi/itof only issue to lower pipes
374 (define_function_unit "ev6_l" 2 0
375 (and (eq_attr "cpu" "ev6")
376 (eq_attr "type" "ftoi"))
379 (define_function_unit "ev6_l" 2 0
380 (and (eq_attr "cpu" "ev6")
381 (eq_attr "type" "itof"))
384 ;; For the FPU we are very similar to EV5, except there's no insn that
385 ;; can issue to fm & fa, so we get to leave that out.
387 (define_function_unit "ev6_fm" 1 0
388 (and (eq_attr "cpu" "ev6")
389 (eq_attr "type" "fmul"))
392 (define_function_unit "ev6_fa" 1 0
393 (and (eq_attr "cpu" "ev6")
394 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
397 (define_function_unit "ev6_fa" 1 0
398 (and (eq_attr "cpu" "ev6")
399 (eq_attr "type" "fcmov"))
402 (define_function_unit "fdiv" 1 0
403 (and (eq_attr "cpu" "ev6")
404 (and (eq_attr "type" "fdiv")
405 (eq_attr "opsize" "si")))
408 (define_function_unit "fdiv" 1 0
409 (and (eq_attr "cpu" "ev6")
410 (and (eq_attr "type" "fdiv")
411 (eq_attr "opsize" "di")))
414 (define_function_unit "fsqrt" 1 0
415 (and (eq_attr "cpu" "ev6")
416 (and (eq_attr "type" "fsqrt")
417 (eq_attr "opsize" "si")))
420 (define_function_unit "fsqrt" 1 0
421 (and (eq_attr "cpu" "ev6")
422 (and (eq_attr "type" "fsqrt")
423 (eq_attr "opsize" "di")))
426 ; ??? The FPU communicates with memory and the integer register file
427 ; via two fp store units. We need a slot in the fst immediately, and
428 ; a slot in LOW after the operand data is ready. At which point the
429 ; data may be moved either to the store queue or the integer register
430 ; file and the insn retired.
433 ;; First define the arithmetic insns. Note that the 32-bit forms also
436 ;; Handle 32-64 bit extension from memory to a floating point register
437 ;; specially, since this occurs frequently in int->double conversions.
439 ;; Note that while we must retain the =f case in the insn for reload's
440 ;; benefit, it should be eliminated after reload, so we should never emit
441 ;; code for that case. But we don't reject the possibility.
443 (define_expand "extendsidi2"
444 [(set (match_operand:DI 0 "register_operand" "")
445 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
449 (define_insn "*extendsidi2_nofix"
450 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
452 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
458 lds %0,%1\;cvtlq %0,%0"
459 [(set_attr "type" "iadd,ild,fadd,fld")
460 (set_attr "length" "*,*,*,8")])
462 (define_insn "*extendsidi2_fix"
463 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
465 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
472 lds %0,%1\;cvtlq %0,%0"
473 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
474 (set_attr "length" "*,*,*,*,8")])
476 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
478 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
479 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
481 [(set (match_dup 2) (match_dup 1))
482 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
483 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
485 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
486 ;; reload when converting fp->int.
489 [(set (match_operand:SI 0 "hard_int_register_operand" "")
490 (match_operand:SI 1 "memory_operand" ""))
491 (set (match_operand:DI 2 "hard_int_register_operand" "")
492 (sign_extend:DI (match_dup 0)))]
493 "true_regnum (operands[0]) == true_regnum (operands[2])
494 || peep2_reg_dead_p (2, operands[0])"
496 (sign_extend:DI (match_dup 1)))]
500 [(set (match_operand:SI 0 "hard_int_register_operand" "")
501 (match_operand:SI 1 "hard_fp_register_operand" ""))
502 (set (match_operand:DI 2 "hard_int_register_operand" "")
503 (sign_extend:DI (match_dup 0)))]
505 && (true_regnum (operands[0]) == true_regnum (operands[2])
506 || peep2_reg_dead_p (2, operands[0]))"
508 (sign_extend:DI (match_dup 1)))]
512 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
513 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
514 (set (match_operand:DI 2 "hard_int_register_operand" "")
516 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
518 (sign_extend:DI (match_dup 1)))]
521 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
522 ;; generates better code. We have the anonymous addsi3 pattern below in
523 ;; case combine wants to make it.
524 (define_expand "addsi3"
525 [(set (match_operand:SI 0 "register_operand" "")
526 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
527 (match_operand:SI 2 "add_operand" "")))]
532 rtx op1 = gen_lowpart (DImode, operands[1]);
533 rtx op2 = gen_lowpart (DImode, operands[2]);
535 if (! cse_not_expected)
537 rtx tmp = gen_reg_rtx (DImode);
538 emit_insn (gen_adddi3 (tmp, op1, op2));
539 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
542 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
547 (define_insn "*addsi_internal"
548 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
549 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
550 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
559 [(set (match_operand:SI 0 "register_operand" "")
560 (plus:SI (match_operand:SI 1 "register_operand" "")
561 (match_operand:SI 2 "const_int_operand" "")))]
562 "! add_operand (operands[2], SImode)"
563 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
564 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
566 HOST_WIDE_INT val = INTVAL (operands[2]);
567 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
568 HOST_WIDE_INT rest = val - low;
570 operands[3] = GEN_INT (rest);
571 operands[4] = GEN_INT (low);
574 (define_insn "*addsi_se"
575 [(set (match_operand:DI 0 "register_operand" "=r,r")
577 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
578 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
585 [(set (match_operand:DI 0 "register_operand" "")
587 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
588 (match_operand:SI 2 "const_int_operand" ""))))
589 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
590 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
591 && INTVAL (operands[2]) % 4 == 0"
592 [(set (match_dup 3) (match_dup 4))
593 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
597 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
603 operands[4] = GEN_INT (val);
604 operands[5] = GEN_INT (mult);
608 [(set (match_operand:DI 0 "register_operand" "")
610 (plus:SI (match_operator:SI 1 "comparison_operator"
611 [(match_operand 2 "" "")
612 (match_operand 3 "" "")])
613 (match_operand:SI 4 "add_operand" ""))))
614 (clobber (match_operand:DI 5 "register_operand" ""))]
616 [(set (match_dup 5) (match_dup 6))
617 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
619 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
620 operands[2], operands[3]);
621 operands[7] = gen_lowpart (SImode, operands[5]);
624 (define_insn "addvsi3"
625 [(set (match_operand:SI 0 "register_operand" "=r,r")
626 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
627 (match_operand:SI 2 "sext_add_operand" "rI,O")))
628 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
629 (sign_extend:DI (match_dup 2)))
630 (sign_extend:DI (plus:SI (match_dup 1)
638 (define_expand "adddi3"
639 [(set (match_operand:DI 0 "register_operand" "")
640 (plus:DI (match_operand:DI 1 "register_operand" "")
641 (match_operand:DI 2 "add_operand" "")))]
645 (define_insn "*adddi_er_high_l"
646 [(set (match_operand:DI 0 "register_operand" "=r")
647 (plus:DI (match_operand:DI 1 "register_operand" "r")
648 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
649 "TARGET_EXPLICIT_RELOCS"
650 "ldah %0,%2(%1)\t\t!gprelhigh")
653 [(set (match_operand:DI 0 "register_operand" "")
654 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
655 "TARGET_EXPLICIT_RELOCS && reload_completed"
657 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
658 "operands[2] = pic_offset_table_rtx;")
660 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
661 ;; With complications like
663 ;; The NT stack unwind code can't handle a subq to adjust the stack
664 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
665 ;; the exception handling code will loop if a subq is used and an
668 ;; The 19980616 change to emit prologues as RTL also confused some
669 ;; versions of GDB, which also interprets prologues. This has been
670 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
673 ;; and the fact that the three insns schedule exactly the same, it's
674 ;; just not worth the effort.
676 (define_insn "*adddi_internal"
677 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
678 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
679 (match_operand:DI 2 "add_operand" "r,K,L")))]
686 ;; ??? Allow large constants when basing off the frame pointer or some
687 ;; virtual register that may eliminate to the frame pointer. This is
688 ;; done because register elimination offsets will change the hi/lo split,
689 ;; and if we split before reload, we will require additional instructions.
691 (define_insn "*adddi_fp_hack"
692 [(set (match_operand:DI 0 "register_operand" "=r")
693 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
694 (match_operand:DI 2 "const_int_operand" "n")))]
695 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
696 && INTVAL (operands[2]) >= 0
697 /* This is the largest constant an lda+ldah pair can add, minus
698 an upper bound on the displacement between SP and AP during
699 register elimination. See INITIAL_ELIMINATION_OFFSET. */
700 && INTVAL (operands[2])
702 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
703 - ALPHA_ROUND(current_function_outgoing_args_size)
704 - (ALPHA_ROUND (get_frame_size ()
705 + max_reg_num () * UNITS_PER_WORD
706 + current_function_pretend_args_size)
707 - current_function_pretend_args_size))"
710 ;; Don't do this if we are adjusting SP since we don't want to do it
711 ;; in two steps. Don't split FP sources for the reason listed above.
713 [(set (match_operand:DI 0 "register_operand" "")
714 (plus:DI (match_operand:DI 1 "register_operand" "")
715 (match_operand:DI 2 "const_int_operand" "")))]
716 "! add_operand (operands[2], DImode)
717 && operands[0] != stack_pointer_rtx
718 && operands[1] != frame_pointer_rtx
719 && operands[1] != arg_pointer_rtx"
720 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
721 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
723 HOST_WIDE_INT val = INTVAL (operands[2]);
724 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
725 HOST_WIDE_INT rest = val - low;
727 operands[4] = GEN_INT (low);
728 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
729 operands[3] = GEN_INT (rest);
730 else if (! no_new_pseudos)
732 operands[3] = gen_reg_rtx (DImode);
733 emit_move_insn (operands[3], operands[2]);
734 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
741 (define_insn "*saddl"
742 [(set (match_operand:SI 0 "register_operand" "=r,r")
743 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
744 (match_operand:SI 2 "const48_operand" "I,I"))
745 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
751 (define_insn "*saddl_se"
752 [(set (match_operand:DI 0 "register_operand" "=r,r")
754 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
755 (match_operand:SI 2 "const48_operand" "I,I"))
756 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
763 [(set (match_operand:DI 0 "register_operand" "")
765 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
766 [(match_operand 2 "" "")
767 (match_operand 3 "" "")])
768 (match_operand:SI 4 "const48_operand" ""))
769 (match_operand:SI 5 "sext_add_operand" ""))))
770 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
772 [(set (match_dup 6) (match_dup 7))
774 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
777 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
778 operands[2], operands[3]);
779 operands[8] = gen_lowpart (SImode, operands[6]);
782 (define_insn "*saddq"
783 [(set (match_operand:DI 0 "register_operand" "=r,r")
784 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
785 (match_operand:DI 2 "const48_operand" "I,I"))
786 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
792 (define_insn "addvdi3"
793 [(set (match_operand:DI 0 "register_operand" "=r,r")
794 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
795 (match_operand:DI 2 "sext_add_operand" "rI,O")))
796 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
797 (sign_extend:TI (match_dup 2)))
798 (sign_extend:TI (plus:DI (match_dup 1)
806 (define_insn "negsi2"
807 [(set (match_operand:SI 0 "register_operand" "=r")
808 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
812 (define_insn "*negsi_se"
813 [(set (match_operand:DI 0 "register_operand" "=r")
814 (sign_extend:DI (neg:SI
815 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
819 (define_insn "negvsi2"
820 [(set (match_operand:SI 0 "register_operand" "=r")
821 (neg:SI (match_operand:SI 1 "register_operand" "r")))
822 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
823 (sign_extend:DI (neg:SI (match_dup 1))))
828 (define_insn "negdi2"
829 [(set (match_operand:DI 0 "register_operand" "=r")
830 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
834 (define_insn "negvdi2"
835 [(set (match_operand:DI 0 "register_operand" "=r")
836 (neg:DI (match_operand:DI 1 "register_operand" "r")))
837 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
838 (sign_extend:TI (neg:DI (match_dup 1))))
843 (define_expand "subsi3"
844 [(set (match_operand:SI 0 "register_operand" "")
845 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
846 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
851 rtx op1 = gen_lowpart (DImode, operands[1]);
852 rtx op2 = gen_lowpart (DImode, operands[2]);
854 if (! cse_not_expected)
856 rtx tmp = gen_reg_rtx (DImode);
857 emit_insn (gen_subdi3 (tmp, op1, op2));
858 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
861 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
866 (define_insn "*subsi_internal"
867 [(set (match_operand:SI 0 "register_operand" "=r")
868 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
869 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
873 (define_insn "*subsi_se"
874 [(set (match_operand:DI 0 "register_operand" "=r")
875 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
876 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
880 (define_insn "subvsi3"
881 [(set (match_operand:SI 0 "register_operand" "=r")
882 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
883 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
884 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
885 (sign_extend:DI (match_dup 2)))
886 (sign_extend:DI (minus:SI (match_dup 1)
892 (define_insn "subdi3"
893 [(set (match_operand:DI 0 "register_operand" "=r")
894 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
895 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
899 (define_insn "*ssubl"
900 [(set (match_operand:SI 0 "register_operand" "=r")
901 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
902 (match_operand:SI 2 "const48_operand" "I"))
903 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
907 (define_insn "*ssubl_se"
908 [(set (match_operand:DI 0 "register_operand" "=r")
910 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
911 (match_operand:SI 2 "const48_operand" "I"))
912 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
916 (define_insn "*ssubq"
917 [(set (match_operand:DI 0 "register_operand" "=r")
918 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
919 (match_operand:DI 2 "const48_operand" "I"))
920 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
924 (define_insn "subvdi3"
925 [(set (match_operand:DI 0 "register_operand" "=r")
926 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
927 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
928 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
929 (sign_extend:TI (match_dup 2)))
930 (sign_extend:TI (minus:DI (match_dup 1)
936 ;; The Unicos/Mk assembler doesn't support mull.
938 (define_insn "mulsi3"
939 [(set (match_operand:SI 0 "register_operand" "=r")
940 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
941 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
942 "!TARGET_ABI_UNICOSMK"
944 [(set_attr "type" "imul")
945 (set_attr "opsize" "si")])
947 (define_insn "*mulsi_se"
948 [(set (match_operand:DI 0 "register_operand" "=r")
950 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
951 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
952 "!TARGET_ABI_UNICOSMK"
954 [(set_attr "type" "imul")
955 (set_attr "opsize" "si")])
957 (define_insn "mulvsi3"
958 [(set (match_operand:SI 0 "register_operand" "=r")
959 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
960 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
961 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
962 (sign_extend:DI (match_dup 2)))
963 (sign_extend:DI (mult:SI (match_dup 1)
966 "!TARGET_ABI_UNICOSMK"
968 [(set_attr "type" "imul")
969 (set_attr "opsize" "si")])
971 (define_insn "muldi3"
972 [(set (match_operand:DI 0 "register_operand" "=r")
973 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
974 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
977 [(set_attr "type" "imul")])
979 (define_insn "mulvdi3"
980 [(set (match_operand:DI 0 "register_operand" "=r")
981 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
982 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
983 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
984 (sign_extend:TI (match_dup 2)))
985 (sign_extend:TI (mult:DI (match_dup 1)
990 [(set_attr "type" "imul")])
992 (define_insn "umuldi3_highpart"
993 [(set (match_operand:DI 0 "register_operand" "=r")
996 (mult:TI (zero_extend:TI
997 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
999 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
1003 [(set_attr "type" "imul")
1004 (set_attr "opsize" "udi")])
1006 (define_insn "*umuldi3_highpart_const"
1007 [(set (match_operand:DI 0 "register_operand" "=r")
1010 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
1011 (match_operand:TI 2 "cint8_operand" "I"))
1015 [(set_attr "type" "imul")
1016 (set_attr "opsize" "udi")])
1018 ;; The divide and remainder operations take their inputs from r24 and
1019 ;; r25, put their output in r27, and clobber r23 and r28 on all
1020 ;; systems except Unicos/Mk. On Unicos, the standard library provides
1021 ;; subroutines which use the standard calling convention and work on
1024 ;; ??? Force sign-extension here because some versions of OSF/1 and
1025 ;; Interix/NT don't do the right thing if the inputs are not properly
1026 ;; sign-extended. But Linux, for instance, does not have this
1027 ;; problem. Is it worth the complication here to eliminate the sign
1030 (define_expand "divsi3"
1032 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1034 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1035 (parallel [(set (match_dup 5)
1036 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
1037 (clobber (reg:DI 23))
1038 (clobber (reg:DI 28))])
1039 (set (match_operand:SI 0 "nonimmediate_operand" "")
1040 (subreg:SI (match_dup 5) 0))]
1041 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1043 operands[3] = gen_reg_rtx (DImode);
1044 operands[4] = gen_reg_rtx (DImode);
1045 operands[5] = gen_reg_rtx (DImode);
1048 (define_expand "udivsi3"
1050 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1052 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1053 (parallel [(set (match_dup 5)
1054 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
1055 (clobber (reg:DI 23))
1056 (clobber (reg:DI 28))])
1057 (set (match_operand:SI 0 "nonimmediate_operand" "")
1058 (subreg:SI (match_dup 5) 0))]
1059 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1061 operands[3] = gen_reg_rtx (DImode);
1062 operands[4] = gen_reg_rtx (DImode);
1063 operands[5] = gen_reg_rtx (DImode);
1066 (define_expand "modsi3"
1068 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1070 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1071 (parallel [(set (match_dup 5)
1072 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
1073 (clobber (reg:DI 23))
1074 (clobber (reg:DI 28))])
1075 (set (match_operand:SI 0 "nonimmediate_operand" "")
1076 (subreg:SI (match_dup 5) 0))]
1077 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1079 operands[3] = gen_reg_rtx (DImode);
1080 operands[4] = gen_reg_rtx (DImode);
1081 operands[5] = gen_reg_rtx (DImode);
1084 (define_expand "umodsi3"
1086 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1088 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1089 (parallel [(set (match_dup 5)
1090 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
1091 (clobber (reg:DI 23))
1092 (clobber (reg:DI 28))])
1093 (set (match_operand:SI 0 "nonimmediate_operand" "")
1094 (subreg:SI (match_dup 5) 0))]
1095 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1097 operands[3] = gen_reg_rtx (DImode);
1098 operands[4] = gen_reg_rtx (DImode);
1099 operands[5] = gen_reg_rtx (DImode);
1102 (define_expand "divdi3"
1103 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1104 (div:DI (match_operand:DI 1 "register_operand" "")
1105 (match_operand:DI 2 "register_operand" "")))
1106 (clobber (reg:DI 23))
1107 (clobber (reg:DI 28))])]
1108 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1111 (define_expand "udivdi3"
1112 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1113 (udiv:DI (match_operand:DI 1 "register_operand" "")
1114 (match_operand:DI 2 "register_operand" "")))
1115 (clobber (reg:DI 23))
1116 (clobber (reg:DI 28))])]
1117 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1120 (define_expand "moddi3"
1121 [(use (match_operand:DI 0 "register_operand" ""))
1122 (use (match_operand:DI 1 "register_operand" ""))
1123 (use (match_operand:DI 2 "register_operand" ""))]
1124 "!TARGET_ABI_OPEN_VMS"
1126 if (TARGET_ABI_UNICOSMK)
1127 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
1129 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
1133 (define_expand "moddi3_dft"
1134 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1135 (mod:DI (match_operand:DI 1 "register_operand" "")
1136 (match_operand:DI 2 "register_operand" "")))
1137 (clobber (reg:DI 23))
1138 (clobber (reg:DI 28))])]
1139 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1142 ;; On Unicos/Mk, we do as the system's C compiler does:
1143 ;; compute the quotient, multiply and subtract.
1145 (define_expand "moddi3_umk"
1146 [(use (match_operand:DI 0 "register_operand" ""))
1147 (use (match_operand:DI 1 "register_operand" ""))
1148 (use (match_operand:DI 2 "register_operand" ""))]
1149 "TARGET_ABI_UNICOSMK"
1151 rtx div, mul = gen_reg_rtx (DImode);
1153 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
1154 NULL_RTX, 0, OPTAB_LIB);
1155 div = force_reg (DImode, div);
1156 emit_insn (gen_muldi3 (mul, operands[2], div));
1157 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1161 (define_expand "umoddi3"
1162 [(use (match_operand:DI 0 "register_operand" ""))
1163 (use (match_operand:DI 1 "register_operand" ""))
1164 (use (match_operand:DI 2 "register_operand" ""))]
1165 "! TARGET_ABI_OPEN_VMS"
1167 if (TARGET_ABI_UNICOSMK)
1168 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
1170 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
1174 (define_expand "umoddi3_dft"
1175 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1176 (umod:DI (match_operand:DI 1 "register_operand" "")
1177 (match_operand:DI 2 "register_operand" "")))
1178 (clobber (reg:DI 23))
1179 (clobber (reg:DI 28))])]
1180 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1183 (define_expand "umoddi3_umk"
1184 [(use (match_operand:DI 0 "register_operand" ""))
1185 (use (match_operand:DI 1 "register_operand" ""))
1186 (use (match_operand:DI 2 "register_operand" ""))]
1187 "TARGET_ABI_UNICOSMK"
1189 rtx div, mul = gen_reg_rtx (DImode);
1191 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
1192 NULL_RTX, 1, OPTAB_LIB);
1193 div = force_reg (DImode, div);
1194 emit_insn (gen_muldi3 (mul, operands[2], div));
1195 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1199 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1200 ;; expanded by the assembler.
1202 (define_insn_and_split "*divmodsi_internal_er"
1203 [(set (match_operand:DI 0 "register_operand" "=c")
1204 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1205 [(match_operand:DI 1 "register_operand" "a")
1206 (match_operand:DI 2 "register_operand" "b")])))
1207 (clobber (reg:DI 23))
1208 (clobber (reg:DI 28))]
1209 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1210 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1211 "&& reload_completed"
1212 [(parallel [(set (match_dup 0)
1213 (sign_extend:DI (match_dup 3)))
1216 (clobber (reg:DI 23))
1217 (clobber (reg:DI 28))])]
1220 switch (GET_CODE (operands[3]))
1237 operands[4] = GEN_INT (alpha_next_sequence_number++);
1238 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1239 gen_rtx_SYMBOL_REF (DImode, str),
1242 [(set_attr "type" "jsr")
1243 (set_attr "length" "8")])
1245 (define_insn "*divmodsi_internal_er_1"
1246 [(set (match_operand:DI 0 "register_operand" "=c")
1247 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1248 [(match_operand:DI 1 "register_operand" "a")
1249 (match_operand:DI 2 "register_operand" "b")])))
1250 (use (match_operand:DI 4 "register_operand" "c"))
1251 (use (match_operand 5 "const_int_operand" ""))
1252 (clobber (reg:DI 23))
1253 (clobber (reg:DI 28))]
1254 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1255 "jsr $23,($27),__%E3%J5"
1256 [(set_attr "type" "jsr")
1257 (set_attr "length" "4")])
1259 (define_insn "*divmodsi_internal"
1260 [(set (match_operand:DI 0 "register_operand" "=c")
1261 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1262 [(match_operand:DI 1 "register_operand" "a")
1263 (match_operand:DI 2 "register_operand" "b")])))
1264 (clobber (reg:DI 23))
1265 (clobber (reg:DI 28))]
1266 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1268 [(set_attr "type" "jsr")
1269 (set_attr "length" "8")])
1271 (define_insn_and_split "*divmoddi_internal_er"
1272 [(set (match_operand:DI 0 "register_operand" "=c")
1273 (match_operator:DI 3 "divmod_operator"
1274 [(match_operand:DI 1 "register_operand" "a")
1275 (match_operand:DI 2 "register_operand" "b")]))
1276 (clobber (reg:DI 23))
1277 (clobber (reg:DI 28))]
1278 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1279 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1280 "&& reload_completed"
1281 [(parallel [(set (match_dup 0) (match_dup 3))
1284 (clobber (reg:DI 23))
1285 (clobber (reg:DI 28))])]
1288 switch (GET_CODE (operands[3]))
1305 operands[4] = GEN_INT (alpha_next_sequence_number++);
1306 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1307 gen_rtx_SYMBOL_REF (DImode, str),
1310 [(set_attr "type" "jsr")
1311 (set_attr "length" "8")])
1313 (define_insn "*divmoddi_internal_er_1"
1314 [(set (match_operand:DI 0 "register_operand" "=c")
1315 (match_operator:DI 3 "divmod_operator"
1316 [(match_operand:DI 1 "register_operand" "a")
1317 (match_operand:DI 2 "register_operand" "b")]))
1318 (use (match_operand:DI 4 "register_operand" "c"))
1319 (use (match_operand 5 "const_int_operand" ""))
1320 (clobber (reg:DI 23))
1321 (clobber (reg:DI 28))]
1322 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1323 "jsr $23,($27),__%E3%J5"
1324 [(set_attr "type" "jsr")
1325 (set_attr "length" "4")])
1327 (define_insn "*divmoddi_internal"
1328 [(set (match_operand:DI 0 "register_operand" "=c")
1329 (match_operator:DI 3 "divmod_operator"
1330 [(match_operand:DI 1 "register_operand" "a")
1331 (match_operand:DI 2 "register_operand" "b")]))
1332 (clobber (reg:DI 23))
1333 (clobber (reg:DI 28))]
1334 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1336 [(set_attr "type" "jsr")
1337 (set_attr "length" "8")])
1339 ;; Next are the basic logical operations. These only exist in DImode.
1341 (define_insn "anddi3"
1342 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1343 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1344 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1350 [(set_attr "type" "ilog,ilog,shift")])
1352 ;; There are times when we can split an AND into two AND insns. This occurs
1353 ;; when we can first clear any bytes and then clear anything else. For
1354 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1355 ;; Only do this when running on 64-bit host since the computations are
1356 ;; too messy otherwise.
1359 [(set (match_operand:DI 0 "register_operand" "")
1360 (and:DI (match_operand:DI 1 "register_operand" "")
1361 (match_operand:DI 2 "const_int_operand" "")))]
1362 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1363 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1364 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1366 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1367 unsigned HOST_WIDE_INT mask2 = mask1;
1370 /* For each byte that isn't all zeros, make it all ones. */
1371 for (i = 0; i < 64; i += 8)
1372 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1373 mask1 |= (HOST_WIDE_INT) 0xff << i;
1375 /* Now turn on any bits we've just turned off. */
1378 operands[3] = GEN_INT (mask1);
1379 operands[4] = GEN_INT (mask2);
1382 (define_expand "zero_extendqihi2"
1383 [(set (match_operand:HI 0 "register_operand" "")
1384 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1388 operands[1] = force_reg (QImode, operands[1]);
1391 (define_insn "*zero_extendqihi2_bwx"
1392 [(set (match_operand:HI 0 "register_operand" "=r,r")
1393 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1398 [(set_attr "type" "ilog,ild")])
1400 (define_insn "*zero_extendqihi2_nobwx"
1401 [(set (match_operand:HI 0 "register_operand" "=r")
1402 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1405 [(set_attr "type" "ilog")])
1407 (define_expand "zero_extendqisi2"
1408 [(set (match_operand:SI 0 "register_operand" "")
1409 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1413 operands[1] = force_reg (QImode, operands[1]);
1416 (define_insn "*zero_extendqisi2_bwx"
1417 [(set (match_operand:SI 0 "register_operand" "=r,r")
1418 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1423 [(set_attr "type" "ilog,ild")])
1425 (define_insn "*zero_extendqisi2_nobwx"
1426 [(set (match_operand:SI 0 "register_operand" "=r")
1427 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1430 [(set_attr "type" "ilog")])
1432 (define_expand "zero_extendqidi2"
1433 [(set (match_operand:DI 0 "register_operand" "")
1434 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1438 operands[1] = force_reg (QImode, operands[1]);
1441 (define_insn "*zero_extendqidi2_bwx"
1442 [(set (match_operand:DI 0 "register_operand" "=r,r")
1443 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1448 [(set_attr "type" "ilog,ild")])
1450 (define_insn "*zero_extendqidi2_nobwx"
1451 [(set (match_operand:DI 0 "register_operand" "=r")
1452 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1455 [(set_attr "type" "ilog")])
1457 (define_expand "zero_extendhisi2"
1458 [(set (match_operand:SI 0 "register_operand" "")
1459 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1463 operands[1] = force_reg (HImode, operands[1]);
1466 (define_insn "*zero_extendhisi2_bwx"
1467 [(set (match_operand:SI 0 "register_operand" "=r,r")
1468 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1473 [(set_attr "type" "shift,ild")])
1475 (define_insn "*zero_extendhisi2_nobwx"
1476 [(set (match_operand:SI 0 "register_operand" "=r")
1477 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1480 [(set_attr "type" "shift")])
1482 (define_expand "zero_extendhidi2"
1483 [(set (match_operand:DI 0 "register_operand" "")
1484 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1488 operands[1] = force_reg (HImode, operands[1]);
1491 (define_insn "*zero_extendhidi2_bwx"
1492 [(set (match_operand:DI 0 "register_operand" "=r,r")
1493 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1498 [(set_attr "type" "shift,ild")])
1500 (define_insn "*zero_extendhidi2_nobwx"
1501 [(set (match_operand:DI 0 "register_operand" "=r")
1502 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1505 [(set_attr "type" "shift")])
1507 (define_insn "zero_extendsidi2"
1508 [(set (match_operand:DI 0 "register_operand" "=r")
1509 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1512 [(set_attr "type" "shift")])
1514 (define_insn "andnotdi3"
1515 [(set (match_operand:DI 0 "register_operand" "=r")
1516 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1517 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1520 [(set_attr "type" "ilog")])
1522 (define_insn "iordi3"
1523 [(set (match_operand:DI 0 "register_operand" "=r,r")
1524 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1525 (match_operand:DI 2 "or_operand" "rI,N")))]
1530 [(set_attr "type" "ilog")])
1532 (define_insn "one_cmpldi2"
1533 [(set (match_operand:DI 0 "register_operand" "=r")
1534 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1537 [(set_attr "type" "ilog")])
1539 (define_insn "*iornot"
1540 [(set (match_operand:DI 0 "register_operand" "=r")
1541 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1542 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1545 [(set_attr "type" "ilog")])
1547 (define_insn "xordi3"
1548 [(set (match_operand:DI 0 "register_operand" "=r,r")
1549 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1550 (match_operand:DI 2 "or_operand" "rI,N")))]
1555 [(set_attr "type" "ilog")])
1557 (define_insn "*xornot"
1558 [(set (match_operand:DI 0 "register_operand" "=r")
1559 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1560 (match_operand:DI 2 "register_operand" "rI"))))]
1563 [(set_attr "type" "ilog")])
1565 ;; Handle the FFS insn iff we support CIX.
1567 (define_expand "ffsdi2"
1569 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1571 (plus:DI (match_dup 2) (const_int 1)))
1572 (set (match_operand:DI 0 "register_operand" "")
1573 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1574 (const_int 0) (match_dup 3)))]
1577 operands[2] = gen_reg_rtx (DImode);
1578 operands[3] = gen_reg_rtx (DImode);
1581 (define_insn "*cttz"
1582 [(set (match_operand:DI 0 "register_operand" "=r")
1583 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1586 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1587 ; reuse the existing type name.
1588 [(set_attr "type" "mvi")])
1590 ;; Next come the shifts and the various extract and insert operations.
1592 (define_insn "ashldi3"
1593 [(set (match_operand:DI 0 "register_operand" "=r,r")
1594 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1595 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1598 switch (which_alternative)
1601 if (operands[2] == const1_rtx)
1602 return "addq %r1,%r1,%0";
1604 return "s%P2addq %r1,0,%0";
1606 return "sll %r1,%2,%0";
1611 [(set_attr "type" "iadd,shift")])
1613 ;; ??? The following pattern is made by combine, but earlier phases
1614 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1615 ;; with this in a better way at some point.
1617 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1619 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1620 ;; (match_operand:DI 2 "const_int_operand" "P"))
1622 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1624 ;; if (operands[2] == const1_rtx)
1625 ;; return "addl %r1,%r1,%0";
1627 ;; return "s%P2addl %r1,0,%0";
1629 ;; [(set_attr "type" "iadd")])
1631 (define_insn "lshrdi3"
1632 [(set (match_operand:DI 0 "register_operand" "=r")
1633 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1634 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1637 [(set_attr "type" "shift")])
1639 (define_insn "ashrdi3"
1640 [(set (match_operand:DI 0 "register_operand" "=r")
1641 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1642 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1645 [(set_attr "type" "shift")])
1647 (define_expand "extendqihi2"
1649 (ashift:DI (match_operand:QI 1 "some_operand" "")
1651 (set (match_operand:HI 0 "register_operand" "")
1652 (ashiftrt:DI (match_dup 2)
1658 emit_insn (gen_extendqihi2x (operands[0],
1659 force_reg (QImode, operands[1])));
1663 /* If we have an unaligned MEM, extend to DImode (which we do
1664 specially) and then copy to the result. */
1665 if (unaligned_memory_operand (operands[1], HImode))
1667 rtx temp = gen_reg_rtx (DImode);
1669 emit_insn (gen_extendqidi2 (temp, operands[1]));
1670 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1674 operands[0] = gen_lowpart (DImode, operands[0]);
1675 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1676 operands[2] = gen_reg_rtx (DImode);
1679 (define_insn "extendqidi2x"
1680 [(set (match_operand:DI 0 "register_operand" "=r")
1681 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1684 [(set_attr "type" "shift")])
1686 (define_insn "extendhidi2x"
1687 [(set (match_operand:DI 0 "register_operand" "=r")
1688 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1691 [(set_attr "type" "shift")])
1693 (define_insn "extendqisi2x"
1694 [(set (match_operand:SI 0 "register_operand" "=r")
1695 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1698 [(set_attr "type" "shift")])
1700 (define_insn "extendhisi2x"
1701 [(set (match_operand:SI 0 "register_operand" "=r")
1702 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1705 [(set_attr "type" "shift")])
1707 (define_insn "extendqihi2x"
1708 [(set (match_operand:HI 0 "register_operand" "=r")
1709 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1712 [(set_attr "type" "shift")])
1714 (define_expand "extendqisi2"
1716 (ashift:DI (match_operand:QI 1 "some_operand" "")
1718 (set (match_operand:SI 0 "register_operand" "")
1719 (ashiftrt:DI (match_dup 2)
1725 emit_insn (gen_extendqisi2x (operands[0],
1726 force_reg (QImode, operands[1])));
1730 /* If we have an unaligned MEM, extend to a DImode form of
1731 the result (which we do specially). */
1732 if (unaligned_memory_operand (operands[1], QImode))
1734 rtx temp = gen_reg_rtx (DImode);
1736 emit_insn (gen_extendqidi2 (temp, operands[1]));
1737 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1741 operands[0] = gen_lowpart (DImode, operands[0]);
1742 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1743 operands[2] = gen_reg_rtx (DImode);
1746 (define_expand "extendqidi2"
1748 (ashift:DI (match_operand:QI 1 "some_operand" "")
1750 (set (match_operand:DI 0 "register_operand" "")
1751 (ashiftrt:DI (match_dup 2)
1757 emit_insn (gen_extendqidi2x (operands[0],
1758 force_reg (QImode, operands[1])));
1762 if (unaligned_memory_operand (operands[1], QImode))
1765 = gen_unaligned_extendqidi (operands[0],
1766 get_unaligned_address (operands[1], 1));
1768 alpha_set_memflags (seq, operands[1]);
1773 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1774 operands[2] = gen_reg_rtx (DImode);
1777 (define_expand "extendhisi2"
1779 (ashift:DI (match_operand:HI 1 "some_operand" "")
1781 (set (match_operand:SI 0 "register_operand" "")
1782 (ashiftrt:DI (match_dup 2)
1788 emit_insn (gen_extendhisi2x (operands[0],
1789 force_reg (HImode, operands[1])));
1793 /* If we have an unaligned MEM, extend to a DImode form of
1794 the result (which we do specially). */
1795 if (unaligned_memory_operand (operands[1], HImode))
1797 rtx temp = gen_reg_rtx (DImode);
1799 emit_insn (gen_extendhidi2 (temp, operands[1]));
1800 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1804 operands[0] = gen_lowpart (DImode, operands[0]);
1805 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1806 operands[2] = gen_reg_rtx (DImode);
1809 (define_expand "extendhidi2"
1811 (ashift:DI (match_operand:HI 1 "some_operand" "")
1813 (set (match_operand:DI 0 "register_operand" "")
1814 (ashiftrt:DI (match_dup 2)
1820 emit_insn (gen_extendhidi2x (operands[0],
1821 force_reg (HImode, operands[1])));
1825 if (unaligned_memory_operand (operands[1], HImode))
1828 = gen_unaligned_extendhidi (operands[0],
1829 get_unaligned_address (operands[1], 2));
1831 alpha_set_memflags (seq, operands[1]);
1836 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1837 operands[2] = gen_reg_rtx (DImode);
1840 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1841 ;; as a pattern saves one instruction. The code is similar to that for
1842 ;; the unaligned loads (see below).
1844 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1845 (define_expand "unaligned_extendqidi"
1846 [(use (match_operand:QI 0 "register_operand" ""))
1847 (use (match_operand:DI 1 "address_operand" ""))]
1850 if (WORDS_BIG_ENDIAN)
1851 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1853 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1857 (define_expand "unaligned_extendqidi_le"
1858 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1860 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1863 (ashift:DI (match_dup 3)
1864 (minus:DI (const_int 64)
1866 (and:DI (match_dup 2) (const_int 7))
1868 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1869 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1870 "! WORDS_BIG_ENDIAN"
1872 operands[2] = gen_reg_rtx (DImode);
1873 operands[3] = gen_reg_rtx (DImode);
1874 operands[4] = gen_reg_rtx (DImode);
1877 (define_expand "unaligned_extendqidi_be"
1878 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1879 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1881 (mem:DI (and:DI (match_dup 3)
1883 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1885 (ashift:DI (match_dup 4)
1888 (plus:DI (match_dup 5) (const_int 1))
1891 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1892 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1895 operands[2] = gen_reg_rtx (DImode);
1896 operands[3] = gen_reg_rtx (DImode);
1897 operands[4] = gen_reg_rtx (DImode);
1898 operands[5] = gen_reg_rtx (DImode);
1899 operands[6] = gen_reg_rtx (DImode);
1902 (define_expand "unaligned_extendhidi"
1903 [(use (match_operand:QI 0 "register_operand" ""))
1904 (use (match_operand:DI 1 "address_operand" ""))]
1907 operands[0] = gen_lowpart (DImode, operands[0]);
1908 emit_insn ((WORDS_BIG_ENDIAN
1909 ? gen_unaligned_extendhidi_be
1910 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1914 (define_expand "unaligned_extendhidi_le"
1915 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1917 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1920 (ashift:DI (match_dup 3)
1921 (minus:DI (const_int 64)
1923 (and:DI (match_dup 2) (const_int 7))
1925 (set (match_operand:DI 0 "register_operand" "")
1926 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1927 "! WORDS_BIG_ENDIAN"
1929 operands[2] = gen_reg_rtx (DImode);
1930 operands[3] = gen_reg_rtx (DImode);
1931 operands[4] = gen_reg_rtx (DImode);
1934 (define_expand "unaligned_extendhidi_be"
1935 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1936 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1938 (mem:DI (and:DI (match_dup 3)
1940 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1942 (ashift:DI (match_dup 4)
1945 (plus:DI (match_dup 5) (const_int 1))
1948 (set (match_operand:DI 0 "register_operand" "")
1949 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1952 operands[2] = gen_reg_rtx (DImode);
1953 operands[3] = gen_reg_rtx (DImode);
1954 operands[4] = gen_reg_rtx (DImode);
1955 operands[5] = gen_reg_rtx (DImode);
1956 operands[6] = gen_reg_rtx (DImode);
1959 (define_insn "*extxl_const"
1960 [(set (match_operand:DI 0 "register_operand" "=r")
1961 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1962 (match_operand:DI 2 "mode_width_operand" "n")
1963 (match_operand:DI 3 "mul8_operand" "I")))]
1965 "ext%M2l %r1,%s3,%0"
1966 [(set_attr "type" "shift")])
1968 (define_insn "extxl_le"
1969 [(set (match_operand:DI 0 "register_operand" "=r")
1970 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1971 (match_operand:DI 2 "mode_width_operand" "n")
1972 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1974 "! WORDS_BIG_ENDIAN"
1976 [(set_attr "type" "shift")])
1978 (define_insn "extxl_be"
1979 [(set (match_operand:DI 0 "register_operand" "=r")
1980 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1981 (match_operand:DI 2 "mode_width_operand" "n")
1985 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1989 [(set_attr "type" "shift")])
1991 ;; Combine has some strange notion of preserving existing undefined behaviour
1992 ;; in shifts larger than a word size. So capture these patterns that it
1993 ;; should have turned into zero_extracts.
1995 (define_insn "*extxl_1_le"
1996 [(set (match_operand:DI 0 "register_operand" "=r")
1997 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1998 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2000 (match_operand:DI 3 "mode_mask_operand" "n")))]
2001 "! WORDS_BIG_ENDIAN"
2003 [(set_attr "type" "shift")])
2005 (define_insn "*extxl_1_be"
2006 [(set (match_operand:DI 0 "register_operand" "=r")
2007 (and:DI (lshiftrt:DI
2008 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2009 (minus:DI (const_int 56)
2010 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2012 (match_operand:DI 3 "mode_mask_operand" "n")))]
2015 [(set_attr "type" "shift")])
2017 (define_insn "*extql_2_le"
2018 [(set (match_operand:DI 0 "register_operand" "=r")
2019 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2020 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2022 "! WORDS_BIG_ENDIAN"
2024 [(set_attr "type" "shift")])
2026 (define_insn "*extql_2_be"
2027 [(set (match_operand:DI 0 "register_operand" "=r")
2029 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2030 (minus:DI (const_int 56)
2032 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2036 [(set_attr "type" "shift")])
2038 (define_insn "extqh_le"
2039 [(set (match_operand:DI 0 "register_operand" "=r")
2041 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2042 (minus:DI (const_int 64)
2045 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2048 "! WORDS_BIG_ENDIAN"
2050 [(set_attr "type" "shift")])
2052 (define_insn "extqh_be"
2053 [(set (match_operand:DI 0 "register_operand" "=r")
2055 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2058 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2064 [(set_attr "type" "shift")])
2066 (define_insn "extlh_le"
2067 [(set (match_operand:DI 0 "register_operand" "=r")
2069 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2070 (const_int 2147483647))
2071 (minus:DI (const_int 64)
2074 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2077 "! WORDS_BIG_ENDIAN"
2079 [(set_attr "type" "shift")])
2081 (define_insn "extlh_be"
2082 [(set (match_operand:DI 0 "register_operand" "=r")
2085 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2089 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2093 (const_int 2147483647)))]
2096 [(set_attr "type" "shift")])
2098 (define_insn "extwh_le"
2099 [(set (match_operand:DI 0 "register_operand" "=r")
2101 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2103 (minus:DI (const_int 64)
2106 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2109 "! WORDS_BIG_ENDIAN"
2111 [(set_attr "type" "shift")])
2113 (define_insn "extwh_be"
2114 [(set (match_operand:DI 0 "register_operand" "=r")
2116 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2120 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2124 (const_int 65535)))]
2127 [(set_attr "type" "shift")])
2129 ;; This converts an extXl into an extXh with an appropriate adjustment
2130 ;; to the address calculation.
2133 ;; [(set (match_operand:DI 0 "register_operand" "")
2134 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2135 ;; (match_operand:DI 2 "mode_width_operand" "")
2136 ;; (ashift:DI (match_operand:DI 3 "" "")
2138 ;; (match_operand:DI 4 "const_int_operand" "")))
2139 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2140 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2141 ;; [(set (match_dup 5) (match_dup 6))
2142 ;; (set (match_dup 0)
2143 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2144 ;; (ashift:DI (plus:DI (match_dup 5)
2150 ;; operands[6] = plus_constant (operands[3],
2151 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2152 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2155 (define_insn "*insbl_const"
2156 [(set (match_operand:DI 0 "register_operand" "=r")
2157 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2158 (match_operand:DI 2 "mul8_operand" "I")))]
2161 [(set_attr "type" "shift")])
2163 (define_insn "*inswl_const"
2164 [(set (match_operand:DI 0 "register_operand" "=r")
2165 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2166 (match_operand:DI 2 "mul8_operand" "I")))]
2169 [(set_attr "type" "shift")])
2171 (define_insn "*insll_const"
2172 [(set (match_operand:DI 0 "register_operand" "=r")
2173 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2174 (match_operand:DI 2 "mul8_operand" "I")))]
2177 [(set_attr "type" "shift")])
2179 (define_insn "insbl_le"
2180 [(set (match_operand:DI 0 "register_operand" "=r")
2181 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2182 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2184 "! WORDS_BIG_ENDIAN"
2186 [(set_attr "type" "shift")])
2188 (define_insn "insbl_be"
2189 [(set (match_operand:DI 0 "register_operand" "=r")
2190 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2191 (minus:DI (const_int 56)
2192 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2196 [(set_attr "type" "shift")])
2198 (define_insn "inswl_le"
2199 [(set (match_operand:DI 0 "register_operand" "=r")
2200 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2201 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2203 "! WORDS_BIG_ENDIAN"
2205 [(set_attr "type" "shift")])
2207 (define_insn "inswl_be"
2208 [(set (match_operand:DI 0 "register_operand" "=r")
2209 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2210 (minus:DI (const_int 56)
2211 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2215 [(set_attr "type" "shift")])
2217 (define_insn "insll_le"
2218 [(set (match_operand:DI 0 "register_operand" "=r")
2219 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2220 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2222 "! WORDS_BIG_ENDIAN"
2224 [(set_attr "type" "shift")])
2226 (define_insn "insll_be"
2227 [(set (match_operand:DI 0 "register_operand" "=r")
2228 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2229 (minus:DI (const_int 56)
2230 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2234 [(set_attr "type" "shift")])
2236 (define_insn "insql_le"
2237 [(set (match_operand:DI 0 "register_operand" "=r")
2238 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2239 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2241 "! WORDS_BIG_ENDIAN"
2243 [(set_attr "type" "shift")])
2245 (define_insn "insql_be"
2246 [(set (match_operand:DI 0 "register_operand" "=r")
2247 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2248 (minus:DI (const_int 56)
2249 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2253 [(set_attr "type" "shift")])
2255 ;; Combine has this sometimes habit of moving the and outside of the
2256 ;; shift, making life more interesting.
2258 (define_insn "*insxl"
2259 [(set (match_operand:DI 0 "register_operand" "=r")
2260 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2261 (match_operand:DI 2 "mul8_operand" "I"))
2262 (match_operand:DI 3 "immediate_operand" "i")))]
2263 "HOST_BITS_PER_WIDE_INT == 64
2264 && GET_CODE (operands[3]) == CONST_INT
2265 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2266 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2267 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2268 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2269 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2270 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2272 #if HOST_BITS_PER_WIDE_INT == 64
2273 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2274 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2275 return "insbl %1,%s2,%0";
2276 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2277 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2278 return "inswl %1,%s2,%0";
2279 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2280 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2281 return "insll %1,%s2,%0";
2285 [(set_attr "type" "shift")])
2287 ;; We do not include the insXh insns because they are complex to express
2288 ;; and it does not appear that we would ever want to generate them.
2290 ;; Since we need them for block moves, though, cop out and use unspec.
2292 (define_insn "insxh"
2293 [(set (match_operand:DI 0 "register_operand" "=r")
2294 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2295 (match_operand:DI 2 "mode_width_operand" "n")
2296 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2300 [(set_attr "type" "shift")])
2302 (define_insn "mskxl_le"
2303 [(set (match_operand:DI 0 "register_operand" "=r")
2304 (and:DI (not:DI (ashift:DI
2305 (match_operand:DI 2 "mode_mask_operand" "n")
2307 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2309 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2310 "! WORDS_BIG_ENDIAN"
2312 [(set_attr "type" "shift")])
2314 (define_insn "mskxl_be"
2315 [(set (match_operand:DI 0 "register_operand" "=r")
2316 (and:DI (not:DI (ashift:DI
2317 (match_operand:DI 2 "mode_mask_operand" "n")
2318 (minus:DI (const_int 56)
2320 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2322 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2325 [(set_attr "type" "shift")])
2327 ;; We do not include the mskXh insns because it does not appear we would
2328 ;; ever generate one.
2330 ;; Again, we do for block moves and we use unspec again.
2332 (define_insn "mskxh"
2333 [(set (match_operand:DI 0 "register_operand" "=r")
2334 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2335 (match_operand:DI 2 "mode_width_operand" "n")
2336 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2340 [(set_attr "type" "shift")])
2342 ;; Prefer AND + NE over LSHIFTRT + AND.
2344 (define_insn_and_split "*ze_and_ne"
2345 [(set (match_operand:DI 0 "register_operand" "=r")
2346 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2348 (match_operand 2 "const_int_operand" "I")))]
2349 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2351 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2353 (and:DI (match_dup 1) (match_dup 3)))
2355 (ne:DI (match_dup 0) (const_int 0)))]
2356 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2358 ;; Floating-point operations. All the double-precision insns can extend
2359 ;; from single, so indicate that. The exception are the ones that simply
2360 ;; play with the sign bits; it's not clear what to do there.
2362 (define_insn "abssf2"
2363 [(set (match_operand:SF 0 "register_operand" "=f")
2364 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2367 [(set_attr "type" "fcpys")])
2369 (define_insn "*nabssf2"
2370 [(set (match_operand:SF 0 "register_operand" "=f")
2371 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2374 [(set_attr "type" "fadd")])
2376 (define_insn "absdf2"
2377 [(set (match_operand:DF 0 "register_operand" "=f")
2378 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2381 [(set_attr "type" "fcpys")])
2383 (define_insn "*nabsdf2"
2384 [(set (match_operand:DF 0 "register_operand" "=f")
2385 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2388 [(set_attr "type" "fadd")])
2390 (define_expand "abstf2"
2391 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2392 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2393 (use (match_dup 2))])]
2394 "TARGET_HAS_XFLOATING_LIBS"
2396 #if HOST_BITS_PER_WIDE_INT >= 64
2397 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2399 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2403 (define_insn_and_split "*abstf_internal"
2404 [(set (match_operand:TF 0 "register_operand" "=r")
2405 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2406 (use (match_operand:DI 2 "register_operand" "r"))]
2407 "TARGET_HAS_XFLOATING_LIBS"
2409 "&& reload_completed"
2411 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2413 (define_insn "negsf2"
2414 [(set (match_operand:SF 0 "register_operand" "=f")
2415 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2418 [(set_attr "type" "fadd")])
2420 (define_insn "negdf2"
2421 [(set (match_operand:DF 0 "register_operand" "=f")
2422 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2425 [(set_attr "type" "fadd")])
2427 (define_expand "negtf2"
2428 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2429 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2430 (use (match_dup 2))])]
2431 "TARGET_HAS_XFLOATING_LIBS"
2433 #if HOST_BITS_PER_WIDE_INT >= 64
2434 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2436 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2440 (define_insn_and_split "*negtf_internal"
2441 [(set (match_operand:TF 0 "register_operand" "=r")
2442 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2443 (use (match_operand:DI 2 "register_operand" "r"))]
2444 "TARGET_HAS_XFLOATING_LIBS"
2446 "&& reload_completed"
2448 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2450 (define_insn "*addsf_ieee"
2451 [(set (match_operand:SF 0 "register_operand" "=&f")
2452 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2453 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2454 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2455 "add%,%/ %R1,%R2,%0"
2456 [(set_attr "type" "fadd")
2457 (set_attr "trap" "yes")
2458 (set_attr "round_suffix" "normal")
2459 (set_attr "trap_suffix" "u_su_sui")])
2461 (define_insn "addsf3"
2462 [(set (match_operand:SF 0 "register_operand" "=f")
2463 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2464 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2466 "add%,%/ %R1,%R2,%0"
2467 [(set_attr "type" "fadd")
2468 (set_attr "trap" "yes")
2469 (set_attr "round_suffix" "normal")
2470 (set_attr "trap_suffix" "u_su_sui")])
2472 (define_insn "*adddf_ieee"
2473 [(set (match_operand:DF 0 "register_operand" "=&f")
2474 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2475 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2476 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2477 "add%-%/ %R1,%R2,%0"
2478 [(set_attr "type" "fadd")
2479 (set_attr "trap" "yes")
2480 (set_attr "round_suffix" "normal")
2481 (set_attr "trap_suffix" "u_su_sui")])
2483 (define_insn "adddf3"
2484 [(set (match_operand:DF 0 "register_operand" "=f")
2485 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2486 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2488 "add%-%/ %R1,%R2,%0"
2489 [(set_attr "type" "fadd")
2490 (set_attr "trap" "yes")
2491 (set_attr "round_suffix" "normal")
2492 (set_attr "trap_suffix" "u_su_sui")])
2494 (define_insn "*adddf_ext1"
2495 [(set (match_operand:DF 0 "register_operand" "=f")
2496 (plus:DF (float_extend:DF
2497 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2498 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2499 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2500 "add%-%/ %R1,%R2,%0"
2501 [(set_attr "type" "fadd")
2502 (set_attr "trap" "yes")
2503 (set_attr "round_suffix" "normal")
2504 (set_attr "trap_suffix" "u_su_sui")])
2506 (define_insn "*adddf_ext2"
2507 [(set (match_operand:DF 0 "register_operand" "=f")
2508 (plus:DF (float_extend:DF
2509 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2511 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2512 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2513 "add%-%/ %R1,%R2,%0"
2514 [(set_attr "type" "fadd")
2515 (set_attr "trap" "yes")
2516 (set_attr "round_suffix" "normal")
2517 (set_attr "trap_suffix" "u_su_sui")])
2519 (define_expand "addtf3"
2520 [(use (match_operand 0 "register_operand" ""))
2521 (use (match_operand 1 "general_operand" ""))
2522 (use (match_operand 2 "general_operand" ""))]
2523 "TARGET_HAS_XFLOATING_LIBS"
2524 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2526 ;; Define conversion operators between DFmode and SImode, using the cvtql
2527 ;; instruction. To allow combine et al to do useful things, we keep the
2528 ;; operation as a unit until after reload, at which point we split the
2531 ;; Note that we (attempt to) only consider this optimization when the
2532 ;; ultimate destination is memory. If we will be doing further integer
2533 ;; processing, it is cheaper to do the truncation in the int regs.
2535 (define_insn "*cvtql"
2536 [(set (match_operand:SI 0 "register_operand" "=f")
2537 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2541 [(set_attr "type" "fadd")
2542 (set_attr "trap" "yes")
2543 (set_attr "trap_suffix" "v_sv")])
2545 (define_insn_and_split "*fix_truncdfsi_ieee"
2546 [(set (match_operand:SI 0 "memory_operand" "=m")
2547 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2548 (clobber (match_scratch:DI 2 "=&f"))
2549 (clobber (match_scratch:SI 3 "=&f"))]
2550 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2552 "&& reload_completed"
2553 [(set (match_dup 2) (fix:DI (match_dup 1)))
2554 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2555 (set (match_dup 0) (match_dup 3))]
2557 [(set_attr "type" "fadd")
2558 (set_attr "trap" "yes")])
2560 (define_insn_and_split "*fix_truncdfsi_internal"
2561 [(set (match_operand:SI 0 "memory_operand" "=m")
2562 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2563 (clobber (match_scratch:DI 2 "=f"))]
2564 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2566 "&& reload_completed"
2567 [(set (match_dup 2) (fix:DI (match_dup 1)))
2568 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2569 (set (match_dup 0) (match_dup 3))]
2570 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2571 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2572 [(set_attr "type" "fadd")
2573 (set_attr "trap" "yes")])
2575 (define_insn "*fix_truncdfdi_ieee"
2576 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2577 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2578 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2580 [(set_attr "type" "fadd")
2581 (set_attr "trap" "yes")
2582 (set_attr "round_suffix" "c")
2583 (set_attr "trap_suffix" "v_sv_svi")])
2585 (define_insn "fix_truncdfdi2"
2586 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2587 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2590 [(set_attr "type" "fadd")
2591 (set_attr "trap" "yes")
2592 (set_attr "round_suffix" "c")
2593 (set_attr "trap_suffix" "v_sv_svi")])
2595 ;; Likewise between SFmode and SImode.
2597 (define_insn_and_split "*fix_truncsfsi_ieee"
2598 [(set (match_operand:SI 0 "memory_operand" "=m")
2599 (subreg:SI (fix:DI (float_extend:DF
2600 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2601 (clobber (match_scratch:DI 2 "=&f"))
2602 (clobber (match_scratch:SI 3 "=&f"))]
2603 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2605 "&& reload_completed"
2606 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2607 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2608 (set (match_dup 0) (match_dup 3))]
2610 [(set_attr "type" "fadd")
2611 (set_attr "trap" "yes")])
2613 (define_insn_and_split "*fix_truncsfsi_internal"
2614 [(set (match_operand:SI 0 "memory_operand" "=m")
2615 (subreg:SI (fix:DI (float_extend:DF
2616 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2617 (clobber (match_scratch:DI 2 "=f"))]
2618 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2620 "&& reload_completed"
2621 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2622 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2623 (set (match_dup 0) (match_dup 3))]
2624 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2625 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2626 [(set_attr "type" "fadd")
2627 (set_attr "trap" "yes")])
2629 (define_insn "*fix_truncsfdi_ieee"
2630 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2631 (fix:DI (float_extend:DF
2632 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2633 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2635 [(set_attr "type" "fadd")
2636 (set_attr "trap" "yes")
2637 (set_attr "round_suffix" "c")
2638 (set_attr "trap_suffix" "v_sv_svi")])
2640 (define_insn "fix_truncsfdi2"
2641 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2642 (fix:DI (float_extend:DF
2643 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2646 [(set_attr "type" "fadd")
2647 (set_attr "trap" "yes")
2648 (set_attr "round_suffix" "c")
2649 (set_attr "trap_suffix" "v_sv_svi")])
2651 (define_expand "fix_trunctfdi2"
2652 [(use (match_operand:DI 0 "register_operand" ""))
2653 (use (match_operand:TF 1 "general_operand" ""))]
2654 "TARGET_HAS_XFLOATING_LIBS"
2655 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2657 (define_insn "*floatdisf_ieee"
2658 [(set (match_operand:SF 0 "register_operand" "=&f")
2659 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2660 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2662 [(set_attr "type" "fadd")
2663 (set_attr "trap" "yes")
2664 (set_attr "round_suffix" "normal")
2665 (set_attr "trap_suffix" "sui")])
2667 (define_insn "floatdisf2"
2668 [(set (match_operand:SF 0 "register_operand" "=f")
2669 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2672 [(set_attr "type" "fadd")
2673 (set_attr "trap" "yes")
2674 (set_attr "round_suffix" "normal")
2675 (set_attr "trap_suffix" "sui")])
2677 (define_insn "*floatdidf_ieee"
2678 [(set (match_operand:DF 0 "register_operand" "=&f")
2679 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2680 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2682 [(set_attr "type" "fadd")
2683 (set_attr "trap" "yes")
2684 (set_attr "round_suffix" "normal")
2685 (set_attr "trap_suffix" "sui")])
2687 (define_insn "floatdidf2"
2688 [(set (match_operand:DF 0 "register_operand" "=f")
2689 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2692 [(set_attr "type" "fadd")
2693 (set_attr "trap" "yes")
2694 (set_attr "round_suffix" "normal")
2695 (set_attr "trap_suffix" "sui")])
2697 (define_expand "floatditf2"
2698 [(use (match_operand:TF 0 "register_operand" ""))
2699 (use (match_operand:DI 1 "general_operand" ""))]
2700 "TARGET_HAS_XFLOATING_LIBS"
2701 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2703 (define_expand "floatunsdisf2"
2704 [(use (match_operand:SF 0 "register_operand" ""))
2705 (use (match_operand:DI 1 "register_operand" ""))]
2707 "alpha_emit_floatuns (operands); DONE;")
2709 (define_expand "floatunsdidf2"
2710 [(use (match_operand:DF 0 "register_operand" ""))
2711 (use (match_operand:DI 1 "register_operand" ""))]
2713 "alpha_emit_floatuns (operands); DONE;")
2715 (define_expand "floatunsditf2"
2716 [(use (match_operand:TF 0 "register_operand" ""))
2717 (use (match_operand:DI 1 "general_operand" ""))]
2718 "TARGET_HAS_XFLOATING_LIBS"
2719 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2721 (define_expand "extendsfdf2"
2722 [(set (match_operand:DF 0 "register_operand" "")
2723 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2726 if (alpha_fptm >= ALPHA_FPTM_SU)
2727 operands[1] = force_reg (SFmode, operands[1]);
2730 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2731 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2733 (define_insn "*extendsfdf2_ieee"
2734 [(set (match_operand:DF 0 "register_operand" "=&f")
2735 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2736 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2738 [(set_attr "type" "fadd")
2739 (set_attr "trap" "yes")])
2741 (define_insn "*extendsfdf2_internal"
2742 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2743 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2744 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2749 [(set_attr "type" "fcpys,fld,fst")])
2751 (define_expand "extendsftf2"
2752 [(use (match_operand:TF 0 "register_operand" ""))
2753 (use (match_operand:SF 1 "general_operand" ""))]
2754 "TARGET_HAS_XFLOATING_LIBS"
2756 rtx tmp = gen_reg_rtx (DFmode);
2757 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2758 emit_insn (gen_extenddftf2 (operands[0], tmp));
2762 (define_expand "extenddftf2"
2763 [(use (match_operand:TF 0 "register_operand" ""))
2764 (use (match_operand:DF 1 "general_operand" ""))]
2765 "TARGET_HAS_XFLOATING_LIBS"
2766 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2768 (define_insn "*truncdfsf2_ieee"
2769 [(set (match_operand:SF 0 "register_operand" "=&f")
2770 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2771 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2773 [(set_attr "type" "fadd")
2774 (set_attr "trap" "yes")
2775 (set_attr "round_suffix" "normal")
2776 (set_attr "trap_suffix" "u_su_sui")])
2778 (define_insn "truncdfsf2"
2779 [(set (match_operand:SF 0 "register_operand" "=f")
2780 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2783 [(set_attr "type" "fadd")
2784 (set_attr "trap" "yes")
2785 (set_attr "round_suffix" "normal")
2786 (set_attr "trap_suffix" "u_su_sui")])
2788 (define_expand "trunctfdf2"
2789 [(use (match_operand:DF 0 "register_operand" ""))
2790 (use (match_operand:TF 1 "general_operand" ""))]
2791 "TARGET_HAS_XFLOATING_LIBS"
2792 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2794 (define_expand "trunctfsf2"
2795 [(use (match_operand:SF 0 "register_operand" ""))
2796 (use (match_operand:TF 1 "general_operand" ""))]
2797 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2799 rtx tmpf, sticky, arg, lo, hi;
2801 tmpf = gen_reg_rtx (DFmode);
2802 sticky = gen_reg_rtx (DImode);
2803 arg = copy_to_mode_reg (TFmode, operands[1]);
2804 lo = gen_lowpart (DImode, arg);
2805 hi = gen_highpart (DImode, arg);
2807 /* Convert the low word of the TFmode value into a sticky rounding bit,
2808 then or it into the low bit of the high word. This leaves the sticky
2809 bit at bit 48 of the fraction, which is representable in DFmode,
2810 which prevents rounding error in the final conversion to SFmode. */
2812 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2813 gen_rtx_NE (DImode, lo, const0_rtx)));
2814 emit_insn (gen_iordi3 (hi, hi, sticky));
2815 emit_insn (gen_trunctfdf2 (tmpf, arg));
2816 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2820 (define_insn "*divsf3_ieee"
2821 [(set (match_operand:SF 0 "register_operand" "=&f")
2822 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2823 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2824 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2825 "div%,%/ %R1,%R2,%0"
2826 [(set_attr "type" "fdiv")
2827 (set_attr "opsize" "si")
2828 (set_attr "trap" "yes")
2829 (set_attr "round_suffix" "normal")
2830 (set_attr "trap_suffix" "u_su_sui")])
2832 (define_insn "divsf3"
2833 [(set (match_operand:SF 0 "register_operand" "=f")
2834 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2835 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2837 "div%,%/ %R1,%R2,%0"
2838 [(set_attr "type" "fdiv")
2839 (set_attr "opsize" "si")
2840 (set_attr "trap" "yes")
2841 (set_attr "round_suffix" "normal")
2842 (set_attr "trap_suffix" "u_su_sui")])
2844 (define_insn "*divdf3_ieee"
2845 [(set (match_operand:DF 0 "register_operand" "=&f")
2846 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2847 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2848 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2849 "div%-%/ %R1,%R2,%0"
2850 [(set_attr "type" "fdiv")
2851 (set_attr "trap" "yes")
2852 (set_attr "round_suffix" "normal")
2853 (set_attr "trap_suffix" "u_su_sui")])
2855 (define_insn "divdf3"
2856 [(set (match_operand:DF 0 "register_operand" "=f")
2857 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2858 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2860 "div%-%/ %R1,%R2,%0"
2861 [(set_attr "type" "fdiv")
2862 (set_attr "trap" "yes")
2863 (set_attr "round_suffix" "normal")
2864 (set_attr "trap_suffix" "u_su_sui")])
2866 (define_insn "*divdf_ext1"
2867 [(set (match_operand:DF 0 "register_operand" "=f")
2868 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2869 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2870 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2871 "div%-%/ %R1,%R2,%0"
2872 [(set_attr "type" "fdiv")
2873 (set_attr "trap" "yes")
2874 (set_attr "round_suffix" "normal")
2875 (set_attr "trap_suffix" "u_su_sui")])
2877 (define_insn "*divdf_ext2"
2878 [(set (match_operand:DF 0 "register_operand" "=f")
2879 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2881 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2882 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2883 "div%-%/ %R1,%R2,%0"
2884 [(set_attr "type" "fdiv")
2885 (set_attr "trap" "yes")
2886 (set_attr "round_suffix" "normal")
2887 (set_attr "trap_suffix" "u_su_sui")])
2889 (define_insn "*divdf_ext3"
2890 [(set (match_operand:DF 0 "register_operand" "=f")
2891 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2892 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2893 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2894 "div%-%/ %R1,%R2,%0"
2895 [(set_attr "type" "fdiv")
2896 (set_attr "trap" "yes")
2897 (set_attr "round_suffix" "normal")
2898 (set_attr "trap_suffix" "u_su_sui")])
2900 (define_expand "divtf3"
2901 [(use (match_operand 0 "register_operand" ""))
2902 (use (match_operand 1 "general_operand" ""))
2903 (use (match_operand 2 "general_operand" ""))]
2904 "TARGET_HAS_XFLOATING_LIBS"
2905 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2907 (define_insn "*mulsf3_ieee"
2908 [(set (match_operand:SF 0 "register_operand" "=&f")
2909 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2910 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2911 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2912 "mul%,%/ %R1,%R2,%0"
2913 [(set_attr "type" "fmul")
2914 (set_attr "trap" "yes")
2915 (set_attr "round_suffix" "normal")
2916 (set_attr "trap_suffix" "u_su_sui")])
2918 (define_insn "mulsf3"
2919 [(set (match_operand:SF 0 "register_operand" "=f")
2920 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2921 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2923 "mul%,%/ %R1,%R2,%0"
2924 [(set_attr "type" "fmul")
2925 (set_attr "trap" "yes")
2926 (set_attr "round_suffix" "normal")
2927 (set_attr "trap_suffix" "u_su_sui")])
2929 (define_insn "*muldf3_ieee"
2930 [(set (match_operand:DF 0 "register_operand" "=&f")
2931 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2932 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2933 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2934 "mul%-%/ %R1,%R2,%0"
2935 [(set_attr "type" "fmul")
2936 (set_attr "trap" "yes")
2937 (set_attr "round_suffix" "normal")
2938 (set_attr "trap_suffix" "u_su_sui")])
2940 (define_insn "muldf3"
2941 [(set (match_operand:DF 0 "register_operand" "=f")
2942 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2943 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2945 "mul%-%/ %R1,%R2,%0"
2946 [(set_attr "type" "fmul")
2947 (set_attr "trap" "yes")
2948 (set_attr "round_suffix" "normal")
2949 (set_attr "trap_suffix" "u_su_sui")])
2951 (define_insn "*muldf_ext1"
2952 [(set (match_operand:DF 0 "register_operand" "=f")
2953 (mult:DF (float_extend:DF
2954 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2955 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2956 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2957 "mul%-%/ %R1,%R2,%0"
2958 [(set_attr "type" "fmul")
2959 (set_attr "trap" "yes")
2960 (set_attr "round_suffix" "normal")
2961 (set_attr "trap_suffix" "u_su_sui")])
2963 (define_insn "*muldf_ext2"
2964 [(set (match_operand:DF 0 "register_operand" "=f")
2965 (mult:DF (float_extend:DF
2966 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2968 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2969 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2970 "mul%-%/ %R1,%R2,%0"
2971 [(set_attr "type" "fmul")
2972 (set_attr "trap" "yes")
2973 (set_attr "round_suffix" "normal")
2974 (set_attr "trap_suffix" "u_su_sui")])
2976 (define_expand "multf3"
2977 [(use (match_operand 0 "register_operand" ""))
2978 (use (match_operand 1 "general_operand" ""))
2979 (use (match_operand 2 "general_operand" ""))]
2980 "TARGET_HAS_XFLOATING_LIBS"
2981 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2983 (define_insn "*subsf3_ieee"
2984 [(set (match_operand:SF 0 "register_operand" "=&f")
2985 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2986 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2987 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2988 "sub%,%/ %R1,%R2,%0"
2989 [(set_attr "type" "fadd")
2990 (set_attr "trap" "yes")
2991 (set_attr "round_suffix" "normal")
2992 (set_attr "trap_suffix" "u_su_sui")])
2994 (define_insn "subsf3"
2995 [(set (match_operand:SF 0 "register_operand" "=f")
2996 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2997 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2999 "sub%,%/ %R1,%R2,%0"
3000 [(set_attr "type" "fadd")
3001 (set_attr "trap" "yes")
3002 (set_attr "round_suffix" "normal")
3003 (set_attr "trap_suffix" "u_su_sui")])
3005 (define_insn "*subdf3_ieee"
3006 [(set (match_operand:DF 0 "register_operand" "=&f")
3007 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3008 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
3009 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3010 "sub%-%/ %R1,%R2,%0"
3011 [(set_attr "type" "fadd")
3012 (set_attr "trap" "yes")
3013 (set_attr "round_suffix" "normal")
3014 (set_attr "trap_suffix" "u_su_sui")])
3016 (define_insn "subdf3"
3017 [(set (match_operand:DF 0 "register_operand" "=f")
3018 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3019 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
3021 "sub%-%/ %R1,%R2,%0"
3022 [(set_attr "type" "fadd")
3023 (set_attr "trap" "yes")
3024 (set_attr "round_suffix" "normal")
3025 (set_attr "trap_suffix" "u_su_sui")])
3027 (define_insn "*subdf_ext1"
3028 [(set (match_operand:DF 0 "register_operand" "=f")
3029 (minus:DF (float_extend:DF
3030 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
3031 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
3032 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3033 "sub%-%/ %R1,%R2,%0"
3034 [(set_attr "type" "fadd")
3035 (set_attr "trap" "yes")
3036 (set_attr "round_suffix" "normal")
3037 (set_attr "trap_suffix" "u_su_sui")])
3039 (define_insn "*subdf_ext2"
3040 [(set (match_operand:DF 0 "register_operand" "=f")
3041 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3043 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3044 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3045 "sub%-%/ %R1,%R2,%0"
3046 [(set_attr "type" "fadd")
3047 (set_attr "trap" "yes")
3048 (set_attr "round_suffix" "normal")
3049 (set_attr "trap_suffix" "u_su_sui")])
3051 (define_insn "*subdf_ext3"
3052 [(set (match_operand:DF 0 "register_operand" "=f")
3053 (minus:DF (float_extend:DF
3054 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
3056 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3057 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3058 "sub%-%/ %R1,%R2,%0"
3059 [(set_attr "type" "fadd")
3060 (set_attr "trap" "yes")
3061 (set_attr "round_suffix" "normal")
3062 (set_attr "trap_suffix" "u_su_sui")])
3064 (define_expand "subtf3"
3065 [(use (match_operand 0 "register_operand" ""))
3066 (use (match_operand 1 "general_operand" ""))
3067 (use (match_operand 2 "general_operand" ""))]
3068 "TARGET_HAS_XFLOATING_LIBS"
3069 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3071 (define_insn "*sqrtsf2_ieee"
3072 [(set (match_operand:SF 0 "register_operand" "=&f")
3073 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3074 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3076 [(set_attr "type" "fsqrt")
3077 (set_attr "opsize" "si")
3078 (set_attr "trap" "yes")
3079 (set_attr "round_suffix" "normal")
3080 (set_attr "trap_suffix" "u_su_sui")])
3082 (define_insn "sqrtsf2"
3083 [(set (match_operand:SF 0 "register_operand" "=f")
3084 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3085 "TARGET_FP && TARGET_FIX"
3087 [(set_attr "type" "fsqrt")
3088 (set_attr "opsize" "si")
3089 (set_attr "trap" "yes")
3090 (set_attr "round_suffix" "normal")
3091 (set_attr "trap_suffix" "u_su_sui")])
3093 (define_insn "*sqrtdf2_ieee"
3094 [(set (match_operand:DF 0 "register_operand" "=&f")
3095 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3096 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3098 [(set_attr "type" "fsqrt")
3099 (set_attr "trap" "yes")
3100 (set_attr "round_suffix" "normal")
3101 (set_attr "trap_suffix" "u_su_sui")])
3103 (define_insn "sqrtdf2"
3104 [(set (match_operand:DF 0 "register_operand" "=f")
3105 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3106 "TARGET_FP && TARGET_FIX"
3108 [(set_attr "type" "fsqrt")
3109 (set_attr "trap" "yes")
3110 (set_attr "round_suffix" "normal")
3111 (set_attr "trap_suffix" "u_su_sui")])
3113 ;; Next are all the integer comparisons, and conditional moves and branches
3114 ;; and some of the related define_expand's and define_split's.
3116 (define_insn "*setcc_internal"
3117 [(set (match_operand 0 "register_operand" "=r")
3118 (match_operator 1 "alpha_comparison_operator"
3119 [(match_operand:DI 2 "register_operand" "r")
3120 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3121 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3122 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3123 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3125 [(set_attr "type" "icmp")])
3127 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3128 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3130 (define_insn "*setcc_swapped_internal"
3131 [(set (match_operand 0 "register_operand" "=r")
3132 (match_operator 1 "alpha_swapped_comparison_operator"
3133 [(match_operand:DI 2 "register_operand" "r")
3134 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3135 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3136 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3137 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3139 [(set_attr "type" "icmp")])
3141 ;; Use match_operator rather than ne directly so that we can match
3142 ;; multiple integer modes.
3143 (define_insn "*setne_internal"
3144 [(set (match_operand 0 "register_operand" "=r")
3145 (match_operator 1 "signed_comparison_operator"
3146 [(match_operand:DI 2 "register_operand" "r")
3148 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3149 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3150 && GET_CODE (operands[1]) == NE
3151 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3153 [(set_attr "type" "icmp")])
3155 ;; The mode folding trick can't be used with const_int operands, since
3156 ;; reload needs to know the proper mode.
3158 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3159 ;; in order to create more pairs of constants. As long as we're allowing
3160 ;; two constants at the same time, and will have to reload one of them...
3162 (define_insn "*movqicc_internal"
3163 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3165 (match_operator 2 "signed_comparison_operator"
3166 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3167 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3168 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3169 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3170 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3176 [(set_attr "type" "icmov")])
3178 (define_insn "*movhicc_internal"
3179 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3181 (match_operator 2 "signed_comparison_operator"
3182 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3183 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3184 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3185 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3186 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3192 [(set_attr "type" "icmov")])
3194 (define_insn "*movsicc_internal"
3195 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3197 (match_operator 2 "signed_comparison_operator"
3198 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3199 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3200 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3201 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3202 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3208 [(set_attr "type" "icmov")])
3210 (define_insn "*movdicc_internal"
3211 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3213 (match_operator 2 "signed_comparison_operator"
3214 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3215 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3216 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3217 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3218 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3224 [(set_attr "type" "icmov")])
3226 (define_insn "*movqicc_lbc"
3227 [(set (match_operand:QI 0 "register_operand" "=r,r")
3229 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3233 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3234 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3239 [(set_attr "type" "icmov")])
3241 (define_insn "*movhicc_lbc"
3242 [(set (match_operand:HI 0 "register_operand" "=r,r")
3244 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3248 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3249 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3254 [(set_attr "type" "icmov")])
3256 (define_insn "*movsicc_lbc"
3257 [(set (match_operand:SI 0 "register_operand" "=r,r")
3259 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3263 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3264 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3269 [(set_attr "type" "icmov")])
3271 (define_insn "*movdicc_lbc"
3272 [(set (match_operand:DI 0 "register_operand" "=r,r")
3274 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3278 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3279 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3284 [(set_attr "type" "icmov")])
3286 (define_insn "*movqicc_lbs"
3287 [(set (match_operand:QI 0 "register_operand" "=r,r")
3289 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3293 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3294 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3299 [(set_attr "type" "icmov")])
3301 (define_insn "*movhicc_lbs"
3302 [(set (match_operand:HI 0 "register_operand" "=r,r")
3304 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3308 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3309 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3314 [(set_attr "type" "icmov")])
3316 (define_insn "*movsicc_lbs"
3317 [(set (match_operand:SI 0 "register_operand" "=r,r")
3319 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3323 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3324 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3329 [(set_attr "type" "icmov")])
3331 (define_insn "*movdicc_lbs"
3332 [(set (match_operand:DI 0 "register_operand" "=r,r")
3334 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3338 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3339 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3344 [(set_attr "type" "icmov")])
3346 ;; For ABS, we have two choices, depending on whether the input and output
3347 ;; registers are the same or not.
3348 (define_expand "absdi2"
3349 [(set (match_operand:DI 0 "register_operand" "")
3350 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3353 if (rtx_equal_p (operands[0], operands[1]))
3354 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3356 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3360 (define_expand "absdi2_same"
3361 [(set (match_operand:DI 1 "register_operand" "")
3362 (neg:DI (match_operand:DI 0 "register_operand" "")))
3364 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3370 (define_expand "absdi2_diff"
3371 [(set (match_operand:DI 0 "register_operand" "")
3372 (neg:DI (match_operand:DI 1 "register_operand" "")))
3374 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3381 [(set (match_operand:DI 0 "register_operand" "")
3382 (abs:DI (match_dup 0)))
3383 (clobber (match_operand:DI 1 "register_operand" ""))]
3385 [(set (match_dup 1) (neg:DI (match_dup 0)))
3386 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3387 (match_dup 0) (match_dup 1)))]
3391 [(set (match_operand:DI 0 "register_operand" "")
3392 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3393 "! rtx_equal_p (operands[0], operands[1])"
3394 [(set (match_dup 0) (neg:DI (match_dup 1)))
3395 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3396 (match_dup 0) (match_dup 1)))]
3400 [(set (match_operand:DI 0 "register_operand" "")
3401 (neg:DI (abs:DI (match_dup 0))))
3402 (clobber (match_operand:DI 1 "register_operand" ""))]
3404 [(set (match_dup 1) (neg:DI (match_dup 0)))
3405 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3406 (match_dup 0) (match_dup 1)))]
3410 [(set (match_operand:DI 0 "register_operand" "")
3411 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3412 "! rtx_equal_p (operands[0], operands[1])"
3413 [(set (match_dup 0) (neg:DI (match_dup 1)))
3414 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3415 (match_dup 0) (match_dup 1)))]
3418 (define_insn "sminqi3"
3419 [(set (match_operand:QI 0 "register_operand" "=r")
3420 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3421 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3424 [(set_attr "type" "mvi")])
3426 (define_insn "uminqi3"
3427 [(set (match_operand:QI 0 "register_operand" "=r")
3428 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3429 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3432 [(set_attr "type" "mvi")])
3434 (define_insn "smaxqi3"
3435 [(set (match_operand:QI 0 "register_operand" "=r")
3436 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3437 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3440 [(set_attr "type" "mvi")])
3442 (define_insn "umaxqi3"
3443 [(set (match_operand:QI 0 "register_operand" "=r")
3444 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3445 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3448 [(set_attr "type" "mvi")])
3450 (define_insn "sminhi3"
3451 [(set (match_operand:HI 0 "register_operand" "=r")
3452 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3453 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3456 [(set_attr "type" "mvi")])
3458 (define_insn "uminhi3"
3459 [(set (match_operand:HI 0 "register_operand" "=r")
3460 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3461 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3464 [(set_attr "type" "mvi")])
3466 (define_insn "smaxhi3"
3467 [(set (match_operand:HI 0 "register_operand" "=r")
3468 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3469 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3472 [(set_attr "type" "mvi")])
3474 (define_insn "umaxhi3"
3475 [(set (match_operand:HI 0 "register_operand" "=r")
3476 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3477 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3480 [(set_attr "type" "shift")])
3482 (define_expand "smaxdi3"
3484 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3485 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3486 (set (match_operand:DI 0 "register_operand" "")
3487 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3488 (match_dup 1) (match_dup 2)))]
3490 { operands[3] = gen_reg_rtx (DImode); })
3493 [(set (match_operand:DI 0 "register_operand" "")
3494 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3495 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3496 (clobber (match_operand:DI 3 "register_operand" ""))]
3497 "operands[2] != const0_rtx"
3498 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3499 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3500 (match_dup 1) (match_dup 2)))]
3503 (define_insn "*smax_const0"
3504 [(set (match_operand:DI 0 "register_operand" "=r")
3505 (smax:DI (match_operand:DI 1 "register_operand" "0")
3509 [(set_attr "type" "icmov")])
3511 (define_expand "smindi3"
3513 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3514 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3515 (set (match_operand:DI 0 "register_operand" "")
3516 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3517 (match_dup 1) (match_dup 2)))]
3519 { operands[3] = gen_reg_rtx (DImode); })
3522 [(set (match_operand:DI 0 "register_operand" "")
3523 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3524 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3525 (clobber (match_operand:DI 3 "register_operand" ""))]
3526 "operands[2] != const0_rtx"
3527 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3528 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3529 (match_dup 1) (match_dup 2)))]
3532 (define_insn "*smin_const0"
3533 [(set (match_operand:DI 0 "register_operand" "=r")
3534 (smin:DI (match_operand:DI 1 "register_operand" "0")
3538 [(set_attr "type" "icmov")])
3540 (define_expand "umaxdi3"
3542 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3543 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3544 (set (match_operand:DI 0 "register_operand" "")
3545 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3546 (match_dup 1) (match_dup 2)))]
3548 "operands[3] = gen_reg_rtx (DImode);")
3551 [(set (match_operand:DI 0 "register_operand" "")
3552 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3553 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3554 (clobber (match_operand:DI 3 "register_operand" ""))]
3555 "operands[2] != const0_rtx"
3556 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3557 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3558 (match_dup 1) (match_dup 2)))]
3561 (define_expand "umindi3"
3563 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3564 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3565 (set (match_operand:DI 0 "register_operand" "")
3566 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3567 (match_dup 1) (match_dup 2)))]
3569 "operands[3] = gen_reg_rtx (DImode);")
3572 [(set (match_operand:DI 0 "register_operand" "")
3573 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3574 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3575 (clobber (match_operand:DI 3 "register_operand" ""))]
3576 "operands[2] != const0_rtx"
3577 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3578 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3579 (match_dup 1) (match_dup 2)))]
3582 (define_insn "*bcc_normal"
3585 (match_operator 1 "signed_comparison_operator"
3586 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3588 (label_ref (match_operand 0 "" ""))
3592 [(set_attr "type" "ibr")])
3594 (define_insn "*bcc_reverse"
3597 (match_operator 1 "signed_comparison_operator"
3598 [(match_operand:DI 2 "register_operand" "r")
3602 (label_ref (match_operand 0 "" ""))))]
3605 [(set_attr "type" "ibr")])
3607 (define_insn "*blbs_normal"
3610 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3614 (label_ref (match_operand 0 "" ""))
3618 [(set_attr "type" "ibr")])
3620 (define_insn "*blbc_normal"
3623 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3627 (label_ref (match_operand 0 "" ""))
3631 [(set_attr "type" "ibr")])
3637 (match_operator 1 "comparison_operator"
3638 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3640 (match_operand:DI 3 "const_int_operand" ""))
3642 (label_ref (match_operand 0 "" ""))
3644 (clobber (match_operand:DI 4 "register_operand" ""))])]
3645 "INTVAL (operands[3]) != 0"
3647 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3649 (if_then_else (match_op_dup 1
3650 [(zero_extract:DI (match_dup 4)
3654 (label_ref (match_dup 0))
3658 ;; The following are the corresponding floating-point insns. Recall
3659 ;; we need to have variants that expand the arguments from SFmode
3662 (define_insn "*cmpdf_ieee"
3663 [(set (match_operand:DF 0 "register_operand" "=&f")
3664 (match_operator:DF 1 "alpha_fp_comparison_operator"
3665 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3666 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3667 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3668 "cmp%-%C1%/ %R2,%R3,%0"
3669 [(set_attr "type" "fadd")
3670 (set_attr "trap" "yes")
3671 (set_attr "trap_suffix" "su")])
3673 (define_insn "*cmpdf_internal"
3674 [(set (match_operand:DF 0 "register_operand" "=f")
3675 (match_operator:DF 1 "alpha_fp_comparison_operator"
3676 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3677 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3678 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3679 "cmp%-%C1%/ %R2,%R3,%0"
3680 [(set_attr "type" "fadd")
3681 (set_attr "trap" "yes")
3682 (set_attr "trap_suffix" "su")])
3684 (define_insn "*cmpdf_ieee_ext1"
3685 [(set (match_operand:DF 0 "register_operand" "=&f")
3686 (match_operator:DF 1 "alpha_fp_comparison_operator"
3688 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3689 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3690 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3691 "cmp%-%C1%/ %R2,%R3,%0"
3692 [(set_attr "type" "fadd")
3693 (set_attr "trap" "yes")
3694 (set_attr "trap_suffix" "su")])
3696 (define_insn "*cmpdf_ext1"
3697 [(set (match_operand:DF 0 "register_operand" "=f")
3698 (match_operator:DF 1 "alpha_fp_comparison_operator"
3700 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3701 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3702 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3703 "cmp%-%C1%/ %R2,%R3,%0"
3704 [(set_attr "type" "fadd")
3705 (set_attr "trap" "yes")
3706 (set_attr "trap_suffix" "su")])
3708 (define_insn "*cmpdf_ieee_ext2"
3709 [(set (match_operand:DF 0 "register_operand" "=&f")
3710 (match_operator:DF 1 "alpha_fp_comparison_operator"
3711 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3713 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3714 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3715 "cmp%-%C1%/ %R2,%R3,%0"
3716 [(set_attr "type" "fadd")
3717 (set_attr "trap" "yes")
3718 (set_attr "trap_suffix" "su")])
3720 (define_insn "*cmpdf_ext2"
3721 [(set (match_operand:DF 0 "register_operand" "=f")
3722 (match_operator:DF 1 "alpha_fp_comparison_operator"
3723 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3725 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3726 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3727 "cmp%-%C1%/ %R2,%R3,%0"
3728 [(set_attr "type" "fadd")
3729 (set_attr "trap" "yes")
3730 (set_attr "trap_suffix" "su")])
3732 (define_insn "*cmpdf_ieee_ext3"
3733 [(set (match_operand:DF 0 "register_operand" "=&f")
3734 (match_operator:DF 1 "alpha_fp_comparison_operator"
3736 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3738 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3739 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3740 "cmp%-%C1%/ %R2,%R3,%0"
3741 [(set_attr "type" "fadd")
3742 (set_attr "trap" "yes")
3743 (set_attr "trap_suffix" "su")])
3745 (define_insn "*cmpdf_ext3"
3746 [(set (match_operand:DF 0 "register_operand" "=f")
3747 (match_operator:DF 1 "alpha_fp_comparison_operator"
3749 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3751 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3752 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3753 "cmp%-%C1%/ %R2,%R3,%0"
3754 [(set_attr "type" "fadd")
3755 (set_attr "trap" "yes")
3756 (set_attr "trap_suffix" "su")])
3758 (define_insn "*movdfcc_internal"
3759 [(set (match_operand:DF 0 "register_operand" "=f,f")
3761 (match_operator 3 "signed_comparison_operator"
3762 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3763 (match_operand:DF 2 "fp0_operand" "G,G")])
3764 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3765 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3769 fcmov%D3 %R4,%R5,%0"
3770 [(set_attr "type" "fcmov")])
3772 (define_insn "*movsfcc_internal"
3773 [(set (match_operand:SF 0 "register_operand" "=f,f")
3775 (match_operator 3 "signed_comparison_operator"
3776 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3777 (match_operand:DF 2 "fp0_operand" "G,G")])
3778 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3779 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3783 fcmov%D3 %R4,%R5,%0"
3784 [(set_attr "type" "fcmov")])
3786 (define_insn "*movdfcc_ext1"
3787 [(set (match_operand:DF 0 "register_operand" "=f,f")
3789 (match_operator 3 "signed_comparison_operator"
3790 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3791 (match_operand:DF 2 "fp0_operand" "G,G")])
3792 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3793 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3797 fcmov%D3 %R4,%R5,%0"
3798 [(set_attr "type" "fcmov")])
3800 (define_insn "*movdfcc_ext2"
3801 [(set (match_operand:DF 0 "register_operand" "=f,f")
3803 (match_operator 3 "signed_comparison_operator"
3805 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3806 (match_operand:DF 2 "fp0_operand" "G,G")])
3807 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3808 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3812 fcmov%D3 %R4,%R5,%0"
3813 [(set_attr "type" "fcmov")])
3815 (define_insn "*movdfcc_ext3"
3816 [(set (match_operand:SF 0 "register_operand" "=f,f")
3818 (match_operator 3 "signed_comparison_operator"
3820 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3821 (match_operand:DF 2 "fp0_operand" "G,G")])
3822 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3823 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3827 fcmov%D3 %R4,%R5,%0"
3828 [(set_attr "type" "fcmov")])
3830 (define_insn "*movdfcc_ext4"
3831 [(set (match_operand:DF 0 "register_operand" "=f,f")
3833 (match_operator 3 "signed_comparison_operator"
3835 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3836 (match_operand:DF 2 "fp0_operand" "G,G")])
3837 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3838 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3842 fcmov%D3 %R4,%R5,%0"
3843 [(set_attr "type" "fcmov")])
3845 (define_expand "maxdf3"
3847 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3848 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3849 (set (match_operand:DF 0 "register_operand" "")
3850 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3851 (match_dup 1) (match_dup 2)))]
3854 operands[3] = gen_reg_rtx (DFmode);
3855 operands[4] = CONST0_RTX (DFmode);
3858 (define_expand "mindf3"
3860 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3861 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3862 (set (match_operand:DF 0 "register_operand" "")
3863 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3864 (match_dup 1) (match_dup 2)))]
3867 operands[3] = gen_reg_rtx (DFmode);
3868 operands[4] = CONST0_RTX (DFmode);
3871 (define_expand "maxsf3"
3873 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3874 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3875 (set (match_operand:SF 0 "register_operand" "")
3876 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3877 (match_dup 1) (match_dup 2)))]
3880 operands[3] = gen_reg_rtx (DFmode);
3881 operands[4] = CONST0_RTX (DFmode);
3884 (define_expand "minsf3"
3886 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3887 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3888 (set (match_operand:SF 0 "register_operand" "")
3889 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3890 (match_dup 1) (match_dup 2)))]
3893 operands[3] = gen_reg_rtx (DFmode);
3894 operands[4] = CONST0_RTX (DFmode);
3897 (define_insn "*fbcc_normal"
3900 (match_operator 1 "signed_comparison_operator"
3901 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3902 (match_operand:DF 3 "fp0_operand" "G")])
3903 (label_ref (match_operand 0 "" ""))
3907 [(set_attr "type" "fbr")])
3909 (define_insn "*fbcc_ext_normal"
3912 (match_operator 1 "signed_comparison_operator"
3914 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3915 (match_operand:DF 3 "fp0_operand" "G")])
3916 (label_ref (match_operand 0 "" ""))
3920 [(set_attr "type" "fbr")])
3922 ;; These are the main define_expand's used to make conditional branches
3925 (define_expand "cmpdf"
3926 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3927 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3930 alpha_compare.op0 = operands[0];
3931 alpha_compare.op1 = operands[1];
3932 alpha_compare.fp_p = 1;
3936 (define_expand "cmptf"
3937 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3938 (match_operand:TF 1 "general_operand" "")))]
3939 "TARGET_HAS_XFLOATING_LIBS"
3941 alpha_compare.op0 = operands[0];
3942 alpha_compare.op1 = operands[1];
3943 alpha_compare.fp_p = 1;
3947 (define_expand "cmpdi"
3948 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3949 (match_operand:DI 1 "general_operand" "")))]
3952 alpha_compare.op0 = operands[0];
3953 alpha_compare.op1 = operands[1];
3954 alpha_compare.fp_p = 0;
3958 (define_expand "beq"
3960 (if_then_else (match_dup 1)
3961 (label_ref (match_operand 0 "" ""))
3964 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3966 (define_expand "bne"
3968 (if_then_else (match_dup 1)
3969 (label_ref (match_operand 0 "" ""))
3972 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3974 (define_expand "blt"
3976 (if_then_else (match_dup 1)
3977 (label_ref (match_operand 0 "" ""))
3980 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3982 (define_expand "ble"
3984 (if_then_else (match_dup 1)
3985 (label_ref (match_operand 0 "" ""))
3988 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3990 (define_expand "bgt"
3992 (if_then_else (match_dup 1)
3993 (label_ref (match_operand 0 "" ""))
3996 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3998 (define_expand "bge"
4000 (if_then_else (match_dup 1)
4001 (label_ref (match_operand 0 "" ""))
4004 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
4006 (define_expand "bltu"
4008 (if_then_else (match_dup 1)
4009 (label_ref (match_operand 0 "" ""))
4012 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
4014 (define_expand "bleu"
4016 (if_then_else (match_dup 1)
4017 (label_ref (match_operand 0 "" ""))
4020 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4022 (define_expand "bgtu"
4024 (if_then_else (match_dup 1)
4025 (label_ref (match_operand 0 "" ""))
4028 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4030 (define_expand "bgeu"
4032 (if_then_else (match_dup 1)
4033 (label_ref (match_operand 0 "" ""))
4036 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4038 (define_expand "bunordered"
4040 (if_then_else (match_dup 1)
4041 (label_ref (match_operand 0 "" ""))
4044 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4046 (define_expand "bordered"
4048 (if_then_else (match_dup 1)
4049 (label_ref (match_operand 0 "" ""))
4052 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4054 (define_expand "seq"
4055 [(set (match_operand:DI 0 "register_operand" "")
4058 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4060 (define_expand "sne"
4061 [(set (match_operand:DI 0 "register_operand" "")
4064 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4066 (define_expand "slt"
4067 [(set (match_operand:DI 0 "register_operand" "")
4070 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4072 (define_expand "sle"
4073 [(set (match_operand:DI 0 "register_operand" "")
4076 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4078 (define_expand "sgt"
4079 [(set (match_operand:DI 0 "register_operand" "")
4082 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4084 (define_expand "sge"
4085 [(set (match_operand:DI 0 "register_operand" "")
4088 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4090 (define_expand "sltu"
4091 [(set (match_operand:DI 0 "register_operand" "")
4094 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4096 (define_expand "sleu"
4097 [(set (match_operand:DI 0 "register_operand" "")
4100 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4102 (define_expand "sgtu"
4103 [(set (match_operand:DI 0 "register_operand" "")
4106 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4108 (define_expand "sgeu"
4109 [(set (match_operand:DI 0 "register_operand" "")
4112 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4114 (define_expand "sunordered"
4115 [(set (match_operand:DI 0 "register_operand" "")
4118 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4120 (define_expand "sordered"
4121 [(set (match_operand:DI 0 "register_operand" "")
4124 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4126 ;; These are the main define_expand's used to make conditional moves.
4128 (define_expand "movsicc"
4129 [(set (match_operand:SI 0 "register_operand" "")
4130 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4131 (match_operand:SI 2 "reg_or_8bit_operand" "")
4132 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4135 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4139 (define_expand "movdicc"
4140 [(set (match_operand:DI 0 "register_operand" "")
4141 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4142 (match_operand:DI 2 "reg_or_8bit_operand" "")
4143 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4146 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4150 (define_expand "movsfcc"
4151 [(set (match_operand:SF 0 "register_operand" "")
4152 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4153 (match_operand:SF 2 "reg_or_8bit_operand" "")
4154 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4157 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4161 (define_expand "movdfcc"
4162 [(set (match_operand:DF 0 "register_operand" "")
4163 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4164 (match_operand:DF 2 "reg_or_8bit_operand" "")
4165 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4168 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4172 ;; These define_split definitions are used in cases when comparisons have
4173 ;; not be stated in the correct way and we need to reverse the second
4174 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4175 ;; comparison that tests the result being reversed. We have one define_split
4176 ;; for each use of a comparison. They do not match valid insns and need
4177 ;; not generate valid insns.
4179 ;; We can also handle equality comparisons (and inequality comparisons in
4180 ;; cases where the resulting add cannot overflow) by doing an add followed by
4181 ;; a comparison with zero. This is faster since the addition takes one
4182 ;; less cycle than a compare when feeding into a conditional move.
4183 ;; For this case, we also have an SImode pattern since we can merge the add
4184 ;; and sign extend and the order doesn't matter.
4186 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4187 ;; operation could have been generated.
4190 [(set (match_operand:DI 0 "register_operand" "")
4192 (match_operator 1 "comparison_operator"
4193 [(match_operand:DI 2 "reg_or_0_operand" "")
4194 (match_operand:DI 3 "reg_or_cint_operand" "")])
4195 (match_operand:DI 4 "reg_or_cint_operand" "")
4196 (match_operand:DI 5 "reg_or_cint_operand" "")))
4197 (clobber (match_operand:DI 6 "register_operand" ""))]
4198 "operands[3] != const0_rtx"
4199 [(set (match_dup 6) (match_dup 7))
4201 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4203 enum rtx_code code = GET_CODE (operands[1]);
4204 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4206 /* If we are comparing for equality with a constant and that constant
4207 appears in the arm when the register equals the constant, use the
4208 register since that is more likely to match (and to produce better code
4211 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4212 && rtx_equal_p (operands[4], operands[3]))
4213 operands[4] = operands[2];
4215 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4216 && rtx_equal_p (operands[5], operands[3]))
4217 operands[5] = operands[2];
4219 if (code == NE || code == EQ
4220 || (extended_count (operands[2], DImode, unsignedp) >= 1
4221 && extended_count (operands[3], DImode, unsignedp) >= 1))
4223 if (GET_CODE (operands[3]) == CONST_INT)
4224 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4225 GEN_INT (- INTVAL (operands[3])));
4227 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4229 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4232 else if (code == EQ || code == LE || code == LT
4233 || code == LEU || code == LTU)
4235 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4236 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4240 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4241 operands[2], operands[3]);
4242 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4247 [(set (match_operand:DI 0 "register_operand" "")
4249 (match_operator 1 "comparison_operator"
4250 [(match_operand:SI 2 "reg_or_0_operand" "")
4251 (match_operand:SI 3 "reg_or_cint_operand" "")])
4252 (match_operand:DI 4 "reg_or_8bit_operand" "")
4253 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4254 (clobber (match_operand:DI 6 "register_operand" ""))]
4255 "operands[3] != const0_rtx
4256 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4257 [(set (match_dup 6) (match_dup 7))
4259 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4261 enum rtx_code code = GET_CODE (operands[1]);
4262 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4265 if ((code != NE && code != EQ
4266 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4267 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4270 if (GET_CODE (operands[3]) == CONST_INT)
4271 tem = gen_rtx_PLUS (SImode, operands[2],
4272 GEN_INT (- INTVAL (operands[3])));
4274 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4276 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4277 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4278 operands[6], const0_rtx);
4284 (match_operator 1 "comparison_operator"
4285 [(match_operand:DI 2 "reg_or_0_operand" "")
4286 (match_operand:DI 3 "reg_or_cint_operand" "")])
4287 (label_ref (match_operand 0 "" ""))
4289 (clobber (match_operand:DI 4 "register_operand" ""))]
4290 "operands[3] != const0_rtx"
4291 [(set (match_dup 4) (match_dup 5))
4292 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4294 enum rtx_code code = GET_CODE (operands[1]);
4295 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4297 if (code == NE || code == EQ
4298 || (extended_count (operands[2], DImode, unsignedp) >= 1
4299 && extended_count (operands[3], DImode, unsignedp) >= 1))
4301 if (GET_CODE (operands[3]) == CONST_INT)
4302 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4303 GEN_INT (- INTVAL (operands[3])));
4305 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4307 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4310 else if (code == EQ || code == LE || code == LT
4311 || code == LEU || code == LTU)
4313 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4314 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4318 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4319 operands[2], operands[3]);
4320 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4327 (match_operator 1 "comparison_operator"
4328 [(match_operand:SI 2 "reg_or_0_operand" "")
4329 (match_operand:SI 3 "const_int_operand" "")])
4330 (label_ref (match_operand 0 "" ""))
4332 (clobber (match_operand:DI 4 "register_operand" ""))]
4333 "operands[3] != const0_rtx
4334 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4335 [(set (match_dup 4) (match_dup 5))
4336 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4340 if (GET_CODE (operands[3]) == CONST_INT)
4341 tem = gen_rtx_PLUS (SImode, operands[2],
4342 GEN_INT (- INTVAL (operands[3])));
4344 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4346 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4347 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4348 operands[4], const0_rtx);
4351 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4352 ;; This eliminates one, and sometimes two, insns when the AND can be done
4355 [(set (match_operand:DI 0 "register_operand" "")
4356 (match_operator:DI 1 "comparison_operator"
4357 [(match_operand:DI 2 "register_operand" "")
4358 (match_operand:DI 3 "const_int_operand" "")]))
4359 (clobber (match_operand:DI 4 "register_operand" ""))]
4360 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4361 && (GET_CODE (operands[1]) == GTU
4362 || GET_CODE (operands[1]) == LEU
4363 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4364 && extended_count (operands[2], DImode, 1) > 0))"
4365 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4366 (set (match_dup 0) (match_dup 6))]
4368 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4369 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4370 || GET_CODE (operands[1]) == GT)
4372 DImode, operands[4], const0_rtx);
4375 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4378 [(set (match_operand 0 "register_operand" "")
4379 (if_then_else (match_operator 1 "signed_comparison_operator"
4380 [(match_operand:DI 2 "reg_or_0_operand" "")
4382 (match_operand 3 "const_int_operand" "")
4383 (match_operand 4 "const_int_operand" "")))]
4387 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4388 operands[2], operands[3], operands[4]))
4394 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4395 ;; Oh well, we match it in movcc, so it must be partially our fault.
4397 [(set (match_operand 0 "register_operand" "")
4398 (if_then_else (match_operator 1 "signed_comparison_operator"
4400 (match_operand:DI 2 "reg_or_0_operand" "")])
4401 (match_operand 3 "const_int_operand" "")
4402 (match_operand 4 "const_int_operand" "")))]
4406 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4407 operands[0], operands[2], operands[3],
4414 (define_insn_and_split "*cmp_sadd_di"
4415 [(set (match_operand:DI 0 "register_operand" "=r")
4416 (plus:DI (if_then_else:DI
4417 (match_operator 1 "alpha_zero_comparison_operator"
4418 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4420 (match_operand:DI 3 "const48_operand" "I")
4422 (match_operand:DI 4 "sext_add_operand" "rIO")))
4423 (clobber (match_scratch:DI 5 "=r"))]
4426 "! no_new_pseudos || reload_completed"
4428 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4430 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4433 if (! no_new_pseudos)
4434 operands[5] = gen_reg_rtx (DImode);
4435 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4436 operands[5] = operands[0];
4439 (define_insn_and_split "*cmp_sadd_si"
4440 [(set (match_operand:SI 0 "register_operand" "=r")
4441 (plus:SI (if_then_else:SI
4442 (match_operator 1 "alpha_zero_comparison_operator"
4443 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4445 (match_operand:SI 3 "const48_operand" "I")
4447 (match_operand:SI 4 "sext_add_operand" "rIO")))
4448 (clobber (match_scratch:SI 5 "=r"))]
4451 "! no_new_pseudos || reload_completed"
4453 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4455 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4458 if (! no_new_pseudos)
4459 operands[5] = gen_reg_rtx (DImode);
4460 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4461 operands[5] = operands[0];
4464 (define_insn_and_split "*cmp_sadd_sidi"
4465 [(set (match_operand:DI 0 "register_operand" "=r")
4467 (plus:SI (if_then_else:SI
4468 (match_operator 1 "alpha_zero_comparison_operator"
4469 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4471 (match_operand:SI 3 "const48_operand" "I")
4473 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4474 (clobber (match_scratch:SI 5 "=r"))]
4477 "! no_new_pseudos || reload_completed"
4479 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4481 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4484 if (! no_new_pseudos)
4485 operands[5] = gen_reg_rtx (DImode);
4486 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4487 operands[5] = operands[0];
4490 (define_insn_and_split "*cmp_ssub_di"
4491 [(set (match_operand:DI 0 "register_operand" "=r")
4492 (minus:DI (if_then_else:DI
4493 (match_operator 1 "alpha_zero_comparison_operator"
4494 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4496 (match_operand:DI 3 "const48_operand" "I")
4498 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4499 (clobber (match_scratch:DI 5 "=r"))]
4502 "! no_new_pseudos || reload_completed"
4504 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4506 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4509 if (! no_new_pseudos)
4510 operands[5] = gen_reg_rtx (DImode);
4511 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4512 operands[5] = operands[0];
4515 (define_insn_and_split "*cmp_ssub_si"
4516 [(set (match_operand:SI 0 "register_operand" "=r")
4517 (minus:SI (if_then_else:SI
4518 (match_operator 1 "alpha_zero_comparison_operator"
4519 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4521 (match_operand:SI 3 "const48_operand" "I")
4523 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4524 (clobber (match_scratch:SI 5 "=r"))]
4527 "! no_new_pseudos || reload_completed"
4529 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4531 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4534 if (! no_new_pseudos)
4535 operands[5] = gen_reg_rtx (DImode);
4536 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4537 operands[5] = operands[0];
4540 (define_insn_and_split "*cmp_ssub_sidi"
4541 [(set (match_operand:DI 0 "register_operand" "=r")
4543 (minus:SI (if_then_else:SI
4544 (match_operator 1 "alpha_zero_comparison_operator"
4545 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4547 (match_operand:SI 3 "const48_operand" "I")
4549 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4550 (clobber (match_scratch:SI 5 "=r"))]
4553 "! no_new_pseudos || reload_completed"
4555 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4557 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4560 if (! no_new_pseudos)
4561 operands[5] = gen_reg_rtx (DImode);
4562 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4563 operands[5] = operands[0];
4566 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4567 ;; work differently, so we have different patterns for each.
4569 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4570 ;; call. The CIW contains information about arguments passed in registers
4571 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4572 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4573 ;; in the presence of inlining since the CIWs for calls performed by the
4574 ;; inlined function must be stored in the SSIB of the function it is inlined
4575 ;; into as well. We encode the CIW in an unspec and append it to the list
4576 ;; of the CIWs for the current function only when the instruction for loading
4577 ;; $25 is generated.
4579 (define_expand "call"
4580 [(use (match_operand:DI 0 "" ""))
4581 (use (match_operand 1 "" ""))
4582 (use (match_operand 2 "" ""))
4583 (use (match_operand 3 "" ""))]
4586 if (TARGET_ABI_WINDOWS_NT)
4587 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4588 else if (TARGET_ABI_OPEN_VMS)
4589 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4590 else if (TARGET_ABI_UNICOSMK)
4591 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4593 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4597 (define_expand "sibcall"
4598 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4599 (match_operand 1 "" ""))
4600 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4603 if (GET_CODE (operands[0]) != MEM)
4605 operands[0] = XEXP (operands[0], 0);
4608 (define_expand "call_osf"
4609 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4610 (match_operand 1 "" ""))
4612 (clobber (reg:DI 26))])]
4615 if (GET_CODE (operands[0]) != MEM)
4618 operands[0] = XEXP (operands[0], 0);
4619 if (! call_operand (operands[0], Pmode))
4620 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4623 (define_expand "call_nt"
4624 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4625 (match_operand 1 "" ""))
4626 (clobber (reg:DI 26))])]
4629 if (GET_CODE (operands[0]) != MEM)
4632 operands[0] = XEXP (operands[0], 0);
4633 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4634 operands[0] = force_reg (DImode, operands[0]);
4637 ;; Calls on Unicos/Mk are always indirect.
4638 ;; op 0: symbol ref for called function
4639 ;; op 1: CIW for $25 represented by an unspec
4641 (define_expand "call_umk"
4642 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4643 (match_operand 1 "" ""))
4645 (clobber (reg:DI 26))])]
4648 if (GET_CODE (operands[0]) != MEM)
4651 /* Always load the address of the called function into a register;
4652 load the CIW in $25. */
4654 operands[0] = XEXP (operands[0], 0);
4655 if (GET_CODE (operands[0]) != REG)
4656 operands[0] = force_reg (DImode, operands[0]);
4658 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4662 ;; call openvms/alpha
4663 ;; op 0: symbol ref for called function
4664 ;; op 1: next_arg_reg (argument information value for R25)
4666 (define_expand "call_vms"
4667 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4668 (match_operand 1 "" ""))
4672 (clobber (reg:DI 27))])]
4675 if (GET_CODE (operands[0]) != MEM)
4678 operands[0] = XEXP (operands[0], 0);
4680 /* Always load AI with argument information, then handle symbolic and
4681 indirect call differently. Load RA and set operands[2] to PV in
4684 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4685 if (GET_CODE (operands[0]) == SYMBOL_REF)
4687 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4689 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4691 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4695 emit_move_insn (gen_rtx_REG (Pmode, 26),
4696 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4697 operands[2] = operands[0];
4702 (define_expand "call_value"
4703 [(use (match_operand 0 "" ""))
4704 (use (match_operand:DI 1 "" ""))
4705 (use (match_operand 2 "" ""))
4706 (use (match_operand 3 "" ""))
4707 (use (match_operand 4 "" ""))]
4710 if (TARGET_ABI_WINDOWS_NT)
4711 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4712 else if (TARGET_ABI_OPEN_VMS)
4713 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4715 else if (TARGET_ABI_UNICOSMK)
4716 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4719 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4724 (define_expand "sibcall_value"
4725 [(parallel [(set (match_operand 0 "" "")
4726 (call (mem:DI (match_operand 1 "" ""))
4727 (match_operand 2 "" "")))
4728 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4731 if (GET_CODE (operands[1]) != MEM)
4733 operands[1] = XEXP (operands[1], 0);
4736 (define_expand "call_value_osf"
4737 [(parallel [(set (match_operand 0 "" "")
4738 (call (mem:DI (match_operand 1 "" ""))
4739 (match_operand 2 "" "")))
4741 (clobber (reg:DI 26))])]
4744 if (GET_CODE (operands[1]) != MEM)
4747 operands[1] = XEXP (operands[1], 0);
4748 if (! call_operand (operands[1], Pmode))
4749 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4752 (define_expand "call_value_nt"
4753 [(parallel [(set (match_operand 0 "" "")
4754 (call (mem:DI (match_operand 1 "" ""))
4755 (match_operand 2 "" "")))
4756 (clobber (reg:DI 26))])]
4759 if (GET_CODE (operands[1]) != MEM)
4762 operands[1] = XEXP (operands[1], 0);
4763 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4764 operands[1] = force_reg (DImode, operands[1]);
4767 (define_expand "call_value_vms"
4768 [(parallel [(set (match_operand 0 "" "")
4769 (call (mem:DI (match_operand:DI 1 "" ""))
4770 (match_operand 2 "" "")))
4774 (clobber (reg:DI 27))])]
4777 if (GET_CODE (operands[1]) != MEM)
4780 operands[1] = XEXP (operands[1], 0);
4782 /* Always load AI with argument information, then handle symbolic and
4783 indirect call differently. Load RA and set operands[3] to PV in
4786 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4787 if (GET_CODE (operands[1]) == SYMBOL_REF)
4789 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4791 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4793 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4797 emit_move_insn (gen_rtx_REG (Pmode, 26),
4798 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4799 operands[3] = operands[1];
4803 (define_expand "call_value_umk"
4804 [(parallel [(set (match_operand 0 "" "")
4805 (call (mem:DI (match_operand 1 "" ""))
4806 (match_operand 2 "" "")))
4808 (clobber (reg:DI 26))])]
4811 if (GET_CODE (operands[1]) != MEM)
4814 operands[1] = XEXP (operands[1], 0);
4815 if (GET_CODE (operands[1]) != REG)
4816 operands[1] = force_reg (DImode, operands[1]);
4818 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4821 (define_insn "*call_osf_1_er"
4822 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4823 (match_operand 1 "" ""))
4825 (clobber (reg:DI 26))]
4826 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4828 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4830 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4831 [(set_attr "type" "jsr")
4832 (set_attr "length" "12,*,16")])
4834 ;; We must use peep2 instead of a split because we need accurate life
4835 ;; information for $gp. Consider the case of { bar(); while (1); }.
4837 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4838 (match_operand 1 "" ""))
4840 (clobber (reg:DI 26))])]
4841 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4842 && ! current_file_function_operand (operands[0], Pmode)
4843 && peep2_regno_dead_p (1, 29)"
4844 [(parallel [(call (mem:DI (match_dup 2))
4846 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4847 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4849 (use (match_dup 3))])]
4851 if (CONSTANT_P (operands[0]))
4853 operands[2] = gen_rtx_REG (Pmode, 27);
4854 operands[3] = GEN_INT (alpha_next_sequence_number++);
4855 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4856 operands[0], operands[3]));
4860 operands[2] = operands[0];
4861 operands[0] = const0_rtx;
4862 operands[3] = const0_rtx;
4867 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4868 (match_operand 1 "" ""))
4870 (clobber (reg:DI 26))])]
4871 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4872 && ! current_file_function_operand (operands[0], Pmode)
4873 && ! peep2_regno_dead_p (1, 29)"
4874 [(parallel [(call (mem:DI (match_dup 2))
4876 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4877 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4879 (use (match_dup 4))])
4881 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4883 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4885 if (CONSTANT_P (operands[0]))
4887 operands[2] = gen_rtx_REG (Pmode, 27);
4888 operands[4] = GEN_INT (alpha_next_sequence_number++);
4889 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4890 operands[0], operands[4]));
4894 operands[2] = operands[0];
4895 operands[0] = const0_rtx;
4896 operands[4] = const0_rtx;
4898 operands[3] = GEN_INT (alpha_next_sequence_number++);
4901 ;; We add a blockage unspec_volatile to prevent insns from moving down
4902 ;; from above the call to in between the call and the ldah gpdisp.
4904 (define_insn "*call_osf_2_er"
4905 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4906 (match_operand 1 "" ""))
4907 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4908 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4909 (use (match_operand 2 "" ""))
4910 (use (match_operand 3 "const_int_operand" ""))]
4911 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4912 "jsr $26,(%0),%2%J3"
4913 [(set_attr "type" "jsr")])
4915 (define_insn "*call_osf_1_noreturn"
4916 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4917 (match_operand 1 "" ""))
4919 (clobber (reg:DI 26))]
4920 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4921 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4926 [(set_attr "type" "jsr")
4927 (set_attr "length" "*,*,8")])
4929 (define_insn "*call_osf_1"
4930 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4931 (match_operand 1 "" ""))
4933 (clobber (reg:DI 26))]
4934 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4936 jsr $26,($27),0\;ldgp $29,0($26)
4938 jsr $26,%0\;ldgp $29,0($26)"
4939 [(set_attr "type" "jsr")
4940 (set_attr "length" "12,*,16")])
4942 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4943 ;; doesn't do what we want.
4944 (define_insn "*sibcall_osf_1_er"
4945 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4946 (match_operand 1 "" ""))
4947 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4948 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4951 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4952 [(set_attr "type" "jsr")
4953 (set_attr "length" "*,8")])
4955 (define_insn "*sibcall_osf_1"
4956 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4957 (match_operand 1 "" ""))
4958 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4959 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4962 lda $27,%0\;jmp $31,($27),%0"
4963 [(set_attr "type" "jsr")
4964 (set_attr "length" "*,8")])
4966 (define_insn "*call_nt_1"
4967 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4968 (match_operand 1 "" ""))
4969 (clobber (reg:DI 26))]
4970 "TARGET_ABI_WINDOWS_NT"
4975 [(set_attr "type" "jsr")
4976 (set_attr "length" "*,*,12")])
4978 (define_insn "*call_vms_1"
4979 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4980 (match_operand 1 "" ""))
4981 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4984 (clobber (reg:DI 27))]
4985 "TARGET_ABI_OPEN_VMS"
4987 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4988 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4989 [(set_attr "type" "jsr")
4990 (set_attr "length" "12,16")])
4992 (define_insn "*call_umk_1"
4993 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4994 (match_operand 1 "" ""))
4996 (clobber (reg:DI 26))]
4997 "TARGET_ABI_UNICOSMK"
4999 [(set_attr "type" "jsr")])
5001 ;; Call subroutine returning any type.
5003 (define_expand "untyped_call"
5004 [(parallel [(call (match_operand 0 "" "")
5006 (match_operand 1 "" "")
5007 (match_operand 2 "" "")])]
5012 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5014 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5016 rtx set = XVECEXP (operands[2], 0, i);
5017 emit_move_insn (SET_DEST (set), SET_SRC (set));
5020 /* The optimizer does not know that the call sets the function value
5021 registers we stored in the result block. We avoid problems by
5022 claiming that all hard registers are used and clobbered at this
5024 emit_insn (gen_blockage ());
5029 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5030 ;; all of memory. This blocks insns from being moved across this point.
5032 (define_insn "blockage"
5033 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5036 [(set_attr "length" "0")])
5040 (label_ref (match_operand 0 "" "")))]
5043 [(set_attr "type" "ibr")])
5045 (define_expand "return"
5050 (define_insn "*return_internal"
5054 [(set_attr "type" "ibr")])
5056 (define_insn "indirect_jump"
5057 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
5060 [(set_attr "type" "ibr")])
5062 (define_expand "tablejump"
5063 [(parallel [(set (pc)
5064 (match_operand 0 "register_operand" ""))
5065 (use (label_ref:DI (match_operand 1 "" "")))])]
5068 if (TARGET_ABI_WINDOWS_NT)
5070 rtx dest = gen_reg_rtx (DImode);
5071 emit_insn (gen_extendsidi2 (dest, operands[0]));
5074 else if (TARGET_ABI_OSF)
5076 rtx dest = gen_reg_rtx (DImode);
5077 emit_insn (gen_extendsidi2 (dest, operands[0]));
5078 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
5083 (define_insn "*tablejump_osf_nt_internal"
5085 (match_operand:DI 0 "register_operand" "r"))
5086 (use (label_ref:DI (match_operand 1 "" "")))]
5087 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5088 && alpha_tablejump_addr_vec (insn)"
5090 operands[2] = alpha_tablejump_best_label (insn);
5091 return "jmp $31,(%0),%2";
5093 [(set_attr "type" "ibr")])
5095 (define_insn "*tablejump_internal"
5097 (match_operand:DI 0 "register_operand" "r"))
5098 (use (label_ref (match_operand 1 "" "")))]
5101 [(set_attr "type" "ibr")])
5103 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5104 ;; want to have to include pal.h in our .s file.
5106 ;; Technically the type for call_pal is jsr, but we use that for determining
5107 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5110 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5113 [(set_attr "type" "ibr")])
5115 ;; Finally, we have the basic data motion insns. The byte and word insns
5116 ;; are done via define_expand. Start with the floating-point insns, since
5117 ;; they are simpler.
5119 (define_insn "*movsf_nofix"
5120 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5121 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5122 "TARGET_FPREGS && ! TARGET_FIX
5123 && (register_operand (operands[0], SFmode)
5124 || reg_or_fp0_operand (operands[1], SFmode))"
5132 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5134 (define_insn "*movsf_fix"
5135 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5136 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5137 "TARGET_FPREGS && TARGET_FIX
5138 && (register_operand (operands[0], SFmode)
5139 || reg_or_fp0_operand (operands[1], SFmode))"
5149 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5151 (define_insn "*movsf_nofp"
5152 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5153 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5155 && (register_operand (operands[0], SFmode)
5156 || reg_or_fp0_operand (operands[1], SFmode))"
5161 [(set_attr "type" "ilog,ild,ist")])
5163 (define_insn "*movdf_nofix"
5164 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5165 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5166 "TARGET_FPREGS && ! TARGET_FIX
5167 && (register_operand (operands[0], DFmode)
5168 || reg_or_fp0_operand (operands[1], DFmode))"
5176 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5178 (define_insn "*movdf_fix"
5179 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5180 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5181 "TARGET_FPREGS && TARGET_FIX
5182 && (register_operand (operands[0], DFmode)
5183 || reg_or_fp0_operand (operands[1], DFmode))"
5193 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5195 (define_insn "*movdf_nofp"
5196 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5197 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5199 && (register_operand (operands[0], DFmode)
5200 || reg_or_fp0_operand (operands[1], DFmode))"
5205 [(set_attr "type" "ilog,ild,ist")])
5207 ;; Subregs suck for register allocation. Pretend we can move TFmode
5208 ;; data between general registers until after reload.
5210 (define_insn_and_split "*movtf_internal"
5211 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5212 (match_operand:TF 1 "input_operand" "roG,rG"))]
5213 "register_operand (operands[0], TFmode)
5214 || reg_or_fp0_operand (operands[1], TFmode)"
5217 [(set (match_dup 0) (match_dup 2))
5218 (set (match_dup 1) (match_dup 3))]
5220 alpha_split_tfmode_pair (operands);
5221 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5224 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5225 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5229 (define_expand "movsf"
5230 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5231 (match_operand:SF 1 "general_operand" ""))]
5234 if (GET_CODE (operands[0]) == MEM
5235 && ! reg_or_fp0_operand (operands[1], SFmode))
5236 operands[1] = force_reg (SFmode, operands[1]);
5239 (define_expand "movdf"
5240 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5241 (match_operand:DF 1 "general_operand" ""))]
5244 if (GET_CODE (operands[0]) == MEM
5245 && ! reg_or_fp0_operand (operands[1], DFmode))
5246 operands[1] = force_reg (DFmode, operands[1]);
5249 (define_expand "movtf"
5250 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5251 (match_operand:TF 1 "general_operand" ""))]
5254 if (GET_CODE (operands[0]) == MEM
5255 && ! reg_or_fp0_operand (operands[1], TFmode))
5256 operands[1] = force_reg (TFmode, operands[1]);
5259 (define_insn "*movsi_nofix"
5260 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5261 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5262 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5263 && (register_operand (operands[0], SImode)
5264 || reg_or_0_operand (operands[1], SImode))"
5274 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5276 (define_insn "*movsi_fix"
5277 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5278 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5279 "TARGET_ABI_OSF && TARGET_FIX
5280 && (register_operand (operands[0], SImode)
5281 || reg_or_0_operand (operands[1], SImode))"
5293 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5295 (define_insn "*movsi_nt_vms_nofix"
5296 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5297 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5298 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5300 && (register_operand (operands[0], SImode)
5301 || reg_or_0_operand (operands[1], SImode))"
5312 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5314 (define_insn "*movsi_nt_vms_fix"
5315 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5316 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5317 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5319 && (register_operand (operands[0], SImode)
5320 || reg_or_0_operand (operands[1], SImode))"
5333 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5335 (define_insn "*movhi_nobwx"
5336 [(set (match_operand:HI 0 "register_operand" "=r,r")
5337 (match_operand:HI 1 "input_operand" "rJ,n"))]
5339 && (register_operand (operands[0], HImode)
5340 || register_operand (operands[1], HImode))"
5344 [(set_attr "type" "ilog,iadd")])
5346 (define_insn "*movhi_bwx"
5347 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5348 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5350 && (register_operand (operands[0], HImode)
5351 || reg_or_0_operand (operands[1], HImode))"
5357 [(set_attr "type" "ilog,iadd,ild,ist")])
5359 (define_insn "*movqi_nobwx"
5360 [(set (match_operand:QI 0 "register_operand" "=r,r")
5361 (match_operand:QI 1 "input_operand" "rJ,n"))]
5363 && (register_operand (operands[0], QImode)
5364 || register_operand (operands[1], QImode))"
5368 [(set_attr "type" "ilog,iadd")])
5370 (define_insn "*movqi_bwx"
5371 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5372 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5374 && (register_operand (operands[0], QImode)
5375 || reg_or_0_operand (operands[1], QImode))"
5381 [(set_attr "type" "ilog,iadd,ild,ist")])
5383 ;; We do two major things here: handle mem->mem and construct long
5386 (define_expand "movsi"
5387 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5388 (match_operand:SI 1 "general_operand" ""))]
5391 if (alpha_expand_mov (SImode, operands))
5395 ;; Split a load of a large constant into the appropriate two-insn
5399 [(set (match_operand:SI 0 "register_operand" "")
5400 (match_operand:SI 1 "const_int_operand" ""))]
5401 "! add_operand (operands[1], SImode)"
5402 [(set (match_dup 0) (match_dup 2))
5403 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5406 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5408 if (tem == operands[0])
5414 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5415 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5416 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5417 ;; notes and update LABEL_NUSES because this is not done automatically.
5418 ;; Labels may be incorrectly deleted if we don't do this.
5420 ;; Describing what the individual instructions do correctly is too complicated
5421 ;; so use UNSPECs for each of the three parts of an address.
5424 [(set (match_operand:DI 0 "register_operand" "")
5425 (match_operand:DI 1 "symbolic_operand" ""))]
5426 "TARGET_ABI_UNICOSMK && reload_completed"
5429 rtx insn1, insn2, insn3;
5431 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5432 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5433 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5434 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5435 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5437 if (GET_CODE (operands[1]) == LABEL_REF)
5441 label = XEXP (operands[1], 0);
5442 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5444 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5446 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5448 LABEL_NUSES (label) += 3;
5453 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5455 (define_insn "umk_laum"
5456 [(set (match_operand:DI 0 "register_operand" "=r")
5457 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5459 "TARGET_ABI_UNICOSMK"
5461 [(set_attr "type" "iadd")])
5463 (define_insn "umk_lalm"
5464 [(set (match_operand:DI 0 "register_operand" "=r")
5465 (plus:DI (match_operand:DI 1 "register_operand" "r")
5466 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5468 "TARGET_ABI_UNICOSMK"
5470 [(set_attr "type" "iadd")])
5472 (define_insn "umk_lal"
5473 [(set (match_operand:DI 0 "register_operand" "=r")
5474 (plus:DI (match_operand:DI 1 "register_operand" "r")
5475 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5477 "TARGET_ABI_UNICOSMK"
5479 [(set_attr "type" "iadd")])
5481 ;; Add a new call information word to the current function's list of CIWs
5482 ;; and load its index into $25. Doing it here ensures that the CIW will be
5483 ;; associated with the correct function even in the presence of inlining.
5485 (define_insn "*umk_load_ciw"
5487 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5488 "TARGET_ABI_UNICOSMK"
5490 operands[0] = unicosmk_add_call_info_word (operands[0]);
5491 return "lda $25,%0";
5493 [(set_attr "type" "iadd")])
5495 (define_insn "*movdi_er_low_l"
5496 [(set (match_operand:DI 0 "register_operand" "=r")
5497 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5498 (match_operand:DI 2 "local_symbolic_operand" "")))]
5499 "TARGET_EXPLICIT_RELOCS"
5501 if (true_regnum (operands[1]) == 29)
5502 return "lda %0,%2(%1)\t\t!gprel";
5504 return "lda %0,%2(%1)\t\t!gprellow";
5508 [(set (match_operand:DI 0 "register_operand" "")
5509 (match_operand:DI 1 "small_symbolic_operand" ""))]
5510 "TARGET_EXPLICIT_RELOCS && reload_completed"
5512 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5513 "operands[2] = pic_offset_table_rtx;")
5516 [(set (match_operand:DI 0 "register_operand" "")
5517 (match_operand:DI 1 "local_symbolic_operand" ""))]
5518 "TARGET_EXPLICIT_RELOCS && reload_completed"
5520 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5522 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5523 "operands[2] = pic_offset_table_rtx;")
5526 [(match_operand 0 "some_small_symbolic_mem_operand" "")]
5527 "TARGET_EXPLICIT_RELOCS && reload_completed"
5529 "operands[0] = split_small_symbolic_mem_operand (operands[0]);")
5531 (define_insn "movdi_er_high_g"
5532 [(set (match_operand:DI 0 "register_operand" "=r")
5533 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5534 (match_operand:DI 2 "global_symbolic_operand" "")
5535 (match_operand 3 "const_int_operand" "")]
5537 "TARGET_EXPLICIT_RELOCS"
5539 if (INTVAL (operands[3]) == 0)
5540 return "ldq %0,%2(%1)\t\t!literal";
5542 return "ldq %0,%2(%1)\t\t!literal!%3";
5544 [(set_attr "type" "ldsym")])
5547 [(set (match_operand:DI 0 "register_operand" "")
5548 (match_operand:DI 1 "global_symbolic_operand" ""))]
5549 "TARGET_EXPLICIT_RELOCS && reload_completed"
5551 (unspec:DI [(match_dup 2)
5553 (const_int 0)] UNSPEC_LITERAL))]
5554 "operands[2] = pic_offset_table_rtx;")
5556 (define_insn "*movdi_er_nofix"
5557 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5558 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5559 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5560 && (register_operand (operands[0], DImode)
5561 || reg_or_0_operand (operands[1], DImode))"
5573 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5575 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5576 ;; have been split up by the rules above but we shouldn't reject the
5577 ;; possibility of them getting through.
5579 (define_insn "*movdi_nofix"
5580 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5581 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5583 && (register_operand (operands[0], DImode)
5584 || reg_or_0_operand (operands[1], DImode))"
5589 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5596 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5597 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5599 (define_insn "*movdi_er_fix"
5600 [(set (match_operand:DI 0 "nonimmediate_operand"
5601 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5602 (match_operand:DI 1 "input_operand"
5603 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5604 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5605 && (register_operand (operands[0], DImode)
5606 || reg_or_0_operand (operands[1], DImode))"
5620 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5622 (define_insn "*movdi_fix"
5623 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5624 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5625 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5626 && (register_operand (operands[0], DImode)
5627 || reg_or_0_operand (operands[1], DImode))"
5640 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5642 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5643 ;; often appears dead to the life analysis code, at which point we
5644 ;; abort for emitting dead prologue instructions. Force this live.
5646 (define_insn "force_movdi"
5647 [(set (match_operand:DI 0 "register_operand" "=r")
5648 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5649 UNSPECV_FORCE_MOV))]
5652 [(set_attr "type" "ilog")])
5654 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5655 ;; memory, and construct long 32-bit constants.
5657 (define_expand "movdi"
5658 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5659 (match_operand:DI 1 "general_operand" ""))]
5662 if (alpha_expand_mov (DImode, operands))
5666 ;; Split a load of a large constant into the appropriate two-insn
5670 [(set (match_operand:DI 0 "register_operand" "")
5671 (match_operand:DI 1 "const_int_operand" ""))]
5672 "! add_operand (operands[1], DImode)"
5673 [(set (match_dup 0) (match_dup 2))
5674 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5677 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5679 if (tem == operands[0])
5685 ;; These are the partial-word cases.
5687 ;; First we have the code to load an aligned word. Operand 0 is the register
5688 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5689 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5690 ;; number of bits within the word that the value is. Operand 3 is an SImode
5691 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5692 ;; same register. It is allowed to conflict with operand 1 as well.
5694 (define_expand "aligned_loadqi"
5695 [(set (match_operand:SI 3 "register_operand" "")
5696 (match_operand:SI 1 "memory_operand" ""))
5697 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5698 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5700 (match_operand:DI 2 "const_int_operand" "")))]
5705 (define_expand "aligned_loadhi"
5706 [(set (match_operand:SI 3 "register_operand" "")
5707 (match_operand:SI 1 "memory_operand" ""))
5708 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5709 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5711 (match_operand:DI 2 "const_int_operand" "")))]
5716 ;; Similar for unaligned loads, where we use the sequence from the
5717 ;; Alpha Architecture manual. We have to distinguish between little-endian
5718 ;; and big-endian systems as the sequences are different.
5720 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5721 ;; operand 3 can overlap the input and output registers.
5723 (define_expand "unaligned_loadqi"
5724 [(use (match_operand:QI 0 "register_operand" ""))
5725 (use (match_operand:DI 1 "address_operand" ""))
5726 (use (match_operand:DI 2 "register_operand" ""))
5727 (use (match_operand:DI 3 "register_operand" ""))]
5730 if (WORDS_BIG_ENDIAN)
5731 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5732 operands[2], operands[3]));
5734 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5735 operands[2], operands[3]));
5739 (define_expand "unaligned_loadqi_le"
5740 [(set (match_operand:DI 2 "register_operand" "")
5741 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5743 (set (match_operand:DI 3 "register_operand" "")
5745 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5746 (zero_extract:DI (match_dup 2)
5748 (ashift:DI (match_dup 3) (const_int 3))))]
5749 "! WORDS_BIG_ENDIAN"
5752 (define_expand "unaligned_loadqi_be"
5753 [(set (match_operand:DI 2 "register_operand" "")
5754 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5756 (set (match_operand:DI 3 "register_operand" "")
5758 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5759 (zero_extract:DI (match_dup 2)
5763 (ashift:DI (match_dup 3) (const_int 3)))))]
5767 (define_expand "unaligned_loadhi"
5768 [(use (match_operand:QI 0 "register_operand" ""))
5769 (use (match_operand:DI 1 "address_operand" ""))
5770 (use (match_operand:DI 2 "register_operand" ""))
5771 (use (match_operand:DI 3 "register_operand" ""))]
5774 if (WORDS_BIG_ENDIAN)
5775 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5776 operands[2], operands[3]));
5778 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5779 operands[2], operands[3]));
5783 (define_expand "unaligned_loadhi_le"
5784 [(set (match_operand:DI 2 "register_operand" "")
5785 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5787 (set (match_operand:DI 3 "register_operand" "")
5789 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5790 (zero_extract:DI (match_dup 2)
5792 (ashift:DI (match_dup 3) (const_int 3))))]
5793 "! WORDS_BIG_ENDIAN"
5796 (define_expand "unaligned_loadhi_be"
5797 [(set (match_operand:DI 2 "register_operand" "")
5798 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5800 (set (match_operand:DI 3 "register_operand" "")
5801 (plus:DI (match_dup 1) (const_int 1)))
5802 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5803 (zero_extract:DI (match_dup 2)
5807 (ashift:DI (match_dup 3) (const_int 3)))))]
5811 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5812 ;; aligned SImode MEM. Operand 1 is the register containing the
5813 ;; byte or word to store. Operand 2 is the number of bits within the word that
5814 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5816 (define_expand "aligned_store"
5817 [(set (match_operand:SI 3 "register_operand" "")
5818 (match_operand:SI 0 "memory_operand" ""))
5819 (set (subreg:DI (match_dup 3) 0)
5820 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5821 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5822 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5823 (match_operand:DI 2 "const_int_operand" "")))
5824 (set (subreg:DI (match_dup 4) 0)
5825 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5826 (set (match_dup 0) (match_dup 4))]
5829 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5830 << INTVAL (operands[2])));
5833 ;; For the unaligned byte and halfword cases, we use code similar to that
5834 ;; in the ;; Architecture book, but reordered to lower the number of registers
5835 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5836 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5837 ;; be the same temporary, if desired. If the address is in a register,
5838 ;; operand 2 can be that register.
5840 (define_expand "unaligned_storeqi"
5841 [(use (match_operand:DI 0 "address_operand" ""))
5842 (use (match_operand:QI 1 "register_operand" ""))
5843 (use (match_operand:DI 2 "register_operand" ""))
5844 (use (match_operand:DI 3 "register_operand" ""))
5845 (use (match_operand:DI 4 "register_operand" ""))]
5848 if (WORDS_BIG_ENDIAN)
5849 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5850 operands[2], operands[3],
5853 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5854 operands[2], operands[3],
5859 (define_expand "unaligned_storeqi_le"
5860 [(set (match_operand:DI 3 "register_operand" "")
5861 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5863 (set (match_operand:DI 2 "register_operand" "")
5866 (and:DI (not:DI (ashift:DI (const_int 255)
5867 (ashift:DI (match_dup 2) (const_int 3))))
5869 (set (match_operand:DI 4 "register_operand" "")
5870 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5871 (ashift:DI (match_dup 2) (const_int 3))))
5872 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5873 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5875 "! WORDS_BIG_ENDIAN"
5878 (define_expand "unaligned_storeqi_be"
5879 [(set (match_operand:DI 3 "register_operand" "")
5880 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5882 (set (match_operand:DI 2 "register_operand" "")
5885 (and:DI (not:DI (ashift:DI (const_int 255)
5886 (minus:DI (const_int 56)
5887 (ashift:DI (match_dup 2) (const_int 3)))))
5889 (set (match_operand:DI 4 "register_operand" "")
5890 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5891 (minus:DI (const_int 56)
5892 (ashift:DI (match_dup 2) (const_int 3)))))
5893 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5894 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5899 (define_expand "unaligned_storehi"
5900 [(use (match_operand:DI 0 "address_operand" ""))
5901 (use (match_operand:HI 1 "register_operand" ""))
5902 (use (match_operand:DI 2 "register_operand" ""))
5903 (use (match_operand:DI 3 "register_operand" ""))
5904 (use (match_operand:DI 4 "register_operand" ""))]
5907 if (WORDS_BIG_ENDIAN)
5908 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5909 operands[2], operands[3],
5912 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5913 operands[2], operands[3],
5918 (define_expand "unaligned_storehi_le"
5919 [(set (match_operand:DI 3 "register_operand" "")
5920 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5922 (set (match_operand:DI 2 "register_operand" "")
5925 (and:DI (not:DI (ashift:DI (const_int 65535)
5926 (ashift:DI (match_dup 2) (const_int 3))))
5928 (set (match_operand:DI 4 "register_operand" "")
5929 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5930 (ashift:DI (match_dup 2) (const_int 3))))
5931 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5932 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5934 "! WORDS_BIG_ENDIAN"
5937 (define_expand "unaligned_storehi_be"
5938 [(set (match_operand:DI 3 "register_operand" "")
5939 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5941 (set (match_operand:DI 2 "register_operand" "")
5942 (plus:DI (match_dup 0) (const_int 1)))
5944 (and:DI (not:DI (ashift:DI
5946 (minus:DI (const_int 56)
5947 (ashift:DI (match_dup 2) (const_int 3)))))
5949 (set (match_operand:DI 4 "register_operand" "")
5950 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5951 (minus:DI (const_int 56)
5952 (ashift:DI (match_dup 2) (const_int 3)))))
5953 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5954 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5959 ;; Here are the define_expand's for QI and HI moves that use the above
5960 ;; patterns. We have the normal sets, plus the ones that need scratch
5961 ;; registers for reload.
5963 (define_expand "movqi"
5964 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5965 (match_operand:QI 1 "general_operand" ""))]
5969 ? alpha_expand_mov (QImode, operands)
5970 : alpha_expand_mov_nobwx (QImode, operands))
5974 (define_expand "movhi"
5975 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5976 (match_operand:HI 1 "general_operand" ""))]
5980 ? alpha_expand_mov (HImode, operands)
5981 : alpha_expand_mov_nobwx (HImode, operands))
5985 ;; Here are the versions for reload. Note that in the unaligned cases
5986 ;; we know that the operand must not be a pseudo-register because stack
5987 ;; slots are always aligned references.
5989 (define_expand "reload_inqi"
5990 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5991 (match_operand:QI 1 "any_memory_operand" "m")
5992 (match_operand:TI 2 "register_operand" "=&r")])]
5997 if (GET_CODE (operands[1]) != MEM)
6000 if (aligned_memory_operand (operands[1], QImode))
6002 seq = gen_reload_inqi_help (operands[0], operands[1],
6003 gen_rtx_REG (SImode, REGNO (operands[2])));
6009 /* It is possible that one of the registers we got for operands[2]
6010 might coincide with that of operands[0] (which is why we made
6011 it TImode). Pick the other one to use as our scratch. */
6012 if (REGNO (operands[0]) == REGNO (operands[2]))
6013 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6015 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6017 addr = get_unaligned_address (operands[1], 0);
6018 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
6019 gen_rtx_REG (DImode, REGNO (operands[0])));
6020 alpha_set_memflags (seq, operands[1]);
6026 (define_expand "reload_inhi"
6027 [(parallel [(match_operand:HI 0 "register_operand" "=r")
6028 (match_operand:HI 1 "any_memory_operand" "m")
6029 (match_operand:TI 2 "register_operand" "=&r")])]
6034 if (GET_CODE (operands[1]) != MEM)
6037 if (aligned_memory_operand (operands[1], HImode))
6039 seq = gen_reload_inhi_help (operands[0], operands[1],
6040 gen_rtx_REG (SImode, REGNO (operands[2])));
6046 /* It is possible that one of the registers we got for operands[2]
6047 might coincide with that of operands[0] (which is why we made
6048 it TImode). Pick the other one to use as our scratch. */
6049 if (REGNO (operands[0]) == REGNO (operands[2]))
6050 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6052 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6054 addr = get_unaligned_address (operands[1], 0);
6055 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
6056 gen_rtx_REG (DImode, REGNO (operands[0])));
6057 alpha_set_memflags (seq, operands[1]);
6063 (define_expand "reload_outqi"
6064 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6065 (match_operand:QI 1 "register_operand" "r")
6066 (match_operand:TI 2 "register_operand" "=&r")])]
6069 if (GET_CODE (operands[0]) != MEM)
6072 if (aligned_memory_operand (operands[0], QImode))
6074 emit_insn (gen_reload_outqi_help
6075 (operands[0], operands[1],
6076 gen_rtx_REG (SImode, REGNO (operands[2])),
6077 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6081 rtx addr = get_unaligned_address (operands[0], 0);
6082 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6083 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6084 rtx scratch3 = scratch1;
6087 if (GET_CODE (addr) == REG)
6090 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6091 scratch2, scratch3);
6092 alpha_set_memflags (seq, operands[0]);
6098 (define_expand "reload_outhi"
6099 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6100 (match_operand:HI 1 "register_operand" "r")
6101 (match_operand:TI 2 "register_operand" "=&r")])]
6104 if (GET_CODE (operands[0]) != MEM)
6107 if (aligned_memory_operand (operands[0], HImode))
6109 emit_insn (gen_reload_outhi_help
6110 (operands[0], operands[1],
6111 gen_rtx_REG (SImode, REGNO (operands[2])),
6112 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6116 rtx addr = get_unaligned_address (operands[0], 0);
6117 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6118 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6119 rtx scratch3 = scratch1;
6122 if (GET_CODE (addr) == REG)
6125 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6126 scratch2, scratch3);
6127 alpha_set_memflags (seq, operands[0]);
6133 ;; Helpers for the above. The way reload is structured, we can't
6134 ;; always get a proper address for a stack slot during reload_foo
6135 ;; expansion, so we must delay our address manipulations until after.
6137 (define_insn "reload_inqi_help"
6138 [(set (match_operand:QI 0 "register_operand" "=r")
6139 (match_operand:QI 1 "memory_operand" "m"))
6140 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6141 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6144 (define_insn "reload_inhi_help"
6145 [(set (match_operand:HI 0 "register_operand" "=r")
6146 (match_operand:HI 1 "memory_operand" "m"))
6147 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6148 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6151 (define_insn "reload_outqi_help"
6152 [(set (match_operand:QI 0 "memory_operand" "=m")
6153 (match_operand:QI 1 "register_operand" "r"))
6154 (clobber (match_operand:SI 2 "register_operand" "=r"))
6155 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6156 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6159 (define_insn "reload_outhi_help"
6160 [(set (match_operand:HI 0 "memory_operand" "=m")
6161 (match_operand:HI 1 "register_operand" "r"))
6162 (clobber (match_operand:SI 2 "register_operand" "=r"))
6163 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6164 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6168 [(set (match_operand:QI 0 "register_operand" "")
6169 (match_operand:QI 1 "memory_operand" ""))
6170 (clobber (match_operand:SI 2 "register_operand" ""))]
6171 "! TARGET_BWX && reload_completed"
6174 rtx aligned_mem, bitnum;
6175 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6177 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6183 [(set (match_operand:HI 0 "register_operand" "")
6184 (match_operand:HI 1 "memory_operand" ""))
6185 (clobber (match_operand:SI 2 "register_operand" ""))]
6186 "! TARGET_BWX && reload_completed"
6189 rtx aligned_mem, bitnum;
6190 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6192 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6198 [(set (match_operand:QI 0 "memory_operand" "")
6199 (match_operand:QI 1 "register_operand" ""))
6200 (clobber (match_operand:SI 2 "register_operand" ""))
6201 (clobber (match_operand:SI 3 "register_operand" ""))]
6202 "! TARGET_BWX && reload_completed"
6205 rtx aligned_mem, bitnum;
6206 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6207 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6208 operands[2], operands[3]));
6213 [(set (match_operand:HI 0 "memory_operand" "")
6214 (match_operand:HI 1 "register_operand" ""))
6215 (clobber (match_operand:SI 2 "register_operand" ""))
6216 (clobber (match_operand:SI 3 "register_operand" ""))]
6217 "! TARGET_BWX && reload_completed"
6220 rtx aligned_mem, bitnum;
6221 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6222 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6223 operands[2], operands[3]));
6227 ;; Bit field extract patterns which use ext[wlq][lh]
6229 (define_expand "extv"
6230 [(set (match_operand:DI 0 "register_operand" "")
6231 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6232 (match_operand:DI 2 "immediate_operand" "")
6233 (match_operand:DI 3 "immediate_operand" "")))]
6238 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6239 if (INTVAL (operands[3]) % 8 != 0
6240 || (INTVAL (operands[2]) != 16
6241 && INTVAL (operands[2]) != 32
6242 && INTVAL (operands[2]) != 64))
6245 /* From mips.md: extract_bit_field doesn't verify that our source
6246 matches the predicate, so we force it to be a MEM here. */
6247 if (GET_CODE (operands[1]) != MEM)
6250 /* The bit number is relative to the mode of operand 1 which is
6251 usually QImode (this might actually be a bug in expmed.c). Note
6252 that the bit number is negative in big-endian mode in this case.
6253 We have to convert that to the offset. */
6254 if (WORDS_BIG_ENDIAN)
6255 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6256 - INTVAL (operands[2]) - INTVAL (operands[3]);
6258 ofs = INTVAL (operands[3]);
6262 alpha_expand_unaligned_load (operands[0], operands[1],
6263 INTVAL (operands[2]) / 8,
6268 (define_expand "extzv"
6269 [(set (match_operand:DI 0 "register_operand" "")
6270 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6271 (match_operand:DI 2 "immediate_operand" "")
6272 (match_operand:DI 3 "immediate_operand" "")))]
6275 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6276 if (INTVAL (operands[3]) % 8 != 0
6277 || (INTVAL (operands[2]) != 8
6278 && INTVAL (operands[2]) != 16
6279 && INTVAL (operands[2]) != 32
6280 && INTVAL (operands[2]) != 64))
6283 if (GET_CODE (operands[1]) == MEM)
6287 /* Fail 8 bit fields, falling back on a simple byte load. */
6288 if (INTVAL (operands[2]) == 8)
6291 /* The bit number is relative to the mode of operand 1 which is
6292 usually QImode (this might actually be a bug in expmed.c). Note
6293 that the bit number is negative in big-endian mode in this case.
6294 We have to convert that to the offset. */
6295 if (WORDS_BIG_ENDIAN)
6296 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6297 - INTVAL (operands[2]) - INTVAL (operands[3]);
6299 ofs = INTVAL (operands[3]);
6303 alpha_expand_unaligned_load (operands[0], operands[1],
6304 INTVAL (operands[2]) / 8,
6310 (define_expand "insv"
6311 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6312 (match_operand:DI 1 "immediate_operand" "")
6313 (match_operand:DI 2 "immediate_operand" ""))
6314 (match_operand:DI 3 "register_operand" ""))]
6319 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6320 if (INTVAL (operands[2]) % 8 != 0
6321 || (INTVAL (operands[1]) != 16
6322 && INTVAL (operands[1]) != 32
6323 && INTVAL (operands[1]) != 64))
6326 /* From mips.md: store_bit_field doesn't verify that our source
6327 matches the predicate, so we force it to be a MEM here. */
6328 if (GET_CODE (operands[0]) != MEM)
6331 /* The bit number is relative to the mode of operand 1 which is
6332 usually QImode (this might actually be a bug in expmed.c). Note
6333 that the bit number is negative in big-endian mode in this case.
6334 We have to convert that to the offset. */
6335 if (WORDS_BIG_ENDIAN)
6336 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6337 - INTVAL (operands[1]) - INTVAL (operands[2]);
6339 ofs = INTVAL (operands[2]);
6343 alpha_expand_unaligned_store (operands[0], operands[3],
6344 INTVAL (operands[1]) / 8, ofs);
6348 ;; Block move/clear, see alpha.c for more details.
6349 ;; Argument 0 is the destination
6350 ;; Argument 1 is the source
6351 ;; Argument 2 is the length
6352 ;; Argument 3 is the alignment
6354 (define_expand "movstrqi"
6355 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6356 (match_operand:BLK 1 "memory_operand" ""))
6357 (use (match_operand:DI 2 "immediate_operand" ""))
6358 (use (match_operand:DI 3 "immediate_operand" ""))])]
6361 if (alpha_expand_block_move (operands))
6367 (define_expand "clrstrqi"
6368 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6370 (use (match_operand:DI 1 "immediate_operand" ""))
6371 (use (match_operand:DI 2 "immediate_operand" ""))])]
6374 if (alpha_expand_block_clear (operands))
6380 ;; Subroutine of stack space allocation. Perform a stack probe.
6381 (define_expand "probe_stack"
6382 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6385 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6386 INTVAL (operands[0])));
6387 MEM_VOLATILE_P (operands[1]) = 1;
6389 operands[0] = const0_rtx;
6392 ;; This is how we allocate stack space. If we are allocating a
6393 ;; constant amount of space and we know it is less than 4096
6394 ;; bytes, we need do nothing.
6396 ;; If it is more than 4096 bytes, we need to probe the stack
6398 (define_expand "allocate_stack"
6400 (plus:DI (reg:DI 30)
6401 (match_operand:DI 1 "reg_or_cint_operand" "")))
6402 (set (match_operand:DI 0 "register_operand" "=r")
6406 if (GET_CODE (operands[1]) == CONST_INT
6407 && INTVAL (operands[1]) < 32768)
6409 if (INTVAL (operands[1]) >= 4096)
6411 /* We do this the same way as in the prologue and generate explicit
6412 probes. Then we update the stack by the constant. */
6416 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6417 while (probed + 8192 < INTVAL (operands[1]))
6418 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6420 if (probed + 4096 < INTVAL (operands[1]))
6421 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6424 operands[1] = GEN_INT (- INTVAL (operands[1]));
6425 operands[2] = virtual_stack_dynamic_rtx;
6430 rtx loop_label = gen_label_rtx ();
6431 rtx want = gen_reg_rtx (Pmode);
6432 rtx tmp = gen_reg_rtx (Pmode);
6435 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6436 force_reg (Pmode, operands[1])));
6437 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6439 if (GET_CODE (operands[1]) != CONST_INT)
6441 out_label = gen_label_rtx ();
6442 emit_insn (gen_cmpdi (want, tmp));
6443 emit_jump_insn (gen_bgeu (out_label));
6446 emit_label (loop_label);
6447 memref = gen_rtx_MEM (DImode, tmp);
6448 MEM_VOLATILE_P (memref) = 1;
6449 emit_move_insn (memref, const0_rtx);
6450 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6451 emit_insn (gen_cmpdi (tmp, want));
6452 emit_jump_insn (gen_bgtu (loop_label));
6454 memref = gen_rtx_MEM (DImode, want);
6455 MEM_VOLATILE_P (memref) = 1;
6456 emit_move_insn (memref, const0_rtx);
6459 emit_label (out_label);
6461 emit_move_insn (stack_pointer_rtx, want);
6462 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6467 ;; This is used by alpha_expand_prolog to do the same thing as above,
6468 ;; except we cannot at that time generate new basic blocks, so we hide
6469 ;; the loop in this one insn.
6471 (define_insn "prologue_stack_probe_loop"
6472 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6473 (match_operand:DI 1 "register_operand" "r")]
6477 operands[2] = gen_label_rtx ();
6478 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6479 CODE_LABEL_NUMBER (operands[2]));
6481 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6483 [(set_attr "length" "16")
6484 (set_attr "type" "multi")])
6486 (define_expand "prologue"
6487 [(clobber (const_int 0))]
6490 alpha_expand_prologue ();
6494 ;; These take care of emitting the ldgp insn in the prologue. This will be
6495 ;; an lda/ldah pair and we want to align them properly. So we have two
6496 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6497 ;; and the second of which emits nothing. However, both are marked as type
6498 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6501 (define_expand "prologue_ldgp"
6503 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6505 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6508 operands[0] = pic_offset_table_rtx;
6509 operands[1] = gen_rtx_REG (Pmode, 27);
6510 operands[2] = (TARGET_EXPLICIT_RELOCS
6511 ? GEN_INT (alpha_next_sequence_number++)
6515 (define_insn "*ldgp_er_1"
6516 [(set (match_operand:DI 0 "register_operand" "=r")
6517 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6518 (match_operand 2 "const_int_operand" "")]
6520 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6521 "ldah %0,0(%1)\t\t!gpdisp!%2")
6523 (define_insn "*ldgp_er_2"
6524 [(set (match_operand:DI 0 "register_operand" "=r")
6525 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6526 (match_operand 2 "const_int_operand" "")]
6528 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6529 "lda %0,0(%1)\t\t!gpdisp!%2")
6531 (define_insn "*prologue_ldgp_er_2"
6532 [(set (match_operand:DI 0 "register_operand" "=r")
6533 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6534 (match_operand 2 "const_int_operand" "")]
6536 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6537 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6539 (define_insn "*prologue_ldgp_1"
6540 [(set (match_operand:DI 0 "register_operand" "=r")
6541 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6542 (match_operand 2 "const_int_operand" "")]
6545 "ldgp %0,0(%1)\n$%~..ng:")
6547 (define_insn "*prologue_ldgp_2"
6548 [(set (match_operand:DI 0 "register_operand" "=r")
6549 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6550 (match_operand 2 "const_int_operand" "")]
6555 ;; The _mcount profiling hook has special calling conventions, and
6556 ;; does not clobber all the registers that a normal call would. So
6557 ;; hide the fact this is a call at all.
6559 (define_insn "prologue_mcount"
6560 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6563 if (TARGET_EXPLICIT_RELOCS)
6564 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6565 cannot be called via the PLT. */
6566 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6568 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6570 [(set_attr "type" "multi")
6571 (set_attr "length" "8")])
6573 (define_insn "init_fp"
6574 [(set (match_operand:DI 0 "register_operand" "=r")
6575 (match_operand:DI 1 "register_operand" "r"))
6576 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6580 (define_expand "epilogue"
6584 alpha_expand_epilogue ();
6587 (define_expand "sibcall_epilogue"
6591 alpha_expand_epilogue ();
6595 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6596 ;; the frame size into a register. We use this pattern to ensure
6597 ;; we get lda instead of addq.
6598 (define_insn "nt_lda"
6599 [(set (match_operand:DI 0 "register_operand" "=r")
6600 (unspec:DI [(match_dup 0)
6601 (match_operand:DI 1 "const_int_operand" "n")]
6606 (define_expand "builtin_longjmp"
6607 [(use (match_operand:DI 0 "register_operand" "r"))]
6610 /* The elements of the buffer are, in order: */
6611 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6612 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6613 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6614 rtx pv = gen_rtx_REG (Pmode, 27);
6616 /* This bit is the same as expand_builtin_longjmp. */
6617 emit_move_insn (hard_frame_pointer_rtx, fp);
6618 emit_move_insn (pv, lab);
6619 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6620 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6621 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6623 /* Load the label we are jumping through into $27 so that we know
6624 where to look for it when we get back to setjmp's function for
6625 restoring the gp. */
6626 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6631 ;; This is effectively a copy of indirect_jump, but constrained such
6632 ;; that register renaming cannot foil our cunning plan with $27.
6633 (define_insn "builtin_longjmp_internal"
6635 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6639 [(set_attr "type" "ibr")])
6641 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6642 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6643 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6644 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6646 (define_insn "*builtin_setjmp_receiver_er_1"
6647 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6648 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6649 "br $27,$LSJ%=\n$LSJ%=:"
6650 [(set_attr "type" "ibr")])
6653 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6654 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6655 && prev_nonnote_insn (insn) == operands[0]"
6659 (define_insn "*builtin_setjmp_receiver_1"
6660 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6662 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6663 [(set_attr "length" "12")
6664 (set_attr "type" "multi")])
6666 (define_expand "builtin_setjmp_receiver_er"
6667 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6669 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6671 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6674 operands[1] = pic_offset_table_rtx;
6675 operands[2] = gen_rtx_REG (Pmode, 27);
6676 operands[3] = GEN_INT (alpha_next_sequence_number++);
6679 (define_expand "builtin_setjmp_receiver"
6680 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6683 if (TARGET_EXPLICIT_RELOCS)
6685 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6690 (define_expand "exception_receiver_er"
6692 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6694 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6697 operands[0] = pic_offset_table_rtx;
6698 operands[1] = gen_rtx_REG (Pmode, 26);
6699 operands[2] = GEN_INT (alpha_next_sequence_number++);
6702 (define_expand "exception_receiver"
6703 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6706 if (TARGET_LD_BUGGY_LDGP)
6707 operands[0] = alpha_gp_save_rtx ();
6708 else if (TARGET_EXPLICIT_RELOCS)
6710 emit_insn (gen_exception_receiver_er ());
6714 operands[0] = const0_rtx;
6717 (define_insn "*exception_receiver_1"
6718 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6719 "! TARGET_LD_BUGGY_LDGP"
6721 [(set_attr "length" "8")
6722 (set_attr "type" "multi")])
6724 (define_insn "*exception_receiver_2"
6725 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
6727 "TARGET_LD_BUGGY_LDGP"
6731 [(set_attr "type" "ilog,ild")])
6733 (define_expand "nonlocal_goto_receiver"
6734 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6735 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6736 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6738 "TARGET_ABI_OPEN_VMS"
6741 (define_insn "arg_home"
6742 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6757 (clobber (mem:BLK (const_int 0)))
6758 (clobber (reg:DI 24))
6759 (clobber (reg:DI 25))
6760 (clobber (reg:DI 0))]
6761 "TARGET_ABI_OPEN_VMS"
6762 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6763 [(set_attr "length" "16")
6764 (set_attr "type" "multi")])
6766 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6768 (define_expand "umk_mismatch_args"
6769 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6770 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6771 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6772 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6775 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6776 "TARGET_ABI_UNICOSMK"
6778 operands[1] = gen_reg_rtx (DImode);
6779 operands[2] = gen_reg_rtx (DImode);
6780 operands[3] = gen_reg_rtx (DImode);
6783 (define_insn "arg_home_umk"
6784 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6799 (clobber (mem:BLK (const_int 0)))
6801 (clobber (reg:DI 22))
6802 (clobber (reg:DI 23))
6803 (clobber (reg:DI 24))
6804 (clobber (reg:DI 0))
6805 (clobber (reg:DI 1))
6806 (clobber (reg:DI 2))
6807 (clobber (reg:DI 3))
6808 (clobber (reg:DI 4))
6809 (clobber (reg:DI 5))
6810 (clobber (reg:DI 6))
6811 (clobber (reg:DI 7))
6812 (clobber (reg:DI 8))])]
6813 "TARGET_ABI_UNICOSMK"
6814 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6815 [(set_attr "length" "16")
6816 (set_attr "type" "multi")])
6820 ;; On EV4, these instructions are nops -- no load occurs.
6822 ;; On EV5, these instructions act as a normal load, and thus can trap
6823 ;; if the address is invalid. The OS may (or may not) handle this in
6824 ;; the entMM fault handler and suppress the fault. If so, then this
6825 ;; has the effect of a read prefetch instruction.
6827 ;; On EV6, these become official prefetch instructions.
6829 (define_insn "prefetch"
6830 [(prefetch (match_operand:DI 0 "address_operand" "p")
6831 (match_operand:DI 1 "const_int_operand" "n")
6832 (match_operand:DI 2 "const_int_operand" "n"))]
6833 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6835 /* Interpret "no temporal locality" as this data should be evicted once
6836 it is used. The "evict next" alternatives load the data into the cache
6837 and leave the LRU eviction counter pointing to that block. */
6838 static const char * const alt[2][2] = {
6840 "lds $f31,%a0", /* read, evict next */
6841 "ldl $31,%a0", /* read, evict last */
6844 "ldt $f31,%a0", /* write, evict next */
6845 "ldq $31,%a0", /* write, evict last */
6849 bool write = INTVAL (operands[1]) != 0;
6850 bool lru = INTVAL (operands[2]) != 0;
6852 return alt[write][lru];
6854 [(set_attr "type" "ild")])
6856 ;; Close the trap shadow of preceding instructions. This is generated
6859 (define_insn "trapb"
6860 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6863 [(set_attr "type" "misc")])
6865 ;; No-op instructions used by machine-dependent reorg to preserve
6866 ;; alignment for instruction issue.
6867 ;; The Unicos/Mk assembler does not support these opcodes.
6873 [(set_attr "type" "ilog")])
6878 "cpys $f31,$f31,$f31"
6879 [(set_attr "type" "fcpys")])
6886 ;; On Unicos/Mk we use a macro for aligning code.
6888 (define_insn "realign"
6889 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6893 if (TARGET_ABI_UNICOSMK)
6894 return "gcc@code@align %0";
6896 return ".align %0 #realign";
6899 ;; The call patterns are at the end of the file because their
6900 ;; wildcard operand0 interferes with nice recognition.
6902 (define_insn "*call_value_osf_1_er"
6903 [(set (match_operand 0 "" "")
6904 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6905 (match_operand 2 "" "")))
6907 (clobber (reg:DI 26))]
6908 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6910 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6912 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6913 [(set_attr "type" "jsr")
6914 (set_attr "length" "12,*,16")])
6916 ;; We must use peep2 instead of a split because we need accurate life
6917 ;; information for $gp. Consider the case of { bar(); while (1); }.
6919 [(parallel [(set (match_operand 0 "" "")
6920 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6921 (match_operand 2 "" "")))
6923 (clobber (reg:DI 26))])]
6924 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6925 && ! current_file_function_operand (operands[1], Pmode)
6926 && peep2_regno_dead_p (1, 29)"
6927 [(parallel [(set (match_dup 0)
6928 (call (mem:DI (match_dup 3))
6930 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6931 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6933 (use (match_dup 4))])]
6935 if (CONSTANT_P (operands[1]))
6937 operands[3] = gen_rtx_REG (Pmode, 27);
6938 operands[4] = GEN_INT (alpha_next_sequence_number++);
6939 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6940 operands[1], operands[4]));
6944 operands[3] = operands[1];
6945 operands[1] = const0_rtx;
6946 operands[4] = const0_rtx;
6951 [(parallel [(set (match_operand 0 "" "")
6952 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6953 (match_operand 2 "" "")))
6955 (clobber (reg:DI 26))])]
6956 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6957 && ! current_file_function_operand (operands[1], Pmode)
6958 && ! peep2_regno_dead_p (1, 29)"
6959 [(parallel [(set (match_dup 0)
6960 (call (mem:DI (match_dup 3))
6962 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6963 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6965 (use (match_dup 5))])
6967 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6969 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6971 if (CONSTANT_P (operands[1]))
6973 operands[3] = gen_rtx_REG (Pmode, 27);
6974 operands[5] = GEN_INT (alpha_next_sequence_number++);
6975 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6976 operands[1], operands[5]));
6980 operands[3] = operands[1];
6981 operands[1] = const0_rtx;
6982 operands[5] = const0_rtx;
6984 operands[4] = GEN_INT (alpha_next_sequence_number++);
6987 ;; We add a blockage unspec_volatile to prevent insns from moving down
6988 ;; from above the call to in between the call and the ldah gpdisp.
6989 (define_insn "*call_value_osf_2_er"
6990 [(set (match_operand 0 "" "")
6991 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6992 (match_operand 2 "" "")))
6994 (plus:DI (pc) (const_int 4)))
6995 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6996 (use (match_operand 3 "" ""))
6997 (use (match_operand 4 "const_int_operand" ""))]
6998 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6999 "jsr $26,(%1),%3%J4"
7000 [(set_attr "type" "jsr")])
7002 (define_insn "*call_value_osf_1_noreturn"
7003 [(set (match_operand 0 "" "")
7004 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7005 (match_operand 2 "" "")))
7007 (clobber (reg:DI 26))]
7008 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7009 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7014 [(set_attr "type" "jsr")
7015 (set_attr "length" "*,*,8")])
7017 (define_insn "*call_value_osf_1"
7018 [(set (match_operand 0 "" "")
7019 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7020 (match_operand 2 "" "")))
7022 (clobber (reg:DI 26))]
7023 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7025 jsr $26,($27),0\;ldgp $29,0($26)
7027 jsr $26,%1\;ldgp $29,0($26)"
7028 [(set_attr "type" "jsr")
7029 (set_attr "length" "12,*,16")])
7031 (define_insn "*sibcall_value_osf_1_er"
7032 [(set (match_operand 0 "" "")
7033 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7034 (match_operand 2 "" "")))
7035 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7036 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7039 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7040 [(set_attr "type" "jsr")
7041 (set_attr "length" "*,8")])
7043 (define_insn "*sibcall_value_osf_1"
7044 [(set (match_operand 0 "" "")
7045 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7046 (match_operand 2 "" "")))
7047 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7048 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7051 lda $27,%1\;jmp $31,($27),%1"
7052 [(set_attr "type" "jsr")
7053 (set_attr "length" "*,8")])
7055 (define_insn "*call_value_nt_1"
7056 [(set (match_operand 0 "" "")
7057 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7058 (match_operand 2 "" "")))
7059 (clobber (reg:DI 26))]
7060 "TARGET_ABI_WINDOWS_NT"
7065 [(set_attr "type" "jsr")
7066 (set_attr "length" "*,*,12")])
7068 (define_insn "*call_value_vms_1"
7069 [(set (match_operand 0 "" "")
7070 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7071 (match_operand 2 "" "")))
7072 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
7075 (clobber (reg:DI 27))]
7076 "TARGET_ABI_OPEN_VMS"
7078 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
7079 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
7080 [(set_attr "type" "jsr")
7081 (set_attr "length" "12,16")])
7083 (define_insn "*call_value_umk"
7084 [(set (match_operand 0 "" "")
7085 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
7086 (match_operand 2 "" "")))
7088 (clobber (reg:DI 26))]
7089 "TARGET_ABI_UNICOSMK"
7091 [(set_attr "type" "jsr")])