1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
49 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
50 (UNSPECV_LONGJMP 3) ; builtin_longjmp
52 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
54 (UNSPECV_EHR 7) ; exception_receiver
58 (UNSPECV_PLDGP2 11) ; prologue ldgp
61 ;; Where necessary, the suffixes _le and _be are used to distinguish between
62 ;; little-endian and big-endian patterns.
64 ;; Note that the Unicos/Mk assembler does not support the following
65 ;; opcodes: mov, fmov, nop, fnop, unop.
67 ;; Processor type -- this attribute must exactly match the processor_type
68 ;; enumeration in alpha.h.
70 (define_attr "cpu" "ev4,ev5,ev6"
71 (const (symbol_ref "alpha_cpu")))
73 ;; Define an insn type attribute. This is used in function unit delay
74 ;; computations, among other purposes. For the most part, we use the names
75 ;; defined in the EV4 documentation, but add a few that we have to know about
79 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
80 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
81 (const_string "iadd"))
83 ;; Describe a user's asm statement.
84 (define_asm_attributes
85 [(set_attr "type" "multi")])
87 ;; Define the operand size an insn operates on. Used primarily by mul
88 ;; and div operations that have size dependent timings.
90 (define_attr "opsize" "si,di,udi"
93 ;; The TRAP attribute marks instructions that may generate traps
94 ;; (which are imprecise and may need a trapb if software completion
97 (define_attr "trap" "no,yes"
100 ;; The ROUND_SUFFIX attribute marks which instructions require a
101 ;; rounding-mode suffix. The value NONE indicates no suffix,
102 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
104 (define_attr "round_suffix" "none,normal,c"
105 (const_string "none"))
107 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
109 ;; SU accepts only /su (cmpt et al)
110 ;; SUI accepts only /sui (cvtqt and cvtqs)
111 ;; V_SV accepts /v and /sv (cvtql only)
112 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
113 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
115 ;; The actual suffix emitted is controled by alpha_fptm.
117 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
118 (const_string "none"))
120 ;; The length of an instruction sequence in bytes.
122 (define_attr "length" ""
125 ;; On EV4 there are two classes of resources to consider: resources needed
126 ;; to issue, and resources needed to execute. IBUS[01] are in the first
127 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
128 ;; (There are a few other register-like resources, but ...)
130 ; First, describe all of the issue constraints with single cycle delays.
131 ; All insns need a bus, but all except loads require one or the other.
132 (define_function_unit "ev4_ibus0" 1 0
133 (and (eq_attr "cpu" "ev4")
134 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
137 (define_function_unit "ev4_ibus1" 1 0
138 (and (eq_attr "cpu" "ev4")
139 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
142 ; Memory delivers its result in three cycles. Actually return one and
143 ; take care of this in adjust_cost, since we want to handle user-defined
145 (define_function_unit "ev4_abox" 1 0
146 (and (eq_attr "cpu" "ev4")
147 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
150 ; Branches have no delay cost, but do tie up the unit for two cycles.
151 (define_function_unit "ev4_bbox" 1 1
152 (and (eq_attr "cpu" "ev4")
153 (eq_attr "type" "ibr,fbr,jsr"))
156 ; Arithmetic insns are normally have their results available after
157 ; two cycles. There are a number of exceptions. They are encoded in
158 ; ADJUST_COST. Some of the other insns have similar exceptions.
159 (define_function_unit "ev4_ebox" 1 0
160 (and (eq_attr "cpu" "ev4")
161 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
164 (define_function_unit "imul" 1 0
165 (and (eq_attr "cpu" "ev4")
166 (and (eq_attr "type" "imul")
167 (eq_attr "opsize" "si")))
170 (define_function_unit "imul" 1 0
171 (and (eq_attr "cpu" "ev4")
172 (and (eq_attr "type" "imul")
173 (eq_attr "opsize" "!si")))
176 (define_function_unit "ev4_fbox" 1 0
177 (and (eq_attr "cpu" "ev4")
178 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
181 (define_function_unit "fdiv" 1 0
182 (and (eq_attr "cpu" "ev4")
183 (and (eq_attr "type" "fdiv")
184 (eq_attr "opsize" "si")))
187 (define_function_unit "fdiv" 1 0
188 (and (eq_attr "cpu" "ev4")
189 (and (eq_attr "type" "fdiv")
190 (eq_attr "opsize" "di")))
193 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
195 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
196 ;; with the combined resource EBOX.
198 (define_function_unit "ev5_ebox" 2 0
199 (and (eq_attr "cpu" "ev5")
200 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
203 ; Memory takes at least 2 clocks. Return one from here and fix up with
204 ; user-defined latencies in adjust_cost.
205 (define_function_unit "ev5_ebox" 2 0
206 (and (eq_attr "cpu" "ev5")
207 (eq_attr "type" "ild,fld,ldsym"))
210 ; Loads can dual issue with one another, but loads and stores do not mix.
211 (define_function_unit "ev5_e0" 1 0
212 (and (eq_attr "cpu" "ev5")
213 (eq_attr "type" "ild,fld,ldsym"))
215 [(eq_attr "type" "ist,fst")])
217 ; Stores, shifts, multiplies can only issue to E0
218 (define_function_unit "ev5_e0" 1 0
219 (and (eq_attr "cpu" "ev5")
220 (eq_attr "type" "ist,fst,shift,imul"))
223 ; Motion video insns also issue only to E0, and take two ticks.
224 (define_function_unit "ev5_e0" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "mvi"))
229 ; Conditional moves always take 2 ticks.
230 (define_function_unit "ev5_ebox" 2 0
231 (and (eq_attr "cpu" "ev5")
232 (eq_attr "type" "icmov"))
235 ; Branches can only issue to E1
236 (define_function_unit "ev5_e1" 1 0
237 (and (eq_attr "cpu" "ev5")
238 (eq_attr "type" "ibr,jsr"))
241 ; Multiplies also use the integer multiplier.
242 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
243 ; cycles before an integer multiplication completes."
244 (define_function_unit "imul" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "imul")
247 (eq_attr "opsize" "si")))
250 (define_function_unit "imul" 1 0
251 (and (eq_attr "cpu" "ev5")
252 (and (eq_attr "type" "imul")
253 (eq_attr "opsize" "di")))
256 (define_function_unit "imul" 1 0
257 (and (eq_attr "cpu" "ev5")
258 (and (eq_attr "type" "imul")
259 (eq_attr "opsize" "udi")))
262 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
263 ;; on either so we have to play the game again.
265 (define_function_unit "ev5_fbox" 2 0
266 (and (eq_attr "cpu" "ev5")
267 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
270 (define_function_unit "ev5_fm" 1 0
271 (and (eq_attr "cpu" "ev5")
272 (eq_attr "type" "fmul"))
275 ; Add and cmov as you would expect; fbr never produces a result;
276 ; fdiv issues through fa to the divider,
277 (define_function_unit "ev5_fa" 1 0
278 (and (eq_attr "cpu" "ev5")
279 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
282 ; ??? How to: "No instruction can be issued to pipe FA exactly five
283 ; cycles before a floating point divide completes."
284 (define_function_unit "fdiv" 1 0
285 (and (eq_attr "cpu" "ev5")
286 (and (eq_attr "type" "fdiv")
287 (eq_attr "opsize" "si")))
288 15 15) ; 15 to 31 data dependent
290 (define_function_unit "fdiv" 1 0
291 (and (eq_attr "cpu" "ev5")
292 (and (eq_attr "type" "fdiv")
293 (eq_attr "opsize" "di")))
294 22 22) ; 22 to 60 data dependent
296 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
298 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
299 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
301 ;; Conditional moves decompose into two independent primitives, each
302 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
304 (define_function_unit "ev6_ebox" 4 0
305 (and (eq_attr "cpu" "ev6")
306 (eq_attr "type" "icmov"))
309 (define_function_unit "ev6_ebox" 4 0
310 (and (eq_attr "cpu" "ev6")
311 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
314 ;; Integer loads take at least 3 clocks, and only issue to lower units.
315 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
316 (define_function_unit "ev6_l" 2 0
317 (and (eq_attr "cpu" "ev6")
318 (eq_attr "type" "ild,ldsym,ist,fst"))
321 ;; FP loads take at least 4 clocks. Return two from here...
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "fld"))
327 ;; Motion video insns also issue only to U0, and take three ticks.
328 (define_function_unit "ev6_u0" 1 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "mvi"))
333 (define_function_unit "ev6_u" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "mvi"))
338 ;; Shifts issue to either upper pipe.
339 (define_function_unit "ev6_u" 2 0
340 (and (eq_attr "cpu" "ev6")
341 (eq_attr "type" "shift"))
344 ;; Multiplies issue only to U1, and all take 7 ticks.
345 ;; Rather than create a new function unit just for U1, reuse IMUL
346 (define_function_unit "imul" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "imul"))
351 (define_function_unit "ev6_u" 2 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "imul"))
356 ;; Branches issue to either upper pipe
357 (define_function_unit "ev6_u" 2 0
358 (and (eq_attr "cpu" "ev6")
359 (eq_attr "type" "ibr"))
362 ;; Calls only issue to L0.
363 (define_function_unit "ev6_l0" 1 0
364 (and (eq_attr "cpu" "ev6")
365 (eq_attr "type" "jsr"))
368 (define_function_unit "ev6_l" 2 0
369 (and (eq_attr "cpu" "ev6")
370 (eq_attr "type" "jsr"))
373 ;; Ftoi/itof only issue to lower pipes
374 (define_function_unit "ev6_l" 2 0
375 (and (eq_attr "cpu" "ev6")
376 (eq_attr "type" "ftoi"))
379 (define_function_unit "ev6_l" 2 0
380 (and (eq_attr "cpu" "ev6")
381 (eq_attr "type" "itof"))
384 ;; For the FPU we are very similar to EV5, except there's no insn that
385 ;; can issue to fm & fa, so we get to leave that out.
387 (define_function_unit "ev6_fm" 1 0
388 (and (eq_attr "cpu" "ev6")
389 (eq_attr "type" "fmul"))
392 (define_function_unit "ev6_fa" 1 0
393 (and (eq_attr "cpu" "ev6")
394 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
397 (define_function_unit "ev6_fa" 1 0
398 (and (eq_attr "cpu" "ev6")
399 (eq_attr "type" "fcmov"))
402 (define_function_unit "fdiv" 1 0
403 (and (eq_attr "cpu" "ev6")
404 (and (eq_attr "type" "fdiv")
405 (eq_attr "opsize" "si")))
408 (define_function_unit "fdiv" 1 0
409 (and (eq_attr "cpu" "ev6")
410 (and (eq_attr "type" "fdiv")
411 (eq_attr "opsize" "di")))
414 (define_function_unit "fsqrt" 1 0
415 (and (eq_attr "cpu" "ev6")
416 (and (eq_attr "type" "fsqrt")
417 (eq_attr "opsize" "si")))
420 (define_function_unit "fsqrt" 1 0
421 (and (eq_attr "cpu" "ev6")
422 (and (eq_attr "type" "fsqrt")
423 (eq_attr "opsize" "di")))
426 ; ??? The FPU communicates with memory and the integer register file
427 ; via two fp store units. We need a slot in the fst immediately, and
428 ; a slot in LOW after the operand data is ready. At which point the
429 ; data may be moved either to the store queue or the integer register
430 ; file and the insn retired.
433 ;; First define the arithmetic insns. Note that the 32-bit forms also
436 ;; Handle 32-64 bit extension from memory to a floating point register
437 ;; specially, since this occurs frequently in int->double conversions.
439 ;; Note that while we must retain the =f case in the insn for reload's
440 ;; benefit, it should be eliminated after reload, so we should never emit
441 ;; code for that case. But we don't reject the possibility.
443 (define_expand "extendsidi2"
444 [(set (match_operand:DI 0 "register_operand" "")
445 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
449 (define_insn "*extendsidi2_nofix"
450 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
452 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
458 lds %0,%1\;cvtlq %0,%0"
459 [(set_attr "type" "iadd,ild,fadd,fld")
460 (set_attr "length" "*,*,*,8")])
462 (define_insn "*extendsidi2_fix"
463 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
465 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
472 lds %0,%1\;cvtlq %0,%0"
473 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
474 (set_attr "length" "*,*,*,*,8")])
476 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
478 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
479 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
481 [(set (match_dup 2) (match_dup 1))
482 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
483 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
485 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
486 ;; reload when converting fp->int.
489 [(set (match_operand:SI 0 "hard_int_register_operand" "")
490 (match_operand:SI 1 "memory_operand" ""))
491 (set (match_operand:DI 2 "hard_int_register_operand" "")
492 (sign_extend:DI (match_dup 0)))]
493 "true_regnum (operands[0]) == true_regnum (operands[2])
494 || peep2_reg_dead_p (2, operands[0])"
496 (sign_extend:DI (match_dup 1)))]
500 [(set (match_operand:SI 0 "hard_int_register_operand" "")
501 (match_operand:SI 1 "hard_fp_register_operand" ""))
502 (set (match_operand:DI 2 "hard_int_register_operand" "")
503 (sign_extend:DI (match_dup 0)))]
505 && (true_regnum (operands[0]) == true_regnum (operands[2])
506 || peep2_reg_dead_p (2, operands[0]))"
508 (sign_extend:DI (match_dup 1)))]
512 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
513 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
514 (set (match_operand:DI 2 "hard_int_register_operand" "")
516 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
518 (sign_extend:DI (match_dup 1)))]
521 ;; Don't say we have addsi3 if optimizing. This generates better code. We
522 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
523 (define_expand "addsi3"
524 [(set (match_operand:SI 0 "register_operand" "")
525 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
526 (match_operand:SI 2 "add_operand" "")))]
530 (define_insn "*addsi_internal"
531 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
532 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
533 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
542 [(set (match_operand:SI 0 "register_operand" "")
543 (plus:SI (match_operand:SI 1 "register_operand" "")
544 (match_operand:SI 2 "const_int_operand" "")))]
545 "! add_operand (operands[2], SImode)"
546 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
547 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
549 HOST_WIDE_INT val = INTVAL (operands[2]);
550 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
551 HOST_WIDE_INT rest = val - low;
553 operands[3] = GEN_INT (rest);
554 operands[4] = GEN_INT (low);
557 (define_insn "*addsi_se"
558 [(set (match_operand:DI 0 "register_operand" "=r,r")
560 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
561 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
567 (define_insn "*addsi_se2"
568 [(set (match_operand:DI 0 "register_operand" "=r,r")
570 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
571 (match_operand:DI 2 "sext_add_operand" "rI,O"))
579 [(set (match_operand:DI 0 "register_operand" "")
581 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
582 (match_operand:SI 2 "const_int_operand" ""))))
583 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
584 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
585 && INTVAL (operands[2]) % 4 == 0"
586 [(set (match_dup 3) (match_dup 4))
587 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
591 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
597 operands[4] = GEN_INT (val);
598 operands[5] = GEN_INT (mult);
602 [(set (match_operand:DI 0 "register_operand" "")
604 (plus:SI (match_operator:SI 1 "comparison_operator"
605 [(match_operand 2 "" "")
606 (match_operand 3 "" "")])
607 (match_operand:SI 4 "add_operand" ""))))
608 (clobber (match_operand:DI 5 "register_operand" ""))]
610 [(set (match_dup 5) (match_dup 6))
611 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
613 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
614 operands[2], operands[3]);
615 operands[7] = gen_lowpart (SImode, operands[5]);
618 (define_insn "addvsi3"
619 [(set (match_operand:SI 0 "register_operand" "=r,r")
620 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
621 (match_operand:SI 2 "sext_add_operand" "rI,O")))
622 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
623 (sign_extend:DI (match_dup 2)))
624 (sign_extend:DI (plus:SI (match_dup 1)
632 (define_expand "adddi3"
633 [(set (match_operand:DI 0 "register_operand" "")
634 (plus:DI (match_operand:DI 1 "register_operand" "")
635 (match_operand:DI 2 "add_operand" "")))]
639 (define_insn "*adddi_er_high_l"
640 [(set (match_operand:DI 0 "register_operand" "=r")
641 (plus:DI (match_operand:DI 1 "register_operand" "r")
642 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
643 "TARGET_EXPLICIT_RELOCS"
644 "ldah %0,%2(%1)\t\t!gprelhigh")
647 [(set (match_operand:DI 0 "register_operand" "")
648 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
649 "TARGET_EXPLICIT_RELOCS && reload_completed"
651 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
652 "operands[2] = pic_offset_table_rtx;")
654 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
655 ;; With complications like
657 ;; The NT stack unwind code can't handle a subq to adjust the stack
658 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
659 ;; the exception handling code will loop if a subq is used and an
662 ;; The 19980616 change to emit prologues as RTL also confused some
663 ;; versions of GDB, which also interprets prologues. This has been
664 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
667 ;; and the fact that the three insns schedule exactly the same, it's
668 ;; just not worth the effort.
670 (define_insn "*adddi_internal"
671 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
672 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
673 (match_operand:DI 2 "add_operand" "r,K,L")))]
680 ;; ??? Allow large constants when basing off the frame pointer or some
681 ;; virtual register that may eliminate to the frame pointer. This is
682 ;; done because register elimination offsets will change the hi/lo split,
683 ;; and if we split before reload, we will require additional instructions.
685 (define_insn "*adddi_fp_hack"
686 [(set (match_operand:DI 0 "register_operand" "=r")
687 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
688 (match_operand:DI 2 "const_int_operand" "n")))]
689 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
690 && INTVAL (operands[2]) >= 0
691 /* This is the largest constant an lda+ldah pair can add, minus
692 an upper bound on the displacement between SP and AP during
693 register elimination. See INITIAL_ELIMINATION_OFFSET. */
694 && INTVAL (operands[2])
696 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
697 - ALPHA_ROUND(current_function_outgoing_args_size)
698 - (ALPHA_ROUND (get_frame_size ()
699 + max_reg_num () * UNITS_PER_WORD
700 + current_function_pretend_args_size)
701 - current_function_pretend_args_size))"
704 ;; Don't do this if we are adjusting SP since we don't want to do it
705 ;; in two steps. Don't split FP sources for the reason listed above.
707 [(set (match_operand:DI 0 "register_operand" "")
708 (plus:DI (match_operand:DI 1 "register_operand" "")
709 (match_operand:DI 2 "const_int_operand" "")))]
710 "! add_operand (operands[2], DImode)
711 && operands[0] != stack_pointer_rtx
712 && operands[1] != frame_pointer_rtx
713 && operands[1] != arg_pointer_rtx"
714 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
715 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
717 HOST_WIDE_INT val = INTVAL (operands[2]);
718 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
719 HOST_WIDE_INT rest = val - low;
721 operands[4] = GEN_INT (low);
722 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
723 operands[3] = GEN_INT (rest);
724 else if (! no_new_pseudos)
726 operands[3] = gen_reg_rtx (DImode);
727 emit_move_insn (operands[3], operands[2]);
728 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
735 (define_insn "*saddl"
736 [(set (match_operand:SI 0 "register_operand" "=r,r")
737 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
738 (match_operand:SI 2 "const48_operand" "I,I"))
739 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
745 (define_insn "*saddl_se"
746 [(set (match_operand:DI 0 "register_operand" "=r,r")
748 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
749 (match_operand:SI 2 "const48_operand" "I,I"))
750 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
757 [(set (match_operand:DI 0 "register_operand" "")
759 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
760 [(match_operand 2 "" "")
761 (match_operand 3 "" "")])
762 (match_operand:SI 4 "const48_operand" ""))
763 (match_operand:SI 5 "sext_add_operand" ""))))
764 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
766 [(set (match_dup 6) (match_dup 7))
768 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
771 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
772 operands[2], operands[3]);
773 operands[8] = gen_lowpart (SImode, operands[6]);
776 (define_insn "*saddq"
777 [(set (match_operand:DI 0 "register_operand" "=r,r")
778 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
779 (match_operand:DI 2 "const48_operand" "I,I"))
780 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
786 (define_insn "addvdi3"
787 [(set (match_operand:DI 0 "register_operand" "=r,r")
788 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
789 (match_operand:DI 2 "sext_add_operand" "rI,O")))
790 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
791 (sign_extend:TI (match_dup 2)))
792 (sign_extend:TI (plus:DI (match_dup 1)
800 (define_insn "negsi2"
801 [(set (match_operand:SI 0 "register_operand" "=r")
802 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
806 (define_insn "*negsi_se"
807 [(set (match_operand:DI 0 "register_operand" "=r")
808 (sign_extend:DI (neg:SI
809 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
813 (define_insn "negvsi2"
814 [(set (match_operand:SI 0 "register_operand" "=r")
815 (neg:SI (match_operand:SI 1 "register_operand" "r")))
816 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
817 (sign_extend:DI (neg:SI (match_dup 1))))
822 (define_insn "negdi2"
823 [(set (match_operand:DI 0 "register_operand" "=r")
824 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
828 (define_insn "negvdi2"
829 [(set (match_operand:DI 0 "register_operand" "=r")
830 (neg:DI (match_operand:DI 1 "register_operand" "r")))
831 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
832 (sign_extend:TI (neg:DI (match_dup 1))))
837 (define_expand "subsi3"
838 [(set (match_operand:SI 0 "register_operand" "")
839 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
840 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
844 (define_insn "*subsi_internal"
845 [(set (match_operand:SI 0 "register_operand" "=r")
846 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
847 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
851 (define_insn "*subsi_se"
852 [(set (match_operand:DI 0 "register_operand" "=r")
853 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
854 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
858 (define_insn "*subsi_se2"
859 [(set (match_operand:DI 0 "register_operand" "=r")
861 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
862 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
867 (define_insn "subvsi3"
868 [(set (match_operand:SI 0 "register_operand" "=r")
869 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
870 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
871 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
872 (sign_extend:DI (match_dup 2)))
873 (sign_extend:DI (minus:SI (match_dup 1)
879 (define_insn "subdi3"
880 [(set (match_operand:DI 0 "register_operand" "=r")
881 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
882 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
886 (define_insn "*ssubl"
887 [(set (match_operand:SI 0 "register_operand" "=r")
888 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
889 (match_operand:SI 2 "const48_operand" "I"))
890 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
894 (define_insn "*ssubl_se"
895 [(set (match_operand:DI 0 "register_operand" "=r")
897 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
898 (match_operand:SI 2 "const48_operand" "I"))
899 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
903 (define_insn "*ssubq"
904 [(set (match_operand:DI 0 "register_operand" "=r")
905 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
906 (match_operand:DI 2 "const48_operand" "I"))
907 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
911 (define_insn "subvdi3"
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
914 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
915 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
916 (sign_extend:TI (match_dup 2)))
917 (sign_extend:TI (minus:DI (match_dup 1)
923 ;; The Unicos/Mk assembler doesn't support mull.
925 (define_insn "mulsi3"
926 [(set (match_operand:SI 0 "register_operand" "=r")
927 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
928 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
929 "!TARGET_ABI_UNICOSMK"
931 [(set_attr "type" "imul")
932 (set_attr "opsize" "si")])
934 (define_insn "*mulsi_se"
935 [(set (match_operand:DI 0 "register_operand" "=r")
937 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
938 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
939 "!TARGET_ABI_UNICOSMK"
941 [(set_attr "type" "imul")
942 (set_attr "opsize" "si")])
944 (define_insn "mulvsi3"
945 [(set (match_operand:SI 0 "register_operand" "=r")
946 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
947 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
948 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
949 (sign_extend:DI (match_dup 2)))
950 (sign_extend:DI (mult:SI (match_dup 1)
953 "!TARGET_ABI_UNICOSMK"
955 [(set_attr "type" "imul")
956 (set_attr "opsize" "si")])
958 (define_insn "muldi3"
959 [(set (match_operand:DI 0 "register_operand" "=r")
960 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
961 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
964 [(set_attr "type" "imul")])
966 (define_insn "mulvdi3"
967 [(set (match_operand:DI 0 "register_operand" "=r")
968 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
969 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
970 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
971 (sign_extend:TI (match_dup 2)))
972 (sign_extend:TI (mult:DI (match_dup 1)
977 [(set_attr "type" "imul")])
979 (define_insn "umuldi3_highpart"
980 [(set (match_operand:DI 0 "register_operand" "=r")
983 (mult:TI (zero_extend:TI
984 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
986 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
990 [(set_attr "type" "imul")
991 (set_attr "opsize" "udi")])
993 (define_insn "*umuldi3_highpart_const"
994 [(set (match_operand:DI 0 "register_operand" "=r")
997 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
998 (match_operand:TI 2 "cint8_operand" "I"))
1002 [(set_attr "type" "imul")
1003 (set_attr "opsize" "udi")])
1005 ;; The divide and remainder operations take their inputs from r24 and
1006 ;; r25, put their output in r27, and clobber r23 and r28 on all
1007 ;; systems except Unicos/Mk. On Unicos, the standard library provides
1008 ;; subroutines which use the standard calling convention and work on
1011 ;; ??? Force sign-extension here because some versions of OSF/1 and
1012 ;; Interix/NT don't do the right thing if the inputs are not properly
1013 ;; sign-extended. But Linux, for instance, does not have this
1014 ;; problem. Is it worth the complication here to eliminate the sign
1017 (define_expand "divsi3"
1019 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1021 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1022 (parallel [(set (match_dup 5)
1023 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
1024 (clobber (reg:DI 23))
1025 (clobber (reg:DI 28))])
1026 (set (match_operand:SI 0 "nonimmediate_operand" "")
1027 (subreg:SI (match_dup 5) 0))]
1028 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1030 operands[3] = gen_reg_rtx (DImode);
1031 operands[4] = gen_reg_rtx (DImode);
1032 operands[5] = gen_reg_rtx (DImode);
1035 (define_expand "udivsi3"
1037 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1039 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1040 (parallel [(set (match_dup 5)
1041 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
1042 (clobber (reg:DI 23))
1043 (clobber (reg:DI 28))])
1044 (set (match_operand:SI 0 "nonimmediate_operand" "")
1045 (subreg:SI (match_dup 5) 0))]
1046 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1048 operands[3] = gen_reg_rtx (DImode);
1049 operands[4] = gen_reg_rtx (DImode);
1050 operands[5] = gen_reg_rtx (DImode);
1053 (define_expand "modsi3"
1055 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1057 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1058 (parallel [(set (match_dup 5)
1059 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
1060 (clobber (reg:DI 23))
1061 (clobber (reg:DI 28))])
1062 (set (match_operand:SI 0 "nonimmediate_operand" "")
1063 (subreg:SI (match_dup 5) 0))]
1064 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1066 operands[3] = gen_reg_rtx (DImode);
1067 operands[4] = gen_reg_rtx (DImode);
1068 operands[5] = gen_reg_rtx (DImode);
1071 (define_expand "umodsi3"
1073 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1075 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1076 (parallel [(set (match_dup 5)
1077 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
1078 (clobber (reg:DI 23))
1079 (clobber (reg:DI 28))])
1080 (set (match_operand:SI 0 "nonimmediate_operand" "")
1081 (subreg:SI (match_dup 5) 0))]
1082 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1084 operands[3] = gen_reg_rtx (DImode);
1085 operands[4] = gen_reg_rtx (DImode);
1086 operands[5] = gen_reg_rtx (DImode);
1089 (define_expand "divdi3"
1090 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1091 (div:DI (match_operand:DI 1 "register_operand" "")
1092 (match_operand:DI 2 "register_operand" "")))
1093 (clobber (reg:DI 23))
1094 (clobber (reg:DI 28))])]
1095 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1098 (define_expand "udivdi3"
1099 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1100 (udiv:DI (match_operand:DI 1 "register_operand" "")
1101 (match_operand:DI 2 "register_operand" "")))
1102 (clobber (reg:DI 23))
1103 (clobber (reg:DI 28))])]
1104 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1107 (define_expand "moddi3"
1108 [(use (match_operand:DI 0 "register_operand" ""))
1109 (use (match_operand:DI 1 "register_operand" ""))
1110 (use (match_operand:DI 2 "register_operand" ""))]
1111 "!TARGET_ABI_OPEN_VMS"
1113 if (TARGET_ABI_UNICOSMK)
1114 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
1116 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
1120 (define_expand "moddi3_dft"
1121 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1122 (mod:DI (match_operand:DI 1 "register_operand" "")
1123 (match_operand:DI 2 "register_operand" "")))
1124 (clobber (reg:DI 23))
1125 (clobber (reg:DI 28))])]
1126 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1129 ;; On Unicos/Mk, we do as the system's C compiler does:
1130 ;; compute the quotient, multiply and subtract.
1132 (define_expand "moddi3_umk"
1133 [(use (match_operand:DI 0 "register_operand" ""))
1134 (use (match_operand:DI 1 "register_operand" ""))
1135 (use (match_operand:DI 2 "register_operand" ""))]
1136 "TARGET_ABI_UNICOSMK"
1138 rtx div, mul = gen_reg_rtx (DImode);
1140 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
1141 NULL_RTX, 0, OPTAB_LIB);
1142 div = force_reg (DImode, div);
1143 emit_insn (gen_muldi3 (mul, operands[2], div));
1144 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1148 (define_expand "umoddi3"
1149 [(use (match_operand:DI 0 "register_operand" ""))
1150 (use (match_operand:DI 1 "register_operand" ""))
1151 (use (match_operand:DI 2 "register_operand" ""))]
1152 "! TARGET_ABI_OPEN_VMS"
1154 if (TARGET_ABI_UNICOSMK)
1155 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
1157 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
1161 (define_expand "umoddi3_dft"
1162 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1163 (umod:DI (match_operand:DI 1 "register_operand" "")
1164 (match_operand:DI 2 "register_operand" "")))
1165 (clobber (reg:DI 23))
1166 (clobber (reg:DI 28))])]
1167 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1170 (define_expand "umoddi3_umk"
1171 [(use (match_operand:DI 0 "register_operand" ""))
1172 (use (match_operand:DI 1 "register_operand" ""))
1173 (use (match_operand:DI 2 "register_operand" ""))]
1174 "TARGET_ABI_UNICOSMK"
1176 rtx div, mul = gen_reg_rtx (DImode);
1178 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
1179 NULL_RTX, 1, OPTAB_LIB);
1180 div = force_reg (DImode, div);
1181 emit_insn (gen_muldi3 (mul, operands[2], div));
1182 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1186 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1187 ;; expanded by the assembler.
1189 (define_insn_and_split "*divmodsi_internal_er"
1190 [(set (match_operand:DI 0 "register_operand" "=c")
1191 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1192 [(match_operand:DI 1 "register_operand" "a")
1193 (match_operand:DI 2 "register_operand" "b")])))
1194 (clobber (reg:DI 23))
1195 (clobber (reg:DI 28))]
1196 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1197 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1198 "&& reload_completed"
1199 [(parallel [(set (match_dup 0)
1200 (sign_extend:DI (match_dup 3)))
1203 (clobber (reg:DI 23))
1204 (clobber (reg:DI 28))])]
1207 switch (GET_CODE (operands[3]))
1224 operands[4] = GEN_INT (alpha_next_sequence_number++);
1225 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1226 gen_rtx_SYMBOL_REF (DImode, str),
1229 [(set_attr "type" "jsr")
1230 (set_attr "length" "8")])
1232 (define_insn "*divmodsi_internal_er_1"
1233 [(set (match_operand:DI 0 "register_operand" "=c")
1234 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1235 [(match_operand:DI 1 "register_operand" "a")
1236 (match_operand:DI 2 "register_operand" "b")])))
1237 (use (match_operand:DI 4 "register_operand" "c"))
1238 (use (match_operand 5 "const_int_operand" ""))
1239 (clobber (reg:DI 23))
1240 (clobber (reg:DI 28))]
1241 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1242 "jsr $23,($27),__%E3%J5"
1243 [(set_attr "type" "jsr")
1244 (set_attr "length" "4")])
1246 (define_insn "*divmodsi_internal"
1247 [(set (match_operand:DI 0 "register_operand" "=c")
1248 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1249 [(match_operand:DI 1 "register_operand" "a")
1250 (match_operand:DI 2 "register_operand" "b")])))
1251 (clobber (reg:DI 23))
1252 (clobber (reg:DI 28))]
1253 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1255 [(set_attr "type" "jsr")
1256 (set_attr "length" "8")])
1258 (define_insn_and_split "*divmoddi_internal_er"
1259 [(set (match_operand:DI 0 "register_operand" "=c")
1260 (match_operator:DI 3 "divmod_operator"
1261 [(match_operand:DI 1 "register_operand" "a")
1262 (match_operand:DI 2 "register_operand" "b")]))
1263 (clobber (reg:DI 23))
1264 (clobber (reg:DI 28))]
1265 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1266 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1267 "&& reload_completed"
1268 [(parallel [(set (match_dup 0) (match_dup 3))
1271 (clobber (reg:DI 23))
1272 (clobber (reg:DI 28))])]
1275 switch (GET_CODE (operands[3]))
1292 operands[4] = GEN_INT (alpha_next_sequence_number++);
1293 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1294 gen_rtx_SYMBOL_REF (DImode, str),
1297 [(set_attr "type" "jsr")
1298 (set_attr "length" "8")])
1300 (define_insn "*divmoddi_internal_er_1"
1301 [(set (match_operand:DI 0 "register_operand" "=c")
1302 (match_operator:DI 3 "divmod_operator"
1303 [(match_operand:DI 1 "register_operand" "a")
1304 (match_operand:DI 2 "register_operand" "b")]))
1305 (use (match_operand:DI 4 "register_operand" "c"))
1306 (use (match_operand 5 "const_int_operand" ""))
1307 (clobber (reg:DI 23))
1308 (clobber (reg:DI 28))]
1309 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1310 "jsr $23,($27),__%E3%J5"
1311 [(set_attr "type" "jsr")
1312 (set_attr "length" "4")])
1314 (define_insn "*divmoddi_internal"
1315 [(set (match_operand:DI 0 "register_operand" "=c")
1316 (match_operator:DI 3 "divmod_operator"
1317 [(match_operand:DI 1 "register_operand" "a")
1318 (match_operand:DI 2 "register_operand" "b")]))
1319 (clobber (reg:DI 23))
1320 (clobber (reg:DI 28))]
1321 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1323 [(set_attr "type" "jsr")
1324 (set_attr "length" "8")])
1326 ;; Next are the basic logical operations. These only exist in DImode.
1328 (define_insn "anddi3"
1329 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1330 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1331 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1337 [(set_attr "type" "ilog,ilog,shift")])
1339 ;; There are times when we can split an AND into two AND insns. This occurs
1340 ;; when we can first clear any bytes and then clear anything else. For
1341 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1342 ;; Only do this when running on 64-bit host since the computations are
1343 ;; too messy otherwise.
1346 [(set (match_operand:DI 0 "register_operand" "")
1347 (and:DI (match_operand:DI 1 "register_operand" "")
1348 (match_operand:DI 2 "const_int_operand" "")))]
1349 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1350 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1351 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1353 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1354 unsigned HOST_WIDE_INT mask2 = mask1;
1357 /* For each byte that isn't all zeros, make it all ones. */
1358 for (i = 0; i < 64; i += 8)
1359 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1360 mask1 |= (HOST_WIDE_INT) 0xff << i;
1362 /* Now turn on any bits we've just turned off. */
1365 operands[3] = GEN_INT (mask1);
1366 operands[4] = GEN_INT (mask2);
1369 (define_expand "zero_extendqihi2"
1370 [(set (match_operand:HI 0 "register_operand" "")
1371 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1375 operands[1] = force_reg (QImode, operands[1]);
1378 (define_insn "*zero_extendqihi2_bwx"
1379 [(set (match_operand:HI 0 "register_operand" "=r,r")
1380 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1385 [(set_attr "type" "ilog,ild")])
1387 (define_insn "*zero_extendqihi2_nobwx"
1388 [(set (match_operand:HI 0 "register_operand" "=r")
1389 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1392 [(set_attr "type" "ilog")])
1394 (define_expand "zero_extendqisi2"
1395 [(set (match_operand:SI 0 "register_operand" "")
1396 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1400 operands[1] = force_reg (QImode, operands[1]);
1403 (define_insn "*zero_extendqisi2_bwx"
1404 [(set (match_operand:SI 0 "register_operand" "=r,r")
1405 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1410 [(set_attr "type" "ilog,ild")])
1412 (define_insn "*zero_extendqisi2_nobwx"
1413 [(set (match_operand:SI 0 "register_operand" "=r")
1414 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1417 [(set_attr "type" "ilog")])
1419 (define_expand "zero_extendqidi2"
1420 [(set (match_operand:DI 0 "register_operand" "")
1421 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1425 operands[1] = force_reg (QImode, operands[1]);
1428 (define_insn "*zero_extendqidi2_bwx"
1429 [(set (match_operand:DI 0 "register_operand" "=r,r")
1430 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1435 [(set_attr "type" "ilog,ild")])
1437 (define_insn "*zero_extendqidi2_nobwx"
1438 [(set (match_operand:DI 0 "register_operand" "=r")
1439 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1442 [(set_attr "type" "ilog")])
1444 (define_expand "zero_extendhisi2"
1445 [(set (match_operand:SI 0 "register_operand" "")
1446 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1450 operands[1] = force_reg (HImode, operands[1]);
1453 (define_insn "*zero_extendhisi2_bwx"
1454 [(set (match_operand:SI 0 "register_operand" "=r,r")
1455 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1460 [(set_attr "type" "shift,ild")])
1462 (define_insn "*zero_extendhisi2_nobwx"
1463 [(set (match_operand:SI 0 "register_operand" "=r")
1464 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1467 [(set_attr "type" "shift")])
1469 (define_expand "zero_extendhidi2"
1470 [(set (match_operand:DI 0 "register_operand" "")
1471 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1475 operands[1] = force_reg (HImode, operands[1]);
1478 (define_insn "*zero_extendhidi2_bwx"
1479 [(set (match_operand:DI 0 "register_operand" "=r,r")
1480 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1485 [(set_attr "type" "shift,ild")])
1487 (define_insn "*zero_extendhidi2_nobwx"
1488 [(set (match_operand:DI 0 "register_operand" "=r")
1489 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1492 [(set_attr "type" "shift")])
1494 (define_insn "zero_extendsidi2"
1495 [(set (match_operand:DI 0 "register_operand" "=r")
1496 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1499 [(set_attr "type" "shift")])
1501 (define_insn "andnotdi3"
1502 [(set (match_operand:DI 0 "register_operand" "=r")
1503 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1504 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1507 [(set_attr "type" "ilog")])
1509 (define_insn "iordi3"
1510 [(set (match_operand:DI 0 "register_operand" "=r,r")
1511 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1512 (match_operand:DI 2 "or_operand" "rI,N")))]
1517 [(set_attr "type" "ilog")])
1519 (define_insn "one_cmpldi2"
1520 [(set (match_operand:DI 0 "register_operand" "=r")
1521 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1524 [(set_attr "type" "ilog")])
1526 (define_insn "*iornot"
1527 [(set (match_operand:DI 0 "register_operand" "=r")
1528 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1529 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1532 [(set_attr "type" "ilog")])
1534 (define_insn "xordi3"
1535 [(set (match_operand:DI 0 "register_operand" "=r,r")
1536 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1537 (match_operand:DI 2 "or_operand" "rI,N")))]
1542 [(set_attr "type" "ilog")])
1544 (define_insn "*xornot"
1545 [(set (match_operand:DI 0 "register_operand" "=r")
1546 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1547 (match_operand:DI 2 "register_operand" "rI"))))]
1550 [(set_attr "type" "ilog")])
1552 ;; Handle the FFS insn iff we support CIX.
1554 (define_expand "ffsdi2"
1556 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1558 (plus:DI (match_dup 2) (const_int 1)))
1559 (set (match_operand:DI 0 "register_operand" "")
1560 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1561 (const_int 0) (match_dup 3)))]
1564 operands[2] = gen_reg_rtx (DImode);
1565 operands[3] = gen_reg_rtx (DImode);
1568 (define_insn "*cttz"
1569 [(set (match_operand:DI 0 "register_operand" "=r")
1570 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1573 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1574 ; reuse the existing type name.
1575 [(set_attr "type" "mvi")])
1577 ;; Next come the shifts and the various extract and insert operations.
1579 (define_insn "ashldi3"
1580 [(set (match_operand:DI 0 "register_operand" "=r,r")
1581 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1582 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1585 switch (which_alternative)
1588 if (operands[2] == const1_rtx)
1589 return "addq %r1,%r1,%0";
1591 return "s%P2addq %r1,0,%0";
1593 return "sll %r1,%2,%0";
1598 [(set_attr "type" "iadd,shift")])
1600 (define_insn "*ashldi_se"
1601 [(set (match_operand:DI 0 "register_operand" "=r")
1603 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1604 (match_operand:DI 2 "const_int_operand" "P"))
1606 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1608 if (operands[2] == const1_rtx)
1609 return "addl %r1,%r1,%0";
1611 return "s%P2addl %r1,0,%0";
1613 [(set_attr "type" "iadd")])
1615 (define_insn "lshrdi3"
1616 [(set (match_operand:DI 0 "register_operand" "=r")
1617 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1618 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1621 [(set_attr "type" "shift")])
1623 (define_insn "ashrdi3"
1624 [(set (match_operand:DI 0 "register_operand" "=r")
1625 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1626 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1629 [(set_attr "type" "shift")])
1631 (define_expand "extendqihi2"
1633 (ashift:DI (match_operand:QI 1 "some_operand" "")
1635 (set (match_operand:HI 0 "register_operand" "")
1636 (ashiftrt:DI (match_dup 2)
1642 emit_insn (gen_extendqihi2x (operands[0],
1643 force_reg (QImode, operands[1])));
1647 /* If we have an unaligned MEM, extend to DImode (which we do
1648 specially) and then copy to the result. */
1649 if (unaligned_memory_operand (operands[1], HImode))
1651 rtx temp = gen_reg_rtx (DImode);
1653 emit_insn (gen_extendqidi2 (temp, operands[1]));
1654 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1658 operands[0] = gen_lowpart (DImode, operands[0]);
1659 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1660 operands[2] = gen_reg_rtx (DImode);
1663 (define_insn "extendqidi2x"
1664 [(set (match_operand:DI 0 "register_operand" "=r")
1665 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1668 [(set_attr "type" "shift")])
1670 (define_insn "extendhidi2x"
1671 [(set (match_operand:DI 0 "register_operand" "=r")
1672 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1675 [(set_attr "type" "shift")])
1677 (define_insn "extendqisi2x"
1678 [(set (match_operand:SI 0 "register_operand" "=r")
1679 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1682 [(set_attr "type" "shift")])
1684 (define_insn "extendhisi2x"
1685 [(set (match_operand:SI 0 "register_operand" "=r")
1686 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1689 [(set_attr "type" "shift")])
1691 (define_insn "extendqihi2x"
1692 [(set (match_operand:HI 0 "register_operand" "=r")
1693 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1696 [(set_attr "type" "shift")])
1698 (define_expand "extendqisi2"
1700 (ashift:DI (match_operand:QI 1 "some_operand" "")
1702 (set (match_operand:SI 0 "register_operand" "")
1703 (ashiftrt:DI (match_dup 2)
1709 emit_insn (gen_extendqisi2x (operands[0],
1710 force_reg (QImode, operands[1])));
1714 /* If we have an unaligned MEM, extend to a DImode form of
1715 the result (which we do specially). */
1716 if (unaligned_memory_operand (operands[1], QImode))
1718 rtx temp = gen_reg_rtx (DImode);
1720 emit_insn (gen_extendqidi2 (temp, operands[1]));
1721 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1725 operands[0] = gen_lowpart (DImode, operands[0]);
1726 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1727 operands[2] = gen_reg_rtx (DImode);
1730 (define_expand "extendqidi2"
1732 (ashift:DI (match_operand:QI 1 "some_operand" "")
1734 (set (match_operand:DI 0 "register_operand" "")
1735 (ashiftrt:DI (match_dup 2)
1741 emit_insn (gen_extendqidi2x (operands[0],
1742 force_reg (QImode, operands[1])));
1746 if (unaligned_memory_operand (operands[1], QImode))
1749 = gen_unaligned_extendqidi (operands[0],
1750 get_unaligned_address (operands[1], 1));
1752 alpha_set_memflags (seq, operands[1]);
1757 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1758 operands[2] = gen_reg_rtx (DImode);
1761 (define_expand "extendhisi2"
1763 (ashift:DI (match_operand:HI 1 "some_operand" "")
1765 (set (match_operand:SI 0 "register_operand" "")
1766 (ashiftrt:DI (match_dup 2)
1772 emit_insn (gen_extendhisi2x (operands[0],
1773 force_reg (HImode, operands[1])));
1777 /* If we have an unaligned MEM, extend to a DImode form of
1778 the result (which we do specially). */
1779 if (unaligned_memory_operand (operands[1], HImode))
1781 rtx temp = gen_reg_rtx (DImode);
1783 emit_insn (gen_extendhidi2 (temp, operands[1]));
1784 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1788 operands[0] = gen_lowpart (DImode, operands[0]);
1789 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1790 operands[2] = gen_reg_rtx (DImode);
1793 (define_expand "extendhidi2"
1795 (ashift:DI (match_operand:HI 1 "some_operand" "")
1797 (set (match_operand:DI 0 "register_operand" "")
1798 (ashiftrt:DI (match_dup 2)
1804 emit_insn (gen_extendhidi2x (operands[0],
1805 force_reg (HImode, operands[1])));
1809 if (unaligned_memory_operand (operands[1], HImode))
1812 = gen_unaligned_extendhidi (operands[0],
1813 get_unaligned_address (operands[1], 2));
1815 alpha_set_memflags (seq, operands[1]);
1820 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1821 operands[2] = gen_reg_rtx (DImode);
1824 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1825 ;; as a pattern saves one instruction. The code is similar to that for
1826 ;; the unaligned loads (see below).
1828 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1829 (define_expand "unaligned_extendqidi"
1830 [(use (match_operand:QI 0 "register_operand" ""))
1831 (use (match_operand:DI 1 "address_operand" ""))]
1834 if (WORDS_BIG_ENDIAN)
1835 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1837 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1841 (define_expand "unaligned_extendqidi_le"
1842 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1844 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1847 (ashift:DI (match_dup 3)
1848 (minus:DI (const_int 64)
1850 (and:DI (match_dup 2) (const_int 7))
1852 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1853 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1854 "! WORDS_BIG_ENDIAN"
1856 operands[2] = gen_reg_rtx (DImode);
1857 operands[3] = gen_reg_rtx (DImode);
1858 operands[4] = gen_reg_rtx (DImode);
1861 (define_expand "unaligned_extendqidi_be"
1862 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1863 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1865 (mem:DI (and:DI (match_dup 3)
1867 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1869 (ashift:DI (match_dup 4)
1872 (plus:DI (match_dup 5) (const_int 1))
1875 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1876 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1879 operands[2] = gen_reg_rtx (DImode);
1880 operands[3] = gen_reg_rtx (DImode);
1881 operands[4] = gen_reg_rtx (DImode);
1882 operands[5] = gen_reg_rtx (DImode);
1883 operands[6] = gen_reg_rtx (DImode);
1886 (define_expand "unaligned_extendhidi"
1887 [(use (match_operand:QI 0 "register_operand" ""))
1888 (use (match_operand:DI 1 "address_operand" ""))]
1891 operands[0] = gen_lowpart (DImode, operands[0]);
1892 emit_insn ((WORDS_BIG_ENDIAN
1893 ? gen_unaligned_extendhidi_be
1894 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1898 (define_expand "unaligned_extendhidi_le"
1899 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1901 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1904 (ashift:DI (match_dup 3)
1905 (minus:DI (const_int 64)
1907 (and:DI (match_dup 2) (const_int 7))
1909 (set (match_operand:DI 0 "register_operand" "")
1910 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1911 "! WORDS_BIG_ENDIAN"
1913 operands[2] = gen_reg_rtx (DImode);
1914 operands[3] = gen_reg_rtx (DImode);
1915 operands[4] = gen_reg_rtx (DImode);
1918 (define_expand "unaligned_extendhidi_be"
1919 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1920 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1922 (mem:DI (and:DI (match_dup 3)
1924 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1926 (ashift:DI (match_dup 4)
1929 (plus:DI (match_dup 5) (const_int 1))
1932 (set (match_operand:DI 0 "register_operand" "")
1933 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1936 operands[2] = gen_reg_rtx (DImode);
1937 operands[3] = gen_reg_rtx (DImode);
1938 operands[4] = gen_reg_rtx (DImode);
1939 operands[5] = gen_reg_rtx (DImode);
1940 operands[6] = gen_reg_rtx (DImode);
1943 (define_insn "*extxl_const"
1944 [(set (match_operand:DI 0 "register_operand" "=r")
1945 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1946 (match_operand:DI 2 "mode_width_operand" "n")
1947 (match_operand:DI 3 "mul8_operand" "I")))]
1949 "ext%M2l %r1,%s3,%0"
1950 [(set_attr "type" "shift")])
1952 (define_insn "extxl_le"
1953 [(set (match_operand:DI 0 "register_operand" "=r")
1954 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1955 (match_operand:DI 2 "mode_width_operand" "n")
1956 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1958 "! WORDS_BIG_ENDIAN"
1960 [(set_attr "type" "shift")])
1962 (define_insn "extxl_be"
1963 [(set (match_operand:DI 0 "register_operand" "=r")
1964 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1965 (match_operand:DI 2 "mode_width_operand" "n")
1969 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1973 [(set_attr "type" "shift")])
1975 ;; Combine has some strange notion of preserving existing undefined behaviour
1976 ;; in shifts larger than a word size. So capture these patterns that it
1977 ;; should have turned into zero_extracts.
1979 (define_insn "*extxl_1_le"
1980 [(set (match_operand:DI 0 "register_operand" "=r")
1981 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1982 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1984 (match_operand:DI 3 "mode_mask_operand" "n")))]
1985 "! WORDS_BIG_ENDIAN"
1987 [(set_attr "type" "shift")])
1989 (define_insn "*extxl_1_be"
1990 [(set (match_operand:DI 0 "register_operand" "=r")
1991 (and:DI (lshiftrt:DI
1992 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1993 (minus:DI (const_int 56)
1994 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1996 (match_operand:DI 3 "mode_mask_operand" "n")))]
1999 [(set_attr "type" "shift")])
2001 (define_insn "*extql_2_le"
2002 [(set (match_operand:DI 0 "register_operand" "=r")
2003 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2004 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2006 "! WORDS_BIG_ENDIAN"
2008 [(set_attr "type" "shift")])
2010 (define_insn "*extql_2_be"
2011 [(set (match_operand:DI 0 "register_operand" "=r")
2013 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2014 (minus:DI (const_int 56)
2016 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2020 [(set_attr "type" "shift")])
2022 (define_insn "extqh_le"
2023 [(set (match_operand:DI 0 "register_operand" "=r")
2025 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2026 (minus:DI (const_int 64)
2029 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2032 "! WORDS_BIG_ENDIAN"
2034 [(set_attr "type" "shift")])
2036 (define_insn "extqh_be"
2037 [(set (match_operand:DI 0 "register_operand" "=r")
2039 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2042 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2048 [(set_attr "type" "shift")])
2050 (define_insn "extlh_le"
2051 [(set (match_operand:DI 0 "register_operand" "=r")
2053 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2054 (const_int 2147483647))
2055 (minus:DI (const_int 64)
2058 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2061 "! WORDS_BIG_ENDIAN"
2063 [(set_attr "type" "shift")])
2065 (define_insn "extlh_be"
2066 [(set (match_operand:DI 0 "register_operand" "=r")
2069 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2073 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2077 (const_int 2147483647)))]
2080 [(set_attr "type" "shift")])
2082 (define_insn "extwh_le"
2083 [(set (match_operand:DI 0 "register_operand" "=r")
2085 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2087 (minus:DI (const_int 64)
2090 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2093 "! WORDS_BIG_ENDIAN"
2095 [(set_attr "type" "shift")])
2097 (define_insn "extwh_be"
2098 [(set (match_operand:DI 0 "register_operand" "=r")
2100 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2104 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2108 (const_int 65535)))]
2111 [(set_attr "type" "shift")])
2113 ;; This converts an extXl into an extXh with an appropriate adjustment
2114 ;; to the address calculation.
2117 ;; [(set (match_operand:DI 0 "register_operand" "")
2118 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2119 ;; (match_operand:DI 2 "mode_width_operand" "")
2120 ;; (ashift:DI (match_operand:DI 3 "" "")
2122 ;; (match_operand:DI 4 "const_int_operand" "")))
2123 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2124 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2125 ;; [(set (match_dup 5) (match_dup 6))
2126 ;; (set (match_dup 0)
2127 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2128 ;; (ashift:DI (plus:DI (match_dup 5)
2134 ;; operands[6] = plus_constant (operands[3],
2135 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2136 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2139 (define_insn "*insbl_const"
2140 [(set (match_operand:DI 0 "register_operand" "=r")
2141 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2142 (match_operand:DI 2 "mul8_operand" "I")))]
2145 [(set_attr "type" "shift")])
2147 (define_insn "*inswl_const"
2148 [(set (match_operand:DI 0 "register_operand" "=r")
2149 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2150 (match_operand:DI 2 "mul8_operand" "I")))]
2153 [(set_attr "type" "shift")])
2155 (define_insn "*insll_const"
2156 [(set (match_operand:DI 0 "register_operand" "=r")
2157 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2158 (match_operand:DI 2 "mul8_operand" "I")))]
2161 [(set_attr "type" "shift")])
2163 (define_insn "insbl_le"
2164 [(set (match_operand:DI 0 "register_operand" "=r")
2165 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2166 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2168 "! WORDS_BIG_ENDIAN"
2170 [(set_attr "type" "shift")])
2172 (define_insn "insbl_be"
2173 [(set (match_operand:DI 0 "register_operand" "=r")
2174 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2175 (minus:DI (const_int 56)
2176 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2180 [(set_attr "type" "shift")])
2182 (define_insn "inswl_le"
2183 [(set (match_operand:DI 0 "register_operand" "=r")
2184 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2185 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2187 "! WORDS_BIG_ENDIAN"
2189 [(set_attr "type" "shift")])
2191 (define_insn "inswl_be"
2192 [(set (match_operand:DI 0 "register_operand" "=r")
2193 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2194 (minus:DI (const_int 56)
2195 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2199 [(set_attr "type" "shift")])
2201 (define_insn "insll_le"
2202 [(set (match_operand:DI 0 "register_operand" "=r")
2203 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2204 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2206 "! WORDS_BIG_ENDIAN"
2208 [(set_attr "type" "shift")])
2210 (define_insn "insll_be"
2211 [(set (match_operand:DI 0 "register_operand" "=r")
2212 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2213 (minus:DI (const_int 56)
2214 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2218 [(set_attr "type" "shift")])
2220 (define_insn "insql_le"
2221 [(set (match_operand:DI 0 "register_operand" "=r")
2222 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2223 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2225 "! WORDS_BIG_ENDIAN"
2227 [(set_attr "type" "shift")])
2229 (define_insn "insql_be"
2230 [(set (match_operand:DI 0 "register_operand" "=r")
2231 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2232 (minus:DI (const_int 56)
2233 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2237 [(set_attr "type" "shift")])
2239 ;; Combine has this sometimes habit of moving the and outside of the
2240 ;; shift, making life more interesting.
2242 (define_insn "*insxl"
2243 [(set (match_operand:DI 0 "register_operand" "=r")
2244 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2245 (match_operand:DI 2 "mul8_operand" "I"))
2246 (match_operand:DI 3 "immediate_operand" "i")))]
2247 "HOST_BITS_PER_WIDE_INT == 64
2248 && GET_CODE (operands[3]) == CONST_INT
2249 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2250 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2251 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2252 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2253 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2254 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2256 #if HOST_BITS_PER_WIDE_INT == 64
2257 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2258 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2259 return "insbl %1,%s2,%0";
2260 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2261 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2262 return "inswl %1,%s2,%0";
2263 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2264 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2265 return "insll %1,%s2,%0";
2269 [(set_attr "type" "shift")])
2271 ;; We do not include the insXh insns because they are complex to express
2272 ;; and it does not appear that we would ever want to generate them.
2274 ;; Since we need them for block moves, though, cop out and use unspec.
2276 (define_insn "insxh"
2277 [(set (match_operand:DI 0 "register_operand" "=r")
2278 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2279 (match_operand:DI 2 "mode_width_operand" "n")
2280 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2284 [(set_attr "type" "shift")])
2286 (define_insn "mskxl_le"
2287 [(set (match_operand:DI 0 "register_operand" "=r")
2288 (and:DI (not:DI (ashift:DI
2289 (match_operand:DI 2 "mode_mask_operand" "n")
2291 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2293 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2294 "! WORDS_BIG_ENDIAN"
2296 [(set_attr "type" "shift")])
2298 (define_insn "mskxl_be"
2299 [(set (match_operand:DI 0 "register_operand" "=r")
2300 (and:DI (not:DI (ashift:DI
2301 (match_operand:DI 2 "mode_mask_operand" "n")
2302 (minus:DI (const_int 56)
2304 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2306 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2309 [(set_attr "type" "shift")])
2311 ;; We do not include the mskXh insns because it does not appear we would
2312 ;; ever generate one.
2314 ;; Again, we do for block moves and we use unspec again.
2316 (define_insn "mskxh"
2317 [(set (match_operand:DI 0 "register_operand" "=r")
2318 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2319 (match_operand:DI 2 "mode_width_operand" "n")
2320 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2324 [(set_attr "type" "shift")])
2326 ;; Prefer AND + NE over LSHIFTRT + AND.
2328 (define_insn_and_split "*ze_and_ne"
2329 [(set (match_operand:DI 0 "register_operand" "=r")
2330 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2332 (match_operand 2 "const_int_operand" "I")))]
2333 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2335 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2337 (and:DI (match_dup 1) (match_dup 3)))
2339 (ne:DI (match_dup 0) (const_int 0)))]
2340 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2342 ;; Floating-point operations. All the double-precision insns can extend
2343 ;; from single, so indicate that. The exception are the ones that simply
2344 ;; play with the sign bits; it's not clear what to do there.
2346 (define_insn "abssf2"
2347 [(set (match_operand:SF 0 "register_operand" "=f")
2348 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2351 [(set_attr "type" "fcpys")])
2353 (define_insn "*nabssf2"
2354 [(set (match_operand:SF 0 "register_operand" "=f")
2355 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2358 [(set_attr "type" "fadd")])
2360 (define_insn "absdf2"
2361 [(set (match_operand:DF 0 "register_operand" "=f")
2362 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2365 [(set_attr "type" "fcpys")])
2367 (define_insn "*nabsdf2"
2368 [(set (match_operand:DF 0 "register_operand" "=f")
2369 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2372 [(set_attr "type" "fadd")])
2374 (define_expand "abstf2"
2375 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2376 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2377 (use (match_dup 2))])]
2378 "TARGET_HAS_XFLOATING_LIBS"
2380 #if HOST_BITS_PER_WIDE_INT >= 64
2381 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2383 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2387 (define_insn_and_split "*abstf_internal"
2388 [(set (match_operand:TF 0 "register_operand" "=r")
2389 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2390 (use (match_operand:DI 2 "register_operand" "r"))]
2391 "TARGET_HAS_XFLOATING_LIBS"
2393 "&& reload_completed"
2395 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2397 (define_insn "negsf2"
2398 [(set (match_operand:SF 0 "register_operand" "=f")
2399 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2402 [(set_attr "type" "fadd")])
2404 (define_insn "negdf2"
2405 [(set (match_operand:DF 0 "register_operand" "=f")
2406 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2409 [(set_attr "type" "fadd")])
2411 (define_expand "negtf2"
2412 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2413 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2414 (use (match_dup 2))])]
2415 "TARGET_HAS_XFLOATING_LIBS"
2417 #if HOST_BITS_PER_WIDE_INT >= 64
2418 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2420 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2424 (define_insn_and_split "*negtf_internal"
2425 [(set (match_operand:TF 0 "register_operand" "=r")
2426 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2427 (use (match_operand:DI 2 "register_operand" "r"))]
2428 "TARGET_HAS_XFLOATING_LIBS"
2430 "&& reload_completed"
2432 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2434 (define_insn "*addsf_ieee"
2435 [(set (match_operand:SF 0 "register_operand" "=&f")
2436 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2437 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2438 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2439 "add%,%/ %R1,%R2,%0"
2440 [(set_attr "type" "fadd")
2441 (set_attr "trap" "yes")
2442 (set_attr "round_suffix" "normal")
2443 (set_attr "trap_suffix" "u_su_sui")])
2445 (define_insn "addsf3"
2446 [(set (match_operand:SF 0 "register_operand" "=f")
2447 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2448 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2450 "add%,%/ %R1,%R2,%0"
2451 [(set_attr "type" "fadd")
2452 (set_attr "trap" "yes")
2453 (set_attr "round_suffix" "normal")
2454 (set_attr "trap_suffix" "u_su_sui")])
2456 (define_insn "*adddf_ieee"
2457 [(set (match_operand:DF 0 "register_operand" "=&f")
2458 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2459 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2460 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2461 "add%-%/ %R1,%R2,%0"
2462 [(set_attr "type" "fadd")
2463 (set_attr "trap" "yes")
2464 (set_attr "round_suffix" "normal")
2465 (set_attr "trap_suffix" "u_su_sui")])
2467 (define_insn "adddf3"
2468 [(set (match_operand:DF 0 "register_operand" "=f")
2469 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2470 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2472 "add%-%/ %R1,%R2,%0"
2473 [(set_attr "type" "fadd")
2474 (set_attr "trap" "yes")
2475 (set_attr "round_suffix" "normal")
2476 (set_attr "trap_suffix" "u_su_sui")])
2478 (define_insn "*adddf_ext1"
2479 [(set (match_operand:DF 0 "register_operand" "=f")
2480 (plus:DF (float_extend:DF
2481 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2482 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2483 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2484 "add%-%/ %R1,%R2,%0"
2485 [(set_attr "type" "fadd")
2486 (set_attr "trap" "yes")
2487 (set_attr "round_suffix" "normal")
2488 (set_attr "trap_suffix" "u_su_sui")])
2490 (define_insn "*adddf_ext2"
2491 [(set (match_operand:DF 0 "register_operand" "=f")
2492 (plus:DF (float_extend:DF
2493 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2495 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2496 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2497 "add%-%/ %R1,%R2,%0"
2498 [(set_attr "type" "fadd")
2499 (set_attr "trap" "yes")
2500 (set_attr "round_suffix" "normal")
2501 (set_attr "trap_suffix" "u_su_sui")])
2503 (define_expand "addtf3"
2504 [(use (match_operand 0 "register_operand" ""))
2505 (use (match_operand 1 "general_operand" ""))
2506 (use (match_operand 2 "general_operand" ""))]
2507 "TARGET_HAS_XFLOATING_LIBS"
2508 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2510 ;; Define conversion operators between DFmode and SImode, using the cvtql
2511 ;; instruction. To allow combine et al to do useful things, we keep the
2512 ;; operation as a unit until after reload, at which point we split the
2515 ;; Note that we (attempt to) only consider this optimization when the
2516 ;; ultimate destination is memory. If we will be doing further integer
2517 ;; processing, it is cheaper to do the truncation in the int regs.
2519 (define_insn "*cvtql"
2520 [(set (match_operand:SI 0 "register_operand" "=f")
2521 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2525 [(set_attr "type" "fadd")
2526 (set_attr "trap" "yes")
2527 (set_attr "trap_suffix" "v_sv")])
2529 (define_insn_and_split "*fix_truncdfsi_ieee"
2530 [(set (match_operand:SI 0 "memory_operand" "=m")
2531 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2532 (clobber (match_scratch:DI 2 "=&f"))
2533 (clobber (match_scratch:SI 3 "=&f"))]
2534 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2536 "&& reload_completed"
2537 [(set (match_dup 2) (fix:DI (match_dup 1)))
2538 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2539 (set (match_dup 0) (match_dup 3))]
2541 [(set_attr "type" "fadd")
2542 (set_attr "trap" "yes")])
2544 (define_insn_and_split "*fix_truncdfsi_internal"
2545 [(set (match_operand:SI 0 "memory_operand" "=m")
2546 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2547 (clobber (match_scratch:DI 2 "=f"))]
2548 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2550 "&& reload_completed"
2551 [(set (match_dup 2) (fix:DI (match_dup 1)))
2552 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2553 (set (match_dup 0) (match_dup 3))]
2554 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2555 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2556 [(set_attr "type" "fadd")
2557 (set_attr "trap" "yes")])
2559 (define_insn "*fix_truncdfdi_ieee"
2560 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2561 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2562 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2564 [(set_attr "type" "fadd")
2565 (set_attr "trap" "yes")
2566 (set_attr "round_suffix" "c")
2567 (set_attr "trap_suffix" "v_sv_svi")])
2569 (define_insn "fix_truncdfdi2"
2570 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2571 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2574 [(set_attr "type" "fadd")
2575 (set_attr "trap" "yes")
2576 (set_attr "round_suffix" "c")
2577 (set_attr "trap_suffix" "v_sv_svi")])
2579 ;; Likewise between SFmode and SImode.
2581 (define_insn_and_split "*fix_truncsfsi_ieee"
2582 [(set (match_operand:SI 0 "memory_operand" "=m")
2583 (subreg:SI (fix:DI (float_extend:DF
2584 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2585 (clobber (match_scratch:DI 2 "=&f"))
2586 (clobber (match_scratch:SI 3 "=&f"))]
2587 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2589 "&& reload_completed"
2590 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2591 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2592 (set (match_dup 0) (match_dup 3))]
2594 [(set_attr "type" "fadd")
2595 (set_attr "trap" "yes")])
2597 (define_insn_and_split "*fix_truncsfsi_internal"
2598 [(set (match_operand:SI 0 "memory_operand" "=m")
2599 (subreg:SI (fix:DI (float_extend:DF
2600 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2601 (clobber (match_scratch:DI 2 "=f"))]
2602 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2604 "&& reload_completed"
2605 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2606 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2607 (set (match_dup 0) (match_dup 3))]
2608 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2609 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2610 [(set_attr "type" "fadd")
2611 (set_attr "trap" "yes")])
2613 (define_insn "*fix_truncsfdi_ieee"
2614 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2615 (fix:DI (float_extend:DF
2616 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2617 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2619 [(set_attr "type" "fadd")
2620 (set_attr "trap" "yes")
2621 (set_attr "round_suffix" "c")
2622 (set_attr "trap_suffix" "v_sv_svi")])
2624 (define_insn "fix_truncsfdi2"
2625 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2626 (fix:DI (float_extend:DF
2627 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2630 [(set_attr "type" "fadd")
2631 (set_attr "trap" "yes")
2632 (set_attr "round_suffix" "c")
2633 (set_attr "trap_suffix" "v_sv_svi")])
2635 (define_expand "fix_trunctfdi2"
2636 [(use (match_operand:DI 0 "register_operand" ""))
2637 (use (match_operand:TF 1 "general_operand" ""))]
2638 "TARGET_HAS_XFLOATING_LIBS"
2639 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2641 (define_insn "*floatdisf_ieee"
2642 [(set (match_operand:SF 0 "register_operand" "=&f")
2643 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2644 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2646 [(set_attr "type" "fadd")
2647 (set_attr "trap" "yes")
2648 (set_attr "round_suffix" "normal")
2649 (set_attr "trap_suffix" "sui")])
2651 (define_insn "floatdisf2"
2652 [(set (match_operand:SF 0 "register_operand" "=f")
2653 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2656 [(set_attr "type" "fadd")
2657 (set_attr "trap" "yes")
2658 (set_attr "round_suffix" "normal")
2659 (set_attr "trap_suffix" "sui")])
2661 (define_insn "*floatdidf_ieee"
2662 [(set (match_operand:DF 0 "register_operand" "=&f")
2663 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2664 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2666 [(set_attr "type" "fadd")
2667 (set_attr "trap" "yes")
2668 (set_attr "round_suffix" "normal")
2669 (set_attr "trap_suffix" "sui")])
2671 (define_insn "floatdidf2"
2672 [(set (match_operand:DF 0 "register_operand" "=f")
2673 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2676 [(set_attr "type" "fadd")
2677 (set_attr "trap" "yes")
2678 (set_attr "round_suffix" "normal")
2679 (set_attr "trap_suffix" "sui")])
2681 (define_expand "floatditf2"
2682 [(use (match_operand:TF 0 "register_operand" ""))
2683 (use (match_operand:DI 1 "general_operand" ""))]
2684 "TARGET_HAS_XFLOATING_LIBS"
2685 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2687 (define_expand "floatunsdisf2"
2688 [(use (match_operand:SF 0 "register_operand" ""))
2689 (use (match_operand:DI 1 "register_operand" ""))]
2691 "alpha_emit_floatuns (operands); DONE;")
2693 (define_expand "floatunsdidf2"
2694 [(use (match_operand:DF 0 "register_operand" ""))
2695 (use (match_operand:DI 1 "register_operand" ""))]
2697 "alpha_emit_floatuns (operands); DONE;")
2699 (define_expand "floatunsditf2"
2700 [(use (match_operand:TF 0 "register_operand" ""))
2701 (use (match_operand:DI 1 "general_operand" ""))]
2702 "TARGET_HAS_XFLOATING_LIBS"
2703 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2705 (define_expand "extendsfdf2"
2706 [(set (match_operand:DF 0 "register_operand" "")
2707 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2710 if (alpha_fptm >= ALPHA_FPTM_SU)
2711 operands[1] = force_reg (SFmode, operands[1]);
2714 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2715 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2717 (define_insn "*extendsfdf2_ieee"
2718 [(set (match_operand:DF 0 "register_operand" "=&f")
2719 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2720 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2722 [(set_attr "type" "fadd")
2723 (set_attr "trap" "yes")])
2725 (define_insn "*extendsfdf2_internal"
2726 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2727 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2728 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2733 [(set_attr "type" "fcpys,fld,fst")])
2735 (define_expand "extendsftf2"
2736 [(use (match_operand:TF 0 "register_operand" ""))
2737 (use (match_operand:SF 1 "general_operand" ""))]
2738 "TARGET_HAS_XFLOATING_LIBS"
2740 rtx tmp = gen_reg_rtx (DFmode);
2741 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2742 emit_insn (gen_extenddftf2 (operands[0], tmp));
2746 (define_expand "extenddftf2"
2747 [(use (match_operand:TF 0 "register_operand" ""))
2748 (use (match_operand:DF 1 "general_operand" ""))]
2749 "TARGET_HAS_XFLOATING_LIBS"
2750 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2752 (define_insn "*truncdfsf2_ieee"
2753 [(set (match_operand:SF 0 "register_operand" "=&f")
2754 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2755 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2757 [(set_attr "type" "fadd")
2758 (set_attr "trap" "yes")
2759 (set_attr "round_suffix" "normal")
2760 (set_attr "trap_suffix" "u_su_sui")])
2762 (define_insn "truncdfsf2"
2763 [(set (match_operand:SF 0 "register_operand" "=f")
2764 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2767 [(set_attr "type" "fadd")
2768 (set_attr "trap" "yes")
2769 (set_attr "round_suffix" "normal")
2770 (set_attr "trap_suffix" "u_su_sui")])
2772 (define_expand "trunctfdf2"
2773 [(use (match_operand:DF 0 "register_operand" ""))
2774 (use (match_operand:TF 1 "general_operand" ""))]
2775 "TARGET_HAS_XFLOATING_LIBS"
2776 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2778 (define_expand "trunctfsf2"
2779 [(use (match_operand:SF 0 "register_operand" ""))
2780 (use (match_operand:TF 1 "general_operand" ""))]
2781 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2783 rtx tmpf, sticky, arg, lo, hi;
2785 tmpf = gen_reg_rtx (DFmode);
2786 sticky = gen_reg_rtx (DImode);
2787 arg = copy_to_mode_reg (TFmode, operands[1]);
2788 lo = gen_lowpart (DImode, arg);
2789 hi = gen_highpart (DImode, arg);
2791 /* Convert the low word of the TFmode value into a sticky rounding bit,
2792 then or it into the low bit of the high word. This leaves the sticky
2793 bit at bit 48 of the fraction, which is representable in DFmode,
2794 which prevents rounding error in the final conversion to SFmode. */
2796 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2797 gen_rtx_NE (DImode, lo, const0_rtx)));
2798 emit_insn (gen_iordi3 (hi, hi, sticky));
2799 emit_insn (gen_trunctfdf2 (tmpf, arg));
2800 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2804 (define_insn "*divsf3_ieee"
2805 [(set (match_operand:SF 0 "register_operand" "=&f")
2806 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2807 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2808 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2809 "div%,%/ %R1,%R2,%0"
2810 [(set_attr "type" "fdiv")
2811 (set_attr "opsize" "si")
2812 (set_attr "trap" "yes")
2813 (set_attr "round_suffix" "normal")
2814 (set_attr "trap_suffix" "u_su_sui")])
2816 (define_insn "divsf3"
2817 [(set (match_operand:SF 0 "register_operand" "=f")
2818 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2819 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2821 "div%,%/ %R1,%R2,%0"
2822 [(set_attr "type" "fdiv")
2823 (set_attr "opsize" "si")
2824 (set_attr "trap" "yes")
2825 (set_attr "round_suffix" "normal")
2826 (set_attr "trap_suffix" "u_su_sui")])
2828 (define_insn "*divdf3_ieee"
2829 [(set (match_operand:DF 0 "register_operand" "=&f")
2830 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2831 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2832 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2833 "div%-%/ %R1,%R2,%0"
2834 [(set_attr "type" "fdiv")
2835 (set_attr "trap" "yes")
2836 (set_attr "round_suffix" "normal")
2837 (set_attr "trap_suffix" "u_su_sui")])
2839 (define_insn "divdf3"
2840 [(set (match_operand:DF 0 "register_operand" "=f")
2841 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2842 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2844 "div%-%/ %R1,%R2,%0"
2845 [(set_attr "type" "fdiv")
2846 (set_attr "trap" "yes")
2847 (set_attr "round_suffix" "normal")
2848 (set_attr "trap_suffix" "u_su_sui")])
2850 (define_insn "*divdf_ext1"
2851 [(set (match_operand:DF 0 "register_operand" "=f")
2852 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2853 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2854 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2855 "div%-%/ %R1,%R2,%0"
2856 [(set_attr "type" "fdiv")
2857 (set_attr "trap" "yes")
2858 (set_attr "round_suffix" "normal")
2859 (set_attr "trap_suffix" "u_su_sui")])
2861 (define_insn "*divdf_ext2"
2862 [(set (match_operand:DF 0 "register_operand" "=f")
2863 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2865 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2866 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2867 "div%-%/ %R1,%R2,%0"
2868 [(set_attr "type" "fdiv")
2869 (set_attr "trap" "yes")
2870 (set_attr "round_suffix" "normal")
2871 (set_attr "trap_suffix" "u_su_sui")])
2873 (define_insn "*divdf_ext3"
2874 [(set (match_operand:DF 0 "register_operand" "=f")
2875 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2876 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2877 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2878 "div%-%/ %R1,%R2,%0"
2879 [(set_attr "type" "fdiv")
2880 (set_attr "trap" "yes")
2881 (set_attr "round_suffix" "normal")
2882 (set_attr "trap_suffix" "u_su_sui")])
2884 (define_expand "divtf3"
2885 [(use (match_operand 0 "register_operand" ""))
2886 (use (match_operand 1 "general_operand" ""))
2887 (use (match_operand 2 "general_operand" ""))]
2888 "TARGET_HAS_XFLOATING_LIBS"
2889 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2891 (define_insn "*mulsf3_ieee"
2892 [(set (match_operand:SF 0 "register_operand" "=&f")
2893 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2894 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2895 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2896 "mul%,%/ %R1,%R2,%0"
2897 [(set_attr "type" "fmul")
2898 (set_attr "trap" "yes")
2899 (set_attr "round_suffix" "normal")
2900 (set_attr "trap_suffix" "u_su_sui")])
2902 (define_insn "mulsf3"
2903 [(set (match_operand:SF 0 "register_operand" "=f")
2904 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2905 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2907 "mul%,%/ %R1,%R2,%0"
2908 [(set_attr "type" "fmul")
2909 (set_attr "trap" "yes")
2910 (set_attr "round_suffix" "normal")
2911 (set_attr "trap_suffix" "u_su_sui")])
2913 (define_insn "*muldf3_ieee"
2914 [(set (match_operand:DF 0 "register_operand" "=&f")
2915 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2916 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2917 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2918 "mul%-%/ %R1,%R2,%0"
2919 [(set_attr "type" "fmul")
2920 (set_attr "trap" "yes")
2921 (set_attr "round_suffix" "normal")
2922 (set_attr "trap_suffix" "u_su_sui")])
2924 (define_insn "muldf3"
2925 [(set (match_operand:DF 0 "register_operand" "=f")
2926 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2927 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2929 "mul%-%/ %R1,%R2,%0"
2930 [(set_attr "type" "fmul")
2931 (set_attr "trap" "yes")
2932 (set_attr "round_suffix" "normal")
2933 (set_attr "trap_suffix" "u_su_sui")])
2935 (define_insn "*muldf_ext1"
2936 [(set (match_operand:DF 0 "register_operand" "=f")
2937 (mult:DF (float_extend:DF
2938 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2939 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2940 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2941 "mul%-%/ %R1,%R2,%0"
2942 [(set_attr "type" "fmul")
2943 (set_attr "trap" "yes")
2944 (set_attr "round_suffix" "normal")
2945 (set_attr "trap_suffix" "u_su_sui")])
2947 (define_insn "*muldf_ext2"
2948 [(set (match_operand:DF 0 "register_operand" "=f")
2949 (mult:DF (float_extend:DF
2950 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2952 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2953 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2954 "mul%-%/ %R1,%R2,%0"
2955 [(set_attr "type" "fmul")
2956 (set_attr "trap" "yes")
2957 (set_attr "round_suffix" "normal")
2958 (set_attr "trap_suffix" "u_su_sui")])
2960 (define_expand "multf3"
2961 [(use (match_operand 0 "register_operand" ""))
2962 (use (match_operand 1 "general_operand" ""))
2963 (use (match_operand 2 "general_operand" ""))]
2964 "TARGET_HAS_XFLOATING_LIBS"
2965 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2967 (define_insn "*subsf3_ieee"
2968 [(set (match_operand:SF 0 "register_operand" "=&f")
2969 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2970 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2971 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2972 "sub%,%/ %R1,%R2,%0"
2973 [(set_attr "type" "fadd")
2974 (set_attr "trap" "yes")
2975 (set_attr "round_suffix" "normal")
2976 (set_attr "trap_suffix" "u_su_sui")])
2978 (define_insn "subsf3"
2979 [(set (match_operand:SF 0 "register_operand" "=f")
2980 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2981 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2983 "sub%,%/ %R1,%R2,%0"
2984 [(set_attr "type" "fadd")
2985 (set_attr "trap" "yes")
2986 (set_attr "round_suffix" "normal")
2987 (set_attr "trap_suffix" "u_su_sui")])
2989 (define_insn "*subdf3_ieee"
2990 [(set (match_operand:DF 0 "register_operand" "=&f")
2991 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2992 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2993 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2994 "sub%-%/ %R1,%R2,%0"
2995 [(set_attr "type" "fadd")
2996 (set_attr "trap" "yes")
2997 (set_attr "round_suffix" "normal")
2998 (set_attr "trap_suffix" "u_su_sui")])
3000 (define_insn "subdf3"
3001 [(set (match_operand:DF 0 "register_operand" "=f")
3002 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3003 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
3005 "sub%-%/ %R1,%R2,%0"
3006 [(set_attr "type" "fadd")
3007 (set_attr "trap" "yes")
3008 (set_attr "round_suffix" "normal")
3009 (set_attr "trap_suffix" "u_su_sui")])
3011 (define_insn "*subdf_ext1"
3012 [(set (match_operand:DF 0 "register_operand" "=f")
3013 (minus:DF (float_extend:DF
3014 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
3015 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
3016 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3017 "sub%-%/ %R1,%R2,%0"
3018 [(set_attr "type" "fadd")
3019 (set_attr "trap" "yes")
3020 (set_attr "round_suffix" "normal")
3021 (set_attr "trap_suffix" "u_su_sui")])
3023 (define_insn "*subdf_ext2"
3024 [(set (match_operand:DF 0 "register_operand" "=f")
3025 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3027 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3028 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3029 "sub%-%/ %R1,%R2,%0"
3030 [(set_attr "type" "fadd")
3031 (set_attr "trap" "yes")
3032 (set_attr "round_suffix" "normal")
3033 (set_attr "trap_suffix" "u_su_sui")])
3035 (define_insn "*subdf_ext3"
3036 [(set (match_operand:DF 0 "register_operand" "=f")
3037 (minus:DF (float_extend:DF
3038 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
3040 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3041 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3042 "sub%-%/ %R1,%R2,%0"
3043 [(set_attr "type" "fadd")
3044 (set_attr "trap" "yes")
3045 (set_attr "round_suffix" "normal")
3046 (set_attr "trap_suffix" "u_su_sui")])
3048 (define_expand "subtf3"
3049 [(use (match_operand 0 "register_operand" ""))
3050 (use (match_operand 1 "general_operand" ""))
3051 (use (match_operand 2 "general_operand" ""))]
3052 "TARGET_HAS_XFLOATING_LIBS"
3053 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3055 (define_insn "*sqrtsf2_ieee"
3056 [(set (match_operand:SF 0 "register_operand" "=&f")
3057 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3058 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3060 [(set_attr "type" "fsqrt")
3061 (set_attr "opsize" "si")
3062 (set_attr "trap" "yes")
3063 (set_attr "round_suffix" "normal")
3064 (set_attr "trap_suffix" "u_su_sui")])
3066 (define_insn "sqrtsf2"
3067 [(set (match_operand:SF 0 "register_operand" "=f")
3068 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3069 "TARGET_FP && TARGET_FIX"
3071 [(set_attr "type" "fsqrt")
3072 (set_attr "opsize" "si")
3073 (set_attr "trap" "yes")
3074 (set_attr "round_suffix" "normal")
3075 (set_attr "trap_suffix" "u_su_sui")])
3077 (define_insn "*sqrtdf2_ieee"
3078 [(set (match_operand:DF 0 "register_operand" "=&f")
3079 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3080 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3082 [(set_attr "type" "fsqrt")
3083 (set_attr "trap" "yes")
3084 (set_attr "round_suffix" "normal")
3085 (set_attr "trap_suffix" "u_su_sui")])
3087 (define_insn "sqrtdf2"
3088 [(set (match_operand:DF 0 "register_operand" "=f")
3089 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3090 "TARGET_FP && TARGET_FIX"
3092 [(set_attr "type" "fsqrt")
3093 (set_attr "trap" "yes")
3094 (set_attr "round_suffix" "normal")
3095 (set_attr "trap_suffix" "u_su_sui")])
3097 ;; Next are all the integer comparisons, and conditional moves and branches
3098 ;; and some of the related define_expand's and define_split's.
3100 (define_insn "*setcc_internal"
3101 [(set (match_operand 0 "register_operand" "=r")
3102 (match_operator 1 "alpha_comparison_operator"
3103 [(match_operand:DI 2 "register_operand" "r")
3104 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3105 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3106 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3107 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3109 [(set_attr "type" "icmp")])
3111 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3112 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3114 (define_insn "*setcc_swapped_internal"
3115 [(set (match_operand 0 "register_operand" "=r")
3116 (match_operator 1 "alpha_swapped_comparison_operator"
3117 [(match_operand:DI 2 "register_operand" "r")
3118 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3119 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3120 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3121 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3123 [(set_attr "type" "icmp")])
3125 ;; Use match_operator rather than ne directly so that we can match
3126 ;; multiple integer modes.
3127 (define_insn "*setne_internal"
3128 [(set (match_operand 0 "register_operand" "=r")
3129 (match_operator 1 "signed_comparison_operator"
3130 [(match_operand:DI 2 "register_operand" "r")
3132 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3133 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3134 && GET_CODE (operands[1]) == NE
3135 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3137 [(set_attr "type" "icmp")])
3139 ;; The mode folding trick can't be used with const_int operands, since
3140 ;; reload needs to know the proper mode.
3142 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3143 ;; in order to create more pairs of constants. As long as we're allowing
3144 ;; two constants at the same time, and will have to reload one of them...
3146 (define_insn "*movqicc_internal"
3147 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3149 (match_operator 2 "signed_comparison_operator"
3150 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3151 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3152 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3153 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3154 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3160 [(set_attr "type" "icmov")])
3162 (define_insn "*movhicc_internal"
3163 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3165 (match_operator 2 "signed_comparison_operator"
3166 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3167 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3168 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3169 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3170 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3176 [(set_attr "type" "icmov")])
3178 (define_insn "*movsicc_internal"
3179 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3181 (match_operator 2 "signed_comparison_operator"
3182 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3183 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3184 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3185 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3186 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3192 [(set_attr "type" "icmov")])
3194 (define_insn "*movdicc_internal"
3195 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3197 (match_operator 2 "signed_comparison_operator"
3198 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3199 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3200 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3201 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3202 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3208 [(set_attr "type" "icmov")])
3210 (define_insn "*movqicc_lbc"
3211 [(set (match_operand:QI 0 "register_operand" "=r,r")
3213 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3217 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3218 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3223 [(set_attr "type" "icmov")])
3225 (define_insn "*movhicc_lbc"
3226 [(set (match_operand:HI 0 "register_operand" "=r,r")
3228 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3232 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3233 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3238 [(set_attr "type" "icmov")])
3240 (define_insn "*movsicc_lbc"
3241 [(set (match_operand:SI 0 "register_operand" "=r,r")
3243 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3247 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3248 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3253 [(set_attr "type" "icmov")])
3255 (define_insn "*movdicc_lbc"
3256 [(set (match_operand:DI 0 "register_operand" "=r,r")
3258 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3262 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3263 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3268 [(set_attr "type" "icmov")])
3270 (define_insn "*movqicc_lbs"
3271 [(set (match_operand:QI 0 "register_operand" "=r,r")
3273 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3277 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3278 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3283 [(set_attr "type" "icmov")])
3285 (define_insn "*movhicc_lbs"
3286 [(set (match_operand:HI 0 "register_operand" "=r,r")
3288 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3292 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3293 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3298 [(set_attr "type" "icmov")])
3300 (define_insn "*movsicc_lbs"
3301 [(set (match_operand:SI 0 "register_operand" "=r,r")
3303 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3307 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3308 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3313 [(set_attr "type" "icmov")])
3315 (define_insn "*movdicc_lbs"
3316 [(set (match_operand:DI 0 "register_operand" "=r,r")
3318 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3322 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3323 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3328 [(set_attr "type" "icmov")])
3330 ;; For ABS, we have two choices, depending on whether the input and output
3331 ;; registers are the same or not.
3332 (define_expand "absdi2"
3333 [(set (match_operand:DI 0 "register_operand" "")
3334 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3337 if (rtx_equal_p (operands[0], operands[1]))
3338 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3340 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3344 (define_expand "absdi2_same"
3345 [(set (match_operand:DI 1 "register_operand" "")
3346 (neg:DI (match_operand:DI 0 "register_operand" "")))
3348 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3354 (define_expand "absdi2_diff"
3355 [(set (match_operand:DI 0 "register_operand" "")
3356 (neg:DI (match_operand:DI 1 "register_operand" "")))
3358 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3365 [(set (match_operand:DI 0 "register_operand" "")
3366 (abs:DI (match_dup 0)))
3367 (clobber (match_operand:DI 1 "register_operand" ""))]
3369 [(set (match_dup 1) (neg:DI (match_dup 0)))
3370 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3371 (match_dup 0) (match_dup 1)))]
3375 [(set (match_operand:DI 0 "register_operand" "")
3376 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3377 "! rtx_equal_p (operands[0], operands[1])"
3378 [(set (match_dup 0) (neg:DI (match_dup 1)))
3379 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3380 (match_dup 0) (match_dup 1)))]
3384 [(set (match_operand:DI 0 "register_operand" "")
3385 (neg:DI (abs:DI (match_dup 0))))
3386 (clobber (match_operand:DI 1 "register_operand" ""))]
3388 [(set (match_dup 1) (neg:DI (match_dup 0)))
3389 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3390 (match_dup 0) (match_dup 1)))]
3394 [(set (match_operand:DI 0 "register_operand" "")
3395 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3396 "! rtx_equal_p (operands[0], operands[1])"
3397 [(set (match_dup 0) (neg:DI (match_dup 1)))
3398 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3399 (match_dup 0) (match_dup 1)))]
3402 (define_insn "sminqi3"
3403 [(set (match_operand:QI 0 "register_operand" "=r")
3404 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3405 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3408 [(set_attr "type" "mvi")])
3410 (define_insn "uminqi3"
3411 [(set (match_operand:QI 0 "register_operand" "=r")
3412 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3413 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3416 [(set_attr "type" "mvi")])
3418 (define_insn "smaxqi3"
3419 [(set (match_operand:QI 0 "register_operand" "=r")
3420 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3421 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3424 [(set_attr "type" "mvi")])
3426 (define_insn "umaxqi3"
3427 [(set (match_operand:QI 0 "register_operand" "=r")
3428 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3429 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3432 [(set_attr "type" "mvi")])
3434 (define_insn "sminhi3"
3435 [(set (match_operand:HI 0 "register_operand" "=r")
3436 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3437 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3440 [(set_attr "type" "mvi")])
3442 (define_insn "uminhi3"
3443 [(set (match_operand:HI 0 "register_operand" "=r")
3444 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3445 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3448 [(set_attr "type" "mvi")])
3450 (define_insn "smaxhi3"
3451 [(set (match_operand:HI 0 "register_operand" "=r")
3452 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3453 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3456 [(set_attr "type" "mvi")])
3458 (define_insn "umaxhi3"
3459 [(set (match_operand:HI 0 "register_operand" "=r")
3460 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3461 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3464 [(set_attr "type" "shift")])
3466 (define_expand "smaxdi3"
3468 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3469 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3470 (set (match_operand:DI 0 "register_operand" "")
3471 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3472 (match_dup 1) (match_dup 2)))]
3474 { operands[3] = gen_reg_rtx (DImode); })
3477 [(set (match_operand:DI 0 "register_operand" "")
3478 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3479 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3480 (clobber (match_operand:DI 3 "register_operand" ""))]
3481 "operands[2] != const0_rtx"
3482 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3483 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3484 (match_dup 1) (match_dup 2)))]
3487 (define_insn "*smax_const0"
3488 [(set (match_operand:DI 0 "register_operand" "=r")
3489 (smax:DI (match_operand:DI 1 "register_operand" "0")
3493 [(set_attr "type" "icmov")])
3495 (define_expand "smindi3"
3497 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3498 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3499 (set (match_operand:DI 0 "register_operand" "")
3500 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3501 (match_dup 1) (match_dup 2)))]
3503 { operands[3] = gen_reg_rtx (DImode); })
3506 [(set (match_operand:DI 0 "register_operand" "")
3507 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3508 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3509 (clobber (match_operand:DI 3 "register_operand" ""))]
3510 "operands[2] != const0_rtx"
3511 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3512 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3513 (match_dup 1) (match_dup 2)))]
3516 (define_insn "*smin_const0"
3517 [(set (match_operand:DI 0 "register_operand" "=r")
3518 (smin:DI (match_operand:DI 1 "register_operand" "0")
3522 [(set_attr "type" "icmov")])
3524 (define_expand "umaxdi3"
3526 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3527 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3528 (set (match_operand:DI 0 "register_operand" "")
3529 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3530 (match_dup 1) (match_dup 2)))]
3532 "operands[3] = gen_reg_rtx (DImode);")
3535 [(set (match_operand:DI 0 "register_operand" "")
3536 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3537 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3538 (clobber (match_operand:DI 3 "register_operand" ""))]
3539 "operands[2] != const0_rtx"
3540 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3541 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3542 (match_dup 1) (match_dup 2)))]
3545 (define_expand "umindi3"
3547 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3548 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3549 (set (match_operand:DI 0 "register_operand" "")
3550 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3551 (match_dup 1) (match_dup 2)))]
3553 "operands[3] = gen_reg_rtx (DImode);")
3556 [(set (match_operand:DI 0 "register_operand" "")
3557 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3558 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3559 (clobber (match_operand:DI 3 "register_operand" ""))]
3560 "operands[2] != const0_rtx"
3561 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3562 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3563 (match_dup 1) (match_dup 2)))]
3566 (define_insn "*bcc_normal"
3569 (match_operator 1 "signed_comparison_operator"
3570 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3572 (label_ref (match_operand 0 "" ""))
3576 [(set_attr "type" "ibr")])
3578 (define_insn "*bcc_reverse"
3581 (match_operator 1 "signed_comparison_operator"
3582 [(match_operand:DI 2 "register_operand" "r")
3586 (label_ref (match_operand 0 "" ""))))]
3589 [(set_attr "type" "ibr")])
3591 (define_insn "*blbs_normal"
3594 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3598 (label_ref (match_operand 0 "" ""))
3602 [(set_attr "type" "ibr")])
3604 (define_insn "*blbc_normal"
3607 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3611 (label_ref (match_operand 0 "" ""))
3615 [(set_attr "type" "ibr")])
3621 (match_operator 1 "comparison_operator"
3622 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3624 (match_operand:DI 3 "const_int_operand" ""))
3626 (label_ref (match_operand 0 "" ""))
3628 (clobber (match_operand:DI 4 "register_operand" ""))])]
3629 "INTVAL (operands[3]) != 0"
3631 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3633 (if_then_else (match_op_dup 1
3634 [(zero_extract:DI (match_dup 4)
3638 (label_ref (match_dup 0))
3642 ;; The following are the corresponding floating-point insns. Recall
3643 ;; we need to have variants that expand the arguments from SFmode
3646 (define_insn "*cmpdf_ieee"
3647 [(set (match_operand:DF 0 "register_operand" "=&f")
3648 (match_operator:DF 1 "alpha_fp_comparison_operator"
3649 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3650 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3651 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3652 "cmp%-%C1%/ %R2,%R3,%0"
3653 [(set_attr "type" "fadd")
3654 (set_attr "trap" "yes")
3655 (set_attr "trap_suffix" "su")])
3657 (define_insn "*cmpdf_internal"
3658 [(set (match_operand:DF 0 "register_operand" "=f")
3659 (match_operator:DF 1 "alpha_fp_comparison_operator"
3660 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3661 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3662 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3663 "cmp%-%C1%/ %R2,%R3,%0"
3664 [(set_attr "type" "fadd")
3665 (set_attr "trap" "yes")
3666 (set_attr "trap_suffix" "su")])
3668 (define_insn "*cmpdf_ieee_ext1"
3669 [(set (match_operand:DF 0 "register_operand" "=&f")
3670 (match_operator:DF 1 "alpha_fp_comparison_operator"
3672 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3673 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3674 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3675 "cmp%-%C1%/ %R2,%R3,%0"
3676 [(set_attr "type" "fadd")
3677 (set_attr "trap" "yes")
3678 (set_attr "trap_suffix" "su")])
3680 (define_insn "*cmpdf_ext1"
3681 [(set (match_operand:DF 0 "register_operand" "=f")
3682 (match_operator:DF 1 "alpha_fp_comparison_operator"
3684 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3685 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3686 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3687 "cmp%-%C1%/ %R2,%R3,%0"
3688 [(set_attr "type" "fadd")
3689 (set_attr "trap" "yes")
3690 (set_attr "trap_suffix" "su")])
3692 (define_insn "*cmpdf_ieee_ext2"
3693 [(set (match_operand:DF 0 "register_operand" "=&f")
3694 (match_operator:DF 1 "alpha_fp_comparison_operator"
3695 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3697 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3698 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3699 "cmp%-%C1%/ %R2,%R3,%0"
3700 [(set_attr "type" "fadd")
3701 (set_attr "trap" "yes")
3702 (set_attr "trap_suffix" "su")])
3704 (define_insn "*cmpdf_ext2"
3705 [(set (match_operand:DF 0 "register_operand" "=f")
3706 (match_operator:DF 1 "alpha_fp_comparison_operator"
3707 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3709 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3710 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3711 "cmp%-%C1%/ %R2,%R3,%0"
3712 [(set_attr "type" "fadd")
3713 (set_attr "trap" "yes")
3714 (set_attr "trap_suffix" "su")])
3716 (define_insn "*cmpdf_ieee_ext3"
3717 [(set (match_operand:DF 0 "register_operand" "=&f")
3718 (match_operator:DF 1 "alpha_fp_comparison_operator"
3720 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3722 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3723 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3724 "cmp%-%C1%/ %R2,%R3,%0"
3725 [(set_attr "type" "fadd")
3726 (set_attr "trap" "yes")
3727 (set_attr "trap_suffix" "su")])
3729 (define_insn "*cmpdf_ext3"
3730 [(set (match_operand:DF 0 "register_operand" "=f")
3731 (match_operator:DF 1 "alpha_fp_comparison_operator"
3733 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3735 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3736 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3737 "cmp%-%C1%/ %R2,%R3,%0"
3738 [(set_attr "type" "fadd")
3739 (set_attr "trap" "yes")
3740 (set_attr "trap_suffix" "su")])
3742 (define_insn "*movdfcc_internal"
3743 [(set (match_operand:DF 0 "register_operand" "=f,f")
3745 (match_operator 3 "signed_comparison_operator"
3746 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3747 (match_operand:DF 2 "fp0_operand" "G,G")])
3748 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3749 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3753 fcmov%D3 %R4,%R5,%0"
3754 [(set_attr "type" "fcmov")])
3756 (define_insn "*movsfcc_internal"
3757 [(set (match_operand:SF 0 "register_operand" "=f,f")
3759 (match_operator 3 "signed_comparison_operator"
3760 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3761 (match_operand:DF 2 "fp0_operand" "G,G")])
3762 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3763 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3767 fcmov%D3 %R4,%R5,%0"
3768 [(set_attr "type" "fcmov")])
3770 (define_insn "*movdfcc_ext1"
3771 [(set (match_operand:DF 0 "register_operand" "=f,f")
3773 (match_operator 3 "signed_comparison_operator"
3774 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3775 (match_operand:DF 2 "fp0_operand" "G,G")])
3776 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3777 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3781 fcmov%D3 %R4,%R5,%0"
3782 [(set_attr "type" "fcmov")])
3784 (define_insn "*movdfcc_ext2"
3785 [(set (match_operand:DF 0 "register_operand" "=f,f")
3787 (match_operator 3 "signed_comparison_operator"
3789 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3790 (match_operand:DF 2 "fp0_operand" "G,G")])
3791 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3792 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3796 fcmov%D3 %R4,%R5,%0"
3797 [(set_attr "type" "fcmov")])
3799 (define_insn "*movdfcc_ext3"
3800 [(set (match_operand:SF 0 "register_operand" "=f,f")
3802 (match_operator 3 "signed_comparison_operator"
3804 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3805 (match_operand:DF 2 "fp0_operand" "G,G")])
3806 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3807 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3811 fcmov%D3 %R4,%R5,%0"
3812 [(set_attr "type" "fcmov")])
3814 (define_insn "*movdfcc_ext4"
3815 [(set (match_operand:DF 0 "register_operand" "=f,f")
3817 (match_operator 3 "signed_comparison_operator"
3819 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3820 (match_operand:DF 2 "fp0_operand" "G,G")])
3821 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3822 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3826 fcmov%D3 %R4,%R5,%0"
3827 [(set_attr "type" "fcmov")])
3829 (define_expand "maxdf3"
3831 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3832 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3833 (set (match_operand:DF 0 "register_operand" "")
3834 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3835 (match_dup 1) (match_dup 2)))]
3838 operands[3] = gen_reg_rtx (DFmode);
3839 operands[4] = CONST0_RTX (DFmode);
3842 (define_expand "mindf3"
3844 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3845 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3846 (set (match_operand:DF 0 "register_operand" "")
3847 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3848 (match_dup 1) (match_dup 2)))]
3851 operands[3] = gen_reg_rtx (DFmode);
3852 operands[4] = CONST0_RTX (DFmode);
3855 (define_expand "maxsf3"
3857 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3858 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3859 (set (match_operand:SF 0 "register_operand" "")
3860 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3861 (match_dup 1) (match_dup 2)))]
3864 operands[3] = gen_reg_rtx (DFmode);
3865 operands[4] = CONST0_RTX (DFmode);
3868 (define_expand "minsf3"
3870 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3871 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3872 (set (match_operand:SF 0 "register_operand" "")
3873 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3874 (match_dup 1) (match_dup 2)))]
3877 operands[3] = gen_reg_rtx (DFmode);
3878 operands[4] = CONST0_RTX (DFmode);
3881 (define_insn "*fbcc_normal"
3884 (match_operator 1 "signed_comparison_operator"
3885 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3886 (match_operand:DF 3 "fp0_operand" "G")])
3887 (label_ref (match_operand 0 "" ""))
3891 [(set_attr "type" "fbr")])
3893 (define_insn "*fbcc_ext_normal"
3896 (match_operator 1 "signed_comparison_operator"
3898 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3899 (match_operand:DF 3 "fp0_operand" "G")])
3900 (label_ref (match_operand 0 "" ""))
3904 [(set_attr "type" "fbr")])
3906 ;; These are the main define_expand's used to make conditional branches
3909 (define_expand "cmpdf"
3910 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3911 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3914 alpha_compare.op0 = operands[0];
3915 alpha_compare.op1 = operands[1];
3916 alpha_compare.fp_p = 1;
3920 (define_expand "cmptf"
3921 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3922 (match_operand:TF 1 "general_operand" "")))]
3923 "TARGET_HAS_XFLOATING_LIBS"
3925 alpha_compare.op0 = operands[0];
3926 alpha_compare.op1 = operands[1];
3927 alpha_compare.fp_p = 1;
3931 (define_expand "cmpdi"
3932 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3933 (match_operand:DI 1 "general_operand" "")))]
3936 alpha_compare.op0 = operands[0];
3937 alpha_compare.op1 = operands[1];
3938 alpha_compare.fp_p = 0;
3942 (define_expand "beq"
3944 (if_then_else (match_dup 1)
3945 (label_ref (match_operand 0 "" ""))
3948 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3950 (define_expand "bne"
3952 (if_then_else (match_dup 1)
3953 (label_ref (match_operand 0 "" ""))
3956 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3958 (define_expand "blt"
3960 (if_then_else (match_dup 1)
3961 (label_ref (match_operand 0 "" ""))
3964 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3966 (define_expand "ble"
3968 (if_then_else (match_dup 1)
3969 (label_ref (match_operand 0 "" ""))
3972 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3974 (define_expand "bgt"
3976 (if_then_else (match_dup 1)
3977 (label_ref (match_operand 0 "" ""))
3980 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3982 (define_expand "bge"
3984 (if_then_else (match_dup 1)
3985 (label_ref (match_operand 0 "" ""))
3988 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3990 (define_expand "bltu"
3992 (if_then_else (match_dup 1)
3993 (label_ref (match_operand 0 "" ""))
3996 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3998 (define_expand "bleu"
4000 (if_then_else (match_dup 1)
4001 (label_ref (match_operand 0 "" ""))
4004 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4006 (define_expand "bgtu"
4008 (if_then_else (match_dup 1)
4009 (label_ref (match_operand 0 "" ""))
4012 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4014 (define_expand "bgeu"
4016 (if_then_else (match_dup 1)
4017 (label_ref (match_operand 0 "" ""))
4020 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4022 (define_expand "bunordered"
4024 (if_then_else (match_dup 1)
4025 (label_ref (match_operand 0 "" ""))
4028 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4030 (define_expand "bordered"
4032 (if_then_else (match_dup 1)
4033 (label_ref (match_operand 0 "" ""))
4036 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4038 (define_expand "seq"
4039 [(set (match_operand:DI 0 "register_operand" "")
4042 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4044 (define_expand "sne"
4045 [(set (match_operand:DI 0 "register_operand" "")
4048 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4050 (define_expand "slt"
4051 [(set (match_operand:DI 0 "register_operand" "")
4054 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4056 (define_expand "sle"
4057 [(set (match_operand:DI 0 "register_operand" "")
4060 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4062 (define_expand "sgt"
4063 [(set (match_operand:DI 0 "register_operand" "")
4066 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4068 (define_expand "sge"
4069 [(set (match_operand:DI 0 "register_operand" "")
4072 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4074 (define_expand "sltu"
4075 [(set (match_operand:DI 0 "register_operand" "")
4078 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4080 (define_expand "sleu"
4081 [(set (match_operand:DI 0 "register_operand" "")
4084 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4086 (define_expand "sgtu"
4087 [(set (match_operand:DI 0 "register_operand" "")
4090 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4092 (define_expand "sgeu"
4093 [(set (match_operand:DI 0 "register_operand" "")
4096 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4098 (define_expand "sunordered"
4099 [(set (match_operand:DI 0 "register_operand" "")
4102 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4104 (define_expand "sordered"
4105 [(set (match_operand:DI 0 "register_operand" "")
4108 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4110 ;; These are the main define_expand's used to make conditional moves.
4112 (define_expand "movsicc"
4113 [(set (match_operand:SI 0 "register_operand" "")
4114 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4115 (match_operand:SI 2 "reg_or_8bit_operand" "")
4116 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4119 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4123 (define_expand "movdicc"
4124 [(set (match_operand:DI 0 "register_operand" "")
4125 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4126 (match_operand:DI 2 "reg_or_8bit_operand" "")
4127 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4130 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4134 (define_expand "movsfcc"
4135 [(set (match_operand:SF 0 "register_operand" "")
4136 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4137 (match_operand:SF 2 "reg_or_8bit_operand" "")
4138 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4141 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4145 (define_expand "movdfcc"
4146 [(set (match_operand:DF 0 "register_operand" "")
4147 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4148 (match_operand:DF 2 "reg_or_8bit_operand" "")
4149 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4152 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4156 ;; These define_split definitions are used in cases when comparisons have
4157 ;; not be stated in the correct way and we need to reverse the second
4158 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4159 ;; comparison that tests the result being reversed. We have one define_split
4160 ;; for each use of a comparison. They do not match valid insns and need
4161 ;; not generate valid insns.
4163 ;; We can also handle equality comparisons (and inequality comparisons in
4164 ;; cases where the resulting add cannot overflow) by doing an add followed by
4165 ;; a comparison with zero. This is faster since the addition takes one
4166 ;; less cycle than a compare when feeding into a conditional move.
4167 ;; For this case, we also have an SImode pattern since we can merge the add
4168 ;; and sign extend and the order doesn't matter.
4170 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4171 ;; operation could have been generated.
4174 [(set (match_operand:DI 0 "register_operand" "")
4176 (match_operator 1 "comparison_operator"
4177 [(match_operand:DI 2 "reg_or_0_operand" "")
4178 (match_operand:DI 3 "reg_or_cint_operand" "")])
4179 (match_operand:DI 4 "reg_or_cint_operand" "")
4180 (match_operand:DI 5 "reg_or_cint_operand" "")))
4181 (clobber (match_operand:DI 6 "register_operand" ""))]
4182 "operands[3] != const0_rtx"
4183 [(set (match_dup 6) (match_dup 7))
4185 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4187 enum rtx_code code = GET_CODE (operands[1]);
4188 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4190 /* If we are comparing for equality with a constant and that constant
4191 appears in the arm when the register equals the constant, use the
4192 register since that is more likely to match (and to produce better code
4195 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4196 && rtx_equal_p (operands[4], operands[3]))
4197 operands[4] = operands[2];
4199 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4200 && rtx_equal_p (operands[5], operands[3]))
4201 operands[5] = operands[2];
4203 if (code == NE || code == EQ
4204 || (extended_count (operands[2], DImode, unsignedp) >= 1
4205 && extended_count (operands[3], DImode, unsignedp) >= 1))
4207 if (GET_CODE (operands[3]) == CONST_INT)
4208 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4209 GEN_INT (- INTVAL (operands[3])));
4211 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4213 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4216 else if (code == EQ || code == LE || code == LT
4217 || code == LEU || code == LTU)
4219 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4220 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4224 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4225 operands[2], operands[3]);
4226 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4231 [(set (match_operand:DI 0 "register_operand" "")
4233 (match_operator 1 "comparison_operator"
4234 [(match_operand:SI 2 "reg_or_0_operand" "")
4235 (match_operand:SI 3 "reg_or_cint_operand" "")])
4236 (match_operand:DI 4 "reg_or_8bit_operand" "")
4237 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4238 (clobber (match_operand:DI 6 "register_operand" ""))]
4239 "operands[3] != const0_rtx
4240 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4241 [(set (match_dup 6) (match_dup 7))
4243 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4245 enum rtx_code code = GET_CODE (operands[1]);
4246 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4249 if ((code != NE && code != EQ
4250 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4251 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4254 if (GET_CODE (operands[3]) == CONST_INT)
4255 tem = gen_rtx_PLUS (SImode, operands[2],
4256 GEN_INT (- INTVAL (operands[3])));
4258 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4260 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4261 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4262 operands[6], const0_rtx);
4268 (match_operator 1 "comparison_operator"
4269 [(match_operand:DI 2 "reg_or_0_operand" "")
4270 (match_operand:DI 3 "reg_or_cint_operand" "")])
4271 (label_ref (match_operand 0 "" ""))
4273 (clobber (match_operand:DI 4 "register_operand" ""))]
4274 "operands[3] != const0_rtx"
4275 [(set (match_dup 4) (match_dup 5))
4276 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4278 enum rtx_code code = GET_CODE (operands[1]);
4279 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4281 if (code == NE || code == EQ
4282 || (extended_count (operands[2], DImode, unsignedp) >= 1
4283 && extended_count (operands[3], DImode, unsignedp) >= 1))
4285 if (GET_CODE (operands[3]) == CONST_INT)
4286 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4287 GEN_INT (- INTVAL (operands[3])));
4289 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4291 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4294 else if (code == EQ || code == LE || code == LT
4295 || code == LEU || code == LTU)
4297 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4298 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4302 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4303 operands[2], operands[3]);
4304 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4311 (match_operator 1 "comparison_operator"
4312 [(match_operand:SI 2 "reg_or_0_operand" "")
4313 (match_operand:SI 3 "const_int_operand" "")])
4314 (label_ref (match_operand 0 "" ""))
4316 (clobber (match_operand:DI 4 "register_operand" ""))]
4317 "operands[3] != const0_rtx
4318 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4319 [(set (match_dup 4) (match_dup 5))
4320 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4324 if (GET_CODE (operands[3]) == CONST_INT)
4325 tem = gen_rtx_PLUS (SImode, operands[2],
4326 GEN_INT (- INTVAL (operands[3])));
4328 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4330 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4331 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4332 operands[4], const0_rtx);
4335 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4336 ;; This eliminates one, and sometimes two, insns when the AND can be done
4339 [(set (match_operand:DI 0 "register_operand" "")
4340 (match_operator:DI 1 "comparison_operator"
4341 [(match_operand:DI 2 "register_operand" "")
4342 (match_operand:DI 3 "const_int_operand" "")]))
4343 (clobber (match_operand:DI 4 "register_operand" ""))]
4344 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4345 && (GET_CODE (operands[1]) == GTU
4346 || GET_CODE (operands[1]) == LEU
4347 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4348 && extended_count (operands[2], DImode, 1) > 0))"
4349 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4350 (set (match_dup 0) (match_dup 6))]
4352 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4353 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4354 || GET_CODE (operands[1]) == GT)
4356 DImode, operands[4], const0_rtx);
4359 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4362 [(set (match_operand 0 "register_operand" "")
4363 (if_then_else (match_operator 1 "signed_comparison_operator"
4364 [(match_operand:DI 2 "reg_or_0_operand" "")
4366 (match_operand 3 "const_int_operand" "")
4367 (match_operand 4 "const_int_operand" "")))]
4371 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4372 operands[2], operands[3], operands[4]))
4378 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4379 ;; Oh well, we match it in movcc, so it must be partially our fault.
4381 [(set (match_operand 0 "register_operand" "")
4382 (if_then_else (match_operator 1 "signed_comparison_operator"
4384 (match_operand:DI 2 "reg_or_0_operand" "")])
4385 (match_operand 3 "const_int_operand" "")
4386 (match_operand 4 "const_int_operand" "")))]
4390 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4391 operands[0], operands[2], operands[3],
4398 (define_insn_and_split "*cmp_sadd_di"
4399 [(set (match_operand:DI 0 "register_operand" "=r")
4400 (plus:DI (if_then_else:DI
4401 (match_operator 1 "alpha_zero_comparison_operator"
4402 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4404 (match_operand:DI 3 "const48_operand" "I")
4406 (match_operand:DI 4 "sext_add_operand" "rIO")))
4407 (clobber (match_scratch:DI 5 "=r"))]
4410 "! no_new_pseudos || reload_completed"
4412 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4414 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4417 if (! no_new_pseudos)
4418 operands[5] = gen_reg_rtx (DImode);
4419 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4420 operands[5] = operands[0];
4423 (define_insn_and_split "*cmp_sadd_si"
4424 [(set (match_operand:SI 0 "register_operand" "=r")
4425 (plus:SI (if_then_else:SI
4426 (match_operator 1 "alpha_zero_comparison_operator"
4427 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4429 (match_operand:SI 3 "const48_operand" "I")
4431 (match_operand:SI 4 "sext_add_operand" "rIO")))
4432 (clobber (match_scratch:SI 5 "=r"))]
4435 "! no_new_pseudos || reload_completed"
4437 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4439 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4442 if (! no_new_pseudos)
4443 operands[5] = gen_reg_rtx (DImode);
4444 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4445 operands[5] = operands[0];
4448 (define_insn_and_split "*cmp_sadd_sidi"
4449 [(set (match_operand:DI 0 "register_operand" "=r")
4451 (plus:SI (if_then_else:SI
4452 (match_operator 1 "alpha_zero_comparison_operator"
4453 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4455 (match_operand:SI 3 "const48_operand" "I")
4457 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4458 (clobber (match_scratch:SI 5 "=r"))]
4461 "! no_new_pseudos || reload_completed"
4463 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4465 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4468 if (! no_new_pseudos)
4469 operands[5] = gen_reg_rtx (DImode);
4470 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4471 operands[5] = operands[0];
4474 (define_insn_and_split "*cmp_ssub_di"
4475 [(set (match_operand:DI 0 "register_operand" "=r")
4476 (minus:DI (if_then_else:DI
4477 (match_operator 1 "alpha_zero_comparison_operator"
4478 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4480 (match_operand:DI 3 "const48_operand" "I")
4482 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4483 (clobber (match_scratch:DI 5 "=r"))]
4486 "! no_new_pseudos || reload_completed"
4488 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4490 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4493 if (! no_new_pseudos)
4494 operands[5] = gen_reg_rtx (DImode);
4495 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4496 operands[5] = operands[0];
4499 (define_insn_and_split "*cmp_ssub_si"
4500 [(set (match_operand:SI 0 "register_operand" "=r")
4501 (minus:SI (if_then_else:SI
4502 (match_operator 1 "alpha_zero_comparison_operator"
4503 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4505 (match_operand:SI 3 "const48_operand" "I")
4507 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4508 (clobber (match_scratch:SI 5 "=r"))]
4511 "! no_new_pseudos || reload_completed"
4513 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4515 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4518 if (! no_new_pseudos)
4519 operands[5] = gen_reg_rtx (DImode);
4520 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4521 operands[5] = operands[0];
4524 (define_insn_and_split "*cmp_ssub_sidi"
4525 [(set (match_operand:DI 0 "register_operand" "=r")
4527 (minus:SI (if_then_else:SI
4528 (match_operator 1 "alpha_zero_comparison_operator"
4529 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4531 (match_operand:SI 3 "const48_operand" "I")
4533 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4534 (clobber (match_scratch:SI 5 "=r"))]
4537 "! no_new_pseudos || reload_completed"
4539 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4541 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4544 if (! no_new_pseudos)
4545 operands[5] = gen_reg_rtx (DImode);
4546 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4547 operands[5] = operands[0];
4550 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4551 ;; work differently, so we have different patterns for each.
4553 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4554 ;; call. The CIW contains information about arguments passed in registers
4555 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4556 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4557 ;; in the presence of inlining since the CIWs for calls performed by the
4558 ;; inlined function must be stored in the SSIB of the function it is inlined
4559 ;; into as well. We encode the CIW in an unspec and append it to the list
4560 ;; of the CIWs for the current function only when the instruction for loading
4561 ;; $25 is generated.
4563 (define_expand "call"
4564 [(use (match_operand:DI 0 "" ""))
4565 (use (match_operand 1 "" ""))
4566 (use (match_operand 2 "" ""))
4567 (use (match_operand 3 "" ""))]
4570 if (TARGET_ABI_WINDOWS_NT)
4571 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4572 else if (TARGET_ABI_OPEN_VMS)
4573 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4574 else if (TARGET_ABI_UNICOSMK)
4575 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4577 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4581 (define_expand "sibcall"
4582 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4583 (match_operand 1 "" ""))
4584 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4587 if (GET_CODE (operands[0]) != MEM)
4589 operands[0] = XEXP (operands[0], 0);
4592 (define_expand "call_osf"
4593 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4594 (match_operand 1 "" ""))
4596 (clobber (reg:DI 26))])]
4599 if (GET_CODE (operands[0]) != MEM)
4602 operands[0] = XEXP (operands[0], 0);
4603 if (! call_operand (operands[0], Pmode))
4604 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4607 (define_expand "call_nt"
4608 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4609 (match_operand 1 "" ""))
4610 (clobber (reg:DI 26))])]
4613 if (GET_CODE (operands[0]) != MEM)
4616 operands[0] = XEXP (operands[0], 0);
4617 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4618 operands[0] = force_reg (DImode, operands[0]);
4621 ;; Calls on Unicos/Mk are always indirect.
4622 ;; op 0: symbol ref for called function
4623 ;; op 1: CIW for $25 represented by an unspec
4625 (define_expand "call_umk"
4626 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4627 (match_operand 1 "" ""))
4629 (clobber (reg:DI 26))])]
4632 if (GET_CODE (operands[0]) != MEM)
4635 /* Always load the address of the called function into a register;
4636 load the CIW in $25. */
4638 operands[0] = XEXP (operands[0], 0);
4639 if (GET_CODE (operands[0]) != REG)
4640 operands[0] = force_reg (DImode, operands[0]);
4642 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4646 ;; call openvms/alpha
4647 ;; op 0: symbol ref for called function
4648 ;; op 1: next_arg_reg (argument information value for R25)
4650 (define_expand "call_vms"
4651 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4652 (match_operand 1 "" ""))
4656 (clobber (reg:DI 27))])]
4659 if (GET_CODE (operands[0]) != MEM)
4662 operands[0] = XEXP (operands[0], 0);
4664 /* Always load AI with argument information, then handle symbolic and
4665 indirect call differently. Load RA and set operands[2] to PV in
4668 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4669 if (GET_CODE (operands[0]) == SYMBOL_REF)
4671 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4673 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4675 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4679 emit_move_insn (gen_rtx_REG (Pmode, 26),
4680 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4681 operands[2] = operands[0];
4686 (define_expand "call_value"
4687 [(use (match_operand 0 "" ""))
4688 (use (match_operand:DI 1 "" ""))
4689 (use (match_operand 2 "" ""))
4690 (use (match_operand 3 "" ""))
4691 (use (match_operand 4 "" ""))]
4694 if (TARGET_ABI_WINDOWS_NT)
4695 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4696 else if (TARGET_ABI_OPEN_VMS)
4697 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4699 else if (TARGET_ABI_UNICOSMK)
4700 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4703 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4708 (define_expand "sibcall_value"
4709 [(parallel [(set (match_operand 0 "" "")
4710 (call (mem:DI (match_operand 1 "" ""))
4711 (match_operand 2 "" "")))
4712 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4715 if (GET_CODE (operands[1]) != MEM)
4717 operands[1] = XEXP (operands[1], 0);
4720 (define_expand "call_value_osf"
4721 [(parallel [(set (match_operand 0 "" "")
4722 (call (mem:DI (match_operand 1 "" ""))
4723 (match_operand 2 "" "")))
4725 (clobber (reg:DI 26))])]
4728 if (GET_CODE (operands[1]) != MEM)
4731 operands[1] = XEXP (operands[1], 0);
4732 if (! call_operand (operands[1], Pmode))
4733 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4736 (define_expand "call_value_nt"
4737 [(parallel [(set (match_operand 0 "" "")
4738 (call (mem:DI (match_operand 1 "" ""))
4739 (match_operand 2 "" "")))
4740 (clobber (reg:DI 26))])]
4743 if (GET_CODE (operands[1]) != MEM)
4746 operands[1] = XEXP (operands[1], 0);
4747 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4748 operands[1] = force_reg (DImode, operands[1]);
4751 (define_expand "call_value_vms"
4752 [(parallel [(set (match_operand 0 "" "")
4753 (call (mem:DI (match_operand:DI 1 "" ""))
4754 (match_operand 2 "" "")))
4758 (clobber (reg:DI 27))])]
4761 if (GET_CODE (operands[1]) != MEM)
4764 operands[1] = XEXP (operands[1], 0);
4766 /* Always load AI with argument information, then handle symbolic and
4767 indirect call differently. Load RA and set operands[3] to PV in
4770 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4771 if (GET_CODE (operands[1]) == SYMBOL_REF)
4773 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4775 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4777 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4781 emit_move_insn (gen_rtx_REG (Pmode, 26),
4782 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4783 operands[3] = operands[1];
4787 (define_expand "call_value_umk"
4788 [(parallel [(set (match_operand 0 "" "")
4789 (call (mem:DI (match_operand 1 "" ""))
4790 (match_operand 2 "" "")))
4792 (clobber (reg:DI 26))])]
4795 if (GET_CODE (operands[1]) != MEM)
4798 operands[1] = XEXP (operands[1], 0);
4799 if (GET_CODE (operands[1]) != REG)
4800 operands[1] = force_reg (DImode, operands[1]);
4802 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4805 (define_insn "*call_osf_1_er"
4806 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4807 (match_operand 1 "" ""))
4809 (clobber (reg:DI 26))]
4810 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4812 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4814 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4815 [(set_attr "type" "jsr")
4816 (set_attr "length" "12,*,16")])
4818 ;; We must use peep2 instead of a split because we need accurate life
4819 ;; information for $gp. Consider the case of { bar(); while (1); }.
4821 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4822 (match_operand 1 "" ""))
4824 (clobber (reg:DI 26))])]
4825 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4826 && ! current_file_function_operand (operands[0], Pmode)
4827 && peep2_regno_dead_p (1, 29)"
4828 [(parallel [(call (mem:DI (match_dup 2))
4830 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4831 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4833 (use (match_dup 3))])]
4835 if (CONSTANT_P (operands[0]))
4837 operands[2] = gen_rtx_REG (Pmode, 27);
4838 operands[3] = GEN_INT (alpha_next_sequence_number++);
4839 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4840 operands[0], operands[3]));
4844 operands[2] = operands[0];
4845 operands[0] = const0_rtx;
4846 operands[3] = const0_rtx;
4851 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4852 (match_operand 1 "" ""))
4854 (clobber (reg:DI 26))])]
4855 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4856 && ! current_file_function_operand (operands[0], Pmode)
4857 && ! peep2_regno_dead_p (1, 29)"
4858 [(parallel [(call (mem:DI (match_dup 2))
4860 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4861 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4863 (use (match_dup 4))])
4865 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4867 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4869 if (CONSTANT_P (operands[0]))
4871 operands[2] = gen_rtx_REG (Pmode, 27);
4872 operands[4] = GEN_INT (alpha_next_sequence_number++);
4873 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4874 operands[0], operands[4]));
4878 operands[2] = operands[0];
4879 operands[0] = const0_rtx;
4880 operands[4] = const0_rtx;
4882 operands[3] = GEN_INT (alpha_next_sequence_number++);
4885 ;; We add a blockage unspec_volatile to prevent insns from moving down
4886 ;; from above the call to in between the call and the ldah gpdisp.
4888 (define_insn "*call_osf_2_er"
4889 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4890 (match_operand 1 "" ""))
4891 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4892 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4893 (use (match_operand 2 "" ""))
4894 (use (match_operand 3 "const_int_operand" ""))]
4895 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4896 "jsr $26,(%0),%2%J3"
4897 [(set_attr "type" "jsr")])
4899 (define_insn "*call_osf_1_noreturn"
4900 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4901 (match_operand 1 "" ""))
4903 (clobber (reg:DI 26))]
4904 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4905 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4910 [(set_attr "type" "jsr")
4911 (set_attr "length" "*,*,8")])
4913 (define_insn "*call_osf_1"
4914 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4915 (match_operand 1 "" ""))
4917 (clobber (reg:DI 26))]
4918 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4920 jsr $26,($27),0\;ldgp $29,0($26)
4922 jsr $26,%0\;ldgp $29,0($26)"
4923 [(set_attr "type" "jsr")
4924 (set_attr "length" "12,*,16")])
4926 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4927 ;; doesn't do what we want.
4928 (define_insn "*sibcall_osf_1_er"
4929 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4930 (match_operand 1 "" ""))
4931 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4932 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4935 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4936 [(set_attr "type" "jsr")
4937 (set_attr "length" "*,8")])
4939 (define_insn "*sibcall_osf_1"
4940 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4941 (match_operand 1 "" ""))
4942 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4943 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4946 lda $27,%0\;jmp $31,($27),%0"
4947 [(set_attr "type" "jsr")
4948 (set_attr "length" "*,8")])
4950 (define_insn "*call_nt_1"
4951 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4952 (match_operand 1 "" ""))
4953 (clobber (reg:DI 26))]
4954 "TARGET_ABI_WINDOWS_NT"
4959 [(set_attr "type" "jsr")
4960 (set_attr "length" "*,*,12")])
4962 (define_insn "*call_vms_1"
4963 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4964 (match_operand 1 "" ""))
4965 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4968 (clobber (reg:DI 27))]
4969 "TARGET_ABI_OPEN_VMS"
4971 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4972 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4973 [(set_attr "type" "jsr")
4974 (set_attr "length" "12,16")])
4976 (define_insn "*call_umk_1"
4977 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4978 (match_operand 1 "" ""))
4980 (clobber (reg:DI 26))]
4981 "TARGET_ABI_UNICOSMK"
4983 [(set_attr "type" "jsr")])
4985 ;; Call subroutine returning any type.
4987 (define_expand "untyped_call"
4988 [(parallel [(call (match_operand 0 "" "")
4990 (match_operand 1 "" "")
4991 (match_operand 2 "" "")])]
4996 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4998 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5000 rtx set = XVECEXP (operands[2], 0, i);
5001 emit_move_insn (SET_DEST (set), SET_SRC (set));
5004 /* The optimizer does not know that the call sets the function value
5005 registers we stored in the result block. We avoid problems by
5006 claiming that all hard registers are used and clobbered at this
5008 emit_insn (gen_blockage ());
5013 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5014 ;; all of memory. This blocks insns from being moved across this point.
5016 (define_insn "blockage"
5017 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5020 [(set_attr "length" "0")])
5024 (label_ref (match_operand 0 "" "")))]
5027 [(set_attr "type" "ibr")])
5029 (define_expand "return"
5034 (define_insn "*return_internal"
5038 [(set_attr "type" "ibr")])
5040 (define_insn "indirect_jump"
5041 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
5044 [(set_attr "type" "ibr")])
5046 (define_expand "tablejump"
5047 [(parallel [(set (pc)
5048 (match_operand 0 "register_operand" ""))
5049 (use (label_ref:DI (match_operand 1 "" "")))])]
5052 if (TARGET_ABI_WINDOWS_NT)
5054 rtx dest = gen_reg_rtx (DImode);
5055 emit_insn (gen_extendsidi2 (dest, operands[0]));
5058 else if (TARGET_ABI_OSF)
5060 rtx dest = gen_reg_rtx (DImode);
5061 emit_insn (gen_extendsidi2 (dest, operands[0]));
5062 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
5067 (define_insn "*tablejump_osf_nt_internal"
5069 (match_operand:DI 0 "register_operand" "r"))
5070 (use (label_ref:DI (match_operand 1 "" "")))]
5071 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5072 && alpha_tablejump_addr_vec (insn)"
5074 operands[2] = alpha_tablejump_best_label (insn);
5075 return "jmp $31,(%0),%2";
5077 [(set_attr "type" "ibr")])
5079 (define_insn "*tablejump_internal"
5081 (match_operand:DI 0 "register_operand" "r"))
5082 (use (label_ref (match_operand 1 "" "")))]
5085 [(set_attr "type" "ibr")])
5087 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5088 ;; want to have to include pal.h in our .s file.
5090 ;; Technically the type for call_pal is jsr, but we use that for determining
5091 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5094 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5097 [(set_attr "type" "ibr")])
5099 ;; Finally, we have the basic data motion insns. The byte and word insns
5100 ;; are done via define_expand. Start with the floating-point insns, since
5101 ;; they are simpler.
5103 (define_insn "*movsf_nofix"
5104 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5105 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5106 "TARGET_FPREGS && ! TARGET_FIX
5107 && (register_operand (operands[0], SFmode)
5108 || reg_or_fp0_operand (operands[1], SFmode))"
5116 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5118 (define_insn "*movsf_fix"
5119 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5120 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5121 "TARGET_FPREGS && TARGET_FIX
5122 && (register_operand (operands[0], SFmode)
5123 || reg_or_fp0_operand (operands[1], SFmode))"
5133 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5135 (define_insn "*movsf_nofp"
5136 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5137 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5139 && (register_operand (operands[0], SFmode)
5140 || reg_or_fp0_operand (operands[1], SFmode))"
5145 [(set_attr "type" "ilog,ild,ist")])
5147 (define_insn "*movdf_nofix"
5148 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5149 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5150 "TARGET_FPREGS && ! TARGET_FIX
5151 && (register_operand (operands[0], DFmode)
5152 || reg_or_fp0_operand (operands[1], DFmode))"
5160 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5162 (define_insn "*movdf_fix"
5163 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5164 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5165 "TARGET_FPREGS && TARGET_FIX
5166 && (register_operand (operands[0], DFmode)
5167 || reg_or_fp0_operand (operands[1], DFmode))"
5177 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5179 (define_insn "*movdf_nofp"
5180 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5181 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5183 && (register_operand (operands[0], DFmode)
5184 || reg_or_fp0_operand (operands[1], DFmode))"
5189 [(set_attr "type" "ilog,ild,ist")])
5191 ;; Subregs suck for register allocation. Pretend we can move TFmode
5192 ;; data between general registers until after reload.
5194 (define_insn_and_split "*movtf_internal"
5195 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5196 (match_operand:TF 1 "input_operand" "roG,rG"))]
5197 "register_operand (operands[0], TFmode)
5198 || reg_or_fp0_operand (operands[1], TFmode)"
5201 [(set (match_dup 0) (match_dup 2))
5202 (set (match_dup 1) (match_dup 3))]
5204 alpha_split_tfmode_pair (operands);
5205 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5208 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5209 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5213 (define_expand "movsf"
5214 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5215 (match_operand:SF 1 "general_operand" ""))]
5218 if (GET_CODE (operands[0]) == MEM
5219 && ! reg_or_fp0_operand (operands[1], SFmode))
5220 operands[1] = force_reg (SFmode, operands[1]);
5223 (define_expand "movdf"
5224 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5225 (match_operand:DF 1 "general_operand" ""))]
5228 if (GET_CODE (operands[0]) == MEM
5229 && ! reg_or_fp0_operand (operands[1], DFmode))
5230 operands[1] = force_reg (DFmode, operands[1]);
5233 (define_expand "movtf"
5234 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5235 (match_operand:TF 1 "general_operand" ""))]
5238 if (GET_CODE (operands[0]) == MEM
5239 && ! reg_or_fp0_operand (operands[1], TFmode))
5240 operands[1] = force_reg (TFmode, operands[1]);
5243 (define_insn "*movsi_nofix"
5244 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5245 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5246 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5247 && (register_operand (operands[0], SImode)
5248 || reg_or_0_operand (operands[1], SImode))"
5258 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5260 (define_insn "*movsi_fix"
5261 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5262 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5263 "TARGET_ABI_OSF && TARGET_FIX
5264 && (register_operand (operands[0], SImode)
5265 || reg_or_0_operand (operands[1], SImode))"
5277 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5279 (define_insn "*movsi_nt_vms_nofix"
5280 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5281 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5282 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5284 && (register_operand (operands[0], SImode)
5285 || reg_or_0_operand (operands[1], SImode))"
5296 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5298 (define_insn "*movsi_nt_vms_fix"
5299 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5300 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5301 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5303 && (register_operand (operands[0], SImode)
5304 || reg_or_0_operand (operands[1], SImode))"
5317 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5319 (define_insn "*movhi_nobwx"
5320 [(set (match_operand:HI 0 "register_operand" "=r,r")
5321 (match_operand:HI 1 "input_operand" "rJ,n"))]
5323 && (register_operand (operands[0], HImode)
5324 || register_operand (operands[1], HImode))"
5328 [(set_attr "type" "ilog,iadd")])
5330 (define_insn "*movhi_bwx"
5331 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5332 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5334 && (register_operand (operands[0], HImode)
5335 || reg_or_0_operand (operands[1], HImode))"
5341 [(set_attr "type" "ilog,iadd,ild,ist")])
5343 (define_insn "*movqi_nobwx"
5344 [(set (match_operand:QI 0 "register_operand" "=r,r")
5345 (match_operand:QI 1 "input_operand" "rJ,n"))]
5347 && (register_operand (operands[0], QImode)
5348 || register_operand (operands[1], QImode))"
5352 [(set_attr "type" "ilog,iadd")])
5354 (define_insn "*movqi_bwx"
5355 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5356 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5358 && (register_operand (operands[0], QImode)
5359 || reg_or_0_operand (operands[1], QImode))"
5365 [(set_attr "type" "ilog,iadd,ild,ist")])
5367 ;; We do two major things here: handle mem->mem and construct long
5370 (define_expand "movsi"
5371 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5372 (match_operand:SI 1 "general_operand" ""))]
5375 if (alpha_expand_mov (SImode, operands))
5379 ;; Split a load of a large constant into the appropriate two-insn
5383 [(set (match_operand:SI 0 "register_operand" "")
5384 (match_operand:SI 1 "const_int_operand" ""))]
5385 "! add_operand (operands[1], SImode)"
5386 [(set (match_dup 0) (match_dup 2))
5387 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5390 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5392 if (tem == operands[0])
5398 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5399 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5400 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5401 ;; notes and update LABEL_NUSES because this is not done automatically.
5402 ;; Labels may be incorrectly deleted if we don't do this.
5404 ;; Describing what the individual instructions do correctly is too complicated
5405 ;; so use UNSPECs for each of the three parts of an address.
5408 [(set (match_operand:DI 0 "register_operand" "")
5409 (match_operand:DI 1 "symbolic_operand" ""))]
5410 "TARGET_ABI_UNICOSMK && reload_completed"
5413 rtx insn1, insn2, insn3;
5415 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5416 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5417 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5418 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5419 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5421 if (GET_CODE (operands[1]) == LABEL_REF)
5425 label = XEXP (operands[1], 0);
5426 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5428 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5430 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5432 LABEL_NUSES (label) += 3;
5437 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5439 (define_insn "umk_laum"
5440 [(set (match_operand:DI 0 "register_operand" "=r")
5441 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5443 "TARGET_ABI_UNICOSMK"
5445 [(set_attr "type" "iadd")])
5447 (define_insn "umk_lalm"
5448 [(set (match_operand:DI 0 "register_operand" "=r")
5449 (plus:DI (match_operand:DI 1 "register_operand" "r")
5450 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5452 "TARGET_ABI_UNICOSMK"
5454 [(set_attr "type" "iadd")])
5456 (define_insn "umk_lal"
5457 [(set (match_operand:DI 0 "register_operand" "=r")
5458 (plus:DI (match_operand:DI 1 "register_operand" "r")
5459 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5461 "TARGET_ABI_UNICOSMK"
5463 [(set_attr "type" "iadd")])
5465 ;; Add a new call information word to the current function's list of CIWs
5466 ;; and load its index into $25. Doing it here ensures that the CIW will be
5467 ;; associated with the correct function even in the presence of inlining.
5469 (define_insn "*umk_load_ciw"
5471 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5472 "TARGET_ABI_UNICOSMK"
5474 operands[0] = unicosmk_add_call_info_word (operands[0]);
5475 return "lda $25,%0";
5477 [(set_attr "type" "iadd")])
5479 (define_insn "*movdi_er_low_l"
5480 [(set (match_operand:DI 0 "register_operand" "=r")
5481 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5482 (match_operand:DI 2 "local_symbolic_operand" "")))]
5483 "TARGET_EXPLICIT_RELOCS"
5485 if (true_regnum (operands[1]) == 29)
5486 return "lda %0,%2(%1)\t\t!gprel";
5488 return "lda %0,%2(%1)\t\t!gprellow";
5492 [(set (match_operand:DI 0 "register_operand" "")
5493 (match_operand:DI 1 "small_symbolic_operand" ""))]
5494 "TARGET_EXPLICIT_RELOCS && reload_completed"
5496 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5497 "operands[2] = pic_offset_table_rtx;")
5500 [(set (match_operand:DI 0 "register_operand" "")
5501 (match_operand:DI 1 "local_symbolic_operand" ""))]
5502 "TARGET_EXPLICIT_RELOCS && reload_completed"
5504 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5506 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5507 "operands[2] = pic_offset_table_rtx;")
5510 [(match_operand 0 "some_small_symbolic_operand" "")]
5511 "TARGET_EXPLICIT_RELOCS && reload_completed"
5513 "operands[0] = split_small_symbolic_operand (operands[0]);")
5515 (define_insn "movdi_er_high_g"
5516 [(set (match_operand:DI 0 "register_operand" "=r")
5517 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5518 (match_operand:DI 2 "global_symbolic_operand" "")
5519 (match_operand 3 "const_int_operand" "")]
5521 "TARGET_EXPLICIT_RELOCS"
5523 if (INTVAL (operands[3]) == 0)
5524 return "ldq %0,%2(%1)\t\t!literal";
5526 return "ldq %0,%2(%1)\t\t!literal!%3";
5528 [(set_attr "type" "ldsym")])
5531 [(set (match_operand:DI 0 "register_operand" "")
5532 (match_operand:DI 1 "global_symbolic_operand" ""))]
5533 "TARGET_EXPLICIT_RELOCS && reload_completed"
5535 (unspec:DI [(match_dup 2)
5537 (const_int 0)] UNSPEC_LITERAL))]
5538 "operands[2] = pic_offset_table_rtx;")
5540 (define_insn "*movdi_er_nofix"
5541 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5542 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5543 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5544 && (register_operand (operands[0], DImode)
5545 || reg_or_0_operand (operands[1], DImode))"
5557 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5559 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5560 ;; have been split up by the rules above but we shouldn't reject the
5561 ;; possibility of them getting through.
5563 (define_insn "*movdi_nofix"
5564 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5565 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5567 && (register_operand (operands[0], DImode)
5568 || reg_or_0_operand (operands[1], DImode))"
5573 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5580 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5581 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5583 (define_insn "*movdi_er_fix"
5584 [(set (match_operand:DI 0 "nonimmediate_operand"
5585 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5586 (match_operand:DI 1 "input_operand"
5587 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5588 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5589 && (register_operand (operands[0], DImode)
5590 || reg_or_0_operand (operands[1], DImode))"
5604 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5606 (define_insn "*movdi_fix"
5607 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5608 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5609 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5610 && (register_operand (operands[0], DImode)
5611 || reg_or_0_operand (operands[1], DImode))"
5624 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5626 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5627 ;; often appears dead to the life analysis code, at which point we
5628 ;; abort for emitting dead prologue instructions. Force this live.
5630 (define_insn "force_movdi"
5631 [(set (match_operand:DI 0 "register_operand" "=r")
5632 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5633 UNSPECV_FORCE_MOV))]
5636 [(set_attr "type" "ilog")])
5638 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5639 ;; memory, and construct long 32-bit constants.
5641 (define_expand "movdi"
5642 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5643 (match_operand:DI 1 "general_operand" ""))]
5646 if (alpha_expand_mov (DImode, operands))
5650 ;; Split a load of a large constant into the appropriate two-insn
5654 [(set (match_operand:DI 0 "register_operand" "")
5655 (match_operand:DI 1 "const_int_operand" ""))]
5656 "! add_operand (operands[1], DImode)"
5657 [(set (match_dup 0) (match_dup 2))
5658 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5661 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5663 if (tem == operands[0])
5669 ;; These are the partial-word cases.
5671 ;; First we have the code to load an aligned word. Operand 0 is the register
5672 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5673 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5674 ;; number of bits within the word that the value is. Operand 3 is an SImode
5675 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5676 ;; same register. It is allowed to conflict with operand 1 as well.
5678 (define_expand "aligned_loadqi"
5679 [(set (match_operand:SI 3 "register_operand" "")
5680 (match_operand:SI 1 "memory_operand" ""))
5681 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5682 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5684 (match_operand:DI 2 "const_int_operand" "")))]
5689 (define_expand "aligned_loadhi"
5690 [(set (match_operand:SI 3 "register_operand" "")
5691 (match_operand:SI 1 "memory_operand" ""))
5692 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5693 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5695 (match_operand:DI 2 "const_int_operand" "")))]
5700 ;; Similar for unaligned loads, where we use the sequence from the
5701 ;; Alpha Architecture manual. We have to distinguish between little-endian
5702 ;; and big-endian systems as the sequences are different.
5704 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5705 ;; operand 3 can overlap the input and output registers.
5707 (define_expand "unaligned_loadqi"
5708 [(use (match_operand:QI 0 "register_operand" ""))
5709 (use (match_operand:DI 1 "address_operand" ""))
5710 (use (match_operand:DI 2 "register_operand" ""))
5711 (use (match_operand:DI 3 "register_operand" ""))]
5714 if (WORDS_BIG_ENDIAN)
5715 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5716 operands[2], operands[3]));
5718 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5719 operands[2], operands[3]));
5723 (define_expand "unaligned_loadqi_le"
5724 [(set (match_operand:DI 2 "register_operand" "")
5725 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5727 (set (match_operand:DI 3 "register_operand" "")
5729 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5730 (zero_extract:DI (match_dup 2)
5732 (ashift:DI (match_dup 3) (const_int 3))))]
5733 "! WORDS_BIG_ENDIAN"
5736 (define_expand "unaligned_loadqi_be"
5737 [(set (match_operand:DI 2 "register_operand" "")
5738 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5740 (set (match_operand:DI 3 "register_operand" "")
5742 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5743 (zero_extract:DI (match_dup 2)
5747 (ashift:DI (match_dup 3) (const_int 3)))))]
5751 (define_expand "unaligned_loadhi"
5752 [(use (match_operand:QI 0 "register_operand" ""))
5753 (use (match_operand:DI 1 "address_operand" ""))
5754 (use (match_operand:DI 2 "register_operand" ""))
5755 (use (match_operand:DI 3 "register_operand" ""))]
5758 if (WORDS_BIG_ENDIAN)
5759 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5760 operands[2], operands[3]));
5762 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5763 operands[2], operands[3]));
5767 (define_expand "unaligned_loadhi_le"
5768 [(set (match_operand:DI 2 "register_operand" "")
5769 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5771 (set (match_operand:DI 3 "register_operand" "")
5773 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5774 (zero_extract:DI (match_dup 2)
5776 (ashift:DI (match_dup 3) (const_int 3))))]
5777 "! WORDS_BIG_ENDIAN"
5780 (define_expand "unaligned_loadhi_be"
5781 [(set (match_operand:DI 2 "register_operand" "")
5782 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5784 (set (match_operand:DI 3 "register_operand" "")
5785 (plus:DI (match_dup 1) (const_int 1)))
5786 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5787 (zero_extract:DI (match_dup 2)
5791 (ashift:DI (match_dup 3) (const_int 3)))))]
5795 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5796 ;; aligned SImode MEM. Operand 1 is the register containing the
5797 ;; byte or word to store. Operand 2 is the number of bits within the word that
5798 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5800 (define_expand "aligned_store"
5801 [(set (match_operand:SI 3 "register_operand" "")
5802 (match_operand:SI 0 "memory_operand" ""))
5803 (set (subreg:DI (match_dup 3) 0)
5804 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5805 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5806 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5807 (match_operand:DI 2 "const_int_operand" "")))
5808 (set (subreg:DI (match_dup 4) 0)
5809 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5810 (set (match_dup 0) (match_dup 4))]
5813 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5814 << INTVAL (operands[2])));
5817 ;; For the unaligned byte and halfword cases, we use code similar to that
5818 ;; in the ;; Architecture book, but reordered to lower the number of registers
5819 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5820 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5821 ;; be the same temporary, if desired. If the address is in a register,
5822 ;; operand 2 can be that register.
5824 (define_expand "unaligned_storeqi"
5825 [(use (match_operand:DI 0 "address_operand" ""))
5826 (use (match_operand:QI 1 "register_operand" ""))
5827 (use (match_operand:DI 2 "register_operand" ""))
5828 (use (match_operand:DI 3 "register_operand" ""))
5829 (use (match_operand:DI 4 "register_operand" ""))]
5832 if (WORDS_BIG_ENDIAN)
5833 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5834 operands[2], operands[3],
5837 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5838 operands[2], operands[3],
5843 (define_expand "unaligned_storeqi_le"
5844 [(set (match_operand:DI 3 "register_operand" "")
5845 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5847 (set (match_operand:DI 2 "register_operand" "")
5850 (and:DI (not:DI (ashift:DI (const_int 255)
5851 (ashift:DI (match_dup 2) (const_int 3))))
5853 (set (match_operand:DI 4 "register_operand" "")
5854 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5855 (ashift:DI (match_dup 2) (const_int 3))))
5856 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5857 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5859 "! WORDS_BIG_ENDIAN"
5862 (define_expand "unaligned_storeqi_be"
5863 [(set (match_operand:DI 3 "register_operand" "")
5864 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5866 (set (match_operand:DI 2 "register_operand" "")
5869 (and:DI (not:DI (ashift:DI (const_int 255)
5870 (minus:DI (const_int 56)
5871 (ashift:DI (match_dup 2) (const_int 3)))))
5873 (set (match_operand:DI 4 "register_operand" "")
5874 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5875 (minus:DI (const_int 56)
5876 (ashift:DI (match_dup 2) (const_int 3)))))
5877 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5878 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5883 (define_expand "unaligned_storehi"
5884 [(use (match_operand:DI 0 "address_operand" ""))
5885 (use (match_operand:HI 1 "register_operand" ""))
5886 (use (match_operand:DI 2 "register_operand" ""))
5887 (use (match_operand:DI 3 "register_operand" ""))
5888 (use (match_operand:DI 4 "register_operand" ""))]
5891 if (WORDS_BIG_ENDIAN)
5892 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5893 operands[2], operands[3],
5896 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5897 operands[2], operands[3],
5902 (define_expand "unaligned_storehi_le"
5903 [(set (match_operand:DI 3 "register_operand" "")
5904 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5906 (set (match_operand:DI 2 "register_operand" "")
5909 (and:DI (not:DI (ashift:DI (const_int 65535)
5910 (ashift:DI (match_dup 2) (const_int 3))))
5912 (set (match_operand:DI 4 "register_operand" "")
5913 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5914 (ashift:DI (match_dup 2) (const_int 3))))
5915 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5916 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5918 "! WORDS_BIG_ENDIAN"
5921 (define_expand "unaligned_storehi_be"
5922 [(set (match_operand:DI 3 "register_operand" "")
5923 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5925 (set (match_operand:DI 2 "register_operand" "")
5926 (plus:DI (match_dup 0) (const_int 1)))
5928 (and:DI (not:DI (ashift:DI
5930 (minus:DI (const_int 56)
5931 (ashift:DI (match_dup 2) (const_int 3)))))
5933 (set (match_operand:DI 4 "register_operand" "")
5934 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5935 (minus:DI (const_int 56)
5936 (ashift:DI (match_dup 2) (const_int 3)))))
5937 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5938 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5943 ;; Here are the define_expand's for QI and HI moves that use the above
5944 ;; patterns. We have the normal sets, plus the ones that need scratch
5945 ;; registers for reload.
5947 (define_expand "movqi"
5948 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5949 (match_operand:QI 1 "general_operand" ""))]
5953 ? alpha_expand_mov (QImode, operands)
5954 : alpha_expand_mov_nobwx (QImode, operands))
5958 (define_expand "movhi"
5959 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5960 (match_operand:HI 1 "general_operand" ""))]
5964 ? alpha_expand_mov (HImode, operands)
5965 : alpha_expand_mov_nobwx (HImode, operands))
5969 ;; Here are the versions for reload. Note that in the unaligned cases
5970 ;; we know that the operand must not be a pseudo-register because stack
5971 ;; slots are always aligned references.
5973 (define_expand "reload_inqi"
5974 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5975 (match_operand:QI 1 "any_memory_operand" "m")
5976 (match_operand:TI 2 "register_operand" "=&r")])]
5981 if (GET_CODE (operands[1]) != MEM)
5984 if (aligned_memory_operand (operands[1], QImode))
5986 seq = gen_reload_inqi_help (operands[0], operands[1],
5987 gen_rtx_REG (SImode, REGNO (operands[2])));
5993 /* It is possible that one of the registers we got for operands[2]
5994 might coincide with that of operands[0] (which is why we made
5995 it TImode). Pick the other one to use as our scratch. */
5996 if (REGNO (operands[0]) == REGNO (operands[2]))
5997 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5999 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6001 addr = get_unaligned_address (operands[1], 0);
6002 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
6003 gen_rtx_REG (DImode, REGNO (operands[0])));
6004 alpha_set_memflags (seq, operands[1]);
6010 (define_expand "reload_inhi"
6011 [(parallel [(match_operand:HI 0 "register_operand" "=r")
6012 (match_operand:HI 1 "any_memory_operand" "m")
6013 (match_operand:TI 2 "register_operand" "=&r")])]
6018 if (GET_CODE (operands[1]) != MEM)
6021 if (aligned_memory_operand (operands[1], HImode))
6023 seq = gen_reload_inhi_help (operands[0], operands[1],
6024 gen_rtx_REG (SImode, REGNO (operands[2])));
6030 /* It is possible that one of the registers we got for operands[2]
6031 might coincide with that of operands[0] (which is why we made
6032 it TImode). Pick the other one to use as our scratch. */
6033 if (REGNO (operands[0]) == REGNO (operands[2]))
6034 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6036 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6038 addr = get_unaligned_address (operands[1], 0);
6039 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
6040 gen_rtx_REG (DImode, REGNO (operands[0])));
6041 alpha_set_memflags (seq, operands[1]);
6047 (define_expand "reload_outqi"
6048 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6049 (match_operand:QI 1 "register_operand" "r")
6050 (match_operand:TI 2 "register_operand" "=&r")])]
6053 if (GET_CODE (operands[0]) != MEM)
6056 if (aligned_memory_operand (operands[0], QImode))
6058 emit_insn (gen_reload_outqi_help
6059 (operands[0], operands[1],
6060 gen_rtx_REG (SImode, REGNO (operands[2])),
6061 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6065 rtx addr = get_unaligned_address (operands[0], 0);
6066 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6067 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6068 rtx scratch3 = scratch1;
6071 if (GET_CODE (addr) == REG)
6074 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6075 scratch2, scratch3);
6076 alpha_set_memflags (seq, operands[0]);
6082 (define_expand "reload_outhi"
6083 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6084 (match_operand:HI 1 "register_operand" "r")
6085 (match_operand:TI 2 "register_operand" "=&r")])]
6088 if (GET_CODE (operands[0]) != MEM)
6091 if (aligned_memory_operand (operands[0], HImode))
6093 emit_insn (gen_reload_outhi_help
6094 (operands[0], operands[1],
6095 gen_rtx_REG (SImode, REGNO (operands[2])),
6096 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6100 rtx addr = get_unaligned_address (operands[0], 0);
6101 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6102 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6103 rtx scratch3 = scratch1;
6106 if (GET_CODE (addr) == REG)
6109 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6110 scratch2, scratch3);
6111 alpha_set_memflags (seq, operands[0]);
6117 ;; Helpers for the above. The way reload is structured, we can't
6118 ;; always get a proper address for a stack slot during reload_foo
6119 ;; expansion, so we must delay our address manipulations until after.
6121 (define_insn "reload_inqi_help"
6122 [(set (match_operand:QI 0 "register_operand" "=r")
6123 (match_operand:QI 1 "memory_operand" "m"))
6124 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6125 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6128 (define_insn "reload_inhi_help"
6129 [(set (match_operand:HI 0 "register_operand" "=r")
6130 (match_operand:HI 1 "memory_operand" "m"))
6131 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6132 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6135 (define_insn "reload_outqi_help"
6136 [(set (match_operand:QI 0 "memory_operand" "=m")
6137 (match_operand:QI 1 "register_operand" "r"))
6138 (clobber (match_operand:SI 2 "register_operand" "=r"))
6139 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6140 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6143 (define_insn "reload_outhi_help"
6144 [(set (match_operand:HI 0 "memory_operand" "=m")
6145 (match_operand:HI 1 "register_operand" "r"))
6146 (clobber (match_operand:SI 2 "register_operand" "=r"))
6147 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6148 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6152 [(set (match_operand:QI 0 "register_operand" "")
6153 (match_operand:QI 1 "memory_operand" ""))
6154 (clobber (match_operand:SI 2 "register_operand" ""))]
6155 "! TARGET_BWX && reload_completed"
6158 rtx aligned_mem, bitnum;
6159 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6161 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6167 [(set (match_operand:HI 0 "register_operand" "")
6168 (match_operand:HI 1 "memory_operand" ""))
6169 (clobber (match_operand:SI 2 "register_operand" ""))]
6170 "! TARGET_BWX && reload_completed"
6173 rtx aligned_mem, bitnum;
6174 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6176 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6182 [(set (match_operand:QI 0 "memory_operand" "")
6183 (match_operand:QI 1 "register_operand" ""))
6184 (clobber (match_operand:SI 2 "register_operand" ""))
6185 (clobber (match_operand:SI 3 "register_operand" ""))]
6186 "! TARGET_BWX && reload_completed"
6189 rtx aligned_mem, bitnum;
6190 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6191 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6192 operands[2], operands[3]));
6197 [(set (match_operand:HI 0 "memory_operand" "")
6198 (match_operand:HI 1 "register_operand" ""))
6199 (clobber (match_operand:SI 2 "register_operand" ""))
6200 (clobber (match_operand:SI 3 "register_operand" ""))]
6201 "! TARGET_BWX && reload_completed"
6204 rtx aligned_mem, bitnum;
6205 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6206 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6207 operands[2], operands[3]));
6211 ;; Bit field extract patterns which use ext[wlq][lh]
6213 (define_expand "extv"
6214 [(set (match_operand:DI 0 "register_operand" "")
6215 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6216 (match_operand:DI 2 "immediate_operand" "")
6217 (match_operand:DI 3 "immediate_operand" "")))]
6222 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6223 if (INTVAL (operands[3]) % 8 != 0
6224 || (INTVAL (operands[2]) != 16
6225 && INTVAL (operands[2]) != 32
6226 && INTVAL (operands[2]) != 64))
6229 /* From mips.md: extract_bit_field doesn't verify that our source
6230 matches the predicate, so we force it to be a MEM here. */
6231 if (GET_CODE (operands[1]) != MEM)
6234 /* The bit number is relative to the mode of operand 1 which is
6235 usually QImode (this might actually be a bug in expmed.c). Note
6236 that the bit number is negative in big-endian mode in this case.
6237 We have to convert that to the offset. */
6238 if (WORDS_BIG_ENDIAN)
6239 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6240 - INTVAL (operands[2]) - INTVAL (operands[3]);
6242 ofs = INTVAL (operands[3]);
6246 alpha_expand_unaligned_load (operands[0], operands[1],
6247 INTVAL (operands[2]) / 8,
6252 (define_expand "extzv"
6253 [(set (match_operand:DI 0 "register_operand" "")
6254 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6255 (match_operand:DI 2 "immediate_operand" "")
6256 (match_operand:DI 3 "immediate_operand" "")))]
6259 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6260 if (INTVAL (operands[3]) % 8 != 0
6261 || (INTVAL (operands[2]) != 8
6262 && INTVAL (operands[2]) != 16
6263 && INTVAL (operands[2]) != 32
6264 && INTVAL (operands[2]) != 64))
6267 if (GET_CODE (operands[1]) == MEM)
6271 /* Fail 8 bit fields, falling back on a simple byte load. */
6272 if (INTVAL (operands[2]) == 8)
6275 /* The bit number is relative to the mode of operand 1 which is
6276 usually QImode (this might actually be a bug in expmed.c). Note
6277 that the bit number is negative in big-endian mode in this case.
6278 We have to convert that to the offset. */
6279 if (WORDS_BIG_ENDIAN)
6280 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6281 - INTVAL (operands[2]) - INTVAL (operands[3]);
6283 ofs = INTVAL (operands[3]);
6287 alpha_expand_unaligned_load (operands[0], operands[1],
6288 INTVAL (operands[2]) / 8,
6294 (define_expand "insv"
6295 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6296 (match_operand:DI 1 "immediate_operand" "")
6297 (match_operand:DI 2 "immediate_operand" ""))
6298 (match_operand:DI 3 "register_operand" ""))]
6303 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6304 if (INTVAL (operands[2]) % 8 != 0
6305 || (INTVAL (operands[1]) != 16
6306 && INTVAL (operands[1]) != 32
6307 && INTVAL (operands[1]) != 64))
6310 /* From mips.md: store_bit_field doesn't verify that our source
6311 matches the predicate, so we force it to be a MEM here. */
6312 if (GET_CODE (operands[0]) != MEM)
6315 /* The bit number is relative to the mode of operand 1 which is
6316 usually QImode (this might actually be a bug in expmed.c). Note
6317 that the bit number is negative in big-endian mode in this case.
6318 We have to convert that to the offset. */
6319 if (WORDS_BIG_ENDIAN)
6320 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6321 - INTVAL (operands[1]) - INTVAL (operands[2]);
6323 ofs = INTVAL (operands[2]);
6327 alpha_expand_unaligned_store (operands[0], operands[3],
6328 INTVAL (operands[1]) / 8, ofs);
6332 ;; Block move/clear, see alpha.c for more details.
6333 ;; Argument 0 is the destination
6334 ;; Argument 1 is the source
6335 ;; Argument 2 is the length
6336 ;; Argument 3 is the alignment
6338 (define_expand "movstrqi"
6339 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6340 (match_operand:BLK 1 "memory_operand" ""))
6341 (use (match_operand:DI 2 "immediate_operand" ""))
6342 (use (match_operand:DI 3 "immediate_operand" ""))])]
6345 if (alpha_expand_block_move (operands))
6351 (define_expand "clrstrqi"
6352 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6354 (use (match_operand:DI 1 "immediate_operand" ""))
6355 (use (match_operand:DI 2 "immediate_operand" ""))])]
6358 if (alpha_expand_block_clear (operands))
6364 ;; Subroutine of stack space allocation. Perform a stack probe.
6365 (define_expand "probe_stack"
6366 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6369 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6370 INTVAL (operands[0])));
6371 MEM_VOLATILE_P (operands[1]) = 1;
6373 operands[0] = const0_rtx;
6376 ;; This is how we allocate stack space. If we are allocating a
6377 ;; constant amount of space and we know it is less than 4096
6378 ;; bytes, we need do nothing.
6380 ;; If it is more than 4096 bytes, we need to probe the stack
6382 (define_expand "allocate_stack"
6384 (plus:DI (reg:DI 30)
6385 (match_operand:DI 1 "reg_or_cint_operand" "")))
6386 (set (match_operand:DI 0 "register_operand" "=r")
6390 if (GET_CODE (operands[1]) == CONST_INT
6391 && INTVAL (operands[1]) < 32768)
6393 if (INTVAL (operands[1]) >= 4096)
6395 /* We do this the same way as in the prologue and generate explicit
6396 probes. Then we update the stack by the constant. */
6400 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6401 while (probed + 8192 < INTVAL (operands[1]))
6402 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6404 if (probed + 4096 < INTVAL (operands[1]))
6405 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6408 operands[1] = GEN_INT (- INTVAL (operands[1]));
6409 operands[2] = virtual_stack_dynamic_rtx;
6414 rtx loop_label = gen_label_rtx ();
6415 rtx want = gen_reg_rtx (Pmode);
6416 rtx tmp = gen_reg_rtx (Pmode);
6419 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6420 force_reg (Pmode, operands[1])));
6421 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6423 if (GET_CODE (operands[1]) != CONST_INT)
6425 out_label = gen_label_rtx ();
6426 emit_insn (gen_cmpdi (want, tmp));
6427 emit_jump_insn (gen_bgeu (out_label));
6430 emit_label (loop_label);
6431 memref = gen_rtx_MEM (DImode, tmp);
6432 MEM_VOLATILE_P (memref) = 1;
6433 emit_move_insn (memref, const0_rtx);
6434 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6435 emit_insn (gen_cmpdi (tmp, want));
6436 emit_jump_insn (gen_bgtu (loop_label));
6438 memref = gen_rtx_MEM (DImode, want);
6439 MEM_VOLATILE_P (memref) = 1;
6440 emit_move_insn (memref, const0_rtx);
6443 emit_label (out_label);
6445 emit_move_insn (stack_pointer_rtx, want);
6446 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6451 ;; This is used by alpha_expand_prolog to do the same thing as above,
6452 ;; except we cannot at that time generate new basic blocks, so we hide
6453 ;; the loop in this one insn.
6455 (define_insn "prologue_stack_probe_loop"
6456 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6457 (match_operand:DI 1 "register_operand" "r")]
6461 operands[2] = gen_label_rtx ();
6462 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6463 CODE_LABEL_NUMBER (operands[2]));
6465 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6467 [(set_attr "length" "16")
6468 (set_attr "type" "multi")])
6470 (define_expand "prologue"
6471 [(clobber (const_int 0))]
6474 alpha_expand_prologue ();
6478 ;; These take care of emitting the ldgp insn in the prologue. This will be
6479 ;; an lda/ldah pair and we want to align them properly. So we have two
6480 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6481 ;; and the second of which emits nothing. However, both are marked as type
6482 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6485 (define_expand "prologue_ldgp"
6487 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6489 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6492 operands[0] = pic_offset_table_rtx;
6493 operands[1] = gen_rtx_REG (Pmode, 27);
6494 operands[2] = (TARGET_EXPLICIT_RELOCS
6495 ? GEN_INT (alpha_next_sequence_number++)
6499 (define_insn "*ldgp_er_1"
6500 [(set (match_operand:DI 0 "register_operand" "=r")
6501 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6502 (match_operand 2 "const_int_operand" "")]
6504 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6505 "ldah %0,0(%1)\t\t!gpdisp!%2")
6507 (define_insn "*ldgp_er_2"
6508 [(set (match_operand:DI 0 "register_operand" "=r")
6509 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6510 (match_operand 2 "const_int_operand" "")]
6512 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6513 "lda %0,0(%1)\t\t!gpdisp!%2")
6515 (define_insn "*prologue_ldgp_er_2"
6516 [(set (match_operand:DI 0 "register_operand" "=r")
6517 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6518 (match_operand 2 "const_int_operand" "")]
6520 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6521 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6523 (define_insn "*prologue_ldgp_1"
6524 [(set (match_operand:DI 0 "register_operand" "=r")
6525 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6526 (match_operand 2 "const_int_operand" "")]
6529 "ldgp %0,0(%1)\n$%~..ng:")
6531 (define_insn "*prologue_ldgp_2"
6532 [(set (match_operand:DI 0 "register_operand" "=r")
6533 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6534 (match_operand 2 "const_int_operand" "")]
6539 ;; The _mcount profiling hook has special calling conventions, and
6540 ;; does not clobber all the registers that a normal call would. So
6541 ;; hide the fact this is a call at all.
6543 (define_insn "prologue_mcount"
6544 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6547 if (TARGET_EXPLICIT_RELOCS)
6548 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6549 cannot be called via the PLT. */
6550 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6552 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6554 [(set_attr "type" "multi")
6555 (set_attr "length" "8")])
6557 (define_insn "init_fp"
6558 [(set (match_operand:DI 0 "register_operand" "=r")
6559 (match_operand:DI 1 "register_operand" "r"))
6560 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6564 (define_expand "epilogue"
6568 alpha_expand_epilogue ();
6571 (define_expand "sibcall_epilogue"
6575 alpha_expand_epilogue ();
6579 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6580 ;; the frame size into a register. We use this pattern to ensure
6581 ;; we get lda instead of addq.
6582 (define_insn "nt_lda"
6583 [(set (match_operand:DI 0 "register_operand" "=r")
6584 (unspec:DI [(match_dup 0)
6585 (match_operand:DI 1 "const_int_operand" "n")]
6590 (define_expand "builtin_longjmp"
6591 [(use (match_operand:DI 0 "register_operand" "r"))]
6594 /* The elements of the buffer are, in order: */
6595 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6596 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6597 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6598 rtx pv = gen_rtx_REG (Pmode, 27);
6600 /* This bit is the same as expand_builtin_longjmp. */
6601 emit_move_insn (hard_frame_pointer_rtx, fp);
6602 emit_move_insn (pv, lab);
6603 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6604 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6605 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6607 /* Load the label we are jumping through into $27 so that we know
6608 where to look for it when we get back to setjmp's function for
6609 restoring the gp. */
6610 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6615 ;; This is effectively a copy of indirect_jump, but constrained such
6616 ;; that register renaming cannot foil our cunning plan with $27.
6617 (define_insn "builtin_longjmp_internal"
6619 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6623 [(set_attr "type" "ibr")])
6625 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6626 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6627 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6628 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6630 (define_insn "*builtin_setjmp_receiver_er_1"
6631 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6632 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6633 "br $27,$LSJ%=\n$LSJ%=:"
6634 [(set_attr "type" "ibr")])
6637 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6638 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6639 && prev_nonnote_insn (insn) == operands[0]"
6643 (define_insn "*builtin_setjmp_receiver_1"
6644 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6646 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6647 [(set_attr "length" "12")
6648 (set_attr "type" "multi")])
6650 (define_expand "builtin_setjmp_receiver_er"
6651 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6653 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6655 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6658 operands[1] = pic_offset_table_rtx;
6659 operands[2] = gen_rtx_REG (Pmode, 27);
6660 operands[3] = GEN_INT (alpha_next_sequence_number++);
6663 (define_expand "builtin_setjmp_receiver"
6664 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6667 if (TARGET_EXPLICIT_RELOCS)
6669 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6674 (define_expand "exception_receiver_er"
6676 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6678 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6681 operands[0] = pic_offset_table_rtx;
6682 operands[1] = gen_rtx_REG (Pmode, 26);
6683 operands[2] = GEN_INT (alpha_next_sequence_number++);
6686 (define_expand "exception_receiver"
6687 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6690 if (TARGET_LD_BUGGY_LDGP)
6691 operands[0] = alpha_gp_save_rtx ();
6692 else if (TARGET_EXPLICIT_RELOCS)
6694 emit_insn (gen_exception_receiver_er ());
6698 operands[0] = const0_rtx;
6701 (define_insn "*exception_receiver_1"
6702 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6703 "! TARGET_LD_BUGGY_LDGP"
6705 [(set_attr "length" "8")
6706 (set_attr "type" "multi")])
6708 (define_insn "*exception_receiver_2"
6709 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6710 "TARGET_LD_BUGGY_LDGP"
6712 [(set_attr "type" "ild")])
6714 (define_expand "nonlocal_goto_receiver"
6715 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6716 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6717 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6719 "TARGET_ABI_OPEN_VMS"
6722 (define_insn "arg_home"
6723 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6738 (clobber (mem:BLK (const_int 0)))
6739 (clobber (reg:DI 24))
6740 (clobber (reg:DI 25))
6741 (clobber (reg:DI 0))]
6742 "TARGET_ABI_OPEN_VMS"
6743 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6744 [(set_attr "length" "16")
6745 (set_attr "type" "multi")])
6747 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6749 (define_expand "umk_mismatch_args"
6750 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6751 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6752 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6753 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6756 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6757 "TARGET_ABI_UNICOSMK"
6759 operands[1] = gen_reg_rtx (DImode);
6760 operands[2] = gen_reg_rtx (DImode);
6761 operands[3] = gen_reg_rtx (DImode);
6764 (define_insn "arg_home_umk"
6765 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6780 (clobber (mem:BLK (const_int 0)))
6782 (clobber (reg:DI 22))
6783 (clobber (reg:DI 23))
6784 (clobber (reg:DI 24))
6785 (clobber (reg:DI 0))
6786 (clobber (reg:DI 1))
6787 (clobber (reg:DI 2))
6788 (clobber (reg:DI 3))
6789 (clobber (reg:DI 4))
6790 (clobber (reg:DI 5))
6791 (clobber (reg:DI 6))
6792 (clobber (reg:DI 7))
6793 (clobber (reg:DI 8))])]
6794 "TARGET_ABI_UNICOSMK"
6795 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6796 [(set_attr "length" "16")
6797 (set_attr "type" "multi")])
6801 ;; On EV4, these instructions are nops -- no load occurs.
6803 ;; On EV5, these instructions act as a normal load, and thus can trap
6804 ;; if the address is invalid. The OS may (or may not) handle this in
6805 ;; the entMM fault handler and suppress the fault. If so, then this
6806 ;; has the effect of a read prefetch instruction.
6808 ;; On EV6, these become official prefetch instructions.
6810 (define_insn "prefetch"
6811 [(prefetch (match_operand:DI 0 "address_operand" "p")
6812 (match_operand:DI 1 "const_int_operand" "n")
6813 (match_operand:DI 2 "const_int_operand" "n"))]
6814 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6816 /* Interpret "no temporal locality" as this data should be evicted once
6817 it is used. The "evict next" alternatives load the data into the cache
6818 and leave the LRU eviction counter pointing to that block. */
6819 static const char * const alt[2][2] = {
6821 "lds $f31,%a0", /* read, evict next */
6822 "ldl $31,%a0", /* read, evict last */
6825 "ldt $f31,%a0", /* write, evict next */
6826 "ldq $31,%a0", /* write, evict last */
6830 bool write = INTVAL (operands[1]) != 0;
6831 bool lru = INTVAL (operands[2]) != 0;
6833 return alt[write][lru];
6835 [(set_attr "type" "ild")])
6837 ;; Close the trap shadow of preceding instructions. This is generated
6840 (define_insn "trapb"
6841 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6844 [(set_attr "type" "misc")])
6846 ;; No-op instructions used by machine-dependent reorg to preserve
6847 ;; alignment for instruction issue.
6848 ;; The Unicos/Mk assembler does not support these opcodes.
6854 [(set_attr "type" "ilog")])
6859 "cpys $f31,$f31,$f31"
6860 [(set_attr "type" "fcpys")])
6867 ;; On Unicos/Mk we use a macro for aligning code.
6869 (define_insn "realign"
6870 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6874 if (TARGET_ABI_UNICOSMK)
6875 return "gcc@code@align %0";
6877 return ".align %0 #realign";
6880 ;; The call patterns are at the end of the file because their
6881 ;; wildcard operand0 interferes with nice recognition.
6883 (define_insn "*call_value_osf_1_er"
6884 [(set (match_operand 0 "" "")
6885 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6886 (match_operand 2 "" "")))
6888 (clobber (reg:DI 26))]
6889 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6891 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6893 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6894 [(set_attr "type" "jsr")
6895 (set_attr "length" "12,*,16")])
6897 ;; We must use peep2 instead of a split because we need accurate life
6898 ;; information for $gp. Consider the case of { bar(); while (1); }.
6900 [(parallel [(set (match_operand 0 "" "")
6901 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6902 (match_operand 2 "" "")))
6904 (clobber (reg:DI 26))])]
6905 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6906 && ! current_file_function_operand (operands[1], Pmode)
6907 && peep2_regno_dead_p (1, 29)"
6908 [(parallel [(set (match_dup 0)
6909 (call (mem:DI (match_dup 3))
6911 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6912 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6914 (use (match_dup 4))])]
6916 if (CONSTANT_P (operands[1]))
6918 operands[3] = gen_rtx_REG (Pmode, 27);
6919 operands[4] = GEN_INT (alpha_next_sequence_number++);
6920 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6921 operands[1], operands[4]));
6925 operands[3] = operands[1];
6926 operands[1] = const0_rtx;
6927 operands[4] = const0_rtx;
6932 [(parallel [(set (match_operand 0 "" "")
6933 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6934 (match_operand 2 "" "")))
6936 (clobber (reg:DI 26))])]
6937 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6938 && ! current_file_function_operand (operands[1], Pmode)
6939 && ! peep2_regno_dead_p (1, 29)"
6940 [(parallel [(set (match_dup 0)
6941 (call (mem:DI (match_dup 3))
6943 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6944 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6946 (use (match_dup 5))])
6948 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6950 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6952 if (CONSTANT_P (operands[1]))
6954 operands[3] = gen_rtx_REG (Pmode, 27);
6955 operands[5] = GEN_INT (alpha_next_sequence_number++);
6956 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6957 operands[1], operands[5]));
6961 operands[3] = operands[1];
6962 operands[1] = const0_rtx;
6963 operands[5] = const0_rtx;
6965 operands[4] = GEN_INT (alpha_next_sequence_number++);
6968 ;; We add a blockage unspec_volatile to prevent insns from moving down
6969 ;; from above the call to in between the call and the ldah gpdisp.
6970 (define_insn "*call_value_osf_2_er"
6971 [(set (match_operand 0 "" "")
6972 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6973 (match_operand 2 "" "")))
6975 (plus:DI (pc) (const_int 4)))
6976 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6977 (use (match_operand 3 "" ""))
6978 (use (match_operand 4 "const_int_operand" ""))]
6979 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6980 "jsr $26,(%1),%3%J4"
6981 [(set_attr "type" "jsr")])
6983 (define_insn "*call_value_osf_1_noreturn"
6984 [(set (match_operand 0 "" "")
6985 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6986 (match_operand 2 "" "")))
6988 (clobber (reg:DI 26))]
6989 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6990 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6995 [(set_attr "type" "jsr")
6996 (set_attr "length" "*,*,8")])
6998 (define_insn "*call_value_osf_1"
6999 [(set (match_operand 0 "" "")
7000 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7001 (match_operand 2 "" "")))
7003 (clobber (reg:DI 26))]
7004 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7006 jsr $26,($27),0\;ldgp $29,0($26)
7008 jsr $26,%1\;ldgp $29,0($26)"
7009 [(set_attr "type" "jsr")
7010 (set_attr "length" "12,*,16")])
7012 (define_insn "*sibcall_value_osf_1_er"
7013 [(set (match_operand 0 "" "")
7014 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7015 (match_operand 2 "" "")))
7016 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7017 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7020 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7021 [(set_attr "type" "jsr")
7022 (set_attr "length" "*,8")])
7024 (define_insn "*sibcall_value_osf_1"
7025 [(set (match_operand 0 "" "")
7026 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7027 (match_operand 2 "" "")))
7028 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7029 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7032 lda $27,%1\;jmp $31,($27),%1"
7033 [(set_attr "type" "jsr")
7034 (set_attr "length" "*,8")])
7036 (define_insn "*call_value_nt_1"
7037 [(set (match_operand 0 "" "")
7038 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7039 (match_operand 2 "" "")))
7040 (clobber (reg:DI 26))]
7041 "TARGET_ABI_WINDOWS_NT"
7046 [(set_attr "type" "jsr")
7047 (set_attr "length" "*,*,12")])
7049 (define_insn "*call_value_vms_1"
7050 [(set (match_operand 0 "" "")
7051 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7052 (match_operand 2 "" "")))
7053 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
7056 (clobber (reg:DI 27))]
7057 "TARGET_ABI_OPEN_VMS"
7059 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
7060 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
7061 [(set_attr "type" "jsr")
7062 (set_attr "length" "12,16")])
7064 (define_insn "*call_value_umk"
7065 [(set (match_operand 0 "" "")
7066 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
7067 (match_operand 2 "" "")))
7069 (clobber (reg:DI 26))]
7070 "TARGET_ABI_UNICOSMK"
7072 [(set_attr "type" "jsr")])