1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
48 ;; Processor type -- this attribute must exactly match the processor_type
49 ;; enumeration in alpha.h.
51 (define_attr "cpu" "ev4,ev5,ev6"
52 (const (symbol_ref "alpha_cpu")))
54 ;; Define an insn type attribute. This is used in function unit delay
55 ;; computations, among other purposes. For the most part, we use the names
56 ;; defined in the EV4 documentation, but add a few that we have to know about
60 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
61 (const_string "iadd"))
63 ;; Describe a user's asm statement.
64 (define_asm_attributes
65 [(set_attr "type" "multi")])
67 ;; Define the operand size an insn operates on. Used primarily by mul
68 ;; and div operations that have size dependant timings.
70 (define_attr "opsize" "si,di,udi" (const_string "di"))
72 ;; The TRAP_TYPE attribute marks instructions that may generate traps
73 ;; (which are imprecise and may need a trapb if software completion
76 (define_attr "trap" "no,yes" (const_string "no"))
78 ;; The length of an instruction sequence in bytes.
80 (define_attr "length" "" (const_int 4))
82 ;; On EV4 there are two classes of resources to consider: resources needed
83 ;; to issue, and resources needed to execute. IBUS[01] are in the first
84 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
85 ;; (There are a few other register-like resources, but ...)
87 ; First, describe all of the issue constraints with single cycle delays.
88 ; All insns need a bus, but all except loads require one or the other.
89 (define_function_unit "ev4_ibus0" 1 0
90 (and (eq_attr "cpu" "ev4")
91 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
94 (define_function_unit "ev4_ibus1" 1 0
95 (and (eq_attr "cpu" "ev4")
96 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
99 ; Memory delivers its result in three cycles. Actually return one and
100 ; take care of this in adjust_cost, since we want to handle user-defined
102 (define_function_unit "ev4_abox" 1 0
103 (and (eq_attr "cpu" "ev4")
104 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
107 ; Branches have no delay cost, but do tie up the unit for two cycles.
108 (define_function_unit "ev4_bbox" 1 1
109 (and (eq_attr "cpu" "ev4")
110 (eq_attr "type" "ibr,fbr,jsr"))
113 ; Arithmetic insns are normally have their results available after
114 ; two cycles. There are a number of exceptions. They are encoded in
115 ; ADJUST_COST. Some of the other insns have similar exceptions.
116 (define_function_unit "ev4_ebox" 1 0
117 (and (eq_attr "cpu" "ev4")
118 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
121 (define_function_unit "imul" 1 0
122 (and (eq_attr "cpu" "ev4")
123 (and (eq_attr "type" "imul")
124 (eq_attr "opsize" "si")))
127 (define_function_unit "imul" 1 0
128 (and (eq_attr "cpu" "ev4")
129 (and (eq_attr "type" "imul")
130 (eq_attr "opsize" "!si")))
133 (define_function_unit "ev4_fbox" 1 0
134 (and (eq_attr "cpu" "ev4")
135 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
138 (define_function_unit "fdiv" 1 0
139 (and (eq_attr "cpu" "ev4")
140 (and (eq_attr "type" "fdiv")
141 (eq_attr "opsize" "si")))
144 (define_function_unit "fdiv" 1 0
145 (and (eq_attr "cpu" "ev4")
146 (and (eq_attr "type" "fdiv")
147 (eq_attr "opsize" "di")))
150 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
152 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
153 ;; with the combined resource EBOX.
155 (define_function_unit "ev5_ebox" 2 0
156 (and (eq_attr "cpu" "ev5")
157 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
160 ; Memory takes at least 2 clocks. Return one from here and fix up with
161 ; user-defined latencies in adjust_cost.
162 (define_function_unit "ev5_ebox" 2 0
163 (and (eq_attr "cpu" "ev5")
164 (eq_attr "type" "ild,fld,ldsym"))
167 ; Loads can dual issue with one another, but loads and stores do not mix.
168 (define_function_unit "ev5_e0" 1 0
169 (and (eq_attr "cpu" "ev5")
170 (eq_attr "type" "ild,fld,ldsym"))
172 [(eq_attr "type" "ist,fst")])
174 ; Stores, shifts, multiplies can only issue to E0
175 (define_function_unit "ev5_e0" 1 0
176 (and (eq_attr "cpu" "ev5")
177 (eq_attr "type" "ist,fst,shift,imul"))
180 ; Motion video insns also issue only to E0, and take two ticks.
181 (define_function_unit "ev5_e0" 1 0
182 (and (eq_attr "cpu" "ev5")
183 (eq_attr "type" "mvi"))
186 ; Conditional moves always take 2 ticks.
187 (define_function_unit "ev5_ebox" 2 0
188 (and (eq_attr "cpu" "ev5")
189 (eq_attr "type" "icmov"))
192 ; Branches can only issue to E1
193 (define_function_unit "ev5_e1" 1 0
194 (and (eq_attr "cpu" "ev5")
195 (eq_attr "type" "ibr,jsr"))
198 ; Multiplies also use the integer multiplier.
199 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
200 ; cycles before an integer multiplication completes."
201 (define_function_unit "imul" 1 0
202 (and (eq_attr "cpu" "ev5")
203 (and (eq_attr "type" "imul")
204 (eq_attr "opsize" "si")))
207 (define_function_unit "imul" 1 0
208 (and (eq_attr "cpu" "ev5")
209 (and (eq_attr "type" "imul")
210 (eq_attr "opsize" "di")))
213 (define_function_unit "imul" 1 0
214 (and (eq_attr "cpu" "ev5")
215 (and (eq_attr "type" "imul")
216 (eq_attr "opsize" "udi")))
219 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
220 ;; on either so we have to play the game again.
222 (define_function_unit "ev5_fbox" 2 0
223 (and (eq_attr "cpu" "ev5")
224 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
227 (define_function_unit "ev5_fm" 1 0
228 (and (eq_attr "cpu" "ev5")
229 (eq_attr "type" "fmul"))
232 ; Add and cmov as you would expect; fbr never produces a result;
233 ; fdiv issues through fa to the divider,
234 (define_function_unit "ev5_fa" 1 0
235 (and (eq_attr "cpu" "ev5")
236 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
239 ; ??? How to: "No instruction can be issued to pipe FA exactly five
240 ; cycles before a floating point divide completes."
241 (define_function_unit "fdiv" 1 0
242 (and (eq_attr "cpu" "ev5")
243 (and (eq_attr "type" "fdiv")
244 (eq_attr "opsize" "si")))
245 15 15) ; 15 to 31 data dependant
247 (define_function_unit "fdiv" 1 0
248 (and (eq_attr "cpu" "ev5")
249 (and (eq_attr "type" "fdiv")
250 (eq_attr "opsize" "di")))
251 22 22) ; 22 to 60 data dependant
253 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
255 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
256 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
258 ;; Conditional moves decompose into two independant primitives, each
259 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
261 (define_function_unit "ev6_ebox" 4 0
262 (and (eq_attr "cpu" "ev6")
263 (eq_attr "type" "icmov"))
266 (define_function_unit "ev6_ebox" 4 0
267 (and (eq_attr "cpu" "ev6")
268 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
271 ;; Integer loads take at least 3 clocks, and only issue to lower units.
272 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
273 (define_function_unit "ev6_l" 2 0
274 (and (eq_attr "cpu" "ev6")
275 (eq_attr "type" "ild,ldsym,ist,fst"))
278 ;; FP loads take at least 4 clocks. Return two from here...
279 (define_function_unit "ev6_l" 2 0
280 (and (eq_attr "cpu" "ev6")
281 (eq_attr "type" "fld"))
284 ;; Motion video insns also issue only to U0, and take three ticks.
285 (define_function_unit "ev6_u0" 1 0
286 (and (eq_attr "cpu" "ev6")
287 (eq_attr "type" "mvi"))
290 (define_function_unit "ev6_u" 2 0
291 (and (eq_attr "cpu" "ev6")
292 (eq_attr "type" "mvi"))
295 ;; Shifts issue to either upper pipe.
296 (define_function_unit "ev6_u" 2 0
297 (and (eq_attr "cpu" "ev6")
298 (eq_attr "type" "shift"))
301 ;; Multiplies issue only to U1, and all take 7 ticks.
302 ;; Rather than create a new function unit just for U1, reuse IMUL
303 (define_function_unit "imul" 1 0
304 (and (eq_attr "cpu" "ev6")
305 (eq_attr "type" "imul"))
308 (define_function_unit "ev6_u" 2 0
309 (and (eq_attr "cpu" "ev6")
310 (eq_attr "type" "imul"))
313 ;; Branches issue to either upper pipe
314 (define_function_unit "ev6_u" 2 0
315 (and (eq_attr "cpu" "ev6")
316 (eq_attr "type" "ibr"))
319 ;; Calls only issue to L0.
320 (define_function_unit "ev6_l0" 1 0
321 (and (eq_attr "cpu" "ev6")
322 (eq_attr "type" "jsr"))
325 (define_function_unit "ev6_l" 2 0
326 (and (eq_attr "cpu" "ev6")
327 (eq_attr "type" "jsr"))
330 ;; Ftoi/itof only issue to lower pipes
331 (define_function_unit "ev6_l" 2 0
332 (and (eq_attr "cpu" "ev6")
333 (eq_attr "type" "ftoi"))
336 (define_function_unit "ev6_l" 2 0
337 (and (eq_attr "cpu" "ev6")
338 (eq_attr "type" "itof"))
341 ;; For the FPU we are very similar to EV5, except there's no insn that
342 ;; can issue to fm & fa, so we get to leave that out.
344 (define_function_unit "ev6_fm" 1 0
345 (and (eq_attr "cpu" "ev6")
346 (eq_attr "type" "fmul"))
349 (define_function_unit "ev6_fa" 1 0
350 (and (eq_attr "cpu" "ev6")
351 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
354 (define_function_unit "ev6_fa" 1 0
355 (and (eq_attr "cpu" "ev6")
356 (eq_attr "type" "fcmov"))
359 (define_function_unit "fdiv" 1 0
360 (and (eq_attr "cpu" "ev6")
361 (and (eq_attr "type" "fdiv")
362 (eq_attr "opsize" "si")))
365 (define_function_unit "fdiv" 1 0
366 (and (eq_attr "cpu" "ev6")
367 (and (eq_attr "type" "fdiv")
368 (eq_attr "opsize" "di")))
371 (define_function_unit "fsqrt" 1 0
372 (and (eq_attr "cpu" "ev6")
373 (and (eq_attr "type" "fsqrt")
374 (eq_attr "opsize" "si")))
377 (define_function_unit "fsqrt" 1 0
378 (and (eq_attr "cpu" "ev6")
379 (and (eq_attr "type" "fsqrt")
380 (eq_attr "opsize" "di")))
383 ; ??? The FPU communicates with memory and the integer register file
384 ; via two fp store units. We need a slot in the fst immediately, and
385 ; a slot in LOW after the operand data is ready. At which point the
386 ; data may be moved either to the store queue or the integer register
387 ; file and the insn retired.
390 ;; First define the arithmetic insns. Note that the 32-bit forms also
393 ;; Handle 32-64 bit extension from memory to a floating point register
394 ;; specially, since this ocurrs frequently in int->double conversions.
396 ;; Note that while we must retain the =f case in the insn for reload's
397 ;; benefit, it should be eliminated after reload, so we should never emit
398 ;; code for that case. But we don't reject the possibility.
400 (define_expand "extendsidi2"
401 [(set (match_operand:DI 0 "register_operand" "")
402 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
407 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
409 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
415 lds %0,%1\;cvtlq %0,%0"
416 [(set_attr "type" "iadd,ild,fadd,fld")
417 (set_attr "length" "*,*,*,8")])
420 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
422 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
429 lds %0,%1\;cvtlq %0,%0"
430 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
431 (set_attr "length" "*,*,*,*,8")])
433 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
435 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
436 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
438 [(set (match_dup 2) (match_dup 1))
439 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
440 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
442 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
443 ;; generates better code. We have the anonymous addsi3 pattern below in
444 ;; case combine wants to make it.
445 (define_expand "addsi3"
446 [(set (match_operand:SI 0 "register_operand" "")
447 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
448 (match_operand:SI 2 "add_operand" "")))]
454 rtx op1 = gen_lowpart (DImode, operands[1]);
455 rtx op2 = gen_lowpart (DImode, operands[2]);
457 if (! cse_not_expected)
459 rtx tmp = gen_reg_rtx (DImode);
460 emit_insn (gen_adddi3 (tmp, op1, op2));
461 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
464 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
470 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
471 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
472 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
481 [(set (match_operand:SI 0 "register_operand" "")
482 (plus:SI (match_operand:SI 1 "register_operand" "")
483 (match_operand:SI 2 "const_int_operand" "")))]
484 "! add_operand (operands[2], SImode)"
485 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
486 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
489 HOST_WIDE_INT val = INTVAL (operands[2]);
490 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
491 HOST_WIDE_INT rest = val - low;
493 operands[3] = GEN_INT (rest);
494 operands[4] = GEN_INT (low);
498 [(set (match_operand:DI 0 "register_operand" "=r,r")
500 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
501 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
508 [(set (match_operand:DI 0 "register_operand" "")
510 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
511 (match_operand:SI 2 "const_int_operand" ""))))
512 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
513 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
514 && INTVAL (operands[2]) % 4 == 0"
515 [(set (match_dup 3) (match_dup 4))
516 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
521 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
527 operands[4] = GEN_INT (val);
528 operands[5] = GEN_INT (mult);
532 [(set (match_operand:DI 0 "register_operand" "")
534 (plus:SI (match_operator:SI 1 "comparison_operator"
535 [(match_operand 2 "" "")
536 (match_operand 3 "" "")])
537 (match_operand:SI 4 "add_operand" ""))))
538 (clobber (match_operand:DI 5 "register_operand" ""))]
540 [(set (match_dup 5) (match_dup 6))
541 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
544 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
545 operands[2], operands[3]);
546 operands[7] = gen_lowpart (SImode, operands[5]);
549 (define_expand "adddi3"
550 [(set (match_operand:DI 0 "register_operand" "")
551 (plus:DI (match_operand:DI 1 "register_operand" "")
552 (match_operand:DI 2 "add_operand" "")))]
556 ;; This pattern exists so that register elimination tries to canonize
557 ;; (plus (plus reg c1) c2).
560 [(set (match_operand:DI 0 "register_operand" "=r")
561 (match_operand:DI 1 "addition_operation" "p"))]
565 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
566 ;; With complications like
568 ;; The NT stack unwind code can't handle a subq to adjust the stack
569 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
570 ;; the exception handling code will loop if a subq is used and an
573 ;; The 19980616 change to emit prologues as RTL also confused some
574 ;; versions of GDB, which also interprets prologues. This has been
575 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
578 ;; and the fact that the three insns schedule exactly the same, it's
579 ;; just not worth the effort.
581 (define_insn "*adddi_2"
582 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
583 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
584 (match_operand:DI 2 "add_operand" "r,K,L")))]
591 ;; ??? Allow large constants when basing off the frame pointer or some
592 ;; virtual register that may eliminate to the frame pointer. This is
593 ;; done because register elimination offsets will change the hi/lo split,
594 ;; and if we split before reload, we will require additional instructions.
597 [(set (match_operand:DI 0 "register_operand" "=r")
598 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
599 (match_operand:DI 2 "const_int_operand" "n")))]
600 "REG_OK_FP_BASE_P (operands[1])
601 && INTVAL (operands[2]) >= 0
602 /* This is the largest constant an lda+ldah pair can add, minus
603 an upper bound on the displacement between SP and AP during
604 register elimination. See INITIAL_ELIMINATION_OFFSET. */
605 && INTVAL (operands[2])
607 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
608 - ALPHA_ROUND(current_function_outgoing_args_size)
609 - (ALPHA_ROUND (get_frame_size ()
610 + max_reg_num () * UNITS_PER_WORD
611 + current_function_pretend_args_size)
612 - current_function_pretend_args_size))"
615 ;; Don't do this if we are adjusting SP since we don't want to do it
616 ;; in two steps. Don't split FP sources for the reason listed above.
618 [(set (match_operand:DI 0 "register_operand" "")
619 (plus:DI (match_operand:DI 1 "register_operand" "")
620 (match_operand:DI 2 "const_int_operand" "")))]
621 "! add_operand (operands[2], DImode)
622 && operands[0] != stack_pointer_rtx
623 && operands[1] != frame_pointer_rtx
624 && operands[1] != arg_pointer_rtx"
625 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
626 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
629 HOST_WIDE_INT val = INTVAL (operands[2]);
630 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
631 HOST_WIDE_INT rest = val - low;
633 operands[4] = GEN_INT (low);
634 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
635 operands[3] = GEN_INT (rest);
636 else if (! no_new_pseudos)
638 operands[3] = gen_reg_rtx (DImode);
639 emit_move_insn (operands[3], operands[2]);
640 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
648 [(set (match_operand:SI 0 "register_operand" "=r,r")
649 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
650 (match_operand:SI 2 "const48_operand" "I,I"))
651 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
658 [(set (match_operand:DI 0 "register_operand" "=r,r")
660 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
661 (match_operand:SI 2 "const48_operand" "I,I"))
662 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
669 [(set (match_operand:DI 0 "register_operand" "")
671 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
672 [(match_operand 2 "" "")
673 (match_operand 3 "" "")])
674 (match_operand:SI 4 "const48_operand" ""))
675 (match_operand:SI 5 "sext_add_operand" ""))))
676 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
678 [(set (match_dup 6) (match_dup 7))
680 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
684 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
685 operands[2], operands[3]);
686 operands[8] = gen_lowpart (SImode, operands[6]);
690 [(set (match_operand:DI 0 "register_operand" "=r,r")
691 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
692 (match_operand:DI 2 "const48_operand" "I,I"))
693 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
699 (define_insn "negsi2"
700 [(set (match_operand:SI 0 "register_operand" "=r")
701 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
706 [(set (match_operand:DI 0 "register_operand" "=r")
707 (sign_extend:DI (neg:SI
708 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
712 (define_insn "negdi2"
713 [(set (match_operand:DI 0 "register_operand" "=r")
714 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
718 (define_expand "subsi3"
719 [(set (match_operand:SI 0 "register_operand" "")
720 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
721 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
727 rtx op1 = gen_lowpart (DImode, operands[1]);
728 rtx op2 = gen_lowpart (DImode, operands[2]);
730 if (! cse_not_expected)
732 rtx tmp = gen_reg_rtx (DImode);
733 emit_insn (gen_subdi3 (tmp, op1, op2));
734 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
737 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
743 [(set (match_operand:SI 0 "register_operand" "=r")
744 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
745 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
750 [(set (match_operand:DI 0 "register_operand" "=r")
751 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
752 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
756 (define_insn "subdi3"
757 [(set (match_operand:DI 0 "register_operand" "=r")
758 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
759 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
764 [(set (match_operand:SI 0 "register_operand" "=r")
765 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
766 (match_operand:SI 2 "const48_operand" "I"))
767 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
772 [(set (match_operand:DI 0 "register_operand" "=r")
774 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
775 (match_operand:SI 2 "const48_operand" "I"))
776 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
781 [(set (match_operand:DI 0 "register_operand" "=r")
782 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
783 (match_operand:DI 2 "const48_operand" "I"))
784 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
788 (define_insn "mulsi3"
789 [(set (match_operand:SI 0 "register_operand" "=r")
790 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
791 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
794 [(set_attr "type" "imul")
795 (set_attr "opsize" "si")])
798 [(set (match_operand:DI 0 "register_operand" "=r")
800 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
801 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
804 [(set_attr "type" "imul")
805 (set_attr "opsize" "si")])
807 (define_insn "muldi3"
808 [(set (match_operand:DI 0 "register_operand" "=r")
809 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
810 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
813 [(set_attr "type" "imul")])
815 (define_insn "umuldi3_highpart"
816 [(set (match_operand:DI 0 "register_operand" "=r")
819 (mult:TI (zero_extend:TI
820 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
822 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
826 [(set_attr "type" "imul")
827 (set_attr "opsize" "udi")])
830 [(set (match_operand:DI 0 "register_operand" "=r")
833 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
834 (match_operand:TI 2 "cint8_operand" "I"))
838 [(set_attr "type" "imul")
839 (set_attr "opsize" "udi")])
841 ;; The divide and remainder operations always take their inputs from
842 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
844 ;; ??? Force sign-extension here because some versions of OSF/1 don't
845 ;; do the right thing if the inputs are not properly sign-extended.
846 ;; But Linux, for instance, does not have this problem. Is it worth
847 ;; the complication here to eliminate the sign extension?
848 ;; Interix/NT has the same sign-extension problem.
850 (define_expand "divsi3"
852 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
854 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
855 (parallel [(set (reg:DI 27)
856 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
857 (clobber (reg:DI 23))
858 (clobber (reg:DI 28))])
859 (set (match_operand:SI 0 "nonimmediate_operand" "")
860 (subreg:SI (reg:DI 27) 0))]
864 (define_expand "udivsi3"
866 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
868 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
869 (parallel [(set (reg:DI 27)
870 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
871 (clobber (reg:DI 23))
872 (clobber (reg:DI 28))])
873 (set (match_operand:SI 0 "nonimmediate_operand" "")
874 (subreg:SI (reg:DI 27) 0))]
878 (define_expand "modsi3"
880 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
882 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
883 (parallel [(set (reg:DI 27)
884 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
885 (clobber (reg:DI 23))
886 (clobber (reg:DI 28))])
887 (set (match_operand:SI 0 "nonimmediate_operand" "")
888 (subreg:SI (reg:DI 27) 0))]
892 (define_expand "umodsi3"
894 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
896 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
897 (parallel [(set (reg:DI 27)
898 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
899 (clobber (reg:DI 23))
900 (clobber (reg:DI 28))])
901 (set (match_operand:SI 0 "nonimmediate_operand" "")
902 (subreg:SI (reg:DI 27) 0))]
906 (define_expand "divdi3"
907 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
908 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
909 (parallel [(set (reg:DI 27)
912 (clobber (reg:DI 23))
913 (clobber (reg:DI 28))])
914 (set (match_operand:DI 0 "nonimmediate_operand" "")
919 (define_expand "udivdi3"
920 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
921 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
922 (parallel [(set (reg:DI 27)
925 (clobber (reg:DI 23))
926 (clobber (reg:DI 28))])
927 (set (match_operand:DI 0 "nonimmediate_operand" "")
932 (define_expand "moddi3"
933 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
934 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
935 (parallel [(set (reg:DI 27)
938 (clobber (reg:DI 23))
939 (clobber (reg:DI 28))])
940 (set (match_operand:DI 0 "nonimmediate_operand" "")
945 (define_expand "umoddi3"
946 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
947 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
948 (parallel [(set (reg:DI 27)
951 (clobber (reg:DI 23))
952 (clobber (reg:DI 28))])
953 (set (match_operand:DI 0 "nonimmediate_operand" "")
958 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
959 ;; expanded by the assembler.
962 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
963 [(reg:DI 24) (reg:DI 25)])))
964 (clobber (reg:DI 23))
965 (clobber (reg:DI 28))]
968 [(set_attr "type" "jsr")
969 (set_attr "length" "8")])
973 (match_operator:DI 1 "divmod_operator"
974 [(reg:DI 24) (reg:DI 25)]))
975 (clobber (reg:DI 23))
976 (clobber (reg:DI 28))]
979 [(set_attr "type" "jsr")
980 (set_attr "length" "8")])
982 ;; Next are the basic logical operations. These only exist in DImode.
984 (define_insn "anddi3"
985 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
986 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
987 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
993 [(set_attr "type" "ilog,ilog,shift")])
995 ;; There are times when we can split an AND into two AND insns. This occurs
996 ;; when we can first clear any bytes and then clear anything else. For
997 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
998 ;; Only do this when running on 64-bit host since the computations are
999 ;; too messy otherwise.
1002 [(set (match_operand:DI 0 "register_operand" "")
1003 (and:DI (match_operand:DI 1 "register_operand" "")
1004 (match_operand:DI 2 "const_int_operand" "")))]
1005 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1006 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1007 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1010 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1011 unsigned HOST_WIDE_INT mask2 = mask1;
1014 /* For each byte that isn't all zeros, make it all ones. */
1015 for (i = 0; i < 64; i += 8)
1016 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1017 mask1 |= (HOST_WIDE_INT) 0xff << i;
1019 /* Now turn on any bits we've just turned off. */
1022 operands[3] = GEN_INT (mask1);
1023 operands[4] = GEN_INT (mask2);
1026 (define_insn "zero_extendqihi2"
1027 [(set (match_operand:HI 0 "register_operand" "=r")
1028 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1031 [(set_attr "type" "ilog")])
1034 [(set (match_operand:SI 0 "register_operand" "=r,r")
1035 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1040 [(set_attr "type" "ilog,ild")])
1043 [(set (match_operand:SI 0 "register_operand" "=r")
1044 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1047 [(set_attr "type" "ilog")])
1049 (define_expand "zero_extendqisi2"
1050 [(set (match_operand:SI 0 "register_operand" "")
1051 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1056 [(set (match_operand:DI 0 "register_operand" "=r,r")
1057 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1062 [(set_attr "type" "ilog,ild")])
1065 [(set (match_operand:DI 0 "register_operand" "=r")
1066 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1069 [(set_attr "type" "ilog")])
1071 (define_expand "zero_extendqidi2"
1072 [(set (match_operand:DI 0 "register_operand" "")
1073 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1078 [(set (match_operand:SI 0 "register_operand" "=r,r")
1079 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1084 [(set_attr "type" "shift,ild")])
1087 [(set (match_operand:SI 0 "register_operand" "=r")
1088 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1091 [(set_attr "type" "shift")])
1093 (define_expand "zero_extendhisi2"
1094 [(set (match_operand:SI 0 "register_operand" "")
1095 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1100 [(set (match_operand:DI 0 "register_operand" "=r,r")
1101 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1106 [(set_attr "type" "shift,ild")])
1109 [(set (match_operand:DI 0 "register_operand" "=r")
1110 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1113 [(set_attr "type" "shift")])
1115 (define_expand "zero_extendhidi2"
1116 [(set (match_operand:DI 0 "register_operand" "")
1117 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1121 (define_insn "zero_extendsidi2"
1122 [(set (match_operand:DI 0 "register_operand" "=r")
1123 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1126 [(set_attr "type" "shift")])
1129 [(set (match_operand:DI 0 "register_operand" "=r")
1130 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1131 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1134 [(set_attr "type" "ilog")])
1136 (define_insn "iordi3"
1137 [(set (match_operand:DI 0 "register_operand" "=r,r")
1138 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1139 (match_operand:DI 2 "or_operand" "rI,N")))]
1144 [(set_attr "type" "ilog")])
1146 (define_insn "one_cmpldi2"
1147 [(set (match_operand:DI 0 "register_operand" "=r")
1148 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1151 [(set_attr "type" "ilog")])
1154 [(set (match_operand:DI 0 "register_operand" "=r")
1155 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1156 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1159 [(set_attr "type" "ilog")])
1161 (define_insn "xordi3"
1162 [(set (match_operand:DI 0 "register_operand" "=r,r")
1163 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1164 (match_operand:DI 2 "or_operand" "rI,N")))]
1169 [(set_attr "type" "ilog")])
1172 [(set (match_operand:DI 0 "register_operand" "=r")
1173 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1174 (match_operand:DI 2 "register_operand" "rI"))))]
1177 [(set_attr "type" "ilog")])
1179 ;; Handle the FFS insn iff we support CIX.
1181 (define_expand "ffsdi2"
1183 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1185 (plus:DI (match_dup 2) (const_int 1)))
1186 (set (match_operand:DI 0 "register_operand" "")
1187 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1188 (const_int 0) (match_dup 3)))]
1192 operands[2] = gen_reg_rtx (DImode);
1193 operands[3] = gen_reg_rtx (DImode);
1197 [(set (match_operand:DI 0 "register_operand" "=r")
1198 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1201 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1202 ; reuse the existing type name.
1203 [(set_attr "type" "mvi")])
1205 ;; Next come the shifts and the various extract and insert operations.
1207 (define_insn "ashldi3"
1208 [(set (match_operand:DI 0 "register_operand" "=r,r")
1209 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1210 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1214 switch (which_alternative)
1217 if (operands[2] == const1_rtx)
1218 return \"addq %r1,%r1,%0\";
1220 return \"s%P2addq %r1,0,%0\";
1222 return \"sll %r1,%2,%0\";
1227 [(set_attr "type" "iadd,shift")])
1229 ;; ??? The following pattern is made by combine, but earlier phases
1230 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1231 ;; with this in a better way at some point.
1233 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1235 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1236 ;; (match_operand:DI 2 "const_int_operand" "P"))
1238 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1241 ;; if (operands[2] == const1_rtx)
1242 ;; return \"addl %r1,%r1,%0\";
1244 ;; return \"s%P2addl %r1,0,%0\";
1246 ;; [(set_attr "type" "iadd")])
1248 (define_insn "lshrdi3"
1249 [(set (match_operand:DI 0 "register_operand" "=r")
1250 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1251 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1254 [(set_attr "type" "shift")])
1256 (define_insn "ashrdi3"
1257 [(set (match_operand:DI 0 "register_operand" "=r")
1258 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1259 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1262 [(set_attr "type" "shift")])
1264 (define_expand "extendqihi2"
1266 (ashift:DI (match_operand:QI 1 "some_operand" "")
1268 (set (match_operand:HI 0 "register_operand" "")
1269 (ashiftrt:DI (match_dup 2)
1276 emit_insn (gen_extendqihi2x (operands[0],
1277 force_reg (QImode, operands[1])));
1281 /* If we have an unaligned MEM, extend to DImode (which we do
1282 specially) and then copy to the result. */
1283 if (unaligned_memory_operand (operands[1], HImode))
1285 rtx temp = gen_reg_rtx (DImode);
1287 emit_insn (gen_extendqidi2 (temp, operands[1]));
1288 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1292 operands[0] = gen_lowpart (DImode, operands[0]);
1293 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1294 operands[2] = gen_reg_rtx (DImode);
1297 (define_insn "extendqidi2x"
1298 [(set (match_operand:DI 0 "register_operand" "=r")
1299 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1302 [(set_attr "type" "shift")])
1304 (define_insn "extendhidi2x"
1305 [(set (match_operand:DI 0 "register_operand" "=r")
1306 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1309 [(set_attr "type" "shift")])
1311 (define_insn "extendqisi2x"
1312 [(set (match_operand:SI 0 "register_operand" "=r")
1313 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1316 [(set_attr "type" "shift")])
1318 (define_insn "extendhisi2x"
1319 [(set (match_operand:SI 0 "register_operand" "=r")
1320 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1323 [(set_attr "type" "shift")])
1325 (define_insn "extendqihi2x"
1326 [(set (match_operand:HI 0 "register_operand" "=r")
1327 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1330 [(set_attr "type" "shift")])
1332 (define_expand "extendqisi2"
1334 (ashift:DI (match_operand:QI 1 "some_operand" "")
1336 (set (match_operand:SI 0 "register_operand" "")
1337 (ashiftrt:DI (match_dup 2)
1344 emit_insn (gen_extendqisi2x (operands[0],
1345 force_reg (QImode, operands[1])));
1349 /* If we have an unaligned MEM, extend to a DImode form of
1350 the result (which we do specially). */
1351 if (unaligned_memory_operand (operands[1], QImode))
1353 rtx temp = gen_reg_rtx (DImode);
1355 emit_insn (gen_extendqidi2 (temp, operands[1]));
1356 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1360 operands[0] = gen_lowpart (DImode, operands[0]);
1361 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1362 operands[2] = gen_reg_rtx (DImode);
1365 (define_expand "extendqidi2"
1367 (ashift:DI (match_operand:QI 1 "some_operand" "")
1369 (set (match_operand:DI 0 "register_operand" "")
1370 (ashiftrt:DI (match_dup 2)
1377 emit_insn (gen_extendqidi2x (operands[0],
1378 force_reg (QImode, operands[1])));
1382 if (unaligned_memory_operand (operands[1], QImode))
1385 = gen_unaligned_extendqidi (operands[0],
1386 get_unaligned_address (operands[1], 1));
1388 alpha_set_memflags (seq, operands[1]);
1393 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1394 operands[2] = gen_reg_rtx (DImode);
1397 (define_expand "extendhisi2"
1399 (ashift:DI (match_operand:HI 1 "some_operand" "")
1401 (set (match_operand:SI 0 "register_operand" "")
1402 (ashiftrt:DI (match_dup 2)
1409 emit_insn (gen_extendhisi2x (operands[0],
1410 force_reg (HImode, operands[1])));
1414 /* If we have an unaligned MEM, extend to a DImode form of
1415 the result (which we do specially). */
1416 if (unaligned_memory_operand (operands[1], HImode))
1418 rtx temp = gen_reg_rtx (DImode);
1420 emit_insn (gen_extendhidi2 (temp, operands[1]));
1421 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1425 operands[0] = gen_lowpart (DImode, operands[0]);
1426 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1427 operands[2] = gen_reg_rtx (DImode);
1430 (define_expand "extendhidi2"
1432 (ashift:DI (match_operand:HI 1 "some_operand" "")
1434 (set (match_operand:DI 0 "register_operand" "")
1435 (ashiftrt:DI (match_dup 2)
1442 emit_insn (gen_extendhidi2x (operands[0],
1443 force_reg (HImode, operands[1])));
1447 if (unaligned_memory_operand (operands[1], HImode))
1450 = gen_unaligned_extendhidi (operands[0],
1451 get_unaligned_address (operands[1], 2));
1453 alpha_set_memflags (seq, operands[1]);
1458 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1459 operands[2] = gen_reg_rtx (DImode);
1462 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1463 ;; as a pattern saves one instruction. The code is similar to that for
1464 ;; the unaligned loads (see below).
1466 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1467 (define_expand "unaligned_extendqidi"
1468 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1470 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1473 (ashift:DI (match_dup 3)
1474 (minus:DI (const_int 64)
1476 (and:DI (match_dup 2) (const_int 7))
1478 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1479 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1482 { operands[2] = gen_reg_rtx (DImode);
1483 operands[3] = gen_reg_rtx (DImode);
1484 operands[4] = gen_reg_rtx (DImode);
1487 (define_expand "unaligned_extendhidi"
1488 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1490 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1493 (ashift:DI (match_dup 3)
1494 (minus:DI (const_int 64)
1496 (and:DI (match_dup 2) (const_int 7))
1498 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1499 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1502 { operands[2] = gen_reg_rtx (DImode);
1503 operands[3] = gen_reg_rtx (DImode);
1504 operands[4] = gen_reg_rtx (DImode);
1508 [(set (match_operand:DI 0 "register_operand" "=r")
1509 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1510 (match_operand:DI 2 "mode_width_operand" "n")
1511 (match_operand:DI 3 "mul8_operand" "I")))]
1513 "ext%M2l %r1,%s3,%0"
1514 [(set_attr "type" "shift")])
1516 (define_insn "extxl"
1517 [(set (match_operand:DI 0 "register_operand" "=r")
1518 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1519 (match_operand:DI 2 "mode_width_operand" "n")
1520 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1524 [(set_attr "type" "shift")])
1526 ;; Combine has some strange notion of preserving existing undefined behaviour
1527 ;; in shifts larger than a word size. So capture these patterns that it
1528 ;; should have turned into zero_extracts.
1531 [(set (match_operand:DI 0 "register_operand" "=r")
1532 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1533 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1535 (match_operand:DI 3 "mode_mask_operand" "n")))]
1538 [(set_attr "type" "shift")])
1541 [(set (match_operand:DI 0 "register_operand" "=r")
1542 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1543 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1547 [(set_attr "type" "shift")])
1549 (define_insn "extqh"
1550 [(set (match_operand:DI 0 "register_operand" "=r")
1552 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1553 (minus:DI (const_int 64)
1556 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1561 [(set_attr "type" "shift")])
1563 (define_insn "extlh"
1564 [(set (match_operand:DI 0 "register_operand" "=r")
1566 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1567 (const_int 2147483647))
1568 (minus:DI (const_int 64)
1571 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1576 [(set_attr "type" "shift")])
1578 (define_insn "extwh"
1579 [(set (match_operand:DI 0 "register_operand" "=r")
1581 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1583 (minus:DI (const_int 64)
1586 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1591 [(set_attr "type" "shift")])
1593 ;; This converts an extXl into an extXh with an appropriate adjustment
1594 ;; to the address calculation.
1597 ;; [(set (match_operand:DI 0 "register_operand" "")
1598 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1599 ;; (match_operand:DI 2 "mode_width_operand" "")
1600 ;; (ashift:DI (match_operand:DI 3 "" "")
1602 ;; (match_operand:DI 4 "const_int_operand" "")))
1603 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1604 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1605 ;; [(set (match_dup 5) (match_dup 6))
1606 ;; (set (match_dup 0)
1607 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1608 ;; (ashift:DI (plus:DI (match_dup 5)
1614 ;; operands[6] = plus_constant (operands[3],
1615 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1616 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1620 [(set (match_operand:DI 0 "register_operand" "=r")
1621 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1622 (match_operand:DI 2 "mul8_operand" "I")))]
1625 [(set_attr "type" "shift")])
1628 [(set (match_operand:DI 0 "register_operand" "=r")
1629 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1630 (match_operand:DI 2 "mul8_operand" "I")))]
1633 [(set_attr "type" "shift")])
1636 [(set (match_operand:DI 0 "register_operand" "=r")
1637 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1638 (match_operand:DI 2 "mul8_operand" "I")))]
1641 [(set_attr "type" "shift")])
1643 (define_insn "insbl"
1644 [(set (match_operand:DI 0 "register_operand" "=r")
1645 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1646 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1650 [(set_attr "type" "shift")])
1652 (define_insn "inswl"
1653 [(set (match_operand:DI 0 "register_operand" "=r")
1654 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1655 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1659 [(set_attr "type" "shift")])
1661 (define_insn "insll"
1662 [(set (match_operand:DI 0 "register_operand" "=r")
1663 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1664 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1668 [(set_attr "type" "shift")])
1670 (define_insn "insql"
1671 [(set (match_operand:DI 0 "register_operand" "=r")
1672 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1673 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1677 [(set_attr "type" "shift")])
1679 ;; Combine has this sometimes habit of moving the and outside of the
1680 ;; shift, making life more interesting.
1683 [(set (match_operand:DI 0 "register_operand" "=r")
1684 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1685 (match_operand:DI 2 "mul8_operand" "I"))
1686 (match_operand:DI 3 "immediate_operand" "i")))]
1687 "HOST_BITS_PER_WIDE_INT == 64
1688 && GET_CODE (operands[3]) == CONST_INT
1689 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1690 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1691 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1692 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1693 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1694 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1697 #if HOST_BITS_PER_WIDE_INT == 64
1698 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1699 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1700 return \"insbl %1,%s2,%0\";
1701 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1702 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1703 return \"inswl %1,%s2,%0\";
1704 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1705 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1706 return \"insll %1,%s2,%0\";
1710 [(set_attr "type" "shift")])
1712 ;; We do not include the insXh insns because they are complex to express
1713 ;; and it does not appear that we would ever want to generate them.
1715 ;; Since we need them for block moves, though, cop out and use unspec.
1717 (define_insn "insxh"
1718 [(set (match_operand:DI 0 "register_operand" "=r")
1719 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1720 (match_operand:DI 2 "mode_width_operand" "n")
1721 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1724 [(set_attr "type" "shift")])
1726 (define_insn "mskxl"
1727 [(set (match_operand:DI 0 "register_operand" "=r")
1728 (and:DI (not:DI (ashift:DI
1729 (match_operand:DI 2 "mode_mask_operand" "n")
1731 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1733 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1736 [(set_attr "type" "shift")])
1738 ;; We do not include the mskXh insns because it does not appear we would
1739 ;; ever generate one.
1741 ;; Again, we do for block moves and we use unspec again.
1743 (define_insn "mskxh"
1744 [(set (match_operand:DI 0 "register_operand" "=r")
1745 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1746 (match_operand:DI 2 "mode_width_operand" "n")
1747 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1750 [(set_attr "type" "shift")])
1752 ;; Prefer AND + NE over LSHIFTRT + AND.
1754 (define_insn_and_split "*ze_and_ne"
1755 [(set (match_operand:DI 0 "register_operand" "=r")
1756 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1758 (match_operand 2 "const_int_operand" "I")))]
1759 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1763 (and:DI (match_dup 1) (match_dup 3)))
1765 (ne:DI (match_dup 0) (const_int 0)))]
1766 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
1768 ;; Floating-point operations. All the double-precision insns can extend
1769 ;; from single, so indicate that. The exception are the ones that simply
1770 ;; play with the sign bits; it's not clear what to do there.
1772 (define_insn "abssf2"
1773 [(set (match_operand:SF 0 "register_operand" "=f")
1774 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1777 [(set_attr "type" "fcpys")])
1779 (define_insn "*nabssf2"
1780 [(set (match_operand:SF 0 "register_operand" "=f")
1781 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1784 [(set_attr "type" "fadd")])
1786 (define_insn "absdf2"
1787 [(set (match_operand:DF 0 "register_operand" "=f")
1788 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1791 [(set_attr "type" "fcpys")])
1793 (define_insn "*nabsdf2"
1794 [(set (match_operand:DF 0 "register_operand" "=f")
1795 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
1798 [(set_attr "type" "fadd")])
1800 (define_expand "abstf2"
1801 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1802 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1803 (use (match_dup 2))])]
1804 "TARGET_HAS_XFLOATING_LIBS"
1807 #if HOST_BITS_PER_WIDE_INT >= 64
1808 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1810 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1815 [(set (match_operand:TF 0 "register_operand" "=r")
1816 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1817 (use (match_operand:DI 2 "register_operand" "=r"))]
1818 "TARGET_HAS_XFLOATING_LIBS"
1822 [(set (match_operand:TF 0 "register_operand" "")
1823 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1824 (use (match_operand:DI 4 "register_operand" ""))]
1832 alpha_split_tfmode_pair (operands);
1835 if (rtx_equal_p (operands[0], operands[2]))
1837 else if (rtx_equal_p (operands[1], operands[2]))
1841 emit_move_insn (operands[0], operands[2]);
1843 tmp = gen_rtx_NOT (DImode, operands[4]);
1844 tmp = gen_rtx_AND (DImode, tmp, operands[3]);
1845 emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
1848 emit_move_insn (operands[0], operands[2]);
1852 (define_insn "negsf2"
1853 [(set (match_operand:SF 0 "register_operand" "=f")
1854 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1857 [(set_attr "type" "fadd")])
1859 (define_insn "negdf2"
1860 [(set (match_operand:DF 0 "register_operand" "=f")
1861 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1864 [(set_attr "type" "fadd")])
1866 (define_expand "negtf2"
1867 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1868 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1869 (use (match_dup 2))])]
1870 "TARGET_HAS_XFLOATING_LIBS"
1873 #if HOST_BITS_PER_WIDE_INT >= 64
1874 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1876 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1881 [(set (match_operand:TF 0 "register_operand" "=r")
1882 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1883 (use (match_operand:DI 2 "register_operand" "=r"))]
1884 "TARGET_HAS_XFLOATING_LIBS"
1888 [(set (match_operand:TF 0 "register_operand" "")
1889 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1890 (use (match_operand:DI 4 "register_operand" ""))]
1897 alpha_split_tfmode_pair (operands);
1900 if (rtx_equal_p (operands[0], operands[2]))
1902 else if (rtx_equal_p (operands[1], operands[2]))
1906 emit_move_insn (operands[0], operands[2]);
1908 emit_insn (gen_xordi3 (operands[1], operands[3], operands[4]));
1911 emit_move_insn (operands[0], operands[2]);
1916 [(set (match_operand:SF 0 "register_operand" "=&f")
1917 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1918 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1919 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1920 "add%,%)%& %R1,%R2,%0"
1921 [(set_attr "type" "fadd")
1922 (set_attr "trap" "yes")])
1924 (define_insn "addsf3"
1925 [(set (match_operand:SF 0 "register_operand" "=f")
1926 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1927 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1929 "add%,%)%& %R1,%R2,%0"
1930 [(set_attr "type" "fadd")
1931 (set_attr "trap" "yes")])
1934 [(set (match_operand:DF 0 "register_operand" "=&f")
1935 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1936 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1937 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1938 "add%-%)%& %R1,%R2,%0"
1939 [(set_attr "type" "fadd")
1940 (set_attr "trap" "yes")])
1942 (define_insn "adddf3"
1943 [(set (match_operand:DF 0 "register_operand" "=f")
1944 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1945 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1947 "add%-%)%& %R1,%R2,%0"
1948 [(set_attr "type" "fadd")
1949 (set_attr "trap" "yes")])
1952 [(set (match_operand:DF 0 "register_operand" "=f")
1953 (plus:DF (float_extend:DF
1954 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1955 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1956 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1957 "add%-%)%& %R1,%R2,%0"
1958 [(set_attr "type" "fadd")
1959 (set_attr "trap" "yes")])
1962 [(set (match_operand:DF 0 "register_operand" "=f")
1963 (plus:DF (float_extend:DF
1964 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1966 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1967 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1968 "add%-%)%& %R1,%R2,%0"
1969 [(set_attr "type" "fadd")
1970 (set_attr "trap" "yes")])
1972 (define_expand "addtf3"
1973 [(use (match_operand 0 "register_operand" ""))
1974 (use (match_operand 1 "general_operand" ""))
1975 (use (match_operand 2 "general_operand" ""))]
1976 "TARGET_HAS_XFLOATING_LIBS"
1977 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
1979 ;; Define conversion operators between DFmode and SImode, using the cvtql
1980 ;; instruction. To allow combine et al to do useful things, we keep the
1981 ;; operation as a unit until after reload, at which point we split the
1984 ;; Note that we (attempt to) only consider this optimization when the
1985 ;; ultimate destination is memory. If we will be doing further integer
1986 ;; processing, it is cheaper to do the truncation in the int regs.
1988 (define_insn "*cvtql"
1989 [(set (match_operand:SI 0 "register_operand" "=f")
1990 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1993 [(set_attr "type" "fadd")
1994 (set_attr "trap" "yes")])
1997 [(set (match_operand:SI 0 "memory_operand" "")
1998 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1999 (clobber (match_scratch:DI 2 ""))
2000 (clobber (match_scratch:SI 3 ""))]
2001 "TARGET_FP && reload_completed"
2002 [(set (match_dup 2) (fix:DI (match_dup 1)))
2003 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2004 (set (match_dup 0) (match_dup 3))]
2008 [(set (match_operand:SI 0 "memory_operand" "")
2009 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
2010 (clobber (match_scratch:DI 2 ""))]
2011 "TARGET_FP && reload_completed"
2012 [(set (match_dup 2) (fix:DI (match_dup 1)))
2013 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2014 (set (match_dup 0) (match_dup 3))]
2015 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2016 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2019 [(set (match_operand:SI 0 "memory_operand" "=m")
2020 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2021 (clobber (match_scratch:DI 2 "=&f"))
2022 (clobber (match_scratch:SI 3 "=&f"))]
2023 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2025 [(set_attr "type" "fadd")
2026 (set_attr "trap" "yes")])
2029 [(set (match_operand:SI 0 "memory_operand" "=m")
2030 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2031 (clobber (match_scratch:DI 2 "=f"))]
2032 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2034 [(set_attr "type" "fadd")
2035 (set_attr "trap" "yes")])
2038 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2039 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2040 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2042 [(set_attr "type" "fadd")
2043 (set_attr "trap" "yes")])
2045 (define_insn "fix_truncdfdi2"
2046 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2047 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2050 [(set_attr "type" "fadd")
2051 (set_attr "trap" "yes")])
2053 ;; Likewise between SFmode and SImode.
2056 [(set (match_operand:SI 0 "memory_operand" "")
2057 (subreg:SI (fix:DI (float_extend:DF
2058 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2059 (clobber (match_scratch:DI 2 ""))
2060 (clobber (match_scratch:SI 3 ""))]
2061 "TARGET_FP && reload_completed"
2062 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2063 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2064 (set (match_dup 0) (match_dup 3))]
2068 [(set (match_operand:SI 0 "memory_operand" "")
2069 (subreg:SI (fix:DI (float_extend:DF
2070 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2071 (clobber (match_scratch:DI 2 ""))]
2072 "TARGET_FP && reload_completed"
2073 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2074 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2075 (set (match_dup 0) (match_dup 3))]
2076 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2077 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2080 [(set (match_operand:SI 0 "memory_operand" "=m")
2081 (subreg:SI (fix:DI (float_extend:DF
2082 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2083 (clobber (match_scratch:DI 2 "=&f"))
2084 (clobber (match_scratch:SI 3 "=&f"))]
2085 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2087 [(set_attr "type" "fadd")
2088 (set_attr "trap" "yes")])
2091 [(set (match_operand:SI 0 "memory_operand" "=m")
2092 (subreg:SI (fix:DI (float_extend:DF
2093 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2094 (clobber (match_scratch:DI 2 "=f"))]
2095 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2097 [(set_attr "type" "fadd")
2098 (set_attr "trap" "yes")])
2101 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2102 (fix:DI (float_extend:DF
2103 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2104 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2106 [(set_attr "type" "fadd")
2107 (set_attr "trap" "yes")])
2109 (define_insn "fix_truncsfdi2"
2110 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2111 (fix:DI (float_extend:DF
2112 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2115 [(set_attr "type" "fadd")
2116 (set_attr "trap" "yes")])
2118 (define_expand "fix_trunctfdi2"
2119 [(use (match_operand:DI 0 "register_operand" ""))
2120 (use (match_operand:TF 1 "general_operand" ""))]
2121 "TARGET_HAS_XFLOATING_LIBS"
2122 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2125 [(set (match_operand:SF 0 "register_operand" "=&f")
2126 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2127 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2129 [(set_attr "type" "fadd")
2130 (set_attr "trap" "yes")])
2132 (define_insn "floatdisf2"
2133 [(set (match_operand:SF 0 "register_operand" "=f")
2134 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2137 [(set_attr "type" "fadd")
2138 (set_attr "trap" "yes")])
2141 [(set (match_operand:DF 0 "register_operand" "=&f")
2142 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2143 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2145 [(set_attr "type" "fadd")
2146 (set_attr "trap" "yes")])
2148 (define_insn "floatdidf2"
2149 [(set (match_operand:DF 0 "register_operand" "=f")
2150 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2153 [(set_attr "type" "fadd")
2154 (set_attr "trap" "yes")])
2156 (define_expand "floatditf2"
2157 [(use (match_operand:TF 0 "register_operand" ""))
2158 (use (match_operand:DI 1 "general_operand" ""))]
2159 "TARGET_HAS_XFLOATING_LIBS"
2160 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2162 (define_expand "floatunsdisf2"
2163 [(use (match_operand:SF 0 "register_operand" ""))
2164 (use (match_operand:DI 1 "register_operand" ""))]
2166 "alpha_emit_floatuns (operands); DONE;")
2168 (define_expand "floatunsdidf2"
2169 [(use (match_operand:DF 0 "register_operand" ""))
2170 (use (match_operand:DI 1 "register_operand" ""))]
2172 "alpha_emit_floatuns (operands); DONE;")
2174 (define_expand "floatunsditf2"
2175 [(use (match_operand:TF 0 "register_operand" ""))
2176 (use (match_operand:DI 1 "general_operand" ""))]
2177 "TARGET_HAS_XFLOATING_LIBS"
2178 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2180 (define_expand "extendsfdf2"
2181 [(set (match_operand:DF 0 "register_operand" "")
2182 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2186 if (alpha_fptm >= ALPHA_FPTM_SU)
2187 operands[1] = force_reg (SFmode, operands[1]);
2191 [(set (match_operand:DF 0 "register_operand" "=&f")
2192 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2193 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2195 [(set_attr "type" "fadd")
2196 (set_attr "trap" "yes")])
2199 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2200 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2201 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2206 [(set_attr "type" "fcpys,fld,fst")])
2208 (define_expand "extendsftf2"
2209 [(use (match_operand:TF 0 "register_operand" ""))
2210 (use (match_operand:SF 1 "general_operand" ""))]
2211 "TARGET_HAS_XFLOATING_LIBS"
2214 rtx tmp = gen_reg_rtx (DFmode);
2215 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2216 emit_insn (gen_extenddftf2 (operands[0], tmp));
2220 (define_expand "extenddftf2"
2221 [(use (match_operand:TF 0 "register_operand" ""))
2222 (use (match_operand:DF 1 "general_operand" ""))]
2223 "TARGET_HAS_XFLOATING_LIBS"
2224 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2227 [(set (match_operand:SF 0 "register_operand" "=&f")
2228 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2229 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2230 "cvt%-%,%)%& %R1,%0"
2231 [(set_attr "type" "fadd")
2232 (set_attr "trap" "yes")])
2234 (define_insn "truncdfsf2"
2235 [(set (match_operand:SF 0 "register_operand" "=f")
2236 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2238 "cvt%-%,%)%& %R1,%0"
2239 [(set_attr "type" "fadd")
2240 (set_attr "trap" "yes")])
2242 (define_expand "trunctfdf2"
2243 [(use (match_operand:DF 0 "register_operand" ""))
2244 (use (match_operand:TF 1 "general_operand" ""))]
2245 "TARGET_HAS_XFLOATING_LIBS"
2246 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2248 (define_expand "trunctfsf2"
2249 [(use (match_operand:SF 0 "register_operand" ""))
2250 (use (match_operand:TF 1 "general_operand" ""))]
2251 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2254 rtx tmpf, sticky, arg, lo, hi;
2256 tmpf = gen_reg_rtx (DFmode);
2257 sticky = gen_reg_rtx (DImode);
2258 arg = copy_to_mode_reg (TFmode, operands[1]);
2259 lo = gen_lowpart (DImode, arg);
2260 hi = gen_highpart (DImode, arg);
2262 /* Convert the low word of the TFmode value into a sticky rounding bit,
2263 then or it into the low bit of the high word. This leaves the sticky
2264 bit at bit 48 of the fraction, which is representable in DFmode,
2265 which prevents rounding error in the final conversion to SFmode. */
2267 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2268 gen_rtx_NE (DImode, lo, const0_rtx)));
2269 emit_insn (gen_iordi3 (hi, hi, sticky));
2270 emit_insn (gen_trunctfdf2 (tmpf, arg));
2271 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2276 [(set (match_operand:SF 0 "register_operand" "=&f")
2277 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2278 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2279 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2280 "div%,%)%& %R1,%R2,%0"
2281 [(set_attr "type" "fdiv")
2282 (set_attr "opsize" "si")
2283 (set_attr "trap" "yes")])
2285 (define_insn "divsf3"
2286 [(set (match_operand:SF 0 "register_operand" "=f")
2287 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2288 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2290 "div%,%)%& %R1,%R2,%0"
2291 [(set_attr "type" "fdiv")
2292 (set_attr "opsize" "si")
2293 (set_attr "trap" "yes")])
2296 [(set (match_operand:DF 0 "register_operand" "=&f")
2297 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2298 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2299 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2300 "div%-%)%& %R1,%R2,%0"
2301 [(set_attr "type" "fdiv")
2302 (set_attr "trap" "yes")])
2304 (define_insn "divdf3"
2305 [(set (match_operand:DF 0 "register_operand" "=f")
2306 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2307 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2309 "div%-%)%& %R1,%R2,%0"
2310 [(set_attr "type" "fdiv")
2311 (set_attr "trap" "yes")])
2314 [(set (match_operand:DF 0 "register_operand" "=f")
2315 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2316 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2317 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2318 "div%-%)%& %R1,%R2,%0"
2319 [(set_attr "type" "fdiv")
2320 (set_attr "trap" "yes")])
2323 [(set (match_operand:DF 0 "register_operand" "=f")
2324 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2326 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2327 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2328 "div%-%)%& %R1,%R2,%0"
2329 [(set_attr "type" "fdiv")
2330 (set_attr "trap" "yes")])
2333 [(set (match_operand:DF 0 "register_operand" "=f")
2334 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2335 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2336 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2337 "div%-%)%& %R1,%R2,%0"
2338 [(set_attr "type" "fdiv")
2339 (set_attr "trap" "yes")])
2341 (define_expand "divtf3"
2342 [(use (match_operand 0 "register_operand" ""))
2343 (use (match_operand 1 "general_operand" ""))
2344 (use (match_operand 2 "general_operand" ""))]
2345 "TARGET_HAS_XFLOATING_LIBS"
2346 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2349 [(set (match_operand:SF 0 "register_operand" "=&f")
2350 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2351 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2352 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2353 "mul%,%)%& %R1,%R2,%0"
2354 [(set_attr "type" "fmul")
2355 (set_attr "trap" "yes")])
2357 (define_insn "mulsf3"
2358 [(set (match_operand:SF 0 "register_operand" "=f")
2359 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2360 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2362 "mul%,%)%& %R1,%R2,%0"
2363 [(set_attr "type" "fmul")
2364 (set_attr "trap" "yes")])
2367 [(set (match_operand:DF 0 "register_operand" "=&f")
2368 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2369 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2370 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2371 "mul%-%)%& %R1,%R2,%0"
2372 [(set_attr "type" "fmul")
2373 (set_attr "trap" "yes")])
2375 (define_insn "muldf3"
2376 [(set (match_operand:DF 0 "register_operand" "=f")
2377 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2378 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2380 "mul%-%)%& %R1,%R2,%0"
2381 [(set_attr "type" "fmul")
2382 (set_attr "trap" "yes")])
2385 [(set (match_operand:DF 0 "register_operand" "=f")
2386 (mult:DF (float_extend:DF
2387 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2388 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2389 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2390 "mul%-%)%& %R1,%R2,%0"
2391 [(set_attr "type" "fmul")
2392 (set_attr "trap" "yes")])
2395 [(set (match_operand:DF 0 "register_operand" "=f")
2396 (mult:DF (float_extend:DF
2397 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2399 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2400 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2401 "mul%-%)%& %R1,%R2,%0"
2402 [(set_attr "type" "fmul")
2403 (set_attr "trap" "yes")])
2405 (define_expand "multf3"
2406 [(use (match_operand 0 "register_operand" ""))
2407 (use (match_operand 1 "general_operand" ""))
2408 (use (match_operand 2 "general_operand" ""))]
2409 "TARGET_HAS_XFLOATING_LIBS"
2410 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2413 [(set (match_operand:SF 0 "register_operand" "=&f")
2414 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2415 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2416 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2417 "sub%,%)%& %R1,%R2,%0"
2418 [(set_attr "type" "fadd")
2419 (set_attr "trap" "yes")])
2421 (define_insn "subsf3"
2422 [(set (match_operand:SF 0 "register_operand" "=f")
2423 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2424 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2426 "sub%,%)%& %R1,%R2,%0"
2427 [(set_attr "type" "fadd")
2428 (set_attr "trap" "yes")])
2431 [(set (match_operand:DF 0 "register_operand" "=&f")
2432 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2433 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2434 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2435 "sub%-%)%& %R1,%R2,%0"
2436 [(set_attr "type" "fadd")
2437 (set_attr "trap" "yes")])
2439 (define_insn "subdf3"
2440 [(set (match_operand:DF 0 "register_operand" "=f")
2441 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2442 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2444 "sub%-%)%& %R1,%R2,%0"
2445 [(set_attr "type" "fadd")
2446 (set_attr "trap" "yes")])
2449 [(set (match_operand:DF 0 "register_operand" "=f")
2450 (minus:DF (float_extend:DF
2451 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2452 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2453 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2454 "sub%-%)%& %R1,%R2,%0"
2455 [(set_attr "type" "fadd")
2456 (set_attr "trap" "yes")])
2459 [(set (match_operand:DF 0 "register_operand" "=f")
2460 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2462 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2463 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2464 "sub%-%)%& %R1,%R2,%0"
2465 [(set_attr "type" "fadd")
2466 (set_attr "trap" "yes")])
2469 [(set (match_operand:DF 0 "register_operand" "=f")
2470 (minus:DF (float_extend:DF
2471 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2473 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2474 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2475 "sub%-%)%& %R1,%R2,%0"
2476 [(set_attr "type" "fadd")
2477 (set_attr "trap" "yes")])
2479 (define_expand "subtf3"
2480 [(use (match_operand 0 "register_operand" ""))
2481 (use (match_operand 1 "general_operand" ""))
2482 (use (match_operand 2 "general_operand" ""))]
2483 "TARGET_HAS_XFLOATING_LIBS"
2484 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2487 [(set (match_operand:SF 0 "register_operand" "=&f")
2488 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2489 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2491 [(set_attr "type" "fsqrt")
2492 (set_attr "opsize" "si")
2493 (set_attr "trap" "yes")])
2495 (define_insn "sqrtsf2"
2496 [(set (match_operand:SF 0 "register_operand" "=f")
2497 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2498 "TARGET_FP && TARGET_FIX"
2500 [(set_attr "type" "fsqrt")
2501 (set_attr "opsize" "si")
2502 (set_attr "trap" "yes")])
2505 [(set (match_operand:DF 0 "register_operand" "=&f")
2506 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2507 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2509 [(set_attr "type" "fsqrt")
2510 (set_attr "trap" "yes")])
2512 (define_insn "sqrtdf2"
2513 [(set (match_operand:DF 0 "register_operand" "=f")
2514 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2515 "TARGET_FP && TARGET_FIX"
2517 [(set_attr "type" "fsqrt")
2518 (set_attr "trap" "yes")])
2520 ;; Next are all the integer comparisons, and conditional moves and branches
2521 ;; and some of the related define_expand's and define_split's.
2523 (define_insn "*setcc_internal"
2524 [(set (match_operand 0 "register_operand" "=r")
2525 (match_operator 1 "alpha_comparison_operator"
2526 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2527 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2528 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2529 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2530 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2532 [(set_attr "type" "icmp")])
2534 (define_insn "*setcc_swapped_internal"
2535 [(set (match_operand 0 "register_operand" "=r")
2536 (match_operator 1 "alpha_swapped_comparison_operator"
2537 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2538 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2539 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2540 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2541 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2543 [(set_attr "type" "icmp")])
2545 (define_insn "*setne_internal"
2546 [(set (match_operand 0 "register_operand" "=r")
2547 (match_operator 1 "signed_comparison_operator"
2548 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2550 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2551 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2552 && GET_CODE (operands[1]) == NE
2553 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2555 [(set_attr "type" "icmp")])
2557 ;; The mode folding trick can't be used with const_int operands, since
2558 ;; reload needs to know the proper mode.
2560 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2561 ;; in order to create more pairs of constants. As long as we're allowing
2562 ;; two constants at the same time, and will have to reload one of them...
2564 (define_insn "*movqicc_internal"
2565 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2567 (match_operator 2 "signed_comparison_operator"
2568 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2569 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2570 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2571 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2572 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2578 [(set_attr "type" "icmov")])
2580 (define_insn "*movhicc_internal"
2581 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2583 (match_operator 2 "signed_comparison_operator"
2584 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2585 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2586 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2587 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2588 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2594 [(set_attr "type" "icmov")])
2596 (define_insn "*movsicc_internal"
2597 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2599 (match_operator 2 "signed_comparison_operator"
2600 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2601 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2602 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2603 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2604 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2610 [(set_attr "type" "icmov")])
2612 (define_insn "*movdicc_internal"
2613 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2615 (match_operator 2 "signed_comparison_operator"
2616 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2617 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2618 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2619 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2620 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2626 [(set_attr "type" "icmov")])
2628 (define_insn "*movqicc_lbc"
2629 [(set (match_operand:QI 0 "register_operand" "=r,r")
2631 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2635 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2636 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2641 [(set_attr "type" "icmov")])
2643 (define_insn "*movhicc_lbc"
2644 [(set (match_operand:HI 0 "register_operand" "=r,r")
2646 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2650 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2651 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2656 [(set_attr "type" "icmov")])
2658 (define_insn "*movsicc_lbc"
2659 [(set (match_operand:SI 0 "register_operand" "=r,r")
2661 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2665 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2666 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2671 [(set_attr "type" "icmov")])
2673 (define_insn "*movdicc_lbc"
2674 [(set (match_operand:DI 0 "register_operand" "=r,r")
2676 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2680 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2681 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2686 [(set_attr "type" "icmov")])
2688 (define_insn "*movqicc_lbs"
2689 [(set (match_operand:QI 0 "register_operand" "=r,r")
2691 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2695 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2696 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2701 [(set_attr "type" "icmov")])
2703 (define_insn "*movhicc_lbs"
2704 [(set (match_operand:HI 0 "register_operand" "=r,r")
2706 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2710 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2711 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2716 [(set_attr "type" "icmov")])
2718 (define_insn "*movsicc_lbs"
2719 [(set (match_operand:SI 0 "register_operand" "=r,r")
2721 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2725 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2726 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2731 [(set_attr "type" "icmov")])
2733 (define_insn "*movdicc_lbs"
2734 [(set (match_operand:DI 0 "register_operand" "=r,r")
2736 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2740 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2741 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2746 [(set_attr "type" "icmov")])
2748 ;; For ABS, we have two choices, depending on whether the input and output
2749 ;; registers are the same or not.
2750 (define_expand "absdi2"
2751 [(set (match_operand:DI 0 "register_operand" "")
2752 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2755 { if (rtx_equal_p (operands[0], operands[1]))
2756 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2758 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2763 (define_expand "absdi2_same"
2764 [(set (match_operand:DI 1 "register_operand" "")
2765 (neg:DI (match_operand:DI 0 "register_operand" "")))
2767 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2773 (define_expand "absdi2_diff"
2774 [(set (match_operand:DI 0 "register_operand" "")
2775 (neg:DI (match_operand:DI 1 "register_operand" "")))
2777 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2784 [(set (match_operand:DI 0 "register_operand" "")
2785 (abs:DI (match_dup 0)))
2786 (clobber (match_operand:DI 2 "register_operand" ""))]
2788 [(set (match_dup 1) (neg:DI (match_dup 0)))
2789 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2790 (match_dup 0) (match_dup 1)))]
2794 [(set (match_operand:DI 0 "register_operand" "")
2795 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2796 "! rtx_equal_p (operands[0], operands[1])"
2797 [(set (match_dup 0) (neg:DI (match_dup 1)))
2798 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2799 (match_dup 0) (match_dup 1)))]
2803 [(set (match_operand:DI 0 "register_operand" "")
2804 (neg:DI (abs:DI (match_dup 0))))
2805 (clobber (match_operand:DI 2 "register_operand" ""))]
2807 [(set (match_dup 1) (neg:DI (match_dup 0)))
2808 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2809 (match_dup 0) (match_dup 1)))]
2813 [(set (match_operand:DI 0 "register_operand" "")
2814 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2815 "! rtx_equal_p (operands[0], operands[1])"
2816 [(set (match_dup 0) (neg:DI (match_dup 1)))
2817 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2818 (match_dup 0) (match_dup 1)))]
2821 (define_insn "sminqi3"
2822 [(set (match_operand:QI 0 "register_operand" "=r")
2823 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2824 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2827 [(set_attr "type" "mvi")])
2829 (define_insn "uminqi3"
2830 [(set (match_operand:QI 0 "register_operand" "=r")
2831 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2832 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2835 [(set_attr "type" "mvi")])
2837 (define_insn "smaxqi3"
2838 [(set (match_operand:QI 0 "register_operand" "=r")
2839 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2840 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2843 [(set_attr "type" "mvi")])
2845 (define_insn "umaxqi3"
2846 [(set (match_operand:QI 0 "register_operand" "=r")
2847 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2848 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2851 [(set_attr "type" "mvi")])
2853 (define_insn "sminhi3"
2854 [(set (match_operand:HI 0 "register_operand" "=r")
2855 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2856 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2859 [(set_attr "type" "mvi")])
2861 (define_insn "uminhi3"
2862 [(set (match_operand:HI 0 "register_operand" "=r")
2863 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2864 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2867 [(set_attr "type" "mvi")])
2869 (define_insn "smaxhi3"
2870 [(set (match_operand:HI 0 "register_operand" "=r")
2871 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2872 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2875 [(set_attr "type" "mvi")])
2877 (define_insn "umaxhi3"
2878 [(set (match_operand:HI 0 "register_operand" "=r")
2879 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2880 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2883 [(set_attr "type" "shift")])
2885 (define_expand "smaxdi3"
2887 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2888 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2889 (set (match_operand:DI 0 "register_operand" "")
2890 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2891 (match_dup 1) (match_dup 2)))]
2894 { operands[3] = gen_reg_rtx (DImode);
2898 [(set (match_operand:DI 0 "register_operand" "")
2899 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2900 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2901 (clobber (match_operand:DI 3 "register_operand" ""))]
2902 "operands[2] != const0_rtx"
2903 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2904 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2905 (match_dup 1) (match_dup 2)))]
2909 [(set (match_operand:DI 0 "register_operand" "=r")
2910 (smax:DI (match_operand:DI 1 "register_operand" "0")
2914 [(set_attr "type" "icmov")])
2916 (define_expand "smindi3"
2918 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2919 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2920 (set (match_operand:DI 0 "register_operand" "")
2921 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2922 (match_dup 1) (match_dup 2)))]
2925 { operands[3] = gen_reg_rtx (DImode);
2929 [(set (match_operand:DI 0 "register_operand" "")
2930 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2931 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2932 (clobber (match_operand:DI 3 "register_operand" ""))]
2933 "operands[2] != const0_rtx"
2934 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2935 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2936 (match_dup 1) (match_dup 2)))]
2940 [(set (match_operand:DI 0 "register_operand" "=r")
2941 (smin:DI (match_operand:DI 1 "register_operand" "0")
2945 [(set_attr "type" "icmov")])
2947 (define_expand "umaxdi3"
2949 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2950 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2951 (set (match_operand:DI 0 "register_operand" "")
2952 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2953 (match_dup 1) (match_dup 2)))]
2956 { operands[3] = gen_reg_rtx (DImode);
2960 [(set (match_operand:DI 0 "register_operand" "")
2961 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2962 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2963 (clobber (match_operand:DI 3 "register_operand" ""))]
2964 "operands[2] != const0_rtx"
2965 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2966 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2967 (match_dup 1) (match_dup 2)))]
2970 (define_expand "umindi3"
2972 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2973 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2974 (set (match_operand:DI 0 "register_operand" "")
2975 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2976 (match_dup 1) (match_dup 2)))]
2979 { operands[3] = gen_reg_rtx (DImode);
2983 [(set (match_operand:DI 0 "register_operand" "")
2984 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2985 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2986 (clobber (match_operand:DI 3 "register_operand" ""))]
2987 "operands[2] != const0_rtx"
2988 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2989 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2990 (match_dup 1) (match_dup 2)))]
2996 (match_operator 1 "signed_comparison_operator"
2997 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2999 (label_ref (match_operand 0 "" ""))
3003 [(set_attr "type" "ibr")])
3008 (match_operator 1 "signed_comparison_operator"
3010 (match_operand:DI 2 "register_operand" "r")])
3011 (label_ref (match_operand 0 "" ""))
3015 [(set_attr "type" "ibr")])
3020 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3024 (label_ref (match_operand 0 "" ""))
3028 [(set_attr "type" "ibr")])
3033 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3037 (label_ref (match_operand 0 "" ""))
3041 [(set_attr "type" "ibr")])
3047 (match_operator 1 "comparison_operator"
3048 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3050 (match_operand:DI 3 "const_int_operand" ""))
3052 (label_ref (match_operand 0 "" ""))
3054 (clobber (match_operand:DI 4 "register_operand" ""))])]
3055 "INTVAL (operands[3]) != 0"
3057 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3059 (if_then_else (match_op_dup 1
3060 [(zero_extract:DI (match_dup 4)
3064 (label_ref (match_dup 0))
3068 ;; The following are the corresponding floating-point insns. Recall
3069 ;; we need to have variants that expand the arguments from SFmode
3072 (define_insn "*cmpdf_tp"
3073 [(set (match_operand:DF 0 "register_operand" "=&f")
3074 (match_operator:DF 1 "alpha_fp_comparison_operator"
3075 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3076 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3077 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3078 "cmp%-%C1%' %R2,%R3,%0"
3079 [(set_attr "type" "fadd")
3080 (set_attr "trap" "yes")])
3082 (define_insn "*cmpdf_no_tp"
3083 [(set (match_operand:DF 0 "register_operand" "=f")
3084 (match_operator:DF 1 "alpha_fp_comparison_operator"
3085 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3086 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3087 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3088 "cmp%-%C1%' %R2,%R3,%0"
3089 [(set_attr "type" "fadd")
3090 (set_attr "trap" "yes")])
3093 [(set (match_operand:DF 0 "register_operand" "=&f")
3094 (match_operator:DF 1 "alpha_fp_comparison_operator"
3096 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3097 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3098 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3099 "cmp%-%C1%' %R2,%R3,%0"
3100 [(set_attr "type" "fadd")
3101 (set_attr "trap" "yes")])
3104 [(set (match_operand:DF 0 "register_operand" "=f")
3105 (match_operator:DF 1 "alpha_fp_comparison_operator"
3107 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3108 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3109 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3110 "cmp%-%C1%' %R2,%R3,%0"
3111 [(set_attr "type" "fadd")
3112 (set_attr "trap" "yes")])
3115 [(set (match_operand:DF 0 "register_operand" "=&f")
3116 (match_operator:DF 1 "alpha_fp_comparison_operator"
3117 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3119 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3120 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3121 "cmp%-%C1%' %R2,%R3,%0"
3122 [(set_attr "type" "fadd")
3123 (set_attr "trap" "yes")])
3126 [(set (match_operand:DF 0 "register_operand" "=f")
3127 (match_operator:DF 1 "alpha_fp_comparison_operator"
3128 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3130 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3131 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3132 "cmp%-%C1%' %R2,%R3,%0"
3133 [(set_attr "type" "fadd")
3134 (set_attr "trap" "yes")])
3137 [(set (match_operand:DF 0 "register_operand" "=&f")
3138 (match_operator:DF 1 "alpha_fp_comparison_operator"
3140 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3142 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3143 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3144 "cmp%-%C1%' %R2,%R3,%0"
3145 [(set_attr "type" "fadd")
3146 (set_attr "trap" "yes")])
3149 [(set (match_operand:DF 0 "register_operand" "=f")
3150 (match_operator:DF 1 "alpha_fp_comparison_operator"
3152 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3154 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3155 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3156 "cmp%-%C1%' %R2,%R3,%0"
3157 [(set_attr "type" "fadd")
3158 (set_attr "trap" "yes")])
3161 [(set (match_operand:DF 0 "register_operand" "=f,f")
3163 (match_operator 3 "signed_comparison_operator"
3164 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3165 (match_operand:DF 2 "fp0_operand" "G,G")])
3166 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3167 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3171 fcmov%D3 %R4,%R5,%0"
3172 [(set_attr "type" "fcmov")])
3175 [(set (match_operand:SF 0 "register_operand" "=f,f")
3177 (match_operator 3 "signed_comparison_operator"
3178 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3179 (match_operand:DF 2 "fp0_operand" "G,G")])
3180 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3181 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3185 fcmov%D3 %R4,%R5,%0"
3186 [(set_attr "type" "fcmov")])
3189 [(set (match_operand:DF 0 "register_operand" "=f,f")
3191 (match_operator 3 "signed_comparison_operator"
3192 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3193 (match_operand:DF 2 "fp0_operand" "G,G")])
3194 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3195 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3199 fcmov%D3 %R4,%R5,%0"
3200 [(set_attr "type" "fcmov")])
3203 [(set (match_operand:DF 0 "register_operand" "=f,f")
3205 (match_operator 3 "signed_comparison_operator"
3207 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3208 (match_operand:DF 2 "fp0_operand" "G,G")])
3209 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3210 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3214 fcmov%D3 %R4,%R5,%0"
3215 [(set_attr "type" "fcmov")])
3218 [(set (match_operand:SF 0 "register_operand" "=f,f")
3220 (match_operator 3 "signed_comparison_operator"
3222 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3223 (match_operand:DF 2 "fp0_operand" "G,G")])
3224 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3225 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3229 fcmov%D3 %R4,%R5,%0"
3230 [(set_attr "type" "fcmov")])
3233 [(set (match_operand:DF 0 "register_operand" "=f,f")
3235 (match_operator 3 "signed_comparison_operator"
3237 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3238 (match_operand:DF 2 "fp0_operand" "G,G")])
3239 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3240 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3244 fcmov%D3 %R4,%R5,%0"
3245 [(set_attr "type" "fcmov")])
3247 (define_expand "maxdf3"
3249 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3250 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3251 (set (match_operand:DF 0 "register_operand" "")
3252 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3253 (match_dup 1) (match_dup 2)))]
3256 { operands[3] = gen_reg_rtx (DFmode);
3257 operands[4] = CONST0_RTX (DFmode);
3260 (define_expand "mindf3"
3262 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3263 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3264 (set (match_operand:DF 0 "register_operand" "")
3265 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3266 (match_dup 1) (match_dup 2)))]
3269 { operands[3] = gen_reg_rtx (DFmode);
3270 operands[4] = CONST0_RTX (DFmode);
3273 (define_expand "maxsf3"
3275 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3276 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3277 (set (match_operand:SF 0 "register_operand" "")
3278 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3279 (match_dup 1) (match_dup 2)))]
3282 { operands[3] = gen_reg_rtx (DFmode);
3283 operands[4] = CONST0_RTX (DFmode);
3286 (define_expand "minsf3"
3288 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3289 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3290 (set (match_operand:SF 0 "register_operand" "")
3291 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3292 (match_dup 1) (match_dup 2)))]
3295 { operands[3] = gen_reg_rtx (DFmode);
3296 operands[4] = CONST0_RTX (DFmode);
3302 (match_operator 1 "signed_comparison_operator"
3303 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3304 (match_operand:DF 3 "fp0_operand" "G")])
3305 (label_ref (match_operand 0 "" ""))
3309 [(set_attr "type" "fbr")])
3314 (match_operator 1 "signed_comparison_operator"
3316 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3317 (match_operand:DF 3 "fp0_operand" "G")])
3318 (label_ref (match_operand 0 "" ""))
3322 [(set_attr "type" "fbr")])
3324 ;; These are the main define_expand's used to make conditional branches
3327 (define_expand "cmpdf"
3328 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3329 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3333 alpha_compare.op0 = operands[0];
3334 alpha_compare.op1 = operands[1];
3335 alpha_compare.fp_p = 1;
3339 (define_expand "cmptf"
3340 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3341 (match_operand:TF 1 "general_operand" "")))]
3342 "TARGET_HAS_XFLOATING_LIBS"
3345 alpha_compare.op0 = operands[0];
3346 alpha_compare.op1 = operands[1];
3347 alpha_compare.fp_p = 1;
3351 (define_expand "cmpdi"
3352 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3353 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3357 alpha_compare.op0 = operands[0];
3358 alpha_compare.op1 = operands[1];
3359 alpha_compare.fp_p = 0;
3363 (define_expand "beq"
3365 (if_then_else (match_dup 1)
3366 (label_ref (match_operand 0 "" ""))
3369 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3371 (define_expand "bne"
3373 (if_then_else (match_dup 1)
3374 (label_ref (match_operand 0 "" ""))
3377 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3379 (define_expand "blt"
3381 (if_then_else (match_dup 1)
3382 (label_ref (match_operand 0 "" ""))
3385 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3387 (define_expand "ble"
3389 (if_then_else (match_dup 1)
3390 (label_ref (match_operand 0 "" ""))
3393 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3395 (define_expand "bgt"
3397 (if_then_else (match_dup 1)
3398 (label_ref (match_operand 0 "" ""))
3401 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3403 (define_expand "bge"
3405 (if_then_else (match_dup 1)
3406 (label_ref (match_operand 0 "" ""))
3409 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3411 (define_expand "bltu"
3413 (if_then_else (match_dup 1)
3414 (label_ref (match_operand 0 "" ""))
3417 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3419 (define_expand "bleu"
3421 (if_then_else (match_dup 1)
3422 (label_ref (match_operand 0 "" ""))
3425 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3427 (define_expand "bgtu"
3429 (if_then_else (match_dup 1)
3430 (label_ref (match_operand 0 "" ""))
3433 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3435 (define_expand "bgeu"
3437 (if_then_else (match_dup 1)
3438 (label_ref (match_operand 0 "" ""))
3441 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3443 (define_expand "bunordered"
3445 (if_then_else (match_dup 1)
3446 (label_ref (match_operand 0 "" ""))
3449 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3451 (define_expand "bordered"
3453 (if_then_else (match_dup 1)
3454 (label_ref (match_operand 0 "" ""))
3457 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3459 (define_expand "seq"
3460 [(set (match_operand:DI 0 "register_operand" "")
3465 if (alpha_compare.fp_p)
3468 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3469 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3472 (define_expand "sne"
3473 [(set (match_operand:DI 0 "register_operand" "")
3475 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3479 if (alpha_compare.fp_p)
3482 if (alpha_compare.op1 == const0_rtx)
3484 operands[1] = gen_rtx_NE (DImode, alpha_compare.op0, alpha_compare.op1);
3485 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3486 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3490 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3491 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3494 (define_expand "slt"
3495 [(set (match_operand:DI 0 "register_operand" "")
3500 if (alpha_compare.fp_p)
3503 operands[1] = gen_rtx_LT (DImode, alpha_compare.op0, alpha_compare.op1);
3504 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3507 (define_expand "sle"
3508 [(set (match_operand:DI 0 "register_operand" "")
3513 if (alpha_compare.fp_p)
3516 operands[1] = gen_rtx_LE (DImode, alpha_compare.op0, alpha_compare.op1);
3517 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3520 (define_expand "sgt"
3521 [(set (match_operand:DI 0 "register_operand" "")
3526 if (alpha_compare.fp_p)
3529 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare.op1),
3531 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3534 (define_expand "sge"
3535 [(set (match_operand:DI 0 "register_operand" "")
3540 if (alpha_compare.fp_p)
3543 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare.op1),
3545 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3548 (define_expand "sltu"
3549 [(set (match_operand:DI 0 "register_operand" "")
3554 if (alpha_compare.fp_p)
3557 operands[1] = gen_rtx_LTU (DImode, alpha_compare.op0, alpha_compare.op1);
3558 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3561 (define_expand "sleu"
3562 [(set (match_operand:DI 0 "register_operand" "")
3567 if (alpha_compare.fp_p)
3570 operands[1] = gen_rtx_LEU (DImode, alpha_compare.op0, alpha_compare.op1);
3571 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3574 (define_expand "sgtu"
3575 [(set (match_operand:DI 0 "register_operand" "")
3580 if (alpha_compare.fp_p)
3583 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare.op1),
3585 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3588 (define_expand "sgeu"
3589 [(set (match_operand:DI 0 "register_operand" "")
3594 if (alpha_compare.fp_p)
3597 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare.op1),
3599 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3602 ;; These are the main define_expand's used to make conditional moves.
3604 (define_expand "movsicc"
3605 [(set (match_operand:SI 0 "register_operand" "")
3606 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3607 (match_operand:SI 2 "reg_or_8bit_operand" "")
3608 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3612 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3616 (define_expand "movdicc"
3617 [(set (match_operand:DI 0 "register_operand" "")
3618 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3619 (match_operand:DI 2 "reg_or_8bit_operand" "")
3620 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3624 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3628 (define_expand "movsfcc"
3629 [(set (match_operand:SF 0 "register_operand" "")
3630 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3631 (match_operand:SF 2 "reg_or_8bit_operand" "")
3632 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3636 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3640 (define_expand "movdfcc"
3641 [(set (match_operand:DF 0 "register_operand" "")
3642 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3643 (match_operand:DF 2 "reg_or_8bit_operand" "")
3644 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3648 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3652 ;; These define_split definitions are used in cases when comparisons have
3653 ;; not be stated in the correct way and we need to reverse the second
3654 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3655 ;; comparison that tests the result being reversed. We have one define_split
3656 ;; for each use of a comparison. They do not match valid insns and need
3657 ;; not generate valid insns.
3659 ;; We can also handle equality comparisons (and inequality comparisons in
3660 ;; cases where the resulting add cannot overflow) by doing an add followed by
3661 ;; a comparison with zero. This is faster since the addition takes one
3662 ;; less cycle than a compare when feeding into a conditional move.
3663 ;; For this case, we also have an SImode pattern since we can merge the add
3664 ;; and sign extend and the order doesn't matter.
3666 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3667 ;; operation could have been generated.
3670 [(set (match_operand:DI 0 "register_operand" "")
3672 (match_operator 1 "comparison_operator"
3673 [(match_operand:DI 2 "reg_or_0_operand" "")
3674 (match_operand:DI 3 "reg_or_cint_operand" "")])
3675 (match_operand:DI 4 "reg_or_cint_operand" "")
3676 (match_operand:DI 5 "reg_or_cint_operand" "")))
3677 (clobber (match_operand:DI 6 "register_operand" ""))]
3678 "operands[3] != const0_rtx"
3679 [(set (match_dup 6) (match_dup 7))
3681 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3683 { enum rtx_code code = GET_CODE (operands[1]);
3684 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3686 /* If we are comparing for equality with a constant and that constant
3687 appears in the arm when the register equals the constant, use the
3688 register since that is more likely to match (and to produce better code
3691 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3692 && rtx_equal_p (operands[4], operands[3]))
3693 operands[4] = operands[2];
3695 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3696 && rtx_equal_p (operands[5], operands[3]))
3697 operands[5] = operands[2];
3699 if (code == NE || code == EQ
3700 || (extended_count (operands[2], DImode, unsignedp) >= 1
3701 && extended_count (operands[3], DImode, unsignedp) >= 1))
3703 if (GET_CODE (operands[3]) == CONST_INT)
3704 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3705 GEN_INT (- INTVAL (operands[3])));
3707 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3709 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3712 else if (code == EQ || code == LE || code == LT
3713 || code == LEU || code == LTU)
3715 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3716 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3720 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3721 operands[2], operands[3]);
3722 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3727 [(set (match_operand:DI 0 "register_operand" "")
3729 (match_operator 1 "comparison_operator"
3730 [(match_operand:SI 2 "reg_or_0_operand" "")
3731 (match_operand:SI 3 "reg_or_cint_operand" "")])
3732 (match_operand:DI 4 "reg_or_8bit_operand" "")
3733 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3734 (clobber (match_operand:DI 6 "register_operand" ""))]
3735 "operands[3] != const0_rtx
3736 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3737 [(set (match_dup 6) (match_dup 7))
3739 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3741 { enum rtx_code code = GET_CODE (operands[1]);
3742 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3745 if ((code != NE && code != EQ
3746 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3747 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3750 if (GET_CODE (operands[3]) == CONST_INT)
3751 tem = gen_rtx_PLUS (SImode, operands[2],
3752 GEN_INT (- INTVAL (operands[3])));
3754 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3756 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3757 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3758 operands[6], const0_rtx);
3764 (match_operator 1 "comparison_operator"
3765 [(match_operand:DI 2 "reg_or_0_operand" "")
3766 (match_operand:DI 3 "reg_or_cint_operand" "")])
3767 (label_ref (match_operand 0 "" ""))
3769 (clobber (match_operand:DI 4 "register_operand" ""))]
3770 "operands[3] != const0_rtx"
3771 [(set (match_dup 4) (match_dup 5))
3772 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3774 { enum rtx_code code = GET_CODE (operands[1]);
3775 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3777 if (code == NE || code == EQ
3778 || (extended_count (operands[2], DImode, unsignedp) >= 1
3779 && extended_count (operands[3], DImode, unsignedp) >= 1))
3781 if (GET_CODE (operands[3]) == CONST_INT)
3782 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3783 GEN_INT (- INTVAL (operands[3])));
3785 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3787 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3790 else if (code == EQ || code == LE || code == LT
3791 || code == LEU || code == LTU)
3793 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3794 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3798 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3799 operands[2], operands[3]);
3800 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3807 (match_operator 1 "comparison_operator"
3808 [(match_operand:SI 2 "reg_or_0_operand" "")
3809 (match_operand:SI 3 "const_int_operand" "")])
3810 (label_ref (match_operand 0 "" ""))
3812 (clobber (match_operand:DI 4 "register_operand" ""))]
3813 "operands[3] != const0_rtx
3814 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3815 [(set (match_dup 4) (match_dup 5))
3816 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3820 if (GET_CODE (operands[3]) == CONST_INT)
3821 tem = gen_rtx_PLUS (SImode, operands[2],
3822 GEN_INT (- INTVAL (operands[3])));
3824 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3826 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3827 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3828 operands[4], const0_rtx);
3831 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3832 ;; This eliminates one, and sometimes two, insns when the AND can be done
3835 [(set (match_operand:DI 0 "register_operand" "")
3836 (match_operator:DI 1 "comparison_operator"
3837 [(match_operand:DI 2 "register_operand" "")
3838 (match_operand:DI 3 "const_int_operand" "")]))
3839 (clobber (match_operand:DI 4 "register_operand" ""))]
3840 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3841 && (GET_CODE (operands[1]) == GTU
3842 || GET_CODE (operands[1]) == LEU
3843 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3844 && extended_count (operands[2], DImode, 1) > 0))"
3845 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3846 (set (match_dup 0) (match_dup 6))]
3849 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3850 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3851 || GET_CODE (operands[1]) == GT)
3853 DImode, operands[4], const0_rtx);
3856 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
3859 [(set (match_operand 0 "register_operand" "")
3860 (if_then_else (match_operator 1 "signed_comparison_operator"
3861 [(match_operand:DI 2 "reg_or_0_operand" "")
3863 (match_operand 3 "const_int_operand" "")
3864 (match_operand 4 "const_int_operand" "")))]
3869 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
3870 operands[2], operands[3], operands[4]))
3876 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
3877 ;; Oh well, we match it in movcc, so it must be partially our fault.
3879 [(set (match_operand 0 "register_operand" "")
3880 (if_then_else (match_operator 1 "signed_comparison_operator"
3882 (match_operand:DI 2 "reg_or_0_operand" "")])
3883 (match_operand 3 "const_int_operand" "")
3884 (match_operand 4 "const_int_operand" "")))]
3889 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
3890 operands[0], operands[2], operands[3],
3897 (define_insn_and_split "*cmp_sadd_di"
3898 [(set (match_operand:DI 0 "register_operand" "=r")
3899 (plus:DI (if_then_else:DI
3900 (match_operator 1 "alpha_zero_comparison_operator"
3901 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3903 (match_operand:DI 3 "const48_operand" "I")
3905 (match_operand:DI 4 "sext_add_operand" "rIO")))
3906 (clobber (match_scratch:DI 5 "=r"))]
3909 "! no_new_pseudos || reload_completed"
3911 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3913 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
3917 if (! no_new_pseudos)
3918 operands[5] = gen_reg_rtx (DImode);
3919 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3920 operands[5] = operands[0];
3923 (define_insn_and_split "*cmp_sadd_si"
3924 [(set (match_operand:SI 0 "register_operand" "=r")
3925 (plus:SI (if_then_else:SI
3926 (match_operator 1 "alpha_zero_comparison_operator"
3927 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3929 (match_operand:SI 3 "const48_operand" "I")
3931 (match_operand:SI 4 "sext_add_operand" "rIO")))
3932 (clobber (match_scratch:SI 5 "=r"))]
3935 "! no_new_pseudos || reload_completed"
3937 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3939 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3943 if (! no_new_pseudos)
3944 operands[5] = gen_reg_rtx (DImode);
3945 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3946 operands[5] = operands[0];
3949 (define_insn_and_split "*cmp_sadd_sidi"
3950 [(set (match_operand:DI 0 "register_operand" "=r")
3952 (plus:SI (if_then_else:SI
3953 (match_operator 1 "alpha_zero_comparison_operator"
3954 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3956 (match_operand:SI 3 "const48_operand" "I")
3958 (match_operand:SI 4 "sext_add_operand" "rIO"))))
3959 (clobber (match_scratch:SI 5 "=r"))]
3962 "! no_new_pseudos || reload_completed"
3964 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3966 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3970 if (! no_new_pseudos)
3971 operands[5] = gen_reg_rtx (DImode);
3972 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3973 operands[5] = operands[0];
3976 (define_insn_and_split "*cmp_ssub_di"
3977 [(set (match_operand:DI 0 "register_operand" "=r")
3978 (minus:DI (if_then_else:DI
3979 (match_operator 1 "alpha_zero_comparison_operator"
3980 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3982 (match_operand:DI 3 "const48_operand" "I")
3984 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
3985 (clobber (match_scratch:DI 5 "=r"))]
3988 "! no_new_pseudos || reload_completed"
3990 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3992 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
3996 if (! no_new_pseudos)
3997 operands[5] = gen_reg_rtx (DImode);
3998 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3999 operands[5] = operands[0];
4002 (define_insn_and_split "*cmp_ssub_si"
4003 [(set (match_operand:SI 0 "register_operand" "=r")
4004 (minus:SI (if_then_else:SI
4005 (match_operator 1 "alpha_zero_comparison_operator"
4006 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4008 (match_operand:SI 3 "const48_operand" "I")
4010 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4011 (clobber (match_scratch:SI 5 "=r"))]
4014 "! no_new_pseudos || reload_completed"
4016 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4018 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4022 if (! no_new_pseudos)
4023 operands[5] = gen_reg_rtx (DImode);
4024 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4025 operands[5] = operands[0];
4028 (define_insn_and_split "*cmp_ssub_sidi"
4029 [(set (match_operand:DI 0 "register_operand" "=r")
4031 (minus:SI (if_then_else:SI
4032 (match_operator 1 "alpha_zero_comparison_operator"
4033 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4035 (match_operand:SI 3 "const48_operand" "I")
4037 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4038 (clobber (match_scratch:SI 5 "=r"))]
4041 "! no_new_pseudos || reload_completed"
4043 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4045 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4049 if (! no_new_pseudos)
4050 operands[5] = gen_reg_rtx (DImode);
4051 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4052 operands[5] = operands[0];
4055 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4056 ;; work differently, so we have different patterns for each.
4058 (define_expand "call"
4059 [(use (match_operand:DI 0 "" ""))
4060 (use (match_operand 1 "" ""))
4061 (use (match_operand 2 "" ""))
4062 (use (match_operand 3 "" ""))]
4065 { if (TARGET_WINDOWS_NT)
4066 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4067 else if (TARGET_OPEN_VMS)
4068 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4070 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4075 (define_expand "sibcall"
4076 [(call (mem:DI (match_operand 0 "" ""))
4077 (match_operand 1 "" ""))]
4078 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4081 if (GET_CODE (operands[0]) != MEM)
4083 operands[0] = XEXP (operands[0], 0);
4086 (define_expand "call_osf"
4087 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4088 (match_operand 1 "" ""))
4089 (clobber (reg:DI 27))
4090 (clobber (reg:DI 26))])]
4093 { if (GET_CODE (operands[0]) != MEM)
4096 operands[0] = XEXP (operands[0], 0);
4098 if (GET_CODE (operands[0]) != SYMBOL_REF
4099 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
4101 rtx tem = gen_rtx_REG (DImode, 27);
4102 emit_move_insn (tem, operands[0]);
4107 (define_expand "call_nt"
4108 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4109 (match_operand 1 "" ""))
4110 (clobber (reg:DI 26))])]
4113 { if (GET_CODE (operands[0]) != MEM)
4116 operands[0] = XEXP (operands[0], 0);
4117 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4118 operands[0] = force_reg (DImode, operands[0]);
4122 ;; call openvms/alpha
4123 ;; op 0: symbol ref for called function
4124 ;; op 1: next_arg_reg (argument information value for R25)
4126 (define_expand "call_vms"
4127 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4128 (match_operand 1 "" ""))
4132 (clobber (reg:DI 27))])]
4135 { if (GET_CODE (operands[0]) != MEM)
4138 operands[0] = XEXP (operands[0], 0);
4140 /* Always load AI with argument information, then handle symbolic and
4141 indirect call differently. Load RA and set operands[2] to PV in
4144 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4145 if (GET_CODE (operands[0]) == SYMBOL_REF)
4147 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4149 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4151 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4155 emit_move_insn (gen_rtx_REG (Pmode, 26),
4156 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4157 operands[2] = operands[0];
4162 (define_expand "call_value"
4163 [(use (match_operand 0 "" ""))
4164 (use (match_operand:DI 1 "" ""))
4165 (use (match_operand 2 "" ""))
4166 (use (match_operand 3 "" ""))
4167 (use (match_operand 4 "" ""))]
4170 { if (TARGET_WINDOWS_NT)
4171 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4172 else if (TARGET_OPEN_VMS)
4173 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4176 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4181 (define_expand "sibcall_value"
4182 [(set (match_operand 0 "" "")
4183 (call (mem:DI (match_operand 1 "" ""))
4184 (match_operand 2 "" "")))]
4185 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4188 if (GET_CODE (operands[1]) != MEM)
4190 operands[1] = XEXP (operands[1], 0);
4193 (define_expand "call_value_osf"
4194 [(parallel [(set (match_operand 0 "" "")
4195 (call (mem:DI (match_operand 1 "" ""))
4196 (match_operand 2 "" "")))
4197 (clobber (reg:DI 27))
4198 (clobber (reg:DI 26))])]
4201 { if (GET_CODE (operands[1]) != MEM)
4204 operands[1] = XEXP (operands[1], 0);
4206 if (GET_CODE (operands[1]) != SYMBOL_REF
4207 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
4209 rtx tem = gen_rtx_REG (DImode, 27);
4210 emit_move_insn (tem, operands[1]);
4215 (define_expand "call_value_nt"
4216 [(parallel [(set (match_operand 0 "" "")
4217 (call (mem:DI (match_operand 1 "" ""))
4218 (match_operand 2 "" "")))
4219 (clobber (reg:DI 26))])]
4222 { if (GET_CODE (operands[1]) != MEM)
4225 operands[1] = XEXP (operands[1], 0);
4226 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4227 operands[1] = force_reg (DImode, operands[1]);
4230 (define_expand "call_value_vms"
4231 [(parallel [(set (match_operand 0 "" "")
4232 (call (mem:DI (match_operand:DI 1 "" ""))
4233 (match_operand 2 "" "")))
4237 (clobber (reg:DI 27))])]
4240 { if (GET_CODE (operands[1]) != MEM)
4243 operands[1] = XEXP (operands[1], 0);
4245 /* Always load AI with argument information, then handle symbolic and
4246 indirect call differently. Load RA and set operands[3] to PV in
4249 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4250 if (GET_CODE (operands[1]) == SYMBOL_REF)
4252 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4254 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4256 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4260 emit_move_insn (gen_rtx_REG (Pmode, 26),
4261 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4262 operands[3] = operands[1];
4266 (define_insn "*call_osf_1"
4267 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4268 (match_operand 1 "" ""))
4269 (clobber (reg:DI 27))
4270 (clobber (reg:DI 26))]
4271 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4273 jsr $26,($27),0\;ldgp $29,0($26)
4275 jsr $26,%0\;ldgp $29,0($26)"
4276 [(set_attr "type" "jsr")
4277 (set_attr "length" "12,*,16")])
4279 (define_insn "*sibcall_osf_1"
4280 [(call (mem:DI (match_operand:DI 0 "call_operand" "R,i"))
4281 (match_operand 1 "" ""))]
4282 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4286 [(set_attr "type" "jsr")
4287 (set_attr "length" "*,8")])
4289 (define_insn "*call_nt_1"
4290 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4291 (match_operand 1 "" ""))
4292 (clobber (reg:DI 26))]
4298 [(set_attr "type" "jsr")
4299 (set_attr "length" "*,*,12")])
4301 (define_insn "*call_vms_1"
4302 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
4303 (match_operand 1 "" ""))
4304 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4307 (clobber (reg:DI 27))]
4310 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4311 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4312 [(set_attr "type" "jsr")
4313 (set_attr "length" "12,16")])
4315 ;; Call subroutine returning any type.
4317 (define_expand "untyped_call"
4318 [(parallel [(call (match_operand 0 "" "")
4320 (match_operand 1 "" "")
4321 (match_operand 2 "" "")])]
4327 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4329 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4331 rtx set = XVECEXP (operands[2], 0, i);
4332 emit_move_insn (SET_DEST (set), SET_SRC (set));
4335 /* The optimizer does not know that the call sets the function value
4336 registers we stored in the result block. We avoid problems by
4337 claiming that all hard registers are used and clobbered at this
4339 emit_insn (gen_blockage ());
4344 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4345 ;; all of memory. This blocks insns from being moved across this point.
4347 (define_insn "blockage"
4348 [(unspec_volatile [(const_int 0)] 1)]
4351 [(set_attr "length" "0")])
4355 (label_ref (match_operand 0 "" "")))]
4358 [(set_attr "type" "ibr")])
4360 (define_expand "return"
4365 (define_insn "*return_internal"
4369 [(set_attr "type" "ibr")])
4371 (define_insn "indirect_jump"
4372 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4375 [(set_attr "type" "ibr")])
4377 (define_expand "tablejump"
4378 [(use (match_operand:SI 0 "register_operand" ""))
4379 (use (match_operand:SI 1 "" ""))]
4383 if (TARGET_WINDOWS_NT)
4384 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4385 else if (TARGET_OPEN_VMS)
4386 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4388 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4393 (define_expand "tablejump_osf"
4395 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4396 (parallel [(set (pc)
4397 (plus:DI (match_dup 3)
4398 (label_ref (match_operand 1 "" ""))))
4399 (clobber (match_scratch:DI 2 "=r"))])]
4402 { operands[3] = gen_reg_rtx (DImode); }")
4404 (define_expand "tablejump_nt"
4406 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4407 (parallel [(set (pc)
4409 (use (label_ref (match_operand 1 "" "")))])]
4412 { operands[3] = gen_reg_rtx (DImode); }")
4415 ;; tablejump, openVMS way
4417 ;; op 1: label preceding jump-table
4419 (define_expand "tablejump_vms"
4421 (match_operand:DI 0 "register_operand" ""))
4423 (plus:DI (match_dup 2)
4424 (label_ref (match_operand 1 "" ""))))]
4427 { operands[2] = gen_reg_rtx (DImode); }")
4431 (plus (match_operand:DI 0 "register_operand" "r")
4432 (label_ref (match_operand 1 "" ""))))
4433 (clobber (match_scratch:DI 2 "=r"))]
4434 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
4435 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4436 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4438 { rtx best_label = 0;
4439 rtx jump_table_insn = next_active_insn (operands[1]);
4441 if (GET_CODE (jump_table_insn) == JUMP_INSN
4442 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4444 rtx jump_table = PATTERN (jump_table_insn);
4445 int n_labels = XVECLEN (jump_table, 1);
4446 int best_count = -1;
4449 for (i = 0; i < n_labels; i++)
4453 for (j = i + 1; j < n_labels; j++)
4454 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4455 == XEXP (XVECEXP (jump_table, 1, j), 0))
4458 if (count > best_count)
4459 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4465 operands[3] = best_label;
4466 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
4469 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
4471 [(set_attr "type" "ibr")
4472 (set_attr "length" "8")])
4476 (match_operand:DI 0 "register_operand" "r"))
4477 (use (label_ref (match_operand 1 "" "")))]
4478 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
4479 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4480 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4482 { rtx best_label = 0;
4483 rtx jump_table_insn = next_active_insn (operands[1]);
4485 if (GET_CODE (jump_table_insn) == JUMP_INSN
4486 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4488 rtx jump_table = PATTERN (jump_table_insn);
4489 int n_labels = XVECLEN (jump_table, 1);
4490 int best_count = -1;
4493 for (i = 0; i < n_labels; i++)
4497 for (j = i + 1; j < n_labels; j++)
4498 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4499 == XEXP (XVECEXP (jump_table, 1, j), 0))
4502 if (count > best_count)
4503 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4509 operands[2] = best_label;
4510 return \"jmp $31,(%0),%2\";
4513 return \"jmp $31,(%0),0\";
4515 [(set_attr "type" "ibr")])
4518 ;; op 0 is table offset
4519 ;; op 1 is table label
4524 (plus (match_operand:DI 0 "register_operand" "r")
4525 (label_ref (match_operand 1 "" ""))))]
4528 [(set_attr "type" "ibr")])
4530 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4531 ;; want to have to include pal.h in our .s file.
4533 ;; Technically the type for call_pal is jsr, but we use that for determining
4534 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4537 [(unspec_volatile [(const_int 0)] 0)]
4540 [(set_attr "type" "ibr")])
4542 ;; Finally, we have the basic data motion insns. The byte and word insns
4543 ;; are done via define_expand. Start with the floating-point insns, since
4544 ;; they are simpler.
4547 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4548 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4549 "TARGET_FPREGS && ! TARGET_FIX
4550 && (register_operand (operands[0], SFmode)
4551 || reg_or_fp0_operand (operands[1], SFmode))"
4559 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4562 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4563 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4564 "TARGET_FPREGS && TARGET_FIX
4565 && (register_operand (operands[0], SFmode)
4566 || reg_or_fp0_operand (operands[1], SFmode))"
4576 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4579 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4580 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4582 && (register_operand (operands[0], SFmode)
4583 || reg_or_fp0_operand (operands[1], SFmode))"
4588 [(set_attr "type" "ilog,ild,ist")])
4591 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4592 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4593 "TARGET_FPREGS && ! TARGET_FIX
4594 && (register_operand (operands[0], DFmode)
4595 || reg_or_fp0_operand (operands[1], DFmode))"
4603 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4606 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4607 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4608 "TARGET_FPREGS && TARGET_FIX
4609 && (register_operand (operands[0], DFmode)
4610 || reg_or_fp0_operand (operands[1], DFmode))"
4620 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4623 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4624 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4626 && (register_operand (operands[0], DFmode)
4627 || reg_or_fp0_operand (operands[1], DFmode))"
4632 [(set_attr "type" "ilog,ild,ist")])
4634 ;; Subregs suck for register allocation. Pretend we can move TFmode
4635 ;; data between general registers until after reload.
4637 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4638 (match_operand:TF 1 "input_operand" "roG,r"))]
4639 "register_operand (operands[0], TFmode)
4640 || reg_or_fp0_operand (operands[1], TFmode)"
4644 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4645 (match_operand:TF 1 "input_operand" ""))]
4647 [(set (match_dup 0) (match_dup 2))
4648 (set (match_dup 1) (match_dup 3))]
4651 alpha_split_tfmode_pair (operands);
4652 if (rtx_equal_p (operands[0], operands[3]))
4655 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4656 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4660 (define_expand "movsf"
4661 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4662 (match_operand:SF 1 "general_operand" ""))]
4666 if (GET_CODE (operands[0]) == MEM
4667 && ! reg_or_fp0_operand (operands[1], SFmode))
4668 operands[1] = force_reg (SFmode, operands[1]);
4671 (define_expand "movdf"
4672 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4673 (match_operand:DF 1 "general_operand" ""))]
4677 if (GET_CODE (operands[0]) == MEM
4678 && ! reg_or_fp0_operand (operands[1], DFmode))
4679 operands[1] = force_reg (DFmode, operands[1]);
4682 (define_expand "movtf"
4683 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4684 (match_operand:TF 1 "general_operand" ""))]
4688 if (GET_CODE (operands[0]) == MEM
4689 && ! reg_or_fp0_operand (operands[1], TFmode))
4690 operands[1] = force_reg (TFmode, operands[1]);
4694 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4695 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4696 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4697 && (register_operand (operands[0], SImode)
4698 || reg_or_0_operand (operands[1], SImode))"
4708 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4711 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4712 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4713 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4714 && (register_operand (operands[0], SImode)
4715 || reg_or_0_operand (operands[1], SImode))"
4727 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4730 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4731 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4732 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4733 && (register_operand (operands[0], SImode)
4734 || reg_or_0_operand (operands[1], SImode))"
4745 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4748 [(set (match_operand:HI 0 "register_operand" "=r,r")
4749 (match_operand:HI 1 "input_operand" "rJ,n"))]
4751 && (register_operand (operands[0], HImode)
4752 || register_operand (operands[1], HImode))"
4756 [(set_attr "type" "ilog,iadd")])
4759 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4760 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4762 && (register_operand (operands[0], HImode)
4763 || reg_or_0_operand (operands[1], HImode))"
4769 [(set_attr "type" "ilog,iadd,ild,ist")])
4772 [(set (match_operand:QI 0 "register_operand" "=r,r")
4773 (match_operand:QI 1 "input_operand" "rJ,n"))]
4775 && (register_operand (operands[0], QImode)
4776 || register_operand (operands[1], QImode))"
4780 [(set_attr "type" "ilog,iadd")])
4783 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4784 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4786 && (register_operand (operands[0], QImode)
4787 || reg_or_0_operand (operands[1], QImode))"
4793 [(set_attr "type" "ilog,iadd,ild,ist")])
4795 ;; We do two major things here: handle mem->mem and construct long
4798 (define_expand "movsi"
4799 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4800 (match_operand:SI 1 "general_operand" ""))]
4804 if (GET_CODE (operands[0]) == MEM
4805 && ! reg_or_0_operand (operands[1], SImode))
4806 operands[1] = force_reg (SImode, operands[1]);
4808 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4810 else if (GET_CODE (operands[1]) == CONST_INT)
4813 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4814 if (rtx_equal_p (operands[0], operands[1]))
4819 ;; Split a load of a large constant into the appropriate two-insn
4823 [(set (match_operand:SI 0 "register_operand" "")
4824 (match_operand:SI 1 "const_int_operand" ""))]
4825 "! add_operand (operands[1], SImode)"
4826 [(set (match_dup 0) (match_dup 2))
4827 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4830 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4832 if (tem == operands[0])
4839 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4840 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4842 && (register_operand (operands[0], DImode)
4843 || reg_or_0_operand (operands[1], DImode))"
4854 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4857 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4858 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4860 && (register_operand (operands[0], DImode)
4861 || reg_or_0_operand (operands[1], DImode))"
4874 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4876 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4877 ;; memory, and construct long 32-bit constants.
4879 (define_expand "movdi"
4880 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4881 (match_operand:DI 1 "general_operand" ""))]
4887 if (GET_CODE (operands[0]) == MEM
4888 && ! reg_or_0_operand (operands[1], DImode))
4889 operands[1] = force_reg (DImode, operands[1]);
4891 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4893 else if (GET_CODE (operands[1]) == CONST_INT
4894 && (tem = alpha_emit_set_const (operands[0], DImode,
4895 INTVAL (operands[1]), 3)) != 0)
4897 if (rtx_equal_p (tem, operands[0]))
4902 else if (CONSTANT_P (operands[1]))
4904 if (TARGET_BUILD_CONSTANTS)
4906 HOST_WIDE_INT i0, i1;
4908 if (GET_CODE (operands[1]) == CONST_INT)
4910 i0 = INTVAL (operands[1]);
4913 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4915 #if HOST_BITS_PER_WIDE_INT >= 64
4916 i0 = CONST_DOUBLE_LOW (operands[1]);
4919 i0 = CONST_DOUBLE_LOW (operands[1]);
4920 i1 = CONST_DOUBLE_HIGH (operands[1]);
4926 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4927 if (rtx_equal_p (tem, operands[0]))
4934 operands[1] = force_const_mem (DImode, operands[1]);
4935 if (reload_in_progress)
4937 emit_move_insn (operands[0], XEXP (operands[1], 0));
4938 operands[1] = copy_rtx (operands[1]);
4939 XEXP (operands[1], 0) = operands[0];
4942 operands[1] = validize_mem (operands[1]);
4949 ;; Split a load of a large constant into the appropriate two-insn
4953 [(set (match_operand:DI 0 "register_operand" "")
4954 (match_operand:DI 1 "const_int_operand" ""))]
4955 "! add_operand (operands[1], DImode)"
4956 [(set (match_dup 0) (match_dup 2))
4957 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4960 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4962 if (tem == operands[0])
4968 ;; These are the partial-word cases.
4970 ;; First we have the code to load an aligned word. Operand 0 is the register
4971 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4972 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4973 ;; number of bits within the word that the value is. Operand 3 is an SImode
4974 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4975 ;; same register. It is allowed to conflict with operand 1 as well.
4977 (define_expand "aligned_loadqi"
4978 [(set (match_operand:SI 3 "register_operand" "")
4979 (match_operand:SI 1 "memory_operand" ""))
4980 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4981 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4983 (match_operand:DI 2 "const_int_operand" "")))]
4988 (define_expand "aligned_loadhi"
4989 [(set (match_operand:SI 3 "register_operand" "")
4990 (match_operand:SI 1 "memory_operand" ""))
4991 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4992 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4994 (match_operand:DI 2 "const_int_operand" "")))]
4999 ;; Similar for unaligned loads, where we use the sequence from the
5000 ;; Alpha Architecture manual.
5002 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5003 ;; operand 3 can overlap the input and output registers.
5005 (define_expand "unaligned_loadqi"
5006 [(set (match_operand:DI 2 "register_operand" "")
5007 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5009 (set (match_operand:DI 3 "register_operand" "")
5011 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5012 (zero_extract:DI (match_dup 2)
5014 (ashift:DI (match_dup 3) (const_int 3))))]
5018 (define_expand "unaligned_loadhi"
5019 [(set (match_operand:DI 2 "register_operand" "")
5020 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5022 (set (match_operand:DI 3 "register_operand" "")
5024 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5025 (zero_extract:DI (match_dup 2)
5027 (ashift:DI (match_dup 3) (const_int 3))))]
5031 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5032 ;; aligned SImode MEM. Operand 1 is the register containing the
5033 ;; byte or word to store. Operand 2 is the number of bits within the word that
5034 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5036 (define_expand "aligned_store"
5037 [(set (match_operand:SI 3 "register_operand" "")
5038 (match_operand:SI 0 "memory_operand" ""))
5039 (set (subreg:DI (match_dup 3) 0)
5040 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5041 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5042 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5043 (match_operand:DI 2 "const_int_operand" "")))
5044 (set (subreg:DI (match_dup 4) 0)
5045 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5046 (set (match_dup 0) (match_dup 4))]
5049 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5050 << INTVAL (operands[2])));
5053 ;; For the unaligned byte and halfword cases, we use code similar to that
5054 ;; in the ;; Architecture book, but reordered to lower the number of registers
5055 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5056 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5057 ;; be the same temporary, if desired. If the address is in a register,
5058 ;; operand 2 can be that register.
5060 (define_expand "unaligned_storeqi"
5061 [(set (match_operand:DI 3 "register_operand" "")
5062 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5064 (set (match_operand:DI 2 "register_operand" "")
5067 (and:DI (not:DI (ashift:DI (const_int 255)
5068 (ashift:DI (match_dup 2) (const_int 3))))
5070 (set (match_operand:DI 4 "register_operand" "")
5071 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5072 (ashift:DI (match_dup 2) (const_int 3))))
5073 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5074 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5079 (define_expand "unaligned_storehi"
5080 [(set (match_operand:DI 3 "register_operand" "")
5081 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5083 (set (match_operand:DI 2 "register_operand" "")
5086 (and:DI (not:DI (ashift:DI (const_int 65535)
5087 (ashift:DI (match_dup 2) (const_int 3))))
5089 (set (match_operand:DI 4 "register_operand" "")
5090 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5091 (ashift:DI (match_dup 2) (const_int 3))))
5092 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5093 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5098 ;; Here are the define_expand's for QI and HI moves that use the above
5099 ;; patterns. We have the normal sets, plus the ones that need scratch
5100 ;; registers for reload.
5102 (define_expand "movqi"
5103 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5104 (match_operand:QI 1 "general_operand" ""))]
5110 if (GET_CODE (operands[0]) == MEM
5111 && ! reg_or_0_operand (operands[1], QImode))
5112 operands[1] = force_reg (QImode, operands[1]);
5114 if (GET_CODE (operands[1]) == CONST_INT
5115 && ! input_operand (operands[1], QImode))
5117 operands[1] = alpha_emit_set_const (operands[0], QImode,
5118 INTVAL (operands[1]), 3);
5120 if (rtx_equal_p (operands[0], operands[1]))
5127 /* If the output is not a register, the input must be. */
5128 if (GET_CODE (operands[0]) == MEM)
5129 operands[1] = force_reg (QImode, operands[1]);
5131 /* Handle four memory cases, unaligned and aligned for either the input
5132 or the output. The only case where we can be called during reload is
5133 for aligned loads; all other cases require temporaries. */
5135 if (GET_CODE (operands[1]) == MEM
5136 || (GET_CODE (operands[1]) == SUBREG
5137 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5138 || (reload_in_progress && GET_CODE (operands[1]) == REG
5139 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5140 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5141 && GET_CODE (SUBREG_REG (operands[1])) == REG
5142 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5144 if (aligned_memory_operand (operands[1], QImode))
5146 if (reload_in_progress)
5148 emit_insn (gen_reload_inqi_help
5149 (operands[0], operands[1],
5150 gen_rtx_REG (SImode, REGNO (operands[0]))));
5154 rtx aligned_mem, bitnum;
5155 rtx scratch = gen_reg_rtx (SImode);
5157 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5159 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5165 /* Don't pass these as parameters since that makes the generated
5166 code depend on parameter evaluation order which will cause
5167 bootstrap failures. */
5169 rtx temp1 = gen_reg_rtx (DImode);
5170 rtx temp2 = gen_reg_rtx (DImode);
5172 = gen_unaligned_loadqi (operands[0],
5173 get_unaligned_address (operands[1], 0),
5176 alpha_set_memflags (seq, operands[1]);
5183 else if (GET_CODE (operands[0]) == MEM
5184 || (GET_CODE (operands[0]) == SUBREG
5185 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5186 || (reload_in_progress && GET_CODE (operands[0]) == REG
5187 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5188 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5189 && GET_CODE (SUBREG_REG (operands[0])) == REG
5190 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5192 if (aligned_memory_operand (operands[0], QImode))
5194 rtx aligned_mem, bitnum;
5195 rtx temp1 = gen_reg_rtx (SImode);
5196 rtx temp2 = gen_reg_rtx (SImode);
5198 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5200 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5205 rtx temp1 = gen_reg_rtx (DImode);
5206 rtx temp2 = gen_reg_rtx (DImode);
5207 rtx temp3 = gen_reg_rtx (DImode);
5209 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
5210 operands[1], temp1, temp2, temp3);
5212 alpha_set_memflags (seq, operands[0]);
5220 (define_expand "movhi"
5221 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5222 (match_operand:HI 1 "general_operand" ""))]
5228 if (GET_CODE (operands[0]) == MEM
5229 && ! reg_or_0_operand (operands[1], HImode))
5230 operands[1] = force_reg (HImode, operands[1]);
5232 if (GET_CODE (operands[1]) == CONST_INT
5233 && ! input_operand (operands[1], HImode))
5235 operands[1] = alpha_emit_set_const (operands[0], HImode,
5236 INTVAL (operands[1]), 3);
5238 if (rtx_equal_p (operands[0], operands[1]))
5245 /* If the output is not a register, the input must be. */
5246 if (GET_CODE (operands[0]) == MEM)
5247 operands[1] = force_reg (HImode, operands[1]);
5249 /* Handle four memory cases, unaligned and aligned for either the input
5250 or the output. The only case where we can be called during reload is
5251 for aligned loads; all other cases require temporaries. */
5253 if (GET_CODE (operands[1]) == MEM
5254 || (GET_CODE (operands[1]) == SUBREG
5255 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5256 || (reload_in_progress && GET_CODE (operands[1]) == REG
5257 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5258 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5259 && GET_CODE (SUBREG_REG (operands[1])) == REG
5260 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5262 if (aligned_memory_operand (operands[1], HImode))
5264 if (reload_in_progress)
5266 emit_insn (gen_reload_inhi_help
5267 (operands[0], operands[1],
5268 gen_rtx_REG (SImode, REGNO (operands[0]))));
5272 rtx aligned_mem, bitnum;
5273 rtx scratch = gen_reg_rtx (SImode);
5275 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5277 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5283 /* Don't pass these as parameters since that makes the generated
5284 code depend on parameter evaluation order which will cause
5285 bootstrap failures. */
5287 rtx temp1 = gen_reg_rtx (DImode);
5288 rtx temp2 = gen_reg_rtx (DImode);
5290 = gen_unaligned_loadhi (operands[0],
5291 get_unaligned_address (operands[1], 0),
5294 alpha_set_memflags (seq, operands[1]);
5301 else if (GET_CODE (operands[0]) == MEM
5302 || (GET_CODE (operands[0]) == SUBREG
5303 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5304 || (reload_in_progress && GET_CODE (operands[0]) == REG
5305 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5306 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5307 && GET_CODE (SUBREG_REG (operands[0])) == REG
5308 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5310 if (aligned_memory_operand (operands[0], HImode))
5312 rtx aligned_mem, bitnum;
5313 rtx temp1 = gen_reg_rtx (SImode);
5314 rtx temp2 = gen_reg_rtx (SImode);
5316 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5318 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5323 rtx temp1 = gen_reg_rtx (DImode);
5324 rtx temp2 = gen_reg_rtx (DImode);
5325 rtx temp3 = gen_reg_rtx (DImode);
5327 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
5328 operands[1], temp1, temp2, temp3);
5330 alpha_set_memflags (seq, operands[0]);
5339 ;; Here are the versions for reload. Note that in the unaligned cases
5340 ;; we know that the operand must not be a pseudo-register because stack
5341 ;; slots are always aligned references.
5343 (define_expand "reload_inqi"
5344 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5345 (match_operand:QI 1 "any_memory_operand" "m")
5346 (match_operand:TI 2 "register_operand" "=&r")])]
5352 if (GET_CODE (operands[1]) != MEM)
5355 if (aligned_memory_operand (operands[1], QImode))
5357 seq = gen_reload_inqi_help (operands[0], operands[1],
5358 gen_rtx_REG (SImode, REGNO (operands[2])));
5364 /* It is possible that one of the registers we got for operands[2]
5365 might coincide with that of operands[0] (which is why we made
5366 it TImode). Pick the other one to use as our scratch. */
5367 if (REGNO (operands[0]) == REGNO (operands[2]))
5368 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5370 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5372 addr = get_unaligned_address (operands[1], 0);
5373 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5374 gen_rtx_REG (DImode, REGNO (operands[0])));
5375 alpha_set_memflags (seq, operands[1]);
5381 (define_expand "reload_inhi"
5382 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5383 (match_operand:HI 1 "any_memory_operand" "m")
5384 (match_operand:TI 2 "register_operand" "=&r")])]
5390 if (GET_CODE (operands[1]) != MEM)
5393 if (aligned_memory_operand (operands[1], HImode))
5395 seq = gen_reload_inhi_help (operands[0], operands[1],
5396 gen_rtx_REG (SImode, REGNO (operands[2])));
5402 /* It is possible that one of the registers we got for operands[2]
5403 might coincide with that of operands[0] (which is why we made
5404 it TImode). Pick the other one to use as our scratch. */
5405 if (REGNO (operands[0]) == REGNO (operands[2]))
5406 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5408 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5410 addr = get_unaligned_address (operands[1], 0);
5411 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5412 gen_rtx_REG (DImode, REGNO (operands[0])));
5413 alpha_set_memflags (seq, operands[1]);
5419 (define_expand "reload_outqi"
5420 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5421 (match_operand:QI 1 "register_operand" "r")
5422 (match_operand:TI 2 "register_operand" "=&r")])]
5426 if (GET_CODE (operands[0]) != MEM)
5429 if (aligned_memory_operand (operands[0], QImode))
5431 emit_insn (gen_reload_outqi_help
5432 (operands[0], operands[1],
5433 gen_rtx_REG (SImode, REGNO (operands[2])),
5434 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5438 rtx addr = get_unaligned_address (operands[0], 0);
5439 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5440 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5441 rtx scratch3 = scratch1;
5444 if (GET_CODE (addr) == REG)
5447 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5448 scratch2, scratch3);
5449 alpha_set_memflags (seq, operands[0]);
5455 (define_expand "reload_outhi"
5456 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5457 (match_operand:HI 1 "register_operand" "r")
5458 (match_operand:TI 2 "register_operand" "=&r")])]
5462 if (GET_CODE (operands[0]) != MEM)
5465 if (aligned_memory_operand (operands[0], HImode))
5467 emit_insn (gen_reload_outhi_help
5468 (operands[0], operands[1],
5469 gen_rtx_REG (SImode, REGNO (operands[2])),
5470 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5474 rtx addr = get_unaligned_address (operands[0], 0);
5475 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5476 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5477 rtx scratch3 = scratch1;
5480 if (GET_CODE (addr) == REG)
5483 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5484 scratch2, scratch3);
5485 alpha_set_memflags (seq, operands[0]);
5491 ;; Helpers for the above. The way reload is structured, we can't
5492 ;; always get a proper address for a stack slot during reload_foo
5493 ;; expansion, so we must delay our address manipulations until after.
5495 (define_insn "reload_inqi_help"
5496 [(set (match_operand:QI 0 "register_operand" "=r")
5497 (match_operand:QI 1 "memory_operand" "m"))
5498 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5499 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5502 (define_insn "reload_inhi_help"
5503 [(set (match_operand:HI 0 "register_operand" "=r")
5504 (match_operand:HI 1 "memory_operand" "m"))
5505 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5506 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5509 (define_insn "reload_outqi_help"
5510 [(set (match_operand:QI 0 "memory_operand" "=m")
5511 (match_operand:QI 1 "register_operand" "r"))
5512 (clobber (match_operand:SI 2 "register_operand" "=r"))
5513 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5514 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5517 (define_insn "reload_outhi_help"
5518 [(set (match_operand:HI 0 "memory_operand" "=m")
5519 (match_operand:HI 1 "register_operand" "r"))
5520 (clobber (match_operand:SI 2 "register_operand" "=r"))
5521 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5522 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5526 [(set (match_operand:QI 0 "register_operand" "")
5527 (match_operand:QI 1 "memory_operand" ""))
5528 (clobber (match_operand:SI 2 "register_operand" ""))]
5529 "! TARGET_BWX && reload_completed"
5533 rtx aligned_mem, bitnum;
5534 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5535 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5541 [(set (match_operand:HI 0 "register_operand" "")
5542 (match_operand:HI 1 "memory_operand" ""))
5543 (clobber (match_operand:SI 2 "register_operand" ""))]
5544 "! TARGET_BWX && reload_completed"
5548 rtx aligned_mem, bitnum;
5549 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5550 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5556 [(set (match_operand:QI 0 "memory_operand" "")
5557 (match_operand:QI 1 "register_operand" ""))
5558 (clobber (match_operand:SI 2 "register_operand" ""))
5559 (clobber (match_operand:SI 3 "register_operand" ""))]
5560 "! TARGET_BWX && reload_completed"
5564 rtx aligned_mem, bitnum;
5565 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5566 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5567 operands[2], operands[3]));
5572 [(set (match_operand:HI 0 "memory_operand" "")
5573 (match_operand:HI 1 "register_operand" ""))
5574 (clobber (match_operand:SI 2 "register_operand" ""))
5575 (clobber (match_operand:SI 3 "register_operand" ""))]
5576 "! TARGET_BWX && reload_completed"
5580 rtx aligned_mem, bitnum;
5581 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5582 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5583 operands[2], operands[3]));
5587 ;; Bit field extract patterns which use ext[wlq][lh]
5589 (define_expand "extv"
5590 [(set (match_operand:DI 0 "register_operand" "")
5591 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5592 (match_operand:DI 2 "immediate_operand" "")
5593 (match_operand:DI 3 "immediate_operand" "")))]
5597 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5598 if (INTVAL (operands[3]) % 8 != 0
5599 || (INTVAL (operands[2]) != 16
5600 && INTVAL (operands[2]) != 32
5601 && INTVAL (operands[2]) != 64))
5604 /* From mips.md: extract_bit_field doesn't verify that our source
5605 matches the predicate, so we force it to be a MEM here. */
5606 if (GET_CODE (operands[1]) != MEM)
5609 alpha_expand_unaligned_load (operands[0], operands[1],
5610 INTVAL (operands[2]) / 8,
5611 INTVAL (operands[3]) / 8, 1);
5615 (define_expand "extzv"
5616 [(set (match_operand:DI 0 "register_operand" "")
5617 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5618 (match_operand:DI 2 "immediate_operand" "")
5619 (match_operand:DI 3 "immediate_operand" "")))]
5623 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5624 if (INTVAL (operands[3]) % 8 != 0
5625 || (INTVAL (operands[2]) != 8
5626 && INTVAL (operands[2]) != 16
5627 && INTVAL (operands[2]) != 32
5628 && INTVAL (operands[2]) != 64))
5631 if (GET_CODE (operands[1]) == MEM)
5633 /* Fail 8 bit fields, falling back on a simple byte load. */
5634 if (INTVAL (operands[2]) == 8)
5637 alpha_expand_unaligned_load (operands[0], operands[1],
5638 INTVAL (operands[2]) / 8,
5639 INTVAL (operands[3]) / 8, 0);
5644 (define_expand "insv"
5645 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5646 (match_operand:DI 1 "immediate_operand" "")
5647 (match_operand:DI 2 "immediate_operand" ""))
5648 (match_operand:DI 3 "register_operand" ""))]
5652 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5653 if (INTVAL (operands[2]) % 8 != 0
5654 || (INTVAL (operands[1]) != 16
5655 && INTVAL (operands[1]) != 32
5656 && INTVAL (operands[1]) != 64))
5659 /* From mips.md: store_bit_field doesn't verify that our source
5660 matches the predicate, so we force it to be a MEM here. */
5661 if (GET_CODE (operands[0]) != MEM)
5664 alpha_expand_unaligned_store (operands[0], operands[3],
5665 INTVAL (operands[1]) / 8,
5666 INTVAL (operands[2]) / 8);
5672 ;; Block move/clear, see alpha.c for more details.
5673 ;; Argument 0 is the destination
5674 ;; Argument 1 is the source
5675 ;; Argument 2 is the length
5676 ;; Argument 3 is the alignment
5678 (define_expand "movstrqi"
5679 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5680 (match_operand:BLK 1 "memory_operand" ""))
5681 (use (match_operand:DI 2 "immediate_operand" ""))
5682 (use (match_operand:DI 3 "immediate_operand" ""))])]
5686 if (alpha_expand_block_move (operands))
5692 (define_expand "clrstrqi"
5693 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5695 (use (match_operand:DI 1 "immediate_operand" ""))
5696 (use (match_operand:DI 2 "immediate_operand" ""))])]
5700 if (alpha_expand_block_clear (operands))
5706 ;; Subroutine of stack space allocation. Perform a stack probe.
5707 (define_expand "probe_stack"
5708 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5712 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5713 INTVAL (operands[0])));
5714 MEM_VOLATILE_P (operands[1]) = 1;
5716 operands[0] = const0_rtx;
5719 ;; This is how we allocate stack space. If we are allocating a
5720 ;; constant amount of space and we know it is less than 4096
5721 ;; bytes, we need do nothing.
5723 ;; If it is more than 4096 bytes, we need to probe the stack
5725 (define_expand "allocate_stack"
5727 (plus:DI (reg:DI 30)
5728 (match_operand:DI 1 "reg_or_cint_operand" "")))
5729 (set (match_operand:DI 0 "register_operand" "=r")
5734 if (GET_CODE (operands[1]) == CONST_INT
5735 && INTVAL (operands[1]) < 32768)
5737 if (INTVAL (operands[1]) >= 4096)
5739 /* We do this the same way as in the prologue and generate explicit
5740 probes. Then we update the stack by the constant. */
5744 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5745 while (probed + 8192 < INTVAL (operands[1]))
5746 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5748 if (probed + 4096 < INTVAL (operands[1]))
5749 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5752 operands[1] = GEN_INT (- INTVAL (operands[1]));
5753 operands[2] = virtual_stack_dynamic_rtx;
5758 rtx loop_label = gen_label_rtx ();
5759 rtx want = gen_reg_rtx (Pmode);
5760 rtx tmp = gen_reg_rtx (Pmode);
5763 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5764 force_reg (Pmode, operands[1])));
5765 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5767 if (GET_CODE (operands[1]) != CONST_INT)
5769 out_label = gen_label_rtx ();
5770 emit_insn (gen_cmpdi (want, tmp));
5771 emit_jump_insn (gen_bgeu (out_label));
5774 emit_label (loop_label);
5775 memref = gen_rtx_MEM (DImode, tmp);
5776 MEM_VOLATILE_P (memref) = 1;
5777 emit_move_insn (memref, const0_rtx);
5778 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5779 emit_insn (gen_cmpdi (tmp, want));
5780 emit_jump_insn (gen_bgtu (loop_label));
5782 memref = gen_rtx_MEM (DImode, want);
5783 MEM_VOLATILE_P (memref) = 1;
5784 emit_move_insn (memref, const0_rtx);
5787 emit_label (out_label);
5789 emit_move_insn (stack_pointer_rtx, want);
5790 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5795 ;; This is used by alpha_expand_prolog to do the same thing as above,
5796 ;; except we cannot at that time generate new basic blocks, so we hide
5797 ;; the loop in this one insn.
5799 (define_insn "prologue_stack_probe_loop"
5800 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5801 (match_operand:DI 1 "register_operand" "r")] 5)]
5805 operands[2] = gen_label_rtx ();
5806 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5807 CODE_LABEL_NUMBER (operands[2]));
5809 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5811 [(set_attr "length" "16")
5812 (set_attr "type" "multi")])
5814 (define_expand "prologue"
5815 [(clobber (const_int 0))]
5819 alpha_expand_prologue ();
5823 ;; These take care of emitting the ldgp insn in the prologue. This will be
5824 ;; an lda/ldah pair and we want to align them properly. So we have two
5825 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
5826 ;; and the second of which emits nothing. However, both are marked as type
5827 ;; IADD (the default) so the alignment code in alpha.c does the right thing
5830 (define_expand "prologue_ldgp"
5831 [(unspec_volatile [(const_int 0)] 9)
5832 (unspec_volatile [(const_int 0)] 10)]
5836 (define_insn "*prologue_ldgp_1"
5837 [(unspec_volatile [(const_int 0)] 9)]
5838 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5839 "ldgp $29,0($27)\\n$%~..ng:")
5841 (define_insn "*prologue_ldgp_2"
5842 [(unspec_volatile [(const_int 0)] 10)]
5843 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5846 ;; The _mcount profiling hook has special calling conventions, and
5847 ;; does not clobber all the registers that a normal call would. So
5848 ;; hide the fact this is a call at all.
5850 (define_insn "prologue_mcount"
5851 [(unspec_volatile [(const_int 0)] 8)]
5853 "lda $28,_mcount\;jsr $28,($28),_mcount"
5854 [(set_attr "type" "multi")
5855 (set_attr "length" "8")])
5857 (define_insn "init_fp"
5858 [(set (match_operand:DI 0 "register_operand" "=r")
5859 (match_operand:DI 1 "register_operand" "r"))
5860 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5864 (define_expand "epilogue"
5869 alpha_expand_epilogue ();
5872 (define_expand "sibcall_epilogue"
5874 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
5877 alpha_expand_epilogue ();
5881 (define_expand "eh_epilogue"
5882 [(use (match_operand:DI 0 "register_operand" "r"))
5883 (use (match_operand:DI 1 "register_operand" "r"))
5884 (use (match_operand:DI 2 "register_operand" "r"))]
5888 cfun->machine->eh_epilogue_sp_ofs = operands[1];
5889 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5891 rtx ra = gen_rtx_REG (Pmode, 26);
5892 emit_move_insn (ra, operands[2]);
5897 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5898 ;; the frame size into a register. We use this pattern to ensure
5899 ;; we get lda instead of addq.
5900 (define_insn "nt_lda"
5901 [(set (match_operand:DI 0 "register_operand" "=r")
5902 (unspec:DI [(match_dup 0)
5903 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5907 (define_expand "builtin_longjmp"
5908 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5909 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5912 /* The elements of the buffer are, in order: */
5913 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5914 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5915 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5916 rtx pv = gen_rtx_REG (Pmode, 27);
5918 /* This bit is the same as expand_builtin_longjmp. */
5919 emit_move_insn (hard_frame_pointer_rtx, fp);
5920 emit_move_insn (pv, lab);
5921 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5922 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5923 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5925 /* Load the label we are jumping through into $27 so that we know
5926 where to look for it when we get back to setjmp's function for
5927 restoring the gp. */
5928 emit_indirect_jump (pv);
5932 (define_insn "builtin_setjmp_receiver"
5933 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5934 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5935 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5936 [(set_attr "length" "8")
5937 (set_attr "type" "multi")])
5940 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5941 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5942 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5943 [(set_attr "length" "12")
5944 (set_attr "type" "multi")])
5946 (define_insn "exception_receiver"
5947 [(unspec_volatile [(const_int 0)] 7)]
5948 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5949 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5950 [(set_attr "length" "12")
5951 (set_attr "type" "multi")])
5953 (define_expand "nonlocal_goto_receiver"
5954 [(unspec_volatile [(const_int 0)] 1)
5955 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5956 (unspec_volatile [(const_int 0)] 1)
5961 (define_insn "arg_home"
5962 [(unspec [(const_int 0)] 0)
5977 (clobber (mem:BLK (const_int 0)))
5978 (clobber (reg:DI 24))
5979 (clobber (reg:DI 25))
5980 (clobber (reg:DI 0))]
5982 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5983 [(set_attr "length" "16")
5984 (set_attr "type" "multi")])
5986 ;; Close the trap shadow of preceeding instructions. This is generated
5989 (define_insn "trapb"
5990 [(unspec_volatile [(const_int 0)] 4)]
5993 [(set_attr "type" "misc")])
5995 ;; No-op instructions used by machine-dependant reorg to preserve
5996 ;; alignment for instruction issue.
6002 [(set_attr "type" "ilog")])
6008 [(set_attr "type" "fcpys")])
6015 (define_insn "realign"
6016 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
6018 ".align %0 #realign")
6020 ;; The call patterns are at the end of the file because their
6021 ;; wildcard operand0 interferes with nice recognition.
6023 (define_insn "*call_value_osf_1"
6024 [(set (match_operand 0 "" "")
6025 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
6026 (match_operand 2 "" "")))
6027 (clobber (reg:DI 27))
6028 (clobber (reg:DI 26))]
6029 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
6031 jsr $26,($27),0\;ldgp $29,0($26)
6033 jsr $26,%1\;ldgp $29,0($26)"
6034 [(set_attr "type" "jsr")
6035 (set_attr "length" "12,*,16")])
6037 (define_insn "*sibcall_value_osf_1"
6038 [(set (match_operand 0 "" "")
6039 (call (mem:DI (match_operand:DI 1 "call_operand" "R,i"))
6040 (match_operand 2 "" "")))]
6041 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
6045 [(set_attr "type" "jsr")
6046 (set_attr "length" "*,8")])
6048 (define_insn "*call_value_nt_1"
6049 [(set (match_operand 0 "" "")
6050 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
6051 (match_operand 2 "" "")))
6052 (clobber (reg:DI 26))]
6058 [(set_attr "type" "jsr")
6059 (set_attr "length" "*,*,12")])
6061 (define_insn "*call_value_vms_1"
6062 [(set (match_operand 0 "" "")
6063 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
6064 (match_operand 2 "" "")))
6065 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6068 (clobber (reg:DI 27))]
6071 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6072 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6073 [(set_attr "type" "jsr")
6074 (set_attr "length" "12,16")])
6076 ;; Peepholes go at the end.
6078 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
6079 ;; reload when converting fp->int.
6082 [(set (match_operand:SI 0 "hard_int_register_operand" "")
6083 (match_operand:SI 1 "memory_operand" ""))
6084 (set (match_operand:DI 2 "hard_int_register_operand" "")
6085 (sign_extend:DI (match_dup 0)))]
6086 "true_regnum (operands[0]) == true_regnum (operands[2])
6087 || peep2_reg_dead_p (2, operands[0])"
6089 (sign_extend:DI (match_dup 1)))]
6093 [(set (match_operand:SI 0 "hard_int_register_operand" "")
6094 (match_operand:SI 1 "hard_fp_register_operand" ""))
6095 (set (match_operand:DI 2 "hard_int_register_operand" "")
6096 (sign_extend:DI (match_dup 0)))]
6098 && (true_regnum (operands[0]) == true_regnum (operands[2])
6099 || peep2_reg_dead_p (2, operands[0]))"
6101 (sign_extend:DI (match_dup 1)))]
6105 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
6106 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
6107 (set (match_operand:DI 2 "hard_int_register_operand" "")
6109 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
6111 (sign_extend:DI (match_dup 1)))]