1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
45 ;; Processor type -- this attribute must exactly match the processor_type
46 ;; enumeration in alpha.h.
48 (define_attr "cpu" "ev4,ev5,ev6"
49 (const (symbol_ref "alpha_cpu")))
51 ;; Define an insn type attribute. This is used in function unit delay
52 ;; computations, among other purposes. For the most part, we use the names
53 ;; defined in the EV4 documentation, but add a few that we have to know about
57 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
58 (const_string "iadd"))
60 ;; Describe a user's asm statement.
61 (define_asm_attributes
62 [(set_attr "type" "multi")])
64 ;; Define the operand size an insn operates on. Used primarily by mul
65 ;; and div operations that have size dependant timings.
67 (define_attr "opsize" "si,di,udi" (const_string "di"))
69 ;; The TRAP_TYPE attribute marks instructions that may generate traps
70 ;; (which are imprecise and may need a trapb if software completion
73 (define_attr "trap" "no,yes" (const_string "no"))
75 ;; The length of an instruction sequence in bytes.
77 (define_attr "length" "" (const_int 4))
79 ;; On EV4 there are two classes of resources to consider: resources needed
80 ;; to issue, and resources needed to execute. IBUS[01] are in the first
81 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
82 ;; (There are a few other register-like resources, but ...)
84 ; First, describe all of the issue constraints with single cycle delays.
85 ; All insns need a bus, but all except loads require one or the other.
86 (define_function_unit "ev4_ibus0" 1 0
87 (and (eq_attr "cpu" "ev4")
88 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
91 (define_function_unit "ev4_ibus1" 1 0
92 (and (eq_attr "cpu" "ev4")
93 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
96 ; Memory delivers its result in three cycles. Actually return one and
97 ; take care of this in adjust_cost, since we want to handle user-defined
99 (define_function_unit "ev4_abox" 1 0
100 (and (eq_attr "cpu" "ev4")
101 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
104 ; Branches have no delay cost, but do tie up the unit for two cycles.
105 (define_function_unit "ev4_bbox" 1 1
106 (and (eq_attr "cpu" "ev4")
107 (eq_attr "type" "ibr,fbr,jsr"))
110 ; Arithmetic insns are normally have their results available after
111 ; two cycles. There are a number of exceptions. They are encoded in
112 ; ADJUST_COST. Some of the other insns have similar exceptions.
113 (define_function_unit "ev4_ebox" 1 0
114 (and (eq_attr "cpu" "ev4")
115 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
118 (define_function_unit "imul" 1 0
119 (and (eq_attr "cpu" "ev4")
120 (and (eq_attr "type" "imul")
121 (eq_attr "opsize" "si")))
124 (define_function_unit "imul" 1 0
125 (and (eq_attr "cpu" "ev4")
126 (and (eq_attr "type" "imul")
127 (eq_attr "opsize" "!si")))
130 (define_function_unit "ev4_fbox" 1 0
131 (and (eq_attr "cpu" "ev4")
132 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
135 (define_function_unit "fdiv" 1 0
136 (and (eq_attr "cpu" "ev4")
137 (and (eq_attr "type" "fdiv")
138 (eq_attr "opsize" "si")))
141 (define_function_unit "fdiv" 1 0
142 (and (eq_attr "cpu" "ev4")
143 (and (eq_attr "type" "fdiv")
144 (eq_attr "opsize" "di")))
147 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
149 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
150 ;; with the combined resource EBOX.
152 (define_function_unit "ev5_ebox" 2 0
153 (and (eq_attr "cpu" "ev5")
154 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
157 ; Memory takes at least 2 clocks. Return one from here and fix up with
158 ; user-defined latencies in adjust_cost.
159 (define_function_unit "ev5_ebox" 2 0
160 (and (eq_attr "cpu" "ev5")
161 (eq_attr "type" "ild,fld,ldsym"))
164 ; Loads can dual issue with one another, but loads and stores do not mix.
165 (define_function_unit "ev5_e0" 1 0
166 (and (eq_attr "cpu" "ev5")
167 (eq_attr "type" "ild,fld,ldsym"))
169 [(eq_attr "type" "ist,fst")])
171 ; Stores, shifts, multiplies can only issue to E0
172 (define_function_unit "ev5_e0" 1 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "ist,fst,shift,imul"))
177 ; Motion video insns also issue only to E0, and take two ticks.
178 (define_function_unit "ev5_e0" 1 0
179 (and (eq_attr "cpu" "ev5")
180 (eq_attr "type" "mvi"))
183 ; Conditional moves always take 2 ticks.
184 (define_function_unit "ev5_ebox" 2 0
185 (and (eq_attr "cpu" "ev5")
186 (eq_attr "type" "icmov"))
189 ; Branches can only issue to E1
190 (define_function_unit "ev5_e1" 1 0
191 (and (eq_attr "cpu" "ev5")
192 (eq_attr "type" "ibr,jsr"))
195 ; Multiplies also use the integer multiplier.
196 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
197 ; cycles before an integer multiplication completes."
198 (define_function_unit "imul" 1 0
199 (and (eq_attr "cpu" "ev5")
200 (and (eq_attr "type" "imul")
201 (eq_attr "opsize" "si")))
204 (define_function_unit "imul" 1 0
205 (and (eq_attr "cpu" "ev5")
206 (and (eq_attr "type" "imul")
207 (eq_attr "opsize" "di")))
210 (define_function_unit "imul" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (and (eq_attr "type" "imul")
213 (eq_attr "opsize" "udi")))
216 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
217 ;; on either so we have to play the game again.
219 (define_function_unit "ev5_fbox" 2 0
220 (and (eq_attr "cpu" "ev5")
221 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
224 (define_function_unit "ev5_fm" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "fmul"))
229 ; Add and cmov as you would expect; fbr never produces a result;
230 ; fdiv issues through fa to the divider,
231 (define_function_unit "ev5_fa" 1 0
232 (and (eq_attr "cpu" "ev5")
233 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
236 ; ??? How to: "No instruction can be issued to pipe FA exactly five
237 ; cycles before a floating point divide completes."
238 (define_function_unit "fdiv" 1 0
239 (and (eq_attr "cpu" "ev5")
240 (and (eq_attr "type" "fdiv")
241 (eq_attr "opsize" "si")))
242 15 15) ; 15 to 31 data dependant
244 (define_function_unit "fdiv" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "fdiv")
247 (eq_attr "opsize" "di")))
248 22 22) ; 22 to 60 data dependant
250 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
252 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
253 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
255 ;; Conditional moves decompose into two independant primitives, each
256 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
258 (define_function_unit "ev6_ebox" 4 0
259 (and (eq_attr "cpu" "ev6")
260 (eq_attr "type" "icmov"))
263 (define_function_unit "ev6_ebox" 4 0
264 (and (eq_attr "cpu" "ev6")
265 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
268 ;; Integer loads take at least 3 clocks, and only issue to lower units.
269 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
270 (define_function_unit "ev6_l" 2 0
271 (and (eq_attr "cpu" "ev6")
272 (eq_attr "type" "ild,ldsym,ist,fst"))
275 ;; FP loads take at least 4 clocks. Return two from here...
276 (define_function_unit "ev6_l" 2 0
277 (and (eq_attr "cpu" "ev6")
278 (eq_attr "type" "fld"))
281 ;; Motion video insns also issue only to U0, and take three ticks.
282 (define_function_unit "ev6_u0" 1 0
283 (and (eq_attr "cpu" "ev6")
284 (eq_attr "type" "mvi"))
287 (define_function_unit "ev6_u" 2 0
288 (and (eq_attr "cpu" "ev6")
289 (eq_attr "type" "mvi"))
292 ;; Shifts issue to either upper pipe.
293 (define_function_unit "ev6_u" 2 0
294 (and (eq_attr "cpu" "ev6")
295 (eq_attr "type" "shift"))
298 ;; Multiplies issue only to U1, and all take 7 ticks.
299 ;; Rather than create a new function unit just for U1, reuse IMUL
300 (define_function_unit "imul" 1 0
301 (and (eq_attr "cpu" "ev6")
302 (eq_attr "type" "imul"))
305 (define_function_unit "ev6_u" 2 0
306 (and (eq_attr "cpu" "ev6")
307 (eq_attr "type" "imul"))
310 ;; Branches issue to either upper pipe
311 (define_function_unit "ev6_u" 2 0
312 (and (eq_attr "cpu" "ev6")
313 (eq_attr "type" "ibr"))
316 ;; Calls only issue to L0.
317 (define_function_unit "ev6_l0" 1 0
318 (and (eq_attr "cpu" "ev6")
319 (eq_attr "type" "jsr"))
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "jsr"))
327 ;; Ftoi/itof only issue to lower pipes
328 (define_function_unit "ev6_l" 2 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "ftoi"))
333 (define_function_unit "ev6_l" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "itof"))
338 ;; For the FPU we are very similar to EV5, except there's no insn that
339 ;; can issue to fm & fa, so we get to leave that out.
341 (define_function_unit "ev6_fm" 1 0
342 (and (eq_attr "cpu" "ev6")
343 (eq_attr "type" "fmul"))
346 (define_function_unit "ev6_fa" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
351 (define_function_unit "ev6_fa" 1 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "fcmov"))
356 (define_function_unit "fdiv" 1 0
357 (and (eq_attr "cpu" "ev6")
358 (and (eq_attr "type" "fdiv")
359 (eq_attr "opsize" "si")))
362 (define_function_unit "fdiv" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (and (eq_attr "type" "fdiv")
365 (eq_attr "opsize" "di")))
368 (define_function_unit "fsqrt" 1 0
369 (and (eq_attr "cpu" "ev6")
370 (and (eq_attr "type" "fsqrt")
371 (eq_attr "opsize" "si")))
374 (define_function_unit "fsqrt" 1 0
375 (and (eq_attr "cpu" "ev6")
376 (and (eq_attr "type" "fsqrt")
377 (eq_attr "opsize" "di")))
380 ; ??? The FPU communicates with memory and the integer register file
381 ; via two fp store units. We need a slot in the fst immediately, and
382 ; a slot in LOW after the operand data is ready. At which point the
383 ; data may be moved either to the store queue or the integer register
384 ; file and the insn retired.
387 ;; First define the arithmetic insns. Note that the 32-bit forms also
390 ;; Handle 32-64 bit extension from memory to a floating point register
391 ;; specially, since this ocurrs frequently in int->double conversions.
393 ;; Note that while we must retain the =f case in the insn for reload's
394 ;; benefit, it should be eliminated after reload, so we should never emit
395 ;; code for that case. But we don't reject the possibility.
397 (define_expand "extendsidi2"
398 [(set (match_operand:DI 0 "register_operand" "")
399 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
404 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
406 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
412 lds %0,%1\;cvtlq %0,%0"
413 [(set_attr "type" "iadd,ild,fadd,fld")
414 (set_attr "length" "*,*,*,8")])
417 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
419 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
426 lds %0,%1\;cvtlq %0,%0"
427 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
428 (set_attr "length" "*,*,*,*,8")])
430 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
432 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
433 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
435 [(set (match_dup 2) (match_dup 1))
436 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
437 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
439 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
440 ;; generates better code. We have the anonymous addsi3 pattern below in
441 ;; case combine wants to make it.
442 (define_expand "addsi3"
443 [(set (match_operand:SI 0 "register_operand" "")
444 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
445 (match_operand:SI 2 "add_operand" "")))]
451 rtx op1 = gen_lowpart (DImode, operands[1]);
452 rtx op2 = gen_lowpart (DImode, operands[2]);
454 if (! cse_not_expected)
456 rtx tmp = gen_reg_rtx (DImode);
457 emit_insn (gen_adddi3 (tmp, op1, op2));
458 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
461 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
467 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
468 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
469 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
478 [(set (match_operand:SI 0 "register_operand" "")
479 (plus:SI (match_operand:SI 1 "register_operand" "")
480 (match_operand:SI 2 "const_int_operand" "")))]
481 "! add_operand (operands[2], SImode)"
482 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
483 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
486 HOST_WIDE_INT val = INTVAL (operands[2]);
487 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
488 HOST_WIDE_INT rest = val - low;
490 operands[3] = GEN_INT (rest);
491 operands[4] = GEN_INT (low);
495 [(set (match_operand:DI 0 "register_operand" "=r,r")
497 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
498 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
505 [(set (match_operand:DI 0 "register_operand" "")
507 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
508 (match_operand:SI 2 "const_int_operand" ""))))
509 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
510 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
511 && INTVAL (operands[2]) % 4 == 0"
512 [(set (match_dup 3) (match_dup 4))
513 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
518 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
524 operands[4] = GEN_INT (val);
525 operands[5] = GEN_INT (mult);
529 [(set (match_operand:DI 0 "register_operand" "")
531 (plus:SI (match_operator:SI 1 "comparison_operator"
532 [(match_operand 2 "" "")
533 (match_operand 3 "" "")])
534 (match_operand:SI 4 "add_operand" ""))))
535 (clobber (match_operand:DI 5 "register_operand" ""))]
537 [(set (match_dup 5) (match_dup 6))
538 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
541 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
542 operands[2], operands[3]);
543 operands[7] = gen_lowpart (SImode, operands[5]);
546 (define_expand "adddi3"
547 [(set (match_operand:DI 0 "register_operand" "")
548 (plus:DI (match_operand:DI 1 "register_operand" "")
549 (match_operand:DI 2 "add_operand" "")))]
553 ;; This pattern exists so that register elimination tries to canonize
554 ;; (plus (plus reg c1) c2).
557 [(set (match_operand:DI 0 "register_operand" "=r")
558 (match_operand:DI 1 "addition_operation" "p"))]
562 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
563 ;; With complications like
565 ;; The NT stack unwind code can't handle a subq to adjust the stack
566 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
567 ;; the exception handling code will loop if a subq is used and an
570 ;; The 19980616 change to emit prologues as RTL also confused some
571 ;; versions of GDB, which also interprets prologues. This has been
572 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
575 ;; and the fact that the three insns schedule exactly the same, it's
576 ;; just not worth the effort.
578 (define_insn "*adddi_2"
579 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
580 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
581 (match_operand:DI 2 "add_operand" "r,K,L")))]
588 ;; ??? Allow large constants when basing off the frame pointer or some
589 ;; virtual register that may eliminate to the frame pointer. This is
590 ;; done because register elimination offsets will change the hi/lo split,
591 ;; and if we split before reload, we will require additional instructions.
594 [(set (match_operand:DI 0 "register_operand" "=r")
595 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
596 (match_operand:DI 2 "const_int_operand" "n")))]
597 "REG_OK_FP_BASE_P (operands[1])
598 && INTVAL (operands[2]) >= 0
599 /* This is the largest constant an lda+ldah pair can add, minus
600 an upper bound on the displacement between SP and AP during
601 register elimination. See INITIAL_ELIMINATION_OFFSET. */
602 && INTVAL (operands[2])
604 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
605 - ALPHA_ROUND(current_function_outgoing_args_size)
606 - (ALPHA_ROUND (get_frame_size ()
607 + max_reg_num () * UNITS_PER_WORD
608 + current_function_pretend_args_size)
609 - current_function_pretend_args_size))"
612 ;; Don't do this if we are adjusting SP since we don't want to do it
613 ;; in two steps. Don't split FP sources for the reason listed above.
615 [(set (match_operand:DI 0 "register_operand" "")
616 (plus:DI (match_operand:DI 1 "register_operand" "")
617 (match_operand:DI 2 "const_int_operand" "")))]
618 "! add_operand (operands[2], DImode)
619 && operands[0] != stack_pointer_rtx
620 && operands[1] != frame_pointer_rtx
621 && operands[1] != arg_pointer_rtx"
622 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
623 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
626 HOST_WIDE_INT val = INTVAL (operands[2]);
627 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
628 HOST_WIDE_INT rest = val - low;
630 operands[4] = GEN_INT (low);
631 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
632 operands[3] = GEN_INT (rest);
633 else if (! no_new_pseudos)
635 operands[3] = gen_reg_rtx (DImode);
636 emit_move_insn (operands[3], operands[2]);
637 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
645 [(set (match_operand:SI 0 "register_operand" "=r,r")
646 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
647 (match_operand:SI 2 "const48_operand" "I,I"))
648 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
655 [(set (match_operand:DI 0 "register_operand" "=r,r")
657 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
658 (match_operand:SI 2 "const48_operand" "I,I"))
659 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
666 [(set (match_operand:DI 0 "register_operand" "")
668 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
669 [(match_operand 2 "" "")
670 (match_operand 3 "" "")])
671 (match_operand:SI 4 "const48_operand" ""))
672 (match_operand:SI 5 "sext_add_operand" ""))))
673 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
675 [(set (match_dup 6) (match_dup 7))
677 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
681 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
682 operands[2], operands[3]);
683 operands[8] = gen_lowpart (SImode, operands[6]);
687 [(set (match_operand:DI 0 "register_operand" "=r,r")
688 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
689 (match_operand:DI 2 "const48_operand" "I,I"))
690 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
696 (define_insn "negsi2"
697 [(set (match_operand:SI 0 "register_operand" "=r")
698 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
703 [(set (match_operand:DI 0 "register_operand" "=r")
704 (sign_extend:DI (neg:SI
705 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
709 (define_insn "negdi2"
710 [(set (match_operand:DI 0 "register_operand" "=r")
711 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
715 (define_expand "subsi3"
716 [(set (match_operand:SI 0 "register_operand" "")
717 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
718 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
724 rtx op1 = gen_lowpart (DImode, operands[1]);
725 rtx op2 = gen_lowpart (DImode, operands[2]);
727 if (! cse_not_expected)
729 rtx tmp = gen_reg_rtx (DImode);
730 emit_insn (gen_subdi3 (tmp, op1, op2));
731 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
734 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
740 [(set (match_operand:SI 0 "register_operand" "=r")
741 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
742 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
747 [(set (match_operand:DI 0 "register_operand" "=r")
748 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
749 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
753 (define_insn "subdi3"
754 [(set (match_operand:DI 0 "register_operand" "=r")
755 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
756 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
761 [(set (match_operand:SI 0 "register_operand" "=r")
762 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
763 (match_operand:SI 2 "const48_operand" "I"))
764 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
769 [(set (match_operand:DI 0 "register_operand" "=r")
771 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
772 (match_operand:SI 2 "const48_operand" "I"))
773 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
778 [(set (match_operand:DI 0 "register_operand" "=r")
779 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
780 (match_operand:DI 2 "const48_operand" "I"))
781 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
785 (define_insn "mulsi3"
786 [(set (match_operand:SI 0 "register_operand" "=r")
787 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
788 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
791 [(set_attr "type" "imul")
792 (set_attr "opsize" "si")])
795 [(set (match_operand:DI 0 "register_operand" "=r")
797 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
798 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
801 [(set_attr "type" "imul")
802 (set_attr "opsize" "si")])
804 (define_insn "muldi3"
805 [(set (match_operand:DI 0 "register_operand" "=r")
806 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
807 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
810 [(set_attr "type" "imul")])
812 (define_insn "umuldi3_highpart"
813 [(set (match_operand:DI 0 "register_operand" "=r")
816 (mult:TI (zero_extend:TI
817 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
819 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
823 [(set_attr "type" "imul")
824 (set_attr "opsize" "udi")])
827 [(set (match_operand:DI 0 "register_operand" "=r")
830 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
831 (match_operand:TI 2 "cint8_operand" "I"))
835 [(set_attr "type" "imul")
836 (set_attr "opsize" "udi")])
838 ;; The divide and remainder operations always take their inputs from
839 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
841 ;; ??? Force sign-extension here because some versions of OSF/1 don't
842 ;; do the right thing if the inputs are not properly sign-extended.
843 ;; But Linux, for instance, does not have this problem. Is it worth
844 ;; the complication here to eliminate the sign extension?
845 ;; Interix/NT has the same sign-extension problem.
847 (define_expand "divsi3"
849 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
851 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
852 (parallel [(set (reg:DI 27)
853 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
854 (clobber (reg:DI 23))
855 (clobber (reg:DI 28))])
856 (set (match_operand:SI 0 "nonimmediate_operand" "")
857 (subreg:SI (reg:DI 27) 0))]
861 (define_expand "udivsi3"
863 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
865 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
866 (parallel [(set (reg:DI 27)
867 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
868 (clobber (reg:DI 23))
869 (clobber (reg:DI 28))])
870 (set (match_operand:SI 0 "nonimmediate_operand" "")
871 (subreg:SI (reg:DI 27) 0))]
875 (define_expand "modsi3"
877 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
879 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
880 (parallel [(set (reg:DI 27)
881 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
882 (clobber (reg:DI 23))
883 (clobber (reg:DI 28))])
884 (set (match_operand:SI 0 "nonimmediate_operand" "")
885 (subreg:SI (reg:DI 27) 0))]
889 (define_expand "umodsi3"
891 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
893 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
894 (parallel [(set (reg:DI 27)
895 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
896 (clobber (reg:DI 23))
897 (clobber (reg:DI 28))])
898 (set (match_operand:SI 0 "nonimmediate_operand" "")
899 (subreg:SI (reg:DI 27) 0))]
903 (define_expand "divdi3"
904 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
905 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
906 (parallel [(set (reg:DI 27)
909 (clobber (reg:DI 23))
910 (clobber (reg:DI 28))])
911 (set (match_operand:DI 0 "nonimmediate_operand" "")
916 (define_expand "udivdi3"
917 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
918 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
919 (parallel [(set (reg:DI 27)
922 (clobber (reg:DI 23))
923 (clobber (reg:DI 28))])
924 (set (match_operand:DI 0 "nonimmediate_operand" "")
929 (define_expand "moddi3"
930 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
931 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
932 (parallel [(set (reg:DI 27)
935 (clobber (reg:DI 23))
936 (clobber (reg:DI 28))])
937 (set (match_operand:DI 0 "nonimmediate_operand" "")
942 (define_expand "umoddi3"
943 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
944 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
945 (parallel [(set (reg:DI 27)
948 (clobber (reg:DI 23))
949 (clobber (reg:DI 28))])
950 (set (match_operand:DI 0 "nonimmediate_operand" "")
955 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
956 ;; expanded by the assembler.
959 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
960 [(reg:DI 24) (reg:DI 25)])))
961 (clobber (reg:DI 23))
962 (clobber (reg:DI 28))]
965 [(set_attr "type" "jsr")
966 (set_attr "length" "8")])
970 (match_operator:DI 1 "divmod_operator"
971 [(reg:DI 24) (reg:DI 25)]))
972 (clobber (reg:DI 23))
973 (clobber (reg:DI 28))]
976 [(set_attr "type" "jsr")
977 (set_attr "length" "8")])
979 ;; Next are the basic logical operations. These only exist in DImode.
981 (define_insn "anddi3"
982 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
983 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
984 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
990 [(set_attr "type" "ilog,ilog,shift")])
992 ;; There are times when we can split an AND into two AND insns. This occurs
993 ;; when we can first clear any bytes and then clear anything else. For
994 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
995 ;; Only do this when running on 64-bit host since the computations are
996 ;; too messy otherwise.
999 [(set (match_operand:DI 0 "register_operand" "")
1000 (and:DI (match_operand:DI 1 "register_operand" "")
1001 (match_operand:DI 2 "const_int_operand" "")))]
1002 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1003 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1004 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1007 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1008 unsigned HOST_WIDE_INT mask2 = mask1;
1011 /* For each byte that isn't all zeros, make it all ones. */
1012 for (i = 0; i < 64; i += 8)
1013 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1014 mask1 |= (HOST_WIDE_INT) 0xff << i;
1016 /* Now turn on any bits we've just turned off. */
1019 operands[3] = GEN_INT (mask1);
1020 operands[4] = GEN_INT (mask2);
1023 (define_insn "zero_extendqihi2"
1024 [(set (match_operand:HI 0 "register_operand" "=r")
1025 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1028 [(set_attr "type" "ilog")])
1031 [(set (match_operand:SI 0 "register_operand" "=r,r")
1032 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1037 [(set_attr "type" "ilog,ild")])
1040 [(set (match_operand:SI 0 "register_operand" "=r")
1041 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1044 [(set_attr "type" "ilog")])
1046 (define_expand "zero_extendqisi2"
1047 [(set (match_operand:SI 0 "register_operand" "")
1048 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1053 [(set (match_operand:DI 0 "register_operand" "=r,r")
1054 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1059 [(set_attr "type" "ilog,ild")])
1062 [(set (match_operand:DI 0 "register_operand" "=r")
1063 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1066 [(set_attr "type" "ilog")])
1068 (define_expand "zero_extendqidi2"
1069 [(set (match_operand:DI 0 "register_operand" "")
1070 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1075 [(set (match_operand:SI 0 "register_operand" "=r,r")
1076 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1081 [(set_attr "type" "shift,ild")])
1084 [(set (match_operand:SI 0 "register_operand" "=r")
1085 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1088 [(set_attr "type" "shift")])
1090 (define_expand "zero_extendhisi2"
1091 [(set (match_operand:SI 0 "register_operand" "")
1092 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1097 [(set (match_operand:DI 0 "register_operand" "=r,r")
1098 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1103 [(set_attr "type" "shift,ild")])
1106 [(set (match_operand:DI 0 "register_operand" "=r")
1107 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1110 [(set_attr "type" "shift")])
1112 (define_expand "zero_extendhidi2"
1113 [(set (match_operand:DI 0 "register_operand" "")
1114 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1118 (define_insn "zero_extendsidi2"
1119 [(set (match_operand:DI 0 "register_operand" "=r")
1120 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1123 [(set_attr "type" "shift")])
1126 [(set (match_operand:DI 0 "register_operand" "=r")
1127 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1128 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1131 [(set_attr "type" "ilog")])
1133 (define_insn "iordi3"
1134 [(set (match_operand:DI 0 "register_operand" "=r,r")
1135 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1136 (match_operand:DI 2 "or_operand" "rI,N")))]
1141 [(set_attr "type" "ilog")])
1143 (define_insn "one_cmpldi2"
1144 [(set (match_operand:DI 0 "register_operand" "=r")
1145 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1148 [(set_attr "type" "ilog")])
1151 [(set (match_operand:DI 0 "register_operand" "=r")
1152 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1153 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1156 [(set_attr "type" "ilog")])
1158 (define_insn "xordi3"
1159 [(set (match_operand:DI 0 "register_operand" "=r,r")
1160 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1161 (match_operand:DI 2 "or_operand" "rI,N")))]
1166 [(set_attr "type" "ilog")])
1169 [(set (match_operand:DI 0 "register_operand" "=r")
1170 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1171 (match_operand:DI 2 "register_operand" "rI"))))]
1174 [(set_attr "type" "ilog")])
1176 ;; Handle the FFS insn iff we support CIX.
1178 ;; These didn't make it into EV6 pass 2 as planned. Instead they
1179 ;; cropped cttz/ctlz/ctpop from the old CIX and renamed it FIX for
1180 ;; "Square Root and Floating Point Convert Extension".
1182 ;; I'm assured that these insns will make it into EV67 (first pass
1183 ;; due Summer 1999), presumably with a new AMASK bit, and presumably
1184 ;; will still be named CIX.
1186 (define_expand "ffsdi2"
1188 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1190 (plus:DI (match_dup 2) (const_int 1)))
1191 (set (match_operand:DI 0 "register_operand" "")
1192 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1193 (const_int 0) (match_dup 3)))]
1197 operands[2] = gen_reg_rtx (DImode);
1198 operands[3] = gen_reg_rtx (DImode);
1202 [(set (match_operand:DI 0 "register_operand" "=r")
1203 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1206 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1207 ; reuse the existing type name.
1208 [(set_attr "type" "mvi")])
1210 ;; Next come the shifts and the various extract and insert operations.
1212 (define_insn "ashldi3"
1213 [(set (match_operand:DI 0 "register_operand" "=r,r")
1214 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1215 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1219 switch (which_alternative)
1222 if (operands[2] == const1_rtx)
1223 return \"addq %r1,%r1,%0\";
1225 return \"s%P2addq %r1,0,%0\";
1227 return \"sll %r1,%2,%0\";
1232 [(set_attr "type" "iadd,shift")])
1234 ;; ??? The following pattern is made by combine, but earlier phases
1235 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1236 ;; with this in a better way at some point.
1238 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1240 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1241 ;; (match_operand:DI 2 "const_int_operand" "P"))
1243 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1246 ;; if (operands[2] == const1_rtx)
1247 ;; return \"addl %r1,%r1,%0\";
1249 ;; return \"s%P2addl %r1,0,%0\";
1251 ;; [(set_attr "type" "iadd")])
1253 (define_insn "lshrdi3"
1254 [(set (match_operand:DI 0 "register_operand" "=r")
1255 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1256 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1259 [(set_attr "type" "shift")])
1261 (define_insn "ashrdi3"
1262 [(set (match_operand:DI 0 "register_operand" "=r")
1263 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1264 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1267 [(set_attr "type" "shift")])
1269 (define_expand "extendqihi2"
1271 (ashift:DI (match_operand:QI 1 "some_operand" "")
1273 (set (match_operand:HI 0 "register_operand" "")
1274 (ashiftrt:DI (match_dup 2)
1281 emit_insn (gen_extendqihi2x (operands[0],
1282 force_reg (QImode, operands[1])));
1286 /* If we have an unaligned MEM, extend to DImode (which we do
1287 specially) and then copy to the result. */
1288 if (unaligned_memory_operand (operands[1], HImode))
1290 rtx temp = gen_reg_rtx (DImode);
1292 emit_insn (gen_extendqidi2 (temp, operands[1]));
1293 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1297 operands[0] = gen_lowpart (DImode, operands[0]);
1298 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1299 operands[2] = gen_reg_rtx (DImode);
1302 (define_insn "extendqidi2x"
1303 [(set (match_operand:DI 0 "register_operand" "=r")
1304 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1307 [(set_attr "type" "shift")])
1309 (define_insn "extendhidi2x"
1310 [(set (match_operand:DI 0 "register_operand" "=r")
1311 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1314 [(set_attr "type" "shift")])
1316 (define_insn "extendqisi2x"
1317 [(set (match_operand:SI 0 "register_operand" "=r")
1318 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1321 [(set_attr "type" "shift")])
1323 (define_insn "extendhisi2x"
1324 [(set (match_operand:SI 0 "register_operand" "=r")
1325 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1328 [(set_attr "type" "shift")])
1330 (define_insn "extendqihi2x"
1331 [(set (match_operand:HI 0 "register_operand" "=r")
1332 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1335 [(set_attr "type" "shift")])
1337 (define_expand "extendqisi2"
1339 (ashift:DI (match_operand:QI 1 "some_operand" "")
1341 (set (match_operand:SI 0 "register_operand" "")
1342 (ashiftrt:DI (match_dup 2)
1349 emit_insn (gen_extendqisi2x (operands[0],
1350 force_reg (QImode, operands[1])));
1354 /* If we have an unaligned MEM, extend to a DImode form of
1355 the result (which we do specially). */
1356 if (unaligned_memory_operand (operands[1], QImode))
1358 rtx temp = gen_reg_rtx (DImode);
1360 emit_insn (gen_extendqidi2 (temp, operands[1]));
1361 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1365 operands[0] = gen_lowpart (DImode, operands[0]);
1366 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1367 operands[2] = gen_reg_rtx (DImode);
1370 (define_expand "extendqidi2"
1372 (ashift:DI (match_operand:QI 1 "some_operand" "")
1374 (set (match_operand:DI 0 "register_operand" "")
1375 (ashiftrt:DI (match_dup 2)
1382 emit_insn (gen_extendqidi2x (operands[0],
1383 force_reg (QImode, operands[1])));
1387 if (unaligned_memory_operand (operands[1], QImode))
1390 = gen_unaligned_extendqidi (operands[0],
1391 get_unaligned_address (operands[1], 1));
1393 alpha_set_memflags (seq, operands[1]);
1398 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1399 operands[2] = gen_reg_rtx (DImode);
1402 (define_expand "extendhisi2"
1404 (ashift:DI (match_operand:HI 1 "some_operand" "")
1406 (set (match_operand:SI 0 "register_operand" "")
1407 (ashiftrt:DI (match_dup 2)
1414 emit_insn (gen_extendhisi2x (operands[0],
1415 force_reg (HImode, operands[1])));
1419 /* If we have an unaligned MEM, extend to a DImode form of
1420 the result (which we do specially). */
1421 if (unaligned_memory_operand (operands[1], HImode))
1423 rtx temp = gen_reg_rtx (DImode);
1425 emit_insn (gen_extendhidi2 (temp, operands[1]));
1426 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1430 operands[0] = gen_lowpart (DImode, operands[0]);
1431 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1432 operands[2] = gen_reg_rtx (DImode);
1435 (define_expand "extendhidi2"
1437 (ashift:DI (match_operand:HI 1 "some_operand" "")
1439 (set (match_operand:DI 0 "register_operand" "")
1440 (ashiftrt:DI (match_dup 2)
1447 emit_insn (gen_extendhidi2x (operands[0],
1448 force_reg (HImode, operands[1])));
1452 if (unaligned_memory_operand (operands[1], HImode))
1455 = gen_unaligned_extendhidi (operands[0],
1456 get_unaligned_address (operands[1], 2));
1458 alpha_set_memflags (seq, operands[1]);
1463 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1464 operands[2] = gen_reg_rtx (DImode);
1467 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1468 ;; as a pattern saves one instruction. The code is similar to that for
1469 ;; the unaligned loads (see below).
1471 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1472 (define_expand "unaligned_extendqidi"
1473 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1475 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1478 (ashift:DI (match_dup 3)
1479 (minus:DI (const_int 64)
1481 (and:DI (match_dup 2) (const_int 7))
1483 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1484 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1487 { operands[2] = gen_reg_rtx (DImode);
1488 operands[3] = gen_reg_rtx (DImode);
1489 operands[4] = gen_reg_rtx (DImode);
1492 (define_expand "unaligned_extendhidi"
1493 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1495 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1498 (ashift:DI (match_dup 3)
1499 (minus:DI (const_int 64)
1501 (and:DI (match_dup 2) (const_int 7))
1503 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1504 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1507 { operands[2] = gen_reg_rtx (DImode);
1508 operands[3] = gen_reg_rtx (DImode);
1509 operands[4] = gen_reg_rtx (DImode);
1513 [(set (match_operand:DI 0 "register_operand" "=r")
1514 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1515 (match_operand:DI 2 "mode_width_operand" "n")
1516 (match_operand:DI 3 "mul8_operand" "I")))]
1518 "ext%M2l %r1,%s3,%0"
1519 [(set_attr "type" "shift")])
1521 (define_insn "extxl"
1522 [(set (match_operand:DI 0 "register_operand" "=r")
1523 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1524 (match_operand:DI 2 "mode_width_operand" "n")
1525 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1529 [(set_attr "type" "shift")])
1531 ;; Combine has some strange notion of preserving existing undefined behaviour
1532 ;; in shifts larger than a word size. So capture these patterns that it
1533 ;; should have turned into zero_extracts.
1536 [(set (match_operand:DI 0 "register_operand" "=r")
1537 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1538 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1540 (match_operand:DI 3 "mode_mask_operand" "n")))]
1543 [(set_attr "type" "shift")])
1546 [(set (match_operand:DI 0 "register_operand" "=r")
1547 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1548 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1552 [(set_attr "type" "shift")])
1554 (define_insn "extqh"
1555 [(set (match_operand:DI 0 "register_operand" "=r")
1557 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1558 (minus:DI (const_int 64)
1561 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1566 [(set_attr "type" "shift")])
1568 (define_insn "extlh"
1569 [(set (match_operand:DI 0 "register_operand" "=r")
1571 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1572 (const_int 2147483647))
1573 (minus:DI (const_int 64)
1576 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1581 [(set_attr "type" "shift")])
1583 (define_insn "extwh"
1584 [(set (match_operand:DI 0 "register_operand" "=r")
1586 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1588 (minus:DI (const_int 64)
1591 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1596 [(set_attr "type" "shift")])
1598 ;; This converts an extXl into an extXh with an appropriate adjustment
1599 ;; to the address calculation.
1602 ;; [(set (match_operand:DI 0 "register_operand" "")
1603 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1604 ;; (match_operand:DI 2 "mode_width_operand" "")
1605 ;; (ashift:DI (match_operand:DI 3 "" "")
1607 ;; (match_operand:DI 4 "const_int_operand" "")))
1608 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1609 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1610 ;; [(set (match_dup 5) (match_dup 6))
1611 ;; (set (match_dup 0)
1612 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1613 ;; (ashift:DI (plus:DI (match_dup 5)
1619 ;; operands[6] = plus_constant (operands[3],
1620 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1621 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1625 [(set (match_operand:DI 0 "register_operand" "=r")
1626 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1627 (match_operand:DI 2 "mul8_operand" "I")))]
1630 [(set_attr "type" "shift")])
1633 [(set (match_operand:DI 0 "register_operand" "=r")
1634 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1635 (match_operand:DI 2 "mul8_operand" "I")))]
1638 [(set_attr "type" "shift")])
1641 [(set (match_operand:DI 0 "register_operand" "=r")
1642 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1643 (match_operand:DI 2 "mul8_operand" "I")))]
1646 [(set_attr "type" "shift")])
1648 (define_insn "insbl"
1649 [(set (match_operand:DI 0 "register_operand" "=r")
1650 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1651 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1655 [(set_attr "type" "shift")])
1657 (define_insn "inswl"
1658 [(set (match_operand:DI 0 "register_operand" "=r")
1659 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1660 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1664 [(set_attr "type" "shift")])
1666 (define_insn "insll"
1667 [(set (match_operand:DI 0 "register_operand" "=r")
1668 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1669 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1673 [(set_attr "type" "shift")])
1675 (define_insn "insql"
1676 [(set (match_operand:DI 0 "register_operand" "=r")
1677 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1678 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1682 [(set_attr "type" "shift")])
1684 ;; Combine has this sometimes habit of moving the and outside of the
1685 ;; shift, making life more interesting.
1688 [(set (match_operand:DI 0 "register_operand" "=r")
1689 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1690 (match_operand:DI 2 "mul8_operand" "I"))
1691 (match_operand:DI 3 "immediate_operand" "i")))]
1692 "HOST_BITS_PER_WIDE_INT == 64
1693 && GET_CODE (operands[3]) == CONST_INT
1694 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1695 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1696 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1697 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1698 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1699 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1702 #if HOST_BITS_PER_WIDE_INT == 64
1703 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1704 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1705 return \"insbl %1,%s2,%0\";
1706 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1707 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1708 return \"inswl %1,%s2,%0\";
1709 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1710 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1711 return \"insll %1,%s2,%0\";
1715 [(set_attr "type" "shift")])
1717 ;; We do not include the insXh insns because they are complex to express
1718 ;; and it does not appear that we would ever want to generate them.
1720 ;; Since we need them for block moves, though, cop out and use unspec.
1722 (define_insn "insxh"
1723 [(set (match_operand:DI 0 "register_operand" "=r")
1724 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1725 (match_operand:DI 2 "mode_width_operand" "n")
1726 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1729 [(set_attr "type" "shift")])
1731 (define_insn "mskxl"
1732 [(set (match_operand:DI 0 "register_operand" "=r")
1733 (and:DI (not:DI (ashift:DI
1734 (match_operand:DI 2 "mode_mask_operand" "n")
1736 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1738 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1741 [(set_attr "type" "shift")])
1743 ;; We do not include the mskXh insns because it does not appear we would
1744 ;; ever generate one.
1746 ;; Again, we do for block moves and we use unspec again.
1748 (define_insn "mskxh"
1749 [(set (match_operand:DI 0 "register_operand" "=r")
1750 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1751 (match_operand:DI 2 "mode_width_operand" "n")
1752 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1755 [(set_attr "type" "shift")])
1757 ;; Floating-point operations. All the double-precision insns can extend
1758 ;; from single, so indicate that. The exception are the ones that simply
1759 ;; play with the sign bits; it's not clear what to do there.
1761 (define_insn "abssf2"
1762 [(set (match_operand:SF 0 "register_operand" "=f")
1763 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1766 [(set_attr "type" "fcpys")])
1768 (define_insn "absdf2"
1769 [(set (match_operand:DF 0 "register_operand" "=f")
1770 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1773 [(set_attr "type" "fcpys")])
1775 (define_expand "abstf2"
1776 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1777 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1778 (use (match_dup 2))])]
1779 "TARGET_HAS_XFLOATING_LIBS"
1782 #if HOST_BITS_PER_WIDE_INT >= 64
1783 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1785 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1790 [(set (match_operand:TF 0 "register_operand" "=r")
1791 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1792 (use (match_operand:DI 2 "register_operand" "=r"))]
1793 "TARGET_HAS_XFLOATING_LIBS"
1797 [(set (match_operand:TF 0 "register_operand" "")
1798 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1799 (use (match_operand:DI 4 "register_operand" ""))]
1807 alpha_split_tfmode_pair (operands);
1810 if (rtx_equal_p (operands[0], operands[2]))
1812 else if (rtx_equal_p (operands[1], operands[2]))
1816 emit_move_insn (operands[0], operands[2]);
1818 tmp = gen_rtx_NOT (DImode, operands[4]);
1819 tmp = gen_rtx_AND (DImode, tmp, operands[3]);
1820 emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
1823 emit_move_insn (operands[0], operands[2]);
1827 (define_insn "negsf2"
1828 [(set (match_operand:SF 0 "register_operand" "=f")
1829 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1832 [(set_attr "type" "fadd")])
1834 (define_insn "negdf2"
1835 [(set (match_operand:DF 0 "register_operand" "=f")
1836 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1839 [(set_attr "type" "fadd")])
1841 (define_expand "negtf2"
1842 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1843 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1844 (use (match_dup 2))])]
1845 "TARGET_HAS_XFLOATING_LIBS"
1848 #if HOST_BITS_PER_WIDE_INT >= 64
1849 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1851 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1856 [(set (match_operand:TF 0 "register_operand" "=r")
1857 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1858 (use (match_operand:DI 2 "register_operand" "=r"))]
1859 "TARGET_HAS_XFLOATING_LIBS"
1863 [(set (match_operand:TF 0 "register_operand" "")
1864 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1865 (use (match_operand:DI 4 "register_operand" ""))]
1872 alpha_split_tfmode_pair (operands);
1875 if (rtx_equal_p (operands[0], operands[2]))
1877 else if (rtx_equal_p (operands[1], operands[2]))
1881 emit_move_insn (operands[0], operands[2]);
1883 emit_insn (gen_xordi3 (operands[1], operands[3], operands[4]));
1886 emit_move_insn (operands[0], operands[2]);
1891 [(set (match_operand:SF 0 "register_operand" "=&f")
1892 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1893 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1894 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1895 "add%,%)%& %R1,%R2,%0"
1896 [(set_attr "type" "fadd")
1897 (set_attr "trap" "yes")])
1899 (define_insn "addsf3"
1900 [(set (match_operand:SF 0 "register_operand" "=f")
1901 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1902 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1904 "add%,%)%& %R1,%R2,%0"
1905 [(set_attr "type" "fadd")
1906 (set_attr "trap" "yes")])
1909 [(set (match_operand:DF 0 "register_operand" "=&f")
1910 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1911 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1912 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1913 "add%-%)%& %R1,%R2,%0"
1914 [(set_attr "type" "fadd")
1915 (set_attr "trap" "yes")])
1917 (define_insn "adddf3"
1918 [(set (match_operand:DF 0 "register_operand" "=f")
1919 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1920 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1922 "add%-%)%& %R1,%R2,%0"
1923 [(set_attr "type" "fadd")
1924 (set_attr "trap" "yes")])
1927 [(set (match_operand:DF 0 "register_operand" "=f")
1928 (plus:DF (float_extend:DF
1929 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1930 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1931 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1932 "add%-%)%& %R1,%R2,%0"
1933 [(set_attr "type" "fadd")
1934 (set_attr "trap" "yes")])
1937 [(set (match_operand:DF 0 "register_operand" "=f")
1938 (plus:DF (float_extend:DF
1939 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1941 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1942 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1943 "add%-%)%& %R1,%R2,%0"
1944 [(set_attr "type" "fadd")
1945 (set_attr "trap" "yes")])
1947 (define_expand "addtf3"
1948 [(use (match_operand 0 "register_operand" ""))
1949 (use (match_operand 1 "general_operand" ""))
1950 (use (match_operand 2 "general_operand" ""))]
1951 "TARGET_HAS_XFLOATING_LIBS"
1952 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
1954 ;; Define conversion operators between DFmode and SImode, using the cvtql
1955 ;; instruction. To allow combine et al to do useful things, we keep the
1956 ;; operation as a unit until after reload, at which point we split the
1959 ;; Note that we (attempt to) only consider this optimization when the
1960 ;; ultimate destination is memory. If we will be doing further integer
1961 ;; processing, it is cheaper to do the truncation in the int regs.
1963 (define_insn "*cvtql"
1964 [(set (match_operand:SI 0 "register_operand" "=f")
1965 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1968 [(set_attr "type" "fadd")
1969 (set_attr "trap" "yes")])
1972 [(set (match_operand:SI 0 "memory_operand" "")
1973 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1974 (clobber (match_scratch:DI 2 ""))
1975 (clobber (match_scratch:SI 3 ""))]
1976 "TARGET_FP && reload_completed"
1977 [(set (match_dup 2) (fix:DI (match_dup 1)))
1978 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1979 (set (match_dup 0) (match_dup 3))]
1983 [(set (match_operand:SI 0 "memory_operand" "")
1984 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1985 (clobber (match_scratch:DI 2 ""))]
1986 "TARGET_FP && reload_completed"
1987 [(set (match_dup 2) (fix:DI (match_dup 1)))
1988 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1989 (set (match_dup 0) (match_dup 3))]
1990 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1991 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1994 [(set (match_operand:SI 0 "memory_operand" "=m")
1995 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1996 (clobber (match_scratch:DI 2 "=&f"))
1997 (clobber (match_scratch:SI 3 "=&f"))]
1998 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2000 [(set_attr "type" "fadd")
2001 (set_attr "trap" "yes")])
2004 [(set (match_operand:SI 0 "memory_operand" "=m")
2005 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2006 (clobber (match_scratch:DI 2 "=f"))]
2007 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2009 [(set_attr "type" "fadd")
2010 (set_attr "trap" "yes")])
2013 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2014 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2015 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2017 [(set_attr "type" "fadd")
2018 (set_attr "trap" "yes")])
2020 (define_insn "fix_truncdfdi2"
2021 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2022 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2025 [(set_attr "type" "fadd")
2026 (set_attr "trap" "yes")])
2028 ;; Likewise between SFmode and SImode.
2031 [(set (match_operand:SI 0 "memory_operand" "")
2032 (subreg:SI (fix:DI (float_extend:DF
2033 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2034 (clobber (match_scratch:DI 2 ""))
2035 (clobber (match_scratch:SI 3 ""))]
2036 "TARGET_FP && reload_completed"
2037 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2038 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2039 (set (match_dup 0) (match_dup 3))]
2043 [(set (match_operand:SI 0 "memory_operand" "")
2044 (subreg:SI (fix:DI (float_extend:DF
2045 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2046 (clobber (match_scratch:DI 2 ""))]
2047 "TARGET_FP && reload_completed"
2048 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2049 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2050 (set (match_dup 0) (match_dup 3))]
2051 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2052 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2055 [(set (match_operand:SI 0 "memory_operand" "=m")
2056 (subreg:SI (fix:DI (float_extend:DF
2057 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2058 (clobber (match_scratch:DI 2 "=&f"))
2059 (clobber (match_scratch:SI 3 "=&f"))]
2060 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2062 [(set_attr "type" "fadd")
2063 (set_attr "trap" "yes")])
2066 [(set (match_operand:SI 0 "memory_operand" "=m")
2067 (subreg:SI (fix:DI (float_extend:DF
2068 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2069 (clobber (match_scratch:DI 2 "=f"))]
2070 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2072 [(set_attr "type" "fadd")
2073 (set_attr "trap" "yes")])
2076 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2077 (fix:DI (float_extend:DF
2078 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2079 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2081 [(set_attr "type" "fadd")
2082 (set_attr "trap" "yes")])
2084 (define_insn "fix_truncsfdi2"
2085 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2086 (fix:DI (float_extend:DF
2087 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2090 [(set_attr "type" "fadd")
2091 (set_attr "trap" "yes")])
2093 (define_expand "fix_trunctfdi2"
2094 [(use (match_operand:DI 0 "register_operand" ""))
2095 (use (match_operand:TF 1 "general_operand" ""))]
2096 "TARGET_HAS_XFLOATING_LIBS"
2097 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2100 [(set (match_operand:SF 0 "register_operand" "=&f")
2101 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2102 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2104 [(set_attr "type" "fadd")
2105 (set_attr "trap" "yes")])
2107 (define_insn "floatdisf2"
2108 [(set (match_operand:SF 0 "register_operand" "=f")
2109 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2112 [(set_attr "type" "fadd")
2113 (set_attr "trap" "yes")])
2116 [(set (match_operand:DF 0 "register_operand" "=&f")
2117 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2118 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2120 [(set_attr "type" "fadd")
2121 (set_attr "trap" "yes")])
2123 (define_insn "floatdidf2"
2124 [(set (match_operand:DF 0 "register_operand" "=f")
2125 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2128 [(set_attr "type" "fadd")
2129 (set_attr "trap" "yes")])
2131 (define_expand "floatditf2"
2132 [(use (match_operand:TF 0 "register_operand" ""))
2133 (use (match_operand:DI 1 "general_operand" ""))]
2134 "TARGET_HAS_XFLOATING_LIBS"
2135 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2137 (define_expand "floatunsdisf2"
2138 [(use (match_operand:SF 0 "register_operand" ""))
2139 (use (match_operand:DI 1 "register_operand" ""))]
2141 "alpha_emit_floatuns (operands); DONE;")
2143 (define_expand "floatunsdidf2"
2144 [(use (match_operand:DF 0 "register_operand" ""))
2145 (use (match_operand:DI 1 "register_operand" ""))]
2147 "alpha_emit_floatuns (operands); DONE;")
2149 (define_expand "floatunsditf2"
2150 [(use (match_operand:TF 0 "register_operand" ""))
2151 (use (match_operand:DI 1 "general_operand" ""))]
2152 "TARGET_HAS_XFLOATING_LIBS"
2153 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2155 (define_expand "extendsfdf2"
2156 [(set (match_operand:DF 0 "register_operand" "")
2157 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2161 if (alpha_fptm >= ALPHA_FPTM_SU)
2162 operands[1] = force_reg (SFmode, operands[1]);
2166 [(set (match_operand:DF 0 "register_operand" "=&f")
2167 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2168 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2170 [(set_attr "type" "fadd")
2171 (set_attr "trap" "yes")])
2174 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2175 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2176 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2181 [(set_attr "type" "fcpys,fld,fst")])
2183 (define_expand "extendsftf2"
2184 [(use (match_operand:TF 0 "register_operand" ""))
2185 (use (match_operand:SF 1 "general_operand" ""))]
2186 "TARGET_HAS_XFLOATING_LIBS"
2189 rtx tmp = gen_reg_rtx (DFmode);
2190 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2191 emit_insn (gen_extenddftf2 (operands[0], tmp));
2195 (define_expand "extenddftf2"
2196 [(use (match_operand:TF 0 "register_operand" ""))
2197 (use (match_operand:DF 1 "general_operand" ""))]
2198 "TARGET_HAS_XFLOATING_LIBS"
2199 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2202 [(set (match_operand:SF 0 "register_operand" "=&f")
2203 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2204 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2205 "cvt%-%,%)%& %R1,%0"
2206 [(set_attr "type" "fadd")
2207 (set_attr "trap" "yes")])
2209 (define_insn "truncdfsf2"
2210 [(set (match_operand:SF 0 "register_operand" "=f")
2211 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2213 "cvt%-%,%)%& %R1,%0"
2214 [(set_attr "type" "fadd")
2215 (set_attr "trap" "yes")])
2217 (define_expand "trunctfdf2"
2218 [(use (match_operand:DF 0 "register_operand" ""))
2219 (use (match_operand:TF 1 "general_operand" ""))]
2220 "TARGET_HAS_XFLOATING_LIBS"
2221 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2223 (define_expand "trunctfsf2"
2224 [(use (match_operand:SF 0 "register_operand" ""))
2225 (use (match_operand:TF 1 "general_operand" ""))]
2226 "TARGET_HAS_XFLOATING_LIBS"
2229 rtx tmpf, sticky, arg, lo, hi;
2231 tmpf = gen_reg_rtx (DFmode);
2232 sticky = gen_reg_rtx (DImode);
2233 arg = copy_to_mode_reg (TFmode, operands[1]);
2234 lo = gen_lowpart (DImode, arg);
2235 hi = gen_highpart (DImode, arg);
2237 /* Convert the low word of the TFmode value into a sticky rounding bit,
2238 then or it into the low bit of the high word. This leaves the sticky
2239 bit at bit 48 of the fraction, which is representable in DFmode,
2240 which prevents rounding error in the final conversion to SFmode. */
2242 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2243 gen_rtx_LTU (DImode, const0_rtx, lo)));
2244 emit_insn (gen_iordi3 (hi, hi, sticky));
2245 emit_insn (gen_trunctfdf2 (tmpf, arg));
2246 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2251 [(set (match_operand:SF 0 "register_operand" "=&f")
2252 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2253 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2254 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2255 "div%,%)%& %R1,%R2,%0"
2256 [(set_attr "type" "fdiv")
2257 (set_attr "opsize" "si")
2258 (set_attr "trap" "yes")])
2260 (define_insn "divsf3"
2261 [(set (match_operand:SF 0 "register_operand" "=f")
2262 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2263 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2265 "div%,%)%& %R1,%R2,%0"
2266 [(set_attr "type" "fdiv")
2267 (set_attr "opsize" "si")
2268 (set_attr "trap" "yes")])
2271 [(set (match_operand:DF 0 "register_operand" "=&f")
2272 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2273 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2274 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2275 "div%-%)%& %R1,%R2,%0"
2276 [(set_attr "type" "fdiv")
2277 (set_attr "trap" "yes")])
2279 (define_insn "divdf3"
2280 [(set (match_operand:DF 0 "register_operand" "=f")
2281 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2282 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2284 "div%-%)%& %R1,%R2,%0"
2285 [(set_attr "type" "fdiv")
2286 (set_attr "trap" "yes")])
2289 [(set (match_operand:DF 0 "register_operand" "=f")
2290 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2291 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2292 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2293 "div%-%)%& %R1,%R2,%0"
2294 [(set_attr "type" "fdiv")
2295 (set_attr "trap" "yes")])
2298 [(set (match_operand:DF 0 "register_operand" "=f")
2299 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2301 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2302 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2303 "div%-%)%& %R1,%R2,%0"
2304 [(set_attr "type" "fdiv")
2305 (set_attr "trap" "yes")])
2308 [(set (match_operand:DF 0 "register_operand" "=f")
2309 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2310 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2311 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2312 "div%-%)%& %R1,%R2,%0"
2313 [(set_attr "type" "fdiv")
2314 (set_attr "trap" "yes")])
2316 (define_expand "divtf3"
2317 [(use (match_operand 0 "register_operand" ""))
2318 (use (match_operand 1 "general_operand" ""))
2319 (use (match_operand 2 "general_operand" ""))]
2320 "TARGET_HAS_XFLOATING_LIBS"
2321 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2324 [(set (match_operand:SF 0 "register_operand" "=&f")
2325 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2326 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2327 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2328 "mul%,%)%& %R1,%R2,%0"
2329 [(set_attr "type" "fmul")
2330 (set_attr "trap" "yes")])
2332 (define_insn "mulsf3"
2333 [(set (match_operand:SF 0 "register_operand" "=f")
2334 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2335 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2337 "mul%,%)%& %R1,%R2,%0"
2338 [(set_attr "type" "fmul")
2339 (set_attr "trap" "yes")])
2342 [(set (match_operand:DF 0 "register_operand" "=&f")
2343 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2344 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2345 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2346 "mul%-%)%& %R1,%R2,%0"
2347 [(set_attr "type" "fmul")
2348 (set_attr "trap" "yes")])
2350 (define_insn "muldf3"
2351 [(set (match_operand:DF 0 "register_operand" "=f")
2352 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2353 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2355 "mul%-%)%& %R1,%R2,%0"
2356 [(set_attr "type" "fmul")
2357 (set_attr "trap" "yes")])
2360 [(set (match_operand:DF 0 "register_operand" "=f")
2361 (mult:DF (float_extend:DF
2362 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2363 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2364 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2365 "mul%-%)%& %R1,%R2,%0"
2366 [(set_attr "type" "fmul")
2367 (set_attr "trap" "yes")])
2370 [(set (match_operand:DF 0 "register_operand" "=f")
2371 (mult:DF (float_extend:DF
2372 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2374 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2375 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2376 "mul%-%)%& %R1,%R2,%0"
2377 [(set_attr "type" "fmul")
2378 (set_attr "trap" "yes")])
2380 (define_expand "multf3"
2381 [(use (match_operand 0 "register_operand" ""))
2382 (use (match_operand 1 "general_operand" ""))
2383 (use (match_operand 2 "general_operand" ""))]
2384 "TARGET_HAS_XFLOATING_LIBS"
2385 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2388 [(set (match_operand:SF 0 "register_operand" "=&f")
2389 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2390 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2391 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2392 "sub%,%)%& %R1,%R2,%0"
2393 [(set_attr "type" "fadd")
2394 (set_attr "trap" "yes")])
2396 (define_insn "subsf3"
2397 [(set (match_operand:SF 0 "register_operand" "=f")
2398 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2399 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2401 "sub%,%)%& %R1,%R2,%0"
2402 [(set_attr "type" "fadd")
2403 (set_attr "trap" "yes")])
2406 [(set (match_operand:DF 0 "register_operand" "=&f")
2407 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2408 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2409 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2410 "sub%-%)%& %R1,%R2,%0"
2411 [(set_attr "type" "fadd")
2412 (set_attr "trap" "yes")])
2414 (define_insn "subdf3"
2415 [(set (match_operand:DF 0 "register_operand" "=f")
2416 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2417 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2419 "sub%-%)%& %R1,%R2,%0"
2420 [(set_attr "type" "fadd")
2421 (set_attr "trap" "yes")])
2424 [(set (match_operand:DF 0 "register_operand" "=f")
2425 (minus:DF (float_extend:DF
2426 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2427 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2428 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2429 "sub%-%)%& %R1,%R2,%0"
2430 [(set_attr "type" "fadd")
2431 (set_attr "trap" "yes")])
2434 [(set (match_operand:DF 0 "register_operand" "=f")
2435 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2437 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2438 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2439 "sub%-%)%& %R1,%R2,%0"
2440 [(set_attr "type" "fadd")
2441 (set_attr "trap" "yes")])
2444 [(set (match_operand:DF 0 "register_operand" "=f")
2445 (minus:DF (float_extend:DF
2446 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2448 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2449 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2450 "sub%-%)%& %R1,%R2,%0"
2451 [(set_attr "type" "fadd")
2452 (set_attr "trap" "yes")])
2454 (define_expand "subtf3"
2455 [(use (match_operand 0 "register_operand" ""))
2456 (use (match_operand 1 "general_operand" ""))
2457 (use (match_operand 2 "general_operand" ""))]
2458 "TARGET_HAS_XFLOATING_LIBS"
2459 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2462 [(set (match_operand:SF 0 "register_operand" "=&f")
2463 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2464 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2466 [(set_attr "type" "fsqrt")
2467 (set_attr "opsize" "si")
2468 (set_attr "trap" "yes")])
2470 (define_insn "sqrtsf2"
2471 [(set (match_operand:SF 0 "register_operand" "=f")
2472 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2473 "TARGET_FP && TARGET_FIX"
2475 [(set_attr "type" "fsqrt")
2476 (set_attr "opsize" "si")
2477 (set_attr "trap" "yes")])
2480 [(set (match_operand:DF 0 "register_operand" "=&f")
2481 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2482 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2484 [(set_attr "type" "fsqrt")
2485 (set_attr "trap" "yes")])
2487 (define_insn "sqrtdf2"
2488 [(set (match_operand:DF 0 "register_operand" "=f")
2489 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2490 "TARGET_FP && TARGET_FIX"
2492 [(set_attr "type" "fsqrt")
2493 (set_attr "trap" "yes")])
2495 ;; Next are all the integer comparisons, and conditional moves and branches
2496 ;; and some of the related define_expand's and define_split's.
2499 [(set (match_operand:DI 0 "register_operand" "=r")
2500 (match_operator:DI 1 "alpha_comparison_operator"
2501 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2502 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2505 [(set_attr "type" "icmp")])
2508 [(set (match_operand:DI 0 "register_operand" "=r")
2509 (match_operator:DI 1 "alpha_swapped_comparison_operator"
2510 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2511 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2514 [(set_attr "type" "icmp")])
2516 ;; This pattern exists so conditional moves of SImode values are handled.
2517 ;; Comparisons are still done in DImode though.
2520 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2522 (match_operator 2 "signed_comparison_operator"
2523 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2524 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2525 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2526 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2527 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2533 [(set_attr "type" "icmov")])
2536 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2538 (match_operator 2 "signed_comparison_operator"
2539 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2540 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2541 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2542 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2543 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2549 [(set_attr "type" "icmov")])
2552 [(set (match_operand:DI 0 "register_operand" "=r,r")
2554 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2558 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2559 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2564 [(set_attr "type" "icmov")])
2567 [(set (match_operand:DI 0 "register_operand" "=r,r")
2569 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2573 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2574 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2579 [(set_attr "type" "icmov")])
2581 ;; For ABS, we have two choices, depending on whether the input and output
2582 ;; registers are the same or not.
2583 (define_expand "absdi2"
2584 [(set (match_operand:DI 0 "register_operand" "")
2585 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2588 { if (rtx_equal_p (operands[0], operands[1]))
2589 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2591 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2596 (define_expand "absdi2_same"
2597 [(set (match_operand:DI 1 "register_operand" "")
2598 (neg:DI (match_operand:DI 0 "register_operand" "")))
2600 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2606 (define_expand "absdi2_diff"
2607 [(set (match_operand:DI 0 "register_operand" "")
2608 (neg:DI (match_operand:DI 1 "register_operand" "")))
2610 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2617 [(set (match_operand:DI 0 "register_operand" "")
2618 (abs:DI (match_dup 0)))
2619 (clobber (match_operand:DI 2 "register_operand" ""))]
2621 [(set (match_dup 1) (neg:DI (match_dup 0)))
2622 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2623 (match_dup 0) (match_dup 1)))]
2627 [(set (match_operand:DI 0 "register_operand" "")
2628 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2629 "! rtx_equal_p (operands[0], operands[1])"
2630 [(set (match_dup 0) (neg:DI (match_dup 1)))
2631 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2632 (match_dup 0) (match_dup 1)))]
2636 [(set (match_operand:DI 0 "register_operand" "")
2637 (neg:DI (abs:DI (match_dup 0))))
2638 (clobber (match_operand:DI 2 "register_operand" ""))]
2640 [(set (match_dup 1) (neg:DI (match_dup 0)))
2641 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2642 (match_dup 0) (match_dup 1)))]
2646 [(set (match_operand:DI 0 "register_operand" "")
2647 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2648 "! rtx_equal_p (operands[0], operands[1])"
2649 [(set (match_dup 0) (neg:DI (match_dup 1)))
2650 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2651 (match_dup 0) (match_dup 1)))]
2654 (define_insn "sminqi3"
2655 [(set (match_operand:QI 0 "register_operand" "=r")
2656 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2657 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2660 [(set_attr "type" "mvi")])
2662 (define_insn "uminqi3"
2663 [(set (match_operand:QI 0 "register_operand" "=r")
2664 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2665 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2668 [(set_attr "type" "mvi")])
2670 (define_insn "smaxqi3"
2671 [(set (match_operand:QI 0 "register_operand" "=r")
2672 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2673 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2676 [(set_attr "type" "mvi")])
2678 (define_insn "umaxqi3"
2679 [(set (match_operand:QI 0 "register_operand" "=r")
2680 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2681 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2684 [(set_attr "type" "mvi")])
2686 (define_insn "sminhi3"
2687 [(set (match_operand:HI 0 "register_operand" "=r")
2688 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2689 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2692 [(set_attr "type" "mvi")])
2694 (define_insn "uminhi3"
2695 [(set (match_operand:HI 0 "register_operand" "=r")
2696 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2697 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2700 [(set_attr "type" "mvi")])
2702 (define_insn "smaxhi3"
2703 [(set (match_operand:HI 0 "register_operand" "=r")
2704 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2705 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2708 [(set_attr "type" "mvi")])
2710 (define_insn "umaxhi3"
2711 [(set (match_operand:HI 0 "register_operand" "=r")
2712 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2713 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2716 [(set_attr "type" "shift")])
2718 (define_expand "smaxdi3"
2720 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2721 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2722 (set (match_operand:DI 0 "register_operand" "")
2723 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2724 (match_dup 1) (match_dup 2)))]
2727 { operands[3] = gen_reg_rtx (DImode);
2731 [(set (match_operand:DI 0 "register_operand" "")
2732 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2733 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2734 (clobber (match_operand:DI 3 "register_operand" ""))]
2735 "operands[2] != const0_rtx"
2736 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2737 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2738 (match_dup 1) (match_dup 2)))]
2742 [(set (match_operand:DI 0 "register_operand" "=r")
2743 (smax:DI (match_operand:DI 1 "register_operand" "0")
2747 [(set_attr "type" "icmov")])
2749 (define_expand "smindi3"
2751 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2752 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2753 (set (match_operand:DI 0 "register_operand" "")
2754 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2755 (match_dup 1) (match_dup 2)))]
2758 { operands[3] = gen_reg_rtx (DImode);
2762 [(set (match_operand:DI 0 "register_operand" "")
2763 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2764 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2765 (clobber (match_operand:DI 3 "register_operand" ""))]
2766 "operands[2] != const0_rtx"
2767 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2768 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2769 (match_dup 1) (match_dup 2)))]
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (smin:DI (match_operand:DI 1 "register_operand" "0")
2778 [(set_attr "type" "icmov")])
2780 (define_expand "umaxdi3"
2782 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2783 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2784 (set (match_operand:DI 0 "register_operand" "")
2785 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2786 (match_dup 1) (match_dup 2)))]
2789 { operands[3] = gen_reg_rtx (DImode);
2793 [(set (match_operand:DI 0 "register_operand" "")
2794 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2795 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2796 (clobber (match_operand:DI 3 "register_operand" ""))]
2797 "operands[2] != const0_rtx"
2798 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2799 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2800 (match_dup 1) (match_dup 2)))]
2803 (define_expand "umindi3"
2805 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2806 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2807 (set (match_operand:DI 0 "register_operand" "")
2808 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2809 (match_dup 1) (match_dup 2)))]
2812 { operands[3] = gen_reg_rtx (DImode);
2816 [(set (match_operand:DI 0 "register_operand" "")
2817 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2818 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2819 (clobber (match_operand:DI 3 "register_operand" ""))]
2820 "operands[2] != const0_rtx"
2821 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2822 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2823 (match_dup 1) (match_dup 2)))]
2829 (match_operator 1 "signed_comparison_operator"
2830 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2832 (label_ref (match_operand 0 "" ""))
2836 [(set_attr "type" "ibr")])
2841 (match_operator 1 "signed_comparison_operator"
2843 (match_operand:DI 2 "register_operand" "r")])
2844 (label_ref (match_operand 0 "" ""))
2848 [(set_attr "type" "ibr")])
2853 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2857 (label_ref (match_operand 0 "" ""))
2861 [(set_attr "type" "ibr")])
2866 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2870 (label_ref (match_operand 0 "" ""))
2874 [(set_attr "type" "ibr")])
2880 (match_operator 1 "comparison_operator"
2881 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2883 (match_operand:DI 3 "const_int_operand" ""))
2885 (label_ref (match_operand 0 "" ""))
2887 (clobber (match_operand:DI 4 "register_operand" ""))])]
2888 "INTVAL (operands[3]) != 0"
2890 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2892 (if_then_else (match_op_dup 1
2893 [(zero_extract:DI (match_dup 4)
2897 (label_ref (match_dup 0))
2901 ;; The following are the corresponding floating-point insns. Recall
2902 ;; we need to have variants that expand the arguments from SFmode
2905 (define_insn "*cmpdf_tp"
2906 [(set (match_operand:DF 0 "register_operand" "=&f")
2907 (match_operator:DF 1 "alpha_fp_comparison_operator"
2908 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2909 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2910 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2911 "cmp%-%C1%' %R2,%R3,%0"
2912 [(set_attr "type" "fadd")
2913 (set_attr "trap" "yes")])
2915 (define_insn "*cmpdf_no_tp"
2916 [(set (match_operand:DF 0 "register_operand" "=f")
2917 (match_operator:DF 1 "alpha_fp_comparison_operator"
2918 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2919 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2920 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2921 "cmp%-%C1%' %R2,%R3,%0"
2922 [(set_attr "type" "fadd")
2923 (set_attr "trap" "yes")])
2926 [(set (match_operand:DF 0 "register_operand" "=&f")
2927 (match_operator:DF 1 "alpha_fp_comparison_operator"
2929 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2930 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2931 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2932 "cmp%-%C1%' %R2,%R3,%0"
2933 [(set_attr "type" "fadd")
2934 (set_attr "trap" "yes")])
2937 [(set (match_operand:DF 0 "register_operand" "=f")
2938 (match_operator:DF 1 "alpha_fp_comparison_operator"
2940 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2941 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2942 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2943 "cmp%-%C1%' %R2,%R3,%0"
2944 [(set_attr "type" "fadd")
2945 (set_attr "trap" "yes")])
2948 [(set (match_operand:DF 0 "register_operand" "=&f")
2949 (match_operator:DF 1 "alpha_fp_comparison_operator"
2950 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2952 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2953 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2954 "cmp%-%C1%' %R2,%R3,%0"
2955 [(set_attr "type" "fadd")
2956 (set_attr "trap" "yes")])
2959 [(set (match_operand:DF 0 "register_operand" "=f")
2960 (match_operator:DF 1 "alpha_fp_comparison_operator"
2961 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2963 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2964 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2965 "cmp%-%C1%' %R2,%R3,%0"
2966 [(set_attr "type" "fadd")
2967 (set_attr "trap" "yes")])
2970 [(set (match_operand:DF 0 "register_operand" "=&f")
2971 (match_operator:DF 1 "alpha_fp_comparison_operator"
2973 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2975 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2976 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2977 "cmp%-%C1%' %R2,%R3,%0"
2978 [(set_attr "type" "fadd")
2979 (set_attr "trap" "yes")])
2982 [(set (match_operand:DF 0 "register_operand" "=f")
2983 (match_operator:DF 1 "alpha_fp_comparison_operator"
2985 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2987 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2988 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2989 "cmp%-%C1%' %R2,%R3,%0"
2990 [(set_attr "type" "fadd")
2991 (set_attr "trap" "yes")])
2994 [(set (match_operand:DF 0 "register_operand" "=f,f")
2996 (match_operator 3 "signed_comparison_operator"
2997 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2998 (match_operand:DF 2 "fp0_operand" "G,G")])
2999 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3000 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3004 fcmov%D3 %R4,%R5,%0"
3005 [(set_attr "type" "fcmov")])
3008 [(set (match_operand:SF 0 "register_operand" "=f,f")
3010 (match_operator 3 "signed_comparison_operator"
3011 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3012 (match_operand:DF 2 "fp0_operand" "G,G")])
3013 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3014 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3018 fcmov%D3 %R4,%R5,%0"
3019 [(set_attr "type" "fcmov")])
3022 [(set (match_operand:DF 0 "register_operand" "=f,f")
3024 (match_operator 3 "signed_comparison_operator"
3025 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3026 (match_operand:DF 2 "fp0_operand" "G,G")])
3027 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3028 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3032 fcmov%D3 %R4,%R5,%0"
3033 [(set_attr "type" "fcmov")])
3036 [(set (match_operand:DF 0 "register_operand" "=f,f")
3038 (match_operator 3 "signed_comparison_operator"
3040 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3041 (match_operand:DF 2 "fp0_operand" "G,G")])
3042 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3043 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3047 fcmov%D3 %R4,%R5,%0"
3048 [(set_attr "type" "fcmov")])
3051 [(set (match_operand:SF 0 "register_operand" "=f,f")
3053 (match_operator 3 "signed_comparison_operator"
3055 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3056 (match_operand:DF 2 "fp0_operand" "G,G")])
3057 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3058 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3062 fcmov%D3 %R4,%R5,%0"
3063 [(set_attr "type" "fcmov")])
3066 [(set (match_operand:DF 0 "register_operand" "=f,f")
3068 (match_operator 3 "signed_comparison_operator"
3070 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3071 (match_operand:DF 2 "fp0_operand" "G,G")])
3072 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3073 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3077 fcmov%D3 %R4,%R5,%0"
3078 [(set_attr "type" "fcmov")])
3080 (define_expand "maxdf3"
3082 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3083 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3084 (set (match_operand:DF 0 "register_operand" "")
3085 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3086 (match_dup 1) (match_dup 2)))]
3089 { operands[3] = gen_reg_rtx (DFmode);
3090 operands[4] = CONST0_RTX (DFmode);
3093 (define_expand "mindf3"
3095 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3096 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3097 (set (match_operand:DF 0 "register_operand" "")
3098 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3099 (match_dup 1) (match_dup 2)))]
3102 { operands[3] = gen_reg_rtx (DFmode);
3103 operands[4] = CONST0_RTX (DFmode);
3106 (define_expand "maxsf3"
3108 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3109 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3110 (set (match_operand:SF 0 "register_operand" "")
3111 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3112 (match_dup 1) (match_dup 2)))]
3115 { operands[3] = gen_reg_rtx (DFmode);
3116 operands[4] = CONST0_RTX (DFmode);
3119 (define_expand "minsf3"
3121 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3122 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3123 (set (match_operand:SF 0 "register_operand" "")
3124 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3125 (match_dup 1) (match_dup 2)))]
3128 { operands[3] = gen_reg_rtx (DFmode);
3129 operands[4] = CONST0_RTX (DFmode);
3135 (match_operator 1 "signed_comparison_operator"
3136 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3137 (match_operand:DF 3 "fp0_operand" "G")])
3138 (label_ref (match_operand 0 "" ""))
3142 [(set_attr "type" "fbr")])
3147 (match_operator 1 "signed_comparison_operator"
3149 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3150 (match_operand:DF 3 "fp0_operand" "G")])
3151 (label_ref (match_operand 0 "" ""))
3155 [(set_attr "type" "fbr")])
3157 ;; These are the main define_expand's used to make conditional branches
3160 (define_expand "cmpdf"
3161 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3162 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3166 alpha_compare.op0 = operands[0];
3167 alpha_compare.op1 = operands[1];
3168 alpha_compare.fp_p = 1;
3172 (define_expand "cmptf"
3173 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3174 (match_operand:TF 1 "general_operand" "")))]
3175 "TARGET_HAS_XFLOATING_LIBS"
3178 alpha_compare.op0 = operands[0];
3179 alpha_compare.op1 = operands[1];
3180 alpha_compare.fp_p = 1;
3184 (define_expand "cmpdi"
3185 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3186 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3190 alpha_compare.op0 = operands[0];
3191 alpha_compare.op1 = operands[1];
3192 alpha_compare.fp_p = 0;
3196 (define_expand "beq"
3198 (if_then_else (match_dup 1)
3199 (label_ref (match_operand 0 "" ""))
3202 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3204 (define_expand "bne"
3206 (if_then_else (match_dup 1)
3207 (label_ref (match_operand 0 "" ""))
3210 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3212 (define_expand "blt"
3214 (if_then_else (match_dup 1)
3215 (label_ref (match_operand 0 "" ""))
3218 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3220 (define_expand "ble"
3222 (if_then_else (match_dup 1)
3223 (label_ref (match_operand 0 "" ""))
3226 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3228 (define_expand "bgt"
3230 (if_then_else (match_dup 1)
3231 (label_ref (match_operand 0 "" ""))
3234 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3236 (define_expand "bge"
3238 (if_then_else (match_dup 1)
3239 (label_ref (match_operand 0 "" ""))
3242 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3244 (define_expand "bltu"
3246 (if_then_else (match_dup 1)
3247 (label_ref (match_operand 0 "" ""))
3250 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3252 (define_expand "bleu"
3254 (if_then_else (match_dup 1)
3255 (label_ref (match_operand 0 "" ""))
3258 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3260 (define_expand "bgtu"
3262 (if_then_else (match_dup 1)
3263 (label_ref (match_operand 0 "" ""))
3266 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3268 (define_expand "bgeu"
3270 (if_then_else (match_dup 1)
3271 (label_ref (match_operand 0 "" ""))
3274 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3276 (define_expand "bunordered"
3278 (if_then_else (match_dup 1)
3279 (label_ref (match_operand 0 "" ""))
3282 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3284 (define_expand "bordered"
3286 (if_then_else (match_dup 1)
3287 (label_ref (match_operand 0 "" ""))
3290 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3292 (define_expand "seq"
3293 [(set (match_operand:DI 0 "register_operand" "")
3298 if (alpha_compare.fp_p)
3301 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3302 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3305 (define_expand "sne"
3306 [(set (match_operand:DI 0 "register_operand" "")
3308 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3312 if (alpha_compare.fp_p)
3315 if (alpha_compare.op1 == const0_rtx)
3317 emit_insn (gen_sgtu (operands[0]));
3321 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3322 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3325 (define_expand "slt"
3326 [(set (match_operand:DI 0 "register_operand" "")
3331 if (alpha_compare.fp_p)
3334 operands[1] = gen_rtx_LT (DImode, alpha_compare.op0, alpha_compare.op1);
3335 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3338 (define_expand "sle"
3339 [(set (match_operand:DI 0 "register_operand" "")
3344 if (alpha_compare.fp_p)
3347 operands[1] = gen_rtx_LE (DImode, alpha_compare.op0, alpha_compare.op1);
3348 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3351 (define_expand "sgt"
3352 [(set (match_operand:DI 0 "register_operand" "")
3357 if (alpha_compare.fp_p)
3360 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare.op1),
3362 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3365 (define_expand "sge"
3366 [(set (match_operand:DI 0 "register_operand" "")
3371 if (alpha_compare.fp_p)
3374 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare.op1),
3376 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3379 (define_expand "sltu"
3380 [(set (match_operand:DI 0 "register_operand" "")
3385 if (alpha_compare.fp_p)
3388 operands[1] = gen_rtx_LTU (DImode, alpha_compare.op0, alpha_compare.op1);
3389 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3392 (define_expand "sleu"
3393 [(set (match_operand:DI 0 "register_operand" "")
3398 if (alpha_compare.fp_p)
3401 operands[1] = gen_rtx_LEU (DImode, alpha_compare.op0, alpha_compare.op1);
3402 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3405 (define_expand "sgtu"
3406 [(set (match_operand:DI 0 "register_operand" "")
3411 if (alpha_compare.fp_p)
3414 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare.op1),
3416 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3419 (define_expand "sgeu"
3420 [(set (match_operand:DI 0 "register_operand" "")
3425 if (alpha_compare.fp_p)
3428 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare.op1),
3430 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3433 ;; These are the main define_expand's used to make conditional moves.
3435 (define_expand "movsicc"
3436 [(set (match_operand:SI 0 "register_operand" "")
3437 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3438 (match_operand:SI 2 "reg_or_8bit_operand" "")
3439 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3443 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3447 (define_expand "movdicc"
3448 [(set (match_operand:DI 0 "register_operand" "")
3449 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3450 (match_operand:DI 2 "reg_or_8bit_operand" "")
3451 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3455 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3459 (define_expand "movsfcc"
3460 [(set (match_operand:SF 0 "register_operand" "")
3461 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3462 (match_operand:SF 2 "reg_or_8bit_operand" "")
3463 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3467 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3471 (define_expand "movdfcc"
3472 [(set (match_operand:DF 0 "register_operand" "")
3473 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3474 (match_operand:DF 2 "reg_or_8bit_operand" "")
3475 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3479 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3483 ;; These define_split definitions are used in cases when comparisons have
3484 ;; not be stated in the correct way and we need to reverse the second
3485 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3486 ;; comparison that tests the result being reversed. We have one define_split
3487 ;; for each use of a comparison. They do not match valid insns and need
3488 ;; not generate valid insns.
3490 ;; We can also handle equality comparisons (and inequality comparisons in
3491 ;; cases where the resulting add cannot overflow) by doing an add followed by
3492 ;; a comparison with zero. This is faster since the addition takes one
3493 ;; less cycle than a compare when feeding into a conditional move.
3494 ;; For this case, we also have an SImode pattern since we can merge the add
3495 ;; and sign extend and the order doesn't matter.
3497 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3498 ;; operation could have been generated.
3501 [(set (match_operand:DI 0 "register_operand" "")
3503 (match_operator 1 "comparison_operator"
3504 [(match_operand:DI 2 "reg_or_0_operand" "")
3505 (match_operand:DI 3 "reg_or_cint_operand" "")])
3506 (match_operand:DI 4 "reg_or_cint_operand" "")
3507 (match_operand:DI 5 "reg_or_cint_operand" "")))
3508 (clobber (match_operand:DI 6 "register_operand" ""))]
3509 "operands[3] != const0_rtx"
3510 [(set (match_dup 6) (match_dup 7))
3512 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3514 { enum rtx_code code = GET_CODE (operands[1]);
3515 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3517 /* If we are comparing for equality with a constant and that constant
3518 appears in the arm when the register equals the constant, use the
3519 register since that is more likely to match (and to produce better code
3522 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3523 && rtx_equal_p (operands[4], operands[3]))
3524 operands[4] = operands[2];
3526 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3527 && rtx_equal_p (operands[5], operands[3]))
3528 operands[5] = operands[2];
3530 if (code == NE || code == EQ
3531 || (extended_count (operands[2], DImode, unsignedp) >= 1
3532 && extended_count (operands[3], DImode, unsignedp) >= 1))
3534 if (GET_CODE (operands[3]) == CONST_INT)
3535 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3536 GEN_INT (- INTVAL (operands[3])));
3538 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3540 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3543 else if (code == EQ || code == LE || code == LT
3544 || code == LEU || code == LTU)
3546 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3547 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3551 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3552 operands[2], operands[3]);
3553 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3558 [(set (match_operand:DI 0 "register_operand" "")
3560 (match_operator 1 "comparison_operator"
3561 [(match_operand:SI 2 "reg_or_0_operand" "")
3562 (match_operand:SI 3 "reg_or_cint_operand" "")])
3563 (match_operand:DI 4 "reg_or_8bit_operand" "")
3564 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3565 (clobber (match_operand:DI 6 "register_operand" ""))]
3566 "operands[3] != const0_rtx
3567 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3568 [(set (match_dup 6) (match_dup 7))
3570 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3572 { enum rtx_code code = GET_CODE (operands[1]);
3573 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3576 if ((code != NE && code != EQ
3577 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3578 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3581 if (GET_CODE (operands[3]) == CONST_INT)
3582 tem = gen_rtx_PLUS (SImode, operands[2],
3583 GEN_INT (- INTVAL (operands[3])));
3585 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3587 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3588 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3589 operands[6], const0_rtx);
3595 (match_operator 1 "comparison_operator"
3596 [(match_operand:DI 2 "reg_or_0_operand" "")
3597 (match_operand:DI 3 "reg_or_cint_operand" "")])
3598 (label_ref (match_operand 0 "" ""))
3600 (clobber (match_operand:DI 4 "register_operand" ""))]
3601 "operands[3] != const0_rtx"
3602 [(set (match_dup 4) (match_dup 5))
3603 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3605 { enum rtx_code code = GET_CODE (operands[1]);
3606 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3608 if (code == NE || code == EQ
3609 || (extended_count (operands[2], DImode, unsignedp) >= 1
3610 && extended_count (operands[3], DImode, unsignedp) >= 1))
3612 if (GET_CODE (operands[3]) == CONST_INT)
3613 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3614 GEN_INT (- INTVAL (operands[3])));
3616 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3618 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3621 else if (code == EQ || code == LE || code == LT
3622 || code == LEU || code == LTU)
3624 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3625 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3629 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3630 operands[2], operands[3]);
3631 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3638 (match_operator 1 "comparison_operator"
3639 [(match_operand:SI 2 "reg_or_0_operand" "")
3640 (match_operand:SI 3 "const_int_operand" "")])
3641 (label_ref (match_operand 0 "" ""))
3643 (clobber (match_operand:DI 4 "register_operand" ""))]
3644 "operands[3] != const0_rtx
3645 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3646 [(set (match_dup 4) (match_dup 5))
3647 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3651 if (GET_CODE (operands[3]) == CONST_INT)
3652 tem = gen_rtx_PLUS (SImode, operands[2],
3653 GEN_INT (- INTVAL (operands[3])));
3655 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3657 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3658 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3659 operands[4], const0_rtx);
3662 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3663 ;; This eliminates one, and sometimes two, insns when the AND can be done
3666 [(set (match_operand:DI 0 "register_operand" "")
3667 (match_operator:DI 1 "comparison_operator"
3668 [(match_operand:DI 2 "register_operand" "")
3669 (match_operand:DI 3 "const_int_operand" "")]))
3670 (clobber (match_operand:DI 4 "register_operand" ""))]
3671 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3672 && (GET_CODE (operands[1]) == GTU
3673 || GET_CODE (operands[1]) == LEU
3674 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3675 && extended_count (operands[2], DImode, 1) > 0))"
3676 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3677 (set (match_dup 0) (match_dup 6))]
3680 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3681 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3682 || GET_CODE (operands[1]) == GT)
3684 DImode, operands[4], const0_rtx);
3687 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3688 ;; work differently, so we have different patterns for each.
3690 (define_expand "call"
3691 [(use (match_operand:DI 0 "" ""))
3692 (use (match_operand 1 "" ""))
3693 (use (match_operand 2 "" ""))
3694 (use (match_operand 3 "" ""))]
3697 { if (TARGET_WINDOWS_NT)
3698 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3699 else if (TARGET_OPEN_VMS)
3700 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3702 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3707 (define_expand "call_osf"
3708 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3709 (match_operand 1 "" ""))
3710 (clobber (reg:DI 27))
3711 (clobber (reg:DI 26))])]
3714 { if (GET_CODE (operands[0]) != MEM)
3717 operands[0] = XEXP (operands[0], 0);
3719 if (GET_CODE (operands[0]) != SYMBOL_REF
3720 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3722 rtx tem = gen_rtx_REG (DImode, 27);
3723 emit_move_insn (tem, operands[0]);
3728 (define_expand "call_nt"
3729 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3730 (match_operand 1 "" ""))
3731 (clobber (reg:DI 26))])]
3734 { if (GET_CODE (operands[0]) != MEM)
3737 operands[0] = XEXP (operands[0], 0);
3738 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3739 operands[0] = force_reg (DImode, operands[0]);
3743 ;; call openvms/alpha
3744 ;; op 0: symbol ref for called function
3745 ;; op 1: next_arg_reg (argument information value for R25)
3747 (define_expand "call_vms"
3748 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3749 (match_operand 1 "" ""))
3753 (clobber (reg:DI 27))])]
3756 { if (GET_CODE (operands[0]) != MEM)
3759 operands[0] = XEXP (operands[0], 0);
3761 /* Always load AI with argument information, then handle symbolic and
3762 indirect call differently. Load RA and set operands[2] to PV in
3765 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3766 if (GET_CODE (operands[0]) == SYMBOL_REF)
3768 extern char *savealloc ();
3769 const char *symbol = XSTR (operands[0], 0);
3775 linksym = savealloc (strlen (symbol) + 6);
3777 alpha_need_linkage (symbol, 0);
3780 strcpy (linksym+1, symbol);
3781 strcat (linksym, \"..lk\");
3782 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3784 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3787 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3791 emit_move_insn (gen_rtx_REG (Pmode, 26),
3792 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3794 operands[2] = operands[0];
3799 (define_expand "call_value"
3800 [(use (match_operand 0 "" ""))
3801 (use (match_operand:DI 1 "" ""))
3802 (use (match_operand 2 "" ""))
3803 (use (match_operand 3 "" ""))
3804 (use (match_operand 4 "" ""))]
3807 { if (TARGET_WINDOWS_NT)
3808 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3809 else if (TARGET_OPEN_VMS)
3810 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3813 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3818 (define_expand "call_value_osf"
3819 [(parallel [(set (match_operand 0 "" "")
3820 (call (mem:DI (match_operand 1 "" ""))
3821 (match_operand 2 "" "")))
3822 (clobber (reg:DI 27))
3823 (clobber (reg:DI 26))])]
3826 { if (GET_CODE (operands[1]) != MEM)
3829 operands[1] = XEXP (operands[1], 0);
3831 if (GET_CODE (operands[1]) != SYMBOL_REF
3832 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3834 rtx tem = gen_rtx_REG (DImode, 27);
3835 emit_move_insn (tem, operands[1]);
3840 (define_expand "call_value_nt"
3841 [(parallel [(set (match_operand 0 "" "")
3842 (call (mem:DI (match_operand 1 "" ""))
3843 (match_operand 2 "" "")))
3844 (clobber (reg:DI 26))])]
3847 { if (GET_CODE (operands[1]) != MEM)
3850 operands[1] = XEXP (operands[1], 0);
3851 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
3852 operands[1] = force_reg (DImode, operands[1]);
3855 (define_expand "call_value_vms"
3856 [(parallel [(set (match_operand 0 "" "")
3857 (call (mem:DI (match_operand:DI 1 "" ""))
3858 (match_operand 2 "" "")))
3862 (clobber (reg:DI 27))])]
3865 { if (GET_CODE (operands[1]) != MEM)
3868 operands[1] = XEXP (operands[1], 0);
3870 /* Always load AI with argument information, then handle symbolic and
3871 indirect call differently. Load RA and set operands[3] to PV in
3874 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3875 if (GET_CODE (operands[1]) == SYMBOL_REF)
3877 extern char *savealloc ();
3878 const char *symbol = XSTR (operands[1], 0);
3884 linksym = savealloc (strlen (symbol) + 6);
3886 alpha_need_linkage (symbol, 0);
3888 strcpy (linksym+1, symbol);
3889 strcat (linksym, \"..lk\");
3890 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3892 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3895 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3899 emit_move_insn (gen_rtx_REG (Pmode, 26),
3900 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
3902 operands[3] = operands[1];
3907 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3908 (match_operand 1 "" ""))
3909 (clobber (reg:DI 27))
3910 (clobber (reg:DI 26))]
3911 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3913 jsr $26,($27),0\;ldgp $29,0($26)
3915 jsr $26,%0\;ldgp $29,0($26)"
3916 [(set_attr "type" "jsr")
3917 (set_attr "length" "12,*,16")])
3920 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3921 (match_operand 1 "" ""))
3922 (clobber (reg:DI 26))]
3928 [(set_attr "type" "jsr")
3929 (set_attr "length" "*,*,12")])
3932 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3933 (match_operand 1 "" ""))
3934 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
3937 (clobber (reg:DI 27))]
3940 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
3941 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3942 [(set_attr "type" "jsr")
3943 (set_attr "length" "12,16")])
3945 ;; Call subroutine returning any type.
3947 (define_expand "untyped_call"
3948 [(parallel [(call (match_operand 0 "" "")
3950 (match_operand 1 "" "")
3951 (match_operand 2 "" "")])]
3957 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3959 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3961 rtx set = XVECEXP (operands[2], 0, i);
3962 emit_move_insn (SET_DEST (set), SET_SRC (set));
3965 /* The optimizer does not know that the call sets the function value
3966 registers we stored in the result block. We avoid problems by
3967 claiming that all hard registers are used and clobbered at this
3969 emit_insn (gen_blockage ());
3974 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3975 ;; all of memory. This blocks insns from being moved across this point.
3977 (define_insn "blockage"
3978 [(unspec_volatile [(const_int 0)] 1)]
3981 [(set_attr "length" "0")])
3985 (label_ref (match_operand 0 "" "")))]
3988 [(set_attr "type" "ibr")])
3990 (define_expand "return"
3995 (define_insn "*return_internal"
3999 [(set_attr "type" "ibr")])
4001 (define_insn "indirect_jump"
4002 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4005 [(set_attr "type" "ibr")])
4007 (define_expand "tablejump"
4008 [(use (match_operand:SI 0 "register_operand" ""))
4009 (use (match_operand:SI 1 "" ""))]
4013 if (TARGET_WINDOWS_NT)
4014 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4015 else if (TARGET_OPEN_VMS)
4016 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4018 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4023 (define_expand "tablejump_osf"
4025 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4026 (parallel [(set (pc)
4027 (plus:DI (match_dup 3)
4028 (label_ref (match_operand 1 "" ""))))
4029 (clobber (match_scratch:DI 2 "=r"))])]
4032 { operands[3] = gen_reg_rtx (DImode); }")
4034 (define_expand "tablejump_nt"
4036 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4037 (parallel [(set (pc)
4039 (use (label_ref (match_operand 1 "" "")))])]
4042 { operands[3] = gen_reg_rtx (DImode); }")
4045 ;; tablejump, openVMS way
4047 ;; op 1: label preceding jump-table
4049 (define_expand "tablejump_vms"
4051 (match_operand:DI 0 "register_operand" ""))
4053 (plus:DI (match_dup 2)
4054 (label_ref (match_operand 1 "" ""))))]
4057 { operands[2] = gen_reg_rtx (DImode); }")
4061 (plus (match_operand:DI 0 "register_operand" "r")
4062 (label_ref (match_operand 1 "" ""))))
4063 (clobber (match_scratch:DI 2 "=r"))]
4064 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
4065 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4066 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4068 { rtx best_label = 0;
4069 rtx jump_table_insn = next_active_insn (operands[1]);
4071 if (GET_CODE (jump_table_insn) == JUMP_INSN
4072 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4074 rtx jump_table = PATTERN (jump_table_insn);
4075 int n_labels = XVECLEN (jump_table, 1);
4076 int best_count = -1;
4079 for (i = 0; i < n_labels; i++)
4083 for (j = i + 1; j < n_labels; j++)
4084 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4085 == XEXP (XVECEXP (jump_table, 1, j), 0))
4088 if (count > best_count)
4089 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4095 operands[3] = best_label;
4096 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
4099 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
4101 [(set_attr "type" "ibr")
4102 (set_attr "length" "8")])
4106 (match_operand:DI 0 "register_operand" "r"))
4107 (use (label_ref (match_operand 1 "" "")))]
4108 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
4109 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4110 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4112 { rtx best_label = 0;
4113 rtx jump_table_insn = next_active_insn (operands[1]);
4115 if (GET_CODE (jump_table_insn) == JUMP_INSN
4116 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4118 rtx jump_table = PATTERN (jump_table_insn);
4119 int n_labels = XVECLEN (jump_table, 1);
4120 int best_count = -1;
4123 for (i = 0; i < n_labels; i++)
4127 for (j = i + 1; j < n_labels; j++)
4128 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4129 == XEXP (XVECEXP (jump_table, 1, j), 0))
4132 if (count > best_count)
4133 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4139 operands[2] = best_label;
4140 return \"jmp $31,(%0),%2\";
4143 return \"jmp $31,(%0),0\";
4145 [(set_attr "type" "ibr")])
4148 ;; op 0 is table offset
4149 ;; op 1 is table label
4154 (plus (match_operand:DI 0 "register_operand" "r")
4155 (label_ref (match_operand 1 "" ""))))]
4158 [(set_attr "type" "ibr")])
4160 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4161 ;; want to have to include pal.h in our .s file.
4163 ;; Technically the type for call_pal is jsr, but we use that for determining
4164 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4167 [(unspec_volatile [(const_int 0)] 0)]
4170 [(set_attr "type" "ibr")])
4172 ;; Finally, we have the basic data motion insns. The byte and word insns
4173 ;; are done via define_expand. Start with the floating-point insns, since
4174 ;; they are simpler.
4177 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4178 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4180 && (register_operand (operands[0], SFmode)
4181 || reg_or_fp0_operand (operands[1], SFmode))"
4189 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4192 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4193 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4195 && (register_operand (operands[0], SFmode)
4196 || reg_or_fp0_operand (operands[1], SFmode))"
4206 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4209 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4210 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4212 && (register_operand (operands[0], DFmode)
4213 || reg_or_fp0_operand (operands[1], DFmode))"
4221 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4224 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4225 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4227 && (register_operand (operands[0], DFmode)
4228 || reg_or_fp0_operand (operands[1], DFmode))"
4238 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4240 ;; Subregs suck for register allocation. Pretend we can move TFmode
4241 ;; data between general registers until after reload.
4243 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4244 (match_operand:TF 1 "input_operand" "roG,r"))]
4245 "register_operand (operands[0], TFmode)
4246 || reg_or_fp0_operand (operands[1], TFmode)"
4250 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4251 (match_operand:TF 1 "input_operand" ""))]
4253 [(set (match_dup 0) (match_dup 2))
4254 (set (match_dup 1) (match_dup 3))]
4257 alpha_split_tfmode_pair (operands);
4258 if (rtx_equal_p (operands[0], operands[3]))
4261 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4262 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4266 (define_expand "movsf"
4267 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4268 (match_operand:SF 1 "general_operand" ""))]
4272 if (GET_CODE (operands[0]) == MEM
4273 && ! reg_or_fp0_operand (operands[1], SFmode))
4274 operands[1] = force_reg (SFmode, operands[1]);
4277 (define_expand "movdf"
4278 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4279 (match_operand:DF 1 "general_operand" ""))]
4283 if (GET_CODE (operands[0]) == MEM
4284 && ! reg_or_fp0_operand (operands[1], DFmode))
4285 operands[1] = force_reg (DFmode, operands[1]);
4288 (define_expand "movtf"
4289 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4290 (match_operand:TF 1 "general_operand" ""))]
4294 if (GET_CODE (operands[0]) == MEM
4295 && ! reg_or_fp0_operand (operands[1], TFmode))
4296 operands[1] = force_reg (TFmode, operands[1]);
4300 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4301 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4302 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4303 && (register_operand (operands[0], SImode)
4304 || reg_or_0_operand (operands[1], SImode))"
4314 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4317 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4318 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4319 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4320 && (register_operand (operands[0], SImode)
4321 || reg_or_0_operand (operands[1], SImode))"
4333 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4336 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4337 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4338 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4339 && (register_operand (operands[0], SImode)
4340 || reg_or_0_operand (operands[1], SImode))"
4351 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4354 [(set (match_operand:HI 0 "register_operand" "=r,r")
4355 (match_operand:HI 1 "input_operand" "rJ,n"))]
4357 && (register_operand (operands[0], HImode)
4358 || register_operand (operands[1], HImode))"
4362 [(set_attr "type" "ilog,iadd")])
4365 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4366 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4368 && (register_operand (operands[0], HImode)
4369 || reg_or_0_operand (operands[1], HImode))"
4375 [(set_attr "type" "ilog,iadd,ild,ist")])
4378 [(set (match_operand:QI 0 "register_operand" "=r,r")
4379 (match_operand:QI 1 "input_operand" "rJ,n"))]
4381 && (register_operand (operands[0], QImode)
4382 || register_operand (operands[1], QImode))"
4386 [(set_attr "type" "ilog,iadd")])
4389 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4390 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4392 && (register_operand (operands[0], QImode)
4393 || reg_or_0_operand (operands[1], QImode))"
4399 [(set_attr "type" "ilog,iadd,ild,ist")])
4401 ;; We do two major things here: handle mem->mem and construct long
4404 (define_expand "movsi"
4405 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4406 (match_operand:SI 1 "general_operand" ""))]
4410 if (GET_CODE (operands[0]) == MEM
4411 && ! reg_or_0_operand (operands[1], SImode))
4412 operands[1] = force_reg (SImode, operands[1]);
4414 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4416 else if (GET_CODE (operands[1]) == CONST_INT)
4419 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4420 if (rtx_equal_p (operands[0], operands[1]))
4425 ;; Split a load of a large constant into the appropriate two-insn
4429 [(set (match_operand:SI 0 "register_operand" "")
4430 (match_operand:SI 1 "const_int_operand" ""))]
4431 "! add_operand (operands[1], SImode)"
4432 [(set (match_dup 0) (match_dup 2))
4433 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4436 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4438 if (tem == operands[0])
4445 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4446 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4448 && (register_operand (operands[0], DImode)
4449 || reg_or_0_operand (operands[1], DImode))"
4460 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4463 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4464 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4466 && (register_operand (operands[0], DImode)
4467 || reg_or_0_operand (operands[1], DImode))"
4480 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4482 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4483 ;; memory, and construct long 32-bit constants.
4485 (define_expand "movdi"
4486 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4487 (match_operand:DI 1 "general_operand" ""))]
4493 if (GET_CODE (operands[0]) == MEM
4494 && ! reg_or_0_operand (operands[1], DImode))
4495 operands[1] = force_reg (DImode, operands[1]);
4497 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4499 else if (GET_CODE (operands[1]) == CONST_INT
4500 && (tem = alpha_emit_set_const (operands[0], DImode,
4501 INTVAL (operands[1]), 3)) != 0)
4503 if (rtx_equal_p (tem, operands[0]))
4508 else if (CONSTANT_P (operands[1]))
4510 if (TARGET_BUILD_CONSTANTS)
4512 HOST_WIDE_INT i0, i1;
4514 if (GET_CODE (operands[1]) == CONST_INT)
4516 i0 = INTVAL (operands[1]);
4519 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4521 #if HOST_BITS_PER_WIDE_INT >= 64
4522 i0 = CONST_DOUBLE_LOW (operands[1]);
4525 i0 = CONST_DOUBLE_LOW (operands[1]);
4526 i1 = CONST_DOUBLE_HIGH (operands[1]);
4532 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4533 if (rtx_equal_p (tem, operands[0]))
4540 operands[1] = force_const_mem (DImode, operands[1]);
4541 if (reload_in_progress)
4543 emit_move_insn (operands[0], XEXP (operands[1], 0));
4544 operands[1] = copy_rtx (operands[1]);
4545 XEXP (operands[1], 0) = operands[0];
4548 operands[1] = validize_mem (operands[1]);
4555 ;; Split a load of a large constant into the appropriate two-insn
4559 [(set (match_operand:DI 0 "register_operand" "")
4560 (match_operand:DI 1 "const_int_operand" ""))]
4561 "! add_operand (operands[1], DImode)"
4562 [(set (match_dup 0) (match_dup 2))
4563 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4566 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4568 if (tem == operands[0])
4574 ;; These are the partial-word cases.
4576 ;; First we have the code to load an aligned word. Operand 0 is the register
4577 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4578 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4579 ;; number of bits within the word that the value is. Operand 3 is an SImode
4580 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4581 ;; same register. It is allowed to conflict with operand 1 as well.
4583 (define_expand "aligned_loadqi"
4584 [(set (match_operand:SI 3 "register_operand" "")
4585 (match_operand:SI 1 "memory_operand" ""))
4586 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4587 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4589 (match_operand:DI 2 "const_int_operand" "")))]
4594 (define_expand "aligned_loadhi"
4595 [(set (match_operand:SI 3 "register_operand" "")
4596 (match_operand:SI 1 "memory_operand" ""))
4597 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4598 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4600 (match_operand:DI 2 "const_int_operand" "")))]
4605 ;; Similar for unaligned loads, where we use the sequence from the
4606 ;; Alpha Architecture manual.
4608 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4609 ;; operand 3 can overlap the input and output registers.
4611 (define_expand "unaligned_loadqi"
4612 [(set (match_operand:DI 2 "register_operand" "")
4613 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4615 (set (match_operand:DI 3 "register_operand" "")
4617 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4618 (zero_extract:DI (match_dup 2)
4620 (ashift:DI (match_dup 3) (const_int 3))))]
4624 (define_expand "unaligned_loadhi"
4625 [(set (match_operand:DI 2 "register_operand" "")
4626 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4628 (set (match_operand:DI 3 "register_operand" "")
4630 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4631 (zero_extract:DI (match_dup 2)
4633 (ashift:DI (match_dup 3) (const_int 3))))]
4637 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4638 ;; aligned SImode MEM. Operand 1 is the register containing the
4639 ;; byte or word to store. Operand 2 is the number of bits within the word that
4640 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4642 (define_expand "aligned_store"
4643 [(set (match_operand:SI 3 "register_operand" "")
4644 (match_operand:SI 0 "memory_operand" ""))
4645 (set (subreg:DI (match_dup 3) 0)
4646 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4647 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4648 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4649 (match_operand:DI 2 "const_int_operand" "")))
4650 (set (subreg:DI (match_dup 4) 0)
4651 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4652 (set (match_dup 0) (match_dup 4))]
4655 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4656 << INTVAL (operands[2])));
4659 ;; For the unaligned byte and halfword cases, we use code similar to that
4660 ;; in the ;; Architecture book, but reordered to lower the number of registers
4661 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4662 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4663 ;; be the same temporary, if desired. If the address is in a register,
4664 ;; operand 2 can be that register.
4666 (define_expand "unaligned_storeqi"
4667 [(set (match_operand:DI 3 "register_operand" "")
4668 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4670 (set (match_operand:DI 2 "register_operand" "")
4673 (and:DI (not:DI (ashift:DI (const_int 255)
4674 (ashift:DI (match_dup 2) (const_int 3))))
4676 (set (match_operand:DI 4 "register_operand" "")
4677 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4678 (ashift:DI (match_dup 2) (const_int 3))))
4679 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4680 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4685 (define_expand "unaligned_storehi"
4686 [(set (match_operand:DI 3 "register_operand" "")
4687 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4689 (set (match_operand:DI 2 "register_operand" "")
4692 (and:DI (not:DI (ashift:DI (const_int 65535)
4693 (ashift:DI (match_dup 2) (const_int 3))))
4695 (set (match_operand:DI 4 "register_operand" "")
4696 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4697 (ashift:DI (match_dup 2) (const_int 3))))
4698 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4699 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4704 ;; Here are the define_expand's for QI and HI moves that use the above
4705 ;; patterns. We have the normal sets, plus the ones that need scratch
4706 ;; registers for reload.
4708 (define_expand "movqi"
4709 [(set (match_operand:QI 0 "nonimmediate_operand" "")
4710 (match_operand:QI 1 "general_operand" ""))]
4716 if (GET_CODE (operands[0]) == MEM
4717 && ! reg_or_0_operand (operands[1], QImode))
4718 operands[1] = force_reg (QImode, operands[1]);
4720 if (GET_CODE (operands[1]) == CONST_INT
4721 && ! input_operand (operands[1], QImode))
4723 operands[1] = alpha_emit_set_const (operands[0], QImode,
4724 INTVAL (operands[1]), 3);
4726 if (rtx_equal_p (operands[0], operands[1]))
4733 /* If the output is not a register, the input must be. */
4734 if (GET_CODE (operands[0]) == MEM)
4735 operands[1] = force_reg (QImode, operands[1]);
4737 /* Handle four memory cases, unaligned and aligned for either the input
4738 or the output. The only case where we can be called during reload is
4739 for aligned loads; all other cases require temporaries. */
4741 if (GET_CODE (operands[1]) == MEM
4742 || (GET_CODE (operands[1]) == SUBREG
4743 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4744 || (reload_in_progress && GET_CODE (operands[1]) == REG
4745 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4746 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4747 && GET_CODE (SUBREG_REG (operands[1])) == REG
4748 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4750 if (aligned_memory_operand (operands[1], QImode))
4752 if (reload_in_progress)
4754 emit_insn (gen_reload_inqi_help
4755 (operands[0], operands[1],
4756 gen_rtx_REG (SImode, REGNO (operands[0]))));
4760 rtx aligned_mem, bitnum;
4761 rtx scratch = gen_reg_rtx (SImode);
4763 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4765 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4771 /* Don't pass these as parameters since that makes the generated
4772 code depend on parameter evaluation order which will cause
4773 bootstrap failures. */
4775 rtx temp1 = gen_reg_rtx (DImode);
4776 rtx temp2 = gen_reg_rtx (DImode);
4778 = gen_unaligned_loadqi (operands[0],
4779 get_unaligned_address (operands[1], 0),
4782 alpha_set_memflags (seq, operands[1]);
4789 else if (GET_CODE (operands[0]) == MEM
4790 || (GET_CODE (operands[0]) == SUBREG
4791 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4792 || (reload_in_progress && GET_CODE (operands[0]) == REG
4793 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4794 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4795 && GET_CODE (SUBREG_REG (operands[0])) == REG
4796 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4798 if (aligned_memory_operand (operands[0], QImode))
4800 rtx aligned_mem, bitnum;
4801 rtx temp1 = gen_reg_rtx (SImode);
4802 rtx temp2 = gen_reg_rtx (SImode);
4804 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4806 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4811 rtx temp1 = gen_reg_rtx (DImode);
4812 rtx temp2 = gen_reg_rtx (DImode);
4813 rtx temp3 = gen_reg_rtx (DImode);
4815 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4816 operands[1], temp1, temp2, temp3);
4818 alpha_set_memflags (seq, operands[0]);
4826 (define_expand "movhi"
4827 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4828 (match_operand:HI 1 "general_operand" ""))]
4834 if (GET_CODE (operands[0]) == MEM
4835 && ! reg_or_0_operand (operands[1], HImode))
4836 operands[1] = force_reg (HImode, operands[1]);
4838 if (GET_CODE (operands[1]) == CONST_INT
4839 && ! input_operand (operands[1], HImode))
4841 operands[1] = alpha_emit_set_const (operands[0], HImode,
4842 INTVAL (operands[1]), 3);
4844 if (rtx_equal_p (operands[0], operands[1]))
4851 /* If the output is not a register, the input must be. */
4852 if (GET_CODE (operands[0]) == MEM)
4853 operands[1] = force_reg (HImode, operands[1]);
4855 /* Handle four memory cases, unaligned and aligned for either the input
4856 or the output. The only case where we can be called during reload is
4857 for aligned loads; all other cases require temporaries. */
4859 if (GET_CODE (operands[1]) == MEM
4860 || (GET_CODE (operands[1]) == SUBREG
4861 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4862 || (reload_in_progress && GET_CODE (operands[1]) == REG
4863 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4864 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4865 && GET_CODE (SUBREG_REG (operands[1])) == REG
4866 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4868 if (aligned_memory_operand (operands[1], HImode))
4870 if (reload_in_progress)
4872 emit_insn (gen_reload_inhi_help
4873 (operands[0], operands[1],
4874 gen_rtx_REG (SImode, REGNO (operands[0]))));
4878 rtx aligned_mem, bitnum;
4879 rtx scratch = gen_reg_rtx (SImode);
4881 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4883 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4889 /* Don't pass these as parameters since that makes the generated
4890 code depend on parameter evaluation order which will cause
4891 bootstrap failures. */
4893 rtx temp1 = gen_reg_rtx (DImode);
4894 rtx temp2 = gen_reg_rtx (DImode);
4896 = gen_unaligned_loadhi (operands[0],
4897 get_unaligned_address (operands[1], 0),
4900 alpha_set_memflags (seq, operands[1]);
4907 else if (GET_CODE (operands[0]) == MEM
4908 || (GET_CODE (operands[0]) == SUBREG
4909 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4910 || (reload_in_progress && GET_CODE (operands[0]) == REG
4911 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4912 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4913 && GET_CODE (SUBREG_REG (operands[0])) == REG
4914 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4916 if (aligned_memory_operand (operands[0], HImode))
4918 rtx aligned_mem, bitnum;
4919 rtx temp1 = gen_reg_rtx (SImode);
4920 rtx temp2 = gen_reg_rtx (SImode);
4922 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4924 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4929 rtx temp1 = gen_reg_rtx (DImode);
4930 rtx temp2 = gen_reg_rtx (DImode);
4931 rtx temp3 = gen_reg_rtx (DImode);
4933 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
4934 operands[1], temp1, temp2, temp3);
4936 alpha_set_memflags (seq, operands[0]);
4945 ;; Here are the versions for reload. Note that in the unaligned cases
4946 ;; we know that the operand must not be a pseudo-register because stack
4947 ;; slots are always aligned references.
4949 (define_expand "reload_inqi"
4950 [(parallel [(match_operand:QI 0 "register_operand" "=r")
4951 (match_operand:QI 1 "any_memory_operand" "m")
4952 (match_operand:TI 2 "register_operand" "=&r")])]
4958 if (GET_CODE (operands[1]) != MEM)
4961 if (aligned_memory_operand (operands[1], QImode))
4963 seq = gen_reload_inqi_help (operands[0], operands[1],
4964 gen_rtx_REG (SImode, REGNO (operands[2])));
4970 /* It is possible that one of the registers we got for operands[2]
4971 might coincide with that of operands[0] (which is why we made
4972 it TImode). Pick the other one to use as our scratch. */
4973 if (REGNO (operands[0]) == REGNO (operands[2]))
4974 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4976 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
4978 addr = get_unaligned_address (operands[1], 0);
4979 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
4980 gen_rtx_REG (DImode, REGNO (operands[0])));
4981 alpha_set_memflags (seq, operands[1]);
4987 (define_expand "reload_inhi"
4988 [(parallel [(match_operand:HI 0 "register_operand" "=r")
4989 (match_operand:HI 1 "any_memory_operand" "m")
4990 (match_operand:TI 2 "register_operand" "=&r")])]
4996 if (GET_CODE (operands[1]) != MEM)
4999 if (aligned_memory_operand (operands[1], HImode))
5001 seq = gen_reload_inhi_help (operands[0], operands[1],
5002 gen_rtx_REG (SImode, REGNO (operands[2])));
5008 /* It is possible that one of the registers we got for operands[2]
5009 might coincide with that of operands[0] (which is why we made
5010 it TImode). Pick the other one to use as our scratch. */
5011 if (REGNO (operands[0]) == REGNO (operands[2]))
5012 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5014 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5016 addr = get_unaligned_address (operands[1], 0);
5017 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5018 gen_rtx_REG (DImode, REGNO (operands[0])));
5019 alpha_set_memflags (seq, operands[1]);
5025 (define_expand "reload_outqi"
5026 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5027 (match_operand:QI 1 "register_operand" "r")
5028 (match_operand:TI 2 "register_operand" "=&r")])]
5032 if (GET_CODE (operands[0]) != MEM)
5035 if (aligned_memory_operand (operands[0], QImode))
5037 emit_insn (gen_reload_outqi_help
5038 (operands[0], operands[1],
5039 gen_rtx_REG (SImode, REGNO (operands[2])),
5040 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5044 rtx addr = get_unaligned_address (operands[0], 0);
5045 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5046 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5047 rtx scratch3 = scratch1;
5050 if (GET_CODE (addr) == REG)
5053 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5054 scratch2, scratch3);
5055 alpha_set_memflags (seq, operands[0]);
5061 (define_expand "reload_outhi"
5062 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5063 (match_operand:HI 1 "register_operand" "r")
5064 (match_operand:TI 2 "register_operand" "=&r")])]
5068 if (GET_CODE (operands[0]) != MEM)
5071 if (aligned_memory_operand (operands[0], HImode))
5073 emit_insn (gen_reload_outhi_help
5074 (operands[0], operands[1],
5075 gen_rtx_REG (SImode, REGNO (operands[2])),
5076 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5080 rtx addr = get_unaligned_address (operands[0], 0);
5081 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5082 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5083 rtx scratch3 = scratch1;
5086 if (GET_CODE (addr) == REG)
5089 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5090 scratch2, scratch3);
5091 alpha_set_memflags (seq, operands[0]);
5097 ;; Helpers for the above. The way reload is structured, we can't
5098 ;; always get a proper address for a stack slot during reload_foo
5099 ;; expansion, so we must delay our address manipulations until after.
5101 (define_insn "reload_inqi_help"
5102 [(set (match_operand:QI 0 "register_operand" "=r")
5103 (match_operand:QI 1 "memory_operand" "m"))
5104 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5105 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5108 (define_insn "reload_inhi_help"
5109 [(set (match_operand:HI 0 "register_operand" "=r")
5110 (match_operand:HI 1 "memory_operand" "m"))
5111 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5112 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5115 (define_insn "reload_outqi_help"
5116 [(set (match_operand:QI 0 "memory_operand" "=m")
5117 (match_operand:QI 1 "register_operand" "r"))
5118 (clobber (match_operand:SI 2 "register_operand" "=r"))
5119 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5120 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5123 (define_insn "reload_outhi_help"
5124 [(set (match_operand:HI 0 "memory_operand" "=m")
5125 (match_operand:HI 1 "register_operand" "r"))
5126 (clobber (match_operand:SI 2 "register_operand" "=r"))
5127 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5128 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5132 [(set (match_operand:QI 0 "register_operand" "")
5133 (match_operand:QI 1 "memory_operand" ""))
5134 (clobber (match_operand:SI 2 "register_operand" ""))]
5135 "! TARGET_BWX && reload_completed"
5139 rtx aligned_mem, bitnum;
5140 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5141 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5147 [(set (match_operand:HI 0 "register_operand" "")
5148 (match_operand:HI 1 "memory_operand" ""))
5149 (clobber (match_operand:SI 2 "register_operand" ""))]
5150 "! TARGET_BWX && reload_completed"
5154 rtx aligned_mem, bitnum;
5155 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5156 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5162 [(set (match_operand:QI 0 "memory_operand" "")
5163 (match_operand:QI 1 "register_operand" ""))
5164 (clobber (match_operand:SI 2 "register_operand" ""))
5165 (clobber (match_operand:SI 3 "register_operand" ""))]
5166 "! TARGET_BWX && reload_completed"
5170 rtx aligned_mem, bitnum;
5171 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5172 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5173 operands[2], operands[3]));
5178 [(set (match_operand:HI 0 "memory_operand" "")
5179 (match_operand:HI 1 "register_operand" ""))
5180 (clobber (match_operand:SI 2 "register_operand" ""))
5181 (clobber (match_operand:SI 3 "register_operand" ""))]
5182 "! TARGET_BWX && reload_completed"
5186 rtx aligned_mem, bitnum;
5187 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5188 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5189 operands[2], operands[3]));
5193 ;; Bit field extract patterns which use ext[wlq][lh]
5195 (define_expand "extv"
5196 [(set (match_operand:DI 0 "register_operand" "")
5197 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5198 (match_operand:DI 2 "immediate_operand" "")
5199 (match_operand:DI 3 "immediate_operand" "")))]
5203 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5204 if (INTVAL (operands[3]) % 8 != 0
5205 || (INTVAL (operands[2]) != 16
5206 && INTVAL (operands[2]) != 32
5207 && INTVAL (operands[2]) != 64))
5210 /* From mips.md: extract_bit_field doesn't verify that our source
5211 matches the predicate, so we force it to be a MEM here. */
5212 if (GET_CODE (operands[1]) != MEM)
5215 alpha_expand_unaligned_load (operands[0], operands[1],
5216 INTVAL (operands[2]) / 8,
5217 INTVAL (operands[3]) / 8, 1);
5221 (define_expand "extzv"
5222 [(set (match_operand:DI 0 "register_operand" "")
5223 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5224 (match_operand:DI 2 "immediate_operand" "")
5225 (match_operand:DI 3 "immediate_operand" "")))]
5229 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5230 if (INTVAL (operands[3]) % 8 != 0
5231 || (INTVAL (operands[2]) != 8
5232 && INTVAL (operands[2]) != 16
5233 && INTVAL (operands[2]) != 32
5234 && INTVAL (operands[2]) != 64))
5237 if (GET_CODE (operands[1]) == MEM)
5239 /* Fail 8 bit fields, falling back on a simple byte load. */
5240 if (INTVAL (operands[2]) == 8)
5243 alpha_expand_unaligned_load (operands[0], operands[1],
5244 INTVAL (operands[2]) / 8,
5245 INTVAL (operands[3]) / 8, 0);
5250 (define_expand "insv"
5251 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5252 (match_operand:DI 1 "immediate_operand" "")
5253 (match_operand:DI 2 "immediate_operand" ""))
5254 (match_operand:DI 3 "register_operand" ""))]
5258 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5259 if (INTVAL (operands[2]) % 8 != 0
5260 || (INTVAL (operands[1]) != 16
5261 && INTVAL (operands[1]) != 32
5262 && INTVAL (operands[1]) != 64))
5265 /* From mips.md: store_bit_field doesn't verify that our source
5266 matches the predicate, so we force it to be a MEM here. */
5267 if (GET_CODE (operands[0]) != MEM)
5270 alpha_expand_unaligned_store (operands[0], operands[3],
5271 INTVAL (operands[1]) / 8,
5272 INTVAL (operands[2]) / 8);
5278 ;; Block move/clear, see alpha.c for more details.
5279 ;; Argument 0 is the destination
5280 ;; Argument 1 is the source
5281 ;; Argument 2 is the length
5282 ;; Argument 3 is the alignment
5284 (define_expand "movstrqi"
5285 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5286 (match_operand:BLK 1 "memory_operand" ""))
5287 (use (match_operand:DI 2 "immediate_operand" ""))
5288 (use (match_operand:DI 3 "immediate_operand" ""))])]
5292 if (alpha_expand_block_move (operands))
5298 (define_expand "clrstrqi"
5299 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5301 (use (match_operand:DI 1 "immediate_operand" ""))
5302 (use (match_operand:DI 2 "immediate_operand" ""))])]
5306 if (alpha_expand_block_clear (operands))
5312 ;; Subroutine of stack space allocation. Perform a stack probe.
5313 (define_expand "probe_stack"
5314 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5318 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5319 INTVAL (operands[0])));
5320 MEM_VOLATILE_P (operands[1]) = 1;
5322 operands[0] = const0_rtx;
5325 ;; This is how we allocate stack space. If we are allocating a
5326 ;; constant amount of space and we know it is less than 4096
5327 ;; bytes, we need do nothing.
5329 ;; If it is more than 4096 bytes, we need to probe the stack
5331 (define_expand "allocate_stack"
5333 (plus:DI (reg:DI 30)
5334 (match_operand:DI 1 "reg_or_cint_operand" "")))
5335 (set (match_operand:DI 0 "register_operand" "=r")
5340 if (GET_CODE (operands[1]) == CONST_INT
5341 && INTVAL (operands[1]) < 32768)
5343 if (INTVAL (operands[1]) >= 4096)
5345 /* We do this the same way as in the prologue and generate explicit
5346 probes. Then we update the stack by the constant. */
5350 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5351 while (probed + 8192 < INTVAL (operands[1]))
5352 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5354 if (probed + 4096 < INTVAL (operands[1]))
5355 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5358 operands[1] = GEN_INT (- INTVAL (operands[1]));
5359 operands[2] = virtual_stack_dynamic_rtx;
5364 rtx loop_label = gen_label_rtx ();
5365 rtx want = gen_reg_rtx (Pmode);
5366 rtx tmp = gen_reg_rtx (Pmode);
5369 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5370 force_reg (Pmode, operands[1])));
5371 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5373 if (GET_CODE (operands[1]) != CONST_INT)
5375 out_label = gen_label_rtx ();
5376 emit_insn (gen_cmpdi (want, tmp));
5377 emit_jump_insn (gen_bgeu (out_label));
5380 emit_label (loop_label);
5381 memref = gen_rtx_MEM (DImode, tmp);
5382 MEM_VOLATILE_P (memref) = 1;
5383 emit_move_insn (memref, const0_rtx);
5384 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5385 emit_insn (gen_cmpdi (tmp, want));
5386 emit_jump_insn (gen_bgtu (loop_label));
5388 memref = gen_rtx_MEM (DImode, want);
5389 MEM_VOLATILE_P (memref) = 1;
5390 emit_move_insn (memref, const0_rtx);
5393 emit_label (out_label);
5395 emit_move_insn (stack_pointer_rtx, want);
5396 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5401 ;; This is used by alpha_expand_prolog to do the same thing as above,
5402 ;; except we cannot at that time generate new basic blocks, so we hide
5403 ;; the loop in this one insn.
5405 (define_insn "prologue_stack_probe_loop"
5406 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5407 (match_operand:DI 1 "register_operand" "r")] 5)]
5411 operands[2] = gen_label_rtx ();
5412 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5413 CODE_LABEL_NUMBER (operands[2]));
5415 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5417 [(set_attr "length" "16")
5418 (set_attr "type" "multi")])
5420 (define_expand "prologue"
5421 [(clobber (const_int 0))]
5423 "alpha_expand_prologue (); DONE;")
5425 (define_insn "init_fp"
5426 [(set (match_operand:DI 0 "register_operand" "=r")
5427 (match_operand:DI 1 "register_operand" "r"))
5428 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5432 (define_expand "epilogue"
5435 "alpha_expand_epilogue ();")
5437 (define_expand "eh_epilogue"
5438 [(use (match_operand:DI 0 "register_operand" "r"))
5439 (use (match_operand:DI 1 "register_operand" "r"))
5440 (use (match_operand:DI 2 "register_operand" "r"))]
5444 cfun->machine->eh_epilogue_sp_ofs = operands[1];
5445 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5447 rtx ra = gen_rtx_REG (Pmode, 26);
5448 emit_move_insn (ra, operands[2]);
5453 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5454 ;; the frame size into a register. We use this pattern to ensure
5455 ;; we get lda instead of addq.
5456 (define_insn "nt_lda"
5457 [(set (match_operand:DI 0 "register_operand" "=r")
5458 (unspec:DI [(match_dup 0)
5459 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5463 (define_expand "builtin_longjmp"
5464 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5465 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5468 /* The elements of the buffer are, in order: */
5469 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5470 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5471 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5472 rtx pv = gen_rtx_REG (Pmode, 27);
5474 /* This bit is the same as expand_builtin_longjmp. */
5475 emit_move_insn (hard_frame_pointer_rtx, fp);
5476 emit_move_insn (pv, lab);
5477 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5478 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5479 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5481 /* Load the label we are jumping through into $27 so that we know
5482 where to look for it when we get back to setjmp's function for
5483 restoring the gp. */
5484 emit_indirect_jump (pv);
5488 (define_insn "builtin_setjmp_receiver"
5489 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5490 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5491 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5492 [(set_attr "length" "8")
5493 (set_attr "type" "multi")])
5496 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5497 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5498 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5499 [(set_attr "length" "12")
5500 (set_attr "type" "multi")])
5502 (define_insn "exception_receiver"
5503 [(unspec_volatile [(const_int 0)] 7)]
5504 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5505 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5506 [(set_attr "length" "12")
5507 (set_attr "type" "multi")])
5509 (define_expand "nonlocal_goto_receiver"
5510 [(unspec_volatile [(const_int 0)] 1)
5511 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5512 (unspec_volatile [(const_int 0)] 1)
5517 (define_insn "arg_home"
5518 [(unspec [(const_int 0)] 0)
5533 (clobber (mem:BLK (const_int 0)))
5534 (clobber (reg:DI 24))
5535 (clobber (reg:DI 25))
5536 (clobber (reg:DI 0))]
5538 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5539 [(set_attr "length" "16")
5540 (set_attr "type" "multi")])
5542 ;; Close the trap shadow of preceeding instructions. This is generated
5545 (define_insn "trapb"
5546 [(unspec_volatile [(const_int 0)] 4)]
5549 [(set_attr "type" "misc")])
5551 ;; No-op instructions used by machine-dependant reorg to preserve
5552 ;; alignment for instruction issue.
5558 [(set_attr "type" "ilog")])
5564 [(set_attr "type" "fcpys")])
5571 (define_insn "realign"
5572 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5574 ".align %0 #realign")
5576 ;; The call patterns are at the end of the file because their
5577 ;; wildcard operand0 interferes with nice recognition.
5580 [(set (match_operand 0 "" "")
5581 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5582 (match_operand 2 "" "")))
5583 (clobber (reg:DI 27))
5584 (clobber (reg:DI 26))]
5585 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5587 jsr $26,($27),0\;ldgp $29,0($26)
5589 jsr $26,%1\;ldgp $29,0($26)"
5590 [(set_attr "type" "jsr")
5591 (set_attr "length" "12,*,16")])
5594 [(set (match_operand 0 "" "")
5595 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5596 (match_operand 2 "" "")))
5597 (clobber (reg:DI 26))]
5603 [(set_attr "type" "jsr")
5604 (set_attr "length" "*,*,12")])
5607 [(set (match_operand 0 "" "")
5608 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
5609 (match_operand 2 "" "")))
5610 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
5613 (clobber (reg:DI 27))]
5616 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
5617 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
5618 [(set_attr "type" "jsr")
5619 (set_attr "length" "12,16")])
5622 ;; Peepholes go at the end.
5624 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5625 ;; reload when converting fp->int.
5628 [(set (match_operand:SI 0 "register_operand" "=r")
5629 (match_operand:SI 1 "memory_operand" "m"))
5630 (set (match_operand:DI 2 "register_operand" "=r")
5631 (sign_extend:DI (match_dup 0)))]
5632 "dead_or_set_p (next_nonnote_insn (insn), operands[0])"
5634 (sign_extend:DI (match_dup 1)))]
5638 [(set (match_operand:SI 0 "register_operand" "=r")
5639 (match_operand:SI 1 "hard_fp_register_operand" "f"))
5640 (set (match_operand:DI 2 "register_operand" "=r")
5641 (sign_extend:DI (match_dup 0)))]
5642 "TARGET_FIX && dead_or_set_p (next_nonnote_insn (insn), operands[0])"
5644 (sign_extend:DI (match_dup 1)))]