1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
69 (UNSPECV_LONGJMP 3) ; builtin_longjmp
71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
73 (UNSPECV_EHR 7) ; exception_receiver
77 (UNSPECV_PLDGP2 11) ; prologue ldgp
82 ;; Where necessary, the suffixes _le and _be are used to distinguish between
83 ;; little-endian and big-endian patterns.
85 ;; Note that the Unicos/Mk assembler does not support the following
86 ;; opcodes: mov, fmov, nop, fnop, unop.
88 ;; Processor type -- this attribute must exactly match the processor_type
89 ;; enumeration in alpha.h.
91 (define_attr "cpu" "ev4,ev5,ev6"
92 (const (symbol_ref "alpha_cpu")))
94 ;; Define an insn type attribute. This is used in function unit delay
95 ;; computations, among other purposes. For the most part, we use the names
96 ;; defined in the EV4 documentation, but add a few that we have to know about
100 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
101 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
102 (const_string "iadd"))
104 ;; Describe a user's asm statement.
105 (define_asm_attributes
106 [(set_attr "type" "multi")])
108 ;; Define the operand size an insn operates on. Used primarily by mul
109 ;; and div operations that have size dependent timings.
111 (define_attr "opsize" "si,di,udi"
114 ;; The TRAP attribute marks instructions that may generate traps
115 ;; (which are imprecise and may need a trapb if software completion
118 (define_attr "trap" "no,yes"
121 ;; The ROUND_SUFFIX attribute marks which instructions require a
122 ;; rounding-mode suffix. The value NONE indicates no suffix,
123 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
125 (define_attr "round_suffix" "none,normal,c"
126 (const_string "none"))
128 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
130 ;; SU accepts only /su (cmpt et al)
131 ;; SUI accepts only /sui (cvtqt and cvtqs)
132 ;; V_SV accepts /v and /sv (cvtql only)
133 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
134 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
136 ;; The actual suffix emitted is controled by alpha_fptm.
138 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
139 (const_string "none"))
141 ;; The length of an instruction sequence in bytes.
143 (define_attr "length" ""
146 ;; Include scheduling descriptions.
152 ;; First define the arithmetic insns. Note that the 32-bit forms also
155 ;; Handle 32-64 bit extension from memory to a floating point register
156 ;; specially, since this occurs frequently in int->double conversions.
158 ;; Note that while we must retain the =f case in the insn for reload's
159 ;; benefit, it should be eliminated after reload, so we should never emit
160 ;; code for that case. But we don't reject the possibility.
162 (define_expand "extendsidi2"
163 [(set (match_operand:DI 0 "register_operand" "")
164 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
168 (define_insn "*extendsidi2_nofix"
169 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
171 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
177 lds %0,%1\;cvtlq %0,%0"
178 [(set_attr "type" "iadd,ild,fadd,fld")
179 (set_attr "length" "*,*,*,8")])
181 (define_insn "*extendsidi2_fix"
182 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
184 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
191 lds %0,%1\;cvtlq %0,%0"
192 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
193 (set_attr "length" "*,*,*,*,8")])
195 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
197 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
198 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
200 [(set (match_dup 2) (match_dup 1))
201 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
202 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
204 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
205 ;; reload when converting fp->int.
208 [(set (match_operand:SI 0 "hard_int_register_operand" "")
209 (match_operand:SI 1 "memory_operand" ""))
210 (set (match_operand:DI 2 "hard_int_register_operand" "")
211 (sign_extend:DI (match_dup 0)))]
212 "true_regnum (operands[0]) == true_regnum (operands[2])
213 || peep2_reg_dead_p (2, operands[0])"
215 (sign_extend:DI (match_dup 1)))]
219 [(set (match_operand:SI 0 "hard_int_register_operand" "")
220 (match_operand:SI 1 "hard_fp_register_operand" ""))
221 (set (match_operand:DI 2 "hard_int_register_operand" "")
222 (sign_extend:DI (match_dup 0)))]
224 && (true_regnum (operands[0]) == true_regnum (operands[2])
225 || peep2_reg_dead_p (2, operands[0]))"
227 (sign_extend:DI (match_dup 1)))]
231 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
232 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
233 (set (match_operand:DI 2 "hard_int_register_operand" "")
235 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
237 (sign_extend:DI (match_dup 1)))]
240 ;; Don't say we have addsi3 if optimizing. This generates better code. We
241 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
242 (define_expand "addsi3"
243 [(set (match_operand:SI 0 "register_operand" "")
244 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
245 (match_operand:SI 2 "add_operand" "")))]
249 (define_insn "*addsi_internal"
250 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
251 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
252 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
261 [(set (match_operand:SI 0 "register_operand" "")
262 (plus:SI (match_operand:SI 1 "register_operand" "")
263 (match_operand:SI 2 "const_int_operand" "")))]
264 "! add_operand (operands[2], SImode)"
265 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
266 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
268 HOST_WIDE_INT val = INTVAL (operands[2]);
269 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
270 HOST_WIDE_INT rest = val - low;
272 operands[3] = GEN_INT (rest);
273 operands[4] = GEN_INT (low);
276 (define_insn "*addsi_se"
277 [(set (match_operand:DI 0 "register_operand" "=r,r")
279 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
280 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
286 (define_insn "*addsi_se2"
287 [(set (match_operand:DI 0 "register_operand" "=r,r")
289 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
290 (match_operand:DI 2 "sext_add_operand" "rI,O"))
298 [(set (match_operand:DI 0 "register_operand" "")
300 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
301 (match_operand:SI 2 "const_int_operand" ""))))
302 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
303 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
304 && INTVAL (operands[2]) % 4 == 0"
305 [(set (match_dup 3) (match_dup 4))
306 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
310 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
316 operands[4] = GEN_INT (val);
317 operands[5] = GEN_INT (mult);
321 [(set (match_operand:DI 0 "register_operand" "")
323 (plus:SI (match_operator:SI 1 "comparison_operator"
324 [(match_operand 2 "" "")
325 (match_operand 3 "" "")])
326 (match_operand:SI 4 "add_operand" ""))))
327 (clobber (match_operand:DI 5 "register_operand" ""))]
329 [(set (match_dup 5) (match_dup 6))
330 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
332 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
333 operands[2], operands[3]);
334 operands[7] = gen_lowpart (SImode, operands[5]);
337 (define_insn "addvsi3"
338 [(set (match_operand:SI 0 "register_operand" "=r,r")
339 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
340 (match_operand:SI 2 "sext_add_operand" "rI,O")))
341 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
342 (sign_extend:DI (match_dup 2)))
343 (sign_extend:DI (plus:SI (match_dup 1)
351 (define_expand "adddi3"
352 [(set (match_operand:DI 0 "register_operand" "")
353 (plus:DI (match_operand:DI 1 "register_operand" "")
354 (match_operand:DI 2 "add_operand" "")))]
358 (define_insn "*adddi_er_lo16_dtp"
359 [(set (match_operand:DI 0 "register_operand" "=r")
360 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
361 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
363 "lda %0,%2(%1)\t\t!dtprel")
365 (define_insn "*adddi_er_hi32_dtp"
366 [(set (match_operand:DI 0 "register_operand" "=r")
367 (plus:DI (match_operand:DI 1 "register_operand" "r")
368 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
370 "ldah %0,%2(%1)\t\t!dtprelhi")
372 (define_insn "*adddi_er_lo32_dtp"
373 [(set (match_operand:DI 0 "register_operand" "=r")
374 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
375 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
377 "lda %0,%2(%1)\t\t!dtprello")
379 (define_insn "*adddi_er_lo16_tp"
380 [(set (match_operand:DI 0 "register_operand" "=r")
381 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
382 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
384 "lda %0,%2(%1)\t\t!tprel")
386 (define_insn "*adddi_er_hi32_tp"
387 [(set (match_operand:DI 0 "register_operand" "=r")
388 (plus:DI (match_operand:DI 1 "register_operand" "r")
389 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
391 "ldah %0,%2(%1)\t\t!tprelhi")
393 (define_insn "*adddi_er_lo32_tp"
394 [(set (match_operand:DI 0 "register_operand" "=r")
395 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
396 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
398 "lda %0,%2(%1)\t\t!tprello")
400 (define_insn "*adddi_er_high_l"
401 [(set (match_operand:DI 0 "register_operand" "=r")
402 (plus:DI (match_operand:DI 1 "register_operand" "r")
403 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
404 "TARGET_EXPLICIT_RELOCS"
405 "ldah %0,%2(%1)\t\t!gprelhigh")
408 [(set (match_operand:DI 0 "register_operand" "")
409 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
410 "TARGET_EXPLICIT_RELOCS && reload_completed"
412 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
413 "operands[2] = pic_offset_table_rtx;")
415 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
416 ;; With complications like
418 ;; The NT stack unwind code can't handle a subq to adjust the stack
419 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
420 ;; the exception handling code will loop if a subq is used and an
423 ;; The 19980616 change to emit prologues as RTL also confused some
424 ;; versions of GDB, which also interprets prologues. This has been
425 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
428 ;; and the fact that the three insns schedule exactly the same, it's
429 ;; just not worth the effort.
431 (define_insn "*adddi_internal"
432 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
433 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
434 (match_operand:DI 2 "add_operand" "r,K,L")))]
441 ;; ??? Allow large constants when basing off the frame pointer or some
442 ;; virtual register that may eliminate to the frame pointer. This is
443 ;; done because register elimination offsets will change the hi/lo split,
444 ;; and if we split before reload, we will require additional instructions.
446 (define_insn "*adddi_fp_hack"
447 [(set (match_operand:DI 0 "register_operand" "=r")
448 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
449 (match_operand:DI 2 "const_int_operand" "n")))]
450 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
451 && INTVAL (operands[2]) >= 0
452 /* This is the largest constant an lda+ldah pair can add, minus
453 an upper bound on the displacement between SP and AP during
454 register elimination. See INITIAL_ELIMINATION_OFFSET. */
455 && INTVAL (operands[2])
457 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
458 - ALPHA_ROUND(current_function_outgoing_args_size)
459 - (ALPHA_ROUND (get_frame_size ()
460 + max_reg_num () * UNITS_PER_WORD
461 + current_function_pretend_args_size)
462 - current_function_pretend_args_size))"
465 ;; Don't do this if we are adjusting SP since we don't want to do it
466 ;; in two steps. Don't split FP sources for the reason listed above.
468 [(set (match_operand:DI 0 "register_operand" "")
469 (plus:DI (match_operand:DI 1 "register_operand" "")
470 (match_operand:DI 2 "const_int_operand" "")))]
471 "! add_operand (operands[2], DImode)
472 && operands[0] != stack_pointer_rtx
473 && operands[1] != frame_pointer_rtx
474 && operands[1] != arg_pointer_rtx"
475 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
476 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
478 HOST_WIDE_INT val = INTVAL (operands[2]);
479 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
480 HOST_WIDE_INT rest = val - low;
482 operands[4] = GEN_INT (low);
483 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
484 operands[3] = GEN_INT (rest);
485 else if (! no_new_pseudos)
487 operands[3] = gen_reg_rtx (DImode);
488 emit_move_insn (operands[3], operands[2]);
489 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
496 (define_insn "*saddl"
497 [(set (match_operand:SI 0 "register_operand" "=r,r")
498 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
499 (match_operand:SI 2 "const48_operand" "I,I"))
500 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
506 (define_insn "*saddl_se"
507 [(set (match_operand:DI 0 "register_operand" "=r,r")
509 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
510 (match_operand:SI 2 "const48_operand" "I,I"))
511 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
518 [(set (match_operand:DI 0 "register_operand" "")
520 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
521 [(match_operand 2 "" "")
522 (match_operand 3 "" "")])
523 (match_operand:SI 4 "const48_operand" ""))
524 (match_operand:SI 5 "sext_add_operand" ""))))
525 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
527 [(set (match_dup 6) (match_dup 7))
529 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
532 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
533 operands[2], operands[3]);
534 operands[8] = gen_lowpart (SImode, operands[6]);
537 (define_insn "*saddq"
538 [(set (match_operand:DI 0 "register_operand" "=r,r")
539 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
540 (match_operand:DI 2 "const48_operand" "I,I"))
541 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
547 (define_insn "addvdi3"
548 [(set (match_operand:DI 0 "register_operand" "=r,r")
549 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
550 (match_operand:DI 2 "sext_add_operand" "rI,O")))
551 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
552 (sign_extend:TI (match_dup 2)))
553 (sign_extend:TI (plus:DI (match_dup 1)
561 (define_insn "negsi2"
562 [(set (match_operand:SI 0 "register_operand" "=r")
563 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
567 (define_insn "*negsi_se"
568 [(set (match_operand:DI 0 "register_operand" "=r")
569 (sign_extend:DI (neg:SI
570 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
574 (define_insn "negvsi2"
575 [(set (match_operand:SI 0 "register_operand" "=r")
576 (neg:SI (match_operand:SI 1 "register_operand" "r")))
577 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
578 (sign_extend:DI (neg:SI (match_dup 1))))
583 (define_insn "negdi2"
584 [(set (match_operand:DI 0 "register_operand" "=r")
585 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
589 (define_insn "negvdi2"
590 [(set (match_operand:DI 0 "register_operand" "=r")
591 (neg:DI (match_operand:DI 1 "register_operand" "r")))
592 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
593 (sign_extend:TI (neg:DI (match_dup 1))))
598 (define_expand "subsi3"
599 [(set (match_operand:SI 0 "register_operand" "")
600 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
601 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
605 (define_insn "*subsi_internal"
606 [(set (match_operand:SI 0 "register_operand" "=r")
607 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
608 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
612 (define_insn "*subsi_se"
613 [(set (match_operand:DI 0 "register_operand" "=r")
614 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
615 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
619 (define_insn "*subsi_se2"
620 [(set (match_operand:DI 0 "register_operand" "=r")
622 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
623 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
628 (define_insn "subvsi3"
629 [(set (match_operand:SI 0 "register_operand" "=r")
630 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
631 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
632 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
633 (sign_extend:DI (match_dup 2)))
634 (sign_extend:DI (minus:SI (match_dup 1)
640 (define_insn "subdi3"
641 [(set (match_operand:DI 0 "register_operand" "=r")
642 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
643 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
647 (define_insn "*ssubl"
648 [(set (match_operand:SI 0 "register_operand" "=r")
649 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
650 (match_operand:SI 2 "const48_operand" "I"))
651 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
655 (define_insn "*ssubl_se"
656 [(set (match_operand:DI 0 "register_operand" "=r")
658 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
659 (match_operand:SI 2 "const48_operand" "I"))
660 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
664 (define_insn "*ssubq"
665 [(set (match_operand:DI 0 "register_operand" "=r")
666 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
667 (match_operand:DI 2 "const48_operand" "I"))
668 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
672 (define_insn "subvdi3"
673 [(set (match_operand:DI 0 "register_operand" "=r")
674 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
675 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
676 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
677 (sign_extend:TI (match_dup 2)))
678 (sign_extend:TI (minus:DI (match_dup 1)
684 ;; The Unicos/Mk assembler doesn't support mull.
686 (define_insn "mulsi3"
687 [(set (match_operand:SI 0 "register_operand" "=r")
688 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
689 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
690 "!TARGET_ABI_UNICOSMK"
692 [(set_attr "type" "imul")
693 (set_attr "opsize" "si")])
695 (define_insn "*mulsi_se"
696 [(set (match_operand:DI 0 "register_operand" "=r")
698 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
699 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
700 "!TARGET_ABI_UNICOSMK"
702 [(set_attr "type" "imul")
703 (set_attr "opsize" "si")])
705 (define_insn "mulvsi3"
706 [(set (match_operand:SI 0 "register_operand" "=r")
707 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
708 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
709 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
710 (sign_extend:DI (match_dup 2)))
711 (sign_extend:DI (mult:SI (match_dup 1)
714 "!TARGET_ABI_UNICOSMK"
716 [(set_attr "type" "imul")
717 (set_attr "opsize" "si")])
719 (define_insn "muldi3"
720 [(set (match_operand:DI 0 "register_operand" "=r")
721 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
722 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
725 [(set_attr "type" "imul")])
727 (define_insn "mulvdi3"
728 [(set (match_operand:DI 0 "register_operand" "=r")
729 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
730 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
731 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
732 (sign_extend:TI (match_dup 2)))
733 (sign_extend:TI (mult:DI (match_dup 1)
738 [(set_attr "type" "imul")])
740 (define_insn "umuldi3_highpart"
741 [(set (match_operand:DI 0 "register_operand" "=r")
744 (mult:TI (zero_extend:TI
745 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
747 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
751 [(set_attr "type" "imul")
752 (set_attr "opsize" "udi")])
754 (define_insn "*umuldi3_highpart_const"
755 [(set (match_operand:DI 0 "register_operand" "=r")
758 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
759 (match_operand:TI 2 "cint8_operand" "I"))
763 [(set_attr "type" "imul")
764 (set_attr "opsize" "udi")])
766 ;; The divide and remainder operations take their inputs from r24 and
767 ;; r25, put their output in r27, and clobber r23 and r28 on all
768 ;; systems except Unicos/Mk. On Unicos, the standard library provides
769 ;; subroutines which use the standard calling convention and work on
772 ;; ??? Force sign-extension here because some versions of OSF/1 and
773 ;; Interix/NT don't do the right thing if the inputs are not properly
774 ;; sign-extended. But Linux, for instance, does not have this
775 ;; problem. Is it worth the complication here to eliminate the sign
778 (define_expand "divsi3"
780 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
782 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
783 (parallel [(set (match_dup 5)
784 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
785 (clobber (reg:DI 23))
786 (clobber (reg:DI 28))])
787 (set (match_operand:SI 0 "nonimmediate_operand" "")
788 (subreg:SI (match_dup 5) 0))]
789 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
791 operands[3] = gen_reg_rtx (DImode);
792 operands[4] = gen_reg_rtx (DImode);
793 operands[5] = gen_reg_rtx (DImode);
796 (define_expand "udivsi3"
798 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
800 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
801 (parallel [(set (match_dup 5)
802 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
803 (clobber (reg:DI 23))
804 (clobber (reg:DI 28))])
805 (set (match_operand:SI 0 "nonimmediate_operand" "")
806 (subreg:SI (match_dup 5) 0))]
807 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
809 operands[3] = gen_reg_rtx (DImode);
810 operands[4] = gen_reg_rtx (DImode);
811 operands[5] = gen_reg_rtx (DImode);
814 (define_expand "modsi3"
816 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
818 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
819 (parallel [(set (match_dup 5)
820 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
821 (clobber (reg:DI 23))
822 (clobber (reg:DI 28))])
823 (set (match_operand:SI 0 "nonimmediate_operand" "")
824 (subreg:SI (match_dup 5) 0))]
825 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
827 operands[3] = gen_reg_rtx (DImode);
828 operands[4] = gen_reg_rtx (DImode);
829 operands[5] = gen_reg_rtx (DImode);
832 (define_expand "umodsi3"
834 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
836 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
837 (parallel [(set (match_dup 5)
838 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
839 (clobber (reg:DI 23))
840 (clobber (reg:DI 28))])
841 (set (match_operand:SI 0 "nonimmediate_operand" "")
842 (subreg:SI (match_dup 5) 0))]
843 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
845 operands[3] = gen_reg_rtx (DImode);
846 operands[4] = gen_reg_rtx (DImode);
847 operands[5] = gen_reg_rtx (DImode);
850 (define_expand "divdi3"
851 [(parallel [(set (match_operand:DI 0 "register_operand" "")
852 (div:DI (match_operand:DI 1 "register_operand" "")
853 (match_operand:DI 2 "register_operand" "")))
854 (clobber (reg:DI 23))
855 (clobber (reg:DI 28))])]
856 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
859 (define_expand "udivdi3"
860 [(parallel [(set (match_operand:DI 0 "register_operand" "")
861 (udiv:DI (match_operand:DI 1 "register_operand" "")
862 (match_operand:DI 2 "register_operand" "")))
863 (clobber (reg:DI 23))
864 (clobber (reg:DI 28))])]
865 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
868 (define_expand "moddi3"
869 [(use (match_operand:DI 0 "register_operand" ""))
870 (use (match_operand:DI 1 "register_operand" ""))
871 (use (match_operand:DI 2 "register_operand" ""))]
872 "!TARGET_ABI_OPEN_VMS"
874 if (TARGET_ABI_UNICOSMK)
875 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
877 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
881 (define_expand "moddi3_dft"
882 [(parallel [(set (match_operand:DI 0 "register_operand" "")
883 (mod:DI (match_operand:DI 1 "register_operand" "")
884 (match_operand:DI 2 "register_operand" "")))
885 (clobber (reg:DI 23))
886 (clobber (reg:DI 28))])]
887 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
890 ;; On Unicos/Mk, we do as the system's C compiler does:
891 ;; compute the quotient, multiply and subtract.
893 (define_expand "moddi3_umk"
894 [(use (match_operand:DI 0 "register_operand" ""))
895 (use (match_operand:DI 1 "register_operand" ""))
896 (use (match_operand:DI 2 "register_operand" ""))]
897 "TARGET_ABI_UNICOSMK"
899 rtx div, mul = gen_reg_rtx (DImode);
901 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
902 NULL_RTX, 0, OPTAB_LIB);
903 div = force_reg (DImode, div);
904 emit_insn (gen_muldi3 (mul, operands[2], div));
905 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
909 (define_expand "umoddi3"
910 [(use (match_operand:DI 0 "register_operand" ""))
911 (use (match_operand:DI 1 "register_operand" ""))
912 (use (match_operand:DI 2 "register_operand" ""))]
913 "! TARGET_ABI_OPEN_VMS"
915 if (TARGET_ABI_UNICOSMK)
916 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
918 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
922 (define_expand "umoddi3_dft"
923 [(parallel [(set (match_operand:DI 0 "register_operand" "")
924 (umod:DI (match_operand:DI 1 "register_operand" "")
925 (match_operand:DI 2 "register_operand" "")))
926 (clobber (reg:DI 23))
927 (clobber (reg:DI 28))])]
928 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
931 (define_expand "umoddi3_umk"
932 [(use (match_operand:DI 0 "register_operand" ""))
933 (use (match_operand:DI 1 "register_operand" ""))
934 (use (match_operand:DI 2 "register_operand" ""))]
935 "TARGET_ABI_UNICOSMK"
937 rtx div, mul = gen_reg_rtx (DImode);
939 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
940 NULL_RTX, 1, OPTAB_LIB);
941 div = force_reg (DImode, div);
942 emit_insn (gen_muldi3 (mul, operands[2], div));
943 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
947 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
948 ;; expanded by the assembler.
950 (define_insn_and_split "*divmodsi_internal_er"
951 [(set (match_operand:DI 0 "register_operand" "=c")
952 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
953 [(match_operand:DI 1 "register_operand" "a")
954 (match_operand:DI 2 "register_operand" "b")])))
955 (clobber (reg:DI 23))
956 (clobber (reg:DI 28))]
957 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
958 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
959 "&& reload_completed"
960 [(parallel [(set (match_dup 0)
961 (sign_extend:DI (match_dup 3)))
964 (clobber (reg:DI 23))
965 (clobber (reg:DI 28))])]
968 switch (GET_CODE (operands[3]))
985 operands[4] = GEN_INT (alpha_next_sequence_number++);
986 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
987 gen_rtx_SYMBOL_REF (DImode, str),
990 [(set_attr "type" "jsr")
991 (set_attr "length" "8")])
993 (define_insn "*divmodsi_internal_er_1"
994 [(set (match_operand:DI 0 "register_operand" "=c")
995 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
996 [(match_operand:DI 1 "register_operand" "a")
997 (match_operand:DI 2 "register_operand" "b")])))
998 (use (match_operand:DI 4 "register_operand" "c"))
999 (use (match_operand 5 "const_int_operand" ""))
1000 (clobber (reg:DI 23))
1001 (clobber (reg:DI 28))]
1002 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1003 "jsr $23,($27),__%E3%J5"
1004 [(set_attr "type" "jsr")
1005 (set_attr "length" "4")])
1007 (define_insn "*divmodsi_internal"
1008 [(set (match_operand:DI 0 "register_operand" "=c")
1009 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1010 [(match_operand:DI 1 "register_operand" "a")
1011 (match_operand:DI 2 "register_operand" "b")])))
1012 (clobber (reg:DI 23))
1013 (clobber (reg:DI 28))]
1014 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1016 [(set_attr "type" "jsr")
1017 (set_attr "length" "8")])
1019 (define_insn_and_split "*divmoddi_internal_er"
1020 [(set (match_operand:DI 0 "register_operand" "=c")
1021 (match_operator:DI 3 "divmod_operator"
1022 [(match_operand:DI 1 "register_operand" "a")
1023 (match_operand:DI 2 "register_operand" "b")]))
1024 (clobber (reg:DI 23))
1025 (clobber (reg:DI 28))]
1026 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1027 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1028 "&& reload_completed"
1029 [(parallel [(set (match_dup 0) (match_dup 3))
1032 (clobber (reg:DI 23))
1033 (clobber (reg:DI 28))])]
1036 switch (GET_CODE (operands[3]))
1053 operands[4] = GEN_INT (alpha_next_sequence_number++);
1054 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1055 gen_rtx_SYMBOL_REF (DImode, str),
1058 [(set_attr "type" "jsr")
1059 (set_attr "length" "8")])
1061 (define_insn "*divmoddi_internal_er_1"
1062 [(set (match_operand:DI 0 "register_operand" "=c")
1063 (match_operator:DI 3 "divmod_operator"
1064 [(match_operand:DI 1 "register_operand" "a")
1065 (match_operand:DI 2 "register_operand" "b")]))
1066 (use (match_operand:DI 4 "register_operand" "c"))
1067 (use (match_operand 5 "const_int_operand" ""))
1068 (clobber (reg:DI 23))
1069 (clobber (reg:DI 28))]
1070 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1071 "jsr $23,($27),__%E3%J5"
1072 [(set_attr "type" "jsr")
1073 (set_attr "length" "4")])
1075 (define_insn "*divmoddi_internal"
1076 [(set (match_operand:DI 0 "register_operand" "=c")
1077 (match_operator:DI 3 "divmod_operator"
1078 [(match_operand:DI 1 "register_operand" "a")
1079 (match_operand:DI 2 "register_operand" "b")]))
1080 (clobber (reg:DI 23))
1081 (clobber (reg:DI 28))]
1082 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1084 [(set_attr "type" "jsr")
1085 (set_attr "length" "8")])
1087 ;; Next are the basic logical operations. These only exist in DImode.
1089 (define_insn "anddi3"
1090 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1091 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1092 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1098 [(set_attr "type" "ilog,ilog,shift")])
1100 ;; There are times when we can split an AND into two AND insns. This occurs
1101 ;; when we can first clear any bytes and then clear anything else. For
1102 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1103 ;; Only do this when running on 64-bit host since the computations are
1104 ;; too messy otherwise.
1107 [(set (match_operand:DI 0 "register_operand" "")
1108 (and:DI (match_operand:DI 1 "register_operand" "")
1109 (match_operand:DI 2 "const_int_operand" "")))]
1110 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1111 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1112 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1114 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1115 unsigned HOST_WIDE_INT mask2 = mask1;
1118 /* For each byte that isn't all zeros, make it all ones. */
1119 for (i = 0; i < 64; i += 8)
1120 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1121 mask1 |= (HOST_WIDE_INT) 0xff << i;
1123 /* Now turn on any bits we've just turned off. */
1126 operands[3] = GEN_INT (mask1);
1127 operands[4] = GEN_INT (mask2);
1130 (define_expand "zero_extendqihi2"
1131 [(set (match_operand:HI 0 "register_operand" "")
1132 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1136 operands[1] = force_reg (QImode, operands[1]);
1139 (define_insn "*zero_extendqihi2_bwx"
1140 [(set (match_operand:HI 0 "register_operand" "=r,r")
1141 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1146 [(set_attr "type" "ilog,ild")])
1148 (define_insn "*zero_extendqihi2_nobwx"
1149 [(set (match_operand:HI 0 "register_operand" "=r")
1150 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1153 [(set_attr "type" "ilog")])
1155 (define_expand "zero_extendqisi2"
1156 [(set (match_operand:SI 0 "register_operand" "")
1157 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1161 operands[1] = force_reg (QImode, operands[1]);
1164 (define_insn "*zero_extendqisi2_bwx"
1165 [(set (match_operand:SI 0 "register_operand" "=r,r")
1166 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1171 [(set_attr "type" "ilog,ild")])
1173 (define_insn "*zero_extendqisi2_nobwx"
1174 [(set (match_operand:SI 0 "register_operand" "=r")
1175 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1178 [(set_attr "type" "ilog")])
1180 (define_expand "zero_extendqidi2"
1181 [(set (match_operand:DI 0 "register_operand" "")
1182 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1186 operands[1] = force_reg (QImode, operands[1]);
1189 (define_insn "*zero_extendqidi2_bwx"
1190 [(set (match_operand:DI 0 "register_operand" "=r,r")
1191 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1196 [(set_attr "type" "ilog,ild")])
1198 (define_insn "*zero_extendqidi2_nobwx"
1199 [(set (match_operand:DI 0 "register_operand" "=r")
1200 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1203 [(set_attr "type" "ilog")])
1205 (define_expand "zero_extendhisi2"
1206 [(set (match_operand:SI 0 "register_operand" "")
1207 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1211 operands[1] = force_reg (HImode, operands[1]);
1214 (define_insn "*zero_extendhisi2_bwx"
1215 [(set (match_operand:SI 0 "register_operand" "=r,r")
1216 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1221 [(set_attr "type" "shift,ild")])
1223 (define_insn "*zero_extendhisi2_nobwx"
1224 [(set (match_operand:SI 0 "register_operand" "=r")
1225 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1228 [(set_attr "type" "shift")])
1230 (define_expand "zero_extendhidi2"
1231 [(set (match_operand:DI 0 "register_operand" "")
1232 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1236 operands[1] = force_reg (HImode, operands[1]);
1239 (define_insn "*zero_extendhidi2_bwx"
1240 [(set (match_operand:DI 0 "register_operand" "=r,r")
1241 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1246 [(set_attr "type" "shift,ild")])
1248 (define_insn "*zero_extendhidi2_nobwx"
1249 [(set (match_operand:DI 0 "register_operand" "=r")
1250 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1253 [(set_attr "type" "shift")])
1255 (define_insn "zero_extendsidi2"
1256 [(set (match_operand:DI 0 "register_operand" "=r")
1257 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1260 [(set_attr "type" "shift")])
1262 (define_insn "andnotdi3"
1263 [(set (match_operand:DI 0 "register_operand" "=r")
1264 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1265 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1268 [(set_attr "type" "ilog")])
1270 (define_insn "iordi3"
1271 [(set (match_operand:DI 0 "register_operand" "=r,r")
1272 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1273 (match_operand:DI 2 "or_operand" "rI,N")))]
1278 [(set_attr "type" "ilog")])
1280 (define_insn "one_cmpldi2"
1281 [(set (match_operand:DI 0 "register_operand" "=r")
1282 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1285 [(set_attr "type" "ilog")])
1287 (define_insn "*iornot"
1288 [(set (match_operand:DI 0 "register_operand" "=r")
1289 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1290 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1293 [(set_attr "type" "ilog")])
1295 (define_insn "xordi3"
1296 [(set (match_operand:DI 0 "register_operand" "=r,r")
1297 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1298 (match_operand:DI 2 "or_operand" "rI,N")))]
1303 [(set_attr "type" "ilog")])
1305 (define_insn "*xornot"
1306 [(set (match_operand:DI 0 "register_operand" "=r")
1307 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1308 (match_operand:DI 2 "register_operand" "rI"))))]
1311 [(set_attr "type" "ilog")])
1313 ;; Handle the FFS insn iff we support CIX.
1315 (define_expand "ffsdi2"
1317 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1319 (plus:DI (match_dup 2) (const_int 1)))
1320 (set (match_operand:DI 0 "register_operand" "")
1321 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1322 (const_int 0) (match_dup 3)))]
1325 operands[2] = gen_reg_rtx (DImode);
1326 operands[3] = gen_reg_rtx (DImode);
1329 (define_insn "*cttz"
1330 [(set (match_operand:DI 0 "register_operand" "=r")
1331 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1334 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1335 ; reuse the existing type name.
1336 [(set_attr "type" "mvi")])
1338 ;; Next come the shifts and the various extract and insert operations.
1340 (define_insn "ashldi3"
1341 [(set (match_operand:DI 0 "register_operand" "=r,r")
1342 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1343 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1346 switch (which_alternative)
1349 if (operands[2] == const1_rtx)
1350 return "addq %r1,%r1,%0";
1352 return "s%P2addq %r1,0,%0";
1354 return "sll %r1,%2,%0";
1359 [(set_attr "type" "iadd,shift")])
1361 (define_insn "*ashldi_se"
1362 [(set (match_operand:DI 0 "register_operand" "=r")
1364 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1365 (match_operand:DI 2 "const_int_operand" "P"))
1367 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1369 if (operands[2] == const1_rtx)
1370 return "addl %r1,%r1,%0";
1372 return "s%P2addl %r1,0,%0";
1374 [(set_attr "type" "iadd")])
1376 (define_insn "lshrdi3"
1377 [(set (match_operand:DI 0 "register_operand" "=r")
1378 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1379 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1382 [(set_attr "type" "shift")])
1384 (define_insn "ashrdi3"
1385 [(set (match_operand:DI 0 "register_operand" "=r")
1386 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1387 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1390 [(set_attr "type" "shift")])
1392 (define_expand "extendqihi2"
1394 (ashift:DI (match_operand:QI 1 "some_operand" "")
1396 (set (match_operand:HI 0 "register_operand" "")
1397 (ashiftrt:DI (match_dup 2)
1403 emit_insn (gen_extendqihi2x (operands[0],
1404 force_reg (QImode, operands[1])));
1408 /* If we have an unaligned MEM, extend to DImode (which we do
1409 specially) and then copy to the result. */
1410 if (unaligned_memory_operand (operands[1], HImode))
1412 rtx temp = gen_reg_rtx (DImode);
1414 emit_insn (gen_extendqidi2 (temp, operands[1]));
1415 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1419 operands[0] = gen_lowpart (DImode, operands[0]);
1420 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1421 operands[2] = gen_reg_rtx (DImode);
1424 (define_insn "extendqidi2x"
1425 [(set (match_operand:DI 0 "register_operand" "=r")
1426 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1429 [(set_attr "type" "shift")])
1431 (define_insn "extendhidi2x"
1432 [(set (match_operand:DI 0 "register_operand" "=r")
1433 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1436 [(set_attr "type" "shift")])
1438 (define_insn "extendqisi2x"
1439 [(set (match_operand:SI 0 "register_operand" "=r")
1440 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1443 [(set_attr "type" "shift")])
1445 (define_insn "extendhisi2x"
1446 [(set (match_operand:SI 0 "register_operand" "=r")
1447 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1450 [(set_attr "type" "shift")])
1452 (define_insn "extendqihi2x"
1453 [(set (match_operand:HI 0 "register_operand" "=r")
1454 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1457 [(set_attr "type" "shift")])
1459 (define_expand "extendqisi2"
1461 (ashift:DI (match_operand:QI 1 "some_operand" "")
1463 (set (match_operand:SI 0 "register_operand" "")
1464 (ashiftrt:DI (match_dup 2)
1470 emit_insn (gen_extendqisi2x (operands[0],
1471 force_reg (QImode, operands[1])));
1475 /* If we have an unaligned MEM, extend to a DImode form of
1476 the result (which we do specially). */
1477 if (unaligned_memory_operand (operands[1], QImode))
1479 rtx temp = gen_reg_rtx (DImode);
1481 emit_insn (gen_extendqidi2 (temp, operands[1]));
1482 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1486 operands[0] = gen_lowpart (DImode, operands[0]);
1487 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1488 operands[2] = gen_reg_rtx (DImode);
1491 (define_expand "extendqidi2"
1493 (ashift:DI (match_operand:QI 1 "some_operand" "")
1495 (set (match_operand:DI 0 "register_operand" "")
1496 (ashiftrt:DI (match_dup 2)
1502 emit_insn (gen_extendqidi2x (operands[0],
1503 force_reg (QImode, operands[1])));
1507 if (unaligned_memory_operand (operands[1], QImode))
1510 = gen_unaligned_extendqidi (operands[0],
1511 get_unaligned_address (operands[1], 1));
1513 alpha_set_memflags (seq, operands[1]);
1518 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1519 operands[2] = gen_reg_rtx (DImode);
1522 (define_expand "extendhisi2"
1524 (ashift:DI (match_operand:HI 1 "some_operand" "")
1526 (set (match_operand:SI 0 "register_operand" "")
1527 (ashiftrt:DI (match_dup 2)
1533 emit_insn (gen_extendhisi2x (operands[0],
1534 force_reg (HImode, operands[1])));
1538 /* If we have an unaligned MEM, extend to a DImode form of
1539 the result (which we do specially). */
1540 if (unaligned_memory_operand (operands[1], HImode))
1542 rtx temp = gen_reg_rtx (DImode);
1544 emit_insn (gen_extendhidi2 (temp, operands[1]));
1545 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1549 operands[0] = gen_lowpart (DImode, operands[0]);
1550 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1551 operands[2] = gen_reg_rtx (DImode);
1554 (define_expand "extendhidi2"
1556 (ashift:DI (match_operand:HI 1 "some_operand" "")
1558 (set (match_operand:DI 0 "register_operand" "")
1559 (ashiftrt:DI (match_dup 2)
1565 emit_insn (gen_extendhidi2x (operands[0],
1566 force_reg (HImode, operands[1])));
1570 if (unaligned_memory_operand (operands[1], HImode))
1573 = gen_unaligned_extendhidi (operands[0],
1574 get_unaligned_address (operands[1], 2));
1576 alpha_set_memflags (seq, operands[1]);
1581 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1582 operands[2] = gen_reg_rtx (DImode);
1585 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1586 ;; as a pattern saves one instruction. The code is similar to that for
1587 ;; the unaligned loads (see below).
1589 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1590 (define_expand "unaligned_extendqidi"
1591 [(use (match_operand:QI 0 "register_operand" ""))
1592 (use (match_operand:DI 1 "address_operand" ""))]
1595 if (WORDS_BIG_ENDIAN)
1596 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1598 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1602 (define_expand "unaligned_extendqidi_le"
1603 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1605 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1608 (ashift:DI (match_dup 3)
1609 (minus:DI (const_int 64)
1611 (and:DI (match_dup 2) (const_int 7))
1613 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1614 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1615 "! WORDS_BIG_ENDIAN"
1617 operands[2] = gen_reg_rtx (DImode);
1618 operands[3] = gen_reg_rtx (DImode);
1619 operands[4] = gen_reg_rtx (DImode);
1622 (define_expand "unaligned_extendqidi_be"
1623 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1624 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1626 (mem:DI (and:DI (match_dup 3)
1628 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1630 (ashift:DI (match_dup 4)
1633 (plus:DI (match_dup 5) (const_int 1))
1636 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1637 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1640 operands[2] = gen_reg_rtx (DImode);
1641 operands[3] = gen_reg_rtx (DImode);
1642 operands[4] = gen_reg_rtx (DImode);
1643 operands[5] = gen_reg_rtx (DImode);
1644 operands[6] = gen_reg_rtx (DImode);
1647 (define_expand "unaligned_extendhidi"
1648 [(use (match_operand:QI 0 "register_operand" ""))
1649 (use (match_operand:DI 1 "address_operand" ""))]
1652 operands[0] = gen_lowpart (DImode, operands[0]);
1653 emit_insn ((WORDS_BIG_ENDIAN
1654 ? gen_unaligned_extendhidi_be
1655 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1659 (define_expand "unaligned_extendhidi_le"
1660 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1662 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1665 (ashift:DI (match_dup 3)
1666 (minus:DI (const_int 64)
1668 (and:DI (match_dup 2) (const_int 7))
1670 (set (match_operand:DI 0 "register_operand" "")
1671 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1672 "! WORDS_BIG_ENDIAN"
1674 operands[2] = gen_reg_rtx (DImode);
1675 operands[3] = gen_reg_rtx (DImode);
1676 operands[4] = gen_reg_rtx (DImode);
1679 (define_expand "unaligned_extendhidi_be"
1680 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1681 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1683 (mem:DI (and:DI (match_dup 3)
1685 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1687 (ashift:DI (match_dup 4)
1690 (plus:DI (match_dup 5) (const_int 1))
1693 (set (match_operand:DI 0 "register_operand" "")
1694 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1697 operands[2] = gen_reg_rtx (DImode);
1698 operands[3] = gen_reg_rtx (DImode);
1699 operands[4] = gen_reg_rtx (DImode);
1700 operands[5] = gen_reg_rtx (DImode);
1701 operands[6] = gen_reg_rtx (DImode);
1704 (define_insn "*extxl_const"
1705 [(set (match_operand:DI 0 "register_operand" "=r")
1706 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1707 (match_operand:DI 2 "mode_width_operand" "n")
1708 (match_operand:DI 3 "mul8_operand" "I")))]
1710 "ext%M2l %r1,%s3,%0"
1711 [(set_attr "type" "shift")])
1713 (define_insn "extxl_le"
1714 [(set (match_operand:DI 0 "register_operand" "=r")
1715 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1716 (match_operand:DI 2 "mode_width_operand" "n")
1717 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1719 "! WORDS_BIG_ENDIAN"
1721 [(set_attr "type" "shift")])
1723 (define_insn "extxl_be"
1724 [(set (match_operand:DI 0 "register_operand" "=r")
1725 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1726 (match_operand:DI 2 "mode_width_operand" "n")
1730 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1734 [(set_attr "type" "shift")])
1736 ;; Combine has some strange notion of preserving existing undefined behavior
1737 ;; in shifts larger than a word size. So capture these patterns that it
1738 ;; should have turned into zero_extracts.
1740 (define_insn "*extxl_1_le"
1741 [(set (match_operand:DI 0 "register_operand" "=r")
1742 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1743 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1745 (match_operand:DI 3 "mode_mask_operand" "n")))]
1746 "! WORDS_BIG_ENDIAN"
1748 [(set_attr "type" "shift")])
1750 (define_insn "*extxl_1_be"
1751 [(set (match_operand:DI 0 "register_operand" "=r")
1752 (and:DI (lshiftrt:DI
1753 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1754 (minus:DI (const_int 56)
1755 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1757 (match_operand:DI 3 "mode_mask_operand" "n")))]
1760 [(set_attr "type" "shift")])
1762 (define_insn "*extql_2_le"
1763 [(set (match_operand:DI 0 "register_operand" "=r")
1764 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1765 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1767 "! WORDS_BIG_ENDIAN"
1769 [(set_attr "type" "shift")])
1771 (define_insn "*extql_2_be"
1772 [(set (match_operand:DI 0 "register_operand" "=r")
1774 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1775 (minus:DI (const_int 56)
1777 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1781 [(set_attr "type" "shift")])
1783 (define_insn "extqh_le"
1784 [(set (match_operand:DI 0 "register_operand" "=r")
1786 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1787 (minus:DI (const_int 64)
1790 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1793 "! WORDS_BIG_ENDIAN"
1795 [(set_attr "type" "shift")])
1797 (define_insn "extqh_be"
1798 [(set (match_operand:DI 0 "register_operand" "=r")
1800 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1803 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1809 [(set_attr "type" "shift")])
1811 (define_insn "extlh_le"
1812 [(set (match_operand:DI 0 "register_operand" "=r")
1814 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1815 (const_int 2147483647))
1816 (minus:DI (const_int 64)
1819 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1822 "! WORDS_BIG_ENDIAN"
1824 [(set_attr "type" "shift")])
1826 (define_insn "extlh_be"
1827 [(set (match_operand:DI 0 "register_operand" "=r")
1830 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1834 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1838 (const_int 2147483647)))]
1841 [(set_attr "type" "shift")])
1843 (define_insn "extwh_le"
1844 [(set (match_operand:DI 0 "register_operand" "=r")
1846 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1848 (minus:DI (const_int 64)
1851 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1854 "! WORDS_BIG_ENDIAN"
1856 [(set_attr "type" "shift")])
1858 (define_insn "extwh_be"
1859 [(set (match_operand:DI 0 "register_operand" "=r")
1861 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1865 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1869 (const_int 65535)))]
1872 [(set_attr "type" "shift")])
1874 ;; This converts an extXl into an extXh with an appropriate adjustment
1875 ;; to the address calculation.
1878 ;; [(set (match_operand:DI 0 "register_operand" "")
1879 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1880 ;; (match_operand:DI 2 "mode_width_operand" "")
1881 ;; (ashift:DI (match_operand:DI 3 "" "")
1883 ;; (match_operand:DI 4 "const_int_operand" "")))
1884 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1885 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1886 ;; [(set (match_dup 5) (match_dup 6))
1887 ;; (set (match_dup 0)
1888 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1889 ;; (ashift:DI (plus:DI (match_dup 5)
1895 ;; operands[6] = plus_constant (operands[3],
1896 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1897 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1900 (define_insn "*insbl_const"
1901 [(set (match_operand:DI 0 "register_operand" "=r")
1902 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1903 (match_operand:DI 2 "mul8_operand" "I")))]
1906 [(set_attr "type" "shift")])
1908 (define_insn "*inswl_const"
1909 [(set (match_operand:DI 0 "register_operand" "=r")
1910 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1911 (match_operand:DI 2 "mul8_operand" "I")))]
1914 [(set_attr "type" "shift")])
1916 (define_insn "*insll_const"
1917 [(set (match_operand:DI 0 "register_operand" "=r")
1918 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1919 (match_operand:DI 2 "mul8_operand" "I")))]
1922 [(set_attr "type" "shift")])
1924 (define_insn "insbl_le"
1925 [(set (match_operand:DI 0 "register_operand" "=r")
1926 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1927 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1929 "! WORDS_BIG_ENDIAN"
1931 [(set_attr "type" "shift")])
1933 (define_insn "insbl_be"
1934 [(set (match_operand:DI 0 "register_operand" "=r")
1935 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1936 (minus:DI (const_int 56)
1937 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1941 [(set_attr "type" "shift")])
1943 (define_insn "inswl_le"
1944 [(set (match_operand:DI 0 "register_operand" "=r")
1945 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1946 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1948 "! WORDS_BIG_ENDIAN"
1950 [(set_attr "type" "shift")])
1952 (define_insn "inswl_be"
1953 [(set (match_operand:DI 0 "register_operand" "=r")
1954 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1955 (minus:DI (const_int 56)
1956 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1960 [(set_attr "type" "shift")])
1962 (define_insn "insll_le"
1963 [(set (match_operand:DI 0 "register_operand" "=r")
1964 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1965 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1967 "! WORDS_BIG_ENDIAN"
1969 [(set_attr "type" "shift")])
1971 (define_insn "insll_be"
1972 [(set (match_operand:DI 0 "register_operand" "=r")
1973 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1974 (minus:DI (const_int 56)
1975 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1979 [(set_attr "type" "shift")])
1981 (define_insn "insql_le"
1982 [(set (match_operand:DI 0 "register_operand" "=r")
1983 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1984 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1986 "! WORDS_BIG_ENDIAN"
1988 [(set_attr "type" "shift")])
1990 (define_insn "insql_be"
1991 [(set (match_operand:DI 0 "register_operand" "=r")
1992 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1993 (minus:DI (const_int 56)
1994 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1998 [(set_attr "type" "shift")])
2000 ;; Combine has this sometimes habit of moving the and outside of the
2001 ;; shift, making life more interesting.
2003 (define_insn "*insxl"
2004 [(set (match_operand:DI 0 "register_operand" "=r")
2005 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2006 (match_operand:DI 2 "mul8_operand" "I"))
2007 (match_operand:DI 3 "immediate_operand" "i")))]
2008 "HOST_BITS_PER_WIDE_INT == 64
2009 && GET_CODE (operands[3]) == CONST_INT
2010 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2011 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2012 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2013 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2014 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2015 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2017 #if HOST_BITS_PER_WIDE_INT == 64
2018 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2019 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2020 return "insbl %1,%s2,%0";
2021 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2022 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2023 return "inswl %1,%s2,%0";
2024 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2025 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2026 return "insll %1,%s2,%0";
2030 [(set_attr "type" "shift")])
2032 ;; We do not include the insXh insns because they are complex to express
2033 ;; and it does not appear that we would ever want to generate them.
2035 ;; Since we need them for block moves, though, cop out and use unspec.
2037 (define_insn "insxh"
2038 [(set (match_operand:DI 0 "register_operand" "=r")
2039 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2040 (match_operand:DI 2 "mode_width_operand" "n")
2041 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2045 [(set_attr "type" "shift")])
2047 (define_insn "mskxl_le"
2048 [(set (match_operand:DI 0 "register_operand" "=r")
2049 (and:DI (not:DI (ashift:DI
2050 (match_operand:DI 2 "mode_mask_operand" "n")
2052 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2054 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2055 "! WORDS_BIG_ENDIAN"
2057 [(set_attr "type" "shift")])
2059 (define_insn "mskxl_be"
2060 [(set (match_operand:DI 0 "register_operand" "=r")
2061 (and:DI (not:DI (ashift:DI
2062 (match_operand:DI 2 "mode_mask_operand" "n")
2063 (minus:DI (const_int 56)
2065 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2067 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2070 [(set_attr "type" "shift")])
2072 ;; We do not include the mskXh insns because it does not appear we would
2073 ;; ever generate one.
2075 ;; Again, we do for block moves and we use unspec again.
2077 (define_insn "mskxh"
2078 [(set (match_operand:DI 0 "register_operand" "=r")
2079 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2080 (match_operand:DI 2 "mode_width_operand" "n")
2081 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2085 [(set_attr "type" "shift")])
2087 ;; Prefer AND + NE over LSHIFTRT + AND.
2089 (define_insn_and_split "*ze_and_ne"
2090 [(set (match_operand:DI 0 "register_operand" "=r")
2091 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2093 (match_operand 2 "const_int_operand" "I")))]
2094 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2096 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2098 (and:DI (match_dup 1) (match_dup 3)))
2100 (ne:DI (match_dup 0) (const_int 0)))]
2101 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2103 ;; Floating-point operations. All the double-precision insns can extend
2104 ;; from single, so indicate that. The exception are the ones that simply
2105 ;; play with the sign bits; it's not clear what to do there.
2107 (define_insn "abssf2"
2108 [(set (match_operand:SF 0 "register_operand" "=f")
2109 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2112 [(set_attr "type" "fcpys")])
2114 (define_insn "*nabssf2"
2115 [(set (match_operand:SF 0 "register_operand" "=f")
2116 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2119 [(set_attr "type" "fadd")])
2121 (define_insn "absdf2"
2122 [(set (match_operand:DF 0 "register_operand" "=f")
2123 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2126 [(set_attr "type" "fcpys")])
2128 (define_insn "*nabsdf2"
2129 [(set (match_operand:DF 0 "register_operand" "=f")
2130 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2133 [(set_attr "type" "fadd")])
2135 (define_expand "abstf2"
2136 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2137 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2138 (use (match_dup 2))])]
2139 "TARGET_HAS_XFLOATING_LIBS"
2141 #if HOST_BITS_PER_WIDE_INT >= 64
2142 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2144 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2148 (define_insn_and_split "*abstf_internal"
2149 [(set (match_operand:TF 0 "register_operand" "=r")
2150 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2151 (use (match_operand:DI 2 "register_operand" "r"))]
2152 "TARGET_HAS_XFLOATING_LIBS"
2154 "&& reload_completed"
2156 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2158 (define_insn "negsf2"
2159 [(set (match_operand:SF 0 "register_operand" "=f")
2160 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2163 [(set_attr "type" "fadd")])
2165 (define_insn "negdf2"
2166 [(set (match_operand:DF 0 "register_operand" "=f")
2167 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2170 [(set_attr "type" "fadd")])
2172 (define_expand "negtf2"
2173 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2174 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2175 (use (match_dup 2))])]
2176 "TARGET_HAS_XFLOATING_LIBS"
2178 #if HOST_BITS_PER_WIDE_INT >= 64
2179 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2181 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2185 (define_insn_and_split "*negtf_internal"
2186 [(set (match_operand:TF 0 "register_operand" "=r")
2187 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2188 (use (match_operand:DI 2 "register_operand" "r"))]
2189 "TARGET_HAS_XFLOATING_LIBS"
2191 "&& reload_completed"
2193 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2195 (define_insn "*addsf_ieee"
2196 [(set (match_operand:SF 0 "register_operand" "=&f")
2197 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2198 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2199 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2200 "add%,%/ %R1,%R2,%0"
2201 [(set_attr "type" "fadd")
2202 (set_attr "trap" "yes")
2203 (set_attr "round_suffix" "normal")
2204 (set_attr "trap_suffix" "u_su_sui")])
2206 (define_insn "addsf3"
2207 [(set (match_operand:SF 0 "register_operand" "=f")
2208 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2209 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2211 "add%,%/ %R1,%R2,%0"
2212 [(set_attr "type" "fadd")
2213 (set_attr "trap" "yes")
2214 (set_attr "round_suffix" "normal")
2215 (set_attr "trap_suffix" "u_su_sui")])
2217 (define_insn "*adddf_ieee"
2218 [(set (match_operand:DF 0 "register_operand" "=&f")
2219 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2220 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2221 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2222 "add%-%/ %R1,%R2,%0"
2223 [(set_attr "type" "fadd")
2224 (set_attr "trap" "yes")
2225 (set_attr "round_suffix" "normal")
2226 (set_attr "trap_suffix" "u_su_sui")])
2228 (define_insn "adddf3"
2229 [(set (match_operand:DF 0 "register_operand" "=f")
2230 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2231 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2233 "add%-%/ %R1,%R2,%0"
2234 [(set_attr "type" "fadd")
2235 (set_attr "trap" "yes")
2236 (set_attr "round_suffix" "normal")
2237 (set_attr "trap_suffix" "u_su_sui")])
2239 (define_insn "*adddf_ext1"
2240 [(set (match_operand:DF 0 "register_operand" "=f")
2241 (plus:DF (float_extend:DF
2242 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2243 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2244 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2245 "add%-%/ %R1,%R2,%0"
2246 [(set_attr "type" "fadd")
2247 (set_attr "trap" "yes")
2248 (set_attr "round_suffix" "normal")
2249 (set_attr "trap_suffix" "u_su_sui")])
2251 (define_insn "*adddf_ext2"
2252 [(set (match_operand:DF 0 "register_operand" "=f")
2253 (plus:DF (float_extend:DF
2254 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2256 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2257 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2258 "add%-%/ %R1,%R2,%0"
2259 [(set_attr "type" "fadd")
2260 (set_attr "trap" "yes")
2261 (set_attr "round_suffix" "normal")
2262 (set_attr "trap_suffix" "u_su_sui")])
2264 (define_expand "addtf3"
2265 [(use (match_operand 0 "register_operand" ""))
2266 (use (match_operand 1 "general_operand" ""))
2267 (use (match_operand 2 "general_operand" ""))]
2268 "TARGET_HAS_XFLOATING_LIBS"
2269 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2271 ;; Define conversion operators between DFmode and SImode, using the cvtql
2272 ;; instruction. To allow combine et al to do useful things, we keep the
2273 ;; operation as a unit until after reload, at which point we split the
2276 ;; Note that we (attempt to) only consider this optimization when the
2277 ;; ultimate destination is memory. If we will be doing further integer
2278 ;; processing, it is cheaper to do the truncation in the int regs.
2280 (define_insn "*cvtql"
2281 [(set (match_operand:SI 0 "register_operand" "=f")
2282 (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2286 [(set_attr "type" "fadd")
2287 (set_attr "trap" "yes")
2288 (set_attr "trap_suffix" "v_sv")])
2290 (define_insn_and_split "*fix_truncdfsi_ieee"
2291 [(set (match_operand:SI 0 "memory_operand" "=m")
2292 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2293 (clobber (match_scratch:DI 2 "=&f"))
2294 (clobber (match_scratch:SI 3 "=&f"))]
2295 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2297 "&& reload_completed"
2298 [(set (match_dup 2) (fix:DI (match_dup 1)))
2299 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2300 (set (match_dup 0) (match_dup 3))]
2302 [(set_attr "type" "fadd")
2303 (set_attr "trap" "yes")])
2305 (define_insn_and_split "*fix_truncdfsi_internal"
2306 [(set (match_operand:SI 0 "memory_operand" "=m")
2307 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2308 (clobber (match_scratch:DI 2 "=f"))]
2309 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2311 "&& reload_completed"
2312 [(set (match_dup 2) (fix:DI (match_dup 1)))
2313 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2314 (set (match_dup 0) (match_dup 3))]
2315 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2316 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2317 [(set_attr "type" "fadd")
2318 (set_attr "trap" "yes")])
2320 (define_insn "*fix_truncdfdi_ieee"
2321 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2322 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2323 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2325 [(set_attr "type" "fadd")
2326 (set_attr "trap" "yes")
2327 (set_attr "round_suffix" "c")
2328 (set_attr "trap_suffix" "v_sv_svi")])
2330 (define_insn "fix_truncdfdi2"
2331 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2332 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2335 [(set_attr "type" "fadd")
2336 (set_attr "trap" "yes")
2337 (set_attr "round_suffix" "c")
2338 (set_attr "trap_suffix" "v_sv_svi")])
2340 ;; Likewise between SFmode and SImode.
2342 (define_insn_and_split "*fix_truncsfsi_ieee"
2343 [(set (match_operand:SI 0 "memory_operand" "=m")
2344 (subreg:SI (fix:DI (float_extend:DF
2345 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2346 (clobber (match_scratch:DI 2 "=&f"))
2347 (clobber (match_scratch:SI 3 "=&f"))]
2348 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2350 "&& reload_completed"
2351 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2352 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2353 (set (match_dup 0) (match_dup 3))]
2355 [(set_attr "type" "fadd")
2356 (set_attr "trap" "yes")])
2358 (define_insn_and_split "*fix_truncsfsi_internal"
2359 [(set (match_operand:SI 0 "memory_operand" "=m")
2360 (subreg:SI (fix:DI (float_extend:DF
2361 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2362 (clobber (match_scratch:DI 2 "=f"))]
2363 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2365 "&& reload_completed"
2366 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2367 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2368 (set (match_dup 0) (match_dup 3))]
2369 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2370 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2371 [(set_attr "type" "fadd")
2372 (set_attr "trap" "yes")])
2374 (define_insn "*fix_truncsfdi_ieee"
2375 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2376 (fix:DI (float_extend:DF
2377 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2378 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2380 [(set_attr "type" "fadd")
2381 (set_attr "trap" "yes")
2382 (set_attr "round_suffix" "c")
2383 (set_attr "trap_suffix" "v_sv_svi")])
2385 (define_insn "fix_truncsfdi2"
2386 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2387 (fix:DI (float_extend:DF
2388 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2391 [(set_attr "type" "fadd")
2392 (set_attr "trap" "yes")
2393 (set_attr "round_suffix" "c")
2394 (set_attr "trap_suffix" "v_sv_svi")])
2396 (define_expand "fix_trunctfdi2"
2397 [(use (match_operand:DI 0 "register_operand" ""))
2398 (use (match_operand:TF 1 "general_operand" ""))]
2399 "TARGET_HAS_XFLOATING_LIBS"
2400 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2402 (define_insn "*floatdisf_ieee"
2403 [(set (match_operand:SF 0 "register_operand" "=&f")
2404 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2405 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2407 [(set_attr "type" "fadd")
2408 (set_attr "trap" "yes")
2409 (set_attr "round_suffix" "normal")
2410 (set_attr "trap_suffix" "sui")])
2412 (define_insn "floatdisf2"
2413 [(set (match_operand:SF 0 "register_operand" "=f")
2414 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2417 [(set_attr "type" "fadd")
2418 (set_attr "trap" "yes")
2419 (set_attr "round_suffix" "normal")
2420 (set_attr "trap_suffix" "sui")])
2422 (define_insn "*floatdidf_ieee"
2423 [(set (match_operand:DF 0 "register_operand" "=&f")
2424 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2425 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2427 [(set_attr "type" "fadd")
2428 (set_attr "trap" "yes")
2429 (set_attr "round_suffix" "normal")
2430 (set_attr "trap_suffix" "sui")])
2432 (define_insn "floatdidf2"
2433 [(set (match_operand:DF 0 "register_operand" "=f")
2434 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2437 [(set_attr "type" "fadd")
2438 (set_attr "trap" "yes")
2439 (set_attr "round_suffix" "normal")
2440 (set_attr "trap_suffix" "sui")])
2442 (define_expand "floatditf2"
2443 [(use (match_operand:TF 0 "register_operand" ""))
2444 (use (match_operand:DI 1 "general_operand" ""))]
2445 "TARGET_HAS_XFLOATING_LIBS"
2446 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2448 (define_expand "floatunsdisf2"
2449 [(use (match_operand:SF 0 "register_operand" ""))
2450 (use (match_operand:DI 1 "register_operand" ""))]
2452 "alpha_emit_floatuns (operands); DONE;")
2454 (define_expand "floatunsdidf2"
2455 [(use (match_operand:DF 0 "register_operand" ""))
2456 (use (match_operand:DI 1 "register_operand" ""))]
2458 "alpha_emit_floatuns (operands); DONE;")
2460 (define_expand "floatunsditf2"
2461 [(use (match_operand:TF 0 "register_operand" ""))
2462 (use (match_operand:DI 1 "general_operand" ""))]
2463 "TARGET_HAS_XFLOATING_LIBS"
2464 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2466 (define_expand "extendsfdf2"
2467 [(set (match_operand:DF 0 "register_operand" "")
2468 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2471 if (alpha_fptm >= ALPHA_FPTM_SU)
2472 operands[1] = force_reg (SFmode, operands[1]);
2475 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2476 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2478 (define_insn "*extendsfdf2_ieee"
2479 [(set (match_operand:DF 0 "register_operand" "=&f")
2480 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2481 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2483 [(set_attr "type" "fadd")
2484 (set_attr "trap" "yes")])
2486 (define_insn "*extendsfdf2_internal"
2487 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2488 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2489 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2494 [(set_attr "type" "fcpys,fld,fst")])
2496 (define_expand "extendsftf2"
2497 [(use (match_operand:TF 0 "register_operand" ""))
2498 (use (match_operand:SF 1 "general_operand" ""))]
2499 "TARGET_HAS_XFLOATING_LIBS"
2501 rtx tmp = gen_reg_rtx (DFmode);
2502 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2503 emit_insn (gen_extenddftf2 (operands[0], tmp));
2507 (define_expand "extenddftf2"
2508 [(use (match_operand:TF 0 "register_operand" ""))
2509 (use (match_operand:DF 1 "general_operand" ""))]
2510 "TARGET_HAS_XFLOATING_LIBS"
2511 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2513 (define_insn "*truncdfsf2_ieee"
2514 [(set (match_operand:SF 0 "register_operand" "=&f")
2515 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2516 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2518 [(set_attr "type" "fadd")
2519 (set_attr "trap" "yes")
2520 (set_attr "round_suffix" "normal")
2521 (set_attr "trap_suffix" "u_su_sui")])
2523 (define_insn "truncdfsf2"
2524 [(set (match_operand:SF 0 "register_operand" "=f")
2525 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2528 [(set_attr "type" "fadd")
2529 (set_attr "trap" "yes")
2530 (set_attr "round_suffix" "normal")
2531 (set_attr "trap_suffix" "u_su_sui")])
2533 (define_expand "trunctfdf2"
2534 [(use (match_operand:DF 0 "register_operand" ""))
2535 (use (match_operand:TF 1 "general_operand" ""))]
2536 "TARGET_HAS_XFLOATING_LIBS"
2537 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2539 (define_expand "trunctfsf2"
2540 [(use (match_operand:SF 0 "register_operand" ""))
2541 (use (match_operand:TF 1 "general_operand" ""))]
2542 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2544 rtx tmpf, sticky, arg, lo, hi;
2546 tmpf = gen_reg_rtx (DFmode);
2547 sticky = gen_reg_rtx (DImode);
2548 arg = copy_to_mode_reg (TFmode, operands[1]);
2549 lo = gen_lowpart (DImode, arg);
2550 hi = gen_highpart (DImode, arg);
2552 /* Convert the low word of the TFmode value into a sticky rounding bit,
2553 then or it into the low bit of the high word. This leaves the sticky
2554 bit at bit 48 of the fraction, which is representable in DFmode,
2555 which prevents rounding error in the final conversion to SFmode. */
2557 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2558 gen_rtx_NE (DImode, lo, const0_rtx)));
2559 emit_insn (gen_iordi3 (hi, hi, sticky));
2560 emit_insn (gen_trunctfdf2 (tmpf, arg));
2561 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2565 (define_insn "*divsf3_ieee"
2566 [(set (match_operand:SF 0 "register_operand" "=&f")
2567 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2568 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2569 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2570 "div%,%/ %R1,%R2,%0"
2571 [(set_attr "type" "fdiv")
2572 (set_attr "opsize" "si")
2573 (set_attr "trap" "yes")
2574 (set_attr "round_suffix" "normal")
2575 (set_attr "trap_suffix" "u_su_sui")])
2577 (define_insn "divsf3"
2578 [(set (match_operand:SF 0 "register_operand" "=f")
2579 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2580 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2582 "div%,%/ %R1,%R2,%0"
2583 [(set_attr "type" "fdiv")
2584 (set_attr "opsize" "si")
2585 (set_attr "trap" "yes")
2586 (set_attr "round_suffix" "normal")
2587 (set_attr "trap_suffix" "u_su_sui")])
2589 (define_insn "*divdf3_ieee"
2590 [(set (match_operand:DF 0 "register_operand" "=&f")
2591 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2592 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2593 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2594 "div%-%/ %R1,%R2,%0"
2595 [(set_attr "type" "fdiv")
2596 (set_attr "trap" "yes")
2597 (set_attr "round_suffix" "normal")
2598 (set_attr "trap_suffix" "u_su_sui")])
2600 (define_insn "divdf3"
2601 [(set (match_operand:DF 0 "register_operand" "=f")
2602 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2603 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2605 "div%-%/ %R1,%R2,%0"
2606 [(set_attr "type" "fdiv")
2607 (set_attr "trap" "yes")
2608 (set_attr "round_suffix" "normal")
2609 (set_attr "trap_suffix" "u_su_sui")])
2611 (define_insn "*divdf_ext1"
2612 [(set (match_operand:DF 0 "register_operand" "=f")
2613 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2614 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2615 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2616 "div%-%/ %R1,%R2,%0"
2617 [(set_attr "type" "fdiv")
2618 (set_attr "trap" "yes")
2619 (set_attr "round_suffix" "normal")
2620 (set_attr "trap_suffix" "u_su_sui")])
2622 (define_insn "*divdf_ext2"
2623 [(set (match_operand:DF 0 "register_operand" "=f")
2624 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2626 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2627 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2628 "div%-%/ %R1,%R2,%0"
2629 [(set_attr "type" "fdiv")
2630 (set_attr "trap" "yes")
2631 (set_attr "round_suffix" "normal")
2632 (set_attr "trap_suffix" "u_su_sui")])
2634 (define_insn "*divdf_ext3"
2635 [(set (match_operand:DF 0 "register_operand" "=f")
2636 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2637 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2638 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2639 "div%-%/ %R1,%R2,%0"
2640 [(set_attr "type" "fdiv")
2641 (set_attr "trap" "yes")
2642 (set_attr "round_suffix" "normal")
2643 (set_attr "trap_suffix" "u_su_sui")])
2645 (define_expand "divtf3"
2646 [(use (match_operand 0 "register_operand" ""))
2647 (use (match_operand 1 "general_operand" ""))
2648 (use (match_operand 2 "general_operand" ""))]
2649 "TARGET_HAS_XFLOATING_LIBS"
2650 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2652 (define_insn "*mulsf3_ieee"
2653 [(set (match_operand:SF 0 "register_operand" "=&f")
2654 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2655 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2656 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2657 "mul%,%/ %R1,%R2,%0"
2658 [(set_attr "type" "fmul")
2659 (set_attr "trap" "yes")
2660 (set_attr "round_suffix" "normal")
2661 (set_attr "trap_suffix" "u_su_sui")])
2663 (define_insn "mulsf3"
2664 [(set (match_operand:SF 0 "register_operand" "=f")
2665 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2666 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2668 "mul%,%/ %R1,%R2,%0"
2669 [(set_attr "type" "fmul")
2670 (set_attr "trap" "yes")
2671 (set_attr "round_suffix" "normal")
2672 (set_attr "trap_suffix" "u_su_sui")])
2674 (define_insn "*muldf3_ieee"
2675 [(set (match_operand:DF 0 "register_operand" "=&f")
2676 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2677 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2678 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2679 "mul%-%/ %R1,%R2,%0"
2680 [(set_attr "type" "fmul")
2681 (set_attr "trap" "yes")
2682 (set_attr "round_suffix" "normal")
2683 (set_attr "trap_suffix" "u_su_sui")])
2685 (define_insn "muldf3"
2686 [(set (match_operand:DF 0 "register_operand" "=f")
2687 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2688 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2690 "mul%-%/ %R1,%R2,%0"
2691 [(set_attr "type" "fmul")
2692 (set_attr "trap" "yes")
2693 (set_attr "round_suffix" "normal")
2694 (set_attr "trap_suffix" "u_su_sui")])
2696 (define_insn "*muldf_ext1"
2697 [(set (match_operand:DF 0 "register_operand" "=f")
2698 (mult:DF (float_extend:DF
2699 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2700 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2701 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2702 "mul%-%/ %R1,%R2,%0"
2703 [(set_attr "type" "fmul")
2704 (set_attr "trap" "yes")
2705 (set_attr "round_suffix" "normal")
2706 (set_attr "trap_suffix" "u_su_sui")])
2708 (define_insn "*muldf_ext2"
2709 [(set (match_operand:DF 0 "register_operand" "=f")
2710 (mult:DF (float_extend:DF
2711 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2713 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2714 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2715 "mul%-%/ %R1,%R2,%0"
2716 [(set_attr "type" "fmul")
2717 (set_attr "trap" "yes")
2718 (set_attr "round_suffix" "normal")
2719 (set_attr "trap_suffix" "u_su_sui")])
2721 (define_expand "multf3"
2722 [(use (match_operand 0 "register_operand" ""))
2723 (use (match_operand 1 "general_operand" ""))
2724 (use (match_operand 2 "general_operand" ""))]
2725 "TARGET_HAS_XFLOATING_LIBS"
2726 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2728 (define_insn "*subsf3_ieee"
2729 [(set (match_operand:SF 0 "register_operand" "=&f")
2730 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2731 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2732 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2733 "sub%,%/ %R1,%R2,%0"
2734 [(set_attr "type" "fadd")
2735 (set_attr "trap" "yes")
2736 (set_attr "round_suffix" "normal")
2737 (set_attr "trap_suffix" "u_su_sui")])
2739 (define_insn "subsf3"
2740 [(set (match_operand:SF 0 "register_operand" "=f")
2741 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2742 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2744 "sub%,%/ %R1,%R2,%0"
2745 [(set_attr "type" "fadd")
2746 (set_attr "trap" "yes")
2747 (set_attr "round_suffix" "normal")
2748 (set_attr "trap_suffix" "u_su_sui")])
2750 (define_insn "*subdf3_ieee"
2751 [(set (match_operand:DF 0 "register_operand" "=&f")
2752 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2753 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2754 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2755 "sub%-%/ %R1,%R2,%0"
2756 [(set_attr "type" "fadd")
2757 (set_attr "trap" "yes")
2758 (set_attr "round_suffix" "normal")
2759 (set_attr "trap_suffix" "u_su_sui")])
2761 (define_insn "subdf3"
2762 [(set (match_operand:DF 0 "register_operand" "=f")
2763 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2764 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2766 "sub%-%/ %R1,%R2,%0"
2767 [(set_attr "type" "fadd")
2768 (set_attr "trap" "yes")
2769 (set_attr "round_suffix" "normal")
2770 (set_attr "trap_suffix" "u_su_sui")])
2772 (define_insn "*subdf_ext1"
2773 [(set (match_operand:DF 0 "register_operand" "=f")
2774 (minus:DF (float_extend:DF
2775 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2776 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2777 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2778 "sub%-%/ %R1,%R2,%0"
2779 [(set_attr "type" "fadd")
2780 (set_attr "trap" "yes")
2781 (set_attr "round_suffix" "normal")
2782 (set_attr "trap_suffix" "u_su_sui")])
2784 (define_insn "*subdf_ext2"
2785 [(set (match_operand:DF 0 "register_operand" "=f")
2786 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2788 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2789 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2790 "sub%-%/ %R1,%R2,%0"
2791 [(set_attr "type" "fadd")
2792 (set_attr "trap" "yes")
2793 (set_attr "round_suffix" "normal")
2794 (set_attr "trap_suffix" "u_su_sui")])
2796 (define_insn "*subdf_ext3"
2797 [(set (match_operand:DF 0 "register_operand" "=f")
2798 (minus:DF (float_extend:DF
2799 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2801 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2802 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2803 "sub%-%/ %R1,%R2,%0"
2804 [(set_attr "type" "fadd")
2805 (set_attr "trap" "yes")
2806 (set_attr "round_suffix" "normal")
2807 (set_attr "trap_suffix" "u_su_sui")])
2809 (define_expand "subtf3"
2810 [(use (match_operand 0 "register_operand" ""))
2811 (use (match_operand 1 "general_operand" ""))
2812 (use (match_operand 2 "general_operand" ""))]
2813 "TARGET_HAS_XFLOATING_LIBS"
2814 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2816 (define_insn "*sqrtsf2_ieee"
2817 [(set (match_operand:SF 0 "register_operand" "=&f")
2818 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2819 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2821 [(set_attr "type" "fsqrt")
2822 (set_attr "opsize" "si")
2823 (set_attr "trap" "yes")
2824 (set_attr "round_suffix" "normal")
2825 (set_attr "trap_suffix" "u_su_sui")])
2827 (define_insn "sqrtsf2"
2828 [(set (match_operand:SF 0 "register_operand" "=f")
2829 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2830 "TARGET_FP && TARGET_FIX"
2832 [(set_attr "type" "fsqrt")
2833 (set_attr "opsize" "si")
2834 (set_attr "trap" "yes")
2835 (set_attr "round_suffix" "normal")
2836 (set_attr "trap_suffix" "u_su_sui")])
2838 (define_insn "*sqrtdf2_ieee"
2839 [(set (match_operand:DF 0 "register_operand" "=&f")
2840 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2841 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2843 [(set_attr "type" "fsqrt")
2844 (set_attr "trap" "yes")
2845 (set_attr "round_suffix" "normal")
2846 (set_attr "trap_suffix" "u_su_sui")])
2848 (define_insn "sqrtdf2"
2849 [(set (match_operand:DF 0 "register_operand" "=f")
2850 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2851 "TARGET_FP && TARGET_FIX"
2853 [(set_attr "type" "fsqrt")
2854 (set_attr "trap" "yes")
2855 (set_attr "round_suffix" "normal")
2856 (set_attr "trap_suffix" "u_su_sui")])
2858 ;; Next are all the integer comparisons, and conditional moves and branches
2859 ;; and some of the related define_expand's and define_split's.
2861 (define_insn "*setcc_internal"
2862 [(set (match_operand 0 "register_operand" "=r")
2863 (match_operator 1 "alpha_comparison_operator"
2864 [(match_operand:DI 2 "register_operand" "r")
2865 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2866 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2867 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2868 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2870 [(set_attr "type" "icmp")])
2872 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2873 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2875 (define_insn "*setcc_swapped_internal"
2876 [(set (match_operand 0 "register_operand" "=r")
2877 (match_operator 1 "alpha_swapped_comparison_operator"
2878 [(match_operand:DI 2 "register_operand" "r")
2879 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2880 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2881 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2882 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2884 [(set_attr "type" "icmp")])
2886 ;; Use match_operator rather than ne directly so that we can match
2887 ;; multiple integer modes.
2888 (define_insn "*setne_internal"
2889 [(set (match_operand 0 "register_operand" "=r")
2890 (match_operator 1 "signed_comparison_operator"
2891 [(match_operand:DI 2 "register_operand" "r")
2893 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2894 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2895 && GET_CODE (operands[1]) == NE
2896 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2898 [(set_attr "type" "icmp")])
2900 ;; The mode folding trick can't be used with const_int operands, since
2901 ;; reload needs to know the proper mode.
2903 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2904 ;; in order to create more pairs of constants. As long as we're allowing
2905 ;; two constants at the same time, and will have to reload one of them...
2907 (define_insn "*movqicc_internal"
2908 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2910 (match_operator 2 "signed_comparison_operator"
2911 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2912 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2913 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2914 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2915 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2921 [(set_attr "type" "icmov")])
2923 (define_insn "*movhicc_internal"
2924 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2926 (match_operator 2 "signed_comparison_operator"
2927 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2928 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2929 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2930 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2931 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2937 [(set_attr "type" "icmov")])
2939 (define_insn "*movsicc_internal"
2940 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2942 (match_operator 2 "signed_comparison_operator"
2943 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2944 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2945 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2946 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2947 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2953 [(set_attr "type" "icmov")])
2955 (define_insn "*movdicc_internal"
2956 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2958 (match_operator 2 "signed_comparison_operator"
2959 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2960 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2961 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2962 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2963 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2969 [(set_attr "type" "icmov")])
2971 (define_insn "*movqicc_lbc"
2972 [(set (match_operand:QI 0 "register_operand" "=r,r")
2974 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2978 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2979 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2984 [(set_attr "type" "icmov")])
2986 (define_insn "*movhicc_lbc"
2987 [(set (match_operand:HI 0 "register_operand" "=r,r")
2989 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2993 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2994 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2999 [(set_attr "type" "icmov")])
3001 (define_insn "*movsicc_lbc"
3002 [(set (match_operand:SI 0 "register_operand" "=r,r")
3004 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3008 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3009 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3014 [(set_attr "type" "icmov")])
3016 (define_insn "*movdicc_lbc"
3017 [(set (match_operand:DI 0 "register_operand" "=r,r")
3019 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3023 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3024 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3029 [(set_attr "type" "icmov")])
3031 (define_insn "*movqicc_lbs"
3032 [(set (match_operand:QI 0 "register_operand" "=r,r")
3034 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3038 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3039 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3044 [(set_attr "type" "icmov")])
3046 (define_insn "*movhicc_lbs"
3047 [(set (match_operand:HI 0 "register_operand" "=r,r")
3049 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3053 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3054 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3059 [(set_attr "type" "icmov")])
3061 (define_insn "*movsicc_lbs"
3062 [(set (match_operand:SI 0 "register_operand" "=r,r")
3064 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3068 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3069 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3074 [(set_attr "type" "icmov")])
3076 (define_insn "*movdicc_lbs"
3077 [(set (match_operand:DI 0 "register_operand" "=r,r")
3079 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3083 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3084 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3089 [(set_attr "type" "icmov")])
3091 ;; For ABS, we have two choices, depending on whether the input and output
3092 ;; registers are the same or not.
3093 (define_expand "absdi2"
3094 [(set (match_operand:DI 0 "register_operand" "")
3095 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3098 if (rtx_equal_p (operands[0], operands[1]))
3099 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3101 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3105 (define_expand "absdi2_same"
3106 [(set (match_operand:DI 1 "register_operand" "")
3107 (neg:DI (match_operand:DI 0 "register_operand" "")))
3109 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3115 (define_expand "absdi2_diff"
3116 [(set (match_operand:DI 0 "register_operand" "")
3117 (neg:DI (match_operand:DI 1 "register_operand" "")))
3119 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3126 [(set (match_operand:DI 0 "register_operand" "")
3127 (abs:DI (match_dup 0)))
3128 (clobber (match_operand:DI 1 "register_operand" ""))]
3130 [(set (match_dup 1) (neg:DI (match_dup 0)))
3131 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3132 (match_dup 0) (match_dup 1)))]
3136 [(set (match_operand:DI 0 "register_operand" "")
3137 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3138 "! rtx_equal_p (operands[0], operands[1])"
3139 [(set (match_dup 0) (neg:DI (match_dup 1)))
3140 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3141 (match_dup 0) (match_dup 1)))]
3145 [(set (match_operand:DI 0 "register_operand" "")
3146 (neg:DI (abs:DI (match_dup 0))))
3147 (clobber (match_operand:DI 1 "register_operand" ""))]
3149 [(set (match_dup 1) (neg:DI (match_dup 0)))
3150 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3151 (match_dup 0) (match_dup 1)))]
3155 [(set (match_operand:DI 0 "register_operand" "")
3156 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3157 "! rtx_equal_p (operands[0], operands[1])"
3158 [(set (match_dup 0) (neg:DI (match_dup 1)))
3159 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3160 (match_dup 0) (match_dup 1)))]
3163 (define_insn "sminqi3"
3164 [(set (match_operand:QI 0 "register_operand" "=r")
3165 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3166 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3169 [(set_attr "type" "mvi")])
3171 (define_insn "uminqi3"
3172 [(set (match_operand:QI 0 "register_operand" "=r")
3173 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3174 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3177 [(set_attr "type" "mvi")])
3179 (define_insn "smaxqi3"
3180 [(set (match_operand:QI 0 "register_operand" "=r")
3181 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3182 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3185 [(set_attr "type" "mvi")])
3187 (define_insn "umaxqi3"
3188 [(set (match_operand:QI 0 "register_operand" "=r")
3189 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3190 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3193 [(set_attr "type" "mvi")])
3195 (define_insn "sminhi3"
3196 [(set (match_operand:HI 0 "register_operand" "=r")
3197 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3198 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3201 [(set_attr "type" "mvi")])
3203 (define_insn "uminhi3"
3204 [(set (match_operand:HI 0 "register_operand" "=r")
3205 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3206 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3209 [(set_attr "type" "mvi")])
3211 (define_insn "smaxhi3"
3212 [(set (match_operand:HI 0 "register_operand" "=r")
3213 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3214 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3217 [(set_attr "type" "mvi")])
3219 (define_insn "umaxhi3"
3220 [(set (match_operand:HI 0 "register_operand" "=r")
3221 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3222 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3225 [(set_attr "type" "mvi")])
3227 (define_expand "smaxdi3"
3229 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3230 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3231 (set (match_operand:DI 0 "register_operand" "")
3232 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3233 (match_dup 1) (match_dup 2)))]
3235 { operands[3] = gen_reg_rtx (DImode); })
3238 [(set (match_operand:DI 0 "register_operand" "")
3239 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3240 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3241 (clobber (match_operand:DI 3 "register_operand" ""))]
3242 "operands[2] != const0_rtx"
3243 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3244 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3245 (match_dup 1) (match_dup 2)))]
3248 (define_insn "*smax_const0"
3249 [(set (match_operand:DI 0 "register_operand" "=r")
3250 (smax:DI (match_operand:DI 1 "register_operand" "0")
3254 [(set_attr "type" "icmov")])
3256 (define_expand "smindi3"
3258 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3259 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3260 (set (match_operand:DI 0 "register_operand" "")
3261 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3262 (match_dup 1) (match_dup 2)))]
3264 { operands[3] = gen_reg_rtx (DImode); })
3267 [(set (match_operand:DI 0 "register_operand" "")
3268 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3269 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3270 (clobber (match_operand:DI 3 "register_operand" ""))]
3271 "operands[2] != const0_rtx"
3272 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3273 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3274 (match_dup 1) (match_dup 2)))]
3277 (define_insn "*smin_const0"
3278 [(set (match_operand:DI 0 "register_operand" "=r")
3279 (smin:DI (match_operand:DI 1 "register_operand" "0")
3283 [(set_attr "type" "icmov")])
3285 (define_expand "umaxdi3"
3287 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3288 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3289 (set (match_operand:DI 0 "register_operand" "")
3290 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3291 (match_dup 1) (match_dup 2)))]
3293 "operands[3] = gen_reg_rtx (DImode);")
3296 [(set (match_operand:DI 0 "register_operand" "")
3297 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3298 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3299 (clobber (match_operand:DI 3 "register_operand" ""))]
3300 "operands[2] != const0_rtx"
3301 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3302 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3303 (match_dup 1) (match_dup 2)))]
3306 (define_expand "umindi3"
3308 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3309 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3310 (set (match_operand:DI 0 "register_operand" "")
3311 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3312 (match_dup 1) (match_dup 2)))]
3314 "operands[3] = gen_reg_rtx (DImode);")
3317 [(set (match_operand:DI 0 "register_operand" "")
3318 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3319 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3320 (clobber (match_operand:DI 3 "register_operand" ""))]
3321 "operands[2] != const0_rtx"
3322 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3323 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3324 (match_dup 1) (match_dup 2)))]
3327 (define_insn "*bcc_normal"
3330 (match_operator 1 "signed_comparison_operator"
3331 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3333 (label_ref (match_operand 0 "" ""))
3337 [(set_attr "type" "ibr")])
3339 (define_insn "*bcc_reverse"
3342 (match_operator 1 "signed_comparison_operator"
3343 [(match_operand:DI 2 "register_operand" "r")
3347 (label_ref (match_operand 0 "" ""))))]
3350 [(set_attr "type" "ibr")])
3352 (define_insn "*blbs_normal"
3355 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3359 (label_ref (match_operand 0 "" ""))
3363 [(set_attr "type" "ibr")])
3365 (define_insn "*blbc_normal"
3368 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3372 (label_ref (match_operand 0 "" ""))
3376 [(set_attr "type" "ibr")])
3382 (match_operator 1 "comparison_operator"
3383 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3385 (match_operand:DI 3 "const_int_operand" ""))
3387 (label_ref (match_operand 0 "" ""))
3389 (clobber (match_operand:DI 4 "register_operand" ""))])]
3390 "INTVAL (operands[3]) != 0"
3392 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3394 (if_then_else (match_op_dup 1
3395 [(zero_extract:DI (match_dup 4)
3399 (label_ref (match_dup 0))
3403 ;; The following are the corresponding floating-point insns. Recall
3404 ;; we need to have variants that expand the arguments from SFmode
3407 (define_insn "*cmpdf_ieee"
3408 [(set (match_operand:DF 0 "register_operand" "=&f")
3409 (match_operator:DF 1 "alpha_fp_comparison_operator"
3410 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3411 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3412 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3413 "cmp%-%C1%/ %R2,%R3,%0"
3414 [(set_attr "type" "fadd")
3415 (set_attr "trap" "yes")
3416 (set_attr "trap_suffix" "su")])
3418 (define_insn "*cmpdf_internal"
3419 [(set (match_operand:DF 0 "register_operand" "=f")
3420 (match_operator:DF 1 "alpha_fp_comparison_operator"
3421 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3422 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3423 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3424 "cmp%-%C1%/ %R2,%R3,%0"
3425 [(set_attr "type" "fadd")
3426 (set_attr "trap" "yes")
3427 (set_attr "trap_suffix" "su")])
3429 (define_insn "*cmpdf_ieee_ext1"
3430 [(set (match_operand:DF 0 "register_operand" "=&f")
3431 (match_operator:DF 1 "alpha_fp_comparison_operator"
3433 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3434 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3435 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3436 "cmp%-%C1%/ %R2,%R3,%0"
3437 [(set_attr "type" "fadd")
3438 (set_attr "trap" "yes")
3439 (set_attr "trap_suffix" "su")])
3441 (define_insn "*cmpdf_ext1"
3442 [(set (match_operand:DF 0 "register_operand" "=f")
3443 (match_operator:DF 1 "alpha_fp_comparison_operator"
3445 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3446 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3447 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3448 "cmp%-%C1%/ %R2,%R3,%0"
3449 [(set_attr "type" "fadd")
3450 (set_attr "trap" "yes")
3451 (set_attr "trap_suffix" "su")])
3453 (define_insn "*cmpdf_ieee_ext2"
3454 [(set (match_operand:DF 0 "register_operand" "=&f")
3455 (match_operator:DF 1 "alpha_fp_comparison_operator"
3456 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3458 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3459 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3460 "cmp%-%C1%/ %R2,%R3,%0"
3461 [(set_attr "type" "fadd")
3462 (set_attr "trap" "yes")
3463 (set_attr "trap_suffix" "su")])
3465 (define_insn "*cmpdf_ext2"
3466 [(set (match_operand:DF 0 "register_operand" "=f")
3467 (match_operator:DF 1 "alpha_fp_comparison_operator"
3468 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3470 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3471 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3472 "cmp%-%C1%/ %R2,%R3,%0"
3473 [(set_attr "type" "fadd")
3474 (set_attr "trap" "yes")
3475 (set_attr "trap_suffix" "su")])
3477 (define_insn "*cmpdf_ieee_ext3"
3478 [(set (match_operand:DF 0 "register_operand" "=&f")
3479 (match_operator:DF 1 "alpha_fp_comparison_operator"
3481 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3483 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3484 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3485 "cmp%-%C1%/ %R2,%R3,%0"
3486 [(set_attr "type" "fadd")
3487 (set_attr "trap" "yes")
3488 (set_attr "trap_suffix" "su")])
3490 (define_insn "*cmpdf_ext3"
3491 [(set (match_operand:DF 0 "register_operand" "=f")
3492 (match_operator:DF 1 "alpha_fp_comparison_operator"
3494 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3496 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3497 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3498 "cmp%-%C1%/ %R2,%R3,%0"
3499 [(set_attr "type" "fadd")
3500 (set_attr "trap" "yes")
3501 (set_attr "trap_suffix" "su")])
3503 (define_insn "*movdfcc_internal"
3504 [(set (match_operand:DF 0 "register_operand" "=f,f")
3506 (match_operator 3 "signed_comparison_operator"
3507 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3508 (match_operand:DF 2 "const0_operand" "G,G")])
3509 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3510 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3514 fcmov%D3 %R4,%R5,%0"
3515 [(set_attr "type" "fcmov")])
3517 (define_insn "*movsfcc_internal"
3518 [(set (match_operand:SF 0 "register_operand" "=f,f")
3520 (match_operator 3 "signed_comparison_operator"
3521 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3522 (match_operand:DF 2 "const0_operand" "G,G")])
3523 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3524 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3528 fcmov%D3 %R4,%R5,%0"
3529 [(set_attr "type" "fcmov")])
3531 (define_insn "*movdfcc_ext1"
3532 [(set (match_operand:DF 0 "register_operand" "=f,f")
3534 (match_operator 3 "signed_comparison_operator"
3535 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3536 (match_operand:DF 2 "const0_operand" "G,G")])
3537 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3538 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3542 fcmov%D3 %R4,%R5,%0"
3543 [(set_attr "type" "fcmov")])
3545 (define_insn "*movdfcc_ext2"
3546 [(set (match_operand:DF 0 "register_operand" "=f,f")
3548 (match_operator 3 "signed_comparison_operator"
3550 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3551 (match_operand:DF 2 "const0_operand" "G,G")])
3552 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3553 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3557 fcmov%D3 %R4,%R5,%0"
3558 [(set_attr "type" "fcmov")])
3560 (define_insn "*movdfcc_ext3"
3561 [(set (match_operand:SF 0 "register_operand" "=f,f")
3563 (match_operator 3 "signed_comparison_operator"
3565 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3566 (match_operand:DF 2 "const0_operand" "G,G")])
3567 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3568 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3572 fcmov%D3 %R4,%R5,%0"
3573 [(set_attr "type" "fcmov")])
3575 (define_insn "*movdfcc_ext4"
3576 [(set (match_operand:DF 0 "register_operand" "=f,f")
3578 (match_operator 3 "signed_comparison_operator"
3580 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3581 (match_operand:DF 2 "const0_operand" "G,G")])
3582 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3583 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3587 fcmov%D3 %R4,%R5,%0"
3588 [(set_attr "type" "fcmov")])
3590 (define_expand "maxdf3"
3592 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3593 (match_operand:DF 2 "reg_or_0_operand" "")))
3594 (set (match_operand:DF 0 "register_operand" "")
3595 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3596 (match_dup 1) (match_dup 2)))]
3599 operands[3] = gen_reg_rtx (DFmode);
3600 operands[4] = CONST0_RTX (DFmode);
3603 (define_expand "mindf3"
3605 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3606 (match_operand:DF 2 "reg_or_0_operand" "")))
3607 (set (match_operand:DF 0 "register_operand" "")
3608 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3609 (match_dup 1) (match_dup 2)))]
3612 operands[3] = gen_reg_rtx (DFmode);
3613 operands[4] = CONST0_RTX (DFmode);
3616 (define_expand "maxsf3"
3618 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3619 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3620 (set (match_operand:SF 0 "register_operand" "")
3621 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3622 (match_dup 1) (match_dup 2)))]
3625 operands[3] = gen_reg_rtx (DFmode);
3626 operands[4] = CONST0_RTX (DFmode);
3629 (define_expand "minsf3"
3631 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3632 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3633 (set (match_operand:SF 0 "register_operand" "")
3634 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3635 (match_dup 1) (match_dup 2)))]
3638 operands[3] = gen_reg_rtx (DFmode);
3639 operands[4] = CONST0_RTX (DFmode);
3642 (define_insn "*fbcc_normal"
3645 (match_operator 1 "signed_comparison_operator"
3646 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3647 (match_operand:DF 3 "const0_operand" "G")])
3648 (label_ref (match_operand 0 "" ""))
3652 [(set_attr "type" "fbr")])
3654 (define_insn "*fbcc_ext_normal"
3657 (match_operator 1 "signed_comparison_operator"
3659 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3660 (match_operand:DF 3 "const0_operand" "G")])
3661 (label_ref (match_operand 0 "" ""))
3665 [(set_attr "type" "fbr")])
3667 ;; These are the main define_expand's used to make conditional branches
3670 (define_expand "cmpdf"
3671 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3672 (match_operand:DF 1 "reg_or_0_operand" "")))]
3675 alpha_compare.op0 = operands[0];
3676 alpha_compare.op1 = operands[1];
3677 alpha_compare.fp_p = 1;
3681 (define_expand "cmptf"
3682 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3683 (match_operand:TF 1 "general_operand" "")))]
3684 "TARGET_HAS_XFLOATING_LIBS"
3686 alpha_compare.op0 = operands[0];
3687 alpha_compare.op1 = operands[1];
3688 alpha_compare.fp_p = 1;
3692 (define_expand "cmpdi"
3693 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3694 (match_operand:DI 1 "general_operand" "")))]
3697 alpha_compare.op0 = operands[0];
3698 alpha_compare.op1 = operands[1];
3699 alpha_compare.fp_p = 0;
3703 (define_expand "beq"
3705 (if_then_else (match_dup 1)
3706 (label_ref (match_operand 0 "" ""))
3709 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3711 (define_expand "bne"
3713 (if_then_else (match_dup 1)
3714 (label_ref (match_operand 0 "" ""))
3717 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3719 (define_expand "blt"
3721 (if_then_else (match_dup 1)
3722 (label_ref (match_operand 0 "" ""))
3725 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3727 (define_expand "ble"
3729 (if_then_else (match_dup 1)
3730 (label_ref (match_operand 0 "" ""))
3733 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3735 (define_expand "bgt"
3737 (if_then_else (match_dup 1)
3738 (label_ref (match_operand 0 "" ""))
3741 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3743 (define_expand "bge"
3745 (if_then_else (match_dup 1)
3746 (label_ref (match_operand 0 "" ""))
3749 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3751 (define_expand "bltu"
3753 (if_then_else (match_dup 1)
3754 (label_ref (match_operand 0 "" ""))
3757 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3759 (define_expand "bleu"
3761 (if_then_else (match_dup 1)
3762 (label_ref (match_operand 0 "" ""))
3765 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3767 (define_expand "bgtu"
3769 (if_then_else (match_dup 1)
3770 (label_ref (match_operand 0 "" ""))
3773 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3775 (define_expand "bgeu"
3777 (if_then_else (match_dup 1)
3778 (label_ref (match_operand 0 "" ""))
3781 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3783 (define_expand "bunordered"
3785 (if_then_else (match_dup 1)
3786 (label_ref (match_operand 0 "" ""))
3789 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3791 (define_expand "bordered"
3793 (if_then_else (match_dup 1)
3794 (label_ref (match_operand 0 "" ""))
3797 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3799 (define_expand "seq"
3800 [(set (match_operand:DI 0 "register_operand" "")
3803 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3805 (define_expand "sne"
3806 [(set (match_operand:DI 0 "register_operand" "")
3809 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3811 (define_expand "slt"
3812 [(set (match_operand:DI 0 "register_operand" "")
3815 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3817 (define_expand "sle"
3818 [(set (match_operand:DI 0 "register_operand" "")
3821 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3823 (define_expand "sgt"
3824 [(set (match_operand:DI 0 "register_operand" "")
3827 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3829 (define_expand "sge"
3830 [(set (match_operand:DI 0 "register_operand" "")
3833 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3835 (define_expand "sltu"
3836 [(set (match_operand:DI 0 "register_operand" "")
3839 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3841 (define_expand "sleu"
3842 [(set (match_operand:DI 0 "register_operand" "")
3845 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3847 (define_expand "sgtu"
3848 [(set (match_operand:DI 0 "register_operand" "")
3851 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3853 (define_expand "sgeu"
3854 [(set (match_operand:DI 0 "register_operand" "")
3857 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3859 (define_expand "sunordered"
3860 [(set (match_operand:DI 0 "register_operand" "")
3863 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3865 (define_expand "sordered"
3866 [(set (match_operand:DI 0 "register_operand" "")
3869 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3871 ;; These are the main define_expand's used to make conditional moves.
3873 (define_expand "movsicc"
3874 [(set (match_operand:SI 0 "register_operand" "")
3875 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3876 (match_operand:SI 2 "reg_or_8bit_operand" "")
3877 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3880 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3884 (define_expand "movdicc"
3885 [(set (match_operand:DI 0 "register_operand" "")
3886 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3887 (match_operand:DI 2 "reg_or_8bit_operand" "")
3888 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3891 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3895 (define_expand "movsfcc"
3896 [(set (match_operand:SF 0 "register_operand" "")
3897 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3898 (match_operand:SF 2 "reg_or_8bit_operand" "")
3899 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3902 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3906 (define_expand "movdfcc"
3907 [(set (match_operand:DF 0 "register_operand" "")
3908 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3909 (match_operand:DF 2 "reg_or_8bit_operand" "")
3910 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3913 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3917 ;; These define_split definitions are used in cases when comparisons have
3918 ;; not be stated in the correct way and we need to reverse the second
3919 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3920 ;; comparison that tests the result being reversed. We have one define_split
3921 ;; for each use of a comparison. They do not match valid insns and need
3922 ;; not generate valid insns.
3924 ;; We can also handle equality comparisons (and inequality comparisons in
3925 ;; cases where the resulting add cannot overflow) by doing an add followed by
3926 ;; a comparison with zero. This is faster since the addition takes one
3927 ;; less cycle than a compare when feeding into a conditional move.
3928 ;; For this case, we also have an SImode pattern since we can merge the add
3929 ;; and sign extend and the order doesn't matter.
3931 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3932 ;; operation could have been generated.
3935 [(set (match_operand:DI 0 "register_operand" "")
3937 (match_operator 1 "comparison_operator"
3938 [(match_operand:DI 2 "reg_or_0_operand" "")
3939 (match_operand:DI 3 "reg_or_cint_operand" "")])
3940 (match_operand:DI 4 "reg_or_cint_operand" "")
3941 (match_operand:DI 5 "reg_or_cint_operand" "")))
3942 (clobber (match_operand:DI 6 "register_operand" ""))]
3943 "operands[3] != const0_rtx"
3944 [(set (match_dup 6) (match_dup 7))
3946 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3948 enum rtx_code code = GET_CODE (operands[1]);
3949 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3951 /* If we are comparing for equality with a constant and that constant
3952 appears in the arm when the register equals the constant, use the
3953 register since that is more likely to match (and to produce better code
3956 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3957 && rtx_equal_p (operands[4], operands[3]))
3958 operands[4] = operands[2];
3960 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3961 && rtx_equal_p (operands[5], operands[3]))
3962 operands[5] = operands[2];
3964 if (code == NE || code == EQ
3965 || (extended_count (operands[2], DImode, unsignedp) >= 1
3966 && extended_count (operands[3], DImode, unsignedp) >= 1))
3968 if (GET_CODE (operands[3]) == CONST_INT)
3969 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3970 GEN_INT (- INTVAL (operands[3])));
3972 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3974 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3977 else if (code == EQ || code == LE || code == LT
3978 || code == LEU || code == LTU)
3980 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3981 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3985 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3986 operands[2], operands[3]);
3987 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3992 [(set (match_operand:DI 0 "register_operand" "")
3994 (match_operator 1 "comparison_operator"
3995 [(match_operand:SI 2 "reg_or_0_operand" "")
3996 (match_operand:SI 3 "reg_or_cint_operand" "")])
3997 (match_operand:DI 4 "reg_or_8bit_operand" "")
3998 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3999 (clobber (match_operand:DI 6 "register_operand" ""))]
4000 "operands[3] != const0_rtx
4001 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4002 [(set (match_dup 6) (match_dup 7))
4004 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4006 enum rtx_code code = GET_CODE (operands[1]);
4007 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4010 if ((code != NE && code != EQ
4011 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4012 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4015 if (GET_CODE (operands[3]) == CONST_INT)
4016 tem = gen_rtx_PLUS (SImode, operands[2],
4017 GEN_INT (- INTVAL (operands[3])));
4019 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4021 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4022 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4023 operands[6], const0_rtx);
4029 (match_operator 1 "comparison_operator"
4030 [(match_operand:DI 2 "reg_or_0_operand" "")
4031 (match_operand:DI 3 "reg_or_cint_operand" "")])
4032 (label_ref (match_operand 0 "" ""))
4034 (clobber (match_operand:DI 4 "register_operand" ""))]
4035 "operands[3] != const0_rtx"
4036 [(set (match_dup 4) (match_dup 5))
4037 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4039 enum rtx_code code = GET_CODE (operands[1]);
4040 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4042 if (code == NE || code == EQ
4043 || (extended_count (operands[2], DImode, unsignedp) >= 1
4044 && extended_count (operands[3], DImode, unsignedp) >= 1))
4046 if (GET_CODE (operands[3]) == CONST_INT)
4047 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4048 GEN_INT (- INTVAL (operands[3])));
4050 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4052 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4055 else if (code == EQ || code == LE || code == LT
4056 || code == LEU || code == LTU)
4058 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4059 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4063 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4064 operands[2], operands[3]);
4065 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4072 (match_operator 1 "comparison_operator"
4073 [(match_operand:SI 2 "reg_or_0_operand" "")
4074 (match_operand:SI 3 "const_int_operand" "")])
4075 (label_ref (match_operand 0 "" ""))
4077 (clobber (match_operand:DI 4 "register_operand" ""))]
4078 "operands[3] != const0_rtx
4079 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4080 [(set (match_dup 4) (match_dup 5))
4081 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4085 if (GET_CODE (operands[3]) == CONST_INT)
4086 tem = gen_rtx_PLUS (SImode, operands[2],
4087 GEN_INT (- INTVAL (operands[3])));
4089 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4091 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4092 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4093 operands[4], const0_rtx);
4096 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4097 ;; This eliminates one, and sometimes two, insns when the AND can be done
4100 [(set (match_operand:DI 0 "register_operand" "")
4101 (match_operator:DI 1 "comparison_operator"
4102 [(match_operand:DI 2 "register_operand" "")
4103 (match_operand:DI 3 "const_int_operand" "")]))
4104 (clobber (match_operand:DI 4 "register_operand" ""))]
4105 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4106 && (GET_CODE (operands[1]) == GTU
4107 || GET_CODE (operands[1]) == LEU
4108 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4109 && extended_count (operands[2], DImode, 1) > 0))"
4110 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4111 (set (match_dup 0) (match_dup 6))]
4113 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4114 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4115 || GET_CODE (operands[1]) == GT)
4117 DImode, operands[4], const0_rtx);
4120 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4123 [(set (match_operand 0 "register_operand" "")
4124 (if_then_else (match_operator 1 "signed_comparison_operator"
4125 [(match_operand:DI 2 "reg_or_0_operand" "")
4127 (match_operand 3 "const_int_operand" "")
4128 (match_operand 4 "const_int_operand" "")))]
4132 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4133 operands[2], operands[3], operands[4]))
4139 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4140 ;; Oh well, we match it in movcc, so it must be partially our fault.
4142 [(set (match_operand 0 "register_operand" "")
4143 (if_then_else (match_operator 1 "signed_comparison_operator"
4145 (match_operand:DI 2 "reg_or_0_operand" "")])
4146 (match_operand 3 "const_int_operand" "")
4147 (match_operand 4 "const_int_operand" "")))]
4151 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4152 operands[0], operands[2], operands[3],
4159 (define_insn_and_split "*cmp_sadd_di"
4160 [(set (match_operand:DI 0 "register_operand" "=r")
4161 (plus:DI (if_then_else:DI
4162 (match_operator 1 "alpha_zero_comparison_operator"
4163 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4165 (match_operand:DI 3 "const48_operand" "I")
4167 (match_operand:DI 4 "sext_add_operand" "rIO")))
4168 (clobber (match_scratch:DI 5 "=r"))]
4171 "! no_new_pseudos || reload_completed"
4173 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4175 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4178 if (! no_new_pseudos)
4179 operands[5] = gen_reg_rtx (DImode);
4180 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4181 operands[5] = operands[0];
4184 (define_insn_and_split "*cmp_sadd_si"
4185 [(set (match_operand:SI 0 "register_operand" "=r")
4186 (plus:SI (if_then_else:SI
4187 (match_operator 1 "alpha_zero_comparison_operator"
4188 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4190 (match_operand:SI 3 "const48_operand" "I")
4192 (match_operand:SI 4 "sext_add_operand" "rIO")))
4193 (clobber (match_scratch:SI 5 "=r"))]
4196 "! no_new_pseudos || reload_completed"
4198 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4200 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4203 if (! no_new_pseudos)
4204 operands[5] = gen_reg_rtx (DImode);
4205 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4206 operands[5] = operands[0];
4209 (define_insn_and_split "*cmp_sadd_sidi"
4210 [(set (match_operand:DI 0 "register_operand" "=r")
4212 (plus:SI (if_then_else:SI
4213 (match_operator 1 "alpha_zero_comparison_operator"
4214 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4216 (match_operand:SI 3 "const48_operand" "I")
4218 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4219 (clobber (match_scratch:SI 5 "=r"))]
4222 "! no_new_pseudos || reload_completed"
4224 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4226 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4229 if (! no_new_pseudos)
4230 operands[5] = gen_reg_rtx (DImode);
4231 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4232 operands[5] = operands[0];
4235 (define_insn_and_split "*cmp_ssub_di"
4236 [(set (match_operand:DI 0 "register_operand" "=r")
4237 (minus:DI (if_then_else:DI
4238 (match_operator 1 "alpha_zero_comparison_operator"
4239 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4241 (match_operand:DI 3 "const48_operand" "I")
4243 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4244 (clobber (match_scratch:DI 5 "=r"))]
4247 "! no_new_pseudos || reload_completed"
4249 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4251 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4254 if (! no_new_pseudos)
4255 operands[5] = gen_reg_rtx (DImode);
4256 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4257 operands[5] = operands[0];
4260 (define_insn_and_split "*cmp_ssub_si"
4261 [(set (match_operand:SI 0 "register_operand" "=r")
4262 (minus:SI (if_then_else:SI
4263 (match_operator 1 "alpha_zero_comparison_operator"
4264 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4266 (match_operand:SI 3 "const48_operand" "I")
4268 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4269 (clobber (match_scratch:SI 5 "=r"))]
4272 "! no_new_pseudos || reload_completed"
4274 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4276 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4279 if (! no_new_pseudos)
4280 operands[5] = gen_reg_rtx (DImode);
4281 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4282 operands[5] = operands[0];
4285 (define_insn_and_split "*cmp_ssub_sidi"
4286 [(set (match_operand:DI 0 "register_operand" "=r")
4288 (minus:SI (if_then_else:SI
4289 (match_operator 1 "alpha_zero_comparison_operator"
4290 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4292 (match_operand:SI 3 "const48_operand" "I")
4294 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4295 (clobber (match_scratch:SI 5 "=r"))]
4298 "! no_new_pseudos || reload_completed"
4300 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4302 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4305 if (! no_new_pseudos)
4306 operands[5] = gen_reg_rtx (DImode);
4307 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4308 operands[5] = operands[0];
4311 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4312 ;; work differently, so we have different patterns for each.
4314 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4315 ;; call. The CIW contains information about arguments passed in registers
4316 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4317 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4318 ;; in the presence of inlining since the CIWs for calls performed by the
4319 ;; inlined function must be stored in the SSIB of the function it is inlined
4320 ;; into as well. We encode the CIW in an unspec and append it to the list
4321 ;; of the CIWs for the current function only when the instruction for loading
4322 ;; $25 is generated.
4324 (define_expand "call"
4325 [(use (match_operand:DI 0 "" ""))
4326 (use (match_operand 1 "" ""))
4327 (use (match_operand 2 "" ""))
4328 (use (match_operand 3 "" ""))]
4331 if (TARGET_ABI_WINDOWS_NT)
4332 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4333 else if (TARGET_ABI_OPEN_VMS)
4334 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4335 else if (TARGET_ABI_UNICOSMK)
4336 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4338 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4342 (define_expand "sibcall"
4343 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4344 (match_operand 1 "" ""))
4345 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4348 if (GET_CODE (operands[0]) != MEM)
4350 operands[0] = XEXP (operands[0], 0);
4353 (define_expand "call_osf"
4354 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4355 (match_operand 1 "" ""))
4357 (clobber (reg:DI 26))])]
4360 if (GET_CODE (operands[0]) != MEM)
4363 operands[0] = XEXP (operands[0], 0);
4364 if (! call_operand (operands[0], Pmode))
4365 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4368 (define_expand "call_nt"
4369 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4370 (match_operand 1 "" ""))
4371 (clobber (reg:DI 26))])]
4374 if (GET_CODE (operands[0]) != MEM)
4377 operands[0] = XEXP (operands[0], 0);
4378 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4379 operands[0] = force_reg (DImode, operands[0]);
4382 ;; Calls on Unicos/Mk are always indirect.
4383 ;; op 0: symbol ref for called function
4384 ;; op 1: CIW for $25 represented by an unspec
4386 (define_expand "call_umk"
4387 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4388 (match_operand 1 "" ""))
4390 (clobber (reg:DI 26))])]
4393 if (GET_CODE (operands[0]) != MEM)
4396 /* Always load the address of the called function into a register;
4397 load the CIW in $25. */
4399 operands[0] = XEXP (operands[0], 0);
4400 if (GET_CODE (operands[0]) != REG)
4401 operands[0] = force_reg (DImode, operands[0]);
4403 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4407 ;; call openvms/alpha
4408 ;; op 0: symbol ref for called function
4409 ;; op 1: next_arg_reg (argument information value for R25)
4411 (define_expand "call_vms"
4412 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4413 (match_operand 1 "" ""))
4417 (clobber (reg:DI 27))])]
4420 if (GET_CODE (operands[0]) != MEM)
4423 operands[0] = XEXP (operands[0], 0);
4425 /* Always load AI with argument information, then handle symbolic and
4426 indirect call differently. Load RA and set operands[2] to PV in
4429 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4430 if (GET_CODE (operands[0]) == SYMBOL_REF)
4432 alpha_need_linkage (XSTR (operands[0], 0), 0);
4434 operands[2] = const0_rtx;
4438 emit_move_insn (gen_rtx_REG (Pmode, 26),
4439 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4440 operands[2] = operands[0];
4445 (define_expand "call_value"
4446 [(use (match_operand 0 "" ""))
4447 (use (match_operand:DI 1 "" ""))
4448 (use (match_operand 2 "" ""))
4449 (use (match_operand 3 "" ""))
4450 (use (match_operand 4 "" ""))]
4453 if (TARGET_ABI_WINDOWS_NT)
4454 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4455 else if (TARGET_ABI_OPEN_VMS)
4456 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4458 else if (TARGET_ABI_UNICOSMK)
4459 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4462 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4467 (define_expand "sibcall_value"
4468 [(parallel [(set (match_operand 0 "" "")
4469 (call (mem:DI (match_operand 1 "" ""))
4470 (match_operand 2 "" "")))
4471 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4474 if (GET_CODE (operands[1]) != MEM)
4476 operands[1] = XEXP (operands[1], 0);
4479 (define_expand "call_value_osf"
4480 [(parallel [(set (match_operand 0 "" "")
4481 (call (mem:DI (match_operand 1 "" ""))
4482 (match_operand 2 "" "")))
4484 (clobber (reg:DI 26))])]
4487 if (GET_CODE (operands[1]) != MEM)
4490 operands[1] = XEXP (operands[1], 0);
4491 if (! call_operand (operands[1], Pmode))
4492 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4495 (define_expand "call_value_nt"
4496 [(parallel [(set (match_operand 0 "" "")
4497 (call (mem:DI (match_operand 1 "" ""))
4498 (match_operand 2 "" "")))
4499 (clobber (reg:DI 26))])]
4502 if (GET_CODE (operands[1]) != MEM)
4505 operands[1] = XEXP (operands[1], 0);
4506 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4507 operands[1] = force_reg (DImode, operands[1]);
4510 (define_expand "call_value_vms"
4511 [(parallel [(set (match_operand 0 "" "")
4512 (call (mem:DI (match_operand:DI 1 "" ""))
4513 (match_operand 2 "" "")))
4517 (clobber (reg:DI 27))])]
4520 if (GET_CODE (operands[1]) != MEM)
4523 operands[1] = XEXP (operands[1], 0);
4525 /* Always load AI with argument information, then handle symbolic and
4526 indirect call differently. Load RA and set operands[3] to PV in
4529 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4530 if (GET_CODE (operands[1]) == SYMBOL_REF)
4532 alpha_need_linkage (XSTR (operands[1], 0), 0);
4534 operands[3] = const0_rtx;
4538 emit_move_insn (gen_rtx_REG (Pmode, 26),
4539 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4540 operands[3] = operands[1];
4544 (define_expand "call_value_umk"
4545 [(parallel [(set (match_operand 0 "" "")
4546 (call (mem:DI (match_operand 1 "" ""))
4547 (match_operand 2 "" "")))
4549 (clobber (reg:DI 26))])]
4552 if (GET_CODE (operands[1]) != MEM)
4555 operands[1] = XEXP (operands[1], 0);
4556 if (GET_CODE (operands[1]) != REG)
4557 operands[1] = force_reg (DImode, operands[1]);
4559 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4562 (define_insn "*call_osf_1_er"
4563 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4564 (match_operand 1 "" ""))
4566 (clobber (reg:DI 26))]
4567 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4569 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4571 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4572 [(set_attr "type" "jsr")
4573 (set_attr "length" "12,*,16")])
4575 ;; We must use peep2 instead of a split because we need accurate life
4576 ;; information for $gp. Consider the case of { bar(); while (1); }.
4578 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4579 (match_operand 1 "" ""))
4581 (clobber (reg:DI 26))])]
4582 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4583 && ! current_file_function_operand (operands[0], Pmode)
4584 && peep2_regno_dead_p (1, 29)"
4585 [(parallel [(call (mem:DI (match_dup 2))
4587 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4588 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4590 (use (match_dup 3))])]
4592 if (CONSTANT_P (operands[0]))
4594 operands[2] = gen_rtx_REG (Pmode, 27);
4595 operands[3] = GEN_INT (alpha_next_sequence_number++);
4596 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4597 operands[0], operands[3]));
4601 operands[2] = operands[0];
4602 operands[0] = const0_rtx;
4603 operands[3] = const0_rtx;
4608 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4609 (match_operand 1 "" ""))
4611 (clobber (reg:DI 26))])]
4612 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4613 && ! current_file_function_operand (operands[0], Pmode)
4614 && ! peep2_regno_dead_p (1, 29)"
4615 [(parallel [(call (mem:DI (match_dup 2))
4617 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4618 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4620 (use (match_dup 4))])
4622 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4624 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4626 if (CONSTANT_P (operands[0]))
4628 operands[2] = gen_rtx_REG (Pmode, 27);
4629 operands[4] = GEN_INT (alpha_next_sequence_number++);
4630 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4631 operands[0], operands[4]));
4635 operands[2] = operands[0];
4636 operands[0] = const0_rtx;
4637 operands[4] = const0_rtx;
4639 operands[3] = GEN_INT (alpha_next_sequence_number++);
4642 ;; We add a blockage unspec_volatile to prevent insns from moving down
4643 ;; from above the call to in between the call and the ldah gpdisp.
4645 (define_insn "*call_osf_2_er"
4646 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4647 (match_operand 1 "" ""))
4648 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4649 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4650 (use (match_operand 2 "" ""))
4651 (use (match_operand 3 "const_int_operand" ""))]
4652 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4653 "jsr $26,(%0),%2%J3"
4654 [(set_attr "type" "jsr")])
4656 (define_insn "*call_osf_1_noreturn"
4657 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4658 (match_operand 1 "" ""))
4660 (clobber (reg:DI 26))]
4661 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4662 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4667 [(set_attr "type" "jsr")
4668 (set_attr "length" "*,*,8")])
4670 (define_insn "*call_osf_1"
4671 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4672 (match_operand 1 "" ""))
4674 (clobber (reg:DI 26))]
4675 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4677 jsr $26,($27),0\;ldgp $29,0($26)
4679 jsr $26,%0\;ldgp $29,0($26)"
4680 [(set_attr "type" "jsr")
4681 (set_attr "length" "12,*,16")])
4683 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4684 ;; doesn't do what we want.
4685 (define_insn "*sibcall_osf_1_er"
4686 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4687 (match_operand 1 "" ""))
4688 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4689 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4692 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4693 [(set_attr "type" "jsr")
4694 (set_attr "length" "*,8")])
4696 (define_insn "*sibcall_osf_1"
4697 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4698 (match_operand 1 "" ""))
4699 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4700 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4703 lda $27,%0\;jmp $31,($27),%0"
4704 [(set_attr "type" "jsr")
4705 (set_attr "length" "*,8")])
4707 (define_insn "*call_nt_1"
4708 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4709 (match_operand 1 "" ""))
4710 (clobber (reg:DI 26))]
4711 "TARGET_ABI_WINDOWS_NT"
4716 [(set_attr "type" "jsr")
4717 (set_attr "length" "*,*,12")])
4719 ; GAS relies on the order and position of instructions output below in order
4720 ; to generate relocs for VMS link to potentially optimize the call.
4721 ; Please do not molest.
4722 (define_insn "*call_vms_1"
4723 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4724 (match_operand 1 "" ""))
4725 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4728 (clobber (reg:DI 27))]
4729 "TARGET_ABI_OPEN_VMS"
4731 switch (which_alternative)
4734 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4736 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4737 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4738 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4743 [(set_attr "type" "jsr")
4744 (set_attr "length" "12,16")])
4746 (define_insn "*call_umk_1"
4747 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4748 (match_operand 1 "" ""))
4750 (clobber (reg:DI 26))]
4751 "TARGET_ABI_UNICOSMK"
4753 [(set_attr "type" "jsr")])
4755 ;; Call subroutine returning any type.
4757 (define_expand "untyped_call"
4758 [(parallel [(call (match_operand 0 "" "")
4760 (match_operand 1 "" "")
4761 (match_operand 2 "" "")])]
4766 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4768 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4770 rtx set = XVECEXP (operands[2], 0, i);
4771 emit_move_insn (SET_DEST (set), SET_SRC (set));
4774 /* The optimizer does not know that the call sets the function value
4775 registers we stored in the result block. We avoid problems by
4776 claiming that all hard registers are used and clobbered at this
4778 emit_insn (gen_blockage ());
4783 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4784 ;; all of memory. This blocks insns from being moved across this point.
4786 (define_insn "blockage"
4787 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4790 [(set_attr "length" "0")
4791 (set_attr "type" "none")])
4795 (label_ref (match_operand 0 "" "")))]
4798 [(set_attr "type" "ibr")])
4800 (define_expand "return"
4805 (define_insn "*return_internal"
4809 [(set_attr "type" "ibr")])
4811 (define_insn "indirect_jump"
4812 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4815 [(set_attr "type" "ibr")])
4817 (define_expand "tablejump"
4818 [(parallel [(set (pc)
4819 (match_operand 0 "register_operand" ""))
4820 (use (label_ref:DI (match_operand 1 "" "")))])]
4823 if (TARGET_ABI_WINDOWS_NT)
4825 rtx dest = gen_reg_rtx (DImode);
4826 emit_insn (gen_extendsidi2 (dest, operands[0]));
4829 else if (TARGET_ABI_OSF)
4831 rtx dest = gen_reg_rtx (DImode);
4832 emit_insn (gen_extendsidi2 (dest, operands[0]));
4833 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4838 (define_insn "*tablejump_osf_nt_internal"
4840 (match_operand:DI 0 "register_operand" "r"))
4841 (use (label_ref:DI (match_operand 1 "" "")))]
4842 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4843 && alpha_tablejump_addr_vec (insn)"
4845 operands[2] = alpha_tablejump_best_label (insn);
4846 return "jmp $31,(%0),%2";
4848 [(set_attr "type" "ibr")])
4850 (define_insn "*tablejump_internal"
4852 (match_operand:DI 0 "register_operand" "r"))
4853 (use (label_ref (match_operand 1 "" "")))]
4856 [(set_attr "type" "ibr")])
4858 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4859 ;; want to have to include pal.h in our .s file.
4861 ;; Technically the type for call_pal is jsr, but we use that for determining
4862 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4865 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4868 [(set_attr "type" "callpal")])
4870 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4871 ;; NT does not document anything at 0x81 -- presumably it would generate
4872 ;; the equivalent of SIGILL, but this isn't that important.
4873 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4875 [(trap_if (const_int 1) (const_int 0))]
4876 "!TARGET_ABI_WINDOWS_NT"
4878 [(set_attr "type" "callpal")])
4880 ;; For userland, we load the thread pointer from the TCB.
4881 ;; For the kernel, we load the per-cpu private value.
4883 (define_insn "load_tp"
4884 [(set (match_operand:DI 0 "register_operand" "=v")
4885 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4888 if (TARGET_TLS_KERNEL)
4889 return "call_pal 0x32";
4891 return "call_pal 0x9e";
4893 [(set_attr "type" "callpal")])
4895 ;; For completeness, and possibly a __builtin function, here's how to
4896 ;; set the thread pointer. Since we don't describe enough of this
4897 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4898 ;; not much point in creating an R16_REG register class.
4900 (define_expand "set_tp"
4901 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4902 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4906 (define_insn "*set_tp"
4907 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4910 if (TARGET_TLS_KERNEL)
4911 return "call_pal 0x31";
4913 return "call_pal 0x9f";
4915 [(set_attr "type" "callpal")])
4917 ;; Finally, we have the basic data motion insns. The byte and word insns
4918 ;; are done via define_expand. Start with the floating-point insns, since
4919 ;; they are simpler.
4921 (define_insn "*movsf_nofix"
4922 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4923 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4924 "TARGET_FPREGS && ! TARGET_FIX
4925 && (register_operand (operands[0], SFmode)
4926 || reg_or_0_operand (operands[1], SFmode))"
4934 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4936 (define_insn "*movsf_fix"
4937 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4938 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4939 "TARGET_FPREGS && TARGET_FIX
4940 && (register_operand (operands[0], SFmode)
4941 || reg_or_0_operand (operands[1], SFmode))"
4951 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4953 (define_insn "*movsf_nofp"
4954 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4955 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4957 && (register_operand (operands[0], SFmode)
4958 || reg_or_0_operand (operands[1], SFmode))"
4963 [(set_attr "type" "ilog,ild,ist")])
4965 (define_insn "*movdf_nofix"
4966 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4967 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4968 "TARGET_FPREGS && ! TARGET_FIX
4969 && (register_operand (operands[0], DFmode)
4970 || reg_or_0_operand (operands[1], DFmode))"
4978 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4980 (define_insn "*movdf_fix"
4981 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4982 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4983 "TARGET_FPREGS && TARGET_FIX
4984 && (register_operand (operands[0], DFmode)
4985 || reg_or_0_operand (operands[1], DFmode))"
4995 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4997 (define_insn "*movdf_nofp"
4998 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4999 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5001 && (register_operand (operands[0], DFmode)
5002 || reg_or_0_operand (operands[1], DFmode))"
5007 [(set_attr "type" "ilog,ild,ist")])
5009 ;; Subregs suck for register allocation. Pretend we can move TFmode
5010 ;; data between general registers until after reload.
5012 (define_insn_and_split "*movtf_internal"
5013 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5014 (match_operand:TF 1 "input_operand" "roG,rG"))]
5015 "register_operand (operands[0], TFmode)
5016 || reg_or_0_operand (operands[1], TFmode)"
5019 [(set (match_dup 0) (match_dup 2))
5020 (set (match_dup 1) (match_dup 3))]
5022 alpha_split_tfmode_pair (operands);
5023 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5026 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5027 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5031 (define_expand "movsf"
5032 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5033 (match_operand:SF 1 "general_operand" ""))]
5036 if (GET_CODE (operands[0]) == MEM
5037 && ! reg_or_0_operand (operands[1], SFmode))
5038 operands[1] = force_reg (SFmode, operands[1]);
5041 (define_expand "movdf"
5042 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5043 (match_operand:DF 1 "general_operand" ""))]
5046 if (GET_CODE (operands[0]) == MEM
5047 && ! reg_or_0_operand (operands[1], DFmode))
5048 operands[1] = force_reg (DFmode, operands[1]);
5051 (define_expand "movtf"
5052 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5053 (match_operand:TF 1 "general_operand" ""))]
5056 if (GET_CODE (operands[0]) == MEM
5057 && ! reg_or_0_operand (operands[1], TFmode))
5058 operands[1] = force_reg (TFmode, operands[1]);
5061 (define_insn "*movsi_nofix"
5062 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5063 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5064 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5065 && (register_operand (operands[0], SImode)
5066 || reg_or_0_operand (operands[1], SImode))"
5076 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5078 (define_insn "*movsi_fix"
5079 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5080 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5081 "TARGET_ABI_OSF && TARGET_FIX
5082 && (register_operand (operands[0], SImode)
5083 || reg_or_0_operand (operands[1], SImode))"
5095 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5097 (define_insn "*movsi_nt_vms_nofix"
5098 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5099 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5100 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5102 && (register_operand (operands[0], SImode)
5103 || reg_or_0_operand (operands[1], SImode))"
5114 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5116 (define_insn "*movsi_nt_vms_fix"
5117 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5118 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5119 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5121 && (register_operand (operands[0], SImode)
5122 || reg_or_0_operand (operands[1], SImode))"
5135 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5137 (define_insn "*movhi_nobwx"
5138 [(set (match_operand:HI 0 "register_operand" "=r,r")
5139 (match_operand:HI 1 "input_operand" "rJ,n"))]
5141 && (register_operand (operands[0], HImode)
5142 || register_operand (operands[1], HImode))"
5146 [(set_attr "type" "ilog,iadd")])
5148 (define_insn "*movhi_bwx"
5149 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5150 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5152 && (register_operand (operands[0], HImode)
5153 || reg_or_0_operand (operands[1], HImode))"
5159 [(set_attr "type" "ilog,iadd,ild,ist")])
5161 (define_insn "*movqi_nobwx"
5162 [(set (match_operand:QI 0 "register_operand" "=r,r")
5163 (match_operand:QI 1 "input_operand" "rJ,n"))]
5165 && (register_operand (operands[0], QImode)
5166 || register_operand (operands[1], QImode))"
5170 [(set_attr "type" "ilog,iadd")])
5172 (define_insn "*movqi_bwx"
5173 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5174 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5176 && (register_operand (operands[0], QImode)
5177 || reg_or_0_operand (operands[1], QImode))"
5183 [(set_attr "type" "ilog,iadd,ild,ist")])
5185 ;; We do two major things here: handle mem->mem and construct long
5188 (define_expand "movsi"
5189 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5190 (match_operand:SI 1 "general_operand" ""))]
5193 if (alpha_expand_mov (SImode, operands))
5197 ;; Split a load of a large constant into the appropriate two-insn
5201 [(set (match_operand:SI 0 "register_operand" "")
5202 (match_operand:SI 1 "const_int_operand" ""))]
5203 "! add_operand (operands[1], SImode)"
5204 [(set (match_dup 0) (match_dup 2))
5205 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5208 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5210 if (tem == operands[0])
5216 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5217 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5218 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5219 ;; notes and update LABEL_NUSES because this is not done automatically.
5220 ;; Labels may be incorrectly deleted if we don't do this.
5222 ;; Describing what the individual instructions do correctly is too complicated
5223 ;; so use UNSPECs for each of the three parts of an address.
5226 [(set (match_operand:DI 0 "register_operand" "")
5227 (match_operand:DI 1 "symbolic_operand" ""))]
5228 "TARGET_ABI_UNICOSMK && reload_completed"
5231 rtx insn1, insn2, insn3;
5233 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5234 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5235 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5236 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5237 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5239 if (GET_CODE (operands[1]) == LABEL_REF)
5243 label = XEXP (operands[1], 0);
5244 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5246 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5248 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5250 LABEL_NUSES (label) += 3;
5255 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5257 (define_insn "umk_laum"
5258 [(set (match_operand:DI 0 "register_operand" "=r")
5259 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5261 "TARGET_ABI_UNICOSMK"
5263 [(set_attr "type" "iadd")])
5265 (define_insn "umk_lalm"
5266 [(set (match_operand:DI 0 "register_operand" "=r")
5267 (plus:DI (match_operand:DI 1 "register_operand" "r")
5268 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5270 "TARGET_ABI_UNICOSMK"
5272 [(set_attr "type" "iadd")])
5274 (define_insn "umk_lal"
5275 [(set (match_operand:DI 0 "register_operand" "=r")
5276 (plus:DI (match_operand:DI 1 "register_operand" "r")
5277 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5279 "TARGET_ABI_UNICOSMK"
5281 [(set_attr "type" "iadd")])
5283 ;; Add a new call information word to the current function's list of CIWs
5284 ;; and load its index into $25. Doing it here ensures that the CIW will be
5285 ;; associated with the correct function even in the presence of inlining.
5287 (define_insn "*umk_load_ciw"
5289 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5290 "TARGET_ABI_UNICOSMK"
5292 operands[0] = unicosmk_add_call_info_word (operands[0]);
5293 return "lda $25,%0";
5295 [(set_attr "type" "iadd")])
5297 (define_insn "*movdi_er_low_l"
5298 [(set (match_operand:DI 0 "register_operand" "=r")
5299 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5300 (match_operand:DI 2 "local_symbolic_operand" "")))]
5301 "TARGET_EXPLICIT_RELOCS"
5303 if (true_regnum (operands[1]) == 29)
5304 return "lda %0,%2(%1)\t\t!gprel";
5306 return "lda %0,%2(%1)\t\t!gprellow";
5310 [(set (match_operand:DI 0 "register_operand" "")
5311 (match_operand:DI 1 "small_symbolic_operand" ""))]
5312 "TARGET_EXPLICIT_RELOCS && reload_completed"
5314 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5315 "operands[2] = pic_offset_table_rtx;")
5318 [(set (match_operand:DI 0 "register_operand" "")
5319 (match_operand:DI 1 "local_symbolic_operand" ""))]
5320 "TARGET_EXPLICIT_RELOCS && reload_completed"
5322 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5324 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5325 "operands[2] = pic_offset_table_rtx;")
5328 [(match_operand 0 "some_small_symbolic_operand" "")]
5329 "TARGET_EXPLICIT_RELOCS && reload_completed"
5331 "operands[0] = split_small_symbolic_operand (operands[0]);")
5333 (define_insn "movdi_er_high_g"
5334 [(set (match_operand:DI 0 "register_operand" "=r")
5335 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5336 (match_operand:DI 2 "global_symbolic_operand" "")
5337 (match_operand 3 "const_int_operand" "")]
5339 "TARGET_EXPLICIT_RELOCS"
5341 if (INTVAL (operands[3]) == 0)
5342 return "ldq %0,%2(%1)\t\t!literal";
5344 return "ldq %0,%2(%1)\t\t!literal!%3";
5346 [(set_attr "type" "ldsym")])
5349 [(set (match_operand:DI 0 "register_operand" "")
5350 (match_operand:DI 1 "global_symbolic_operand" ""))]
5351 "TARGET_EXPLICIT_RELOCS && reload_completed"
5353 (unspec:DI [(match_dup 2)
5355 (const_int 0)] UNSPEC_LITERAL))]
5356 "operands[2] = pic_offset_table_rtx;")
5358 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5359 ;; compiled at the end of compilation. In the meantime, someone can
5360 ;; re-encode-section-info on some symbol changing it e.g. from global
5361 ;; to local-not-small. If this happens, we'd have emitted a plain
5362 ;; load rather than a high+losum load and not recognize the insn.
5364 ;; So if rtl inlining is in effect, we delay the global/not-global
5365 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5367 (define_insn_and_split "movdi_er_maybe_g"
5368 [(set (match_operand:DI 0 "register_operand" "=r")
5369 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5371 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5374 [(set (match_dup 0) (match_dup 1))]
5376 if (local_symbolic_operand (operands[1], Pmode)
5377 && !small_symbolic_operand (operands[1], Pmode))
5379 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5382 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5383 if (reload_completed)
5384 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5385 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5387 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5388 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5393 (define_insn "movdi_er_tlsgd"
5394 [(set (match_operand:DI 0 "register_operand" "=r")
5395 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5396 (match_operand:DI 2 "symbolic_operand" "")
5397 (match_operand 3 "const_int_operand" "")]
5401 if (INTVAL (operands[3]) == 0)
5402 return "lda %0,%2(%1)\t\t!tlsgd";
5404 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5407 (define_insn "movdi_er_tlsldm"
5408 [(set (match_operand:DI 0 "register_operand" "=r")
5409 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5410 (match_operand 2 "const_int_operand" "")]
5414 if (INTVAL (operands[2]) == 0)
5415 return "lda %0,%&(%1)\t\t!tlsldm";
5417 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5420 (define_insn "*movdi_er_gotdtp"
5421 [(set (match_operand:DI 0 "register_operand" "=r")
5422 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5423 (match_operand:DI 2 "symbolic_operand" "")]
5426 "ldq %0,%2(%1)\t\t!gotdtprel"
5427 [(set_attr "type" "ild")])
5430 [(set (match_operand:DI 0 "register_operand" "")
5431 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5432 "HAVE_AS_TLS && reload_completed"
5434 (unspec:DI [(match_dup 2)
5435 (match_dup 1)] UNSPEC_DTPREL))]
5437 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5438 operands[2] = pic_offset_table_rtx;
5441 (define_insn "*movdi_er_gottp"
5442 [(set (match_operand:DI 0 "register_operand" "=r")
5443 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5444 (match_operand:DI 2 "symbolic_operand" "")]
5447 "ldq %0,%2(%1)\t\t!gottprel"
5448 [(set_attr "type" "ild")])
5451 [(set (match_operand:DI 0 "register_operand" "")
5452 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5453 "HAVE_AS_TLS && reload_completed"
5455 (unspec:DI [(match_dup 2)
5456 (match_dup 1)] UNSPEC_TPREL))]
5458 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5459 operands[2] = pic_offset_table_rtx;
5462 (define_insn "*movdi_er_nofix"
5463 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5464 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5465 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5466 && (register_operand (operands[0], DImode)
5467 || reg_or_0_operand (operands[1], DImode))"
5479 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5481 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5482 ;; have been split up by the rules above but we shouldn't reject the
5483 ;; possibility of them getting through.
5485 (define_insn "*movdi_nofix"
5486 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5487 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5489 && (register_operand (operands[0], DImode)
5490 || reg_or_0_operand (operands[1], DImode))"
5495 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5502 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5503 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5505 (define_insn "*movdi_er_fix"
5506 [(set (match_operand:DI 0 "nonimmediate_operand"
5507 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5508 (match_operand:DI 1 "input_operand"
5509 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5510 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5511 && (register_operand (operands[0], DImode)
5512 || reg_or_0_operand (operands[1], DImode))"
5526 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5528 (define_insn "*movdi_fix"
5529 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5530 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5531 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5532 && (register_operand (operands[0], DImode)
5533 || reg_or_0_operand (operands[1], DImode))"
5546 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5548 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5549 ;; often appears dead to the life analysis code, at which point we
5550 ;; abort for emitting dead prologue instructions. Force this live.
5552 (define_insn "force_movdi"
5553 [(set (match_operand:DI 0 "register_operand" "=r")
5554 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5555 UNSPECV_FORCE_MOV))]
5558 [(set_attr "type" "ilog")])
5560 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5561 ;; memory, and construct long 32-bit constants.
5563 (define_expand "movdi"
5564 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5565 (match_operand:DI 1 "general_operand" ""))]
5568 if (alpha_expand_mov (DImode, operands))
5572 ;; Split a load of a large constant into the appropriate two-insn
5576 [(set (match_operand:DI 0 "register_operand" "")
5577 (match_operand:DI 1 "const_int_operand" ""))]
5578 "! add_operand (operands[1], DImode)"
5579 [(set (match_dup 0) (match_dup 2))
5580 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5583 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5585 if (tem == operands[0])
5591 ;; These are the partial-word cases.
5593 ;; First we have the code to load an aligned word. Operand 0 is the register
5594 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5595 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5596 ;; number of bits within the word that the value is. Operand 3 is an SImode
5597 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5598 ;; same register. It is allowed to conflict with operand 1 as well.
5600 (define_expand "aligned_loadqi"
5601 [(set (match_operand:SI 3 "register_operand" "")
5602 (match_operand:SI 1 "memory_operand" ""))
5603 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5604 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5606 (match_operand:DI 2 "const_int_operand" "")))]
5611 (define_expand "aligned_loadhi"
5612 [(set (match_operand:SI 3 "register_operand" "")
5613 (match_operand:SI 1 "memory_operand" ""))
5614 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5615 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5617 (match_operand:DI 2 "const_int_operand" "")))]
5622 ;; Similar for unaligned loads, where we use the sequence from the
5623 ;; Alpha Architecture manual. We have to distinguish between little-endian
5624 ;; and big-endian systems as the sequences are different.
5626 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5627 ;; operand 3 can overlap the input and output registers.
5629 (define_expand "unaligned_loadqi"
5630 [(use (match_operand:QI 0 "register_operand" ""))
5631 (use (match_operand:DI 1 "address_operand" ""))
5632 (use (match_operand:DI 2 "register_operand" ""))
5633 (use (match_operand:DI 3 "register_operand" ""))]
5636 if (WORDS_BIG_ENDIAN)
5637 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5638 operands[2], operands[3]));
5640 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5641 operands[2], operands[3]));
5645 (define_expand "unaligned_loadqi_le"
5646 [(set (match_operand:DI 2 "register_operand" "")
5647 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5649 (set (match_operand:DI 3 "register_operand" "")
5651 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5652 (zero_extract:DI (match_dup 2)
5654 (ashift:DI (match_dup 3) (const_int 3))))]
5655 "! WORDS_BIG_ENDIAN"
5658 (define_expand "unaligned_loadqi_be"
5659 [(set (match_operand:DI 2 "register_operand" "")
5660 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5662 (set (match_operand:DI 3 "register_operand" "")
5664 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5665 (zero_extract:DI (match_dup 2)
5669 (ashift:DI (match_dup 3) (const_int 3)))))]
5673 (define_expand "unaligned_loadhi"
5674 [(use (match_operand:QI 0 "register_operand" ""))
5675 (use (match_operand:DI 1 "address_operand" ""))
5676 (use (match_operand:DI 2 "register_operand" ""))
5677 (use (match_operand:DI 3 "register_operand" ""))]
5680 if (WORDS_BIG_ENDIAN)
5681 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5682 operands[2], operands[3]));
5684 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5685 operands[2], operands[3]));
5689 (define_expand "unaligned_loadhi_le"
5690 [(set (match_operand:DI 2 "register_operand" "")
5691 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5693 (set (match_operand:DI 3 "register_operand" "")
5695 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5696 (zero_extract:DI (match_dup 2)
5698 (ashift:DI (match_dup 3) (const_int 3))))]
5699 "! WORDS_BIG_ENDIAN"
5702 (define_expand "unaligned_loadhi_be"
5703 [(set (match_operand:DI 2 "register_operand" "")
5704 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5706 (set (match_operand:DI 3 "register_operand" "")
5707 (plus:DI (match_dup 1) (const_int 1)))
5708 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5709 (zero_extract:DI (match_dup 2)
5713 (ashift:DI (match_dup 3) (const_int 3)))))]
5717 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5718 ;; aligned SImode MEM. Operand 1 is the register containing the
5719 ;; byte or word to store. Operand 2 is the number of bits within the word that
5720 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5722 (define_expand "aligned_store"
5723 [(set (match_operand:SI 3 "register_operand" "")
5724 (match_operand:SI 0 "memory_operand" ""))
5725 (set (subreg:DI (match_dup 3) 0)
5726 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5727 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5728 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5729 (match_operand:DI 2 "const_int_operand" "")))
5730 (set (subreg:DI (match_dup 4) 0)
5731 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5732 (set (match_dup 0) (match_dup 4))]
5735 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5736 << INTVAL (operands[2])));
5739 ;; For the unaligned byte and halfword cases, we use code similar to that
5740 ;; in the ;; Architecture book, but reordered to lower the number of registers
5741 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5742 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5743 ;; be the same temporary, if desired. If the address is in a register,
5744 ;; operand 2 can be that register.
5746 (define_expand "unaligned_storeqi"
5747 [(use (match_operand:DI 0 "address_operand" ""))
5748 (use (match_operand:QI 1 "register_operand" ""))
5749 (use (match_operand:DI 2 "register_operand" ""))
5750 (use (match_operand:DI 3 "register_operand" ""))
5751 (use (match_operand:DI 4 "register_operand" ""))]
5754 if (WORDS_BIG_ENDIAN)
5755 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5756 operands[2], operands[3],
5759 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5760 operands[2], operands[3],
5765 (define_expand "unaligned_storeqi_le"
5766 [(set (match_operand:DI 3 "register_operand" "")
5767 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5769 (set (match_operand:DI 2 "register_operand" "")
5772 (and:DI (not:DI (ashift:DI (const_int 255)
5773 (ashift:DI (match_dup 2) (const_int 3))))
5775 (set (match_operand:DI 4 "register_operand" "")
5776 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5777 (ashift:DI (match_dup 2) (const_int 3))))
5778 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5779 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5781 "! WORDS_BIG_ENDIAN"
5784 (define_expand "unaligned_storeqi_be"
5785 [(set (match_operand:DI 3 "register_operand" "")
5786 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5788 (set (match_operand:DI 2 "register_operand" "")
5791 (and:DI (not:DI (ashift:DI (const_int 255)
5792 (minus:DI (const_int 56)
5793 (ashift:DI (match_dup 2) (const_int 3)))))
5795 (set (match_operand:DI 4 "register_operand" "")
5796 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5797 (minus:DI (const_int 56)
5798 (ashift:DI (match_dup 2) (const_int 3)))))
5799 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5800 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5805 (define_expand "unaligned_storehi"
5806 [(use (match_operand:DI 0 "address_operand" ""))
5807 (use (match_operand:HI 1 "register_operand" ""))
5808 (use (match_operand:DI 2 "register_operand" ""))
5809 (use (match_operand:DI 3 "register_operand" ""))
5810 (use (match_operand:DI 4 "register_operand" ""))]
5813 if (WORDS_BIG_ENDIAN)
5814 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5815 operands[2], operands[3],
5818 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5819 operands[2], operands[3],
5824 (define_expand "unaligned_storehi_le"
5825 [(set (match_operand:DI 3 "register_operand" "")
5826 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5828 (set (match_operand:DI 2 "register_operand" "")
5831 (and:DI (not:DI (ashift:DI (const_int 65535)
5832 (ashift:DI (match_dup 2) (const_int 3))))
5834 (set (match_operand:DI 4 "register_operand" "")
5835 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5836 (ashift:DI (match_dup 2) (const_int 3))))
5837 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5838 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5840 "! WORDS_BIG_ENDIAN"
5843 (define_expand "unaligned_storehi_be"
5844 [(set (match_operand:DI 3 "register_operand" "")
5845 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5847 (set (match_operand:DI 2 "register_operand" "")
5848 (plus:DI (match_dup 0) (const_int 1)))
5850 (and:DI (not:DI (ashift:DI
5852 (minus:DI (const_int 56)
5853 (ashift:DI (match_dup 2) (const_int 3)))))
5855 (set (match_operand:DI 4 "register_operand" "")
5856 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5857 (minus:DI (const_int 56)
5858 (ashift:DI (match_dup 2) (const_int 3)))))
5859 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5860 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5865 ;; Here are the define_expand's for QI and HI moves that use the above
5866 ;; patterns. We have the normal sets, plus the ones that need scratch
5867 ;; registers for reload.
5869 (define_expand "movqi"
5870 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5871 (match_operand:QI 1 "general_operand" ""))]
5875 ? alpha_expand_mov (QImode, operands)
5876 : alpha_expand_mov_nobwx (QImode, operands))
5880 (define_expand "movhi"
5881 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5882 (match_operand:HI 1 "general_operand" ""))]
5886 ? alpha_expand_mov (HImode, operands)
5887 : alpha_expand_mov_nobwx (HImode, operands))
5891 ;; Here are the versions for reload. Note that in the unaligned cases
5892 ;; we know that the operand must not be a pseudo-register because stack
5893 ;; slots are always aligned references.
5895 (define_expand "reload_inqi"
5896 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5897 (match_operand:QI 1 "any_memory_operand" "m")
5898 (match_operand:TI 2 "register_operand" "=&r")])]
5903 if (GET_CODE (operands[1]) != MEM)
5906 if (aligned_memory_operand (operands[1], QImode))
5908 seq = gen_reload_inqi_help (operands[0], operands[1],
5909 gen_rtx_REG (SImode, REGNO (operands[2])));
5915 /* It is possible that one of the registers we got for operands[2]
5916 might coincide with that of operands[0] (which is why we made
5917 it TImode). Pick the other one to use as our scratch. */
5918 if (REGNO (operands[0]) == REGNO (operands[2]))
5919 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5921 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5923 addr = get_unaligned_address (operands[1], 0);
5924 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5925 gen_rtx_REG (DImode, REGNO (operands[0])));
5926 alpha_set_memflags (seq, operands[1]);
5932 (define_expand "reload_inhi"
5933 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5934 (match_operand:HI 1 "any_memory_operand" "m")
5935 (match_operand:TI 2 "register_operand" "=&r")])]
5940 if (GET_CODE (operands[1]) != MEM)
5943 if (aligned_memory_operand (operands[1], HImode))
5945 seq = gen_reload_inhi_help (operands[0], operands[1],
5946 gen_rtx_REG (SImode, REGNO (operands[2])));
5952 /* It is possible that one of the registers we got for operands[2]
5953 might coincide with that of operands[0] (which is why we made
5954 it TImode). Pick the other one to use as our scratch. */
5955 if (REGNO (operands[0]) == REGNO (operands[2]))
5956 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5958 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5960 addr = get_unaligned_address (operands[1], 0);
5961 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5962 gen_rtx_REG (DImode, REGNO (operands[0])));
5963 alpha_set_memflags (seq, operands[1]);
5969 (define_expand "reload_outqi"
5970 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5971 (match_operand:QI 1 "register_operand" "r")
5972 (match_operand:TI 2 "register_operand" "=&r")])]
5975 if (GET_CODE (operands[0]) != MEM)
5978 if (aligned_memory_operand (operands[0], QImode))
5980 emit_insn (gen_reload_outqi_help
5981 (operands[0], operands[1],
5982 gen_rtx_REG (SImode, REGNO (operands[2])),
5983 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5987 rtx addr = get_unaligned_address (operands[0], 0);
5988 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5989 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5990 rtx scratch3 = scratch1;
5993 if (GET_CODE (addr) == REG)
5996 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5997 scratch2, scratch3);
5998 alpha_set_memflags (seq, operands[0]);
6004 (define_expand "reload_outhi"
6005 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6006 (match_operand:HI 1 "register_operand" "r")
6007 (match_operand:TI 2 "register_operand" "=&r")])]
6010 if (GET_CODE (operands[0]) != MEM)
6013 if (aligned_memory_operand (operands[0], HImode))
6015 emit_insn (gen_reload_outhi_help
6016 (operands[0], operands[1],
6017 gen_rtx_REG (SImode, REGNO (operands[2])),
6018 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6022 rtx addr = get_unaligned_address (operands[0], 0);
6023 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6024 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6025 rtx scratch3 = scratch1;
6028 if (GET_CODE (addr) == REG)
6031 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6032 scratch2, scratch3);
6033 alpha_set_memflags (seq, operands[0]);
6039 ;; Helpers for the above. The way reload is structured, we can't
6040 ;; always get a proper address for a stack slot during reload_foo
6041 ;; expansion, so we must delay our address manipulations until after.
6043 (define_insn "reload_inqi_help"
6044 [(set (match_operand:QI 0 "register_operand" "=r")
6045 (match_operand:QI 1 "memory_operand" "m"))
6046 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6047 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6050 (define_insn "reload_inhi_help"
6051 [(set (match_operand:HI 0 "register_operand" "=r")
6052 (match_operand:HI 1 "memory_operand" "m"))
6053 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6054 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6057 (define_insn "reload_outqi_help"
6058 [(set (match_operand:QI 0 "memory_operand" "=m")
6059 (match_operand:QI 1 "register_operand" "r"))
6060 (clobber (match_operand:SI 2 "register_operand" "=r"))
6061 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6062 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6065 (define_insn "reload_outhi_help"
6066 [(set (match_operand:HI 0 "memory_operand" "=m")
6067 (match_operand:HI 1 "register_operand" "r"))
6068 (clobber (match_operand:SI 2 "register_operand" "=r"))
6069 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6070 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6074 [(set (match_operand:QI 0 "register_operand" "")
6075 (match_operand:QI 1 "memory_operand" ""))
6076 (clobber (match_operand:SI 2 "register_operand" ""))]
6077 "! TARGET_BWX && reload_completed"
6080 rtx aligned_mem, bitnum;
6081 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6083 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6089 [(set (match_operand:HI 0 "register_operand" "")
6090 (match_operand:HI 1 "memory_operand" ""))
6091 (clobber (match_operand:SI 2 "register_operand" ""))]
6092 "! TARGET_BWX && reload_completed"
6095 rtx aligned_mem, bitnum;
6096 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6098 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6104 [(set (match_operand:QI 0 "memory_operand" "")
6105 (match_operand:QI 1 "register_operand" ""))
6106 (clobber (match_operand:SI 2 "register_operand" ""))
6107 (clobber (match_operand:SI 3 "register_operand" ""))]
6108 "! TARGET_BWX && reload_completed"
6111 rtx aligned_mem, bitnum;
6112 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6113 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6114 operands[2], operands[3]));
6119 [(set (match_operand:HI 0 "memory_operand" "")
6120 (match_operand:HI 1 "register_operand" ""))
6121 (clobber (match_operand:SI 2 "register_operand" ""))
6122 (clobber (match_operand:SI 3 "register_operand" ""))]
6123 "! TARGET_BWX && reload_completed"
6126 rtx aligned_mem, bitnum;
6127 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6128 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6129 operands[2], operands[3]));
6133 ;; Vector operations
6135 (define_expand "movv8qi"
6136 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
6137 (match_operand:V8QI 1 "general_operand" ""))]
6140 if (alpha_expand_mov (V8QImode, operands))
6144 (define_insn "*movv8qi_fix"
6145 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6146 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6148 && (register_operand (operands[0], V8QImode)
6149 || reg_or_0_operand (operands[1], V8QImode))"
6159 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6161 (define_insn "*movv8qi_nofix"
6162 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6163 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6165 && (register_operand (operands[0], V8QImode)
6166 || reg_or_0_operand (operands[1], V8QImode))"
6174 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6176 (define_expand "movv4hi"
6177 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
6178 (match_operand:V4HI 1 "general_operand" ""))]
6181 if (alpha_expand_mov (V4HImode, operands))
6185 (define_insn "*movv4hi_fix"
6186 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6187 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6189 && (register_operand (operands[0], V4HImode)
6190 || reg_or_0_operand (operands[1], V4HImode))"
6200 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6202 (define_insn "*movv4hi_nofix"
6203 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6204 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6206 && (register_operand (operands[0], V4HImode)
6207 || reg_or_0_operand (operands[1], V4HImode))"
6215 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6217 (define_expand "movv2si"
6218 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
6219 (match_operand:V2SI 1 "general_operand" ""))]
6222 if (alpha_expand_mov (V2SImode, operands))
6226 (define_insn "*movv2si_fix"
6227 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6228 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6230 && (register_operand (operands[0], V2SImode)
6231 || reg_or_0_operand (operands[1], V2SImode))"
6241 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6243 (define_insn "*movv2si_nofix"
6244 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6245 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6247 && (register_operand (operands[0], V2SImode)
6248 || reg_or_0_operand (operands[1], V2SImode))"
6256 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6258 (define_insn "uminv8qi3"
6259 [(set (match_operand:V8QI 0 "register_operand" "=r")
6260 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6261 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6264 [(set_attr "type" "mvi")])
6266 (define_insn "sminv8qi3"
6267 [(set (match_operand:V8QI 0 "register_operand" "=r")
6268 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6269 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6272 [(set_attr "type" "mvi")])
6274 (define_insn "uminv4hi3"
6275 [(set (match_operand:V4HI 0 "register_operand" "=r")
6276 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6277 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6280 [(set_attr "type" "mvi")])
6282 (define_insn "sminv4hi3"
6283 [(set (match_operand:V4HI 0 "register_operand" "=r")
6284 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6285 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6288 [(set_attr "type" "mvi")])
6290 (define_insn "umaxv8qi3"
6291 [(set (match_operand:V8QI 0 "register_operand" "=r")
6292 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6293 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6296 [(set_attr "type" "mvi")])
6298 (define_insn "smaxv8qi3"
6299 [(set (match_operand:V8QI 0 "register_operand" "=r")
6300 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6301 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6304 [(set_attr "type" "mvi")])
6306 (define_insn "umaxv4hi3"
6307 [(set (match_operand:V4HI 0 "register_operand" "=r")
6308 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6309 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6312 [(set_attr "type" "mvi")])
6314 (define_insn "smaxv4hi3"
6315 [(set (match_operand:V4HI 0 "register_operand" "=r")
6316 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6317 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6320 [(set_attr "type" "mvi")])
6322 ;; Bit field extract patterns which use ext[wlq][lh]
6324 (define_expand "extv"
6325 [(set (match_operand:DI 0 "register_operand" "")
6326 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6327 (match_operand:DI 2 "immediate_operand" "")
6328 (match_operand:DI 3 "immediate_operand" "")))]
6333 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6334 if (INTVAL (operands[3]) % 8 != 0
6335 || (INTVAL (operands[2]) != 16
6336 && INTVAL (operands[2]) != 32
6337 && INTVAL (operands[2]) != 64))
6340 /* From mips.md: extract_bit_field doesn't verify that our source
6341 matches the predicate, so we force it to be a MEM here. */
6342 if (GET_CODE (operands[1]) != MEM)
6345 /* The bit number is relative to the mode of operand 1 which is
6346 usually QImode (this might actually be a bug in expmed.c). Note
6347 that the bit number is negative in big-endian mode in this case.
6348 We have to convert that to the offset. */
6349 if (WORDS_BIG_ENDIAN)
6350 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6351 - INTVAL (operands[2]) - INTVAL (operands[3]);
6353 ofs = INTVAL (operands[3]);
6357 alpha_expand_unaligned_load (operands[0], operands[1],
6358 INTVAL (operands[2]) / 8,
6363 (define_expand "extzv"
6364 [(set (match_operand:DI 0 "register_operand" "")
6365 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6366 (match_operand:DI 2 "immediate_operand" "")
6367 (match_operand:DI 3 "immediate_operand" "")))]
6370 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6371 if (INTVAL (operands[3]) % 8 != 0
6372 || (INTVAL (operands[2]) != 8
6373 && INTVAL (operands[2]) != 16
6374 && INTVAL (operands[2]) != 32
6375 && INTVAL (operands[2]) != 64))
6378 if (GET_CODE (operands[1]) == MEM)
6382 /* Fail 8 bit fields, falling back on a simple byte load. */
6383 if (INTVAL (operands[2]) == 8)
6386 /* The bit number is relative to the mode of operand 1 which is
6387 usually QImode (this might actually be a bug in expmed.c). Note
6388 that the bit number is negative in big-endian mode in this case.
6389 We have to convert that to the offset. */
6390 if (WORDS_BIG_ENDIAN)
6391 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6392 - INTVAL (operands[2]) - INTVAL (operands[3]);
6394 ofs = INTVAL (operands[3]);
6398 alpha_expand_unaligned_load (operands[0], operands[1],
6399 INTVAL (operands[2]) / 8,
6405 (define_expand "insv"
6406 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6407 (match_operand:DI 1 "immediate_operand" "")
6408 (match_operand:DI 2 "immediate_operand" ""))
6409 (match_operand:DI 3 "register_operand" ""))]
6414 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6415 if (INTVAL (operands[2]) % 8 != 0
6416 || (INTVAL (operands[1]) != 16
6417 && INTVAL (operands[1]) != 32
6418 && INTVAL (operands[1]) != 64))
6421 /* From mips.md: store_bit_field doesn't verify that our source
6422 matches the predicate, so we force it to be a MEM here. */
6423 if (GET_CODE (operands[0]) != MEM)
6426 /* The bit number is relative to the mode of operand 1 which is
6427 usually QImode (this might actually be a bug in expmed.c). Note
6428 that the bit number is negative in big-endian mode in this case.
6429 We have to convert that to the offset. */
6430 if (WORDS_BIG_ENDIAN)
6431 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6432 - INTVAL (operands[1]) - INTVAL (operands[2]);
6434 ofs = INTVAL (operands[2]);
6438 alpha_expand_unaligned_store (operands[0], operands[3],
6439 INTVAL (operands[1]) / 8, ofs);
6443 ;; Block move/clear, see alpha.c for more details.
6444 ;; Argument 0 is the destination
6445 ;; Argument 1 is the source
6446 ;; Argument 2 is the length
6447 ;; Argument 3 is the alignment
6449 (define_expand "movstrqi"
6450 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6451 (match_operand:BLK 1 "memory_operand" ""))
6452 (use (match_operand:DI 2 "immediate_operand" ""))
6453 (use (match_operand:DI 3 "immediate_operand" ""))])]
6456 if (alpha_expand_block_move (operands))
6462 (define_expand "movstrdi"
6463 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6464 (match_operand:BLK 1 "memory_operand" ""))
6465 (use (match_operand:DI 2 "immediate_operand" ""))
6466 (use (match_operand:DI 3 "immediate_operand" ""))
6468 (clobber (reg:DI 25))
6469 (clobber (reg:DI 16))
6470 (clobber (reg:DI 17))
6471 (clobber (reg:DI 18))
6472 (clobber (reg:DI 19))
6473 (clobber (reg:DI 20))
6474 (clobber (reg:DI 26))
6475 (clobber (reg:DI 27))])]
6476 "TARGET_ABI_OPEN_VMS"
6478 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6479 alpha_need_linkage (XSTR (operands[4], 0), 0);
6482 (define_insn "*movstrdi_1"
6483 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6484 (match_operand:BLK 1 "memory_operand" "m,m"))
6485 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6486 (use (match_operand:DI 3 "immediate_operand" ""))
6487 (use (match_operand:DI 4 "call_operand" "i,i"))
6488 (clobber (reg:DI 25))
6489 (clobber (reg:DI 16))
6490 (clobber (reg:DI 17))
6491 (clobber (reg:DI 18))
6492 (clobber (reg:DI 19))
6493 (clobber (reg:DI 20))
6494 (clobber (reg:DI 26))
6495 (clobber (reg:DI 27))]
6496 "TARGET_ABI_OPEN_VMS"
6498 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6499 switch (which_alternative)
6502 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6504 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6509 [(set_attr "type" "multi")
6510 (set_attr "length" "28")])
6512 (define_expand "clrstrqi"
6513 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6515 (use (match_operand:DI 1 "immediate_operand" ""))
6516 (use (match_operand:DI 2 "immediate_operand" ""))])]
6519 if (alpha_expand_block_clear (operands))
6525 (define_expand "clrstrdi"
6526 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6528 (use (match_operand:DI 1 "immediate_operand" ""))
6529 (use (match_operand:DI 2 "immediate_operand" ""))
6531 (clobber (reg:DI 25))
6532 (clobber (reg:DI 16))
6533 (clobber (reg:DI 17))
6534 (clobber (reg:DI 26))
6535 (clobber (reg:DI 27))])]
6536 "TARGET_ABI_OPEN_VMS"
6538 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6539 alpha_need_linkage (XSTR (operands[3], 0), 0);
6542 (define_insn "*clrstrdi_1"
6543 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6545 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6546 (use (match_operand:DI 2 "immediate_operand" ""))
6547 (use (match_operand:DI 3 "call_operand" "i,i"))
6548 (clobber (reg:DI 25))
6549 (clobber (reg:DI 16))
6550 (clobber (reg:DI 17))
6551 (clobber (reg:DI 26))
6552 (clobber (reg:DI 27))]
6553 "TARGET_ABI_OPEN_VMS"
6555 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6556 switch (which_alternative)
6559 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6561 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6566 [(set_attr "type" "multi")
6567 (set_attr "length" "24")])
6570 ;; Subroutine of stack space allocation. Perform a stack probe.
6571 (define_expand "probe_stack"
6572 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6575 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6576 INTVAL (operands[0])));
6577 MEM_VOLATILE_P (operands[1]) = 1;
6579 operands[0] = const0_rtx;
6582 ;; This is how we allocate stack space. If we are allocating a
6583 ;; constant amount of space and we know it is less than 4096
6584 ;; bytes, we need do nothing.
6586 ;; If it is more than 4096 bytes, we need to probe the stack
6588 (define_expand "allocate_stack"
6590 (plus:DI (reg:DI 30)
6591 (match_operand:DI 1 "reg_or_cint_operand" "")))
6592 (set (match_operand:DI 0 "register_operand" "=r")
6596 if (GET_CODE (operands[1]) == CONST_INT
6597 && INTVAL (operands[1]) < 32768)
6599 if (INTVAL (operands[1]) >= 4096)
6601 /* We do this the same way as in the prologue and generate explicit
6602 probes. Then we update the stack by the constant. */
6606 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6607 while (probed + 8192 < INTVAL (operands[1]))
6608 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6610 if (probed + 4096 < INTVAL (operands[1]))
6611 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6614 operands[1] = GEN_INT (- INTVAL (operands[1]));
6615 operands[2] = virtual_stack_dynamic_rtx;
6620 rtx loop_label = gen_label_rtx ();
6621 rtx want = gen_reg_rtx (Pmode);
6622 rtx tmp = gen_reg_rtx (Pmode);
6625 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6626 force_reg (Pmode, operands[1])));
6627 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6629 if (GET_CODE (operands[1]) != CONST_INT)
6631 out_label = gen_label_rtx ();
6632 emit_insn (gen_cmpdi (want, tmp));
6633 emit_jump_insn (gen_bgeu (out_label));
6636 emit_label (loop_label);
6637 memref = gen_rtx_MEM (DImode, tmp);
6638 MEM_VOLATILE_P (memref) = 1;
6639 emit_move_insn (memref, const0_rtx);
6640 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6641 emit_insn (gen_cmpdi (tmp, want));
6642 emit_jump_insn (gen_bgtu (loop_label));
6644 memref = gen_rtx_MEM (DImode, want);
6645 MEM_VOLATILE_P (memref) = 1;
6646 emit_move_insn (memref, const0_rtx);
6649 emit_label (out_label);
6651 emit_move_insn (stack_pointer_rtx, want);
6652 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6657 ;; This is used by alpha_expand_prolog to do the same thing as above,
6658 ;; except we cannot at that time generate new basic blocks, so we hide
6659 ;; the loop in this one insn.
6661 (define_insn "prologue_stack_probe_loop"
6662 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6663 (match_operand:DI 1 "register_operand" "r")]
6667 operands[2] = gen_label_rtx ();
6668 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6669 CODE_LABEL_NUMBER (operands[2]));
6671 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6673 [(set_attr "length" "16")
6674 (set_attr "type" "multi")])
6676 (define_expand "prologue"
6677 [(clobber (const_int 0))]
6680 alpha_expand_prologue ();
6684 ;; These take care of emitting the ldgp insn in the prologue. This will be
6685 ;; an lda/ldah pair and we want to align them properly. So we have two
6686 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6687 ;; and the second of which emits nothing. However, both are marked as type
6688 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6691 (define_expand "prologue_ldgp"
6693 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6695 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6698 operands[0] = pic_offset_table_rtx;
6699 operands[1] = gen_rtx_REG (Pmode, 27);
6700 operands[2] = (TARGET_EXPLICIT_RELOCS
6701 ? GEN_INT (alpha_next_sequence_number++)
6705 (define_insn "*ldgp_er_1"
6706 [(set (match_operand:DI 0 "register_operand" "=r")
6707 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6708 (match_operand 2 "const_int_operand" "")]
6710 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6711 "ldah %0,0(%1)\t\t!gpdisp!%2")
6713 (define_insn "*ldgp_er_2"
6714 [(set (match_operand:DI 0 "register_operand" "=r")
6715 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6716 (match_operand 2 "const_int_operand" "")]
6718 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6719 "lda %0,0(%1)\t\t!gpdisp!%2")
6721 (define_insn "*prologue_ldgp_er_2"
6722 [(set (match_operand:DI 0 "register_operand" "=r")
6723 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6724 (match_operand 2 "const_int_operand" "")]
6726 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6727 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6729 (define_insn "*prologue_ldgp_1"
6730 [(set (match_operand:DI 0 "register_operand" "=r")
6731 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6732 (match_operand 2 "const_int_operand" "")]
6735 "ldgp %0,0(%1)\n$%~..ng:")
6737 (define_insn "*prologue_ldgp_2"
6738 [(set (match_operand:DI 0 "register_operand" "=r")
6739 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6740 (match_operand 2 "const_int_operand" "")]
6745 ;; The _mcount profiling hook has special calling conventions, and
6746 ;; does not clobber all the registers that a normal call would. So
6747 ;; hide the fact this is a call at all.
6749 (define_insn "prologue_mcount"
6750 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6753 if (TARGET_EXPLICIT_RELOCS)
6754 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6755 cannot be called via the PLT. */
6756 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6758 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6760 [(set_attr "type" "multi")
6761 (set_attr "length" "8")])
6763 (define_insn "init_fp"
6764 [(set (match_operand:DI 0 "register_operand" "=r")
6765 (match_operand:DI 1 "register_operand" "r"))
6766 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6770 (define_expand "epilogue"
6774 alpha_expand_epilogue ();
6777 (define_expand "sibcall_epilogue"
6781 alpha_expand_epilogue ();
6785 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6786 ;; the frame size into a register. We use this pattern to ensure
6787 ;; we get lda instead of addq.
6788 (define_insn "nt_lda"
6789 [(set (match_operand:DI 0 "register_operand" "=r")
6790 (unspec:DI [(match_dup 0)
6791 (match_operand:DI 1 "const_int_operand" "n")]
6796 (define_expand "builtin_longjmp"
6797 [(use (match_operand:DI 0 "register_operand" "r"))]
6800 /* The elements of the buffer are, in order: */
6801 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6802 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6803 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6804 rtx pv = gen_rtx_REG (Pmode, 27);
6806 /* This bit is the same as expand_builtin_longjmp. */
6807 emit_move_insn (hard_frame_pointer_rtx, fp);
6808 emit_move_insn (pv, lab);
6809 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6810 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6811 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6813 /* Load the label we are jumping through into $27 so that we know
6814 where to look for it when we get back to setjmp's function for
6815 restoring the gp. */
6816 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6821 ;; This is effectively a copy of indirect_jump, but constrained such
6822 ;; that register renaming cannot foil our cunning plan with $27.
6823 (define_insn "builtin_longjmp_internal"
6825 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6829 [(set_attr "type" "ibr")])
6831 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6832 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6833 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6834 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6836 (define_insn "*builtin_setjmp_receiver_er_1"
6837 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6838 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6839 "br $27,$LSJ%=\n$LSJ%=:"
6840 [(set_attr "type" "ibr")])
6843 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6844 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6845 && prev_nonnote_insn (insn) == operands[0]"
6849 emit_note (NULL, NOTE_INSN_DELETED);
6853 (define_insn "*builtin_setjmp_receiver_1"
6854 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6856 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6857 [(set_attr "length" "12")
6858 (set_attr "type" "multi")])
6860 (define_expand "builtin_setjmp_receiver_er"
6861 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6863 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6865 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6868 operands[1] = pic_offset_table_rtx;
6869 operands[2] = gen_rtx_REG (Pmode, 27);
6870 operands[3] = GEN_INT (alpha_next_sequence_number++);
6873 (define_expand "builtin_setjmp_receiver"
6874 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6877 if (TARGET_EXPLICIT_RELOCS)
6879 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6884 (define_expand "exception_receiver_er"
6886 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6888 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6891 operands[0] = pic_offset_table_rtx;
6892 operands[1] = gen_rtx_REG (Pmode, 26);
6893 operands[2] = GEN_INT (alpha_next_sequence_number++);
6896 (define_expand "exception_receiver"
6897 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6900 if (TARGET_LD_BUGGY_LDGP)
6901 operands[0] = alpha_gp_save_rtx ();
6902 else if (TARGET_EXPLICIT_RELOCS)
6904 emit_insn (gen_exception_receiver_er ());
6908 operands[0] = const0_rtx;
6911 (define_insn "*exception_receiver_1"
6912 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6913 "! TARGET_LD_BUGGY_LDGP"
6915 [(set_attr "length" "8")
6916 (set_attr "type" "multi")])
6918 (define_insn "*exception_receiver_2"
6919 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6920 "TARGET_LD_BUGGY_LDGP"
6922 [(set_attr "type" "ild")])
6924 (define_expand "nonlocal_goto_receiver"
6925 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6926 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6927 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6929 "TARGET_ABI_OPEN_VMS"
6932 (define_insn "arg_home"
6933 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6948 (clobber (mem:BLK (const_int 0)))
6949 (clobber (reg:DI 24))
6950 (clobber (reg:DI 25))
6951 (clobber (reg:DI 0))]
6952 "TARGET_ABI_OPEN_VMS"
6953 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6954 [(set_attr "length" "16")
6955 (set_attr "type" "multi")])
6957 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6959 (define_expand "umk_mismatch_args"
6960 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6961 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6962 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6963 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6966 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6967 "TARGET_ABI_UNICOSMK"
6969 operands[1] = gen_reg_rtx (DImode);
6970 operands[2] = gen_reg_rtx (DImode);
6971 operands[3] = gen_reg_rtx (DImode);
6974 (define_insn "arg_home_umk"
6975 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6990 (clobber (mem:BLK (const_int 0)))
6992 (clobber (reg:DI 22))
6993 (clobber (reg:DI 23))
6994 (clobber (reg:DI 24))
6995 (clobber (reg:DI 0))
6996 (clobber (reg:DI 1))
6997 (clobber (reg:DI 2))
6998 (clobber (reg:DI 3))
6999 (clobber (reg:DI 4))
7000 (clobber (reg:DI 5))
7001 (clobber (reg:DI 6))
7002 (clobber (reg:DI 7))
7003 (clobber (reg:DI 8))])]
7004 "TARGET_ABI_UNICOSMK"
7005 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7006 [(set_attr "length" "16")
7007 (set_attr "type" "multi")])
7011 ;; On EV4, these instructions are nops -- no load occurs.
7013 ;; On EV5, these instructions act as a normal load, and thus can trap
7014 ;; if the address is invalid. The OS may (or may not) handle this in
7015 ;; the entMM fault handler and suppress the fault. If so, then this
7016 ;; has the effect of a read prefetch instruction.
7018 ;; On EV6, these become official prefetch instructions.
7020 (define_insn "prefetch"
7021 [(prefetch (match_operand:DI 0 "address_operand" "p")
7022 (match_operand:DI 1 "const_int_operand" "n")
7023 (match_operand:DI 2 "const_int_operand" "n"))]
7024 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
7026 /* Interpret "no temporal locality" as this data should be evicted once
7027 it is used. The "evict next" alternatives load the data into the cache
7028 and leave the LRU eviction counter pointing to that block. */
7029 static const char * const alt[2][2] = {
7031 "ldq $31,%a0", /* read, evict next */
7032 "ldl $31,%a0", /* read, evict last */
7035 "ldt $f31,%a0", /* write, evict next */
7036 "lds $f31,%a0", /* write, evict last */
7040 bool write = INTVAL (operands[1]) != 0;
7041 bool lru = INTVAL (operands[2]) != 0;
7043 return alt[write][lru];
7045 [(set_attr "type" "ild")])
7047 ;; Close the trap shadow of preceding instructions. This is generated
7050 (define_insn "trapb"
7051 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7054 [(set_attr "type" "misc")])
7056 ;; No-op instructions used by machine-dependent reorg to preserve
7057 ;; alignment for instruction issue.
7058 ;; The Unicos/Mk assembler does not support these opcodes.
7064 [(set_attr "type" "ilog")])
7069 "cpys $f31,$f31,$f31"
7070 [(set_attr "type" "fcpys")])
7077 ;; On Unicos/Mk we use a macro for aligning code.
7079 (define_insn "realign"
7080 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7084 if (TARGET_ABI_UNICOSMK)
7085 return "gcc@code@align %0";
7087 return ".align %0 #realign";
7090 ;; Instructions to be emitted from __builtins.
7092 (define_insn "builtin_cmpbge"
7093 [(set (match_operand:DI 0 "register_operand" "=r")
7094 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7095 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7099 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7100 ;; actually differentiate between ILOG and ICMP in the schedule.
7101 [(set_attr "type" "icmp")])
7103 (define_expand "builtin_extbl"
7104 [(match_operand:DI 0 "register_operand" "")
7105 (match_operand:DI 1 "reg_or_0_operand" "")
7106 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7109 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7110 if (WORDS_BIG_ENDIAN)
7114 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7118 (define_expand "builtin_extwl"
7119 [(match_operand:DI 0 "register_operand" "")
7120 (match_operand:DI 1 "reg_or_0_operand" "")
7121 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7124 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7125 if (WORDS_BIG_ENDIAN)
7129 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7133 (define_expand "builtin_extll"
7134 [(match_operand:DI 0 "register_operand" "")
7135 (match_operand:DI 1 "reg_or_0_operand" "")
7136 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7139 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7140 if (WORDS_BIG_ENDIAN)
7144 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7148 (define_expand "builtin_extql"
7149 [(match_operand:DI 0 "register_operand" "")
7150 (match_operand:DI 1 "reg_or_0_operand" "")
7151 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7154 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7155 if (WORDS_BIG_ENDIAN)
7159 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7163 (define_expand "builtin_extwh"
7164 [(match_operand:DI 0 "register_operand" "")
7165 (match_operand:DI 1 "reg_or_0_operand" "")
7166 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7169 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7170 if (WORDS_BIG_ENDIAN)
7174 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7178 (define_expand "builtin_extlh"
7179 [(match_operand:DI 0 "register_operand" "")
7180 (match_operand:DI 1 "reg_or_0_operand" "")
7181 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7184 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7185 if (WORDS_BIG_ENDIAN)
7189 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7193 (define_expand "builtin_extqh"
7194 [(match_operand:DI 0 "register_operand" "")
7195 (match_operand:DI 1 "reg_or_0_operand" "")
7196 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7199 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7200 if (WORDS_BIG_ENDIAN)
7204 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7208 (define_expand "builtin_insbl"
7209 [(match_operand:DI 0 "register_operand" "")
7210 (match_operand:DI 1 "reg_or_0_operand" "")
7211 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7214 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7215 if (WORDS_BIG_ENDIAN)
7219 operands[1] = gen_lowpart (QImode, operands[1]);
7220 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7224 (define_expand "builtin_inswl"
7225 [(match_operand:DI 0 "register_operand" "")
7226 (match_operand:DI 1 "reg_or_0_operand" "")
7227 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7230 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7231 if (WORDS_BIG_ENDIAN)
7235 operands[1] = gen_lowpart (HImode, operands[1]);
7236 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7240 (define_expand "builtin_insll"
7241 [(match_operand:DI 0 "register_operand" "")
7242 (match_operand:DI 1 "reg_or_0_operand" "")
7243 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7246 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7247 if (WORDS_BIG_ENDIAN)
7251 operands[1] = gen_lowpart (SImode, operands[1]);
7252 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7253 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7257 (define_expand "builtin_insql"
7258 [(match_operand:DI 0 "register_operand" "")
7259 (match_operand:DI 1 "reg_or_0_operand" "")
7260 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7263 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7264 if (WORDS_BIG_ENDIAN)
7268 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7272 (define_expand "builtin_inswh"
7273 [(match_operand:DI 0 "register_operand" "")
7274 (match_operand:DI 1 "register_operand" "")
7275 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7278 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7282 (define_expand "builtin_inslh"
7283 [(match_operand:DI 0 "register_operand" "")
7284 (match_operand:DI 1 "register_operand" "")
7285 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7288 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7292 (define_expand "builtin_insqh"
7293 [(match_operand:DI 0 "register_operand" "")
7294 (match_operand:DI 1 "register_operand" "")
7295 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7298 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7302 (define_expand "builtin_mskbl"
7303 [(match_operand:DI 0 "register_operand" "")
7304 (match_operand:DI 1 "reg_or_0_operand" "")
7305 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7308 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7310 if (WORDS_BIG_ENDIAN)
7314 mask = GEN_INT (0xff);
7315 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7319 (define_expand "builtin_mskwl"
7320 [(match_operand:DI 0 "register_operand" "")
7321 (match_operand:DI 1 "reg_or_0_operand" "")
7322 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7325 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7327 if (WORDS_BIG_ENDIAN)
7331 mask = GEN_INT (0xffff);
7332 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7336 (define_expand "builtin_mskll"
7337 [(match_operand:DI 0 "register_operand" "")
7338 (match_operand:DI 1 "reg_or_0_operand" "")
7339 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7342 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7344 if (WORDS_BIG_ENDIAN)
7348 mask = immed_double_const (0xffffffff, 0, DImode);
7349 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7353 (define_expand "builtin_mskql"
7354 [(match_operand:DI 0 "register_operand" "")
7355 (match_operand:DI 1 "reg_or_0_operand" "")
7356 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7359 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7361 if (WORDS_BIG_ENDIAN)
7366 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7370 (define_expand "builtin_mskwh"
7371 [(match_operand:DI 0 "register_operand" "")
7372 (match_operand:DI 1 "register_operand" "")
7373 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7376 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7380 (define_expand "builtin_msklh"
7381 [(match_operand:DI 0 "register_operand" "")
7382 (match_operand:DI 1 "register_operand" "")
7383 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7386 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7390 (define_expand "builtin_mskqh"
7391 [(match_operand:DI 0 "register_operand" "")
7392 (match_operand:DI 1 "register_operand" "")
7393 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7396 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7400 (define_expand "builtin_zap"
7401 [(set (match_operand:DI 0 "register_operand" "")
7403 [(match_operand:DI 2 "reg_or_const_int_operand" "")]
7405 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7408 if (GET_CODE (operands[2]) == CONST_INT)
7410 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7412 if (mask == const0_rtx)
7414 emit_move_insn (operands[0], const0_rtx);
7417 if (mask == constm1_rtx)
7419 emit_move_insn (operands[0], operands[1]);
7423 operands[1] = force_reg (DImode, operands[1]);
7424 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7428 operands[1] = force_reg (DImode, operands[1]);
7429 operands[2] = gen_lowpart (QImode, operands[2]);
7432 (define_insn "*builtin_zap_1"
7433 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7435 [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")]
7437 (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))]
7444 [(set_attr "type" "shift,shift,ilog,shift")])
7447 [(set (match_operand:DI 0 "register_operand" "")
7449 [(match_operand:QI 2 "const_int_operand" "")]
7451 (match_operand:DI 1 "const_int_operand" "")))]
7455 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7456 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7457 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7460 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7461 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7462 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7463 c_hi & CONST_DOUBLE_HIGH (mask),
7466 emit_move_insn (operands[0], operands[1]);
7471 [(set (match_operand:DI 0 "register_operand" "")
7473 [(match_operand:QI 2 "const_int_operand" "")]
7475 (match_operand:DI 1 "register_operand" "")))]
7478 (and:DI (match_dup 1) (match_dup 2)))]
7480 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7481 if (operands[2] == const0_rtx)
7483 emit_move_insn (operands[0], const0_rtx);
7486 if (operands[2] == constm1_rtx)
7488 emit_move_insn (operands[0], operands[1]);
7493 (define_expand "builtin_zapnot"
7494 [(set (match_operand:DI 0 "register_operand" "")
7496 [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))]
7498 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7501 if (GET_CODE (operands[2]) == CONST_INT)
7503 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7505 if (mask == const0_rtx)
7507 emit_move_insn (operands[0], const0_rtx);
7510 if (mask == constm1_rtx)
7512 emit_move_insn (operands[0], operands[1]);
7516 operands[1] = force_reg (DImode, operands[1]);
7517 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7521 operands[1] = force_reg (DImode, operands[1]);
7522 operands[2] = gen_lowpart (QImode, operands[2]);
7525 (define_insn "*builtin_zapnot_1"
7526 [(set (match_operand:DI 0 "register_operand" "=r")
7528 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7530 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7533 [(set_attr "type" "shift")])
7535 (define_insn "builtin_amask"
7536 [(set (match_operand:DI 0 "register_operand" "=r")
7537 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7541 [(set_attr "type" "ilog")])
7543 (define_insn "builtin_implver"
7544 [(set (match_operand:DI 0 "register_operand" "=r")
7545 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7548 [(set_attr "type" "ilog")])
7550 (define_insn "builtin_rpcc"
7551 [(set (match_operand:DI 0 "register_operand" "=r")
7552 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7555 [(set_attr "type" "ilog")])
7557 (define_expand "builtin_minub8"
7558 [(match_operand:DI 0 "register_operand" "")
7559 (match_operand:DI 1 "reg_or_0_operand" "")
7560 (match_operand:DI 2 "reg_or_0_operand" "")]
7563 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7564 operands[1], operands[2]);
7568 (define_expand "builtin_minsb8"
7569 [(match_operand:DI 0 "register_operand" "")
7570 (match_operand:DI 1 "reg_or_0_operand" "")
7571 (match_operand:DI 2 "reg_or_0_operand" "")]
7574 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7575 operands[1], operands[2]);
7579 (define_expand "builtin_minuw4"
7580 [(match_operand:DI 0 "register_operand" "")
7581 (match_operand:DI 1 "reg_or_0_operand" "")
7582 (match_operand:DI 2 "reg_or_0_operand" "")]
7585 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7586 operands[1], operands[2]);
7590 (define_expand "builtin_minsw4"
7591 [(match_operand:DI 0 "register_operand" "")
7592 (match_operand:DI 1 "reg_or_0_operand" "")
7593 (match_operand:DI 2 "reg_or_0_operand" "")]
7596 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7597 operands[1], operands[2]);
7601 (define_expand "builtin_maxub8"
7602 [(match_operand:DI 0 "register_operand" "")
7603 (match_operand:DI 1 "reg_or_0_operand" "")
7604 (match_operand:DI 2 "reg_or_0_operand" "")]
7607 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7608 operands[1], operands[2]);
7612 (define_expand "builtin_maxsb8"
7613 [(match_operand:DI 0 "register_operand" "")
7614 (match_operand:DI 1 "reg_or_0_operand" "")
7615 (match_operand:DI 2 "reg_or_0_operand" "")]
7618 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7619 operands[1], operands[2]);
7623 (define_expand "builtin_maxuw4"
7624 [(match_operand:DI 0 "register_operand" "")
7625 (match_operand:DI 1 "reg_or_0_operand" "")
7626 (match_operand:DI 2 "reg_or_0_operand" "")]
7629 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7630 operands[1], operands[2]);
7634 (define_expand "builtin_maxsw4"
7635 [(match_operand:DI 0 "register_operand" "")
7636 (match_operand:DI 1 "reg_or_0_operand" "")
7637 (match_operand:DI 2 "reg_or_0_operand" "")]
7640 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7641 operands[1], operands[2]);
7645 (define_insn "builtin_perr"
7646 [(set (match_operand:DI 0 "register_operand" "=r")
7647 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7648 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7652 [(set_attr "type" "mvi")])
7654 (define_expand "builtin_pklb"
7655 [(set (match_operand:DI 0 "register_operand" "")
7658 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7663 operands[0] = gen_lowpart (V8QImode, operands[0]);
7664 operands[1] = gen_lowpart (V2SImode, operands[1]);
7665 operands[2] = CONST0_RTX (V2QImode);
7666 operands[3] = CONST0_RTX (V4QImode);
7669 (define_insn "*pklb"
7670 [(set (match_operand:V8QI 0 "register_operand" "=r")
7673 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7674 (match_operand:V2QI 2 "const0_operand" ""))
7675 (match_operand:V4QI 3 "const0_operand" "")))]
7678 [(set_attr "type" "mvi")])
7680 (define_expand "builtin_pkwb"
7681 [(set (match_operand:DI 0 "register_operand" "")
7683 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7687 operands[0] = gen_lowpart (V8QImode, operands[0]);
7688 operands[1] = gen_lowpart (V4HImode, operands[1]);
7689 operands[2] = CONST0_RTX (V4QImode);
7692 (define_insn "*pkwb"
7693 [(set (match_operand:V8QI 0 "register_operand" "=r")
7695 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7696 (match_operand:V4QI 2 "const0_operand" "")))]
7699 [(set_attr "type" "mvi")])
7701 (define_expand "builtin_unpkbl"
7702 [(set (match_operand:DI 0 "register_operand" "")
7704 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7705 (parallel [(const_int 0) (const_int 1)]))))]
7708 operands[0] = gen_lowpart (V2SImode, operands[0]);
7709 operands[1] = gen_lowpart (V8QImode, operands[1]);
7712 (define_insn "*unpkbl"
7713 [(set (match_operand:V2SI 0 "register_operand" "=r")
7715 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7716 (parallel [(const_int 0) (const_int 1)]))))]
7719 [(set_attr "type" "mvi")])
7721 (define_expand "builtin_unpkbw"
7722 [(set (match_operand:DI 0 "register_operand" "")
7724 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7725 (parallel [(const_int 0)
7731 operands[0] = gen_lowpart (V4HImode, operands[0]);
7732 operands[1] = gen_lowpart (V8QImode, operands[1]);
7735 (define_insn "*unpkbw"
7736 [(set (match_operand:V4HI 0 "register_operand" "=r")
7738 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7739 (parallel [(const_int 0)
7745 [(set_attr "type" "mvi")])
7747 (define_expand "builtin_cttz"
7748 [(set (match_operand:DI 0 "register_operand" "")
7749 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7754 (define_insn "builtin_ctlz"
7755 [(set (match_operand:DI 0 "register_operand" "=r")
7756 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7760 [(set_attr "type" "mvi")])
7762 (define_insn "builtin_ctpop"
7763 [(set (match_operand:DI 0 "register_operand" "=r")
7764 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7768 [(set_attr "type" "mvi")])
7770 ;; The call patterns are at the end of the file because their
7771 ;; wildcard operand0 interferes with nice recognition.
7773 (define_insn "*call_value_osf_1_er"
7774 [(set (match_operand 0 "" "")
7775 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7776 (match_operand 2 "" "")))
7778 (clobber (reg:DI 26))]
7779 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7781 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7783 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7784 [(set_attr "type" "jsr")
7785 (set_attr "length" "12,*,16")])
7787 ;; We must use peep2 instead of a split because we need accurate life
7788 ;; information for $gp. Consider the case of { bar(); while (1); }.
7790 [(parallel [(set (match_operand 0 "" "")
7791 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7792 (match_operand 2 "" "")))
7794 (clobber (reg:DI 26))])]
7795 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7796 && ! current_file_function_operand (operands[1], Pmode)
7797 && peep2_regno_dead_p (1, 29)"
7798 [(parallel [(set (match_dup 0)
7799 (call (mem:DI (match_dup 3))
7801 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7802 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7804 (use (match_dup 4))])]
7806 if (CONSTANT_P (operands[1]))
7808 operands[3] = gen_rtx_REG (Pmode, 27);
7809 operands[4] = GEN_INT (alpha_next_sequence_number++);
7810 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7811 operands[1], operands[4]));
7815 operands[3] = operands[1];
7816 operands[1] = const0_rtx;
7817 operands[4] = const0_rtx;
7822 [(parallel [(set (match_operand 0 "" "")
7823 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7824 (match_operand 2 "" "")))
7826 (clobber (reg:DI 26))])]
7827 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7828 && ! current_file_function_operand (operands[1], Pmode)
7829 && ! peep2_regno_dead_p (1, 29)"
7830 [(parallel [(set (match_dup 0)
7831 (call (mem:DI (match_dup 3))
7833 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7834 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7836 (use (match_dup 5))])
7838 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7840 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7842 if (CONSTANT_P (operands[1]))
7844 operands[3] = gen_rtx_REG (Pmode, 27);
7845 operands[5] = GEN_INT (alpha_next_sequence_number++);
7846 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7847 operands[1], operands[5]));
7851 operands[3] = operands[1];
7852 operands[1] = const0_rtx;
7853 operands[5] = const0_rtx;
7855 operands[4] = GEN_INT (alpha_next_sequence_number++);
7858 ;; We add a blockage unspec_volatile to prevent insns from moving down
7859 ;; from above the call to in between the call and the ldah gpdisp.
7860 (define_insn "*call_value_osf_2_er"
7861 [(set (match_operand 0 "" "")
7862 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7863 (match_operand 2 "" "")))
7865 (plus:DI (pc) (const_int 4)))
7866 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7867 (use (match_operand 3 "" ""))
7868 (use (match_operand 4 "" ""))]
7869 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7870 "jsr $26,(%1),%3%J4"
7871 [(set_attr "type" "jsr")])
7873 (define_insn "*call_value_osf_1_noreturn"
7874 [(set (match_operand 0 "" "")
7875 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7876 (match_operand 2 "" "")))
7878 (clobber (reg:DI 26))]
7879 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7880 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7885 [(set_attr "type" "jsr")
7886 (set_attr "length" "*,*,8")])
7888 (define_insn_and_split "call_value_osf_tlsgd"
7889 [(set (match_operand 0 "" "")
7890 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7892 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7894 (clobber (reg:DI 26))]
7897 "&& reload_completed"
7899 (unspec:DI [(match_dup 5)
7901 (match_dup 2)] UNSPEC_LITERAL))
7902 (parallel [(set (match_dup 0)
7903 (call (mem:DI (match_dup 3))
7905 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7906 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7908 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7910 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7912 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7914 operands[3] = gen_rtx_REG (Pmode, 27);
7915 operands[4] = GEN_INT (alpha_next_sequence_number++);
7916 operands[5] = pic_offset_table_rtx;
7918 [(set_attr "type" "multi")])
7920 (define_insn_and_split "call_value_osf_tlsldm"
7921 [(set (match_operand 0 "" "")
7922 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7924 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7926 (clobber (reg:DI 26))]
7929 "&& reload_completed"
7931 (unspec:DI [(match_dup 5)
7933 (match_dup 2)] UNSPEC_LITERAL))
7934 (parallel [(set (match_dup 0)
7935 (call (mem:DI (match_dup 3))
7937 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7938 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7940 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7942 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7944 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7946 operands[3] = gen_rtx_REG (Pmode, 27);
7947 operands[4] = GEN_INT (alpha_next_sequence_number++);
7948 operands[5] = pic_offset_table_rtx;
7950 [(set_attr "type" "multi")])
7952 (define_insn "*call_value_osf_1"
7953 [(set (match_operand 0 "" "")
7954 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7955 (match_operand 2 "" "")))
7957 (clobber (reg:DI 26))]
7958 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7960 jsr $26,($27),0\;ldgp $29,0($26)
7962 jsr $26,%1\;ldgp $29,0($26)"
7963 [(set_attr "type" "jsr")
7964 (set_attr "length" "12,*,16")])
7966 (define_insn "*sibcall_value_osf_1_er"
7967 [(set (match_operand 0 "" "")
7968 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7969 (match_operand 2 "" "")))
7970 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7971 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7974 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7975 [(set_attr "type" "jsr")
7976 (set_attr "length" "*,8")])
7978 (define_insn "*sibcall_value_osf_1"
7979 [(set (match_operand 0 "" "")
7980 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7981 (match_operand 2 "" "")))
7982 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7983 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7986 lda $27,%1\;jmp $31,($27),%1"
7987 [(set_attr "type" "jsr")
7988 (set_attr "length" "*,8")])
7990 (define_insn "*call_value_nt_1"
7991 [(set (match_operand 0 "" "")
7992 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7993 (match_operand 2 "" "")))
7994 (clobber (reg:DI 26))]
7995 "TARGET_ABI_WINDOWS_NT"
8000 [(set_attr "type" "jsr")
8001 (set_attr "length" "*,*,12")])
8003 ; GAS relies on the order and position of instructions output below in order
8004 ; to generate relocs for VMS link to potentially optimize the call.
8005 ; Please do not molest.
8006 (define_insn "*call_value_vms_1"
8007 [(set (match_operand 0 "" "")
8008 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8009 (match_operand 2 "" "")))
8010 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8013 (clobber (reg:DI 27))]
8014 "TARGET_ABI_OPEN_VMS"
8016 switch (which_alternative)
8019 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8021 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8022 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8023 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8028 [(set_attr "type" "jsr")
8029 (set_attr "length" "12,16")])
8031 (define_insn "*call_value_umk"
8032 [(set (match_operand 0 "" "")
8033 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8034 (match_operand 2 "" "")))
8036 (clobber (reg:DI 26))]
8037 "TARGET_ABI_UNICOSMK"
8039 [(set_attr "type" "jsr")])