1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
41 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
42 (UNSPECV_LONGJMP 3) ; builtin_longjmp
44 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
46 (UNSPECV_EHR 7) ; exception_receiver
50 (UNSPECV_FORCE_MOV 11)
53 ;; Processor type -- this attribute must exactly match the processor_type
54 ;; enumeration in alpha.h.
56 (define_attr "cpu" "ev4,ev5,ev6"
57 (const (symbol_ref "alpha_cpu")))
59 ;; Define an insn type attribute. This is used in function unit delay
60 ;; computations, among other purposes. For the most part, we use the names
61 ;; defined in the EV4 documentation, but add a few that we have to know about
65 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
66 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
67 (const_string "iadd"))
69 ;; Describe a user's asm statement.
70 (define_asm_attributes
71 [(set_attr "type" "multi")])
73 ;; Define the operand size an insn operates on. Used primarily by mul
74 ;; and div operations that have size dependant timings.
76 (define_attr "opsize" "si,di,udi"
79 ;; The TRAP attribute marks instructions that may generate traps
80 ;; (which are imprecise and may need a trapb if software completion
83 (define_attr "trap" "no,yes"
86 ;; The ROUND_SUFFIX attribute marks which instructions require a
87 ;; rounding-mode suffix. The value NONE indicates no suffix,
88 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
90 (define_attr "round_suffix" "none,normal,c"
91 (const_string "none"))
93 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
95 ;; SU accepts only /su (cmpt et al)
96 ;; SUI accepts only /sui (cvtqt and cvtqs)
97 ;; V_SV accepts /v and /sv (cvtql only)
98 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
99 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
101 ;; The actual suffix emitted is controled by alpha_fptm.
103 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
104 (const_string "none"))
106 ;; The length of an instruction sequence in bytes.
108 (define_attr "length" ""
111 ;; On EV4 there are two classes of resources to consider: resources needed
112 ;; to issue, and resources needed to execute. IBUS[01] are in the first
113 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
114 ;; (There are a few other register-like resources, but ...)
116 ; First, describe all of the issue constraints with single cycle delays.
117 ; All insns need a bus, but all except loads require one or the other.
118 (define_function_unit "ev4_ibus0" 1 0
119 (and (eq_attr "cpu" "ev4")
120 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
123 (define_function_unit "ev4_ibus1" 1 0
124 (and (eq_attr "cpu" "ev4")
125 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
128 ; Memory delivers its result in three cycles. Actually return one and
129 ; take care of this in adjust_cost, since we want to handle user-defined
131 (define_function_unit "ev4_abox" 1 0
132 (and (eq_attr "cpu" "ev4")
133 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
136 ; Branches have no delay cost, but do tie up the unit for two cycles.
137 (define_function_unit "ev4_bbox" 1 1
138 (and (eq_attr "cpu" "ev4")
139 (eq_attr "type" "ibr,fbr,jsr"))
142 ; Arithmetic insns are normally have their results available after
143 ; two cycles. There are a number of exceptions. They are encoded in
144 ; ADJUST_COST. Some of the other insns have similar exceptions.
145 (define_function_unit "ev4_ebox" 1 0
146 (and (eq_attr "cpu" "ev4")
147 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
150 (define_function_unit "imul" 1 0
151 (and (eq_attr "cpu" "ev4")
152 (and (eq_attr "type" "imul")
153 (eq_attr "opsize" "si")))
156 (define_function_unit "imul" 1 0
157 (and (eq_attr "cpu" "ev4")
158 (and (eq_attr "type" "imul")
159 (eq_attr "opsize" "!si")))
162 (define_function_unit "ev4_fbox" 1 0
163 (and (eq_attr "cpu" "ev4")
164 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
167 (define_function_unit "fdiv" 1 0
168 (and (eq_attr "cpu" "ev4")
169 (and (eq_attr "type" "fdiv")
170 (eq_attr "opsize" "si")))
173 (define_function_unit "fdiv" 1 0
174 (and (eq_attr "cpu" "ev4")
175 (and (eq_attr "type" "fdiv")
176 (eq_attr "opsize" "di")))
179 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
181 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
182 ;; with the combined resource EBOX.
184 (define_function_unit "ev5_ebox" 2 0
185 (and (eq_attr "cpu" "ev5")
186 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
189 ; Memory takes at least 2 clocks. Return one from here and fix up with
190 ; user-defined latencies in adjust_cost.
191 (define_function_unit "ev5_ebox" 2 0
192 (and (eq_attr "cpu" "ev5")
193 (eq_attr "type" "ild,fld,ldsym"))
196 ; Loads can dual issue with one another, but loads and stores do not mix.
197 (define_function_unit "ev5_e0" 1 0
198 (and (eq_attr "cpu" "ev5")
199 (eq_attr "type" "ild,fld,ldsym"))
201 [(eq_attr "type" "ist,fst")])
203 ; Stores, shifts, multiplies can only issue to E0
204 (define_function_unit "ev5_e0" 1 0
205 (and (eq_attr "cpu" "ev5")
206 (eq_attr "type" "ist,fst,shift,imul"))
209 ; Motion video insns also issue only to E0, and take two ticks.
210 (define_function_unit "ev5_e0" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (eq_attr "type" "mvi"))
215 ; Conditional moves always take 2 ticks.
216 (define_function_unit "ev5_ebox" 2 0
217 (and (eq_attr "cpu" "ev5")
218 (eq_attr "type" "icmov"))
221 ; Branches can only issue to E1
222 (define_function_unit "ev5_e1" 1 0
223 (and (eq_attr "cpu" "ev5")
224 (eq_attr "type" "ibr,jsr"))
227 ; Multiplies also use the integer multiplier.
228 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
229 ; cycles before an integer multiplication completes."
230 (define_function_unit "imul" 1 0
231 (and (eq_attr "cpu" "ev5")
232 (and (eq_attr "type" "imul")
233 (eq_attr "opsize" "si")))
236 (define_function_unit "imul" 1 0
237 (and (eq_attr "cpu" "ev5")
238 (and (eq_attr "type" "imul")
239 (eq_attr "opsize" "di")))
242 (define_function_unit "imul" 1 0
243 (and (eq_attr "cpu" "ev5")
244 (and (eq_attr "type" "imul")
245 (eq_attr "opsize" "udi")))
248 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
249 ;; on either so we have to play the game again.
251 (define_function_unit "ev5_fbox" 2 0
252 (and (eq_attr "cpu" "ev5")
253 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
256 (define_function_unit "ev5_fm" 1 0
257 (and (eq_attr "cpu" "ev5")
258 (eq_attr "type" "fmul"))
261 ; Add and cmov as you would expect; fbr never produces a result;
262 ; fdiv issues through fa to the divider,
263 (define_function_unit "ev5_fa" 1 0
264 (and (eq_attr "cpu" "ev5")
265 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
268 ; ??? How to: "No instruction can be issued to pipe FA exactly five
269 ; cycles before a floating point divide completes."
270 (define_function_unit "fdiv" 1 0
271 (and (eq_attr "cpu" "ev5")
272 (and (eq_attr "type" "fdiv")
273 (eq_attr "opsize" "si")))
274 15 15) ; 15 to 31 data dependant
276 (define_function_unit "fdiv" 1 0
277 (and (eq_attr "cpu" "ev5")
278 (and (eq_attr "type" "fdiv")
279 (eq_attr "opsize" "di")))
280 22 22) ; 22 to 60 data dependant
282 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
284 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
285 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
287 ;; Conditional moves decompose into two independant primitives, each
288 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
290 (define_function_unit "ev6_ebox" 4 0
291 (and (eq_attr "cpu" "ev6")
292 (eq_attr "type" "icmov"))
295 (define_function_unit "ev6_ebox" 4 0
296 (and (eq_attr "cpu" "ev6")
297 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
300 ;; Integer loads take at least 3 clocks, and only issue to lower units.
301 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
302 (define_function_unit "ev6_l" 2 0
303 (and (eq_attr "cpu" "ev6")
304 (eq_attr "type" "ild,ldsym,ist,fst"))
307 ;; FP loads take at least 4 clocks. Return two from here...
308 (define_function_unit "ev6_l" 2 0
309 (and (eq_attr "cpu" "ev6")
310 (eq_attr "type" "fld"))
313 ;; Motion video insns also issue only to U0, and take three ticks.
314 (define_function_unit "ev6_u0" 1 0
315 (and (eq_attr "cpu" "ev6")
316 (eq_attr "type" "mvi"))
319 (define_function_unit "ev6_u" 2 0
320 (and (eq_attr "cpu" "ev6")
321 (eq_attr "type" "mvi"))
324 ;; Shifts issue to either upper pipe.
325 (define_function_unit "ev6_u" 2 0
326 (and (eq_attr "cpu" "ev6")
327 (eq_attr "type" "shift"))
330 ;; Multiplies issue only to U1, and all take 7 ticks.
331 ;; Rather than create a new function unit just for U1, reuse IMUL
332 (define_function_unit "imul" 1 0
333 (and (eq_attr "cpu" "ev6")
334 (eq_attr "type" "imul"))
337 (define_function_unit "ev6_u" 2 0
338 (and (eq_attr "cpu" "ev6")
339 (eq_attr "type" "imul"))
342 ;; Branches issue to either upper pipe
343 (define_function_unit "ev6_u" 2 0
344 (and (eq_attr "cpu" "ev6")
345 (eq_attr "type" "ibr"))
348 ;; Calls only issue to L0.
349 (define_function_unit "ev6_l0" 1 0
350 (and (eq_attr "cpu" "ev6")
351 (eq_attr "type" "jsr"))
354 (define_function_unit "ev6_l" 2 0
355 (and (eq_attr "cpu" "ev6")
356 (eq_attr "type" "jsr"))
359 ;; Ftoi/itof only issue to lower pipes
360 (define_function_unit "ev6_l" 2 0
361 (and (eq_attr "cpu" "ev6")
362 (eq_attr "type" "ftoi"))
365 (define_function_unit "ev6_l" 2 0
366 (and (eq_attr "cpu" "ev6")
367 (eq_attr "type" "itof"))
370 ;; For the FPU we are very similar to EV5, except there's no insn that
371 ;; can issue to fm & fa, so we get to leave that out.
373 (define_function_unit "ev6_fm" 1 0
374 (and (eq_attr "cpu" "ev6")
375 (eq_attr "type" "fmul"))
378 (define_function_unit "ev6_fa" 1 0
379 (and (eq_attr "cpu" "ev6")
380 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
383 (define_function_unit "ev6_fa" 1 0
384 (and (eq_attr "cpu" "ev6")
385 (eq_attr "type" "fcmov"))
388 (define_function_unit "fdiv" 1 0
389 (and (eq_attr "cpu" "ev6")
390 (and (eq_attr "type" "fdiv")
391 (eq_attr "opsize" "si")))
394 (define_function_unit "fdiv" 1 0
395 (and (eq_attr "cpu" "ev6")
396 (and (eq_attr "type" "fdiv")
397 (eq_attr "opsize" "di")))
400 (define_function_unit "fsqrt" 1 0
401 (and (eq_attr "cpu" "ev6")
402 (and (eq_attr "type" "fsqrt")
403 (eq_attr "opsize" "si")))
406 (define_function_unit "fsqrt" 1 0
407 (and (eq_attr "cpu" "ev6")
408 (and (eq_attr "type" "fsqrt")
409 (eq_attr "opsize" "di")))
412 ; ??? The FPU communicates with memory and the integer register file
413 ; via two fp store units. We need a slot in the fst immediately, and
414 ; a slot in LOW after the operand data is ready. At which point the
415 ; data may be moved either to the store queue or the integer register
416 ; file and the insn retired.
419 ;; First define the arithmetic insns. Note that the 32-bit forms also
422 ;; Handle 32-64 bit extension from memory to a floating point register
423 ;; specially, since this ocurrs frequently in int->double conversions.
425 ;; Note that while we must retain the =f case in the insn for reload's
426 ;; benefit, it should be eliminated after reload, so we should never emit
427 ;; code for that case. But we don't reject the possibility.
429 (define_expand "extendsidi2"
430 [(set (match_operand:DI 0 "register_operand" "")
431 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
435 (define_insn "*extendsidi2_nofix"
436 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
438 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
444 lds %0,%1\;cvtlq %0,%0"
445 [(set_attr "type" "iadd,ild,fadd,fld")
446 (set_attr "length" "*,*,*,8")])
448 (define_insn "*extendsidi2_fix"
449 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
451 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
458 lds %0,%1\;cvtlq %0,%0"
459 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
460 (set_attr "length" "*,*,*,*,8")])
462 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
464 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
465 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
467 [(set (match_dup 2) (match_dup 1))
468 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
469 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
471 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
472 ;; reload when converting fp->int.
475 [(set (match_operand:SI 0 "hard_int_register_operand" "")
476 (match_operand:SI 1 "memory_operand" ""))
477 (set (match_operand:DI 2 "hard_int_register_operand" "")
478 (sign_extend:DI (match_dup 0)))]
479 "true_regnum (operands[0]) == true_regnum (operands[2])
480 || peep2_reg_dead_p (2, operands[0])"
482 (sign_extend:DI (match_dup 1)))]
486 [(set (match_operand:SI 0 "hard_int_register_operand" "")
487 (match_operand:SI 1 "hard_fp_register_operand" ""))
488 (set (match_operand:DI 2 "hard_int_register_operand" "")
489 (sign_extend:DI (match_dup 0)))]
491 && (true_regnum (operands[0]) == true_regnum (operands[2])
492 || peep2_reg_dead_p (2, operands[0]))"
494 (sign_extend:DI (match_dup 1)))]
498 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
499 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
500 (set (match_operand:DI 2 "hard_int_register_operand" "")
502 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
504 (sign_extend:DI (match_dup 1)))]
507 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
508 ;; generates better code. We have the anonymous addsi3 pattern below in
509 ;; case combine wants to make it.
510 (define_expand "addsi3"
511 [(set (match_operand:SI 0 "register_operand" "")
512 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
513 (match_operand:SI 2 "add_operand" "")))]
518 rtx op1 = gen_lowpart (DImode, operands[1]);
519 rtx op2 = gen_lowpart (DImode, operands[2]);
521 if (! cse_not_expected)
523 rtx tmp = gen_reg_rtx (DImode);
524 emit_insn (gen_adddi3 (tmp, op1, op2));
525 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
528 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
533 (define_insn "*addsi_internal"
534 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
535 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
536 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
545 [(set (match_operand:SI 0 "register_operand" "")
546 (plus:SI (match_operand:SI 1 "register_operand" "")
547 (match_operand:SI 2 "const_int_operand" "")))]
548 "! add_operand (operands[2], SImode)"
549 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
550 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
552 HOST_WIDE_INT val = INTVAL (operands[2]);
553 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
554 HOST_WIDE_INT rest = val - low;
556 operands[3] = GEN_INT (rest);
557 operands[4] = GEN_INT (low);
560 (define_insn "*addsi_se"
561 [(set (match_operand:DI 0 "register_operand" "=r,r")
563 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
564 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
571 [(set (match_operand:DI 0 "register_operand" "")
573 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
574 (match_operand:SI 2 "const_int_operand" ""))))
575 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
576 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
577 && INTVAL (operands[2]) % 4 == 0"
578 [(set (match_dup 3) (match_dup 4))
579 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
583 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
589 operands[4] = GEN_INT (val);
590 operands[5] = GEN_INT (mult);
594 [(set (match_operand:DI 0 "register_operand" "")
596 (plus:SI (match_operator:SI 1 "comparison_operator"
597 [(match_operand 2 "" "")
598 (match_operand 3 "" "")])
599 (match_operand:SI 4 "add_operand" ""))))
600 (clobber (match_operand:DI 5 "register_operand" ""))]
602 [(set (match_dup 5) (match_dup 6))
603 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
605 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
606 operands[2], operands[3]);
607 operands[7] = gen_lowpart (SImode, operands[5]);
610 (define_insn "addvsi3"
611 [(set (match_operand:SI 0 "register_operand" "=r,r")
612 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
613 (match_operand:SI 2 "sext_add_operand" "rI,O")))
614 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
615 (sign_extend:DI (match_dup 2)))
616 (sign_extend:DI (plus:SI (match_dup 1)
624 (define_expand "adddi3"
625 [(set (match_operand:DI 0 "register_operand" "")
626 (plus:DI (match_operand:DI 1 "register_operand" "")
627 (match_operand:DI 2 "add_operand" "")))]
631 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
632 ;; With complications like
634 ;; The NT stack unwind code can't handle a subq to adjust the stack
635 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
636 ;; the exception handling code will loop if a subq is used and an
639 ;; The 19980616 change to emit prologues as RTL also confused some
640 ;; versions of GDB, which also interprets prologues. This has been
641 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
644 ;; and the fact that the three insns schedule exactly the same, it's
645 ;; just not worth the effort.
647 (define_insn "*adddi_internal"
648 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
649 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
650 (match_operand:DI 2 "add_operand" "r,K,L")))]
657 ;; ??? Allow large constants when basing off the frame pointer or some
658 ;; virtual register that may eliminate to the frame pointer. This is
659 ;; done because register elimination offsets will change the hi/lo split,
660 ;; and if we split before reload, we will require additional instructions.
662 (define_insn "*adddi_fp_hack"
663 [(set (match_operand:DI 0 "register_operand" "=r")
664 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
665 (match_operand:DI 2 "const_int_operand" "n")))]
666 "REG_OK_FP_BASE_P (operands[1])
667 && INTVAL (operands[2]) >= 0
668 /* This is the largest constant an lda+ldah pair can add, minus
669 an upper bound on the displacement between SP and AP during
670 register elimination. See INITIAL_ELIMINATION_OFFSET. */
671 && INTVAL (operands[2])
673 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
674 - ALPHA_ROUND(current_function_outgoing_args_size)
675 - (ALPHA_ROUND (get_frame_size ()
676 + max_reg_num () * UNITS_PER_WORD
677 + current_function_pretend_args_size)
678 - current_function_pretend_args_size))"
681 ;; Don't do this if we are adjusting SP since we don't want to do it
682 ;; in two steps. Don't split FP sources for the reason listed above.
684 [(set (match_operand:DI 0 "register_operand" "")
685 (plus:DI (match_operand:DI 1 "register_operand" "")
686 (match_operand:DI 2 "const_int_operand" "")))]
687 "! add_operand (operands[2], DImode)
688 && operands[0] != stack_pointer_rtx
689 && operands[1] != frame_pointer_rtx
690 && operands[1] != arg_pointer_rtx"
691 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
692 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
694 HOST_WIDE_INT val = INTVAL (operands[2]);
695 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
696 HOST_WIDE_INT rest = val - low;
698 operands[4] = GEN_INT (low);
699 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
700 operands[3] = GEN_INT (rest);
701 else if (! no_new_pseudos)
703 operands[3] = gen_reg_rtx (DImode);
704 emit_move_insn (operands[3], operands[2]);
705 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
712 (define_insn "*saddl"
713 [(set (match_operand:SI 0 "register_operand" "=r,r")
714 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
715 (match_operand:SI 2 "const48_operand" "I,I"))
716 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
722 (define_insn "*saddl_se"
723 [(set (match_operand:DI 0 "register_operand" "=r,r")
725 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
726 (match_operand:SI 2 "const48_operand" "I,I"))
727 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
734 [(set (match_operand:DI 0 "register_operand" "")
736 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
737 [(match_operand 2 "" "")
738 (match_operand 3 "" "")])
739 (match_operand:SI 4 "const48_operand" ""))
740 (match_operand:SI 5 "sext_add_operand" ""))))
741 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
743 [(set (match_dup 6) (match_dup 7))
745 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
748 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
749 operands[2], operands[3]);
750 operands[8] = gen_lowpart (SImode, operands[6]);
753 (define_insn "*saddq"
754 [(set (match_operand:DI 0 "register_operand" "=r,r")
755 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
756 (match_operand:DI 2 "const48_operand" "I,I"))
757 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
763 (define_insn "addvdi3"
764 [(set (match_operand:DI 0 "register_operand" "=r,r")
765 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
766 (match_operand:DI 2 "sext_add_operand" "rI,O")))
767 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
768 (sign_extend:TI (match_dup 2)))
769 (sign_extend:TI (plus:DI (match_dup 1)
777 (define_insn "negsi2"
778 [(set (match_operand:SI 0 "register_operand" "=r")
779 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
783 (define_insn "*negsi_se"
784 [(set (match_operand:DI 0 "register_operand" "=r")
785 (sign_extend:DI (neg:SI
786 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
790 (define_insn "negvsi2"
791 [(set (match_operand:SI 0 "register_operand" "=r")
792 (neg:SI (match_operand:SI 1 "register_operand" "r")))
793 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
794 (sign_extend:DI (neg:SI (match_dup 1))))
799 (define_insn "negdi2"
800 [(set (match_operand:DI 0 "register_operand" "=r")
801 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
805 (define_insn "negvdi2"
806 [(set (match_operand:DI 0 "register_operand" "=r")
807 (neg:DI (match_operand:DI 1 "register_operand" "r")))
808 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
809 (sign_extend:TI (neg:DI (match_dup 1))))
814 (define_expand "subsi3"
815 [(set (match_operand:SI 0 "register_operand" "")
816 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
817 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
822 rtx op1 = gen_lowpart (DImode, operands[1]);
823 rtx op2 = gen_lowpart (DImode, operands[2]);
825 if (! cse_not_expected)
827 rtx tmp = gen_reg_rtx (DImode);
828 emit_insn (gen_subdi3 (tmp, op1, op2));
829 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
832 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
837 (define_insn "*subsi_internal"
838 [(set (match_operand:SI 0 "register_operand" "=r")
839 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
840 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
844 (define_insn "*subsi_se"
845 [(set (match_operand:DI 0 "register_operand" "=r")
846 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
847 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
851 (define_insn "subvsi3"
852 [(set (match_operand:SI 0 "register_operand" "=r")
853 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
854 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
855 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
856 (sign_extend:DI (match_dup 2)))
857 (sign_extend:DI (minus:SI (match_dup 1)
863 (define_insn "subdi3"
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
866 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
870 (define_insn "*ssubl"
871 [(set (match_operand:SI 0 "register_operand" "=r")
872 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
873 (match_operand:SI 2 "const48_operand" "I"))
874 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
878 (define_insn "*ssubl_se"
879 [(set (match_operand:DI 0 "register_operand" "=r")
881 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
882 (match_operand:SI 2 "const48_operand" "I"))
883 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
887 (define_insn "*ssubq"
888 [(set (match_operand:DI 0 "register_operand" "=r")
889 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
890 (match_operand:DI 2 "const48_operand" "I"))
891 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
895 (define_insn "subvdi3"
896 [(set (match_operand:DI 0 "register_operand" "=r")
897 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
898 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
899 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
900 (sign_extend:TI (match_dup 2)))
901 (sign_extend:TI (minus:DI (match_dup 1)
907 (define_insn "mulsi3"
908 [(set (match_operand:SI 0 "register_operand" "=r")
909 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
910 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
913 [(set_attr "type" "imul")
914 (set_attr "opsize" "si")])
916 (define_insn "*mulsi_se"
917 [(set (match_operand:DI 0 "register_operand" "=r")
919 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
920 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
923 [(set_attr "type" "imul")
924 (set_attr "opsize" "si")])
926 (define_insn "mulvsi3"
927 [(set (match_operand:SI 0 "register_operand" "=r")
928 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
929 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
930 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
931 (sign_extend:DI (match_dup 2)))
932 (sign_extend:DI (mult:SI (match_dup 1)
937 [(set_attr "type" "imul")
938 (set_attr "opsize" "si")])
940 (define_insn "muldi3"
941 [(set (match_operand:DI 0 "register_operand" "=r")
942 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
943 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
946 [(set_attr "type" "imul")])
948 (define_insn "mulvdi3"
949 [(set (match_operand:DI 0 "register_operand" "=r")
950 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
951 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
952 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
953 (sign_extend:TI (match_dup 2)))
954 (sign_extend:TI (mult:DI (match_dup 1)
959 [(set_attr "type" "imul")])
961 (define_insn "umuldi3_highpart"
962 [(set (match_operand:DI 0 "register_operand" "=r")
965 (mult:TI (zero_extend:TI
966 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
968 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
972 [(set_attr "type" "imul")
973 (set_attr "opsize" "udi")])
975 (define_insn "*umuldi3_highpart_const"
976 [(set (match_operand:DI 0 "register_operand" "=r")
979 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
980 (match_operand:TI 2 "cint8_operand" "I"))
984 [(set_attr "type" "imul")
985 (set_attr "opsize" "udi")])
987 ;; The divide and remainder operations always take their inputs from
988 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
990 ;; ??? Force sign-extension here because some versions of OSF/1 don't
991 ;; do the right thing if the inputs are not properly sign-extended.
992 ;; But Linux, for instance, does not have this problem. Is it worth
993 ;; the complication here to eliminate the sign extension?
994 ;; Interix/NT has the same sign-extension problem.
996 (define_expand "divsi3"
998 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1000 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1001 (parallel [(set (reg:DI 27)
1002 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
1003 (clobber (reg:DI 23))
1004 (clobber (reg:DI 28))])
1005 (set (match_operand:SI 0 "nonimmediate_operand" "")
1006 (subreg:SI (reg:DI 27) 0))]
1007 "! TARGET_ABI_OPEN_VMS"
1010 (define_expand "udivsi3"
1012 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1014 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1015 (parallel [(set (reg:DI 27)
1016 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
1017 (clobber (reg:DI 23))
1018 (clobber (reg:DI 28))])
1019 (set (match_operand:SI 0 "nonimmediate_operand" "")
1020 (subreg:SI (reg:DI 27) 0))]
1021 "! TARGET_ABI_OPEN_VMS"
1024 (define_expand "modsi3"
1026 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1028 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1029 (parallel [(set (reg:DI 27)
1030 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
1031 (clobber (reg:DI 23))
1032 (clobber (reg:DI 28))])
1033 (set (match_operand:SI 0 "nonimmediate_operand" "")
1034 (subreg:SI (reg:DI 27) 0))]
1035 "! TARGET_ABI_OPEN_VMS"
1038 (define_expand "umodsi3"
1040 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1042 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1043 (parallel [(set (reg:DI 27)
1044 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
1045 (clobber (reg:DI 23))
1046 (clobber (reg:DI 28))])
1047 (set (match_operand:SI 0 "nonimmediate_operand" "")
1048 (subreg:SI (reg:DI 27) 0))]
1049 "! TARGET_ABI_OPEN_VMS"
1052 (define_expand "divdi3"
1053 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1054 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1055 (parallel [(set (reg:DI 27)
1058 (clobber (reg:DI 23))
1059 (clobber (reg:DI 28))])
1060 (set (match_operand:DI 0 "nonimmediate_operand" "")
1062 "! TARGET_ABI_OPEN_VMS"
1065 (define_expand "udivdi3"
1066 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1067 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1068 (parallel [(set (reg:DI 27)
1069 (udiv:DI (reg:DI 24)
1071 (clobber (reg:DI 23))
1072 (clobber (reg:DI 28))])
1073 (set (match_operand:DI 0 "nonimmediate_operand" "")
1075 "! TARGET_ABI_OPEN_VMS"
1078 (define_expand "moddi3"
1079 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1080 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1081 (parallel [(set (reg:DI 27)
1084 (clobber (reg:DI 23))
1085 (clobber (reg:DI 28))])
1086 (set (match_operand:DI 0 "nonimmediate_operand" "")
1088 "! TARGET_ABI_OPEN_VMS"
1091 (define_expand "umoddi3"
1092 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1093 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1094 (parallel [(set (reg:DI 27)
1095 (umod:DI (reg:DI 24)
1097 (clobber (reg:DI 23))
1098 (clobber (reg:DI 28))])
1099 (set (match_operand:DI 0 "nonimmediate_operand" "")
1101 "! TARGET_ABI_OPEN_VMS"
1104 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1105 ;; expanded by the assembler.
1106 (define_insn "*divmodsi_internal"
1108 (sign_extend:DI (match_operator:SI 0 "divmod_operator"
1109 [(reg:DI 24) (reg:DI 25)])))
1110 (clobber (reg:DI 23))
1111 (clobber (reg:DI 28))]
1112 "! TARGET_ABI_OPEN_VMS"
1114 [(set_attr "type" "jsr")
1115 (set_attr "length" "8")])
1117 (define_insn "*divmoddi_internal"
1119 (match_operator:DI 0 "divmod_operator"
1120 [(reg:DI 24) (reg:DI 25)]))
1121 (clobber (reg:DI 23))
1122 (clobber (reg:DI 28))]
1123 "! TARGET_ABI_OPEN_VMS"
1125 [(set_attr "type" "jsr")
1126 (set_attr "length" "8")])
1128 ;; Next are the basic logical operations. These only exist in DImode.
1130 (define_insn "anddi3"
1131 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1132 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1133 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1139 [(set_attr "type" "ilog,ilog,shift")])
1141 ;; There are times when we can split an AND into two AND insns. This occurs
1142 ;; when we can first clear any bytes and then clear anything else. For
1143 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1144 ;; Only do this when running on 64-bit host since the computations are
1145 ;; too messy otherwise.
1148 [(set (match_operand:DI 0 "register_operand" "")
1149 (and:DI (match_operand:DI 1 "register_operand" "")
1150 (match_operand:DI 2 "const_int_operand" "")))]
1151 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1152 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1153 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1155 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1156 unsigned HOST_WIDE_INT mask2 = mask1;
1159 /* For each byte that isn't all zeros, make it all ones. */
1160 for (i = 0; i < 64; i += 8)
1161 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1162 mask1 |= (HOST_WIDE_INT) 0xff << i;
1164 /* Now turn on any bits we've just turned off. */
1167 operands[3] = GEN_INT (mask1);
1168 operands[4] = GEN_INT (mask2);
1171 (define_expand "zero_extendqihi2"
1172 [(set (match_operand:HI 0 "register_operand" "")
1173 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1177 operands[1] = force_reg (QImode, operands[1]);
1180 (define_insn "*zero_extendqihi2_bwx"
1181 [(set (match_operand:HI 0 "register_operand" "=r,r")
1182 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1187 [(set_attr "type" "ilog,ild")])
1189 (define_insn "*zero_extendqihi2_nobwx"
1190 [(set (match_operand:HI 0 "register_operand" "=r")
1191 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1194 [(set_attr "type" "ilog")])
1196 (define_expand "zero_extendqisi2"
1197 [(set (match_operand:SI 0 "register_operand" "")
1198 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1202 operands[1] = force_reg (QImode, operands[1]);
1205 (define_insn "*zero_extendqisi2_bwx"
1206 [(set (match_operand:SI 0 "register_operand" "=r,r")
1207 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1212 [(set_attr "type" "ilog,ild")])
1214 (define_insn "*zero_extendqisi2_nobwx"
1215 [(set (match_operand:SI 0 "register_operand" "=r")
1216 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1219 [(set_attr "type" "ilog")])
1221 (define_expand "zero_extendqidi2"
1222 [(set (match_operand:DI 0 "register_operand" "")
1223 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1227 operands[1] = force_reg (QImode, operands[1]);
1230 (define_insn "*zero_extendqidi2_bwx"
1231 [(set (match_operand:DI 0 "register_operand" "=r,r")
1232 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1237 [(set_attr "type" "ilog,ild")])
1239 (define_insn "*zero_extendqidi2_nobwx"
1240 [(set (match_operand:DI 0 "register_operand" "=r")
1241 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1244 [(set_attr "type" "ilog")])
1246 (define_expand "zero_extendhisi2"
1247 [(set (match_operand:SI 0 "register_operand" "")
1248 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1252 operands[1] = force_reg (HImode, operands[1]);
1255 (define_insn "*zero_extendhisi2_bwx"
1256 [(set (match_operand:SI 0 "register_operand" "=r,r")
1257 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1262 [(set_attr "type" "shift,ild")])
1264 (define_insn "*zero_extendhisi2_nobwx"
1265 [(set (match_operand:SI 0 "register_operand" "=r")
1266 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1269 [(set_attr "type" "shift")])
1271 (define_expand "zero_extendhidi2"
1272 [(set (match_operand:DI 0 "register_operand" "")
1273 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1277 operands[1] = force_reg (HImode, operands[1]);
1280 (define_insn "*zero_extendhidi2_bwx"
1281 [(set (match_operand:DI 0 "register_operand" "=r,r")
1282 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1287 [(set_attr "type" "shift,ild")])
1289 (define_insn "*zero_extendhidi2_nobwx"
1290 [(set (match_operand:DI 0 "register_operand" "=r")
1291 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1294 [(set_attr "type" "shift")])
1296 (define_insn "zero_extendsidi2"
1297 [(set (match_operand:DI 0 "register_operand" "=r")
1298 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1301 [(set_attr "type" "shift")])
1303 (define_insn "andnotdi3"
1304 [(set (match_operand:DI 0 "register_operand" "=r")
1305 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1306 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1309 [(set_attr "type" "ilog")])
1311 (define_insn "iordi3"
1312 [(set (match_operand:DI 0 "register_operand" "=r,r")
1313 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1314 (match_operand:DI 2 "or_operand" "rI,N")))]
1319 [(set_attr "type" "ilog")])
1321 (define_insn "one_cmpldi2"
1322 [(set (match_operand:DI 0 "register_operand" "=r")
1323 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1326 [(set_attr "type" "ilog")])
1328 (define_insn "*iornot"
1329 [(set (match_operand:DI 0 "register_operand" "=r")
1330 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1331 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1334 [(set_attr "type" "ilog")])
1336 (define_insn "xordi3"
1337 [(set (match_operand:DI 0 "register_operand" "=r,r")
1338 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1339 (match_operand:DI 2 "or_operand" "rI,N")))]
1344 [(set_attr "type" "ilog")])
1346 (define_insn "*xornot"
1347 [(set (match_operand:DI 0 "register_operand" "=r")
1348 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1349 (match_operand:DI 2 "register_operand" "rI"))))]
1352 [(set_attr "type" "ilog")])
1354 ;; Handle the FFS insn iff we support CIX.
1356 (define_expand "ffsdi2"
1358 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1360 (plus:DI (match_dup 2) (const_int 1)))
1361 (set (match_operand:DI 0 "register_operand" "")
1362 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1363 (const_int 0) (match_dup 3)))]
1366 operands[2] = gen_reg_rtx (DImode);
1367 operands[3] = gen_reg_rtx (DImode);
1370 (define_insn "*cttz"
1371 [(set (match_operand:DI 0 "register_operand" "=r")
1372 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1375 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1376 ; reuse the existing type name.
1377 [(set_attr "type" "mvi")])
1379 ;; Next come the shifts and the various extract and insert operations.
1381 (define_insn "ashldi3"
1382 [(set (match_operand:DI 0 "register_operand" "=r,r")
1383 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1384 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1387 switch (which_alternative)
1390 if (operands[2] == const1_rtx)
1391 return "addq %r1,%r1,%0";
1393 return "s%P2addq %r1,0,%0";
1395 return "sll %r1,%2,%0";
1400 [(set_attr "type" "iadd,shift")])
1402 ;; ??? The following pattern is made by combine, but earlier phases
1403 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1404 ;; with this in a better way at some point.
1406 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1408 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1409 ;; (match_operand:DI 2 "const_int_operand" "P"))
1411 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1413 ;; if (operands[2] == const1_rtx)
1414 ;; return "addl %r1,%r1,%0";
1416 ;; return "s%P2addl %r1,0,%0";
1418 ;; [(set_attr "type" "iadd")])
1420 (define_insn "lshrdi3"
1421 [(set (match_operand:DI 0 "register_operand" "=r")
1422 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1423 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1426 [(set_attr "type" "shift")])
1428 (define_insn "ashrdi3"
1429 [(set (match_operand:DI 0 "register_operand" "=r")
1430 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1431 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1434 [(set_attr "type" "shift")])
1436 (define_expand "extendqihi2"
1438 (ashift:DI (match_operand:QI 1 "some_operand" "")
1440 (set (match_operand:HI 0 "register_operand" "")
1441 (ashiftrt:DI (match_dup 2)
1447 emit_insn (gen_extendqihi2x (operands[0],
1448 force_reg (QImode, operands[1])));
1452 /* If we have an unaligned MEM, extend to DImode (which we do
1453 specially) and then copy to the result. */
1454 if (unaligned_memory_operand (operands[1], HImode))
1456 rtx temp = gen_reg_rtx (DImode);
1458 emit_insn (gen_extendqidi2 (temp, operands[1]));
1459 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1463 operands[0] = gen_lowpart (DImode, operands[0]);
1464 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1465 operands[2] = gen_reg_rtx (DImode);
1468 (define_insn "extendqidi2x"
1469 [(set (match_operand:DI 0 "register_operand" "=r")
1470 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1473 [(set_attr "type" "shift")])
1475 (define_insn "extendhidi2x"
1476 [(set (match_operand:DI 0 "register_operand" "=r")
1477 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1480 [(set_attr "type" "shift")])
1482 (define_insn "extendqisi2x"
1483 [(set (match_operand:SI 0 "register_operand" "=r")
1484 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1487 [(set_attr "type" "shift")])
1489 (define_insn "extendhisi2x"
1490 [(set (match_operand:SI 0 "register_operand" "=r")
1491 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1494 [(set_attr "type" "shift")])
1496 (define_insn "extendqihi2x"
1497 [(set (match_operand:HI 0 "register_operand" "=r")
1498 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1501 [(set_attr "type" "shift")])
1503 (define_expand "extendqisi2"
1505 (ashift:DI (match_operand:QI 1 "some_operand" "")
1507 (set (match_operand:SI 0 "register_operand" "")
1508 (ashiftrt:DI (match_dup 2)
1514 emit_insn (gen_extendqisi2x (operands[0],
1515 force_reg (QImode, operands[1])));
1519 /* If we have an unaligned MEM, extend to a DImode form of
1520 the result (which we do specially). */
1521 if (unaligned_memory_operand (operands[1], QImode))
1523 rtx temp = gen_reg_rtx (DImode);
1525 emit_insn (gen_extendqidi2 (temp, operands[1]));
1526 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1530 operands[0] = gen_lowpart (DImode, operands[0]);
1531 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1532 operands[2] = gen_reg_rtx (DImode);
1535 (define_expand "extendqidi2"
1537 (ashift:DI (match_operand:QI 1 "some_operand" "")
1539 (set (match_operand:DI 0 "register_operand" "")
1540 (ashiftrt:DI (match_dup 2)
1546 emit_insn (gen_extendqidi2x (operands[0],
1547 force_reg (QImode, operands[1])));
1551 if (unaligned_memory_operand (operands[1], QImode))
1554 = gen_unaligned_extendqidi (operands[0],
1555 get_unaligned_address (operands[1], 1));
1557 alpha_set_memflags (seq, operands[1]);
1562 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1563 operands[2] = gen_reg_rtx (DImode);
1566 (define_expand "extendhisi2"
1568 (ashift:DI (match_operand:HI 1 "some_operand" "")
1570 (set (match_operand:SI 0 "register_operand" "")
1571 (ashiftrt:DI (match_dup 2)
1577 emit_insn (gen_extendhisi2x (operands[0],
1578 force_reg (HImode, operands[1])));
1582 /* If we have an unaligned MEM, extend to a DImode form of
1583 the result (which we do specially). */
1584 if (unaligned_memory_operand (operands[1], HImode))
1586 rtx temp = gen_reg_rtx (DImode);
1588 emit_insn (gen_extendhidi2 (temp, operands[1]));
1589 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1593 operands[0] = gen_lowpart (DImode, operands[0]);
1594 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1595 operands[2] = gen_reg_rtx (DImode);
1598 (define_expand "extendhidi2"
1600 (ashift:DI (match_operand:HI 1 "some_operand" "")
1602 (set (match_operand:DI 0 "register_operand" "")
1603 (ashiftrt:DI (match_dup 2)
1609 emit_insn (gen_extendhidi2x (operands[0],
1610 force_reg (HImode, operands[1])));
1614 if (unaligned_memory_operand (operands[1], HImode))
1617 = gen_unaligned_extendhidi (operands[0],
1618 get_unaligned_address (operands[1], 2));
1620 alpha_set_memflags (seq, operands[1]);
1625 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1626 operands[2] = gen_reg_rtx (DImode);
1629 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1630 ;; as a pattern saves one instruction. The code is similar to that for
1631 ;; the unaligned loads (see below).
1633 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1634 (define_expand "unaligned_extendqidi"
1635 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1637 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1640 (ashift:DI (match_dup 3)
1641 (minus:DI (const_int 64)
1643 (and:DI (match_dup 2) (const_int 7))
1645 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1646 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1649 operands[2] = gen_reg_rtx (DImode);
1650 operands[3] = gen_reg_rtx (DImode);
1651 operands[4] = gen_reg_rtx (DImode);
1654 (define_expand "unaligned_extendhidi"
1655 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1657 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1660 (ashift:DI (match_dup 3)
1661 (minus:DI (const_int 64)
1663 (and:DI (match_dup 2) (const_int 7))
1665 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1666 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1669 operands[2] = gen_reg_rtx (DImode);
1670 operands[3] = gen_reg_rtx (DImode);
1671 operands[4] = gen_reg_rtx (DImode);
1674 (define_insn "*extxl_const"
1675 [(set (match_operand:DI 0 "register_operand" "=r")
1676 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1677 (match_operand:DI 2 "mode_width_operand" "n")
1678 (match_operand:DI 3 "mul8_operand" "I")))]
1680 "ext%M2l %r1,%s3,%0"
1681 [(set_attr "type" "shift")])
1683 (define_insn "extxl"
1684 [(set (match_operand:DI 0 "register_operand" "=r")
1685 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1686 (match_operand:DI 2 "mode_width_operand" "n")
1687 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1691 [(set_attr "type" "shift")])
1693 ;; Combine has some strange notion of preserving existing undefined behaviour
1694 ;; in shifts larger than a word size. So capture these patterns that it
1695 ;; should have turned into zero_extracts.
1697 (define_insn "*extxl_1"
1698 [(set (match_operand:DI 0 "register_operand" "=r")
1699 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1700 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1702 (match_operand:DI 3 "mode_mask_operand" "n")))]
1705 [(set_attr "type" "shift")])
1707 (define_insn "*extql_2"
1708 [(set (match_operand:DI 0 "register_operand" "=r")
1709 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1710 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1714 [(set_attr "type" "shift")])
1716 (define_insn "extqh"
1717 [(set (match_operand:DI 0 "register_operand" "=r")
1719 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1720 (minus:DI (const_int 64)
1723 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1728 [(set_attr "type" "shift")])
1730 (define_insn "extlh"
1731 [(set (match_operand:DI 0 "register_operand" "=r")
1733 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1734 (const_int 2147483647))
1735 (minus:DI (const_int 64)
1738 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1743 [(set_attr "type" "shift")])
1745 (define_insn "extwh"
1746 [(set (match_operand:DI 0 "register_operand" "=r")
1748 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1750 (minus:DI (const_int 64)
1753 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1758 [(set_attr "type" "shift")])
1760 ;; This converts an extXl into an extXh with an appropriate adjustment
1761 ;; to the address calculation.
1764 ;; [(set (match_operand:DI 0 "register_operand" "")
1765 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1766 ;; (match_operand:DI 2 "mode_width_operand" "")
1767 ;; (ashift:DI (match_operand:DI 3 "" "")
1769 ;; (match_operand:DI 4 "const_int_operand" "")))
1770 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1771 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1772 ;; [(set (match_dup 5) (match_dup 6))
1773 ;; (set (match_dup 0)
1774 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1775 ;; (ashift:DI (plus:DI (match_dup 5)
1781 ;; operands[6] = plus_constant (operands[3],
1782 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1783 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1786 (define_insn "*insbl_const"
1787 [(set (match_operand:DI 0 "register_operand" "=r")
1788 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1789 (match_operand:DI 2 "mul8_operand" "I")))]
1792 [(set_attr "type" "shift")])
1794 (define_insn "*inswl_const"
1795 [(set (match_operand:DI 0 "register_operand" "=r")
1796 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1797 (match_operand:DI 2 "mul8_operand" "I")))]
1800 [(set_attr "type" "shift")])
1802 (define_insn "*insll_const"
1803 [(set (match_operand:DI 0 "register_operand" "=r")
1804 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1805 (match_operand:DI 2 "mul8_operand" "I")))]
1808 [(set_attr "type" "shift")])
1810 (define_insn "insbl"
1811 [(set (match_operand:DI 0 "register_operand" "=r")
1812 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1813 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1817 [(set_attr "type" "shift")])
1819 (define_insn "inswl"
1820 [(set (match_operand:DI 0 "register_operand" "=r")
1821 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1822 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1826 [(set_attr "type" "shift")])
1828 (define_insn "insll"
1829 [(set (match_operand:DI 0 "register_operand" "=r")
1830 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1831 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1835 [(set_attr "type" "shift")])
1837 (define_insn "insql"
1838 [(set (match_operand:DI 0 "register_operand" "=r")
1839 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1840 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1844 [(set_attr "type" "shift")])
1846 ;; Combine has this sometimes habit of moving the and outside of the
1847 ;; shift, making life more interesting.
1849 (define_insn "*insxl"
1850 [(set (match_operand:DI 0 "register_operand" "=r")
1851 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1852 (match_operand:DI 2 "mul8_operand" "I"))
1853 (match_operand:DI 3 "immediate_operand" "i")))]
1854 "HOST_BITS_PER_WIDE_INT == 64
1855 && GET_CODE (operands[3]) == CONST_INT
1856 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1857 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1858 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1859 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1860 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1861 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1863 #if HOST_BITS_PER_WIDE_INT == 64
1864 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1865 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1866 return "insbl %1,%s2,%0";
1867 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1868 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1869 return "inswl %1,%s2,%0";
1870 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1871 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1872 return "insll %1,%s2,%0";
1876 [(set_attr "type" "shift")])
1878 ;; We do not include the insXh insns because they are complex to express
1879 ;; and it does not appear that we would ever want to generate them.
1881 ;; Since we need them for block moves, though, cop out and use unspec.
1883 (define_insn "insxh"
1884 [(set (match_operand:DI 0 "register_operand" "=r")
1885 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1886 (match_operand:DI 2 "mode_width_operand" "n")
1887 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
1891 [(set_attr "type" "shift")])
1893 (define_insn "mskxl"
1894 [(set (match_operand:DI 0 "register_operand" "=r")
1895 (and:DI (not:DI (ashift:DI
1896 (match_operand:DI 2 "mode_mask_operand" "n")
1898 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1900 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1903 [(set_attr "type" "shift")])
1905 ;; We do not include the mskXh insns because it does not appear we would
1906 ;; ever generate one.
1908 ;; Again, we do for block moves and we use unspec again.
1910 (define_insn "mskxh"
1911 [(set (match_operand:DI 0 "register_operand" "=r")
1912 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1913 (match_operand:DI 2 "mode_width_operand" "n")
1914 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
1918 [(set_attr "type" "shift")])
1920 ;; Prefer AND + NE over LSHIFTRT + AND.
1922 (define_insn_and_split "*ze_and_ne"
1923 [(set (match_operand:DI 0 "register_operand" "=r")
1924 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1926 (match_operand 2 "const_int_operand" "I")))]
1927 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1929 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1931 (and:DI (match_dup 1) (match_dup 3)))
1933 (ne:DI (match_dup 0) (const_int 0)))]
1934 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
1936 ;; Floating-point operations. All the double-precision insns can extend
1937 ;; from single, so indicate that. The exception are the ones that simply
1938 ;; play with the sign bits; it's not clear what to do there.
1940 (define_insn "abssf2"
1941 [(set (match_operand:SF 0 "register_operand" "=f")
1942 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1945 [(set_attr "type" "fcpys")])
1947 (define_insn "*nabssf2"
1948 [(set (match_operand:SF 0 "register_operand" "=f")
1949 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1952 [(set_attr "type" "fadd")])
1954 (define_insn "absdf2"
1955 [(set (match_operand:DF 0 "register_operand" "=f")
1956 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1959 [(set_attr "type" "fcpys")])
1961 (define_insn "*nabsdf2"
1962 [(set (match_operand:DF 0 "register_operand" "=f")
1963 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
1966 [(set_attr "type" "fadd")])
1968 (define_expand "abstf2"
1969 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1970 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1971 (use (match_dup 2))])]
1972 "TARGET_HAS_XFLOATING_LIBS"
1974 #if HOST_BITS_PER_WIDE_INT >= 64
1975 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1977 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1981 (define_insn_and_split "*abstf_internal"
1982 [(set (match_operand:TF 0 "register_operand" "=r")
1983 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1984 (use (match_operand:DI 2 "register_operand" "r"))]
1985 "TARGET_HAS_XFLOATING_LIBS"
1987 "&& reload_completed"
1989 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
1991 (define_insn "negsf2"
1992 [(set (match_operand:SF 0 "register_operand" "=f")
1993 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1996 [(set_attr "type" "fadd")])
1998 (define_insn "negdf2"
1999 [(set (match_operand:DF 0 "register_operand" "=f")
2000 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2003 [(set_attr "type" "fadd")])
2005 (define_expand "negtf2"
2006 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2007 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2008 (use (match_dup 2))])]
2009 "TARGET_HAS_XFLOATING_LIBS"
2011 #if HOST_BITS_PER_WIDE_INT >= 64
2012 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2014 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2018 (define_insn_and_split "*negtf_internal"
2019 [(set (match_operand:TF 0 "register_operand" "=r")
2020 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2021 (use (match_operand:DI 2 "register_operand" "r"))]
2022 "TARGET_HAS_XFLOATING_LIBS"
2024 "&& reload_completed"
2026 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2028 (define_insn "*addsf_ieee"
2029 [(set (match_operand:SF 0 "register_operand" "=&f")
2030 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2031 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2032 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2033 "add%,%/ %R1,%R2,%0"
2034 [(set_attr "type" "fadd")
2035 (set_attr "trap" "yes")
2036 (set_attr "round_suffix" "normal")
2037 (set_attr "trap_suffix" "u_su_sui")])
2039 (define_insn "addsf3"
2040 [(set (match_operand:SF 0 "register_operand" "=f")
2041 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2042 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2044 "add%,%/ %R1,%R2,%0"
2045 [(set_attr "type" "fadd")
2046 (set_attr "trap" "yes")
2047 (set_attr "round_suffix" "normal")
2048 (set_attr "trap_suffix" "u_su_sui")])
2050 (define_insn "*adddf_ieee"
2051 [(set (match_operand:DF 0 "register_operand" "=&f")
2052 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2053 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2054 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2055 "add%-%/ %R1,%R2,%0"
2056 [(set_attr "type" "fadd")
2057 (set_attr "trap" "yes")
2058 (set_attr "round_suffix" "normal")
2059 (set_attr "trap_suffix" "u_su_sui")])
2061 (define_insn "adddf3"
2062 [(set (match_operand:DF 0 "register_operand" "=f")
2063 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2064 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2066 "add%-%/ %R1,%R2,%0"
2067 [(set_attr "type" "fadd")
2068 (set_attr "trap" "yes")
2069 (set_attr "round_suffix" "normal")
2070 (set_attr "trap_suffix" "u_su_sui")])
2072 (define_insn "*adddf_ext1"
2073 [(set (match_operand:DF 0 "register_operand" "=f")
2074 (plus:DF (float_extend:DF
2075 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2076 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2077 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2078 "add%-%/ %R1,%R2,%0"
2079 [(set_attr "type" "fadd")
2080 (set_attr "trap" "yes")
2081 (set_attr "round_suffix" "normal")
2082 (set_attr "trap_suffix" "u_su_sui")])
2084 (define_insn "*adddf_ext2"
2085 [(set (match_operand:DF 0 "register_operand" "=f")
2086 (plus:DF (float_extend:DF
2087 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2089 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2090 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2091 "add%-%/ %R1,%R2,%0"
2092 [(set_attr "type" "fadd")
2093 (set_attr "trap" "yes")
2094 (set_attr "round_suffix" "normal")
2095 (set_attr "trap_suffix" "u_su_sui")])
2097 (define_expand "addtf3"
2098 [(use (match_operand 0 "register_operand" ""))
2099 (use (match_operand 1 "general_operand" ""))
2100 (use (match_operand 2 "general_operand" ""))]
2101 "TARGET_HAS_XFLOATING_LIBS"
2102 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2104 ;; Define conversion operators between DFmode and SImode, using the cvtql
2105 ;; instruction. To allow combine et al to do useful things, we keep the
2106 ;; operation as a unit until after reload, at which point we split the
2109 ;; Note that we (attempt to) only consider this optimization when the
2110 ;; ultimate destination is memory. If we will be doing further integer
2111 ;; processing, it is cheaper to do the truncation in the int regs.
2113 (define_insn "*cvtql"
2114 [(set (match_operand:SI 0 "register_operand" "=f")
2115 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2119 [(set_attr "type" "fadd")
2120 (set_attr "trap" "yes")
2121 (set_attr "trap_suffix" "v_sv")])
2123 (define_insn_and_split "*fix_truncdfsi_ieee"
2124 [(set (match_operand:SI 0 "memory_operand" "=m")
2125 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2126 (clobber (match_scratch:DI 2 "=&f"))
2127 (clobber (match_scratch:SI 3 "=&f"))]
2128 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2130 "&& reload_completed"
2131 [(set (match_dup 2) (fix:DI (match_dup 1)))
2132 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2133 (set (match_dup 0) (match_dup 3))]
2135 [(set_attr "type" "fadd")
2136 (set_attr "trap" "yes")])
2138 (define_insn_and_split "*fix_truncdfsi_internal"
2139 [(set (match_operand:SI 0 "memory_operand" "=m")
2140 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2141 (clobber (match_scratch:DI 2 "=f"))]
2142 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2144 "&& reload_completed"
2145 [(set (match_dup 2) (fix:DI (match_dup 1)))
2146 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2147 (set (match_dup 0) (match_dup 3))]
2148 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2149 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2150 [(set_attr "type" "fadd")
2151 (set_attr "trap" "yes")])
2153 (define_insn "*fix_truncdfdi_ieee"
2154 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2155 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2156 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2158 [(set_attr "type" "fadd")
2159 (set_attr "trap" "yes")
2160 (set_attr "round_suffix" "c")
2161 (set_attr "trap_suffix" "v_sv_svi")])
2163 (define_insn "fix_truncdfdi2"
2164 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2165 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2168 [(set_attr "type" "fadd")
2169 (set_attr "trap" "yes")
2170 (set_attr "round_suffix" "c")
2171 (set_attr "trap_suffix" "v_sv_svi")])
2173 ;; Likewise between SFmode and SImode.
2175 (define_insn_and_split "*fix_truncsfsi_ieee"
2176 [(set (match_operand:SI 0 "memory_operand" "=m")
2177 (subreg:SI (fix:DI (float_extend:DF
2178 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2179 (clobber (match_scratch:DI 2 "=&f"))
2180 (clobber (match_scratch:SI 3 "=&f"))]
2181 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2183 "&& reload_completed"
2184 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2185 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2186 (set (match_dup 0) (match_dup 3))]
2188 [(set_attr "type" "fadd")
2189 (set_attr "trap" "yes")])
2191 (define_insn_and_split "*fix_truncsfsi_internal"
2192 [(set (match_operand:SI 0 "memory_operand" "=m")
2193 (subreg:SI (fix:DI (float_extend:DF
2194 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2195 (clobber (match_scratch:DI 2 "=f"))]
2196 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2198 "&& reload_completed"
2199 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2200 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2201 (set (match_dup 0) (match_dup 3))]
2202 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2203 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2204 [(set_attr "type" "fadd")
2205 (set_attr "trap" "yes")])
2207 (define_insn "*fix_truncsfdi_ieee"
2208 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2209 (fix:DI (float_extend:DF
2210 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2211 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2213 [(set_attr "type" "fadd")
2214 (set_attr "trap" "yes")
2215 (set_attr "round_suffix" "c")
2216 (set_attr "trap_suffix" "v_sv_svi")])
2218 (define_insn "fix_truncsfdi2"
2219 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2220 (fix:DI (float_extend:DF
2221 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2224 [(set_attr "type" "fadd")
2225 (set_attr "trap" "yes")
2226 (set_attr "round_suffix" "c")
2227 (set_attr "trap_suffix" "v_sv_svi")])
2229 (define_expand "fix_trunctfdi2"
2230 [(use (match_operand:DI 0 "register_operand" ""))
2231 (use (match_operand:TF 1 "general_operand" ""))]
2232 "TARGET_HAS_XFLOATING_LIBS"
2233 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2235 (define_insn "*floatdisf_ieee"
2236 [(set (match_operand:SF 0 "register_operand" "=&f")
2237 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2238 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2240 [(set_attr "type" "fadd")
2241 (set_attr "trap" "yes")
2242 (set_attr "round_suffix" "normal")
2243 (set_attr "trap_suffix" "sui")])
2245 (define_insn "floatdisf2"
2246 [(set (match_operand:SF 0 "register_operand" "=f")
2247 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2250 [(set_attr "type" "fadd")
2251 (set_attr "trap" "yes")
2252 (set_attr "round_suffix" "normal")
2253 (set_attr "trap_suffix" "sui")])
2255 (define_insn "*floatdidf_ieee"
2256 [(set (match_operand:DF 0 "register_operand" "=&f")
2257 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2258 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2260 [(set_attr "type" "fadd")
2261 (set_attr "trap" "yes")
2262 (set_attr "round_suffix" "normal")
2263 (set_attr "trap_suffix" "sui")])
2265 (define_insn "floatdidf2"
2266 [(set (match_operand:DF 0 "register_operand" "=f")
2267 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2270 [(set_attr "type" "fadd")
2271 (set_attr "trap" "yes")
2272 (set_attr "round_suffix" "normal")
2273 (set_attr "trap_suffix" "sui")])
2275 (define_expand "floatditf2"
2276 [(use (match_operand:TF 0 "register_operand" ""))
2277 (use (match_operand:DI 1 "general_operand" ""))]
2278 "TARGET_HAS_XFLOATING_LIBS"
2279 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2281 (define_expand "floatunsdisf2"
2282 [(use (match_operand:SF 0 "register_operand" ""))
2283 (use (match_operand:DI 1 "register_operand" ""))]
2285 "alpha_emit_floatuns (operands); DONE;")
2287 (define_expand "floatunsdidf2"
2288 [(use (match_operand:DF 0 "register_operand" ""))
2289 (use (match_operand:DI 1 "register_operand" ""))]
2291 "alpha_emit_floatuns (operands); DONE;")
2293 (define_expand "floatunsditf2"
2294 [(use (match_operand:TF 0 "register_operand" ""))
2295 (use (match_operand:DI 1 "general_operand" ""))]
2296 "TARGET_HAS_XFLOATING_LIBS"
2297 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2299 (define_expand "extendsfdf2"
2300 [(set (match_operand:DF 0 "register_operand" "")
2301 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2304 if (alpha_fptm >= ALPHA_FPTM_SU)
2305 operands[1] = force_reg (SFmode, operands[1]);
2308 (define_insn "*extendsfdf2_ieee"
2309 [(set (match_operand:DF 0 "register_operand" "=&f")
2310 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2311 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2313 [(set_attr "type" "fadd")
2314 (set_attr "trap" "yes")])
2316 (define_insn "*extendsfdf2_internal"
2317 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2318 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2319 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2324 [(set_attr "type" "fcpys,fld,fst")])
2326 (define_expand "extendsftf2"
2327 [(use (match_operand:TF 0 "register_operand" ""))
2328 (use (match_operand:SF 1 "general_operand" ""))]
2329 "TARGET_HAS_XFLOATING_LIBS"
2331 rtx tmp = gen_reg_rtx (DFmode);
2332 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2333 emit_insn (gen_extenddftf2 (operands[0], tmp));
2337 (define_expand "extenddftf2"
2338 [(use (match_operand:TF 0 "register_operand" ""))
2339 (use (match_operand:DF 1 "general_operand" ""))]
2340 "TARGET_HAS_XFLOATING_LIBS"
2341 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2343 (define_insn "*truncdfsf2_ieee"
2344 [(set (match_operand:SF 0 "register_operand" "=&f")
2345 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2346 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2348 [(set_attr "type" "fadd")
2349 (set_attr "trap" "yes")
2350 (set_attr "round_suffix" "normal")
2351 (set_attr "trap_suffix" "u_su_sui")])
2353 (define_insn "truncdfsf2"
2354 [(set (match_operand:SF 0 "register_operand" "=f")
2355 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2358 [(set_attr "type" "fadd")
2359 (set_attr "trap" "yes")
2360 (set_attr "round_suffix" "normal")
2361 (set_attr "trap_suffix" "u_su_sui")])
2363 (define_expand "trunctfdf2"
2364 [(use (match_operand:DF 0 "register_operand" ""))
2365 (use (match_operand:TF 1 "general_operand" ""))]
2366 "TARGET_HAS_XFLOATING_LIBS"
2367 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2369 (define_expand "trunctfsf2"
2370 [(use (match_operand:SF 0 "register_operand" ""))
2371 (use (match_operand:TF 1 "general_operand" ""))]
2372 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2374 rtx tmpf, sticky, arg, lo, hi;
2376 tmpf = gen_reg_rtx (DFmode);
2377 sticky = gen_reg_rtx (DImode);
2378 arg = copy_to_mode_reg (TFmode, operands[1]);
2379 lo = gen_lowpart (DImode, arg);
2380 hi = gen_highpart (DImode, arg);
2382 /* Convert the low word of the TFmode value into a sticky rounding bit,
2383 then or it into the low bit of the high word. This leaves the sticky
2384 bit at bit 48 of the fraction, which is representable in DFmode,
2385 which prevents rounding error in the final conversion to SFmode. */
2387 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2388 gen_rtx_NE (DImode, lo, const0_rtx)));
2389 emit_insn (gen_iordi3 (hi, hi, sticky));
2390 emit_insn (gen_trunctfdf2 (tmpf, arg));
2391 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2395 (define_insn "*divsf3_ieee"
2396 [(set (match_operand:SF 0 "register_operand" "=&f")
2397 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2398 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2399 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2400 "div%,%/ %R1,%R2,%0"
2401 [(set_attr "type" "fdiv")
2402 (set_attr "opsize" "si")
2403 (set_attr "trap" "yes")
2404 (set_attr "round_suffix" "normal")
2405 (set_attr "trap_suffix" "u_su_sui")])
2407 (define_insn "divsf3"
2408 [(set (match_operand:SF 0 "register_operand" "=f")
2409 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2410 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2412 "div%,%/ %R1,%R2,%0"
2413 [(set_attr "type" "fdiv")
2414 (set_attr "opsize" "si")
2415 (set_attr "trap" "yes")
2416 (set_attr "round_suffix" "normal")
2417 (set_attr "trap_suffix" "u_su_sui")])
2419 (define_insn "*divdf3_ieee"
2420 [(set (match_operand:DF 0 "register_operand" "=&f")
2421 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2422 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2423 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2424 "div%-%/ %R1,%R2,%0"
2425 [(set_attr "type" "fdiv")
2426 (set_attr "trap" "yes")
2427 (set_attr "round_suffix" "normal")
2428 (set_attr "trap_suffix" "u_su_sui")])
2430 (define_insn "divdf3"
2431 [(set (match_operand:DF 0 "register_operand" "=f")
2432 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2433 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2435 "div%-%/ %R1,%R2,%0"
2436 [(set_attr "type" "fdiv")
2437 (set_attr "trap" "yes")
2438 (set_attr "round_suffix" "normal")
2439 (set_attr "trap_suffix" "u_su_sui")])
2441 (define_insn "*divdf_ext1"
2442 [(set (match_operand:DF 0 "register_operand" "=f")
2443 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2444 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2445 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2446 "div%-%/ %R1,%R2,%0"
2447 [(set_attr "type" "fdiv")
2448 (set_attr "trap" "yes")
2449 (set_attr "round_suffix" "normal")
2450 (set_attr "trap_suffix" "u_su_sui")])
2452 (define_insn "*divdf_ext2"
2453 [(set (match_operand:DF 0 "register_operand" "=f")
2454 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2456 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2457 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2458 "div%-%/ %R1,%R2,%0"
2459 [(set_attr "type" "fdiv")
2460 (set_attr "trap" "yes")
2461 (set_attr "round_suffix" "normal")
2462 (set_attr "trap_suffix" "u_su_sui")])
2464 (define_insn "*divdf_ext3"
2465 [(set (match_operand:DF 0 "register_operand" "=f")
2466 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2467 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2468 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2469 "div%-%/ %R1,%R2,%0"
2470 [(set_attr "type" "fdiv")
2471 (set_attr "trap" "yes")
2472 (set_attr "round_suffix" "normal")
2473 (set_attr "trap_suffix" "u_su_sui")])
2475 (define_expand "divtf3"
2476 [(use (match_operand 0 "register_operand" ""))
2477 (use (match_operand 1 "general_operand" ""))
2478 (use (match_operand 2 "general_operand" ""))]
2479 "TARGET_HAS_XFLOATING_LIBS"
2480 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2482 (define_insn "*mulsf3_ieee"
2483 [(set (match_operand:SF 0 "register_operand" "=&f")
2484 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2485 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2486 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2487 "mul%,%/ %R1,%R2,%0"
2488 [(set_attr "type" "fmul")
2489 (set_attr "trap" "yes")
2490 (set_attr "round_suffix" "normal")
2491 (set_attr "trap_suffix" "u_su_sui")])
2493 (define_insn "mulsf3"
2494 [(set (match_operand:SF 0 "register_operand" "=f")
2495 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2496 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2498 "mul%,%/ %R1,%R2,%0"
2499 [(set_attr "type" "fmul")
2500 (set_attr "trap" "yes")
2501 (set_attr "round_suffix" "normal")
2502 (set_attr "trap_suffix" "u_su_sui")])
2504 (define_insn "*muldf3_ieee"
2505 [(set (match_operand:DF 0 "register_operand" "=&f")
2506 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2507 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2508 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2509 "mul%-%/ %R1,%R2,%0"
2510 [(set_attr "type" "fmul")
2511 (set_attr "trap" "yes")
2512 (set_attr "round_suffix" "normal")
2513 (set_attr "trap_suffix" "u_su_sui")])
2515 (define_insn "muldf3"
2516 [(set (match_operand:DF 0 "register_operand" "=f")
2517 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2518 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2520 "mul%-%/ %R1,%R2,%0"
2521 [(set_attr "type" "fmul")
2522 (set_attr "trap" "yes")
2523 (set_attr "round_suffix" "normal")
2524 (set_attr "trap_suffix" "u_su_sui")])
2526 (define_insn "*muldf_ext1"
2527 [(set (match_operand:DF 0 "register_operand" "=f")
2528 (mult:DF (float_extend:DF
2529 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2530 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2531 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2532 "mul%-%/ %R1,%R2,%0"
2533 [(set_attr "type" "fmul")
2534 (set_attr "trap" "yes")
2535 (set_attr "round_suffix" "normal")
2536 (set_attr "trap_suffix" "u_su_sui")])
2538 (define_insn "*muldf_ext2"
2539 [(set (match_operand:DF 0 "register_operand" "=f")
2540 (mult:DF (float_extend:DF
2541 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2543 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2544 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2545 "mul%-%/ %R1,%R2,%0"
2546 [(set_attr "type" "fmul")
2547 (set_attr "trap" "yes")
2548 (set_attr "round_suffix" "normal")
2549 (set_attr "trap_suffix" "u_su_sui")])
2551 (define_expand "multf3"
2552 [(use (match_operand 0 "register_operand" ""))
2553 (use (match_operand 1 "general_operand" ""))
2554 (use (match_operand 2 "general_operand" ""))]
2555 "TARGET_HAS_XFLOATING_LIBS"
2556 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2558 (define_insn "*subsf3_ieee"
2559 [(set (match_operand:SF 0 "register_operand" "=&f")
2560 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2561 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2562 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2563 "sub%,%/ %R1,%R2,%0"
2564 [(set_attr "type" "fadd")
2565 (set_attr "trap" "yes")
2566 (set_attr "round_suffix" "normal")
2567 (set_attr "trap_suffix" "u_su_sui")])
2569 (define_insn "subsf3"
2570 [(set (match_operand:SF 0 "register_operand" "=f")
2571 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2572 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2574 "sub%,%/ %R1,%R2,%0"
2575 [(set_attr "type" "fadd")
2576 (set_attr "trap" "yes")
2577 (set_attr "round_suffix" "normal")
2578 (set_attr "trap_suffix" "u_su_sui")])
2580 (define_insn "*subdf3_ieee"
2581 [(set (match_operand:DF 0 "register_operand" "=&f")
2582 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2583 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2584 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2585 "sub%-%/ %R1,%R2,%0"
2586 [(set_attr "type" "fadd")
2587 (set_attr "trap" "yes")
2588 (set_attr "round_suffix" "normal")
2589 (set_attr "trap_suffix" "u_su_sui")])
2591 (define_insn "subdf3"
2592 [(set (match_operand:DF 0 "register_operand" "=f")
2593 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2594 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2596 "sub%-%/ %R1,%R2,%0"
2597 [(set_attr "type" "fadd")
2598 (set_attr "trap" "yes")
2599 (set_attr "round_suffix" "normal")
2600 (set_attr "trap_suffix" "u_su_sui")])
2602 (define_insn "*subdf_ext1"
2603 [(set (match_operand:DF 0 "register_operand" "=f")
2604 (minus:DF (float_extend:DF
2605 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2606 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2607 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2608 "sub%-%/ %R1,%R2,%0"
2609 [(set_attr "type" "fadd")
2610 (set_attr "trap" "yes")
2611 (set_attr "round_suffix" "normal")
2612 (set_attr "trap_suffix" "u_su_sui")])
2614 (define_insn "*subdf_ext2"
2615 [(set (match_operand:DF 0 "register_operand" "=f")
2616 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2618 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2619 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2620 "sub%-%/ %R1,%R2,%0"
2621 [(set_attr "type" "fadd")
2622 (set_attr "trap" "yes")
2623 (set_attr "round_suffix" "normal")
2624 (set_attr "trap_suffix" "u_su_sui")])
2626 (define_insn "*subdf_ext3"
2627 [(set (match_operand:DF 0 "register_operand" "=f")
2628 (minus:DF (float_extend:DF
2629 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2631 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2632 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2633 "sub%-%/ %R1,%R2,%0"
2634 [(set_attr "type" "fadd")
2635 (set_attr "trap" "yes")
2636 (set_attr "round_suffix" "normal")
2637 (set_attr "trap_suffix" "u_su_sui")])
2639 (define_expand "subtf3"
2640 [(use (match_operand 0 "register_operand" ""))
2641 (use (match_operand 1 "general_operand" ""))
2642 (use (match_operand 2 "general_operand" ""))]
2643 "TARGET_HAS_XFLOATING_LIBS"
2644 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2646 (define_insn "*sqrtsf2_ieee"
2647 [(set (match_operand:SF 0 "register_operand" "=&f")
2648 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2649 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2651 [(set_attr "type" "fsqrt")
2652 (set_attr "opsize" "si")
2653 (set_attr "trap" "yes")
2654 (set_attr "round_suffix" "normal")
2655 (set_attr "trap_suffix" "u_su_sui")])
2657 (define_insn "sqrtsf2"
2658 [(set (match_operand:SF 0 "register_operand" "=f")
2659 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2660 "TARGET_FP && TARGET_FIX"
2662 [(set_attr "type" "fsqrt")
2663 (set_attr "opsize" "si")
2664 (set_attr "trap" "yes")
2665 (set_attr "round_suffix" "normal")
2666 (set_attr "trap_suffix" "u_su_sui")])
2668 (define_insn "*sqrtdf2_ieee"
2669 [(set (match_operand:DF 0 "register_operand" "=&f")
2670 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2671 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2673 [(set_attr "type" "fsqrt")
2674 (set_attr "trap" "yes")
2675 (set_attr "round_suffix" "normal")
2676 (set_attr "trap_suffix" "u_su_sui")])
2678 (define_insn "sqrtdf2"
2679 [(set (match_operand:DF 0 "register_operand" "=f")
2680 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2681 "TARGET_FP && TARGET_FIX"
2683 [(set_attr "type" "fsqrt")
2684 (set_attr "trap" "yes")
2685 (set_attr "round_suffix" "normal")
2686 (set_attr "trap_suffix" "u_su_sui")])
2688 ;; Next are all the integer comparisons, and conditional moves and branches
2689 ;; and some of the related define_expand's and define_split's.
2691 (define_insn "*setcc_internal"
2692 [(set (match_operand 0 "register_operand" "=r")
2693 (match_operator 1 "alpha_comparison_operator"
2694 [(match_operand:DI 2 "register_operand" "r")
2695 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2696 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2697 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2698 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2700 [(set_attr "type" "icmp")])
2702 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2703 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2705 (define_insn "*setcc_swapped_internal"
2706 [(set (match_operand 0 "register_operand" "=r")
2707 (match_operator 1 "alpha_swapped_comparison_operator"
2708 [(match_operand:DI 2 "register_operand" "r")
2709 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2710 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2711 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2712 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2714 [(set_attr "type" "icmp")])
2716 ;; Use match_operator rather than ne directly so that we can match
2717 ;; multiple integer modes.
2718 (define_insn "*setne_internal"
2719 [(set (match_operand 0 "register_operand" "=r")
2720 (match_operator 1 "signed_comparison_operator"
2721 [(match_operand:DI 2 "register_operand" "r")
2723 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2724 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2725 && GET_CODE (operands[1]) == NE
2726 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2728 [(set_attr "type" "icmp")])
2730 ;; The mode folding trick can't be used with const_int operands, since
2731 ;; reload needs to know the proper mode.
2733 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2734 ;; in order to create more pairs of constants. As long as we're allowing
2735 ;; two constants at the same time, and will have to reload one of them...
2737 (define_insn "*movqicc_internal"
2738 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2740 (match_operator 2 "signed_comparison_operator"
2741 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2742 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2743 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2744 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2745 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2751 [(set_attr "type" "icmov")])
2753 (define_insn "*movhicc_internal"
2754 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2756 (match_operator 2 "signed_comparison_operator"
2757 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2758 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2759 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2760 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2761 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2767 [(set_attr "type" "icmov")])
2769 (define_insn "*movsicc_internal"
2770 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2772 (match_operator 2 "signed_comparison_operator"
2773 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2774 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2775 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2776 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2777 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2783 [(set_attr "type" "icmov")])
2785 (define_insn "*movdicc_internal"
2786 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2788 (match_operator 2 "signed_comparison_operator"
2789 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2790 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2791 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2792 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2793 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2799 [(set_attr "type" "icmov")])
2801 (define_insn "*movqicc_lbc"
2802 [(set (match_operand:QI 0 "register_operand" "=r,r")
2804 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2808 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2809 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2814 [(set_attr "type" "icmov")])
2816 (define_insn "*movhicc_lbc"
2817 [(set (match_operand:HI 0 "register_operand" "=r,r")
2819 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2823 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2824 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2829 [(set_attr "type" "icmov")])
2831 (define_insn "*movsicc_lbc"
2832 [(set (match_operand:SI 0 "register_operand" "=r,r")
2834 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2838 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2839 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2844 [(set_attr "type" "icmov")])
2846 (define_insn "*movdicc_lbc"
2847 [(set (match_operand:DI 0 "register_operand" "=r,r")
2849 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2853 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2854 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2859 [(set_attr "type" "icmov")])
2861 (define_insn "*movqicc_lbs"
2862 [(set (match_operand:QI 0 "register_operand" "=r,r")
2864 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2868 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2869 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2874 [(set_attr "type" "icmov")])
2876 (define_insn "*movhicc_lbs"
2877 [(set (match_operand:HI 0 "register_operand" "=r,r")
2879 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2883 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2884 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2889 [(set_attr "type" "icmov")])
2891 (define_insn "*movsicc_lbs"
2892 [(set (match_operand:SI 0 "register_operand" "=r,r")
2894 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2898 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2899 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2904 [(set_attr "type" "icmov")])
2906 (define_insn "*movdicc_lbs"
2907 [(set (match_operand:DI 0 "register_operand" "=r,r")
2909 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2913 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2914 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2919 [(set_attr "type" "icmov")])
2921 ;; For ABS, we have two choices, depending on whether the input and output
2922 ;; registers are the same or not.
2923 (define_expand "absdi2"
2924 [(set (match_operand:DI 0 "register_operand" "")
2925 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2928 if (rtx_equal_p (operands[0], operands[1]))
2929 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2931 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2935 (define_expand "absdi2_same"
2936 [(set (match_operand:DI 1 "register_operand" "")
2937 (neg:DI (match_operand:DI 0 "register_operand" "")))
2939 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2945 (define_expand "absdi2_diff"
2946 [(set (match_operand:DI 0 "register_operand" "")
2947 (neg:DI (match_operand:DI 1 "register_operand" "")))
2949 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2956 [(set (match_operand:DI 0 "register_operand" "")
2957 (abs:DI (match_dup 0)))
2958 (clobber (match_operand:DI 1 "register_operand" ""))]
2960 [(set (match_dup 1) (neg:DI (match_dup 0)))
2961 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2962 (match_dup 0) (match_dup 1)))]
2966 [(set (match_operand:DI 0 "register_operand" "")
2967 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2968 "! rtx_equal_p (operands[0], operands[1])"
2969 [(set (match_dup 0) (neg:DI (match_dup 1)))
2970 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2971 (match_dup 0) (match_dup 1)))]
2975 [(set (match_operand:DI 0 "register_operand" "")
2976 (neg:DI (abs:DI (match_dup 0))))
2977 (clobber (match_operand:DI 1 "register_operand" ""))]
2979 [(set (match_dup 1) (neg:DI (match_dup 0)))
2980 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2981 (match_dup 0) (match_dup 1)))]
2985 [(set (match_operand:DI 0 "register_operand" "")
2986 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2987 "! rtx_equal_p (operands[0], operands[1])"
2988 [(set (match_dup 0) (neg:DI (match_dup 1)))
2989 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2990 (match_dup 0) (match_dup 1)))]
2993 (define_insn "sminqi3"
2994 [(set (match_operand:QI 0 "register_operand" "=r")
2995 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2996 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2999 [(set_attr "type" "mvi")])
3001 (define_insn "uminqi3"
3002 [(set (match_operand:QI 0 "register_operand" "=r")
3003 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3004 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3007 [(set_attr "type" "mvi")])
3009 (define_insn "smaxqi3"
3010 [(set (match_operand:QI 0 "register_operand" "=r")
3011 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3012 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3015 [(set_attr "type" "mvi")])
3017 (define_insn "umaxqi3"
3018 [(set (match_operand:QI 0 "register_operand" "=r")
3019 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3020 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3023 [(set_attr "type" "mvi")])
3025 (define_insn "sminhi3"
3026 [(set (match_operand:HI 0 "register_operand" "=r")
3027 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3028 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3031 [(set_attr "type" "mvi")])
3033 (define_insn "uminhi3"
3034 [(set (match_operand:HI 0 "register_operand" "=r")
3035 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3036 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3039 [(set_attr "type" "mvi")])
3041 (define_insn "smaxhi3"
3042 [(set (match_operand:HI 0 "register_operand" "=r")
3043 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3044 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3047 [(set_attr "type" "mvi")])
3049 (define_insn "umaxhi3"
3050 [(set (match_operand:HI 0 "register_operand" "=r")
3051 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3052 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3055 [(set_attr "type" "shift")])
3057 (define_expand "smaxdi3"
3059 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3060 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3061 (set (match_operand:DI 0 "register_operand" "")
3062 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3063 (match_dup 1) (match_dup 2)))]
3065 { operands[3] = gen_reg_rtx (DImode); })
3068 [(set (match_operand:DI 0 "register_operand" "")
3069 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3070 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3071 (clobber (match_operand:DI 3 "register_operand" ""))]
3072 "operands[2] != const0_rtx"
3073 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3074 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3075 (match_dup 1) (match_dup 2)))]
3078 (define_insn "*smax_const0"
3079 [(set (match_operand:DI 0 "register_operand" "=r")
3080 (smax:DI (match_operand:DI 1 "register_operand" "0")
3084 [(set_attr "type" "icmov")])
3086 (define_expand "smindi3"
3088 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3089 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3090 (set (match_operand:DI 0 "register_operand" "")
3091 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3092 (match_dup 1) (match_dup 2)))]
3094 { operands[3] = gen_reg_rtx (DImode); })
3097 [(set (match_operand:DI 0 "register_operand" "")
3098 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3099 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3100 (clobber (match_operand:DI 3 "register_operand" ""))]
3101 "operands[2] != const0_rtx"
3102 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3103 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3104 (match_dup 1) (match_dup 2)))]
3107 (define_insn "*smin_const0"
3108 [(set (match_operand:DI 0 "register_operand" "=r")
3109 (smin:DI (match_operand:DI 1 "register_operand" "0")
3113 [(set_attr "type" "icmov")])
3115 (define_expand "umaxdi3"
3117 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3118 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3119 (set (match_operand:DI 0 "register_operand" "")
3120 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3121 (match_dup 1) (match_dup 2)))]
3123 "operands[3] = gen_reg_rtx (DImode);")
3126 [(set (match_operand:DI 0 "register_operand" "")
3127 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3128 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3129 (clobber (match_operand:DI 3 "register_operand" ""))]
3130 "operands[2] != const0_rtx"
3131 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3132 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3133 (match_dup 1) (match_dup 2)))]
3136 (define_expand "umindi3"
3138 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3139 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3140 (set (match_operand:DI 0 "register_operand" "")
3141 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3142 (match_dup 1) (match_dup 2)))]
3144 "operands[3] = gen_reg_rtx (DImode);")
3147 [(set (match_operand:DI 0 "register_operand" "")
3148 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3149 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3150 (clobber (match_operand:DI 3 "register_operand" ""))]
3151 "operands[2] != const0_rtx"
3152 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3153 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3154 (match_dup 1) (match_dup 2)))]
3157 (define_insn "*bcc_normal"
3160 (match_operator 1 "signed_comparison_operator"
3161 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3163 (label_ref (match_operand 0 "" ""))
3167 [(set_attr "type" "ibr")])
3169 (define_insn "*bcc_reverse"
3172 (match_operator 1 "signed_comparison_operator"
3173 [(match_operand:DI 2 "register_operand" "r")
3177 (label_ref (match_operand 0 "" ""))))]
3180 [(set_attr "type" "ibr")])
3182 (define_insn "*blbs_normal"
3185 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3189 (label_ref (match_operand 0 "" ""))
3193 [(set_attr "type" "ibr")])
3195 (define_insn "*blbc_normal"
3198 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3202 (label_ref (match_operand 0 "" ""))
3206 [(set_attr "type" "ibr")])
3212 (match_operator 1 "comparison_operator"
3213 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3215 (match_operand:DI 3 "const_int_operand" ""))
3217 (label_ref (match_operand 0 "" ""))
3219 (clobber (match_operand:DI 4 "register_operand" ""))])]
3220 "INTVAL (operands[3]) != 0"
3222 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3224 (if_then_else (match_op_dup 1
3225 [(zero_extract:DI (match_dup 4)
3229 (label_ref (match_dup 0))
3233 ;; The following are the corresponding floating-point insns. Recall
3234 ;; we need to have variants that expand the arguments from SFmode
3237 (define_insn "*cmpdf_ieee"
3238 [(set (match_operand:DF 0 "register_operand" "=&f")
3239 (match_operator:DF 1 "alpha_fp_comparison_operator"
3240 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3241 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3242 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3243 "cmp%-%C1%/ %R2,%R3,%0"
3244 [(set_attr "type" "fadd")
3245 (set_attr "trap" "yes")
3246 (set_attr "trap_suffix" "su")])
3248 (define_insn "*cmpdf_internal"
3249 [(set (match_operand:DF 0 "register_operand" "=f")
3250 (match_operator:DF 1 "alpha_fp_comparison_operator"
3251 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3252 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3253 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3254 "cmp%-%C1%/ %R2,%R3,%0"
3255 [(set_attr "type" "fadd")
3256 (set_attr "trap" "yes")
3257 (set_attr "trap_suffix" "su")])
3259 (define_insn "*cmpdf_ieee_ext1"
3260 [(set (match_operand:DF 0 "register_operand" "=&f")
3261 (match_operator:DF 1 "alpha_fp_comparison_operator"
3263 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3264 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3265 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3266 "cmp%-%C1%/ %R2,%R3,%0"
3267 [(set_attr "type" "fadd")
3268 (set_attr "trap" "yes")
3269 (set_attr "trap_suffix" "su")])
3271 (define_insn "*cmpdf_ext1"
3272 [(set (match_operand:DF 0 "register_operand" "=f")
3273 (match_operator:DF 1 "alpha_fp_comparison_operator"
3275 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3276 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3277 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3278 "cmp%-%C1%/ %R2,%R3,%0"
3279 [(set_attr "type" "fadd")
3280 (set_attr "trap" "yes")
3281 (set_attr "trap_suffix" "su")])
3283 (define_insn "*cmpdf_ieee_ext2"
3284 [(set (match_operand:DF 0 "register_operand" "=&f")
3285 (match_operator:DF 1 "alpha_fp_comparison_operator"
3286 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3288 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3289 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3290 "cmp%-%C1%/ %R2,%R3,%0"
3291 [(set_attr "type" "fadd")
3292 (set_attr "trap" "yes")
3293 (set_attr "trap_suffix" "su")])
3295 (define_insn "*cmpdf_ext2"
3296 [(set (match_operand:DF 0 "register_operand" "=f")
3297 (match_operator:DF 1 "alpha_fp_comparison_operator"
3298 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3300 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3301 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3302 "cmp%-%C1%/ %R2,%R3,%0"
3303 [(set_attr "type" "fadd")
3304 (set_attr "trap" "yes")
3305 (set_attr "trap_suffix" "su")])
3307 (define_insn "*cmpdf_ieee_ext3"
3308 [(set (match_operand:DF 0 "register_operand" "=&f")
3309 (match_operator:DF 1 "alpha_fp_comparison_operator"
3311 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3313 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3314 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3315 "cmp%-%C1%/ %R2,%R3,%0"
3316 [(set_attr "type" "fadd")
3317 (set_attr "trap" "yes")
3318 (set_attr "trap_suffix" "su")])
3320 (define_insn "*cmpdf_ext3"
3321 [(set (match_operand:DF 0 "register_operand" "=f")
3322 (match_operator:DF 1 "alpha_fp_comparison_operator"
3324 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3326 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3327 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3328 "cmp%-%C1%/ %R2,%R3,%0"
3329 [(set_attr "type" "fadd")
3330 (set_attr "trap" "yes")
3331 (set_attr "trap_suffix" "su")])
3333 (define_insn "*movdfcc_internal"
3334 [(set (match_operand:DF 0 "register_operand" "=f,f")
3336 (match_operator 3 "signed_comparison_operator"
3337 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3338 (match_operand:DF 2 "fp0_operand" "G,G")])
3339 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3340 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3344 fcmov%D3 %R4,%R5,%0"
3345 [(set_attr "type" "fcmov")])
3347 (define_insn "*movsfcc_internal"
3348 [(set (match_operand:SF 0 "register_operand" "=f,f")
3350 (match_operator 3 "signed_comparison_operator"
3351 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3352 (match_operand:DF 2 "fp0_operand" "G,G")])
3353 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3354 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3358 fcmov%D3 %R4,%R5,%0"
3359 [(set_attr "type" "fcmov")])
3361 (define_insn "*movdfcc_ext1"
3362 [(set (match_operand:DF 0 "register_operand" "=f,f")
3364 (match_operator 3 "signed_comparison_operator"
3365 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3366 (match_operand:DF 2 "fp0_operand" "G,G")])
3367 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3368 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3372 fcmov%D3 %R4,%R5,%0"
3373 [(set_attr "type" "fcmov")])
3375 (define_insn "*movdfcc_ext2"
3376 [(set (match_operand:DF 0 "register_operand" "=f,f")
3378 (match_operator 3 "signed_comparison_operator"
3380 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3381 (match_operand:DF 2 "fp0_operand" "G,G")])
3382 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3383 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3387 fcmov%D3 %R4,%R5,%0"
3388 [(set_attr "type" "fcmov")])
3390 (define_insn "*movdfcc_ext3"
3391 [(set (match_operand:SF 0 "register_operand" "=f,f")
3393 (match_operator 3 "signed_comparison_operator"
3395 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3396 (match_operand:DF 2 "fp0_operand" "G,G")])
3397 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3398 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3402 fcmov%D3 %R4,%R5,%0"
3403 [(set_attr "type" "fcmov")])
3405 (define_insn "*movdfcc_ext4"
3406 [(set (match_operand:DF 0 "register_operand" "=f,f")
3408 (match_operator 3 "signed_comparison_operator"
3410 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3411 (match_operand:DF 2 "fp0_operand" "G,G")])
3412 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3413 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3417 fcmov%D3 %R4,%R5,%0"
3418 [(set_attr "type" "fcmov")])
3420 (define_expand "maxdf3"
3422 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3423 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3424 (set (match_operand:DF 0 "register_operand" "")
3425 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3426 (match_dup 1) (match_dup 2)))]
3429 operands[3] = gen_reg_rtx (DFmode);
3430 operands[4] = CONST0_RTX (DFmode);
3433 (define_expand "mindf3"
3435 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3436 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3437 (set (match_operand:DF 0 "register_operand" "")
3438 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3439 (match_dup 1) (match_dup 2)))]
3442 operands[3] = gen_reg_rtx (DFmode);
3443 operands[4] = CONST0_RTX (DFmode);
3446 (define_expand "maxsf3"
3448 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3449 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3450 (set (match_operand:SF 0 "register_operand" "")
3451 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3452 (match_dup 1) (match_dup 2)))]
3455 operands[3] = gen_reg_rtx (DFmode);
3456 operands[4] = CONST0_RTX (DFmode);
3459 (define_expand "minsf3"
3461 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3462 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3463 (set (match_operand:SF 0 "register_operand" "")
3464 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3465 (match_dup 1) (match_dup 2)))]
3468 operands[3] = gen_reg_rtx (DFmode);
3469 operands[4] = CONST0_RTX (DFmode);
3472 (define_insn "*fbcc_normal"
3475 (match_operator 1 "signed_comparison_operator"
3476 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3477 (match_operand:DF 3 "fp0_operand" "G")])
3478 (label_ref (match_operand 0 "" ""))
3482 [(set_attr "type" "fbr")])
3484 (define_insn "*fbcc_ext_normal"
3487 (match_operator 1 "signed_comparison_operator"
3489 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3490 (match_operand:DF 3 "fp0_operand" "G")])
3491 (label_ref (match_operand 0 "" ""))
3495 [(set_attr "type" "fbr")])
3497 ;; These are the main define_expand's used to make conditional branches
3500 (define_expand "cmpdf"
3501 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3502 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3505 alpha_compare.op0 = operands[0];
3506 alpha_compare.op1 = operands[1];
3507 alpha_compare.fp_p = 1;
3511 (define_expand "cmptf"
3512 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3513 (match_operand:TF 1 "general_operand" "")))]
3514 "TARGET_HAS_XFLOATING_LIBS"
3516 alpha_compare.op0 = operands[0];
3517 alpha_compare.op1 = operands[1];
3518 alpha_compare.fp_p = 1;
3522 (define_expand "cmpdi"
3523 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3524 (match_operand:DI 1 "general_operand" "")))]
3527 alpha_compare.op0 = operands[0];
3528 alpha_compare.op1 = operands[1];
3529 alpha_compare.fp_p = 0;
3533 (define_expand "beq"
3535 (if_then_else (match_dup 1)
3536 (label_ref (match_operand 0 "" ""))
3539 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3541 (define_expand "bne"
3543 (if_then_else (match_dup 1)
3544 (label_ref (match_operand 0 "" ""))
3547 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3549 (define_expand "blt"
3551 (if_then_else (match_dup 1)
3552 (label_ref (match_operand 0 "" ""))
3555 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3557 (define_expand "ble"
3559 (if_then_else (match_dup 1)
3560 (label_ref (match_operand 0 "" ""))
3563 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3565 (define_expand "bgt"
3567 (if_then_else (match_dup 1)
3568 (label_ref (match_operand 0 "" ""))
3571 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3573 (define_expand "bge"
3575 (if_then_else (match_dup 1)
3576 (label_ref (match_operand 0 "" ""))
3579 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3581 (define_expand "bltu"
3583 (if_then_else (match_dup 1)
3584 (label_ref (match_operand 0 "" ""))
3587 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3589 (define_expand "bleu"
3591 (if_then_else (match_dup 1)
3592 (label_ref (match_operand 0 "" ""))
3595 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3597 (define_expand "bgtu"
3599 (if_then_else (match_dup 1)
3600 (label_ref (match_operand 0 "" ""))
3603 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3605 (define_expand "bgeu"
3607 (if_then_else (match_dup 1)
3608 (label_ref (match_operand 0 "" ""))
3611 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3613 (define_expand "bunordered"
3615 (if_then_else (match_dup 1)
3616 (label_ref (match_operand 0 "" ""))
3619 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3621 (define_expand "bordered"
3623 (if_then_else (match_dup 1)
3624 (label_ref (match_operand 0 "" ""))
3627 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3629 (define_expand "seq"
3630 [(set (match_operand:DI 0 "register_operand" "")
3633 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3635 (define_expand "sne"
3636 [(set (match_operand:DI 0 "register_operand" "")
3639 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3641 (define_expand "slt"
3642 [(set (match_operand:DI 0 "register_operand" "")
3645 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3647 (define_expand "sle"
3648 [(set (match_operand:DI 0 "register_operand" "")
3651 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3653 (define_expand "sgt"
3654 [(set (match_operand:DI 0 "register_operand" "")
3657 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3659 (define_expand "sge"
3660 [(set (match_operand:DI 0 "register_operand" "")
3663 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3665 (define_expand "sltu"
3666 [(set (match_operand:DI 0 "register_operand" "")
3669 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3671 (define_expand "sleu"
3672 [(set (match_operand:DI 0 "register_operand" "")
3675 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3677 (define_expand "sgtu"
3678 [(set (match_operand:DI 0 "register_operand" "")
3681 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3683 (define_expand "sgeu"
3684 [(set (match_operand:DI 0 "register_operand" "")
3687 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3689 (define_expand "sunordered"
3690 [(set (match_operand:DI 0 "register_operand" "")
3693 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3695 (define_expand "sordered"
3696 [(set (match_operand:DI 0 "register_operand" "")
3699 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3701 ;; These are the main define_expand's used to make conditional moves.
3703 (define_expand "movsicc"
3704 [(set (match_operand:SI 0 "register_operand" "")
3705 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3706 (match_operand:SI 2 "reg_or_8bit_operand" "")
3707 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3710 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3714 (define_expand "movdicc"
3715 [(set (match_operand:DI 0 "register_operand" "")
3716 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3717 (match_operand:DI 2 "reg_or_8bit_operand" "")
3718 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3721 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3725 (define_expand "movsfcc"
3726 [(set (match_operand:SF 0 "register_operand" "")
3727 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3728 (match_operand:SF 2 "reg_or_8bit_operand" "")
3729 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3732 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3736 (define_expand "movdfcc"
3737 [(set (match_operand:DF 0 "register_operand" "")
3738 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3739 (match_operand:DF 2 "reg_or_8bit_operand" "")
3740 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3743 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3747 ;; These define_split definitions are used in cases when comparisons have
3748 ;; not be stated in the correct way and we need to reverse the second
3749 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3750 ;; comparison that tests the result being reversed. We have one define_split
3751 ;; for each use of a comparison. They do not match valid insns and need
3752 ;; not generate valid insns.
3754 ;; We can also handle equality comparisons (and inequality comparisons in
3755 ;; cases where the resulting add cannot overflow) by doing an add followed by
3756 ;; a comparison with zero. This is faster since the addition takes one
3757 ;; less cycle than a compare when feeding into a conditional move.
3758 ;; For this case, we also have an SImode pattern since we can merge the add
3759 ;; and sign extend and the order doesn't matter.
3761 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3762 ;; operation could have been generated.
3765 [(set (match_operand:DI 0 "register_operand" "")
3767 (match_operator 1 "comparison_operator"
3768 [(match_operand:DI 2 "reg_or_0_operand" "")
3769 (match_operand:DI 3 "reg_or_cint_operand" "")])
3770 (match_operand:DI 4 "reg_or_cint_operand" "")
3771 (match_operand:DI 5 "reg_or_cint_operand" "")))
3772 (clobber (match_operand:DI 6 "register_operand" ""))]
3773 "operands[3] != const0_rtx"
3774 [(set (match_dup 6) (match_dup 7))
3776 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3778 enum rtx_code code = GET_CODE (operands[1]);
3779 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3781 /* If we are comparing for equality with a constant and that constant
3782 appears in the arm when the register equals the constant, use the
3783 register since that is more likely to match (and to produce better code
3786 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3787 && rtx_equal_p (operands[4], operands[3]))
3788 operands[4] = operands[2];
3790 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3791 && rtx_equal_p (operands[5], operands[3]))
3792 operands[5] = operands[2];
3794 if (code == NE || code == EQ
3795 || (extended_count (operands[2], DImode, unsignedp) >= 1
3796 && extended_count (operands[3], DImode, unsignedp) >= 1))
3798 if (GET_CODE (operands[3]) == CONST_INT)
3799 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3800 GEN_INT (- INTVAL (operands[3])));
3802 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3804 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3807 else if (code == EQ || code == LE || code == LT
3808 || code == LEU || code == LTU)
3810 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3811 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3815 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3816 operands[2], operands[3]);
3817 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3822 [(set (match_operand:DI 0 "register_operand" "")
3824 (match_operator 1 "comparison_operator"
3825 [(match_operand:SI 2 "reg_or_0_operand" "")
3826 (match_operand:SI 3 "reg_or_cint_operand" "")])
3827 (match_operand:DI 4 "reg_or_8bit_operand" "")
3828 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3829 (clobber (match_operand:DI 6 "register_operand" ""))]
3830 "operands[3] != const0_rtx
3831 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3832 [(set (match_dup 6) (match_dup 7))
3834 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3836 enum rtx_code code = GET_CODE (operands[1]);
3837 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3840 if ((code != NE && code != EQ
3841 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3842 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3845 if (GET_CODE (operands[3]) == CONST_INT)
3846 tem = gen_rtx_PLUS (SImode, operands[2],
3847 GEN_INT (- INTVAL (operands[3])));
3849 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3851 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3852 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3853 operands[6], const0_rtx);
3859 (match_operator 1 "comparison_operator"
3860 [(match_operand:DI 2 "reg_or_0_operand" "")
3861 (match_operand:DI 3 "reg_or_cint_operand" "")])
3862 (label_ref (match_operand 0 "" ""))
3864 (clobber (match_operand:DI 4 "register_operand" ""))]
3865 "operands[3] != const0_rtx"
3866 [(set (match_dup 4) (match_dup 5))
3867 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3869 enum rtx_code code = GET_CODE (operands[1]);
3870 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3872 if (code == NE || code == EQ
3873 || (extended_count (operands[2], DImode, unsignedp) >= 1
3874 && extended_count (operands[3], DImode, unsignedp) >= 1))
3876 if (GET_CODE (operands[3]) == CONST_INT)
3877 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3878 GEN_INT (- INTVAL (operands[3])));
3880 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3882 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3885 else if (code == EQ || code == LE || code == LT
3886 || code == LEU || code == LTU)
3888 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3889 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3893 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3894 operands[2], operands[3]);
3895 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3902 (match_operator 1 "comparison_operator"
3903 [(match_operand:SI 2 "reg_or_0_operand" "")
3904 (match_operand:SI 3 "const_int_operand" "")])
3905 (label_ref (match_operand 0 "" ""))
3907 (clobber (match_operand:DI 4 "register_operand" ""))]
3908 "operands[3] != const0_rtx
3909 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3910 [(set (match_dup 4) (match_dup 5))
3911 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3915 if (GET_CODE (operands[3]) == CONST_INT)
3916 tem = gen_rtx_PLUS (SImode, operands[2],
3917 GEN_INT (- INTVAL (operands[3])));
3919 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3921 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3922 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3923 operands[4], const0_rtx);
3926 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3927 ;; This eliminates one, and sometimes two, insns when the AND can be done
3930 [(set (match_operand:DI 0 "register_operand" "")
3931 (match_operator:DI 1 "comparison_operator"
3932 [(match_operand:DI 2 "register_operand" "")
3933 (match_operand:DI 3 "const_int_operand" "")]))
3934 (clobber (match_operand:DI 4 "register_operand" ""))]
3935 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3936 && (GET_CODE (operands[1]) == GTU
3937 || GET_CODE (operands[1]) == LEU
3938 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3939 && extended_count (operands[2], DImode, 1) > 0))"
3940 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3941 (set (match_dup 0) (match_dup 6))]
3943 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3944 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3945 || GET_CODE (operands[1]) == GT)
3947 DImode, operands[4], const0_rtx);
3950 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
3953 [(set (match_operand 0 "register_operand" "")
3954 (if_then_else (match_operator 1 "signed_comparison_operator"
3955 [(match_operand:DI 2 "reg_or_0_operand" "")
3957 (match_operand 3 "const_int_operand" "")
3958 (match_operand 4 "const_int_operand" "")))]
3962 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
3963 operands[2], operands[3], operands[4]))
3969 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
3970 ;; Oh well, we match it in movcc, so it must be partially our fault.
3972 [(set (match_operand 0 "register_operand" "")
3973 (if_then_else (match_operator 1 "signed_comparison_operator"
3975 (match_operand:DI 2 "reg_or_0_operand" "")])
3976 (match_operand 3 "const_int_operand" "")
3977 (match_operand 4 "const_int_operand" "")))]
3981 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
3982 operands[0], operands[2], operands[3],
3989 (define_insn_and_split "*cmp_sadd_di"
3990 [(set (match_operand:DI 0 "register_operand" "=r")
3991 (plus:DI (if_then_else:DI
3992 (match_operator 1 "alpha_zero_comparison_operator"
3993 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3995 (match_operand:DI 3 "const48_operand" "I")
3997 (match_operand:DI 4 "sext_add_operand" "rIO")))
3998 (clobber (match_scratch:DI 5 "=r"))]
4001 "! no_new_pseudos || reload_completed"
4003 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4005 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4008 if (! no_new_pseudos)
4009 operands[5] = gen_reg_rtx (DImode);
4010 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4011 operands[5] = operands[0];
4014 (define_insn_and_split "*cmp_sadd_si"
4015 [(set (match_operand:SI 0 "register_operand" "=r")
4016 (plus:SI (if_then_else:SI
4017 (match_operator 1 "alpha_zero_comparison_operator"
4018 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4020 (match_operand:SI 3 "const48_operand" "I")
4022 (match_operand:SI 4 "sext_add_operand" "rIO")))
4023 (clobber (match_scratch:SI 5 "=r"))]
4026 "! no_new_pseudos || reload_completed"
4028 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4030 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4033 if (! no_new_pseudos)
4034 operands[5] = gen_reg_rtx (DImode);
4035 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4036 operands[5] = operands[0];
4039 (define_insn_and_split "*cmp_sadd_sidi"
4040 [(set (match_operand:DI 0 "register_operand" "=r")
4042 (plus:SI (if_then_else:SI
4043 (match_operator 1 "alpha_zero_comparison_operator"
4044 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4046 (match_operand:SI 3 "const48_operand" "I")
4048 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4049 (clobber (match_scratch:SI 5 "=r"))]
4052 "! no_new_pseudos || reload_completed"
4054 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4056 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4059 if (! no_new_pseudos)
4060 operands[5] = gen_reg_rtx (DImode);
4061 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4062 operands[5] = operands[0];
4065 (define_insn_and_split "*cmp_ssub_di"
4066 [(set (match_operand:DI 0 "register_operand" "=r")
4067 (minus:DI (if_then_else:DI
4068 (match_operator 1 "alpha_zero_comparison_operator"
4069 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4071 (match_operand:DI 3 "const48_operand" "I")
4073 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4074 (clobber (match_scratch:DI 5 "=r"))]
4077 "! no_new_pseudos || reload_completed"
4079 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4081 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4084 if (! no_new_pseudos)
4085 operands[5] = gen_reg_rtx (DImode);
4086 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4087 operands[5] = operands[0];
4090 (define_insn_and_split "*cmp_ssub_si"
4091 [(set (match_operand:SI 0 "register_operand" "=r")
4092 (minus:SI (if_then_else:SI
4093 (match_operator 1 "alpha_zero_comparison_operator"
4094 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4096 (match_operand:SI 3 "const48_operand" "I")
4098 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4099 (clobber (match_scratch:SI 5 "=r"))]
4102 "! no_new_pseudos || reload_completed"
4104 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4106 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4109 if (! no_new_pseudos)
4110 operands[5] = gen_reg_rtx (DImode);
4111 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4112 operands[5] = operands[0];
4115 (define_insn_and_split "*cmp_ssub_sidi"
4116 [(set (match_operand:DI 0 "register_operand" "=r")
4118 (minus:SI (if_then_else:SI
4119 (match_operator 1 "alpha_zero_comparison_operator"
4120 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4122 (match_operand:SI 3 "const48_operand" "I")
4124 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4125 (clobber (match_scratch:SI 5 "=r"))]
4128 "! no_new_pseudos || reload_completed"
4130 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4132 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4135 if (! no_new_pseudos)
4136 operands[5] = gen_reg_rtx (DImode);
4137 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4138 operands[5] = operands[0];
4141 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4142 ;; work differently, so we have different patterns for each.
4144 (define_expand "call"
4145 [(use (match_operand:DI 0 "" ""))
4146 (use (match_operand 1 "" ""))
4147 (use (match_operand 2 "" ""))
4148 (use (match_operand 3 "" ""))]
4151 if (TARGET_ABI_WINDOWS_NT)
4152 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4153 else if (TARGET_ABI_OPEN_VMS)
4154 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4156 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4160 (define_expand "sibcall"
4161 [(call (mem:DI (match_operand 0 "" ""))
4162 (match_operand 1 "" ""))]
4165 if (GET_CODE (operands[0]) != MEM)
4167 operands[0] = XEXP (operands[0], 0);
4170 (define_expand "call_osf"
4171 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4172 (match_operand 1 "" ""))
4173 (clobber (reg:DI 27))
4174 (clobber (reg:DI 26))])]
4177 if (GET_CODE (operands[0]) != MEM)
4180 operands[0] = XEXP (operands[0], 0);
4182 if (GET_CODE (operands[0]) != SYMBOL_REF
4183 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
4185 rtx tem = gen_rtx_REG (DImode, 27);
4186 emit_move_insn (tem, operands[0]);
4191 (define_expand "call_nt"
4192 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4193 (match_operand 1 "" ""))
4194 (clobber (reg:DI 26))])]
4197 if (GET_CODE (operands[0]) != MEM)
4200 operands[0] = XEXP (operands[0], 0);
4201 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4202 operands[0] = force_reg (DImode, operands[0]);
4206 ;; call openvms/alpha
4207 ;; op 0: symbol ref for called function
4208 ;; op 1: next_arg_reg (argument information value for R25)
4210 (define_expand "call_vms"
4211 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4212 (match_operand 1 "" ""))
4216 (clobber (reg:DI 27))])]
4219 if (GET_CODE (operands[0]) != MEM)
4222 operands[0] = XEXP (operands[0], 0);
4224 /* Always load AI with argument information, then handle symbolic and
4225 indirect call differently. Load RA and set operands[2] to PV in
4228 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4229 if (GET_CODE (operands[0]) == SYMBOL_REF)
4231 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4233 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4235 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4239 emit_move_insn (gen_rtx_REG (Pmode, 26),
4240 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4241 operands[2] = operands[0];
4246 (define_expand "call_value"
4247 [(use (match_operand 0 "" ""))
4248 (use (match_operand:DI 1 "" ""))
4249 (use (match_operand 2 "" ""))
4250 (use (match_operand 3 "" ""))
4251 (use (match_operand 4 "" ""))]
4254 if (TARGET_ABI_WINDOWS_NT)
4255 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4256 else if (TARGET_ABI_OPEN_VMS)
4257 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4260 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4265 (define_expand "sibcall_value"
4266 [(set (match_operand 0 "" "")
4267 (call (mem:DI (match_operand 1 "" ""))
4268 (match_operand 2 "" "")))]
4271 if (GET_CODE (operands[1]) != MEM)
4273 operands[1] = XEXP (operands[1], 0);
4276 (define_expand "call_value_osf"
4277 [(parallel [(set (match_operand 0 "" "")
4278 (call (mem:DI (match_operand 1 "" ""))
4279 (match_operand 2 "" "")))
4280 (clobber (reg:DI 27))
4281 (clobber (reg:DI 26))])]
4284 if (GET_CODE (operands[1]) != MEM)
4287 operands[1] = XEXP (operands[1], 0);
4289 if (GET_CODE (operands[1]) != SYMBOL_REF
4290 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
4292 rtx tem = gen_rtx_REG (DImode, 27);
4293 emit_move_insn (tem, operands[1]);
4298 (define_expand "call_value_nt"
4299 [(parallel [(set (match_operand 0 "" "")
4300 (call (mem:DI (match_operand 1 "" ""))
4301 (match_operand 2 "" "")))
4302 (clobber (reg:DI 26))])]
4305 if (GET_CODE (operands[1]) != MEM)
4308 operands[1] = XEXP (operands[1], 0);
4309 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4310 operands[1] = force_reg (DImode, operands[1]);
4313 (define_expand "call_value_vms"
4314 [(parallel [(set (match_operand 0 "" "")
4315 (call (mem:DI (match_operand:DI 1 "" ""))
4316 (match_operand 2 "" "")))
4320 (clobber (reg:DI 27))])]
4323 if (GET_CODE (operands[1]) != MEM)
4326 operands[1] = XEXP (operands[1], 0);
4328 /* Always load AI with argument information, then handle symbolic and
4329 indirect call differently. Load RA and set operands[3] to PV in
4332 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4333 if (GET_CODE (operands[1]) == SYMBOL_REF)
4335 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4337 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4339 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4343 emit_move_insn (gen_rtx_REG (Pmode, 26),
4344 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4345 operands[3] = operands[1];
4349 (define_insn "*call_osf_1_noreturn"
4350 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4351 (match_operand 1 "" ""))
4352 (clobber (reg:DI 27))
4353 (clobber (reg:DI 26))]
4354 "TARGET_ABI_OSF && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4359 [(set_attr "type" "jsr")
4360 (set_attr "length" "*,*,8")])
4362 (define_insn "*call_osf_1"
4363 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4364 (match_operand 1 "" ""))
4365 (clobber (reg:DI 27))
4366 (clobber (reg:DI 26))]
4369 jsr $26,($27),0\;ldgp $29,0($26)
4371 jsr $26,%0\;ldgp $29,0($26)"
4372 [(set_attr "type" "jsr")
4373 (set_attr "length" "12,*,16")])
4375 (define_insn "*sibcall_osf_1"
4376 [(call (mem:DI (match_operand:DI 0 "call_operand" "R,i"))
4377 (match_operand 1 "" ""))]
4382 [(set_attr "type" "jsr")
4383 (set_attr "length" "*,8")])
4385 (define_insn "*call_nt_1"
4386 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4387 (match_operand 1 "" ""))
4388 (clobber (reg:DI 26))]
4389 "TARGET_ABI_WINDOWS_NT"
4394 [(set_attr "type" "jsr")
4395 (set_attr "length" "*,*,12")])
4397 (define_insn "*call_vms_1"
4398 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
4399 (match_operand 1 "" ""))
4400 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4403 (clobber (reg:DI 27))]
4404 "TARGET_ABI_OPEN_VMS"
4406 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4407 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4408 [(set_attr "type" "jsr")
4409 (set_attr "length" "12,16")])
4411 ;; Call subroutine returning any type.
4413 (define_expand "untyped_call"
4414 [(parallel [(call (match_operand 0 "" "")
4416 (match_operand 1 "" "")
4417 (match_operand 2 "" "")])]
4422 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4424 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4426 rtx set = XVECEXP (operands[2], 0, i);
4427 emit_move_insn (SET_DEST (set), SET_SRC (set));
4430 /* The optimizer does not know that the call sets the function value
4431 registers we stored in the result block. We avoid problems by
4432 claiming that all hard registers are used and clobbered at this
4434 emit_insn (gen_blockage ());
4439 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4440 ;; all of memory. This blocks insns from being moved across this point.
4442 (define_insn "blockage"
4443 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4446 [(set_attr "length" "0")])
4450 (label_ref (match_operand 0 "" "")))]
4453 [(set_attr "type" "ibr")])
4455 (define_expand "return"
4460 (define_insn "*return_internal"
4464 [(set_attr "type" "ibr")])
4466 (define_insn "indirect_jump"
4467 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4470 [(set_attr "type" "ibr")])
4472 (define_expand "tablejump"
4473 [(use (match_operand:SI 0 "register_operand" ""))
4474 (use (match_operand:SI 1 "" ""))]
4477 if (TARGET_ABI_WINDOWS_NT)
4478 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4479 else if (TARGET_ABI_OPEN_VMS)
4480 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4482 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4487 (define_expand "tablejump_osf"
4489 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4491 (plus:DI (reg:DI 29) (match_dup 3)))
4492 (parallel [(set (pc)
4494 (use (label_ref (match_operand 1 "" "")))])]
4496 { operands[3] = gen_reg_rtx (DImode); })
4498 (define_expand "tablejump_nt"
4500 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4501 (parallel [(set (pc)
4503 (use (label_ref (match_operand 1 "" "")))])]
4505 { operands[3] = gen_reg_rtx (DImode); })
4508 ;; tablejump, openVMS way
4510 ;; op 1: label preceding jump-table
4512 (define_expand "tablejump_vms"
4514 (match_operand:DI 0 "register_operand" ""))
4516 (plus:DI (match_dup 2)
4517 (label_ref (match_operand 1 "" ""))))]
4519 { operands[2] = gen_reg_rtx (DImode); })
4521 (define_insn "*tablejump_osf_nt_internal"
4523 (match_operand:DI 0 "register_operand" "r"))
4524 (use (label_ref (match_operand 1 "" "")))]
4525 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4526 && alpha_tablejump_addr_vec (insn)"
4528 operands[2] = alpha_tablejump_best_label (insn);
4529 return "jmp $31,(%0),%2";
4531 [(set_attr "type" "ibr")])
4534 ;; op 0 is table offset
4535 ;; op 1 is table label
4538 (define_insn "*tablejump_vms_internal"
4540 (plus (match_operand:DI 0 "register_operand" "r")
4541 (label_ref (match_operand 1 "" ""))))]
4542 "TARGET_ABI_OPEN_VMS"
4544 [(set_attr "type" "ibr")])
4546 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4547 ;; want to have to include pal.h in our .s file.
4549 ;; Technically the type for call_pal is jsr, but we use that for determining
4550 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4553 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4556 [(set_attr "type" "ibr")])
4558 ;; Finally, we have the basic data motion insns. The byte and word insns
4559 ;; are done via define_expand. Start with the floating-point insns, since
4560 ;; they are simpler.
4562 (define_insn "*movsf_nofix"
4563 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4564 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4565 "TARGET_FPREGS && ! TARGET_FIX
4566 && (register_operand (operands[0], SFmode)
4567 || reg_or_fp0_operand (operands[1], SFmode))"
4575 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4577 (define_insn "*movsf_fix"
4578 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4579 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4580 "TARGET_FPREGS && TARGET_FIX
4581 && (register_operand (operands[0], SFmode)
4582 || reg_or_fp0_operand (operands[1], SFmode))"
4592 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4594 (define_insn "*movsf_nofp"
4595 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4596 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4598 && (register_operand (operands[0], SFmode)
4599 || reg_or_fp0_operand (operands[1], SFmode))"
4604 [(set_attr "type" "ilog,ild,ist")])
4606 (define_insn "*movdf_nofix"
4607 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4608 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4609 "TARGET_FPREGS && ! TARGET_FIX
4610 && (register_operand (operands[0], DFmode)
4611 || reg_or_fp0_operand (operands[1], DFmode))"
4619 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4621 (define_insn "*movdf_fix"
4622 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4623 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4624 "TARGET_FPREGS && TARGET_FIX
4625 && (register_operand (operands[0], DFmode)
4626 || reg_or_fp0_operand (operands[1], DFmode))"
4636 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4638 (define_insn "*movdf_nofp"
4639 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4640 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4642 && (register_operand (operands[0], DFmode)
4643 || reg_or_fp0_operand (operands[1], DFmode))"
4648 [(set_attr "type" "ilog,ild,ist")])
4650 ;; Subregs suck for register allocation. Pretend we can move TFmode
4651 ;; data between general registers until after reload.
4653 (define_insn_and_split "*movtf_internal"
4654 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4655 (match_operand:TF 1 "input_operand" "roG,rG"))]
4656 "register_operand (operands[0], TFmode)
4657 || reg_or_fp0_operand (operands[1], TFmode)"
4660 [(set (match_dup 0) (match_dup 2))
4661 (set (match_dup 1) (match_dup 3))]
4663 alpha_split_tfmode_pair (operands);
4664 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4667 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4668 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4672 (define_expand "movsf"
4673 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4674 (match_operand:SF 1 "general_operand" ""))]
4677 if (GET_CODE (operands[0]) == MEM
4678 && ! reg_or_fp0_operand (operands[1], SFmode))
4679 operands[1] = force_reg (SFmode, operands[1]);
4682 (define_expand "movdf"
4683 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4684 (match_operand:DF 1 "general_operand" ""))]
4687 if (GET_CODE (operands[0]) == MEM
4688 && ! reg_or_fp0_operand (operands[1], DFmode))
4689 operands[1] = force_reg (DFmode, operands[1]);
4692 (define_expand "movtf"
4693 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4694 (match_operand:TF 1 "general_operand" ""))]
4697 if (GET_CODE (operands[0]) == MEM
4698 && ! reg_or_fp0_operand (operands[1], TFmode))
4699 operands[1] = force_reg (TFmode, operands[1]);
4702 (define_insn "*movsi_nofix"
4703 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4704 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4705 "TARGET_ABI_OSF && ! TARGET_FIX
4706 && (register_operand (operands[0], SImode)
4707 || reg_or_0_operand (operands[1], SImode))"
4717 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4719 (define_insn "*movsi_fix"
4720 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4721 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4722 "TARGET_ABI_OSF && TARGET_FIX
4723 && (register_operand (operands[0], SImode)
4724 || reg_or_0_operand (operands[1], SImode))"
4736 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4738 (define_insn "*movsi_nt_vms"
4739 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4740 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4741 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
4742 && (register_operand (operands[0], SImode)
4743 || reg_or_0_operand (operands[1], SImode))"
4754 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4756 (define_insn "*movhi_nobwx"
4757 [(set (match_operand:HI 0 "register_operand" "=r,r")
4758 (match_operand:HI 1 "input_operand" "rJ,n"))]
4760 && (register_operand (operands[0], HImode)
4761 || register_operand (operands[1], HImode))"
4765 [(set_attr "type" "ilog,iadd")])
4767 (define_insn "*movhi_bwx"
4768 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4769 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4771 && (register_operand (operands[0], HImode)
4772 || reg_or_0_operand (operands[1], HImode))"
4778 [(set_attr "type" "ilog,iadd,ild,ist")])
4780 (define_insn "*movqi_nobwx"
4781 [(set (match_operand:QI 0 "register_operand" "=r,r")
4782 (match_operand:QI 1 "input_operand" "rJ,n"))]
4784 && (register_operand (operands[0], QImode)
4785 || register_operand (operands[1], QImode))"
4789 [(set_attr "type" "ilog,iadd")])
4791 (define_insn "*movqi_bwx"
4792 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4793 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4795 && (register_operand (operands[0], QImode)
4796 || reg_or_0_operand (operands[1], QImode))"
4802 [(set_attr "type" "ilog,iadd,ild,ist")])
4804 ;; We do two major things here: handle mem->mem and construct long
4807 (define_expand "movsi"
4808 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4809 (match_operand:SI 1 "general_operand" ""))]
4812 if (GET_CODE (operands[0]) == MEM
4813 && ! reg_or_0_operand (operands[1], SImode))
4814 operands[1] = force_reg (SImode, operands[1]);
4816 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4818 else if (GET_CODE (operands[1]) == CONST_INT)
4821 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4822 if (rtx_equal_p (operands[0], operands[1]))
4827 ;; Split a load of a large constant into the appropriate two-insn
4831 [(set (match_operand:SI 0 "register_operand" "")
4832 (match_operand:SI 1 "const_int_operand" ""))]
4833 "! add_operand (operands[1], SImode)"
4834 [(set (match_dup 0) (match_dup 2))
4835 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4838 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4840 if (tem == operands[0])
4846 (define_insn "*movdi_nofix"
4847 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4848 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4850 && (register_operand (operands[0], DImode)
4851 || reg_or_0_operand (operands[1], DImode))"
4862 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4864 (define_insn "*movdi_fix"
4865 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4866 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4868 && (register_operand (operands[0], DImode)
4869 || reg_or_0_operand (operands[1], DImode))"
4882 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4884 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
4885 ;; often appears dead to the life analysis code, at which point we
4886 ;; abort for emitting dead prologue instructions. Force this live.
4888 (define_insn "force_movdi"
4889 [(set (match_operand:DI 0 "register_operand" "=r")
4890 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
4891 UNSPECV_FORCE_MOV))]
4894 [(set_attr "type" "ilog")])
4896 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4897 ;; memory, and construct long 32-bit constants.
4899 (define_expand "movdi"
4900 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4901 (match_operand:DI 1 "general_operand" ""))]
4906 if (GET_CODE (operands[0]) == MEM
4907 && ! reg_or_0_operand (operands[1], DImode))
4908 operands[1] = force_reg (DImode, operands[1]);
4910 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4912 else if (GET_CODE (operands[1]) == CONST_INT
4913 && (tem = alpha_emit_set_const (operands[0], DImode,
4914 INTVAL (operands[1]), 3)) != 0)
4916 if (rtx_equal_p (tem, operands[0]))
4921 else if (CONSTANT_P (operands[1]))
4923 if (TARGET_BUILD_CONSTANTS)
4925 HOST_WIDE_INT i0, i1;
4927 if (GET_CODE (operands[1]) == CONST_INT)
4929 i0 = INTVAL (operands[1]);
4932 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4934 #if HOST_BITS_PER_WIDE_INT >= 64
4935 i0 = CONST_DOUBLE_LOW (operands[1]);
4938 i0 = CONST_DOUBLE_LOW (operands[1]);
4939 i1 = CONST_DOUBLE_HIGH (operands[1]);
4945 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4946 if (rtx_equal_p (tem, operands[0]))
4953 operands[1] = force_const_mem (DImode, operands[1]);
4954 if (reload_in_progress)
4956 emit_move_insn (operands[0], XEXP (operands[1], 0));
4957 operands[1] = copy_rtx (operands[1]);
4958 XEXP (operands[1], 0) = operands[0];
4961 operands[1] = validize_mem (operands[1]);
4968 ;; Split a load of a large constant into the appropriate two-insn
4972 [(set (match_operand:DI 0 "register_operand" "")
4973 (match_operand:DI 1 "const_int_operand" ""))]
4974 "! add_operand (operands[1], DImode)"
4975 [(set (match_dup 0) (match_dup 2))
4976 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4979 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4981 if (tem == operands[0])
4987 ;; These are the partial-word cases.
4989 ;; First we have the code to load an aligned word. Operand 0 is the register
4990 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4991 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4992 ;; number of bits within the word that the value is. Operand 3 is an SImode
4993 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4994 ;; same register. It is allowed to conflict with operand 1 as well.
4996 (define_expand "aligned_loadqi"
4997 [(set (match_operand:SI 3 "register_operand" "")
4998 (match_operand:SI 1 "memory_operand" ""))
4999 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5000 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5002 (match_operand:DI 2 "const_int_operand" "")))]
5007 (define_expand "aligned_loadhi"
5008 [(set (match_operand:SI 3 "register_operand" "")
5009 (match_operand:SI 1 "memory_operand" ""))
5010 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5011 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5013 (match_operand:DI 2 "const_int_operand" "")))]
5018 ;; Similar for unaligned loads, where we use the sequence from the
5019 ;; Alpha Architecture manual.
5021 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5022 ;; operand 3 can overlap the input and output registers.
5024 (define_expand "unaligned_loadqi"
5025 [(set (match_operand:DI 2 "register_operand" "")
5026 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5028 (set (match_operand:DI 3 "register_operand" "")
5030 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5031 (zero_extract:DI (match_dup 2)
5033 (ashift:DI (match_dup 3) (const_int 3))))]
5037 (define_expand "unaligned_loadhi"
5038 [(set (match_operand:DI 2 "register_operand" "")
5039 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5041 (set (match_operand:DI 3 "register_operand" "")
5043 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5044 (zero_extract:DI (match_dup 2)
5046 (ashift:DI (match_dup 3) (const_int 3))))]
5050 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5051 ;; aligned SImode MEM. Operand 1 is the register containing the
5052 ;; byte or word to store. Operand 2 is the number of bits within the word that
5053 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5055 (define_expand "aligned_store"
5056 [(set (match_operand:SI 3 "register_operand" "")
5057 (match_operand:SI 0 "memory_operand" ""))
5058 (set (subreg:DI (match_dup 3) 0)
5059 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5060 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5061 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5062 (match_operand:DI 2 "const_int_operand" "")))
5063 (set (subreg:DI (match_dup 4) 0)
5064 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5065 (set (match_dup 0) (match_dup 4))]
5068 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5069 << INTVAL (operands[2])));
5072 ;; For the unaligned byte and halfword cases, we use code similar to that
5073 ;; in the ;; Architecture book, but reordered to lower the number of registers
5074 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5075 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5076 ;; be the same temporary, if desired. If the address is in a register,
5077 ;; operand 2 can be that register.
5079 (define_expand "unaligned_storeqi"
5080 [(set (match_operand:DI 3 "register_operand" "")
5081 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5083 (set (match_operand:DI 2 "register_operand" "")
5086 (and:DI (not:DI (ashift:DI (const_int 255)
5087 (ashift:DI (match_dup 2) (const_int 3))))
5089 (set (match_operand:DI 4 "register_operand" "")
5090 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5091 (ashift:DI (match_dup 2) (const_int 3))))
5092 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5093 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5098 (define_expand "unaligned_storehi"
5099 [(set (match_operand:DI 3 "register_operand" "")
5100 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5102 (set (match_operand:DI 2 "register_operand" "")
5105 (and:DI (not:DI (ashift:DI (const_int 65535)
5106 (ashift:DI (match_dup 2) (const_int 3))))
5108 (set (match_operand:DI 4 "register_operand" "")
5109 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5110 (ashift:DI (match_dup 2) (const_int 3))))
5111 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5112 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5117 ;; Here are the define_expand's for QI and HI moves that use the above
5118 ;; patterns. We have the normal sets, plus the ones that need scratch
5119 ;; registers for reload.
5121 (define_expand "movqi"
5122 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5123 (match_operand:QI 1 "general_operand" ""))]
5128 if (GET_CODE (operands[0]) == MEM
5129 && ! reg_or_0_operand (operands[1], QImode))
5130 operands[1] = force_reg (QImode, operands[1]);
5132 if (GET_CODE (operands[1]) == CONST_INT
5133 && ! input_operand (operands[1], QImode))
5135 operands[1] = alpha_emit_set_const (operands[0], QImode,
5136 INTVAL (operands[1]), 3);
5138 if (rtx_equal_p (operands[0], operands[1]))
5145 /* If the output is not a register, the input must be. */
5146 if (GET_CODE (operands[0]) == MEM)
5147 operands[1] = force_reg (QImode, operands[1]);
5149 /* Handle four memory cases, unaligned and aligned for either the input
5150 or the output. The only case where we can be called during reload is
5151 for aligned loads; all other cases require temporaries. */
5153 if (GET_CODE (operands[1]) == MEM
5154 || (GET_CODE (operands[1]) == SUBREG
5155 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5156 || (reload_in_progress && GET_CODE (operands[1]) == REG
5157 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5158 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5159 && GET_CODE (SUBREG_REG (operands[1])) == REG
5160 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5162 if (aligned_memory_operand (operands[1], QImode))
5164 if (reload_in_progress)
5166 emit_insn (gen_reload_inqi_help
5167 (operands[0], operands[1],
5168 gen_rtx_REG (SImode, REGNO (operands[0]))));
5172 rtx aligned_mem, bitnum;
5173 rtx scratch = gen_reg_rtx (SImode);
5175 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5177 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5183 /* Don't pass these as parameters since that makes the generated
5184 code depend on parameter evaluation order which will cause
5185 bootstrap failures. */
5187 rtx temp1 = gen_reg_rtx (DImode);
5188 rtx temp2 = gen_reg_rtx (DImode);
5190 = gen_unaligned_loadqi (operands[0],
5191 get_unaligned_address (operands[1], 0),
5194 alpha_set_memflags (seq, operands[1]);
5201 else if (GET_CODE (operands[0]) == MEM
5202 || (GET_CODE (operands[0]) == SUBREG
5203 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5204 || (reload_in_progress && GET_CODE (operands[0]) == REG
5205 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5206 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5207 && GET_CODE (SUBREG_REG (operands[0])) == REG
5208 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5210 if (aligned_memory_operand (operands[0], QImode))
5212 rtx aligned_mem, bitnum;
5213 rtx temp1 = gen_reg_rtx (SImode);
5214 rtx temp2 = gen_reg_rtx (SImode);
5216 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5218 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5223 rtx temp1 = gen_reg_rtx (DImode);
5224 rtx temp2 = gen_reg_rtx (DImode);
5225 rtx temp3 = gen_reg_rtx (DImode);
5227 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
5228 operands[1], temp1, temp2, temp3);
5230 alpha_set_memflags (seq, operands[0]);
5238 (define_expand "movhi"
5239 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5240 (match_operand:HI 1 "general_operand" ""))]
5245 if (GET_CODE (operands[0]) == MEM
5246 && ! reg_or_0_operand (operands[1], HImode))
5247 operands[1] = force_reg (HImode, operands[1]);
5249 if (GET_CODE (operands[1]) == CONST_INT
5250 && ! input_operand (operands[1], HImode))
5252 operands[1] = alpha_emit_set_const (operands[0], HImode,
5253 INTVAL (operands[1]), 3);
5255 if (rtx_equal_p (operands[0], operands[1]))
5262 /* If the output is not a register, the input must be. */
5263 if (GET_CODE (operands[0]) == MEM)
5264 operands[1] = force_reg (HImode, operands[1]);
5266 /* Handle four memory cases, unaligned and aligned for either the input
5267 or the output. The only case where we can be called during reload is
5268 for aligned loads; all other cases require temporaries. */
5270 if (GET_CODE (operands[1]) == MEM
5271 || (GET_CODE (operands[1]) == SUBREG
5272 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5273 || (reload_in_progress && GET_CODE (operands[1]) == REG
5274 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5275 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5276 && GET_CODE (SUBREG_REG (operands[1])) == REG
5277 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5279 if (aligned_memory_operand (operands[1], HImode))
5281 if (reload_in_progress)
5283 emit_insn (gen_reload_inhi_help
5284 (operands[0], operands[1],
5285 gen_rtx_REG (SImode, REGNO (operands[0]))));
5289 rtx aligned_mem, bitnum;
5290 rtx scratch = gen_reg_rtx (SImode);
5292 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5294 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5300 /* Don't pass these as parameters since that makes the generated
5301 code depend on parameter evaluation order which will cause
5302 bootstrap failures. */
5304 rtx temp1 = gen_reg_rtx (DImode);
5305 rtx temp2 = gen_reg_rtx (DImode);
5307 = gen_unaligned_loadhi (operands[0],
5308 get_unaligned_address (operands[1], 0),
5311 alpha_set_memflags (seq, operands[1]);
5318 else if (GET_CODE (operands[0]) == MEM
5319 || (GET_CODE (operands[0]) == SUBREG
5320 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5321 || (reload_in_progress && GET_CODE (operands[0]) == REG
5322 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5323 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5324 && GET_CODE (SUBREG_REG (operands[0])) == REG
5325 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5327 if (aligned_memory_operand (operands[0], HImode))
5329 rtx aligned_mem, bitnum;
5330 rtx temp1 = gen_reg_rtx (SImode);
5331 rtx temp2 = gen_reg_rtx (SImode);
5333 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5335 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5340 rtx temp1 = gen_reg_rtx (DImode);
5341 rtx temp2 = gen_reg_rtx (DImode);
5342 rtx temp3 = gen_reg_rtx (DImode);
5344 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
5345 operands[1], temp1, temp2, temp3);
5347 alpha_set_memflags (seq, operands[0]);
5356 ;; Here are the versions for reload. Note that in the unaligned cases
5357 ;; we know that the operand must not be a pseudo-register because stack
5358 ;; slots are always aligned references.
5360 (define_expand "reload_inqi"
5361 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5362 (match_operand:QI 1 "any_memory_operand" "m")
5363 (match_operand:TI 2 "register_operand" "=&r")])]
5368 if (GET_CODE (operands[1]) != MEM)
5371 if (aligned_memory_operand (operands[1], QImode))
5373 seq = gen_reload_inqi_help (operands[0], operands[1],
5374 gen_rtx_REG (SImode, REGNO (operands[2])));
5380 /* It is possible that one of the registers we got for operands[2]
5381 might coincide with that of operands[0] (which is why we made
5382 it TImode). Pick the other one to use as our scratch. */
5383 if (REGNO (operands[0]) == REGNO (operands[2]))
5384 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5386 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5388 addr = get_unaligned_address (operands[1], 0);
5389 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5390 gen_rtx_REG (DImode, REGNO (operands[0])));
5391 alpha_set_memflags (seq, operands[1]);
5397 (define_expand "reload_inhi"
5398 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5399 (match_operand:HI 1 "any_memory_operand" "m")
5400 (match_operand:TI 2 "register_operand" "=&r")])]
5405 if (GET_CODE (operands[1]) != MEM)
5408 if (aligned_memory_operand (operands[1], HImode))
5410 seq = gen_reload_inhi_help (operands[0], operands[1],
5411 gen_rtx_REG (SImode, REGNO (operands[2])));
5417 /* It is possible that one of the registers we got for operands[2]
5418 might coincide with that of operands[0] (which is why we made
5419 it TImode). Pick the other one to use as our scratch. */
5420 if (REGNO (operands[0]) == REGNO (operands[2]))
5421 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5423 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5425 addr = get_unaligned_address (operands[1], 0);
5426 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5427 gen_rtx_REG (DImode, REGNO (operands[0])));
5428 alpha_set_memflags (seq, operands[1]);
5434 (define_expand "reload_outqi"
5435 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5436 (match_operand:QI 1 "register_operand" "r")
5437 (match_operand:TI 2 "register_operand" "=&r")])]
5440 if (GET_CODE (operands[0]) != MEM)
5443 if (aligned_memory_operand (operands[0], QImode))
5445 emit_insn (gen_reload_outqi_help
5446 (operands[0], operands[1],
5447 gen_rtx_REG (SImode, REGNO (operands[2])),
5448 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5452 rtx addr = get_unaligned_address (operands[0], 0);
5453 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5454 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5455 rtx scratch3 = scratch1;
5458 if (GET_CODE (addr) == REG)
5461 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5462 scratch2, scratch3);
5463 alpha_set_memflags (seq, operands[0]);
5469 (define_expand "reload_outhi"
5470 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5471 (match_operand:HI 1 "register_operand" "r")
5472 (match_operand:TI 2 "register_operand" "=&r")])]
5475 if (GET_CODE (operands[0]) != MEM)
5478 if (aligned_memory_operand (operands[0], HImode))
5480 emit_insn (gen_reload_outhi_help
5481 (operands[0], operands[1],
5482 gen_rtx_REG (SImode, REGNO (operands[2])),
5483 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5487 rtx addr = get_unaligned_address (operands[0], 0);
5488 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5489 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5490 rtx scratch3 = scratch1;
5493 if (GET_CODE (addr) == REG)
5496 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5497 scratch2, scratch3);
5498 alpha_set_memflags (seq, operands[0]);
5504 ;; Helpers for the above. The way reload is structured, we can't
5505 ;; always get a proper address for a stack slot during reload_foo
5506 ;; expansion, so we must delay our address manipulations until after.
5508 (define_insn "reload_inqi_help"
5509 [(set (match_operand:QI 0 "register_operand" "=r")
5510 (match_operand:QI 1 "memory_operand" "m"))
5511 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5512 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5515 (define_insn "reload_inhi_help"
5516 [(set (match_operand:HI 0 "register_operand" "=r")
5517 (match_operand:HI 1 "memory_operand" "m"))
5518 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5519 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5522 (define_insn "reload_outqi_help"
5523 [(set (match_operand:QI 0 "memory_operand" "=m")
5524 (match_operand:QI 1 "register_operand" "r"))
5525 (clobber (match_operand:SI 2 "register_operand" "=r"))
5526 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5527 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5530 (define_insn "reload_outhi_help"
5531 [(set (match_operand:HI 0 "memory_operand" "=m")
5532 (match_operand:HI 1 "register_operand" "r"))
5533 (clobber (match_operand:SI 2 "register_operand" "=r"))
5534 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5535 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5539 [(set (match_operand:QI 0 "register_operand" "")
5540 (match_operand:QI 1 "memory_operand" ""))
5541 (clobber (match_operand:SI 2 "register_operand" ""))]
5542 "! TARGET_BWX && reload_completed"
5545 rtx aligned_mem, bitnum;
5546 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5547 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5553 [(set (match_operand:HI 0 "register_operand" "")
5554 (match_operand:HI 1 "memory_operand" ""))
5555 (clobber (match_operand:SI 2 "register_operand" ""))]
5556 "! TARGET_BWX && reload_completed"
5559 rtx aligned_mem, bitnum;
5560 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5561 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5567 [(set (match_operand:QI 0 "memory_operand" "")
5568 (match_operand:QI 1 "register_operand" ""))
5569 (clobber (match_operand:SI 2 "register_operand" ""))
5570 (clobber (match_operand:SI 3 "register_operand" ""))]
5571 "! TARGET_BWX && reload_completed"
5574 rtx aligned_mem, bitnum;
5575 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5576 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5577 operands[2], operands[3]));
5582 [(set (match_operand:HI 0 "memory_operand" "")
5583 (match_operand:HI 1 "register_operand" ""))
5584 (clobber (match_operand:SI 2 "register_operand" ""))
5585 (clobber (match_operand:SI 3 "register_operand" ""))]
5586 "! TARGET_BWX && reload_completed"
5589 rtx aligned_mem, bitnum;
5590 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5591 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5592 operands[2], operands[3]));
5596 ;; Bit field extract patterns which use ext[wlq][lh]
5598 (define_expand "extv"
5599 [(set (match_operand:DI 0 "register_operand" "")
5600 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5601 (match_operand:DI 2 "immediate_operand" "")
5602 (match_operand:DI 3 "immediate_operand" "")))]
5605 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5606 if (INTVAL (operands[3]) % 8 != 0
5607 || (INTVAL (operands[2]) != 16
5608 && INTVAL (operands[2]) != 32
5609 && INTVAL (operands[2]) != 64))
5612 /* From mips.md: extract_bit_field doesn't verify that our source
5613 matches the predicate, so we force it to be a MEM here. */
5614 if (GET_CODE (operands[1]) != MEM)
5617 alpha_expand_unaligned_load (operands[0], operands[1],
5618 INTVAL (operands[2]) / 8,
5619 INTVAL (operands[3]) / 8, 1);
5623 (define_expand "extzv"
5624 [(set (match_operand:DI 0 "register_operand" "")
5625 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5626 (match_operand:DI 2 "immediate_operand" "")
5627 (match_operand:DI 3 "immediate_operand" "")))]
5630 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5631 if (INTVAL (operands[3]) % 8 != 0
5632 || (INTVAL (operands[2]) != 8
5633 && INTVAL (operands[2]) != 16
5634 && INTVAL (operands[2]) != 32
5635 && INTVAL (operands[2]) != 64))
5638 if (GET_CODE (operands[1]) == MEM)
5640 /* Fail 8 bit fields, falling back on a simple byte load. */
5641 if (INTVAL (operands[2]) == 8)
5644 alpha_expand_unaligned_load (operands[0], operands[1],
5645 INTVAL (operands[2]) / 8,
5646 INTVAL (operands[3]) / 8, 0);
5651 (define_expand "insv"
5652 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5653 (match_operand:DI 1 "immediate_operand" "")
5654 (match_operand:DI 2 "immediate_operand" ""))
5655 (match_operand:DI 3 "register_operand" ""))]
5658 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5659 if (INTVAL (operands[2]) % 8 != 0
5660 || (INTVAL (operands[1]) != 16
5661 && INTVAL (operands[1]) != 32
5662 && INTVAL (operands[1]) != 64))
5665 /* From mips.md: store_bit_field doesn't verify that our source
5666 matches the predicate, so we force it to be a MEM here. */
5667 if (GET_CODE (operands[0]) != MEM)
5670 alpha_expand_unaligned_store (operands[0], operands[3],
5671 INTVAL (operands[1]) / 8,
5672 INTVAL (operands[2]) / 8);
5676 ;; Block move/clear, see alpha.c for more details.
5677 ;; Argument 0 is the destination
5678 ;; Argument 1 is the source
5679 ;; Argument 2 is the length
5680 ;; Argument 3 is the alignment
5682 (define_expand "movstrqi"
5683 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5684 (match_operand:BLK 1 "memory_operand" ""))
5685 (use (match_operand:DI 2 "immediate_operand" ""))
5686 (use (match_operand:DI 3 "immediate_operand" ""))])]
5689 if (alpha_expand_block_move (operands))
5695 (define_expand "clrstrqi"
5696 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5698 (use (match_operand:DI 1 "immediate_operand" ""))
5699 (use (match_operand:DI 2 "immediate_operand" ""))])]
5702 if (alpha_expand_block_clear (operands))
5708 ;; Subroutine of stack space allocation. Perform a stack probe.
5709 (define_expand "probe_stack"
5710 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5713 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5714 INTVAL (operands[0])));
5715 MEM_VOLATILE_P (operands[1]) = 1;
5717 operands[0] = const0_rtx;
5720 ;; This is how we allocate stack space. If we are allocating a
5721 ;; constant amount of space and we know it is less than 4096
5722 ;; bytes, we need do nothing.
5724 ;; If it is more than 4096 bytes, we need to probe the stack
5726 (define_expand "allocate_stack"
5728 (plus:DI (reg:DI 30)
5729 (match_operand:DI 1 "reg_or_cint_operand" "")))
5730 (set (match_operand:DI 0 "register_operand" "=r")
5734 if (GET_CODE (operands[1]) == CONST_INT
5735 && INTVAL (operands[1]) < 32768)
5737 if (INTVAL (operands[1]) >= 4096)
5739 /* We do this the same way as in the prologue and generate explicit
5740 probes. Then we update the stack by the constant. */
5744 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5745 while (probed + 8192 < INTVAL (operands[1]))
5746 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5748 if (probed + 4096 < INTVAL (operands[1]))
5749 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5752 operands[1] = GEN_INT (- INTVAL (operands[1]));
5753 operands[2] = virtual_stack_dynamic_rtx;
5758 rtx loop_label = gen_label_rtx ();
5759 rtx want = gen_reg_rtx (Pmode);
5760 rtx tmp = gen_reg_rtx (Pmode);
5763 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5764 force_reg (Pmode, operands[1])));
5765 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5767 if (GET_CODE (operands[1]) != CONST_INT)
5769 out_label = gen_label_rtx ();
5770 emit_insn (gen_cmpdi (want, tmp));
5771 emit_jump_insn (gen_bgeu (out_label));
5774 emit_label (loop_label);
5775 memref = gen_rtx_MEM (DImode, tmp);
5776 MEM_VOLATILE_P (memref) = 1;
5777 emit_move_insn (memref, const0_rtx);
5778 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5779 emit_insn (gen_cmpdi (tmp, want));
5780 emit_jump_insn (gen_bgtu (loop_label));
5782 memref = gen_rtx_MEM (DImode, want);
5783 MEM_VOLATILE_P (memref) = 1;
5784 emit_move_insn (memref, const0_rtx);
5787 emit_label (out_label);
5789 emit_move_insn (stack_pointer_rtx, want);
5790 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5795 ;; This is used by alpha_expand_prolog to do the same thing as above,
5796 ;; except we cannot at that time generate new basic blocks, so we hide
5797 ;; the loop in this one insn.
5799 (define_insn "prologue_stack_probe_loop"
5800 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5801 (match_operand:DI 1 "register_operand" "r")]
5805 operands[2] = gen_label_rtx ();
5806 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5807 CODE_LABEL_NUMBER (operands[2]));
5809 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
5811 [(set_attr "length" "16")
5812 (set_attr "type" "multi")])
5814 (define_expand "prologue"
5815 [(clobber (const_int 0))]
5818 alpha_expand_prologue ();
5822 ;; These take care of emitting the ldgp insn in the prologue. This will be
5823 ;; an lda/ldah pair and we want to align them properly. So we have two
5824 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
5825 ;; and the second of which emits nothing. However, both are marked as type
5826 ;; IADD (the default) so the alignment code in alpha.c does the right thing
5829 (define_expand "prologue_ldgp"
5830 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP1)
5831 (unspec_volatile [(const_int 0)] UNSPECV_LDGP2)]
5835 (define_insn "*prologue_ldgp_1"
5836 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP1)]
5838 "ldgp $29,0($27)\n$%~..ng:")
5840 (define_insn "*prologue_ldgp_2"
5841 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP2)]
5845 ;; The _mcount profiling hook has special calling conventions, and
5846 ;; does not clobber all the registers that a normal call would. So
5847 ;; hide the fact this is a call at all.
5849 (define_insn "prologue_mcount"
5850 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
5852 "lda $28,_mcount\;jsr $28,($28),_mcount"
5853 [(set_attr "type" "multi")
5854 (set_attr "length" "8")])
5856 (define_insn "init_fp"
5857 [(set (match_operand:DI 0 "register_operand" "=r")
5858 (match_operand:DI 1 "register_operand" "r"))
5859 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5863 (define_expand "epilogue"
5867 alpha_expand_epilogue ();
5870 (define_expand "sibcall_epilogue"
5874 alpha_expand_epilogue ();
5878 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5879 ;; the frame size into a register. We use this pattern to ensure
5880 ;; we get lda instead of addq.
5881 (define_insn "nt_lda"
5882 [(set (match_operand:DI 0 "register_operand" "=r")
5883 (unspec:DI [(match_dup 0)
5884 (match_operand:DI 1 "const_int_operand" "n")]
5889 (define_expand "builtin_longjmp"
5890 [(use (match_operand:DI 0 "register_operand" "r"))]
5893 /* The elements of the buffer are, in order: */
5894 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5895 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5896 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5897 rtx pv = gen_rtx_REG (Pmode, 27);
5899 /* This bit is the same as expand_builtin_longjmp. */
5900 emit_move_insn (hard_frame_pointer_rtx, fp);
5901 emit_move_insn (pv, lab);
5902 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5903 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5904 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5906 /* Load the label we are jumping through into $27 so that we know
5907 where to look for it when we get back to setjmp's function for
5908 restoring the gp. */
5909 emit_jump_insn (gen_builtin_longjmp_internal (pv));
5914 ;; This is effectively a copy of indirect_jump, but constrained such
5915 ;; that register renaming cannot foil our cunning plan with $27.
5916 (define_insn "builtin_longjmp_internal"
5918 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
5922 [(set_attr "type" "ibr")])
5924 (define_insn "*builtin_setjmp_receiver_sub_label"
5925 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
5926 "TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
5927 "\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5928 [(set_attr "length" "8")
5929 (set_attr "type" "multi")])
5931 (define_insn "builtin_setjmp_receiver"
5932 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
5934 "br $29,$LSJ%=\n$LSJ%=:\;ldgp $29,0($29)"
5935 [(set_attr "length" "12")
5936 (set_attr "type" "multi")])
5938 (define_expand "exception_receiver"
5939 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
5942 if (TARGET_LD_BUGGY_LDGP)
5943 operands[0] = alpha_gp_save_rtx ();
5945 operands[0] = const0_rtx;
5948 (define_insn "*exception_receiver_1"
5949 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
5950 "! TARGET_LD_BUGGY_LDGP"
5952 [(set_attr "length" "8")
5953 (set_attr "type" "multi")])
5955 ;; ??? We don't represent the usage of $29 properly in address loads
5956 ;; and function calls. This leads to the following move being deleted
5957 ;; as dead code unless it is represented as a volatile unspec.
5959 (define_insn "*exception_receiver_2"
5960 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
5962 "TARGET_LD_BUGGY_LDGP"
5966 [(set_attr "type" "ilog,ild")])
5968 (define_expand "nonlocal_goto_receiver"
5969 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
5970 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5971 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
5973 "TARGET_ABI_OPEN_VMS"
5976 (define_insn "arg_home"
5977 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
5992 (clobber (mem:BLK (const_int 0)))
5993 (clobber (reg:DI 24))
5994 (clobber (reg:DI 25))
5995 (clobber (reg:DI 0))]
5996 "TARGET_ABI_OPEN_VMS"
5997 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5998 [(set_attr "length" "16")
5999 (set_attr "type" "multi")])
6001 ;; Close the trap shadow of preceeding instructions. This is generated
6004 (define_insn "trapb"
6005 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6008 [(set_attr "type" "misc")])
6010 ;; No-op instructions used by machine-dependant reorg to preserve
6011 ;; alignment for instruction issue.
6017 [(set_attr "type" "ilog")])
6023 [(set_attr "type" "fcpys")])
6030 (define_insn "realign"
6031 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6034 ".align %0 #realign")
6036 ;; The call patterns are at the end of the file because their
6037 ;; wildcard operand0 interferes with nice recognition.
6039 (define_insn "*call_value_osf_1"
6040 [(set (match_operand 0 "" "")
6041 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,i"))
6042 (match_operand 2 "" "")))
6043 (clobber (reg:DI 27))
6044 (clobber (reg:DI 26))]
6047 jsr $26,($27),0\;ldgp $29,0($26)
6049 jsr $26,%1\;ldgp $29,0($26)"
6050 [(set_attr "type" "jsr")
6051 (set_attr "length" "12,*,16")])
6053 (define_insn "*sibcall_value_osf_1"
6054 [(set (match_operand 0 "" "")
6055 (call (mem:DI (match_operand:DI 1 "call_operand" "R,i"))
6056 (match_operand 2 "" "")))]
6061 [(set_attr "type" "jsr")
6062 (set_attr "length" "*,8")])
6064 (define_insn "*call_value_nt_1"
6065 [(set (match_operand 0 "" "")
6066 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
6067 (match_operand 2 "" "")))
6068 (clobber (reg:DI 26))]
6069 "TARGET_ABI_WINDOWS_NT"
6074 [(set_attr "type" "jsr")
6075 (set_attr "length" "*,*,12")])
6077 (define_insn "*call_value_vms_1"
6078 [(set (match_operand 0 "" "")
6079 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
6080 (match_operand 2 "" "")))
6081 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6084 (clobber (reg:DI 27))]
6085 "TARGET_ABI_OPEN_VMS"
6087 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6088 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6089 [(set_attr "type" "jsr")
6090 (set_attr "length" "12,16")])