1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
69 (UNSPECV_LONGJMP 3) ; builtin_longjmp
71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
73 (UNSPECV_EHR 7) ; exception_receiver
77 (UNSPECV_PLDGP2 11) ; prologue ldgp
82 ;; Where necessary, the suffixes _le and _be are used to distinguish between
83 ;; little-endian and big-endian patterns.
85 ;; Note that the Unicos/Mk assembler does not support the following
86 ;; opcodes: mov, fmov, nop, fnop, unop.
88 ;; Processor type -- this attribute must exactly match the processor_type
89 ;; enumeration in alpha.h.
91 (define_attr "cpu" "ev4,ev5,ev6"
92 (const (symbol_ref "alpha_cpu")))
94 ;; Define an insn type attribute. This is used in function unit delay
95 ;; computations, among other purposes. For the most part, we use the names
96 ;; defined in the EV4 documentation, but add a few that we have to know about
100 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
101 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
102 (const_string "iadd"))
104 ;; Describe a user's asm statement.
105 (define_asm_attributes
106 [(set_attr "type" "multi")])
108 ;; Define the operand size an insn operates on. Used primarily by mul
109 ;; and div operations that have size dependent timings.
111 (define_attr "opsize" "si,di,udi"
114 ;; The TRAP attribute marks instructions that may generate traps
115 ;; (which are imprecise and may need a trapb if software completion
118 (define_attr "trap" "no,yes"
121 ;; The ROUND_SUFFIX attribute marks which instructions require a
122 ;; rounding-mode suffix. The value NONE indicates no suffix,
123 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
125 (define_attr "round_suffix" "none,normal,c"
126 (const_string "none"))
128 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
130 ;; SU accepts only /su (cmpt et al)
131 ;; SUI accepts only /sui (cvtqt and cvtqs)
132 ;; V_SV accepts /v and /sv (cvtql only)
133 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
134 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
136 ;; The actual suffix emitted is controled by alpha_fptm.
138 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
139 (const_string "none"))
141 ;; The length of an instruction sequence in bytes.
143 (define_attr "length" ""
146 ;; The USEGP attribute marks instructions that have relocations that use
149 (define_attr "usegp" "no,yes"
150 (cond [(eq_attr "type" "ldsym,jsr")
152 (eq_attr "type" "ild,fld,ist,fst")
153 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
155 (const_string "no")))
158 ;; Include scheduling descriptions.
164 ;; First define the arithmetic insns. Note that the 32-bit forms also
167 ;; Handle 32-64 bit extension from memory to a floating point register
168 ;; specially, since this occurs frequently in int->double conversions.
170 ;; Note that while we must retain the =f case in the insn for reload's
171 ;; benefit, it should be eliminated after reload, so we should never emit
172 ;; code for that case. But we don't reject the possibility.
174 (define_expand "extendsidi2"
175 [(set (match_operand:DI 0 "register_operand" "")
176 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
180 (define_insn "*extendsidi2_nofix"
181 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
183 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
189 lds %0,%1\;cvtlq %0,%0"
190 [(set_attr "type" "iadd,ild,fadd,fld")
191 (set_attr "length" "*,*,*,8")])
193 (define_insn "*extendsidi2_fix"
194 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
196 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
203 lds %0,%1\;cvtlq %0,%0"
204 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
205 (set_attr "length" "*,*,*,*,8")])
207 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
209 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
210 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
212 [(set (match_dup 2) (match_dup 1))
213 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
214 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
216 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
217 ;; reload when converting fp->int.
220 [(set (match_operand:SI 0 "hard_int_register_operand" "")
221 (match_operand:SI 1 "memory_operand" ""))
222 (set (match_operand:DI 2 "hard_int_register_operand" "")
223 (sign_extend:DI (match_dup 0)))]
224 "true_regnum (operands[0]) == true_regnum (operands[2])
225 || peep2_reg_dead_p (2, operands[0])"
227 (sign_extend:DI (match_dup 1)))]
231 [(set (match_operand:SI 0 "hard_int_register_operand" "")
232 (match_operand:SI 1 "hard_fp_register_operand" ""))
233 (set (match_operand:DI 2 "hard_int_register_operand" "")
234 (sign_extend:DI (match_dup 0)))]
236 && (true_regnum (operands[0]) == true_regnum (operands[2])
237 || peep2_reg_dead_p (2, operands[0]))"
239 (sign_extend:DI (match_dup 1)))]
243 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
244 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
245 (set (match_operand:DI 2 "hard_int_register_operand" "")
247 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
249 (sign_extend:DI (match_dup 1)))]
252 ;; Don't say we have addsi3 if optimizing. This generates better code. We
253 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
254 (define_expand "addsi3"
255 [(set (match_operand:SI 0 "register_operand" "")
256 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
257 (match_operand:SI 2 "add_operand" "")))]
261 (define_insn "*addsi_internal"
262 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
263 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
264 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
273 [(set (match_operand:SI 0 "register_operand" "")
274 (plus:SI (match_operand:SI 1 "register_operand" "")
275 (match_operand:SI 2 "const_int_operand" "")))]
276 "! add_operand (operands[2], SImode)"
277 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
278 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
280 HOST_WIDE_INT val = INTVAL (operands[2]);
281 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
282 HOST_WIDE_INT rest = val - low;
284 operands[3] = GEN_INT (rest);
285 operands[4] = GEN_INT (low);
288 (define_insn "*addsi_se"
289 [(set (match_operand:DI 0 "register_operand" "=r,r")
291 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
292 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
298 (define_insn "*addsi_se2"
299 [(set (match_operand:DI 0 "register_operand" "=r,r")
301 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
302 (match_operand:DI 2 "sext_add_operand" "rI,O"))
310 [(set (match_operand:DI 0 "register_operand" "")
312 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
313 (match_operand:SI 2 "const_int_operand" ""))))
314 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
315 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
316 && INTVAL (operands[2]) % 4 == 0"
317 [(set (match_dup 3) (match_dup 4))
318 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
322 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
328 operands[4] = GEN_INT (val);
329 operands[5] = GEN_INT (mult);
333 [(set (match_operand:DI 0 "register_operand" "")
335 (plus:SI (match_operator:SI 1 "comparison_operator"
336 [(match_operand 2 "" "")
337 (match_operand 3 "" "")])
338 (match_operand:SI 4 "add_operand" ""))))
339 (clobber (match_operand:DI 5 "register_operand" ""))]
341 [(set (match_dup 5) (match_dup 6))
342 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
344 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
345 operands[2], operands[3]);
346 operands[7] = gen_lowpart (SImode, operands[5]);
349 (define_insn "addvsi3"
350 [(set (match_operand:SI 0 "register_operand" "=r,r")
351 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
352 (match_operand:SI 2 "sext_add_operand" "rI,O")))
353 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
354 (sign_extend:DI (match_dup 2)))
355 (sign_extend:DI (plus:SI (match_dup 1)
363 (define_expand "adddi3"
364 [(set (match_operand:DI 0 "register_operand" "")
365 (plus:DI (match_operand:DI 1 "register_operand" "")
366 (match_operand:DI 2 "add_operand" "")))]
370 (define_insn "*adddi_er_lo16_dtp"
371 [(set (match_operand:DI 0 "register_operand" "=r")
372 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
373 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
375 "lda %0,%2(%1)\t\t!dtprel")
377 (define_insn "*adddi_er_hi32_dtp"
378 [(set (match_operand:DI 0 "register_operand" "=r")
379 (plus:DI (match_operand:DI 1 "register_operand" "r")
380 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
382 "ldah %0,%2(%1)\t\t!dtprelhi")
384 (define_insn "*adddi_er_lo32_dtp"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
387 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
389 "lda %0,%2(%1)\t\t!dtprello")
391 (define_insn "*adddi_er_lo16_tp"
392 [(set (match_operand:DI 0 "register_operand" "=r")
393 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
394 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
396 "lda %0,%2(%1)\t\t!tprel")
398 (define_insn "*adddi_er_hi32_tp"
399 [(set (match_operand:DI 0 "register_operand" "=r")
400 (plus:DI (match_operand:DI 1 "register_operand" "r")
401 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
403 "ldah %0,%2(%1)\t\t!tprelhi")
405 (define_insn "*adddi_er_lo32_tp"
406 [(set (match_operand:DI 0 "register_operand" "=r")
407 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
408 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
410 "lda %0,%2(%1)\t\t!tprello")
412 (define_insn "*adddi_er_high_l"
413 [(set (match_operand:DI 0 "register_operand" "=r")
414 (plus:DI (match_operand:DI 1 "register_operand" "r")
415 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
416 "TARGET_EXPLICIT_RELOCS && reload_completed"
417 "ldah %0,%2(%1)\t\t!gprelhigh"
418 [(set_attr "usegp" "yes")])
421 [(set (match_operand:DI 0 "register_operand" "")
422 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
423 "TARGET_EXPLICIT_RELOCS && reload_completed"
425 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
426 "operands[2] = pic_offset_table_rtx;")
428 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
429 ;; With complications like
431 ;; The NT stack unwind code can't handle a subq to adjust the stack
432 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
433 ;; the exception handling code will loop if a subq is used and an
436 ;; The 19980616 change to emit prologues as RTL also confused some
437 ;; versions of GDB, which also interprets prologues. This has been
438 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
441 ;; and the fact that the three insns schedule exactly the same, it's
442 ;; just not worth the effort.
444 (define_insn "*adddi_internal"
445 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
446 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
447 (match_operand:DI 2 "add_operand" "r,K,L")))]
454 ;; ??? Allow large constants when basing off the frame pointer or some
455 ;; virtual register that may eliminate to the frame pointer. This is
456 ;; done because register elimination offsets will change the hi/lo split,
457 ;; and if we split before reload, we will require additional instructions.
459 (define_insn "*adddi_fp_hack"
460 [(set (match_operand:DI 0 "register_operand" "=r")
461 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
462 (match_operand:DI 2 "const_int_operand" "n")))]
463 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
464 && INTVAL (operands[2]) >= 0
465 /* This is the largest constant an lda+ldah pair can add, minus
466 an upper bound on the displacement between SP and AP during
467 register elimination. See INITIAL_ELIMINATION_OFFSET. */
468 && INTVAL (operands[2])
470 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
471 - ALPHA_ROUND(current_function_outgoing_args_size)
472 - (ALPHA_ROUND (get_frame_size ()
473 + max_reg_num () * UNITS_PER_WORD
474 + current_function_pretend_args_size)
475 - current_function_pretend_args_size))"
478 ;; Don't do this if we are adjusting SP since we don't want to do it
479 ;; in two steps. Don't split FP sources for the reason listed above.
481 [(set (match_operand:DI 0 "register_operand" "")
482 (plus:DI (match_operand:DI 1 "register_operand" "")
483 (match_operand:DI 2 "const_int_operand" "")))]
484 "! add_operand (operands[2], DImode)
485 && operands[0] != stack_pointer_rtx
486 && operands[1] != frame_pointer_rtx
487 && operands[1] != arg_pointer_rtx"
488 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
489 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
491 HOST_WIDE_INT val = INTVAL (operands[2]);
492 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
493 HOST_WIDE_INT rest = val - low;
495 operands[4] = GEN_INT (low);
496 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
497 operands[3] = GEN_INT (rest);
498 else if (! no_new_pseudos)
500 operands[3] = gen_reg_rtx (DImode);
501 emit_move_insn (operands[3], operands[2]);
502 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
509 (define_insn "*saddl"
510 [(set (match_operand:SI 0 "register_operand" "=r,r")
511 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
512 (match_operand:SI 2 "const48_operand" "I,I"))
513 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
519 (define_insn "*saddl_se"
520 [(set (match_operand:DI 0 "register_operand" "=r,r")
522 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
523 (match_operand:SI 2 "const48_operand" "I,I"))
524 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
531 [(set (match_operand:DI 0 "register_operand" "")
533 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
534 [(match_operand 2 "" "")
535 (match_operand 3 "" "")])
536 (match_operand:SI 4 "const48_operand" ""))
537 (match_operand:SI 5 "sext_add_operand" ""))))
538 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
540 [(set (match_dup 6) (match_dup 7))
542 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
545 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
546 operands[2], operands[3]);
547 operands[8] = gen_lowpart (SImode, operands[6]);
550 (define_insn "*saddq"
551 [(set (match_operand:DI 0 "register_operand" "=r,r")
552 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
553 (match_operand:DI 2 "const48_operand" "I,I"))
554 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
560 (define_insn "addvdi3"
561 [(set (match_operand:DI 0 "register_operand" "=r,r")
562 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
563 (match_operand:DI 2 "sext_add_operand" "rI,O")))
564 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
565 (sign_extend:TI (match_dup 2)))
566 (sign_extend:TI (plus:DI (match_dup 1)
574 (define_insn "negsi2"
575 [(set (match_operand:SI 0 "register_operand" "=r")
576 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
580 (define_insn "*negsi_se"
581 [(set (match_operand:DI 0 "register_operand" "=r")
582 (sign_extend:DI (neg:SI
583 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
587 (define_insn "negvsi2"
588 [(set (match_operand:SI 0 "register_operand" "=r")
589 (neg:SI (match_operand:SI 1 "register_operand" "r")))
590 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
591 (sign_extend:DI (neg:SI (match_dup 1))))
596 (define_insn "negdi2"
597 [(set (match_operand:DI 0 "register_operand" "=r")
598 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
602 (define_insn "negvdi2"
603 [(set (match_operand:DI 0 "register_operand" "=r")
604 (neg:DI (match_operand:DI 1 "register_operand" "r")))
605 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
606 (sign_extend:TI (neg:DI (match_dup 1))))
611 (define_expand "subsi3"
612 [(set (match_operand:SI 0 "register_operand" "")
613 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
614 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
618 (define_insn "*subsi_internal"
619 [(set (match_operand:SI 0 "register_operand" "=r")
620 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
621 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
625 (define_insn "*subsi_se"
626 [(set (match_operand:DI 0 "register_operand" "=r")
627 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
628 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
632 (define_insn "*subsi_se2"
633 [(set (match_operand:DI 0 "register_operand" "=r")
635 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
636 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
641 (define_insn "subvsi3"
642 [(set (match_operand:SI 0 "register_operand" "=r")
643 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
644 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
645 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
646 (sign_extend:DI (match_dup 2)))
647 (sign_extend:DI (minus:SI (match_dup 1)
653 (define_insn "subdi3"
654 [(set (match_operand:DI 0 "register_operand" "=r")
655 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
656 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
660 (define_insn "*ssubl"
661 [(set (match_operand:SI 0 "register_operand" "=r")
662 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
663 (match_operand:SI 2 "const48_operand" "I"))
664 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
668 (define_insn "*ssubl_se"
669 [(set (match_operand:DI 0 "register_operand" "=r")
671 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
672 (match_operand:SI 2 "const48_operand" "I"))
673 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
677 (define_insn "*ssubq"
678 [(set (match_operand:DI 0 "register_operand" "=r")
679 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
680 (match_operand:DI 2 "const48_operand" "I"))
681 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
685 (define_insn "subvdi3"
686 [(set (match_operand:DI 0 "register_operand" "=r")
687 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
688 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
689 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
690 (sign_extend:TI (match_dup 2)))
691 (sign_extend:TI (minus:DI (match_dup 1)
697 ;; The Unicos/Mk assembler doesn't support mull.
699 (define_insn "mulsi3"
700 [(set (match_operand:SI 0 "register_operand" "=r")
701 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
702 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
703 "!TARGET_ABI_UNICOSMK"
705 [(set_attr "type" "imul")
706 (set_attr "opsize" "si")])
708 (define_insn "*mulsi_se"
709 [(set (match_operand:DI 0 "register_operand" "=r")
711 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
712 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
713 "!TARGET_ABI_UNICOSMK"
715 [(set_attr "type" "imul")
716 (set_attr "opsize" "si")])
718 (define_insn "mulvsi3"
719 [(set (match_operand:SI 0 "register_operand" "=r")
720 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
721 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
722 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
723 (sign_extend:DI (match_dup 2)))
724 (sign_extend:DI (mult:SI (match_dup 1)
727 "!TARGET_ABI_UNICOSMK"
729 [(set_attr "type" "imul")
730 (set_attr "opsize" "si")])
732 (define_insn "muldi3"
733 [(set (match_operand:DI 0 "register_operand" "=r")
734 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
735 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
738 [(set_attr "type" "imul")])
740 (define_insn "mulvdi3"
741 [(set (match_operand:DI 0 "register_operand" "=r")
742 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
743 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
744 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
745 (sign_extend:TI (match_dup 2)))
746 (sign_extend:TI (mult:DI (match_dup 1)
751 [(set_attr "type" "imul")])
753 (define_expand "umuldi3_highpart"
754 [(set (match_operand:DI 0 "register_operand" "")
757 (mult:TI (zero_extend:TI
758 (match_operand:DI 1 "register_operand" ""))
759 (match_operand:DI 2 "reg_or_8bit_operand" ""))
763 if (REG_P (operands[2]))
764 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
767 (define_insn "*umuldi3_highpart_reg"
768 [(set (match_operand:DI 0 "register_operand" "=r")
771 (mult:TI (zero_extend:TI
772 (match_operand:DI 1 "register_operand" "r"))
774 (match_operand:DI 2 "register_operand" "r")))
778 [(set_attr "type" "imul")
779 (set_attr "opsize" "udi")])
781 (define_insn "*umuldi3_highpart_const"
782 [(set (match_operand:DI 0 "register_operand" "=r")
785 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
786 (match_operand:TI 2 "cint8_operand" "I"))
790 [(set_attr "type" "imul")
791 (set_attr "opsize" "udi")])
793 ;; The divide and remainder operations take their inputs from r24 and
794 ;; r25, put their output in r27, and clobber r23 and r28 on all
795 ;; systems except Unicos/Mk. On Unicos, the standard library provides
796 ;; subroutines which use the standard calling convention and work on
799 ;; ??? Force sign-extension here because some versions of OSF/1 and
800 ;; Interix/NT don't do the right thing if the inputs are not properly
801 ;; sign-extended. But Linux, for instance, does not have this
802 ;; problem. Is it worth the complication here to eliminate the sign
805 (define_expand "divsi3"
807 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
809 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
810 (parallel [(set (match_dup 5)
811 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
812 (clobber (reg:DI 23))
813 (clobber (reg:DI 28))])
814 (set (match_operand:SI 0 "nonimmediate_operand" "")
815 (subreg:SI (match_dup 5) 0))]
816 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
818 operands[3] = gen_reg_rtx (DImode);
819 operands[4] = gen_reg_rtx (DImode);
820 operands[5] = gen_reg_rtx (DImode);
823 (define_expand "udivsi3"
825 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
827 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
828 (parallel [(set (match_dup 5)
829 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
830 (clobber (reg:DI 23))
831 (clobber (reg:DI 28))])
832 (set (match_operand:SI 0 "nonimmediate_operand" "")
833 (subreg:SI (match_dup 5) 0))]
834 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
836 operands[3] = gen_reg_rtx (DImode);
837 operands[4] = gen_reg_rtx (DImode);
838 operands[5] = gen_reg_rtx (DImode);
841 (define_expand "modsi3"
843 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
845 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
846 (parallel [(set (match_dup 5)
847 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
848 (clobber (reg:DI 23))
849 (clobber (reg:DI 28))])
850 (set (match_operand:SI 0 "nonimmediate_operand" "")
851 (subreg:SI (match_dup 5) 0))]
852 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
854 operands[3] = gen_reg_rtx (DImode);
855 operands[4] = gen_reg_rtx (DImode);
856 operands[5] = gen_reg_rtx (DImode);
859 (define_expand "umodsi3"
861 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
863 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
864 (parallel [(set (match_dup 5)
865 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
866 (clobber (reg:DI 23))
867 (clobber (reg:DI 28))])
868 (set (match_operand:SI 0 "nonimmediate_operand" "")
869 (subreg:SI (match_dup 5) 0))]
870 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
872 operands[3] = gen_reg_rtx (DImode);
873 operands[4] = gen_reg_rtx (DImode);
874 operands[5] = gen_reg_rtx (DImode);
877 (define_expand "divdi3"
878 [(parallel [(set (match_operand:DI 0 "register_operand" "")
879 (div:DI (match_operand:DI 1 "register_operand" "")
880 (match_operand:DI 2 "register_operand" "")))
881 (clobber (reg:DI 23))
882 (clobber (reg:DI 28))])]
883 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
886 (define_expand "udivdi3"
887 [(parallel [(set (match_operand:DI 0 "register_operand" "")
888 (udiv:DI (match_operand:DI 1 "register_operand" "")
889 (match_operand:DI 2 "register_operand" "")))
890 (clobber (reg:DI 23))
891 (clobber (reg:DI 28))])]
892 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
895 (define_expand "moddi3"
896 [(use (match_operand:DI 0 "register_operand" ""))
897 (use (match_operand:DI 1 "register_operand" ""))
898 (use (match_operand:DI 2 "register_operand" ""))]
899 "!TARGET_ABI_OPEN_VMS"
901 if (TARGET_ABI_UNICOSMK)
902 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
904 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
908 (define_expand "moddi3_dft"
909 [(parallel [(set (match_operand:DI 0 "register_operand" "")
910 (mod:DI (match_operand:DI 1 "register_operand" "")
911 (match_operand:DI 2 "register_operand" "")))
912 (clobber (reg:DI 23))
913 (clobber (reg:DI 28))])]
914 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
917 ;; On Unicos/Mk, we do as the system's C compiler does:
918 ;; compute the quotient, multiply and subtract.
920 (define_expand "moddi3_umk"
921 [(use (match_operand:DI 0 "register_operand" ""))
922 (use (match_operand:DI 1 "register_operand" ""))
923 (use (match_operand:DI 2 "register_operand" ""))]
924 "TARGET_ABI_UNICOSMK"
926 rtx div, mul = gen_reg_rtx (DImode);
928 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
929 NULL_RTX, 0, OPTAB_LIB);
930 div = force_reg (DImode, div);
931 emit_insn (gen_muldi3 (mul, operands[2], div));
932 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
936 (define_expand "umoddi3"
937 [(use (match_operand:DI 0 "register_operand" ""))
938 (use (match_operand:DI 1 "register_operand" ""))
939 (use (match_operand:DI 2 "register_operand" ""))]
940 "! TARGET_ABI_OPEN_VMS"
942 if (TARGET_ABI_UNICOSMK)
943 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
945 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
949 (define_expand "umoddi3_dft"
950 [(parallel [(set (match_operand:DI 0 "register_operand" "")
951 (umod:DI (match_operand:DI 1 "register_operand" "")
952 (match_operand:DI 2 "register_operand" "")))
953 (clobber (reg:DI 23))
954 (clobber (reg:DI 28))])]
955 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
958 (define_expand "umoddi3_umk"
959 [(use (match_operand:DI 0 "register_operand" ""))
960 (use (match_operand:DI 1 "register_operand" ""))
961 (use (match_operand:DI 2 "register_operand" ""))]
962 "TARGET_ABI_UNICOSMK"
964 rtx div, mul = gen_reg_rtx (DImode);
966 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
967 NULL_RTX, 1, OPTAB_LIB);
968 div = force_reg (DImode, div);
969 emit_insn (gen_muldi3 (mul, operands[2], div));
970 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
974 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
975 ;; expanded by the assembler.
977 (define_insn_and_split "*divmodsi_internal_er"
978 [(set (match_operand:DI 0 "register_operand" "=c")
979 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
980 [(match_operand:DI 1 "register_operand" "a")
981 (match_operand:DI 2 "register_operand" "b")])))
982 (clobber (reg:DI 23))
983 (clobber (reg:DI 28))]
984 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
985 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
986 "&& reload_completed"
987 [(parallel [(set (match_dup 0)
988 (sign_extend:DI (match_dup 3)))
991 (clobber (reg:DI 23))
992 (clobber (reg:DI 28))])]
995 switch (GET_CODE (operands[3]))
1012 operands[4] = GEN_INT (alpha_next_sequence_number++);
1013 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1014 gen_rtx_SYMBOL_REF (DImode, str),
1017 [(set_attr "type" "jsr")
1018 (set_attr "length" "8")])
1020 (define_insn "*divmodsi_internal_er_1"
1021 [(set (match_operand:DI 0 "register_operand" "=c")
1022 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1023 [(match_operand:DI 1 "register_operand" "a")
1024 (match_operand:DI 2 "register_operand" "b")])))
1025 (use (match_operand:DI 4 "register_operand" "c"))
1026 (use (match_operand 5 "const_int_operand" ""))
1027 (clobber (reg:DI 23))
1028 (clobber (reg:DI 28))]
1029 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1030 "jsr $23,($27),__%E3%J5"
1031 [(set_attr "type" "jsr")
1032 (set_attr "length" "4")])
1034 (define_insn "*divmodsi_internal"
1035 [(set (match_operand:DI 0 "register_operand" "=c")
1036 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1037 [(match_operand:DI 1 "register_operand" "a")
1038 (match_operand:DI 2 "register_operand" "b")])))
1039 (clobber (reg:DI 23))
1040 (clobber (reg:DI 28))]
1041 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1043 [(set_attr "type" "jsr")
1044 (set_attr "length" "8")])
1046 (define_insn_and_split "*divmoddi_internal_er"
1047 [(set (match_operand:DI 0 "register_operand" "=c")
1048 (match_operator:DI 3 "divmod_operator"
1049 [(match_operand:DI 1 "register_operand" "a")
1050 (match_operand:DI 2 "register_operand" "b")]))
1051 (clobber (reg:DI 23))
1052 (clobber (reg:DI 28))]
1053 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1054 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1055 "&& reload_completed"
1056 [(parallel [(set (match_dup 0) (match_dup 3))
1059 (clobber (reg:DI 23))
1060 (clobber (reg:DI 28))])]
1063 switch (GET_CODE (operands[3]))
1080 operands[4] = GEN_INT (alpha_next_sequence_number++);
1081 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1082 gen_rtx_SYMBOL_REF (DImode, str),
1085 [(set_attr "type" "jsr")
1086 (set_attr "length" "8")])
1088 (define_insn "*divmoddi_internal_er_1"
1089 [(set (match_operand:DI 0 "register_operand" "=c")
1090 (match_operator:DI 3 "divmod_operator"
1091 [(match_operand:DI 1 "register_operand" "a")
1092 (match_operand:DI 2 "register_operand" "b")]))
1093 (use (match_operand:DI 4 "register_operand" "c"))
1094 (use (match_operand 5 "const_int_operand" ""))
1095 (clobber (reg:DI 23))
1096 (clobber (reg:DI 28))]
1097 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1098 "jsr $23,($27),__%E3%J5"
1099 [(set_attr "type" "jsr")
1100 (set_attr "length" "4")])
1102 (define_insn "*divmoddi_internal"
1103 [(set (match_operand:DI 0 "register_operand" "=c")
1104 (match_operator:DI 3 "divmod_operator"
1105 [(match_operand:DI 1 "register_operand" "a")
1106 (match_operand:DI 2 "register_operand" "b")]))
1107 (clobber (reg:DI 23))
1108 (clobber (reg:DI 28))]
1109 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1111 [(set_attr "type" "jsr")
1112 (set_attr "length" "8")])
1114 ;; Next are the basic logical operations. These only exist in DImode.
1116 (define_insn "anddi3"
1117 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1118 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1119 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1125 [(set_attr "type" "ilog,ilog,shift")])
1127 ;; There are times when we can split an AND into two AND insns. This occurs
1128 ;; when we can first clear any bytes and then clear anything else. For
1129 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1130 ;; Only do this when running on 64-bit host since the computations are
1131 ;; too messy otherwise.
1134 [(set (match_operand:DI 0 "register_operand" "")
1135 (and:DI (match_operand:DI 1 "register_operand" "")
1136 (match_operand:DI 2 "const_int_operand" "")))]
1137 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1138 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1139 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1141 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1142 unsigned HOST_WIDE_INT mask2 = mask1;
1145 /* For each byte that isn't all zeros, make it all ones. */
1146 for (i = 0; i < 64; i += 8)
1147 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1148 mask1 |= (HOST_WIDE_INT) 0xff << i;
1150 /* Now turn on any bits we've just turned off. */
1153 operands[3] = GEN_INT (mask1);
1154 operands[4] = GEN_INT (mask2);
1157 (define_expand "zero_extendqihi2"
1158 [(set (match_operand:HI 0 "register_operand" "")
1159 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1163 operands[1] = force_reg (QImode, operands[1]);
1166 (define_insn "*zero_extendqihi2_bwx"
1167 [(set (match_operand:HI 0 "register_operand" "=r,r")
1168 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1173 [(set_attr "type" "ilog,ild")])
1175 (define_insn "*zero_extendqihi2_nobwx"
1176 [(set (match_operand:HI 0 "register_operand" "=r")
1177 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1180 [(set_attr "type" "ilog")])
1182 (define_expand "zero_extendqisi2"
1183 [(set (match_operand:SI 0 "register_operand" "")
1184 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1188 operands[1] = force_reg (QImode, operands[1]);
1191 (define_insn "*zero_extendqisi2_bwx"
1192 [(set (match_operand:SI 0 "register_operand" "=r,r")
1193 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1198 [(set_attr "type" "ilog,ild")])
1200 (define_insn "*zero_extendqisi2_nobwx"
1201 [(set (match_operand:SI 0 "register_operand" "=r")
1202 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1205 [(set_attr "type" "ilog")])
1207 (define_expand "zero_extendqidi2"
1208 [(set (match_operand:DI 0 "register_operand" "")
1209 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1213 operands[1] = force_reg (QImode, operands[1]);
1216 (define_insn "*zero_extendqidi2_bwx"
1217 [(set (match_operand:DI 0 "register_operand" "=r,r")
1218 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1223 [(set_attr "type" "ilog,ild")])
1225 (define_insn "*zero_extendqidi2_nobwx"
1226 [(set (match_operand:DI 0 "register_operand" "=r")
1227 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1230 [(set_attr "type" "ilog")])
1232 (define_expand "zero_extendhisi2"
1233 [(set (match_operand:SI 0 "register_operand" "")
1234 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1238 operands[1] = force_reg (HImode, operands[1]);
1241 (define_insn "*zero_extendhisi2_bwx"
1242 [(set (match_operand:SI 0 "register_operand" "=r,r")
1243 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1248 [(set_attr "type" "shift,ild")])
1250 (define_insn "*zero_extendhisi2_nobwx"
1251 [(set (match_operand:SI 0 "register_operand" "=r")
1252 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1255 [(set_attr "type" "shift")])
1257 (define_expand "zero_extendhidi2"
1258 [(set (match_operand:DI 0 "register_operand" "")
1259 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1263 operands[1] = force_reg (HImode, operands[1]);
1266 (define_insn "*zero_extendhidi2_bwx"
1267 [(set (match_operand:DI 0 "register_operand" "=r,r")
1268 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1273 [(set_attr "type" "shift,ild")])
1275 (define_insn "*zero_extendhidi2_nobwx"
1276 [(set (match_operand:DI 0 "register_operand" "=r")
1277 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1280 [(set_attr "type" "shift")])
1282 (define_insn "zero_extendsidi2"
1283 [(set (match_operand:DI 0 "register_operand" "=r")
1284 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1287 [(set_attr "type" "shift")])
1289 (define_insn "andnotdi3"
1290 [(set (match_operand:DI 0 "register_operand" "=r")
1291 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1292 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1295 [(set_attr "type" "ilog")])
1297 (define_insn "iordi3"
1298 [(set (match_operand:DI 0 "register_operand" "=r,r")
1299 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1300 (match_operand:DI 2 "or_operand" "rI,N")))]
1305 [(set_attr "type" "ilog")])
1307 (define_insn "one_cmpldi2"
1308 [(set (match_operand:DI 0 "register_operand" "=r")
1309 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1312 [(set_attr "type" "ilog")])
1314 (define_insn "*iornot"
1315 [(set (match_operand:DI 0 "register_operand" "=r")
1316 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1317 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1320 [(set_attr "type" "ilog")])
1322 (define_insn "xordi3"
1323 [(set (match_operand:DI 0 "register_operand" "=r,r")
1324 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1325 (match_operand:DI 2 "or_operand" "rI,N")))]
1330 [(set_attr "type" "ilog")])
1332 (define_insn "*xornot"
1333 [(set (match_operand:DI 0 "register_operand" "=r")
1334 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1335 (match_operand:DI 2 "register_operand" "rI"))))]
1338 [(set_attr "type" "ilog")])
1340 ;; Handle FFS and related insns iff we support CIX.
1342 (define_expand "ffsdi2"
1344 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1346 (plus:DI (match_dup 2) (const_int 1)))
1347 (set (match_operand:DI 0 "register_operand" "")
1348 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1349 (const_int 0) (match_dup 3)))]
1352 operands[2] = gen_reg_rtx (DImode);
1353 operands[3] = gen_reg_rtx (DImode);
1356 (define_insn "*cttz"
1357 [(set (match_operand:DI 0 "register_operand" "=r")
1358 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1361 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1362 ; reuse the existing type name.
1363 [(set_attr "type" "mvi")])
1365 (define_insn "clzdi2"
1366 [(set (match_operand:DI 0 "register_operand" "=r")
1367 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1370 [(set_attr "type" "mvi")])
1372 (define_insn "ctzdi2"
1373 [(set (match_operand:DI 0 "register_operand" "=r")
1374 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1377 [(set_attr "type" "mvi")])
1379 (define_insn "popcountdi2"
1380 [(set (match_operand:DI 0 "register_operand" "=r")
1381 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1384 [(set_attr "type" "mvi")])
1386 ;; Next come the shifts and the various extract and insert operations.
1388 (define_insn "ashldi3"
1389 [(set (match_operand:DI 0 "register_operand" "=r,r")
1390 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1391 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1394 switch (which_alternative)
1397 if (operands[2] == const1_rtx)
1398 return "addq %r1,%r1,%0";
1400 return "s%P2addq %r1,0,%0";
1402 return "sll %r1,%2,%0";
1407 [(set_attr "type" "iadd,shift")])
1409 (define_insn "*ashldi_se"
1410 [(set (match_operand:DI 0 "register_operand" "=r")
1412 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1413 (match_operand:DI 2 "const_int_operand" "P"))
1415 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1417 if (operands[2] == const1_rtx)
1418 return "addl %r1,%r1,%0";
1420 return "s%P2addl %r1,0,%0";
1422 [(set_attr "type" "iadd")])
1424 (define_insn "lshrdi3"
1425 [(set (match_operand:DI 0 "register_operand" "=r")
1426 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1427 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1430 [(set_attr "type" "shift")])
1432 (define_insn "ashrdi3"
1433 [(set (match_operand:DI 0 "register_operand" "=r")
1434 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1435 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1438 [(set_attr "type" "shift")])
1440 (define_expand "extendqihi2"
1442 (ashift:DI (match_operand:QI 1 "some_operand" "")
1444 (set (match_operand:HI 0 "register_operand" "")
1445 (ashiftrt:DI (match_dup 2)
1451 emit_insn (gen_extendqihi2x (operands[0],
1452 force_reg (QImode, operands[1])));
1456 /* If we have an unaligned MEM, extend to DImode (which we do
1457 specially) and then copy to the result. */
1458 if (unaligned_memory_operand (operands[1], HImode))
1460 rtx temp = gen_reg_rtx (DImode);
1462 emit_insn (gen_extendqidi2 (temp, operands[1]));
1463 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1467 operands[0] = gen_lowpart (DImode, operands[0]);
1468 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1469 operands[2] = gen_reg_rtx (DImode);
1472 (define_insn "extendqidi2x"
1473 [(set (match_operand:DI 0 "register_operand" "=r")
1474 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1477 [(set_attr "type" "shift")])
1479 (define_insn "extendhidi2x"
1480 [(set (match_operand:DI 0 "register_operand" "=r")
1481 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1484 [(set_attr "type" "shift")])
1486 (define_insn "extendqisi2x"
1487 [(set (match_operand:SI 0 "register_operand" "=r")
1488 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1491 [(set_attr "type" "shift")])
1493 (define_insn "extendhisi2x"
1494 [(set (match_operand:SI 0 "register_operand" "=r")
1495 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1498 [(set_attr "type" "shift")])
1500 (define_insn "extendqihi2x"
1501 [(set (match_operand:HI 0 "register_operand" "=r")
1502 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1505 [(set_attr "type" "shift")])
1507 (define_expand "extendqisi2"
1509 (ashift:DI (match_operand:QI 1 "some_operand" "")
1511 (set (match_operand:SI 0 "register_operand" "")
1512 (ashiftrt:DI (match_dup 2)
1518 emit_insn (gen_extendqisi2x (operands[0],
1519 force_reg (QImode, operands[1])));
1523 /* If we have an unaligned MEM, extend to a DImode form of
1524 the result (which we do specially). */
1525 if (unaligned_memory_operand (operands[1], QImode))
1527 rtx temp = gen_reg_rtx (DImode);
1529 emit_insn (gen_extendqidi2 (temp, operands[1]));
1530 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1534 operands[0] = gen_lowpart (DImode, operands[0]);
1535 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1536 operands[2] = gen_reg_rtx (DImode);
1539 (define_expand "extendqidi2"
1541 (ashift:DI (match_operand:QI 1 "some_operand" "")
1543 (set (match_operand:DI 0 "register_operand" "")
1544 (ashiftrt:DI (match_dup 2)
1550 emit_insn (gen_extendqidi2x (operands[0],
1551 force_reg (QImode, operands[1])));
1555 if (unaligned_memory_operand (operands[1], QImode))
1558 = gen_unaligned_extendqidi (operands[0],
1559 get_unaligned_address (operands[1], 1));
1561 alpha_set_memflags (seq, operands[1]);
1566 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1567 operands[2] = gen_reg_rtx (DImode);
1570 (define_expand "extendhisi2"
1572 (ashift:DI (match_operand:HI 1 "some_operand" "")
1574 (set (match_operand:SI 0 "register_operand" "")
1575 (ashiftrt:DI (match_dup 2)
1581 emit_insn (gen_extendhisi2x (operands[0],
1582 force_reg (HImode, operands[1])));
1586 /* If we have an unaligned MEM, extend to a DImode form of
1587 the result (which we do specially). */
1588 if (unaligned_memory_operand (operands[1], HImode))
1590 rtx temp = gen_reg_rtx (DImode);
1592 emit_insn (gen_extendhidi2 (temp, operands[1]));
1593 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1597 operands[0] = gen_lowpart (DImode, operands[0]);
1598 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1599 operands[2] = gen_reg_rtx (DImode);
1602 (define_expand "extendhidi2"
1604 (ashift:DI (match_operand:HI 1 "some_operand" "")
1606 (set (match_operand:DI 0 "register_operand" "")
1607 (ashiftrt:DI (match_dup 2)
1613 emit_insn (gen_extendhidi2x (operands[0],
1614 force_reg (HImode, operands[1])));
1618 if (unaligned_memory_operand (operands[1], HImode))
1621 = gen_unaligned_extendhidi (operands[0],
1622 get_unaligned_address (operands[1], 2));
1624 alpha_set_memflags (seq, operands[1]);
1629 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1630 operands[2] = gen_reg_rtx (DImode);
1633 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1634 ;; as a pattern saves one instruction. The code is similar to that for
1635 ;; the unaligned loads (see below).
1637 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1638 (define_expand "unaligned_extendqidi"
1639 [(use (match_operand:QI 0 "register_operand" ""))
1640 (use (match_operand:DI 1 "address_operand" ""))]
1643 if (WORDS_BIG_ENDIAN)
1644 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1646 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1650 (define_expand "unaligned_extendqidi_le"
1651 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1653 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1656 (ashift:DI (match_dup 3)
1657 (minus:DI (const_int 64)
1659 (and:DI (match_dup 2) (const_int 7))
1661 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1662 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1663 "! WORDS_BIG_ENDIAN"
1665 operands[2] = gen_reg_rtx (DImode);
1666 operands[3] = gen_reg_rtx (DImode);
1667 operands[4] = gen_reg_rtx (DImode);
1670 (define_expand "unaligned_extendqidi_be"
1671 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1672 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1674 (mem:DI (and:DI (match_dup 3)
1676 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1678 (ashift:DI (match_dup 4)
1681 (plus:DI (match_dup 5) (const_int 1))
1684 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1685 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1688 operands[2] = gen_reg_rtx (DImode);
1689 operands[3] = gen_reg_rtx (DImode);
1690 operands[4] = gen_reg_rtx (DImode);
1691 operands[5] = gen_reg_rtx (DImode);
1692 operands[6] = gen_reg_rtx (DImode);
1695 (define_expand "unaligned_extendhidi"
1696 [(use (match_operand:QI 0 "register_operand" ""))
1697 (use (match_operand:DI 1 "address_operand" ""))]
1700 operands[0] = gen_lowpart (DImode, operands[0]);
1701 emit_insn ((WORDS_BIG_ENDIAN
1702 ? gen_unaligned_extendhidi_be
1703 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1707 (define_expand "unaligned_extendhidi_le"
1708 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1710 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1713 (ashift:DI (match_dup 3)
1714 (minus:DI (const_int 64)
1716 (and:DI (match_dup 2) (const_int 7))
1718 (set (match_operand:DI 0 "register_operand" "")
1719 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1720 "! WORDS_BIG_ENDIAN"
1722 operands[2] = gen_reg_rtx (DImode);
1723 operands[3] = gen_reg_rtx (DImode);
1724 operands[4] = gen_reg_rtx (DImode);
1727 (define_expand "unaligned_extendhidi_be"
1728 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1729 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1731 (mem:DI (and:DI (match_dup 3)
1733 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1735 (ashift:DI (match_dup 4)
1738 (plus:DI (match_dup 5) (const_int 1))
1741 (set (match_operand:DI 0 "register_operand" "")
1742 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1745 operands[2] = gen_reg_rtx (DImode);
1746 operands[3] = gen_reg_rtx (DImode);
1747 operands[4] = gen_reg_rtx (DImode);
1748 operands[5] = gen_reg_rtx (DImode);
1749 operands[6] = gen_reg_rtx (DImode);
1752 (define_insn "*extxl_const"
1753 [(set (match_operand:DI 0 "register_operand" "=r")
1754 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1755 (match_operand:DI 2 "mode_width_operand" "n")
1756 (match_operand:DI 3 "mul8_operand" "I")))]
1758 "ext%M2l %r1,%s3,%0"
1759 [(set_attr "type" "shift")])
1761 (define_insn "extxl_le"
1762 [(set (match_operand:DI 0 "register_operand" "=r")
1763 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1764 (match_operand:DI 2 "mode_width_operand" "n")
1765 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1767 "! WORDS_BIG_ENDIAN"
1769 [(set_attr "type" "shift")])
1771 (define_insn "extxl_be"
1772 [(set (match_operand:DI 0 "register_operand" "=r")
1773 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1774 (match_operand:DI 2 "mode_width_operand" "n")
1778 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1782 [(set_attr "type" "shift")])
1784 ;; Combine has some strange notion of preserving existing undefined behavior
1785 ;; in shifts larger than a word size. So capture these patterns that it
1786 ;; should have turned into zero_extracts.
1788 (define_insn "*extxl_1_le"
1789 [(set (match_operand:DI 0 "register_operand" "=r")
1790 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1791 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1793 (match_operand:DI 3 "mode_mask_operand" "n")))]
1794 "! WORDS_BIG_ENDIAN"
1796 [(set_attr "type" "shift")])
1798 (define_insn "*extxl_1_be"
1799 [(set (match_operand:DI 0 "register_operand" "=r")
1800 (and:DI (lshiftrt:DI
1801 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1802 (minus:DI (const_int 56)
1803 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1805 (match_operand:DI 3 "mode_mask_operand" "n")))]
1808 [(set_attr "type" "shift")])
1810 (define_insn "*extql_2_le"
1811 [(set (match_operand:DI 0 "register_operand" "=r")
1812 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1813 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1815 "! WORDS_BIG_ENDIAN"
1817 [(set_attr "type" "shift")])
1819 (define_insn "*extql_2_be"
1820 [(set (match_operand:DI 0 "register_operand" "=r")
1822 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1823 (minus:DI (const_int 56)
1825 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1829 [(set_attr "type" "shift")])
1831 (define_insn "extqh_le"
1832 [(set (match_operand:DI 0 "register_operand" "=r")
1834 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1835 (minus:DI (const_int 64)
1838 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1841 "! WORDS_BIG_ENDIAN"
1843 [(set_attr "type" "shift")])
1845 (define_insn "extqh_be"
1846 [(set (match_operand:DI 0 "register_operand" "=r")
1848 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1851 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1857 [(set_attr "type" "shift")])
1859 (define_insn "extlh_le"
1860 [(set (match_operand:DI 0 "register_operand" "=r")
1862 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1863 (const_int 2147483647))
1864 (minus:DI (const_int 64)
1867 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1870 "! WORDS_BIG_ENDIAN"
1872 [(set_attr "type" "shift")])
1874 (define_insn "extlh_be"
1875 [(set (match_operand:DI 0 "register_operand" "=r")
1878 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1882 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1886 (const_int 2147483647)))]
1889 [(set_attr "type" "shift")])
1891 (define_insn "extwh_le"
1892 [(set (match_operand:DI 0 "register_operand" "=r")
1894 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1896 (minus:DI (const_int 64)
1899 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1902 "! WORDS_BIG_ENDIAN"
1904 [(set_attr "type" "shift")])
1906 (define_insn "extwh_be"
1907 [(set (match_operand:DI 0 "register_operand" "=r")
1909 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1913 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1917 (const_int 65535)))]
1920 [(set_attr "type" "shift")])
1922 ;; This converts an extXl into an extXh with an appropriate adjustment
1923 ;; to the address calculation.
1926 ;; [(set (match_operand:DI 0 "register_operand" "")
1927 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1928 ;; (match_operand:DI 2 "mode_width_operand" "")
1929 ;; (ashift:DI (match_operand:DI 3 "" "")
1931 ;; (match_operand:DI 4 "const_int_operand" "")))
1932 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1933 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1934 ;; [(set (match_dup 5) (match_dup 6))
1935 ;; (set (match_dup 0)
1936 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1937 ;; (ashift:DI (plus:DI (match_dup 5)
1943 ;; operands[6] = plus_constant (operands[3],
1944 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1945 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1948 (define_insn "*insbl_const"
1949 [(set (match_operand:DI 0 "register_operand" "=r")
1950 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1951 (match_operand:DI 2 "mul8_operand" "I")))]
1954 [(set_attr "type" "shift")])
1956 (define_insn "*inswl_const"
1957 [(set (match_operand:DI 0 "register_operand" "=r")
1958 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1959 (match_operand:DI 2 "mul8_operand" "I")))]
1962 [(set_attr "type" "shift")])
1964 (define_insn "*insll_const"
1965 [(set (match_operand:DI 0 "register_operand" "=r")
1966 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1967 (match_operand:DI 2 "mul8_operand" "I")))]
1970 [(set_attr "type" "shift")])
1972 (define_insn "insbl_le"
1973 [(set (match_operand:DI 0 "register_operand" "=r")
1974 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1975 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1977 "! WORDS_BIG_ENDIAN"
1979 [(set_attr "type" "shift")])
1981 (define_insn "insbl_be"
1982 [(set (match_operand:DI 0 "register_operand" "=r")
1983 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1984 (minus:DI (const_int 56)
1985 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1989 [(set_attr "type" "shift")])
1991 (define_insn "inswl_le"
1992 [(set (match_operand:DI 0 "register_operand" "=r")
1993 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1994 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1996 "! WORDS_BIG_ENDIAN"
1998 [(set_attr "type" "shift")])
2000 (define_insn "inswl_be"
2001 [(set (match_operand:DI 0 "register_operand" "=r")
2002 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2003 (minus:DI (const_int 56)
2004 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2008 [(set_attr "type" "shift")])
2010 (define_insn "insll_le"
2011 [(set (match_operand:DI 0 "register_operand" "=r")
2012 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2013 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2015 "! WORDS_BIG_ENDIAN"
2017 [(set_attr "type" "shift")])
2019 (define_insn "insll_be"
2020 [(set (match_operand:DI 0 "register_operand" "=r")
2021 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2022 (minus:DI (const_int 56)
2023 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2027 [(set_attr "type" "shift")])
2029 (define_insn "insql_le"
2030 [(set (match_operand:DI 0 "register_operand" "=r")
2031 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2032 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2034 "! WORDS_BIG_ENDIAN"
2036 [(set_attr "type" "shift")])
2038 (define_insn "insql_be"
2039 [(set (match_operand:DI 0 "register_operand" "=r")
2040 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2041 (minus:DI (const_int 56)
2042 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2046 [(set_attr "type" "shift")])
2048 ;; Combine has this sometimes habit of moving the and outside of the
2049 ;; shift, making life more interesting.
2051 (define_insn "*insxl"
2052 [(set (match_operand:DI 0 "register_operand" "=r")
2053 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2054 (match_operand:DI 2 "mul8_operand" "I"))
2055 (match_operand:DI 3 "immediate_operand" "i")))]
2056 "HOST_BITS_PER_WIDE_INT == 64
2057 && GET_CODE (operands[3]) == CONST_INT
2058 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2059 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2060 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2061 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2062 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2063 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2065 #if HOST_BITS_PER_WIDE_INT == 64
2066 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2067 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2068 return "insbl %1,%s2,%0";
2069 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2070 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2071 return "inswl %1,%s2,%0";
2072 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2073 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2074 return "insll %1,%s2,%0";
2078 [(set_attr "type" "shift")])
2080 ;; We do not include the insXh insns because they are complex to express
2081 ;; and it does not appear that we would ever want to generate them.
2083 ;; Since we need them for block moves, though, cop out and use unspec.
2085 (define_insn "insxh"
2086 [(set (match_operand:DI 0 "register_operand" "=r")
2087 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2088 (match_operand:DI 2 "mode_width_operand" "n")
2089 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2093 [(set_attr "type" "shift")])
2095 (define_insn "mskxl_le"
2096 [(set (match_operand:DI 0 "register_operand" "=r")
2097 (and:DI (not:DI (ashift:DI
2098 (match_operand:DI 2 "mode_mask_operand" "n")
2100 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2102 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2103 "! WORDS_BIG_ENDIAN"
2105 [(set_attr "type" "shift")])
2107 (define_insn "mskxl_be"
2108 [(set (match_operand:DI 0 "register_operand" "=r")
2109 (and:DI (not:DI (ashift:DI
2110 (match_operand:DI 2 "mode_mask_operand" "n")
2111 (minus:DI (const_int 56)
2113 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2115 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2118 [(set_attr "type" "shift")])
2120 ;; We do not include the mskXh insns because it does not appear we would
2121 ;; ever generate one.
2123 ;; Again, we do for block moves and we use unspec again.
2125 (define_insn "mskxh"
2126 [(set (match_operand:DI 0 "register_operand" "=r")
2127 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2128 (match_operand:DI 2 "mode_width_operand" "n")
2129 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2133 [(set_attr "type" "shift")])
2135 ;; Prefer AND + NE over LSHIFTRT + AND.
2137 (define_insn_and_split "*ze_and_ne"
2138 [(set (match_operand:DI 0 "register_operand" "=r")
2139 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2141 (match_operand 2 "const_int_operand" "I")))]
2142 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2144 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2146 (and:DI (match_dup 1) (match_dup 3)))
2148 (ne:DI (match_dup 0) (const_int 0)))]
2149 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2151 ;; Floating-point operations. All the double-precision insns can extend
2152 ;; from single, so indicate that. The exception are the ones that simply
2153 ;; play with the sign bits; it's not clear what to do there.
2155 (define_insn "abssf2"
2156 [(set (match_operand:SF 0 "register_operand" "=f")
2157 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2160 [(set_attr "type" "fcpys")])
2162 (define_insn "*nabssf2"
2163 [(set (match_operand:SF 0 "register_operand" "=f")
2164 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2167 [(set_attr "type" "fadd")])
2169 (define_insn "absdf2"
2170 [(set (match_operand:DF 0 "register_operand" "=f")
2171 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2174 [(set_attr "type" "fcpys")])
2176 (define_insn "*nabsdf2"
2177 [(set (match_operand:DF 0 "register_operand" "=f")
2178 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2181 [(set_attr "type" "fadd")])
2183 (define_expand "abstf2"
2184 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2185 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2186 (use (match_dup 2))])]
2187 "TARGET_HAS_XFLOATING_LIBS"
2189 #if HOST_BITS_PER_WIDE_INT >= 64
2190 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2192 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2196 (define_insn_and_split "*abstf_internal"
2197 [(set (match_operand:TF 0 "register_operand" "=r")
2198 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2199 (use (match_operand:DI 2 "register_operand" "r"))]
2200 "TARGET_HAS_XFLOATING_LIBS"
2202 "&& reload_completed"
2204 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2206 (define_insn "negsf2"
2207 [(set (match_operand:SF 0 "register_operand" "=f")
2208 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2211 [(set_attr "type" "fadd")])
2213 (define_insn "negdf2"
2214 [(set (match_operand:DF 0 "register_operand" "=f")
2215 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2218 [(set_attr "type" "fadd")])
2220 (define_expand "negtf2"
2221 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2222 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2223 (use (match_dup 2))])]
2224 "TARGET_HAS_XFLOATING_LIBS"
2226 #if HOST_BITS_PER_WIDE_INT >= 64
2227 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2229 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2233 (define_insn_and_split "*negtf_internal"
2234 [(set (match_operand:TF 0 "register_operand" "=r")
2235 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2236 (use (match_operand:DI 2 "register_operand" "r"))]
2237 "TARGET_HAS_XFLOATING_LIBS"
2239 "&& reload_completed"
2241 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2243 (define_insn "*addsf_ieee"
2244 [(set (match_operand:SF 0 "register_operand" "=&f")
2245 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2246 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2247 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2248 "add%,%/ %R1,%R2,%0"
2249 [(set_attr "type" "fadd")
2250 (set_attr "trap" "yes")
2251 (set_attr "round_suffix" "normal")
2252 (set_attr "trap_suffix" "u_su_sui")])
2254 (define_insn "addsf3"
2255 [(set (match_operand:SF 0 "register_operand" "=f")
2256 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2257 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2259 "add%,%/ %R1,%R2,%0"
2260 [(set_attr "type" "fadd")
2261 (set_attr "trap" "yes")
2262 (set_attr "round_suffix" "normal")
2263 (set_attr "trap_suffix" "u_su_sui")])
2265 (define_insn "*adddf_ieee"
2266 [(set (match_operand:DF 0 "register_operand" "=&f")
2267 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2268 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2269 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2270 "add%-%/ %R1,%R2,%0"
2271 [(set_attr "type" "fadd")
2272 (set_attr "trap" "yes")
2273 (set_attr "round_suffix" "normal")
2274 (set_attr "trap_suffix" "u_su_sui")])
2276 (define_insn "adddf3"
2277 [(set (match_operand:DF 0 "register_operand" "=f")
2278 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2279 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2281 "add%-%/ %R1,%R2,%0"
2282 [(set_attr "type" "fadd")
2283 (set_attr "trap" "yes")
2284 (set_attr "round_suffix" "normal")
2285 (set_attr "trap_suffix" "u_su_sui")])
2287 (define_insn "*adddf_ext1"
2288 [(set (match_operand:DF 0 "register_operand" "=f")
2289 (plus:DF (float_extend:DF
2290 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2291 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2292 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2293 "add%-%/ %R1,%R2,%0"
2294 [(set_attr "type" "fadd")
2295 (set_attr "trap" "yes")
2296 (set_attr "round_suffix" "normal")
2297 (set_attr "trap_suffix" "u_su_sui")])
2299 (define_insn "*adddf_ext2"
2300 [(set (match_operand:DF 0 "register_operand" "=f")
2301 (plus:DF (float_extend:DF
2302 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2304 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2305 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2306 "add%-%/ %R1,%R2,%0"
2307 [(set_attr "type" "fadd")
2308 (set_attr "trap" "yes")
2309 (set_attr "round_suffix" "normal")
2310 (set_attr "trap_suffix" "u_su_sui")])
2312 (define_expand "addtf3"
2313 [(use (match_operand 0 "register_operand" ""))
2314 (use (match_operand 1 "general_operand" ""))
2315 (use (match_operand 2 "general_operand" ""))]
2316 "TARGET_HAS_XFLOATING_LIBS"
2317 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2319 ;; Define conversion operators between DFmode and SImode, using the cvtql
2320 ;; instruction. To allow combine et al to do useful things, we keep the
2321 ;; operation as a unit until after reload, at which point we split the
2324 ;; Note that we (attempt to) only consider this optimization when the
2325 ;; ultimate destination is memory. If we will be doing further integer
2326 ;; processing, it is cheaper to do the truncation in the int regs.
2328 (define_insn "*cvtql"
2329 [(set (match_operand:SI 0 "register_operand" "=f")
2330 (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2334 [(set_attr "type" "fadd")
2335 (set_attr "trap" "yes")
2336 (set_attr "trap_suffix" "v_sv")])
2338 (define_insn_and_split "*fix_truncdfsi_ieee"
2339 [(set (match_operand:SI 0 "memory_operand" "=m")
2340 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2341 (clobber (match_scratch:DI 2 "=&f"))
2342 (clobber (match_scratch:SI 3 "=&f"))]
2343 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2345 "&& reload_completed"
2346 [(set (match_dup 2) (fix:DI (match_dup 1)))
2347 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2348 (set (match_dup 0) (match_dup 3))]
2350 [(set_attr "type" "fadd")
2351 (set_attr "trap" "yes")])
2353 (define_insn_and_split "*fix_truncdfsi_internal"
2354 [(set (match_operand:SI 0 "memory_operand" "=m")
2355 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2356 (clobber (match_scratch:DI 2 "=f"))]
2357 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2359 "&& reload_completed"
2360 [(set (match_dup 2) (fix:DI (match_dup 1)))
2361 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2362 (set (match_dup 0) (match_dup 3))]
2363 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2364 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2365 [(set_attr "type" "fadd")
2366 (set_attr "trap" "yes")])
2368 (define_insn "*fix_truncdfdi_ieee"
2369 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2370 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2371 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2373 [(set_attr "type" "fadd")
2374 (set_attr "trap" "yes")
2375 (set_attr "round_suffix" "c")
2376 (set_attr "trap_suffix" "v_sv_svi")])
2378 (define_insn "fix_truncdfdi2"
2379 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2380 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2383 [(set_attr "type" "fadd")
2384 (set_attr "trap" "yes")
2385 (set_attr "round_suffix" "c")
2386 (set_attr "trap_suffix" "v_sv_svi")])
2388 ;; Likewise between SFmode and SImode.
2390 (define_insn_and_split "*fix_truncsfsi_ieee"
2391 [(set (match_operand:SI 0 "memory_operand" "=m")
2392 (subreg:SI (fix:DI (float_extend:DF
2393 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2394 (clobber (match_scratch:DI 2 "=&f"))
2395 (clobber (match_scratch:SI 3 "=&f"))]
2396 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2398 "&& reload_completed"
2399 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2400 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2401 (set (match_dup 0) (match_dup 3))]
2403 [(set_attr "type" "fadd")
2404 (set_attr "trap" "yes")])
2406 (define_insn_and_split "*fix_truncsfsi_internal"
2407 [(set (match_operand:SI 0 "memory_operand" "=m")
2408 (subreg:SI (fix:DI (float_extend:DF
2409 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2410 (clobber (match_scratch:DI 2 "=f"))]
2411 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2413 "&& reload_completed"
2414 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2415 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2416 (set (match_dup 0) (match_dup 3))]
2417 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2418 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2419 [(set_attr "type" "fadd")
2420 (set_attr "trap" "yes")])
2422 (define_insn "*fix_truncsfdi_ieee"
2423 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2424 (fix:DI (float_extend:DF
2425 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2426 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2428 [(set_attr "type" "fadd")
2429 (set_attr "trap" "yes")
2430 (set_attr "round_suffix" "c")
2431 (set_attr "trap_suffix" "v_sv_svi")])
2433 (define_insn "fix_truncsfdi2"
2434 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2435 (fix:DI (float_extend:DF
2436 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2439 [(set_attr "type" "fadd")
2440 (set_attr "trap" "yes")
2441 (set_attr "round_suffix" "c")
2442 (set_attr "trap_suffix" "v_sv_svi")])
2444 (define_expand "fix_trunctfdi2"
2445 [(use (match_operand:DI 0 "register_operand" ""))
2446 (use (match_operand:TF 1 "general_operand" ""))]
2447 "TARGET_HAS_XFLOATING_LIBS"
2448 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2450 (define_insn "*floatdisf_ieee"
2451 [(set (match_operand:SF 0 "register_operand" "=&f")
2452 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2453 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2455 [(set_attr "type" "fadd")
2456 (set_attr "trap" "yes")
2457 (set_attr "round_suffix" "normal")
2458 (set_attr "trap_suffix" "sui")])
2460 (define_insn "floatdisf2"
2461 [(set (match_operand:SF 0 "register_operand" "=f")
2462 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2465 [(set_attr "type" "fadd")
2466 (set_attr "trap" "yes")
2467 (set_attr "round_suffix" "normal")
2468 (set_attr "trap_suffix" "sui")])
2470 (define_insn "*floatdidf_ieee"
2471 [(set (match_operand:DF 0 "register_operand" "=&f")
2472 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2473 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2475 [(set_attr "type" "fadd")
2476 (set_attr "trap" "yes")
2477 (set_attr "round_suffix" "normal")
2478 (set_attr "trap_suffix" "sui")])
2480 (define_insn "floatdidf2"
2481 [(set (match_operand:DF 0 "register_operand" "=f")
2482 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2485 [(set_attr "type" "fadd")
2486 (set_attr "trap" "yes")
2487 (set_attr "round_suffix" "normal")
2488 (set_attr "trap_suffix" "sui")])
2490 (define_expand "floatditf2"
2491 [(use (match_operand:TF 0 "register_operand" ""))
2492 (use (match_operand:DI 1 "general_operand" ""))]
2493 "TARGET_HAS_XFLOATING_LIBS"
2494 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2496 (define_expand "floatunsdisf2"
2497 [(use (match_operand:SF 0 "register_operand" ""))
2498 (use (match_operand:DI 1 "register_operand" ""))]
2500 "alpha_emit_floatuns (operands); DONE;")
2502 (define_expand "floatunsdidf2"
2503 [(use (match_operand:DF 0 "register_operand" ""))
2504 (use (match_operand:DI 1 "register_operand" ""))]
2506 "alpha_emit_floatuns (operands); DONE;")
2508 (define_expand "floatunsditf2"
2509 [(use (match_operand:TF 0 "register_operand" ""))
2510 (use (match_operand:DI 1 "general_operand" ""))]
2511 "TARGET_HAS_XFLOATING_LIBS"
2512 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2514 (define_expand "extendsfdf2"
2515 [(set (match_operand:DF 0 "register_operand" "")
2516 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2519 if (alpha_fptm >= ALPHA_FPTM_SU)
2520 operands[1] = force_reg (SFmode, operands[1]);
2523 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2524 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2526 (define_insn "*extendsfdf2_ieee"
2527 [(set (match_operand:DF 0 "register_operand" "=&f")
2528 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2529 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2531 [(set_attr "type" "fadd")
2532 (set_attr "trap" "yes")])
2534 (define_insn "*extendsfdf2_internal"
2535 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2536 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2537 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2542 [(set_attr "type" "fcpys,fld,fst")])
2544 (define_expand "extendsftf2"
2545 [(use (match_operand:TF 0 "register_operand" ""))
2546 (use (match_operand:SF 1 "general_operand" ""))]
2547 "TARGET_HAS_XFLOATING_LIBS"
2549 rtx tmp = gen_reg_rtx (DFmode);
2550 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2551 emit_insn (gen_extenddftf2 (operands[0], tmp));
2555 (define_expand "extenddftf2"
2556 [(use (match_operand:TF 0 "register_operand" ""))
2557 (use (match_operand:DF 1 "general_operand" ""))]
2558 "TARGET_HAS_XFLOATING_LIBS"
2559 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2561 (define_insn "*truncdfsf2_ieee"
2562 [(set (match_operand:SF 0 "register_operand" "=&f")
2563 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2564 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2566 [(set_attr "type" "fadd")
2567 (set_attr "trap" "yes")
2568 (set_attr "round_suffix" "normal")
2569 (set_attr "trap_suffix" "u_su_sui")])
2571 (define_insn "truncdfsf2"
2572 [(set (match_operand:SF 0 "register_operand" "=f")
2573 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2576 [(set_attr "type" "fadd")
2577 (set_attr "trap" "yes")
2578 (set_attr "round_suffix" "normal")
2579 (set_attr "trap_suffix" "u_su_sui")])
2581 (define_expand "trunctfdf2"
2582 [(use (match_operand:DF 0 "register_operand" ""))
2583 (use (match_operand:TF 1 "general_operand" ""))]
2584 "TARGET_HAS_XFLOATING_LIBS"
2585 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2587 (define_expand "trunctfsf2"
2588 [(use (match_operand:SF 0 "register_operand" ""))
2589 (use (match_operand:TF 1 "general_operand" ""))]
2590 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2592 rtx tmpf, sticky, arg, lo, hi;
2594 tmpf = gen_reg_rtx (DFmode);
2595 sticky = gen_reg_rtx (DImode);
2596 arg = copy_to_mode_reg (TFmode, operands[1]);
2597 lo = gen_lowpart (DImode, arg);
2598 hi = gen_highpart (DImode, arg);
2600 /* Convert the low word of the TFmode value into a sticky rounding bit,
2601 then or it into the low bit of the high word. This leaves the sticky
2602 bit at bit 48 of the fraction, which is representable in DFmode,
2603 which prevents rounding error in the final conversion to SFmode. */
2605 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2606 gen_rtx_NE (DImode, lo, const0_rtx)));
2607 emit_insn (gen_iordi3 (hi, hi, sticky));
2608 emit_insn (gen_trunctfdf2 (tmpf, arg));
2609 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2613 (define_insn "*divsf3_ieee"
2614 [(set (match_operand:SF 0 "register_operand" "=&f")
2615 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2616 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2617 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2618 "div%,%/ %R1,%R2,%0"
2619 [(set_attr "type" "fdiv")
2620 (set_attr "opsize" "si")
2621 (set_attr "trap" "yes")
2622 (set_attr "round_suffix" "normal")
2623 (set_attr "trap_suffix" "u_su_sui")])
2625 (define_insn "divsf3"
2626 [(set (match_operand:SF 0 "register_operand" "=f")
2627 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2628 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2630 "div%,%/ %R1,%R2,%0"
2631 [(set_attr "type" "fdiv")
2632 (set_attr "opsize" "si")
2633 (set_attr "trap" "yes")
2634 (set_attr "round_suffix" "normal")
2635 (set_attr "trap_suffix" "u_su_sui")])
2637 (define_insn "*divdf3_ieee"
2638 [(set (match_operand:DF 0 "register_operand" "=&f")
2639 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2640 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2641 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2642 "div%-%/ %R1,%R2,%0"
2643 [(set_attr "type" "fdiv")
2644 (set_attr "trap" "yes")
2645 (set_attr "round_suffix" "normal")
2646 (set_attr "trap_suffix" "u_su_sui")])
2648 (define_insn "divdf3"
2649 [(set (match_operand:DF 0 "register_operand" "=f")
2650 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2651 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2653 "div%-%/ %R1,%R2,%0"
2654 [(set_attr "type" "fdiv")
2655 (set_attr "trap" "yes")
2656 (set_attr "round_suffix" "normal")
2657 (set_attr "trap_suffix" "u_su_sui")])
2659 (define_insn "*divdf_ext1"
2660 [(set (match_operand:DF 0 "register_operand" "=f")
2661 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2662 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2663 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2664 "div%-%/ %R1,%R2,%0"
2665 [(set_attr "type" "fdiv")
2666 (set_attr "trap" "yes")
2667 (set_attr "round_suffix" "normal")
2668 (set_attr "trap_suffix" "u_su_sui")])
2670 (define_insn "*divdf_ext2"
2671 [(set (match_operand:DF 0 "register_operand" "=f")
2672 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2674 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2675 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2676 "div%-%/ %R1,%R2,%0"
2677 [(set_attr "type" "fdiv")
2678 (set_attr "trap" "yes")
2679 (set_attr "round_suffix" "normal")
2680 (set_attr "trap_suffix" "u_su_sui")])
2682 (define_insn "*divdf_ext3"
2683 [(set (match_operand:DF 0 "register_operand" "=f")
2684 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2685 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2686 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2687 "div%-%/ %R1,%R2,%0"
2688 [(set_attr "type" "fdiv")
2689 (set_attr "trap" "yes")
2690 (set_attr "round_suffix" "normal")
2691 (set_attr "trap_suffix" "u_su_sui")])
2693 (define_expand "divtf3"
2694 [(use (match_operand 0 "register_operand" ""))
2695 (use (match_operand 1 "general_operand" ""))
2696 (use (match_operand 2 "general_operand" ""))]
2697 "TARGET_HAS_XFLOATING_LIBS"
2698 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2700 (define_insn "*mulsf3_ieee"
2701 [(set (match_operand:SF 0 "register_operand" "=&f")
2702 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2703 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2704 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2705 "mul%,%/ %R1,%R2,%0"
2706 [(set_attr "type" "fmul")
2707 (set_attr "trap" "yes")
2708 (set_attr "round_suffix" "normal")
2709 (set_attr "trap_suffix" "u_su_sui")])
2711 (define_insn "mulsf3"
2712 [(set (match_operand:SF 0 "register_operand" "=f")
2713 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2714 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2716 "mul%,%/ %R1,%R2,%0"
2717 [(set_attr "type" "fmul")
2718 (set_attr "trap" "yes")
2719 (set_attr "round_suffix" "normal")
2720 (set_attr "trap_suffix" "u_su_sui")])
2722 (define_insn "*muldf3_ieee"
2723 [(set (match_operand:DF 0 "register_operand" "=&f")
2724 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2725 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2726 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2727 "mul%-%/ %R1,%R2,%0"
2728 [(set_attr "type" "fmul")
2729 (set_attr "trap" "yes")
2730 (set_attr "round_suffix" "normal")
2731 (set_attr "trap_suffix" "u_su_sui")])
2733 (define_insn "muldf3"
2734 [(set (match_operand:DF 0 "register_operand" "=f")
2735 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2736 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2738 "mul%-%/ %R1,%R2,%0"
2739 [(set_attr "type" "fmul")
2740 (set_attr "trap" "yes")
2741 (set_attr "round_suffix" "normal")
2742 (set_attr "trap_suffix" "u_su_sui")])
2744 (define_insn "*muldf_ext1"
2745 [(set (match_operand:DF 0 "register_operand" "=f")
2746 (mult:DF (float_extend:DF
2747 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2748 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2749 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2750 "mul%-%/ %R1,%R2,%0"
2751 [(set_attr "type" "fmul")
2752 (set_attr "trap" "yes")
2753 (set_attr "round_suffix" "normal")
2754 (set_attr "trap_suffix" "u_su_sui")])
2756 (define_insn "*muldf_ext2"
2757 [(set (match_operand:DF 0 "register_operand" "=f")
2758 (mult:DF (float_extend:DF
2759 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2761 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2762 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2763 "mul%-%/ %R1,%R2,%0"
2764 [(set_attr "type" "fmul")
2765 (set_attr "trap" "yes")
2766 (set_attr "round_suffix" "normal")
2767 (set_attr "trap_suffix" "u_su_sui")])
2769 (define_expand "multf3"
2770 [(use (match_operand 0 "register_operand" ""))
2771 (use (match_operand 1 "general_operand" ""))
2772 (use (match_operand 2 "general_operand" ""))]
2773 "TARGET_HAS_XFLOATING_LIBS"
2774 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2776 (define_insn "*subsf3_ieee"
2777 [(set (match_operand:SF 0 "register_operand" "=&f")
2778 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2779 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2780 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2781 "sub%,%/ %R1,%R2,%0"
2782 [(set_attr "type" "fadd")
2783 (set_attr "trap" "yes")
2784 (set_attr "round_suffix" "normal")
2785 (set_attr "trap_suffix" "u_su_sui")])
2787 (define_insn "subsf3"
2788 [(set (match_operand:SF 0 "register_operand" "=f")
2789 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2790 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2792 "sub%,%/ %R1,%R2,%0"
2793 [(set_attr "type" "fadd")
2794 (set_attr "trap" "yes")
2795 (set_attr "round_suffix" "normal")
2796 (set_attr "trap_suffix" "u_su_sui")])
2798 (define_insn "*subdf3_ieee"
2799 [(set (match_operand:DF 0 "register_operand" "=&f")
2800 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2801 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2802 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2803 "sub%-%/ %R1,%R2,%0"
2804 [(set_attr "type" "fadd")
2805 (set_attr "trap" "yes")
2806 (set_attr "round_suffix" "normal")
2807 (set_attr "trap_suffix" "u_su_sui")])
2809 (define_insn "subdf3"
2810 [(set (match_operand:DF 0 "register_operand" "=f")
2811 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2812 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2814 "sub%-%/ %R1,%R2,%0"
2815 [(set_attr "type" "fadd")
2816 (set_attr "trap" "yes")
2817 (set_attr "round_suffix" "normal")
2818 (set_attr "trap_suffix" "u_su_sui")])
2820 (define_insn "*subdf_ext1"
2821 [(set (match_operand:DF 0 "register_operand" "=f")
2822 (minus:DF (float_extend:DF
2823 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2824 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2825 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2826 "sub%-%/ %R1,%R2,%0"
2827 [(set_attr "type" "fadd")
2828 (set_attr "trap" "yes")
2829 (set_attr "round_suffix" "normal")
2830 (set_attr "trap_suffix" "u_su_sui")])
2832 (define_insn "*subdf_ext2"
2833 [(set (match_operand:DF 0 "register_operand" "=f")
2834 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2836 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2837 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2838 "sub%-%/ %R1,%R2,%0"
2839 [(set_attr "type" "fadd")
2840 (set_attr "trap" "yes")
2841 (set_attr "round_suffix" "normal")
2842 (set_attr "trap_suffix" "u_su_sui")])
2844 (define_insn "*subdf_ext3"
2845 [(set (match_operand:DF 0 "register_operand" "=f")
2846 (minus:DF (float_extend:DF
2847 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2849 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2850 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2851 "sub%-%/ %R1,%R2,%0"
2852 [(set_attr "type" "fadd")
2853 (set_attr "trap" "yes")
2854 (set_attr "round_suffix" "normal")
2855 (set_attr "trap_suffix" "u_su_sui")])
2857 (define_expand "subtf3"
2858 [(use (match_operand 0 "register_operand" ""))
2859 (use (match_operand 1 "general_operand" ""))
2860 (use (match_operand 2 "general_operand" ""))]
2861 "TARGET_HAS_XFLOATING_LIBS"
2862 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2864 (define_insn "*sqrtsf2_ieee"
2865 [(set (match_operand:SF 0 "register_operand" "=&f")
2866 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2867 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2869 [(set_attr "type" "fsqrt")
2870 (set_attr "opsize" "si")
2871 (set_attr "trap" "yes")
2872 (set_attr "round_suffix" "normal")
2873 (set_attr "trap_suffix" "u_su_sui")])
2875 (define_insn "sqrtsf2"
2876 [(set (match_operand:SF 0 "register_operand" "=f")
2877 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2878 "TARGET_FP && TARGET_FIX"
2880 [(set_attr "type" "fsqrt")
2881 (set_attr "opsize" "si")
2882 (set_attr "trap" "yes")
2883 (set_attr "round_suffix" "normal")
2884 (set_attr "trap_suffix" "u_su_sui")])
2886 (define_insn "*sqrtdf2_ieee"
2887 [(set (match_operand:DF 0 "register_operand" "=&f")
2888 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2889 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2891 [(set_attr "type" "fsqrt")
2892 (set_attr "trap" "yes")
2893 (set_attr "round_suffix" "normal")
2894 (set_attr "trap_suffix" "u_su_sui")])
2896 (define_insn "sqrtdf2"
2897 [(set (match_operand:DF 0 "register_operand" "=f")
2898 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2899 "TARGET_FP && TARGET_FIX"
2901 [(set_attr "type" "fsqrt")
2902 (set_attr "trap" "yes")
2903 (set_attr "round_suffix" "normal")
2904 (set_attr "trap_suffix" "u_su_sui")])
2906 ;; Next are all the integer comparisons, and conditional moves and branches
2907 ;; and some of the related define_expand's and define_split's.
2909 (define_insn "*setcc_internal"
2910 [(set (match_operand 0 "register_operand" "=r")
2911 (match_operator 1 "alpha_comparison_operator"
2912 [(match_operand:DI 2 "register_operand" "r")
2913 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2914 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2915 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2916 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2918 [(set_attr "type" "icmp")])
2920 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2921 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2923 (define_insn "*setcc_swapped_internal"
2924 [(set (match_operand 0 "register_operand" "=r")
2925 (match_operator 1 "alpha_swapped_comparison_operator"
2926 [(match_operand:DI 2 "register_operand" "r")
2927 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2928 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2929 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2930 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2932 [(set_attr "type" "icmp")])
2934 ;; Use match_operator rather than ne directly so that we can match
2935 ;; multiple integer modes.
2936 (define_insn "*setne_internal"
2937 [(set (match_operand 0 "register_operand" "=r")
2938 (match_operator 1 "signed_comparison_operator"
2939 [(match_operand:DI 2 "register_operand" "r")
2941 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2942 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2943 && GET_CODE (operands[1]) == NE
2944 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2946 [(set_attr "type" "icmp")])
2948 ;; The mode folding trick can't be used with const_int operands, since
2949 ;; reload needs to know the proper mode.
2951 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2952 ;; in order to create more pairs of constants. As long as we're allowing
2953 ;; two constants at the same time, and will have to reload one of them...
2955 (define_insn "*movqicc_internal"
2956 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2958 (match_operator 2 "signed_comparison_operator"
2959 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2960 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2961 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2962 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2963 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2969 [(set_attr "type" "icmov")])
2971 (define_insn "*movhicc_internal"
2972 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2974 (match_operator 2 "signed_comparison_operator"
2975 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2976 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2977 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2978 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2979 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2985 [(set_attr "type" "icmov")])
2987 (define_insn "*movsicc_internal"
2988 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2990 (match_operator 2 "signed_comparison_operator"
2991 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2992 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2993 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2994 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2995 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3001 [(set_attr "type" "icmov")])
3003 (define_insn "*movdicc_internal"
3004 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3006 (match_operator 2 "signed_comparison_operator"
3007 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3008 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3009 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3010 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3011 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3017 [(set_attr "type" "icmov")])
3019 (define_insn "*movqicc_lbc"
3020 [(set (match_operand:QI 0 "register_operand" "=r,r")
3022 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3026 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3027 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3032 [(set_attr "type" "icmov")])
3034 (define_insn "*movhicc_lbc"
3035 [(set (match_operand:HI 0 "register_operand" "=r,r")
3037 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3041 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3042 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3047 [(set_attr "type" "icmov")])
3049 (define_insn "*movsicc_lbc"
3050 [(set (match_operand:SI 0 "register_operand" "=r,r")
3052 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3056 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3057 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3062 [(set_attr "type" "icmov")])
3064 (define_insn "*movdicc_lbc"
3065 [(set (match_operand:DI 0 "register_operand" "=r,r")
3067 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3071 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3072 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3077 [(set_attr "type" "icmov")])
3079 (define_insn "*movqicc_lbs"
3080 [(set (match_operand:QI 0 "register_operand" "=r,r")
3082 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3086 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3087 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3092 [(set_attr "type" "icmov")])
3094 (define_insn "*movhicc_lbs"
3095 [(set (match_operand:HI 0 "register_operand" "=r,r")
3097 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3101 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3102 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3107 [(set_attr "type" "icmov")])
3109 (define_insn "*movsicc_lbs"
3110 [(set (match_operand:SI 0 "register_operand" "=r,r")
3112 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3116 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3117 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3122 [(set_attr "type" "icmov")])
3124 (define_insn "*movdicc_lbs"
3125 [(set (match_operand:DI 0 "register_operand" "=r,r")
3127 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3131 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3132 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3137 [(set_attr "type" "icmov")])
3139 ;; For ABS, we have two choices, depending on whether the input and output
3140 ;; registers are the same or not.
3141 (define_expand "absdi2"
3142 [(set (match_operand:DI 0 "register_operand" "")
3143 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3146 if (rtx_equal_p (operands[0], operands[1]))
3147 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3149 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3153 (define_expand "absdi2_same"
3154 [(set (match_operand:DI 1 "register_operand" "")
3155 (neg:DI (match_operand:DI 0 "register_operand" "")))
3157 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3163 (define_expand "absdi2_diff"
3164 [(set (match_operand:DI 0 "register_operand" "")
3165 (neg:DI (match_operand:DI 1 "register_operand" "")))
3167 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3174 [(set (match_operand:DI 0 "register_operand" "")
3175 (abs:DI (match_dup 0)))
3176 (clobber (match_operand:DI 1 "register_operand" ""))]
3178 [(set (match_dup 1) (neg:DI (match_dup 0)))
3179 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3180 (match_dup 0) (match_dup 1)))]
3184 [(set (match_operand:DI 0 "register_operand" "")
3185 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3186 "! rtx_equal_p (operands[0], operands[1])"
3187 [(set (match_dup 0) (neg:DI (match_dup 1)))
3188 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3189 (match_dup 0) (match_dup 1)))]
3193 [(set (match_operand:DI 0 "register_operand" "")
3194 (neg:DI (abs:DI (match_dup 0))))
3195 (clobber (match_operand:DI 1 "register_operand" ""))]
3197 [(set (match_dup 1) (neg:DI (match_dup 0)))
3198 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3199 (match_dup 0) (match_dup 1)))]
3203 [(set (match_operand:DI 0 "register_operand" "")
3204 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3205 "! rtx_equal_p (operands[0], operands[1])"
3206 [(set (match_dup 0) (neg:DI (match_dup 1)))
3207 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3208 (match_dup 0) (match_dup 1)))]
3211 (define_insn "sminqi3"
3212 [(set (match_operand:QI 0 "register_operand" "=r")
3213 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3214 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3217 [(set_attr "type" "mvi")])
3219 (define_insn "uminqi3"
3220 [(set (match_operand:QI 0 "register_operand" "=r")
3221 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3222 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3225 [(set_attr "type" "mvi")])
3227 (define_insn "smaxqi3"
3228 [(set (match_operand:QI 0 "register_operand" "=r")
3229 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3230 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3233 [(set_attr "type" "mvi")])
3235 (define_insn "umaxqi3"
3236 [(set (match_operand:QI 0 "register_operand" "=r")
3237 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3238 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3241 [(set_attr "type" "mvi")])
3243 (define_insn "sminhi3"
3244 [(set (match_operand:HI 0 "register_operand" "=r")
3245 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3246 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3249 [(set_attr "type" "mvi")])
3251 (define_insn "uminhi3"
3252 [(set (match_operand:HI 0 "register_operand" "=r")
3253 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3254 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3257 [(set_attr "type" "mvi")])
3259 (define_insn "smaxhi3"
3260 [(set (match_operand:HI 0 "register_operand" "=r")
3261 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3262 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3265 [(set_attr "type" "mvi")])
3267 (define_insn "umaxhi3"
3268 [(set (match_operand:HI 0 "register_operand" "=r")
3269 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3270 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3273 [(set_attr "type" "mvi")])
3275 (define_expand "smaxdi3"
3277 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3278 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3279 (set (match_operand:DI 0 "register_operand" "")
3280 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3281 (match_dup 1) (match_dup 2)))]
3283 { operands[3] = gen_reg_rtx (DImode); })
3286 [(set (match_operand:DI 0 "register_operand" "")
3287 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3288 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3289 (clobber (match_operand:DI 3 "register_operand" ""))]
3290 "operands[2] != const0_rtx"
3291 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3292 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3293 (match_dup 1) (match_dup 2)))]
3296 (define_insn "*smax_const0"
3297 [(set (match_operand:DI 0 "register_operand" "=r")
3298 (smax:DI (match_operand:DI 1 "register_operand" "0")
3302 [(set_attr "type" "icmov")])
3304 (define_expand "smindi3"
3306 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3307 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3308 (set (match_operand:DI 0 "register_operand" "")
3309 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3310 (match_dup 1) (match_dup 2)))]
3312 { operands[3] = gen_reg_rtx (DImode); })
3315 [(set (match_operand:DI 0 "register_operand" "")
3316 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3317 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3318 (clobber (match_operand:DI 3 "register_operand" ""))]
3319 "operands[2] != const0_rtx"
3320 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3321 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3322 (match_dup 1) (match_dup 2)))]
3325 (define_insn "*smin_const0"
3326 [(set (match_operand:DI 0 "register_operand" "=r")
3327 (smin:DI (match_operand:DI 1 "register_operand" "0")
3331 [(set_attr "type" "icmov")])
3333 (define_expand "umaxdi3"
3335 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3336 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3337 (set (match_operand:DI 0 "register_operand" "")
3338 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3339 (match_dup 1) (match_dup 2)))]
3341 "operands[3] = gen_reg_rtx (DImode);")
3344 [(set (match_operand:DI 0 "register_operand" "")
3345 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3346 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3347 (clobber (match_operand:DI 3 "register_operand" ""))]
3348 "operands[2] != const0_rtx"
3349 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3350 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3351 (match_dup 1) (match_dup 2)))]
3354 (define_expand "umindi3"
3356 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3357 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3358 (set (match_operand:DI 0 "register_operand" "")
3359 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3360 (match_dup 1) (match_dup 2)))]
3362 "operands[3] = gen_reg_rtx (DImode);")
3365 [(set (match_operand:DI 0 "register_operand" "")
3366 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3367 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3368 (clobber (match_operand:DI 3 "register_operand" ""))]
3369 "operands[2] != const0_rtx"
3370 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3371 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3372 (match_dup 1) (match_dup 2)))]
3375 (define_insn "*bcc_normal"
3378 (match_operator 1 "signed_comparison_operator"
3379 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3381 (label_ref (match_operand 0 "" ""))
3385 [(set_attr "type" "ibr")])
3387 (define_insn "*bcc_reverse"
3390 (match_operator 1 "signed_comparison_operator"
3391 [(match_operand:DI 2 "register_operand" "r")
3395 (label_ref (match_operand 0 "" ""))))]
3398 [(set_attr "type" "ibr")])
3400 (define_insn "*blbs_normal"
3403 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3407 (label_ref (match_operand 0 "" ""))
3411 [(set_attr "type" "ibr")])
3413 (define_insn "*blbc_normal"
3416 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3420 (label_ref (match_operand 0 "" ""))
3424 [(set_attr "type" "ibr")])
3430 (match_operator 1 "comparison_operator"
3431 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3433 (match_operand:DI 3 "const_int_operand" ""))
3435 (label_ref (match_operand 0 "" ""))
3437 (clobber (match_operand:DI 4 "register_operand" ""))])]
3438 "INTVAL (operands[3]) != 0"
3440 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3442 (if_then_else (match_op_dup 1
3443 [(zero_extract:DI (match_dup 4)
3447 (label_ref (match_dup 0))
3451 ;; The following are the corresponding floating-point insns. Recall
3452 ;; we need to have variants that expand the arguments from SFmode
3455 (define_insn "*cmpdf_ieee"
3456 [(set (match_operand:DF 0 "register_operand" "=&f")
3457 (match_operator:DF 1 "alpha_fp_comparison_operator"
3458 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3459 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3460 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3461 "cmp%-%C1%/ %R2,%R3,%0"
3462 [(set_attr "type" "fadd")
3463 (set_attr "trap" "yes")
3464 (set_attr "trap_suffix" "su")])
3466 (define_insn "*cmpdf_internal"
3467 [(set (match_operand:DF 0 "register_operand" "=f")
3468 (match_operator:DF 1 "alpha_fp_comparison_operator"
3469 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3470 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3471 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3472 "cmp%-%C1%/ %R2,%R3,%0"
3473 [(set_attr "type" "fadd")
3474 (set_attr "trap" "yes")
3475 (set_attr "trap_suffix" "su")])
3477 (define_insn "*cmpdf_ieee_ext1"
3478 [(set (match_operand:DF 0 "register_operand" "=&f")
3479 (match_operator:DF 1 "alpha_fp_comparison_operator"
3481 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3482 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3483 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3484 "cmp%-%C1%/ %R2,%R3,%0"
3485 [(set_attr "type" "fadd")
3486 (set_attr "trap" "yes")
3487 (set_attr "trap_suffix" "su")])
3489 (define_insn "*cmpdf_ext1"
3490 [(set (match_operand:DF 0 "register_operand" "=f")
3491 (match_operator:DF 1 "alpha_fp_comparison_operator"
3493 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3494 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3495 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3496 "cmp%-%C1%/ %R2,%R3,%0"
3497 [(set_attr "type" "fadd")
3498 (set_attr "trap" "yes")
3499 (set_attr "trap_suffix" "su")])
3501 (define_insn "*cmpdf_ieee_ext2"
3502 [(set (match_operand:DF 0 "register_operand" "=&f")
3503 (match_operator:DF 1 "alpha_fp_comparison_operator"
3504 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3506 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3507 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3508 "cmp%-%C1%/ %R2,%R3,%0"
3509 [(set_attr "type" "fadd")
3510 (set_attr "trap" "yes")
3511 (set_attr "trap_suffix" "su")])
3513 (define_insn "*cmpdf_ext2"
3514 [(set (match_operand:DF 0 "register_operand" "=f")
3515 (match_operator:DF 1 "alpha_fp_comparison_operator"
3516 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3518 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3519 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3520 "cmp%-%C1%/ %R2,%R3,%0"
3521 [(set_attr "type" "fadd")
3522 (set_attr "trap" "yes")
3523 (set_attr "trap_suffix" "su")])
3525 (define_insn "*cmpdf_ieee_ext3"
3526 [(set (match_operand:DF 0 "register_operand" "=&f")
3527 (match_operator:DF 1 "alpha_fp_comparison_operator"
3529 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3531 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3532 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3533 "cmp%-%C1%/ %R2,%R3,%0"
3534 [(set_attr "type" "fadd")
3535 (set_attr "trap" "yes")
3536 (set_attr "trap_suffix" "su")])
3538 (define_insn "*cmpdf_ext3"
3539 [(set (match_operand:DF 0 "register_operand" "=f")
3540 (match_operator:DF 1 "alpha_fp_comparison_operator"
3542 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3544 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3545 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3546 "cmp%-%C1%/ %R2,%R3,%0"
3547 [(set_attr "type" "fadd")
3548 (set_attr "trap" "yes")
3549 (set_attr "trap_suffix" "su")])
3551 (define_insn "*movdfcc_internal"
3552 [(set (match_operand:DF 0 "register_operand" "=f,f")
3554 (match_operator 3 "signed_comparison_operator"
3555 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3556 (match_operand:DF 2 "const0_operand" "G,G")])
3557 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3558 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3562 fcmov%D3 %R4,%R5,%0"
3563 [(set_attr "type" "fcmov")])
3565 (define_insn "*movsfcc_internal"
3566 [(set (match_operand:SF 0 "register_operand" "=f,f")
3568 (match_operator 3 "signed_comparison_operator"
3569 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3570 (match_operand:DF 2 "const0_operand" "G,G")])
3571 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3572 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3576 fcmov%D3 %R4,%R5,%0"
3577 [(set_attr "type" "fcmov")])
3579 (define_insn "*movdfcc_ext1"
3580 [(set (match_operand:DF 0 "register_operand" "=f,f")
3582 (match_operator 3 "signed_comparison_operator"
3583 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3584 (match_operand:DF 2 "const0_operand" "G,G")])
3585 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3586 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3590 fcmov%D3 %R4,%R5,%0"
3591 [(set_attr "type" "fcmov")])
3593 (define_insn "*movdfcc_ext2"
3594 [(set (match_operand:DF 0 "register_operand" "=f,f")
3596 (match_operator 3 "signed_comparison_operator"
3598 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3599 (match_operand:DF 2 "const0_operand" "G,G")])
3600 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3601 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3605 fcmov%D3 %R4,%R5,%0"
3606 [(set_attr "type" "fcmov")])
3608 (define_insn "*movdfcc_ext3"
3609 [(set (match_operand:SF 0 "register_operand" "=f,f")
3611 (match_operator 3 "signed_comparison_operator"
3613 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3614 (match_operand:DF 2 "const0_operand" "G,G")])
3615 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3616 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3620 fcmov%D3 %R4,%R5,%0"
3621 [(set_attr "type" "fcmov")])
3623 (define_insn "*movdfcc_ext4"
3624 [(set (match_operand:DF 0 "register_operand" "=f,f")
3626 (match_operator 3 "signed_comparison_operator"
3628 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3629 (match_operand:DF 2 "const0_operand" "G,G")])
3630 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3631 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3635 fcmov%D3 %R4,%R5,%0"
3636 [(set_attr "type" "fcmov")])
3638 (define_expand "maxdf3"
3640 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3641 (match_operand:DF 2 "reg_or_0_operand" "")))
3642 (set (match_operand:DF 0 "register_operand" "")
3643 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3644 (match_dup 1) (match_dup 2)))]
3647 operands[3] = gen_reg_rtx (DFmode);
3648 operands[4] = CONST0_RTX (DFmode);
3651 (define_expand "mindf3"
3653 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3654 (match_operand:DF 2 "reg_or_0_operand" "")))
3655 (set (match_operand:DF 0 "register_operand" "")
3656 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3657 (match_dup 1) (match_dup 2)))]
3660 operands[3] = gen_reg_rtx (DFmode);
3661 operands[4] = CONST0_RTX (DFmode);
3664 (define_expand "maxsf3"
3666 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3667 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3668 (set (match_operand:SF 0 "register_operand" "")
3669 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3670 (match_dup 1) (match_dup 2)))]
3673 operands[3] = gen_reg_rtx (DFmode);
3674 operands[4] = CONST0_RTX (DFmode);
3677 (define_expand "minsf3"
3679 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3680 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3681 (set (match_operand:SF 0 "register_operand" "")
3682 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3683 (match_dup 1) (match_dup 2)))]
3686 operands[3] = gen_reg_rtx (DFmode);
3687 operands[4] = CONST0_RTX (DFmode);
3690 (define_insn "*fbcc_normal"
3693 (match_operator 1 "signed_comparison_operator"
3694 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3695 (match_operand:DF 3 "const0_operand" "G")])
3696 (label_ref (match_operand 0 "" ""))
3700 [(set_attr "type" "fbr")])
3702 (define_insn "*fbcc_ext_normal"
3705 (match_operator 1 "signed_comparison_operator"
3707 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3708 (match_operand:DF 3 "const0_operand" "G")])
3709 (label_ref (match_operand 0 "" ""))
3713 [(set_attr "type" "fbr")])
3715 ;; These are the main define_expand's used to make conditional branches
3718 (define_expand "cmpdf"
3719 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3720 (match_operand:DF 1 "reg_or_0_operand" "")))]
3723 alpha_compare.op0 = operands[0];
3724 alpha_compare.op1 = operands[1];
3725 alpha_compare.fp_p = 1;
3729 (define_expand "cmptf"
3730 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3731 (match_operand:TF 1 "general_operand" "")))]
3732 "TARGET_HAS_XFLOATING_LIBS"
3734 alpha_compare.op0 = operands[0];
3735 alpha_compare.op1 = operands[1];
3736 alpha_compare.fp_p = 1;
3740 (define_expand "cmpdi"
3741 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3742 (match_operand:DI 1 "general_operand" "")))]
3745 alpha_compare.op0 = operands[0];
3746 alpha_compare.op1 = operands[1];
3747 alpha_compare.fp_p = 0;
3751 (define_expand "beq"
3753 (if_then_else (match_dup 1)
3754 (label_ref (match_operand 0 "" ""))
3757 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3759 (define_expand "bne"
3761 (if_then_else (match_dup 1)
3762 (label_ref (match_operand 0 "" ""))
3765 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3767 (define_expand "blt"
3769 (if_then_else (match_dup 1)
3770 (label_ref (match_operand 0 "" ""))
3773 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3775 (define_expand "ble"
3777 (if_then_else (match_dup 1)
3778 (label_ref (match_operand 0 "" ""))
3781 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3783 (define_expand "bgt"
3785 (if_then_else (match_dup 1)
3786 (label_ref (match_operand 0 "" ""))
3789 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3791 (define_expand "bge"
3793 (if_then_else (match_dup 1)
3794 (label_ref (match_operand 0 "" ""))
3797 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3799 (define_expand "bltu"
3801 (if_then_else (match_dup 1)
3802 (label_ref (match_operand 0 "" ""))
3805 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3807 (define_expand "bleu"
3809 (if_then_else (match_dup 1)
3810 (label_ref (match_operand 0 "" ""))
3813 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3815 (define_expand "bgtu"
3817 (if_then_else (match_dup 1)
3818 (label_ref (match_operand 0 "" ""))
3821 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3823 (define_expand "bgeu"
3825 (if_then_else (match_dup 1)
3826 (label_ref (match_operand 0 "" ""))
3829 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3831 (define_expand "bunordered"
3833 (if_then_else (match_dup 1)
3834 (label_ref (match_operand 0 "" ""))
3837 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3839 (define_expand "bordered"
3841 (if_then_else (match_dup 1)
3842 (label_ref (match_operand 0 "" ""))
3845 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3847 (define_expand "seq"
3848 [(set (match_operand:DI 0 "register_operand" "")
3851 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3853 (define_expand "sne"
3854 [(set (match_operand:DI 0 "register_operand" "")
3857 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3859 (define_expand "slt"
3860 [(set (match_operand:DI 0 "register_operand" "")
3863 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3865 (define_expand "sle"
3866 [(set (match_operand:DI 0 "register_operand" "")
3869 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3871 (define_expand "sgt"
3872 [(set (match_operand:DI 0 "register_operand" "")
3875 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3877 (define_expand "sge"
3878 [(set (match_operand:DI 0 "register_operand" "")
3881 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3883 (define_expand "sltu"
3884 [(set (match_operand:DI 0 "register_operand" "")
3887 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3889 (define_expand "sleu"
3890 [(set (match_operand:DI 0 "register_operand" "")
3893 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3895 (define_expand "sgtu"
3896 [(set (match_operand:DI 0 "register_operand" "")
3899 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3901 (define_expand "sgeu"
3902 [(set (match_operand:DI 0 "register_operand" "")
3905 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3907 (define_expand "sunordered"
3908 [(set (match_operand:DI 0 "register_operand" "")
3911 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3913 (define_expand "sordered"
3914 [(set (match_operand:DI 0 "register_operand" "")
3917 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3919 ;; These are the main define_expand's used to make conditional moves.
3921 (define_expand "movsicc"
3922 [(set (match_operand:SI 0 "register_operand" "")
3923 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3924 (match_operand:SI 2 "reg_or_8bit_operand" "")
3925 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3928 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3932 (define_expand "movdicc"
3933 [(set (match_operand:DI 0 "register_operand" "")
3934 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3935 (match_operand:DI 2 "reg_or_8bit_operand" "")
3936 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3939 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3943 (define_expand "movsfcc"
3944 [(set (match_operand:SF 0 "register_operand" "")
3945 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3946 (match_operand:SF 2 "reg_or_8bit_operand" "")
3947 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3950 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3954 (define_expand "movdfcc"
3955 [(set (match_operand:DF 0 "register_operand" "")
3956 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3957 (match_operand:DF 2 "reg_or_8bit_operand" "")
3958 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3961 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3965 ;; These define_split definitions are used in cases when comparisons have
3966 ;; not be stated in the correct way and we need to reverse the second
3967 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3968 ;; comparison that tests the result being reversed. We have one define_split
3969 ;; for each use of a comparison. They do not match valid insns and need
3970 ;; not generate valid insns.
3972 ;; We can also handle equality comparisons (and inequality comparisons in
3973 ;; cases where the resulting add cannot overflow) by doing an add followed by
3974 ;; a comparison with zero. This is faster since the addition takes one
3975 ;; less cycle than a compare when feeding into a conditional move.
3976 ;; For this case, we also have an SImode pattern since we can merge the add
3977 ;; and sign extend and the order doesn't matter.
3979 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3980 ;; operation could have been generated.
3983 [(set (match_operand:DI 0 "register_operand" "")
3985 (match_operator 1 "comparison_operator"
3986 [(match_operand:DI 2 "reg_or_0_operand" "")
3987 (match_operand:DI 3 "reg_or_cint_operand" "")])
3988 (match_operand:DI 4 "reg_or_cint_operand" "")
3989 (match_operand:DI 5 "reg_or_cint_operand" "")))
3990 (clobber (match_operand:DI 6 "register_operand" ""))]
3991 "operands[3] != const0_rtx"
3992 [(set (match_dup 6) (match_dup 7))
3994 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3996 enum rtx_code code = GET_CODE (operands[1]);
3997 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3999 /* If we are comparing for equality with a constant and that constant
4000 appears in the arm when the register equals the constant, use the
4001 register since that is more likely to match (and to produce better code
4004 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4005 && rtx_equal_p (operands[4], operands[3]))
4006 operands[4] = operands[2];
4008 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4009 && rtx_equal_p (operands[5], operands[3]))
4010 operands[5] = operands[2];
4012 if (code == NE || code == EQ
4013 || (extended_count (operands[2], DImode, unsignedp) >= 1
4014 && extended_count (operands[3], DImode, unsignedp) >= 1))
4016 if (GET_CODE (operands[3]) == CONST_INT)
4017 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4018 GEN_INT (- INTVAL (operands[3])));
4020 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4022 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4025 else if (code == EQ || code == LE || code == LT
4026 || code == LEU || code == LTU)
4028 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4029 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4033 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4034 operands[2], operands[3]);
4035 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4040 [(set (match_operand:DI 0 "register_operand" "")
4042 (match_operator 1 "comparison_operator"
4043 [(match_operand:SI 2 "reg_or_0_operand" "")
4044 (match_operand:SI 3 "reg_or_cint_operand" "")])
4045 (match_operand:DI 4 "reg_or_8bit_operand" "")
4046 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4047 (clobber (match_operand:DI 6 "register_operand" ""))]
4048 "operands[3] != const0_rtx
4049 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4050 [(set (match_dup 6) (match_dup 7))
4052 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4054 enum rtx_code code = GET_CODE (operands[1]);
4055 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4058 if ((code != NE && code != EQ
4059 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4060 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4063 if (GET_CODE (operands[3]) == CONST_INT)
4064 tem = gen_rtx_PLUS (SImode, operands[2],
4065 GEN_INT (- INTVAL (operands[3])));
4067 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4069 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4070 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4071 operands[6], const0_rtx);
4077 (match_operator 1 "comparison_operator"
4078 [(match_operand:DI 2 "reg_or_0_operand" "")
4079 (match_operand:DI 3 "reg_or_cint_operand" "")])
4080 (label_ref (match_operand 0 "" ""))
4082 (clobber (match_operand:DI 4 "register_operand" ""))]
4083 "operands[3] != const0_rtx"
4084 [(set (match_dup 4) (match_dup 5))
4085 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4087 enum rtx_code code = GET_CODE (operands[1]);
4088 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4090 if (code == NE || code == EQ
4091 || (extended_count (operands[2], DImode, unsignedp) >= 1
4092 && extended_count (operands[3], DImode, unsignedp) >= 1))
4094 if (GET_CODE (operands[3]) == CONST_INT)
4095 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4096 GEN_INT (- INTVAL (operands[3])));
4098 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4100 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4103 else if (code == EQ || code == LE || code == LT
4104 || code == LEU || code == LTU)
4106 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4107 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4111 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4112 operands[2], operands[3]);
4113 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4120 (match_operator 1 "comparison_operator"
4121 [(match_operand:SI 2 "reg_or_0_operand" "")
4122 (match_operand:SI 3 "const_int_operand" "")])
4123 (label_ref (match_operand 0 "" ""))
4125 (clobber (match_operand:DI 4 "register_operand" ""))]
4126 "operands[3] != const0_rtx
4127 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4128 [(set (match_dup 4) (match_dup 5))
4129 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4133 if (GET_CODE (operands[3]) == CONST_INT)
4134 tem = gen_rtx_PLUS (SImode, operands[2],
4135 GEN_INT (- INTVAL (operands[3])));
4137 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4139 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4140 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4141 operands[4], const0_rtx);
4144 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4145 ;; This eliminates one, and sometimes two, insns when the AND can be done
4148 [(set (match_operand:DI 0 "register_operand" "")
4149 (match_operator:DI 1 "comparison_operator"
4150 [(match_operand:DI 2 "register_operand" "")
4151 (match_operand:DI 3 "const_int_operand" "")]))
4152 (clobber (match_operand:DI 4 "register_operand" ""))]
4153 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4154 && (GET_CODE (operands[1]) == GTU
4155 || GET_CODE (operands[1]) == LEU
4156 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4157 && extended_count (operands[2], DImode, 1) > 0))"
4158 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4159 (set (match_dup 0) (match_dup 6))]
4161 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4162 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4163 || GET_CODE (operands[1]) == GT)
4165 DImode, operands[4], const0_rtx);
4168 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4171 [(set (match_operand 0 "register_operand" "")
4172 (if_then_else (match_operator 1 "signed_comparison_operator"
4173 [(match_operand:DI 2 "reg_or_0_operand" "")
4175 (match_operand 3 "const_int_operand" "")
4176 (match_operand 4 "const_int_operand" "")))]
4180 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4181 operands[2], operands[3], operands[4]))
4187 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4188 ;; Oh well, we match it in movcc, so it must be partially our fault.
4190 [(set (match_operand 0 "register_operand" "")
4191 (if_then_else (match_operator 1 "signed_comparison_operator"
4193 (match_operand:DI 2 "reg_or_0_operand" "")])
4194 (match_operand 3 "const_int_operand" "")
4195 (match_operand 4 "const_int_operand" "")))]
4199 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4200 operands[0], operands[2], operands[3],
4207 (define_insn_and_split "*cmp_sadd_di"
4208 [(set (match_operand:DI 0 "register_operand" "=r")
4209 (plus:DI (if_then_else:DI
4210 (match_operator 1 "alpha_zero_comparison_operator"
4211 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4213 (match_operand:DI 3 "const48_operand" "I")
4215 (match_operand:DI 4 "sext_add_operand" "rIO")))
4216 (clobber (match_scratch:DI 5 "=r"))]
4219 "! no_new_pseudos || reload_completed"
4221 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4223 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4226 if (! no_new_pseudos)
4227 operands[5] = gen_reg_rtx (DImode);
4228 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4229 operands[5] = operands[0];
4232 (define_insn_and_split "*cmp_sadd_si"
4233 [(set (match_operand:SI 0 "register_operand" "=r")
4234 (plus:SI (if_then_else:SI
4235 (match_operator 1 "alpha_zero_comparison_operator"
4236 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4238 (match_operand:SI 3 "const48_operand" "I")
4240 (match_operand:SI 4 "sext_add_operand" "rIO")))
4241 (clobber (match_scratch:SI 5 "=r"))]
4244 "! no_new_pseudos || reload_completed"
4246 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4248 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4251 if (! no_new_pseudos)
4252 operands[5] = gen_reg_rtx (DImode);
4253 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4254 operands[5] = operands[0];
4257 (define_insn_and_split "*cmp_sadd_sidi"
4258 [(set (match_operand:DI 0 "register_operand" "=r")
4260 (plus:SI (if_then_else:SI
4261 (match_operator 1 "alpha_zero_comparison_operator"
4262 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4264 (match_operand:SI 3 "const48_operand" "I")
4266 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4267 (clobber (match_scratch:SI 5 "=r"))]
4270 "! no_new_pseudos || reload_completed"
4272 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4274 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4277 if (! no_new_pseudos)
4278 operands[5] = gen_reg_rtx (DImode);
4279 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4280 operands[5] = operands[0];
4283 (define_insn_and_split "*cmp_ssub_di"
4284 [(set (match_operand:DI 0 "register_operand" "=r")
4285 (minus:DI (if_then_else:DI
4286 (match_operator 1 "alpha_zero_comparison_operator"
4287 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4289 (match_operand:DI 3 "const48_operand" "I")
4291 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4292 (clobber (match_scratch:DI 5 "=r"))]
4295 "! no_new_pseudos || reload_completed"
4297 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4299 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4302 if (! no_new_pseudos)
4303 operands[5] = gen_reg_rtx (DImode);
4304 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4305 operands[5] = operands[0];
4308 (define_insn_and_split "*cmp_ssub_si"
4309 [(set (match_operand:SI 0 "register_operand" "=r")
4310 (minus:SI (if_then_else:SI
4311 (match_operator 1 "alpha_zero_comparison_operator"
4312 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4314 (match_operand:SI 3 "const48_operand" "I")
4316 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4317 (clobber (match_scratch:SI 5 "=r"))]
4320 "! no_new_pseudos || reload_completed"
4322 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4324 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4327 if (! no_new_pseudos)
4328 operands[5] = gen_reg_rtx (DImode);
4329 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4330 operands[5] = operands[0];
4333 (define_insn_and_split "*cmp_ssub_sidi"
4334 [(set (match_operand:DI 0 "register_operand" "=r")
4336 (minus:SI (if_then_else:SI
4337 (match_operator 1 "alpha_zero_comparison_operator"
4338 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4340 (match_operand:SI 3 "const48_operand" "I")
4342 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4343 (clobber (match_scratch:SI 5 "=r"))]
4346 "! no_new_pseudos || reload_completed"
4348 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4350 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4353 if (! no_new_pseudos)
4354 operands[5] = gen_reg_rtx (DImode);
4355 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4356 operands[5] = operands[0];
4359 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4360 ;; work differently, so we have different patterns for each.
4362 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4363 ;; call. The CIW contains information about arguments passed in registers
4364 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4365 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4366 ;; in the presence of inlining since the CIWs for calls performed by the
4367 ;; inlined function must be stored in the SSIB of the function it is inlined
4368 ;; into as well. We encode the CIW in an unspec and append it to the list
4369 ;; of the CIWs for the current function only when the instruction for loading
4370 ;; $25 is generated.
4372 (define_expand "call"
4373 [(use (match_operand:DI 0 "" ""))
4374 (use (match_operand 1 "" ""))
4375 (use (match_operand 2 "" ""))
4376 (use (match_operand 3 "" ""))]
4379 if (TARGET_ABI_WINDOWS_NT)
4380 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4381 else if (TARGET_ABI_OPEN_VMS)
4382 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4383 else if (TARGET_ABI_UNICOSMK)
4384 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4386 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4390 (define_expand "sibcall"
4391 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4392 (match_operand 1 "" ""))
4393 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4396 if (GET_CODE (operands[0]) != MEM)
4398 operands[0] = XEXP (operands[0], 0);
4401 (define_expand "call_osf"
4402 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4403 (match_operand 1 "" ""))
4405 (clobber (reg:DI 26))])]
4408 if (GET_CODE (operands[0]) != MEM)
4411 operands[0] = XEXP (operands[0], 0);
4412 if (! call_operand (operands[0], Pmode))
4413 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4416 (define_expand "call_nt"
4417 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4418 (match_operand 1 "" ""))
4419 (clobber (reg:DI 26))])]
4422 if (GET_CODE (operands[0]) != MEM)
4425 operands[0] = XEXP (operands[0], 0);
4426 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4427 operands[0] = force_reg (DImode, operands[0]);
4430 ;; Calls on Unicos/Mk are always indirect.
4431 ;; op 0: symbol ref for called function
4432 ;; op 1: CIW for $25 represented by an unspec
4434 (define_expand "call_umk"
4435 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4436 (match_operand 1 "" ""))
4438 (clobber (reg:DI 26))])]
4441 if (GET_CODE (operands[0]) != MEM)
4444 /* Always load the address of the called function into a register;
4445 load the CIW in $25. */
4447 operands[0] = XEXP (operands[0], 0);
4448 if (GET_CODE (operands[0]) != REG)
4449 operands[0] = force_reg (DImode, operands[0]);
4451 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4455 ;; call openvms/alpha
4456 ;; op 0: symbol ref for called function
4457 ;; op 1: next_arg_reg (argument information value for R25)
4459 (define_expand "call_vms"
4460 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4461 (match_operand 1 "" ""))
4465 (clobber (reg:DI 27))])]
4468 if (GET_CODE (operands[0]) != MEM)
4471 operands[0] = XEXP (operands[0], 0);
4473 /* Always load AI with argument information, then handle symbolic and
4474 indirect call differently. Load RA and set operands[2] to PV in
4477 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4478 if (GET_CODE (operands[0]) == SYMBOL_REF)
4480 alpha_need_linkage (XSTR (operands[0], 0), 0);
4482 operands[2] = const0_rtx;
4486 emit_move_insn (gen_rtx_REG (Pmode, 26),
4487 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4488 operands[2] = operands[0];
4493 (define_expand "call_value"
4494 [(use (match_operand 0 "" ""))
4495 (use (match_operand:DI 1 "" ""))
4496 (use (match_operand 2 "" ""))
4497 (use (match_operand 3 "" ""))
4498 (use (match_operand 4 "" ""))]
4501 if (TARGET_ABI_WINDOWS_NT)
4502 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4503 else if (TARGET_ABI_OPEN_VMS)
4504 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4506 else if (TARGET_ABI_UNICOSMK)
4507 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4510 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4515 (define_expand "sibcall_value"
4516 [(parallel [(set (match_operand 0 "" "")
4517 (call (mem:DI (match_operand 1 "" ""))
4518 (match_operand 2 "" "")))
4519 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4522 if (GET_CODE (operands[1]) != MEM)
4524 operands[1] = XEXP (operands[1], 0);
4527 (define_expand "call_value_osf"
4528 [(parallel [(set (match_operand 0 "" "")
4529 (call (mem:DI (match_operand 1 "" ""))
4530 (match_operand 2 "" "")))
4532 (clobber (reg:DI 26))])]
4535 if (GET_CODE (operands[1]) != MEM)
4538 operands[1] = XEXP (operands[1], 0);
4539 if (! call_operand (operands[1], Pmode))
4540 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4543 (define_expand "call_value_nt"
4544 [(parallel [(set (match_operand 0 "" "")
4545 (call (mem:DI (match_operand 1 "" ""))
4546 (match_operand 2 "" "")))
4547 (clobber (reg:DI 26))])]
4550 if (GET_CODE (operands[1]) != MEM)
4553 operands[1] = XEXP (operands[1], 0);
4554 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4555 operands[1] = force_reg (DImode, operands[1]);
4558 (define_expand "call_value_vms"
4559 [(parallel [(set (match_operand 0 "" "")
4560 (call (mem:DI (match_operand:DI 1 "" ""))
4561 (match_operand 2 "" "")))
4565 (clobber (reg:DI 27))])]
4568 if (GET_CODE (operands[1]) != MEM)
4571 operands[1] = XEXP (operands[1], 0);
4573 /* Always load AI with argument information, then handle symbolic and
4574 indirect call differently. Load RA and set operands[3] to PV in
4577 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4578 if (GET_CODE (operands[1]) == SYMBOL_REF)
4580 alpha_need_linkage (XSTR (operands[1], 0), 0);
4582 operands[3] = const0_rtx;
4586 emit_move_insn (gen_rtx_REG (Pmode, 26),
4587 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4588 operands[3] = operands[1];
4592 (define_expand "call_value_umk"
4593 [(parallel [(set (match_operand 0 "" "")
4594 (call (mem:DI (match_operand 1 "" ""))
4595 (match_operand 2 "" "")))
4597 (clobber (reg:DI 26))])]
4600 if (GET_CODE (operands[1]) != MEM)
4603 operands[1] = XEXP (operands[1], 0);
4604 if (GET_CODE (operands[1]) != REG)
4605 operands[1] = force_reg (DImode, operands[1]);
4607 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4610 (define_insn "*call_osf_1_er"
4611 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4612 (match_operand 1 "" ""))
4614 (clobber (reg:DI 26))]
4615 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4617 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4618 bsr $26,%0\t\t!samegp
4619 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4620 [(set_attr "type" "jsr")
4621 (set_attr "length" "12,*,16")])
4623 ;; We must use peep2 instead of a split because we need accurate life
4624 ;; information for $gp. Consider the case of { bar(); while (1); }.
4626 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4627 (match_operand 1 "" ""))
4629 (clobber (reg:DI 26))])]
4630 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4631 && ! samegp_function_operand (operands[0], Pmode)
4632 && peep2_regno_dead_p (1, 29)"
4633 [(parallel [(call (mem:DI (match_dup 2))
4635 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4636 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4638 (use (match_dup 3))])]
4640 if (CONSTANT_P (operands[0]))
4642 operands[2] = gen_rtx_REG (Pmode, 27);
4643 operands[3] = GEN_INT (alpha_next_sequence_number++);
4644 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4645 operands[0], operands[3]));
4649 operands[2] = operands[0];
4650 operands[0] = const0_rtx;
4651 operands[3] = const0_rtx;
4656 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4657 (match_operand 1 "" ""))
4659 (clobber (reg:DI 26))])]
4660 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4661 && ! samegp_function_operand (operands[0], Pmode)
4662 && ! peep2_regno_dead_p (1, 29)"
4663 [(parallel [(call (mem:DI (match_dup 2))
4665 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4666 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4668 (use (match_dup 4))])
4670 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4672 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4674 if (CONSTANT_P (operands[0]))
4676 operands[2] = gen_rtx_REG (Pmode, 27);
4677 operands[4] = GEN_INT (alpha_next_sequence_number++);
4678 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4679 operands[0], operands[4]));
4683 operands[2] = operands[0];
4684 operands[0] = const0_rtx;
4685 operands[4] = const0_rtx;
4687 operands[3] = GEN_INT (alpha_next_sequence_number++);
4690 ;; We add a blockage unspec_volatile to prevent insns from moving down
4691 ;; from above the call to in between the call and the ldah gpdisp.
4693 (define_insn "*call_osf_2_er"
4694 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4695 (match_operand 1 "" ""))
4696 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4697 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4698 (use (match_operand 2 "" ""))
4699 (use (match_operand 3 "const_int_operand" ""))]
4700 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4701 "jsr $26,(%0),%2%J3"
4702 [(set_attr "type" "jsr")])
4704 ;; We output a nop after noreturn calls at the very end of the function to
4705 ;; ensure that the return address always remains in the caller's code range,
4706 ;; as not doing so might confuse unwinding engines.
4708 ;; The potential change in insn length is not reflected in the length
4709 ;; attributes at this stage. Since the extra space is only actually added at
4710 ;; the very end of the compilation process (via final/print_operand), it
4711 ;; really seems harmless and not worth the trouble of some extra computation
4712 ;; cost and complexity.
4714 (define_insn "*call_osf_1_noreturn"
4715 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4716 (match_operand 1 "" ""))
4718 (clobber (reg:DI 26))]
4719 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4720 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4725 [(set_attr "type" "jsr")
4726 (set_attr "length" "*,*,8")])
4728 (define_insn "*call_osf_1"
4729 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4730 (match_operand 1 "" ""))
4732 (clobber (reg:DI 26))]
4733 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4735 jsr $26,($27),0\;ldgp $29,0($26)
4737 jsr $26,%0\;ldgp $29,0($26)"
4738 [(set_attr "type" "jsr")
4739 (set_attr "length" "12,*,16")])
4741 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4742 ;; doesn't do what we want.
4743 (define_insn "*sibcall_osf_1_er"
4744 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4745 (match_operand 1 "" ""))
4746 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4747 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4749 br $31,%0\t\t!samegp
4750 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4751 [(set_attr "type" "jsr")
4752 (set_attr "length" "*,8")])
4754 (define_insn "*sibcall_osf_1"
4755 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4756 (match_operand 1 "" ""))
4757 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4758 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4761 lda $27,%0\;jmp $31,($27),%0"
4762 [(set_attr "type" "jsr")
4763 (set_attr "length" "*,8")])
4765 (define_insn "*call_nt_1"
4766 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4767 (match_operand 1 "" ""))
4768 (clobber (reg:DI 26))]
4769 "TARGET_ABI_WINDOWS_NT"
4774 [(set_attr "type" "jsr")
4775 (set_attr "length" "*,*,12")])
4777 ; GAS relies on the order and position of instructions output below in order
4778 ; to generate relocs for VMS link to potentially optimize the call.
4779 ; Please do not molest.
4780 (define_insn "*call_vms_1"
4781 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4782 (match_operand 1 "" ""))
4783 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4786 (clobber (reg:DI 27))]
4787 "TARGET_ABI_OPEN_VMS"
4789 switch (which_alternative)
4792 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4794 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4795 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4796 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4801 [(set_attr "type" "jsr")
4802 (set_attr "length" "12,16")])
4804 (define_insn "*call_umk_1"
4805 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4806 (match_operand 1 "" ""))
4808 (clobber (reg:DI 26))]
4809 "TARGET_ABI_UNICOSMK"
4811 [(set_attr "type" "jsr")])
4813 ;; Call subroutine returning any type.
4815 (define_expand "untyped_call"
4816 [(parallel [(call (match_operand 0 "" "")
4818 (match_operand 1 "" "")
4819 (match_operand 2 "" "")])]
4824 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4826 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4828 rtx set = XVECEXP (operands[2], 0, i);
4829 emit_move_insn (SET_DEST (set), SET_SRC (set));
4832 /* The optimizer does not know that the call sets the function value
4833 registers we stored in the result block. We avoid problems by
4834 claiming that all hard registers are used and clobbered at this
4836 emit_insn (gen_blockage ());
4841 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4842 ;; all of memory. This blocks insns from being moved across this point.
4844 (define_insn "blockage"
4845 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4848 [(set_attr "length" "0")
4849 (set_attr "type" "none")])
4853 (label_ref (match_operand 0 "" "")))]
4856 [(set_attr "type" "ibr")])
4858 (define_expand "return"
4863 (define_insn "*return_internal"
4867 [(set_attr "type" "ibr")])
4869 (define_insn "indirect_jump"
4870 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4873 [(set_attr "type" "ibr")])
4875 (define_expand "tablejump"
4876 [(parallel [(set (pc)
4877 (match_operand 0 "register_operand" ""))
4878 (use (label_ref:DI (match_operand 1 "" "")))])]
4881 if (TARGET_ABI_WINDOWS_NT)
4883 rtx dest = gen_reg_rtx (DImode);
4884 emit_insn (gen_extendsidi2 (dest, operands[0]));
4887 else if (TARGET_ABI_OSF)
4889 rtx dest = gen_reg_rtx (DImode);
4890 emit_insn (gen_extendsidi2 (dest, operands[0]));
4891 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4896 (define_insn "*tablejump_osf_nt_internal"
4898 (match_operand:DI 0 "register_operand" "r"))
4899 (use (label_ref:DI (match_operand 1 "" "")))]
4900 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4901 && alpha_tablejump_addr_vec (insn)"
4903 operands[2] = alpha_tablejump_best_label (insn);
4904 return "jmp $31,(%0),%2";
4906 [(set_attr "type" "ibr")])
4908 (define_insn "*tablejump_internal"
4910 (match_operand:DI 0 "register_operand" "r"))
4911 (use (label_ref (match_operand 1 "" "")))]
4914 [(set_attr "type" "ibr")])
4916 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4917 ;; want to have to include pal.h in our .s file.
4919 ;; Technically the type for call_pal is jsr, but we use that for determining
4920 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4923 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4926 [(set_attr "type" "callpal")])
4928 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4929 ;; NT does not document anything at 0x81 -- presumably it would generate
4930 ;; the equivalent of SIGILL, but this isn't that important.
4931 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4933 [(trap_if (const_int 1) (const_int 0))]
4934 "!TARGET_ABI_WINDOWS_NT"
4936 [(set_attr "type" "callpal")])
4938 ;; For userland, we load the thread pointer from the TCB.
4939 ;; For the kernel, we load the per-cpu private value.
4941 (define_insn "load_tp"
4942 [(set (match_operand:DI 0 "register_operand" "=v")
4943 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4946 if (TARGET_TLS_KERNEL)
4947 return "call_pal 0x32";
4949 return "call_pal 0x9e";
4951 [(set_attr "type" "callpal")])
4953 ;; For completeness, and possibly a __builtin function, here's how to
4954 ;; set the thread pointer. Since we don't describe enough of this
4955 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4956 ;; not much point in creating an R16_REG register class.
4958 (define_expand "set_tp"
4959 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4960 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4964 (define_insn "*set_tp"
4965 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4968 if (TARGET_TLS_KERNEL)
4969 return "call_pal 0x31";
4971 return "call_pal 0x9f";
4973 [(set_attr "type" "callpal")])
4975 ;; Finally, we have the basic data motion insns. The byte and word insns
4976 ;; are done via define_expand. Start with the floating-point insns, since
4977 ;; they are simpler.
4979 (define_insn "*movsf_nofix"
4980 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4981 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4982 "TARGET_FPREGS && ! TARGET_FIX
4983 && (register_operand (operands[0], SFmode)
4984 || reg_or_0_operand (operands[1], SFmode))"
4992 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4994 (define_insn "*movsf_fix"
4995 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4996 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4997 "TARGET_FPREGS && TARGET_FIX
4998 && (register_operand (operands[0], SFmode)
4999 || reg_or_0_operand (operands[1], SFmode))"
5009 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5011 (define_insn "*movsf_nofp"
5012 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5013 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5015 && (register_operand (operands[0], SFmode)
5016 || reg_or_0_operand (operands[1], SFmode))"
5021 [(set_attr "type" "ilog,ild,ist")])
5023 (define_insn "*movdf_nofix"
5024 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5025 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5026 "TARGET_FPREGS && ! TARGET_FIX
5027 && (register_operand (operands[0], DFmode)
5028 || reg_or_0_operand (operands[1], DFmode))"
5036 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5038 (define_insn "*movdf_fix"
5039 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5040 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5041 "TARGET_FPREGS && TARGET_FIX
5042 && (register_operand (operands[0], DFmode)
5043 || reg_or_0_operand (operands[1], DFmode))"
5053 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5055 (define_insn "*movdf_nofp"
5056 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5057 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5059 && (register_operand (operands[0], DFmode)
5060 || reg_or_0_operand (operands[1], DFmode))"
5065 [(set_attr "type" "ilog,ild,ist")])
5067 ;; Subregs suck for register allocation. Pretend we can move TFmode
5068 ;; data between general registers until after reload.
5070 (define_insn_and_split "*movtf_internal"
5071 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5072 (match_operand:TF 1 "input_operand" "roG,rG"))]
5073 "register_operand (operands[0], TFmode)
5074 || reg_or_0_operand (operands[1], TFmode)"
5077 [(set (match_dup 0) (match_dup 2))
5078 (set (match_dup 1) (match_dup 3))]
5080 alpha_split_tfmode_pair (operands);
5081 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5084 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5085 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5089 (define_expand "movsf"
5090 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5091 (match_operand:SF 1 "general_operand" ""))]
5094 if (GET_CODE (operands[0]) == MEM
5095 && ! reg_or_0_operand (operands[1], SFmode))
5096 operands[1] = force_reg (SFmode, operands[1]);
5099 (define_expand "movdf"
5100 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5101 (match_operand:DF 1 "general_operand" ""))]
5104 if (GET_CODE (operands[0]) == MEM
5105 && ! reg_or_0_operand (operands[1], DFmode))
5106 operands[1] = force_reg (DFmode, operands[1]);
5109 (define_expand "movtf"
5110 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5111 (match_operand:TF 1 "general_operand" ""))]
5114 if (GET_CODE (operands[0]) == MEM
5115 && ! reg_or_0_operand (operands[1], TFmode))
5116 operands[1] = force_reg (TFmode, operands[1]);
5119 (define_insn "*movsi_nofix"
5120 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5121 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5122 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5123 && (register_operand (operands[0], SImode)
5124 || reg_or_0_operand (operands[1], SImode))"
5134 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5136 (define_insn "*movsi_fix"
5137 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5138 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5139 "TARGET_ABI_OSF && TARGET_FIX
5140 && (register_operand (operands[0], SImode)
5141 || reg_or_0_operand (operands[1], SImode))"
5153 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5155 (define_insn "*movsi_nt_vms_nofix"
5156 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5157 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5158 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5160 && (register_operand (operands[0], SImode)
5161 || reg_or_0_operand (operands[1], SImode))"
5172 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5174 (define_insn "*movsi_nt_vms_fix"
5175 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5176 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5177 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5179 && (register_operand (operands[0], SImode)
5180 || reg_or_0_operand (operands[1], SImode))"
5193 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5195 (define_insn "*movhi_nobwx"
5196 [(set (match_operand:HI 0 "register_operand" "=r,r")
5197 (match_operand:HI 1 "input_operand" "rJ,n"))]
5199 && (register_operand (operands[0], HImode)
5200 || register_operand (operands[1], HImode))"
5204 [(set_attr "type" "ilog,iadd")])
5206 (define_insn "*movhi_bwx"
5207 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5208 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5210 && (register_operand (operands[0], HImode)
5211 || reg_or_0_operand (operands[1], HImode))"
5217 [(set_attr "type" "ilog,iadd,ild,ist")])
5219 (define_insn "*movqi_nobwx"
5220 [(set (match_operand:QI 0 "register_operand" "=r,r")
5221 (match_operand:QI 1 "input_operand" "rJ,n"))]
5223 && (register_operand (operands[0], QImode)
5224 || register_operand (operands[1], QImode))"
5228 [(set_attr "type" "ilog,iadd")])
5230 (define_insn "*movqi_bwx"
5231 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5232 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5234 && (register_operand (operands[0], QImode)
5235 || reg_or_0_operand (operands[1], QImode))"
5241 [(set_attr "type" "ilog,iadd,ild,ist")])
5243 ;; We do two major things here: handle mem->mem and construct long
5246 (define_expand "movsi"
5247 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5248 (match_operand:SI 1 "general_operand" ""))]
5251 if (alpha_expand_mov (SImode, operands))
5255 ;; Split a load of a large constant into the appropriate two-insn
5259 [(set (match_operand:SI 0 "register_operand" "")
5260 (match_operand:SI 1 "const_int_operand" ""))]
5261 "! add_operand (operands[1], SImode)"
5262 [(set (match_dup 0) (match_dup 2))
5263 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5266 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5268 if (tem == operands[0])
5274 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5275 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5276 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5277 ;; notes and update LABEL_NUSES because this is not done automatically.
5278 ;; Labels may be incorrectly deleted if we don't do this.
5280 ;; Describing what the individual instructions do correctly is too complicated
5281 ;; so use UNSPECs for each of the three parts of an address.
5284 [(set (match_operand:DI 0 "register_operand" "")
5285 (match_operand:DI 1 "symbolic_operand" ""))]
5286 "TARGET_ABI_UNICOSMK && reload_completed"
5289 rtx insn1, insn2, insn3;
5291 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5292 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5293 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5294 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5295 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5297 if (GET_CODE (operands[1]) == LABEL_REF)
5301 label = XEXP (operands[1], 0);
5302 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5304 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5306 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5308 LABEL_NUSES (label) += 3;
5313 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5315 (define_insn "umk_laum"
5316 [(set (match_operand:DI 0 "register_operand" "=r")
5317 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5319 "TARGET_ABI_UNICOSMK"
5321 [(set_attr "type" "iadd")])
5323 (define_insn "umk_lalm"
5324 [(set (match_operand:DI 0 "register_operand" "=r")
5325 (plus:DI (match_operand:DI 1 "register_operand" "r")
5326 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5328 "TARGET_ABI_UNICOSMK"
5330 [(set_attr "type" "iadd")])
5332 (define_insn "umk_lal"
5333 [(set (match_operand:DI 0 "register_operand" "=r")
5334 (plus:DI (match_operand:DI 1 "register_operand" "r")
5335 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5337 "TARGET_ABI_UNICOSMK"
5339 [(set_attr "type" "iadd")])
5341 ;; Add a new call information word to the current function's list of CIWs
5342 ;; and load its index into $25. Doing it here ensures that the CIW will be
5343 ;; associated with the correct function even in the presence of inlining.
5345 (define_insn "*umk_load_ciw"
5347 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5348 "TARGET_ABI_UNICOSMK"
5350 operands[0] = unicosmk_add_call_info_word (operands[0]);
5351 return "lda $25,%0";
5353 [(set_attr "type" "iadd")])
5355 (define_insn "*movdi_er_low_l"
5356 [(set (match_operand:DI 0 "register_operand" "=r")
5357 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5358 (match_operand:DI 2 "local_symbolic_operand" "")))]
5359 "TARGET_EXPLICIT_RELOCS"
5361 if (true_regnum (operands[1]) == 29)
5362 return "lda %0,%2(%1)\t\t!gprel";
5364 return "lda %0,%2(%1)\t\t!gprellow";
5366 [(set_attr "usegp" "yes")])
5369 [(set (match_operand:DI 0 "register_operand" "")
5370 (match_operand:DI 1 "small_symbolic_operand" ""))]
5371 "TARGET_EXPLICIT_RELOCS && reload_completed"
5373 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5374 "operands[2] = pic_offset_table_rtx;")
5377 [(set (match_operand:DI 0 "register_operand" "")
5378 (match_operand:DI 1 "local_symbolic_operand" ""))]
5379 "TARGET_EXPLICIT_RELOCS && reload_completed"
5381 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5383 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5384 "operands[2] = pic_offset_table_rtx;")
5387 [(match_operand 0 "some_small_symbolic_operand" "")]
5388 "TARGET_EXPLICIT_RELOCS && reload_completed"
5390 "operands[0] = split_small_symbolic_operand (operands[0]);")
5392 ;; Accepts any symbolic, not just global, since function calls that
5393 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5394 (define_insn "movdi_er_high_g"
5395 [(set (match_operand:DI 0 "register_operand" "=r")
5396 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5397 (match_operand:DI 2 "symbolic_operand" "")
5398 (match_operand 3 "const_int_operand" "")]
5400 "TARGET_EXPLICIT_RELOCS"
5402 if (INTVAL (operands[3]) == 0)
5403 return "ldq %0,%2(%1)\t\t!literal";
5405 return "ldq %0,%2(%1)\t\t!literal!%3";
5407 [(set_attr "type" "ldsym")])
5410 [(set (match_operand:DI 0 "register_operand" "")
5411 (match_operand:DI 1 "global_symbolic_operand" ""))]
5412 "TARGET_EXPLICIT_RELOCS && reload_completed"
5414 (unspec:DI [(match_dup 2)
5416 (const_int 0)] UNSPEC_LITERAL))]
5417 "operands[2] = pic_offset_table_rtx;")
5419 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5420 ;; compiled at the end of compilation. In the meantime, someone can
5421 ;; re-encode-section-info on some symbol changing it e.g. from global
5422 ;; to local-not-small. If this happens, we'd have emitted a plain
5423 ;; load rather than a high+losum load and not recognize the insn.
5425 ;; So if rtl inlining is in effect, we delay the global/not-global
5426 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5428 (define_insn_and_split "movdi_er_maybe_g"
5429 [(set (match_operand:DI 0 "register_operand" "=r")
5430 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5432 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5435 [(set (match_dup 0) (match_dup 1))]
5437 if (local_symbolic_operand (operands[1], Pmode)
5438 && !small_symbolic_operand (operands[1], Pmode))
5440 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5443 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5444 if (reload_completed)
5445 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5446 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5448 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5449 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5454 (define_insn "movdi_er_tlsgd"
5455 [(set (match_operand:DI 0 "register_operand" "=r")
5456 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5457 (match_operand:DI 2 "symbolic_operand" "")
5458 (match_operand 3 "const_int_operand" "")]
5462 if (INTVAL (operands[3]) == 0)
5463 return "lda %0,%2(%1)\t\t!tlsgd";
5465 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5468 (define_insn "movdi_er_tlsldm"
5469 [(set (match_operand:DI 0 "register_operand" "=r")
5470 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5471 (match_operand 2 "const_int_operand" "")]
5475 if (INTVAL (operands[2]) == 0)
5476 return "lda %0,%&(%1)\t\t!tlsldm";
5478 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5481 (define_insn "*movdi_er_gotdtp"
5482 [(set (match_operand:DI 0 "register_operand" "=r")
5483 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5484 (match_operand:DI 2 "symbolic_operand" "")]
5487 "ldq %0,%2(%1)\t\t!gotdtprel"
5488 [(set_attr "type" "ild")
5489 (set_attr "usegp" "yes")])
5492 [(set (match_operand:DI 0 "register_operand" "")
5493 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5494 "HAVE_AS_TLS && reload_completed"
5496 (unspec:DI [(match_dup 2)
5497 (match_dup 1)] UNSPEC_DTPREL))]
5499 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5500 operands[2] = pic_offset_table_rtx;
5503 (define_insn "*movdi_er_gottp"
5504 [(set (match_operand:DI 0 "register_operand" "=r")
5505 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5506 (match_operand:DI 2 "symbolic_operand" "")]
5509 "ldq %0,%2(%1)\t\t!gottprel"
5510 [(set_attr "type" "ild")
5511 (set_attr "usegp" "yes")])
5514 [(set (match_operand:DI 0 "register_operand" "")
5515 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5516 "HAVE_AS_TLS && reload_completed"
5518 (unspec:DI [(match_dup 2)
5519 (match_dup 1)] UNSPEC_TPREL))]
5521 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5522 operands[2] = pic_offset_table_rtx;
5525 (define_insn "*movdi_er_nofix"
5526 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5527 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5528 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5529 && (register_operand (operands[0], DImode)
5530 || reg_or_0_operand (operands[1], DImode))"
5542 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")
5543 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")])
5545 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5546 ;; have been split up by the rules above but we shouldn't reject the
5547 ;; possibility of them getting through.
5549 (define_insn "*movdi_nofix"
5550 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5551 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5553 && (register_operand (operands[0], DImode)
5554 || reg_or_0_operand (operands[1], DImode))"
5559 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5566 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5567 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5569 (define_insn "*movdi_er_fix"
5570 [(set (match_operand:DI 0 "nonimmediate_operand"
5571 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5572 (match_operand:DI 1 "input_operand"
5573 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5574 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5575 && (register_operand (operands[0], DImode)
5576 || reg_or_0_operand (operands[1], DImode))"
5590 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
5591 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")])
5593 (define_insn "*movdi_fix"
5594 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5595 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5596 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5597 && (register_operand (operands[0], DImode)
5598 || reg_or_0_operand (operands[1], DImode))"
5611 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5613 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5614 ;; often appears dead to the life analysis code, at which point we
5615 ;; abort for emitting dead prologue instructions. Force this live.
5617 (define_insn "force_movdi"
5618 [(set (match_operand:DI 0 "register_operand" "=r")
5619 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5620 UNSPECV_FORCE_MOV))]
5623 [(set_attr "type" "ilog")])
5625 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5626 ;; memory, and construct long 32-bit constants.
5628 (define_expand "movdi"
5629 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5630 (match_operand:DI 1 "general_operand" ""))]
5633 if (alpha_expand_mov (DImode, operands))
5637 ;; Split a load of a large constant into the appropriate two-insn
5641 [(set (match_operand:DI 0 "register_operand" "")
5642 (match_operand:DI 1 "const_int_operand" ""))]
5643 "! add_operand (operands[1], DImode)"
5644 [(set (match_dup 0) (match_dup 2))
5645 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5648 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5650 if (tem == operands[0])
5656 ;; These are the partial-word cases.
5658 ;; First we have the code to load an aligned word. Operand 0 is the register
5659 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5660 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5661 ;; number of bits within the word that the value is. Operand 3 is an SImode
5662 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5663 ;; same register. It is allowed to conflict with operand 1 as well.
5665 (define_expand "aligned_loadqi"
5666 [(set (match_operand:SI 3 "register_operand" "")
5667 (match_operand:SI 1 "memory_operand" ""))
5668 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5669 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5671 (match_operand:DI 2 "const_int_operand" "")))]
5676 (define_expand "aligned_loadhi"
5677 [(set (match_operand:SI 3 "register_operand" "")
5678 (match_operand:SI 1 "memory_operand" ""))
5679 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5680 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5682 (match_operand:DI 2 "const_int_operand" "")))]
5687 ;; Similar for unaligned loads, where we use the sequence from the
5688 ;; Alpha Architecture manual. We have to distinguish between little-endian
5689 ;; and big-endian systems as the sequences are different.
5691 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5692 ;; operand 3 can overlap the input and output registers.
5694 (define_expand "unaligned_loadqi"
5695 [(use (match_operand:QI 0 "register_operand" ""))
5696 (use (match_operand:DI 1 "address_operand" ""))
5697 (use (match_operand:DI 2 "register_operand" ""))
5698 (use (match_operand:DI 3 "register_operand" ""))]
5701 if (WORDS_BIG_ENDIAN)
5702 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5703 operands[2], operands[3]));
5705 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5706 operands[2], operands[3]));
5710 (define_expand "unaligned_loadqi_le"
5711 [(set (match_operand:DI 2 "register_operand" "")
5712 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5714 (set (match_operand:DI 3 "register_operand" "")
5716 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5717 (zero_extract:DI (match_dup 2)
5719 (ashift:DI (match_dup 3) (const_int 3))))]
5720 "! WORDS_BIG_ENDIAN"
5723 (define_expand "unaligned_loadqi_be"
5724 [(set (match_operand:DI 2 "register_operand" "")
5725 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5727 (set (match_operand:DI 3 "register_operand" "")
5729 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5730 (zero_extract:DI (match_dup 2)
5734 (ashift:DI (match_dup 3) (const_int 3)))))]
5738 (define_expand "unaligned_loadhi"
5739 [(use (match_operand:QI 0 "register_operand" ""))
5740 (use (match_operand:DI 1 "address_operand" ""))
5741 (use (match_operand:DI 2 "register_operand" ""))
5742 (use (match_operand:DI 3 "register_operand" ""))]
5745 if (WORDS_BIG_ENDIAN)
5746 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5747 operands[2], operands[3]));
5749 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5750 operands[2], operands[3]));
5754 (define_expand "unaligned_loadhi_le"
5755 [(set (match_operand:DI 2 "register_operand" "")
5756 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5758 (set (match_operand:DI 3 "register_operand" "")
5760 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5761 (zero_extract:DI (match_dup 2)
5763 (ashift:DI (match_dup 3) (const_int 3))))]
5764 "! WORDS_BIG_ENDIAN"
5767 (define_expand "unaligned_loadhi_be"
5768 [(set (match_operand:DI 2 "register_operand" "")
5769 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5771 (set (match_operand:DI 3 "register_operand" "")
5772 (plus:DI (match_dup 1) (const_int 1)))
5773 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5774 (zero_extract:DI (match_dup 2)
5778 (ashift:DI (match_dup 3) (const_int 3)))))]
5782 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5783 ;; aligned SImode MEM. Operand 1 is the register containing the
5784 ;; byte or word to store. Operand 2 is the number of bits within the word that
5785 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5787 (define_expand "aligned_store"
5788 [(set (match_operand:SI 3 "register_operand" "")
5789 (match_operand:SI 0 "memory_operand" ""))
5790 (set (subreg:DI (match_dup 3) 0)
5791 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5792 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5793 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5794 (match_operand:DI 2 "const_int_operand" "")))
5795 (set (subreg:DI (match_dup 4) 0)
5796 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5797 (set (match_dup 0) (match_dup 4))]
5800 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5801 << INTVAL (operands[2])));
5804 ;; For the unaligned byte and halfword cases, we use code similar to that
5805 ;; in the ;; Architecture book, but reordered to lower the number of registers
5806 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5807 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5808 ;; be the same temporary, if desired. If the address is in a register,
5809 ;; operand 2 can be that register.
5811 (define_expand "unaligned_storeqi"
5812 [(use (match_operand:DI 0 "address_operand" ""))
5813 (use (match_operand:QI 1 "register_operand" ""))
5814 (use (match_operand:DI 2 "register_operand" ""))
5815 (use (match_operand:DI 3 "register_operand" ""))
5816 (use (match_operand:DI 4 "register_operand" ""))]
5819 if (WORDS_BIG_ENDIAN)
5820 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5821 operands[2], operands[3],
5824 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5825 operands[2], operands[3],
5830 (define_expand "unaligned_storeqi_le"
5831 [(set (match_operand:DI 3 "register_operand" "")
5832 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5834 (set (match_operand:DI 2 "register_operand" "")
5837 (and:DI (not:DI (ashift:DI (const_int 255)
5838 (ashift:DI (match_dup 2) (const_int 3))))
5840 (set (match_operand:DI 4 "register_operand" "")
5841 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5842 (ashift:DI (match_dup 2) (const_int 3))))
5843 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5844 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5846 "! WORDS_BIG_ENDIAN"
5849 (define_expand "unaligned_storeqi_be"
5850 [(set (match_operand:DI 3 "register_operand" "")
5851 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5853 (set (match_operand:DI 2 "register_operand" "")
5856 (and:DI (not:DI (ashift:DI (const_int 255)
5857 (minus:DI (const_int 56)
5858 (ashift:DI (match_dup 2) (const_int 3)))))
5860 (set (match_operand:DI 4 "register_operand" "")
5861 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5862 (minus:DI (const_int 56)
5863 (ashift:DI (match_dup 2) (const_int 3)))))
5864 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5865 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5870 (define_expand "unaligned_storehi"
5871 [(use (match_operand:DI 0 "address_operand" ""))
5872 (use (match_operand:HI 1 "register_operand" ""))
5873 (use (match_operand:DI 2 "register_operand" ""))
5874 (use (match_operand:DI 3 "register_operand" ""))
5875 (use (match_operand:DI 4 "register_operand" ""))]
5878 if (WORDS_BIG_ENDIAN)
5879 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5880 operands[2], operands[3],
5883 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5884 operands[2], operands[3],
5889 (define_expand "unaligned_storehi_le"
5890 [(set (match_operand:DI 3 "register_operand" "")
5891 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5893 (set (match_operand:DI 2 "register_operand" "")
5896 (and:DI (not:DI (ashift:DI (const_int 65535)
5897 (ashift:DI (match_dup 2) (const_int 3))))
5899 (set (match_operand:DI 4 "register_operand" "")
5900 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5901 (ashift:DI (match_dup 2) (const_int 3))))
5902 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5903 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5905 "! WORDS_BIG_ENDIAN"
5908 (define_expand "unaligned_storehi_be"
5909 [(set (match_operand:DI 3 "register_operand" "")
5910 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5912 (set (match_operand:DI 2 "register_operand" "")
5913 (plus:DI (match_dup 0) (const_int 1)))
5915 (and:DI (not:DI (ashift:DI
5917 (minus:DI (const_int 56)
5918 (ashift:DI (match_dup 2) (const_int 3)))))
5920 (set (match_operand:DI 4 "register_operand" "")
5921 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5922 (minus:DI (const_int 56)
5923 (ashift:DI (match_dup 2) (const_int 3)))))
5924 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5925 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5930 ;; Here are the define_expand's for QI and HI moves that use the above
5931 ;; patterns. We have the normal sets, plus the ones that need scratch
5932 ;; registers for reload.
5934 (define_expand "movqi"
5935 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5936 (match_operand:QI 1 "general_operand" ""))]
5940 ? alpha_expand_mov (QImode, operands)
5941 : alpha_expand_mov_nobwx (QImode, operands))
5945 (define_expand "movhi"
5946 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5947 (match_operand:HI 1 "general_operand" ""))]
5951 ? alpha_expand_mov (HImode, operands)
5952 : alpha_expand_mov_nobwx (HImode, operands))
5956 ;; Here are the versions for reload. Note that in the unaligned cases
5957 ;; we know that the operand must not be a pseudo-register because stack
5958 ;; slots are always aligned references.
5960 (define_expand "reload_inqi"
5961 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5962 (match_operand:QI 1 "any_memory_operand" "m")
5963 (match_operand:TI 2 "register_operand" "=&r")])]
5968 if (GET_CODE (operands[1]) != MEM)
5971 if (aligned_memory_operand (operands[1], QImode))
5973 seq = gen_reload_inqi_help (operands[0], operands[1],
5974 gen_rtx_REG (SImode, REGNO (operands[2])));
5980 /* It is possible that one of the registers we got for operands[2]
5981 might coincide with that of operands[0] (which is why we made
5982 it TImode). Pick the other one to use as our scratch. */
5983 if (REGNO (operands[0]) == REGNO (operands[2]))
5984 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5986 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5988 addr = get_unaligned_address (operands[1], 0);
5989 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5990 gen_rtx_REG (DImode, REGNO (operands[0])));
5991 alpha_set_memflags (seq, operands[1]);
5997 (define_expand "reload_inhi"
5998 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5999 (match_operand:HI 1 "any_memory_operand" "m")
6000 (match_operand:TI 2 "register_operand" "=&r")])]
6005 if (GET_CODE (operands[1]) != MEM)
6008 if (aligned_memory_operand (operands[1], HImode))
6010 seq = gen_reload_inhi_help (operands[0], operands[1],
6011 gen_rtx_REG (SImode, REGNO (operands[2])));
6017 /* It is possible that one of the registers we got for operands[2]
6018 might coincide with that of operands[0] (which is why we made
6019 it TImode). Pick the other one to use as our scratch. */
6020 if (REGNO (operands[0]) == REGNO (operands[2]))
6021 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6023 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6025 addr = get_unaligned_address (operands[1], 0);
6026 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
6027 gen_rtx_REG (DImode, REGNO (operands[0])));
6028 alpha_set_memflags (seq, operands[1]);
6034 (define_expand "reload_outqi"
6035 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6036 (match_operand:QI 1 "register_operand" "r")
6037 (match_operand:TI 2 "register_operand" "=&r")])]
6040 if (GET_CODE (operands[0]) != MEM)
6043 if (aligned_memory_operand (operands[0], QImode))
6045 emit_insn (gen_reload_outqi_help
6046 (operands[0], operands[1],
6047 gen_rtx_REG (SImode, REGNO (operands[2])),
6048 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6052 rtx addr = get_unaligned_address (operands[0], 0);
6053 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6054 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6055 rtx scratch3 = scratch1;
6058 if (GET_CODE (addr) == REG)
6061 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6062 scratch2, scratch3);
6063 alpha_set_memflags (seq, operands[0]);
6069 (define_expand "reload_outhi"
6070 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6071 (match_operand:HI 1 "register_operand" "r")
6072 (match_operand:TI 2 "register_operand" "=&r")])]
6075 if (GET_CODE (operands[0]) != MEM)
6078 if (aligned_memory_operand (operands[0], HImode))
6080 emit_insn (gen_reload_outhi_help
6081 (operands[0], operands[1],
6082 gen_rtx_REG (SImode, REGNO (operands[2])),
6083 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6087 rtx addr = get_unaligned_address (operands[0], 0);
6088 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6089 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6090 rtx scratch3 = scratch1;
6093 if (GET_CODE (addr) == REG)
6096 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6097 scratch2, scratch3);
6098 alpha_set_memflags (seq, operands[0]);
6104 ;; Helpers for the above. The way reload is structured, we can't
6105 ;; always get a proper address for a stack slot during reload_foo
6106 ;; expansion, so we must delay our address manipulations until after.
6108 (define_insn "reload_inqi_help"
6109 [(set (match_operand:QI 0 "register_operand" "=r")
6110 (match_operand:QI 1 "memory_operand" "m"))
6111 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6112 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6115 (define_insn "reload_inhi_help"
6116 [(set (match_operand:HI 0 "register_operand" "=r")
6117 (match_operand:HI 1 "memory_operand" "m"))
6118 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6119 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6122 (define_insn "reload_outqi_help"
6123 [(set (match_operand:QI 0 "memory_operand" "=m")
6124 (match_operand:QI 1 "register_operand" "r"))
6125 (clobber (match_operand:SI 2 "register_operand" "=r"))
6126 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6127 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6130 (define_insn "reload_outhi_help"
6131 [(set (match_operand:HI 0 "memory_operand" "=m")
6132 (match_operand:HI 1 "register_operand" "r"))
6133 (clobber (match_operand:SI 2 "register_operand" "=r"))
6134 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6135 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6139 [(set (match_operand:QI 0 "register_operand" "")
6140 (match_operand:QI 1 "memory_operand" ""))
6141 (clobber (match_operand:SI 2 "register_operand" ""))]
6142 "! TARGET_BWX && reload_completed"
6145 rtx aligned_mem, bitnum;
6146 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6148 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6154 [(set (match_operand:HI 0 "register_operand" "")
6155 (match_operand:HI 1 "memory_operand" ""))
6156 (clobber (match_operand:SI 2 "register_operand" ""))]
6157 "! TARGET_BWX && reload_completed"
6160 rtx aligned_mem, bitnum;
6161 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6163 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6169 [(set (match_operand:QI 0 "memory_operand" "")
6170 (match_operand:QI 1 "register_operand" ""))
6171 (clobber (match_operand:SI 2 "register_operand" ""))
6172 (clobber (match_operand:SI 3 "register_operand" ""))]
6173 "! TARGET_BWX && reload_completed"
6176 rtx aligned_mem, bitnum;
6177 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6178 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6179 operands[2], operands[3]));
6184 [(set (match_operand:HI 0 "memory_operand" "")
6185 (match_operand:HI 1 "register_operand" ""))
6186 (clobber (match_operand:SI 2 "register_operand" ""))
6187 (clobber (match_operand:SI 3 "register_operand" ""))]
6188 "! TARGET_BWX && reload_completed"
6191 rtx aligned_mem, bitnum;
6192 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6193 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6194 operands[2], operands[3]));
6198 ;; Vector operations
6200 (define_expand "movv8qi"
6201 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
6202 (match_operand:V8QI 1 "general_operand" ""))]
6205 if (alpha_expand_mov (V8QImode, operands))
6209 (define_insn "*movv8qi_fix"
6210 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6211 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6213 && (register_operand (operands[0], V8QImode)
6214 || reg_or_0_operand (operands[1], V8QImode))"
6224 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6226 (define_insn "*movv8qi_nofix"
6227 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6228 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6230 && (register_operand (operands[0], V8QImode)
6231 || reg_or_0_operand (operands[1], V8QImode))"
6239 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6241 (define_expand "movv4hi"
6242 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
6243 (match_operand:V4HI 1 "general_operand" ""))]
6246 if (alpha_expand_mov (V4HImode, operands))
6250 (define_insn "*movv4hi_fix"
6251 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6252 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6254 && (register_operand (operands[0], V4HImode)
6255 || reg_or_0_operand (operands[1], V4HImode))"
6265 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6267 (define_insn "*movv4hi_nofix"
6268 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6269 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6271 && (register_operand (operands[0], V4HImode)
6272 || reg_or_0_operand (operands[1], V4HImode))"
6280 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6282 (define_expand "movv2si"
6283 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
6284 (match_operand:V2SI 1 "general_operand" ""))]
6287 if (alpha_expand_mov (V2SImode, operands))
6291 (define_insn "*movv2si_fix"
6292 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6293 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6295 && (register_operand (operands[0], V2SImode)
6296 || reg_or_0_operand (operands[1], V2SImode))"
6306 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6308 (define_insn "*movv2si_nofix"
6309 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6310 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6312 && (register_operand (operands[0], V2SImode)
6313 || reg_or_0_operand (operands[1], V2SImode))"
6321 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6323 (define_insn "uminv8qi3"
6324 [(set (match_operand:V8QI 0 "register_operand" "=r")
6325 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6326 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6329 [(set_attr "type" "mvi")])
6331 (define_insn "sminv8qi3"
6332 [(set (match_operand:V8QI 0 "register_operand" "=r")
6333 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6334 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6337 [(set_attr "type" "mvi")])
6339 (define_insn "uminv4hi3"
6340 [(set (match_operand:V4HI 0 "register_operand" "=r")
6341 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6342 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6345 [(set_attr "type" "mvi")])
6347 (define_insn "sminv4hi3"
6348 [(set (match_operand:V4HI 0 "register_operand" "=r")
6349 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6350 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6353 [(set_attr "type" "mvi")])
6355 (define_insn "umaxv8qi3"
6356 [(set (match_operand:V8QI 0 "register_operand" "=r")
6357 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6358 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6361 [(set_attr "type" "mvi")])
6363 (define_insn "smaxv8qi3"
6364 [(set (match_operand:V8QI 0 "register_operand" "=r")
6365 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6366 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6369 [(set_attr "type" "mvi")])
6371 (define_insn "umaxv4hi3"
6372 [(set (match_operand:V4HI 0 "register_operand" "=r")
6373 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6374 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6377 [(set_attr "type" "mvi")])
6379 (define_insn "smaxv4hi3"
6380 [(set (match_operand:V4HI 0 "register_operand" "=r")
6381 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6382 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6385 [(set_attr "type" "mvi")])
6387 ;; Bit field extract patterns which use ext[wlq][lh]
6389 (define_expand "extv"
6390 [(set (match_operand:DI 0 "register_operand" "")
6391 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6392 (match_operand:DI 2 "immediate_operand" "")
6393 (match_operand:DI 3 "immediate_operand" "")))]
6398 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6399 if (INTVAL (operands[3]) % 8 != 0
6400 || (INTVAL (operands[2]) != 16
6401 && INTVAL (operands[2]) != 32
6402 && INTVAL (operands[2]) != 64))
6405 /* From mips.md: extract_bit_field doesn't verify that our source
6406 matches the predicate, so we force it to be a MEM here. */
6407 if (GET_CODE (operands[1]) != MEM)
6410 /* The bit number is relative to the mode of operand 1 which is
6411 usually QImode (this might actually be a bug in expmed.c). Note
6412 that the bit number is negative in big-endian mode in this case.
6413 We have to convert that to the offset. */
6414 if (WORDS_BIG_ENDIAN)
6415 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6416 - INTVAL (operands[2]) - INTVAL (operands[3]);
6418 ofs = INTVAL (operands[3]);
6422 alpha_expand_unaligned_load (operands[0], operands[1],
6423 INTVAL (operands[2]) / 8,
6428 (define_expand "extzv"
6429 [(set (match_operand:DI 0 "register_operand" "")
6430 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6431 (match_operand:DI 2 "immediate_operand" "")
6432 (match_operand:DI 3 "immediate_operand" "")))]
6435 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6436 if (INTVAL (operands[3]) % 8 != 0
6437 || (INTVAL (operands[2]) != 8
6438 && INTVAL (operands[2]) != 16
6439 && INTVAL (operands[2]) != 32
6440 && INTVAL (operands[2]) != 64))
6443 if (GET_CODE (operands[1]) == MEM)
6447 /* Fail 8 bit fields, falling back on a simple byte load. */
6448 if (INTVAL (operands[2]) == 8)
6451 /* The bit number is relative to the mode of operand 1 which is
6452 usually QImode (this might actually be a bug in expmed.c). Note
6453 that the bit number is negative in big-endian mode in this case.
6454 We have to convert that to the offset. */
6455 if (WORDS_BIG_ENDIAN)
6456 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6457 - INTVAL (operands[2]) - INTVAL (operands[3]);
6459 ofs = INTVAL (operands[3]);
6463 alpha_expand_unaligned_load (operands[0], operands[1],
6464 INTVAL (operands[2]) / 8,
6470 (define_expand "insv"
6471 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6472 (match_operand:DI 1 "immediate_operand" "")
6473 (match_operand:DI 2 "immediate_operand" ""))
6474 (match_operand:DI 3 "register_operand" ""))]
6479 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6480 if (INTVAL (operands[2]) % 8 != 0
6481 || (INTVAL (operands[1]) != 16
6482 && INTVAL (operands[1]) != 32
6483 && INTVAL (operands[1]) != 64))
6486 /* From mips.md: store_bit_field doesn't verify that our source
6487 matches the predicate, so we force it to be a MEM here. */
6488 if (GET_CODE (operands[0]) != MEM)
6491 /* The bit number is relative to the mode of operand 1 which is
6492 usually QImode (this might actually be a bug in expmed.c). Note
6493 that the bit number is negative in big-endian mode in this case.
6494 We have to convert that to the offset. */
6495 if (WORDS_BIG_ENDIAN)
6496 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6497 - INTVAL (operands[1]) - INTVAL (operands[2]);
6499 ofs = INTVAL (operands[2]);
6503 alpha_expand_unaligned_store (operands[0], operands[3],
6504 INTVAL (operands[1]) / 8, ofs);
6508 ;; Block move/clear, see alpha.c for more details.
6509 ;; Argument 0 is the destination
6510 ;; Argument 1 is the source
6511 ;; Argument 2 is the length
6512 ;; Argument 3 is the alignment
6514 (define_expand "movstrqi"
6515 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6516 (match_operand:BLK 1 "memory_operand" ""))
6517 (use (match_operand:DI 2 "immediate_operand" ""))
6518 (use (match_operand:DI 3 "immediate_operand" ""))])]
6521 if (alpha_expand_block_move (operands))
6527 (define_expand "movstrdi"
6528 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6529 (match_operand:BLK 1 "memory_operand" ""))
6530 (use (match_operand:DI 2 "immediate_operand" ""))
6531 (use (match_operand:DI 3 "immediate_operand" ""))
6533 (clobber (reg:DI 25))
6534 (clobber (reg:DI 16))
6535 (clobber (reg:DI 17))
6536 (clobber (reg:DI 18))
6537 (clobber (reg:DI 19))
6538 (clobber (reg:DI 20))
6539 (clobber (reg:DI 26))
6540 (clobber (reg:DI 27))])]
6541 "TARGET_ABI_OPEN_VMS"
6543 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6544 alpha_need_linkage (XSTR (operands[4], 0), 0);
6547 (define_insn "*movstrdi_1"
6548 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6549 (match_operand:BLK 1 "memory_operand" "m,m"))
6550 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6551 (use (match_operand:DI 3 "immediate_operand" ""))
6552 (use (match_operand:DI 4 "call_operand" "i,i"))
6553 (clobber (reg:DI 25))
6554 (clobber (reg:DI 16))
6555 (clobber (reg:DI 17))
6556 (clobber (reg:DI 18))
6557 (clobber (reg:DI 19))
6558 (clobber (reg:DI 20))
6559 (clobber (reg:DI 26))
6560 (clobber (reg:DI 27))]
6561 "TARGET_ABI_OPEN_VMS"
6563 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6564 switch (which_alternative)
6567 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6569 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6574 [(set_attr "type" "multi")
6575 (set_attr "length" "28")])
6577 (define_expand "clrstrqi"
6578 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6580 (use (match_operand:DI 1 "immediate_operand" ""))
6581 (use (match_operand:DI 2 "immediate_operand" ""))])]
6584 if (alpha_expand_block_clear (operands))
6590 (define_expand "clrstrdi"
6591 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6593 (use (match_operand:DI 1 "immediate_operand" ""))
6594 (use (match_operand:DI 2 "immediate_operand" ""))
6596 (clobber (reg:DI 25))
6597 (clobber (reg:DI 16))
6598 (clobber (reg:DI 17))
6599 (clobber (reg:DI 26))
6600 (clobber (reg:DI 27))])]
6601 "TARGET_ABI_OPEN_VMS"
6603 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6604 alpha_need_linkage (XSTR (operands[3], 0), 0);
6607 (define_insn "*clrstrdi_1"
6608 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6610 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6611 (use (match_operand:DI 2 "immediate_operand" ""))
6612 (use (match_operand:DI 3 "call_operand" "i,i"))
6613 (clobber (reg:DI 25))
6614 (clobber (reg:DI 16))
6615 (clobber (reg:DI 17))
6616 (clobber (reg:DI 26))
6617 (clobber (reg:DI 27))]
6618 "TARGET_ABI_OPEN_VMS"
6620 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6621 switch (which_alternative)
6624 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6626 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6631 [(set_attr "type" "multi")
6632 (set_attr "length" "24")])
6635 ;; Subroutine of stack space allocation. Perform a stack probe.
6636 (define_expand "probe_stack"
6637 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6640 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6641 INTVAL (operands[0])));
6642 MEM_VOLATILE_P (operands[1]) = 1;
6644 operands[0] = const0_rtx;
6647 ;; This is how we allocate stack space. If we are allocating a
6648 ;; constant amount of space and we know it is less than 4096
6649 ;; bytes, we need do nothing.
6651 ;; If it is more than 4096 bytes, we need to probe the stack
6653 (define_expand "allocate_stack"
6655 (plus:DI (reg:DI 30)
6656 (match_operand:DI 1 "reg_or_cint_operand" "")))
6657 (set (match_operand:DI 0 "register_operand" "=r")
6661 if (GET_CODE (operands[1]) == CONST_INT
6662 && INTVAL (operands[1]) < 32768)
6664 if (INTVAL (operands[1]) >= 4096)
6666 /* We do this the same way as in the prologue and generate explicit
6667 probes. Then we update the stack by the constant. */
6671 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6672 while (probed + 8192 < INTVAL (operands[1]))
6673 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6675 if (probed + 4096 < INTVAL (operands[1]))
6676 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6679 operands[1] = GEN_INT (- INTVAL (operands[1]));
6680 operands[2] = virtual_stack_dynamic_rtx;
6685 rtx loop_label = gen_label_rtx ();
6686 rtx want = gen_reg_rtx (Pmode);
6687 rtx tmp = gen_reg_rtx (Pmode);
6690 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6691 force_reg (Pmode, operands[1])));
6692 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6694 if (GET_CODE (operands[1]) != CONST_INT)
6696 out_label = gen_label_rtx ();
6697 emit_insn (gen_cmpdi (want, tmp));
6698 emit_jump_insn (gen_bgeu (out_label));
6701 emit_label (loop_label);
6702 memref = gen_rtx_MEM (DImode, tmp);
6703 MEM_VOLATILE_P (memref) = 1;
6704 emit_move_insn (memref, const0_rtx);
6705 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6706 emit_insn (gen_cmpdi (tmp, want));
6707 emit_jump_insn (gen_bgtu (loop_label));
6709 memref = gen_rtx_MEM (DImode, want);
6710 MEM_VOLATILE_P (memref) = 1;
6711 emit_move_insn (memref, const0_rtx);
6714 emit_label (out_label);
6716 emit_move_insn (stack_pointer_rtx, want);
6717 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6722 ;; This is used by alpha_expand_prolog to do the same thing as above,
6723 ;; except we cannot at that time generate new basic blocks, so we hide
6724 ;; the loop in this one insn.
6726 (define_insn "prologue_stack_probe_loop"
6727 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6728 (match_operand:DI 1 "register_operand" "r")]
6732 operands[2] = gen_label_rtx ();
6733 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6734 CODE_LABEL_NUMBER (operands[2]));
6736 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6738 [(set_attr "length" "16")
6739 (set_attr "type" "multi")])
6741 (define_expand "prologue"
6742 [(clobber (const_int 0))]
6745 alpha_expand_prologue ();
6749 ;; These take care of emitting the ldgp insn in the prologue. This will be
6750 ;; an lda/ldah pair and we want to align them properly. So we have two
6751 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6752 ;; and the second of which emits nothing. However, both are marked as type
6753 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6756 (define_expand "prologue_ldgp"
6758 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6760 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6763 operands[0] = pic_offset_table_rtx;
6764 operands[1] = gen_rtx_REG (Pmode, 27);
6765 operands[2] = (TARGET_EXPLICIT_RELOCS
6766 ? GEN_INT (alpha_next_sequence_number++)
6770 (define_insn "*ldgp_er_1"
6771 [(set (match_operand:DI 0 "register_operand" "=r")
6772 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6773 (match_operand 2 "const_int_operand" "")]
6775 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6776 "ldah %0,0(%1)\t\t!gpdisp!%2")
6778 (define_insn "*ldgp_er_2"
6779 [(set (match_operand:DI 0 "register_operand" "=r")
6780 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6781 (match_operand 2 "const_int_operand" "")]
6783 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6784 "lda %0,0(%1)\t\t!gpdisp!%2")
6786 (define_insn "*prologue_ldgp_er_2"
6787 [(set (match_operand:DI 0 "register_operand" "=r")
6788 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6789 (match_operand 2 "const_int_operand" "")]
6791 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6792 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6794 (define_insn "*prologue_ldgp_1"
6795 [(set (match_operand:DI 0 "register_operand" "=r")
6796 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6797 (match_operand 2 "const_int_operand" "")]
6800 "ldgp %0,0(%1)\n$%~..ng:")
6802 (define_insn "*prologue_ldgp_2"
6803 [(set (match_operand:DI 0 "register_operand" "=r")
6804 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6805 (match_operand 2 "const_int_operand" "")]
6810 ;; The _mcount profiling hook has special calling conventions, and
6811 ;; does not clobber all the registers that a normal call would. So
6812 ;; hide the fact this is a call at all.
6814 (define_insn "prologue_mcount"
6815 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6818 if (TARGET_EXPLICIT_RELOCS)
6819 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6820 cannot be called via the PLT. */
6821 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6823 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6825 [(set_attr "type" "multi")
6826 (set_attr "length" "8")])
6828 (define_insn "init_fp"
6829 [(set (match_operand:DI 0 "register_operand" "=r")
6830 (match_operand:DI 1 "register_operand" "r"))
6831 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6835 (define_expand "epilogue"
6839 alpha_expand_epilogue ();
6842 (define_expand "sibcall_epilogue"
6846 alpha_expand_epilogue ();
6850 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6851 ;; the frame size into a register. We use this pattern to ensure
6852 ;; we get lda instead of addq.
6853 (define_insn "nt_lda"
6854 [(set (match_operand:DI 0 "register_operand" "=r")
6855 (unspec:DI [(match_dup 0)
6856 (match_operand:DI 1 "const_int_operand" "n")]
6861 (define_expand "builtin_longjmp"
6862 [(use (match_operand:DI 0 "register_operand" "r"))]
6865 /* The elements of the buffer are, in order: */
6866 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6867 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6868 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6869 rtx pv = gen_rtx_REG (Pmode, 27);
6871 /* This bit is the same as expand_builtin_longjmp. */
6872 emit_move_insn (hard_frame_pointer_rtx, fp);
6873 emit_move_insn (pv, lab);
6874 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6875 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6876 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6878 /* Load the label we are jumping through into $27 so that we know
6879 where to look for it when we get back to setjmp's function for
6880 restoring the gp. */
6881 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6886 ;; This is effectively a copy of indirect_jump, but constrained such
6887 ;; that register renaming cannot foil our cunning plan with $27.
6888 (define_insn "builtin_longjmp_internal"
6890 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6894 [(set_attr "type" "ibr")])
6896 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6897 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6898 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6899 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6901 (define_insn "*builtin_setjmp_receiver_er_1"
6902 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6903 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6904 "br $27,$LSJ%=\n$LSJ%=:"
6905 [(set_attr "type" "ibr")])
6908 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6909 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6910 && prev_nonnote_insn (insn) == operands[0]"
6914 emit_note (NOTE_INSN_DELETED);
6918 (define_insn "*builtin_setjmp_receiver_1"
6919 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6921 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6922 [(set_attr "length" "12")
6923 (set_attr "type" "multi")])
6925 (define_expand "builtin_setjmp_receiver_er"
6926 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6928 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6930 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6933 operands[1] = pic_offset_table_rtx;
6934 operands[2] = gen_rtx_REG (Pmode, 27);
6935 operands[3] = GEN_INT (alpha_next_sequence_number++);
6938 (define_expand "builtin_setjmp_receiver"
6939 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6942 if (TARGET_EXPLICIT_RELOCS)
6944 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6949 (define_expand "exception_receiver_er"
6951 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6953 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6956 operands[0] = pic_offset_table_rtx;
6957 operands[1] = gen_rtx_REG (Pmode, 26);
6958 operands[2] = GEN_INT (alpha_next_sequence_number++);
6961 (define_expand "exception_receiver"
6962 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6965 if (TARGET_LD_BUGGY_LDGP)
6966 operands[0] = alpha_gp_save_rtx ();
6967 else if (TARGET_EXPLICIT_RELOCS)
6969 emit_insn (gen_exception_receiver_er ());
6973 operands[0] = const0_rtx;
6976 (define_insn "*exception_receiver_1"
6977 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6978 "! TARGET_LD_BUGGY_LDGP"
6980 [(set_attr "length" "8")
6981 (set_attr "type" "multi")])
6983 (define_insn "*exception_receiver_2"
6984 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6985 "TARGET_LD_BUGGY_LDGP"
6987 [(set_attr "type" "ild")])
6989 (define_expand "nonlocal_goto_receiver"
6990 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6991 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6992 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6994 "TARGET_ABI_OPEN_VMS"
6997 (define_insn "arg_home"
6998 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7013 (clobber (mem:BLK (const_int 0)))
7014 (clobber (reg:DI 24))
7015 (clobber (reg:DI 25))
7016 (clobber (reg:DI 0))]
7017 "TARGET_ABI_OPEN_VMS"
7018 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7019 [(set_attr "length" "16")
7020 (set_attr "type" "multi")])
7022 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7024 (define_expand "umk_mismatch_args"
7025 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7026 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7027 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7028 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7031 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7032 "TARGET_ABI_UNICOSMK"
7034 operands[1] = gen_reg_rtx (DImode);
7035 operands[2] = gen_reg_rtx (DImode);
7036 operands[3] = gen_reg_rtx (DImode);
7039 (define_insn "arg_home_umk"
7040 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7055 (clobber (mem:BLK (const_int 0)))
7057 (clobber (reg:DI 22))
7058 (clobber (reg:DI 23))
7059 (clobber (reg:DI 24))
7060 (clobber (reg:DI 0))
7061 (clobber (reg:DI 1))
7062 (clobber (reg:DI 2))
7063 (clobber (reg:DI 3))
7064 (clobber (reg:DI 4))
7065 (clobber (reg:DI 5))
7066 (clobber (reg:DI 6))
7067 (clobber (reg:DI 7))
7068 (clobber (reg:DI 8))])]
7069 "TARGET_ABI_UNICOSMK"
7070 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7071 [(set_attr "length" "16")
7072 (set_attr "type" "multi")])
7076 ;; On EV4, these instructions are nops -- no load occurs.
7078 ;; On EV5, these instructions act as a normal load, and thus can trap
7079 ;; if the address is invalid. The OS may (or may not) handle this in
7080 ;; the entMM fault handler and suppress the fault. If so, then this
7081 ;; has the effect of a read prefetch instruction.
7083 ;; On EV6, these become official prefetch instructions.
7085 (define_insn "prefetch"
7086 [(prefetch (match_operand:DI 0 "address_operand" "p")
7087 (match_operand:DI 1 "const_int_operand" "n")
7088 (match_operand:DI 2 "const_int_operand" "n"))]
7089 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
7091 /* Interpret "no temporal locality" as this data should be evicted once
7092 it is used. The "evict next" alternatives load the data into the cache
7093 and leave the LRU eviction counter pointing to that block. */
7094 static const char * const alt[2][2] = {
7096 "ldq $31,%a0", /* read, evict next */
7097 "ldl $31,%a0", /* read, evict last */
7100 "ldt $f31,%a0", /* write, evict next */
7101 "lds $f31,%a0", /* write, evict last */
7105 bool write = INTVAL (operands[1]) != 0;
7106 bool lru = INTVAL (operands[2]) != 0;
7108 return alt[write][lru];
7110 [(set_attr "type" "ild")])
7112 ;; Close the trap shadow of preceding instructions. This is generated
7115 (define_insn "trapb"
7116 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7119 [(set_attr "type" "misc")])
7121 ;; No-op instructions used by machine-dependent reorg to preserve
7122 ;; alignment for instruction issue.
7123 ;; The Unicos/Mk assembler does not support these opcodes.
7129 [(set_attr "type" "ilog")])
7134 "cpys $f31,$f31,$f31"
7135 [(set_attr "type" "fcpys")])
7142 ;; On Unicos/Mk we use a macro for aligning code.
7144 (define_insn "realign"
7145 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7149 if (TARGET_ABI_UNICOSMK)
7150 return "gcc@code@align %0";
7152 return ".align %0 #realign";
7155 ;; Instructions to be emitted from __builtins.
7157 (define_insn "builtin_cmpbge"
7158 [(set (match_operand:DI 0 "register_operand" "=r")
7159 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7160 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7164 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7165 ;; actually differentiate between ILOG and ICMP in the schedule.
7166 [(set_attr "type" "icmp")])
7168 (define_expand "builtin_extbl"
7169 [(match_operand:DI 0 "register_operand" "")
7170 (match_operand:DI 1 "reg_or_0_operand" "")
7171 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7174 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7175 if (WORDS_BIG_ENDIAN)
7179 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7183 (define_expand "builtin_extwl"
7184 [(match_operand:DI 0 "register_operand" "")
7185 (match_operand:DI 1 "reg_or_0_operand" "")
7186 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7189 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7190 if (WORDS_BIG_ENDIAN)
7194 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7198 (define_expand "builtin_extll"
7199 [(match_operand:DI 0 "register_operand" "")
7200 (match_operand:DI 1 "reg_or_0_operand" "")
7201 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7204 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7205 if (WORDS_BIG_ENDIAN)
7209 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7213 (define_expand "builtin_extql"
7214 [(match_operand:DI 0 "register_operand" "")
7215 (match_operand:DI 1 "reg_or_0_operand" "")
7216 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7219 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7220 if (WORDS_BIG_ENDIAN)
7224 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7228 (define_expand "builtin_extwh"
7229 [(match_operand:DI 0 "register_operand" "")
7230 (match_operand:DI 1 "reg_or_0_operand" "")
7231 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7234 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7235 if (WORDS_BIG_ENDIAN)
7239 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7243 (define_expand "builtin_extlh"
7244 [(match_operand:DI 0 "register_operand" "")
7245 (match_operand:DI 1 "reg_or_0_operand" "")
7246 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7249 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7250 if (WORDS_BIG_ENDIAN)
7254 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7258 (define_expand "builtin_extqh"
7259 [(match_operand:DI 0 "register_operand" "")
7260 (match_operand:DI 1 "reg_or_0_operand" "")
7261 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7264 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7265 if (WORDS_BIG_ENDIAN)
7269 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7273 (define_expand "builtin_insbl"
7274 [(match_operand:DI 0 "register_operand" "")
7275 (match_operand:DI 1 "reg_or_0_operand" "")
7276 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7279 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7280 if (WORDS_BIG_ENDIAN)
7284 operands[1] = gen_lowpart (QImode, operands[1]);
7285 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7289 (define_expand "builtin_inswl"
7290 [(match_operand:DI 0 "register_operand" "")
7291 (match_operand:DI 1 "reg_or_0_operand" "")
7292 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7295 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7296 if (WORDS_BIG_ENDIAN)
7300 operands[1] = gen_lowpart (HImode, operands[1]);
7301 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7305 (define_expand "builtin_insll"
7306 [(match_operand:DI 0 "register_operand" "")
7307 (match_operand:DI 1 "reg_or_0_operand" "")
7308 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7311 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7312 if (WORDS_BIG_ENDIAN)
7316 operands[1] = gen_lowpart (SImode, operands[1]);
7317 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7318 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7322 (define_expand "builtin_insql"
7323 [(match_operand:DI 0 "register_operand" "")
7324 (match_operand:DI 1 "reg_or_0_operand" "")
7325 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7328 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7329 if (WORDS_BIG_ENDIAN)
7333 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7337 (define_expand "builtin_inswh"
7338 [(match_operand:DI 0 "register_operand" "")
7339 (match_operand:DI 1 "register_operand" "")
7340 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7343 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7347 (define_expand "builtin_inslh"
7348 [(match_operand:DI 0 "register_operand" "")
7349 (match_operand:DI 1 "register_operand" "")
7350 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7353 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7357 (define_expand "builtin_insqh"
7358 [(match_operand:DI 0 "register_operand" "")
7359 (match_operand:DI 1 "register_operand" "")
7360 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7363 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7367 (define_expand "builtin_mskbl"
7368 [(match_operand:DI 0 "register_operand" "")
7369 (match_operand:DI 1 "reg_or_0_operand" "")
7370 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7373 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7375 if (WORDS_BIG_ENDIAN)
7379 mask = GEN_INT (0xff);
7380 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7384 (define_expand "builtin_mskwl"
7385 [(match_operand:DI 0 "register_operand" "")
7386 (match_operand:DI 1 "reg_or_0_operand" "")
7387 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7390 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7392 if (WORDS_BIG_ENDIAN)
7396 mask = GEN_INT (0xffff);
7397 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7401 (define_expand "builtin_mskll"
7402 [(match_operand:DI 0 "register_operand" "")
7403 (match_operand:DI 1 "reg_or_0_operand" "")
7404 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7407 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7409 if (WORDS_BIG_ENDIAN)
7413 mask = immed_double_const (0xffffffff, 0, DImode);
7414 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7418 (define_expand "builtin_mskql"
7419 [(match_operand:DI 0 "register_operand" "")
7420 (match_operand:DI 1 "reg_or_0_operand" "")
7421 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7424 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7426 if (WORDS_BIG_ENDIAN)
7431 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7435 (define_expand "builtin_mskwh"
7436 [(match_operand:DI 0 "register_operand" "")
7437 (match_operand:DI 1 "register_operand" "")
7438 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7441 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7445 (define_expand "builtin_msklh"
7446 [(match_operand:DI 0 "register_operand" "")
7447 (match_operand:DI 1 "register_operand" "")
7448 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7451 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7455 (define_expand "builtin_mskqh"
7456 [(match_operand:DI 0 "register_operand" "")
7457 (match_operand:DI 1 "register_operand" "")
7458 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7461 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7465 (define_expand "builtin_zap"
7466 [(set (match_operand:DI 0 "register_operand" "")
7468 [(match_operand:DI 2 "reg_or_const_int_operand" "")]
7470 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7473 if (GET_CODE (operands[2]) == CONST_INT)
7475 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7477 if (mask == const0_rtx)
7479 emit_move_insn (operands[0], const0_rtx);
7482 if (mask == constm1_rtx)
7484 emit_move_insn (operands[0], operands[1]);
7488 operands[1] = force_reg (DImode, operands[1]);
7489 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7493 operands[1] = force_reg (DImode, operands[1]);
7494 operands[2] = gen_lowpart (QImode, operands[2]);
7497 (define_insn "*builtin_zap_1"
7498 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7500 [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")]
7502 (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))]
7509 [(set_attr "type" "shift,shift,ilog,shift")])
7512 [(set (match_operand:DI 0 "register_operand" "")
7514 [(match_operand:QI 2 "const_int_operand" "")]
7516 (match_operand:DI 1 "const_int_operand" "")))]
7520 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7521 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7522 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7525 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7526 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7527 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7528 c_hi & CONST_DOUBLE_HIGH (mask),
7531 emit_move_insn (operands[0], operands[1]);
7536 [(set (match_operand:DI 0 "register_operand" "")
7538 [(match_operand:QI 2 "const_int_operand" "")]
7540 (match_operand:DI 1 "register_operand" "")))]
7543 (and:DI (match_dup 1) (match_dup 2)))]
7545 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7546 if (operands[2] == const0_rtx)
7548 emit_move_insn (operands[0], const0_rtx);
7551 if (operands[2] == constm1_rtx)
7553 emit_move_insn (operands[0], operands[1]);
7558 (define_expand "builtin_zapnot"
7559 [(set (match_operand:DI 0 "register_operand" "")
7561 [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))]
7563 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7566 if (GET_CODE (operands[2]) == CONST_INT)
7568 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7570 if (mask == const0_rtx)
7572 emit_move_insn (operands[0], const0_rtx);
7575 if (mask == constm1_rtx)
7577 emit_move_insn (operands[0], operands[1]);
7581 operands[1] = force_reg (DImode, operands[1]);
7582 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7586 operands[1] = force_reg (DImode, operands[1]);
7587 operands[2] = gen_lowpart (QImode, operands[2]);
7590 (define_insn "*builtin_zapnot_1"
7591 [(set (match_operand:DI 0 "register_operand" "=r")
7593 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7595 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7598 [(set_attr "type" "shift")])
7600 (define_insn "builtin_amask"
7601 [(set (match_operand:DI 0 "register_operand" "=r")
7602 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7606 [(set_attr "type" "ilog")])
7608 (define_insn "builtin_implver"
7609 [(set (match_operand:DI 0 "register_operand" "=r")
7610 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7613 [(set_attr "type" "ilog")])
7615 (define_insn "builtin_rpcc"
7616 [(set (match_operand:DI 0 "register_operand" "=r")
7617 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7620 [(set_attr "type" "ilog")])
7622 (define_expand "builtin_minub8"
7623 [(match_operand:DI 0 "register_operand" "")
7624 (match_operand:DI 1 "reg_or_0_operand" "")
7625 (match_operand:DI 2 "reg_or_0_operand" "")]
7628 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7629 operands[1], operands[2]);
7633 (define_expand "builtin_minsb8"
7634 [(match_operand:DI 0 "register_operand" "")
7635 (match_operand:DI 1 "reg_or_0_operand" "")
7636 (match_operand:DI 2 "reg_or_0_operand" "")]
7639 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7640 operands[1], operands[2]);
7644 (define_expand "builtin_minuw4"
7645 [(match_operand:DI 0 "register_operand" "")
7646 (match_operand:DI 1 "reg_or_0_operand" "")
7647 (match_operand:DI 2 "reg_or_0_operand" "")]
7650 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7651 operands[1], operands[2]);
7655 (define_expand "builtin_minsw4"
7656 [(match_operand:DI 0 "register_operand" "")
7657 (match_operand:DI 1 "reg_or_0_operand" "")
7658 (match_operand:DI 2 "reg_or_0_operand" "")]
7661 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7662 operands[1], operands[2]);
7666 (define_expand "builtin_maxub8"
7667 [(match_operand:DI 0 "register_operand" "")
7668 (match_operand:DI 1 "reg_or_0_operand" "")
7669 (match_operand:DI 2 "reg_or_0_operand" "")]
7672 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7673 operands[1], operands[2]);
7677 (define_expand "builtin_maxsb8"
7678 [(match_operand:DI 0 "register_operand" "")
7679 (match_operand:DI 1 "reg_or_0_operand" "")
7680 (match_operand:DI 2 "reg_or_0_operand" "")]
7683 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7684 operands[1], operands[2]);
7688 (define_expand "builtin_maxuw4"
7689 [(match_operand:DI 0 "register_operand" "")
7690 (match_operand:DI 1 "reg_or_0_operand" "")
7691 (match_operand:DI 2 "reg_or_0_operand" "")]
7694 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7695 operands[1], operands[2]);
7699 (define_expand "builtin_maxsw4"
7700 [(match_operand:DI 0 "register_operand" "")
7701 (match_operand:DI 1 "reg_or_0_operand" "")
7702 (match_operand:DI 2 "reg_or_0_operand" "")]
7705 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7706 operands[1], operands[2]);
7710 (define_insn "builtin_perr"
7711 [(set (match_operand:DI 0 "register_operand" "=r")
7712 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7713 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7717 [(set_attr "type" "mvi")])
7719 (define_expand "builtin_pklb"
7720 [(set (match_operand:DI 0 "register_operand" "")
7723 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7728 operands[0] = gen_lowpart (V8QImode, operands[0]);
7729 operands[1] = gen_lowpart (V2SImode, operands[1]);
7730 operands[2] = CONST0_RTX (V2QImode);
7731 operands[3] = CONST0_RTX (V4QImode);
7734 (define_insn "*pklb"
7735 [(set (match_operand:V8QI 0 "register_operand" "=r")
7738 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7739 (match_operand:V2QI 2 "const0_operand" ""))
7740 (match_operand:V4QI 3 "const0_operand" "")))]
7743 [(set_attr "type" "mvi")])
7745 (define_expand "builtin_pkwb"
7746 [(set (match_operand:DI 0 "register_operand" "")
7748 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7752 operands[0] = gen_lowpart (V8QImode, operands[0]);
7753 operands[1] = gen_lowpart (V4HImode, operands[1]);
7754 operands[2] = CONST0_RTX (V4QImode);
7757 (define_insn "*pkwb"
7758 [(set (match_operand:V8QI 0 "register_operand" "=r")
7760 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7761 (match_operand:V4QI 2 "const0_operand" "")))]
7764 [(set_attr "type" "mvi")])
7766 (define_expand "builtin_unpkbl"
7767 [(set (match_operand:DI 0 "register_operand" "")
7769 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7770 (parallel [(const_int 0) (const_int 1)]))))]
7773 operands[0] = gen_lowpart (V2SImode, operands[0]);
7774 operands[1] = gen_lowpart (V8QImode, operands[1]);
7777 (define_insn "*unpkbl"
7778 [(set (match_operand:V2SI 0 "register_operand" "=r")
7780 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7781 (parallel [(const_int 0) (const_int 1)]))))]
7784 [(set_attr "type" "mvi")])
7786 (define_expand "builtin_unpkbw"
7787 [(set (match_operand:DI 0 "register_operand" "")
7789 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7790 (parallel [(const_int 0)
7796 operands[0] = gen_lowpart (V4HImode, operands[0]);
7797 operands[1] = gen_lowpart (V8QImode, operands[1]);
7800 (define_insn "*unpkbw"
7801 [(set (match_operand:V4HI 0 "register_operand" "=r")
7803 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7804 (parallel [(const_int 0)
7810 [(set_attr "type" "mvi")])
7812 (define_expand "builtin_cttz"
7813 [(set (match_operand:DI 0 "register_operand" "")
7814 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7819 (define_insn "builtin_ctlz"
7820 [(set (match_operand:DI 0 "register_operand" "=r")
7821 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7825 [(set_attr "type" "mvi")])
7827 (define_insn "builtin_ctpop"
7828 [(set (match_operand:DI 0 "register_operand" "=r")
7829 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7833 [(set_attr "type" "mvi")])
7835 ;; The call patterns are at the end of the file because their
7836 ;; wildcard operand0 interferes with nice recognition.
7838 (define_insn "*call_value_osf_1_er"
7839 [(set (match_operand 0 "" "")
7840 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7841 (match_operand 2 "" "")))
7843 (clobber (reg:DI 26))]
7844 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7846 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7847 bsr $26,%1\t\t!samegp
7848 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7849 [(set_attr "type" "jsr")
7850 (set_attr "length" "12,*,16")])
7852 ;; We must use peep2 instead of a split because we need accurate life
7853 ;; information for $gp. Consider the case of { bar(); while (1); }.
7855 [(parallel [(set (match_operand 0 "" "")
7856 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7857 (match_operand 2 "" "")))
7859 (clobber (reg:DI 26))])]
7860 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7861 && ! samegp_function_operand (operands[1], Pmode)
7862 && peep2_regno_dead_p (1, 29)"
7863 [(parallel [(set (match_dup 0)
7864 (call (mem:DI (match_dup 3))
7866 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7867 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7869 (use (match_dup 4))])]
7871 if (CONSTANT_P (operands[1]))
7873 operands[3] = gen_rtx_REG (Pmode, 27);
7874 operands[4] = GEN_INT (alpha_next_sequence_number++);
7875 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7876 operands[1], operands[4]));
7880 operands[3] = operands[1];
7881 operands[1] = const0_rtx;
7882 operands[4] = const0_rtx;
7887 [(parallel [(set (match_operand 0 "" "")
7888 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7889 (match_operand 2 "" "")))
7891 (clobber (reg:DI 26))])]
7892 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7893 && ! samegp_function_operand (operands[1], Pmode)
7894 && ! peep2_regno_dead_p (1, 29)"
7895 [(parallel [(set (match_dup 0)
7896 (call (mem:DI (match_dup 3))
7898 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7899 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7901 (use (match_dup 5))])
7903 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7905 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7907 if (CONSTANT_P (operands[1]))
7909 operands[3] = gen_rtx_REG (Pmode, 27);
7910 operands[5] = GEN_INT (alpha_next_sequence_number++);
7911 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7912 operands[1], operands[5]));
7916 operands[3] = operands[1];
7917 operands[1] = const0_rtx;
7918 operands[5] = const0_rtx;
7920 operands[4] = GEN_INT (alpha_next_sequence_number++);
7923 ;; We add a blockage unspec_volatile to prevent insns from moving down
7924 ;; from above the call to in between the call and the ldah gpdisp.
7925 (define_insn "*call_value_osf_2_er"
7926 [(set (match_operand 0 "" "")
7927 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7928 (match_operand 2 "" "")))
7930 (plus:DI (pc) (const_int 4)))
7931 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7932 (use (match_operand 3 "" ""))
7933 (use (match_operand 4 "" ""))]
7934 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7935 "jsr $26,(%1),%3%J4"
7936 [(set_attr "type" "jsr")])
7938 (define_insn "*call_value_osf_1_noreturn"
7939 [(set (match_operand 0 "" "")
7940 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7941 (match_operand 2 "" "")))
7943 (clobber (reg:DI 26))]
7944 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7945 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7950 [(set_attr "type" "jsr")
7951 (set_attr "length" "*,*,8")])
7953 (define_insn_and_split "call_value_osf_tlsgd"
7954 [(set (match_operand 0 "" "")
7955 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7957 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7959 (clobber (reg:DI 26))]
7962 "&& reload_completed"
7964 (unspec:DI [(match_dup 5)
7966 (match_dup 2)] UNSPEC_LITERAL))
7967 (parallel [(set (match_dup 0)
7968 (call (mem:DI (match_dup 3))
7970 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7971 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7973 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7975 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7977 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7979 operands[3] = gen_rtx_REG (Pmode, 27);
7980 operands[4] = GEN_INT (alpha_next_sequence_number++);
7981 operands[5] = pic_offset_table_rtx;
7983 [(set_attr "type" "multi")])
7985 (define_insn_and_split "call_value_osf_tlsldm"
7986 [(set (match_operand 0 "" "")
7987 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7989 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7991 (clobber (reg:DI 26))]
7994 "&& reload_completed"
7996 (unspec:DI [(match_dup 5)
7998 (match_dup 2)] UNSPEC_LITERAL))
7999 (parallel [(set (match_dup 0)
8000 (call (mem:DI (match_dup 3))
8002 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
8003 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
8005 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
8007 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
8009 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
8011 operands[3] = gen_rtx_REG (Pmode, 27);
8012 operands[4] = GEN_INT (alpha_next_sequence_number++);
8013 operands[5] = pic_offset_table_rtx;
8015 [(set_attr "type" "multi")])
8017 (define_insn "*call_value_osf_1"
8018 [(set (match_operand 0 "" "")
8019 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8020 (match_operand 2 "" "")))
8022 (clobber (reg:DI 26))]
8023 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8025 jsr $26,($27),0\;ldgp $29,0($26)
8027 jsr $26,%1\;ldgp $29,0($26)"
8028 [(set_attr "type" "jsr")
8029 (set_attr "length" "12,*,16")])
8031 (define_insn "*sibcall_value_osf_1_er"
8032 [(set (match_operand 0 "" "")
8033 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8034 (match_operand 2 "" "")))
8035 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8036 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8038 br $31,%1\t\t!samegp
8039 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8040 [(set_attr "type" "jsr")
8041 (set_attr "length" "*,8")])
8043 (define_insn "*sibcall_value_osf_1"
8044 [(set (match_operand 0 "" "")
8045 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8046 (match_operand 2 "" "")))
8047 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8048 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8051 lda $27,%1\;jmp $31,($27),%1"
8052 [(set_attr "type" "jsr")
8053 (set_attr "length" "*,8")])
8055 (define_insn "*call_value_nt_1"
8056 [(set (match_operand 0 "" "")
8057 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8058 (match_operand 2 "" "")))
8059 (clobber (reg:DI 26))]
8060 "TARGET_ABI_WINDOWS_NT"
8065 [(set_attr "type" "jsr")
8066 (set_attr "length" "*,*,12")])
8068 ; GAS relies on the order and position of instructions output below in order
8069 ; to generate relocs for VMS link to potentially optimize the call.
8070 ; Please do not molest.
8071 (define_insn "*call_value_vms_1"
8072 [(set (match_operand 0 "" "")
8073 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8074 (match_operand 2 "" "")))
8075 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8078 (clobber (reg:DI 27))]
8079 "TARGET_ABI_OPEN_VMS"
8081 switch (which_alternative)
8084 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8086 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8087 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8088 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8093 [(set_attr "type" "jsr")
8094 (set_attr "length" "12,16")])
8096 (define_insn "*call_value_umk"
8097 [(set (match_operand 0 "" "")
8098 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8099 (match_operand 2 "" "")))
8101 (clobber (reg:DI 26))]
8102 "TARGET_ABI_UNICOSMK"
8104 [(set_attr "type" "jsr")])