1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
66 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
67 (UNSPECV_LONGJMP 3) ; builtin_longjmp
69 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
71 (UNSPECV_EHR 7) ; exception_receiver
75 (UNSPECV_PLDGP2 11) ; prologue ldgp
80 ;; Where necessary, the suffixes _le and _be are used to distinguish between
81 ;; little-endian and big-endian patterns.
83 ;; Note that the Unicos/Mk assembler does not support the following
84 ;; opcodes: mov, fmov, nop, fnop, unop.
86 ;; Processor type -- this attribute must exactly match the processor_type
87 ;; enumeration in alpha.h.
89 (define_attr "cpu" "ev4,ev5,ev6"
90 (const (symbol_ref "alpha_cpu")))
92 ;; Define an insn type attribute. This is used in function unit delay
93 ;; computations, among other purposes. For the most part, we use the names
94 ;; defined in the EV4 documentation, but add a few that we have to know about
98 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
99 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
100 (const_string "iadd"))
102 ;; Describe a user's asm statement.
103 (define_asm_attributes
104 [(set_attr "type" "multi")])
106 ;; Define the operand size an insn operates on. Used primarily by mul
107 ;; and div operations that have size dependent timings.
109 (define_attr "opsize" "si,di,udi"
112 ;; The TRAP attribute marks instructions that may generate traps
113 ;; (which are imprecise and may need a trapb if software completion
116 (define_attr "trap" "no,yes"
119 ;; The ROUND_SUFFIX attribute marks which instructions require a
120 ;; rounding-mode suffix. The value NONE indicates no suffix,
121 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
123 (define_attr "round_suffix" "none,normal,c"
124 (const_string "none"))
126 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
128 ;; SU accepts only /su (cmpt et al)
129 ;; SUI accepts only /sui (cvtqt and cvtqs)
130 ;; V_SV accepts /v and /sv (cvtql only)
131 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
132 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
134 ;; The actual suffix emitted is controled by alpha_fptm.
136 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
137 (const_string "none"))
139 ;; The length of an instruction sequence in bytes.
141 (define_attr "length" ""
144 ;; Include scheduling descriptions.
150 ;; First define the arithmetic insns. Note that the 32-bit forms also
153 ;; Handle 32-64 bit extension from memory to a floating point register
154 ;; specially, since this occurs frequently in int->double conversions.
156 ;; Note that while we must retain the =f case in the insn for reload's
157 ;; benefit, it should be eliminated after reload, so we should never emit
158 ;; code for that case. But we don't reject the possibility.
160 (define_expand "extendsidi2"
161 [(set (match_operand:DI 0 "register_operand" "")
162 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
166 (define_insn "*extendsidi2_nofix"
167 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
169 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
175 lds %0,%1\;cvtlq %0,%0"
176 [(set_attr "type" "iadd,ild,fadd,fld")
177 (set_attr "length" "*,*,*,8")])
179 (define_insn "*extendsidi2_fix"
180 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
182 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
189 lds %0,%1\;cvtlq %0,%0"
190 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
191 (set_attr "length" "*,*,*,*,8")])
193 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
195 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
196 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
198 [(set (match_dup 2) (match_dup 1))
199 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
200 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
202 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
203 ;; reload when converting fp->int.
206 [(set (match_operand:SI 0 "hard_int_register_operand" "")
207 (match_operand:SI 1 "memory_operand" ""))
208 (set (match_operand:DI 2 "hard_int_register_operand" "")
209 (sign_extend:DI (match_dup 0)))]
210 "true_regnum (operands[0]) == true_regnum (operands[2])
211 || peep2_reg_dead_p (2, operands[0])"
213 (sign_extend:DI (match_dup 1)))]
217 [(set (match_operand:SI 0 "hard_int_register_operand" "")
218 (match_operand:SI 1 "hard_fp_register_operand" ""))
219 (set (match_operand:DI 2 "hard_int_register_operand" "")
220 (sign_extend:DI (match_dup 0)))]
222 && (true_regnum (operands[0]) == true_regnum (operands[2])
223 || peep2_reg_dead_p (2, operands[0]))"
225 (sign_extend:DI (match_dup 1)))]
229 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
230 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
231 (set (match_operand:DI 2 "hard_int_register_operand" "")
233 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
235 (sign_extend:DI (match_dup 1)))]
238 ;; Don't say we have addsi3 if optimizing. This generates better code. We
239 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
240 (define_expand "addsi3"
241 [(set (match_operand:SI 0 "register_operand" "")
242 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
243 (match_operand:SI 2 "add_operand" "")))]
247 (define_insn "*addsi_internal"
248 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
249 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
250 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
259 [(set (match_operand:SI 0 "register_operand" "")
260 (plus:SI (match_operand:SI 1 "register_operand" "")
261 (match_operand:SI 2 "const_int_operand" "")))]
262 "! add_operand (operands[2], SImode)"
263 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
264 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
266 HOST_WIDE_INT val = INTVAL (operands[2]);
267 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
268 HOST_WIDE_INT rest = val - low;
270 operands[3] = GEN_INT (rest);
271 operands[4] = GEN_INT (low);
274 (define_insn "*addsi_se"
275 [(set (match_operand:DI 0 "register_operand" "=r,r")
277 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
278 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
284 (define_insn "*addsi_se2"
285 [(set (match_operand:DI 0 "register_operand" "=r,r")
287 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
288 (match_operand:DI 2 "sext_add_operand" "rI,O"))
296 [(set (match_operand:DI 0 "register_operand" "")
298 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
299 (match_operand:SI 2 "const_int_operand" ""))))
300 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
301 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
302 && INTVAL (operands[2]) % 4 == 0"
303 [(set (match_dup 3) (match_dup 4))
304 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
308 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
314 operands[4] = GEN_INT (val);
315 operands[5] = GEN_INT (mult);
319 [(set (match_operand:DI 0 "register_operand" "")
321 (plus:SI (match_operator:SI 1 "comparison_operator"
322 [(match_operand 2 "" "")
323 (match_operand 3 "" "")])
324 (match_operand:SI 4 "add_operand" ""))))
325 (clobber (match_operand:DI 5 "register_operand" ""))]
327 [(set (match_dup 5) (match_dup 6))
328 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
330 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
331 operands[2], operands[3]);
332 operands[7] = gen_lowpart (SImode, operands[5]);
335 (define_insn "addvsi3"
336 [(set (match_operand:SI 0 "register_operand" "=r,r")
337 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
338 (match_operand:SI 2 "sext_add_operand" "rI,O")))
339 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
340 (sign_extend:DI (match_dup 2)))
341 (sign_extend:DI (plus:SI (match_dup 1)
349 (define_expand "adddi3"
350 [(set (match_operand:DI 0 "register_operand" "")
351 (plus:DI (match_operand:DI 1 "register_operand" "")
352 (match_operand:DI 2 "add_operand" "")))]
356 (define_insn "*adddi_er_lo16_dtp"
357 [(set (match_operand:DI 0 "register_operand" "=r")
358 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
359 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
361 "lda %0,%2(%1)\t\t!dtprel")
363 (define_insn "*adddi_er_hi32_dtp"
364 [(set (match_operand:DI 0 "register_operand" "=r")
365 (plus:DI (match_operand:DI 1 "register_operand" "r")
366 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
368 "ldah %0,%2(%1)\t\t!dtprelhi")
370 (define_insn "*adddi_er_lo32_dtp"
371 [(set (match_operand:DI 0 "register_operand" "=r")
372 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
373 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
375 "lda %0,%2(%1)\t\t!dtprello")
377 (define_insn "*adddi_er_lo16_tp"
378 [(set (match_operand:DI 0 "register_operand" "=r")
379 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
380 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
382 "lda %0,%2(%1)\t\t!tprel")
384 (define_insn "*adddi_er_hi32_tp"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (plus:DI (match_operand:DI 1 "register_operand" "r")
387 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
389 "ldah %0,%2(%1)\t\t!tprelhi")
391 (define_insn "*adddi_er_lo32_tp"
392 [(set (match_operand:DI 0 "register_operand" "=r")
393 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
394 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
396 "lda %0,%2(%1)\t\t!tprello")
398 (define_insn "*adddi_er_high_l"
399 [(set (match_operand:DI 0 "register_operand" "=r")
400 (plus:DI (match_operand:DI 1 "register_operand" "r")
401 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
402 "TARGET_EXPLICIT_RELOCS"
403 "ldah %0,%2(%1)\t\t!gprelhigh")
406 [(set (match_operand:DI 0 "register_operand" "")
407 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
408 "TARGET_EXPLICIT_RELOCS && reload_completed"
410 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
411 "operands[2] = pic_offset_table_rtx;")
413 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
414 ;; With complications like
416 ;; The NT stack unwind code can't handle a subq to adjust the stack
417 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
418 ;; the exception handling code will loop if a subq is used and an
421 ;; The 19980616 change to emit prologues as RTL also confused some
422 ;; versions of GDB, which also interprets prologues. This has been
423 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
426 ;; and the fact that the three insns schedule exactly the same, it's
427 ;; just not worth the effort.
429 (define_insn "*adddi_internal"
430 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
431 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
432 (match_operand:DI 2 "add_operand" "r,K,L")))]
439 ;; ??? Allow large constants when basing off the frame pointer or some
440 ;; virtual register that may eliminate to the frame pointer. This is
441 ;; done because register elimination offsets will change the hi/lo split,
442 ;; and if we split before reload, we will require additional instructions.
444 (define_insn "*adddi_fp_hack"
445 [(set (match_operand:DI 0 "register_operand" "=r")
446 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
447 (match_operand:DI 2 "const_int_operand" "n")))]
448 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
449 && INTVAL (operands[2]) >= 0
450 /* This is the largest constant an lda+ldah pair can add, minus
451 an upper bound on the displacement between SP and AP during
452 register elimination. See INITIAL_ELIMINATION_OFFSET. */
453 && INTVAL (operands[2])
455 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
456 - ALPHA_ROUND(current_function_outgoing_args_size)
457 - (ALPHA_ROUND (get_frame_size ()
458 + max_reg_num () * UNITS_PER_WORD
459 + current_function_pretend_args_size)
460 - current_function_pretend_args_size))"
463 ;; Don't do this if we are adjusting SP since we don't want to do it
464 ;; in two steps. Don't split FP sources for the reason listed above.
466 [(set (match_operand:DI 0 "register_operand" "")
467 (plus:DI (match_operand:DI 1 "register_operand" "")
468 (match_operand:DI 2 "const_int_operand" "")))]
469 "! add_operand (operands[2], DImode)
470 && operands[0] != stack_pointer_rtx
471 && operands[1] != frame_pointer_rtx
472 && operands[1] != arg_pointer_rtx"
473 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
474 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
476 HOST_WIDE_INT val = INTVAL (operands[2]);
477 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
478 HOST_WIDE_INT rest = val - low;
480 operands[4] = GEN_INT (low);
481 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
482 operands[3] = GEN_INT (rest);
483 else if (! no_new_pseudos)
485 operands[3] = gen_reg_rtx (DImode);
486 emit_move_insn (operands[3], operands[2]);
487 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
494 (define_insn "*saddl"
495 [(set (match_operand:SI 0 "register_operand" "=r,r")
496 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
497 (match_operand:SI 2 "const48_operand" "I,I"))
498 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
504 (define_insn "*saddl_se"
505 [(set (match_operand:DI 0 "register_operand" "=r,r")
507 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
508 (match_operand:SI 2 "const48_operand" "I,I"))
509 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
516 [(set (match_operand:DI 0 "register_operand" "")
518 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
519 [(match_operand 2 "" "")
520 (match_operand 3 "" "")])
521 (match_operand:SI 4 "const48_operand" ""))
522 (match_operand:SI 5 "sext_add_operand" ""))))
523 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
525 [(set (match_dup 6) (match_dup 7))
527 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
530 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
531 operands[2], operands[3]);
532 operands[8] = gen_lowpart (SImode, operands[6]);
535 (define_insn "*saddq"
536 [(set (match_operand:DI 0 "register_operand" "=r,r")
537 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
538 (match_operand:DI 2 "const48_operand" "I,I"))
539 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
545 (define_insn "addvdi3"
546 [(set (match_operand:DI 0 "register_operand" "=r,r")
547 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
548 (match_operand:DI 2 "sext_add_operand" "rI,O")))
549 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
550 (sign_extend:TI (match_dup 2)))
551 (sign_extend:TI (plus:DI (match_dup 1)
559 (define_insn "negsi2"
560 [(set (match_operand:SI 0 "register_operand" "=r")
561 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
565 (define_insn "*negsi_se"
566 [(set (match_operand:DI 0 "register_operand" "=r")
567 (sign_extend:DI (neg:SI
568 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
572 (define_insn "negvsi2"
573 [(set (match_operand:SI 0 "register_operand" "=r")
574 (neg:SI (match_operand:SI 1 "register_operand" "r")))
575 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
576 (sign_extend:DI (neg:SI (match_dup 1))))
581 (define_insn "negdi2"
582 [(set (match_operand:DI 0 "register_operand" "=r")
583 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
587 (define_insn "negvdi2"
588 [(set (match_operand:DI 0 "register_operand" "=r")
589 (neg:DI (match_operand:DI 1 "register_operand" "r")))
590 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
591 (sign_extend:TI (neg:DI (match_dup 1))))
596 (define_expand "subsi3"
597 [(set (match_operand:SI 0 "register_operand" "")
598 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
599 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
603 (define_insn "*subsi_internal"
604 [(set (match_operand:SI 0 "register_operand" "=r")
605 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
606 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
610 (define_insn "*subsi_se"
611 [(set (match_operand:DI 0 "register_operand" "=r")
612 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
613 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
617 (define_insn "*subsi_se2"
618 [(set (match_operand:DI 0 "register_operand" "=r")
620 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
621 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
626 (define_insn "subvsi3"
627 [(set (match_operand:SI 0 "register_operand" "=r")
628 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
629 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
630 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
631 (sign_extend:DI (match_dup 2)))
632 (sign_extend:DI (minus:SI (match_dup 1)
638 (define_insn "subdi3"
639 [(set (match_operand:DI 0 "register_operand" "=r")
640 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
641 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
645 (define_insn "*ssubl"
646 [(set (match_operand:SI 0 "register_operand" "=r")
647 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
648 (match_operand:SI 2 "const48_operand" "I"))
649 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
653 (define_insn "*ssubl_se"
654 [(set (match_operand:DI 0 "register_operand" "=r")
656 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
657 (match_operand:SI 2 "const48_operand" "I"))
658 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
662 (define_insn "*ssubq"
663 [(set (match_operand:DI 0 "register_operand" "=r")
664 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
665 (match_operand:DI 2 "const48_operand" "I"))
666 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
670 (define_insn "subvdi3"
671 [(set (match_operand:DI 0 "register_operand" "=r")
672 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
673 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
674 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
675 (sign_extend:TI (match_dup 2)))
676 (sign_extend:TI (minus:DI (match_dup 1)
682 ;; The Unicos/Mk assembler doesn't support mull.
684 (define_insn "mulsi3"
685 [(set (match_operand:SI 0 "register_operand" "=r")
686 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
687 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
688 "!TARGET_ABI_UNICOSMK"
690 [(set_attr "type" "imul")
691 (set_attr "opsize" "si")])
693 (define_insn "*mulsi_se"
694 [(set (match_operand:DI 0 "register_operand" "=r")
696 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
697 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
698 "!TARGET_ABI_UNICOSMK"
700 [(set_attr "type" "imul")
701 (set_attr "opsize" "si")])
703 (define_insn "mulvsi3"
704 [(set (match_operand:SI 0 "register_operand" "=r")
705 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
706 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
707 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
708 (sign_extend:DI (match_dup 2)))
709 (sign_extend:DI (mult:SI (match_dup 1)
712 "!TARGET_ABI_UNICOSMK"
714 [(set_attr "type" "imul")
715 (set_attr "opsize" "si")])
717 (define_insn "muldi3"
718 [(set (match_operand:DI 0 "register_operand" "=r")
719 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
720 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
723 [(set_attr "type" "imul")])
725 (define_insn "mulvdi3"
726 [(set (match_operand:DI 0 "register_operand" "=r")
727 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
728 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
729 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
730 (sign_extend:TI (match_dup 2)))
731 (sign_extend:TI (mult:DI (match_dup 1)
736 [(set_attr "type" "imul")])
738 (define_insn "umuldi3_highpart"
739 [(set (match_operand:DI 0 "register_operand" "=r")
742 (mult:TI (zero_extend:TI
743 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
745 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
749 [(set_attr "type" "imul")
750 (set_attr "opsize" "udi")])
752 (define_insn "*umuldi3_highpart_const"
753 [(set (match_operand:DI 0 "register_operand" "=r")
756 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
757 (match_operand:TI 2 "cint8_operand" "I"))
761 [(set_attr "type" "imul")
762 (set_attr "opsize" "udi")])
764 ;; The divide and remainder operations take their inputs from r24 and
765 ;; r25, put their output in r27, and clobber r23 and r28 on all
766 ;; systems except Unicos/Mk. On Unicos, the standard library provides
767 ;; subroutines which use the standard calling convention and work on
770 ;; ??? Force sign-extension here because some versions of OSF/1 and
771 ;; Interix/NT don't do the right thing if the inputs are not properly
772 ;; sign-extended. But Linux, for instance, does not have this
773 ;; problem. Is it worth the complication here to eliminate the sign
776 (define_expand "divsi3"
778 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
780 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
781 (parallel [(set (match_dup 5)
782 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
783 (clobber (reg:DI 23))
784 (clobber (reg:DI 28))])
785 (set (match_operand:SI 0 "nonimmediate_operand" "")
786 (subreg:SI (match_dup 5) 0))]
787 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
789 operands[3] = gen_reg_rtx (DImode);
790 operands[4] = gen_reg_rtx (DImode);
791 operands[5] = gen_reg_rtx (DImode);
794 (define_expand "udivsi3"
796 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
798 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
799 (parallel [(set (match_dup 5)
800 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
801 (clobber (reg:DI 23))
802 (clobber (reg:DI 28))])
803 (set (match_operand:SI 0 "nonimmediate_operand" "")
804 (subreg:SI (match_dup 5) 0))]
805 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
807 operands[3] = gen_reg_rtx (DImode);
808 operands[4] = gen_reg_rtx (DImode);
809 operands[5] = gen_reg_rtx (DImode);
812 (define_expand "modsi3"
814 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
816 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
817 (parallel [(set (match_dup 5)
818 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
819 (clobber (reg:DI 23))
820 (clobber (reg:DI 28))])
821 (set (match_operand:SI 0 "nonimmediate_operand" "")
822 (subreg:SI (match_dup 5) 0))]
823 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
825 operands[3] = gen_reg_rtx (DImode);
826 operands[4] = gen_reg_rtx (DImode);
827 operands[5] = gen_reg_rtx (DImode);
830 (define_expand "umodsi3"
832 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
834 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
835 (parallel [(set (match_dup 5)
836 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
837 (clobber (reg:DI 23))
838 (clobber (reg:DI 28))])
839 (set (match_operand:SI 0 "nonimmediate_operand" "")
840 (subreg:SI (match_dup 5) 0))]
841 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
843 operands[3] = gen_reg_rtx (DImode);
844 operands[4] = gen_reg_rtx (DImode);
845 operands[5] = gen_reg_rtx (DImode);
848 (define_expand "divdi3"
849 [(parallel [(set (match_operand:DI 0 "register_operand" "")
850 (div:DI (match_operand:DI 1 "register_operand" "")
851 (match_operand:DI 2 "register_operand" "")))
852 (clobber (reg:DI 23))
853 (clobber (reg:DI 28))])]
854 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
857 (define_expand "udivdi3"
858 [(parallel [(set (match_operand:DI 0 "register_operand" "")
859 (udiv:DI (match_operand:DI 1 "register_operand" "")
860 (match_operand:DI 2 "register_operand" "")))
861 (clobber (reg:DI 23))
862 (clobber (reg:DI 28))])]
863 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
866 (define_expand "moddi3"
867 [(use (match_operand:DI 0 "register_operand" ""))
868 (use (match_operand:DI 1 "register_operand" ""))
869 (use (match_operand:DI 2 "register_operand" ""))]
870 "!TARGET_ABI_OPEN_VMS"
872 if (TARGET_ABI_UNICOSMK)
873 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
875 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
879 (define_expand "moddi3_dft"
880 [(parallel [(set (match_operand:DI 0 "register_operand" "")
881 (mod:DI (match_operand:DI 1 "register_operand" "")
882 (match_operand:DI 2 "register_operand" "")))
883 (clobber (reg:DI 23))
884 (clobber (reg:DI 28))])]
885 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
888 ;; On Unicos/Mk, we do as the system's C compiler does:
889 ;; compute the quotient, multiply and subtract.
891 (define_expand "moddi3_umk"
892 [(use (match_operand:DI 0 "register_operand" ""))
893 (use (match_operand:DI 1 "register_operand" ""))
894 (use (match_operand:DI 2 "register_operand" ""))]
895 "TARGET_ABI_UNICOSMK"
897 rtx div, mul = gen_reg_rtx (DImode);
899 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
900 NULL_RTX, 0, OPTAB_LIB);
901 div = force_reg (DImode, div);
902 emit_insn (gen_muldi3 (mul, operands[2], div));
903 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
907 (define_expand "umoddi3"
908 [(use (match_operand:DI 0 "register_operand" ""))
909 (use (match_operand:DI 1 "register_operand" ""))
910 (use (match_operand:DI 2 "register_operand" ""))]
911 "! TARGET_ABI_OPEN_VMS"
913 if (TARGET_ABI_UNICOSMK)
914 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
916 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
920 (define_expand "umoddi3_dft"
921 [(parallel [(set (match_operand:DI 0 "register_operand" "")
922 (umod:DI (match_operand:DI 1 "register_operand" "")
923 (match_operand:DI 2 "register_operand" "")))
924 (clobber (reg:DI 23))
925 (clobber (reg:DI 28))])]
926 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
929 (define_expand "umoddi3_umk"
930 [(use (match_operand:DI 0 "register_operand" ""))
931 (use (match_operand:DI 1 "register_operand" ""))
932 (use (match_operand:DI 2 "register_operand" ""))]
933 "TARGET_ABI_UNICOSMK"
935 rtx div, mul = gen_reg_rtx (DImode);
937 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
938 NULL_RTX, 1, OPTAB_LIB);
939 div = force_reg (DImode, div);
940 emit_insn (gen_muldi3 (mul, operands[2], div));
941 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
945 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
946 ;; expanded by the assembler.
948 (define_insn_and_split "*divmodsi_internal_er"
949 [(set (match_operand:DI 0 "register_operand" "=c")
950 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
951 [(match_operand:DI 1 "register_operand" "a")
952 (match_operand:DI 2 "register_operand" "b")])))
953 (clobber (reg:DI 23))
954 (clobber (reg:DI 28))]
955 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
956 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
957 "&& reload_completed"
958 [(parallel [(set (match_dup 0)
959 (sign_extend:DI (match_dup 3)))
962 (clobber (reg:DI 23))
963 (clobber (reg:DI 28))])]
966 switch (GET_CODE (operands[3]))
983 operands[4] = GEN_INT (alpha_next_sequence_number++);
984 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
985 gen_rtx_SYMBOL_REF (DImode, str),
988 [(set_attr "type" "jsr")
989 (set_attr "length" "8")])
991 (define_insn "*divmodsi_internal_er_1"
992 [(set (match_operand:DI 0 "register_operand" "=c")
993 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
994 [(match_operand:DI 1 "register_operand" "a")
995 (match_operand:DI 2 "register_operand" "b")])))
996 (use (match_operand:DI 4 "register_operand" "c"))
997 (use (match_operand 5 "const_int_operand" ""))
998 (clobber (reg:DI 23))
999 (clobber (reg:DI 28))]
1000 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1001 "jsr $23,($27),__%E3%J5"
1002 [(set_attr "type" "jsr")
1003 (set_attr "length" "4")])
1005 (define_insn "*divmodsi_internal"
1006 [(set (match_operand:DI 0 "register_operand" "=c")
1007 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1008 [(match_operand:DI 1 "register_operand" "a")
1009 (match_operand:DI 2 "register_operand" "b")])))
1010 (clobber (reg:DI 23))
1011 (clobber (reg:DI 28))]
1012 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1014 [(set_attr "type" "jsr")
1015 (set_attr "length" "8")])
1017 (define_insn_and_split "*divmoddi_internal_er"
1018 [(set (match_operand:DI 0 "register_operand" "=c")
1019 (match_operator:DI 3 "divmod_operator"
1020 [(match_operand:DI 1 "register_operand" "a")
1021 (match_operand:DI 2 "register_operand" "b")]))
1022 (clobber (reg:DI 23))
1023 (clobber (reg:DI 28))]
1024 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1025 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1026 "&& reload_completed"
1027 [(parallel [(set (match_dup 0) (match_dup 3))
1030 (clobber (reg:DI 23))
1031 (clobber (reg:DI 28))])]
1034 switch (GET_CODE (operands[3]))
1051 operands[4] = GEN_INT (alpha_next_sequence_number++);
1052 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1053 gen_rtx_SYMBOL_REF (DImode, str),
1056 [(set_attr "type" "jsr")
1057 (set_attr "length" "8")])
1059 (define_insn "*divmoddi_internal_er_1"
1060 [(set (match_operand:DI 0 "register_operand" "=c")
1061 (match_operator:DI 3 "divmod_operator"
1062 [(match_operand:DI 1 "register_operand" "a")
1063 (match_operand:DI 2 "register_operand" "b")]))
1064 (use (match_operand:DI 4 "register_operand" "c"))
1065 (use (match_operand 5 "const_int_operand" ""))
1066 (clobber (reg:DI 23))
1067 (clobber (reg:DI 28))]
1068 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1069 "jsr $23,($27),__%E3%J5"
1070 [(set_attr "type" "jsr")
1071 (set_attr "length" "4")])
1073 (define_insn "*divmoddi_internal"
1074 [(set (match_operand:DI 0 "register_operand" "=c")
1075 (match_operator:DI 3 "divmod_operator"
1076 [(match_operand:DI 1 "register_operand" "a")
1077 (match_operand:DI 2 "register_operand" "b")]))
1078 (clobber (reg:DI 23))
1079 (clobber (reg:DI 28))]
1080 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1082 [(set_attr "type" "jsr")
1083 (set_attr "length" "8")])
1085 ;; Next are the basic logical operations. These only exist in DImode.
1087 (define_insn "anddi3"
1088 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1089 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1090 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1096 [(set_attr "type" "ilog,ilog,shift")])
1098 ;; There are times when we can split an AND into two AND insns. This occurs
1099 ;; when we can first clear any bytes and then clear anything else. For
1100 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1101 ;; Only do this when running on 64-bit host since the computations are
1102 ;; too messy otherwise.
1105 [(set (match_operand:DI 0 "register_operand" "")
1106 (and:DI (match_operand:DI 1 "register_operand" "")
1107 (match_operand:DI 2 "const_int_operand" "")))]
1108 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1109 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1110 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1112 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1113 unsigned HOST_WIDE_INT mask2 = mask1;
1116 /* For each byte that isn't all zeros, make it all ones. */
1117 for (i = 0; i < 64; i += 8)
1118 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1119 mask1 |= (HOST_WIDE_INT) 0xff << i;
1121 /* Now turn on any bits we've just turned off. */
1124 operands[3] = GEN_INT (mask1);
1125 operands[4] = GEN_INT (mask2);
1128 (define_expand "zero_extendqihi2"
1129 [(set (match_operand:HI 0 "register_operand" "")
1130 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1134 operands[1] = force_reg (QImode, operands[1]);
1137 (define_insn "*zero_extendqihi2_bwx"
1138 [(set (match_operand:HI 0 "register_operand" "=r,r")
1139 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1144 [(set_attr "type" "ilog,ild")])
1146 (define_insn "*zero_extendqihi2_nobwx"
1147 [(set (match_operand:HI 0 "register_operand" "=r")
1148 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1151 [(set_attr "type" "ilog")])
1153 (define_expand "zero_extendqisi2"
1154 [(set (match_operand:SI 0 "register_operand" "")
1155 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1159 operands[1] = force_reg (QImode, operands[1]);
1162 (define_insn "*zero_extendqisi2_bwx"
1163 [(set (match_operand:SI 0 "register_operand" "=r,r")
1164 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1169 [(set_attr "type" "ilog,ild")])
1171 (define_insn "*zero_extendqisi2_nobwx"
1172 [(set (match_operand:SI 0 "register_operand" "=r")
1173 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1176 [(set_attr "type" "ilog")])
1178 (define_expand "zero_extendqidi2"
1179 [(set (match_operand:DI 0 "register_operand" "")
1180 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1184 operands[1] = force_reg (QImode, operands[1]);
1187 (define_insn "*zero_extendqidi2_bwx"
1188 [(set (match_operand:DI 0 "register_operand" "=r,r")
1189 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1194 [(set_attr "type" "ilog,ild")])
1196 (define_insn "*zero_extendqidi2_nobwx"
1197 [(set (match_operand:DI 0 "register_operand" "=r")
1198 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1201 [(set_attr "type" "ilog")])
1203 (define_expand "zero_extendhisi2"
1204 [(set (match_operand:SI 0 "register_operand" "")
1205 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1209 operands[1] = force_reg (HImode, operands[1]);
1212 (define_insn "*zero_extendhisi2_bwx"
1213 [(set (match_operand:SI 0 "register_operand" "=r,r")
1214 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1219 [(set_attr "type" "shift,ild")])
1221 (define_insn "*zero_extendhisi2_nobwx"
1222 [(set (match_operand:SI 0 "register_operand" "=r")
1223 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1226 [(set_attr "type" "shift")])
1228 (define_expand "zero_extendhidi2"
1229 [(set (match_operand:DI 0 "register_operand" "")
1230 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1234 operands[1] = force_reg (HImode, operands[1]);
1237 (define_insn "*zero_extendhidi2_bwx"
1238 [(set (match_operand:DI 0 "register_operand" "=r,r")
1239 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1244 [(set_attr "type" "shift,ild")])
1246 (define_insn "*zero_extendhidi2_nobwx"
1247 [(set (match_operand:DI 0 "register_operand" "=r")
1248 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1251 [(set_attr "type" "shift")])
1253 (define_insn "zero_extendsidi2"
1254 [(set (match_operand:DI 0 "register_operand" "=r")
1255 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1258 [(set_attr "type" "shift")])
1260 (define_insn "andnotdi3"
1261 [(set (match_operand:DI 0 "register_operand" "=r")
1262 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1263 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1266 [(set_attr "type" "ilog")])
1268 (define_insn "iordi3"
1269 [(set (match_operand:DI 0 "register_operand" "=r,r")
1270 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1271 (match_operand:DI 2 "or_operand" "rI,N")))]
1276 [(set_attr "type" "ilog")])
1278 (define_insn "one_cmpldi2"
1279 [(set (match_operand:DI 0 "register_operand" "=r")
1280 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1283 [(set_attr "type" "ilog")])
1285 (define_insn "*iornot"
1286 [(set (match_operand:DI 0 "register_operand" "=r")
1287 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1288 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1291 [(set_attr "type" "ilog")])
1293 (define_insn "xordi3"
1294 [(set (match_operand:DI 0 "register_operand" "=r,r")
1295 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1296 (match_operand:DI 2 "or_operand" "rI,N")))]
1301 [(set_attr "type" "ilog")])
1303 (define_insn "*xornot"
1304 [(set (match_operand:DI 0 "register_operand" "=r")
1305 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1306 (match_operand:DI 2 "register_operand" "rI"))))]
1309 [(set_attr "type" "ilog")])
1311 ;; Handle the FFS insn iff we support CIX.
1313 (define_expand "ffsdi2"
1315 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1317 (plus:DI (match_dup 2) (const_int 1)))
1318 (set (match_operand:DI 0 "register_operand" "")
1319 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1320 (const_int 0) (match_dup 3)))]
1323 operands[2] = gen_reg_rtx (DImode);
1324 operands[3] = gen_reg_rtx (DImode);
1327 (define_insn "*cttz"
1328 [(set (match_operand:DI 0 "register_operand" "=r")
1329 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1332 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1333 ; reuse the existing type name.
1334 [(set_attr "type" "mvi")])
1336 ;; Next come the shifts and the various extract and insert operations.
1338 (define_insn "ashldi3"
1339 [(set (match_operand:DI 0 "register_operand" "=r,r")
1340 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1341 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1344 switch (which_alternative)
1347 if (operands[2] == const1_rtx)
1348 return "addq %r1,%r1,%0";
1350 return "s%P2addq %r1,0,%0";
1352 return "sll %r1,%2,%0";
1357 [(set_attr "type" "iadd,shift")])
1359 (define_insn "*ashldi_se"
1360 [(set (match_operand:DI 0 "register_operand" "=r")
1362 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1363 (match_operand:DI 2 "const_int_operand" "P"))
1365 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1367 if (operands[2] == const1_rtx)
1368 return "addl %r1,%r1,%0";
1370 return "s%P2addl %r1,0,%0";
1372 [(set_attr "type" "iadd")])
1374 (define_insn "lshrdi3"
1375 [(set (match_operand:DI 0 "register_operand" "=r")
1376 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1377 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1380 [(set_attr "type" "shift")])
1382 (define_insn "ashrdi3"
1383 [(set (match_operand:DI 0 "register_operand" "=r")
1384 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1385 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1388 [(set_attr "type" "shift")])
1390 (define_expand "extendqihi2"
1392 (ashift:DI (match_operand:QI 1 "some_operand" "")
1394 (set (match_operand:HI 0 "register_operand" "")
1395 (ashiftrt:DI (match_dup 2)
1401 emit_insn (gen_extendqihi2x (operands[0],
1402 force_reg (QImode, operands[1])));
1406 /* If we have an unaligned MEM, extend to DImode (which we do
1407 specially) and then copy to the result. */
1408 if (unaligned_memory_operand (operands[1], HImode))
1410 rtx temp = gen_reg_rtx (DImode);
1412 emit_insn (gen_extendqidi2 (temp, operands[1]));
1413 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1417 operands[0] = gen_lowpart (DImode, operands[0]);
1418 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1419 operands[2] = gen_reg_rtx (DImode);
1422 (define_insn "extendqidi2x"
1423 [(set (match_operand:DI 0 "register_operand" "=r")
1424 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1427 [(set_attr "type" "shift")])
1429 (define_insn "extendhidi2x"
1430 [(set (match_operand:DI 0 "register_operand" "=r")
1431 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1434 [(set_attr "type" "shift")])
1436 (define_insn "extendqisi2x"
1437 [(set (match_operand:SI 0 "register_operand" "=r")
1438 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1441 [(set_attr "type" "shift")])
1443 (define_insn "extendhisi2x"
1444 [(set (match_operand:SI 0 "register_operand" "=r")
1445 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1448 [(set_attr "type" "shift")])
1450 (define_insn "extendqihi2x"
1451 [(set (match_operand:HI 0 "register_operand" "=r")
1452 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1455 [(set_attr "type" "shift")])
1457 (define_expand "extendqisi2"
1459 (ashift:DI (match_operand:QI 1 "some_operand" "")
1461 (set (match_operand:SI 0 "register_operand" "")
1462 (ashiftrt:DI (match_dup 2)
1468 emit_insn (gen_extendqisi2x (operands[0],
1469 force_reg (QImode, operands[1])));
1473 /* If we have an unaligned MEM, extend to a DImode form of
1474 the result (which we do specially). */
1475 if (unaligned_memory_operand (operands[1], QImode))
1477 rtx temp = gen_reg_rtx (DImode);
1479 emit_insn (gen_extendqidi2 (temp, operands[1]));
1480 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1484 operands[0] = gen_lowpart (DImode, operands[0]);
1485 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1486 operands[2] = gen_reg_rtx (DImode);
1489 (define_expand "extendqidi2"
1491 (ashift:DI (match_operand:QI 1 "some_operand" "")
1493 (set (match_operand:DI 0 "register_operand" "")
1494 (ashiftrt:DI (match_dup 2)
1500 emit_insn (gen_extendqidi2x (operands[0],
1501 force_reg (QImode, operands[1])));
1505 if (unaligned_memory_operand (operands[1], QImode))
1508 = gen_unaligned_extendqidi (operands[0],
1509 get_unaligned_address (operands[1], 1));
1511 alpha_set_memflags (seq, operands[1]);
1516 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1517 operands[2] = gen_reg_rtx (DImode);
1520 (define_expand "extendhisi2"
1522 (ashift:DI (match_operand:HI 1 "some_operand" "")
1524 (set (match_operand:SI 0 "register_operand" "")
1525 (ashiftrt:DI (match_dup 2)
1531 emit_insn (gen_extendhisi2x (operands[0],
1532 force_reg (HImode, operands[1])));
1536 /* If we have an unaligned MEM, extend to a DImode form of
1537 the result (which we do specially). */
1538 if (unaligned_memory_operand (operands[1], HImode))
1540 rtx temp = gen_reg_rtx (DImode);
1542 emit_insn (gen_extendhidi2 (temp, operands[1]));
1543 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1547 operands[0] = gen_lowpart (DImode, operands[0]);
1548 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1549 operands[2] = gen_reg_rtx (DImode);
1552 (define_expand "extendhidi2"
1554 (ashift:DI (match_operand:HI 1 "some_operand" "")
1556 (set (match_operand:DI 0 "register_operand" "")
1557 (ashiftrt:DI (match_dup 2)
1563 emit_insn (gen_extendhidi2x (operands[0],
1564 force_reg (HImode, operands[1])));
1568 if (unaligned_memory_operand (operands[1], HImode))
1571 = gen_unaligned_extendhidi (operands[0],
1572 get_unaligned_address (operands[1], 2));
1574 alpha_set_memflags (seq, operands[1]);
1579 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1580 operands[2] = gen_reg_rtx (DImode);
1583 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1584 ;; as a pattern saves one instruction. The code is similar to that for
1585 ;; the unaligned loads (see below).
1587 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1588 (define_expand "unaligned_extendqidi"
1589 [(use (match_operand:QI 0 "register_operand" ""))
1590 (use (match_operand:DI 1 "address_operand" ""))]
1593 if (WORDS_BIG_ENDIAN)
1594 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1596 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1600 (define_expand "unaligned_extendqidi_le"
1601 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1603 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1606 (ashift:DI (match_dup 3)
1607 (minus:DI (const_int 64)
1609 (and:DI (match_dup 2) (const_int 7))
1611 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1612 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1613 "! WORDS_BIG_ENDIAN"
1615 operands[2] = gen_reg_rtx (DImode);
1616 operands[3] = gen_reg_rtx (DImode);
1617 operands[4] = gen_reg_rtx (DImode);
1620 (define_expand "unaligned_extendqidi_be"
1621 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1622 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1624 (mem:DI (and:DI (match_dup 3)
1626 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1628 (ashift:DI (match_dup 4)
1631 (plus:DI (match_dup 5) (const_int 1))
1634 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1635 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1638 operands[2] = gen_reg_rtx (DImode);
1639 operands[3] = gen_reg_rtx (DImode);
1640 operands[4] = gen_reg_rtx (DImode);
1641 operands[5] = gen_reg_rtx (DImode);
1642 operands[6] = gen_reg_rtx (DImode);
1645 (define_expand "unaligned_extendhidi"
1646 [(use (match_operand:QI 0 "register_operand" ""))
1647 (use (match_operand:DI 1 "address_operand" ""))]
1650 operands[0] = gen_lowpart (DImode, operands[0]);
1651 emit_insn ((WORDS_BIG_ENDIAN
1652 ? gen_unaligned_extendhidi_be
1653 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1657 (define_expand "unaligned_extendhidi_le"
1658 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1660 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1663 (ashift:DI (match_dup 3)
1664 (minus:DI (const_int 64)
1666 (and:DI (match_dup 2) (const_int 7))
1668 (set (match_operand:DI 0 "register_operand" "")
1669 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1670 "! WORDS_BIG_ENDIAN"
1672 operands[2] = gen_reg_rtx (DImode);
1673 operands[3] = gen_reg_rtx (DImode);
1674 operands[4] = gen_reg_rtx (DImode);
1677 (define_expand "unaligned_extendhidi_be"
1678 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1679 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1681 (mem:DI (and:DI (match_dup 3)
1683 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1685 (ashift:DI (match_dup 4)
1688 (plus:DI (match_dup 5) (const_int 1))
1691 (set (match_operand:DI 0 "register_operand" "")
1692 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1695 operands[2] = gen_reg_rtx (DImode);
1696 operands[3] = gen_reg_rtx (DImode);
1697 operands[4] = gen_reg_rtx (DImode);
1698 operands[5] = gen_reg_rtx (DImode);
1699 operands[6] = gen_reg_rtx (DImode);
1702 (define_insn "*extxl_const"
1703 [(set (match_operand:DI 0 "register_operand" "=r")
1704 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1705 (match_operand:DI 2 "mode_width_operand" "n")
1706 (match_operand:DI 3 "mul8_operand" "I")))]
1708 "ext%M2l %r1,%s3,%0"
1709 [(set_attr "type" "shift")])
1711 (define_insn "extxl_le"
1712 [(set (match_operand:DI 0 "register_operand" "=r")
1713 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1714 (match_operand:DI 2 "mode_width_operand" "n")
1715 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1717 "! WORDS_BIG_ENDIAN"
1719 [(set_attr "type" "shift")])
1721 (define_insn "extxl_be"
1722 [(set (match_operand:DI 0 "register_operand" "=r")
1723 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1724 (match_operand:DI 2 "mode_width_operand" "n")
1728 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1732 [(set_attr "type" "shift")])
1734 ;; Combine has some strange notion of preserving existing undefined behaviour
1735 ;; in shifts larger than a word size. So capture these patterns that it
1736 ;; should have turned into zero_extracts.
1738 (define_insn "*extxl_1_le"
1739 [(set (match_operand:DI 0 "register_operand" "=r")
1740 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1741 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1743 (match_operand:DI 3 "mode_mask_operand" "n")))]
1744 "! WORDS_BIG_ENDIAN"
1746 [(set_attr "type" "shift")])
1748 (define_insn "*extxl_1_be"
1749 [(set (match_operand:DI 0 "register_operand" "=r")
1750 (and:DI (lshiftrt:DI
1751 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1752 (minus:DI (const_int 56)
1753 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1755 (match_operand:DI 3 "mode_mask_operand" "n")))]
1758 [(set_attr "type" "shift")])
1760 (define_insn "*extql_2_le"
1761 [(set (match_operand:DI 0 "register_operand" "=r")
1762 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1763 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1765 "! WORDS_BIG_ENDIAN"
1767 [(set_attr "type" "shift")])
1769 (define_insn "*extql_2_be"
1770 [(set (match_operand:DI 0 "register_operand" "=r")
1772 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1773 (minus:DI (const_int 56)
1775 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1779 [(set_attr "type" "shift")])
1781 (define_insn "extqh_le"
1782 [(set (match_operand:DI 0 "register_operand" "=r")
1784 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1785 (minus:DI (const_int 64)
1788 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1791 "! WORDS_BIG_ENDIAN"
1793 [(set_attr "type" "shift")])
1795 (define_insn "extqh_be"
1796 [(set (match_operand:DI 0 "register_operand" "=r")
1798 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1801 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1807 [(set_attr "type" "shift")])
1809 (define_insn "extlh_le"
1810 [(set (match_operand:DI 0 "register_operand" "=r")
1812 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1813 (const_int 2147483647))
1814 (minus:DI (const_int 64)
1817 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1820 "! WORDS_BIG_ENDIAN"
1822 [(set_attr "type" "shift")])
1824 (define_insn "extlh_be"
1825 [(set (match_operand:DI 0 "register_operand" "=r")
1828 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1832 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1836 (const_int 2147483647)))]
1839 [(set_attr "type" "shift")])
1841 (define_insn "extwh_le"
1842 [(set (match_operand:DI 0 "register_operand" "=r")
1844 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1846 (minus:DI (const_int 64)
1849 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1852 "! WORDS_BIG_ENDIAN"
1854 [(set_attr "type" "shift")])
1856 (define_insn "extwh_be"
1857 [(set (match_operand:DI 0 "register_operand" "=r")
1859 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1863 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1867 (const_int 65535)))]
1870 [(set_attr "type" "shift")])
1872 ;; This converts an extXl into an extXh with an appropriate adjustment
1873 ;; to the address calculation.
1876 ;; [(set (match_operand:DI 0 "register_operand" "")
1877 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1878 ;; (match_operand:DI 2 "mode_width_operand" "")
1879 ;; (ashift:DI (match_operand:DI 3 "" "")
1881 ;; (match_operand:DI 4 "const_int_operand" "")))
1882 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1883 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1884 ;; [(set (match_dup 5) (match_dup 6))
1885 ;; (set (match_dup 0)
1886 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1887 ;; (ashift:DI (plus:DI (match_dup 5)
1893 ;; operands[6] = plus_constant (operands[3],
1894 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1895 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1898 (define_insn "*insbl_const"
1899 [(set (match_operand:DI 0 "register_operand" "=r")
1900 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1901 (match_operand:DI 2 "mul8_operand" "I")))]
1904 [(set_attr "type" "shift")])
1906 (define_insn "*inswl_const"
1907 [(set (match_operand:DI 0 "register_operand" "=r")
1908 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1909 (match_operand:DI 2 "mul8_operand" "I")))]
1912 [(set_attr "type" "shift")])
1914 (define_insn "*insll_const"
1915 [(set (match_operand:DI 0 "register_operand" "=r")
1916 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1917 (match_operand:DI 2 "mul8_operand" "I")))]
1920 [(set_attr "type" "shift")])
1922 (define_insn "insbl_le"
1923 [(set (match_operand:DI 0 "register_operand" "=r")
1924 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1925 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1927 "! WORDS_BIG_ENDIAN"
1929 [(set_attr "type" "shift")])
1931 (define_insn "insbl_be"
1932 [(set (match_operand:DI 0 "register_operand" "=r")
1933 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1934 (minus:DI (const_int 56)
1935 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1939 [(set_attr "type" "shift")])
1941 (define_insn "inswl_le"
1942 [(set (match_operand:DI 0 "register_operand" "=r")
1943 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1944 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1946 "! WORDS_BIG_ENDIAN"
1948 [(set_attr "type" "shift")])
1950 (define_insn "inswl_be"
1951 [(set (match_operand:DI 0 "register_operand" "=r")
1952 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1953 (minus:DI (const_int 56)
1954 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1958 [(set_attr "type" "shift")])
1960 (define_insn "insll_le"
1961 [(set (match_operand:DI 0 "register_operand" "=r")
1962 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1963 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1965 "! WORDS_BIG_ENDIAN"
1967 [(set_attr "type" "shift")])
1969 (define_insn "insll_be"
1970 [(set (match_operand:DI 0 "register_operand" "=r")
1971 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1972 (minus:DI (const_int 56)
1973 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1977 [(set_attr "type" "shift")])
1979 (define_insn "insql_le"
1980 [(set (match_operand:DI 0 "register_operand" "=r")
1981 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1982 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1984 "! WORDS_BIG_ENDIAN"
1986 [(set_attr "type" "shift")])
1988 (define_insn "insql_be"
1989 [(set (match_operand:DI 0 "register_operand" "=r")
1990 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1991 (minus:DI (const_int 56)
1992 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1996 [(set_attr "type" "shift")])
1998 ;; Combine has this sometimes habit of moving the and outside of the
1999 ;; shift, making life more interesting.
2001 (define_insn "*insxl"
2002 [(set (match_operand:DI 0 "register_operand" "=r")
2003 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2004 (match_operand:DI 2 "mul8_operand" "I"))
2005 (match_operand:DI 3 "immediate_operand" "i")))]
2006 "HOST_BITS_PER_WIDE_INT == 64
2007 && GET_CODE (operands[3]) == CONST_INT
2008 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2009 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2010 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2011 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2012 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2013 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2015 #if HOST_BITS_PER_WIDE_INT == 64
2016 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2017 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2018 return "insbl %1,%s2,%0";
2019 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2020 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2021 return "inswl %1,%s2,%0";
2022 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2023 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2024 return "insll %1,%s2,%0";
2028 [(set_attr "type" "shift")])
2030 ;; We do not include the insXh insns because they are complex to express
2031 ;; and it does not appear that we would ever want to generate them.
2033 ;; Since we need them for block moves, though, cop out and use unspec.
2035 (define_insn "insxh"
2036 [(set (match_operand:DI 0 "register_operand" "=r")
2037 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2038 (match_operand:DI 2 "mode_width_operand" "n")
2039 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2043 [(set_attr "type" "shift")])
2045 (define_insn "mskxl_le"
2046 [(set (match_operand:DI 0 "register_operand" "=r")
2047 (and:DI (not:DI (ashift:DI
2048 (match_operand:DI 2 "mode_mask_operand" "n")
2050 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2052 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2053 "! WORDS_BIG_ENDIAN"
2055 [(set_attr "type" "shift")])
2057 (define_insn "mskxl_be"
2058 [(set (match_operand:DI 0 "register_operand" "=r")
2059 (and:DI (not:DI (ashift:DI
2060 (match_operand:DI 2 "mode_mask_operand" "n")
2061 (minus:DI (const_int 56)
2063 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2065 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2068 [(set_attr "type" "shift")])
2070 ;; We do not include the mskXh insns because it does not appear we would
2071 ;; ever generate one.
2073 ;; Again, we do for block moves and we use unspec again.
2075 (define_insn "mskxh"
2076 [(set (match_operand:DI 0 "register_operand" "=r")
2077 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2078 (match_operand:DI 2 "mode_width_operand" "n")
2079 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2083 [(set_attr "type" "shift")])
2085 ;; Prefer AND + NE over LSHIFTRT + AND.
2087 (define_insn_and_split "*ze_and_ne"
2088 [(set (match_operand:DI 0 "register_operand" "=r")
2089 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2091 (match_operand 2 "const_int_operand" "I")))]
2092 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2094 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2096 (and:DI (match_dup 1) (match_dup 3)))
2098 (ne:DI (match_dup 0) (const_int 0)))]
2099 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2101 ;; Floating-point operations. All the double-precision insns can extend
2102 ;; from single, so indicate that. The exception are the ones that simply
2103 ;; play with the sign bits; it's not clear what to do there.
2105 (define_insn "abssf2"
2106 [(set (match_operand:SF 0 "register_operand" "=f")
2107 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2110 [(set_attr "type" "fcpys")])
2112 (define_insn "*nabssf2"
2113 [(set (match_operand:SF 0 "register_operand" "=f")
2114 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2117 [(set_attr "type" "fadd")])
2119 (define_insn "absdf2"
2120 [(set (match_operand:DF 0 "register_operand" "=f")
2121 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2124 [(set_attr "type" "fcpys")])
2126 (define_insn "*nabsdf2"
2127 [(set (match_operand:DF 0 "register_operand" "=f")
2128 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2131 [(set_attr "type" "fadd")])
2133 (define_expand "abstf2"
2134 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2135 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2136 (use (match_dup 2))])]
2137 "TARGET_HAS_XFLOATING_LIBS"
2139 #if HOST_BITS_PER_WIDE_INT >= 64
2140 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2142 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2146 (define_insn_and_split "*abstf_internal"
2147 [(set (match_operand:TF 0 "register_operand" "=r")
2148 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2149 (use (match_operand:DI 2 "register_operand" "r"))]
2150 "TARGET_HAS_XFLOATING_LIBS"
2152 "&& reload_completed"
2154 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2156 (define_insn "negsf2"
2157 [(set (match_operand:SF 0 "register_operand" "=f")
2158 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2161 [(set_attr "type" "fadd")])
2163 (define_insn "negdf2"
2164 [(set (match_operand:DF 0 "register_operand" "=f")
2165 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2168 [(set_attr "type" "fadd")])
2170 (define_expand "negtf2"
2171 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2172 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2173 (use (match_dup 2))])]
2174 "TARGET_HAS_XFLOATING_LIBS"
2176 #if HOST_BITS_PER_WIDE_INT >= 64
2177 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2179 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2183 (define_insn_and_split "*negtf_internal"
2184 [(set (match_operand:TF 0 "register_operand" "=r")
2185 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2186 (use (match_operand:DI 2 "register_operand" "r"))]
2187 "TARGET_HAS_XFLOATING_LIBS"
2189 "&& reload_completed"
2191 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2193 (define_insn "*addsf_ieee"
2194 [(set (match_operand:SF 0 "register_operand" "=&f")
2195 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2196 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2197 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2198 "add%,%/ %R1,%R2,%0"
2199 [(set_attr "type" "fadd")
2200 (set_attr "trap" "yes")
2201 (set_attr "round_suffix" "normal")
2202 (set_attr "trap_suffix" "u_su_sui")])
2204 (define_insn "addsf3"
2205 [(set (match_operand:SF 0 "register_operand" "=f")
2206 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2207 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2209 "add%,%/ %R1,%R2,%0"
2210 [(set_attr "type" "fadd")
2211 (set_attr "trap" "yes")
2212 (set_attr "round_suffix" "normal")
2213 (set_attr "trap_suffix" "u_su_sui")])
2215 (define_insn "*adddf_ieee"
2216 [(set (match_operand:DF 0 "register_operand" "=&f")
2217 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2218 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2219 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2220 "add%-%/ %R1,%R2,%0"
2221 [(set_attr "type" "fadd")
2222 (set_attr "trap" "yes")
2223 (set_attr "round_suffix" "normal")
2224 (set_attr "trap_suffix" "u_su_sui")])
2226 (define_insn "adddf3"
2227 [(set (match_operand:DF 0 "register_operand" "=f")
2228 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2229 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2231 "add%-%/ %R1,%R2,%0"
2232 [(set_attr "type" "fadd")
2233 (set_attr "trap" "yes")
2234 (set_attr "round_suffix" "normal")
2235 (set_attr "trap_suffix" "u_su_sui")])
2237 (define_insn "*adddf_ext1"
2238 [(set (match_operand:DF 0 "register_operand" "=f")
2239 (plus:DF (float_extend:DF
2240 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2241 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2242 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2243 "add%-%/ %R1,%R2,%0"
2244 [(set_attr "type" "fadd")
2245 (set_attr "trap" "yes")
2246 (set_attr "round_suffix" "normal")
2247 (set_attr "trap_suffix" "u_su_sui")])
2249 (define_insn "*adddf_ext2"
2250 [(set (match_operand:DF 0 "register_operand" "=f")
2251 (plus:DF (float_extend:DF
2252 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2254 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2255 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2256 "add%-%/ %R1,%R2,%0"
2257 [(set_attr "type" "fadd")
2258 (set_attr "trap" "yes")
2259 (set_attr "round_suffix" "normal")
2260 (set_attr "trap_suffix" "u_su_sui")])
2262 (define_expand "addtf3"
2263 [(use (match_operand 0 "register_operand" ""))
2264 (use (match_operand 1 "general_operand" ""))
2265 (use (match_operand 2 "general_operand" ""))]
2266 "TARGET_HAS_XFLOATING_LIBS"
2267 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2269 ;; Define conversion operators between DFmode and SImode, using the cvtql
2270 ;; instruction. To allow combine et al to do useful things, we keep the
2271 ;; operation as a unit until after reload, at which point we split the
2274 ;; Note that we (attempt to) only consider this optimization when the
2275 ;; ultimate destination is memory. If we will be doing further integer
2276 ;; processing, it is cheaper to do the truncation in the int regs.
2278 (define_insn "*cvtql"
2279 [(set (match_operand:SI 0 "register_operand" "=f")
2280 (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2284 [(set_attr "type" "fadd")
2285 (set_attr "trap" "yes")
2286 (set_attr "trap_suffix" "v_sv")])
2288 (define_insn_and_split "*fix_truncdfsi_ieee"
2289 [(set (match_operand:SI 0 "memory_operand" "=m")
2290 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2291 (clobber (match_scratch:DI 2 "=&f"))
2292 (clobber (match_scratch:SI 3 "=&f"))]
2293 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2295 "&& reload_completed"
2296 [(set (match_dup 2) (fix:DI (match_dup 1)))
2297 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2298 (set (match_dup 0) (match_dup 3))]
2300 [(set_attr "type" "fadd")
2301 (set_attr "trap" "yes")])
2303 (define_insn_and_split "*fix_truncdfsi_internal"
2304 [(set (match_operand:SI 0 "memory_operand" "=m")
2305 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2306 (clobber (match_scratch:DI 2 "=f"))]
2307 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2309 "&& reload_completed"
2310 [(set (match_dup 2) (fix:DI (match_dup 1)))
2311 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2312 (set (match_dup 0) (match_dup 3))]
2313 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2314 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2315 [(set_attr "type" "fadd")
2316 (set_attr "trap" "yes")])
2318 (define_insn "*fix_truncdfdi_ieee"
2319 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2320 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2321 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2323 [(set_attr "type" "fadd")
2324 (set_attr "trap" "yes")
2325 (set_attr "round_suffix" "c")
2326 (set_attr "trap_suffix" "v_sv_svi")])
2328 (define_insn "fix_truncdfdi2"
2329 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2330 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2333 [(set_attr "type" "fadd")
2334 (set_attr "trap" "yes")
2335 (set_attr "round_suffix" "c")
2336 (set_attr "trap_suffix" "v_sv_svi")])
2338 ;; Likewise between SFmode and SImode.
2340 (define_insn_and_split "*fix_truncsfsi_ieee"
2341 [(set (match_operand:SI 0 "memory_operand" "=m")
2342 (subreg:SI (fix:DI (float_extend:DF
2343 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2344 (clobber (match_scratch:DI 2 "=&f"))
2345 (clobber (match_scratch:SI 3 "=&f"))]
2346 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2348 "&& reload_completed"
2349 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2350 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2351 (set (match_dup 0) (match_dup 3))]
2353 [(set_attr "type" "fadd")
2354 (set_attr "trap" "yes")])
2356 (define_insn_and_split "*fix_truncsfsi_internal"
2357 [(set (match_operand:SI 0 "memory_operand" "=m")
2358 (subreg:SI (fix:DI (float_extend:DF
2359 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2360 (clobber (match_scratch:DI 2 "=f"))]
2361 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2363 "&& reload_completed"
2364 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2365 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2366 (set (match_dup 0) (match_dup 3))]
2367 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2368 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2369 [(set_attr "type" "fadd")
2370 (set_attr "trap" "yes")])
2372 (define_insn "*fix_truncsfdi_ieee"
2373 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2374 (fix:DI (float_extend:DF
2375 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2376 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2378 [(set_attr "type" "fadd")
2379 (set_attr "trap" "yes")
2380 (set_attr "round_suffix" "c")
2381 (set_attr "trap_suffix" "v_sv_svi")])
2383 (define_insn "fix_truncsfdi2"
2384 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2385 (fix:DI (float_extend:DF
2386 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2389 [(set_attr "type" "fadd")
2390 (set_attr "trap" "yes")
2391 (set_attr "round_suffix" "c")
2392 (set_attr "trap_suffix" "v_sv_svi")])
2394 (define_expand "fix_trunctfdi2"
2395 [(use (match_operand:DI 0 "register_operand" ""))
2396 (use (match_operand:TF 1 "general_operand" ""))]
2397 "TARGET_HAS_XFLOATING_LIBS"
2398 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2400 (define_insn "*floatdisf_ieee"
2401 [(set (match_operand:SF 0 "register_operand" "=&f")
2402 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2403 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2405 [(set_attr "type" "fadd")
2406 (set_attr "trap" "yes")
2407 (set_attr "round_suffix" "normal")
2408 (set_attr "trap_suffix" "sui")])
2410 (define_insn "floatdisf2"
2411 [(set (match_operand:SF 0 "register_operand" "=f")
2412 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2415 [(set_attr "type" "fadd")
2416 (set_attr "trap" "yes")
2417 (set_attr "round_suffix" "normal")
2418 (set_attr "trap_suffix" "sui")])
2420 (define_insn "*floatdidf_ieee"
2421 [(set (match_operand:DF 0 "register_operand" "=&f")
2422 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2423 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2425 [(set_attr "type" "fadd")
2426 (set_attr "trap" "yes")
2427 (set_attr "round_suffix" "normal")
2428 (set_attr "trap_suffix" "sui")])
2430 (define_insn "floatdidf2"
2431 [(set (match_operand:DF 0 "register_operand" "=f")
2432 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2435 [(set_attr "type" "fadd")
2436 (set_attr "trap" "yes")
2437 (set_attr "round_suffix" "normal")
2438 (set_attr "trap_suffix" "sui")])
2440 (define_expand "floatditf2"
2441 [(use (match_operand:TF 0 "register_operand" ""))
2442 (use (match_operand:DI 1 "general_operand" ""))]
2443 "TARGET_HAS_XFLOATING_LIBS"
2444 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2446 (define_expand "floatunsdisf2"
2447 [(use (match_operand:SF 0 "register_operand" ""))
2448 (use (match_operand:DI 1 "register_operand" ""))]
2450 "alpha_emit_floatuns (operands); DONE;")
2452 (define_expand "floatunsdidf2"
2453 [(use (match_operand:DF 0 "register_operand" ""))
2454 (use (match_operand:DI 1 "register_operand" ""))]
2456 "alpha_emit_floatuns (operands); DONE;")
2458 (define_expand "floatunsditf2"
2459 [(use (match_operand:TF 0 "register_operand" ""))
2460 (use (match_operand:DI 1 "general_operand" ""))]
2461 "TARGET_HAS_XFLOATING_LIBS"
2462 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2464 (define_expand "extendsfdf2"
2465 [(set (match_operand:DF 0 "register_operand" "")
2466 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2469 if (alpha_fptm >= ALPHA_FPTM_SU)
2470 operands[1] = force_reg (SFmode, operands[1]);
2473 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2474 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2476 (define_insn "*extendsfdf2_ieee"
2477 [(set (match_operand:DF 0 "register_operand" "=&f")
2478 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2479 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2481 [(set_attr "type" "fadd")
2482 (set_attr "trap" "yes")])
2484 (define_insn "*extendsfdf2_internal"
2485 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2486 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2487 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2492 [(set_attr "type" "fcpys,fld,fst")])
2494 (define_expand "extendsftf2"
2495 [(use (match_operand:TF 0 "register_operand" ""))
2496 (use (match_operand:SF 1 "general_operand" ""))]
2497 "TARGET_HAS_XFLOATING_LIBS"
2499 rtx tmp = gen_reg_rtx (DFmode);
2500 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2501 emit_insn (gen_extenddftf2 (operands[0], tmp));
2505 (define_expand "extenddftf2"
2506 [(use (match_operand:TF 0 "register_operand" ""))
2507 (use (match_operand:DF 1 "general_operand" ""))]
2508 "TARGET_HAS_XFLOATING_LIBS"
2509 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2511 (define_insn "*truncdfsf2_ieee"
2512 [(set (match_operand:SF 0 "register_operand" "=&f")
2513 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2514 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2516 [(set_attr "type" "fadd")
2517 (set_attr "trap" "yes")
2518 (set_attr "round_suffix" "normal")
2519 (set_attr "trap_suffix" "u_su_sui")])
2521 (define_insn "truncdfsf2"
2522 [(set (match_operand:SF 0 "register_operand" "=f")
2523 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2526 [(set_attr "type" "fadd")
2527 (set_attr "trap" "yes")
2528 (set_attr "round_suffix" "normal")
2529 (set_attr "trap_suffix" "u_su_sui")])
2531 (define_expand "trunctfdf2"
2532 [(use (match_operand:DF 0 "register_operand" ""))
2533 (use (match_operand:TF 1 "general_operand" ""))]
2534 "TARGET_HAS_XFLOATING_LIBS"
2535 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2537 (define_expand "trunctfsf2"
2538 [(use (match_operand:SF 0 "register_operand" ""))
2539 (use (match_operand:TF 1 "general_operand" ""))]
2540 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2542 rtx tmpf, sticky, arg, lo, hi;
2544 tmpf = gen_reg_rtx (DFmode);
2545 sticky = gen_reg_rtx (DImode);
2546 arg = copy_to_mode_reg (TFmode, operands[1]);
2547 lo = gen_lowpart (DImode, arg);
2548 hi = gen_highpart (DImode, arg);
2550 /* Convert the low word of the TFmode value into a sticky rounding bit,
2551 then or it into the low bit of the high word. This leaves the sticky
2552 bit at bit 48 of the fraction, which is representable in DFmode,
2553 which prevents rounding error in the final conversion to SFmode. */
2555 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2556 gen_rtx_NE (DImode, lo, const0_rtx)));
2557 emit_insn (gen_iordi3 (hi, hi, sticky));
2558 emit_insn (gen_trunctfdf2 (tmpf, arg));
2559 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2563 (define_insn "*divsf3_ieee"
2564 [(set (match_operand:SF 0 "register_operand" "=&f")
2565 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2566 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2567 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2568 "div%,%/ %R1,%R2,%0"
2569 [(set_attr "type" "fdiv")
2570 (set_attr "opsize" "si")
2571 (set_attr "trap" "yes")
2572 (set_attr "round_suffix" "normal")
2573 (set_attr "trap_suffix" "u_su_sui")])
2575 (define_insn "divsf3"
2576 [(set (match_operand:SF 0 "register_operand" "=f")
2577 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2578 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2580 "div%,%/ %R1,%R2,%0"
2581 [(set_attr "type" "fdiv")
2582 (set_attr "opsize" "si")
2583 (set_attr "trap" "yes")
2584 (set_attr "round_suffix" "normal")
2585 (set_attr "trap_suffix" "u_su_sui")])
2587 (define_insn "*divdf3_ieee"
2588 [(set (match_operand:DF 0 "register_operand" "=&f")
2589 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2590 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2591 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2592 "div%-%/ %R1,%R2,%0"
2593 [(set_attr "type" "fdiv")
2594 (set_attr "trap" "yes")
2595 (set_attr "round_suffix" "normal")
2596 (set_attr "trap_suffix" "u_su_sui")])
2598 (define_insn "divdf3"
2599 [(set (match_operand:DF 0 "register_operand" "=f")
2600 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2601 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2603 "div%-%/ %R1,%R2,%0"
2604 [(set_attr "type" "fdiv")
2605 (set_attr "trap" "yes")
2606 (set_attr "round_suffix" "normal")
2607 (set_attr "trap_suffix" "u_su_sui")])
2609 (define_insn "*divdf_ext1"
2610 [(set (match_operand:DF 0 "register_operand" "=f")
2611 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2612 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2613 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2614 "div%-%/ %R1,%R2,%0"
2615 [(set_attr "type" "fdiv")
2616 (set_attr "trap" "yes")
2617 (set_attr "round_suffix" "normal")
2618 (set_attr "trap_suffix" "u_su_sui")])
2620 (define_insn "*divdf_ext2"
2621 [(set (match_operand:DF 0 "register_operand" "=f")
2622 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2624 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2625 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2626 "div%-%/ %R1,%R2,%0"
2627 [(set_attr "type" "fdiv")
2628 (set_attr "trap" "yes")
2629 (set_attr "round_suffix" "normal")
2630 (set_attr "trap_suffix" "u_su_sui")])
2632 (define_insn "*divdf_ext3"
2633 [(set (match_operand:DF 0 "register_operand" "=f")
2634 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2635 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2636 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2637 "div%-%/ %R1,%R2,%0"
2638 [(set_attr "type" "fdiv")
2639 (set_attr "trap" "yes")
2640 (set_attr "round_suffix" "normal")
2641 (set_attr "trap_suffix" "u_su_sui")])
2643 (define_expand "divtf3"
2644 [(use (match_operand 0 "register_operand" ""))
2645 (use (match_operand 1 "general_operand" ""))
2646 (use (match_operand 2 "general_operand" ""))]
2647 "TARGET_HAS_XFLOATING_LIBS"
2648 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2650 (define_insn "*mulsf3_ieee"
2651 [(set (match_operand:SF 0 "register_operand" "=&f")
2652 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2653 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2654 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2655 "mul%,%/ %R1,%R2,%0"
2656 [(set_attr "type" "fmul")
2657 (set_attr "trap" "yes")
2658 (set_attr "round_suffix" "normal")
2659 (set_attr "trap_suffix" "u_su_sui")])
2661 (define_insn "mulsf3"
2662 [(set (match_operand:SF 0 "register_operand" "=f")
2663 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2664 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2666 "mul%,%/ %R1,%R2,%0"
2667 [(set_attr "type" "fmul")
2668 (set_attr "trap" "yes")
2669 (set_attr "round_suffix" "normal")
2670 (set_attr "trap_suffix" "u_su_sui")])
2672 (define_insn "*muldf3_ieee"
2673 [(set (match_operand:DF 0 "register_operand" "=&f")
2674 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2675 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2676 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2677 "mul%-%/ %R1,%R2,%0"
2678 [(set_attr "type" "fmul")
2679 (set_attr "trap" "yes")
2680 (set_attr "round_suffix" "normal")
2681 (set_attr "trap_suffix" "u_su_sui")])
2683 (define_insn "muldf3"
2684 [(set (match_operand:DF 0 "register_operand" "=f")
2685 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2686 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2688 "mul%-%/ %R1,%R2,%0"
2689 [(set_attr "type" "fmul")
2690 (set_attr "trap" "yes")
2691 (set_attr "round_suffix" "normal")
2692 (set_attr "trap_suffix" "u_su_sui")])
2694 (define_insn "*muldf_ext1"
2695 [(set (match_operand:DF 0 "register_operand" "=f")
2696 (mult:DF (float_extend:DF
2697 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2698 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2699 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2700 "mul%-%/ %R1,%R2,%0"
2701 [(set_attr "type" "fmul")
2702 (set_attr "trap" "yes")
2703 (set_attr "round_suffix" "normal")
2704 (set_attr "trap_suffix" "u_su_sui")])
2706 (define_insn "*muldf_ext2"
2707 [(set (match_operand:DF 0 "register_operand" "=f")
2708 (mult:DF (float_extend:DF
2709 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2711 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2712 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2713 "mul%-%/ %R1,%R2,%0"
2714 [(set_attr "type" "fmul")
2715 (set_attr "trap" "yes")
2716 (set_attr "round_suffix" "normal")
2717 (set_attr "trap_suffix" "u_su_sui")])
2719 (define_expand "multf3"
2720 [(use (match_operand 0 "register_operand" ""))
2721 (use (match_operand 1 "general_operand" ""))
2722 (use (match_operand 2 "general_operand" ""))]
2723 "TARGET_HAS_XFLOATING_LIBS"
2724 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2726 (define_insn "*subsf3_ieee"
2727 [(set (match_operand:SF 0 "register_operand" "=&f")
2728 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2729 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2730 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2731 "sub%,%/ %R1,%R2,%0"
2732 [(set_attr "type" "fadd")
2733 (set_attr "trap" "yes")
2734 (set_attr "round_suffix" "normal")
2735 (set_attr "trap_suffix" "u_su_sui")])
2737 (define_insn "subsf3"
2738 [(set (match_operand:SF 0 "register_operand" "=f")
2739 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2740 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2742 "sub%,%/ %R1,%R2,%0"
2743 [(set_attr "type" "fadd")
2744 (set_attr "trap" "yes")
2745 (set_attr "round_suffix" "normal")
2746 (set_attr "trap_suffix" "u_su_sui")])
2748 (define_insn "*subdf3_ieee"
2749 [(set (match_operand:DF 0 "register_operand" "=&f")
2750 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2751 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2752 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2753 "sub%-%/ %R1,%R2,%0"
2754 [(set_attr "type" "fadd")
2755 (set_attr "trap" "yes")
2756 (set_attr "round_suffix" "normal")
2757 (set_attr "trap_suffix" "u_su_sui")])
2759 (define_insn "subdf3"
2760 [(set (match_operand:DF 0 "register_operand" "=f")
2761 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2762 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2764 "sub%-%/ %R1,%R2,%0"
2765 [(set_attr "type" "fadd")
2766 (set_attr "trap" "yes")
2767 (set_attr "round_suffix" "normal")
2768 (set_attr "trap_suffix" "u_su_sui")])
2770 (define_insn "*subdf_ext1"
2771 [(set (match_operand:DF 0 "register_operand" "=f")
2772 (minus:DF (float_extend:DF
2773 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2774 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2775 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2776 "sub%-%/ %R1,%R2,%0"
2777 [(set_attr "type" "fadd")
2778 (set_attr "trap" "yes")
2779 (set_attr "round_suffix" "normal")
2780 (set_attr "trap_suffix" "u_su_sui")])
2782 (define_insn "*subdf_ext2"
2783 [(set (match_operand:DF 0 "register_operand" "=f")
2784 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2786 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2787 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2788 "sub%-%/ %R1,%R2,%0"
2789 [(set_attr "type" "fadd")
2790 (set_attr "trap" "yes")
2791 (set_attr "round_suffix" "normal")
2792 (set_attr "trap_suffix" "u_su_sui")])
2794 (define_insn "*subdf_ext3"
2795 [(set (match_operand:DF 0 "register_operand" "=f")
2796 (minus:DF (float_extend:DF
2797 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2799 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2800 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2801 "sub%-%/ %R1,%R2,%0"
2802 [(set_attr "type" "fadd")
2803 (set_attr "trap" "yes")
2804 (set_attr "round_suffix" "normal")
2805 (set_attr "trap_suffix" "u_su_sui")])
2807 (define_expand "subtf3"
2808 [(use (match_operand 0 "register_operand" ""))
2809 (use (match_operand 1 "general_operand" ""))
2810 (use (match_operand 2 "general_operand" ""))]
2811 "TARGET_HAS_XFLOATING_LIBS"
2812 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2814 (define_insn "*sqrtsf2_ieee"
2815 [(set (match_operand:SF 0 "register_operand" "=&f")
2816 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2817 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2819 [(set_attr "type" "fsqrt")
2820 (set_attr "opsize" "si")
2821 (set_attr "trap" "yes")
2822 (set_attr "round_suffix" "normal")
2823 (set_attr "trap_suffix" "u_su_sui")])
2825 (define_insn "sqrtsf2"
2826 [(set (match_operand:SF 0 "register_operand" "=f")
2827 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2828 "TARGET_FP && TARGET_FIX"
2830 [(set_attr "type" "fsqrt")
2831 (set_attr "opsize" "si")
2832 (set_attr "trap" "yes")
2833 (set_attr "round_suffix" "normal")
2834 (set_attr "trap_suffix" "u_su_sui")])
2836 (define_insn "*sqrtdf2_ieee"
2837 [(set (match_operand:DF 0 "register_operand" "=&f")
2838 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2839 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2841 [(set_attr "type" "fsqrt")
2842 (set_attr "trap" "yes")
2843 (set_attr "round_suffix" "normal")
2844 (set_attr "trap_suffix" "u_su_sui")])
2846 (define_insn "sqrtdf2"
2847 [(set (match_operand:DF 0 "register_operand" "=f")
2848 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2849 "TARGET_FP && TARGET_FIX"
2851 [(set_attr "type" "fsqrt")
2852 (set_attr "trap" "yes")
2853 (set_attr "round_suffix" "normal")
2854 (set_attr "trap_suffix" "u_su_sui")])
2856 ;; Next are all the integer comparisons, and conditional moves and branches
2857 ;; and some of the related define_expand's and define_split's.
2859 (define_insn "*setcc_internal"
2860 [(set (match_operand 0 "register_operand" "=r")
2861 (match_operator 1 "alpha_comparison_operator"
2862 [(match_operand:DI 2 "register_operand" "r")
2863 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2864 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2865 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2866 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2868 [(set_attr "type" "icmp")])
2870 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2871 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2873 (define_insn "*setcc_swapped_internal"
2874 [(set (match_operand 0 "register_operand" "=r")
2875 (match_operator 1 "alpha_swapped_comparison_operator"
2876 [(match_operand:DI 2 "register_operand" "r")
2877 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2878 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2879 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2880 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2882 [(set_attr "type" "icmp")])
2884 ;; Use match_operator rather than ne directly so that we can match
2885 ;; multiple integer modes.
2886 (define_insn "*setne_internal"
2887 [(set (match_operand 0 "register_operand" "=r")
2888 (match_operator 1 "signed_comparison_operator"
2889 [(match_operand:DI 2 "register_operand" "r")
2891 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2892 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2893 && GET_CODE (operands[1]) == NE
2894 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2896 [(set_attr "type" "icmp")])
2898 ;; The mode folding trick can't be used with const_int operands, since
2899 ;; reload needs to know the proper mode.
2901 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2902 ;; in order to create more pairs of constants. As long as we're allowing
2903 ;; two constants at the same time, and will have to reload one of them...
2905 (define_insn "*movqicc_internal"
2906 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2908 (match_operator 2 "signed_comparison_operator"
2909 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2910 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2911 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2912 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2913 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2919 [(set_attr "type" "icmov")])
2921 (define_insn "*movhicc_internal"
2922 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2924 (match_operator 2 "signed_comparison_operator"
2925 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2926 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2927 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2928 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2929 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2935 [(set_attr "type" "icmov")])
2937 (define_insn "*movsicc_internal"
2938 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2940 (match_operator 2 "signed_comparison_operator"
2941 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2942 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2943 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2944 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2945 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2951 [(set_attr "type" "icmov")])
2953 (define_insn "*movdicc_internal"
2954 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2956 (match_operator 2 "signed_comparison_operator"
2957 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2958 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2959 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2960 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2961 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2967 [(set_attr "type" "icmov")])
2969 (define_insn "*movqicc_lbc"
2970 [(set (match_operand:QI 0 "register_operand" "=r,r")
2972 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2976 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2977 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2982 [(set_attr "type" "icmov")])
2984 (define_insn "*movhicc_lbc"
2985 [(set (match_operand:HI 0 "register_operand" "=r,r")
2987 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2991 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2992 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2997 [(set_attr "type" "icmov")])
2999 (define_insn "*movsicc_lbc"
3000 [(set (match_operand:SI 0 "register_operand" "=r,r")
3002 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3006 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3007 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3012 [(set_attr "type" "icmov")])
3014 (define_insn "*movdicc_lbc"
3015 [(set (match_operand:DI 0 "register_operand" "=r,r")
3017 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3021 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3022 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3027 [(set_attr "type" "icmov")])
3029 (define_insn "*movqicc_lbs"
3030 [(set (match_operand:QI 0 "register_operand" "=r,r")
3032 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3036 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3037 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3042 [(set_attr "type" "icmov")])
3044 (define_insn "*movhicc_lbs"
3045 [(set (match_operand:HI 0 "register_operand" "=r,r")
3047 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3051 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3052 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3057 [(set_attr "type" "icmov")])
3059 (define_insn "*movsicc_lbs"
3060 [(set (match_operand:SI 0 "register_operand" "=r,r")
3062 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3066 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3067 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3072 [(set_attr "type" "icmov")])
3074 (define_insn "*movdicc_lbs"
3075 [(set (match_operand:DI 0 "register_operand" "=r,r")
3077 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3081 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3082 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3087 [(set_attr "type" "icmov")])
3089 ;; For ABS, we have two choices, depending on whether the input and output
3090 ;; registers are the same or not.
3091 (define_expand "absdi2"
3092 [(set (match_operand:DI 0 "register_operand" "")
3093 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3096 if (rtx_equal_p (operands[0], operands[1]))
3097 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3099 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3103 (define_expand "absdi2_same"
3104 [(set (match_operand:DI 1 "register_operand" "")
3105 (neg:DI (match_operand:DI 0 "register_operand" "")))
3107 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3113 (define_expand "absdi2_diff"
3114 [(set (match_operand:DI 0 "register_operand" "")
3115 (neg:DI (match_operand:DI 1 "register_operand" "")))
3117 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3124 [(set (match_operand:DI 0 "register_operand" "")
3125 (abs:DI (match_dup 0)))
3126 (clobber (match_operand:DI 1 "register_operand" ""))]
3128 [(set (match_dup 1) (neg:DI (match_dup 0)))
3129 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3130 (match_dup 0) (match_dup 1)))]
3134 [(set (match_operand:DI 0 "register_operand" "")
3135 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3136 "! rtx_equal_p (operands[0], operands[1])"
3137 [(set (match_dup 0) (neg:DI (match_dup 1)))
3138 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3139 (match_dup 0) (match_dup 1)))]
3143 [(set (match_operand:DI 0 "register_operand" "")
3144 (neg:DI (abs:DI (match_dup 0))))
3145 (clobber (match_operand:DI 1 "register_operand" ""))]
3147 [(set (match_dup 1) (neg:DI (match_dup 0)))
3148 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3149 (match_dup 0) (match_dup 1)))]
3153 [(set (match_operand:DI 0 "register_operand" "")
3154 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3155 "! rtx_equal_p (operands[0], operands[1])"
3156 [(set (match_dup 0) (neg:DI (match_dup 1)))
3157 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3158 (match_dup 0) (match_dup 1)))]
3161 (define_insn "sminqi3"
3162 [(set (match_operand:QI 0 "register_operand" "=r")
3163 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3164 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3167 [(set_attr "type" "mvi")])
3169 (define_insn "uminqi3"
3170 [(set (match_operand:QI 0 "register_operand" "=r")
3171 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3172 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3175 [(set_attr "type" "mvi")])
3177 (define_insn "smaxqi3"
3178 [(set (match_operand:QI 0 "register_operand" "=r")
3179 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3180 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3183 [(set_attr "type" "mvi")])
3185 (define_insn "umaxqi3"
3186 [(set (match_operand:QI 0 "register_operand" "=r")
3187 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3188 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3191 [(set_attr "type" "mvi")])
3193 (define_insn "sminhi3"
3194 [(set (match_operand:HI 0 "register_operand" "=r")
3195 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3196 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3199 [(set_attr "type" "mvi")])
3201 (define_insn "uminhi3"
3202 [(set (match_operand:HI 0 "register_operand" "=r")
3203 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3204 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3207 [(set_attr "type" "mvi")])
3209 (define_insn "smaxhi3"
3210 [(set (match_operand:HI 0 "register_operand" "=r")
3211 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3212 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3215 [(set_attr "type" "mvi")])
3217 (define_insn "umaxhi3"
3218 [(set (match_operand:HI 0 "register_operand" "=r")
3219 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3220 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3223 [(set_attr "type" "shift")])
3225 (define_expand "smaxdi3"
3227 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3228 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3229 (set (match_operand:DI 0 "register_operand" "")
3230 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3231 (match_dup 1) (match_dup 2)))]
3233 { operands[3] = gen_reg_rtx (DImode); })
3236 [(set (match_operand:DI 0 "register_operand" "")
3237 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3238 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3239 (clobber (match_operand:DI 3 "register_operand" ""))]
3240 "operands[2] != const0_rtx"
3241 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3242 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3243 (match_dup 1) (match_dup 2)))]
3246 (define_insn "*smax_const0"
3247 [(set (match_operand:DI 0 "register_operand" "=r")
3248 (smax:DI (match_operand:DI 1 "register_operand" "0")
3252 [(set_attr "type" "icmov")])
3254 (define_expand "smindi3"
3256 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3257 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3258 (set (match_operand:DI 0 "register_operand" "")
3259 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3260 (match_dup 1) (match_dup 2)))]
3262 { operands[3] = gen_reg_rtx (DImode); })
3265 [(set (match_operand:DI 0 "register_operand" "")
3266 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3267 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3268 (clobber (match_operand:DI 3 "register_operand" ""))]
3269 "operands[2] != const0_rtx"
3270 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3271 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3272 (match_dup 1) (match_dup 2)))]
3275 (define_insn "*smin_const0"
3276 [(set (match_operand:DI 0 "register_operand" "=r")
3277 (smin:DI (match_operand:DI 1 "register_operand" "0")
3281 [(set_attr "type" "icmov")])
3283 (define_expand "umaxdi3"
3285 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3286 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3287 (set (match_operand:DI 0 "register_operand" "")
3288 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3289 (match_dup 1) (match_dup 2)))]
3291 "operands[3] = gen_reg_rtx (DImode);")
3294 [(set (match_operand:DI 0 "register_operand" "")
3295 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3296 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3297 (clobber (match_operand:DI 3 "register_operand" ""))]
3298 "operands[2] != const0_rtx"
3299 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3300 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3301 (match_dup 1) (match_dup 2)))]
3304 (define_expand "umindi3"
3306 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3307 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3308 (set (match_operand:DI 0 "register_operand" "")
3309 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3310 (match_dup 1) (match_dup 2)))]
3312 "operands[3] = gen_reg_rtx (DImode);")
3315 [(set (match_operand:DI 0 "register_operand" "")
3316 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3317 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3318 (clobber (match_operand:DI 3 "register_operand" ""))]
3319 "operands[2] != const0_rtx"
3320 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3321 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3322 (match_dup 1) (match_dup 2)))]
3325 (define_insn "*bcc_normal"
3328 (match_operator 1 "signed_comparison_operator"
3329 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3331 (label_ref (match_operand 0 "" ""))
3335 [(set_attr "type" "ibr")])
3337 (define_insn "*bcc_reverse"
3340 (match_operator 1 "signed_comparison_operator"
3341 [(match_operand:DI 2 "register_operand" "r")
3345 (label_ref (match_operand 0 "" ""))))]
3348 [(set_attr "type" "ibr")])
3350 (define_insn "*blbs_normal"
3353 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3357 (label_ref (match_operand 0 "" ""))
3361 [(set_attr "type" "ibr")])
3363 (define_insn "*blbc_normal"
3366 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3370 (label_ref (match_operand 0 "" ""))
3374 [(set_attr "type" "ibr")])
3380 (match_operator 1 "comparison_operator"
3381 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3383 (match_operand:DI 3 "const_int_operand" ""))
3385 (label_ref (match_operand 0 "" ""))
3387 (clobber (match_operand:DI 4 "register_operand" ""))])]
3388 "INTVAL (operands[3]) != 0"
3390 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3392 (if_then_else (match_op_dup 1
3393 [(zero_extract:DI (match_dup 4)
3397 (label_ref (match_dup 0))
3401 ;; The following are the corresponding floating-point insns. Recall
3402 ;; we need to have variants that expand the arguments from SFmode
3405 (define_insn "*cmpdf_ieee"
3406 [(set (match_operand:DF 0 "register_operand" "=&f")
3407 (match_operator:DF 1 "alpha_fp_comparison_operator"
3408 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3409 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3410 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3411 "cmp%-%C1%/ %R2,%R3,%0"
3412 [(set_attr "type" "fadd")
3413 (set_attr "trap" "yes")
3414 (set_attr "trap_suffix" "su")])
3416 (define_insn "*cmpdf_internal"
3417 [(set (match_operand:DF 0 "register_operand" "=f")
3418 (match_operator:DF 1 "alpha_fp_comparison_operator"
3419 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3420 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3421 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3422 "cmp%-%C1%/ %R2,%R3,%0"
3423 [(set_attr "type" "fadd")
3424 (set_attr "trap" "yes")
3425 (set_attr "trap_suffix" "su")])
3427 (define_insn "*cmpdf_ieee_ext1"
3428 [(set (match_operand:DF 0 "register_operand" "=&f")
3429 (match_operator:DF 1 "alpha_fp_comparison_operator"
3431 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3432 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3433 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3434 "cmp%-%C1%/ %R2,%R3,%0"
3435 [(set_attr "type" "fadd")
3436 (set_attr "trap" "yes")
3437 (set_attr "trap_suffix" "su")])
3439 (define_insn "*cmpdf_ext1"
3440 [(set (match_operand:DF 0 "register_operand" "=f")
3441 (match_operator:DF 1 "alpha_fp_comparison_operator"
3443 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3444 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3445 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3446 "cmp%-%C1%/ %R2,%R3,%0"
3447 [(set_attr "type" "fadd")
3448 (set_attr "trap" "yes")
3449 (set_attr "trap_suffix" "su")])
3451 (define_insn "*cmpdf_ieee_ext2"
3452 [(set (match_operand:DF 0 "register_operand" "=&f")
3453 (match_operator:DF 1 "alpha_fp_comparison_operator"
3454 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3456 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3457 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3458 "cmp%-%C1%/ %R2,%R3,%0"
3459 [(set_attr "type" "fadd")
3460 (set_attr "trap" "yes")
3461 (set_attr "trap_suffix" "su")])
3463 (define_insn "*cmpdf_ext2"
3464 [(set (match_operand:DF 0 "register_operand" "=f")
3465 (match_operator:DF 1 "alpha_fp_comparison_operator"
3466 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3468 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3469 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3470 "cmp%-%C1%/ %R2,%R3,%0"
3471 [(set_attr "type" "fadd")
3472 (set_attr "trap" "yes")
3473 (set_attr "trap_suffix" "su")])
3475 (define_insn "*cmpdf_ieee_ext3"
3476 [(set (match_operand:DF 0 "register_operand" "=&f")
3477 (match_operator:DF 1 "alpha_fp_comparison_operator"
3479 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3481 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3482 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3483 "cmp%-%C1%/ %R2,%R3,%0"
3484 [(set_attr "type" "fadd")
3485 (set_attr "trap" "yes")
3486 (set_attr "trap_suffix" "su")])
3488 (define_insn "*cmpdf_ext3"
3489 [(set (match_operand:DF 0 "register_operand" "=f")
3490 (match_operator:DF 1 "alpha_fp_comparison_operator"
3492 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3494 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3495 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3496 "cmp%-%C1%/ %R2,%R3,%0"
3497 [(set_attr "type" "fadd")
3498 (set_attr "trap" "yes")
3499 (set_attr "trap_suffix" "su")])
3501 (define_insn "*movdfcc_internal"
3502 [(set (match_operand:DF 0 "register_operand" "=f,f")
3504 (match_operator 3 "signed_comparison_operator"
3505 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3506 (match_operand:DF 2 "const0_operand" "G,G")])
3507 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3508 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3512 fcmov%D3 %R4,%R5,%0"
3513 [(set_attr "type" "fcmov")])
3515 (define_insn "*movsfcc_internal"
3516 [(set (match_operand:SF 0 "register_operand" "=f,f")
3518 (match_operator 3 "signed_comparison_operator"
3519 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3520 (match_operand:DF 2 "const0_operand" "G,G")])
3521 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3522 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3526 fcmov%D3 %R4,%R5,%0"
3527 [(set_attr "type" "fcmov")])
3529 (define_insn "*movdfcc_ext1"
3530 [(set (match_operand:DF 0 "register_operand" "=f,f")
3532 (match_operator 3 "signed_comparison_operator"
3533 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3534 (match_operand:DF 2 "const0_operand" "G,G")])
3535 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3536 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3540 fcmov%D3 %R4,%R5,%0"
3541 [(set_attr "type" "fcmov")])
3543 (define_insn "*movdfcc_ext2"
3544 [(set (match_operand:DF 0 "register_operand" "=f,f")
3546 (match_operator 3 "signed_comparison_operator"
3548 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3549 (match_operand:DF 2 "const0_operand" "G,G")])
3550 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3551 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3555 fcmov%D3 %R4,%R5,%0"
3556 [(set_attr "type" "fcmov")])
3558 (define_insn "*movdfcc_ext3"
3559 [(set (match_operand:SF 0 "register_operand" "=f,f")
3561 (match_operator 3 "signed_comparison_operator"
3563 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3564 (match_operand:DF 2 "const0_operand" "G,G")])
3565 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3566 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3570 fcmov%D3 %R4,%R5,%0"
3571 [(set_attr "type" "fcmov")])
3573 (define_insn "*movdfcc_ext4"
3574 [(set (match_operand:DF 0 "register_operand" "=f,f")
3576 (match_operator 3 "signed_comparison_operator"
3578 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3579 (match_operand:DF 2 "const0_operand" "G,G")])
3580 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3581 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3585 fcmov%D3 %R4,%R5,%0"
3586 [(set_attr "type" "fcmov")])
3588 (define_expand "maxdf3"
3590 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3591 (match_operand:DF 2 "reg_or_0_operand" "")))
3592 (set (match_operand:DF 0 "register_operand" "")
3593 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3594 (match_dup 1) (match_dup 2)))]
3597 operands[3] = gen_reg_rtx (DFmode);
3598 operands[4] = CONST0_RTX (DFmode);
3601 (define_expand "mindf3"
3603 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3604 (match_operand:DF 2 "reg_or_0_operand" "")))
3605 (set (match_operand:DF 0 "register_operand" "")
3606 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3607 (match_dup 1) (match_dup 2)))]
3610 operands[3] = gen_reg_rtx (DFmode);
3611 operands[4] = CONST0_RTX (DFmode);
3614 (define_expand "maxsf3"
3616 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3617 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3618 (set (match_operand:SF 0 "register_operand" "")
3619 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3620 (match_dup 1) (match_dup 2)))]
3623 operands[3] = gen_reg_rtx (DFmode);
3624 operands[4] = CONST0_RTX (DFmode);
3627 (define_expand "minsf3"
3629 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3630 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3631 (set (match_operand:SF 0 "register_operand" "")
3632 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3633 (match_dup 1) (match_dup 2)))]
3636 operands[3] = gen_reg_rtx (DFmode);
3637 operands[4] = CONST0_RTX (DFmode);
3640 (define_insn "*fbcc_normal"
3643 (match_operator 1 "signed_comparison_operator"
3644 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3645 (match_operand:DF 3 "const0_operand" "G")])
3646 (label_ref (match_operand 0 "" ""))
3650 [(set_attr "type" "fbr")])
3652 (define_insn "*fbcc_ext_normal"
3655 (match_operator 1 "signed_comparison_operator"
3657 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3658 (match_operand:DF 3 "const0_operand" "G")])
3659 (label_ref (match_operand 0 "" ""))
3663 [(set_attr "type" "fbr")])
3665 ;; These are the main define_expand's used to make conditional branches
3668 (define_expand "cmpdf"
3669 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3670 (match_operand:DF 1 "reg_or_0_operand" "")))]
3673 alpha_compare.op0 = operands[0];
3674 alpha_compare.op1 = operands[1];
3675 alpha_compare.fp_p = 1;
3679 (define_expand "cmptf"
3680 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3681 (match_operand:TF 1 "general_operand" "")))]
3682 "TARGET_HAS_XFLOATING_LIBS"
3684 alpha_compare.op0 = operands[0];
3685 alpha_compare.op1 = operands[1];
3686 alpha_compare.fp_p = 1;
3690 (define_expand "cmpdi"
3691 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3692 (match_operand:DI 1 "general_operand" "")))]
3695 alpha_compare.op0 = operands[0];
3696 alpha_compare.op1 = operands[1];
3697 alpha_compare.fp_p = 0;
3701 (define_expand "beq"
3703 (if_then_else (match_dup 1)
3704 (label_ref (match_operand 0 "" ""))
3707 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3709 (define_expand "bne"
3711 (if_then_else (match_dup 1)
3712 (label_ref (match_operand 0 "" ""))
3715 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3717 (define_expand "blt"
3719 (if_then_else (match_dup 1)
3720 (label_ref (match_operand 0 "" ""))
3723 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3725 (define_expand "ble"
3727 (if_then_else (match_dup 1)
3728 (label_ref (match_operand 0 "" ""))
3731 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3733 (define_expand "bgt"
3735 (if_then_else (match_dup 1)
3736 (label_ref (match_operand 0 "" ""))
3739 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3741 (define_expand "bge"
3743 (if_then_else (match_dup 1)
3744 (label_ref (match_operand 0 "" ""))
3747 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3749 (define_expand "bltu"
3751 (if_then_else (match_dup 1)
3752 (label_ref (match_operand 0 "" ""))
3755 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3757 (define_expand "bleu"
3759 (if_then_else (match_dup 1)
3760 (label_ref (match_operand 0 "" ""))
3763 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3765 (define_expand "bgtu"
3767 (if_then_else (match_dup 1)
3768 (label_ref (match_operand 0 "" ""))
3771 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3773 (define_expand "bgeu"
3775 (if_then_else (match_dup 1)
3776 (label_ref (match_operand 0 "" ""))
3779 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3781 (define_expand "bunordered"
3783 (if_then_else (match_dup 1)
3784 (label_ref (match_operand 0 "" ""))
3787 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3789 (define_expand "bordered"
3791 (if_then_else (match_dup 1)
3792 (label_ref (match_operand 0 "" ""))
3795 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3797 (define_expand "seq"
3798 [(set (match_operand:DI 0 "register_operand" "")
3801 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3803 (define_expand "sne"
3804 [(set (match_operand:DI 0 "register_operand" "")
3807 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3809 (define_expand "slt"
3810 [(set (match_operand:DI 0 "register_operand" "")
3813 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3815 (define_expand "sle"
3816 [(set (match_operand:DI 0 "register_operand" "")
3819 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3821 (define_expand "sgt"
3822 [(set (match_operand:DI 0 "register_operand" "")
3825 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3827 (define_expand "sge"
3828 [(set (match_operand:DI 0 "register_operand" "")
3831 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3833 (define_expand "sltu"
3834 [(set (match_operand:DI 0 "register_operand" "")
3837 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3839 (define_expand "sleu"
3840 [(set (match_operand:DI 0 "register_operand" "")
3843 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3845 (define_expand "sgtu"
3846 [(set (match_operand:DI 0 "register_operand" "")
3849 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3851 (define_expand "sgeu"
3852 [(set (match_operand:DI 0 "register_operand" "")
3855 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3857 (define_expand "sunordered"
3858 [(set (match_operand:DI 0 "register_operand" "")
3861 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3863 (define_expand "sordered"
3864 [(set (match_operand:DI 0 "register_operand" "")
3867 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3869 ;; These are the main define_expand's used to make conditional moves.
3871 (define_expand "movsicc"
3872 [(set (match_operand:SI 0 "register_operand" "")
3873 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3874 (match_operand:SI 2 "reg_or_8bit_operand" "")
3875 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3878 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3882 (define_expand "movdicc"
3883 [(set (match_operand:DI 0 "register_operand" "")
3884 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3885 (match_operand:DI 2 "reg_or_8bit_operand" "")
3886 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3889 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3893 (define_expand "movsfcc"
3894 [(set (match_operand:SF 0 "register_operand" "")
3895 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3896 (match_operand:SF 2 "reg_or_8bit_operand" "")
3897 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3900 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3904 (define_expand "movdfcc"
3905 [(set (match_operand:DF 0 "register_operand" "")
3906 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3907 (match_operand:DF 2 "reg_or_8bit_operand" "")
3908 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3911 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3915 ;; These define_split definitions are used in cases when comparisons have
3916 ;; not be stated in the correct way and we need to reverse the second
3917 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3918 ;; comparison that tests the result being reversed. We have one define_split
3919 ;; for each use of a comparison. They do not match valid insns and need
3920 ;; not generate valid insns.
3922 ;; We can also handle equality comparisons (and inequality comparisons in
3923 ;; cases where the resulting add cannot overflow) by doing an add followed by
3924 ;; a comparison with zero. This is faster since the addition takes one
3925 ;; less cycle than a compare when feeding into a conditional move.
3926 ;; For this case, we also have an SImode pattern since we can merge the add
3927 ;; and sign extend and the order doesn't matter.
3929 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3930 ;; operation could have been generated.
3933 [(set (match_operand:DI 0 "register_operand" "")
3935 (match_operator 1 "comparison_operator"
3936 [(match_operand:DI 2 "reg_or_0_operand" "")
3937 (match_operand:DI 3 "reg_or_cint_operand" "")])
3938 (match_operand:DI 4 "reg_or_cint_operand" "")
3939 (match_operand:DI 5 "reg_or_cint_operand" "")))
3940 (clobber (match_operand:DI 6 "register_operand" ""))]
3941 "operands[3] != const0_rtx"
3942 [(set (match_dup 6) (match_dup 7))
3944 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3946 enum rtx_code code = GET_CODE (operands[1]);
3947 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3949 /* If we are comparing for equality with a constant and that constant
3950 appears in the arm when the register equals the constant, use the
3951 register since that is more likely to match (and to produce better code
3954 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3955 && rtx_equal_p (operands[4], operands[3]))
3956 operands[4] = operands[2];
3958 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3959 && rtx_equal_p (operands[5], operands[3]))
3960 operands[5] = operands[2];
3962 if (code == NE || code == EQ
3963 || (extended_count (operands[2], DImode, unsignedp) >= 1
3964 && extended_count (operands[3], DImode, unsignedp) >= 1))
3966 if (GET_CODE (operands[3]) == CONST_INT)
3967 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3968 GEN_INT (- INTVAL (operands[3])));
3970 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3972 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3975 else if (code == EQ || code == LE || code == LT
3976 || code == LEU || code == LTU)
3978 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3979 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3983 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3984 operands[2], operands[3]);
3985 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3990 [(set (match_operand:DI 0 "register_operand" "")
3992 (match_operator 1 "comparison_operator"
3993 [(match_operand:SI 2 "reg_or_0_operand" "")
3994 (match_operand:SI 3 "reg_or_cint_operand" "")])
3995 (match_operand:DI 4 "reg_or_8bit_operand" "")
3996 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3997 (clobber (match_operand:DI 6 "register_operand" ""))]
3998 "operands[3] != const0_rtx
3999 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4000 [(set (match_dup 6) (match_dup 7))
4002 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4004 enum rtx_code code = GET_CODE (operands[1]);
4005 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4008 if ((code != NE && code != EQ
4009 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4010 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4013 if (GET_CODE (operands[3]) == CONST_INT)
4014 tem = gen_rtx_PLUS (SImode, operands[2],
4015 GEN_INT (- INTVAL (operands[3])));
4017 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4019 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4020 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4021 operands[6], const0_rtx);
4027 (match_operator 1 "comparison_operator"
4028 [(match_operand:DI 2 "reg_or_0_operand" "")
4029 (match_operand:DI 3 "reg_or_cint_operand" "")])
4030 (label_ref (match_operand 0 "" ""))
4032 (clobber (match_operand:DI 4 "register_operand" ""))]
4033 "operands[3] != const0_rtx"
4034 [(set (match_dup 4) (match_dup 5))
4035 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4037 enum rtx_code code = GET_CODE (operands[1]);
4038 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4040 if (code == NE || code == EQ
4041 || (extended_count (operands[2], DImode, unsignedp) >= 1
4042 && extended_count (operands[3], DImode, unsignedp) >= 1))
4044 if (GET_CODE (operands[3]) == CONST_INT)
4045 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4046 GEN_INT (- INTVAL (operands[3])));
4048 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4050 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4053 else if (code == EQ || code == LE || code == LT
4054 || code == LEU || code == LTU)
4056 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4057 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4061 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4062 operands[2], operands[3]);
4063 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4070 (match_operator 1 "comparison_operator"
4071 [(match_operand:SI 2 "reg_or_0_operand" "")
4072 (match_operand:SI 3 "const_int_operand" "")])
4073 (label_ref (match_operand 0 "" ""))
4075 (clobber (match_operand:DI 4 "register_operand" ""))]
4076 "operands[3] != const0_rtx
4077 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4078 [(set (match_dup 4) (match_dup 5))
4079 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4083 if (GET_CODE (operands[3]) == CONST_INT)
4084 tem = gen_rtx_PLUS (SImode, operands[2],
4085 GEN_INT (- INTVAL (operands[3])));
4087 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4089 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4090 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4091 operands[4], const0_rtx);
4094 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4095 ;; This eliminates one, and sometimes two, insns when the AND can be done
4098 [(set (match_operand:DI 0 "register_operand" "")
4099 (match_operator:DI 1 "comparison_operator"
4100 [(match_operand:DI 2 "register_operand" "")
4101 (match_operand:DI 3 "const_int_operand" "")]))
4102 (clobber (match_operand:DI 4 "register_operand" ""))]
4103 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4104 && (GET_CODE (operands[1]) == GTU
4105 || GET_CODE (operands[1]) == LEU
4106 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4107 && extended_count (operands[2], DImode, 1) > 0))"
4108 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4109 (set (match_dup 0) (match_dup 6))]
4111 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4112 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4113 || GET_CODE (operands[1]) == GT)
4115 DImode, operands[4], const0_rtx);
4118 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4121 [(set (match_operand 0 "register_operand" "")
4122 (if_then_else (match_operator 1 "signed_comparison_operator"
4123 [(match_operand:DI 2 "reg_or_0_operand" "")
4125 (match_operand 3 "const_int_operand" "")
4126 (match_operand 4 "const_int_operand" "")))]
4130 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4131 operands[2], operands[3], operands[4]))
4137 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4138 ;; Oh well, we match it in movcc, so it must be partially our fault.
4140 [(set (match_operand 0 "register_operand" "")
4141 (if_then_else (match_operator 1 "signed_comparison_operator"
4143 (match_operand:DI 2 "reg_or_0_operand" "")])
4144 (match_operand 3 "const_int_operand" "")
4145 (match_operand 4 "const_int_operand" "")))]
4149 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4150 operands[0], operands[2], operands[3],
4157 (define_insn_and_split "*cmp_sadd_di"
4158 [(set (match_operand:DI 0 "register_operand" "=r")
4159 (plus:DI (if_then_else:DI
4160 (match_operator 1 "alpha_zero_comparison_operator"
4161 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4163 (match_operand:DI 3 "const48_operand" "I")
4165 (match_operand:DI 4 "sext_add_operand" "rIO")))
4166 (clobber (match_scratch:DI 5 "=r"))]
4169 "! no_new_pseudos || reload_completed"
4171 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4173 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4176 if (! no_new_pseudos)
4177 operands[5] = gen_reg_rtx (DImode);
4178 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4179 operands[5] = operands[0];
4182 (define_insn_and_split "*cmp_sadd_si"
4183 [(set (match_operand:SI 0 "register_operand" "=r")
4184 (plus:SI (if_then_else:SI
4185 (match_operator 1 "alpha_zero_comparison_operator"
4186 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4188 (match_operand:SI 3 "const48_operand" "I")
4190 (match_operand:SI 4 "sext_add_operand" "rIO")))
4191 (clobber (match_scratch:SI 5 "=r"))]
4194 "! no_new_pseudos || reload_completed"
4196 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4198 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4201 if (! no_new_pseudos)
4202 operands[5] = gen_reg_rtx (DImode);
4203 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4204 operands[5] = operands[0];
4207 (define_insn_and_split "*cmp_sadd_sidi"
4208 [(set (match_operand:DI 0 "register_operand" "=r")
4210 (plus:SI (if_then_else:SI
4211 (match_operator 1 "alpha_zero_comparison_operator"
4212 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4214 (match_operand:SI 3 "const48_operand" "I")
4216 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4217 (clobber (match_scratch:SI 5 "=r"))]
4220 "! no_new_pseudos || reload_completed"
4222 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4224 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4227 if (! no_new_pseudos)
4228 operands[5] = gen_reg_rtx (DImode);
4229 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4230 operands[5] = operands[0];
4233 (define_insn_and_split "*cmp_ssub_di"
4234 [(set (match_operand:DI 0 "register_operand" "=r")
4235 (minus:DI (if_then_else:DI
4236 (match_operator 1 "alpha_zero_comparison_operator"
4237 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4239 (match_operand:DI 3 "const48_operand" "I")
4241 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4242 (clobber (match_scratch:DI 5 "=r"))]
4245 "! no_new_pseudos || reload_completed"
4247 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4249 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4252 if (! no_new_pseudos)
4253 operands[5] = gen_reg_rtx (DImode);
4254 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4255 operands[5] = operands[0];
4258 (define_insn_and_split "*cmp_ssub_si"
4259 [(set (match_operand:SI 0 "register_operand" "=r")
4260 (minus:SI (if_then_else:SI
4261 (match_operator 1 "alpha_zero_comparison_operator"
4262 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4264 (match_operand:SI 3 "const48_operand" "I")
4266 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4267 (clobber (match_scratch:SI 5 "=r"))]
4270 "! no_new_pseudos || reload_completed"
4272 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4274 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4277 if (! no_new_pseudos)
4278 operands[5] = gen_reg_rtx (DImode);
4279 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4280 operands[5] = operands[0];
4283 (define_insn_and_split "*cmp_ssub_sidi"
4284 [(set (match_operand:DI 0 "register_operand" "=r")
4286 (minus:SI (if_then_else:SI
4287 (match_operator 1 "alpha_zero_comparison_operator"
4288 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4290 (match_operand:SI 3 "const48_operand" "I")
4292 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4293 (clobber (match_scratch:SI 5 "=r"))]
4296 "! no_new_pseudos || reload_completed"
4298 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4300 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4303 if (! no_new_pseudos)
4304 operands[5] = gen_reg_rtx (DImode);
4305 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4306 operands[5] = operands[0];
4309 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4310 ;; work differently, so we have different patterns for each.
4312 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4313 ;; call. The CIW contains information about arguments passed in registers
4314 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4315 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4316 ;; in the presence of inlining since the CIWs for calls performed by the
4317 ;; inlined function must be stored in the SSIB of the function it is inlined
4318 ;; into as well. We encode the CIW in an unspec and append it to the list
4319 ;; of the CIWs for the current function only when the instruction for loading
4320 ;; $25 is generated.
4322 (define_expand "call"
4323 [(use (match_operand:DI 0 "" ""))
4324 (use (match_operand 1 "" ""))
4325 (use (match_operand 2 "" ""))
4326 (use (match_operand 3 "" ""))]
4329 if (TARGET_ABI_WINDOWS_NT)
4330 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4331 else if (TARGET_ABI_OPEN_VMS)
4332 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4333 else if (TARGET_ABI_UNICOSMK)
4334 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4336 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4340 (define_expand "sibcall"
4341 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4342 (match_operand 1 "" ""))
4343 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4346 if (GET_CODE (operands[0]) != MEM)
4348 operands[0] = XEXP (operands[0], 0);
4351 (define_expand "call_osf"
4352 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4353 (match_operand 1 "" ""))
4355 (clobber (reg:DI 26))])]
4358 if (GET_CODE (operands[0]) != MEM)
4361 operands[0] = XEXP (operands[0], 0);
4362 if (! call_operand (operands[0], Pmode))
4363 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4366 (define_expand "call_nt"
4367 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4368 (match_operand 1 "" ""))
4369 (clobber (reg:DI 26))])]
4372 if (GET_CODE (operands[0]) != MEM)
4375 operands[0] = XEXP (operands[0], 0);
4376 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4377 operands[0] = force_reg (DImode, operands[0]);
4380 ;; Calls on Unicos/Mk are always indirect.
4381 ;; op 0: symbol ref for called function
4382 ;; op 1: CIW for $25 represented by an unspec
4384 (define_expand "call_umk"
4385 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4386 (match_operand 1 "" ""))
4388 (clobber (reg:DI 26))])]
4391 if (GET_CODE (operands[0]) != MEM)
4394 /* Always load the address of the called function into a register;
4395 load the CIW in $25. */
4397 operands[0] = XEXP (operands[0], 0);
4398 if (GET_CODE (operands[0]) != REG)
4399 operands[0] = force_reg (DImode, operands[0]);
4401 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4405 ;; call openvms/alpha
4406 ;; op 0: symbol ref for called function
4407 ;; op 1: next_arg_reg (argument information value for R25)
4409 (define_expand "call_vms"
4410 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4411 (match_operand 1 "" ""))
4415 (clobber (reg:DI 27))])]
4418 if (GET_CODE (operands[0]) != MEM)
4421 operands[0] = XEXP (operands[0], 0);
4423 /* Always load AI with argument information, then handle symbolic and
4424 indirect call differently. Load RA and set operands[2] to PV in
4427 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4428 if (GET_CODE (operands[0]) == SYMBOL_REF)
4430 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4432 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4434 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4438 emit_move_insn (gen_rtx_REG (Pmode, 26),
4439 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4440 operands[2] = operands[0];
4445 (define_expand "call_value"
4446 [(use (match_operand 0 "" ""))
4447 (use (match_operand:DI 1 "" ""))
4448 (use (match_operand 2 "" ""))
4449 (use (match_operand 3 "" ""))
4450 (use (match_operand 4 "" ""))]
4453 if (TARGET_ABI_WINDOWS_NT)
4454 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4455 else if (TARGET_ABI_OPEN_VMS)
4456 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4458 else if (TARGET_ABI_UNICOSMK)
4459 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4462 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4467 (define_expand "sibcall_value"
4468 [(parallel [(set (match_operand 0 "" "")
4469 (call (mem:DI (match_operand 1 "" ""))
4470 (match_operand 2 "" "")))
4471 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4474 if (GET_CODE (operands[1]) != MEM)
4476 operands[1] = XEXP (operands[1], 0);
4479 (define_expand "call_value_osf"
4480 [(parallel [(set (match_operand 0 "" "")
4481 (call (mem:DI (match_operand 1 "" ""))
4482 (match_operand 2 "" "")))
4484 (clobber (reg:DI 26))])]
4487 if (GET_CODE (operands[1]) != MEM)
4490 operands[1] = XEXP (operands[1], 0);
4491 if (! call_operand (operands[1], Pmode))
4492 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4495 (define_expand "call_value_nt"
4496 [(parallel [(set (match_operand 0 "" "")
4497 (call (mem:DI (match_operand 1 "" ""))
4498 (match_operand 2 "" "")))
4499 (clobber (reg:DI 26))])]
4502 if (GET_CODE (operands[1]) != MEM)
4505 operands[1] = XEXP (operands[1], 0);
4506 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4507 operands[1] = force_reg (DImode, operands[1]);
4510 (define_expand "call_value_vms"
4511 [(parallel [(set (match_operand 0 "" "")
4512 (call (mem:DI (match_operand:DI 1 "" ""))
4513 (match_operand 2 "" "")))
4517 (clobber (reg:DI 27))])]
4520 if (GET_CODE (operands[1]) != MEM)
4523 operands[1] = XEXP (operands[1], 0);
4525 /* Always load AI with argument information, then handle symbolic and
4526 indirect call differently. Load RA and set operands[3] to PV in
4529 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4530 if (GET_CODE (operands[1]) == SYMBOL_REF)
4532 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4534 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4536 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4540 emit_move_insn (gen_rtx_REG (Pmode, 26),
4541 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4542 operands[3] = operands[1];
4546 (define_expand "call_value_umk"
4547 [(parallel [(set (match_operand 0 "" "")
4548 (call (mem:DI (match_operand 1 "" ""))
4549 (match_operand 2 "" "")))
4551 (clobber (reg:DI 26))])]
4554 if (GET_CODE (operands[1]) != MEM)
4557 operands[1] = XEXP (operands[1], 0);
4558 if (GET_CODE (operands[1]) != REG)
4559 operands[1] = force_reg (DImode, operands[1]);
4561 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4564 (define_insn "*call_osf_1_er"
4565 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4566 (match_operand 1 "" ""))
4568 (clobber (reg:DI 26))]
4569 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4571 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4573 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4574 [(set_attr "type" "jsr")
4575 (set_attr "length" "12,*,16")])
4577 ;; We must use peep2 instead of a split because we need accurate life
4578 ;; information for $gp. Consider the case of { bar(); while (1); }.
4580 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4581 (match_operand 1 "" ""))
4583 (clobber (reg:DI 26))])]
4584 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4585 && ! current_file_function_operand (operands[0], Pmode)
4586 && peep2_regno_dead_p (1, 29)"
4587 [(parallel [(call (mem:DI (match_dup 2))
4589 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4590 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4592 (use (match_dup 3))])]
4594 if (CONSTANT_P (operands[0]))
4596 operands[2] = gen_rtx_REG (Pmode, 27);
4597 operands[3] = GEN_INT (alpha_next_sequence_number++);
4598 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4599 operands[0], operands[3]));
4603 operands[2] = operands[0];
4604 operands[0] = const0_rtx;
4605 operands[3] = const0_rtx;
4610 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4611 (match_operand 1 "" ""))
4613 (clobber (reg:DI 26))])]
4614 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4615 && ! current_file_function_operand (operands[0], Pmode)
4616 && ! peep2_regno_dead_p (1, 29)"
4617 [(parallel [(call (mem:DI (match_dup 2))
4619 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4620 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4622 (use (match_dup 4))])
4624 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4626 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4628 if (CONSTANT_P (operands[0]))
4630 operands[2] = gen_rtx_REG (Pmode, 27);
4631 operands[4] = GEN_INT (alpha_next_sequence_number++);
4632 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4633 operands[0], operands[4]));
4637 operands[2] = operands[0];
4638 operands[0] = const0_rtx;
4639 operands[4] = const0_rtx;
4641 operands[3] = GEN_INT (alpha_next_sequence_number++);
4644 ;; We add a blockage unspec_volatile to prevent insns from moving down
4645 ;; from above the call to in between the call and the ldah gpdisp.
4647 (define_insn "*call_osf_2_er"
4648 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4649 (match_operand 1 "" ""))
4650 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4651 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4652 (use (match_operand 2 "" ""))
4653 (use (match_operand 3 "const_int_operand" ""))]
4654 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4655 "jsr $26,(%0),%2%J3"
4656 [(set_attr "type" "jsr")])
4658 (define_insn "*call_osf_1_noreturn"
4659 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4660 (match_operand 1 "" ""))
4662 (clobber (reg:DI 26))]
4663 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4664 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4669 [(set_attr "type" "jsr")
4670 (set_attr "length" "*,*,8")])
4672 (define_insn "*call_osf_1"
4673 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4674 (match_operand 1 "" ""))
4676 (clobber (reg:DI 26))]
4677 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4679 jsr $26,($27),0\;ldgp $29,0($26)
4681 jsr $26,%0\;ldgp $29,0($26)"
4682 [(set_attr "type" "jsr")
4683 (set_attr "length" "12,*,16")])
4685 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4686 ;; doesn't do what we want.
4687 (define_insn "*sibcall_osf_1_er"
4688 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4689 (match_operand 1 "" ""))
4690 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4691 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4694 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4695 [(set_attr "type" "jsr")
4696 (set_attr "length" "*,8")])
4698 (define_insn "*sibcall_osf_1"
4699 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4700 (match_operand 1 "" ""))
4701 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4702 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4705 lda $27,%0\;jmp $31,($27),%0"
4706 [(set_attr "type" "jsr")
4707 (set_attr "length" "*,8")])
4709 (define_insn "*call_nt_1"
4710 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4711 (match_operand 1 "" ""))
4712 (clobber (reg:DI 26))]
4713 "TARGET_ABI_WINDOWS_NT"
4718 [(set_attr "type" "jsr")
4719 (set_attr "length" "*,*,12")])
4721 (define_insn "*call_vms_1"
4722 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4723 (match_operand 1 "" ""))
4724 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4727 (clobber (reg:DI 27))]
4728 "TARGET_ABI_OPEN_VMS"
4730 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4731 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4732 [(set_attr "type" "jsr")
4733 (set_attr "length" "12,16")])
4735 (define_insn "*call_umk_1"
4736 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4737 (match_operand 1 "" ""))
4739 (clobber (reg:DI 26))]
4740 "TARGET_ABI_UNICOSMK"
4742 [(set_attr "type" "jsr")])
4744 ;; Call subroutine returning any type.
4746 (define_expand "untyped_call"
4747 [(parallel [(call (match_operand 0 "" "")
4749 (match_operand 1 "" "")
4750 (match_operand 2 "" "")])]
4755 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4757 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4759 rtx set = XVECEXP (operands[2], 0, i);
4760 emit_move_insn (SET_DEST (set), SET_SRC (set));
4763 /* The optimizer does not know that the call sets the function value
4764 registers we stored in the result block. We avoid problems by
4765 claiming that all hard registers are used and clobbered at this
4767 emit_insn (gen_blockage ());
4772 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4773 ;; all of memory. This blocks insns from being moved across this point.
4775 (define_insn "blockage"
4776 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4779 [(set_attr "length" "0")
4780 (set_attr "type" "none")])
4784 (label_ref (match_operand 0 "" "")))]
4787 [(set_attr "type" "ibr")])
4789 (define_expand "return"
4794 (define_insn "*return_internal"
4798 [(set_attr "type" "ibr")])
4800 (define_insn "indirect_jump"
4801 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4804 [(set_attr "type" "ibr")])
4806 (define_expand "tablejump"
4807 [(parallel [(set (pc)
4808 (match_operand 0 "register_operand" ""))
4809 (use (label_ref:DI (match_operand 1 "" "")))])]
4812 if (TARGET_ABI_WINDOWS_NT)
4814 rtx dest = gen_reg_rtx (DImode);
4815 emit_insn (gen_extendsidi2 (dest, operands[0]));
4818 else if (TARGET_ABI_OSF)
4820 rtx dest = gen_reg_rtx (DImode);
4821 emit_insn (gen_extendsidi2 (dest, operands[0]));
4822 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4827 (define_insn "*tablejump_osf_nt_internal"
4829 (match_operand:DI 0 "register_operand" "r"))
4830 (use (label_ref:DI (match_operand 1 "" "")))]
4831 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4832 && alpha_tablejump_addr_vec (insn)"
4834 operands[2] = alpha_tablejump_best_label (insn);
4835 return "jmp $31,(%0),%2";
4837 [(set_attr "type" "ibr")])
4839 (define_insn "*tablejump_internal"
4841 (match_operand:DI 0 "register_operand" "r"))
4842 (use (label_ref (match_operand 1 "" "")))]
4845 [(set_attr "type" "ibr")])
4847 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4848 ;; want to have to include pal.h in our .s file.
4850 ;; Technically the type for call_pal is jsr, but we use that for determining
4851 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4854 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4857 [(set_attr "type" "ibr")])
4859 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4860 ;; NT does not document anything at 0x81 -- presumably it would generate
4861 ;; the equivalent of SIGILL, but this isn't that important.
4862 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4864 [(trap_if (const_int 1) (const_int 0))]
4865 "!TARGET_ABI_WINDOWS_NT"
4867 [(set_attr "type" "ibr")])
4869 ;; For userland, we load the thread pointer from the TCB.
4870 ;; For the kernel, we load the per-cpu private value.
4872 (define_insn "load_tp"
4873 [(set (match_operand:DI 0 "register_operand" "=v")
4874 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4877 if (TARGET_TLS_KERNEL)
4878 return "call_pal 0x32";
4880 return "call_pal 0x9e";
4882 [(set_attr "type" "ibr")])
4884 ;; For completeness, and possibly a __builtin function, here's how to
4885 ;; set the thread pointer. Since we don't describe enough of this
4886 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4887 ;; not much point in creating an R16_REG register class.
4889 (define_expand "set_tp"
4890 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4891 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4895 (define_insn "*set_tp"
4896 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4899 if (TARGET_TLS_KERNEL)
4900 return "call_pal 0x31";
4902 return "call_pal 0x9f";
4904 [(set_attr "type" "ibr")])
4906 ;; Finally, we have the basic data motion insns. The byte and word insns
4907 ;; are done via define_expand. Start with the floating-point insns, since
4908 ;; they are simpler.
4910 (define_insn "*movsf_nofix"
4911 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4912 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4913 "TARGET_FPREGS && ! TARGET_FIX
4914 && (register_operand (operands[0], SFmode)
4915 || reg_or_0_operand (operands[1], SFmode))"
4923 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4925 (define_insn "*movsf_fix"
4926 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4927 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4928 "TARGET_FPREGS && TARGET_FIX
4929 && (register_operand (operands[0], SFmode)
4930 || reg_or_0_operand (operands[1], SFmode))"
4940 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4942 (define_insn "*movsf_nofp"
4943 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4944 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4946 && (register_operand (operands[0], SFmode)
4947 || reg_or_0_operand (operands[1], SFmode))"
4952 [(set_attr "type" "ilog,ild,ist")])
4954 (define_insn "*movdf_nofix"
4955 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4956 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4957 "TARGET_FPREGS && ! TARGET_FIX
4958 && (register_operand (operands[0], DFmode)
4959 || reg_or_0_operand (operands[1], DFmode))"
4967 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4969 (define_insn "*movdf_fix"
4970 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4971 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4972 "TARGET_FPREGS && TARGET_FIX
4973 && (register_operand (operands[0], DFmode)
4974 || reg_or_0_operand (operands[1], DFmode))"
4984 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4986 (define_insn "*movdf_nofp"
4987 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4988 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4990 && (register_operand (operands[0], DFmode)
4991 || reg_or_0_operand (operands[1], DFmode))"
4996 [(set_attr "type" "ilog,ild,ist")])
4998 ;; Subregs suck for register allocation. Pretend we can move TFmode
4999 ;; data between general registers until after reload.
5001 (define_insn_and_split "*movtf_internal"
5002 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5003 (match_operand:TF 1 "input_operand" "roG,rG"))]
5004 "register_operand (operands[0], TFmode)
5005 || reg_or_0_operand (operands[1], TFmode)"
5008 [(set (match_dup 0) (match_dup 2))
5009 (set (match_dup 1) (match_dup 3))]
5011 alpha_split_tfmode_pair (operands);
5012 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5015 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5016 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5020 (define_expand "movsf"
5021 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5022 (match_operand:SF 1 "general_operand" ""))]
5025 if (GET_CODE (operands[0]) == MEM
5026 && ! reg_or_0_operand (operands[1], SFmode))
5027 operands[1] = force_reg (SFmode, operands[1]);
5030 (define_expand "movdf"
5031 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5032 (match_operand:DF 1 "general_operand" ""))]
5035 if (GET_CODE (operands[0]) == MEM
5036 && ! reg_or_0_operand (operands[1], DFmode))
5037 operands[1] = force_reg (DFmode, operands[1]);
5040 (define_expand "movtf"
5041 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5042 (match_operand:TF 1 "general_operand" ""))]
5045 if (GET_CODE (operands[0]) == MEM
5046 && ! reg_or_0_operand (operands[1], TFmode))
5047 operands[1] = force_reg (TFmode, operands[1]);
5050 (define_insn "*movsi_nofix"
5051 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5052 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5053 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5054 && (register_operand (operands[0], SImode)
5055 || reg_or_0_operand (operands[1], SImode))"
5065 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5067 (define_insn "*movsi_fix"
5068 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5069 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5070 "TARGET_ABI_OSF && TARGET_FIX
5071 && (register_operand (operands[0], SImode)
5072 || reg_or_0_operand (operands[1], SImode))"
5084 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5086 (define_insn "*movsi_nt_vms_nofix"
5087 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5088 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5089 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5091 && (register_operand (operands[0], SImode)
5092 || reg_or_0_operand (operands[1], SImode))"
5103 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5105 (define_insn "*movsi_nt_vms_fix"
5106 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5107 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5108 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5110 && (register_operand (operands[0], SImode)
5111 || reg_or_0_operand (operands[1], SImode))"
5124 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5126 (define_insn "*movhi_nobwx"
5127 [(set (match_operand:HI 0 "register_operand" "=r,r")
5128 (match_operand:HI 1 "input_operand" "rJ,n"))]
5130 && (register_operand (operands[0], HImode)
5131 || register_operand (operands[1], HImode))"
5135 [(set_attr "type" "ilog,iadd")])
5137 (define_insn "*movhi_bwx"
5138 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5139 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5141 && (register_operand (operands[0], HImode)
5142 || reg_or_0_operand (operands[1], HImode))"
5148 [(set_attr "type" "ilog,iadd,ild,ist")])
5150 (define_insn "*movqi_nobwx"
5151 [(set (match_operand:QI 0 "register_operand" "=r,r")
5152 (match_operand:QI 1 "input_operand" "rJ,n"))]
5154 && (register_operand (operands[0], QImode)
5155 || register_operand (operands[1], QImode))"
5159 [(set_attr "type" "ilog,iadd")])
5161 (define_insn "*movqi_bwx"
5162 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5163 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5165 && (register_operand (operands[0], QImode)
5166 || reg_or_0_operand (operands[1], QImode))"
5172 [(set_attr "type" "ilog,iadd,ild,ist")])
5174 ;; We do two major things here: handle mem->mem and construct long
5177 (define_expand "movsi"
5178 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5179 (match_operand:SI 1 "general_operand" ""))]
5182 if (alpha_expand_mov (SImode, operands))
5186 ;; Split a load of a large constant into the appropriate two-insn
5190 [(set (match_operand:SI 0 "register_operand" "")
5191 (match_operand:SI 1 "const_int_operand" ""))]
5192 "! add_operand (operands[1], SImode)"
5193 [(set (match_dup 0) (match_dup 2))
5194 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5197 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5199 if (tem == operands[0])
5205 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5206 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5207 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5208 ;; notes and update LABEL_NUSES because this is not done automatically.
5209 ;; Labels may be incorrectly deleted if we don't do this.
5211 ;; Describing what the individual instructions do correctly is too complicated
5212 ;; so use UNSPECs for each of the three parts of an address.
5215 [(set (match_operand:DI 0 "register_operand" "")
5216 (match_operand:DI 1 "symbolic_operand" ""))]
5217 "TARGET_ABI_UNICOSMK && reload_completed"
5220 rtx insn1, insn2, insn3;
5222 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5223 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5224 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5225 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5226 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5228 if (GET_CODE (operands[1]) == LABEL_REF)
5232 label = XEXP (operands[1], 0);
5233 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5235 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5237 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5239 LABEL_NUSES (label) += 3;
5244 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5246 (define_insn "umk_laum"
5247 [(set (match_operand:DI 0 "register_operand" "=r")
5248 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5250 "TARGET_ABI_UNICOSMK"
5252 [(set_attr "type" "iadd")])
5254 (define_insn "umk_lalm"
5255 [(set (match_operand:DI 0 "register_operand" "=r")
5256 (plus:DI (match_operand:DI 1 "register_operand" "r")
5257 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5259 "TARGET_ABI_UNICOSMK"
5261 [(set_attr "type" "iadd")])
5263 (define_insn "umk_lal"
5264 [(set (match_operand:DI 0 "register_operand" "=r")
5265 (plus:DI (match_operand:DI 1 "register_operand" "r")
5266 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5268 "TARGET_ABI_UNICOSMK"
5270 [(set_attr "type" "iadd")])
5272 ;; Add a new call information word to the current function's list of CIWs
5273 ;; and load its index into $25. Doing it here ensures that the CIW will be
5274 ;; associated with the correct function even in the presence of inlining.
5276 (define_insn "*umk_load_ciw"
5278 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5279 "TARGET_ABI_UNICOSMK"
5281 operands[0] = unicosmk_add_call_info_word (operands[0]);
5282 return "lda $25,%0";
5284 [(set_attr "type" "iadd")])
5286 (define_insn "*movdi_er_low_l"
5287 [(set (match_operand:DI 0 "register_operand" "=r")
5288 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5289 (match_operand:DI 2 "local_symbolic_operand" "")))]
5290 "TARGET_EXPLICIT_RELOCS"
5292 if (true_regnum (operands[1]) == 29)
5293 return "lda %0,%2(%1)\t\t!gprel";
5295 return "lda %0,%2(%1)\t\t!gprellow";
5299 [(set (match_operand:DI 0 "register_operand" "")
5300 (match_operand:DI 1 "small_symbolic_operand" ""))]
5301 "TARGET_EXPLICIT_RELOCS && reload_completed"
5303 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5304 "operands[2] = pic_offset_table_rtx;")
5307 [(set (match_operand:DI 0 "register_operand" "")
5308 (match_operand:DI 1 "local_symbolic_operand" ""))]
5309 "TARGET_EXPLICIT_RELOCS && reload_completed"
5311 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5313 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5314 "operands[2] = pic_offset_table_rtx;")
5317 [(match_operand 0 "some_small_symbolic_operand" "")]
5318 "TARGET_EXPLICIT_RELOCS && reload_completed"
5320 "operands[0] = split_small_symbolic_operand (operands[0]);")
5322 (define_insn "movdi_er_high_g"
5323 [(set (match_operand:DI 0 "register_operand" "=r")
5324 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5325 (match_operand:DI 2 "global_symbolic_operand" "")
5326 (match_operand 3 "const_int_operand" "")]
5328 "TARGET_EXPLICIT_RELOCS"
5330 if (INTVAL (operands[3]) == 0)
5331 return "ldq %0,%2(%1)\t\t!literal";
5333 return "ldq %0,%2(%1)\t\t!literal!%3";
5335 [(set_attr "type" "ldsym")])
5338 [(set (match_operand:DI 0 "register_operand" "")
5339 (match_operand:DI 1 "global_symbolic_operand" ""))]
5340 "TARGET_EXPLICIT_RELOCS && reload_completed"
5342 (unspec:DI [(match_dup 2)
5344 (const_int 0)] UNSPEC_LITERAL))]
5345 "operands[2] = pic_offset_table_rtx;")
5347 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5348 ;; compiled at the end of compilation. In the meantime, someone can
5349 ;; re-encode-section-info on some symbol changing it e.g. from global
5350 ;; to local-not-small. If this happens, we'd have emitted a plain
5351 ;; load rather than a high+losum load and not recognize the insn.
5353 ;; So if rtl inlining is in effect, we delay the global/not-global
5354 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5356 (define_insn_and_split "movdi_er_maybe_g"
5357 [(set (match_operand:DI 0 "register_operand" "=r")
5358 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5360 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5363 [(set (match_dup 0) (match_dup 1))]
5365 if (local_symbolic_operand (operands[1], Pmode)
5366 && !small_symbolic_operand (operands[1], Pmode))
5368 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5371 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5372 if (reload_completed)
5373 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5374 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5376 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5377 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5382 (define_insn "movdi_er_tlsgd"
5383 [(set (match_operand:DI 0 "register_operand" "=r")
5384 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5385 (match_operand:DI 2 "symbolic_operand" "")
5386 (match_operand 3 "const_int_operand" "")]
5390 if (INTVAL (operands[3]) == 0)
5391 return "lda %0,%2(%1)\t\t!tlsgd";
5393 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5396 (define_insn "movdi_er_tlsldm"
5397 [(set (match_operand:DI 0 "register_operand" "=r")
5398 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5399 (match_operand 2 "const_int_operand" "")]
5403 if (INTVAL (operands[2]) == 0)
5404 return "lda %0,%&(%1)\t\t!tlsldm";
5406 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5409 (define_insn "*movdi_er_gotdtp"
5410 [(set (match_operand:DI 0 "register_operand" "=r")
5411 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5412 (match_operand:DI 2 "symbolic_operand" "")]
5415 "ldq %0,%2(%1)\t\t!gotdtprel"
5416 [(set_attr "type" "ild")])
5419 [(set (match_operand:DI 0 "register_operand" "")
5420 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5421 "HAVE_AS_TLS && reload_completed"
5423 (unspec:DI [(match_dup 2)
5424 (match_dup 1)] UNSPEC_DTPREL))]
5426 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5427 operands[2] = pic_offset_table_rtx;
5430 (define_insn "*movdi_er_gottp"
5431 [(set (match_operand:DI 0 "register_operand" "=r")
5432 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5433 (match_operand:DI 2 "symbolic_operand" "")]
5436 "ldq %0,%2(%1)\t\t!gottprel"
5437 [(set_attr "type" "ild")])
5440 [(set (match_operand:DI 0 "register_operand" "")
5441 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5442 "HAVE_AS_TLS && reload_completed"
5444 (unspec:DI [(match_dup 2)
5445 (match_dup 1)] UNSPEC_TPREL))]
5447 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5448 operands[2] = pic_offset_table_rtx;
5451 (define_insn "*movdi_er_nofix"
5452 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5453 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5454 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5455 && (register_operand (operands[0], DImode)
5456 || reg_or_0_operand (operands[1], DImode))"
5468 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5470 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5471 ;; have been split up by the rules above but we shouldn't reject the
5472 ;; possibility of them getting through.
5474 (define_insn "*movdi_nofix"
5475 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5476 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5478 && (register_operand (operands[0], DImode)
5479 || reg_or_0_operand (operands[1], DImode))"
5484 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5491 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5492 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5494 (define_insn "*movdi_er_fix"
5495 [(set (match_operand:DI 0 "nonimmediate_operand"
5496 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5497 (match_operand:DI 1 "input_operand"
5498 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5499 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5500 && (register_operand (operands[0], DImode)
5501 || reg_or_0_operand (operands[1], DImode))"
5515 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5517 (define_insn "*movdi_fix"
5518 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5519 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5520 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5521 && (register_operand (operands[0], DImode)
5522 || reg_or_0_operand (operands[1], DImode))"
5535 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5537 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5538 ;; often appears dead to the life analysis code, at which point we
5539 ;; abort for emitting dead prologue instructions. Force this live.
5541 (define_insn "force_movdi"
5542 [(set (match_operand:DI 0 "register_operand" "=r")
5543 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5544 UNSPECV_FORCE_MOV))]
5547 [(set_attr "type" "ilog")])
5549 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5550 ;; memory, and construct long 32-bit constants.
5552 (define_expand "movdi"
5553 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5554 (match_operand:DI 1 "general_operand" ""))]
5557 if (alpha_expand_mov (DImode, operands))
5561 ;; Split a load of a large constant into the appropriate two-insn
5565 [(set (match_operand:DI 0 "register_operand" "")
5566 (match_operand:DI 1 "const_int_operand" ""))]
5567 "! add_operand (operands[1], DImode)"
5568 [(set (match_dup 0) (match_dup 2))
5569 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5572 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5574 if (tem == operands[0])
5580 ;; These are the partial-word cases.
5582 ;; First we have the code to load an aligned word. Operand 0 is the register
5583 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5584 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5585 ;; number of bits within the word that the value is. Operand 3 is an SImode
5586 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5587 ;; same register. It is allowed to conflict with operand 1 as well.
5589 (define_expand "aligned_loadqi"
5590 [(set (match_operand:SI 3 "register_operand" "")
5591 (match_operand:SI 1 "memory_operand" ""))
5592 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5593 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5595 (match_operand:DI 2 "const_int_operand" "")))]
5600 (define_expand "aligned_loadhi"
5601 [(set (match_operand:SI 3 "register_operand" "")
5602 (match_operand:SI 1 "memory_operand" ""))
5603 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5604 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5606 (match_operand:DI 2 "const_int_operand" "")))]
5611 ;; Similar for unaligned loads, where we use the sequence from the
5612 ;; Alpha Architecture manual. We have to distinguish between little-endian
5613 ;; and big-endian systems as the sequences are different.
5615 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5616 ;; operand 3 can overlap the input and output registers.
5618 (define_expand "unaligned_loadqi"
5619 [(use (match_operand:QI 0 "register_operand" ""))
5620 (use (match_operand:DI 1 "address_operand" ""))
5621 (use (match_operand:DI 2 "register_operand" ""))
5622 (use (match_operand:DI 3 "register_operand" ""))]
5625 if (WORDS_BIG_ENDIAN)
5626 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5627 operands[2], operands[3]));
5629 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5630 operands[2], operands[3]));
5634 (define_expand "unaligned_loadqi_le"
5635 [(set (match_operand:DI 2 "register_operand" "")
5636 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5638 (set (match_operand:DI 3 "register_operand" "")
5640 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5641 (zero_extract:DI (match_dup 2)
5643 (ashift:DI (match_dup 3) (const_int 3))))]
5644 "! WORDS_BIG_ENDIAN"
5647 (define_expand "unaligned_loadqi_be"
5648 [(set (match_operand:DI 2 "register_operand" "")
5649 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5651 (set (match_operand:DI 3 "register_operand" "")
5653 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5654 (zero_extract:DI (match_dup 2)
5658 (ashift:DI (match_dup 3) (const_int 3)))))]
5662 (define_expand "unaligned_loadhi"
5663 [(use (match_operand:QI 0 "register_operand" ""))
5664 (use (match_operand:DI 1 "address_operand" ""))
5665 (use (match_operand:DI 2 "register_operand" ""))
5666 (use (match_operand:DI 3 "register_operand" ""))]
5669 if (WORDS_BIG_ENDIAN)
5670 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5671 operands[2], operands[3]));
5673 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5674 operands[2], operands[3]));
5678 (define_expand "unaligned_loadhi_le"
5679 [(set (match_operand:DI 2 "register_operand" "")
5680 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5682 (set (match_operand:DI 3 "register_operand" "")
5684 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5685 (zero_extract:DI (match_dup 2)
5687 (ashift:DI (match_dup 3) (const_int 3))))]
5688 "! WORDS_BIG_ENDIAN"
5691 (define_expand "unaligned_loadhi_be"
5692 [(set (match_operand:DI 2 "register_operand" "")
5693 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5695 (set (match_operand:DI 3 "register_operand" "")
5696 (plus:DI (match_dup 1) (const_int 1)))
5697 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5698 (zero_extract:DI (match_dup 2)
5702 (ashift:DI (match_dup 3) (const_int 3)))))]
5706 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5707 ;; aligned SImode MEM. Operand 1 is the register containing the
5708 ;; byte or word to store. Operand 2 is the number of bits within the word that
5709 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5711 (define_expand "aligned_store"
5712 [(set (match_operand:SI 3 "register_operand" "")
5713 (match_operand:SI 0 "memory_operand" ""))
5714 (set (subreg:DI (match_dup 3) 0)
5715 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5716 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5717 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5718 (match_operand:DI 2 "const_int_operand" "")))
5719 (set (subreg:DI (match_dup 4) 0)
5720 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5721 (set (match_dup 0) (match_dup 4))]
5724 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5725 << INTVAL (operands[2])));
5728 ;; For the unaligned byte and halfword cases, we use code similar to that
5729 ;; in the ;; Architecture book, but reordered to lower the number of registers
5730 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5731 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5732 ;; be the same temporary, if desired. If the address is in a register,
5733 ;; operand 2 can be that register.
5735 (define_expand "unaligned_storeqi"
5736 [(use (match_operand:DI 0 "address_operand" ""))
5737 (use (match_operand:QI 1 "register_operand" ""))
5738 (use (match_operand:DI 2 "register_operand" ""))
5739 (use (match_operand:DI 3 "register_operand" ""))
5740 (use (match_operand:DI 4 "register_operand" ""))]
5743 if (WORDS_BIG_ENDIAN)
5744 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5745 operands[2], operands[3],
5748 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5749 operands[2], operands[3],
5754 (define_expand "unaligned_storeqi_le"
5755 [(set (match_operand:DI 3 "register_operand" "")
5756 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5758 (set (match_operand:DI 2 "register_operand" "")
5761 (and:DI (not:DI (ashift:DI (const_int 255)
5762 (ashift:DI (match_dup 2) (const_int 3))))
5764 (set (match_operand:DI 4 "register_operand" "")
5765 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5766 (ashift:DI (match_dup 2) (const_int 3))))
5767 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5768 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5770 "! WORDS_BIG_ENDIAN"
5773 (define_expand "unaligned_storeqi_be"
5774 [(set (match_operand:DI 3 "register_operand" "")
5775 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5777 (set (match_operand:DI 2 "register_operand" "")
5780 (and:DI (not:DI (ashift:DI (const_int 255)
5781 (minus:DI (const_int 56)
5782 (ashift:DI (match_dup 2) (const_int 3)))))
5784 (set (match_operand:DI 4 "register_operand" "")
5785 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5786 (minus:DI (const_int 56)
5787 (ashift:DI (match_dup 2) (const_int 3)))))
5788 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5789 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5794 (define_expand "unaligned_storehi"
5795 [(use (match_operand:DI 0 "address_operand" ""))
5796 (use (match_operand:HI 1 "register_operand" ""))
5797 (use (match_operand:DI 2 "register_operand" ""))
5798 (use (match_operand:DI 3 "register_operand" ""))
5799 (use (match_operand:DI 4 "register_operand" ""))]
5802 if (WORDS_BIG_ENDIAN)
5803 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5804 operands[2], operands[3],
5807 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5808 operands[2], operands[3],
5813 (define_expand "unaligned_storehi_le"
5814 [(set (match_operand:DI 3 "register_operand" "")
5815 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5817 (set (match_operand:DI 2 "register_operand" "")
5820 (and:DI (not:DI (ashift:DI (const_int 65535)
5821 (ashift:DI (match_dup 2) (const_int 3))))
5823 (set (match_operand:DI 4 "register_operand" "")
5824 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5825 (ashift:DI (match_dup 2) (const_int 3))))
5826 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5827 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5829 "! WORDS_BIG_ENDIAN"
5832 (define_expand "unaligned_storehi_be"
5833 [(set (match_operand:DI 3 "register_operand" "")
5834 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5836 (set (match_operand:DI 2 "register_operand" "")
5837 (plus:DI (match_dup 0) (const_int 1)))
5839 (and:DI (not:DI (ashift:DI
5841 (minus:DI (const_int 56)
5842 (ashift:DI (match_dup 2) (const_int 3)))))
5844 (set (match_operand:DI 4 "register_operand" "")
5845 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5846 (minus:DI (const_int 56)
5847 (ashift:DI (match_dup 2) (const_int 3)))))
5848 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5849 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5854 ;; Here are the define_expand's for QI and HI moves that use the above
5855 ;; patterns. We have the normal sets, plus the ones that need scratch
5856 ;; registers for reload.
5858 (define_expand "movqi"
5859 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5860 (match_operand:QI 1 "general_operand" ""))]
5864 ? alpha_expand_mov (QImode, operands)
5865 : alpha_expand_mov_nobwx (QImode, operands))
5869 (define_expand "movhi"
5870 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5871 (match_operand:HI 1 "general_operand" ""))]
5875 ? alpha_expand_mov (HImode, operands)
5876 : alpha_expand_mov_nobwx (HImode, operands))
5880 ;; Here are the versions for reload. Note that in the unaligned cases
5881 ;; we know that the operand must not be a pseudo-register because stack
5882 ;; slots are always aligned references.
5884 (define_expand "reload_inqi"
5885 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5886 (match_operand:QI 1 "any_memory_operand" "m")
5887 (match_operand:TI 2 "register_operand" "=&r")])]
5892 if (GET_CODE (operands[1]) != MEM)
5895 if (aligned_memory_operand (operands[1], QImode))
5897 seq = gen_reload_inqi_help (operands[0], operands[1],
5898 gen_rtx_REG (SImode, REGNO (operands[2])));
5904 /* It is possible that one of the registers we got for operands[2]
5905 might coincide with that of operands[0] (which is why we made
5906 it TImode). Pick the other one to use as our scratch. */
5907 if (REGNO (operands[0]) == REGNO (operands[2]))
5908 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5910 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5912 addr = get_unaligned_address (operands[1], 0);
5913 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5914 gen_rtx_REG (DImode, REGNO (operands[0])));
5915 alpha_set_memflags (seq, operands[1]);
5921 (define_expand "reload_inhi"
5922 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5923 (match_operand:HI 1 "any_memory_operand" "m")
5924 (match_operand:TI 2 "register_operand" "=&r")])]
5929 if (GET_CODE (operands[1]) != MEM)
5932 if (aligned_memory_operand (operands[1], HImode))
5934 seq = gen_reload_inhi_help (operands[0], operands[1],
5935 gen_rtx_REG (SImode, REGNO (operands[2])));
5941 /* It is possible that one of the registers we got for operands[2]
5942 might coincide with that of operands[0] (which is why we made
5943 it TImode). Pick the other one to use as our scratch. */
5944 if (REGNO (operands[0]) == REGNO (operands[2]))
5945 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5947 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5949 addr = get_unaligned_address (operands[1], 0);
5950 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5951 gen_rtx_REG (DImode, REGNO (operands[0])));
5952 alpha_set_memflags (seq, operands[1]);
5958 (define_expand "reload_outqi"
5959 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5960 (match_operand:QI 1 "register_operand" "r")
5961 (match_operand:TI 2 "register_operand" "=&r")])]
5964 if (GET_CODE (operands[0]) != MEM)
5967 if (aligned_memory_operand (operands[0], QImode))
5969 emit_insn (gen_reload_outqi_help
5970 (operands[0], operands[1],
5971 gen_rtx_REG (SImode, REGNO (operands[2])),
5972 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5976 rtx addr = get_unaligned_address (operands[0], 0);
5977 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5978 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5979 rtx scratch3 = scratch1;
5982 if (GET_CODE (addr) == REG)
5985 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5986 scratch2, scratch3);
5987 alpha_set_memflags (seq, operands[0]);
5993 (define_expand "reload_outhi"
5994 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5995 (match_operand:HI 1 "register_operand" "r")
5996 (match_operand:TI 2 "register_operand" "=&r")])]
5999 if (GET_CODE (operands[0]) != MEM)
6002 if (aligned_memory_operand (operands[0], HImode))
6004 emit_insn (gen_reload_outhi_help
6005 (operands[0], operands[1],
6006 gen_rtx_REG (SImode, REGNO (operands[2])),
6007 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6011 rtx addr = get_unaligned_address (operands[0], 0);
6012 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6013 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6014 rtx scratch3 = scratch1;
6017 if (GET_CODE (addr) == REG)
6020 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6021 scratch2, scratch3);
6022 alpha_set_memflags (seq, operands[0]);
6028 ;; Helpers for the above. The way reload is structured, we can't
6029 ;; always get a proper address for a stack slot during reload_foo
6030 ;; expansion, so we must delay our address manipulations until after.
6032 (define_insn "reload_inqi_help"
6033 [(set (match_operand:QI 0 "register_operand" "=r")
6034 (match_operand:QI 1 "memory_operand" "m"))
6035 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6036 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6039 (define_insn "reload_inhi_help"
6040 [(set (match_operand:HI 0 "register_operand" "=r")
6041 (match_operand:HI 1 "memory_operand" "m"))
6042 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6043 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6046 (define_insn "reload_outqi_help"
6047 [(set (match_operand:QI 0 "memory_operand" "=m")
6048 (match_operand:QI 1 "register_operand" "r"))
6049 (clobber (match_operand:SI 2 "register_operand" "=r"))
6050 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6051 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6054 (define_insn "reload_outhi_help"
6055 [(set (match_operand:HI 0 "memory_operand" "=m")
6056 (match_operand:HI 1 "register_operand" "r"))
6057 (clobber (match_operand:SI 2 "register_operand" "=r"))
6058 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6059 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6063 [(set (match_operand:QI 0 "register_operand" "")
6064 (match_operand:QI 1 "memory_operand" ""))
6065 (clobber (match_operand:SI 2 "register_operand" ""))]
6066 "! TARGET_BWX && reload_completed"
6069 rtx aligned_mem, bitnum;
6070 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6072 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6078 [(set (match_operand:HI 0 "register_operand" "")
6079 (match_operand:HI 1 "memory_operand" ""))
6080 (clobber (match_operand:SI 2 "register_operand" ""))]
6081 "! TARGET_BWX && reload_completed"
6084 rtx aligned_mem, bitnum;
6085 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6087 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6093 [(set (match_operand:QI 0 "memory_operand" "")
6094 (match_operand:QI 1 "register_operand" ""))
6095 (clobber (match_operand:SI 2 "register_operand" ""))
6096 (clobber (match_operand:SI 3 "register_operand" ""))]
6097 "! TARGET_BWX && reload_completed"
6100 rtx aligned_mem, bitnum;
6101 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6102 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6103 operands[2], operands[3]));
6108 [(set (match_operand:HI 0 "memory_operand" "")
6109 (match_operand:HI 1 "register_operand" ""))
6110 (clobber (match_operand:SI 2 "register_operand" ""))
6111 (clobber (match_operand:SI 3 "register_operand" ""))]
6112 "! TARGET_BWX && reload_completed"
6115 rtx aligned_mem, bitnum;
6116 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6117 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6118 operands[2], operands[3]));
6122 ;; Vector operations
6124 (define_expand "movv8qi"
6125 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
6126 (match_operand:V8QI 1 "general_operand" ""))]
6129 if (alpha_expand_mov (V8QImode, operands))
6133 (define_insn "*movv8qi_fix"
6134 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6135 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6137 && (register_operand (operands[0], V8QImode)
6138 || reg_or_0_operand (operands[1], V8QImode))"
6148 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6150 (define_insn "*movv8qi_nofix"
6151 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6152 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6154 && (register_operand (operands[0], V8QImode)
6155 || reg_or_0_operand (operands[1], V8QImode))"
6163 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6165 (define_expand "movv4hi"
6166 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
6167 (match_operand:V4HI 1 "general_operand" ""))]
6170 if (alpha_expand_mov (V4HImode, operands))
6174 (define_insn "*movv4hi_fix"
6175 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6176 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6178 && (register_operand (operands[0], V4HImode)
6179 || reg_or_0_operand (operands[1], V4HImode))"
6189 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6191 (define_insn "*movv4hi_nofix"
6192 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6193 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6195 && (register_operand (operands[0], V4HImode)
6196 || reg_or_0_operand (operands[1], V4HImode))"
6204 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6206 (define_expand "movv2si"
6207 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
6208 (match_operand:V2SI 1 "general_operand" ""))]
6211 if (alpha_expand_mov (V2SImode, operands))
6215 (define_insn "*movv2si_fix"
6216 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6217 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6219 && (register_operand (operands[0], V2SImode)
6220 || reg_or_0_operand (operands[1], V2SImode))"
6230 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6232 (define_insn "*movv2si_nofix"
6233 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6234 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6236 && (register_operand (operands[0], V2SImode)
6237 || reg_or_0_operand (operands[1], V2SImode))"
6245 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6247 (define_insn "uminv8qi3"
6248 [(set (match_operand:V8QI 0 "register_operand" "=r")
6249 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6250 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6253 [(set_attr "type" "mvi")])
6255 (define_insn "sminv8qi3"
6256 [(set (match_operand:V8QI 0 "register_operand" "=r")
6257 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6258 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6261 [(set_attr "type" "mvi")])
6263 (define_insn "uminv4hi3"
6264 [(set (match_operand:V4HI 0 "register_operand" "=r")
6265 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6266 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6269 [(set_attr "type" "mvi")])
6271 (define_insn "sminv4hi3"
6272 [(set (match_operand:V4HI 0 "register_operand" "=r")
6273 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6274 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6277 [(set_attr "type" "mvi")])
6279 (define_insn "umaxv8qi3"
6280 [(set (match_operand:V8QI 0 "register_operand" "=r")
6281 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6282 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6285 [(set_attr "type" "mvi")])
6287 (define_insn "smaxv8qi3"
6288 [(set (match_operand:V8QI 0 "register_operand" "=r")
6289 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6290 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6293 [(set_attr "type" "mvi")])
6295 (define_insn "umaxv4hi3"
6296 [(set (match_operand:V4HI 0 "register_operand" "=r")
6297 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6298 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6301 [(set_attr "type" "mvi")])
6303 (define_insn "smaxv4hi3"
6304 [(set (match_operand:V4HI 0 "register_operand" "=r")
6305 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6306 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6309 [(set_attr "type" "mvi")])
6311 ;; Bit field extract patterns which use ext[wlq][lh]
6313 (define_expand "extv"
6314 [(set (match_operand:DI 0 "register_operand" "")
6315 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6316 (match_operand:DI 2 "immediate_operand" "")
6317 (match_operand:DI 3 "immediate_operand" "")))]
6322 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6323 if (INTVAL (operands[3]) % 8 != 0
6324 || (INTVAL (operands[2]) != 16
6325 && INTVAL (operands[2]) != 32
6326 && INTVAL (operands[2]) != 64))
6329 /* From mips.md: extract_bit_field doesn't verify that our source
6330 matches the predicate, so we force it to be a MEM here. */
6331 if (GET_CODE (operands[1]) != MEM)
6334 /* The bit number is relative to the mode of operand 1 which is
6335 usually QImode (this might actually be a bug in expmed.c). Note
6336 that the bit number is negative in big-endian mode in this case.
6337 We have to convert that to the offset. */
6338 if (WORDS_BIG_ENDIAN)
6339 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6340 - INTVAL (operands[2]) - INTVAL (operands[3]);
6342 ofs = INTVAL (operands[3]);
6346 alpha_expand_unaligned_load (operands[0], operands[1],
6347 INTVAL (operands[2]) / 8,
6352 (define_expand "extzv"
6353 [(set (match_operand:DI 0 "register_operand" "")
6354 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6355 (match_operand:DI 2 "immediate_operand" "")
6356 (match_operand:DI 3 "immediate_operand" "")))]
6359 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6360 if (INTVAL (operands[3]) % 8 != 0
6361 || (INTVAL (operands[2]) != 8
6362 && INTVAL (operands[2]) != 16
6363 && INTVAL (operands[2]) != 32
6364 && INTVAL (operands[2]) != 64))
6367 if (GET_CODE (operands[1]) == MEM)
6371 /* Fail 8 bit fields, falling back on a simple byte load. */
6372 if (INTVAL (operands[2]) == 8)
6375 /* The bit number is relative to the mode of operand 1 which is
6376 usually QImode (this might actually be a bug in expmed.c). Note
6377 that the bit number is negative in big-endian mode in this case.
6378 We have to convert that to the offset. */
6379 if (WORDS_BIG_ENDIAN)
6380 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6381 - INTVAL (operands[2]) - INTVAL (operands[3]);
6383 ofs = INTVAL (operands[3]);
6387 alpha_expand_unaligned_load (operands[0], operands[1],
6388 INTVAL (operands[2]) / 8,
6394 (define_expand "insv"
6395 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6396 (match_operand:DI 1 "immediate_operand" "")
6397 (match_operand:DI 2 "immediate_operand" ""))
6398 (match_operand:DI 3 "register_operand" ""))]
6403 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6404 if (INTVAL (operands[2]) % 8 != 0
6405 || (INTVAL (operands[1]) != 16
6406 && INTVAL (operands[1]) != 32
6407 && INTVAL (operands[1]) != 64))
6410 /* From mips.md: store_bit_field doesn't verify that our source
6411 matches the predicate, so we force it to be a MEM here. */
6412 if (GET_CODE (operands[0]) != MEM)
6415 /* The bit number is relative to the mode of operand 1 which is
6416 usually QImode (this might actually be a bug in expmed.c). Note
6417 that the bit number is negative in big-endian mode in this case.
6418 We have to convert that to the offset. */
6419 if (WORDS_BIG_ENDIAN)
6420 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6421 - INTVAL (operands[1]) - INTVAL (operands[2]);
6423 ofs = INTVAL (operands[2]);
6427 alpha_expand_unaligned_store (operands[0], operands[3],
6428 INTVAL (operands[1]) / 8, ofs);
6432 ;; Block move/clear, see alpha.c for more details.
6433 ;; Argument 0 is the destination
6434 ;; Argument 1 is the source
6435 ;; Argument 2 is the length
6436 ;; Argument 3 is the alignment
6438 (define_expand "movstrqi"
6439 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6440 (match_operand:BLK 1 "memory_operand" ""))
6441 (use (match_operand:DI 2 "immediate_operand" ""))
6442 (use (match_operand:DI 3 "immediate_operand" ""))])]
6445 if (alpha_expand_block_move (operands))
6451 (define_expand "clrstrqi"
6452 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6454 (use (match_operand:DI 1 "immediate_operand" ""))
6455 (use (match_operand:DI 2 "immediate_operand" ""))])]
6458 if (alpha_expand_block_clear (operands))
6464 ;; Subroutine of stack space allocation. Perform a stack probe.
6465 (define_expand "probe_stack"
6466 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6469 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6470 INTVAL (operands[0])));
6471 MEM_VOLATILE_P (operands[1]) = 1;
6473 operands[0] = const0_rtx;
6476 ;; This is how we allocate stack space. If we are allocating a
6477 ;; constant amount of space and we know it is less than 4096
6478 ;; bytes, we need do nothing.
6480 ;; If it is more than 4096 bytes, we need to probe the stack
6482 (define_expand "allocate_stack"
6484 (plus:DI (reg:DI 30)
6485 (match_operand:DI 1 "reg_or_cint_operand" "")))
6486 (set (match_operand:DI 0 "register_operand" "=r")
6490 if (GET_CODE (operands[1]) == CONST_INT
6491 && INTVAL (operands[1]) < 32768)
6493 if (INTVAL (operands[1]) >= 4096)
6495 /* We do this the same way as in the prologue and generate explicit
6496 probes. Then we update the stack by the constant. */
6500 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6501 while (probed + 8192 < INTVAL (operands[1]))
6502 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6504 if (probed + 4096 < INTVAL (operands[1]))
6505 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6508 operands[1] = GEN_INT (- INTVAL (operands[1]));
6509 operands[2] = virtual_stack_dynamic_rtx;
6514 rtx loop_label = gen_label_rtx ();
6515 rtx want = gen_reg_rtx (Pmode);
6516 rtx tmp = gen_reg_rtx (Pmode);
6519 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6520 force_reg (Pmode, operands[1])));
6521 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6523 if (GET_CODE (operands[1]) != CONST_INT)
6525 out_label = gen_label_rtx ();
6526 emit_insn (gen_cmpdi (want, tmp));
6527 emit_jump_insn (gen_bgeu (out_label));
6530 emit_label (loop_label);
6531 memref = gen_rtx_MEM (DImode, tmp);
6532 MEM_VOLATILE_P (memref) = 1;
6533 emit_move_insn (memref, const0_rtx);
6534 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6535 emit_insn (gen_cmpdi (tmp, want));
6536 emit_jump_insn (gen_bgtu (loop_label));
6538 memref = gen_rtx_MEM (DImode, want);
6539 MEM_VOLATILE_P (memref) = 1;
6540 emit_move_insn (memref, const0_rtx);
6543 emit_label (out_label);
6545 emit_move_insn (stack_pointer_rtx, want);
6546 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6551 ;; This is used by alpha_expand_prolog to do the same thing as above,
6552 ;; except we cannot at that time generate new basic blocks, so we hide
6553 ;; the loop in this one insn.
6555 (define_insn "prologue_stack_probe_loop"
6556 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6557 (match_operand:DI 1 "register_operand" "r")]
6561 operands[2] = gen_label_rtx ();
6562 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6563 CODE_LABEL_NUMBER (operands[2]));
6565 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6567 [(set_attr "length" "16")
6568 (set_attr "type" "multi")])
6570 (define_expand "prologue"
6571 [(clobber (const_int 0))]
6574 alpha_expand_prologue ();
6578 ;; These take care of emitting the ldgp insn in the prologue. This will be
6579 ;; an lda/ldah pair and we want to align them properly. So we have two
6580 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6581 ;; and the second of which emits nothing. However, both are marked as type
6582 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6585 (define_expand "prologue_ldgp"
6587 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6589 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6592 operands[0] = pic_offset_table_rtx;
6593 operands[1] = gen_rtx_REG (Pmode, 27);
6594 operands[2] = (TARGET_EXPLICIT_RELOCS
6595 ? GEN_INT (alpha_next_sequence_number++)
6599 (define_insn "*ldgp_er_1"
6600 [(set (match_operand:DI 0 "register_operand" "=r")
6601 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6602 (match_operand 2 "const_int_operand" "")]
6604 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6605 "ldah %0,0(%1)\t\t!gpdisp!%2")
6607 (define_insn "*ldgp_er_2"
6608 [(set (match_operand:DI 0 "register_operand" "=r")
6609 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6610 (match_operand 2 "const_int_operand" "")]
6612 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6613 "lda %0,0(%1)\t\t!gpdisp!%2")
6615 (define_insn "*prologue_ldgp_er_2"
6616 [(set (match_operand:DI 0 "register_operand" "=r")
6617 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6618 (match_operand 2 "const_int_operand" "")]
6620 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6621 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6623 (define_insn "*prologue_ldgp_1"
6624 [(set (match_operand:DI 0 "register_operand" "=r")
6625 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6626 (match_operand 2 "const_int_operand" "")]
6629 "ldgp %0,0(%1)\n$%~..ng:")
6631 (define_insn "*prologue_ldgp_2"
6632 [(set (match_operand:DI 0 "register_operand" "=r")
6633 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6634 (match_operand 2 "const_int_operand" "")]
6639 ;; The _mcount profiling hook has special calling conventions, and
6640 ;; does not clobber all the registers that a normal call would. So
6641 ;; hide the fact this is a call at all.
6643 (define_insn "prologue_mcount"
6644 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6647 if (TARGET_EXPLICIT_RELOCS)
6648 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6649 cannot be called via the PLT. */
6650 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6652 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6654 [(set_attr "type" "multi")
6655 (set_attr "length" "8")])
6657 (define_insn "init_fp"
6658 [(set (match_operand:DI 0 "register_operand" "=r")
6659 (match_operand:DI 1 "register_operand" "r"))
6660 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6664 (define_expand "epilogue"
6668 alpha_expand_epilogue ();
6671 (define_expand "sibcall_epilogue"
6675 alpha_expand_epilogue ();
6679 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6680 ;; the frame size into a register. We use this pattern to ensure
6681 ;; we get lda instead of addq.
6682 (define_insn "nt_lda"
6683 [(set (match_operand:DI 0 "register_operand" "=r")
6684 (unspec:DI [(match_dup 0)
6685 (match_operand:DI 1 "const_int_operand" "n")]
6690 (define_expand "builtin_longjmp"
6691 [(use (match_operand:DI 0 "register_operand" "r"))]
6694 /* The elements of the buffer are, in order: */
6695 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6696 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6697 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6698 rtx pv = gen_rtx_REG (Pmode, 27);
6700 /* This bit is the same as expand_builtin_longjmp. */
6701 emit_move_insn (hard_frame_pointer_rtx, fp);
6702 emit_move_insn (pv, lab);
6703 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6704 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6705 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6707 /* Load the label we are jumping through into $27 so that we know
6708 where to look for it when we get back to setjmp's function for
6709 restoring the gp. */
6710 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6715 ;; This is effectively a copy of indirect_jump, but constrained such
6716 ;; that register renaming cannot foil our cunning plan with $27.
6717 (define_insn "builtin_longjmp_internal"
6719 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6723 [(set_attr "type" "ibr")])
6725 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6726 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6727 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6728 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6730 (define_insn "*builtin_setjmp_receiver_er_1"
6731 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6732 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6733 "br $27,$LSJ%=\n$LSJ%=:"
6734 [(set_attr "type" "ibr")])
6737 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6738 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6739 && prev_nonnote_insn (insn) == operands[0]"
6743 (define_insn "*builtin_setjmp_receiver_1"
6744 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6746 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6747 [(set_attr "length" "12")
6748 (set_attr "type" "multi")])
6750 (define_expand "builtin_setjmp_receiver_er"
6751 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6753 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6755 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6758 operands[1] = pic_offset_table_rtx;
6759 operands[2] = gen_rtx_REG (Pmode, 27);
6760 operands[3] = GEN_INT (alpha_next_sequence_number++);
6763 (define_expand "builtin_setjmp_receiver"
6764 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6767 if (TARGET_EXPLICIT_RELOCS)
6769 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6774 (define_expand "exception_receiver_er"
6776 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6778 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6781 operands[0] = pic_offset_table_rtx;
6782 operands[1] = gen_rtx_REG (Pmode, 26);
6783 operands[2] = GEN_INT (alpha_next_sequence_number++);
6786 (define_expand "exception_receiver"
6787 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6790 if (TARGET_LD_BUGGY_LDGP)
6791 operands[0] = alpha_gp_save_rtx ();
6792 else if (TARGET_EXPLICIT_RELOCS)
6794 emit_insn (gen_exception_receiver_er ());
6798 operands[0] = const0_rtx;
6801 (define_insn "*exception_receiver_1"
6802 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6803 "! TARGET_LD_BUGGY_LDGP"
6805 [(set_attr "length" "8")
6806 (set_attr "type" "multi")])
6808 (define_insn "*exception_receiver_2"
6809 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6810 "TARGET_LD_BUGGY_LDGP"
6812 [(set_attr "type" "ild")])
6814 (define_expand "nonlocal_goto_receiver"
6815 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6816 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6817 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6819 "TARGET_ABI_OPEN_VMS"
6822 (define_insn "arg_home"
6823 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6838 (clobber (mem:BLK (const_int 0)))
6839 (clobber (reg:DI 24))
6840 (clobber (reg:DI 25))
6841 (clobber (reg:DI 0))]
6842 "TARGET_ABI_OPEN_VMS"
6843 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6844 [(set_attr "length" "16")
6845 (set_attr "type" "multi")])
6847 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6849 (define_expand "umk_mismatch_args"
6850 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6851 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6852 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6853 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6856 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6857 "TARGET_ABI_UNICOSMK"
6859 operands[1] = gen_reg_rtx (DImode);
6860 operands[2] = gen_reg_rtx (DImode);
6861 operands[3] = gen_reg_rtx (DImode);
6864 (define_insn "arg_home_umk"
6865 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6880 (clobber (mem:BLK (const_int 0)))
6882 (clobber (reg:DI 22))
6883 (clobber (reg:DI 23))
6884 (clobber (reg:DI 24))
6885 (clobber (reg:DI 0))
6886 (clobber (reg:DI 1))
6887 (clobber (reg:DI 2))
6888 (clobber (reg:DI 3))
6889 (clobber (reg:DI 4))
6890 (clobber (reg:DI 5))
6891 (clobber (reg:DI 6))
6892 (clobber (reg:DI 7))
6893 (clobber (reg:DI 8))])]
6894 "TARGET_ABI_UNICOSMK"
6895 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6896 [(set_attr "length" "16")
6897 (set_attr "type" "multi")])
6901 ;; On EV4, these instructions are nops -- no load occurs.
6903 ;; On EV5, these instructions act as a normal load, and thus can trap
6904 ;; if the address is invalid. The OS may (or may not) handle this in
6905 ;; the entMM fault handler and suppress the fault. If so, then this
6906 ;; has the effect of a read prefetch instruction.
6908 ;; On EV6, these become official prefetch instructions.
6910 (define_insn "prefetch"
6911 [(prefetch (match_operand:DI 0 "address_operand" "p")
6912 (match_operand:DI 1 "const_int_operand" "n")
6913 (match_operand:DI 2 "const_int_operand" "n"))]
6914 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6916 /* Interpret "no temporal locality" as this data should be evicted once
6917 it is used. The "evict next" alternatives load the data into the cache
6918 and leave the LRU eviction counter pointing to that block. */
6919 static const char * const alt[2][2] = {
6921 "lds $f31,%a0", /* read, evict next */
6922 "ldl $31,%a0", /* read, evict last */
6925 "ldt $f31,%a0", /* write, evict next */
6926 "ldq $31,%a0", /* write, evict last */
6930 bool write = INTVAL (operands[1]) != 0;
6931 bool lru = INTVAL (operands[2]) != 0;
6933 return alt[write][lru];
6935 [(set_attr "type" "ild")])
6937 ;; Close the trap shadow of preceding instructions. This is generated
6940 (define_insn "trapb"
6941 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6944 [(set_attr "type" "misc")])
6946 ;; No-op instructions used by machine-dependent reorg to preserve
6947 ;; alignment for instruction issue.
6948 ;; The Unicos/Mk assembler does not support these opcodes.
6954 [(set_attr "type" "ilog")])
6959 "cpys $f31,$f31,$f31"
6960 [(set_attr "type" "fcpys")])
6967 ;; On Unicos/Mk we use a macro for aligning code.
6969 (define_insn "realign"
6970 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6974 if (TARGET_ABI_UNICOSMK)
6975 return "gcc@code@align %0";
6977 return ".align %0 #realign";
6980 ;; Instructions to be emitted from __builtins.
6982 (define_insn "builtin_cmpbge"
6983 [(set (match_operand:DI 0 "register_operand" "=r")
6984 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
6985 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
6989 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
6990 ;; actually differentiate between ILOG and ICMP in the schedule.
6991 [(set_attr "type" "icmp")])
6993 (define_expand "builtin_extql"
6994 [(match_operand:DI 0 "register_operand" "")
6995 (match_operand:DI 1 "reg_or_0_operand" "")
6996 (match_operand:DI 2 "reg_or_8bit_operand" "")]
6999 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7000 if (WORDS_BIG_ENDIAN)
7004 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7008 (define_expand "builtin_extqh"
7009 [(match_operand:DI 0 "register_operand" "")
7010 (match_operand:DI 1 "reg_or_0_operand" "")
7011 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7014 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7015 if (WORDS_BIG_ENDIAN)
7019 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7023 (define_expand "builtin_zap"
7024 [(set (match_operand:DI 0 "register_operand" "")
7026 [(match_operand:DI 2 "reg_or_const_int_operand" "")]
7028 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7031 if (GET_CODE (operands[2]) == CONST_INT)
7033 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7035 if (operands[1] == const0_rtx)
7037 emit_move_insn (operands[0], const0_rtx);
7040 if (operands[1] == constm1_rtx)
7042 emit_move_insn (operands[0], operands[1]);
7046 operands[1] = force_reg (DImode, operands[1]);
7047 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7051 operands[1] = force_reg (DImode, operands[1]);
7052 operands[2] = gen_lowpart (QImode, operands[2]);
7055 (define_insn "*builtin_zap_1"
7056 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7058 [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")]
7060 (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))]
7067 [(set_attr "type" "shift,shift,ilog,shift")])
7070 [(set (match_operand:DI 0 "register_operand" "")
7072 [(match_operand:QI 2 "const_int_operand" "")]
7074 (match_operand:DI 1 "const_int_operand" "")))]
7078 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7079 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7080 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7083 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7084 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7085 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7086 c_hi & CONST_DOUBLE_HIGH (mask),
7089 emit_move_insn (operands[0], operands[1]);
7094 [(set (match_operand:DI 0 "register_operand" "")
7096 [(match_operand:QI 2 "const_int_operand" "")]
7098 (match_operand:DI 1 "register_operand" "")))]
7101 (and:DI (match_dup 1) (match_dup 2)))]
7103 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7104 if (operands[2] == const0_rtx)
7106 emit_move_insn (operands[0], const0_rtx);
7109 if (operands[2] == constm1_rtx)
7111 emit_move_insn (operands[0], operands[1]);
7116 (define_expand "builtin_zapnot"
7117 [(set (match_operand:DI 0 "register_operand" "")
7119 [(not:QI (match_operand:QI 2 "reg_or_const_int_operand" ""))]
7121 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7124 if (GET_CODE (operands[2]) == CONST_INT)
7126 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7128 if (operands[1] == const0_rtx)
7130 emit_move_insn (operands[0], const0_rtx);
7133 if (operands[1] == constm1_rtx)
7135 emit_move_insn (operands[0], operands[1]);
7139 operands[1] = force_reg (DImode, operands[1]);
7140 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7144 operands[1] = force_reg (DImode, operands[1]);
7145 operands[2] = gen_lowpart (QImode, operands[2]);
7148 (define_insn "*builtin_zapnot_1"
7149 [(set (match_operand:DI 0 "register_operand" "=r")
7151 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7153 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7156 [(set_attr "type" "shift")])
7158 (define_insn "builtin_amask"
7159 [(set (match_operand:DI 0 "register_operand" "=r")
7160 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7164 [(set_attr "type" "ilog")])
7166 (define_insn "builtin_implver"
7167 [(set (match_operand:DI 0 "register_operand" "=r")
7168 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7171 [(set_attr "type" "ilog")])
7173 (define_insn "builtin_rpcc"
7174 [(set (match_operand:DI 0 "register_operand" "=r")
7175 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7178 [(set_attr "type" "ilog")])
7180 (define_expand "builtin_minub8"
7181 [(match_operand:DI 0 "register_operand" "")
7182 (match_operand:DI 1 "reg_or_0_operand" "")
7183 (match_operand:DI 2 "reg_or_0_operand" "")]
7186 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7187 operands[1], operands[2]);
7191 (define_expand "builtin_minsb8"
7192 [(match_operand:DI 0 "register_operand" "")
7193 (match_operand:DI 1 "reg_or_0_operand" "")
7194 (match_operand:DI 2 "reg_or_0_operand" "")]
7197 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7198 operands[1], operands[2]);
7202 (define_expand "builtin_minuw4"
7203 [(match_operand:DI 0 "register_operand" "")
7204 (match_operand:DI 1 "reg_or_0_operand" "")
7205 (match_operand:DI 2 "reg_or_0_operand" "")]
7208 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7209 operands[1], operands[2]);
7213 (define_expand "builtin_minsw4"
7214 [(match_operand:DI 0 "register_operand" "")
7215 (match_operand:DI 1 "reg_or_0_operand" "")
7216 (match_operand:DI 2 "reg_or_0_operand" "")]
7219 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7220 operands[1], operands[2]);
7224 (define_expand "builtin_maxub8"
7225 [(match_operand:DI 0 "register_operand" "")
7226 (match_operand:DI 1 "reg_or_0_operand" "")
7227 (match_operand:DI 2 "reg_or_0_operand" "")]
7230 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7231 operands[1], operands[2]);
7235 (define_expand "builtin_maxsb8"
7236 [(match_operand:DI 0 "register_operand" "")
7237 (match_operand:DI 1 "reg_or_0_operand" "")
7238 (match_operand:DI 2 "reg_or_0_operand" "")]
7241 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7242 operands[1], operands[2]);
7246 (define_expand "builtin_maxuw4"
7247 [(match_operand:DI 0 "register_operand" "")
7248 (match_operand:DI 1 "reg_or_0_operand" "")
7249 (match_operand:DI 2 "reg_or_0_operand" "")]
7252 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7253 operands[1], operands[2]);
7257 (define_expand "builtin_maxsw4"
7258 [(match_operand:DI 0 "register_operand" "")
7259 (match_operand:DI 1 "reg_or_0_operand" "")
7260 (match_operand:DI 2 "reg_or_0_operand" "")]
7263 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7264 operands[1], operands[2]);
7268 (define_insn "builtin_perr"
7269 [(set (match_operand:DI 0 "register_operand" "=r")
7270 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7271 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7275 [(set_attr "type" "mvi")])
7277 (define_expand "builtin_pklb"
7278 [(set (match_operand:DI 0 "register_operand" "")
7281 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7286 operands[0] = gen_lowpart (V8QImode, operands[0]);
7287 operands[1] = gen_lowpart (V2SImode, operands[1]);
7288 operands[2] = CONST0_RTX (V2QImode);
7289 operands[3] = CONST0_RTX (V4QImode);
7292 (define_insn "*pklb"
7293 [(set (match_operand:V8QI 0 "register_operand" "=r")
7296 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7297 (match_operand:V2QI 2 "const0_operand" ""))
7298 (match_operand:V4QI 3 "const0_operand" "")))]
7301 [(set_attr "type" "mvi")])
7303 (define_expand "builtin_pkwb"
7304 [(set (match_operand:DI 0 "register_operand" "")
7306 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7310 operands[0] = gen_lowpart (V8QImode, operands[0]);
7311 operands[1] = gen_lowpart (V4HImode, operands[1]);
7312 operands[2] = CONST0_RTX (V4QImode);
7315 (define_insn "*pkwb"
7316 [(set (match_operand:V8QI 0 "register_operand" "")
7318 (truncate:V4QI (match_operand:V4HI 1 "register_operand" ""))
7319 (match_operand:V4QI 2 "const0_operand" "")))]
7322 [(set_attr "type" "mvi")])
7324 (define_expand "builtin_unpkbl"
7325 [(set (match_operand:DI 0 "register_operand" "")
7327 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7328 (parallel [(const_int 0) (const_int 1)]))))]
7331 operands[0] = gen_lowpart (V2SImode, operands[0]);
7332 operands[1] = gen_lowpart (V8QImode, operands[1]);
7335 (define_insn "*unpkbl"
7336 [(set (match_operand:V2SI 0 "register_operand" "=r")
7338 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7339 (parallel [(const_int 0) (const_int 1)]))))]
7342 [(set_attr "type" "mvi")])
7344 (define_expand "builtin_unpkbw"
7345 [(set (match_operand:DI 0 "register_operand" "")
7347 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7348 (parallel [(const_int 0)
7354 operands[0] = gen_lowpart (V4HImode, operands[0]);
7355 operands[1] = gen_lowpart (V8QImode, operands[1]);
7358 (define_insn "*unpkbw"
7359 [(set (match_operand:V4HI 0 "register_operand" "=r")
7361 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7362 (parallel [(const_int 0)
7368 [(set_attr "type" "mvi")])
7370 ;; The call patterns are at the end of the file because their
7371 ;; wildcard operand0 interferes with nice recognition.
7373 (define_insn "*call_value_osf_1_er"
7374 [(set (match_operand 0 "" "")
7375 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7376 (match_operand 2 "" "")))
7378 (clobber (reg:DI 26))]
7379 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7381 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7383 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7384 [(set_attr "type" "jsr")
7385 (set_attr "length" "12,*,16")])
7387 ;; We must use peep2 instead of a split because we need accurate life
7388 ;; information for $gp. Consider the case of { bar(); while (1); }.
7390 [(parallel [(set (match_operand 0 "" "")
7391 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7392 (match_operand 2 "" "")))
7394 (clobber (reg:DI 26))])]
7395 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7396 && ! current_file_function_operand (operands[1], Pmode)
7397 && peep2_regno_dead_p (1, 29)"
7398 [(parallel [(set (match_dup 0)
7399 (call (mem:DI (match_dup 3))
7401 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7402 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7404 (use (match_dup 4))])]
7406 if (CONSTANT_P (operands[1]))
7408 operands[3] = gen_rtx_REG (Pmode, 27);
7409 operands[4] = GEN_INT (alpha_next_sequence_number++);
7410 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7411 operands[1], operands[4]));
7415 operands[3] = operands[1];
7416 operands[1] = const0_rtx;
7417 operands[4] = const0_rtx;
7422 [(parallel [(set (match_operand 0 "" "")
7423 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7424 (match_operand 2 "" "")))
7426 (clobber (reg:DI 26))])]
7427 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7428 && ! current_file_function_operand (operands[1], Pmode)
7429 && ! peep2_regno_dead_p (1, 29)"
7430 [(parallel [(set (match_dup 0)
7431 (call (mem:DI (match_dup 3))
7433 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7434 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7436 (use (match_dup 5))])
7438 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7440 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7442 if (CONSTANT_P (operands[1]))
7444 operands[3] = gen_rtx_REG (Pmode, 27);
7445 operands[5] = GEN_INT (alpha_next_sequence_number++);
7446 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7447 operands[1], operands[5]));
7451 operands[3] = operands[1];
7452 operands[1] = const0_rtx;
7453 operands[5] = const0_rtx;
7455 operands[4] = GEN_INT (alpha_next_sequence_number++);
7458 ;; We add a blockage unspec_volatile to prevent insns from moving down
7459 ;; from above the call to in between the call and the ldah gpdisp.
7460 (define_insn "*call_value_osf_2_er"
7461 [(set (match_operand 0 "" "")
7462 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7463 (match_operand 2 "" "")))
7465 (plus:DI (pc) (const_int 4)))
7466 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7467 (use (match_operand 3 "" ""))
7468 (use (match_operand 4 "" ""))]
7469 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7470 "jsr $26,(%1),%3%J4"
7471 [(set_attr "type" "jsr")])
7473 (define_insn "*call_value_osf_1_noreturn"
7474 [(set (match_operand 0 "" "")
7475 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7476 (match_operand 2 "" "")))
7478 (clobber (reg:DI 26))]
7479 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7480 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7485 [(set_attr "type" "jsr")
7486 (set_attr "length" "*,*,8")])
7488 (define_insn_and_split "call_value_osf_tlsgd"
7489 [(set (match_operand 0 "" "")
7490 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7492 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7494 (clobber (reg:DI 26))]
7497 "&& reload_completed"
7499 (unspec:DI [(match_dup 5)
7501 (match_dup 2)] UNSPEC_LITERAL))
7502 (parallel [(set (match_dup 0)
7503 (call (mem:DI (match_dup 3))
7505 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7506 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7508 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7510 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7512 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7514 operands[3] = gen_rtx_REG (Pmode, 27);
7515 operands[4] = GEN_INT (alpha_next_sequence_number++);
7516 operands[5] = pic_offset_table_rtx;
7518 [(set_attr "type" "multi")])
7520 (define_insn_and_split "call_value_osf_tlsldm"
7521 [(set (match_operand 0 "" "")
7522 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7524 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7526 (clobber (reg:DI 26))]
7529 "&& reload_completed"
7531 (unspec:DI [(match_dup 5)
7533 (match_dup 2)] UNSPEC_LITERAL))
7534 (parallel [(set (match_dup 0)
7535 (call (mem:DI (match_dup 3))
7537 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7538 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7540 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7542 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7544 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7546 operands[3] = gen_rtx_REG (Pmode, 27);
7547 operands[4] = GEN_INT (alpha_next_sequence_number++);
7548 operands[5] = pic_offset_table_rtx;
7550 [(set_attr "type" "multi")])
7552 (define_insn "*call_value_osf_1"
7553 [(set (match_operand 0 "" "")
7554 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7555 (match_operand 2 "" "")))
7557 (clobber (reg:DI 26))]
7558 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7560 jsr $26,($27),0\;ldgp $29,0($26)
7562 jsr $26,%1\;ldgp $29,0($26)"
7563 [(set_attr "type" "jsr")
7564 (set_attr "length" "12,*,16")])
7566 (define_insn "*sibcall_value_osf_1_er"
7567 [(set (match_operand 0 "" "")
7568 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7569 (match_operand 2 "" "")))
7570 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7571 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7574 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7575 [(set_attr "type" "jsr")
7576 (set_attr "length" "*,8")])
7578 (define_insn "*sibcall_value_osf_1"
7579 [(set (match_operand 0 "" "")
7580 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7581 (match_operand 2 "" "")))
7582 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7583 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7586 lda $27,%1\;jmp $31,($27),%1"
7587 [(set_attr "type" "jsr")
7588 (set_attr "length" "*,8")])
7590 (define_insn "*call_value_nt_1"
7591 [(set (match_operand 0 "" "")
7592 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7593 (match_operand 2 "" "")))
7594 (clobber (reg:DI 26))]
7595 "TARGET_ABI_WINDOWS_NT"
7600 [(set_attr "type" "jsr")
7601 (set_attr "length" "*,*,12")])
7603 (define_insn "*call_value_vms_1"
7604 [(set (match_operand 0 "" "")
7605 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7606 (match_operand 2 "" "")))
7607 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
7610 (clobber (reg:DI 27))]
7611 "TARGET_ABI_OPEN_VMS"
7613 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
7614 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
7615 [(set_attr "type" "jsr")
7616 (set_attr "length" "12,16")])
7618 (define_insn "*call_value_umk"
7619 [(set (match_operand 0 "" "")
7620 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
7621 (match_operand 2 "" "")))
7623 (clobber (reg:DI 26))]
7624 "TARGET_ABI_UNICOSMK"
7626 [(set_attr "type" "jsr")])