1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
59 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
60 (UNSPECV_LONGJMP 3) ; builtin_longjmp
62 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
64 (UNSPECV_EHR 7) ; exception_receiver
68 (UNSPECV_PLDGP2 11) ; prologue ldgp
72 ;; Where necessary, the suffixes _le and _be are used to distinguish between
73 ;; little-endian and big-endian patterns.
75 ;; Note that the Unicos/Mk assembler does not support the following
76 ;; opcodes: mov, fmov, nop, fnop, unop.
78 ;; Processor type -- this attribute must exactly match the processor_type
79 ;; enumeration in alpha.h.
81 (define_attr "cpu" "ev4,ev5,ev6"
82 (const (symbol_ref "alpha_cpu")))
84 ;; Define an insn type attribute. This is used in function unit delay
85 ;; computations, among other purposes. For the most part, we use the names
86 ;; defined in the EV4 documentation, but add a few that we have to know about
90 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
91 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
92 (const_string "iadd"))
94 ;; Describe a user's asm statement.
95 (define_asm_attributes
96 [(set_attr "type" "multi")])
98 ;; Define the operand size an insn operates on. Used primarily by mul
99 ;; and div operations that have size dependent timings.
101 (define_attr "opsize" "si,di,udi"
104 ;; The TRAP attribute marks instructions that may generate traps
105 ;; (which are imprecise and may need a trapb if software completion
108 (define_attr "trap" "no,yes"
111 ;; The ROUND_SUFFIX attribute marks which instructions require a
112 ;; rounding-mode suffix. The value NONE indicates no suffix,
113 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
115 (define_attr "round_suffix" "none,normal,c"
116 (const_string "none"))
118 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
120 ;; SU accepts only /su (cmpt et al)
121 ;; SUI accepts only /sui (cvtqt and cvtqs)
122 ;; V_SV accepts /v and /sv (cvtql only)
123 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
124 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
126 ;; The actual suffix emitted is controled by alpha_fptm.
128 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
129 (const_string "none"))
131 ;; The length of an instruction sequence in bytes.
133 (define_attr "length" ""
136 ;; Include scheduling descriptions.
142 ;; First define the arithmetic insns. Note that the 32-bit forms also
145 ;; Handle 32-64 bit extension from memory to a floating point register
146 ;; specially, since this occurs frequently in int->double conversions.
148 ;; Note that while we must retain the =f case in the insn for reload's
149 ;; benefit, it should be eliminated after reload, so we should never emit
150 ;; code for that case. But we don't reject the possibility.
152 (define_expand "extendsidi2"
153 [(set (match_operand:DI 0 "register_operand" "")
154 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
158 (define_insn "*extendsidi2_nofix"
159 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
161 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
167 lds %0,%1\;cvtlq %0,%0"
168 [(set_attr "type" "iadd,ild,fadd,fld")
169 (set_attr "length" "*,*,*,8")])
171 (define_insn "*extendsidi2_fix"
172 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
174 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
181 lds %0,%1\;cvtlq %0,%0"
182 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
183 (set_attr "length" "*,*,*,*,8")])
185 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
187 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
188 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
190 [(set (match_dup 2) (match_dup 1))
191 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
192 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
194 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
195 ;; reload when converting fp->int.
198 [(set (match_operand:SI 0 "hard_int_register_operand" "")
199 (match_operand:SI 1 "memory_operand" ""))
200 (set (match_operand:DI 2 "hard_int_register_operand" "")
201 (sign_extend:DI (match_dup 0)))]
202 "true_regnum (operands[0]) == true_regnum (operands[2])
203 || peep2_reg_dead_p (2, operands[0])"
205 (sign_extend:DI (match_dup 1)))]
209 [(set (match_operand:SI 0 "hard_int_register_operand" "")
210 (match_operand:SI 1 "hard_fp_register_operand" ""))
211 (set (match_operand:DI 2 "hard_int_register_operand" "")
212 (sign_extend:DI (match_dup 0)))]
214 && (true_regnum (operands[0]) == true_regnum (operands[2])
215 || peep2_reg_dead_p (2, operands[0]))"
217 (sign_extend:DI (match_dup 1)))]
221 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
222 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
223 (set (match_operand:DI 2 "hard_int_register_operand" "")
225 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
227 (sign_extend:DI (match_dup 1)))]
230 ;; Don't say we have addsi3 if optimizing. This generates better code. We
231 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
232 (define_expand "addsi3"
233 [(set (match_operand:SI 0 "register_operand" "")
234 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
235 (match_operand:SI 2 "add_operand" "")))]
239 (define_insn "*addsi_internal"
240 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
241 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
242 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
251 [(set (match_operand:SI 0 "register_operand" "")
252 (plus:SI (match_operand:SI 1 "register_operand" "")
253 (match_operand:SI 2 "const_int_operand" "")))]
254 "! add_operand (operands[2], SImode)"
255 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
256 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
258 HOST_WIDE_INT val = INTVAL (operands[2]);
259 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
260 HOST_WIDE_INT rest = val - low;
262 operands[3] = GEN_INT (rest);
263 operands[4] = GEN_INT (low);
266 (define_insn "*addsi_se"
267 [(set (match_operand:DI 0 "register_operand" "=r,r")
269 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
270 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
276 (define_insn "*addsi_se2"
277 [(set (match_operand:DI 0 "register_operand" "=r,r")
279 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
280 (match_operand:DI 2 "sext_add_operand" "rI,O"))
288 [(set (match_operand:DI 0 "register_operand" "")
290 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
291 (match_operand:SI 2 "const_int_operand" ""))))
292 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
293 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
294 && INTVAL (operands[2]) % 4 == 0"
295 [(set (match_dup 3) (match_dup 4))
296 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
300 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
306 operands[4] = GEN_INT (val);
307 operands[5] = GEN_INT (mult);
311 [(set (match_operand:DI 0 "register_operand" "")
313 (plus:SI (match_operator:SI 1 "comparison_operator"
314 [(match_operand 2 "" "")
315 (match_operand 3 "" "")])
316 (match_operand:SI 4 "add_operand" ""))))
317 (clobber (match_operand:DI 5 "register_operand" ""))]
319 [(set (match_dup 5) (match_dup 6))
320 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
322 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
323 operands[2], operands[3]);
324 operands[7] = gen_lowpart (SImode, operands[5]);
327 (define_insn "addvsi3"
328 [(set (match_operand:SI 0 "register_operand" "=r,r")
329 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
330 (match_operand:SI 2 "sext_add_operand" "rI,O")))
331 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
332 (sign_extend:DI (match_dup 2)))
333 (sign_extend:DI (plus:SI (match_dup 1)
341 (define_expand "adddi3"
342 [(set (match_operand:DI 0 "register_operand" "")
343 (plus:DI (match_operand:DI 1 "register_operand" "")
344 (match_operand:DI 2 "add_operand" "")))]
348 (define_insn "*adddi_er_lo16_dtp"
349 [(set (match_operand:DI 0 "register_operand" "=r")
350 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
351 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
353 "lda %0,%2(%1)\t\t!dtprel")
355 (define_insn "*adddi_er_hi32_dtp"
356 [(set (match_operand:DI 0 "register_operand" "=r")
357 (plus:DI (match_operand:DI 1 "register_operand" "r")
358 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
360 "ldah %0,%2(%1)\t\t!dtprelhi")
362 (define_insn "*adddi_er_lo32_dtp"
363 [(set (match_operand:DI 0 "register_operand" "=r")
364 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
365 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
367 "lda %0,%2(%1)\t\t!dtprello")
369 (define_insn "*adddi_er_lo16_tp"
370 [(set (match_operand:DI 0 "register_operand" "=r")
371 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
372 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
374 "lda %0,%2(%1)\t\t!tprel")
376 (define_insn "*adddi_er_hi32_tp"
377 [(set (match_operand:DI 0 "register_operand" "=r")
378 (plus:DI (match_operand:DI 1 "register_operand" "r")
379 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
381 "ldah %0,%2(%1)\t\t!tprelhi")
383 (define_insn "*adddi_er_lo32_tp"
384 [(set (match_operand:DI 0 "register_operand" "=r")
385 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
386 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
388 "lda %0,%2(%1)\t\t!tprello")
390 (define_insn "*adddi_er_high_l"
391 [(set (match_operand:DI 0 "register_operand" "=r")
392 (plus:DI (match_operand:DI 1 "register_operand" "r")
393 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
394 "TARGET_EXPLICIT_RELOCS"
395 "ldah %0,%2(%1)\t\t!gprelhigh")
398 [(set (match_operand:DI 0 "register_operand" "")
399 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
400 "TARGET_EXPLICIT_RELOCS && reload_completed"
402 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
403 "operands[2] = pic_offset_table_rtx;")
405 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
406 ;; With complications like
408 ;; The NT stack unwind code can't handle a subq to adjust the stack
409 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
410 ;; the exception handling code will loop if a subq is used and an
413 ;; The 19980616 change to emit prologues as RTL also confused some
414 ;; versions of GDB, which also interprets prologues. This has been
415 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
418 ;; and the fact that the three insns schedule exactly the same, it's
419 ;; just not worth the effort.
421 (define_insn "*adddi_internal"
422 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
423 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
424 (match_operand:DI 2 "add_operand" "r,K,L")))]
431 ;; ??? Allow large constants when basing off the frame pointer or some
432 ;; virtual register that may eliminate to the frame pointer. This is
433 ;; done because register elimination offsets will change the hi/lo split,
434 ;; and if we split before reload, we will require additional instructions.
436 (define_insn "*adddi_fp_hack"
437 [(set (match_operand:DI 0 "register_operand" "=r")
438 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
439 (match_operand:DI 2 "const_int_operand" "n")))]
440 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
441 && INTVAL (operands[2]) >= 0
442 /* This is the largest constant an lda+ldah pair can add, minus
443 an upper bound on the displacement between SP and AP during
444 register elimination. See INITIAL_ELIMINATION_OFFSET. */
445 && INTVAL (operands[2])
447 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
448 - ALPHA_ROUND(current_function_outgoing_args_size)
449 - (ALPHA_ROUND (get_frame_size ()
450 + max_reg_num () * UNITS_PER_WORD
451 + current_function_pretend_args_size)
452 - current_function_pretend_args_size))"
455 ;; Don't do this if we are adjusting SP since we don't want to do it
456 ;; in two steps. Don't split FP sources for the reason listed above.
458 [(set (match_operand:DI 0 "register_operand" "")
459 (plus:DI (match_operand:DI 1 "register_operand" "")
460 (match_operand:DI 2 "const_int_operand" "")))]
461 "! add_operand (operands[2], DImode)
462 && operands[0] != stack_pointer_rtx
463 && operands[1] != frame_pointer_rtx
464 && operands[1] != arg_pointer_rtx"
465 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
466 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
468 HOST_WIDE_INT val = INTVAL (operands[2]);
469 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
470 HOST_WIDE_INT rest = val - low;
472 operands[4] = GEN_INT (low);
473 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
474 operands[3] = GEN_INT (rest);
475 else if (! no_new_pseudos)
477 operands[3] = gen_reg_rtx (DImode);
478 emit_move_insn (operands[3], operands[2]);
479 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
486 (define_insn "*saddl"
487 [(set (match_operand:SI 0 "register_operand" "=r,r")
488 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
489 (match_operand:SI 2 "const48_operand" "I,I"))
490 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
496 (define_insn "*saddl_se"
497 [(set (match_operand:DI 0 "register_operand" "=r,r")
499 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
500 (match_operand:SI 2 "const48_operand" "I,I"))
501 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
508 [(set (match_operand:DI 0 "register_operand" "")
510 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
511 [(match_operand 2 "" "")
512 (match_operand 3 "" "")])
513 (match_operand:SI 4 "const48_operand" ""))
514 (match_operand:SI 5 "sext_add_operand" ""))))
515 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
517 [(set (match_dup 6) (match_dup 7))
519 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
522 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
523 operands[2], operands[3]);
524 operands[8] = gen_lowpart (SImode, operands[6]);
527 (define_insn "*saddq"
528 [(set (match_operand:DI 0 "register_operand" "=r,r")
529 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
530 (match_operand:DI 2 "const48_operand" "I,I"))
531 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
537 (define_insn "addvdi3"
538 [(set (match_operand:DI 0 "register_operand" "=r,r")
539 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
540 (match_operand:DI 2 "sext_add_operand" "rI,O")))
541 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
542 (sign_extend:TI (match_dup 2)))
543 (sign_extend:TI (plus:DI (match_dup 1)
551 (define_insn "negsi2"
552 [(set (match_operand:SI 0 "register_operand" "=r")
553 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
557 (define_insn "*negsi_se"
558 [(set (match_operand:DI 0 "register_operand" "=r")
559 (sign_extend:DI (neg:SI
560 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
564 (define_insn "negvsi2"
565 [(set (match_operand:SI 0 "register_operand" "=r")
566 (neg:SI (match_operand:SI 1 "register_operand" "r")))
567 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
568 (sign_extend:DI (neg:SI (match_dup 1))))
573 (define_insn "negdi2"
574 [(set (match_operand:DI 0 "register_operand" "=r")
575 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
579 (define_insn "negvdi2"
580 [(set (match_operand:DI 0 "register_operand" "=r")
581 (neg:DI (match_operand:DI 1 "register_operand" "r")))
582 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
583 (sign_extend:TI (neg:DI (match_dup 1))))
588 (define_expand "subsi3"
589 [(set (match_operand:SI 0 "register_operand" "")
590 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
591 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
595 (define_insn "*subsi_internal"
596 [(set (match_operand:SI 0 "register_operand" "=r")
597 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
598 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
602 (define_insn "*subsi_se"
603 [(set (match_operand:DI 0 "register_operand" "=r")
604 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
605 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
609 (define_insn "*subsi_se2"
610 [(set (match_operand:DI 0 "register_operand" "=r")
612 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
613 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
618 (define_insn "subvsi3"
619 [(set (match_operand:SI 0 "register_operand" "=r")
620 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
621 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
622 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
623 (sign_extend:DI (match_dup 2)))
624 (sign_extend:DI (minus:SI (match_dup 1)
630 (define_insn "subdi3"
631 [(set (match_operand:DI 0 "register_operand" "=r")
632 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
633 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
637 (define_insn "*ssubl"
638 [(set (match_operand:SI 0 "register_operand" "=r")
639 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
640 (match_operand:SI 2 "const48_operand" "I"))
641 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
645 (define_insn "*ssubl_se"
646 [(set (match_operand:DI 0 "register_operand" "=r")
648 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
649 (match_operand:SI 2 "const48_operand" "I"))
650 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
654 (define_insn "*ssubq"
655 [(set (match_operand:DI 0 "register_operand" "=r")
656 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
657 (match_operand:DI 2 "const48_operand" "I"))
658 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
662 (define_insn "subvdi3"
663 [(set (match_operand:DI 0 "register_operand" "=r")
664 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
665 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
666 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
667 (sign_extend:TI (match_dup 2)))
668 (sign_extend:TI (minus:DI (match_dup 1)
674 ;; The Unicos/Mk assembler doesn't support mull.
676 (define_insn "mulsi3"
677 [(set (match_operand:SI 0 "register_operand" "=r")
678 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
679 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
680 "!TARGET_ABI_UNICOSMK"
682 [(set_attr "type" "imul")
683 (set_attr "opsize" "si")])
685 (define_insn "*mulsi_se"
686 [(set (match_operand:DI 0 "register_operand" "=r")
688 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
689 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
690 "!TARGET_ABI_UNICOSMK"
692 [(set_attr "type" "imul")
693 (set_attr "opsize" "si")])
695 (define_insn "mulvsi3"
696 [(set (match_operand:SI 0 "register_operand" "=r")
697 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
698 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
699 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
700 (sign_extend:DI (match_dup 2)))
701 (sign_extend:DI (mult:SI (match_dup 1)
704 "!TARGET_ABI_UNICOSMK"
706 [(set_attr "type" "imul")
707 (set_attr "opsize" "si")])
709 (define_insn "muldi3"
710 [(set (match_operand:DI 0 "register_operand" "=r")
711 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
712 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
715 [(set_attr "type" "imul")])
717 (define_insn "mulvdi3"
718 [(set (match_operand:DI 0 "register_operand" "=r")
719 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
720 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
721 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
722 (sign_extend:TI (match_dup 2)))
723 (sign_extend:TI (mult:DI (match_dup 1)
728 [(set_attr "type" "imul")])
730 (define_insn "umuldi3_highpart"
731 [(set (match_operand:DI 0 "register_operand" "=r")
734 (mult:TI (zero_extend:TI
735 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
737 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
741 [(set_attr "type" "imul")
742 (set_attr "opsize" "udi")])
744 (define_insn "*umuldi3_highpart_const"
745 [(set (match_operand:DI 0 "register_operand" "=r")
748 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
749 (match_operand:TI 2 "cint8_operand" "I"))
753 [(set_attr "type" "imul")
754 (set_attr "opsize" "udi")])
756 ;; The divide and remainder operations take their inputs from r24 and
757 ;; r25, put their output in r27, and clobber r23 and r28 on all
758 ;; systems except Unicos/Mk. On Unicos, the standard library provides
759 ;; subroutines which use the standard calling convention and work on
762 ;; ??? Force sign-extension here because some versions of OSF/1 and
763 ;; Interix/NT don't do the right thing if the inputs are not properly
764 ;; sign-extended. But Linux, for instance, does not have this
765 ;; problem. Is it worth the complication here to eliminate the sign
768 (define_expand "divsi3"
770 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
772 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
773 (parallel [(set (match_dup 5)
774 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
775 (clobber (reg:DI 23))
776 (clobber (reg:DI 28))])
777 (set (match_operand:SI 0 "nonimmediate_operand" "")
778 (subreg:SI (match_dup 5) 0))]
779 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
781 operands[3] = gen_reg_rtx (DImode);
782 operands[4] = gen_reg_rtx (DImode);
783 operands[5] = gen_reg_rtx (DImode);
786 (define_expand "udivsi3"
788 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
790 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
791 (parallel [(set (match_dup 5)
792 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
793 (clobber (reg:DI 23))
794 (clobber (reg:DI 28))])
795 (set (match_operand:SI 0 "nonimmediate_operand" "")
796 (subreg:SI (match_dup 5) 0))]
797 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
799 operands[3] = gen_reg_rtx (DImode);
800 operands[4] = gen_reg_rtx (DImode);
801 operands[5] = gen_reg_rtx (DImode);
804 (define_expand "modsi3"
806 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
808 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
809 (parallel [(set (match_dup 5)
810 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
811 (clobber (reg:DI 23))
812 (clobber (reg:DI 28))])
813 (set (match_operand:SI 0 "nonimmediate_operand" "")
814 (subreg:SI (match_dup 5) 0))]
815 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
817 operands[3] = gen_reg_rtx (DImode);
818 operands[4] = gen_reg_rtx (DImode);
819 operands[5] = gen_reg_rtx (DImode);
822 (define_expand "umodsi3"
824 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
826 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
827 (parallel [(set (match_dup 5)
828 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
829 (clobber (reg:DI 23))
830 (clobber (reg:DI 28))])
831 (set (match_operand:SI 0 "nonimmediate_operand" "")
832 (subreg:SI (match_dup 5) 0))]
833 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
835 operands[3] = gen_reg_rtx (DImode);
836 operands[4] = gen_reg_rtx (DImode);
837 operands[5] = gen_reg_rtx (DImode);
840 (define_expand "divdi3"
841 [(parallel [(set (match_operand:DI 0 "register_operand" "")
842 (div:DI (match_operand:DI 1 "register_operand" "")
843 (match_operand:DI 2 "register_operand" "")))
844 (clobber (reg:DI 23))
845 (clobber (reg:DI 28))])]
846 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
849 (define_expand "udivdi3"
850 [(parallel [(set (match_operand:DI 0 "register_operand" "")
851 (udiv:DI (match_operand:DI 1 "register_operand" "")
852 (match_operand:DI 2 "register_operand" "")))
853 (clobber (reg:DI 23))
854 (clobber (reg:DI 28))])]
855 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
858 (define_expand "moddi3"
859 [(use (match_operand:DI 0 "register_operand" ""))
860 (use (match_operand:DI 1 "register_operand" ""))
861 (use (match_operand:DI 2 "register_operand" ""))]
862 "!TARGET_ABI_OPEN_VMS"
864 if (TARGET_ABI_UNICOSMK)
865 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
867 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
871 (define_expand "moddi3_dft"
872 [(parallel [(set (match_operand:DI 0 "register_operand" "")
873 (mod:DI (match_operand:DI 1 "register_operand" "")
874 (match_operand:DI 2 "register_operand" "")))
875 (clobber (reg:DI 23))
876 (clobber (reg:DI 28))])]
877 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
880 ;; On Unicos/Mk, we do as the system's C compiler does:
881 ;; compute the quotient, multiply and subtract.
883 (define_expand "moddi3_umk"
884 [(use (match_operand:DI 0 "register_operand" ""))
885 (use (match_operand:DI 1 "register_operand" ""))
886 (use (match_operand:DI 2 "register_operand" ""))]
887 "TARGET_ABI_UNICOSMK"
889 rtx div, mul = gen_reg_rtx (DImode);
891 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
892 NULL_RTX, 0, OPTAB_LIB);
893 div = force_reg (DImode, div);
894 emit_insn (gen_muldi3 (mul, operands[2], div));
895 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
899 (define_expand "umoddi3"
900 [(use (match_operand:DI 0 "register_operand" ""))
901 (use (match_operand:DI 1 "register_operand" ""))
902 (use (match_operand:DI 2 "register_operand" ""))]
903 "! TARGET_ABI_OPEN_VMS"
905 if (TARGET_ABI_UNICOSMK)
906 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
908 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
912 (define_expand "umoddi3_dft"
913 [(parallel [(set (match_operand:DI 0 "register_operand" "")
914 (umod:DI (match_operand:DI 1 "register_operand" "")
915 (match_operand:DI 2 "register_operand" "")))
916 (clobber (reg:DI 23))
917 (clobber (reg:DI 28))])]
918 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
921 (define_expand "umoddi3_umk"
922 [(use (match_operand:DI 0 "register_operand" ""))
923 (use (match_operand:DI 1 "register_operand" ""))
924 (use (match_operand:DI 2 "register_operand" ""))]
925 "TARGET_ABI_UNICOSMK"
927 rtx div, mul = gen_reg_rtx (DImode);
929 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
930 NULL_RTX, 1, OPTAB_LIB);
931 div = force_reg (DImode, div);
932 emit_insn (gen_muldi3 (mul, operands[2], div));
933 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
937 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
938 ;; expanded by the assembler.
940 (define_insn_and_split "*divmodsi_internal_er"
941 [(set (match_operand:DI 0 "register_operand" "=c")
942 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
943 [(match_operand:DI 1 "register_operand" "a")
944 (match_operand:DI 2 "register_operand" "b")])))
945 (clobber (reg:DI 23))
946 (clobber (reg:DI 28))]
947 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
948 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
949 "&& reload_completed"
950 [(parallel [(set (match_dup 0)
951 (sign_extend:DI (match_dup 3)))
954 (clobber (reg:DI 23))
955 (clobber (reg:DI 28))])]
958 switch (GET_CODE (operands[3]))
975 operands[4] = GEN_INT (alpha_next_sequence_number++);
976 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
977 gen_rtx_SYMBOL_REF (DImode, str),
980 [(set_attr "type" "jsr")
981 (set_attr "length" "8")])
983 (define_insn "*divmodsi_internal_er_1"
984 [(set (match_operand:DI 0 "register_operand" "=c")
985 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
986 [(match_operand:DI 1 "register_operand" "a")
987 (match_operand:DI 2 "register_operand" "b")])))
988 (use (match_operand:DI 4 "register_operand" "c"))
989 (use (match_operand 5 "const_int_operand" ""))
990 (clobber (reg:DI 23))
991 (clobber (reg:DI 28))]
992 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
993 "jsr $23,($27),__%E3%J5"
994 [(set_attr "type" "jsr")
995 (set_attr "length" "4")])
997 (define_insn "*divmodsi_internal"
998 [(set (match_operand:DI 0 "register_operand" "=c")
999 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1000 [(match_operand:DI 1 "register_operand" "a")
1001 (match_operand:DI 2 "register_operand" "b")])))
1002 (clobber (reg:DI 23))
1003 (clobber (reg:DI 28))]
1004 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1006 [(set_attr "type" "jsr")
1007 (set_attr "length" "8")])
1009 (define_insn_and_split "*divmoddi_internal_er"
1010 [(set (match_operand:DI 0 "register_operand" "=c")
1011 (match_operator:DI 3 "divmod_operator"
1012 [(match_operand:DI 1 "register_operand" "a")
1013 (match_operand:DI 2 "register_operand" "b")]))
1014 (clobber (reg:DI 23))
1015 (clobber (reg:DI 28))]
1016 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1017 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1018 "&& reload_completed"
1019 [(parallel [(set (match_dup 0) (match_dup 3))
1022 (clobber (reg:DI 23))
1023 (clobber (reg:DI 28))])]
1026 switch (GET_CODE (operands[3]))
1043 operands[4] = GEN_INT (alpha_next_sequence_number++);
1044 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1045 gen_rtx_SYMBOL_REF (DImode, str),
1048 [(set_attr "type" "jsr")
1049 (set_attr "length" "8")])
1051 (define_insn "*divmoddi_internal_er_1"
1052 [(set (match_operand:DI 0 "register_operand" "=c")
1053 (match_operator:DI 3 "divmod_operator"
1054 [(match_operand:DI 1 "register_operand" "a")
1055 (match_operand:DI 2 "register_operand" "b")]))
1056 (use (match_operand:DI 4 "register_operand" "c"))
1057 (use (match_operand 5 "const_int_operand" ""))
1058 (clobber (reg:DI 23))
1059 (clobber (reg:DI 28))]
1060 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1061 "jsr $23,($27),__%E3%J5"
1062 [(set_attr "type" "jsr")
1063 (set_attr "length" "4")])
1065 (define_insn "*divmoddi_internal"
1066 [(set (match_operand:DI 0 "register_operand" "=c")
1067 (match_operator:DI 3 "divmod_operator"
1068 [(match_operand:DI 1 "register_operand" "a")
1069 (match_operand:DI 2 "register_operand" "b")]))
1070 (clobber (reg:DI 23))
1071 (clobber (reg:DI 28))]
1072 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1074 [(set_attr "type" "jsr")
1075 (set_attr "length" "8")])
1077 ;; Next are the basic logical operations. These only exist in DImode.
1079 (define_insn "anddi3"
1080 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1081 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1082 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1088 [(set_attr "type" "ilog,ilog,shift")])
1090 ;; There are times when we can split an AND into two AND insns. This occurs
1091 ;; when we can first clear any bytes and then clear anything else. For
1092 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1093 ;; Only do this when running on 64-bit host since the computations are
1094 ;; too messy otherwise.
1097 [(set (match_operand:DI 0 "register_operand" "")
1098 (and:DI (match_operand:DI 1 "register_operand" "")
1099 (match_operand:DI 2 "const_int_operand" "")))]
1100 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1101 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1102 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1104 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1105 unsigned HOST_WIDE_INT mask2 = mask1;
1108 /* For each byte that isn't all zeros, make it all ones. */
1109 for (i = 0; i < 64; i += 8)
1110 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1111 mask1 |= (HOST_WIDE_INT) 0xff << i;
1113 /* Now turn on any bits we've just turned off. */
1116 operands[3] = GEN_INT (mask1);
1117 operands[4] = GEN_INT (mask2);
1120 (define_expand "zero_extendqihi2"
1121 [(set (match_operand:HI 0 "register_operand" "")
1122 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1126 operands[1] = force_reg (QImode, operands[1]);
1129 (define_insn "*zero_extendqihi2_bwx"
1130 [(set (match_operand:HI 0 "register_operand" "=r,r")
1131 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1136 [(set_attr "type" "ilog,ild")])
1138 (define_insn "*zero_extendqihi2_nobwx"
1139 [(set (match_operand:HI 0 "register_operand" "=r")
1140 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1143 [(set_attr "type" "ilog")])
1145 (define_expand "zero_extendqisi2"
1146 [(set (match_operand:SI 0 "register_operand" "")
1147 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1151 operands[1] = force_reg (QImode, operands[1]);
1154 (define_insn "*zero_extendqisi2_bwx"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1161 [(set_attr "type" "ilog,ild")])
1163 (define_insn "*zero_extendqisi2_nobwx"
1164 [(set (match_operand:SI 0 "register_operand" "=r")
1165 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1168 [(set_attr "type" "ilog")])
1170 (define_expand "zero_extendqidi2"
1171 [(set (match_operand:DI 0 "register_operand" "")
1172 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1176 operands[1] = force_reg (QImode, operands[1]);
1179 (define_insn "*zero_extendqidi2_bwx"
1180 [(set (match_operand:DI 0 "register_operand" "=r,r")
1181 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1186 [(set_attr "type" "ilog,ild")])
1188 (define_insn "*zero_extendqidi2_nobwx"
1189 [(set (match_operand:DI 0 "register_operand" "=r")
1190 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1193 [(set_attr "type" "ilog")])
1195 (define_expand "zero_extendhisi2"
1196 [(set (match_operand:SI 0 "register_operand" "")
1197 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1201 operands[1] = force_reg (HImode, operands[1]);
1204 (define_insn "*zero_extendhisi2_bwx"
1205 [(set (match_operand:SI 0 "register_operand" "=r,r")
1206 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1211 [(set_attr "type" "shift,ild")])
1213 (define_insn "*zero_extendhisi2_nobwx"
1214 [(set (match_operand:SI 0 "register_operand" "=r")
1215 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1218 [(set_attr "type" "shift")])
1220 (define_expand "zero_extendhidi2"
1221 [(set (match_operand:DI 0 "register_operand" "")
1222 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1226 operands[1] = force_reg (HImode, operands[1]);
1229 (define_insn "*zero_extendhidi2_bwx"
1230 [(set (match_operand:DI 0 "register_operand" "=r,r")
1231 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1236 [(set_attr "type" "shift,ild")])
1238 (define_insn "*zero_extendhidi2_nobwx"
1239 [(set (match_operand:DI 0 "register_operand" "=r")
1240 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1243 [(set_attr "type" "shift")])
1245 (define_insn "zero_extendsidi2"
1246 [(set (match_operand:DI 0 "register_operand" "=r")
1247 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1250 [(set_attr "type" "shift")])
1252 (define_insn "andnotdi3"
1253 [(set (match_operand:DI 0 "register_operand" "=r")
1254 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1255 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1258 [(set_attr "type" "ilog")])
1260 (define_insn "iordi3"
1261 [(set (match_operand:DI 0 "register_operand" "=r,r")
1262 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1263 (match_operand:DI 2 "or_operand" "rI,N")))]
1268 [(set_attr "type" "ilog")])
1270 (define_insn "one_cmpldi2"
1271 [(set (match_operand:DI 0 "register_operand" "=r")
1272 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1275 [(set_attr "type" "ilog")])
1277 (define_insn "*iornot"
1278 [(set (match_operand:DI 0 "register_operand" "=r")
1279 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1280 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1283 [(set_attr "type" "ilog")])
1285 (define_insn "xordi3"
1286 [(set (match_operand:DI 0 "register_operand" "=r,r")
1287 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1288 (match_operand:DI 2 "or_operand" "rI,N")))]
1293 [(set_attr "type" "ilog")])
1295 (define_insn "*xornot"
1296 [(set (match_operand:DI 0 "register_operand" "=r")
1297 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1298 (match_operand:DI 2 "register_operand" "rI"))))]
1301 [(set_attr "type" "ilog")])
1303 ;; Handle the FFS insn iff we support CIX.
1305 (define_expand "ffsdi2"
1307 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1309 (plus:DI (match_dup 2) (const_int 1)))
1310 (set (match_operand:DI 0 "register_operand" "")
1311 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1312 (const_int 0) (match_dup 3)))]
1315 operands[2] = gen_reg_rtx (DImode);
1316 operands[3] = gen_reg_rtx (DImode);
1319 (define_insn "*cttz"
1320 [(set (match_operand:DI 0 "register_operand" "=r")
1321 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1324 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1325 ; reuse the existing type name.
1326 [(set_attr "type" "mvi")])
1328 ;; Next come the shifts and the various extract and insert operations.
1330 (define_insn "ashldi3"
1331 [(set (match_operand:DI 0 "register_operand" "=r,r")
1332 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1333 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1336 switch (which_alternative)
1339 if (operands[2] == const1_rtx)
1340 return "addq %r1,%r1,%0";
1342 return "s%P2addq %r1,0,%0";
1344 return "sll %r1,%2,%0";
1349 [(set_attr "type" "iadd,shift")])
1351 (define_insn "*ashldi_se"
1352 [(set (match_operand:DI 0 "register_operand" "=r")
1354 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1355 (match_operand:DI 2 "const_int_operand" "P"))
1357 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1359 if (operands[2] == const1_rtx)
1360 return "addl %r1,%r1,%0";
1362 return "s%P2addl %r1,0,%0";
1364 [(set_attr "type" "iadd")])
1366 (define_insn "lshrdi3"
1367 [(set (match_operand:DI 0 "register_operand" "=r")
1368 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1369 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1372 [(set_attr "type" "shift")])
1374 (define_insn "ashrdi3"
1375 [(set (match_operand:DI 0 "register_operand" "=r")
1376 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1377 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1380 [(set_attr "type" "shift")])
1382 (define_expand "extendqihi2"
1384 (ashift:DI (match_operand:QI 1 "some_operand" "")
1386 (set (match_operand:HI 0 "register_operand" "")
1387 (ashiftrt:DI (match_dup 2)
1393 emit_insn (gen_extendqihi2x (operands[0],
1394 force_reg (QImode, operands[1])));
1398 /* If we have an unaligned MEM, extend to DImode (which we do
1399 specially) and then copy to the result. */
1400 if (unaligned_memory_operand (operands[1], HImode))
1402 rtx temp = gen_reg_rtx (DImode);
1404 emit_insn (gen_extendqidi2 (temp, operands[1]));
1405 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1409 operands[0] = gen_lowpart (DImode, operands[0]);
1410 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1411 operands[2] = gen_reg_rtx (DImode);
1414 (define_insn "extendqidi2x"
1415 [(set (match_operand:DI 0 "register_operand" "=r")
1416 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1419 [(set_attr "type" "shift")])
1421 (define_insn "extendhidi2x"
1422 [(set (match_operand:DI 0 "register_operand" "=r")
1423 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1426 [(set_attr "type" "shift")])
1428 (define_insn "extendqisi2x"
1429 [(set (match_operand:SI 0 "register_operand" "=r")
1430 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1433 [(set_attr "type" "shift")])
1435 (define_insn "extendhisi2x"
1436 [(set (match_operand:SI 0 "register_operand" "=r")
1437 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1440 [(set_attr "type" "shift")])
1442 (define_insn "extendqihi2x"
1443 [(set (match_operand:HI 0 "register_operand" "=r")
1444 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1447 [(set_attr "type" "shift")])
1449 (define_expand "extendqisi2"
1451 (ashift:DI (match_operand:QI 1 "some_operand" "")
1453 (set (match_operand:SI 0 "register_operand" "")
1454 (ashiftrt:DI (match_dup 2)
1460 emit_insn (gen_extendqisi2x (operands[0],
1461 force_reg (QImode, operands[1])));
1465 /* If we have an unaligned MEM, extend to a DImode form of
1466 the result (which we do specially). */
1467 if (unaligned_memory_operand (operands[1], QImode))
1469 rtx temp = gen_reg_rtx (DImode);
1471 emit_insn (gen_extendqidi2 (temp, operands[1]));
1472 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1476 operands[0] = gen_lowpart (DImode, operands[0]);
1477 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1478 operands[2] = gen_reg_rtx (DImode);
1481 (define_expand "extendqidi2"
1483 (ashift:DI (match_operand:QI 1 "some_operand" "")
1485 (set (match_operand:DI 0 "register_operand" "")
1486 (ashiftrt:DI (match_dup 2)
1492 emit_insn (gen_extendqidi2x (operands[0],
1493 force_reg (QImode, operands[1])));
1497 if (unaligned_memory_operand (operands[1], QImode))
1500 = gen_unaligned_extendqidi (operands[0],
1501 get_unaligned_address (operands[1], 1));
1503 alpha_set_memflags (seq, operands[1]);
1508 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1509 operands[2] = gen_reg_rtx (DImode);
1512 (define_expand "extendhisi2"
1514 (ashift:DI (match_operand:HI 1 "some_operand" "")
1516 (set (match_operand:SI 0 "register_operand" "")
1517 (ashiftrt:DI (match_dup 2)
1523 emit_insn (gen_extendhisi2x (operands[0],
1524 force_reg (HImode, operands[1])));
1528 /* If we have an unaligned MEM, extend to a DImode form of
1529 the result (which we do specially). */
1530 if (unaligned_memory_operand (operands[1], HImode))
1532 rtx temp = gen_reg_rtx (DImode);
1534 emit_insn (gen_extendhidi2 (temp, operands[1]));
1535 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1539 operands[0] = gen_lowpart (DImode, operands[0]);
1540 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1541 operands[2] = gen_reg_rtx (DImode);
1544 (define_expand "extendhidi2"
1546 (ashift:DI (match_operand:HI 1 "some_operand" "")
1548 (set (match_operand:DI 0 "register_operand" "")
1549 (ashiftrt:DI (match_dup 2)
1555 emit_insn (gen_extendhidi2x (operands[0],
1556 force_reg (HImode, operands[1])));
1560 if (unaligned_memory_operand (operands[1], HImode))
1563 = gen_unaligned_extendhidi (operands[0],
1564 get_unaligned_address (operands[1], 2));
1566 alpha_set_memflags (seq, operands[1]);
1571 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1572 operands[2] = gen_reg_rtx (DImode);
1575 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1576 ;; as a pattern saves one instruction. The code is similar to that for
1577 ;; the unaligned loads (see below).
1579 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1580 (define_expand "unaligned_extendqidi"
1581 [(use (match_operand:QI 0 "register_operand" ""))
1582 (use (match_operand:DI 1 "address_operand" ""))]
1585 if (WORDS_BIG_ENDIAN)
1586 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1588 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1592 (define_expand "unaligned_extendqidi_le"
1593 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1595 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1598 (ashift:DI (match_dup 3)
1599 (minus:DI (const_int 64)
1601 (and:DI (match_dup 2) (const_int 7))
1603 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1604 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1605 "! WORDS_BIG_ENDIAN"
1607 operands[2] = gen_reg_rtx (DImode);
1608 operands[3] = gen_reg_rtx (DImode);
1609 operands[4] = gen_reg_rtx (DImode);
1612 (define_expand "unaligned_extendqidi_be"
1613 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1614 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1616 (mem:DI (and:DI (match_dup 3)
1618 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1620 (ashift:DI (match_dup 4)
1623 (plus:DI (match_dup 5) (const_int 1))
1626 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1627 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1630 operands[2] = gen_reg_rtx (DImode);
1631 operands[3] = gen_reg_rtx (DImode);
1632 operands[4] = gen_reg_rtx (DImode);
1633 operands[5] = gen_reg_rtx (DImode);
1634 operands[6] = gen_reg_rtx (DImode);
1637 (define_expand "unaligned_extendhidi"
1638 [(use (match_operand:QI 0 "register_operand" ""))
1639 (use (match_operand:DI 1 "address_operand" ""))]
1642 operands[0] = gen_lowpart (DImode, operands[0]);
1643 emit_insn ((WORDS_BIG_ENDIAN
1644 ? gen_unaligned_extendhidi_be
1645 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1649 (define_expand "unaligned_extendhidi_le"
1650 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1652 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1655 (ashift:DI (match_dup 3)
1656 (minus:DI (const_int 64)
1658 (and:DI (match_dup 2) (const_int 7))
1660 (set (match_operand:DI 0 "register_operand" "")
1661 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1662 "! WORDS_BIG_ENDIAN"
1664 operands[2] = gen_reg_rtx (DImode);
1665 operands[3] = gen_reg_rtx (DImode);
1666 operands[4] = gen_reg_rtx (DImode);
1669 (define_expand "unaligned_extendhidi_be"
1670 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1671 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1673 (mem:DI (and:DI (match_dup 3)
1675 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1677 (ashift:DI (match_dup 4)
1680 (plus:DI (match_dup 5) (const_int 1))
1683 (set (match_operand:DI 0 "register_operand" "")
1684 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1687 operands[2] = gen_reg_rtx (DImode);
1688 operands[3] = gen_reg_rtx (DImode);
1689 operands[4] = gen_reg_rtx (DImode);
1690 operands[5] = gen_reg_rtx (DImode);
1691 operands[6] = gen_reg_rtx (DImode);
1694 (define_insn "*extxl_const"
1695 [(set (match_operand:DI 0 "register_operand" "=r")
1696 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1697 (match_operand:DI 2 "mode_width_operand" "n")
1698 (match_operand:DI 3 "mul8_operand" "I")))]
1700 "ext%M2l %r1,%s3,%0"
1701 [(set_attr "type" "shift")])
1703 (define_insn "extxl_le"
1704 [(set (match_operand:DI 0 "register_operand" "=r")
1705 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1706 (match_operand:DI 2 "mode_width_operand" "n")
1707 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1709 "! WORDS_BIG_ENDIAN"
1711 [(set_attr "type" "shift")])
1713 (define_insn "extxl_be"
1714 [(set (match_operand:DI 0 "register_operand" "=r")
1715 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1716 (match_operand:DI 2 "mode_width_operand" "n")
1720 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1724 [(set_attr "type" "shift")])
1726 ;; Combine has some strange notion of preserving existing undefined behaviour
1727 ;; in shifts larger than a word size. So capture these patterns that it
1728 ;; should have turned into zero_extracts.
1730 (define_insn "*extxl_1_le"
1731 [(set (match_operand:DI 0 "register_operand" "=r")
1732 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1733 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1735 (match_operand:DI 3 "mode_mask_operand" "n")))]
1736 "! WORDS_BIG_ENDIAN"
1738 [(set_attr "type" "shift")])
1740 (define_insn "*extxl_1_be"
1741 [(set (match_operand:DI 0 "register_operand" "=r")
1742 (and:DI (lshiftrt:DI
1743 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1744 (minus:DI (const_int 56)
1745 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1747 (match_operand:DI 3 "mode_mask_operand" "n")))]
1750 [(set_attr "type" "shift")])
1752 (define_insn "*extql_2_le"
1753 [(set (match_operand:DI 0 "register_operand" "=r")
1754 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1755 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1757 "! WORDS_BIG_ENDIAN"
1759 [(set_attr "type" "shift")])
1761 (define_insn "*extql_2_be"
1762 [(set (match_operand:DI 0 "register_operand" "=r")
1764 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1765 (minus:DI (const_int 56)
1767 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1771 [(set_attr "type" "shift")])
1773 (define_insn "extqh_le"
1774 [(set (match_operand:DI 0 "register_operand" "=r")
1776 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1777 (minus:DI (const_int 64)
1780 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1783 "! WORDS_BIG_ENDIAN"
1785 [(set_attr "type" "shift")])
1787 (define_insn "extqh_be"
1788 [(set (match_operand:DI 0 "register_operand" "=r")
1790 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1793 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1799 [(set_attr "type" "shift")])
1801 (define_insn "extlh_le"
1802 [(set (match_operand:DI 0 "register_operand" "=r")
1804 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1805 (const_int 2147483647))
1806 (minus:DI (const_int 64)
1809 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1812 "! WORDS_BIG_ENDIAN"
1814 [(set_attr "type" "shift")])
1816 (define_insn "extlh_be"
1817 [(set (match_operand:DI 0 "register_operand" "=r")
1820 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1824 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1828 (const_int 2147483647)))]
1831 [(set_attr "type" "shift")])
1833 (define_insn "extwh_le"
1834 [(set (match_operand:DI 0 "register_operand" "=r")
1836 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1838 (minus:DI (const_int 64)
1841 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1844 "! WORDS_BIG_ENDIAN"
1846 [(set_attr "type" "shift")])
1848 (define_insn "extwh_be"
1849 [(set (match_operand:DI 0 "register_operand" "=r")
1851 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1855 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1859 (const_int 65535)))]
1862 [(set_attr "type" "shift")])
1864 ;; This converts an extXl into an extXh with an appropriate adjustment
1865 ;; to the address calculation.
1868 ;; [(set (match_operand:DI 0 "register_operand" "")
1869 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1870 ;; (match_operand:DI 2 "mode_width_operand" "")
1871 ;; (ashift:DI (match_operand:DI 3 "" "")
1873 ;; (match_operand:DI 4 "const_int_operand" "")))
1874 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1875 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1876 ;; [(set (match_dup 5) (match_dup 6))
1877 ;; (set (match_dup 0)
1878 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1879 ;; (ashift:DI (plus:DI (match_dup 5)
1885 ;; operands[6] = plus_constant (operands[3],
1886 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1887 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1890 (define_insn "*insbl_const"
1891 [(set (match_operand:DI 0 "register_operand" "=r")
1892 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1893 (match_operand:DI 2 "mul8_operand" "I")))]
1896 [(set_attr "type" "shift")])
1898 (define_insn "*inswl_const"
1899 [(set (match_operand:DI 0 "register_operand" "=r")
1900 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1901 (match_operand:DI 2 "mul8_operand" "I")))]
1904 [(set_attr "type" "shift")])
1906 (define_insn "*insll_const"
1907 [(set (match_operand:DI 0 "register_operand" "=r")
1908 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1909 (match_operand:DI 2 "mul8_operand" "I")))]
1912 [(set_attr "type" "shift")])
1914 (define_insn "insbl_le"
1915 [(set (match_operand:DI 0 "register_operand" "=r")
1916 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1917 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1919 "! WORDS_BIG_ENDIAN"
1921 [(set_attr "type" "shift")])
1923 (define_insn "insbl_be"
1924 [(set (match_operand:DI 0 "register_operand" "=r")
1925 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1926 (minus:DI (const_int 56)
1927 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1931 [(set_attr "type" "shift")])
1933 (define_insn "inswl_le"
1934 [(set (match_operand:DI 0 "register_operand" "=r")
1935 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1936 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1938 "! WORDS_BIG_ENDIAN"
1940 [(set_attr "type" "shift")])
1942 (define_insn "inswl_be"
1943 [(set (match_operand:DI 0 "register_operand" "=r")
1944 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1945 (minus:DI (const_int 56)
1946 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1950 [(set_attr "type" "shift")])
1952 (define_insn "insll_le"
1953 [(set (match_operand:DI 0 "register_operand" "=r")
1954 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1955 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1957 "! WORDS_BIG_ENDIAN"
1959 [(set_attr "type" "shift")])
1961 (define_insn "insll_be"
1962 [(set (match_operand:DI 0 "register_operand" "=r")
1963 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1964 (minus:DI (const_int 56)
1965 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1969 [(set_attr "type" "shift")])
1971 (define_insn "insql_le"
1972 [(set (match_operand:DI 0 "register_operand" "=r")
1973 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1974 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1976 "! WORDS_BIG_ENDIAN"
1978 [(set_attr "type" "shift")])
1980 (define_insn "insql_be"
1981 [(set (match_operand:DI 0 "register_operand" "=r")
1982 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1983 (minus:DI (const_int 56)
1984 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1988 [(set_attr "type" "shift")])
1990 ;; Combine has this sometimes habit of moving the and outside of the
1991 ;; shift, making life more interesting.
1993 (define_insn "*insxl"
1994 [(set (match_operand:DI 0 "register_operand" "=r")
1995 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1996 (match_operand:DI 2 "mul8_operand" "I"))
1997 (match_operand:DI 3 "immediate_operand" "i")))]
1998 "HOST_BITS_PER_WIDE_INT == 64
1999 && GET_CODE (operands[3]) == CONST_INT
2000 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2001 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2002 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2003 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2004 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2005 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2007 #if HOST_BITS_PER_WIDE_INT == 64
2008 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2009 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2010 return "insbl %1,%s2,%0";
2011 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2012 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2013 return "inswl %1,%s2,%0";
2014 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2015 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2016 return "insll %1,%s2,%0";
2020 [(set_attr "type" "shift")])
2022 ;; We do not include the insXh insns because they are complex to express
2023 ;; and it does not appear that we would ever want to generate them.
2025 ;; Since we need them for block moves, though, cop out and use unspec.
2027 (define_insn "insxh"
2028 [(set (match_operand:DI 0 "register_operand" "=r")
2029 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2030 (match_operand:DI 2 "mode_width_operand" "n")
2031 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2035 [(set_attr "type" "shift")])
2037 (define_insn "mskxl_le"
2038 [(set (match_operand:DI 0 "register_operand" "=r")
2039 (and:DI (not:DI (ashift:DI
2040 (match_operand:DI 2 "mode_mask_operand" "n")
2042 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2044 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2045 "! WORDS_BIG_ENDIAN"
2047 [(set_attr "type" "shift")])
2049 (define_insn "mskxl_be"
2050 [(set (match_operand:DI 0 "register_operand" "=r")
2051 (and:DI (not:DI (ashift:DI
2052 (match_operand:DI 2 "mode_mask_operand" "n")
2053 (minus:DI (const_int 56)
2055 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2057 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2060 [(set_attr "type" "shift")])
2062 ;; We do not include the mskXh insns because it does not appear we would
2063 ;; ever generate one.
2065 ;; Again, we do for block moves and we use unspec again.
2067 (define_insn "mskxh"
2068 [(set (match_operand:DI 0 "register_operand" "=r")
2069 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2070 (match_operand:DI 2 "mode_width_operand" "n")
2071 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2075 [(set_attr "type" "shift")])
2077 ;; Prefer AND + NE over LSHIFTRT + AND.
2079 (define_insn_and_split "*ze_and_ne"
2080 [(set (match_operand:DI 0 "register_operand" "=r")
2081 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2083 (match_operand 2 "const_int_operand" "I")))]
2084 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2086 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2088 (and:DI (match_dup 1) (match_dup 3)))
2090 (ne:DI (match_dup 0) (const_int 0)))]
2091 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2093 ;; Floating-point operations. All the double-precision insns can extend
2094 ;; from single, so indicate that. The exception are the ones that simply
2095 ;; play with the sign bits; it's not clear what to do there.
2097 (define_insn "abssf2"
2098 [(set (match_operand:SF 0 "register_operand" "=f")
2099 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2102 [(set_attr "type" "fcpys")])
2104 (define_insn "*nabssf2"
2105 [(set (match_operand:SF 0 "register_operand" "=f")
2106 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2109 [(set_attr "type" "fadd")])
2111 (define_insn "absdf2"
2112 [(set (match_operand:DF 0 "register_operand" "=f")
2113 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2116 [(set_attr "type" "fcpys")])
2118 (define_insn "*nabsdf2"
2119 [(set (match_operand:DF 0 "register_operand" "=f")
2120 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2123 [(set_attr "type" "fadd")])
2125 (define_expand "abstf2"
2126 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2127 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2128 (use (match_dup 2))])]
2129 "TARGET_HAS_XFLOATING_LIBS"
2131 #if HOST_BITS_PER_WIDE_INT >= 64
2132 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2134 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2138 (define_insn_and_split "*abstf_internal"
2139 [(set (match_operand:TF 0 "register_operand" "=r")
2140 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2141 (use (match_operand:DI 2 "register_operand" "r"))]
2142 "TARGET_HAS_XFLOATING_LIBS"
2144 "&& reload_completed"
2146 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2148 (define_insn "negsf2"
2149 [(set (match_operand:SF 0 "register_operand" "=f")
2150 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2153 [(set_attr "type" "fadd")])
2155 (define_insn "negdf2"
2156 [(set (match_operand:DF 0 "register_operand" "=f")
2157 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2160 [(set_attr "type" "fadd")])
2162 (define_expand "negtf2"
2163 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2164 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2165 (use (match_dup 2))])]
2166 "TARGET_HAS_XFLOATING_LIBS"
2168 #if HOST_BITS_PER_WIDE_INT >= 64
2169 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2171 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2175 (define_insn_and_split "*negtf_internal"
2176 [(set (match_operand:TF 0 "register_operand" "=r")
2177 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2178 (use (match_operand:DI 2 "register_operand" "r"))]
2179 "TARGET_HAS_XFLOATING_LIBS"
2181 "&& reload_completed"
2183 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2185 (define_insn "*addsf_ieee"
2186 [(set (match_operand:SF 0 "register_operand" "=&f")
2187 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2188 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2189 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2190 "add%,%/ %R1,%R2,%0"
2191 [(set_attr "type" "fadd")
2192 (set_attr "trap" "yes")
2193 (set_attr "round_suffix" "normal")
2194 (set_attr "trap_suffix" "u_su_sui")])
2196 (define_insn "addsf3"
2197 [(set (match_operand:SF 0 "register_operand" "=f")
2198 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2199 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2201 "add%,%/ %R1,%R2,%0"
2202 [(set_attr "type" "fadd")
2203 (set_attr "trap" "yes")
2204 (set_attr "round_suffix" "normal")
2205 (set_attr "trap_suffix" "u_su_sui")])
2207 (define_insn "*adddf_ieee"
2208 [(set (match_operand:DF 0 "register_operand" "=&f")
2209 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2210 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2211 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2212 "add%-%/ %R1,%R2,%0"
2213 [(set_attr "type" "fadd")
2214 (set_attr "trap" "yes")
2215 (set_attr "round_suffix" "normal")
2216 (set_attr "trap_suffix" "u_su_sui")])
2218 (define_insn "adddf3"
2219 [(set (match_operand:DF 0 "register_operand" "=f")
2220 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2221 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2223 "add%-%/ %R1,%R2,%0"
2224 [(set_attr "type" "fadd")
2225 (set_attr "trap" "yes")
2226 (set_attr "round_suffix" "normal")
2227 (set_attr "trap_suffix" "u_su_sui")])
2229 (define_insn "*adddf_ext1"
2230 [(set (match_operand:DF 0 "register_operand" "=f")
2231 (plus:DF (float_extend:DF
2232 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2233 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2234 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2235 "add%-%/ %R1,%R2,%0"
2236 [(set_attr "type" "fadd")
2237 (set_attr "trap" "yes")
2238 (set_attr "round_suffix" "normal")
2239 (set_attr "trap_suffix" "u_su_sui")])
2241 (define_insn "*adddf_ext2"
2242 [(set (match_operand:DF 0 "register_operand" "=f")
2243 (plus:DF (float_extend:DF
2244 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2246 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2247 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2248 "add%-%/ %R1,%R2,%0"
2249 [(set_attr "type" "fadd")
2250 (set_attr "trap" "yes")
2251 (set_attr "round_suffix" "normal")
2252 (set_attr "trap_suffix" "u_su_sui")])
2254 (define_expand "addtf3"
2255 [(use (match_operand 0 "register_operand" ""))
2256 (use (match_operand 1 "general_operand" ""))
2257 (use (match_operand 2 "general_operand" ""))]
2258 "TARGET_HAS_XFLOATING_LIBS"
2259 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2261 ;; Define conversion operators between DFmode and SImode, using the cvtql
2262 ;; instruction. To allow combine et al to do useful things, we keep the
2263 ;; operation as a unit until after reload, at which point we split the
2266 ;; Note that we (attempt to) only consider this optimization when the
2267 ;; ultimate destination is memory. If we will be doing further integer
2268 ;; processing, it is cheaper to do the truncation in the int regs.
2270 (define_insn "*cvtql"
2271 [(set (match_operand:SI 0 "register_operand" "=f")
2272 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2276 [(set_attr "type" "fadd")
2277 (set_attr "trap" "yes")
2278 (set_attr "trap_suffix" "v_sv")])
2280 (define_insn_and_split "*fix_truncdfsi_ieee"
2281 [(set (match_operand:SI 0 "memory_operand" "=m")
2282 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2283 (clobber (match_scratch:DI 2 "=&f"))
2284 (clobber (match_scratch:SI 3 "=&f"))]
2285 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2287 "&& reload_completed"
2288 [(set (match_dup 2) (fix:DI (match_dup 1)))
2289 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2290 (set (match_dup 0) (match_dup 3))]
2292 [(set_attr "type" "fadd")
2293 (set_attr "trap" "yes")])
2295 (define_insn_and_split "*fix_truncdfsi_internal"
2296 [(set (match_operand:SI 0 "memory_operand" "=m")
2297 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2298 (clobber (match_scratch:DI 2 "=f"))]
2299 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2301 "&& reload_completed"
2302 [(set (match_dup 2) (fix:DI (match_dup 1)))
2303 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2304 (set (match_dup 0) (match_dup 3))]
2305 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2306 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2307 [(set_attr "type" "fadd")
2308 (set_attr "trap" "yes")])
2310 (define_insn "*fix_truncdfdi_ieee"
2311 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2312 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2313 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2315 [(set_attr "type" "fadd")
2316 (set_attr "trap" "yes")
2317 (set_attr "round_suffix" "c")
2318 (set_attr "trap_suffix" "v_sv_svi")])
2320 (define_insn "fix_truncdfdi2"
2321 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2322 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2325 [(set_attr "type" "fadd")
2326 (set_attr "trap" "yes")
2327 (set_attr "round_suffix" "c")
2328 (set_attr "trap_suffix" "v_sv_svi")])
2330 ;; Likewise between SFmode and SImode.
2332 (define_insn_and_split "*fix_truncsfsi_ieee"
2333 [(set (match_operand:SI 0 "memory_operand" "=m")
2334 (subreg:SI (fix:DI (float_extend:DF
2335 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2336 (clobber (match_scratch:DI 2 "=&f"))
2337 (clobber (match_scratch:SI 3 "=&f"))]
2338 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2340 "&& reload_completed"
2341 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2342 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2343 (set (match_dup 0) (match_dup 3))]
2345 [(set_attr "type" "fadd")
2346 (set_attr "trap" "yes")])
2348 (define_insn_and_split "*fix_truncsfsi_internal"
2349 [(set (match_operand:SI 0 "memory_operand" "=m")
2350 (subreg:SI (fix:DI (float_extend:DF
2351 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2352 (clobber (match_scratch:DI 2 "=f"))]
2353 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2355 "&& reload_completed"
2356 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2357 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2358 (set (match_dup 0) (match_dup 3))]
2359 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2360 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2361 [(set_attr "type" "fadd")
2362 (set_attr "trap" "yes")])
2364 (define_insn "*fix_truncsfdi_ieee"
2365 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2366 (fix:DI (float_extend:DF
2367 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2368 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2370 [(set_attr "type" "fadd")
2371 (set_attr "trap" "yes")
2372 (set_attr "round_suffix" "c")
2373 (set_attr "trap_suffix" "v_sv_svi")])
2375 (define_insn "fix_truncsfdi2"
2376 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2377 (fix:DI (float_extend:DF
2378 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2381 [(set_attr "type" "fadd")
2382 (set_attr "trap" "yes")
2383 (set_attr "round_suffix" "c")
2384 (set_attr "trap_suffix" "v_sv_svi")])
2386 (define_expand "fix_trunctfdi2"
2387 [(use (match_operand:DI 0 "register_operand" ""))
2388 (use (match_operand:TF 1 "general_operand" ""))]
2389 "TARGET_HAS_XFLOATING_LIBS"
2390 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2392 (define_insn "*floatdisf_ieee"
2393 [(set (match_operand:SF 0 "register_operand" "=&f")
2394 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2395 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2397 [(set_attr "type" "fadd")
2398 (set_attr "trap" "yes")
2399 (set_attr "round_suffix" "normal")
2400 (set_attr "trap_suffix" "sui")])
2402 (define_insn "floatdisf2"
2403 [(set (match_operand:SF 0 "register_operand" "=f")
2404 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2407 [(set_attr "type" "fadd")
2408 (set_attr "trap" "yes")
2409 (set_attr "round_suffix" "normal")
2410 (set_attr "trap_suffix" "sui")])
2412 (define_insn "*floatdidf_ieee"
2413 [(set (match_operand:DF 0 "register_operand" "=&f")
2414 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2415 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2417 [(set_attr "type" "fadd")
2418 (set_attr "trap" "yes")
2419 (set_attr "round_suffix" "normal")
2420 (set_attr "trap_suffix" "sui")])
2422 (define_insn "floatdidf2"
2423 [(set (match_operand:DF 0 "register_operand" "=f")
2424 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2427 [(set_attr "type" "fadd")
2428 (set_attr "trap" "yes")
2429 (set_attr "round_suffix" "normal")
2430 (set_attr "trap_suffix" "sui")])
2432 (define_expand "floatditf2"
2433 [(use (match_operand:TF 0 "register_operand" ""))
2434 (use (match_operand:DI 1 "general_operand" ""))]
2435 "TARGET_HAS_XFLOATING_LIBS"
2436 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2438 (define_expand "floatunsdisf2"
2439 [(use (match_operand:SF 0 "register_operand" ""))
2440 (use (match_operand:DI 1 "register_operand" ""))]
2442 "alpha_emit_floatuns (operands); DONE;")
2444 (define_expand "floatunsdidf2"
2445 [(use (match_operand:DF 0 "register_operand" ""))
2446 (use (match_operand:DI 1 "register_operand" ""))]
2448 "alpha_emit_floatuns (operands); DONE;")
2450 (define_expand "floatunsditf2"
2451 [(use (match_operand:TF 0 "register_operand" ""))
2452 (use (match_operand:DI 1 "general_operand" ""))]
2453 "TARGET_HAS_XFLOATING_LIBS"
2454 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2456 (define_expand "extendsfdf2"
2457 [(set (match_operand:DF 0 "register_operand" "")
2458 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2461 if (alpha_fptm >= ALPHA_FPTM_SU)
2462 operands[1] = force_reg (SFmode, operands[1]);
2465 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2466 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2468 (define_insn "*extendsfdf2_ieee"
2469 [(set (match_operand:DF 0 "register_operand" "=&f")
2470 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2471 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2473 [(set_attr "type" "fadd")
2474 (set_attr "trap" "yes")])
2476 (define_insn "*extendsfdf2_internal"
2477 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2478 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2479 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2484 [(set_attr "type" "fcpys,fld,fst")])
2486 (define_expand "extendsftf2"
2487 [(use (match_operand:TF 0 "register_operand" ""))
2488 (use (match_operand:SF 1 "general_operand" ""))]
2489 "TARGET_HAS_XFLOATING_LIBS"
2491 rtx tmp = gen_reg_rtx (DFmode);
2492 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2493 emit_insn (gen_extenddftf2 (operands[0], tmp));
2497 (define_expand "extenddftf2"
2498 [(use (match_operand:TF 0 "register_operand" ""))
2499 (use (match_operand:DF 1 "general_operand" ""))]
2500 "TARGET_HAS_XFLOATING_LIBS"
2501 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2503 (define_insn "*truncdfsf2_ieee"
2504 [(set (match_operand:SF 0 "register_operand" "=&f")
2505 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2506 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2508 [(set_attr "type" "fadd")
2509 (set_attr "trap" "yes")
2510 (set_attr "round_suffix" "normal")
2511 (set_attr "trap_suffix" "u_su_sui")])
2513 (define_insn "truncdfsf2"
2514 [(set (match_operand:SF 0 "register_operand" "=f")
2515 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2518 [(set_attr "type" "fadd")
2519 (set_attr "trap" "yes")
2520 (set_attr "round_suffix" "normal")
2521 (set_attr "trap_suffix" "u_su_sui")])
2523 (define_expand "trunctfdf2"
2524 [(use (match_operand:DF 0 "register_operand" ""))
2525 (use (match_operand:TF 1 "general_operand" ""))]
2526 "TARGET_HAS_XFLOATING_LIBS"
2527 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2529 (define_expand "trunctfsf2"
2530 [(use (match_operand:SF 0 "register_operand" ""))
2531 (use (match_operand:TF 1 "general_operand" ""))]
2532 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2534 rtx tmpf, sticky, arg, lo, hi;
2536 tmpf = gen_reg_rtx (DFmode);
2537 sticky = gen_reg_rtx (DImode);
2538 arg = copy_to_mode_reg (TFmode, operands[1]);
2539 lo = gen_lowpart (DImode, arg);
2540 hi = gen_highpart (DImode, arg);
2542 /* Convert the low word of the TFmode value into a sticky rounding bit,
2543 then or it into the low bit of the high word. This leaves the sticky
2544 bit at bit 48 of the fraction, which is representable in DFmode,
2545 which prevents rounding error in the final conversion to SFmode. */
2547 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2548 gen_rtx_NE (DImode, lo, const0_rtx)));
2549 emit_insn (gen_iordi3 (hi, hi, sticky));
2550 emit_insn (gen_trunctfdf2 (tmpf, arg));
2551 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2555 (define_insn "*divsf3_ieee"
2556 [(set (match_operand:SF 0 "register_operand" "=&f")
2557 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2558 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2559 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2560 "div%,%/ %R1,%R2,%0"
2561 [(set_attr "type" "fdiv")
2562 (set_attr "opsize" "si")
2563 (set_attr "trap" "yes")
2564 (set_attr "round_suffix" "normal")
2565 (set_attr "trap_suffix" "u_su_sui")])
2567 (define_insn "divsf3"
2568 [(set (match_operand:SF 0 "register_operand" "=f")
2569 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2570 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2572 "div%,%/ %R1,%R2,%0"
2573 [(set_attr "type" "fdiv")
2574 (set_attr "opsize" "si")
2575 (set_attr "trap" "yes")
2576 (set_attr "round_suffix" "normal")
2577 (set_attr "trap_suffix" "u_su_sui")])
2579 (define_insn "*divdf3_ieee"
2580 [(set (match_operand:DF 0 "register_operand" "=&f")
2581 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2582 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2583 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2584 "div%-%/ %R1,%R2,%0"
2585 [(set_attr "type" "fdiv")
2586 (set_attr "trap" "yes")
2587 (set_attr "round_suffix" "normal")
2588 (set_attr "trap_suffix" "u_su_sui")])
2590 (define_insn "divdf3"
2591 [(set (match_operand:DF 0 "register_operand" "=f")
2592 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2593 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2595 "div%-%/ %R1,%R2,%0"
2596 [(set_attr "type" "fdiv")
2597 (set_attr "trap" "yes")
2598 (set_attr "round_suffix" "normal")
2599 (set_attr "trap_suffix" "u_su_sui")])
2601 (define_insn "*divdf_ext1"
2602 [(set (match_operand:DF 0 "register_operand" "=f")
2603 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2604 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2605 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2606 "div%-%/ %R1,%R2,%0"
2607 [(set_attr "type" "fdiv")
2608 (set_attr "trap" "yes")
2609 (set_attr "round_suffix" "normal")
2610 (set_attr "trap_suffix" "u_su_sui")])
2612 (define_insn "*divdf_ext2"
2613 [(set (match_operand:DF 0 "register_operand" "=f")
2614 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2616 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2617 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2618 "div%-%/ %R1,%R2,%0"
2619 [(set_attr "type" "fdiv")
2620 (set_attr "trap" "yes")
2621 (set_attr "round_suffix" "normal")
2622 (set_attr "trap_suffix" "u_su_sui")])
2624 (define_insn "*divdf_ext3"
2625 [(set (match_operand:DF 0 "register_operand" "=f")
2626 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2627 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2628 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2629 "div%-%/ %R1,%R2,%0"
2630 [(set_attr "type" "fdiv")
2631 (set_attr "trap" "yes")
2632 (set_attr "round_suffix" "normal")
2633 (set_attr "trap_suffix" "u_su_sui")])
2635 (define_expand "divtf3"
2636 [(use (match_operand 0 "register_operand" ""))
2637 (use (match_operand 1 "general_operand" ""))
2638 (use (match_operand 2 "general_operand" ""))]
2639 "TARGET_HAS_XFLOATING_LIBS"
2640 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2642 (define_insn "*mulsf3_ieee"
2643 [(set (match_operand:SF 0 "register_operand" "=&f")
2644 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2645 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2646 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2647 "mul%,%/ %R1,%R2,%0"
2648 [(set_attr "type" "fmul")
2649 (set_attr "trap" "yes")
2650 (set_attr "round_suffix" "normal")
2651 (set_attr "trap_suffix" "u_su_sui")])
2653 (define_insn "mulsf3"
2654 [(set (match_operand:SF 0 "register_operand" "=f")
2655 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2656 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2658 "mul%,%/ %R1,%R2,%0"
2659 [(set_attr "type" "fmul")
2660 (set_attr "trap" "yes")
2661 (set_attr "round_suffix" "normal")
2662 (set_attr "trap_suffix" "u_su_sui")])
2664 (define_insn "*muldf3_ieee"
2665 [(set (match_operand:DF 0 "register_operand" "=&f")
2666 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2667 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2668 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2669 "mul%-%/ %R1,%R2,%0"
2670 [(set_attr "type" "fmul")
2671 (set_attr "trap" "yes")
2672 (set_attr "round_suffix" "normal")
2673 (set_attr "trap_suffix" "u_su_sui")])
2675 (define_insn "muldf3"
2676 [(set (match_operand:DF 0 "register_operand" "=f")
2677 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2678 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2680 "mul%-%/ %R1,%R2,%0"
2681 [(set_attr "type" "fmul")
2682 (set_attr "trap" "yes")
2683 (set_attr "round_suffix" "normal")
2684 (set_attr "trap_suffix" "u_su_sui")])
2686 (define_insn "*muldf_ext1"
2687 [(set (match_operand:DF 0 "register_operand" "=f")
2688 (mult:DF (float_extend:DF
2689 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2690 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2691 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2692 "mul%-%/ %R1,%R2,%0"
2693 [(set_attr "type" "fmul")
2694 (set_attr "trap" "yes")
2695 (set_attr "round_suffix" "normal")
2696 (set_attr "trap_suffix" "u_su_sui")])
2698 (define_insn "*muldf_ext2"
2699 [(set (match_operand:DF 0 "register_operand" "=f")
2700 (mult:DF (float_extend:DF
2701 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2703 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2704 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2705 "mul%-%/ %R1,%R2,%0"
2706 [(set_attr "type" "fmul")
2707 (set_attr "trap" "yes")
2708 (set_attr "round_suffix" "normal")
2709 (set_attr "trap_suffix" "u_su_sui")])
2711 (define_expand "multf3"
2712 [(use (match_operand 0 "register_operand" ""))
2713 (use (match_operand 1 "general_operand" ""))
2714 (use (match_operand 2 "general_operand" ""))]
2715 "TARGET_HAS_XFLOATING_LIBS"
2716 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2718 (define_insn "*subsf3_ieee"
2719 [(set (match_operand:SF 0 "register_operand" "=&f")
2720 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2721 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2722 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2723 "sub%,%/ %R1,%R2,%0"
2724 [(set_attr "type" "fadd")
2725 (set_attr "trap" "yes")
2726 (set_attr "round_suffix" "normal")
2727 (set_attr "trap_suffix" "u_su_sui")])
2729 (define_insn "subsf3"
2730 [(set (match_operand:SF 0 "register_operand" "=f")
2731 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2732 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2734 "sub%,%/ %R1,%R2,%0"
2735 [(set_attr "type" "fadd")
2736 (set_attr "trap" "yes")
2737 (set_attr "round_suffix" "normal")
2738 (set_attr "trap_suffix" "u_su_sui")])
2740 (define_insn "*subdf3_ieee"
2741 [(set (match_operand:DF 0 "register_operand" "=&f")
2742 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2743 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2744 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2745 "sub%-%/ %R1,%R2,%0"
2746 [(set_attr "type" "fadd")
2747 (set_attr "trap" "yes")
2748 (set_attr "round_suffix" "normal")
2749 (set_attr "trap_suffix" "u_su_sui")])
2751 (define_insn "subdf3"
2752 [(set (match_operand:DF 0 "register_operand" "=f")
2753 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2754 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2756 "sub%-%/ %R1,%R2,%0"
2757 [(set_attr "type" "fadd")
2758 (set_attr "trap" "yes")
2759 (set_attr "round_suffix" "normal")
2760 (set_attr "trap_suffix" "u_su_sui")])
2762 (define_insn "*subdf_ext1"
2763 [(set (match_operand:DF 0 "register_operand" "=f")
2764 (minus:DF (float_extend:DF
2765 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2766 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2767 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2768 "sub%-%/ %R1,%R2,%0"
2769 [(set_attr "type" "fadd")
2770 (set_attr "trap" "yes")
2771 (set_attr "round_suffix" "normal")
2772 (set_attr "trap_suffix" "u_su_sui")])
2774 (define_insn "*subdf_ext2"
2775 [(set (match_operand:DF 0 "register_operand" "=f")
2776 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2778 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2779 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2780 "sub%-%/ %R1,%R2,%0"
2781 [(set_attr "type" "fadd")
2782 (set_attr "trap" "yes")
2783 (set_attr "round_suffix" "normal")
2784 (set_attr "trap_suffix" "u_su_sui")])
2786 (define_insn "*subdf_ext3"
2787 [(set (match_operand:DF 0 "register_operand" "=f")
2788 (minus:DF (float_extend:DF
2789 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2791 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2792 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2793 "sub%-%/ %R1,%R2,%0"
2794 [(set_attr "type" "fadd")
2795 (set_attr "trap" "yes")
2796 (set_attr "round_suffix" "normal")
2797 (set_attr "trap_suffix" "u_su_sui")])
2799 (define_expand "subtf3"
2800 [(use (match_operand 0 "register_operand" ""))
2801 (use (match_operand 1 "general_operand" ""))
2802 (use (match_operand 2 "general_operand" ""))]
2803 "TARGET_HAS_XFLOATING_LIBS"
2804 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2806 (define_insn "*sqrtsf2_ieee"
2807 [(set (match_operand:SF 0 "register_operand" "=&f")
2808 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2809 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2811 [(set_attr "type" "fsqrt")
2812 (set_attr "opsize" "si")
2813 (set_attr "trap" "yes")
2814 (set_attr "round_suffix" "normal")
2815 (set_attr "trap_suffix" "u_su_sui")])
2817 (define_insn "sqrtsf2"
2818 [(set (match_operand:SF 0 "register_operand" "=f")
2819 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2820 "TARGET_FP && TARGET_FIX"
2822 [(set_attr "type" "fsqrt")
2823 (set_attr "opsize" "si")
2824 (set_attr "trap" "yes")
2825 (set_attr "round_suffix" "normal")
2826 (set_attr "trap_suffix" "u_su_sui")])
2828 (define_insn "*sqrtdf2_ieee"
2829 [(set (match_operand:DF 0 "register_operand" "=&f")
2830 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2831 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2833 [(set_attr "type" "fsqrt")
2834 (set_attr "trap" "yes")
2835 (set_attr "round_suffix" "normal")
2836 (set_attr "trap_suffix" "u_su_sui")])
2838 (define_insn "sqrtdf2"
2839 [(set (match_operand:DF 0 "register_operand" "=f")
2840 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2841 "TARGET_FP && TARGET_FIX"
2843 [(set_attr "type" "fsqrt")
2844 (set_attr "trap" "yes")
2845 (set_attr "round_suffix" "normal")
2846 (set_attr "trap_suffix" "u_su_sui")])
2848 ;; Next are all the integer comparisons, and conditional moves and branches
2849 ;; and some of the related define_expand's and define_split's.
2851 (define_insn "*setcc_internal"
2852 [(set (match_operand 0 "register_operand" "=r")
2853 (match_operator 1 "alpha_comparison_operator"
2854 [(match_operand:DI 2 "register_operand" "r")
2855 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2856 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2857 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2858 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2860 [(set_attr "type" "icmp")])
2862 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2863 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2865 (define_insn "*setcc_swapped_internal"
2866 [(set (match_operand 0 "register_operand" "=r")
2867 (match_operator 1 "alpha_swapped_comparison_operator"
2868 [(match_operand:DI 2 "register_operand" "r")
2869 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2870 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2871 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2872 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2874 [(set_attr "type" "icmp")])
2876 ;; Use match_operator rather than ne directly so that we can match
2877 ;; multiple integer modes.
2878 (define_insn "*setne_internal"
2879 [(set (match_operand 0 "register_operand" "=r")
2880 (match_operator 1 "signed_comparison_operator"
2881 [(match_operand:DI 2 "register_operand" "r")
2883 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2884 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2885 && GET_CODE (operands[1]) == NE
2886 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2888 [(set_attr "type" "icmp")])
2890 ;; The mode folding trick can't be used with const_int operands, since
2891 ;; reload needs to know the proper mode.
2893 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2894 ;; in order to create more pairs of constants. As long as we're allowing
2895 ;; two constants at the same time, and will have to reload one of them...
2897 (define_insn "*movqicc_internal"
2898 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2900 (match_operator 2 "signed_comparison_operator"
2901 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2902 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2903 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2904 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2905 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2911 [(set_attr "type" "icmov")])
2913 (define_insn "*movhicc_internal"
2914 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2916 (match_operator 2 "signed_comparison_operator"
2917 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2918 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2919 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2920 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2921 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2927 [(set_attr "type" "icmov")])
2929 (define_insn "*movsicc_internal"
2930 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2932 (match_operator 2 "signed_comparison_operator"
2933 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2934 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2935 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2936 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2937 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2943 [(set_attr "type" "icmov")])
2945 (define_insn "*movdicc_internal"
2946 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2948 (match_operator 2 "signed_comparison_operator"
2949 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2950 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2951 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2952 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2953 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2959 [(set_attr "type" "icmov")])
2961 (define_insn "*movqicc_lbc"
2962 [(set (match_operand:QI 0 "register_operand" "=r,r")
2964 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2968 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2969 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2974 [(set_attr "type" "icmov")])
2976 (define_insn "*movhicc_lbc"
2977 [(set (match_operand:HI 0 "register_operand" "=r,r")
2979 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2983 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2984 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2989 [(set_attr "type" "icmov")])
2991 (define_insn "*movsicc_lbc"
2992 [(set (match_operand:SI 0 "register_operand" "=r,r")
2994 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2998 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2999 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3004 [(set_attr "type" "icmov")])
3006 (define_insn "*movdicc_lbc"
3007 [(set (match_operand:DI 0 "register_operand" "=r,r")
3009 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3013 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3014 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3019 [(set_attr "type" "icmov")])
3021 (define_insn "*movqicc_lbs"
3022 [(set (match_operand:QI 0 "register_operand" "=r,r")
3024 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3028 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3029 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3034 [(set_attr "type" "icmov")])
3036 (define_insn "*movhicc_lbs"
3037 [(set (match_operand:HI 0 "register_operand" "=r,r")
3039 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3043 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3044 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3049 [(set_attr "type" "icmov")])
3051 (define_insn "*movsicc_lbs"
3052 [(set (match_operand:SI 0 "register_operand" "=r,r")
3054 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3058 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3059 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3064 [(set_attr "type" "icmov")])
3066 (define_insn "*movdicc_lbs"
3067 [(set (match_operand:DI 0 "register_operand" "=r,r")
3069 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3073 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3074 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3079 [(set_attr "type" "icmov")])
3081 ;; For ABS, we have two choices, depending on whether the input and output
3082 ;; registers are the same or not.
3083 (define_expand "absdi2"
3084 [(set (match_operand:DI 0 "register_operand" "")
3085 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3088 if (rtx_equal_p (operands[0], operands[1]))
3089 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3091 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3095 (define_expand "absdi2_same"
3096 [(set (match_operand:DI 1 "register_operand" "")
3097 (neg:DI (match_operand:DI 0 "register_operand" "")))
3099 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3105 (define_expand "absdi2_diff"
3106 [(set (match_operand:DI 0 "register_operand" "")
3107 (neg:DI (match_operand:DI 1 "register_operand" "")))
3109 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3116 [(set (match_operand:DI 0 "register_operand" "")
3117 (abs:DI (match_dup 0)))
3118 (clobber (match_operand:DI 1 "register_operand" ""))]
3120 [(set (match_dup 1) (neg:DI (match_dup 0)))
3121 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3122 (match_dup 0) (match_dup 1)))]
3126 [(set (match_operand:DI 0 "register_operand" "")
3127 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3128 "! rtx_equal_p (operands[0], operands[1])"
3129 [(set (match_dup 0) (neg:DI (match_dup 1)))
3130 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3131 (match_dup 0) (match_dup 1)))]
3135 [(set (match_operand:DI 0 "register_operand" "")
3136 (neg:DI (abs:DI (match_dup 0))))
3137 (clobber (match_operand:DI 1 "register_operand" ""))]
3139 [(set (match_dup 1) (neg:DI (match_dup 0)))
3140 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3141 (match_dup 0) (match_dup 1)))]
3145 [(set (match_operand:DI 0 "register_operand" "")
3146 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3147 "! rtx_equal_p (operands[0], operands[1])"
3148 [(set (match_dup 0) (neg:DI (match_dup 1)))
3149 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3150 (match_dup 0) (match_dup 1)))]
3153 (define_insn "sminqi3"
3154 [(set (match_operand:QI 0 "register_operand" "=r")
3155 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3156 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3159 [(set_attr "type" "mvi")])
3161 (define_insn "uminqi3"
3162 [(set (match_operand:QI 0 "register_operand" "=r")
3163 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3164 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3167 [(set_attr "type" "mvi")])
3169 (define_insn "smaxqi3"
3170 [(set (match_operand:QI 0 "register_operand" "=r")
3171 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3172 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3175 [(set_attr "type" "mvi")])
3177 (define_insn "umaxqi3"
3178 [(set (match_operand:QI 0 "register_operand" "=r")
3179 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3180 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3183 [(set_attr "type" "mvi")])
3185 (define_insn "sminhi3"
3186 [(set (match_operand:HI 0 "register_operand" "=r")
3187 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3188 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3191 [(set_attr "type" "mvi")])
3193 (define_insn "uminhi3"
3194 [(set (match_operand:HI 0 "register_operand" "=r")
3195 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3196 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3199 [(set_attr "type" "mvi")])
3201 (define_insn "smaxhi3"
3202 [(set (match_operand:HI 0 "register_operand" "=r")
3203 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3204 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3207 [(set_attr "type" "mvi")])
3209 (define_insn "umaxhi3"
3210 [(set (match_operand:HI 0 "register_operand" "=r")
3211 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3212 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3215 [(set_attr "type" "shift")])
3217 (define_expand "smaxdi3"
3219 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3220 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3221 (set (match_operand:DI 0 "register_operand" "")
3222 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3223 (match_dup 1) (match_dup 2)))]
3225 { operands[3] = gen_reg_rtx (DImode); })
3228 [(set (match_operand:DI 0 "register_operand" "")
3229 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3230 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3231 (clobber (match_operand:DI 3 "register_operand" ""))]
3232 "operands[2] != const0_rtx"
3233 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3234 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3235 (match_dup 1) (match_dup 2)))]
3238 (define_insn "*smax_const0"
3239 [(set (match_operand:DI 0 "register_operand" "=r")
3240 (smax:DI (match_operand:DI 1 "register_operand" "0")
3244 [(set_attr "type" "icmov")])
3246 (define_expand "smindi3"
3248 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3249 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3250 (set (match_operand:DI 0 "register_operand" "")
3251 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3252 (match_dup 1) (match_dup 2)))]
3254 { operands[3] = gen_reg_rtx (DImode); })
3257 [(set (match_operand:DI 0 "register_operand" "")
3258 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3259 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3260 (clobber (match_operand:DI 3 "register_operand" ""))]
3261 "operands[2] != const0_rtx"
3262 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3263 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3264 (match_dup 1) (match_dup 2)))]
3267 (define_insn "*smin_const0"
3268 [(set (match_operand:DI 0 "register_operand" "=r")
3269 (smin:DI (match_operand:DI 1 "register_operand" "0")
3273 [(set_attr "type" "icmov")])
3275 (define_expand "umaxdi3"
3277 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3278 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3279 (set (match_operand:DI 0 "register_operand" "")
3280 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3281 (match_dup 1) (match_dup 2)))]
3283 "operands[3] = gen_reg_rtx (DImode);")
3286 [(set (match_operand:DI 0 "register_operand" "")
3287 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3288 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3289 (clobber (match_operand:DI 3 "register_operand" ""))]
3290 "operands[2] != const0_rtx"
3291 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3292 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3293 (match_dup 1) (match_dup 2)))]
3296 (define_expand "umindi3"
3298 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3299 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3300 (set (match_operand:DI 0 "register_operand" "")
3301 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3302 (match_dup 1) (match_dup 2)))]
3304 "operands[3] = gen_reg_rtx (DImode);")
3307 [(set (match_operand:DI 0 "register_operand" "")
3308 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3309 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3310 (clobber (match_operand:DI 3 "register_operand" ""))]
3311 "operands[2] != const0_rtx"
3312 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3313 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3314 (match_dup 1) (match_dup 2)))]
3317 (define_insn "*bcc_normal"
3320 (match_operator 1 "signed_comparison_operator"
3321 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3323 (label_ref (match_operand 0 "" ""))
3327 [(set_attr "type" "ibr")])
3329 (define_insn "*bcc_reverse"
3332 (match_operator 1 "signed_comparison_operator"
3333 [(match_operand:DI 2 "register_operand" "r")
3337 (label_ref (match_operand 0 "" ""))))]
3340 [(set_attr "type" "ibr")])
3342 (define_insn "*blbs_normal"
3345 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3349 (label_ref (match_operand 0 "" ""))
3353 [(set_attr "type" "ibr")])
3355 (define_insn "*blbc_normal"
3358 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3362 (label_ref (match_operand 0 "" ""))
3366 [(set_attr "type" "ibr")])
3372 (match_operator 1 "comparison_operator"
3373 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3375 (match_operand:DI 3 "const_int_operand" ""))
3377 (label_ref (match_operand 0 "" ""))
3379 (clobber (match_operand:DI 4 "register_operand" ""))])]
3380 "INTVAL (operands[3]) != 0"
3382 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3384 (if_then_else (match_op_dup 1
3385 [(zero_extract:DI (match_dup 4)
3389 (label_ref (match_dup 0))
3393 ;; The following are the corresponding floating-point insns. Recall
3394 ;; we need to have variants that expand the arguments from SFmode
3397 (define_insn "*cmpdf_ieee"
3398 [(set (match_operand:DF 0 "register_operand" "=&f")
3399 (match_operator:DF 1 "alpha_fp_comparison_operator"
3400 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3401 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3402 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3403 "cmp%-%C1%/ %R2,%R3,%0"
3404 [(set_attr "type" "fadd")
3405 (set_attr "trap" "yes")
3406 (set_attr "trap_suffix" "su")])
3408 (define_insn "*cmpdf_internal"
3409 [(set (match_operand:DF 0 "register_operand" "=f")
3410 (match_operator:DF 1 "alpha_fp_comparison_operator"
3411 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3412 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3413 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3414 "cmp%-%C1%/ %R2,%R3,%0"
3415 [(set_attr "type" "fadd")
3416 (set_attr "trap" "yes")
3417 (set_attr "trap_suffix" "su")])
3419 (define_insn "*cmpdf_ieee_ext1"
3420 [(set (match_operand:DF 0 "register_operand" "=&f")
3421 (match_operator:DF 1 "alpha_fp_comparison_operator"
3423 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3424 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3425 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3426 "cmp%-%C1%/ %R2,%R3,%0"
3427 [(set_attr "type" "fadd")
3428 (set_attr "trap" "yes")
3429 (set_attr "trap_suffix" "su")])
3431 (define_insn "*cmpdf_ext1"
3432 [(set (match_operand:DF 0 "register_operand" "=f")
3433 (match_operator:DF 1 "alpha_fp_comparison_operator"
3435 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3436 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3437 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3438 "cmp%-%C1%/ %R2,%R3,%0"
3439 [(set_attr "type" "fadd")
3440 (set_attr "trap" "yes")
3441 (set_attr "trap_suffix" "su")])
3443 (define_insn "*cmpdf_ieee_ext2"
3444 [(set (match_operand:DF 0 "register_operand" "=&f")
3445 (match_operator:DF 1 "alpha_fp_comparison_operator"
3446 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3448 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3449 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3450 "cmp%-%C1%/ %R2,%R3,%0"
3451 [(set_attr "type" "fadd")
3452 (set_attr "trap" "yes")
3453 (set_attr "trap_suffix" "su")])
3455 (define_insn "*cmpdf_ext2"
3456 [(set (match_operand:DF 0 "register_operand" "=f")
3457 (match_operator:DF 1 "alpha_fp_comparison_operator"
3458 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3460 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3461 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3462 "cmp%-%C1%/ %R2,%R3,%0"
3463 [(set_attr "type" "fadd")
3464 (set_attr "trap" "yes")
3465 (set_attr "trap_suffix" "su")])
3467 (define_insn "*cmpdf_ieee_ext3"
3468 [(set (match_operand:DF 0 "register_operand" "=&f")
3469 (match_operator:DF 1 "alpha_fp_comparison_operator"
3471 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3473 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3474 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3475 "cmp%-%C1%/ %R2,%R3,%0"
3476 [(set_attr "type" "fadd")
3477 (set_attr "trap" "yes")
3478 (set_attr "trap_suffix" "su")])
3480 (define_insn "*cmpdf_ext3"
3481 [(set (match_operand:DF 0 "register_operand" "=f")
3482 (match_operator:DF 1 "alpha_fp_comparison_operator"
3484 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3486 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3487 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3488 "cmp%-%C1%/ %R2,%R3,%0"
3489 [(set_attr "type" "fadd")
3490 (set_attr "trap" "yes")
3491 (set_attr "trap_suffix" "su")])
3493 (define_insn "*movdfcc_internal"
3494 [(set (match_operand:DF 0 "register_operand" "=f,f")
3496 (match_operator 3 "signed_comparison_operator"
3497 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3498 (match_operand:DF 2 "fp0_operand" "G,G")])
3499 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3500 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3504 fcmov%D3 %R4,%R5,%0"
3505 [(set_attr "type" "fcmov")])
3507 (define_insn "*movsfcc_internal"
3508 [(set (match_operand:SF 0 "register_operand" "=f,f")
3510 (match_operator 3 "signed_comparison_operator"
3511 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3512 (match_operand:DF 2 "fp0_operand" "G,G")])
3513 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3514 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3518 fcmov%D3 %R4,%R5,%0"
3519 [(set_attr "type" "fcmov")])
3521 (define_insn "*movdfcc_ext1"
3522 [(set (match_operand:DF 0 "register_operand" "=f,f")
3524 (match_operator 3 "signed_comparison_operator"
3525 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3526 (match_operand:DF 2 "fp0_operand" "G,G")])
3527 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3528 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3532 fcmov%D3 %R4,%R5,%0"
3533 [(set_attr "type" "fcmov")])
3535 (define_insn "*movdfcc_ext2"
3536 [(set (match_operand:DF 0 "register_operand" "=f,f")
3538 (match_operator 3 "signed_comparison_operator"
3540 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3541 (match_operand:DF 2 "fp0_operand" "G,G")])
3542 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3543 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3547 fcmov%D3 %R4,%R5,%0"
3548 [(set_attr "type" "fcmov")])
3550 (define_insn "*movdfcc_ext3"
3551 [(set (match_operand:SF 0 "register_operand" "=f,f")
3553 (match_operator 3 "signed_comparison_operator"
3555 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3556 (match_operand:DF 2 "fp0_operand" "G,G")])
3557 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3558 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3562 fcmov%D3 %R4,%R5,%0"
3563 [(set_attr "type" "fcmov")])
3565 (define_insn "*movdfcc_ext4"
3566 [(set (match_operand:DF 0 "register_operand" "=f,f")
3568 (match_operator 3 "signed_comparison_operator"
3570 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3571 (match_operand:DF 2 "fp0_operand" "G,G")])
3572 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3573 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3577 fcmov%D3 %R4,%R5,%0"
3578 [(set_attr "type" "fcmov")])
3580 (define_expand "maxdf3"
3582 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3583 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3584 (set (match_operand:DF 0 "register_operand" "")
3585 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3586 (match_dup 1) (match_dup 2)))]
3589 operands[3] = gen_reg_rtx (DFmode);
3590 operands[4] = CONST0_RTX (DFmode);
3593 (define_expand "mindf3"
3595 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3596 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3597 (set (match_operand:DF 0 "register_operand" "")
3598 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3599 (match_dup 1) (match_dup 2)))]
3602 operands[3] = gen_reg_rtx (DFmode);
3603 operands[4] = CONST0_RTX (DFmode);
3606 (define_expand "maxsf3"
3608 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3609 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3610 (set (match_operand:SF 0 "register_operand" "")
3611 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3612 (match_dup 1) (match_dup 2)))]
3615 operands[3] = gen_reg_rtx (DFmode);
3616 operands[4] = CONST0_RTX (DFmode);
3619 (define_expand "minsf3"
3621 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3622 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3623 (set (match_operand:SF 0 "register_operand" "")
3624 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3625 (match_dup 1) (match_dup 2)))]
3628 operands[3] = gen_reg_rtx (DFmode);
3629 operands[4] = CONST0_RTX (DFmode);
3632 (define_insn "*fbcc_normal"
3635 (match_operator 1 "signed_comparison_operator"
3636 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3637 (match_operand:DF 3 "fp0_operand" "G")])
3638 (label_ref (match_operand 0 "" ""))
3642 [(set_attr "type" "fbr")])
3644 (define_insn "*fbcc_ext_normal"
3647 (match_operator 1 "signed_comparison_operator"
3649 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3650 (match_operand:DF 3 "fp0_operand" "G")])
3651 (label_ref (match_operand 0 "" ""))
3655 [(set_attr "type" "fbr")])
3657 ;; These are the main define_expand's used to make conditional branches
3660 (define_expand "cmpdf"
3661 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3662 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3665 alpha_compare.op0 = operands[0];
3666 alpha_compare.op1 = operands[1];
3667 alpha_compare.fp_p = 1;
3671 (define_expand "cmptf"
3672 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3673 (match_operand:TF 1 "general_operand" "")))]
3674 "TARGET_HAS_XFLOATING_LIBS"
3676 alpha_compare.op0 = operands[0];
3677 alpha_compare.op1 = operands[1];
3678 alpha_compare.fp_p = 1;
3682 (define_expand "cmpdi"
3683 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3684 (match_operand:DI 1 "general_operand" "")))]
3687 alpha_compare.op0 = operands[0];
3688 alpha_compare.op1 = operands[1];
3689 alpha_compare.fp_p = 0;
3693 (define_expand "beq"
3695 (if_then_else (match_dup 1)
3696 (label_ref (match_operand 0 "" ""))
3699 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3701 (define_expand "bne"
3703 (if_then_else (match_dup 1)
3704 (label_ref (match_operand 0 "" ""))
3707 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3709 (define_expand "blt"
3711 (if_then_else (match_dup 1)
3712 (label_ref (match_operand 0 "" ""))
3715 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3717 (define_expand "ble"
3719 (if_then_else (match_dup 1)
3720 (label_ref (match_operand 0 "" ""))
3723 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3725 (define_expand "bgt"
3727 (if_then_else (match_dup 1)
3728 (label_ref (match_operand 0 "" ""))
3731 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3733 (define_expand "bge"
3735 (if_then_else (match_dup 1)
3736 (label_ref (match_operand 0 "" ""))
3739 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3741 (define_expand "bltu"
3743 (if_then_else (match_dup 1)
3744 (label_ref (match_operand 0 "" ""))
3747 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3749 (define_expand "bleu"
3751 (if_then_else (match_dup 1)
3752 (label_ref (match_operand 0 "" ""))
3755 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3757 (define_expand "bgtu"
3759 (if_then_else (match_dup 1)
3760 (label_ref (match_operand 0 "" ""))
3763 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3765 (define_expand "bgeu"
3767 (if_then_else (match_dup 1)
3768 (label_ref (match_operand 0 "" ""))
3771 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3773 (define_expand "bunordered"
3775 (if_then_else (match_dup 1)
3776 (label_ref (match_operand 0 "" ""))
3779 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3781 (define_expand "bordered"
3783 (if_then_else (match_dup 1)
3784 (label_ref (match_operand 0 "" ""))
3787 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3789 (define_expand "seq"
3790 [(set (match_operand:DI 0 "register_operand" "")
3793 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3795 (define_expand "sne"
3796 [(set (match_operand:DI 0 "register_operand" "")
3799 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3801 (define_expand "slt"
3802 [(set (match_operand:DI 0 "register_operand" "")
3805 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3807 (define_expand "sle"
3808 [(set (match_operand:DI 0 "register_operand" "")
3811 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3813 (define_expand "sgt"
3814 [(set (match_operand:DI 0 "register_operand" "")
3817 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3819 (define_expand "sge"
3820 [(set (match_operand:DI 0 "register_operand" "")
3823 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3825 (define_expand "sltu"
3826 [(set (match_operand:DI 0 "register_operand" "")
3829 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3831 (define_expand "sleu"
3832 [(set (match_operand:DI 0 "register_operand" "")
3835 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3837 (define_expand "sgtu"
3838 [(set (match_operand:DI 0 "register_operand" "")
3841 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3843 (define_expand "sgeu"
3844 [(set (match_operand:DI 0 "register_operand" "")
3847 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3849 (define_expand "sunordered"
3850 [(set (match_operand:DI 0 "register_operand" "")
3853 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3855 (define_expand "sordered"
3856 [(set (match_operand:DI 0 "register_operand" "")
3859 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3861 ;; These are the main define_expand's used to make conditional moves.
3863 (define_expand "movsicc"
3864 [(set (match_operand:SI 0 "register_operand" "")
3865 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3866 (match_operand:SI 2 "reg_or_8bit_operand" "")
3867 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3870 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3874 (define_expand "movdicc"
3875 [(set (match_operand:DI 0 "register_operand" "")
3876 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3877 (match_operand:DI 2 "reg_or_8bit_operand" "")
3878 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3881 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3885 (define_expand "movsfcc"
3886 [(set (match_operand:SF 0 "register_operand" "")
3887 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3888 (match_operand:SF 2 "reg_or_8bit_operand" "")
3889 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3892 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3896 (define_expand "movdfcc"
3897 [(set (match_operand:DF 0 "register_operand" "")
3898 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3899 (match_operand:DF 2 "reg_or_8bit_operand" "")
3900 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3903 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3907 ;; These define_split definitions are used in cases when comparisons have
3908 ;; not be stated in the correct way and we need to reverse the second
3909 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3910 ;; comparison that tests the result being reversed. We have one define_split
3911 ;; for each use of a comparison. They do not match valid insns and need
3912 ;; not generate valid insns.
3914 ;; We can also handle equality comparisons (and inequality comparisons in
3915 ;; cases where the resulting add cannot overflow) by doing an add followed by
3916 ;; a comparison with zero. This is faster since the addition takes one
3917 ;; less cycle than a compare when feeding into a conditional move.
3918 ;; For this case, we also have an SImode pattern since we can merge the add
3919 ;; and sign extend and the order doesn't matter.
3921 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3922 ;; operation could have been generated.
3925 [(set (match_operand:DI 0 "register_operand" "")
3927 (match_operator 1 "comparison_operator"
3928 [(match_operand:DI 2 "reg_or_0_operand" "")
3929 (match_operand:DI 3 "reg_or_cint_operand" "")])
3930 (match_operand:DI 4 "reg_or_cint_operand" "")
3931 (match_operand:DI 5 "reg_or_cint_operand" "")))
3932 (clobber (match_operand:DI 6 "register_operand" ""))]
3933 "operands[3] != const0_rtx"
3934 [(set (match_dup 6) (match_dup 7))
3936 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3938 enum rtx_code code = GET_CODE (operands[1]);
3939 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3941 /* If we are comparing for equality with a constant and that constant
3942 appears in the arm when the register equals the constant, use the
3943 register since that is more likely to match (and to produce better code
3946 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3947 && rtx_equal_p (operands[4], operands[3]))
3948 operands[4] = operands[2];
3950 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3951 && rtx_equal_p (operands[5], operands[3]))
3952 operands[5] = operands[2];
3954 if (code == NE || code == EQ
3955 || (extended_count (operands[2], DImode, unsignedp) >= 1
3956 && extended_count (operands[3], DImode, unsignedp) >= 1))
3958 if (GET_CODE (operands[3]) == CONST_INT)
3959 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3960 GEN_INT (- INTVAL (operands[3])));
3962 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3964 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3967 else if (code == EQ || code == LE || code == LT
3968 || code == LEU || code == LTU)
3970 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3971 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3975 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3976 operands[2], operands[3]);
3977 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3982 [(set (match_operand:DI 0 "register_operand" "")
3984 (match_operator 1 "comparison_operator"
3985 [(match_operand:SI 2 "reg_or_0_operand" "")
3986 (match_operand:SI 3 "reg_or_cint_operand" "")])
3987 (match_operand:DI 4 "reg_or_8bit_operand" "")
3988 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3989 (clobber (match_operand:DI 6 "register_operand" ""))]
3990 "operands[3] != const0_rtx
3991 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3992 [(set (match_dup 6) (match_dup 7))
3994 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3996 enum rtx_code code = GET_CODE (operands[1]);
3997 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4000 if ((code != NE && code != EQ
4001 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4002 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4005 if (GET_CODE (operands[3]) == CONST_INT)
4006 tem = gen_rtx_PLUS (SImode, operands[2],
4007 GEN_INT (- INTVAL (operands[3])));
4009 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4011 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4012 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4013 operands[6], const0_rtx);
4019 (match_operator 1 "comparison_operator"
4020 [(match_operand:DI 2 "reg_or_0_operand" "")
4021 (match_operand:DI 3 "reg_or_cint_operand" "")])
4022 (label_ref (match_operand 0 "" ""))
4024 (clobber (match_operand:DI 4 "register_operand" ""))]
4025 "operands[3] != const0_rtx"
4026 [(set (match_dup 4) (match_dup 5))
4027 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4029 enum rtx_code code = GET_CODE (operands[1]);
4030 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4032 if (code == NE || code == EQ
4033 || (extended_count (operands[2], DImode, unsignedp) >= 1
4034 && extended_count (operands[3], DImode, unsignedp) >= 1))
4036 if (GET_CODE (operands[3]) == CONST_INT)
4037 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4038 GEN_INT (- INTVAL (operands[3])));
4040 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4042 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4045 else if (code == EQ || code == LE || code == LT
4046 || code == LEU || code == LTU)
4048 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4049 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4053 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4054 operands[2], operands[3]);
4055 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4062 (match_operator 1 "comparison_operator"
4063 [(match_operand:SI 2 "reg_or_0_operand" "")
4064 (match_operand:SI 3 "const_int_operand" "")])
4065 (label_ref (match_operand 0 "" ""))
4067 (clobber (match_operand:DI 4 "register_operand" ""))]
4068 "operands[3] != const0_rtx
4069 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4070 [(set (match_dup 4) (match_dup 5))
4071 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4075 if (GET_CODE (operands[3]) == CONST_INT)
4076 tem = gen_rtx_PLUS (SImode, operands[2],
4077 GEN_INT (- INTVAL (operands[3])));
4079 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4081 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4082 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4083 operands[4], const0_rtx);
4086 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4087 ;; This eliminates one, and sometimes two, insns when the AND can be done
4090 [(set (match_operand:DI 0 "register_operand" "")
4091 (match_operator:DI 1 "comparison_operator"
4092 [(match_operand:DI 2 "register_operand" "")
4093 (match_operand:DI 3 "const_int_operand" "")]))
4094 (clobber (match_operand:DI 4 "register_operand" ""))]
4095 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4096 && (GET_CODE (operands[1]) == GTU
4097 || GET_CODE (operands[1]) == LEU
4098 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4099 && extended_count (operands[2], DImode, 1) > 0))"
4100 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4101 (set (match_dup 0) (match_dup 6))]
4103 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4104 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4105 || GET_CODE (operands[1]) == GT)
4107 DImode, operands[4], const0_rtx);
4110 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4113 [(set (match_operand 0 "register_operand" "")
4114 (if_then_else (match_operator 1 "signed_comparison_operator"
4115 [(match_operand:DI 2 "reg_or_0_operand" "")
4117 (match_operand 3 "const_int_operand" "")
4118 (match_operand 4 "const_int_operand" "")))]
4122 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4123 operands[2], operands[3], operands[4]))
4129 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4130 ;; Oh well, we match it in movcc, so it must be partially our fault.
4132 [(set (match_operand 0 "register_operand" "")
4133 (if_then_else (match_operator 1 "signed_comparison_operator"
4135 (match_operand:DI 2 "reg_or_0_operand" "")])
4136 (match_operand 3 "const_int_operand" "")
4137 (match_operand 4 "const_int_operand" "")))]
4141 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4142 operands[0], operands[2], operands[3],
4149 (define_insn_and_split "*cmp_sadd_di"
4150 [(set (match_operand:DI 0 "register_operand" "=r")
4151 (plus:DI (if_then_else:DI
4152 (match_operator 1 "alpha_zero_comparison_operator"
4153 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4155 (match_operand:DI 3 "const48_operand" "I")
4157 (match_operand:DI 4 "sext_add_operand" "rIO")))
4158 (clobber (match_scratch:DI 5 "=r"))]
4161 "! no_new_pseudos || reload_completed"
4163 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4165 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4168 if (! no_new_pseudos)
4169 operands[5] = gen_reg_rtx (DImode);
4170 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4171 operands[5] = operands[0];
4174 (define_insn_and_split "*cmp_sadd_si"
4175 [(set (match_operand:SI 0 "register_operand" "=r")
4176 (plus:SI (if_then_else:SI
4177 (match_operator 1 "alpha_zero_comparison_operator"
4178 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4180 (match_operand:SI 3 "const48_operand" "I")
4182 (match_operand:SI 4 "sext_add_operand" "rIO")))
4183 (clobber (match_scratch:SI 5 "=r"))]
4186 "! no_new_pseudos || reload_completed"
4188 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4190 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4193 if (! no_new_pseudos)
4194 operands[5] = gen_reg_rtx (DImode);
4195 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4196 operands[5] = operands[0];
4199 (define_insn_and_split "*cmp_sadd_sidi"
4200 [(set (match_operand:DI 0 "register_operand" "=r")
4202 (plus:SI (if_then_else:SI
4203 (match_operator 1 "alpha_zero_comparison_operator"
4204 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4206 (match_operand:SI 3 "const48_operand" "I")
4208 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4209 (clobber (match_scratch:SI 5 "=r"))]
4212 "! no_new_pseudos || reload_completed"
4214 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4216 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4219 if (! no_new_pseudos)
4220 operands[5] = gen_reg_rtx (DImode);
4221 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4222 operands[5] = operands[0];
4225 (define_insn_and_split "*cmp_ssub_di"
4226 [(set (match_operand:DI 0 "register_operand" "=r")
4227 (minus:DI (if_then_else:DI
4228 (match_operator 1 "alpha_zero_comparison_operator"
4229 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4231 (match_operand:DI 3 "const48_operand" "I")
4233 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4234 (clobber (match_scratch:DI 5 "=r"))]
4237 "! no_new_pseudos || reload_completed"
4239 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4241 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4244 if (! no_new_pseudos)
4245 operands[5] = gen_reg_rtx (DImode);
4246 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4247 operands[5] = operands[0];
4250 (define_insn_and_split "*cmp_ssub_si"
4251 [(set (match_operand:SI 0 "register_operand" "=r")
4252 (minus:SI (if_then_else:SI
4253 (match_operator 1 "alpha_zero_comparison_operator"
4254 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4256 (match_operand:SI 3 "const48_operand" "I")
4258 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4259 (clobber (match_scratch:SI 5 "=r"))]
4262 "! no_new_pseudos || reload_completed"
4264 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4266 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4269 if (! no_new_pseudos)
4270 operands[5] = gen_reg_rtx (DImode);
4271 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4272 operands[5] = operands[0];
4275 (define_insn_and_split "*cmp_ssub_sidi"
4276 [(set (match_operand:DI 0 "register_operand" "=r")
4278 (minus:SI (if_then_else:SI
4279 (match_operator 1 "alpha_zero_comparison_operator"
4280 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4282 (match_operand:SI 3 "const48_operand" "I")
4284 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4285 (clobber (match_scratch:SI 5 "=r"))]
4288 "! no_new_pseudos || reload_completed"
4290 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4292 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4295 if (! no_new_pseudos)
4296 operands[5] = gen_reg_rtx (DImode);
4297 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4298 operands[5] = operands[0];
4301 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4302 ;; work differently, so we have different patterns for each.
4304 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4305 ;; call. The CIW contains information about arguments passed in registers
4306 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4307 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4308 ;; in the presence of inlining since the CIWs for calls performed by the
4309 ;; inlined function must be stored in the SSIB of the function it is inlined
4310 ;; into as well. We encode the CIW in an unspec and append it to the list
4311 ;; of the CIWs for the current function only when the instruction for loading
4312 ;; $25 is generated.
4314 (define_expand "call"
4315 [(use (match_operand:DI 0 "" ""))
4316 (use (match_operand 1 "" ""))
4317 (use (match_operand 2 "" ""))
4318 (use (match_operand 3 "" ""))]
4321 if (TARGET_ABI_WINDOWS_NT)
4322 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4323 else if (TARGET_ABI_OPEN_VMS)
4324 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4325 else if (TARGET_ABI_UNICOSMK)
4326 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4328 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4332 (define_expand "sibcall"
4333 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4334 (match_operand 1 "" ""))
4335 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4338 if (GET_CODE (operands[0]) != MEM)
4340 operands[0] = XEXP (operands[0], 0);
4343 (define_expand "call_osf"
4344 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4345 (match_operand 1 "" ""))
4347 (clobber (reg:DI 26))])]
4350 if (GET_CODE (operands[0]) != MEM)
4353 operands[0] = XEXP (operands[0], 0);
4354 if (! call_operand (operands[0], Pmode))
4355 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4358 (define_expand "call_nt"
4359 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4360 (match_operand 1 "" ""))
4361 (clobber (reg:DI 26))])]
4364 if (GET_CODE (operands[0]) != MEM)
4367 operands[0] = XEXP (operands[0], 0);
4368 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4369 operands[0] = force_reg (DImode, operands[0]);
4372 ;; Calls on Unicos/Mk are always indirect.
4373 ;; op 0: symbol ref for called function
4374 ;; op 1: CIW for $25 represented by an unspec
4376 (define_expand "call_umk"
4377 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4378 (match_operand 1 "" ""))
4380 (clobber (reg:DI 26))])]
4383 if (GET_CODE (operands[0]) != MEM)
4386 /* Always load the address of the called function into a register;
4387 load the CIW in $25. */
4389 operands[0] = XEXP (operands[0], 0);
4390 if (GET_CODE (operands[0]) != REG)
4391 operands[0] = force_reg (DImode, operands[0]);
4393 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4397 ;; call openvms/alpha
4398 ;; op 0: symbol ref for called function
4399 ;; op 1: next_arg_reg (argument information value for R25)
4401 (define_expand "call_vms"
4402 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4403 (match_operand 1 "" ""))
4407 (clobber (reg:DI 27))])]
4410 if (GET_CODE (operands[0]) != MEM)
4413 operands[0] = XEXP (operands[0], 0);
4415 /* Always load AI with argument information, then handle symbolic and
4416 indirect call differently. Load RA and set operands[2] to PV in
4419 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4420 if (GET_CODE (operands[0]) == SYMBOL_REF)
4422 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4424 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4426 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4430 emit_move_insn (gen_rtx_REG (Pmode, 26),
4431 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4432 operands[2] = operands[0];
4437 (define_expand "call_value"
4438 [(use (match_operand 0 "" ""))
4439 (use (match_operand:DI 1 "" ""))
4440 (use (match_operand 2 "" ""))
4441 (use (match_operand 3 "" ""))
4442 (use (match_operand 4 "" ""))]
4445 if (TARGET_ABI_WINDOWS_NT)
4446 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4447 else if (TARGET_ABI_OPEN_VMS)
4448 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4450 else if (TARGET_ABI_UNICOSMK)
4451 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4454 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4459 (define_expand "sibcall_value"
4460 [(parallel [(set (match_operand 0 "" "")
4461 (call (mem:DI (match_operand 1 "" ""))
4462 (match_operand 2 "" "")))
4463 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4466 if (GET_CODE (operands[1]) != MEM)
4468 operands[1] = XEXP (operands[1], 0);
4471 (define_expand "call_value_osf"
4472 [(parallel [(set (match_operand 0 "" "")
4473 (call (mem:DI (match_operand 1 "" ""))
4474 (match_operand 2 "" "")))
4476 (clobber (reg:DI 26))])]
4479 if (GET_CODE (operands[1]) != MEM)
4482 operands[1] = XEXP (operands[1], 0);
4483 if (! call_operand (operands[1], Pmode))
4484 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4487 (define_expand "call_value_nt"
4488 [(parallel [(set (match_operand 0 "" "")
4489 (call (mem:DI (match_operand 1 "" ""))
4490 (match_operand 2 "" "")))
4491 (clobber (reg:DI 26))])]
4494 if (GET_CODE (operands[1]) != MEM)
4497 operands[1] = XEXP (operands[1], 0);
4498 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4499 operands[1] = force_reg (DImode, operands[1]);
4502 (define_expand "call_value_vms"
4503 [(parallel [(set (match_operand 0 "" "")
4504 (call (mem:DI (match_operand:DI 1 "" ""))
4505 (match_operand 2 "" "")))
4509 (clobber (reg:DI 27))])]
4512 if (GET_CODE (operands[1]) != MEM)
4515 operands[1] = XEXP (operands[1], 0);
4517 /* Always load AI with argument information, then handle symbolic and
4518 indirect call differently. Load RA and set operands[3] to PV in
4521 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4522 if (GET_CODE (operands[1]) == SYMBOL_REF)
4524 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4526 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4528 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4532 emit_move_insn (gen_rtx_REG (Pmode, 26),
4533 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4534 operands[3] = operands[1];
4538 (define_expand "call_value_umk"
4539 [(parallel [(set (match_operand 0 "" "")
4540 (call (mem:DI (match_operand 1 "" ""))
4541 (match_operand 2 "" "")))
4543 (clobber (reg:DI 26))])]
4546 if (GET_CODE (operands[1]) != MEM)
4549 operands[1] = XEXP (operands[1], 0);
4550 if (GET_CODE (operands[1]) != REG)
4551 operands[1] = force_reg (DImode, operands[1]);
4553 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4556 (define_insn "*call_osf_1_er"
4557 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4558 (match_operand 1 "" ""))
4560 (clobber (reg:DI 26))]
4561 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4563 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4565 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4566 [(set_attr "type" "jsr")
4567 (set_attr "length" "12,*,16")])
4569 ;; We must use peep2 instead of a split because we need accurate life
4570 ;; information for $gp. Consider the case of { bar(); while (1); }.
4572 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4573 (match_operand 1 "" ""))
4575 (clobber (reg:DI 26))])]
4576 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4577 && ! current_file_function_operand (operands[0], Pmode)
4578 && peep2_regno_dead_p (1, 29)"
4579 [(parallel [(call (mem:DI (match_dup 2))
4581 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4582 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4584 (use (match_dup 3))])]
4586 if (CONSTANT_P (operands[0]))
4588 operands[2] = gen_rtx_REG (Pmode, 27);
4589 operands[3] = GEN_INT (alpha_next_sequence_number++);
4590 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4591 operands[0], operands[3]));
4595 operands[2] = operands[0];
4596 operands[0] = const0_rtx;
4597 operands[3] = const0_rtx;
4602 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4603 (match_operand 1 "" ""))
4605 (clobber (reg:DI 26))])]
4606 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4607 && ! current_file_function_operand (operands[0], Pmode)
4608 && ! peep2_regno_dead_p (1, 29)"
4609 [(parallel [(call (mem:DI (match_dup 2))
4611 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4612 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4614 (use (match_dup 4))])
4616 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4618 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4620 if (CONSTANT_P (operands[0]))
4622 operands[2] = gen_rtx_REG (Pmode, 27);
4623 operands[4] = GEN_INT (alpha_next_sequence_number++);
4624 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4625 operands[0], operands[4]));
4629 operands[2] = operands[0];
4630 operands[0] = const0_rtx;
4631 operands[4] = const0_rtx;
4633 operands[3] = GEN_INT (alpha_next_sequence_number++);
4636 ;; We add a blockage unspec_volatile to prevent insns from moving down
4637 ;; from above the call to in between the call and the ldah gpdisp.
4639 (define_insn "*call_osf_2_er"
4640 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4641 (match_operand 1 "" ""))
4642 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4643 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4644 (use (match_operand 2 "" ""))
4645 (use (match_operand 3 "const_int_operand" ""))]
4646 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4647 "jsr $26,(%0),%2%J3"
4648 [(set_attr "type" "jsr")])
4650 (define_insn "*call_osf_1_noreturn"
4651 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4652 (match_operand 1 "" ""))
4654 (clobber (reg:DI 26))]
4655 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4656 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4661 [(set_attr "type" "jsr")
4662 (set_attr "length" "*,*,8")])
4664 (define_insn "*call_osf_1"
4665 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4666 (match_operand 1 "" ""))
4668 (clobber (reg:DI 26))]
4669 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4671 jsr $26,($27),0\;ldgp $29,0($26)
4673 jsr $26,%0\;ldgp $29,0($26)"
4674 [(set_attr "type" "jsr")
4675 (set_attr "length" "12,*,16")])
4677 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4678 ;; doesn't do what we want.
4679 (define_insn "*sibcall_osf_1_er"
4680 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4681 (match_operand 1 "" ""))
4682 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4683 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4686 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4687 [(set_attr "type" "jsr")
4688 (set_attr "length" "*,8")])
4690 (define_insn "*sibcall_osf_1"
4691 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4692 (match_operand 1 "" ""))
4693 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4694 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4697 lda $27,%0\;jmp $31,($27),%0"
4698 [(set_attr "type" "jsr")
4699 (set_attr "length" "*,8")])
4701 (define_insn "*call_nt_1"
4702 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4703 (match_operand 1 "" ""))
4704 (clobber (reg:DI 26))]
4705 "TARGET_ABI_WINDOWS_NT"
4710 [(set_attr "type" "jsr")
4711 (set_attr "length" "*,*,12")])
4713 (define_insn "*call_vms_1"
4714 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4715 (match_operand 1 "" ""))
4716 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4719 (clobber (reg:DI 27))]
4720 "TARGET_ABI_OPEN_VMS"
4722 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4723 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4724 [(set_attr "type" "jsr")
4725 (set_attr "length" "12,16")])
4727 (define_insn "*call_umk_1"
4728 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4729 (match_operand 1 "" ""))
4731 (clobber (reg:DI 26))]
4732 "TARGET_ABI_UNICOSMK"
4734 [(set_attr "type" "jsr")])
4736 ;; Call subroutine returning any type.
4738 (define_expand "untyped_call"
4739 [(parallel [(call (match_operand 0 "" "")
4741 (match_operand 1 "" "")
4742 (match_operand 2 "" "")])]
4747 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4749 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4751 rtx set = XVECEXP (operands[2], 0, i);
4752 emit_move_insn (SET_DEST (set), SET_SRC (set));
4755 /* The optimizer does not know that the call sets the function value
4756 registers we stored in the result block. We avoid problems by
4757 claiming that all hard registers are used and clobbered at this
4759 emit_insn (gen_blockage ());
4764 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4765 ;; all of memory. This blocks insns from being moved across this point.
4767 (define_insn "blockage"
4768 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4771 [(set_attr "length" "0")
4772 (set_attr "type" "none")])
4776 (label_ref (match_operand 0 "" "")))]
4779 [(set_attr "type" "ibr")])
4781 (define_expand "return"
4786 (define_insn "*return_internal"
4790 [(set_attr "type" "ibr")])
4792 (define_insn "indirect_jump"
4793 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4796 [(set_attr "type" "ibr")])
4798 (define_expand "tablejump"
4799 [(parallel [(set (pc)
4800 (match_operand 0 "register_operand" ""))
4801 (use (label_ref:DI (match_operand 1 "" "")))])]
4804 if (TARGET_ABI_WINDOWS_NT)
4806 rtx dest = gen_reg_rtx (DImode);
4807 emit_insn (gen_extendsidi2 (dest, operands[0]));
4810 else if (TARGET_ABI_OSF)
4812 rtx dest = gen_reg_rtx (DImode);
4813 emit_insn (gen_extendsidi2 (dest, operands[0]));
4814 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4819 (define_insn "*tablejump_osf_nt_internal"
4821 (match_operand:DI 0 "register_operand" "r"))
4822 (use (label_ref:DI (match_operand 1 "" "")))]
4823 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4824 && alpha_tablejump_addr_vec (insn)"
4826 operands[2] = alpha_tablejump_best_label (insn);
4827 return "jmp $31,(%0),%2";
4829 [(set_attr "type" "ibr")])
4831 (define_insn "*tablejump_internal"
4833 (match_operand:DI 0 "register_operand" "r"))
4834 (use (label_ref (match_operand 1 "" "")))]
4837 [(set_attr "type" "ibr")])
4839 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4840 ;; want to have to include pal.h in our .s file.
4842 ;; Technically the type for call_pal is jsr, but we use that for determining
4843 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4846 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4849 [(set_attr "type" "ibr")])
4851 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4852 ;; NT does not document anything at 0x81 -- presumably it would generate
4853 ;; the equivalent of SIGILL, but this isn't that important.
4854 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4856 [(trap_if (const_int 1) (const_int 0))]
4857 "!TARGET_ABI_WINDOWS_NT"
4859 [(set_attr "type" "ibr")])
4861 ;; For userland, we load the thread pointer from the TCB.
4862 ;; For the kernel, we load the per-cpu private value.
4864 (define_insn "load_tp"
4865 [(set (match_operand:DI 0 "register_operand" "=v")
4866 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4869 if (TARGET_TLS_KERNEL)
4870 return "call_pal 0x32";
4872 return "call_pal 0x9e";
4874 [(set_attr "type" "ibr")])
4876 ;; For completeness, and possibly a __builtin function, here's how to
4877 ;; set the thread pointer. Since we don't describe enough of this
4878 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4879 ;; not much point in creating an R16_REG register class.
4881 (define_expand "set_tp"
4882 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4883 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4887 (define_insn "*set_tp"
4888 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4891 if (TARGET_TLS_KERNEL)
4892 return "call_pal 0x31";
4894 return "call_pal 0x9f";
4896 [(set_attr "type" "ibr")])
4898 ;; Finally, we have the basic data motion insns. The byte and word insns
4899 ;; are done via define_expand. Start with the floating-point insns, since
4900 ;; they are simpler.
4902 (define_insn "*movsf_nofix"
4903 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4904 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4905 "TARGET_FPREGS && ! TARGET_FIX
4906 && (register_operand (operands[0], SFmode)
4907 || reg_or_fp0_operand (operands[1], SFmode))"
4915 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4917 (define_insn "*movsf_fix"
4918 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4919 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4920 "TARGET_FPREGS && TARGET_FIX
4921 && (register_operand (operands[0], SFmode)
4922 || reg_or_fp0_operand (operands[1], SFmode))"
4932 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4934 (define_insn "*movsf_nofp"
4935 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4936 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4938 && (register_operand (operands[0], SFmode)
4939 || reg_or_fp0_operand (operands[1], SFmode))"
4944 [(set_attr "type" "ilog,ild,ist")])
4946 (define_insn "*movdf_nofix"
4947 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4948 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4949 "TARGET_FPREGS && ! TARGET_FIX
4950 && (register_operand (operands[0], DFmode)
4951 || reg_or_fp0_operand (operands[1], DFmode))"
4959 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4961 (define_insn "*movdf_fix"
4962 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4963 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4964 "TARGET_FPREGS && TARGET_FIX
4965 && (register_operand (operands[0], DFmode)
4966 || reg_or_fp0_operand (operands[1], DFmode))"
4976 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4978 (define_insn "*movdf_nofp"
4979 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4980 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4982 && (register_operand (operands[0], DFmode)
4983 || reg_or_fp0_operand (operands[1], DFmode))"
4988 [(set_attr "type" "ilog,ild,ist")])
4990 ;; Subregs suck for register allocation. Pretend we can move TFmode
4991 ;; data between general registers until after reload.
4993 (define_insn_and_split "*movtf_internal"
4994 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4995 (match_operand:TF 1 "input_operand" "roG,rG"))]
4996 "register_operand (operands[0], TFmode)
4997 || reg_or_fp0_operand (operands[1], TFmode)"
5000 [(set (match_dup 0) (match_dup 2))
5001 (set (match_dup 1) (match_dup 3))]
5003 alpha_split_tfmode_pair (operands);
5004 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5007 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5008 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5012 (define_expand "movsf"
5013 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5014 (match_operand:SF 1 "general_operand" ""))]
5017 if (GET_CODE (operands[0]) == MEM
5018 && ! reg_or_fp0_operand (operands[1], SFmode))
5019 operands[1] = force_reg (SFmode, operands[1]);
5022 (define_expand "movdf"
5023 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5024 (match_operand:DF 1 "general_operand" ""))]
5027 if (GET_CODE (operands[0]) == MEM
5028 && ! reg_or_fp0_operand (operands[1], DFmode))
5029 operands[1] = force_reg (DFmode, operands[1]);
5032 (define_expand "movtf"
5033 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5034 (match_operand:TF 1 "general_operand" ""))]
5037 if (GET_CODE (operands[0]) == MEM
5038 && ! reg_or_fp0_operand (operands[1], TFmode))
5039 operands[1] = force_reg (TFmode, operands[1]);
5042 (define_insn "*movsi_nofix"
5043 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5044 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5045 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5046 && (register_operand (operands[0], SImode)
5047 || reg_or_0_operand (operands[1], SImode))"
5057 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5059 (define_insn "*movsi_fix"
5060 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5061 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5062 "TARGET_ABI_OSF && TARGET_FIX
5063 && (register_operand (operands[0], SImode)
5064 || reg_or_0_operand (operands[1], SImode))"
5076 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5078 (define_insn "*movsi_nt_vms_nofix"
5079 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5080 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5081 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5083 && (register_operand (operands[0], SImode)
5084 || reg_or_0_operand (operands[1], SImode))"
5095 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5097 (define_insn "*movsi_nt_vms_fix"
5098 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5099 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5100 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5102 && (register_operand (operands[0], SImode)
5103 || reg_or_0_operand (operands[1], SImode))"
5116 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5118 (define_insn "*movhi_nobwx"
5119 [(set (match_operand:HI 0 "register_operand" "=r,r")
5120 (match_operand:HI 1 "input_operand" "rJ,n"))]
5122 && (register_operand (operands[0], HImode)
5123 || register_operand (operands[1], HImode))"
5127 [(set_attr "type" "ilog,iadd")])
5129 (define_insn "*movhi_bwx"
5130 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5131 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5133 && (register_operand (operands[0], HImode)
5134 || reg_or_0_operand (operands[1], HImode))"
5140 [(set_attr "type" "ilog,iadd,ild,ist")])
5142 (define_insn "*movqi_nobwx"
5143 [(set (match_operand:QI 0 "register_operand" "=r,r")
5144 (match_operand:QI 1 "input_operand" "rJ,n"))]
5146 && (register_operand (operands[0], QImode)
5147 || register_operand (operands[1], QImode))"
5151 [(set_attr "type" "ilog,iadd")])
5153 (define_insn "*movqi_bwx"
5154 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5155 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5157 && (register_operand (operands[0], QImode)
5158 || reg_or_0_operand (operands[1], QImode))"
5164 [(set_attr "type" "ilog,iadd,ild,ist")])
5166 ;; We do two major things here: handle mem->mem and construct long
5169 (define_expand "movsi"
5170 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5171 (match_operand:SI 1 "general_operand" ""))]
5174 if (alpha_expand_mov (SImode, operands))
5178 ;; Split a load of a large constant into the appropriate two-insn
5182 [(set (match_operand:SI 0 "register_operand" "")
5183 (match_operand:SI 1 "const_int_operand" ""))]
5184 "! add_operand (operands[1], SImode)"
5185 [(set (match_dup 0) (match_dup 2))
5186 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5189 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5191 if (tem == operands[0])
5197 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5198 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5199 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5200 ;; notes and update LABEL_NUSES because this is not done automatically.
5201 ;; Labels may be incorrectly deleted if we don't do this.
5203 ;; Describing what the individual instructions do correctly is too complicated
5204 ;; so use UNSPECs for each of the three parts of an address.
5207 [(set (match_operand:DI 0 "register_operand" "")
5208 (match_operand:DI 1 "symbolic_operand" ""))]
5209 "TARGET_ABI_UNICOSMK && reload_completed"
5212 rtx insn1, insn2, insn3;
5214 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5215 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5216 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5217 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5218 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5220 if (GET_CODE (operands[1]) == LABEL_REF)
5224 label = XEXP (operands[1], 0);
5225 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5227 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5229 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5231 LABEL_NUSES (label) += 3;
5236 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5238 (define_insn "umk_laum"
5239 [(set (match_operand:DI 0 "register_operand" "=r")
5240 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5242 "TARGET_ABI_UNICOSMK"
5244 [(set_attr "type" "iadd")])
5246 (define_insn "umk_lalm"
5247 [(set (match_operand:DI 0 "register_operand" "=r")
5248 (plus:DI (match_operand:DI 1 "register_operand" "r")
5249 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5251 "TARGET_ABI_UNICOSMK"
5253 [(set_attr "type" "iadd")])
5255 (define_insn "umk_lal"
5256 [(set (match_operand:DI 0 "register_operand" "=r")
5257 (plus:DI (match_operand:DI 1 "register_operand" "r")
5258 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5260 "TARGET_ABI_UNICOSMK"
5262 [(set_attr "type" "iadd")])
5264 ;; Add a new call information word to the current function's list of CIWs
5265 ;; and load its index into $25. Doing it here ensures that the CIW will be
5266 ;; associated with the correct function even in the presence of inlining.
5268 (define_insn "*umk_load_ciw"
5270 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5271 "TARGET_ABI_UNICOSMK"
5273 operands[0] = unicosmk_add_call_info_word (operands[0]);
5274 return "lda $25,%0";
5276 [(set_attr "type" "iadd")])
5278 (define_insn "*movdi_er_low_l"
5279 [(set (match_operand:DI 0 "register_operand" "=r")
5280 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5281 (match_operand:DI 2 "local_symbolic_operand" "")))]
5282 "TARGET_EXPLICIT_RELOCS"
5284 if (true_regnum (operands[1]) == 29)
5285 return "lda %0,%2(%1)\t\t!gprel";
5287 return "lda %0,%2(%1)\t\t!gprellow";
5291 [(set (match_operand:DI 0 "register_operand" "")
5292 (match_operand:DI 1 "small_symbolic_operand" ""))]
5293 "TARGET_EXPLICIT_RELOCS && reload_completed"
5295 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5296 "operands[2] = pic_offset_table_rtx;")
5299 [(set (match_operand:DI 0 "register_operand" "")
5300 (match_operand:DI 1 "local_symbolic_operand" ""))]
5301 "TARGET_EXPLICIT_RELOCS && reload_completed"
5303 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5305 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5306 "operands[2] = pic_offset_table_rtx;")
5309 [(match_operand 0 "some_small_symbolic_operand" "")]
5310 "TARGET_EXPLICIT_RELOCS && reload_completed"
5312 "operands[0] = split_small_symbolic_operand (operands[0]);")
5314 (define_insn "movdi_er_high_g"
5315 [(set (match_operand:DI 0 "register_operand" "=r")
5316 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5317 (match_operand:DI 2 "global_symbolic_operand" "")
5318 (match_operand 3 "const_int_operand" "")]
5320 "TARGET_EXPLICIT_RELOCS"
5322 if (INTVAL (operands[3]) == 0)
5323 return "ldq %0,%2(%1)\t\t!literal";
5325 return "ldq %0,%2(%1)\t\t!literal!%3";
5327 [(set_attr "type" "ldsym")])
5330 [(set (match_operand:DI 0 "register_operand" "")
5331 (match_operand:DI 1 "global_symbolic_operand" ""))]
5332 "TARGET_EXPLICIT_RELOCS && reload_completed"
5334 (unspec:DI [(match_dup 2)
5336 (const_int 0)] UNSPEC_LITERAL))]
5337 "operands[2] = pic_offset_table_rtx;")
5339 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5340 ;; compiled at the end of compilation. In the meantime, someone can
5341 ;; re-encode-section-info on some symbol changing it e.g. from global
5342 ;; to local-not-small. If this happens, we'd have emitted a plain
5343 ;; load rather than a high+losum load and not recognize the insn.
5345 ;; So if rtl inlining is in effect, we delay the global/not-global
5346 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5348 (define_insn_and_split "movdi_er_maybe_g"
5349 [(set (match_operand:DI 0 "register_operand" "=r")
5350 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5352 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5355 [(set (match_dup 0) (match_dup 1))]
5357 if (local_symbolic_operand (operands[1], Pmode)
5358 && !small_symbolic_operand (operands[1], Pmode))
5360 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5363 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5364 if (reload_completed)
5365 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5366 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5368 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5369 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5374 (define_insn "movdi_er_tlsgd"
5375 [(set (match_operand:DI 0 "register_operand" "=r")
5376 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5377 (match_operand:DI 2 "symbolic_operand" "")
5378 (match_operand 3 "const_int_operand" "")]
5382 if (INTVAL (operands[3]) == 0)
5383 return "lda %0,%2(%1)\t\t!tlsgd";
5385 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5388 (define_insn "movdi_er_tlsldm"
5389 [(set (match_operand:DI 0 "register_operand" "=r")
5390 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5391 (match_operand 2 "const_int_operand" "")]
5395 if (INTVAL (operands[2]) == 0)
5396 return "lda %0,%&(%1)\t\t!tlsldm";
5398 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5401 (define_insn "*movdi_er_gotdtp"
5402 [(set (match_operand:DI 0 "register_operand" "=r")
5403 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5404 (match_operand:DI 2 "symbolic_operand" "")]
5407 "ldq %0,%2(%1)\t\t!gotdtprel"
5408 [(set_attr "type" "ild")])
5411 [(set (match_operand:DI 0 "register_operand" "")
5412 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5413 "HAVE_AS_TLS && reload_completed"
5415 (unspec:DI [(match_dup 2)
5416 (match_dup 1)] UNSPEC_DTPREL))]
5418 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5419 operands[2] = pic_offset_table_rtx;
5422 (define_insn "*movdi_er_gottp"
5423 [(set (match_operand:DI 0 "register_operand" "=r")
5424 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5425 (match_operand:DI 2 "symbolic_operand" "")]
5428 "ldq %0,%2(%1)\t\t!gottprel"
5429 [(set_attr "type" "ild")])
5432 [(set (match_operand:DI 0 "register_operand" "")
5433 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5434 "HAVE_AS_TLS && reload_completed"
5436 (unspec:DI [(match_dup 2)
5437 (match_dup 1)] UNSPEC_TPREL))]
5439 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5440 operands[2] = pic_offset_table_rtx;
5443 (define_insn "*movdi_er_nofix"
5444 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5445 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5446 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5447 && (register_operand (operands[0], DImode)
5448 || reg_or_0_operand (operands[1], DImode))"
5460 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5462 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5463 ;; have been split up by the rules above but we shouldn't reject the
5464 ;; possibility of them getting through.
5466 (define_insn "*movdi_nofix"
5467 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5468 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5470 && (register_operand (operands[0], DImode)
5471 || reg_or_0_operand (operands[1], DImode))"
5476 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5483 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5484 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5486 (define_insn "*movdi_er_fix"
5487 [(set (match_operand:DI 0 "nonimmediate_operand"
5488 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5489 (match_operand:DI 1 "input_operand"
5490 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5491 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5492 && (register_operand (operands[0], DImode)
5493 || reg_or_0_operand (operands[1], DImode))"
5507 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5509 (define_insn "*movdi_fix"
5510 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5511 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5512 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5513 && (register_operand (operands[0], DImode)
5514 || reg_or_0_operand (operands[1], DImode))"
5527 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5529 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5530 ;; often appears dead to the life analysis code, at which point we
5531 ;; abort for emitting dead prologue instructions. Force this live.
5533 (define_insn "force_movdi"
5534 [(set (match_operand:DI 0 "register_operand" "=r")
5535 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5536 UNSPECV_FORCE_MOV))]
5539 [(set_attr "type" "ilog")])
5541 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5542 ;; memory, and construct long 32-bit constants.
5544 (define_expand "movdi"
5545 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5546 (match_operand:DI 1 "general_operand" ""))]
5549 if (alpha_expand_mov (DImode, operands))
5553 ;; Split a load of a large constant into the appropriate two-insn
5557 [(set (match_operand:DI 0 "register_operand" "")
5558 (match_operand:DI 1 "const_int_operand" ""))]
5559 "! add_operand (operands[1], DImode)"
5560 [(set (match_dup 0) (match_dup 2))
5561 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5564 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5566 if (tem == operands[0])
5572 ;; These are the partial-word cases.
5574 ;; First we have the code to load an aligned word. Operand 0 is the register
5575 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5576 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5577 ;; number of bits within the word that the value is. Operand 3 is an SImode
5578 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5579 ;; same register. It is allowed to conflict with operand 1 as well.
5581 (define_expand "aligned_loadqi"
5582 [(set (match_operand:SI 3 "register_operand" "")
5583 (match_operand:SI 1 "memory_operand" ""))
5584 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5585 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5587 (match_operand:DI 2 "const_int_operand" "")))]
5592 (define_expand "aligned_loadhi"
5593 [(set (match_operand:SI 3 "register_operand" "")
5594 (match_operand:SI 1 "memory_operand" ""))
5595 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5596 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5598 (match_operand:DI 2 "const_int_operand" "")))]
5603 ;; Similar for unaligned loads, where we use the sequence from the
5604 ;; Alpha Architecture manual. We have to distinguish between little-endian
5605 ;; and big-endian systems as the sequences are different.
5607 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5608 ;; operand 3 can overlap the input and output registers.
5610 (define_expand "unaligned_loadqi"
5611 [(use (match_operand:QI 0 "register_operand" ""))
5612 (use (match_operand:DI 1 "address_operand" ""))
5613 (use (match_operand:DI 2 "register_operand" ""))
5614 (use (match_operand:DI 3 "register_operand" ""))]
5617 if (WORDS_BIG_ENDIAN)
5618 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5619 operands[2], operands[3]));
5621 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5622 operands[2], operands[3]));
5626 (define_expand "unaligned_loadqi_le"
5627 [(set (match_operand:DI 2 "register_operand" "")
5628 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5630 (set (match_operand:DI 3 "register_operand" "")
5632 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5633 (zero_extract:DI (match_dup 2)
5635 (ashift:DI (match_dup 3) (const_int 3))))]
5636 "! WORDS_BIG_ENDIAN"
5639 (define_expand "unaligned_loadqi_be"
5640 [(set (match_operand:DI 2 "register_operand" "")
5641 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5643 (set (match_operand:DI 3 "register_operand" "")
5645 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5646 (zero_extract:DI (match_dup 2)
5650 (ashift:DI (match_dup 3) (const_int 3)))))]
5654 (define_expand "unaligned_loadhi"
5655 [(use (match_operand:QI 0 "register_operand" ""))
5656 (use (match_operand:DI 1 "address_operand" ""))
5657 (use (match_operand:DI 2 "register_operand" ""))
5658 (use (match_operand:DI 3 "register_operand" ""))]
5661 if (WORDS_BIG_ENDIAN)
5662 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5663 operands[2], operands[3]));
5665 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5666 operands[2], operands[3]));
5670 (define_expand "unaligned_loadhi_le"
5671 [(set (match_operand:DI 2 "register_operand" "")
5672 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5674 (set (match_operand:DI 3 "register_operand" "")
5676 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5677 (zero_extract:DI (match_dup 2)
5679 (ashift:DI (match_dup 3) (const_int 3))))]
5680 "! WORDS_BIG_ENDIAN"
5683 (define_expand "unaligned_loadhi_be"
5684 [(set (match_operand:DI 2 "register_operand" "")
5685 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5687 (set (match_operand:DI 3 "register_operand" "")
5688 (plus:DI (match_dup 1) (const_int 1)))
5689 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5690 (zero_extract:DI (match_dup 2)
5694 (ashift:DI (match_dup 3) (const_int 3)))))]
5698 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5699 ;; aligned SImode MEM. Operand 1 is the register containing the
5700 ;; byte or word to store. Operand 2 is the number of bits within the word that
5701 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5703 (define_expand "aligned_store"
5704 [(set (match_operand:SI 3 "register_operand" "")
5705 (match_operand:SI 0 "memory_operand" ""))
5706 (set (subreg:DI (match_dup 3) 0)
5707 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5708 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5709 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5710 (match_operand:DI 2 "const_int_operand" "")))
5711 (set (subreg:DI (match_dup 4) 0)
5712 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5713 (set (match_dup 0) (match_dup 4))]
5716 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5717 << INTVAL (operands[2])));
5720 ;; For the unaligned byte and halfword cases, we use code similar to that
5721 ;; in the ;; Architecture book, but reordered to lower the number of registers
5722 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5723 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5724 ;; be the same temporary, if desired. If the address is in a register,
5725 ;; operand 2 can be that register.
5727 (define_expand "unaligned_storeqi"
5728 [(use (match_operand:DI 0 "address_operand" ""))
5729 (use (match_operand:QI 1 "register_operand" ""))
5730 (use (match_operand:DI 2 "register_operand" ""))
5731 (use (match_operand:DI 3 "register_operand" ""))
5732 (use (match_operand:DI 4 "register_operand" ""))]
5735 if (WORDS_BIG_ENDIAN)
5736 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5737 operands[2], operands[3],
5740 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5741 operands[2], operands[3],
5746 (define_expand "unaligned_storeqi_le"
5747 [(set (match_operand:DI 3 "register_operand" "")
5748 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5750 (set (match_operand:DI 2 "register_operand" "")
5753 (and:DI (not:DI (ashift:DI (const_int 255)
5754 (ashift:DI (match_dup 2) (const_int 3))))
5756 (set (match_operand:DI 4 "register_operand" "")
5757 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5758 (ashift:DI (match_dup 2) (const_int 3))))
5759 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5760 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5762 "! WORDS_BIG_ENDIAN"
5765 (define_expand "unaligned_storeqi_be"
5766 [(set (match_operand:DI 3 "register_operand" "")
5767 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5769 (set (match_operand:DI 2 "register_operand" "")
5772 (and:DI (not:DI (ashift:DI (const_int 255)
5773 (minus:DI (const_int 56)
5774 (ashift:DI (match_dup 2) (const_int 3)))))
5776 (set (match_operand:DI 4 "register_operand" "")
5777 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5778 (minus:DI (const_int 56)
5779 (ashift:DI (match_dup 2) (const_int 3)))))
5780 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5781 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5786 (define_expand "unaligned_storehi"
5787 [(use (match_operand:DI 0 "address_operand" ""))
5788 (use (match_operand:HI 1 "register_operand" ""))
5789 (use (match_operand:DI 2 "register_operand" ""))
5790 (use (match_operand:DI 3 "register_operand" ""))
5791 (use (match_operand:DI 4 "register_operand" ""))]
5794 if (WORDS_BIG_ENDIAN)
5795 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5796 operands[2], operands[3],
5799 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5800 operands[2], operands[3],
5805 (define_expand "unaligned_storehi_le"
5806 [(set (match_operand:DI 3 "register_operand" "")
5807 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5809 (set (match_operand:DI 2 "register_operand" "")
5812 (and:DI (not:DI (ashift:DI (const_int 65535)
5813 (ashift:DI (match_dup 2) (const_int 3))))
5815 (set (match_operand:DI 4 "register_operand" "")
5816 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5817 (ashift:DI (match_dup 2) (const_int 3))))
5818 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5819 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5821 "! WORDS_BIG_ENDIAN"
5824 (define_expand "unaligned_storehi_be"
5825 [(set (match_operand:DI 3 "register_operand" "")
5826 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5828 (set (match_operand:DI 2 "register_operand" "")
5829 (plus:DI (match_dup 0) (const_int 1)))
5831 (and:DI (not:DI (ashift:DI
5833 (minus:DI (const_int 56)
5834 (ashift:DI (match_dup 2) (const_int 3)))))
5836 (set (match_operand:DI 4 "register_operand" "")
5837 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5838 (minus:DI (const_int 56)
5839 (ashift:DI (match_dup 2) (const_int 3)))))
5840 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5841 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5846 ;; Here are the define_expand's for QI and HI moves that use the above
5847 ;; patterns. We have the normal sets, plus the ones that need scratch
5848 ;; registers for reload.
5850 (define_expand "movqi"
5851 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5852 (match_operand:QI 1 "general_operand" ""))]
5856 ? alpha_expand_mov (QImode, operands)
5857 : alpha_expand_mov_nobwx (QImode, operands))
5861 (define_expand "movhi"
5862 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5863 (match_operand:HI 1 "general_operand" ""))]
5867 ? alpha_expand_mov (HImode, operands)
5868 : alpha_expand_mov_nobwx (HImode, operands))
5872 ;; Here are the versions for reload. Note that in the unaligned cases
5873 ;; we know that the operand must not be a pseudo-register because stack
5874 ;; slots are always aligned references.
5876 (define_expand "reload_inqi"
5877 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5878 (match_operand:QI 1 "any_memory_operand" "m")
5879 (match_operand:TI 2 "register_operand" "=&r")])]
5884 if (GET_CODE (operands[1]) != MEM)
5887 if (aligned_memory_operand (operands[1], QImode))
5889 seq = gen_reload_inqi_help (operands[0], operands[1],
5890 gen_rtx_REG (SImode, REGNO (operands[2])));
5896 /* It is possible that one of the registers we got for operands[2]
5897 might coincide with that of operands[0] (which is why we made
5898 it TImode). Pick the other one to use as our scratch. */
5899 if (REGNO (operands[0]) == REGNO (operands[2]))
5900 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5902 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5904 addr = get_unaligned_address (operands[1], 0);
5905 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5906 gen_rtx_REG (DImode, REGNO (operands[0])));
5907 alpha_set_memflags (seq, operands[1]);
5913 (define_expand "reload_inhi"
5914 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5915 (match_operand:HI 1 "any_memory_operand" "m")
5916 (match_operand:TI 2 "register_operand" "=&r")])]
5921 if (GET_CODE (operands[1]) != MEM)
5924 if (aligned_memory_operand (operands[1], HImode))
5926 seq = gen_reload_inhi_help (operands[0], operands[1],
5927 gen_rtx_REG (SImode, REGNO (operands[2])));
5933 /* It is possible that one of the registers we got for operands[2]
5934 might coincide with that of operands[0] (which is why we made
5935 it TImode). Pick the other one to use as our scratch. */
5936 if (REGNO (operands[0]) == REGNO (operands[2]))
5937 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5939 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5941 addr = get_unaligned_address (operands[1], 0);
5942 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5943 gen_rtx_REG (DImode, REGNO (operands[0])));
5944 alpha_set_memflags (seq, operands[1]);
5950 (define_expand "reload_outqi"
5951 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5952 (match_operand:QI 1 "register_operand" "r")
5953 (match_operand:TI 2 "register_operand" "=&r")])]
5956 if (GET_CODE (operands[0]) != MEM)
5959 if (aligned_memory_operand (operands[0], QImode))
5961 emit_insn (gen_reload_outqi_help
5962 (operands[0], operands[1],
5963 gen_rtx_REG (SImode, REGNO (operands[2])),
5964 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5968 rtx addr = get_unaligned_address (operands[0], 0);
5969 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5970 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5971 rtx scratch3 = scratch1;
5974 if (GET_CODE (addr) == REG)
5977 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5978 scratch2, scratch3);
5979 alpha_set_memflags (seq, operands[0]);
5985 (define_expand "reload_outhi"
5986 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5987 (match_operand:HI 1 "register_operand" "r")
5988 (match_operand:TI 2 "register_operand" "=&r")])]
5991 if (GET_CODE (operands[0]) != MEM)
5994 if (aligned_memory_operand (operands[0], HImode))
5996 emit_insn (gen_reload_outhi_help
5997 (operands[0], operands[1],
5998 gen_rtx_REG (SImode, REGNO (operands[2])),
5999 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6003 rtx addr = get_unaligned_address (operands[0], 0);
6004 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6005 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6006 rtx scratch3 = scratch1;
6009 if (GET_CODE (addr) == REG)
6012 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6013 scratch2, scratch3);
6014 alpha_set_memflags (seq, operands[0]);
6020 ;; Helpers for the above. The way reload is structured, we can't
6021 ;; always get a proper address for a stack slot during reload_foo
6022 ;; expansion, so we must delay our address manipulations until after.
6024 (define_insn "reload_inqi_help"
6025 [(set (match_operand:QI 0 "register_operand" "=r")
6026 (match_operand:QI 1 "memory_operand" "m"))
6027 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6028 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6031 (define_insn "reload_inhi_help"
6032 [(set (match_operand:HI 0 "register_operand" "=r")
6033 (match_operand:HI 1 "memory_operand" "m"))
6034 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6035 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6038 (define_insn "reload_outqi_help"
6039 [(set (match_operand:QI 0 "memory_operand" "=m")
6040 (match_operand:QI 1 "register_operand" "r"))
6041 (clobber (match_operand:SI 2 "register_operand" "=r"))
6042 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6043 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6046 (define_insn "reload_outhi_help"
6047 [(set (match_operand:HI 0 "memory_operand" "=m")
6048 (match_operand:HI 1 "register_operand" "r"))
6049 (clobber (match_operand:SI 2 "register_operand" "=r"))
6050 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6051 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6055 [(set (match_operand:QI 0 "register_operand" "")
6056 (match_operand:QI 1 "memory_operand" ""))
6057 (clobber (match_operand:SI 2 "register_operand" ""))]
6058 "! TARGET_BWX && reload_completed"
6061 rtx aligned_mem, bitnum;
6062 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6064 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6070 [(set (match_operand:HI 0 "register_operand" "")
6071 (match_operand:HI 1 "memory_operand" ""))
6072 (clobber (match_operand:SI 2 "register_operand" ""))]
6073 "! TARGET_BWX && reload_completed"
6076 rtx aligned_mem, bitnum;
6077 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6079 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6085 [(set (match_operand:QI 0 "memory_operand" "")
6086 (match_operand:QI 1 "register_operand" ""))
6087 (clobber (match_operand:SI 2 "register_operand" ""))
6088 (clobber (match_operand:SI 3 "register_operand" ""))]
6089 "! TARGET_BWX && reload_completed"
6092 rtx aligned_mem, bitnum;
6093 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6094 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6095 operands[2], operands[3]));
6100 [(set (match_operand:HI 0 "memory_operand" "")
6101 (match_operand:HI 1 "register_operand" ""))
6102 (clobber (match_operand:SI 2 "register_operand" ""))
6103 (clobber (match_operand:SI 3 "register_operand" ""))]
6104 "! TARGET_BWX && reload_completed"
6107 rtx aligned_mem, bitnum;
6108 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6109 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6110 operands[2], operands[3]));
6114 ;; Bit field extract patterns which use ext[wlq][lh]
6116 (define_expand "extv"
6117 [(set (match_operand:DI 0 "register_operand" "")
6118 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6119 (match_operand:DI 2 "immediate_operand" "")
6120 (match_operand:DI 3 "immediate_operand" "")))]
6125 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6126 if (INTVAL (operands[3]) % 8 != 0
6127 || (INTVAL (operands[2]) != 16
6128 && INTVAL (operands[2]) != 32
6129 && INTVAL (operands[2]) != 64))
6132 /* From mips.md: extract_bit_field doesn't verify that our source
6133 matches the predicate, so we force it to be a MEM here. */
6134 if (GET_CODE (operands[1]) != MEM)
6137 /* The bit number is relative to the mode of operand 1 which is
6138 usually QImode (this might actually be a bug in expmed.c). Note
6139 that the bit number is negative in big-endian mode in this case.
6140 We have to convert that to the offset. */
6141 if (WORDS_BIG_ENDIAN)
6142 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6143 - INTVAL (operands[2]) - INTVAL (operands[3]);
6145 ofs = INTVAL (operands[3]);
6149 alpha_expand_unaligned_load (operands[0], operands[1],
6150 INTVAL (operands[2]) / 8,
6155 (define_expand "extzv"
6156 [(set (match_operand:DI 0 "register_operand" "")
6157 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6158 (match_operand:DI 2 "immediate_operand" "")
6159 (match_operand:DI 3 "immediate_operand" "")))]
6162 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6163 if (INTVAL (operands[3]) % 8 != 0
6164 || (INTVAL (operands[2]) != 8
6165 && INTVAL (operands[2]) != 16
6166 && INTVAL (operands[2]) != 32
6167 && INTVAL (operands[2]) != 64))
6170 if (GET_CODE (operands[1]) == MEM)
6174 /* Fail 8 bit fields, falling back on a simple byte load. */
6175 if (INTVAL (operands[2]) == 8)
6178 /* The bit number is relative to the mode of operand 1 which is
6179 usually QImode (this might actually be a bug in expmed.c). Note
6180 that the bit number is negative in big-endian mode in this case.
6181 We have to convert that to the offset. */
6182 if (WORDS_BIG_ENDIAN)
6183 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6184 - INTVAL (operands[2]) - INTVAL (operands[3]);
6186 ofs = INTVAL (operands[3]);
6190 alpha_expand_unaligned_load (operands[0], operands[1],
6191 INTVAL (operands[2]) / 8,
6197 (define_expand "insv"
6198 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6199 (match_operand:DI 1 "immediate_operand" "")
6200 (match_operand:DI 2 "immediate_operand" ""))
6201 (match_operand:DI 3 "register_operand" ""))]
6206 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6207 if (INTVAL (operands[2]) % 8 != 0
6208 || (INTVAL (operands[1]) != 16
6209 && INTVAL (operands[1]) != 32
6210 && INTVAL (operands[1]) != 64))
6213 /* From mips.md: store_bit_field doesn't verify that our source
6214 matches the predicate, so we force it to be a MEM here. */
6215 if (GET_CODE (operands[0]) != MEM)
6218 /* The bit number is relative to the mode of operand 1 which is
6219 usually QImode (this might actually be a bug in expmed.c). Note
6220 that the bit number is negative in big-endian mode in this case.
6221 We have to convert that to the offset. */
6222 if (WORDS_BIG_ENDIAN)
6223 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6224 - INTVAL (operands[1]) - INTVAL (operands[2]);
6226 ofs = INTVAL (operands[2]);
6230 alpha_expand_unaligned_store (operands[0], operands[3],
6231 INTVAL (operands[1]) / 8, ofs);
6235 ;; Block move/clear, see alpha.c for more details.
6236 ;; Argument 0 is the destination
6237 ;; Argument 1 is the source
6238 ;; Argument 2 is the length
6239 ;; Argument 3 is the alignment
6241 (define_expand "movstrqi"
6242 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6243 (match_operand:BLK 1 "memory_operand" ""))
6244 (use (match_operand:DI 2 "immediate_operand" ""))
6245 (use (match_operand:DI 3 "immediate_operand" ""))])]
6248 if (alpha_expand_block_move (operands))
6254 (define_expand "clrstrqi"
6255 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6257 (use (match_operand:DI 1 "immediate_operand" ""))
6258 (use (match_operand:DI 2 "immediate_operand" ""))])]
6261 if (alpha_expand_block_clear (operands))
6267 ;; Subroutine of stack space allocation. Perform a stack probe.
6268 (define_expand "probe_stack"
6269 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6272 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6273 INTVAL (operands[0])));
6274 MEM_VOLATILE_P (operands[1]) = 1;
6276 operands[0] = const0_rtx;
6279 ;; This is how we allocate stack space. If we are allocating a
6280 ;; constant amount of space and we know it is less than 4096
6281 ;; bytes, we need do nothing.
6283 ;; If it is more than 4096 bytes, we need to probe the stack
6285 (define_expand "allocate_stack"
6287 (plus:DI (reg:DI 30)
6288 (match_operand:DI 1 "reg_or_cint_operand" "")))
6289 (set (match_operand:DI 0 "register_operand" "=r")
6293 if (GET_CODE (operands[1]) == CONST_INT
6294 && INTVAL (operands[1]) < 32768)
6296 if (INTVAL (operands[1]) >= 4096)
6298 /* We do this the same way as in the prologue and generate explicit
6299 probes. Then we update the stack by the constant. */
6303 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6304 while (probed + 8192 < INTVAL (operands[1]))
6305 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6307 if (probed + 4096 < INTVAL (operands[1]))
6308 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6311 operands[1] = GEN_INT (- INTVAL (operands[1]));
6312 operands[2] = virtual_stack_dynamic_rtx;
6317 rtx loop_label = gen_label_rtx ();
6318 rtx want = gen_reg_rtx (Pmode);
6319 rtx tmp = gen_reg_rtx (Pmode);
6322 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6323 force_reg (Pmode, operands[1])));
6324 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6326 if (GET_CODE (operands[1]) != CONST_INT)
6328 out_label = gen_label_rtx ();
6329 emit_insn (gen_cmpdi (want, tmp));
6330 emit_jump_insn (gen_bgeu (out_label));
6333 emit_label (loop_label);
6334 memref = gen_rtx_MEM (DImode, tmp);
6335 MEM_VOLATILE_P (memref) = 1;
6336 emit_move_insn (memref, const0_rtx);
6337 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6338 emit_insn (gen_cmpdi (tmp, want));
6339 emit_jump_insn (gen_bgtu (loop_label));
6341 memref = gen_rtx_MEM (DImode, want);
6342 MEM_VOLATILE_P (memref) = 1;
6343 emit_move_insn (memref, const0_rtx);
6346 emit_label (out_label);
6348 emit_move_insn (stack_pointer_rtx, want);
6349 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6354 ;; This is used by alpha_expand_prolog to do the same thing as above,
6355 ;; except we cannot at that time generate new basic blocks, so we hide
6356 ;; the loop in this one insn.
6358 (define_insn "prologue_stack_probe_loop"
6359 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6360 (match_operand:DI 1 "register_operand" "r")]
6364 operands[2] = gen_label_rtx ();
6365 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6366 CODE_LABEL_NUMBER (operands[2]));
6368 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6370 [(set_attr "length" "16")
6371 (set_attr "type" "multi")])
6373 (define_expand "prologue"
6374 [(clobber (const_int 0))]
6377 alpha_expand_prologue ();
6381 ;; These take care of emitting the ldgp insn in the prologue. This will be
6382 ;; an lda/ldah pair and we want to align them properly. So we have two
6383 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6384 ;; and the second of which emits nothing. However, both are marked as type
6385 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6388 (define_expand "prologue_ldgp"
6390 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6392 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6395 operands[0] = pic_offset_table_rtx;
6396 operands[1] = gen_rtx_REG (Pmode, 27);
6397 operands[2] = (TARGET_EXPLICIT_RELOCS
6398 ? GEN_INT (alpha_next_sequence_number++)
6402 (define_insn "*ldgp_er_1"
6403 [(set (match_operand:DI 0 "register_operand" "=r")
6404 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6405 (match_operand 2 "const_int_operand" "")]
6407 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6408 "ldah %0,0(%1)\t\t!gpdisp!%2")
6410 (define_insn "*ldgp_er_2"
6411 [(set (match_operand:DI 0 "register_operand" "=r")
6412 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6413 (match_operand 2 "const_int_operand" "")]
6415 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6416 "lda %0,0(%1)\t\t!gpdisp!%2")
6418 (define_insn "*prologue_ldgp_er_2"
6419 [(set (match_operand:DI 0 "register_operand" "=r")
6420 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6421 (match_operand 2 "const_int_operand" "")]
6423 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6424 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6426 (define_insn "*prologue_ldgp_1"
6427 [(set (match_operand:DI 0 "register_operand" "=r")
6428 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6429 (match_operand 2 "const_int_operand" "")]
6432 "ldgp %0,0(%1)\n$%~..ng:")
6434 (define_insn "*prologue_ldgp_2"
6435 [(set (match_operand:DI 0 "register_operand" "=r")
6436 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6437 (match_operand 2 "const_int_operand" "")]
6442 ;; The _mcount profiling hook has special calling conventions, and
6443 ;; does not clobber all the registers that a normal call would. So
6444 ;; hide the fact this is a call at all.
6446 (define_insn "prologue_mcount"
6447 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6450 if (TARGET_EXPLICIT_RELOCS)
6451 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6452 cannot be called via the PLT. */
6453 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6455 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6457 [(set_attr "type" "multi")
6458 (set_attr "length" "8")])
6460 (define_insn "init_fp"
6461 [(set (match_operand:DI 0 "register_operand" "=r")
6462 (match_operand:DI 1 "register_operand" "r"))
6463 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6467 (define_expand "epilogue"
6471 alpha_expand_epilogue ();
6474 (define_expand "sibcall_epilogue"
6478 alpha_expand_epilogue ();
6482 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6483 ;; the frame size into a register. We use this pattern to ensure
6484 ;; we get lda instead of addq.
6485 (define_insn "nt_lda"
6486 [(set (match_operand:DI 0 "register_operand" "=r")
6487 (unspec:DI [(match_dup 0)
6488 (match_operand:DI 1 "const_int_operand" "n")]
6493 (define_expand "builtin_longjmp"
6494 [(use (match_operand:DI 0 "register_operand" "r"))]
6497 /* The elements of the buffer are, in order: */
6498 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6499 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6500 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6501 rtx pv = gen_rtx_REG (Pmode, 27);
6503 /* This bit is the same as expand_builtin_longjmp. */
6504 emit_move_insn (hard_frame_pointer_rtx, fp);
6505 emit_move_insn (pv, lab);
6506 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6507 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6508 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6510 /* Load the label we are jumping through into $27 so that we know
6511 where to look for it when we get back to setjmp's function for
6512 restoring the gp. */
6513 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6518 ;; This is effectively a copy of indirect_jump, but constrained such
6519 ;; that register renaming cannot foil our cunning plan with $27.
6520 (define_insn "builtin_longjmp_internal"
6522 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6526 [(set_attr "type" "ibr")])
6528 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6529 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6530 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6531 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6533 (define_insn "*builtin_setjmp_receiver_er_1"
6534 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6535 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6536 "br $27,$LSJ%=\n$LSJ%=:"
6537 [(set_attr "type" "ibr")])
6540 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6541 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6542 && prev_nonnote_insn (insn) == operands[0]"
6546 (define_insn "*builtin_setjmp_receiver_1"
6547 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6549 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6550 [(set_attr "length" "12")
6551 (set_attr "type" "multi")])
6553 (define_expand "builtin_setjmp_receiver_er"
6554 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6556 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6558 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6561 operands[1] = pic_offset_table_rtx;
6562 operands[2] = gen_rtx_REG (Pmode, 27);
6563 operands[3] = GEN_INT (alpha_next_sequence_number++);
6566 (define_expand "builtin_setjmp_receiver"
6567 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6570 if (TARGET_EXPLICIT_RELOCS)
6572 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6577 (define_expand "exception_receiver_er"
6579 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6581 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6584 operands[0] = pic_offset_table_rtx;
6585 operands[1] = gen_rtx_REG (Pmode, 26);
6586 operands[2] = GEN_INT (alpha_next_sequence_number++);
6589 (define_expand "exception_receiver"
6590 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6593 if (TARGET_LD_BUGGY_LDGP)
6594 operands[0] = alpha_gp_save_rtx ();
6595 else if (TARGET_EXPLICIT_RELOCS)
6597 emit_insn (gen_exception_receiver_er ());
6601 operands[0] = const0_rtx;
6604 (define_insn "*exception_receiver_1"
6605 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6606 "! TARGET_LD_BUGGY_LDGP"
6608 [(set_attr "length" "8")
6609 (set_attr "type" "multi")])
6611 (define_insn "*exception_receiver_2"
6612 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6613 "TARGET_LD_BUGGY_LDGP"
6615 [(set_attr "type" "ild")])
6617 (define_expand "nonlocal_goto_receiver"
6618 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6619 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6620 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6622 "TARGET_ABI_OPEN_VMS"
6625 (define_insn "arg_home"
6626 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6641 (clobber (mem:BLK (const_int 0)))
6642 (clobber (reg:DI 24))
6643 (clobber (reg:DI 25))
6644 (clobber (reg:DI 0))]
6645 "TARGET_ABI_OPEN_VMS"
6646 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6647 [(set_attr "length" "16")
6648 (set_attr "type" "multi")])
6650 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6652 (define_expand "umk_mismatch_args"
6653 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6654 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6655 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6656 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6659 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6660 "TARGET_ABI_UNICOSMK"
6662 operands[1] = gen_reg_rtx (DImode);
6663 operands[2] = gen_reg_rtx (DImode);
6664 operands[3] = gen_reg_rtx (DImode);
6667 (define_insn "arg_home_umk"
6668 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6683 (clobber (mem:BLK (const_int 0)))
6685 (clobber (reg:DI 22))
6686 (clobber (reg:DI 23))
6687 (clobber (reg:DI 24))
6688 (clobber (reg:DI 0))
6689 (clobber (reg:DI 1))
6690 (clobber (reg:DI 2))
6691 (clobber (reg:DI 3))
6692 (clobber (reg:DI 4))
6693 (clobber (reg:DI 5))
6694 (clobber (reg:DI 6))
6695 (clobber (reg:DI 7))
6696 (clobber (reg:DI 8))])]
6697 "TARGET_ABI_UNICOSMK"
6698 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6699 [(set_attr "length" "16")
6700 (set_attr "type" "multi")])
6704 ;; On EV4, these instructions are nops -- no load occurs.
6706 ;; On EV5, these instructions act as a normal load, and thus can trap
6707 ;; if the address is invalid. The OS may (or may not) handle this in
6708 ;; the entMM fault handler and suppress the fault. If so, then this
6709 ;; has the effect of a read prefetch instruction.
6711 ;; On EV6, these become official prefetch instructions.
6713 (define_insn "prefetch"
6714 [(prefetch (match_operand:DI 0 "address_operand" "p")
6715 (match_operand:DI 1 "const_int_operand" "n")
6716 (match_operand:DI 2 "const_int_operand" "n"))]
6717 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6719 /* Interpret "no temporal locality" as this data should be evicted once
6720 it is used. The "evict next" alternatives load the data into the cache
6721 and leave the LRU eviction counter pointing to that block. */
6722 static const char * const alt[2][2] = {
6724 "lds $f31,%a0", /* read, evict next */
6725 "ldl $31,%a0", /* read, evict last */
6728 "ldt $f31,%a0", /* write, evict next */
6729 "ldq $31,%a0", /* write, evict last */
6733 bool write = INTVAL (operands[1]) != 0;
6734 bool lru = INTVAL (operands[2]) != 0;
6736 return alt[write][lru];
6738 [(set_attr "type" "ild")])
6740 ;; Close the trap shadow of preceding instructions. This is generated
6743 (define_insn "trapb"
6744 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6747 [(set_attr "type" "misc")])
6749 ;; No-op instructions used by machine-dependent reorg to preserve
6750 ;; alignment for instruction issue.
6751 ;; The Unicos/Mk assembler does not support these opcodes.
6757 [(set_attr "type" "ilog")])
6762 "cpys $f31,$f31,$f31"
6763 [(set_attr "type" "fcpys")])
6770 ;; On Unicos/Mk we use a macro for aligning code.
6772 (define_insn "realign"
6773 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6777 if (TARGET_ABI_UNICOSMK)
6778 return "gcc@code@align %0";
6780 return ".align %0 #realign";
6783 ;; The call patterns are at the end of the file because their
6784 ;; wildcard operand0 interferes with nice recognition.
6786 (define_insn "*call_value_osf_1_er"
6787 [(set (match_operand 0 "" "")
6788 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6789 (match_operand 2 "" "")))
6791 (clobber (reg:DI 26))]
6792 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6794 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6796 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6797 [(set_attr "type" "jsr")
6798 (set_attr "length" "12,*,16")])
6800 ;; We must use peep2 instead of a split because we need accurate life
6801 ;; information for $gp. Consider the case of { bar(); while (1); }.
6803 [(parallel [(set (match_operand 0 "" "")
6804 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6805 (match_operand 2 "" "")))
6807 (clobber (reg:DI 26))])]
6808 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6809 && ! current_file_function_operand (operands[1], Pmode)
6810 && peep2_regno_dead_p (1, 29)"
6811 [(parallel [(set (match_dup 0)
6812 (call (mem:DI (match_dup 3))
6814 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6815 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6817 (use (match_dup 4))])]
6819 if (CONSTANT_P (operands[1]))
6821 operands[3] = gen_rtx_REG (Pmode, 27);
6822 operands[4] = GEN_INT (alpha_next_sequence_number++);
6823 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6824 operands[1], operands[4]));
6828 operands[3] = operands[1];
6829 operands[1] = const0_rtx;
6830 operands[4] = const0_rtx;
6835 [(parallel [(set (match_operand 0 "" "")
6836 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6837 (match_operand 2 "" "")))
6839 (clobber (reg:DI 26))])]
6840 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6841 && ! current_file_function_operand (operands[1], Pmode)
6842 && ! peep2_regno_dead_p (1, 29)"
6843 [(parallel [(set (match_dup 0)
6844 (call (mem:DI (match_dup 3))
6846 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6847 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6849 (use (match_dup 5))])
6851 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6853 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6855 if (CONSTANT_P (operands[1]))
6857 operands[3] = gen_rtx_REG (Pmode, 27);
6858 operands[5] = GEN_INT (alpha_next_sequence_number++);
6859 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6860 operands[1], operands[5]));
6864 operands[3] = operands[1];
6865 operands[1] = const0_rtx;
6866 operands[5] = const0_rtx;
6868 operands[4] = GEN_INT (alpha_next_sequence_number++);
6871 ;; We add a blockage unspec_volatile to prevent insns from moving down
6872 ;; from above the call to in between the call and the ldah gpdisp.
6873 (define_insn "*call_value_osf_2_er"
6874 [(set (match_operand 0 "" "")
6875 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6876 (match_operand 2 "" "")))
6878 (plus:DI (pc) (const_int 4)))
6879 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6880 (use (match_operand 3 "" ""))
6881 (use (match_operand 4 "" ""))]
6882 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6883 "jsr $26,(%1),%3%J4"
6884 [(set_attr "type" "jsr")])
6886 (define_insn "*call_value_osf_1_noreturn"
6887 [(set (match_operand 0 "" "")
6888 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6889 (match_operand 2 "" "")))
6891 (clobber (reg:DI 26))]
6892 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6893 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6898 [(set_attr "type" "jsr")
6899 (set_attr "length" "*,*,8")])
6901 (define_insn_and_split "call_value_osf_tlsgd"
6902 [(set (match_operand 0 "" "")
6903 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
6905 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
6907 (clobber (reg:DI 26))]
6910 "&& reload_completed"
6912 (unspec:DI [(match_dup 5)
6914 (match_dup 2)] UNSPEC_LITERAL))
6915 (parallel [(set (match_dup 0)
6916 (call (mem:DI (match_dup 3))
6918 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6919 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
6921 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
6923 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6925 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
6927 operands[3] = gen_rtx_REG (Pmode, 27);
6928 operands[4] = GEN_INT (alpha_next_sequence_number++);
6929 operands[5] = pic_offset_table_rtx;
6931 [(set_attr "type" "multi")])
6933 (define_insn_and_split "call_value_osf_tlsldm"
6934 [(set (match_operand 0 "" "")
6935 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
6937 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
6939 (clobber (reg:DI 26))]
6942 "&& reload_completed"
6944 (unspec:DI [(match_dup 5)
6946 (match_dup 2)] UNSPEC_LITERAL))
6947 (parallel [(set (match_dup 0)
6948 (call (mem:DI (match_dup 3))
6950 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6951 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
6953 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
6955 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6957 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6959 operands[3] = gen_rtx_REG (Pmode, 27);
6960 operands[4] = GEN_INT (alpha_next_sequence_number++);
6961 operands[5] = pic_offset_table_rtx;
6963 [(set_attr "type" "multi")])
6965 (define_insn "*call_value_osf_1"
6966 [(set (match_operand 0 "" "")
6967 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6968 (match_operand 2 "" "")))
6970 (clobber (reg:DI 26))]
6971 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6973 jsr $26,($27),0\;ldgp $29,0($26)
6975 jsr $26,%1\;ldgp $29,0($26)"
6976 [(set_attr "type" "jsr")
6977 (set_attr "length" "12,*,16")])
6979 (define_insn "*sibcall_value_osf_1_er"
6980 [(set (match_operand 0 "" "")
6981 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
6982 (match_operand 2 "" "")))
6983 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
6984 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6987 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
6988 [(set_attr "type" "jsr")
6989 (set_attr "length" "*,8")])
6991 (define_insn "*sibcall_value_osf_1"
6992 [(set (match_operand 0 "" "")
6993 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
6994 (match_operand 2 "" "")))
6995 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
6996 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6999 lda $27,%1\;jmp $31,($27),%1"
7000 [(set_attr "type" "jsr")
7001 (set_attr "length" "*,8")])
7003 (define_insn "*call_value_nt_1"
7004 [(set (match_operand 0 "" "")
7005 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7006 (match_operand 2 "" "")))
7007 (clobber (reg:DI 26))]
7008 "TARGET_ABI_WINDOWS_NT"
7013 [(set_attr "type" "jsr")
7014 (set_attr "length" "*,*,12")])
7016 (define_insn "*call_value_vms_1"
7017 [(set (match_operand 0 "" "")
7018 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7019 (match_operand 2 "" "")))
7020 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
7023 (clobber (reg:DI 27))]
7024 "TARGET_ABI_OPEN_VMS"
7026 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
7027 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
7028 [(set_attr "type" "jsr")
7029 (set_attr "length" "12,16")])
7031 (define_insn "*call_value_umk"
7032 [(set (match_operand 0 "" "")
7033 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
7034 (match_operand 2 "" "")))
7036 (clobber (reg:DI 26))]
7037 "TARGET_ABI_UNICOSMK"
7039 [(set_attr "type" "jsr")])