1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
41 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
42 (UNSPECV_LONGJMP 3) ; builtin_longjmp
44 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
46 (UNSPECV_EHR 7) ; exception_receiver
52 ;; Processor type -- this attribute must exactly match the processor_type
53 ;; enumeration in alpha.h.
55 (define_attr "cpu" "ev4,ev5,ev6"
56 (const (symbol_ref "alpha_cpu")))
58 ;; Define an insn type attribute. This is used in function unit delay
59 ;; computations, among other purposes. For the most part, we use the names
60 ;; defined in the EV4 documentation, but add a few that we have to know about
64 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
65 (const_string "iadd"))
67 ;; Describe a user's asm statement.
68 (define_asm_attributes
69 [(set_attr "type" "multi")])
71 ;; Define the operand size an insn operates on. Used primarily by mul
72 ;; and div operations that have size dependant timings.
74 (define_attr "opsize" "si,di,udi" (const_string "di"))
76 ;; The TRAP_TYPE attribute marks instructions that may generate traps
77 ;; (which are imprecise and may need a trapb if software completion
80 (define_attr "trap" "no,yes" (const_string "no"))
82 ;; The length of an instruction sequence in bytes.
84 (define_attr "length" "" (const_int 4))
86 ;; On EV4 there are two classes of resources to consider: resources needed
87 ;; to issue, and resources needed to execute. IBUS[01] are in the first
88 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
89 ;; (There are a few other register-like resources, but ...)
91 ; First, describe all of the issue constraints with single cycle delays.
92 ; All insns need a bus, but all except loads require one or the other.
93 (define_function_unit "ev4_ibus0" 1 0
94 (and (eq_attr "cpu" "ev4")
95 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
98 (define_function_unit "ev4_ibus1" 1 0
99 (and (eq_attr "cpu" "ev4")
100 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
103 ; Memory delivers its result in three cycles. Actually return one and
104 ; take care of this in adjust_cost, since we want to handle user-defined
106 (define_function_unit "ev4_abox" 1 0
107 (and (eq_attr "cpu" "ev4")
108 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
111 ; Branches have no delay cost, but do tie up the unit for two cycles.
112 (define_function_unit "ev4_bbox" 1 1
113 (and (eq_attr "cpu" "ev4")
114 (eq_attr "type" "ibr,fbr,jsr"))
117 ; Arithmetic insns are normally have their results available after
118 ; two cycles. There are a number of exceptions. They are encoded in
119 ; ADJUST_COST. Some of the other insns have similar exceptions.
120 (define_function_unit "ev4_ebox" 1 0
121 (and (eq_attr "cpu" "ev4")
122 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
125 (define_function_unit "imul" 1 0
126 (and (eq_attr "cpu" "ev4")
127 (and (eq_attr "type" "imul")
128 (eq_attr "opsize" "si")))
131 (define_function_unit "imul" 1 0
132 (and (eq_attr "cpu" "ev4")
133 (and (eq_attr "type" "imul")
134 (eq_attr "opsize" "!si")))
137 (define_function_unit "ev4_fbox" 1 0
138 (and (eq_attr "cpu" "ev4")
139 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
142 (define_function_unit "fdiv" 1 0
143 (and (eq_attr "cpu" "ev4")
144 (and (eq_attr "type" "fdiv")
145 (eq_attr "opsize" "si")))
148 (define_function_unit "fdiv" 1 0
149 (and (eq_attr "cpu" "ev4")
150 (and (eq_attr "type" "fdiv")
151 (eq_attr "opsize" "di")))
154 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
156 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
157 ;; with the combined resource EBOX.
159 (define_function_unit "ev5_ebox" 2 0
160 (and (eq_attr "cpu" "ev5")
161 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
164 ; Memory takes at least 2 clocks. Return one from here and fix up with
165 ; user-defined latencies in adjust_cost.
166 (define_function_unit "ev5_ebox" 2 0
167 (and (eq_attr "cpu" "ev5")
168 (eq_attr "type" "ild,fld,ldsym"))
171 ; Loads can dual issue with one another, but loads and stores do not mix.
172 (define_function_unit "ev5_e0" 1 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "ild,fld,ldsym"))
176 [(eq_attr "type" "ist,fst")])
178 ; Stores, shifts, multiplies can only issue to E0
179 (define_function_unit "ev5_e0" 1 0
180 (and (eq_attr "cpu" "ev5")
181 (eq_attr "type" "ist,fst,shift,imul"))
184 ; Motion video insns also issue only to E0, and take two ticks.
185 (define_function_unit "ev5_e0" 1 0
186 (and (eq_attr "cpu" "ev5")
187 (eq_attr "type" "mvi"))
190 ; Conditional moves always take 2 ticks.
191 (define_function_unit "ev5_ebox" 2 0
192 (and (eq_attr "cpu" "ev5")
193 (eq_attr "type" "icmov"))
196 ; Branches can only issue to E1
197 (define_function_unit "ev5_e1" 1 0
198 (and (eq_attr "cpu" "ev5")
199 (eq_attr "type" "ibr,jsr"))
202 ; Multiplies also use the integer multiplier.
203 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
204 ; cycles before an integer multiplication completes."
205 (define_function_unit "imul" 1 0
206 (and (eq_attr "cpu" "ev5")
207 (and (eq_attr "type" "imul")
208 (eq_attr "opsize" "si")))
211 (define_function_unit "imul" 1 0
212 (and (eq_attr "cpu" "ev5")
213 (and (eq_attr "type" "imul")
214 (eq_attr "opsize" "di")))
217 (define_function_unit "imul" 1 0
218 (and (eq_attr "cpu" "ev5")
219 (and (eq_attr "type" "imul")
220 (eq_attr "opsize" "udi")))
223 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
224 ;; on either so we have to play the game again.
226 (define_function_unit "ev5_fbox" 2 0
227 (and (eq_attr "cpu" "ev5")
228 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
231 (define_function_unit "ev5_fm" 1 0
232 (and (eq_attr "cpu" "ev5")
233 (eq_attr "type" "fmul"))
236 ; Add and cmov as you would expect; fbr never produces a result;
237 ; fdiv issues through fa to the divider,
238 (define_function_unit "ev5_fa" 1 0
239 (and (eq_attr "cpu" "ev5")
240 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
243 ; ??? How to: "No instruction can be issued to pipe FA exactly five
244 ; cycles before a floating point divide completes."
245 (define_function_unit "fdiv" 1 0
246 (and (eq_attr "cpu" "ev5")
247 (and (eq_attr "type" "fdiv")
248 (eq_attr "opsize" "si")))
249 15 15) ; 15 to 31 data dependant
251 (define_function_unit "fdiv" 1 0
252 (and (eq_attr "cpu" "ev5")
253 (and (eq_attr "type" "fdiv")
254 (eq_attr "opsize" "di")))
255 22 22) ; 22 to 60 data dependant
257 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
259 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
260 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
262 ;; Conditional moves decompose into two independant primitives, each
263 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
265 (define_function_unit "ev6_ebox" 4 0
266 (and (eq_attr "cpu" "ev6")
267 (eq_attr "type" "icmov"))
270 (define_function_unit "ev6_ebox" 4 0
271 (and (eq_attr "cpu" "ev6")
272 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
275 ;; Integer loads take at least 3 clocks, and only issue to lower units.
276 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
277 (define_function_unit "ev6_l" 2 0
278 (and (eq_attr "cpu" "ev6")
279 (eq_attr "type" "ild,ldsym,ist,fst"))
282 ;; FP loads take at least 4 clocks. Return two from here...
283 (define_function_unit "ev6_l" 2 0
284 (and (eq_attr "cpu" "ev6")
285 (eq_attr "type" "fld"))
288 ;; Motion video insns also issue only to U0, and take three ticks.
289 (define_function_unit "ev6_u0" 1 0
290 (and (eq_attr "cpu" "ev6")
291 (eq_attr "type" "mvi"))
294 (define_function_unit "ev6_u" 2 0
295 (and (eq_attr "cpu" "ev6")
296 (eq_attr "type" "mvi"))
299 ;; Shifts issue to either upper pipe.
300 (define_function_unit "ev6_u" 2 0
301 (and (eq_attr "cpu" "ev6")
302 (eq_attr "type" "shift"))
305 ;; Multiplies issue only to U1, and all take 7 ticks.
306 ;; Rather than create a new function unit just for U1, reuse IMUL
307 (define_function_unit "imul" 1 0
308 (and (eq_attr "cpu" "ev6")
309 (eq_attr "type" "imul"))
312 (define_function_unit "ev6_u" 2 0
313 (and (eq_attr "cpu" "ev6")
314 (eq_attr "type" "imul"))
317 ;; Branches issue to either upper pipe
318 (define_function_unit "ev6_u" 2 0
319 (and (eq_attr "cpu" "ev6")
320 (eq_attr "type" "ibr"))
323 ;; Calls only issue to L0.
324 (define_function_unit "ev6_l0" 1 0
325 (and (eq_attr "cpu" "ev6")
326 (eq_attr "type" "jsr"))
329 (define_function_unit "ev6_l" 2 0
330 (and (eq_attr "cpu" "ev6")
331 (eq_attr "type" "jsr"))
334 ;; Ftoi/itof only issue to lower pipes
335 (define_function_unit "ev6_l" 2 0
336 (and (eq_attr "cpu" "ev6")
337 (eq_attr "type" "ftoi"))
340 (define_function_unit "ev6_l" 2 0
341 (and (eq_attr "cpu" "ev6")
342 (eq_attr "type" "itof"))
345 ;; For the FPU we are very similar to EV5, except there's no insn that
346 ;; can issue to fm & fa, so we get to leave that out.
348 (define_function_unit "ev6_fm" 1 0
349 (and (eq_attr "cpu" "ev6")
350 (eq_attr "type" "fmul"))
353 (define_function_unit "ev6_fa" 1 0
354 (and (eq_attr "cpu" "ev6")
355 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
358 (define_function_unit "ev6_fa" 1 0
359 (and (eq_attr "cpu" "ev6")
360 (eq_attr "type" "fcmov"))
363 (define_function_unit "fdiv" 1 0
364 (and (eq_attr "cpu" "ev6")
365 (and (eq_attr "type" "fdiv")
366 (eq_attr "opsize" "si")))
369 (define_function_unit "fdiv" 1 0
370 (and (eq_attr "cpu" "ev6")
371 (and (eq_attr "type" "fdiv")
372 (eq_attr "opsize" "di")))
375 (define_function_unit "fsqrt" 1 0
376 (and (eq_attr "cpu" "ev6")
377 (and (eq_attr "type" "fsqrt")
378 (eq_attr "opsize" "si")))
381 (define_function_unit "fsqrt" 1 0
382 (and (eq_attr "cpu" "ev6")
383 (and (eq_attr "type" "fsqrt")
384 (eq_attr "opsize" "di")))
387 ; ??? The FPU communicates with memory and the integer register file
388 ; via two fp store units. We need a slot in the fst immediately, and
389 ; a slot in LOW after the operand data is ready. At which point the
390 ; data may be moved either to the store queue or the integer register
391 ; file and the insn retired.
394 ;; First define the arithmetic insns. Note that the 32-bit forms also
397 ;; Handle 32-64 bit extension from memory to a floating point register
398 ;; specially, since this ocurrs frequently in int->double conversions.
400 ;; Note that while we must retain the =f case in the insn for reload's
401 ;; benefit, it should be eliminated after reload, so we should never emit
402 ;; code for that case. But we don't reject the possibility.
404 (define_expand "extendsidi2"
405 [(set (match_operand:DI 0 "register_operand" "")
406 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
410 (define_insn "*extendsidi2_nofix"
411 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
413 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
419 lds %0,%1\;cvtlq %0,%0"
420 [(set_attr "type" "iadd,ild,fadd,fld")
421 (set_attr "length" "*,*,*,8")])
423 (define_insn "*extendsidi2_fix"
424 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
426 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
433 lds %0,%1\;cvtlq %0,%0"
434 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
435 (set_attr "length" "*,*,*,*,8")])
437 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
439 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
440 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
442 [(set (match_dup 2) (match_dup 1))
443 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
444 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
446 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
447 ;; reload when converting fp->int.
450 [(set (match_operand:SI 0 "hard_int_register_operand" "")
451 (match_operand:SI 1 "memory_operand" ""))
452 (set (match_operand:DI 2 "hard_int_register_operand" "")
453 (sign_extend:DI (match_dup 0)))]
454 "true_regnum (operands[0]) == true_regnum (operands[2])
455 || peep2_reg_dead_p (2, operands[0])"
457 (sign_extend:DI (match_dup 1)))]
461 [(set (match_operand:SI 0 "hard_int_register_operand" "")
462 (match_operand:SI 1 "hard_fp_register_operand" ""))
463 (set (match_operand:DI 2 "hard_int_register_operand" "")
464 (sign_extend:DI (match_dup 0)))]
466 && (true_regnum (operands[0]) == true_regnum (operands[2])
467 || peep2_reg_dead_p (2, operands[0]))"
469 (sign_extend:DI (match_dup 1)))]
473 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
474 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
475 (set (match_operand:DI 2 "hard_int_register_operand" "")
477 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
479 (sign_extend:DI (match_dup 1)))]
482 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
483 ;; generates better code. We have the anonymous addsi3 pattern below in
484 ;; case combine wants to make it.
485 (define_expand "addsi3"
486 [(set (match_operand:SI 0 "register_operand" "")
487 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
488 (match_operand:SI 2 "add_operand" "")))]
494 rtx op1 = gen_lowpart (DImode, operands[1]);
495 rtx op2 = gen_lowpart (DImode, operands[2]);
497 if (! cse_not_expected)
499 rtx tmp = gen_reg_rtx (DImode);
500 emit_insn (gen_adddi3 (tmp, op1, op2));
501 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
504 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
509 (define_insn "*addsi_internal"
510 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
511 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
512 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
521 [(set (match_operand:SI 0 "register_operand" "")
522 (plus:SI (match_operand:SI 1 "register_operand" "")
523 (match_operand:SI 2 "const_int_operand" "")))]
524 "! add_operand (operands[2], SImode)"
525 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
526 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
529 HOST_WIDE_INT val = INTVAL (operands[2]);
530 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
531 HOST_WIDE_INT rest = val - low;
533 operands[3] = GEN_INT (rest);
534 operands[4] = GEN_INT (low);
537 (define_insn "*addsi_se"
538 [(set (match_operand:DI 0 "register_operand" "=r,r")
540 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
541 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
548 [(set (match_operand:DI 0 "register_operand" "")
550 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
551 (match_operand:SI 2 "const_int_operand" ""))))
552 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
553 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
554 && INTVAL (operands[2]) % 4 == 0"
555 [(set (match_dup 3) (match_dup 4))
556 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
561 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
567 operands[4] = GEN_INT (val);
568 operands[5] = GEN_INT (mult);
572 [(set (match_operand:DI 0 "register_operand" "")
574 (plus:SI (match_operator:SI 1 "comparison_operator"
575 [(match_operand 2 "" "")
576 (match_operand 3 "" "")])
577 (match_operand:SI 4 "add_operand" ""))))
578 (clobber (match_operand:DI 5 "register_operand" ""))]
580 [(set (match_dup 5) (match_dup 6))
581 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
584 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
585 operands[2], operands[3]);
586 operands[7] = gen_lowpart (SImode, operands[5]);
589 (define_insn "addvsi3"
590 [(set (match_operand:SI 0 "register_operand" "=r,r")
591 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
592 (match_operand:SI 2 "sext_add_operand" "rI,O")))
593 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
594 (sign_extend:DI (match_dup 2)))
595 (sign_extend:DI (plus:SI (match_dup 1)
603 (define_expand "adddi3"
604 [(set (match_operand:DI 0 "register_operand" "")
605 (plus:DI (match_operand:DI 1 "register_operand" "")
606 (match_operand:DI 2 "add_operand" "")))]
610 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
611 ;; With complications like
613 ;; The NT stack unwind code can't handle a subq to adjust the stack
614 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
615 ;; the exception handling code will loop if a subq is used and an
618 ;; The 19980616 change to emit prologues as RTL also confused some
619 ;; versions of GDB, which also interprets prologues. This has been
620 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
623 ;; and the fact that the three insns schedule exactly the same, it's
624 ;; just not worth the effort.
626 (define_insn "*adddi_internal"
627 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
628 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
629 (match_operand:DI 2 "add_operand" "r,K,L")))]
636 ;; ??? Allow large constants when basing off the frame pointer or some
637 ;; virtual register that may eliminate to the frame pointer. This is
638 ;; done because register elimination offsets will change the hi/lo split,
639 ;; and if we split before reload, we will require additional instructions.
641 (define_insn "*adddi_fp_hack"
642 [(set (match_operand:DI 0 "register_operand" "=r")
643 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
644 (match_operand:DI 2 "const_int_operand" "n")))]
645 "REG_OK_FP_BASE_P (operands[1])
646 && INTVAL (operands[2]) >= 0
647 /* This is the largest constant an lda+ldah pair can add, minus
648 an upper bound on the displacement between SP and AP during
649 register elimination. See INITIAL_ELIMINATION_OFFSET. */
650 && INTVAL (operands[2])
652 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
653 - ALPHA_ROUND(current_function_outgoing_args_size)
654 - (ALPHA_ROUND (get_frame_size ()
655 + max_reg_num () * UNITS_PER_WORD
656 + current_function_pretend_args_size)
657 - current_function_pretend_args_size))"
660 ;; Don't do this if we are adjusting SP since we don't want to do it
661 ;; in two steps. Don't split FP sources for the reason listed above.
663 [(set (match_operand:DI 0 "register_operand" "")
664 (plus:DI (match_operand:DI 1 "register_operand" "")
665 (match_operand:DI 2 "const_int_operand" "")))]
666 "! add_operand (operands[2], DImode)
667 && operands[0] != stack_pointer_rtx
668 && operands[1] != frame_pointer_rtx
669 && operands[1] != arg_pointer_rtx"
670 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
671 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
674 HOST_WIDE_INT val = INTVAL (operands[2]);
675 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
676 HOST_WIDE_INT rest = val - low;
678 operands[4] = GEN_INT (low);
679 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
680 operands[3] = GEN_INT (rest);
681 else if (! no_new_pseudos)
683 operands[3] = gen_reg_rtx (DImode);
684 emit_move_insn (operands[3], operands[2]);
685 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
692 (define_insn "*saddl"
693 [(set (match_operand:SI 0 "register_operand" "=r,r")
694 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
695 (match_operand:SI 2 "const48_operand" "I,I"))
696 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
702 (define_insn "*saddl_se"
703 [(set (match_operand:DI 0 "register_operand" "=r,r")
705 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
706 (match_operand:SI 2 "const48_operand" "I,I"))
707 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
714 [(set (match_operand:DI 0 "register_operand" "")
716 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
717 [(match_operand 2 "" "")
718 (match_operand 3 "" "")])
719 (match_operand:SI 4 "const48_operand" ""))
720 (match_operand:SI 5 "sext_add_operand" ""))))
721 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
723 [(set (match_dup 6) (match_dup 7))
725 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
729 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
730 operands[2], operands[3]);
731 operands[8] = gen_lowpart (SImode, operands[6]);
734 (define_insn "*saddq"
735 [(set (match_operand:DI 0 "register_operand" "=r,r")
736 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
737 (match_operand:DI 2 "const48_operand" "I,I"))
738 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
744 (define_insn "addvdi3"
745 [(set (match_operand:DI 0 "register_operand" "=r,r")
746 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
747 (match_operand:DI 2 "sext_add_operand" "rI,O")))
748 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
749 (sign_extend:TI (match_dup 2)))
750 (sign_extend:TI (plus:DI (match_dup 1)
758 (define_insn "negsi2"
759 [(set (match_operand:SI 0 "register_operand" "=r")
760 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
764 (define_insn "*negsi_se"
765 [(set (match_operand:DI 0 "register_operand" "=r")
766 (sign_extend:DI (neg:SI
767 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
771 (define_insn "negvsi2"
772 [(set (match_operand:SI 0 "register_operand" "=r")
773 (neg:SI (match_operand:SI 1 "register_operand" "r")))
774 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
775 (sign_extend:DI (neg:SI (match_dup 1))))
780 (define_insn "negdi2"
781 [(set (match_operand:DI 0 "register_operand" "=r")
782 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
786 (define_insn "negvdi2"
787 [(set (match_operand:DI 0 "register_operand" "=r")
788 (neg:DI (match_operand:DI 1 "register_operand" "r")))
789 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
790 (sign_extend:TI (neg:DI (match_dup 1))))
795 (define_expand "subsi3"
796 [(set (match_operand:SI 0 "register_operand" "")
797 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
798 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
804 rtx op1 = gen_lowpart (DImode, operands[1]);
805 rtx op2 = gen_lowpart (DImode, operands[2]);
807 if (! cse_not_expected)
809 rtx tmp = gen_reg_rtx (DImode);
810 emit_insn (gen_subdi3 (tmp, op1, op2));
811 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
814 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
819 (define_insn "*subsi_internal"
820 [(set (match_operand:SI 0 "register_operand" "=r")
821 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
822 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
826 (define_insn "*subsi_se"
827 [(set (match_operand:DI 0 "register_operand" "=r")
828 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
829 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
833 (define_insn "subvsi3"
834 [(set (match_operand:SI 0 "register_operand" "=r")
835 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
836 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
837 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
838 (sign_extend:DI (match_dup 2)))
839 (sign_extend:DI (minus:SI (match_dup 1)
845 (define_insn "subdi3"
846 [(set (match_operand:DI 0 "register_operand" "=r")
847 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
848 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
852 (define_insn "*ssubl"
853 [(set (match_operand:SI 0 "register_operand" "=r")
854 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
855 (match_operand:SI 2 "const48_operand" "I"))
856 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
860 (define_insn "*ssubl_se"
861 [(set (match_operand:DI 0 "register_operand" "=r")
863 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
864 (match_operand:SI 2 "const48_operand" "I"))
865 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
869 (define_insn "*ssubq"
870 [(set (match_operand:DI 0 "register_operand" "=r")
871 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
872 (match_operand:DI 2 "const48_operand" "I"))
873 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
877 (define_insn "subvdi3"
878 [(set (match_operand:DI 0 "register_operand" "=r")
879 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
880 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
881 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
882 (sign_extend:TI (match_dup 2)))
883 (sign_extend:TI (minus:DI (match_dup 1)
889 (define_insn "mulsi3"
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
892 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
895 [(set_attr "type" "imul")
896 (set_attr "opsize" "si")])
898 (define_insn "*mulsi_se"
899 [(set (match_operand:DI 0 "register_operand" "=r")
901 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
902 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
905 [(set_attr "type" "imul")
906 (set_attr "opsize" "si")])
908 (define_insn "mulvsi3"
909 [(set (match_operand:SI 0 "register_operand" "=r")
910 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
911 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
912 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
913 (sign_extend:DI (match_dup 2)))
914 (sign_extend:DI (mult:SI (match_dup 1)
919 [(set_attr "type" "imul")
920 (set_attr "opsize" "si")])
922 (define_insn "muldi3"
923 [(set (match_operand:DI 0 "register_operand" "=r")
924 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
925 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
928 [(set_attr "type" "imul")])
930 (define_insn "mulvdi3"
931 [(set (match_operand:DI 0 "register_operand" "=r")
932 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
933 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
934 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
935 (sign_extend:TI (match_dup 2)))
936 (sign_extend:TI (mult:DI (match_dup 1)
941 [(set_attr "type" "imul")])
943 (define_insn "umuldi3_highpart"
944 [(set (match_operand:DI 0 "register_operand" "=r")
947 (mult:TI (zero_extend:TI
948 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
950 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
954 [(set_attr "type" "imul")
955 (set_attr "opsize" "udi")])
957 (define_insn "*umuldi3_highpart_const"
958 [(set (match_operand:DI 0 "register_operand" "=r")
961 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
962 (match_operand:TI 2 "cint8_operand" "I"))
966 [(set_attr "type" "imul")
967 (set_attr "opsize" "udi")])
969 ;; The divide and remainder operations always take their inputs from
970 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
972 ;; ??? Force sign-extension here because some versions of OSF/1 don't
973 ;; do the right thing if the inputs are not properly sign-extended.
974 ;; But Linux, for instance, does not have this problem. Is it worth
975 ;; the complication here to eliminate the sign extension?
976 ;; Interix/NT has the same sign-extension problem.
978 (define_expand "divsi3"
980 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
982 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
983 (parallel [(set (reg:DI 27)
984 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
985 (clobber (reg:DI 23))
986 (clobber (reg:DI 28))])
987 (set (match_operand:SI 0 "nonimmediate_operand" "")
988 (subreg:SI (reg:DI 27) 0))]
992 (define_expand "udivsi3"
994 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
996 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
997 (parallel [(set (reg:DI 27)
998 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
999 (clobber (reg:DI 23))
1000 (clobber (reg:DI 28))])
1001 (set (match_operand:SI 0 "nonimmediate_operand" "")
1002 (subreg:SI (reg:DI 27) 0))]
1006 (define_expand "modsi3"
1008 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1010 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1011 (parallel [(set (reg:DI 27)
1012 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
1013 (clobber (reg:DI 23))
1014 (clobber (reg:DI 28))])
1015 (set (match_operand:SI 0 "nonimmediate_operand" "")
1016 (subreg:SI (reg:DI 27) 0))]
1020 (define_expand "umodsi3"
1022 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1024 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1025 (parallel [(set (reg:DI 27)
1026 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
1027 (clobber (reg:DI 23))
1028 (clobber (reg:DI 28))])
1029 (set (match_operand:SI 0 "nonimmediate_operand" "")
1030 (subreg:SI (reg:DI 27) 0))]
1034 (define_expand "divdi3"
1035 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1036 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1037 (parallel [(set (reg:DI 27)
1040 (clobber (reg:DI 23))
1041 (clobber (reg:DI 28))])
1042 (set (match_operand:DI 0 "nonimmediate_operand" "")
1047 (define_expand "udivdi3"
1048 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1049 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1050 (parallel [(set (reg:DI 27)
1051 (udiv:DI (reg:DI 24)
1053 (clobber (reg:DI 23))
1054 (clobber (reg:DI 28))])
1055 (set (match_operand:DI 0 "nonimmediate_operand" "")
1060 (define_expand "moddi3"
1061 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1062 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1063 (parallel [(set (reg:DI 27)
1066 (clobber (reg:DI 23))
1067 (clobber (reg:DI 28))])
1068 (set (match_operand:DI 0 "nonimmediate_operand" "")
1073 (define_expand "umoddi3"
1074 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1075 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1076 (parallel [(set (reg:DI 27)
1077 (umod:DI (reg:DI 24)
1079 (clobber (reg:DI 23))
1080 (clobber (reg:DI 28))])
1081 (set (match_operand:DI 0 "nonimmediate_operand" "")
1086 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1087 ;; expanded by the assembler.
1088 (define_insn "*divmodsi_internal"
1090 (sign_extend:DI (match_operator:SI 0 "divmod_operator"
1091 [(reg:DI 24) (reg:DI 25)])))
1092 (clobber (reg:DI 23))
1093 (clobber (reg:DI 28))]
1096 [(set_attr "type" "jsr")
1097 (set_attr "length" "8")])
1099 (define_insn "*divmoddi_internal"
1101 (match_operator:DI 0 "divmod_operator"
1102 [(reg:DI 24) (reg:DI 25)]))
1103 (clobber (reg:DI 23))
1104 (clobber (reg:DI 28))]
1107 [(set_attr "type" "jsr")
1108 (set_attr "length" "8")])
1110 ;; Next are the basic logical operations. These only exist in DImode.
1112 (define_insn "anddi3"
1113 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1114 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1115 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1121 [(set_attr "type" "ilog,ilog,shift")])
1123 ;; There are times when we can split an AND into two AND insns. This occurs
1124 ;; when we can first clear any bytes and then clear anything else. For
1125 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1126 ;; Only do this when running on 64-bit host since the computations are
1127 ;; too messy otherwise.
1130 [(set (match_operand:DI 0 "register_operand" "")
1131 (and:DI (match_operand:DI 1 "register_operand" "")
1132 (match_operand:DI 2 "const_int_operand" "")))]
1133 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1134 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1135 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1138 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1139 unsigned HOST_WIDE_INT mask2 = mask1;
1142 /* For each byte that isn't all zeros, make it all ones. */
1143 for (i = 0; i < 64; i += 8)
1144 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1145 mask1 |= (HOST_WIDE_INT) 0xff << i;
1147 /* Now turn on any bits we've just turned off. */
1150 operands[3] = GEN_INT (mask1);
1151 operands[4] = GEN_INT (mask2);
1154 (define_expand "zero_extendqihi2"
1155 [(set (match_operand:HI 0 "register_operand" "")
1156 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1161 operands[1] = force_reg (QImode, operands[1]);
1164 (define_insn "*zero_extendqihi2_bwx"
1165 [(set (match_operand:HI 0 "register_operand" "=r,r")
1166 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1171 [(set_attr "type" "ilog,ild")])
1173 (define_insn "*zero_extendqihi2_nobwx"
1174 [(set (match_operand:HI 0 "register_operand" "=r")
1175 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1178 [(set_attr "type" "ilog")])
1180 (define_expand "zero_extendqisi2"
1181 [(set (match_operand:SI 0 "register_operand" "")
1182 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1187 operands[1] = force_reg (QImode, operands[1]);
1190 (define_insn "*zero_extendqisi2_bwx"
1191 [(set (match_operand:SI 0 "register_operand" "=r,r")
1192 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1197 [(set_attr "type" "ilog,ild")])
1199 (define_insn "*zero_extendqisi2_nobwx"
1200 [(set (match_operand:SI 0 "register_operand" "=r")
1201 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1204 [(set_attr "type" "ilog")])
1206 (define_expand "zero_extendqidi2"
1207 [(set (match_operand:DI 0 "register_operand" "")
1208 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1213 operands[1] = force_reg (QImode, operands[1]);
1216 (define_insn "*zero_extendqidi2_bwx"
1217 [(set (match_operand:DI 0 "register_operand" "=r,r")
1218 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1223 [(set_attr "type" "ilog,ild")])
1225 (define_insn "*zero_extendqidi2_nobwx"
1226 [(set (match_operand:DI 0 "register_operand" "=r")
1227 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1230 [(set_attr "type" "ilog")])
1232 (define_expand "zero_extendhisi2"
1233 [(set (match_operand:SI 0 "register_operand" "")
1234 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1239 operands[1] = force_reg (HImode, operands[1]);
1242 (define_insn "*zero_extendhisi2_bwx"
1243 [(set (match_operand:SI 0 "register_operand" "=r,r")
1244 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1249 [(set_attr "type" "shift,ild")])
1251 (define_insn "*zero_extendhisi2_nobwx"
1252 [(set (match_operand:SI 0 "register_operand" "=r")
1253 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1256 [(set_attr "type" "shift")])
1258 (define_expand "zero_extendhidi2"
1259 [(set (match_operand:DI 0 "register_operand" "")
1260 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1265 operands[1] = force_reg (HImode, operands[1]);
1268 (define_insn "*zero_extendhidi2_bwx"
1269 [(set (match_operand:DI 0 "register_operand" "=r,r")
1270 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1275 [(set_attr "type" "shift,ild")])
1277 (define_insn "*zero_extendhidi2_nobwx"
1278 [(set (match_operand:DI 0 "register_operand" "=r")
1279 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1282 [(set_attr "type" "shift")])
1284 (define_insn "zero_extendsidi2"
1285 [(set (match_operand:DI 0 "register_operand" "=r")
1286 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1289 [(set_attr "type" "shift")])
1291 (define_insn "andnotdi3"
1292 [(set (match_operand:DI 0 "register_operand" "=r")
1293 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1294 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1297 [(set_attr "type" "ilog")])
1299 (define_insn "iordi3"
1300 [(set (match_operand:DI 0 "register_operand" "=r,r")
1301 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1302 (match_operand:DI 2 "or_operand" "rI,N")))]
1307 [(set_attr "type" "ilog")])
1309 (define_insn "one_cmpldi2"
1310 [(set (match_operand:DI 0 "register_operand" "=r")
1311 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1314 [(set_attr "type" "ilog")])
1316 (define_insn "*iornot"
1317 [(set (match_operand:DI 0 "register_operand" "=r")
1318 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1319 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1322 [(set_attr "type" "ilog")])
1324 (define_insn "xordi3"
1325 [(set (match_operand:DI 0 "register_operand" "=r,r")
1326 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1327 (match_operand:DI 2 "or_operand" "rI,N")))]
1332 [(set_attr "type" "ilog")])
1334 (define_insn "*xornot"
1335 [(set (match_operand:DI 0 "register_operand" "=r")
1336 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1337 (match_operand:DI 2 "register_operand" "rI"))))]
1340 [(set_attr "type" "ilog")])
1342 ;; Handle the FFS insn iff we support CIX.
1344 (define_expand "ffsdi2"
1346 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1348 (plus:DI (match_dup 2) (const_int 1)))
1349 (set (match_operand:DI 0 "register_operand" "")
1350 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1351 (const_int 0) (match_dup 3)))]
1355 operands[2] = gen_reg_rtx (DImode);
1356 operands[3] = gen_reg_rtx (DImode);
1359 (define_insn "*cttz"
1360 [(set (match_operand:DI 0 "register_operand" "=r")
1361 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1364 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1365 ; reuse the existing type name.
1366 [(set_attr "type" "mvi")])
1368 ;; Next come the shifts and the various extract and insert operations.
1370 (define_insn "ashldi3"
1371 [(set (match_operand:DI 0 "register_operand" "=r,r")
1372 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1373 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1377 switch (which_alternative)
1380 if (operands[2] == const1_rtx)
1381 return \"addq %r1,%r1,%0\";
1383 return \"s%P2addq %r1,0,%0\";
1385 return \"sll %r1,%2,%0\";
1390 [(set_attr "type" "iadd,shift")])
1392 ;; ??? The following pattern is made by combine, but earlier phases
1393 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1394 ;; with this in a better way at some point.
1396 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1398 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1399 ;; (match_operand:DI 2 "const_int_operand" "P"))
1401 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1404 ;; if (operands[2] == const1_rtx)
1405 ;; return \"addl %r1,%r1,%0\";
1407 ;; return \"s%P2addl %r1,0,%0\";
1409 ;; [(set_attr "type" "iadd")])
1411 (define_insn "lshrdi3"
1412 [(set (match_operand:DI 0 "register_operand" "=r")
1413 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1414 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1417 [(set_attr "type" "shift")])
1419 (define_insn "ashrdi3"
1420 [(set (match_operand:DI 0 "register_operand" "=r")
1421 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1422 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1425 [(set_attr "type" "shift")])
1427 (define_expand "extendqihi2"
1429 (ashift:DI (match_operand:QI 1 "some_operand" "")
1431 (set (match_operand:HI 0 "register_operand" "")
1432 (ashiftrt:DI (match_dup 2)
1439 emit_insn (gen_extendqihi2x (operands[0],
1440 force_reg (QImode, operands[1])));
1444 /* If we have an unaligned MEM, extend to DImode (which we do
1445 specially) and then copy to the result. */
1446 if (unaligned_memory_operand (operands[1], HImode))
1448 rtx temp = gen_reg_rtx (DImode);
1450 emit_insn (gen_extendqidi2 (temp, operands[1]));
1451 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1455 operands[0] = gen_lowpart (DImode, operands[0]);
1456 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1457 operands[2] = gen_reg_rtx (DImode);
1460 (define_insn "extendqidi2x"
1461 [(set (match_operand:DI 0 "register_operand" "=r")
1462 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1465 [(set_attr "type" "shift")])
1467 (define_insn "extendhidi2x"
1468 [(set (match_operand:DI 0 "register_operand" "=r")
1469 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1472 [(set_attr "type" "shift")])
1474 (define_insn "extendqisi2x"
1475 [(set (match_operand:SI 0 "register_operand" "=r")
1476 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1479 [(set_attr "type" "shift")])
1481 (define_insn "extendhisi2x"
1482 [(set (match_operand:SI 0 "register_operand" "=r")
1483 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1486 [(set_attr "type" "shift")])
1488 (define_insn "extendqihi2x"
1489 [(set (match_operand:HI 0 "register_operand" "=r")
1490 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1493 [(set_attr "type" "shift")])
1495 (define_expand "extendqisi2"
1497 (ashift:DI (match_operand:QI 1 "some_operand" "")
1499 (set (match_operand:SI 0 "register_operand" "")
1500 (ashiftrt:DI (match_dup 2)
1507 emit_insn (gen_extendqisi2x (operands[0],
1508 force_reg (QImode, operands[1])));
1512 /* If we have an unaligned MEM, extend to a DImode form of
1513 the result (which we do specially). */
1514 if (unaligned_memory_operand (operands[1], QImode))
1516 rtx temp = gen_reg_rtx (DImode);
1518 emit_insn (gen_extendqidi2 (temp, operands[1]));
1519 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1523 operands[0] = gen_lowpart (DImode, operands[0]);
1524 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1525 operands[2] = gen_reg_rtx (DImode);
1528 (define_expand "extendqidi2"
1530 (ashift:DI (match_operand:QI 1 "some_operand" "")
1532 (set (match_operand:DI 0 "register_operand" "")
1533 (ashiftrt:DI (match_dup 2)
1540 emit_insn (gen_extendqidi2x (operands[0],
1541 force_reg (QImode, operands[1])));
1545 if (unaligned_memory_operand (operands[1], QImode))
1548 = gen_unaligned_extendqidi (operands[0],
1549 get_unaligned_address (operands[1], 1));
1551 alpha_set_memflags (seq, operands[1]);
1556 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1557 operands[2] = gen_reg_rtx (DImode);
1560 (define_expand "extendhisi2"
1562 (ashift:DI (match_operand:HI 1 "some_operand" "")
1564 (set (match_operand:SI 0 "register_operand" "")
1565 (ashiftrt:DI (match_dup 2)
1572 emit_insn (gen_extendhisi2x (operands[0],
1573 force_reg (HImode, operands[1])));
1577 /* If we have an unaligned MEM, extend to a DImode form of
1578 the result (which we do specially). */
1579 if (unaligned_memory_operand (operands[1], HImode))
1581 rtx temp = gen_reg_rtx (DImode);
1583 emit_insn (gen_extendhidi2 (temp, operands[1]));
1584 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1588 operands[0] = gen_lowpart (DImode, operands[0]);
1589 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1590 operands[2] = gen_reg_rtx (DImode);
1593 (define_expand "extendhidi2"
1595 (ashift:DI (match_operand:HI 1 "some_operand" "")
1597 (set (match_operand:DI 0 "register_operand" "")
1598 (ashiftrt:DI (match_dup 2)
1605 emit_insn (gen_extendhidi2x (operands[0],
1606 force_reg (HImode, operands[1])));
1610 if (unaligned_memory_operand (operands[1], HImode))
1613 = gen_unaligned_extendhidi (operands[0],
1614 get_unaligned_address (operands[1], 2));
1616 alpha_set_memflags (seq, operands[1]);
1621 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1622 operands[2] = gen_reg_rtx (DImode);
1625 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1626 ;; as a pattern saves one instruction. The code is similar to that for
1627 ;; the unaligned loads (see below).
1629 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1630 (define_expand "unaligned_extendqidi"
1631 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1633 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1636 (ashift:DI (match_dup 3)
1637 (minus:DI (const_int 64)
1639 (and:DI (match_dup 2) (const_int 7))
1641 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1642 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1645 { operands[2] = gen_reg_rtx (DImode);
1646 operands[3] = gen_reg_rtx (DImode);
1647 operands[4] = gen_reg_rtx (DImode);
1650 (define_expand "unaligned_extendhidi"
1651 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1653 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1656 (ashift:DI (match_dup 3)
1657 (minus:DI (const_int 64)
1659 (and:DI (match_dup 2) (const_int 7))
1661 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1662 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1665 { operands[2] = gen_reg_rtx (DImode);
1666 operands[3] = gen_reg_rtx (DImode);
1667 operands[4] = gen_reg_rtx (DImode);
1670 (define_insn "*extxl_const"
1671 [(set (match_operand:DI 0 "register_operand" "=r")
1672 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1673 (match_operand:DI 2 "mode_width_operand" "n")
1674 (match_operand:DI 3 "mul8_operand" "I")))]
1676 "ext%M2l %r1,%s3,%0"
1677 [(set_attr "type" "shift")])
1679 (define_insn "extxl"
1680 [(set (match_operand:DI 0 "register_operand" "=r")
1681 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1682 (match_operand:DI 2 "mode_width_operand" "n")
1683 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1687 [(set_attr "type" "shift")])
1689 ;; Combine has some strange notion of preserving existing undefined behaviour
1690 ;; in shifts larger than a word size. So capture these patterns that it
1691 ;; should have turned into zero_extracts.
1693 (define_insn "*extxl_1"
1694 [(set (match_operand:DI 0 "register_operand" "=r")
1695 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1696 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1698 (match_operand:DI 3 "mode_mask_operand" "n")))]
1701 [(set_attr "type" "shift")])
1703 (define_insn "*extql_2"
1704 [(set (match_operand:DI 0 "register_operand" "=r")
1705 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1706 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1710 [(set_attr "type" "shift")])
1712 (define_insn "extqh"
1713 [(set (match_operand:DI 0 "register_operand" "=r")
1715 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1716 (minus:DI (const_int 64)
1719 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1724 [(set_attr "type" "shift")])
1726 (define_insn "extlh"
1727 [(set (match_operand:DI 0 "register_operand" "=r")
1729 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1730 (const_int 2147483647))
1731 (minus:DI (const_int 64)
1734 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1739 [(set_attr "type" "shift")])
1741 (define_insn "extwh"
1742 [(set (match_operand:DI 0 "register_operand" "=r")
1744 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1746 (minus:DI (const_int 64)
1749 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1754 [(set_attr "type" "shift")])
1756 ;; This converts an extXl into an extXh with an appropriate adjustment
1757 ;; to the address calculation.
1760 ;; [(set (match_operand:DI 0 "register_operand" "")
1761 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1762 ;; (match_operand:DI 2 "mode_width_operand" "")
1763 ;; (ashift:DI (match_operand:DI 3 "" "")
1765 ;; (match_operand:DI 4 "const_int_operand" "")))
1766 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1767 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1768 ;; [(set (match_dup 5) (match_dup 6))
1769 ;; (set (match_dup 0)
1770 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1771 ;; (ashift:DI (plus:DI (match_dup 5)
1777 ;; operands[6] = plus_constant (operands[3],
1778 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1779 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1782 (define_insn "*insbl_const"
1783 [(set (match_operand:DI 0 "register_operand" "=r")
1784 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1785 (match_operand:DI 2 "mul8_operand" "I")))]
1788 [(set_attr "type" "shift")])
1790 (define_insn "*inswl_const"
1791 [(set (match_operand:DI 0 "register_operand" "=r")
1792 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1793 (match_operand:DI 2 "mul8_operand" "I")))]
1796 [(set_attr "type" "shift")])
1798 (define_insn "*insll_const"
1799 [(set (match_operand:DI 0 "register_operand" "=r")
1800 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1801 (match_operand:DI 2 "mul8_operand" "I")))]
1804 [(set_attr "type" "shift")])
1806 (define_insn "insbl"
1807 [(set (match_operand:DI 0 "register_operand" "=r")
1808 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1809 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1813 [(set_attr "type" "shift")])
1815 (define_insn "inswl"
1816 [(set (match_operand:DI 0 "register_operand" "=r")
1817 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1818 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1822 [(set_attr "type" "shift")])
1824 (define_insn "insll"
1825 [(set (match_operand:DI 0 "register_operand" "=r")
1826 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1827 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1831 [(set_attr "type" "shift")])
1833 (define_insn "insql"
1834 [(set (match_operand:DI 0 "register_operand" "=r")
1835 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1836 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1840 [(set_attr "type" "shift")])
1842 ;; Combine has this sometimes habit of moving the and outside of the
1843 ;; shift, making life more interesting.
1845 (define_insn "*insxl"
1846 [(set (match_operand:DI 0 "register_operand" "=r")
1847 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1848 (match_operand:DI 2 "mul8_operand" "I"))
1849 (match_operand:DI 3 "immediate_operand" "i")))]
1850 "HOST_BITS_PER_WIDE_INT == 64
1851 && GET_CODE (operands[3]) == CONST_INT
1852 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1853 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1854 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1855 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1856 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1857 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1860 #if HOST_BITS_PER_WIDE_INT == 64
1861 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1862 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1863 return \"insbl %1,%s2,%0\";
1864 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1865 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1866 return \"inswl %1,%s2,%0\";
1867 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1868 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1869 return \"insll %1,%s2,%0\";
1873 [(set_attr "type" "shift")])
1875 ;; We do not include the insXh insns because they are complex to express
1876 ;; and it does not appear that we would ever want to generate them.
1878 ;; Since we need them for block moves, though, cop out and use unspec.
1880 (define_insn "insxh"
1881 [(set (match_operand:DI 0 "register_operand" "=r")
1882 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1883 (match_operand:DI 2 "mode_width_operand" "n")
1884 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
1888 [(set_attr "type" "shift")])
1890 (define_insn "mskxl"
1891 [(set (match_operand:DI 0 "register_operand" "=r")
1892 (and:DI (not:DI (ashift:DI
1893 (match_operand:DI 2 "mode_mask_operand" "n")
1895 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1897 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1900 [(set_attr "type" "shift")])
1902 ;; We do not include the mskXh insns because it does not appear we would
1903 ;; ever generate one.
1905 ;; Again, we do for block moves and we use unspec again.
1907 (define_insn "mskxh"
1908 [(set (match_operand:DI 0 "register_operand" "=r")
1909 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1910 (match_operand:DI 2 "mode_width_operand" "n")
1911 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
1915 [(set_attr "type" "shift")])
1917 ;; Prefer AND + NE over LSHIFTRT + AND.
1919 (define_insn_and_split "*ze_and_ne"
1920 [(set (match_operand:DI 0 "register_operand" "=r")
1921 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1923 (match_operand 2 "const_int_operand" "I")))]
1924 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1926 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1928 (and:DI (match_dup 1) (match_dup 3)))
1930 (ne:DI (match_dup 0) (const_int 0)))]
1931 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
1933 ;; Floating-point operations. All the double-precision insns can extend
1934 ;; from single, so indicate that. The exception are the ones that simply
1935 ;; play with the sign bits; it's not clear what to do there.
1937 (define_insn "abssf2"
1938 [(set (match_operand:SF 0 "register_operand" "=f")
1939 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1942 [(set_attr "type" "fcpys")])
1944 (define_insn "*nabssf2"
1945 [(set (match_operand:SF 0 "register_operand" "=f")
1946 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1949 [(set_attr "type" "fadd")])
1951 (define_insn "absdf2"
1952 [(set (match_operand:DF 0 "register_operand" "=f")
1953 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1956 [(set_attr "type" "fcpys")])
1958 (define_insn "*nabsdf2"
1959 [(set (match_operand:DF 0 "register_operand" "=f")
1960 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
1963 [(set_attr "type" "fadd")])
1965 (define_expand "abstf2"
1966 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1967 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1968 (use (match_dup 2))])]
1969 "TARGET_HAS_XFLOATING_LIBS"
1972 #if HOST_BITS_PER_WIDE_INT >= 64
1973 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1975 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1979 (define_insn_and_split "*abstf_internal"
1980 [(set (match_operand:TF 0 "register_operand" "=r")
1981 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1982 (use (match_operand:DI 2 "register_operand" "r"))]
1983 "TARGET_HAS_XFLOATING_LIBS"
1985 "&& reload_completed"
1987 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
1989 (define_insn "negsf2"
1990 [(set (match_operand:SF 0 "register_operand" "=f")
1991 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1994 [(set_attr "type" "fadd")])
1996 (define_insn "negdf2"
1997 [(set (match_operand:DF 0 "register_operand" "=f")
1998 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2001 [(set_attr "type" "fadd")])
2003 (define_expand "negtf2"
2004 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2005 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2006 (use (match_dup 2))])]
2007 "TARGET_HAS_XFLOATING_LIBS"
2010 #if HOST_BITS_PER_WIDE_INT >= 64
2011 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2013 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2017 (define_insn_and_split "*negtf_internal"
2018 [(set (match_operand:TF 0 "register_operand" "=r")
2019 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2020 (use (match_operand:DI 2 "register_operand" "r"))]
2021 "TARGET_HAS_XFLOATING_LIBS"
2023 "&& reload_completed"
2025 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2027 (define_insn "*addsf_ieee"
2028 [(set (match_operand:SF 0 "register_operand" "=&f")
2029 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2030 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2031 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2032 "add%,%)%& %R1,%R2,%0"
2033 [(set_attr "type" "fadd")
2034 (set_attr "trap" "yes")])
2036 (define_insn "addsf3"
2037 [(set (match_operand:SF 0 "register_operand" "=f")
2038 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2039 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2041 "add%,%)%& %R1,%R2,%0"
2042 [(set_attr "type" "fadd")
2043 (set_attr "trap" "yes")])
2045 (define_insn "*adddf_ieee"
2046 [(set (match_operand:DF 0 "register_operand" "=&f")
2047 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2048 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2049 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2050 "add%-%)%& %R1,%R2,%0"
2051 [(set_attr "type" "fadd")
2052 (set_attr "trap" "yes")])
2054 (define_insn "adddf3"
2055 [(set (match_operand:DF 0 "register_operand" "=f")
2056 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2057 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2059 "add%-%)%& %R1,%R2,%0"
2060 [(set_attr "type" "fadd")
2061 (set_attr "trap" "yes")])
2063 (define_insn "*adddf_ext1"
2064 [(set (match_operand:DF 0 "register_operand" "=f")
2065 (plus:DF (float_extend:DF
2066 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2067 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2068 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2069 "add%-%)%& %R1,%R2,%0"
2070 [(set_attr "type" "fadd")
2071 (set_attr "trap" "yes")])
2073 (define_insn "*adddf_ext2"
2074 [(set (match_operand:DF 0 "register_operand" "=f")
2075 (plus:DF (float_extend:DF
2076 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2078 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2079 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2080 "add%-%)%& %R1,%R2,%0"
2081 [(set_attr "type" "fadd")
2082 (set_attr "trap" "yes")])
2084 (define_expand "addtf3"
2085 [(use (match_operand 0 "register_operand" ""))
2086 (use (match_operand 1 "general_operand" ""))
2087 (use (match_operand 2 "general_operand" ""))]
2088 "TARGET_HAS_XFLOATING_LIBS"
2089 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2091 ;; Define conversion operators between DFmode and SImode, using the cvtql
2092 ;; instruction. To allow combine et al to do useful things, we keep the
2093 ;; operation as a unit until after reload, at which point we split the
2096 ;; Note that we (attempt to) only consider this optimization when the
2097 ;; ultimate destination is memory. If we will be doing further integer
2098 ;; processing, it is cheaper to do the truncation in the int regs.
2100 (define_insn "*cvtql"
2101 [(set (match_operand:SI 0 "register_operand" "=f")
2102 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2106 [(set_attr "type" "fadd")
2107 (set_attr "trap" "yes")])
2109 (define_insn_and_split "*fix_truncdfsi_ieee"
2110 [(set (match_operand:SI 0 "memory_operand" "=m")
2111 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2112 (clobber (match_scratch:DI 2 "=&f"))
2113 (clobber (match_scratch:SI 3 "=&f"))]
2114 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2116 "&& reload_completed"
2117 [(set (match_dup 2) (fix:DI (match_dup 1)))
2118 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2119 (set (match_dup 0) (match_dup 3))]
2121 [(set_attr "type" "fadd")
2122 (set_attr "trap" "yes")])
2124 (define_insn_and_split "*fix_truncdfsi_internal"
2125 [(set (match_operand:SI 0 "memory_operand" "=m")
2126 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2127 (clobber (match_scratch:DI 2 "=f"))]
2128 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2130 "&& reload_completed"
2131 [(set (match_dup 2) (fix:DI (match_dup 1)))
2132 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2133 (set (match_dup 0) (match_dup 3))]
2134 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2135 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2136 [(set_attr "type" "fadd")
2137 (set_attr "trap" "yes")])
2139 (define_insn "*fix_truncdfdi_ieee"
2140 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2141 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2142 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2144 [(set_attr "type" "fadd")
2145 (set_attr "trap" "yes")])
2147 (define_insn "fix_truncdfdi2"
2148 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2149 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2152 [(set_attr "type" "fadd")
2153 (set_attr "trap" "yes")])
2155 ;; Likewise between SFmode and SImode.
2157 (define_insn_and_split "*fix_truncsfsi_ieee"
2158 [(set (match_operand:SI 0 "memory_operand" "=m")
2159 (subreg:SI (fix:DI (float_extend:DF
2160 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2161 (clobber (match_scratch:DI 2 "=&f"))
2162 (clobber (match_scratch:SI 3 "=&f"))]
2163 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2165 "&& reload_completed"
2166 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2167 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2168 (set (match_dup 0) (match_dup 3))]
2170 [(set_attr "type" "fadd")
2171 (set_attr "trap" "yes")])
2173 (define_insn_and_split "*fix_truncsfsi_internal"
2174 [(set (match_operand:SI 0 "memory_operand" "=m")
2175 (subreg:SI (fix:DI (float_extend:DF
2176 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2177 (clobber (match_scratch:DI 2 "=f"))]
2178 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2180 "&& reload_completed"
2181 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2182 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2183 (set (match_dup 0) (match_dup 3))]
2184 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2185 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2186 [(set_attr "type" "fadd")
2187 (set_attr "trap" "yes")])
2189 (define_insn "*fix_truncsfdi_ieee"
2190 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2191 (fix:DI (float_extend:DF
2192 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2193 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2195 [(set_attr "type" "fadd")
2196 (set_attr "trap" "yes")])
2198 (define_insn "fix_truncsfdi2"
2199 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2200 (fix:DI (float_extend:DF
2201 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2204 [(set_attr "type" "fadd")
2205 (set_attr "trap" "yes")])
2207 (define_expand "fix_trunctfdi2"
2208 [(use (match_operand:DI 0 "register_operand" ""))
2209 (use (match_operand:TF 1 "general_operand" ""))]
2210 "TARGET_HAS_XFLOATING_LIBS"
2211 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2213 (define_insn "*floatdisf_ieee"
2214 [(set (match_operand:SF 0 "register_operand" "=&f")
2215 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2216 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2218 [(set_attr "type" "fadd")
2219 (set_attr "trap" "yes")])
2221 (define_insn "floatdisf2"
2222 [(set (match_operand:SF 0 "register_operand" "=f")
2223 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2226 [(set_attr "type" "fadd")
2227 (set_attr "trap" "yes")])
2229 (define_insn "*floatdidf_ieee"
2230 [(set (match_operand:DF 0 "register_operand" "=&f")
2231 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2232 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2234 [(set_attr "type" "fadd")
2235 (set_attr "trap" "yes")])
2237 (define_insn "floatdidf2"
2238 [(set (match_operand:DF 0 "register_operand" "=f")
2239 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2242 [(set_attr "type" "fadd")
2243 (set_attr "trap" "yes")])
2245 (define_expand "floatditf2"
2246 [(use (match_operand:TF 0 "register_operand" ""))
2247 (use (match_operand:DI 1 "general_operand" ""))]
2248 "TARGET_HAS_XFLOATING_LIBS"
2249 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2251 (define_expand "floatunsdisf2"
2252 [(use (match_operand:SF 0 "register_operand" ""))
2253 (use (match_operand:DI 1 "register_operand" ""))]
2255 "alpha_emit_floatuns (operands); DONE;")
2257 (define_expand "floatunsdidf2"
2258 [(use (match_operand:DF 0 "register_operand" ""))
2259 (use (match_operand:DI 1 "register_operand" ""))]
2261 "alpha_emit_floatuns (operands); DONE;")
2263 (define_expand "floatunsditf2"
2264 [(use (match_operand:TF 0 "register_operand" ""))
2265 (use (match_operand:DI 1 "general_operand" ""))]
2266 "TARGET_HAS_XFLOATING_LIBS"
2267 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2269 (define_expand "extendsfdf2"
2270 [(set (match_operand:DF 0 "register_operand" "")
2271 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2275 if (alpha_fptm >= ALPHA_FPTM_SU)
2276 operands[1] = force_reg (SFmode, operands[1]);
2279 (define_insn "*extendsfdf2_ieee"
2280 [(set (match_operand:DF 0 "register_operand" "=&f")
2281 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2282 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2284 [(set_attr "type" "fadd")
2285 (set_attr "trap" "yes")])
2287 (define_insn "*extendsfdf2_internal"
2288 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2289 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2290 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2295 [(set_attr "type" "fcpys,fld,fst")])
2297 (define_expand "extendsftf2"
2298 [(use (match_operand:TF 0 "register_operand" ""))
2299 (use (match_operand:SF 1 "general_operand" ""))]
2300 "TARGET_HAS_XFLOATING_LIBS"
2303 rtx tmp = gen_reg_rtx (DFmode);
2304 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2305 emit_insn (gen_extenddftf2 (operands[0], tmp));
2309 (define_expand "extenddftf2"
2310 [(use (match_operand:TF 0 "register_operand" ""))
2311 (use (match_operand:DF 1 "general_operand" ""))]
2312 "TARGET_HAS_XFLOATING_LIBS"
2313 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2315 (define_insn "*truncdfsf2_ieee"
2316 [(set (match_operand:SF 0 "register_operand" "=&f")
2317 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2318 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2319 "cvt%-%,%)%& %R1,%0"
2320 [(set_attr "type" "fadd")
2321 (set_attr "trap" "yes")])
2323 (define_insn "truncdfsf2"
2324 [(set (match_operand:SF 0 "register_operand" "=f")
2325 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2327 "cvt%-%,%)%& %R1,%0"
2328 [(set_attr "type" "fadd")
2329 (set_attr "trap" "yes")])
2331 (define_expand "trunctfdf2"
2332 [(use (match_operand:DF 0 "register_operand" ""))
2333 (use (match_operand:TF 1 "general_operand" ""))]
2334 "TARGET_HAS_XFLOATING_LIBS"
2335 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2337 (define_expand "trunctfsf2"
2338 [(use (match_operand:SF 0 "register_operand" ""))
2339 (use (match_operand:TF 1 "general_operand" ""))]
2340 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2343 rtx tmpf, sticky, arg, lo, hi;
2345 tmpf = gen_reg_rtx (DFmode);
2346 sticky = gen_reg_rtx (DImode);
2347 arg = copy_to_mode_reg (TFmode, operands[1]);
2348 lo = gen_lowpart (DImode, arg);
2349 hi = gen_highpart (DImode, arg);
2351 /* Convert the low word of the TFmode value into a sticky rounding bit,
2352 then or it into the low bit of the high word. This leaves the sticky
2353 bit at bit 48 of the fraction, which is representable in DFmode,
2354 which prevents rounding error in the final conversion to SFmode. */
2356 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2357 gen_rtx_NE (DImode, lo, const0_rtx)));
2358 emit_insn (gen_iordi3 (hi, hi, sticky));
2359 emit_insn (gen_trunctfdf2 (tmpf, arg));
2360 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2364 (define_insn "*divsf3_ieee"
2365 [(set (match_operand:SF 0 "register_operand" "=&f")
2366 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2367 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2368 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2369 "div%,%)%& %R1,%R2,%0"
2370 [(set_attr "type" "fdiv")
2371 (set_attr "opsize" "si")
2372 (set_attr "trap" "yes")])
2374 (define_insn "divsf3"
2375 [(set (match_operand:SF 0 "register_operand" "=f")
2376 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2377 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2379 "div%,%)%& %R1,%R2,%0"
2380 [(set_attr "type" "fdiv")
2381 (set_attr "opsize" "si")
2382 (set_attr "trap" "yes")])
2384 (define_insn "*divdf3_ieee"
2385 [(set (match_operand:DF 0 "register_operand" "=&f")
2386 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2387 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2388 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2389 "div%-%)%& %R1,%R2,%0"
2390 [(set_attr "type" "fdiv")
2391 (set_attr "trap" "yes")])
2393 (define_insn "divdf3"
2394 [(set (match_operand:DF 0 "register_operand" "=f")
2395 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2396 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2398 "div%-%)%& %R1,%R2,%0"
2399 [(set_attr "type" "fdiv")
2400 (set_attr "trap" "yes")])
2402 (define_insn "*divdf_ext1"
2403 [(set (match_operand:DF 0 "register_operand" "=f")
2404 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2405 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2406 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2407 "div%-%)%& %R1,%R2,%0"
2408 [(set_attr "type" "fdiv")
2409 (set_attr "trap" "yes")])
2411 (define_insn "*divdf_ext2"
2412 [(set (match_operand:DF 0 "register_operand" "=f")
2413 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2415 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2416 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2417 "div%-%)%& %R1,%R2,%0"
2418 [(set_attr "type" "fdiv")
2419 (set_attr "trap" "yes")])
2421 (define_insn "*divdf_ext3"
2422 [(set (match_operand:DF 0 "register_operand" "=f")
2423 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2424 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2425 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2426 "div%-%)%& %R1,%R2,%0"
2427 [(set_attr "type" "fdiv")
2428 (set_attr "trap" "yes")])
2430 (define_expand "divtf3"
2431 [(use (match_operand 0 "register_operand" ""))
2432 (use (match_operand 1 "general_operand" ""))
2433 (use (match_operand 2 "general_operand" ""))]
2434 "TARGET_HAS_XFLOATING_LIBS"
2435 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2437 (define_insn "*mulsf3_ieee"
2438 [(set (match_operand:SF 0 "register_operand" "=&f")
2439 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2440 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2441 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2442 "mul%,%)%& %R1,%R2,%0"
2443 [(set_attr "type" "fmul")
2444 (set_attr "trap" "yes")])
2446 (define_insn "mulsf3"
2447 [(set (match_operand:SF 0 "register_operand" "=f")
2448 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2449 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2451 "mul%,%)%& %R1,%R2,%0"
2452 [(set_attr "type" "fmul")
2453 (set_attr "trap" "yes")])
2455 (define_insn "*muldf3_ieee"
2456 [(set (match_operand:DF 0 "register_operand" "=&f")
2457 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2458 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2459 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2460 "mul%-%)%& %R1,%R2,%0"
2461 [(set_attr "type" "fmul")
2462 (set_attr "trap" "yes")])
2464 (define_insn "muldf3"
2465 [(set (match_operand:DF 0 "register_operand" "=f")
2466 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2467 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2469 "mul%-%)%& %R1,%R2,%0"
2470 [(set_attr "type" "fmul")
2471 (set_attr "trap" "yes")])
2473 (define_insn "*muldf_ext1"
2474 [(set (match_operand:DF 0 "register_operand" "=f")
2475 (mult:DF (float_extend:DF
2476 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2477 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2478 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2479 "mul%-%)%& %R1,%R2,%0"
2480 [(set_attr "type" "fmul")
2481 (set_attr "trap" "yes")])
2483 (define_insn "*muldf_ext2"
2484 [(set (match_operand:DF 0 "register_operand" "=f")
2485 (mult:DF (float_extend:DF
2486 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2488 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2489 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2490 "mul%-%)%& %R1,%R2,%0"
2491 [(set_attr "type" "fmul")
2492 (set_attr "trap" "yes")])
2494 (define_expand "multf3"
2495 [(use (match_operand 0 "register_operand" ""))
2496 (use (match_operand 1 "general_operand" ""))
2497 (use (match_operand 2 "general_operand" ""))]
2498 "TARGET_HAS_XFLOATING_LIBS"
2499 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2501 (define_insn "*subsf3_ieee"
2502 [(set (match_operand:SF 0 "register_operand" "=&f")
2503 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2504 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2505 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2506 "sub%,%)%& %R1,%R2,%0"
2507 [(set_attr "type" "fadd")
2508 (set_attr "trap" "yes")])
2510 (define_insn "subsf3"
2511 [(set (match_operand:SF 0 "register_operand" "=f")
2512 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2513 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2515 "sub%,%)%& %R1,%R2,%0"
2516 [(set_attr "type" "fadd")
2517 (set_attr "trap" "yes")])
2519 (define_insn "*subdf3_ieee"
2520 [(set (match_operand:DF 0 "register_operand" "=&f")
2521 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2522 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2523 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2524 "sub%-%)%& %R1,%R2,%0"
2525 [(set_attr "type" "fadd")
2526 (set_attr "trap" "yes")])
2528 (define_insn "subdf3"
2529 [(set (match_operand:DF 0 "register_operand" "=f")
2530 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2531 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2533 "sub%-%)%& %R1,%R2,%0"
2534 [(set_attr "type" "fadd")
2535 (set_attr "trap" "yes")])
2537 (define_insn "*subdf_ext1"
2538 [(set (match_operand:DF 0 "register_operand" "=f")
2539 (minus:DF (float_extend:DF
2540 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2541 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2542 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2543 "sub%-%)%& %R1,%R2,%0"
2544 [(set_attr "type" "fadd")
2545 (set_attr "trap" "yes")])
2547 (define_insn "*subdf_ext2"
2548 [(set (match_operand:DF 0 "register_operand" "=f")
2549 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2551 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2552 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2553 "sub%-%)%& %R1,%R2,%0"
2554 [(set_attr "type" "fadd")
2555 (set_attr "trap" "yes")])
2557 (define_insn "*subdf_ext3"
2558 [(set (match_operand:DF 0 "register_operand" "=f")
2559 (minus:DF (float_extend:DF
2560 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2562 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2563 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2564 "sub%-%)%& %R1,%R2,%0"
2565 [(set_attr "type" "fadd")
2566 (set_attr "trap" "yes")])
2568 (define_expand "subtf3"
2569 [(use (match_operand 0 "register_operand" ""))
2570 (use (match_operand 1 "general_operand" ""))
2571 (use (match_operand 2 "general_operand" ""))]
2572 "TARGET_HAS_XFLOATING_LIBS"
2573 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2575 (define_insn "*sqrtsf2_ieee"
2576 [(set (match_operand:SF 0 "register_operand" "=&f")
2577 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2578 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2580 [(set_attr "type" "fsqrt")
2581 (set_attr "opsize" "si")
2582 (set_attr "trap" "yes")])
2584 (define_insn "sqrtsf2"
2585 [(set (match_operand:SF 0 "register_operand" "=f")
2586 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2587 "TARGET_FP && TARGET_FIX"
2589 [(set_attr "type" "fsqrt")
2590 (set_attr "opsize" "si")
2591 (set_attr "trap" "yes")])
2593 (define_insn "*sqrtdf2_ieee"
2594 [(set (match_operand:DF 0 "register_operand" "=&f")
2595 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2596 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2598 [(set_attr "type" "fsqrt")
2599 (set_attr "trap" "yes")])
2601 (define_insn "sqrtdf2"
2602 [(set (match_operand:DF 0 "register_operand" "=f")
2603 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2604 "TARGET_FP && TARGET_FIX"
2606 [(set_attr "type" "fsqrt")
2607 (set_attr "trap" "yes")])
2609 ;; Next are all the integer comparisons, and conditional moves and branches
2610 ;; and some of the related define_expand's and define_split's.
2612 (define_insn "*setcc_internal"
2613 [(set (match_operand 0 "register_operand" "=r")
2614 (match_operator 1 "alpha_comparison_operator"
2615 [(match_operand:DI 2 "register_operand" "r")
2616 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2617 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2618 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2619 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2621 [(set_attr "type" "icmp")])
2623 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2624 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2626 (define_insn "*setcc_swapped_internal"
2627 [(set (match_operand 0 "register_operand" "=r")
2628 (match_operator 1 "alpha_swapped_comparison_operator"
2629 [(match_operand:DI 2 "register_operand" "r")
2630 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2631 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2632 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2633 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2635 [(set_attr "type" "icmp")])
2637 ;; Use match_operator rather than ne directly so that we can match
2638 ;; multiple integer modes.
2639 (define_insn "*setne_internal"
2640 [(set (match_operand 0 "register_operand" "=r")
2641 (match_operator 1 "signed_comparison_operator"
2642 [(match_operand:DI 2 "register_operand" "r")
2644 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2645 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2646 && GET_CODE (operands[1]) == NE
2647 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2649 [(set_attr "type" "icmp")])
2651 ;; The mode folding trick can't be used with const_int operands, since
2652 ;; reload needs to know the proper mode.
2654 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2655 ;; in order to create more pairs of constants. As long as we're allowing
2656 ;; two constants at the same time, and will have to reload one of them...
2658 (define_insn "*movqicc_internal"
2659 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2661 (match_operator 2 "signed_comparison_operator"
2662 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2663 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2664 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2665 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2666 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2672 [(set_attr "type" "icmov")])
2674 (define_insn "*movhicc_internal"
2675 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2677 (match_operator 2 "signed_comparison_operator"
2678 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2679 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2680 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2681 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2682 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2688 [(set_attr "type" "icmov")])
2690 (define_insn "*movsicc_internal"
2691 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2693 (match_operator 2 "signed_comparison_operator"
2694 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2695 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2696 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2697 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2698 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2704 [(set_attr "type" "icmov")])
2706 (define_insn "*movdicc_internal"
2707 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2709 (match_operator 2 "signed_comparison_operator"
2710 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2711 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2712 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2713 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2714 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2720 [(set_attr "type" "icmov")])
2722 (define_insn "*movqicc_lbc"
2723 [(set (match_operand:QI 0 "register_operand" "=r,r")
2725 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2729 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2730 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2735 [(set_attr "type" "icmov")])
2737 (define_insn "*movhicc_lbc"
2738 [(set (match_operand:HI 0 "register_operand" "=r,r")
2740 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2744 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2745 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2750 [(set_attr "type" "icmov")])
2752 (define_insn "*movsicc_lbc"
2753 [(set (match_operand:SI 0 "register_operand" "=r,r")
2755 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2759 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2760 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2765 [(set_attr "type" "icmov")])
2767 (define_insn "*movdicc_lbc"
2768 [(set (match_operand:DI 0 "register_operand" "=r,r")
2770 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2774 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2775 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2780 [(set_attr "type" "icmov")])
2782 (define_insn "*movqicc_lbs"
2783 [(set (match_operand:QI 0 "register_operand" "=r,r")
2785 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2789 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2790 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2795 [(set_attr "type" "icmov")])
2797 (define_insn "*movhicc_lbs"
2798 [(set (match_operand:HI 0 "register_operand" "=r,r")
2800 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2804 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2805 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2810 [(set_attr "type" "icmov")])
2812 (define_insn "*movsicc_lbs"
2813 [(set (match_operand:SI 0 "register_operand" "=r,r")
2815 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2819 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2820 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2825 [(set_attr "type" "icmov")])
2827 (define_insn "*movdicc_lbs"
2828 [(set (match_operand:DI 0 "register_operand" "=r,r")
2830 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2834 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2835 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2840 [(set_attr "type" "icmov")])
2842 ;; For ABS, we have two choices, depending on whether the input and output
2843 ;; registers are the same or not.
2844 (define_expand "absdi2"
2845 [(set (match_operand:DI 0 "register_operand" "")
2846 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2849 { if (rtx_equal_p (operands[0], operands[1]))
2850 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2852 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2857 (define_expand "absdi2_same"
2858 [(set (match_operand:DI 1 "register_operand" "")
2859 (neg:DI (match_operand:DI 0 "register_operand" "")))
2861 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2867 (define_expand "absdi2_diff"
2868 [(set (match_operand:DI 0 "register_operand" "")
2869 (neg:DI (match_operand:DI 1 "register_operand" "")))
2871 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2878 [(set (match_operand:DI 0 "register_operand" "")
2879 (abs:DI (match_dup 0)))
2880 (clobber (match_operand:DI 1 "register_operand" ""))]
2882 [(set (match_dup 1) (neg:DI (match_dup 0)))
2883 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2884 (match_dup 0) (match_dup 1)))]
2888 [(set (match_operand:DI 0 "register_operand" "")
2889 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2890 "! rtx_equal_p (operands[0], operands[1])"
2891 [(set (match_dup 0) (neg:DI (match_dup 1)))
2892 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2893 (match_dup 0) (match_dup 1)))]
2897 [(set (match_operand:DI 0 "register_operand" "")
2898 (neg:DI (abs:DI (match_dup 0))))
2899 (clobber (match_operand:DI 1 "register_operand" ""))]
2901 [(set (match_dup 1) (neg:DI (match_dup 0)))
2902 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2903 (match_dup 0) (match_dup 1)))]
2907 [(set (match_operand:DI 0 "register_operand" "")
2908 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2909 "! rtx_equal_p (operands[0], operands[1])"
2910 [(set (match_dup 0) (neg:DI (match_dup 1)))
2911 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2912 (match_dup 0) (match_dup 1)))]
2915 (define_insn "sminqi3"
2916 [(set (match_operand:QI 0 "register_operand" "=r")
2917 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2918 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2921 [(set_attr "type" "mvi")])
2923 (define_insn "uminqi3"
2924 [(set (match_operand:QI 0 "register_operand" "=r")
2925 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2926 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2929 [(set_attr "type" "mvi")])
2931 (define_insn "smaxqi3"
2932 [(set (match_operand:QI 0 "register_operand" "=r")
2933 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2934 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2937 [(set_attr "type" "mvi")])
2939 (define_insn "umaxqi3"
2940 [(set (match_operand:QI 0 "register_operand" "=r")
2941 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2942 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2945 [(set_attr "type" "mvi")])
2947 (define_insn "sminhi3"
2948 [(set (match_operand:HI 0 "register_operand" "=r")
2949 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2950 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2953 [(set_attr "type" "mvi")])
2955 (define_insn "uminhi3"
2956 [(set (match_operand:HI 0 "register_operand" "=r")
2957 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2958 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2961 [(set_attr "type" "mvi")])
2963 (define_insn "smaxhi3"
2964 [(set (match_operand:HI 0 "register_operand" "=r")
2965 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2966 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2969 [(set_attr "type" "mvi")])
2971 (define_insn "umaxhi3"
2972 [(set (match_operand:HI 0 "register_operand" "=r")
2973 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2974 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2977 [(set_attr "type" "shift")])
2979 (define_expand "smaxdi3"
2981 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2982 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2983 (set (match_operand:DI 0 "register_operand" "")
2984 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2985 (match_dup 1) (match_dup 2)))]
2988 { operands[3] = gen_reg_rtx (DImode);
2992 [(set (match_operand:DI 0 "register_operand" "")
2993 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2994 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2995 (clobber (match_operand:DI 3 "register_operand" ""))]
2996 "operands[2] != const0_rtx"
2997 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2998 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2999 (match_dup 1) (match_dup 2)))]
3002 (define_insn "*smax_const0"
3003 [(set (match_operand:DI 0 "register_operand" "=r")
3004 (smax:DI (match_operand:DI 1 "register_operand" "0")
3008 [(set_attr "type" "icmov")])
3010 (define_expand "smindi3"
3012 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3013 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3014 (set (match_operand:DI 0 "register_operand" "")
3015 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3016 (match_dup 1) (match_dup 2)))]
3019 { operands[3] = gen_reg_rtx (DImode);
3023 [(set (match_operand:DI 0 "register_operand" "")
3024 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3025 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3026 (clobber (match_operand:DI 3 "register_operand" ""))]
3027 "operands[2] != const0_rtx"
3028 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3029 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3030 (match_dup 1) (match_dup 2)))]
3033 (define_insn "*smin_const0"
3034 [(set (match_operand:DI 0 "register_operand" "=r")
3035 (smin:DI (match_operand:DI 1 "register_operand" "0")
3039 [(set_attr "type" "icmov")])
3041 (define_expand "umaxdi3"
3043 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3044 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3045 (set (match_operand:DI 0 "register_operand" "")
3046 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3047 (match_dup 1) (match_dup 2)))]
3049 "operands[3] = gen_reg_rtx (DImode);")
3052 [(set (match_operand:DI 0 "register_operand" "")
3053 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3054 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3055 (clobber (match_operand:DI 3 "register_operand" ""))]
3056 "operands[2] != const0_rtx"
3057 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3058 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3059 (match_dup 1) (match_dup 2)))]
3062 (define_expand "umindi3"
3064 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3065 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3066 (set (match_operand:DI 0 "register_operand" "")
3067 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3068 (match_dup 1) (match_dup 2)))]
3070 "operands[3] = gen_reg_rtx (DImode);")
3073 [(set (match_operand:DI 0 "register_operand" "")
3074 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3075 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3076 (clobber (match_operand:DI 3 "register_operand" ""))]
3077 "operands[2] != const0_rtx"
3078 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3079 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3080 (match_dup 1) (match_dup 2)))]
3083 (define_insn "*bcc_normal"
3086 (match_operator 1 "signed_comparison_operator"
3087 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3089 (label_ref (match_operand 0 "" ""))
3093 [(set_attr "type" "ibr")])
3095 (define_insn "*bcc_reverse"
3098 (match_operator 1 "signed_comparison_operator"
3099 [(match_operand:DI 2 "register_operand" "r")
3103 (label_ref (match_operand 0 "" ""))))]
3106 [(set_attr "type" "ibr")])
3108 (define_insn "*blbs_normal"
3111 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3115 (label_ref (match_operand 0 "" ""))
3119 [(set_attr "type" "ibr")])
3121 (define_insn "*blbc_normal"
3124 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3128 (label_ref (match_operand 0 "" ""))
3132 [(set_attr "type" "ibr")])
3138 (match_operator 1 "comparison_operator"
3139 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3141 (match_operand:DI 3 "const_int_operand" ""))
3143 (label_ref (match_operand 0 "" ""))
3145 (clobber (match_operand:DI 4 "register_operand" ""))])]
3146 "INTVAL (operands[3]) != 0"
3148 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3150 (if_then_else (match_op_dup 1
3151 [(zero_extract:DI (match_dup 4)
3155 (label_ref (match_dup 0))
3159 ;; The following are the corresponding floating-point insns. Recall
3160 ;; we need to have variants that expand the arguments from SFmode
3163 (define_insn "*cmpdf_ieee"
3164 [(set (match_operand:DF 0 "register_operand" "=&f")
3165 (match_operator:DF 1 "alpha_fp_comparison_operator"
3166 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3167 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3168 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3169 "cmp%-%C1%' %R2,%R3,%0"
3170 [(set_attr "type" "fadd")
3171 (set_attr "trap" "yes")])
3173 (define_insn "*cmpdf_internal"
3174 [(set (match_operand:DF 0 "register_operand" "=f")
3175 (match_operator:DF 1 "alpha_fp_comparison_operator"
3176 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3177 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3178 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3179 "cmp%-%C1%' %R2,%R3,%0"
3180 [(set_attr "type" "fadd")
3181 (set_attr "trap" "yes")])
3183 (define_insn "*cmpdf_ieee_ext1"
3184 [(set (match_operand:DF 0 "register_operand" "=&f")
3185 (match_operator:DF 1 "alpha_fp_comparison_operator"
3187 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3188 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3189 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3190 "cmp%-%C1%' %R2,%R3,%0"
3191 [(set_attr "type" "fadd")
3192 (set_attr "trap" "yes")])
3194 (define_insn "*cmpdf_ext1"
3195 [(set (match_operand:DF 0 "register_operand" "=f")
3196 (match_operator:DF 1 "alpha_fp_comparison_operator"
3198 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3199 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3200 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3201 "cmp%-%C1%' %R2,%R3,%0"
3202 [(set_attr "type" "fadd")
3203 (set_attr "trap" "yes")])
3205 (define_insn "*cmpdf_ieee_ext2"
3206 [(set (match_operand:DF 0 "register_operand" "=&f")
3207 (match_operator:DF 1 "alpha_fp_comparison_operator"
3208 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3210 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3211 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3212 "cmp%-%C1%' %R2,%R3,%0"
3213 [(set_attr "type" "fadd")
3214 (set_attr "trap" "yes")])
3216 (define_insn "*cmpdf_ext2"
3217 [(set (match_operand:DF 0 "register_operand" "=f")
3218 (match_operator:DF 1 "alpha_fp_comparison_operator"
3219 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3221 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3222 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3223 "cmp%-%C1%' %R2,%R3,%0"
3224 [(set_attr "type" "fadd")
3225 (set_attr "trap" "yes")])
3227 (define_insn "*cmpdf_ieee_ext3"
3228 [(set (match_operand:DF 0 "register_operand" "=&f")
3229 (match_operator:DF 1 "alpha_fp_comparison_operator"
3231 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3233 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3234 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3235 "cmp%-%C1%' %R2,%R3,%0"
3236 [(set_attr "type" "fadd")
3237 (set_attr "trap" "yes")])
3239 (define_insn "*cmpdf_ext3"
3240 [(set (match_operand:DF 0 "register_operand" "=f")
3241 (match_operator:DF 1 "alpha_fp_comparison_operator"
3243 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3245 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3246 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3247 "cmp%-%C1%' %R2,%R3,%0"
3248 [(set_attr "type" "fadd")
3249 (set_attr "trap" "yes")])
3251 (define_insn "*movdfcc_internal"
3252 [(set (match_operand:DF 0 "register_operand" "=f,f")
3254 (match_operator 3 "signed_comparison_operator"
3255 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3256 (match_operand:DF 2 "fp0_operand" "G,G")])
3257 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3258 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3262 fcmov%D3 %R4,%R5,%0"
3263 [(set_attr "type" "fcmov")])
3265 (define_insn "*movsfcc_internal"
3266 [(set (match_operand:SF 0 "register_operand" "=f,f")
3268 (match_operator 3 "signed_comparison_operator"
3269 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3270 (match_operand:DF 2 "fp0_operand" "G,G")])
3271 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3272 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3276 fcmov%D3 %R4,%R5,%0"
3277 [(set_attr "type" "fcmov")])
3279 (define_insn "*movdfcc_ext1"
3280 [(set (match_operand:DF 0 "register_operand" "=f,f")
3282 (match_operator 3 "signed_comparison_operator"
3283 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3284 (match_operand:DF 2 "fp0_operand" "G,G")])
3285 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3286 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3290 fcmov%D3 %R4,%R5,%0"
3291 [(set_attr "type" "fcmov")])
3293 (define_insn "*movdfcc_ext2"
3294 [(set (match_operand:DF 0 "register_operand" "=f,f")
3296 (match_operator 3 "signed_comparison_operator"
3298 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3299 (match_operand:DF 2 "fp0_operand" "G,G")])
3300 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3301 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3305 fcmov%D3 %R4,%R5,%0"
3306 [(set_attr "type" "fcmov")])
3308 (define_insn "*movdfcc_ext3"
3309 [(set (match_operand:SF 0 "register_operand" "=f,f")
3311 (match_operator 3 "signed_comparison_operator"
3313 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3314 (match_operand:DF 2 "fp0_operand" "G,G")])
3315 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3316 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3320 fcmov%D3 %R4,%R5,%0"
3321 [(set_attr "type" "fcmov")])
3323 (define_insn "*movdfcc_ext4"
3324 [(set (match_operand:DF 0 "register_operand" "=f,f")
3326 (match_operator 3 "signed_comparison_operator"
3328 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3329 (match_operand:DF 2 "fp0_operand" "G,G")])
3330 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3331 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3335 fcmov%D3 %R4,%R5,%0"
3336 [(set_attr "type" "fcmov")])
3338 (define_expand "maxdf3"
3340 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3341 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3342 (set (match_operand:DF 0 "register_operand" "")
3343 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3344 (match_dup 1) (match_dup 2)))]
3347 { operands[3] = gen_reg_rtx (DFmode);
3348 operands[4] = CONST0_RTX (DFmode);
3351 (define_expand "mindf3"
3353 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3354 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3355 (set (match_operand:DF 0 "register_operand" "")
3356 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3357 (match_dup 1) (match_dup 2)))]
3360 { operands[3] = gen_reg_rtx (DFmode);
3361 operands[4] = CONST0_RTX (DFmode);
3364 (define_expand "maxsf3"
3366 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3367 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3368 (set (match_operand:SF 0 "register_operand" "")
3369 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3370 (match_dup 1) (match_dup 2)))]
3373 { operands[3] = gen_reg_rtx (DFmode);
3374 operands[4] = CONST0_RTX (DFmode);
3377 (define_expand "minsf3"
3379 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3380 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3381 (set (match_operand:SF 0 "register_operand" "")
3382 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3383 (match_dup 1) (match_dup 2)))]
3386 { operands[3] = gen_reg_rtx (DFmode);
3387 operands[4] = CONST0_RTX (DFmode);
3390 (define_insn "*fbcc_normal"
3393 (match_operator 1 "signed_comparison_operator"
3394 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3395 (match_operand:DF 3 "fp0_operand" "G")])
3396 (label_ref (match_operand 0 "" ""))
3400 [(set_attr "type" "fbr")])
3402 (define_insn "*fbcc_ext_normal"
3405 (match_operator 1 "signed_comparison_operator"
3407 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3408 (match_operand:DF 3 "fp0_operand" "G")])
3409 (label_ref (match_operand 0 "" ""))
3413 [(set_attr "type" "fbr")])
3415 ;; These are the main define_expand's used to make conditional branches
3418 (define_expand "cmpdf"
3419 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3420 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3424 alpha_compare.op0 = operands[0];
3425 alpha_compare.op1 = operands[1];
3426 alpha_compare.fp_p = 1;
3430 (define_expand "cmptf"
3431 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3432 (match_operand:TF 1 "general_operand" "")))]
3433 "TARGET_HAS_XFLOATING_LIBS"
3436 alpha_compare.op0 = operands[0];
3437 alpha_compare.op1 = operands[1];
3438 alpha_compare.fp_p = 1;
3442 (define_expand "cmpdi"
3443 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3444 (match_operand:DI 1 "general_operand" "")))]
3448 alpha_compare.op0 = operands[0];
3449 alpha_compare.op1 = operands[1];
3450 alpha_compare.fp_p = 0;
3454 (define_expand "beq"
3456 (if_then_else (match_dup 1)
3457 (label_ref (match_operand 0 "" ""))
3460 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3462 (define_expand "bne"
3464 (if_then_else (match_dup 1)
3465 (label_ref (match_operand 0 "" ""))
3468 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3470 (define_expand "blt"
3472 (if_then_else (match_dup 1)
3473 (label_ref (match_operand 0 "" ""))
3476 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3478 (define_expand "ble"
3480 (if_then_else (match_dup 1)
3481 (label_ref (match_operand 0 "" ""))
3484 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3486 (define_expand "bgt"
3488 (if_then_else (match_dup 1)
3489 (label_ref (match_operand 0 "" ""))
3492 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3494 (define_expand "bge"
3496 (if_then_else (match_dup 1)
3497 (label_ref (match_operand 0 "" ""))
3500 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3502 (define_expand "bltu"
3504 (if_then_else (match_dup 1)
3505 (label_ref (match_operand 0 "" ""))
3508 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3510 (define_expand "bleu"
3512 (if_then_else (match_dup 1)
3513 (label_ref (match_operand 0 "" ""))
3516 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3518 (define_expand "bgtu"
3520 (if_then_else (match_dup 1)
3521 (label_ref (match_operand 0 "" ""))
3524 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3526 (define_expand "bgeu"
3528 (if_then_else (match_dup 1)
3529 (label_ref (match_operand 0 "" ""))
3532 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3534 (define_expand "bunordered"
3536 (if_then_else (match_dup 1)
3537 (label_ref (match_operand 0 "" ""))
3540 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3542 (define_expand "bordered"
3544 (if_then_else (match_dup 1)
3545 (label_ref (match_operand 0 "" ""))
3548 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3550 (define_expand "seq"
3551 [(set (match_operand:DI 0 "register_operand" "")
3554 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3556 (define_expand "sne"
3557 [(set (match_operand:DI 0 "register_operand" "")
3560 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3562 (define_expand "slt"
3563 [(set (match_operand:DI 0 "register_operand" "")
3566 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3568 (define_expand "sle"
3569 [(set (match_operand:DI 0 "register_operand" "")
3572 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3574 (define_expand "sgt"
3575 [(set (match_operand:DI 0 "register_operand" "")
3578 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3580 (define_expand "sge"
3581 [(set (match_operand:DI 0 "register_operand" "")
3584 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3586 (define_expand "sltu"
3587 [(set (match_operand:DI 0 "register_operand" "")
3590 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3592 (define_expand "sleu"
3593 [(set (match_operand:DI 0 "register_operand" "")
3596 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3598 (define_expand "sgtu"
3599 [(set (match_operand:DI 0 "register_operand" "")
3602 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3604 (define_expand "sgeu"
3605 [(set (match_operand:DI 0 "register_operand" "")
3608 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3610 (define_expand "sunordered"
3611 [(set (match_operand:DI 0 "register_operand" "")
3614 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3616 (define_expand "sordered"
3617 [(set (match_operand:DI 0 "register_operand" "")
3620 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3622 ;; These are the main define_expand's used to make conditional moves.
3624 (define_expand "movsicc"
3625 [(set (match_operand:SI 0 "register_operand" "")
3626 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3627 (match_operand:SI 2 "reg_or_8bit_operand" "")
3628 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3632 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3636 (define_expand "movdicc"
3637 [(set (match_operand:DI 0 "register_operand" "")
3638 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3639 (match_operand:DI 2 "reg_or_8bit_operand" "")
3640 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3644 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3648 (define_expand "movsfcc"
3649 [(set (match_operand:SF 0 "register_operand" "")
3650 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3651 (match_operand:SF 2 "reg_or_8bit_operand" "")
3652 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3656 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3660 (define_expand "movdfcc"
3661 [(set (match_operand:DF 0 "register_operand" "")
3662 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3663 (match_operand:DF 2 "reg_or_8bit_operand" "")
3664 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3668 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3672 ;; These define_split definitions are used in cases when comparisons have
3673 ;; not be stated in the correct way and we need to reverse the second
3674 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3675 ;; comparison that tests the result being reversed. We have one define_split
3676 ;; for each use of a comparison. They do not match valid insns and need
3677 ;; not generate valid insns.
3679 ;; We can also handle equality comparisons (and inequality comparisons in
3680 ;; cases where the resulting add cannot overflow) by doing an add followed by
3681 ;; a comparison with zero. This is faster since the addition takes one
3682 ;; less cycle than a compare when feeding into a conditional move.
3683 ;; For this case, we also have an SImode pattern since we can merge the add
3684 ;; and sign extend and the order doesn't matter.
3686 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3687 ;; operation could have been generated.
3690 [(set (match_operand:DI 0 "register_operand" "")
3692 (match_operator 1 "comparison_operator"
3693 [(match_operand:DI 2 "reg_or_0_operand" "")
3694 (match_operand:DI 3 "reg_or_cint_operand" "")])
3695 (match_operand:DI 4 "reg_or_cint_operand" "")
3696 (match_operand:DI 5 "reg_or_cint_operand" "")))
3697 (clobber (match_operand:DI 6 "register_operand" ""))]
3698 "operands[3] != const0_rtx"
3699 [(set (match_dup 6) (match_dup 7))
3701 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3703 { enum rtx_code code = GET_CODE (operands[1]);
3704 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3706 /* If we are comparing for equality with a constant and that constant
3707 appears in the arm when the register equals the constant, use the
3708 register since that is more likely to match (and to produce better code
3711 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3712 && rtx_equal_p (operands[4], operands[3]))
3713 operands[4] = operands[2];
3715 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3716 && rtx_equal_p (operands[5], operands[3]))
3717 operands[5] = operands[2];
3719 if (code == NE || code == EQ
3720 || (extended_count (operands[2], DImode, unsignedp) >= 1
3721 && extended_count (operands[3], DImode, unsignedp) >= 1))
3723 if (GET_CODE (operands[3]) == CONST_INT)
3724 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3725 GEN_INT (- INTVAL (operands[3])));
3727 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3729 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3732 else if (code == EQ || code == LE || code == LT
3733 || code == LEU || code == LTU)
3735 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3736 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3740 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3741 operands[2], operands[3]);
3742 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3747 [(set (match_operand:DI 0 "register_operand" "")
3749 (match_operator 1 "comparison_operator"
3750 [(match_operand:SI 2 "reg_or_0_operand" "")
3751 (match_operand:SI 3 "reg_or_cint_operand" "")])
3752 (match_operand:DI 4 "reg_or_8bit_operand" "")
3753 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3754 (clobber (match_operand:DI 6 "register_operand" ""))]
3755 "operands[3] != const0_rtx
3756 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3757 [(set (match_dup 6) (match_dup 7))
3759 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3761 { enum rtx_code code = GET_CODE (operands[1]);
3762 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3765 if ((code != NE && code != EQ
3766 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3767 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3770 if (GET_CODE (operands[3]) == CONST_INT)
3771 tem = gen_rtx_PLUS (SImode, operands[2],
3772 GEN_INT (- INTVAL (operands[3])));
3774 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3776 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3777 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3778 operands[6], const0_rtx);
3784 (match_operator 1 "comparison_operator"
3785 [(match_operand:DI 2 "reg_or_0_operand" "")
3786 (match_operand:DI 3 "reg_or_cint_operand" "")])
3787 (label_ref (match_operand 0 "" ""))
3789 (clobber (match_operand:DI 4 "register_operand" ""))]
3790 "operands[3] != const0_rtx"
3791 [(set (match_dup 4) (match_dup 5))
3792 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3794 { enum rtx_code code = GET_CODE (operands[1]);
3795 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3797 if (code == NE || code == EQ
3798 || (extended_count (operands[2], DImode, unsignedp) >= 1
3799 && extended_count (operands[3], DImode, unsignedp) >= 1))
3801 if (GET_CODE (operands[3]) == CONST_INT)
3802 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3803 GEN_INT (- INTVAL (operands[3])));
3805 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3807 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3810 else if (code == EQ || code == LE || code == LT
3811 || code == LEU || code == LTU)
3813 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3814 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3818 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3819 operands[2], operands[3]);
3820 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3827 (match_operator 1 "comparison_operator"
3828 [(match_operand:SI 2 "reg_or_0_operand" "")
3829 (match_operand:SI 3 "const_int_operand" "")])
3830 (label_ref (match_operand 0 "" ""))
3832 (clobber (match_operand:DI 4 "register_operand" ""))]
3833 "operands[3] != const0_rtx
3834 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3835 [(set (match_dup 4) (match_dup 5))
3836 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3840 if (GET_CODE (operands[3]) == CONST_INT)
3841 tem = gen_rtx_PLUS (SImode, operands[2],
3842 GEN_INT (- INTVAL (operands[3])));
3844 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3846 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3847 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3848 operands[4], const0_rtx);
3851 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3852 ;; This eliminates one, and sometimes two, insns when the AND can be done
3855 [(set (match_operand:DI 0 "register_operand" "")
3856 (match_operator:DI 1 "comparison_operator"
3857 [(match_operand:DI 2 "register_operand" "")
3858 (match_operand:DI 3 "const_int_operand" "")]))
3859 (clobber (match_operand:DI 4 "register_operand" ""))]
3860 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3861 && (GET_CODE (operands[1]) == GTU
3862 || GET_CODE (operands[1]) == LEU
3863 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3864 && extended_count (operands[2], DImode, 1) > 0))"
3865 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3866 (set (match_dup 0) (match_dup 6))]
3869 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3870 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3871 || GET_CODE (operands[1]) == GT)
3873 DImode, operands[4], const0_rtx);
3876 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
3879 [(set (match_operand 0 "register_operand" "")
3880 (if_then_else (match_operator 1 "signed_comparison_operator"
3881 [(match_operand:DI 2 "reg_or_0_operand" "")
3883 (match_operand 3 "const_int_operand" "")
3884 (match_operand 4 "const_int_operand" "")))]
3889 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
3890 operands[2], operands[3], operands[4]))
3896 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
3897 ;; Oh well, we match it in movcc, so it must be partially our fault.
3899 [(set (match_operand 0 "register_operand" "")
3900 (if_then_else (match_operator 1 "signed_comparison_operator"
3902 (match_operand:DI 2 "reg_or_0_operand" "")])
3903 (match_operand 3 "const_int_operand" "")
3904 (match_operand 4 "const_int_operand" "")))]
3909 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
3910 operands[0], operands[2], operands[3],
3917 (define_insn_and_split "*cmp_sadd_di"
3918 [(set (match_operand:DI 0 "register_operand" "=r")
3919 (plus:DI (if_then_else:DI
3920 (match_operator 1 "alpha_zero_comparison_operator"
3921 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3923 (match_operand:DI 3 "const48_operand" "I")
3925 (match_operand:DI 4 "sext_add_operand" "rIO")))
3926 (clobber (match_scratch:DI 5 "=r"))]
3929 "! no_new_pseudos || reload_completed"
3931 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3933 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
3937 if (! no_new_pseudos)
3938 operands[5] = gen_reg_rtx (DImode);
3939 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3940 operands[5] = operands[0];
3943 (define_insn_and_split "*cmp_sadd_si"
3944 [(set (match_operand:SI 0 "register_operand" "=r")
3945 (plus:SI (if_then_else:SI
3946 (match_operator 1 "alpha_zero_comparison_operator"
3947 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3949 (match_operand:SI 3 "const48_operand" "I")
3951 (match_operand:SI 4 "sext_add_operand" "rIO")))
3952 (clobber (match_scratch:SI 5 "=r"))]
3955 "! no_new_pseudos || reload_completed"
3957 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3959 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3963 if (! no_new_pseudos)
3964 operands[5] = gen_reg_rtx (DImode);
3965 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3966 operands[5] = operands[0];
3969 (define_insn_and_split "*cmp_sadd_sidi"
3970 [(set (match_operand:DI 0 "register_operand" "=r")
3972 (plus:SI (if_then_else:SI
3973 (match_operator 1 "alpha_zero_comparison_operator"
3974 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3976 (match_operand:SI 3 "const48_operand" "I")
3978 (match_operand:SI 4 "sext_add_operand" "rIO"))))
3979 (clobber (match_scratch:SI 5 "=r"))]
3982 "! no_new_pseudos || reload_completed"
3984 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3986 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3990 if (! no_new_pseudos)
3991 operands[5] = gen_reg_rtx (DImode);
3992 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3993 operands[5] = operands[0];
3996 (define_insn_and_split "*cmp_ssub_di"
3997 [(set (match_operand:DI 0 "register_operand" "=r")
3998 (minus:DI (if_then_else:DI
3999 (match_operator 1 "alpha_zero_comparison_operator"
4000 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4002 (match_operand:DI 3 "const48_operand" "I")
4004 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4005 (clobber (match_scratch:DI 5 "=r"))]
4008 "! no_new_pseudos || reload_completed"
4010 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4012 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4016 if (! no_new_pseudos)
4017 operands[5] = gen_reg_rtx (DImode);
4018 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4019 operands[5] = operands[0];
4022 (define_insn_and_split "*cmp_ssub_si"
4023 [(set (match_operand:SI 0 "register_operand" "=r")
4024 (minus:SI (if_then_else:SI
4025 (match_operator 1 "alpha_zero_comparison_operator"
4026 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4028 (match_operand:SI 3 "const48_operand" "I")
4030 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4031 (clobber (match_scratch:SI 5 "=r"))]
4034 "! no_new_pseudos || reload_completed"
4036 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4038 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4042 if (! no_new_pseudos)
4043 operands[5] = gen_reg_rtx (DImode);
4044 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4045 operands[5] = operands[0];
4048 (define_insn_and_split "*cmp_ssub_sidi"
4049 [(set (match_operand:DI 0 "register_operand" "=r")
4051 (minus:SI (if_then_else:SI
4052 (match_operator 1 "alpha_zero_comparison_operator"
4053 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4055 (match_operand:SI 3 "const48_operand" "I")
4057 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4058 (clobber (match_scratch:SI 5 "=r"))]
4061 "! no_new_pseudos || reload_completed"
4063 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4065 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4069 if (! no_new_pseudos)
4070 operands[5] = gen_reg_rtx (DImode);
4071 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4072 operands[5] = operands[0];
4075 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4076 ;; work differently, so we have different patterns for each.
4078 (define_expand "call"
4079 [(use (match_operand:DI 0 "" ""))
4080 (use (match_operand 1 "" ""))
4081 (use (match_operand 2 "" ""))
4082 (use (match_operand 3 "" ""))]
4085 { if (TARGET_WINDOWS_NT)
4086 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4087 else if (TARGET_OPEN_VMS)
4088 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4090 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4095 (define_expand "sibcall"
4096 [(call (mem:DI (match_operand 0 "" ""))
4097 (match_operand 1 "" ""))]
4098 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4101 if (GET_CODE (operands[0]) != MEM)
4103 operands[0] = XEXP (operands[0], 0);
4106 (define_expand "call_osf"
4107 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4108 (match_operand 1 "" ""))
4109 (clobber (reg:DI 27))
4110 (clobber (reg:DI 26))])]
4113 { if (GET_CODE (operands[0]) != MEM)
4116 operands[0] = XEXP (operands[0], 0);
4118 if (GET_CODE (operands[0]) != SYMBOL_REF
4119 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
4121 rtx tem = gen_rtx_REG (DImode, 27);
4122 emit_move_insn (tem, operands[0]);
4127 (define_expand "call_nt"
4128 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4129 (match_operand 1 "" ""))
4130 (clobber (reg:DI 26))])]
4133 { if (GET_CODE (operands[0]) != MEM)
4136 operands[0] = XEXP (operands[0], 0);
4137 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4138 operands[0] = force_reg (DImode, operands[0]);
4142 ;; call openvms/alpha
4143 ;; op 0: symbol ref for called function
4144 ;; op 1: next_arg_reg (argument information value for R25)
4146 (define_expand "call_vms"
4147 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4148 (match_operand 1 "" ""))
4152 (clobber (reg:DI 27))])]
4155 { if (GET_CODE (operands[0]) != MEM)
4158 operands[0] = XEXP (operands[0], 0);
4160 /* Always load AI with argument information, then handle symbolic and
4161 indirect call differently. Load RA and set operands[2] to PV in
4164 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4165 if (GET_CODE (operands[0]) == SYMBOL_REF)
4167 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4169 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4171 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4175 emit_move_insn (gen_rtx_REG (Pmode, 26),
4176 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4177 operands[2] = operands[0];
4182 (define_expand "call_value"
4183 [(use (match_operand 0 "" ""))
4184 (use (match_operand:DI 1 "" ""))
4185 (use (match_operand 2 "" ""))
4186 (use (match_operand 3 "" ""))
4187 (use (match_operand 4 "" ""))]
4190 { if (TARGET_WINDOWS_NT)
4191 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4192 else if (TARGET_OPEN_VMS)
4193 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4196 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4201 (define_expand "sibcall_value"
4202 [(set (match_operand 0 "" "")
4203 (call (mem:DI (match_operand 1 "" ""))
4204 (match_operand 2 "" "")))]
4205 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4208 if (GET_CODE (operands[1]) != MEM)
4210 operands[1] = XEXP (operands[1], 0);
4213 (define_expand "call_value_osf"
4214 [(parallel [(set (match_operand 0 "" "")
4215 (call (mem:DI (match_operand 1 "" ""))
4216 (match_operand 2 "" "")))
4217 (clobber (reg:DI 27))
4218 (clobber (reg:DI 26))])]
4221 { if (GET_CODE (operands[1]) != MEM)
4224 operands[1] = XEXP (operands[1], 0);
4226 if (GET_CODE (operands[1]) != SYMBOL_REF
4227 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
4229 rtx tem = gen_rtx_REG (DImode, 27);
4230 emit_move_insn (tem, operands[1]);
4235 (define_expand "call_value_nt"
4236 [(parallel [(set (match_operand 0 "" "")
4237 (call (mem:DI (match_operand 1 "" ""))
4238 (match_operand 2 "" "")))
4239 (clobber (reg:DI 26))])]
4242 { if (GET_CODE (operands[1]) != MEM)
4245 operands[1] = XEXP (operands[1], 0);
4246 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4247 operands[1] = force_reg (DImode, operands[1]);
4250 (define_expand "call_value_vms"
4251 [(parallel [(set (match_operand 0 "" "")
4252 (call (mem:DI (match_operand:DI 1 "" ""))
4253 (match_operand 2 "" "")))
4257 (clobber (reg:DI 27))])]
4260 { if (GET_CODE (operands[1]) != MEM)
4263 operands[1] = XEXP (operands[1], 0);
4265 /* Always load AI with argument information, then handle symbolic and
4266 indirect call differently. Load RA and set operands[3] to PV in
4269 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4270 if (GET_CODE (operands[1]) == SYMBOL_REF)
4272 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4274 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4276 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4280 emit_move_insn (gen_rtx_REG (Pmode, 26),
4281 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4282 operands[3] = operands[1];
4286 (define_insn "*call_osf_1_noreturn"
4287 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4288 (match_operand 1 "" ""))
4289 (clobber (reg:DI 27))
4290 (clobber (reg:DI 26))]
4291 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS
4292 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4297 [(set_attr "type" "jsr")
4298 (set_attr "length" "*,*,8")])
4300 (define_insn "*call_osf_1"
4301 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4302 (match_operand 1 "" ""))
4303 (clobber (reg:DI 27))
4304 (clobber (reg:DI 26))]
4305 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4307 jsr $26,($27),0\;ldgp $29,0($26)
4309 jsr $26,%0\;ldgp $29,0($26)"
4310 [(set_attr "type" "jsr")
4311 (set_attr "length" "12,*,16")])
4313 (define_insn "*sibcall_osf_1"
4314 [(call (mem:DI (match_operand:DI 0 "call_operand" "R,i"))
4315 (match_operand 1 "" ""))]
4316 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4320 [(set_attr "type" "jsr")
4321 (set_attr "length" "*,8")])
4323 (define_insn "*call_nt_1"
4324 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4325 (match_operand 1 "" ""))
4326 (clobber (reg:DI 26))]
4332 [(set_attr "type" "jsr")
4333 (set_attr "length" "*,*,12")])
4335 (define_insn "*call_vms_1"
4336 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
4337 (match_operand 1 "" ""))
4338 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4341 (clobber (reg:DI 27))]
4344 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4345 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4346 [(set_attr "type" "jsr")
4347 (set_attr "length" "12,16")])
4349 ;; Call subroutine returning any type.
4351 (define_expand "untyped_call"
4352 [(parallel [(call (match_operand 0 "" "")
4354 (match_operand 1 "" "")
4355 (match_operand 2 "" "")])]
4361 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4363 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4365 rtx set = XVECEXP (operands[2], 0, i);
4366 emit_move_insn (SET_DEST (set), SET_SRC (set));
4369 /* The optimizer does not know that the call sets the function value
4370 registers we stored in the result block. We avoid problems by
4371 claiming that all hard registers are used and clobbered at this
4373 emit_insn (gen_blockage ());
4378 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4379 ;; all of memory. This blocks insns from being moved across this point.
4381 (define_insn "blockage"
4382 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4385 [(set_attr "length" "0")])
4389 (label_ref (match_operand 0 "" "")))]
4392 [(set_attr "type" "ibr")])
4394 (define_expand "return"
4399 (define_insn "*return_internal"
4403 [(set_attr "type" "ibr")])
4405 (define_insn "indirect_jump"
4406 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4409 [(set_attr "type" "ibr")])
4411 (define_expand "tablejump"
4412 [(use (match_operand:SI 0 "register_operand" ""))
4413 (use (match_operand:SI 1 "" ""))]
4417 if (TARGET_WINDOWS_NT)
4418 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4419 else if (TARGET_OPEN_VMS)
4420 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4422 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4427 (define_expand "tablejump_osf"
4429 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4430 (parallel [(set (pc)
4431 (plus:DI (match_dup 3)
4432 (label_ref (match_operand 1 "" ""))))
4433 (clobber (match_scratch:DI 2 "=r"))])]
4436 { operands[3] = gen_reg_rtx (DImode); }")
4438 (define_expand "tablejump_nt"
4440 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4441 (parallel [(set (pc)
4443 (use (label_ref (match_operand 1 "" "")))])]
4446 { operands[3] = gen_reg_rtx (DImode); }")
4449 ;; tablejump, openVMS way
4451 ;; op 1: label preceding jump-table
4453 (define_expand "tablejump_vms"
4455 (match_operand:DI 0 "register_operand" ""))
4457 (plus:DI (match_dup 2)
4458 (label_ref (match_operand 1 "" ""))))]
4461 { operands[2] = gen_reg_rtx (DImode); }")
4463 (define_insn "*tablejump_osf_internal"
4465 (plus (match_operand:DI 0 "register_operand" "r")
4466 (label_ref (match_operand 1 "" ""))))
4467 (clobber (match_scratch:DI 2 "=r"))]
4468 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
4469 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4470 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4472 { rtx best_label = 0;
4473 rtx jump_table_insn = next_active_insn (operands[1]);
4475 if (GET_CODE (jump_table_insn) == JUMP_INSN
4476 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4478 rtx jump_table = PATTERN (jump_table_insn);
4479 int n_labels = XVECLEN (jump_table, 1);
4480 int best_count = -1;
4483 for (i = 0; i < n_labels; i++)
4487 for (j = i + 1; j < n_labels; j++)
4488 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4489 == XEXP (XVECEXP (jump_table, 1, j), 0))
4492 if (count > best_count)
4493 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4499 operands[3] = best_label;
4500 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
4503 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
4505 [(set_attr "type" "ibr")
4506 (set_attr "length" "8")])
4508 (define_insn "*tablejump_nt_internal"
4510 (match_operand:DI 0 "register_operand" "r"))
4511 (use (label_ref (match_operand 1 "" "")))]
4512 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
4513 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4514 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4516 { rtx best_label = 0;
4517 rtx jump_table_insn = next_active_insn (operands[1]);
4519 if (GET_CODE (jump_table_insn) == JUMP_INSN
4520 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4522 rtx jump_table = PATTERN (jump_table_insn);
4523 int n_labels = XVECLEN (jump_table, 1);
4524 int best_count = -1;
4527 for (i = 0; i < n_labels; i++)
4531 for (j = i + 1; j < n_labels; j++)
4532 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4533 == XEXP (XVECEXP (jump_table, 1, j), 0))
4536 if (count > best_count)
4537 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4543 operands[2] = best_label;
4544 return \"jmp $31,(%0),%2\";
4547 return \"jmp $31,(%0),0\";
4549 [(set_attr "type" "ibr")])
4552 ;; op 0 is table offset
4553 ;; op 1 is table label
4556 (define_insn "*tablejump_vms_internal"
4558 (plus (match_operand:DI 0 "register_operand" "r")
4559 (label_ref (match_operand 1 "" ""))))]
4562 [(set_attr "type" "ibr")])
4564 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4565 ;; want to have to include pal.h in our .s file.
4567 ;; Technically the type for call_pal is jsr, but we use that for determining
4568 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4571 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4574 [(set_attr "type" "ibr")])
4576 ;; Finally, we have the basic data motion insns. The byte and word insns
4577 ;; are done via define_expand. Start with the floating-point insns, since
4578 ;; they are simpler.
4580 (define_insn "*movsf_nofix"
4581 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4582 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4583 "TARGET_FPREGS && ! TARGET_FIX
4584 && (register_operand (operands[0], SFmode)
4585 || reg_or_fp0_operand (operands[1], SFmode))"
4593 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4595 (define_insn "*movsf_fix"
4596 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4597 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4598 "TARGET_FPREGS && TARGET_FIX
4599 && (register_operand (operands[0], SFmode)
4600 || reg_or_fp0_operand (operands[1], SFmode))"
4610 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4612 (define_insn "*movsf_nofp"
4613 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4614 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4616 && (register_operand (operands[0], SFmode)
4617 || reg_or_fp0_operand (operands[1], SFmode))"
4622 [(set_attr "type" "ilog,ild,ist")])
4624 (define_insn "*movdf_nofix"
4625 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4626 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4627 "TARGET_FPREGS && ! TARGET_FIX
4628 && (register_operand (operands[0], DFmode)
4629 || reg_or_fp0_operand (operands[1], DFmode))"
4637 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4639 (define_insn "*movdf_fix"
4640 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4641 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4642 "TARGET_FPREGS && TARGET_FIX
4643 && (register_operand (operands[0], DFmode)
4644 || reg_or_fp0_operand (operands[1], DFmode))"
4654 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4656 (define_insn "*movdf_nofp"
4657 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4658 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4660 && (register_operand (operands[0], DFmode)
4661 || reg_or_fp0_operand (operands[1], DFmode))"
4666 [(set_attr "type" "ilog,ild,ist")])
4668 ;; Subregs suck for register allocation. Pretend we can move TFmode
4669 ;; data between general registers until after reload.
4671 (define_insn_and_split "*movtf_internal"
4672 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4673 (match_operand:TF 1 "input_operand" "roG,rG"))]
4674 "register_operand (operands[0], TFmode)
4675 || reg_or_fp0_operand (operands[1], TFmode)"
4678 [(set (match_dup 0) (match_dup 2))
4679 (set (match_dup 1) (match_dup 3))]
4682 alpha_split_tfmode_pair (operands);
4683 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4686 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4687 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4691 (define_expand "movsf"
4692 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4693 (match_operand:SF 1 "general_operand" ""))]
4697 if (GET_CODE (operands[0]) == MEM
4698 && ! reg_or_fp0_operand (operands[1], SFmode))
4699 operands[1] = force_reg (SFmode, operands[1]);
4702 (define_expand "movdf"
4703 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4704 (match_operand:DF 1 "general_operand" ""))]
4708 if (GET_CODE (operands[0]) == MEM
4709 && ! reg_or_fp0_operand (operands[1], DFmode))
4710 operands[1] = force_reg (DFmode, operands[1]);
4713 (define_expand "movtf"
4714 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4715 (match_operand:TF 1 "general_operand" ""))]
4719 if (GET_CODE (operands[0]) == MEM
4720 && ! reg_or_fp0_operand (operands[1], TFmode))
4721 operands[1] = force_reg (TFmode, operands[1]);
4724 (define_insn "*movsi_nofix"
4725 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4726 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4727 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4728 && (register_operand (operands[0], SImode)
4729 || reg_or_0_operand (operands[1], SImode))"
4739 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4741 (define_insn "*movsi_fix"
4742 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4743 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4744 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4745 && (register_operand (operands[0], SImode)
4746 || reg_or_0_operand (operands[1], SImode))"
4758 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4760 (define_insn "*movsi_nt_vms"
4761 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4762 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4763 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4764 && (register_operand (operands[0], SImode)
4765 || reg_or_0_operand (operands[1], SImode))"
4776 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4778 (define_insn "*movhi_nobwx"
4779 [(set (match_operand:HI 0 "register_operand" "=r,r")
4780 (match_operand:HI 1 "input_operand" "rJ,n"))]
4782 && (register_operand (operands[0], HImode)
4783 || register_operand (operands[1], HImode))"
4787 [(set_attr "type" "ilog,iadd")])
4789 (define_insn "*movhi_bwx"
4790 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4791 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4793 && (register_operand (operands[0], HImode)
4794 || reg_or_0_operand (operands[1], HImode))"
4800 [(set_attr "type" "ilog,iadd,ild,ist")])
4802 (define_insn "*movqi_nobwx"
4803 [(set (match_operand:QI 0 "register_operand" "=r,r")
4804 (match_operand:QI 1 "input_operand" "rJ,n"))]
4806 && (register_operand (operands[0], QImode)
4807 || register_operand (operands[1], QImode))"
4811 [(set_attr "type" "ilog,iadd")])
4813 (define_insn "*movqi_bwx"
4814 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4815 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4817 && (register_operand (operands[0], QImode)
4818 || reg_or_0_operand (operands[1], QImode))"
4824 [(set_attr "type" "ilog,iadd,ild,ist")])
4826 ;; We do two major things here: handle mem->mem and construct long
4829 (define_expand "movsi"
4830 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4831 (match_operand:SI 1 "general_operand" ""))]
4835 if (GET_CODE (operands[0]) == MEM
4836 && ! reg_or_0_operand (operands[1], SImode))
4837 operands[1] = force_reg (SImode, operands[1]);
4839 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4841 else if (GET_CODE (operands[1]) == CONST_INT)
4844 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4845 if (rtx_equal_p (operands[0], operands[1]))
4850 ;; Split a load of a large constant into the appropriate two-insn
4854 [(set (match_operand:SI 0 "register_operand" "")
4855 (match_operand:SI 1 "const_int_operand" ""))]
4856 "! add_operand (operands[1], SImode)"
4857 [(set (match_dup 0) (match_dup 2))
4858 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4861 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4863 if (tem == operands[0])
4869 (define_insn "*movdi_nofix"
4870 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4871 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4873 && (register_operand (operands[0], DImode)
4874 || reg_or_0_operand (operands[1], DImode))"
4885 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4887 (define_insn "*movdi_fix"
4888 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4889 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4891 && (register_operand (operands[0], DImode)
4892 || reg_or_0_operand (operands[1], DImode))"
4905 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4907 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4908 ;; memory, and construct long 32-bit constants.
4910 (define_expand "movdi"
4911 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4912 (match_operand:DI 1 "general_operand" ""))]
4918 if (GET_CODE (operands[0]) == MEM
4919 && ! reg_or_0_operand (operands[1], DImode))
4920 operands[1] = force_reg (DImode, operands[1]);
4922 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4924 else if (GET_CODE (operands[1]) == CONST_INT
4925 && (tem = alpha_emit_set_const (operands[0], DImode,
4926 INTVAL (operands[1]), 3)) != 0)
4928 if (rtx_equal_p (tem, operands[0]))
4933 else if (CONSTANT_P (operands[1]))
4935 if (TARGET_BUILD_CONSTANTS)
4937 HOST_WIDE_INT i0, i1;
4939 if (GET_CODE (operands[1]) == CONST_INT)
4941 i0 = INTVAL (operands[1]);
4944 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4946 #if HOST_BITS_PER_WIDE_INT >= 64
4947 i0 = CONST_DOUBLE_LOW (operands[1]);
4950 i0 = CONST_DOUBLE_LOW (operands[1]);
4951 i1 = CONST_DOUBLE_HIGH (operands[1]);
4957 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4958 if (rtx_equal_p (tem, operands[0]))
4965 operands[1] = force_const_mem (DImode, operands[1]);
4966 if (reload_in_progress)
4968 emit_move_insn (operands[0], XEXP (operands[1], 0));
4969 operands[1] = copy_rtx (operands[1]);
4970 XEXP (operands[1], 0) = operands[0];
4973 operands[1] = validize_mem (operands[1]);
4980 ;; Split a load of a large constant into the appropriate two-insn
4984 [(set (match_operand:DI 0 "register_operand" "")
4985 (match_operand:DI 1 "const_int_operand" ""))]
4986 "! add_operand (operands[1], DImode)"
4987 [(set (match_dup 0) (match_dup 2))
4988 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4991 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4993 if (tem == operands[0])
4999 ;; These are the partial-word cases.
5001 ;; First we have the code to load an aligned word. Operand 0 is the register
5002 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5003 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5004 ;; number of bits within the word that the value is. Operand 3 is an SImode
5005 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5006 ;; same register. It is allowed to conflict with operand 1 as well.
5008 (define_expand "aligned_loadqi"
5009 [(set (match_operand:SI 3 "register_operand" "")
5010 (match_operand:SI 1 "memory_operand" ""))
5011 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5012 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5014 (match_operand:DI 2 "const_int_operand" "")))]
5019 (define_expand "aligned_loadhi"
5020 [(set (match_operand:SI 3 "register_operand" "")
5021 (match_operand:SI 1 "memory_operand" ""))
5022 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5023 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5025 (match_operand:DI 2 "const_int_operand" "")))]
5030 ;; Similar for unaligned loads, where we use the sequence from the
5031 ;; Alpha Architecture manual.
5033 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5034 ;; operand 3 can overlap the input and output registers.
5036 (define_expand "unaligned_loadqi"
5037 [(set (match_operand:DI 2 "register_operand" "")
5038 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5040 (set (match_operand:DI 3 "register_operand" "")
5042 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5043 (zero_extract:DI (match_dup 2)
5045 (ashift:DI (match_dup 3) (const_int 3))))]
5049 (define_expand "unaligned_loadhi"
5050 [(set (match_operand:DI 2 "register_operand" "")
5051 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5053 (set (match_operand:DI 3 "register_operand" "")
5055 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5056 (zero_extract:DI (match_dup 2)
5058 (ashift:DI (match_dup 3) (const_int 3))))]
5062 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5063 ;; aligned SImode MEM. Operand 1 is the register containing the
5064 ;; byte or word to store. Operand 2 is the number of bits within the word that
5065 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5067 (define_expand "aligned_store"
5068 [(set (match_operand:SI 3 "register_operand" "")
5069 (match_operand:SI 0 "memory_operand" ""))
5070 (set (subreg:DI (match_dup 3) 0)
5071 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5072 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5073 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5074 (match_operand:DI 2 "const_int_operand" "")))
5075 (set (subreg:DI (match_dup 4) 0)
5076 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5077 (set (match_dup 0) (match_dup 4))]
5080 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5081 << INTVAL (operands[2])));
5084 ;; For the unaligned byte and halfword cases, we use code similar to that
5085 ;; in the ;; Architecture book, but reordered to lower the number of registers
5086 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5087 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5088 ;; be the same temporary, if desired. If the address is in a register,
5089 ;; operand 2 can be that register.
5091 (define_expand "unaligned_storeqi"
5092 [(set (match_operand:DI 3 "register_operand" "")
5093 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5095 (set (match_operand:DI 2 "register_operand" "")
5098 (and:DI (not:DI (ashift:DI (const_int 255)
5099 (ashift:DI (match_dup 2) (const_int 3))))
5101 (set (match_operand:DI 4 "register_operand" "")
5102 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5103 (ashift:DI (match_dup 2) (const_int 3))))
5104 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5105 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5110 (define_expand "unaligned_storehi"
5111 [(set (match_operand:DI 3 "register_operand" "")
5112 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5114 (set (match_operand:DI 2 "register_operand" "")
5117 (and:DI (not:DI (ashift:DI (const_int 65535)
5118 (ashift:DI (match_dup 2) (const_int 3))))
5120 (set (match_operand:DI 4 "register_operand" "")
5121 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5122 (ashift:DI (match_dup 2) (const_int 3))))
5123 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5124 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5129 ;; Here are the define_expand's for QI and HI moves that use the above
5130 ;; patterns. We have the normal sets, plus the ones that need scratch
5131 ;; registers for reload.
5133 (define_expand "movqi"
5134 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5135 (match_operand:QI 1 "general_operand" ""))]
5141 if (GET_CODE (operands[0]) == MEM
5142 && ! reg_or_0_operand (operands[1], QImode))
5143 operands[1] = force_reg (QImode, operands[1]);
5145 if (GET_CODE (operands[1]) == CONST_INT
5146 && ! input_operand (operands[1], QImode))
5148 operands[1] = alpha_emit_set_const (operands[0], QImode,
5149 INTVAL (operands[1]), 3);
5151 if (rtx_equal_p (operands[0], operands[1]))
5158 /* If the output is not a register, the input must be. */
5159 if (GET_CODE (operands[0]) == MEM)
5160 operands[1] = force_reg (QImode, operands[1]);
5162 /* Handle four memory cases, unaligned and aligned for either the input
5163 or the output. The only case where we can be called during reload is
5164 for aligned loads; all other cases require temporaries. */
5166 if (GET_CODE (operands[1]) == MEM
5167 || (GET_CODE (operands[1]) == SUBREG
5168 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5169 || (reload_in_progress && GET_CODE (operands[1]) == REG
5170 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5171 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5172 && GET_CODE (SUBREG_REG (operands[1])) == REG
5173 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5175 if (aligned_memory_operand (operands[1], QImode))
5177 if (reload_in_progress)
5179 emit_insn (gen_reload_inqi_help
5180 (operands[0], operands[1],
5181 gen_rtx_REG (SImode, REGNO (operands[0]))));
5185 rtx aligned_mem, bitnum;
5186 rtx scratch = gen_reg_rtx (SImode);
5188 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5190 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5196 /* Don't pass these as parameters since that makes the generated
5197 code depend on parameter evaluation order which will cause
5198 bootstrap failures. */
5200 rtx temp1 = gen_reg_rtx (DImode);
5201 rtx temp2 = gen_reg_rtx (DImode);
5203 = gen_unaligned_loadqi (operands[0],
5204 get_unaligned_address (operands[1], 0),
5207 alpha_set_memflags (seq, operands[1]);
5214 else if (GET_CODE (operands[0]) == MEM
5215 || (GET_CODE (operands[0]) == SUBREG
5216 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5217 || (reload_in_progress && GET_CODE (operands[0]) == REG
5218 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5219 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5220 && GET_CODE (SUBREG_REG (operands[0])) == REG
5221 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5223 if (aligned_memory_operand (operands[0], QImode))
5225 rtx aligned_mem, bitnum;
5226 rtx temp1 = gen_reg_rtx (SImode);
5227 rtx temp2 = gen_reg_rtx (SImode);
5229 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5231 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5236 rtx temp1 = gen_reg_rtx (DImode);
5237 rtx temp2 = gen_reg_rtx (DImode);
5238 rtx temp3 = gen_reg_rtx (DImode);
5240 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
5241 operands[1], temp1, temp2, temp3);
5243 alpha_set_memflags (seq, operands[0]);
5251 (define_expand "movhi"
5252 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5253 (match_operand:HI 1 "general_operand" ""))]
5259 if (GET_CODE (operands[0]) == MEM
5260 && ! reg_or_0_operand (operands[1], HImode))
5261 operands[1] = force_reg (HImode, operands[1]);
5263 if (GET_CODE (operands[1]) == CONST_INT
5264 && ! input_operand (operands[1], HImode))
5266 operands[1] = alpha_emit_set_const (operands[0], HImode,
5267 INTVAL (operands[1]), 3);
5269 if (rtx_equal_p (operands[0], operands[1]))
5276 /* If the output is not a register, the input must be. */
5277 if (GET_CODE (operands[0]) == MEM)
5278 operands[1] = force_reg (HImode, operands[1]);
5280 /* Handle four memory cases, unaligned and aligned for either the input
5281 or the output. The only case where we can be called during reload is
5282 for aligned loads; all other cases require temporaries. */
5284 if (GET_CODE (operands[1]) == MEM
5285 || (GET_CODE (operands[1]) == SUBREG
5286 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5287 || (reload_in_progress && GET_CODE (operands[1]) == REG
5288 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5289 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5290 && GET_CODE (SUBREG_REG (operands[1])) == REG
5291 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5293 if (aligned_memory_operand (operands[1], HImode))
5295 if (reload_in_progress)
5297 emit_insn (gen_reload_inhi_help
5298 (operands[0], operands[1],
5299 gen_rtx_REG (SImode, REGNO (operands[0]))));
5303 rtx aligned_mem, bitnum;
5304 rtx scratch = gen_reg_rtx (SImode);
5306 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5308 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5314 /* Don't pass these as parameters since that makes the generated
5315 code depend on parameter evaluation order which will cause
5316 bootstrap failures. */
5318 rtx temp1 = gen_reg_rtx (DImode);
5319 rtx temp2 = gen_reg_rtx (DImode);
5321 = gen_unaligned_loadhi (operands[0],
5322 get_unaligned_address (operands[1], 0),
5325 alpha_set_memflags (seq, operands[1]);
5332 else if (GET_CODE (operands[0]) == MEM
5333 || (GET_CODE (operands[0]) == SUBREG
5334 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5335 || (reload_in_progress && GET_CODE (operands[0]) == REG
5336 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5337 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5338 && GET_CODE (SUBREG_REG (operands[0])) == REG
5339 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5341 if (aligned_memory_operand (operands[0], HImode))
5343 rtx aligned_mem, bitnum;
5344 rtx temp1 = gen_reg_rtx (SImode);
5345 rtx temp2 = gen_reg_rtx (SImode);
5347 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5349 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5354 rtx temp1 = gen_reg_rtx (DImode);
5355 rtx temp2 = gen_reg_rtx (DImode);
5356 rtx temp3 = gen_reg_rtx (DImode);
5358 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
5359 operands[1], temp1, temp2, temp3);
5361 alpha_set_memflags (seq, operands[0]);
5370 ;; Here are the versions for reload. Note that in the unaligned cases
5371 ;; we know that the operand must not be a pseudo-register because stack
5372 ;; slots are always aligned references.
5374 (define_expand "reload_inqi"
5375 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5376 (match_operand:QI 1 "any_memory_operand" "m")
5377 (match_operand:TI 2 "register_operand" "=&r")])]
5383 if (GET_CODE (operands[1]) != MEM)
5386 if (aligned_memory_operand (operands[1], QImode))
5388 seq = gen_reload_inqi_help (operands[0], operands[1],
5389 gen_rtx_REG (SImode, REGNO (operands[2])));
5395 /* It is possible that one of the registers we got for operands[2]
5396 might coincide with that of operands[0] (which is why we made
5397 it TImode). Pick the other one to use as our scratch. */
5398 if (REGNO (operands[0]) == REGNO (operands[2]))
5399 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5401 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5403 addr = get_unaligned_address (operands[1], 0);
5404 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5405 gen_rtx_REG (DImode, REGNO (operands[0])));
5406 alpha_set_memflags (seq, operands[1]);
5412 (define_expand "reload_inhi"
5413 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5414 (match_operand:HI 1 "any_memory_operand" "m")
5415 (match_operand:TI 2 "register_operand" "=&r")])]
5421 if (GET_CODE (operands[1]) != MEM)
5424 if (aligned_memory_operand (operands[1], HImode))
5426 seq = gen_reload_inhi_help (operands[0], operands[1],
5427 gen_rtx_REG (SImode, REGNO (operands[2])));
5433 /* It is possible that one of the registers we got for operands[2]
5434 might coincide with that of operands[0] (which is why we made
5435 it TImode). Pick the other one to use as our scratch. */
5436 if (REGNO (operands[0]) == REGNO (operands[2]))
5437 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5439 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5441 addr = get_unaligned_address (operands[1], 0);
5442 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5443 gen_rtx_REG (DImode, REGNO (operands[0])));
5444 alpha_set_memflags (seq, operands[1]);
5450 (define_expand "reload_outqi"
5451 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5452 (match_operand:QI 1 "register_operand" "r")
5453 (match_operand:TI 2 "register_operand" "=&r")])]
5457 if (GET_CODE (operands[0]) != MEM)
5460 if (aligned_memory_operand (operands[0], QImode))
5462 emit_insn (gen_reload_outqi_help
5463 (operands[0], operands[1],
5464 gen_rtx_REG (SImode, REGNO (operands[2])),
5465 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5469 rtx addr = get_unaligned_address (operands[0], 0);
5470 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5471 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5472 rtx scratch3 = scratch1;
5475 if (GET_CODE (addr) == REG)
5478 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5479 scratch2, scratch3);
5480 alpha_set_memflags (seq, operands[0]);
5486 (define_expand "reload_outhi"
5487 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5488 (match_operand:HI 1 "register_operand" "r")
5489 (match_operand:TI 2 "register_operand" "=&r")])]
5493 if (GET_CODE (operands[0]) != MEM)
5496 if (aligned_memory_operand (operands[0], HImode))
5498 emit_insn (gen_reload_outhi_help
5499 (operands[0], operands[1],
5500 gen_rtx_REG (SImode, REGNO (operands[2])),
5501 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5505 rtx addr = get_unaligned_address (operands[0], 0);
5506 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5507 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5508 rtx scratch3 = scratch1;
5511 if (GET_CODE (addr) == REG)
5514 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5515 scratch2, scratch3);
5516 alpha_set_memflags (seq, operands[0]);
5522 ;; Helpers for the above. The way reload is structured, we can't
5523 ;; always get a proper address for a stack slot during reload_foo
5524 ;; expansion, so we must delay our address manipulations until after.
5526 (define_insn "reload_inqi_help"
5527 [(set (match_operand:QI 0 "register_operand" "=r")
5528 (match_operand:QI 1 "memory_operand" "m"))
5529 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5530 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5533 (define_insn "reload_inhi_help"
5534 [(set (match_operand:HI 0 "register_operand" "=r")
5535 (match_operand:HI 1 "memory_operand" "m"))
5536 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5537 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5540 (define_insn "reload_outqi_help"
5541 [(set (match_operand:QI 0 "memory_operand" "=m")
5542 (match_operand:QI 1 "register_operand" "r"))
5543 (clobber (match_operand:SI 2 "register_operand" "=r"))
5544 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5545 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5548 (define_insn "reload_outhi_help"
5549 [(set (match_operand:HI 0 "memory_operand" "=m")
5550 (match_operand:HI 1 "register_operand" "r"))
5551 (clobber (match_operand:SI 2 "register_operand" "=r"))
5552 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5553 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5557 [(set (match_operand:QI 0 "register_operand" "")
5558 (match_operand:QI 1 "memory_operand" ""))
5559 (clobber (match_operand:SI 2 "register_operand" ""))]
5560 "! TARGET_BWX && reload_completed"
5564 rtx aligned_mem, bitnum;
5565 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5566 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5572 [(set (match_operand:HI 0 "register_operand" "")
5573 (match_operand:HI 1 "memory_operand" ""))
5574 (clobber (match_operand:SI 2 "register_operand" ""))]
5575 "! TARGET_BWX && reload_completed"
5579 rtx aligned_mem, bitnum;
5580 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5581 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5587 [(set (match_operand:QI 0 "memory_operand" "")
5588 (match_operand:QI 1 "register_operand" ""))
5589 (clobber (match_operand:SI 2 "register_operand" ""))
5590 (clobber (match_operand:SI 3 "register_operand" ""))]
5591 "! TARGET_BWX && reload_completed"
5595 rtx aligned_mem, bitnum;
5596 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5597 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5598 operands[2], operands[3]));
5603 [(set (match_operand:HI 0 "memory_operand" "")
5604 (match_operand:HI 1 "register_operand" ""))
5605 (clobber (match_operand:SI 2 "register_operand" ""))
5606 (clobber (match_operand:SI 3 "register_operand" ""))]
5607 "! TARGET_BWX && reload_completed"
5611 rtx aligned_mem, bitnum;
5612 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5613 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5614 operands[2], operands[3]));
5618 ;; Bit field extract patterns which use ext[wlq][lh]
5620 (define_expand "extv"
5621 [(set (match_operand:DI 0 "register_operand" "")
5622 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5623 (match_operand:DI 2 "immediate_operand" "")
5624 (match_operand:DI 3 "immediate_operand" "")))]
5628 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5629 if (INTVAL (operands[3]) % 8 != 0
5630 || (INTVAL (operands[2]) != 16
5631 && INTVAL (operands[2]) != 32
5632 && INTVAL (operands[2]) != 64))
5635 /* From mips.md: extract_bit_field doesn't verify that our source
5636 matches the predicate, so we force it to be a MEM here. */
5637 if (GET_CODE (operands[1]) != MEM)
5640 alpha_expand_unaligned_load (operands[0], operands[1],
5641 INTVAL (operands[2]) / 8,
5642 INTVAL (operands[3]) / 8, 1);
5646 (define_expand "extzv"
5647 [(set (match_operand:DI 0 "register_operand" "")
5648 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5649 (match_operand:DI 2 "immediate_operand" "")
5650 (match_operand:DI 3 "immediate_operand" "")))]
5654 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5655 if (INTVAL (operands[3]) % 8 != 0
5656 || (INTVAL (operands[2]) != 8
5657 && INTVAL (operands[2]) != 16
5658 && INTVAL (operands[2]) != 32
5659 && INTVAL (operands[2]) != 64))
5662 if (GET_CODE (operands[1]) == MEM)
5664 /* Fail 8 bit fields, falling back on a simple byte load. */
5665 if (INTVAL (operands[2]) == 8)
5668 alpha_expand_unaligned_load (operands[0], operands[1],
5669 INTVAL (operands[2]) / 8,
5670 INTVAL (operands[3]) / 8, 0);
5675 (define_expand "insv"
5676 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5677 (match_operand:DI 1 "immediate_operand" "")
5678 (match_operand:DI 2 "immediate_operand" ""))
5679 (match_operand:DI 3 "register_operand" ""))]
5683 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5684 if (INTVAL (operands[2]) % 8 != 0
5685 || (INTVAL (operands[1]) != 16
5686 && INTVAL (operands[1]) != 32
5687 && INTVAL (operands[1]) != 64))
5690 /* From mips.md: store_bit_field doesn't verify that our source
5691 matches the predicate, so we force it to be a MEM here. */
5692 if (GET_CODE (operands[0]) != MEM)
5695 alpha_expand_unaligned_store (operands[0], operands[3],
5696 INTVAL (operands[1]) / 8,
5697 INTVAL (operands[2]) / 8);
5701 ;; Block move/clear, see alpha.c for more details.
5702 ;; Argument 0 is the destination
5703 ;; Argument 1 is the source
5704 ;; Argument 2 is the length
5705 ;; Argument 3 is the alignment
5707 (define_expand "movstrqi"
5708 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5709 (match_operand:BLK 1 "memory_operand" ""))
5710 (use (match_operand:DI 2 "immediate_operand" ""))
5711 (use (match_operand:DI 3 "immediate_operand" ""))])]
5715 if (alpha_expand_block_move (operands))
5721 (define_expand "clrstrqi"
5722 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5724 (use (match_operand:DI 1 "immediate_operand" ""))
5725 (use (match_operand:DI 2 "immediate_operand" ""))])]
5729 if (alpha_expand_block_clear (operands))
5735 ;; Subroutine of stack space allocation. Perform a stack probe.
5736 (define_expand "probe_stack"
5737 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5741 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5742 INTVAL (operands[0])));
5743 MEM_VOLATILE_P (operands[1]) = 1;
5745 operands[0] = const0_rtx;
5748 ;; This is how we allocate stack space. If we are allocating a
5749 ;; constant amount of space and we know it is less than 4096
5750 ;; bytes, we need do nothing.
5752 ;; If it is more than 4096 bytes, we need to probe the stack
5754 (define_expand "allocate_stack"
5756 (plus:DI (reg:DI 30)
5757 (match_operand:DI 1 "reg_or_cint_operand" "")))
5758 (set (match_operand:DI 0 "register_operand" "=r")
5763 if (GET_CODE (operands[1]) == CONST_INT
5764 && INTVAL (operands[1]) < 32768)
5766 if (INTVAL (operands[1]) >= 4096)
5768 /* We do this the same way as in the prologue and generate explicit
5769 probes. Then we update the stack by the constant. */
5773 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5774 while (probed + 8192 < INTVAL (operands[1]))
5775 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5777 if (probed + 4096 < INTVAL (operands[1]))
5778 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5781 operands[1] = GEN_INT (- INTVAL (operands[1]));
5782 operands[2] = virtual_stack_dynamic_rtx;
5787 rtx loop_label = gen_label_rtx ();
5788 rtx want = gen_reg_rtx (Pmode);
5789 rtx tmp = gen_reg_rtx (Pmode);
5792 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5793 force_reg (Pmode, operands[1])));
5794 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5796 if (GET_CODE (operands[1]) != CONST_INT)
5798 out_label = gen_label_rtx ();
5799 emit_insn (gen_cmpdi (want, tmp));
5800 emit_jump_insn (gen_bgeu (out_label));
5803 emit_label (loop_label);
5804 memref = gen_rtx_MEM (DImode, tmp);
5805 MEM_VOLATILE_P (memref) = 1;
5806 emit_move_insn (memref, const0_rtx);
5807 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5808 emit_insn (gen_cmpdi (tmp, want));
5809 emit_jump_insn (gen_bgtu (loop_label));
5811 memref = gen_rtx_MEM (DImode, want);
5812 MEM_VOLATILE_P (memref) = 1;
5813 emit_move_insn (memref, const0_rtx);
5816 emit_label (out_label);
5818 emit_move_insn (stack_pointer_rtx, want);
5819 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5824 ;; This is used by alpha_expand_prolog to do the same thing as above,
5825 ;; except we cannot at that time generate new basic blocks, so we hide
5826 ;; the loop in this one insn.
5828 (define_insn "prologue_stack_probe_loop"
5829 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5830 (match_operand:DI 1 "register_operand" "r")]
5835 operands[2] = gen_label_rtx ();
5836 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5837 CODE_LABEL_NUMBER (operands[2]));
5839 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5841 [(set_attr "length" "16")
5842 (set_attr "type" "multi")])
5844 (define_expand "prologue"
5845 [(clobber (const_int 0))]
5849 alpha_expand_prologue ();
5853 ;; These take care of emitting the ldgp insn in the prologue. This will be
5854 ;; an lda/ldah pair and we want to align them properly. So we have two
5855 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
5856 ;; and the second of which emits nothing. However, both are marked as type
5857 ;; IADD (the default) so the alignment code in alpha.c does the right thing
5860 (define_expand "prologue_ldgp"
5861 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP1)
5862 (unspec_volatile [(const_int 0)] UNSPECV_LDGP2)]
5866 (define_insn "*prologue_ldgp_1"
5867 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP1)]
5869 "ldgp $29,0($27)\\n$%~..ng:")
5871 (define_insn "*prologue_ldgp_2"
5872 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP2)]
5876 ;; The _mcount profiling hook has special calling conventions, and
5877 ;; does not clobber all the registers that a normal call would. So
5878 ;; hide the fact this is a call at all.
5880 (define_insn "prologue_mcount"
5881 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
5883 "lda $28,_mcount\;jsr $28,($28),_mcount"
5884 [(set_attr "type" "multi")
5885 (set_attr "length" "8")])
5887 (define_insn "init_fp"
5888 [(set (match_operand:DI 0 "register_operand" "=r")
5889 (match_operand:DI 1 "register_operand" "r"))
5890 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5894 (define_expand "epilogue"
5899 alpha_expand_epilogue ();
5902 (define_expand "sibcall_epilogue"
5904 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
5907 alpha_expand_epilogue ();
5911 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5912 ;; the frame size into a register. We use this pattern to ensure
5913 ;; we get lda instead of addq.
5914 (define_insn "nt_lda"
5915 [(set (match_operand:DI 0 "register_operand" "=r")
5916 (unspec:DI [(match_dup 0)
5917 (match_operand:DI 1 "const_int_operand" "n")]
5922 (define_expand "builtin_longjmp"
5923 [(use (match_operand:DI 0 "register_operand" "r"))]
5924 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5927 /* The elements of the buffer are, in order: */
5928 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5929 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5930 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5931 rtx pv = gen_rtx_REG (Pmode, 27);
5933 /* This bit is the same as expand_builtin_longjmp. */
5934 emit_move_insn (hard_frame_pointer_rtx, fp);
5935 emit_move_insn (pv, lab);
5936 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5937 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5938 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5940 /* Load the label we are jumping through into $27 so that we know
5941 where to look for it when we get back to setjmp's function for
5942 restoring the gp. */
5943 emit_jump_insn (gen_builtin_longjmp_internal (pv));
5948 ;; This is effectively a copy of indirect_jump, but constrained such
5949 ;; that register renaming cannot foil our cunning plan with $27.
5950 (define_insn "builtin_longjmp_internal"
5952 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
5956 [(set_attr "type" "ibr")])
5958 (define_insn "*builtin_setjmp_receiver_sub_label"
5959 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
5960 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5961 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5962 [(set_attr "length" "8")
5963 (set_attr "type" "multi")])
5965 (define_insn "builtin_setjmp_receiver"
5966 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
5967 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5968 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5969 [(set_attr "length" "12")
5970 (set_attr "type" "multi")])
5972 (define_expand "exception_receiver"
5973 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
5974 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5977 if (TARGET_LD_BUGGY_LDGP)
5978 operands[0] = alpha_gp_save_rtx ();
5980 operands[0] = const0_rtx;
5983 (define_insn "*exception_receiver_1"
5984 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
5985 "! TARGET_LD_BUGGY_LDGP"
5987 [(set_attr "length" "8")
5988 (set_attr "type" "multi")])
5990 ;; ??? We don't represent the usage of $29 properly in address loads
5991 ;; and function calls. This leads to the following move being deleted
5992 ;; as dead code unless it is represented as a volatile unspec.
5994 (define_insn "*exception_receiver_2"
5995 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
5997 "TARGET_LD_BUGGY_LDGP"
6001 [(set_attr "type" "ilog,ild")])
6003 (define_expand "nonlocal_goto_receiver"
6004 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6005 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6006 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6011 (define_insn "arg_home"
6012 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6027 (clobber (mem:BLK (const_int 0)))
6028 (clobber (reg:DI 24))
6029 (clobber (reg:DI 25))
6030 (clobber (reg:DI 0))]
6032 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6033 [(set_attr "length" "16")
6034 (set_attr "type" "multi")])
6036 ;; Close the trap shadow of preceeding instructions. This is generated
6039 (define_insn "trapb"
6040 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6043 [(set_attr "type" "misc")])
6045 ;; No-op instructions used by machine-dependant reorg to preserve
6046 ;; alignment for instruction issue.
6052 [(set_attr "type" "ilog")])
6058 [(set_attr "type" "fcpys")])
6065 (define_insn "realign"
6066 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6069 ".align %0 #realign")
6071 ;; The call patterns are at the end of the file because their
6072 ;; wildcard operand0 interferes with nice recognition.
6074 (define_insn "*call_value_osf_1"
6075 [(set (match_operand 0 "" "")
6076 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,i"))
6077 (match_operand 2 "" "")))
6078 (clobber (reg:DI 27))
6079 (clobber (reg:DI 26))]
6080 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
6082 jsr $26,($27),0\;ldgp $29,0($26)
6084 jsr $26,%1\;ldgp $29,0($26)"
6085 [(set_attr "type" "jsr")
6086 (set_attr "length" "12,*,16")])
6088 (define_insn "*sibcall_value_osf_1"
6089 [(set (match_operand 0 "" "")
6090 (call (mem:DI (match_operand:DI 1 "call_operand" "R,i"))
6091 (match_operand 2 "" "")))]
6092 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
6096 [(set_attr "type" "jsr")
6097 (set_attr "length" "*,8")])
6099 (define_insn "*call_value_nt_1"
6100 [(set (match_operand 0 "" "")
6101 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
6102 (match_operand 2 "" "")))
6103 (clobber (reg:DI 26))]
6109 [(set_attr "type" "jsr")
6110 (set_attr "length" "*,*,12")])
6112 (define_insn "*call_value_vms_1"
6113 [(set (match_operand 0 "" "")
6114 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
6115 (match_operand 2 "" "")))
6116 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6119 (clobber (reg:DI 27))]
6122 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6123 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6124 [(set_attr "type" "jsr")
6125 (set_attr "length" "12,16")])