1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
48 ;; Processor type -- this attribute must exactly match the processor_type
49 ;; enumeration in alpha.h.
51 (define_attr "cpu" "ev4,ev5,ev6"
52 (const (symbol_ref "alpha_cpu")))
54 ;; Define an insn type attribute. This is used in function unit delay
55 ;; computations, among other purposes. For the most part, we use the names
56 ;; defined in the EV4 documentation, but add a few that we have to know about
60 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
61 (const_string "iadd"))
63 ;; Describe a user's asm statement.
64 (define_asm_attributes
65 [(set_attr "type" "multi")])
67 ;; Define the operand size an insn operates on. Used primarily by mul
68 ;; and div operations that have size dependant timings.
70 (define_attr "opsize" "si,di,udi" (const_string "di"))
72 ;; The TRAP_TYPE attribute marks instructions that may generate traps
73 ;; (which are imprecise and may need a trapb if software completion
76 (define_attr "trap" "no,yes" (const_string "no"))
78 ;; The length of an instruction sequence in bytes.
80 (define_attr "length" "" (const_int 4))
82 ;; On EV4 there are two classes of resources to consider: resources needed
83 ;; to issue, and resources needed to execute. IBUS[01] are in the first
84 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
85 ;; (There are a few other register-like resources, but ...)
87 ; First, describe all of the issue constraints with single cycle delays.
88 ; All insns need a bus, but all except loads require one or the other.
89 (define_function_unit "ev4_ibus0" 1 0
90 (and (eq_attr "cpu" "ev4")
91 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
94 (define_function_unit "ev4_ibus1" 1 0
95 (and (eq_attr "cpu" "ev4")
96 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
99 ; Memory delivers its result in three cycles. Actually return one and
100 ; take care of this in adjust_cost, since we want to handle user-defined
102 (define_function_unit "ev4_abox" 1 0
103 (and (eq_attr "cpu" "ev4")
104 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
107 ; Branches have no delay cost, but do tie up the unit for two cycles.
108 (define_function_unit "ev4_bbox" 1 1
109 (and (eq_attr "cpu" "ev4")
110 (eq_attr "type" "ibr,fbr,jsr"))
113 ; Arithmetic insns are normally have their results available after
114 ; two cycles. There are a number of exceptions. They are encoded in
115 ; ADJUST_COST. Some of the other insns have similar exceptions.
116 (define_function_unit "ev4_ebox" 1 0
117 (and (eq_attr "cpu" "ev4")
118 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
121 (define_function_unit "imul" 1 0
122 (and (eq_attr "cpu" "ev4")
123 (and (eq_attr "type" "imul")
124 (eq_attr "opsize" "si")))
127 (define_function_unit "imul" 1 0
128 (and (eq_attr "cpu" "ev4")
129 (and (eq_attr "type" "imul")
130 (eq_attr "opsize" "!si")))
133 (define_function_unit "ev4_fbox" 1 0
134 (and (eq_attr "cpu" "ev4")
135 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
138 (define_function_unit "fdiv" 1 0
139 (and (eq_attr "cpu" "ev4")
140 (and (eq_attr "type" "fdiv")
141 (eq_attr "opsize" "si")))
144 (define_function_unit "fdiv" 1 0
145 (and (eq_attr "cpu" "ev4")
146 (and (eq_attr "type" "fdiv")
147 (eq_attr "opsize" "di")))
150 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
152 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
153 ;; with the combined resource EBOX.
155 (define_function_unit "ev5_ebox" 2 0
156 (and (eq_attr "cpu" "ev5")
157 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
160 ; Memory takes at least 2 clocks. Return one from here and fix up with
161 ; user-defined latencies in adjust_cost.
162 (define_function_unit "ev5_ebox" 2 0
163 (and (eq_attr "cpu" "ev5")
164 (eq_attr "type" "ild,fld,ldsym"))
167 ; Loads can dual issue with one another, but loads and stores do not mix.
168 (define_function_unit "ev5_e0" 1 0
169 (and (eq_attr "cpu" "ev5")
170 (eq_attr "type" "ild,fld,ldsym"))
172 [(eq_attr "type" "ist,fst")])
174 ; Stores, shifts, multiplies can only issue to E0
175 (define_function_unit "ev5_e0" 1 0
176 (and (eq_attr "cpu" "ev5")
177 (eq_attr "type" "ist,fst,shift,imul"))
180 ; Motion video insns also issue only to E0, and take two ticks.
181 (define_function_unit "ev5_e0" 1 0
182 (and (eq_attr "cpu" "ev5")
183 (eq_attr "type" "mvi"))
186 ; Conditional moves always take 2 ticks.
187 (define_function_unit "ev5_ebox" 2 0
188 (and (eq_attr "cpu" "ev5")
189 (eq_attr "type" "icmov"))
192 ; Branches can only issue to E1
193 (define_function_unit "ev5_e1" 1 0
194 (and (eq_attr "cpu" "ev5")
195 (eq_attr "type" "ibr,jsr"))
198 ; Multiplies also use the integer multiplier.
199 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
200 ; cycles before an integer multiplication completes."
201 (define_function_unit "imul" 1 0
202 (and (eq_attr "cpu" "ev5")
203 (and (eq_attr "type" "imul")
204 (eq_attr "opsize" "si")))
207 (define_function_unit "imul" 1 0
208 (and (eq_attr "cpu" "ev5")
209 (and (eq_attr "type" "imul")
210 (eq_attr "opsize" "di")))
213 (define_function_unit "imul" 1 0
214 (and (eq_attr "cpu" "ev5")
215 (and (eq_attr "type" "imul")
216 (eq_attr "opsize" "udi")))
219 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
220 ;; on either so we have to play the game again.
222 (define_function_unit "ev5_fbox" 2 0
223 (and (eq_attr "cpu" "ev5")
224 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
227 (define_function_unit "ev5_fm" 1 0
228 (and (eq_attr "cpu" "ev5")
229 (eq_attr "type" "fmul"))
232 ; Add and cmov as you would expect; fbr never produces a result;
233 ; fdiv issues through fa to the divider,
234 (define_function_unit "ev5_fa" 1 0
235 (and (eq_attr "cpu" "ev5")
236 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
239 ; ??? How to: "No instruction can be issued to pipe FA exactly five
240 ; cycles before a floating point divide completes."
241 (define_function_unit "fdiv" 1 0
242 (and (eq_attr "cpu" "ev5")
243 (and (eq_attr "type" "fdiv")
244 (eq_attr "opsize" "si")))
245 15 15) ; 15 to 31 data dependant
247 (define_function_unit "fdiv" 1 0
248 (and (eq_attr "cpu" "ev5")
249 (and (eq_attr "type" "fdiv")
250 (eq_attr "opsize" "di")))
251 22 22) ; 22 to 60 data dependant
253 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
255 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
256 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
258 ;; Conditional moves decompose into two independant primitives, each
259 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
261 (define_function_unit "ev6_ebox" 4 0
262 (and (eq_attr "cpu" "ev6")
263 (eq_attr "type" "icmov"))
266 (define_function_unit "ev6_ebox" 4 0
267 (and (eq_attr "cpu" "ev6")
268 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
271 ;; Integer loads take at least 3 clocks, and only issue to lower units.
272 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
273 (define_function_unit "ev6_l" 2 0
274 (and (eq_attr "cpu" "ev6")
275 (eq_attr "type" "ild,ldsym,ist,fst"))
278 ;; FP loads take at least 4 clocks. Return two from here...
279 (define_function_unit "ev6_l" 2 0
280 (and (eq_attr "cpu" "ev6")
281 (eq_attr "type" "fld"))
284 ;; Motion video insns also issue only to U0, and take three ticks.
285 (define_function_unit "ev6_u0" 1 0
286 (and (eq_attr "cpu" "ev6")
287 (eq_attr "type" "mvi"))
290 (define_function_unit "ev6_u" 2 0
291 (and (eq_attr "cpu" "ev6")
292 (eq_attr "type" "mvi"))
295 ;; Shifts issue to either upper pipe.
296 (define_function_unit "ev6_u" 2 0
297 (and (eq_attr "cpu" "ev6")
298 (eq_attr "type" "shift"))
301 ;; Multiplies issue only to U1, and all take 7 ticks.
302 ;; Rather than create a new function unit just for U1, reuse IMUL
303 (define_function_unit "imul" 1 0
304 (and (eq_attr "cpu" "ev6")
305 (eq_attr "type" "imul"))
308 (define_function_unit "ev6_u" 2 0
309 (and (eq_attr "cpu" "ev6")
310 (eq_attr "type" "imul"))
313 ;; Branches issue to either upper pipe
314 (define_function_unit "ev6_u" 2 0
315 (and (eq_attr "cpu" "ev6")
316 (eq_attr "type" "ibr"))
319 ;; Calls only issue to L0.
320 (define_function_unit "ev6_l0" 1 0
321 (and (eq_attr "cpu" "ev6")
322 (eq_attr "type" "jsr"))
325 (define_function_unit "ev6_l" 2 0
326 (and (eq_attr "cpu" "ev6")
327 (eq_attr "type" "jsr"))
330 ;; Ftoi/itof only issue to lower pipes
331 (define_function_unit "ev6_l" 2 0
332 (and (eq_attr "cpu" "ev6")
333 (eq_attr "type" "ftoi"))
336 (define_function_unit "ev6_l" 2 0
337 (and (eq_attr "cpu" "ev6")
338 (eq_attr "type" "itof"))
341 ;; For the FPU we are very similar to EV5, except there's no insn that
342 ;; can issue to fm & fa, so we get to leave that out.
344 (define_function_unit "ev6_fm" 1 0
345 (and (eq_attr "cpu" "ev6")
346 (eq_attr "type" "fmul"))
349 (define_function_unit "ev6_fa" 1 0
350 (and (eq_attr "cpu" "ev6")
351 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
354 (define_function_unit "ev6_fa" 1 0
355 (and (eq_attr "cpu" "ev6")
356 (eq_attr "type" "fcmov"))
359 (define_function_unit "fdiv" 1 0
360 (and (eq_attr "cpu" "ev6")
361 (and (eq_attr "type" "fdiv")
362 (eq_attr "opsize" "si")))
365 (define_function_unit "fdiv" 1 0
366 (and (eq_attr "cpu" "ev6")
367 (and (eq_attr "type" "fdiv")
368 (eq_attr "opsize" "di")))
371 (define_function_unit "fsqrt" 1 0
372 (and (eq_attr "cpu" "ev6")
373 (and (eq_attr "type" "fsqrt")
374 (eq_attr "opsize" "si")))
377 (define_function_unit "fsqrt" 1 0
378 (and (eq_attr "cpu" "ev6")
379 (and (eq_attr "type" "fsqrt")
380 (eq_attr "opsize" "di")))
383 ; ??? The FPU communicates with memory and the integer register file
384 ; via two fp store units. We need a slot in the fst immediately, and
385 ; a slot in LOW after the operand data is ready. At which point the
386 ; data may be moved either to the store queue or the integer register
387 ; file and the insn retired.
390 ;; First define the arithmetic insns. Note that the 32-bit forms also
393 ;; Handle 32-64 bit extension from memory to a floating point register
394 ;; specially, since this ocurrs frequently in int->double conversions.
396 ;; Note that while we must retain the =f case in the insn for reload's
397 ;; benefit, it should be eliminated after reload, so we should never emit
398 ;; code for that case. But we don't reject the possibility.
400 (define_expand "extendsidi2"
401 [(set (match_operand:DI 0 "register_operand" "")
402 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
407 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
409 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
415 lds %0,%1\;cvtlq %0,%0"
416 [(set_attr "type" "iadd,ild,fadd,fld")
417 (set_attr "length" "*,*,*,8")])
420 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
422 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
429 lds %0,%1\;cvtlq %0,%0"
430 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
431 (set_attr "length" "*,*,*,*,8")])
433 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
435 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
436 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
438 [(set (match_dup 2) (match_dup 1))
439 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
440 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
442 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
443 ;; generates better code. We have the anonymous addsi3 pattern below in
444 ;; case combine wants to make it.
445 (define_expand "addsi3"
446 [(set (match_operand:SI 0 "register_operand" "")
447 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
448 (match_operand:SI 2 "add_operand" "")))]
454 rtx op1 = gen_lowpart (DImode, operands[1]);
455 rtx op2 = gen_lowpart (DImode, operands[2]);
457 if (! cse_not_expected)
459 rtx tmp = gen_reg_rtx (DImode);
460 emit_insn (gen_adddi3 (tmp, op1, op2));
461 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
464 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
470 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
471 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
472 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
481 [(set (match_operand:SI 0 "register_operand" "")
482 (plus:SI (match_operand:SI 1 "register_operand" "")
483 (match_operand:SI 2 "const_int_operand" "")))]
484 "! add_operand (operands[2], SImode)"
485 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
486 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
489 HOST_WIDE_INT val = INTVAL (operands[2]);
490 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
491 HOST_WIDE_INT rest = val - low;
493 operands[3] = GEN_INT (rest);
494 operands[4] = GEN_INT (low);
498 [(set (match_operand:DI 0 "register_operand" "=r,r")
500 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
501 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
508 [(set (match_operand:DI 0 "register_operand" "")
510 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
511 (match_operand:SI 2 "const_int_operand" ""))))
512 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
513 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
514 && INTVAL (operands[2]) % 4 == 0"
515 [(set (match_dup 3) (match_dup 4))
516 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
521 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
527 operands[4] = GEN_INT (val);
528 operands[5] = GEN_INT (mult);
532 [(set (match_operand:DI 0 "register_operand" "")
534 (plus:SI (match_operator:SI 1 "comparison_operator"
535 [(match_operand 2 "" "")
536 (match_operand 3 "" "")])
537 (match_operand:SI 4 "add_operand" ""))))
538 (clobber (match_operand:DI 5 "register_operand" ""))]
540 [(set (match_dup 5) (match_dup 6))
541 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
544 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
545 operands[2], operands[3]);
546 operands[7] = gen_lowpart (SImode, operands[5]);
549 (define_expand "adddi3"
550 [(set (match_operand:DI 0 "register_operand" "")
551 (plus:DI (match_operand:DI 1 "register_operand" "")
552 (match_operand:DI 2 "add_operand" "")))]
556 ;; This pattern exists so that register elimination tries to canonize
557 ;; (plus (plus reg c1) c2).
560 [(set (match_operand:DI 0 "register_operand" "=r")
561 (match_operand:DI 1 "addition_operation" "p"))]
565 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
566 ;; With complications like
568 ;; The NT stack unwind code can't handle a subq to adjust the stack
569 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
570 ;; the exception handling code will loop if a subq is used and an
573 ;; The 19980616 change to emit prologues as RTL also confused some
574 ;; versions of GDB, which also interprets prologues. This has been
575 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
578 ;; and the fact that the three insns schedule exactly the same, it's
579 ;; just not worth the effort.
581 (define_insn "*adddi_2"
582 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
583 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
584 (match_operand:DI 2 "add_operand" "r,K,L")))]
591 ;; ??? Allow large constants when basing off the frame pointer or some
592 ;; virtual register that may eliminate to the frame pointer. This is
593 ;; done because register elimination offsets will change the hi/lo split,
594 ;; and if we split before reload, we will require additional instructions.
597 [(set (match_operand:DI 0 "register_operand" "=r")
598 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
599 (match_operand:DI 2 "const_int_operand" "n")))]
600 "REG_OK_FP_BASE_P (operands[1])
601 && INTVAL (operands[2]) >= 0
602 /* This is the largest constant an lda+ldah pair can add, minus
603 an upper bound on the displacement between SP and AP during
604 register elimination. See INITIAL_ELIMINATION_OFFSET. */
605 && INTVAL (operands[2])
607 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
608 - ALPHA_ROUND(current_function_outgoing_args_size)
609 - (ALPHA_ROUND (get_frame_size ()
610 + max_reg_num () * UNITS_PER_WORD
611 + current_function_pretend_args_size)
612 - current_function_pretend_args_size))"
615 ;; Don't do this if we are adjusting SP since we don't want to do it
616 ;; in two steps. Don't split FP sources for the reason listed above.
618 [(set (match_operand:DI 0 "register_operand" "")
619 (plus:DI (match_operand:DI 1 "register_operand" "")
620 (match_operand:DI 2 "const_int_operand" "")))]
621 "! add_operand (operands[2], DImode)
622 && operands[0] != stack_pointer_rtx
623 && operands[1] != frame_pointer_rtx
624 && operands[1] != arg_pointer_rtx"
625 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
626 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
629 HOST_WIDE_INT val = INTVAL (operands[2]);
630 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
631 HOST_WIDE_INT rest = val - low;
633 operands[4] = GEN_INT (low);
634 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
635 operands[3] = GEN_INT (rest);
636 else if (! no_new_pseudos)
638 operands[3] = gen_reg_rtx (DImode);
639 emit_move_insn (operands[3], operands[2]);
640 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
648 [(set (match_operand:SI 0 "register_operand" "=r,r")
649 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
650 (match_operand:SI 2 "const48_operand" "I,I"))
651 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
658 [(set (match_operand:DI 0 "register_operand" "=r,r")
660 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
661 (match_operand:SI 2 "const48_operand" "I,I"))
662 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
669 [(set (match_operand:DI 0 "register_operand" "")
671 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
672 [(match_operand 2 "" "")
673 (match_operand 3 "" "")])
674 (match_operand:SI 4 "const48_operand" ""))
675 (match_operand:SI 5 "sext_add_operand" ""))))
676 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
678 [(set (match_dup 6) (match_dup 7))
680 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
684 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
685 operands[2], operands[3]);
686 operands[8] = gen_lowpart (SImode, operands[6]);
690 [(set (match_operand:DI 0 "register_operand" "=r,r")
691 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
692 (match_operand:DI 2 "const48_operand" "I,I"))
693 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
699 (define_insn "negsi2"
700 [(set (match_operand:SI 0 "register_operand" "=r")
701 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
706 [(set (match_operand:DI 0 "register_operand" "=r")
707 (sign_extend:DI (neg:SI
708 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
712 (define_insn "negdi2"
713 [(set (match_operand:DI 0 "register_operand" "=r")
714 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
718 (define_expand "subsi3"
719 [(set (match_operand:SI 0 "register_operand" "")
720 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
721 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
727 rtx op1 = gen_lowpart (DImode, operands[1]);
728 rtx op2 = gen_lowpart (DImode, operands[2]);
730 if (! cse_not_expected)
732 rtx tmp = gen_reg_rtx (DImode);
733 emit_insn (gen_subdi3 (tmp, op1, op2));
734 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
737 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
743 [(set (match_operand:SI 0 "register_operand" "=r")
744 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
745 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
750 [(set (match_operand:DI 0 "register_operand" "=r")
751 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
752 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
756 (define_insn "subdi3"
757 [(set (match_operand:DI 0 "register_operand" "=r")
758 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
759 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
764 [(set (match_operand:SI 0 "register_operand" "=r")
765 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
766 (match_operand:SI 2 "const48_operand" "I"))
767 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
772 [(set (match_operand:DI 0 "register_operand" "=r")
774 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
775 (match_operand:SI 2 "const48_operand" "I"))
776 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
781 [(set (match_operand:DI 0 "register_operand" "=r")
782 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
783 (match_operand:DI 2 "const48_operand" "I"))
784 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
788 (define_insn "mulsi3"
789 [(set (match_operand:SI 0 "register_operand" "=r")
790 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
791 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
794 [(set_attr "type" "imul")
795 (set_attr "opsize" "si")])
798 [(set (match_operand:DI 0 "register_operand" "=r")
800 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
801 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
804 [(set_attr "type" "imul")
805 (set_attr "opsize" "si")])
807 (define_insn "muldi3"
808 [(set (match_operand:DI 0 "register_operand" "=r")
809 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
810 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
813 [(set_attr "type" "imul")])
815 (define_insn "umuldi3_highpart"
816 [(set (match_operand:DI 0 "register_operand" "=r")
819 (mult:TI (zero_extend:TI
820 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
822 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
826 [(set_attr "type" "imul")
827 (set_attr "opsize" "udi")])
830 [(set (match_operand:DI 0 "register_operand" "=r")
833 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
834 (match_operand:TI 2 "cint8_operand" "I"))
838 [(set_attr "type" "imul")
839 (set_attr "opsize" "udi")])
841 ;; The divide and remainder operations always take their inputs from
842 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
844 ;; ??? Force sign-extension here because some versions of OSF/1 don't
845 ;; do the right thing if the inputs are not properly sign-extended.
846 ;; But Linux, for instance, does not have this problem. Is it worth
847 ;; the complication here to eliminate the sign extension?
848 ;; Interix/NT has the same sign-extension problem.
850 (define_expand "divsi3"
852 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
854 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
855 (parallel [(set (reg:DI 27)
856 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
857 (clobber (reg:DI 23))
858 (clobber (reg:DI 28))])
859 (set (match_operand:SI 0 "nonimmediate_operand" "")
860 (subreg:SI (reg:DI 27) 0))]
864 (define_expand "udivsi3"
866 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
868 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
869 (parallel [(set (reg:DI 27)
870 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
871 (clobber (reg:DI 23))
872 (clobber (reg:DI 28))])
873 (set (match_operand:SI 0 "nonimmediate_operand" "")
874 (subreg:SI (reg:DI 27) 0))]
878 (define_expand "modsi3"
880 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
882 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
883 (parallel [(set (reg:DI 27)
884 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
885 (clobber (reg:DI 23))
886 (clobber (reg:DI 28))])
887 (set (match_operand:SI 0 "nonimmediate_operand" "")
888 (subreg:SI (reg:DI 27) 0))]
892 (define_expand "umodsi3"
894 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
896 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
897 (parallel [(set (reg:DI 27)
898 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
899 (clobber (reg:DI 23))
900 (clobber (reg:DI 28))])
901 (set (match_operand:SI 0 "nonimmediate_operand" "")
902 (subreg:SI (reg:DI 27) 0))]
906 (define_expand "divdi3"
907 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
908 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
909 (parallel [(set (reg:DI 27)
912 (clobber (reg:DI 23))
913 (clobber (reg:DI 28))])
914 (set (match_operand:DI 0 "nonimmediate_operand" "")
919 (define_expand "udivdi3"
920 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
921 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
922 (parallel [(set (reg:DI 27)
925 (clobber (reg:DI 23))
926 (clobber (reg:DI 28))])
927 (set (match_operand:DI 0 "nonimmediate_operand" "")
932 (define_expand "moddi3"
933 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
934 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
935 (parallel [(set (reg:DI 27)
938 (clobber (reg:DI 23))
939 (clobber (reg:DI 28))])
940 (set (match_operand:DI 0 "nonimmediate_operand" "")
945 (define_expand "umoddi3"
946 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
947 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
948 (parallel [(set (reg:DI 27)
951 (clobber (reg:DI 23))
952 (clobber (reg:DI 28))])
953 (set (match_operand:DI 0 "nonimmediate_operand" "")
958 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
959 ;; expanded by the assembler.
962 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
963 [(reg:DI 24) (reg:DI 25)])))
964 (clobber (reg:DI 23))
965 (clobber (reg:DI 28))]
968 [(set_attr "type" "jsr")
969 (set_attr "length" "8")])
973 (match_operator:DI 1 "divmod_operator"
974 [(reg:DI 24) (reg:DI 25)]))
975 (clobber (reg:DI 23))
976 (clobber (reg:DI 28))]
979 [(set_attr "type" "jsr")
980 (set_attr "length" "8")])
982 ;; Next are the basic logical operations. These only exist in DImode.
984 (define_insn "anddi3"
985 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
986 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
987 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
993 [(set_attr "type" "ilog,ilog,shift")])
995 ;; There are times when we can split an AND into two AND insns. This occurs
996 ;; when we can first clear any bytes and then clear anything else. For
997 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
998 ;; Only do this when running on 64-bit host since the computations are
999 ;; too messy otherwise.
1002 [(set (match_operand:DI 0 "register_operand" "")
1003 (and:DI (match_operand:DI 1 "register_operand" "")
1004 (match_operand:DI 2 "const_int_operand" "")))]
1005 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1006 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1007 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1010 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1011 unsigned HOST_WIDE_INT mask2 = mask1;
1014 /* For each byte that isn't all zeros, make it all ones. */
1015 for (i = 0; i < 64; i += 8)
1016 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1017 mask1 |= (HOST_WIDE_INT) 0xff << i;
1019 /* Now turn on any bits we've just turned off. */
1022 operands[3] = GEN_INT (mask1);
1023 operands[4] = GEN_INT (mask2);
1026 (define_insn "zero_extendqihi2"
1027 [(set (match_operand:HI 0 "register_operand" "=r")
1028 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1031 [(set_attr "type" "ilog")])
1034 [(set (match_operand:SI 0 "register_operand" "=r,r")
1035 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1040 [(set_attr "type" "ilog,ild")])
1043 [(set (match_operand:SI 0 "register_operand" "=r")
1044 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1047 [(set_attr "type" "ilog")])
1049 (define_expand "zero_extendqisi2"
1050 [(set (match_operand:SI 0 "register_operand" "")
1051 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1056 [(set (match_operand:DI 0 "register_operand" "=r,r")
1057 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1062 [(set_attr "type" "ilog,ild")])
1065 [(set (match_operand:DI 0 "register_operand" "=r")
1066 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1069 [(set_attr "type" "ilog")])
1071 (define_expand "zero_extendqidi2"
1072 [(set (match_operand:DI 0 "register_operand" "")
1073 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1078 [(set (match_operand:SI 0 "register_operand" "=r,r")
1079 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1084 [(set_attr "type" "shift,ild")])
1087 [(set (match_operand:SI 0 "register_operand" "=r")
1088 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1091 [(set_attr "type" "shift")])
1093 (define_expand "zero_extendhisi2"
1094 [(set (match_operand:SI 0 "register_operand" "")
1095 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1100 [(set (match_operand:DI 0 "register_operand" "=r,r")
1101 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1106 [(set_attr "type" "shift,ild")])
1109 [(set (match_operand:DI 0 "register_operand" "=r")
1110 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1113 [(set_attr "type" "shift")])
1115 (define_expand "zero_extendhidi2"
1116 [(set (match_operand:DI 0 "register_operand" "")
1117 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1121 (define_insn "zero_extendsidi2"
1122 [(set (match_operand:DI 0 "register_operand" "=r")
1123 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1126 [(set_attr "type" "shift")])
1129 [(set (match_operand:DI 0 "register_operand" "=r")
1130 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1131 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1134 [(set_attr "type" "ilog")])
1136 (define_insn "iordi3"
1137 [(set (match_operand:DI 0 "register_operand" "=r,r")
1138 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1139 (match_operand:DI 2 "or_operand" "rI,N")))]
1144 [(set_attr "type" "ilog")])
1146 (define_insn "one_cmpldi2"
1147 [(set (match_operand:DI 0 "register_operand" "=r")
1148 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1151 [(set_attr "type" "ilog")])
1154 [(set (match_operand:DI 0 "register_operand" "=r")
1155 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1156 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1159 [(set_attr "type" "ilog")])
1161 (define_insn "xordi3"
1162 [(set (match_operand:DI 0 "register_operand" "=r,r")
1163 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1164 (match_operand:DI 2 "or_operand" "rI,N")))]
1169 [(set_attr "type" "ilog")])
1172 [(set (match_operand:DI 0 "register_operand" "=r")
1173 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1174 (match_operand:DI 2 "register_operand" "rI"))))]
1177 [(set_attr "type" "ilog")])
1179 ;; Handle the FFS insn iff we support CIX.
1181 (define_expand "ffsdi2"
1183 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1185 (plus:DI (match_dup 2) (const_int 1)))
1186 (set (match_operand:DI 0 "register_operand" "")
1187 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1188 (const_int 0) (match_dup 3)))]
1192 operands[2] = gen_reg_rtx (DImode);
1193 operands[3] = gen_reg_rtx (DImode);
1197 [(set (match_operand:DI 0 "register_operand" "=r")
1198 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1201 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1202 ; reuse the existing type name.
1203 [(set_attr "type" "mvi")])
1205 ;; Next come the shifts and the various extract and insert operations.
1207 (define_insn "ashldi3"
1208 [(set (match_operand:DI 0 "register_operand" "=r,r")
1209 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1210 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1214 switch (which_alternative)
1217 if (operands[2] == const1_rtx)
1218 return \"addq %r1,%r1,%0\";
1220 return \"s%P2addq %r1,0,%0\";
1222 return \"sll %r1,%2,%0\";
1227 [(set_attr "type" "iadd,shift")])
1229 ;; ??? The following pattern is made by combine, but earlier phases
1230 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1231 ;; with this in a better way at some point.
1233 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1235 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1236 ;; (match_operand:DI 2 "const_int_operand" "P"))
1238 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1241 ;; if (operands[2] == const1_rtx)
1242 ;; return \"addl %r1,%r1,%0\";
1244 ;; return \"s%P2addl %r1,0,%0\";
1246 ;; [(set_attr "type" "iadd")])
1248 (define_insn "lshrdi3"
1249 [(set (match_operand:DI 0 "register_operand" "=r")
1250 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1251 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1254 [(set_attr "type" "shift")])
1256 (define_insn "ashrdi3"
1257 [(set (match_operand:DI 0 "register_operand" "=r")
1258 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1259 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1262 [(set_attr "type" "shift")])
1264 (define_expand "extendqihi2"
1266 (ashift:DI (match_operand:QI 1 "some_operand" "")
1268 (set (match_operand:HI 0 "register_operand" "")
1269 (ashiftrt:DI (match_dup 2)
1276 emit_insn (gen_extendqihi2x (operands[0],
1277 force_reg (QImode, operands[1])));
1281 /* If we have an unaligned MEM, extend to DImode (which we do
1282 specially) and then copy to the result. */
1283 if (unaligned_memory_operand (operands[1], HImode))
1285 rtx temp = gen_reg_rtx (DImode);
1287 emit_insn (gen_extendqidi2 (temp, operands[1]));
1288 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1292 operands[0] = gen_lowpart (DImode, operands[0]);
1293 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1294 operands[2] = gen_reg_rtx (DImode);
1297 (define_insn "extendqidi2x"
1298 [(set (match_operand:DI 0 "register_operand" "=r")
1299 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1302 [(set_attr "type" "shift")])
1304 (define_insn "extendhidi2x"
1305 [(set (match_operand:DI 0 "register_operand" "=r")
1306 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1309 [(set_attr "type" "shift")])
1311 (define_insn "extendqisi2x"
1312 [(set (match_operand:SI 0 "register_operand" "=r")
1313 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1316 [(set_attr "type" "shift")])
1318 (define_insn "extendhisi2x"
1319 [(set (match_operand:SI 0 "register_operand" "=r")
1320 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1323 [(set_attr "type" "shift")])
1325 (define_insn "extendqihi2x"
1326 [(set (match_operand:HI 0 "register_operand" "=r")
1327 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1330 [(set_attr "type" "shift")])
1332 (define_expand "extendqisi2"
1334 (ashift:DI (match_operand:QI 1 "some_operand" "")
1336 (set (match_operand:SI 0 "register_operand" "")
1337 (ashiftrt:DI (match_dup 2)
1344 emit_insn (gen_extendqisi2x (operands[0],
1345 force_reg (QImode, operands[1])));
1349 /* If we have an unaligned MEM, extend to a DImode form of
1350 the result (which we do specially). */
1351 if (unaligned_memory_operand (operands[1], QImode))
1353 rtx temp = gen_reg_rtx (DImode);
1355 emit_insn (gen_extendqidi2 (temp, operands[1]));
1356 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1360 operands[0] = gen_lowpart (DImode, operands[0]);
1361 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1362 operands[2] = gen_reg_rtx (DImode);
1365 (define_expand "extendqidi2"
1367 (ashift:DI (match_operand:QI 1 "some_operand" "")
1369 (set (match_operand:DI 0 "register_operand" "")
1370 (ashiftrt:DI (match_dup 2)
1377 emit_insn (gen_extendqidi2x (operands[0],
1378 force_reg (QImode, operands[1])));
1382 if (unaligned_memory_operand (operands[1], QImode))
1385 = gen_unaligned_extendqidi (operands[0],
1386 get_unaligned_address (operands[1], 1));
1388 alpha_set_memflags (seq, operands[1]);
1393 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1394 operands[2] = gen_reg_rtx (DImode);
1397 (define_expand "extendhisi2"
1399 (ashift:DI (match_operand:HI 1 "some_operand" "")
1401 (set (match_operand:SI 0 "register_operand" "")
1402 (ashiftrt:DI (match_dup 2)
1409 emit_insn (gen_extendhisi2x (operands[0],
1410 force_reg (HImode, operands[1])));
1414 /* If we have an unaligned MEM, extend to a DImode form of
1415 the result (which we do specially). */
1416 if (unaligned_memory_operand (operands[1], HImode))
1418 rtx temp = gen_reg_rtx (DImode);
1420 emit_insn (gen_extendhidi2 (temp, operands[1]));
1421 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1425 operands[0] = gen_lowpart (DImode, operands[0]);
1426 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1427 operands[2] = gen_reg_rtx (DImode);
1430 (define_expand "extendhidi2"
1432 (ashift:DI (match_operand:HI 1 "some_operand" "")
1434 (set (match_operand:DI 0 "register_operand" "")
1435 (ashiftrt:DI (match_dup 2)
1442 emit_insn (gen_extendhidi2x (operands[0],
1443 force_reg (HImode, operands[1])));
1447 if (unaligned_memory_operand (operands[1], HImode))
1450 = gen_unaligned_extendhidi (operands[0],
1451 get_unaligned_address (operands[1], 2));
1453 alpha_set_memflags (seq, operands[1]);
1458 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1459 operands[2] = gen_reg_rtx (DImode);
1462 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1463 ;; as a pattern saves one instruction. The code is similar to that for
1464 ;; the unaligned loads (see below).
1466 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1467 (define_expand "unaligned_extendqidi"
1468 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1470 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1473 (ashift:DI (match_dup 3)
1474 (minus:DI (const_int 64)
1476 (and:DI (match_dup 2) (const_int 7))
1478 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1479 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1482 { operands[2] = gen_reg_rtx (DImode);
1483 operands[3] = gen_reg_rtx (DImode);
1484 operands[4] = gen_reg_rtx (DImode);
1487 (define_expand "unaligned_extendhidi"
1488 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1490 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1493 (ashift:DI (match_dup 3)
1494 (minus:DI (const_int 64)
1496 (and:DI (match_dup 2) (const_int 7))
1498 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1499 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1502 { operands[2] = gen_reg_rtx (DImode);
1503 operands[3] = gen_reg_rtx (DImode);
1504 operands[4] = gen_reg_rtx (DImode);
1508 [(set (match_operand:DI 0 "register_operand" "=r")
1509 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1510 (match_operand:DI 2 "mode_width_operand" "n")
1511 (match_operand:DI 3 "mul8_operand" "I")))]
1513 "ext%M2l %r1,%s3,%0"
1514 [(set_attr "type" "shift")])
1516 (define_insn "extxl"
1517 [(set (match_operand:DI 0 "register_operand" "=r")
1518 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1519 (match_operand:DI 2 "mode_width_operand" "n")
1520 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1524 [(set_attr "type" "shift")])
1526 ;; Combine has some strange notion of preserving existing undefined behaviour
1527 ;; in shifts larger than a word size. So capture these patterns that it
1528 ;; should have turned into zero_extracts.
1531 [(set (match_operand:DI 0 "register_operand" "=r")
1532 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1533 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1535 (match_operand:DI 3 "mode_mask_operand" "n")))]
1538 [(set_attr "type" "shift")])
1541 [(set (match_operand:DI 0 "register_operand" "=r")
1542 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1543 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1547 [(set_attr "type" "shift")])
1549 (define_insn "extqh"
1550 [(set (match_operand:DI 0 "register_operand" "=r")
1552 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1553 (minus:DI (const_int 64)
1556 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1561 [(set_attr "type" "shift")])
1563 (define_insn "extlh"
1564 [(set (match_operand:DI 0 "register_operand" "=r")
1566 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1567 (const_int 2147483647))
1568 (minus:DI (const_int 64)
1571 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1576 [(set_attr "type" "shift")])
1578 (define_insn "extwh"
1579 [(set (match_operand:DI 0 "register_operand" "=r")
1581 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1583 (minus:DI (const_int 64)
1586 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1591 [(set_attr "type" "shift")])
1593 ;; This converts an extXl into an extXh with an appropriate adjustment
1594 ;; to the address calculation.
1597 ;; [(set (match_operand:DI 0 "register_operand" "")
1598 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1599 ;; (match_operand:DI 2 "mode_width_operand" "")
1600 ;; (ashift:DI (match_operand:DI 3 "" "")
1602 ;; (match_operand:DI 4 "const_int_operand" "")))
1603 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1604 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1605 ;; [(set (match_dup 5) (match_dup 6))
1606 ;; (set (match_dup 0)
1607 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1608 ;; (ashift:DI (plus:DI (match_dup 5)
1614 ;; operands[6] = plus_constant (operands[3],
1615 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1616 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1620 [(set (match_operand:DI 0 "register_operand" "=r")
1621 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1622 (match_operand:DI 2 "mul8_operand" "I")))]
1625 [(set_attr "type" "shift")])
1628 [(set (match_operand:DI 0 "register_operand" "=r")
1629 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1630 (match_operand:DI 2 "mul8_operand" "I")))]
1633 [(set_attr "type" "shift")])
1636 [(set (match_operand:DI 0 "register_operand" "=r")
1637 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1638 (match_operand:DI 2 "mul8_operand" "I")))]
1641 [(set_attr "type" "shift")])
1643 (define_insn "insbl"
1644 [(set (match_operand:DI 0 "register_operand" "=r")
1645 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1646 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1650 [(set_attr "type" "shift")])
1652 (define_insn "inswl"
1653 [(set (match_operand:DI 0 "register_operand" "=r")
1654 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1655 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1659 [(set_attr "type" "shift")])
1661 (define_insn "insll"
1662 [(set (match_operand:DI 0 "register_operand" "=r")
1663 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1664 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1668 [(set_attr "type" "shift")])
1670 (define_insn "insql"
1671 [(set (match_operand:DI 0 "register_operand" "=r")
1672 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1673 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1677 [(set_attr "type" "shift")])
1679 ;; Combine has this sometimes habit of moving the and outside of the
1680 ;; shift, making life more interesting.
1683 [(set (match_operand:DI 0 "register_operand" "=r")
1684 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1685 (match_operand:DI 2 "mul8_operand" "I"))
1686 (match_operand:DI 3 "immediate_operand" "i")))]
1687 "HOST_BITS_PER_WIDE_INT == 64
1688 && GET_CODE (operands[3]) == CONST_INT
1689 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1690 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1691 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1692 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1693 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1694 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1697 #if HOST_BITS_PER_WIDE_INT == 64
1698 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1699 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1700 return \"insbl %1,%s2,%0\";
1701 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1702 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1703 return \"inswl %1,%s2,%0\";
1704 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1705 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1706 return \"insll %1,%s2,%0\";
1710 [(set_attr "type" "shift")])
1712 ;; We do not include the insXh insns because they are complex to express
1713 ;; and it does not appear that we would ever want to generate them.
1715 ;; Since we need them for block moves, though, cop out and use unspec.
1717 (define_insn "insxh"
1718 [(set (match_operand:DI 0 "register_operand" "=r")
1719 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1720 (match_operand:DI 2 "mode_width_operand" "n")
1721 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1724 [(set_attr "type" "shift")])
1726 (define_insn "mskxl"
1727 [(set (match_operand:DI 0 "register_operand" "=r")
1728 (and:DI (not:DI (ashift:DI
1729 (match_operand:DI 2 "mode_mask_operand" "n")
1731 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1733 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1736 [(set_attr "type" "shift")])
1738 ;; We do not include the mskXh insns because it does not appear we would
1739 ;; ever generate one.
1741 ;; Again, we do for block moves and we use unspec again.
1743 (define_insn "mskxh"
1744 [(set (match_operand:DI 0 "register_operand" "=r")
1745 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1746 (match_operand:DI 2 "mode_width_operand" "n")
1747 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1750 [(set_attr "type" "shift")])
1752 ;; Prefer AND + NE over LSHIFTRT + AND.
1754 (define_insn_and_split "*ze_and_ne"
1755 [(set (match_operand:DI 0 "register_operand" "=r")
1756 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1758 (match_operand 2 "const_int_operand" "I")))]
1759 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1763 (and:DI (match_dup 1) (match_dup 3)))
1765 (ne:DI (match_dup 0) (const_int 0)))]
1766 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
1768 ;; Floating-point operations. All the double-precision insns can extend
1769 ;; from single, so indicate that. The exception are the ones that simply
1770 ;; play with the sign bits; it's not clear what to do there.
1772 (define_insn "abssf2"
1773 [(set (match_operand:SF 0 "register_operand" "=f")
1774 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1777 [(set_attr "type" "fcpys")])
1779 (define_insn "*nabssf2"
1780 [(set (match_operand:SF 0 "register_operand" "=f")
1781 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1784 [(set_attr "type" "fadd")])
1786 (define_insn "absdf2"
1787 [(set (match_operand:DF 0 "register_operand" "=f")
1788 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1791 [(set_attr "type" "fcpys")])
1793 (define_insn "*nabsdf2"
1794 [(set (match_operand:DF 0 "register_operand" "=f")
1795 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
1798 [(set_attr "type" "fadd")])
1800 (define_expand "abstf2"
1801 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1802 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1803 (use (match_dup 2))])]
1804 "TARGET_HAS_XFLOATING_LIBS"
1807 #if HOST_BITS_PER_WIDE_INT >= 64
1808 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1810 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1815 [(set (match_operand:TF 0 "register_operand" "=r")
1816 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1817 (use (match_operand:DI 2 "register_operand" "=r"))]
1818 "TARGET_HAS_XFLOATING_LIBS"
1822 [(set (match_operand:TF 0 "register_operand" "")
1823 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1824 (use (match_operand:DI 4 "register_operand" ""))]
1832 alpha_split_tfmode_pair (operands);
1835 if (rtx_equal_p (operands[0], operands[2]))
1837 else if (rtx_equal_p (operands[1], operands[2]))
1841 emit_move_insn (operands[0], operands[2]);
1843 tmp = gen_rtx_NOT (DImode, operands[4]);
1844 tmp = gen_rtx_AND (DImode, tmp, operands[3]);
1845 emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
1848 emit_move_insn (operands[0], operands[2]);
1852 (define_insn "negsf2"
1853 [(set (match_operand:SF 0 "register_operand" "=f")
1854 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1857 [(set_attr "type" "fadd")])
1859 (define_insn "negdf2"
1860 [(set (match_operand:DF 0 "register_operand" "=f")
1861 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1864 [(set_attr "type" "fadd")])
1866 (define_expand "negtf2"
1867 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1868 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1869 (use (match_dup 2))])]
1870 "TARGET_HAS_XFLOATING_LIBS"
1873 #if HOST_BITS_PER_WIDE_INT >= 64
1874 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1876 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1881 [(set (match_operand:TF 0 "register_operand" "=r")
1882 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1883 (use (match_operand:DI 2 "register_operand" "=r"))]
1884 "TARGET_HAS_XFLOATING_LIBS"
1888 [(set (match_operand:TF 0 "register_operand" "")
1889 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1890 (use (match_operand:DI 4 "register_operand" ""))]
1897 alpha_split_tfmode_pair (operands);
1900 if (rtx_equal_p (operands[0], operands[2]))
1902 else if (rtx_equal_p (operands[1], operands[2]))
1906 emit_move_insn (operands[0], operands[2]);
1908 emit_insn (gen_xordi3 (operands[1], operands[3], operands[4]));
1911 emit_move_insn (operands[0], operands[2]);
1916 [(set (match_operand:SF 0 "register_operand" "=&f")
1917 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1918 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1919 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1920 "add%,%)%& %R1,%R2,%0"
1921 [(set_attr "type" "fadd")
1922 (set_attr "trap" "yes")])
1924 (define_insn "addsf3"
1925 [(set (match_operand:SF 0 "register_operand" "=f")
1926 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1927 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1929 "add%,%)%& %R1,%R2,%0"
1930 [(set_attr "type" "fadd")
1931 (set_attr "trap" "yes")])
1934 [(set (match_operand:DF 0 "register_operand" "=&f")
1935 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1936 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1937 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1938 "add%-%)%& %R1,%R2,%0"
1939 [(set_attr "type" "fadd")
1940 (set_attr "trap" "yes")])
1942 (define_insn "adddf3"
1943 [(set (match_operand:DF 0 "register_operand" "=f")
1944 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1945 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1947 "add%-%)%& %R1,%R2,%0"
1948 [(set_attr "type" "fadd")
1949 (set_attr "trap" "yes")])
1952 [(set (match_operand:DF 0 "register_operand" "=f")
1953 (plus:DF (float_extend:DF
1954 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1955 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1956 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1957 "add%-%)%& %R1,%R2,%0"
1958 [(set_attr "type" "fadd")
1959 (set_attr "trap" "yes")])
1962 [(set (match_operand:DF 0 "register_operand" "=f")
1963 (plus:DF (float_extend:DF
1964 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1966 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1967 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1968 "add%-%)%& %R1,%R2,%0"
1969 [(set_attr "type" "fadd")
1970 (set_attr "trap" "yes")])
1972 (define_expand "addtf3"
1973 [(use (match_operand 0 "register_operand" ""))
1974 (use (match_operand 1 "general_operand" ""))
1975 (use (match_operand 2 "general_operand" ""))]
1976 "TARGET_HAS_XFLOATING_LIBS"
1977 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
1979 ;; Define conversion operators between DFmode and SImode, using the cvtql
1980 ;; instruction. To allow combine et al to do useful things, we keep the
1981 ;; operation as a unit until after reload, at which point we split the
1984 ;; Note that we (attempt to) only consider this optimization when the
1985 ;; ultimate destination is memory. If we will be doing further integer
1986 ;; processing, it is cheaper to do the truncation in the int regs.
1988 (define_insn "*cvtql"
1989 [(set (match_operand:SI 0 "register_operand" "=f")
1990 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1993 [(set_attr "type" "fadd")
1994 (set_attr "trap" "yes")])
1997 [(set (match_operand:SI 0 "memory_operand" "")
1998 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1999 (clobber (match_scratch:DI 2 ""))
2000 (clobber (match_scratch:SI 3 ""))]
2001 "TARGET_FP && reload_completed"
2002 [(set (match_dup 2) (fix:DI (match_dup 1)))
2003 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2004 (set (match_dup 0) (match_dup 3))]
2008 [(set (match_operand:SI 0 "memory_operand" "")
2009 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
2010 (clobber (match_scratch:DI 2 ""))]
2011 "TARGET_FP && reload_completed"
2012 [(set (match_dup 2) (fix:DI (match_dup 1)))
2013 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2014 (set (match_dup 0) (match_dup 3))]
2015 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2016 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2019 [(set (match_operand:SI 0 "memory_operand" "=m")
2020 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2021 (clobber (match_scratch:DI 2 "=&f"))
2022 (clobber (match_scratch:SI 3 "=&f"))]
2023 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2025 [(set_attr "type" "fadd")
2026 (set_attr "trap" "yes")])
2029 [(set (match_operand:SI 0 "memory_operand" "=m")
2030 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2031 (clobber (match_scratch:DI 2 "=f"))]
2032 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2034 [(set_attr "type" "fadd")
2035 (set_attr "trap" "yes")])
2038 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2039 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2040 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2042 [(set_attr "type" "fadd")
2043 (set_attr "trap" "yes")])
2045 (define_insn "fix_truncdfdi2"
2046 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2047 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2050 [(set_attr "type" "fadd")
2051 (set_attr "trap" "yes")])
2053 ;; Likewise between SFmode and SImode.
2056 [(set (match_operand:SI 0 "memory_operand" "")
2057 (subreg:SI (fix:DI (float_extend:DF
2058 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2059 (clobber (match_scratch:DI 2 ""))
2060 (clobber (match_scratch:SI 3 ""))]
2061 "TARGET_FP && reload_completed"
2062 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2063 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2064 (set (match_dup 0) (match_dup 3))]
2068 [(set (match_operand:SI 0 "memory_operand" "")
2069 (subreg:SI (fix:DI (float_extend:DF
2070 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2071 (clobber (match_scratch:DI 2 ""))]
2072 "TARGET_FP && reload_completed"
2073 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2074 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2075 (set (match_dup 0) (match_dup 3))]
2076 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2077 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2080 [(set (match_operand:SI 0 "memory_operand" "=m")
2081 (subreg:SI (fix:DI (float_extend:DF
2082 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2083 (clobber (match_scratch:DI 2 "=&f"))
2084 (clobber (match_scratch:SI 3 "=&f"))]
2085 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2087 [(set_attr "type" "fadd")
2088 (set_attr "trap" "yes")])
2091 [(set (match_operand:SI 0 "memory_operand" "=m")
2092 (subreg:SI (fix:DI (float_extend:DF
2093 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2094 (clobber (match_scratch:DI 2 "=f"))]
2095 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2097 [(set_attr "type" "fadd")
2098 (set_attr "trap" "yes")])
2101 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2102 (fix:DI (float_extend:DF
2103 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2104 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2106 [(set_attr "type" "fadd")
2107 (set_attr "trap" "yes")])
2109 (define_insn "fix_truncsfdi2"
2110 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2111 (fix:DI (float_extend:DF
2112 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2115 [(set_attr "type" "fadd")
2116 (set_attr "trap" "yes")])
2118 (define_expand "fix_trunctfdi2"
2119 [(use (match_operand:DI 0 "register_operand" ""))
2120 (use (match_operand:TF 1 "general_operand" ""))]
2121 "TARGET_HAS_XFLOATING_LIBS"
2122 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2125 [(set (match_operand:SF 0 "register_operand" "=&f")
2126 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2127 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2129 [(set_attr "type" "fadd")
2130 (set_attr "trap" "yes")])
2132 (define_insn "floatdisf2"
2133 [(set (match_operand:SF 0 "register_operand" "=f")
2134 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2137 [(set_attr "type" "fadd")
2138 (set_attr "trap" "yes")])
2141 [(set (match_operand:DF 0 "register_operand" "=&f")
2142 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2143 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2145 [(set_attr "type" "fadd")
2146 (set_attr "trap" "yes")])
2148 (define_insn "floatdidf2"
2149 [(set (match_operand:DF 0 "register_operand" "=f")
2150 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2153 [(set_attr "type" "fadd")
2154 (set_attr "trap" "yes")])
2156 (define_expand "floatditf2"
2157 [(use (match_operand:TF 0 "register_operand" ""))
2158 (use (match_operand:DI 1 "general_operand" ""))]
2159 "TARGET_HAS_XFLOATING_LIBS"
2160 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2162 (define_expand "floatunsdisf2"
2163 [(use (match_operand:SF 0 "register_operand" ""))
2164 (use (match_operand:DI 1 "register_operand" ""))]
2166 "alpha_emit_floatuns (operands); DONE;")
2168 (define_expand "floatunsdidf2"
2169 [(use (match_operand:DF 0 "register_operand" ""))
2170 (use (match_operand:DI 1 "register_operand" ""))]
2172 "alpha_emit_floatuns (operands); DONE;")
2174 (define_expand "floatunsditf2"
2175 [(use (match_operand:TF 0 "register_operand" ""))
2176 (use (match_operand:DI 1 "general_operand" ""))]
2177 "TARGET_HAS_XFLOATING_LIBS"
2178 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2180 (define_expand "extendsfdf2"
2181 [(set (match_operand:DF 0 "register_operand" "")
2182 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2186 if (alpha_fptm >= ALPHA_FPTM_SU)
2187 operands[1] = force_reg (SFmode, operands[1]);
2191 [(set (match_operand:DF 0 "register_operand" "=&f")
2192 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2193 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2195 [(set_attr "type" "fadd")
2196 (set_attr "trap" "yes")])
2199 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2200 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2201 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2206 [(set_attr "type" "fcpys,fld,fst")])
2208 (define_expand "extendsftf2"
2209 [(use (match_operand:TF 0 "register_operand" ""))
2210 (use (match_operand:SF 1 "general_operand" ""))]
2211 "TARGET_HAS_XFLOATING_LIBS"
2214 rtx tmp = gen_reg_rtx (DFmode);
2215 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2216 emit_insn (gen_extenddftf2 (operands[0], tmp));
2220 (define_expand "extenddftf2"
2221 [(use (match_operand:TF 0 "register_operand" ""))
2222 (use (match_operand:DF 1 "general_operand" ""))]
2223 "TARGET_HAS_XFLOATING_LIBS"
2224 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2227 [(set (match_operand:SF 0 "register_operand" "=&f")
2228 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2229 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2230 "cvt%-%,%)%& %R1,%0"
2231 [(set_attr "type" "fadd")
2232 (set_attr "trap" "yes")])
2234 (define_insn "truncdfsf2"
2235 [(set (match_operand:SF 0 "register_operand" "=f")
2236 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2238 "cvt%-%,%)%& %R1,%0"
2239 [(set_attr "type" "fadd")
2240 (set_attr "trap" "yes")])
2242 (define_expand "trunctfdf2"
2243 [(use (match_operand:DF 0 "register_operand" ""))
2244 (use (match_operand:TF 1 "general_operand" ""))]
2245 "TARGET_HAS_XFLOATING_LIBS"
2246 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2248 (define_expand "trunctfsf2"
2249 [(use (match_operand:SF 0 "register_operand" ""))
2250 (use (match_operand:TF 1 "general_operand" ""))]
2251 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2254 rtx tmpf, sticky, arg, lo, hi;
2256 tmpf = gen_reg_rtx (DFmode);
2257 sticky = gen_reg_rtx (DImode);
2258 arg = copy_to_mode_reg (TFmode, operands[1]);
2259 lo = gen_lowpart (DImode, arg);
2260 hi = gen_highpart (DImode, arg);
2262 /* Convert the low word of the TFmode value into a sticky rounding bit,
2263 then or it into the low bit of the high word. This leaves the sticky
2264 bit at bit 48 of the fraction, which is representable in DFmode,
2265 which prevents rounding error in the final conversion to SFmode. */
2267 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2268 gen_rtx_NE (DImode, lo, const0_rtx)));
2269 emit_insn (gen_iordi3 (hi, hi, sticky));
2270 emit_insn (gen_trunctfdf2 (tmpf, arg));
2271 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2276 [(set (match_operand:SF 0 "register_operand" "=&f")
2277 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2278 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2279 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2280 "div%,%)%& %R1,%R2,%0"
2281 [(set_attr "type" "fdiv")
2282 (set_attr "opsize" "si")
2283 (set_attr "trap" "yes")])
2285 (define_insn "divsf3"
2286 [(set (match_operand:SF 0 "register_operand" "=f")
2287 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2288 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2290 "div%,%)%& %R1,%R2,%0"
2291 [(set_attr "type" "fdiv")
2292 (set_attr "opsize" "si")
2293 (set_attr "trap" "yes")])
2296 [(set (match_operand:DF 0 "register_operand" "=&f")
2297 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2298 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2299 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2300 "div%-%)%& %R1,%R2,%0"
2301 [(set_attr "type" "fdiv")
2302 (set_attr "trap" "yes")])
2304 (define_insn "divdf3"
2305 [(set (match_operand:DF 0 "register_operand" "=f")
2306 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2307 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2309 "div%-%)%& %R1,%R2,%0"
2310 [(set_attr "type" "fdiv")
2311 (set_attr "trap" "yes")])
2314 [(set (match_operand:DF 0 "register_operand" "=f")
2315 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2316 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2317 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2318 "div%-%)%& %R1,%R2,%0"
2319 [(set_attr "type" "fdiv")
2320 (set_attr "trap" "yes")])
2323 [(set (match_operand:DF 0 "register_operand" "=f")
2324 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2326 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2327 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2328 "div%-%)%& %R1,%R2,%0"
2329 [(set_attr "type" "fdiv")
2330 (set_attr "trap" "yes")])
2333 [(set (match_operand:DF 0 "register_operand" "=f")
2334 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2335 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2336 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2337 "div%-%)%& %R1,%R2,%0"
2338 [(set_attr "type" "fdiv")
2339 (set_attr "trap" "yes")])
2341 (define_expand "divtf3"
2342 [(use (match_operand 0 "register_operand" ""))
2343 (use (match_operand 1 "general_operand" ""))
2344 (use (match_operand 2 "general_operand" ""))]
2345 "TARGET_HAS_XFLOATING_LIBS"
2346 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2349 [(set (match_operand:SF 0 "register_operand" "=&f")
2350 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2351 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2352 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2353 "mul%,%)%& %R1,%R2,%0"
2354 [(set_attr "type" "fmul")
2355 (set_attr "trap" "yes")])
2357 (define_insn "mulsf3"
2358 [(set (match_operand:SF 0 "register_operand" "=f")
2359 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2360 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2362 "mul%,%)%& %R1,%R2,%0"
2363 [(set_attr "type" "fmul")
2364 (set_attr "trap" "yes")])
2367 [(set (match_operand:DF 0 "register_operand" "=&f")
2368 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2369 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2370 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2371 "mul%-%)%& %R1,%R2,%0"
2372 [(set_attr "type" "fmul")
2373 (set_attr "trap" "yes")])
2375 (define_insn "muldf3"
2376 [(set (match_operand:DF 0 "register_operand" "=f")
2377 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2378 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2380 "mul%-%)%& %R1,%R2,%0"
2381 [(set_attr "type" "fmul")
2382 (set_attr "trap" "yes")])
2385 [(set (match_operand:DF 0 "register_operand" "=f")
2386 (mult:DF (float_extend:DF
2387 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2388 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2389 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2390 "mul%-%)%& %R1,%R2,%0"
2391 [(set_attr "type" "fmul")
2392 (set_attr "trap" "yes")])
2395 [(set (match_operand:DF 0 "register_operand" "=f")
2396 (mult:DF (float_extend:DF
2397 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2399 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2400 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2401 "mul%-%)%& %R1,%R2,%0"
2402 [(set_attr "type" "fmul")
2403 (set_attr "trap" "yes")])
2405 (define_expand "multf3"
2406 [(use (match_operand 0 "register_operand" ""))
2407 (use (match_operand 1 "general_operand" ""))
2408 (use (match_operand 2 "general_operand" ""))]
2409 "TARGET_HAS_XFLOATING_LIBS"
2410 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2413 [(set (match_operand:SF 0 "register_operand" "=&f")
2414 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2415 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2416 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2417 "sub%,%)%& %R1,%R2,%0"
2418 [(set_attr "type" "fadd")
2419 (set_attr "trap" "yes")])
2421 (define_insn "subsf3"
2422 [(set (match_operand:SF 0 "register_operand" "=f")
2423 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2424 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2426 "sub%,%)%& %R1,%R2,%0"
2427 [(set_attr "type" "fadd")
2428 (set_attr "trap" "yes")])
2431 [(set (match_operand:DF 0 "register_operand" "=&f")
2432 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2433 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2434 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2435 "sub%-%)%& %R1,%R2,%0"
2436 [(set_attr "type" "fadd")
2437 (set_attr "trap" "yes")])
2439 (define_insn "subdf3"
2440 [(set (match_operand:DF 0 "register_operand" "=f")
2441 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2442 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2444 "sub%-%)%& %R1,%R2,%0"
2445 [(set_attr "type" "fadd")
2446 (set_attr "trap" "yes")])
2449 [(set (match_operand:DF 0 "register_operand" "=f")
2450 (minus:DF (float_extend:DF
2451 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2452 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2453 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2454 "sub%-%)%& %R1,%R2,%0"
2455 [(set_attr "type" "fadd")
2456 (set_attr "trap" "yes")])
2459 [(set (match_operand:DF 0 "register_operand" "=f")
2460 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2462 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2463 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2464 "sub%-%)%& %R1,%R2,%0"
2465 [(set_attr "type" "fadd")
2466 (set_attr "trap" "yes")])
2469 [(set (match_operand:DF 0 "register_operand" "=f")
2470 (minus:DF (float_extend:DF
2471 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2473 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2474 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2475 "sub%-%)%& %R1,%R2,%0"
2476 [(set_attr "type" "fadd")
2477 (set_attr "trap" "yes")])
2479 (define_expand "subtf3"
2480 [(use (match_operand 0 "register_operand" ""))
2481 (use (match_operand 1 "general_operand" ""))
2482 (use (match_operand 2 "general_operand" ""))]
2483 "TARGET_HAS_XFLOATING_LIBS"
2484 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2487 [(set (match_operand:SF 0 "register_operand" "=&f")
2488 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2489 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2491 [(set_attr "type" "fsqrt")
2492 (set_attr "opsize" "si")
2493 (set_attr "trap" "yes")])
2495 (define_insn "sqrtsf2"
2496 [(set (match_operand:SF 0 "register_operand" "=f")
2497 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2498 "TARGET_FP && TARGET_FIX"
2500 [(set_attr "type" "fsqrt")
2501 (set_attr "opsize" "si")
2502 (set_attr "trap" "yes")])
2505 [(set (match_operand:DF 0 "register_operand" "=&f")
2506 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2507 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2509 [(set_attr "type" "fsqrt")
2510 (set_attr "trap" "yes")])
2512 (define_insn "sqrtdf2"
2513 [(set (match_operand:DF 0 "register_operand" "=f")
2514 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2515 "TARGET_FP && TARGET_FIX"
2517 [(set_attr "type" "fsqrt")
2518 (set_attr "trap" "yes")])
2520 ;; Next are all the integer comparisons, and conditional moves and branches
2521 ;; and some of the related define_expand's and define_split's.
2523 (define_insn "*setcc_internal"
2524 [(set (match_operand 0 "register_operand" "=r")
2525 (match_operator 1 "alpha_comparison_operator"
2526 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2527 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2528 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2529 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2530 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2532 [(set_attr "type" "icmp")])
2534 (define_insn "*setcc_swapped_internal"
2535 [(set (match_operand 0 "register_operand" "=r")
2536 (match_operator 1 "alpha_swapped_comparison_operator"
2537 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2538 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2539 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2540 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2541 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2543 [(set_attr "type" "icmp")])
2545 (define_insn "*setne_internal"
2546 [(set (match_operand 0 "register_operand" "=r")
2547 (match_operator 1 "signed_comparison_operator"
2548 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2550 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2551 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2552 && GET_CODE (operands[1]) == NE
2553 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2555 [(set_attr "type" "icmp")])
2557 ;; The mode folding trick can't be used with const_int operands, since
2558 ;; reload needs to know the proper mode.
2560 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2561 ;; in order to create more pairs of constants. As long as we're allowing
2562 ;; two constants at the same time, and will have to reload one of them...
2564 (define_insn "*movqicc_internal"
2565 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2567 (match_operator 2 "signed_comparison_operator"
2568 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2569 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2570 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2571 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2572 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2578 [(set_attr "type" "icmov")])
2580 (define_insn "*movhicc_internal"
2581 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2583 (match_operator 2 "signed_comparison_operator"
2584 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2585 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2586 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2587 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2588 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2594 [(set_attr "type" "icmov")])
2596 (define_insn "*movsicc_internal"
2597 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2599 (match_operator 2 "signed_comparison_operator"
2600 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2601 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2602 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2603 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2604 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2610 [(set_attr "type" "icmov")])
2612 (define_insn "*movdicc_internal"
2613 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2615 (match_operator 2 "signed_comparison_operator"
2616 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2617 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2618 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2619 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2620 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2626 [(set_attr "type" "icmov")])
2628 (define_insn "*movqicc_lbc"
2629 [(set (match_operand:QI 0 "register_operand" "=r,r")
2631 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2635 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2636 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2641 [(set_attr "type" "icmov")])
2643 (define_insn "*movhicc_lbc"
2644 [(set (match_operand:HI 0 "register_operand" "=r,r")
2646 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2650 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2651 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2656 [(set_attr "type" "icmov")])
2658 (define_insn "*movsicc_lbc"
2659 [(set (match_operand:SI 0 "register_operand" "=r,r")
2661 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2665 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2666 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2671 [(set_attr "type" "icmov")])
2673 (define_insn "*movdicc_lbc"
2674 [(set (match_operand:DI 0 "register_operand" "=r,r")
2676 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2680 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2681 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2686 [(set_attr "type" "icmov")])
2688 (define_insn "*movqicc_lbs"
2689 [(set (match_operand:QI 0 "register_operand" "=r,r")
2691 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2695 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2696 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2701 [(set_attr "type" "icmov")])
2703 (define_insn "*movhicc_lbs"
2704 [(set (match_operand:HI 0 "register_operand" "=r,r")
2706 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2710 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2711 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2716 [(set_attr "type" "icmov")])
2718 (define_insn "*movsicc_lbs"
2719 [(set (match_operand:SI 0 "register_operand" "=r,r")
2721 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2725 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2726 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2731 [(set_attr "type" "icmov")])
2733 (define_insn "*movdicc_lbs"
2734 [(set (match_operand:DI 0 "register_operand" "=r,r")
2736 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2740 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2741 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2746 [(set_attr "type" "icmov")])
2748 ;; For ABS, we have two choices, depending on whether the input and output
2749 ;; registers are the same or not.
2750 (define_expand "absdi2"
2751 [(set (match_operand:DI 0 "register_operand" "")
2752 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2755 { if (rtx_equal_p (operands[0], operands[1]))
2756 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2758 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2763 (define_expand "absdi2_same"
2764 [(set (match_operand:DI 1 "register_operand" "")
2765 (neg:DI (match_operand:DI 0 "register_operand" "")))
2767 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2773 (define_expand "absdi2_diff"
2774 [(set (match_operand:DI 0 "register_operand" "")
2775 (neg:DI (match_operand:DI 1 "register_operand" "")))
2777 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2784 [(set (match_operand:DI 0 "register_operand" "")
2785 (abs:DI (match_dup 0)))
2786 (clobber (match_operand:DI 2 "register_operand" ""))]
2788 [(set (match_dup 1) (neg:DI (match_dup 0)))
2789 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2790 (match_dup 0) (match_dup 1)))]
2794 [(set (match_operand:DI 0 "register_operand" "")
2795 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2796 "! rtx_equal_p (operands[0], operands[1])"
2797 [(set (match_dup 0) (neg:DI (match_dup 1)))
2798 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2799 (match_dup 0) (match_dup 1)))]
2803 [(set (match_operand:DI 0 "register_operand" "")
2804 (neg:DI (abs:DI (match_dup 0))))
2805 (clobber (match_operand:DI 2 "register_operand" ""))]
2807 [(set (match_dup 1) (neg:DI (match_dup 0)))
2808 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2809 (match_dup 0) (match_dup 1)))]
2813 [(set (match_operand:DI 0 "register_operand" "")
2814 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2815 "! rtx_equal_p (operands[0], operands[1])"
2816 [(set (match_dup 0) (neg:DI (match_dup 1)))
2817 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2818 (match_dup 0) (match_dup 1)))]
2821 (define_insn "sminqi3"
2822 [(set (match_operand:QI 0 "register_operand" "=r")
2823 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2824 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2827 [(set_attr "type" "mvi")])
2829 (define_insn "uminqi3"
2830 [(set (match_operand:QI 0 "register_operand" "=r")
2831 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2832 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2835 [(set_attr "type" "mvi")])
2837 (define_insn "smaxqi3"
2838 [(set (match_operand:QI 0 "register_operand" "=r")
2839 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2840 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2843 [(set_attr "type" "mvi")])
2845 (define_insn "umaxqi3"
2846 [(set (match_operand:QI 0 "register_operand" "=r")
2847 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2848 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2851 [(set_attr "type" "mvi")])
2853 (define_insn "sminhi3"
2854 [(set (match_operand:HI 0 "register_operand" "=r")
2855 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2856 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2859 [(set_attr "type" "mvi")])
2861 (define_insn "uminhi3"
2862 [(set (match_operand:HI 0 "register_operand" "=r")
2863 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2864 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2867 [(set_attr "type" "mvi")])
2869 (define_insn "smaxhi3"
2870 [(set (match_operand:HI 0 "register_operand" "=r")
2871 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2872 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2875 [(set_attr "type" "mvi")])
2877 (define_insn "umaxhi3"
2878 [(set (match_operand:HI 0 "register_operand" "=r")
2879 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2880 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2883 [(set_attr "type" "shift")])
2885 (define_expand "smaxdi3"
2887 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2888 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2889 (set (match_operand:DI 0 "register_operand" "")
2890 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2891 (match_dup 1) (match_dup 2)))]
2894 { operands[3] = gen_reg_rtx (DImode);
2898 [(set (match_operand:DI 0 "register_operand" "")
2899 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2900 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2901 (clobber (match_operand:DI 3 "register_operand" ""))]
2902 "operands[2] != const0_rtx"
2903 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2904 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2905 (match_dup 1) (match_dup 2)))]
2909 [(set (match_operand:DI 0 "register_operand" "=r")
2910 (smax:DI (match_operand:DI 1 "register_operand" "0")
2914 [(set_attr "type" "icmov")])
2916 (define_expand "smindi3"
2918 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2919 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2920 (set (match_operand:DI 0 "register_operand" "")
2921 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2922 (match_dup 1) (match_dup 2)))]
2925 { operands[3] = gen_reg_rtx (DImode);
2929 [(set (match_operand:DI 0 "register_operand" "")
2930 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2931 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2932 (clobber (match_operand:DI 3 "register_operand" ""))]
2933 "operands[2] != const0_rtx"
2934 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2935 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2936 (match_dup 1) (match_dup 2)))]
2940 [(set (match_operand:DI 0 "register_operand" "=r")
2941 (smin:DI (match_operand:DI 1 "register_operand" "0")
2945 [(set_attr "type" "icmov")])
2947 (define_expand "umaxdi3"
2949 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2950 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2951 (set (match_operand:DI 0 "register_operand" "")
2952 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2953 (match_dup 1) (match_dup 2)))]
2956 { operands[3] = gen_reg_rtx (DImode);
2960 [(set (match_operand:DI 0 "register_operand" "")
2961 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2962 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2963 (clobber (match_operand:DI 3 "register_operand" ""))]
2964 "operands[2] != const0_rtx"
2965 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2966 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2967 (match_dup 1) (match_dup 2)))]
2970 (define_expand "umindi3"
2972 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2973 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2974 (set (match_operand:DI 0 "register_operand" "")
2975 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2976 (match_dup 1) (match_dup 2)))]
2979 { operands[3] = gen_reg_rtx (DImode);
2983 [(set (match_operand:DI 0 "register_operand" "")
2984 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2985 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2986 (clobber (match_operand:DI 3 "register_operand" ""))]
2987 "operands[2] != const0_rtx"
2988 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2989 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2990 (match_dup 1) (match_dup 2)))]
2996 (match_operator 1 "signed_comparison_operator"
2997 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2999 (label_ref (match_operand 0 "" ""))
3003 [(set_attr "type" "ibr")])
3008 (match_operator 1 "signed_comparison_operator"
3010 (match_operand:DI 2 "register_operand" "r")])
3011 (label_ref (match_operand 0 "" ""))
3015 [(set_attr "type" "ibr")])
3020 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3024 (label_ref (match_operand 0 "" ""))
3028 [(set_attr "type" "ibr")])
3033 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3037 (label_ref (match_operand 0 "" ""))
3041 [(set_attr "type" "ibr")])
3047 (match_operator 1 "comparison_operator"
3048 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3050 (match_operand:DI 3 "const_int_operand" ""))
3052 (label_ref (match_operand 0 "" ""))
3054 (clobber (match_operand:DI 4 "register_operand" ""))])]
3055 "INTVAL (operands[3]) != 0"
3057 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3059 (if_then_else (match_op_dup 1
3060 [(zero_extract:DI (match_dup 4)
3064 (label_ref (match_dup 0))
3068 ;; The following are the corresponding floating-point insns. Recall
3069 ;; we need to have variants that expand the arguments from SFmode
3072 (define_insn "*cmpdf_tp"
3073 [(set (match_operand:DF 0 "register_operand" "=&f")
3074 (match_operator:DF 1 "alpha_fp_comparison_operator"
3075 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3076 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3077 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3078 "cmp%-%C1%' %R2,%R3,%0"
3079 [(set_attr "type" "fadd")
3080 (set_attr "trap" "yes")])
3082 (define_insn "*cmpdf_no_tp"
3083 [(set (match_operand:DF 0 "register_operand" "=f")
3084 (match_operator:DF 1 "alpha_fp_comparison_operator"
3085 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3086 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3087 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3088 "cmp%-%C1%' %R2,%R3,%0"
3089 [(set_attr "type" "fadd")
3090 (set_attr "trap" "yes")])
3093 [(set (match_operand:DF 0 "register_operand" "=&f")
3094 (match_operator:DF 1 "alpha_fp_comparison_operator"
3096 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3097 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3098 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3099 "cmp%-%C1%' %R2,%R3,%0"
3100 [(set_attr "type" "fadd")
3101 (set_attr "trap" "yes")])
3104 [(set (match_operand:DF 0 "register_operand" "=f")
3105 (match_operator:DF 1 "alpha_fp_comparison_operator"
3107 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3108 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3109 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3110 "cmp%-%C1%' %R2,%R3,%0"
3111 [(set_attr "type" "fadd")
3112 (set_attr "trap" "yes")])
3115 [(set (match_operand:DF 0 "register_operand" "=&f")
3116 (match_operator:DF 1 "alpha_fp_comparison_operator"
3117 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3119 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3120 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3121 "cmp%-%C1%' %R2,%R3,%0"
3122 [(set_attr "type" "fadd")
3123 (set_attr "trap" "yes")])
3126 [(set (match_operand:DF 0 "register_operand" "=f")
3127 (match_operator:DF 1 "alpha_fp_comparison_operator"
3128 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3130 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3131 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3132 "cmp%-%C1%' %R2,%R3,%0"
3133 [(set_attr "type" "fadd")
3134 (set_attr "trap" "yes")])
3137 [(set (match_operand:DF 0 "register_operand" "=&f")
3138 (match_operator:DF 1 "alpha_fp_comparison_operator"
3140 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3142 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3143 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3144 "cmp%-%C1%' %R2,%R3,%0"
3145 [(set_attr "type" "fadd")
3146 (set_attr "trap" "yes")])
3149 [(set (match_operand:DF 0 "register_operand" "=f")
3150 (match_operator:DF 1 "alpha_fp_comparison_operator"
3152 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3154 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3155 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3156 "cmp%-%C1%' %R2,%R3,%0"
3157 [(set_attr "type" "fadd")
3158 (set_attr "trap" "yes")])
3161 [(set (match_operand:DF 0 "register_operand" "=f,f")
3163 (match_operator 3 "signed_comparison_operator"
3164 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3165 (match_operand:DF 2 "fp0_operand" "G,G")])
3166 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3167 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3171 fcmov%D3 %R4,%R5,%0"
3172 [(set_attr "type" "fcmov")])
3175 [(set (match_operand:SF 0 "register_operand" "=f,f")
3177 (match_operator 3 "signed_comparison_operator"
3178 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3179 (match_operand:DF 2 "fp0_operand" "G,G")])
3180 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3181 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3185 fcmov%D3 %R4,%R5,%0"
3186 [(set_attr "type" "fcmov")])
3189 [(set (match_operand:DF 0 "register_operand" "=f,f")
3191 (match_operator 3 "signed_comparison_operator"
3192 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3193 (match_operand:DF 2 "fp0_operand" "G,G")])
3194 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3195 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3199 fcmov%D3 %R4,%R5,%0"
3200 [(set_attr "type" "fcmov")])
3203 [(set (match_operand:DF 0 "register_operand" "=f,f")
3205 (match_operator 3 "signed_comparison_operator"
3207 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3208 (match_operand:DF 2 "fp0_operand" "G,G")])
3209 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3210 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3214 fcmov%D3 %R4,%R5,%0"
3215 [(set_attr "type" "fcmov")])
3218 [(set (match_operand:SF 0 "register_operand" "=f,f")
3220 (match_operator 3 "signed_comparison_operator"
3222 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3223 (match_operand:DF 2 "fp0_operand" "G,G")])
3224 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3225 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3229 fcmov%D3 %R4,%R5,%0"
3230 [(set_attr "type" "fcmov")])
3233 [(set (match_operand:DF 0 "register_operand" "=f,f")
3235 (match_operator 3 "signed_comparison_operator"
3237 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3238 (match_operand:DF 2 "fp0_operand" "G,G")])
3239 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3240 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3244 fcmov%D3 %R4,%R5,%0"
3245 [(set_attr "type" "fcmov")])
3247 (define_expand "maxdf3"
3249 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3250 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3251 (set (match_operand:DF 0 "register_operand" "")
3252 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3253 (match_dup 1) (match_dup 2)))]
3256 { operands[3] = gen_reg_rtx (DFmode);
3257 operands[4] = CONST0_RTX (DFmode);
3260 (define_expand "mindf3"
3262 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3263 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3264 (set (match_operand:DF 0 "register_operand" "")
3265 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3266 (match_dup 1) (match_dup 2)))]
3269 { operands[3] = gen_reg_rtx (DFmode);
3270 operands[4] = CONST0_RTX (DFmode);
3273 (define_expand "maxsf3"
3275 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3276 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3277 (set (match_operand:SF 0 "register_operand" "")
3278 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3279 (match_dup 1) (match_dup 2)))]
3282 { operands[3] = gen_reg_rtx (DFmode);
3283 operands[4] = CONST0_RTX (DFmode);
3286 (define_expand "minsf3"
3288 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3289 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3290 (set (match_operand:SF 0 "register_operand" "")
3291 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3292 (match_dup 1) (match_dup 2)))]
3295 { operands[3] = gen_reg_rtx (DFmode);
3296 operands[4] = CONST0_RTX (DFmode);
3302 (match_operator 1 "signed_comparison_operator"
3303 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3304 (match_operand:DF 3 "fp0_operand" "G")])
3305 (label_ref (match_operand 0 "" ""))
3309 [(set_attr "type" "fbr")])
3314 (match_operator 1 "signed_comparison_operator"
3316 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3317 (match_operand:DF 3 "fp0_operand" "G")])
3318 (label_ref (match_operand 0 "" ""))
3322 [(set_attr "type" "fbr")])
3324 ;; These are the main define_expand's used to make conditional branches
3327 (define_expand "cmpdf"
3328 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3329 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3333 alpha_compare.op0 = operands[0];
3334 alpha_compare.op1 = operands[1];
3335 alpha_compare.fp_p = 1;
3339 (define_expand "cmptf"
3340 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3341 (match_operand:TF 1 "general_operand" "")))]
3342 "TARGET_HAS_XFLOATING_LIBS"
3345 alpha_compare.op0 = operands[0];
3346 alpha_compare.op1 = operands[1];
3347 alpha_compare.fp_p = 1;
3351 (define_expand "cmpdi"
3352 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3353 (match_operand:DI 1 "general_operand" "")))]
3357 alpha_compare.op0 = operands[0];
3358 alpha_compare.op1 = operands[1];
3359 alpha_compare.fp_p = 0;
3363 (define_expand "beq"
3365 (if_then_else (match_dup 1)
3366 (label_ref (match_operand 0 "" ""))
3369 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3371 (define_expand "bne"
3373 (if_then_else (match_dup 1)
3374 (label_ref (match_operand 0 "" ""))
3377 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3379 (define_expand "blt"
3381 (if_then_else (match_dup 1)
3382 (label_ref (match_operand 0 "" ""))
3385 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3387 (define_expand "ble"
3389 (if_then_else (match_dup 1)
3390 (label_ref (match_operand 0 "" ""))
3393 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3395 (define_expand "bgt"
3397 (if_then_else (match_dup 1)
3398 (label_ref (match_operand 0 "" ""))
3401 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3403 (define_expand "bge"
3405 (if_then_else (match_dup 1)
3406 (label_ref (match_operand 0 "" ""))
3409 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3411 (define_expand "bltu"
3413 (if_then_else (match_dup 1)
3414 (label_ref (match_operand 0 "" ""))
3417 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3419 (define_expand "bleu"
3421 (if_then_else (match_dup 1)
3422 (label_ref (match_operand 0 "" ""))
3425 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3427 (define_expand "bgtu"
3429 (if_then_else (match_dup 1)
3430 (label_ref (match_operand 0 "" ""))
3433 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3435 (define_expand "bgeu"
3437 (if_then_else (match_dup 1)
3438 (label_ref (match_operand 0 "" ""))
3441 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3443 (define_expand "bunordered"
3445 (if_then_else (match_dup 1)
3446 (label_ref (match_operand 0 "" ""))
3449 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3451 (define_expand "bordered"
3453 (if_then_else (match_dup 1)
3454 (label_ref (match_operand 0 "" ""))
3457 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3459 (define_expand "seq"
3460 [(set (match_operand:DI 0 "register_operand" "")
3463 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3465 (define_expand "sne"
3466 [(set (match_operand:DI 0 "register_operand" "")
3469 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3471 (define_expand "slt"
3472 [(set (match_operand:DI 0 "register_operand" "")
3475 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3477 (define_expand "sle"
3478 [(set (match_operand:DI 0 "register_operand" "")
3481 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3483 (define_expand "sgt"
3484 [(set (match_operand:DI 0 "register_operand" "")
3487 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3489 (define_expand "sge"
3490 [(set (match_operand:DI 0 "register_operand" "")
3493 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3495 (define_expand "sltu"
3496 [(set (match_operand:DI 0 "register_operand" "")
3499 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3501 (define_expand "sleu"
3502 [(set (match_operand:DI 0 "register_operand" "")
3505 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3507 (define_expand "sgtu"
3508 [(set (match_operand:DI 0 "register_operand" "")
3511 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3513 (define_expand "sgeu"
3514 [(set (match_operand:DI 0 "register_operand" "")
3517 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3519 (define_expand "sunordered"
3520 [(set (match_operand:DI 0 "register_operand" "")
3523 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3525 (define_expand "sordered"
3526 [(set (match_operand:DI 0 "register_operand" "")
3529 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3531 ;; These are the main define_expand's used to make conditional moves.
3533 (define_expand "movsicc"
3534 [(set (match_operand:SI 0 "register_operand" "")
3535 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3536 (match_operand:SI 2 "reg_or_8bit_operand" "")
3537 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3541 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3545 (define_expand "movdicc"
3546 [(set (match_operand:DI 0 "register_operand" "")
3547 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3548 (match_operand:DI 2 "reg_or_8bit_operand" "")
3549 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3553 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3557 (define_expand "movsfcc"
3558 [(set (match_operand:SF 0 "register_operand" "")
3559 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3560 (match_operand:SF 2 "reg_or_8bit_operand" "")
3561 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3565 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3569 (define_expand "movdfcc"
3570 [(set (match_operand:DF 0 "register_operand" "")
3571 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3572 (match_operand:DF 2 "reg_or_8bit_operand" "")
3573 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3577 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3581 ;; These define_split definitions are used in cases when comparisons have
3582 ;; not be stated in the correct way and we need to reverse the second
3583 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3584 ;; comparison that tests the result being reversed. We have one define_split
3585 ;; for each use of a comparison. They do not match valid insns and need
3586 ;; not generate valid insns.
3588 ;; We can also handle equality comparisons (and inequality comparisons in
3589 ;; cases where the resulting add cannot overflow) by doing an add followed by
3590 ;; a comparison with zero. This is faster since the addition takes one
3591 ;; less cycle than a compare when feeding into a conditional move.
3592 ;; For this case, we also have an SImode pattern since we can merge the add
3593 ;; and sign extend and the order doesn't matter.
3595 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3596 ;; operation could have been generated.
3599 [(set (match_operand:DI 0 "register_operand" "")
3601 (match_operator 1 "comparison_operator"
3602 [(match_operand:DI 2 "reg_or_0_operand" "")
3603 (match_operand:DI 3 "reg_or_cint_operand" "")])
3604 (match_operand:DI 4 "reg_or_cint_operand" "")
3605 (match_operand:DI 5 "reg_or_cint_operand" "")))
3606 (clobber (match_operand:DI 6 "register_operand" ""))]
3607 "operands[3] != const0_rtx"
3608 [(set (match_dup 6) (match_dup 7))
3610 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3612 { enum rtx_code code = GET_CODE (operands[1]);
3613 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3615 /* If we are comparing for equality with a constant and that constant
3616 appears in the arm when the register equals the constant, use the
3617 register since that is more likely to match (and to produce better code
3620 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3621 && rtx_equal_p (operands[4], operands[3]))
3622 operands[4] = operands[2];
3624 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3625 && rtx_equal_p (operands[5], operands[3]))
3626 operands[5] = operands[2];
3628 if (code == NE || code == EQ
3629 || (extended_count (operands[2], DImode, unsignedp) >= 1
3630 && extended_count (operands[3], DImode, unsignedp) >= 1))
3632 if (GET_CODE (operands[3]) == CONST_INT)
3633 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3634 GEN_INT (- INTVAL (operands[3])));
3636 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3638 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3641 else if (code == EQ || code == LE || code == LT
3642 || code == LEU || code == LTU)
3644 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3645 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3649 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3650 operands[2], operands[3]);
3651 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3656 [(set (match_operand:DI 0 "register_operand" "")
3658 (match_operator 1 "comparison_operator"
3659 [(match_operand:SI 2 "reg_or_0_operand" "")
3660 (match_operand:SI 3 "reg_or_cint_operand" "")])
3661 (match_operand:DI 4 "reg_or_8bit_operand" "")
3662 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3663 (clobber (match_operand:DI 6 "register_operand" ""))]
3664 "operands[3] != const0_rtx
3665 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3666 [(set (match_dup 6) (match_dup 7))
3668 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3670 { enum rtx_code code = GET_CODE (operands[1]);
3671 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3674 if ((code != NE && code != EQ
3675 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3676 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3679 if (GET_CODE (operands[3]) == CONST_INT)
3680 tem = gen_rtx_PLUS (SImode, operands[2],
3681 GEN_INT (- INTVAL (operands[3])));
3683 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3685 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3686 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3687 operands[6], const0_rtx);
3693 (match_operator 1 "comparison_operator"
3694 [(match_operand:DI 2 "reg_or_0_operand" "")
3695 (match_operand:DI 3 "reg_or_cint_operand" "")])
3696 (label_ref (match_operand 0 "" ""))
3698 (clobber (match_operand:DI 4 "register_operand" ""))]
3699 "operands[3] != const0_rtx"
3700 [(set (match_dup 4) (match_dup 5))
3701 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3703 { enum rtx_code code = GET_CODE (operands[1]);
3704 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3706 if (code == NE || code == EQ
3707 || (extended_count (operands[2], DImode, unsignedp) >= 1
3708 && extended_count (operands[3], DImode, unsignedp) >= 1))
3710 if (GET_CODE (operands[3]) == CONST_INT)
3711 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3712 GEN_INT (- INTVAL (operands[3])));
3714 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3716 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3719 else if (code == EQ || code == LE || code == LT
3720 || code == LEU || code == LTU)
3722 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3723 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3727 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3728 operands[2], operands[3]);
3729 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3736 (match_operator 1 "comparison_operator"
3737 [(match_operand:SI 2 "reg_or_0_operand" "")
3738 (match_operand:SI 3 "const_int_operand" "")])
3739 (label_ref (match_operand 0 "" ""))
3741 (clobber (match_operand:DI 4 "register_operand" ""))]
3742 "operands[3] != const0_rtx
3743 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3744 [(set (match_dup 4) (match_dup 5))
3745 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3749 if (GET_CODE (operands[3]) == CONST_INT)
3750 tem = gen_rtx_PLUS (SImode, operands[2],
3751 GEN_INT (- INTVAL (operands[3])));
3753 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3755 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3756 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3757 operands[4], const0_rtx);
3760 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3761 ;; This eliminates one, and sometimes two, insns when the AND can be done
3764 [(set (match_operand:DI 0 "register_operand" "")
3765 (match_operator:DI 1 "comparison_operator"
3766 [(match_operand:DI 2 "register_operand" "")
3767 (match_operand:DI 3 "const_int_operand" "")]))
3768 (clobber (match_operand:DI 4 "register_operand" ""))]
3769 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3770 && (GET_CODE (operands[1]) == GTU
3771 || GET_CODE (operands[1]) == LEU
3772 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3773 && extended_count (operands[2], DImode, 1) > 0))"
3774 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3775 (set (match_dup 0) (match_dup 6))]
3778 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3779 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3780 || GET_CODE (operands[1]) == GT)
3782 DImode, operands[4], const0_rtx);
3785 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
3788 [(set (match_operand 0 "register_operand" "")
3789 (if_then_else (match_operator 1 "signed_comparison_operator"
3790 [(match_operand:DI 2 "reg_or_0_operand" "")
3792 (match_operand 3 "const_int_operand" "")
3793 (match_operand 4 "const_int_operand" "")))]
3798 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
3799 operands[2], operands[3], operands[4]))
3805 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
3806 ;; Oh well, we match it in movcc, so it must be partially our fault.
3808 [(set (match_operand 0 "register_operand" "")
3809 (if_then_else (match_operator 1 "signed_comparison_operator"
3811 (match_operand:DI 2 "reg_or_0_operand" "")])
3812 (match_operand 3 "const_int_operand" "")
3813 (match_operand 4 "const_int_operand" "")))]
3818 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
3819 operands[0], operands[2], operands[3],
3826 (define_insn_and_split "*cmp_sadd_di"
3827 [(set (match_operand:DI 0 "register_operand" "=r")
3828 (plus:DI (if_then_else:DI
3829 (match_operator 1 "alpha_zero_comparison_operator"
3830 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3832 (match_operand:DI 3 "const48_operand" "I")
3834 (match_operand:DI 4 "sext_add_operand" "rIO")))
3835 (clobber (match_scratch:DI 5 "=r"))]
3838 "! no_new_pseudos || reload_completed"
3840 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3842 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
3846 if (! no_new_pseudos)
3847 operands[5] = gen_reg_rtx (DImode);
3848 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3849 operands[5] = operands[0];
3852 (define_insn_and_split "*cmp_sadd_si"
3853 [(set (match_operand:SI 0 "register_operand" "=r")
3854 (plus:SI (if_then_else:SI
3855 (match_operator 1 "alpha_zero_comparison_operator"
3856 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3858 (match_operand:SI 3 "const48_operand" "I")
3860 (match_operand:SI 4 "sext_add_operand" "rIO")))
3861 (clobber (match_scratch:SI 5 "=r"))]
3864 "! no_new_pseudos || reload_completed"
3866 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3868 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3872 if (! no_new_pseudos)
3873 operands[5] = gen_reg_rtx (DImode);
3874 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3875 operands[5] = operands[0];
3878 (define_insn_and_split "*cmp_sadd_sidi"
3879 [(set (match_operand:DI 0 "register_operand" "=r")
3881 (plus:SI (if_then_else:SI
3882 (match_operator 1 "alpha_zero_comparison_operator"
3883 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3885 (match_operand:SI 3 "const48_operand" "I")
3887 (match_operand:SI 4 "sext_add_operand" "rIO"))))
3888 (clobber (match_scratch:SI 5 "=r"))]
3891 "! no_new_pseudos || reload_completed"
3893 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3895 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3899 if (! no_new_pseudos)
3900 operands[5] = gen_reg_rtx (DImode);
3901 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3902 operands[5] = operands[0];
3905 (define_insn_and_split "*cmp_ssub_di"
3906 [(set (match_operand:DI 0 "register_operand" "=r")
3907 (minus:DI (if_then_else:DI
3908 (match_operator 1 "alpha_zero_comparison_operator"
3909 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3911 (match_operand:DI 3 "const48_operand" "I")
3913 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
3914 (clobber (match_scratch:DI 5 "=r"))]
3917 "! no_new_pseudos || reload_completed"
3919 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3921 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
3925 if (! no_new_pseudos)
3926 operands[5] = gen_reg_rtx (DImode);
3927 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3928 operands[5] = operands[0];
3931 (define_insn_and_split "*cmp_ssub_si"
3932 [(set (match_operand:SI 0 "register_operand" "=r")
3933 (minus:SI (if_then_else:SI
3934 (match_operator 1 "alpha_zero_comparison_operator"
3935 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3937 (match_operand:SI 3 "const48_operand" "I")
3939 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
3940 (clobber (match_scratch:SI 5 "=r"))]
3943 "! no_new_pseudos || reload_completed"
3945 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3947 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
3951 if (! no_new_pseudos)
3952 operands[5] = gen_reg_rtx (DImode);
3953 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3954 operands[5] = operands[0];
3957 (define_insn_and_split "*cmp_ssub_sidi"
3958 [(set (match_operand:DI 0 "register_operand" "=r")
3960 (minus:SI (if_then_else:SI
3961 (match_operator 1 "alpha_zero_comparison_operator"
3962 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3964 (match_operand:SI 3 "const48_operand" "I")
3966 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
3967 (clobber (match_scratch:SI 5 "=r"))]
3970 "! no_new_pseudos || reload_completed"
3972 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3974 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
3978 if (! no_new_pseudos)
3979 operands[5] = gen_reg_rtx (DImode);
3980 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3981 operands[5] = operands[0];
3984 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3985 ;; work differently, so we have different patterns for each.
3987 (define_expand "call"
3988 [(use (match_operand:DI 0 "" ""))
3989 (use (match_operand 1 "" ""))
3990 (use (match_operand 2 "" ""))
3991 (use (match_operand 3 "" ""))]
3994 { if (TARGET_WINDOWS_NT)
3995 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3996 else if (TARGET_OPEN_VMS)
3997 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3999 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4004 (define_expand "sibcall"
4005 [(call (mem:DI (match_operand 0 "" ""))
4006 (match_operand 1 "" ""))]
4007 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4010 if (GET_CODE (operands[0]) != MEM)
4012 operands[0] = XEXP (operands[0], 0);
4015 (define_expand "call_osf"
4016 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4017 (match_operand 1 "" ""))
4018 (clobber (reg:DI 27))
4019 (clobber (reg:DI 26))])]
4022 { if (GET_CODE (operands[0]) != MEM)
4025 operands[0] = XEXP (operands[0], 0);
4027 if (GET_CODE (operands[0]) != SYMBOL_REF
4028 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
4030 rtx tem = gen_rtx_REG (DImode, 27);
4031 emit_move_insn (tem, operands[0]);
4036 (define_expand "call_nt"
4037 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4038 (match_operand 1 "" ""))
4039 (clobber (reg:DI 26))])]
4042 { if (GET_CODE (operands[0]) != MEM)
4045 operands[0] = XEXP (operands[0], 0);
4046 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4047 operands[0] = force_reg (DImode, operands[0]);
4051 ;; call openvms/alpha
4052 ;; op 0: symbol ref for called function
4053 ;; op 1: next_arg_reg (argument information value for R25)
4055 (define_expand "call_vms"
4056 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4057 (match_operand 1 "" ""))
4061 (clobber (reg:DI 27))])]
4064 { if (GET_CODE (operands[0]) != MEM)
4067 operands[0] = XEXP (operands[0], 0);
4069 /* Always load AI with argument information, then handle symbolic and
4070 indirect call differently. Load RA and set operands[2] to PV in
4073 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4074 if (GET_CODE (operands[0]) == SYMBOL_REF)
4076 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4078 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4080 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4084 emit_move_insn (gen_rtx_REG (Pmode, 26),
4085 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4086 operands[2] = operands[0];
4091 (define_expand "call_value"
4092 [(use (match_operand 0 "" ""))
4093 (use (match_operand:DI 1 "" ""))
4094 (use (match_operand 2 "" ""))
4095 (use (match_operand 3 "" ""))
4096 (use (match_operand 4 "" ""))]
4099 { if (TARGET_WINDOWS_NT)
4100 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4101 else if (TARGET_OPEN_VMS)
4102 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4105 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4110 (define_expand "sibcall_value"
4111 [(set (match_operand 0 "" "")
4112 (call (mem:DI (match_operand 1 "" ""))
4113 (match_operand 2 "" "")))]
4114 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4117 if (GET_CODE (operands[1]) != MEM)
4119 operands[1] = XEXP (operands[1], 0);
4122 (define_expand "call_value_osf"
4123 [(parallel [(set (match_operand 0 "" "")
4124 (call (mem:DI (match_operand 1 "" ""))
4125 (match_operand 2 "" "")))
4126 (clobber (reg:DI 27))
4127 (clobber (reg:DI 26))])]
4130 { if (GET_CODE (operands[1]) != MEM)
4133 operands[1] = XEXP (operands[1], 0);
4135 if (GET_CODE (operands[1]) != SYMBOL_REF
4136 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
4138 rtx tem = gen_rtx_REG (DImode, 27);
4139 emit_move_insn (tem, operands[1]);
4144 (define_expand "call_value_nt"
4145 [(parallel [(set (match_operand 0 "" "")
4146 (call (mem:DI (match_operand 1 "" ""))
4147 (match_operand 2 "" "")))
4148 (clobber (reg:DI 26))])]
4151 { if (GET_CODE (operands[1]) != MEM)
4154 operands[1] = XEXP (operands[1], 0);
4155 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4156 operands[1] = force_reg (DImode, operands[1]);
4159 (define_expand "call_value_vms"
4160 [(parallel [(set (match_operand 0 "" "")
4161 (call (mem:DI (match_operand:DI 1 "" ""))
4162 (match_operand 2 "" "")))
4166 (clobber (reg:DI 27))])]
4169 { if (GET_CODE (operands[1]) != MEM)
4172 operands[1] = XEXP (operands[1], 0);
4174 /* Always load AI with argument information, then handle symbolic and
4175 indirect call differently. Load RA and set operands[3] to PV in
4178 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4179 if (GET_CODE (operands[1]) == SYMBOL_REF)
4181 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4183 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4185 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4189 emit_move_insn (gen_rtx_REG (Pmode, 26),
4190 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4191 operands[3] = operands[1];
4195 (define_insn "*call_osf_1"
4196 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4197 (match_operand 1 "" ""))
4198 (clobber (reg:DI 27))
4199 (clobber (reg:DI 26))]
4200 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4202 jsr $26,($27),0\;ldgp $29,0($26)
4204 jsr $26,%0\;ldgp $29,0($26)"
4205 [(set_attr "type" "jsr")
4206 (set_attr "length" "12,*,16")])
4208 (define_insn "*sibcall_osf_1"
4209 [(call (mem:DI (match_operand:DI 0 "call_operand" "R,i"))
4210 (match_operand 1 "" ""))]
4211 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4215 [(set_attr "type" "jsr")
4216 (set_attr "length" "*,8")])
4218 (define_insn "*call_nt_1"
4219 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4220 (match_operand 1 "" ""))
4221 (clobber (reg:DI 26))]
4227 [(set_attr "type" "jsr")
4228 (set_attr "length" "*,*,12")])
4230 (define_insn "*call_vms_1"
4231 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
4232 (match_operand 1 "" ""))
4233 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4236 (clobber (reg:DI 27))]
4239 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4240 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4241 [(set_attr "type" "jsr")
4242 (set_attr "length" "12,16")])
4244 ;; Call subroutine returning any type.
4246 (define_expand "untyped_call"
4247 [(parallel [(call (match_operand 0 "" "")
4249 (match_operand 1 "" "")
4250 (match_operand 2 "" "")])]
4256 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4258 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4260 rtx set = XVECEXP (operands[2], 0, i);
4261 emit_move_insn (SET_DEST (set), SET_SRC (set));
4264 /* The optimizer does not know that the call sets the function value
4265 registers we stored in the result block. We avoid problems by
4266 claiming that all hard registers are used and clobbered at this
4268 emit_insn (gen_blockage ());
4273 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4274 ;; all of memory. This blocks insns from being moved across this point.
4276 (define_insn "blockage"
4277 [(unspec_volatile [(const_int 0)] 1)]
4280 [(set_attr "length" "0")])
4284 (label_ref (match_operand 0 "" "")))]
4287 [(set_attr "type" "ibr")])
4289 (define_expand "return"
4294 (define_insn "*return_internal"
4298 [(set_attr "type" "ibr")])
4300 (define_insn "indirect_jump"
4301 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4304 [(set_attr "type" "ibr")])
4306 (define_expand "tablejump"
4307 [(use (match_operand:SI 0 "register_operand" ""))
4308 (use (match_operand:SI 1 "" ""))]
4312 if (TARGET_WINDOWS_NT)
4313 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4314 else if (TARGET_OPEN_VMS)
4315 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4317 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4322 (define_expand "tablejump_osf"
4324 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4325 (parallel [(set (pc)
4326 (plus:DI (match_dup 3)
4327 (label_ref (match_operand 1 "" ""))))
4328 (clobber (match_scratch:DI 2 "=r"))])]
4331 { operands[3] = gen_reg_rtx (DImode); }")
4333 (define_expand "tablejump_nt"
4335 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4336 (parallel [(set (pc)
4338 (use (label_ref (match_operand 1 "" "")))])]
4341 { operands[3] = gen_reg_rtx (DImode); }")
4344 ;; tablejump, openVMS way
4346 ;; op 1: label preceding jump-table
4348 (define_expand "tablejump_vms"
4350 (match_operand:DI 0 "register_operand" ""))
4352 (plus:DI (match_dup 2)
4353 (label_ref (match_operand 1 "" ""))))]
4356 { operands[2] = gen_reg_rtx (DImode); }")
4360 (plus (match_operand:DI 0 "register_operand" "r")
4361 (label_ref (match_operand 1 "" ""))))
4362 (clobber (match_scratch:DI 2 "=r"))]
4363 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
4364 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4365 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4367 { rtx best_label = 0;
4368 rtx jump_table_insn = next_active_insn (operands[1]);
4370 if (GET_CODE (jump_table_insn) == JUMP_INSN
4371 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4373 rtx jump_table = PATTERN (jump_table_insn);
4374 int n_labels = XVECLEN (jump_table, 1);
4375 int best_count = -1;
4378 for (i = 0; i < n_labels; i++)
4382 for (j = i + 1; j < n_labels; j++)
4383 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4384 == XEXP (XVECEXP (jump_table, 1, j), 0))
4387 if (count > best_count)
4388 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4394 operands[3] = best_label;
4395 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
4398 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
4400 [(set_attr "type" "ibr")
4401 (set_attr "length" "8")])
4405 (match_operand:DI 0 "register_operand" "r"))
4406 (use (label_ref (match_operand 1 "" "")))]
4407 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
4408 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4409 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4411 { rtx best_label = 0;
4412 rtx jump_table_insn = next_active_insn (operands[1]);
4414 if (GET_CODE (jump_table_insn) == JUMP_INSN
4415 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4417 rtx jump_table = PATTERN (jump_table_insn);
4418 int n_labels = XVECLEN (jump_table, 1);
4419 int best_count = -1;
4422 for (i = 0; i < n_labels; i++)
4426 for (j = i + 1; j < n_labels; j++)
4427 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4428 == XEXP (XVECEXP (jump_table, 1, j), 0))
4431 if (count > best_count)
4432 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4438 operands[2] = best_label;
4439 return \"jmp $31,(%0),%2\";
4442 return \"jmp $31,(%0),0\";
4444 [(set_attr "type" "ibr")])
4447 ;; op 0 is table offset
4448 ;; op 1 is table label
4453 (plus (match_operand:DI 0 "register_operand" "r")
4454 (label_ref (match_operand 1 "" ""))))]
4457 [(set_attr "type" "ibr")])
4459 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4460 ;; want to have to include pal.h in our .s file.
4462 ;; Technically the type for call_pal is jsr, but we use that for determining
4463 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4466 [(unspec_volatile [(const_int 0)] 0)]
4469 [(set_attr "type" "ibr")])
4471 ;; Finally, we have the basic data motion insns. The byte and word insns
4472 ;; are done via define_expand. Start with the floating-point insns, since
4473 ;; they are simpler.
4476 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4477 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4478 "TARGET_FPREGS && ! TARGET_FIX
4479 && (register_operand (operands[0], SFmode)
4480 || reg_or_fp0_operand (operands[1], SFmode))"
4488 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4491 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4492 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4493 "TARGET_FPREGS && TARGET_FIX
4494 && (register_operand (operands[0], SFmode)
4495 || reg_or_fp0_operand (operands[1], SFmode))"
4505 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4508 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4509 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4511 && (register_operand (operands[0], SFmode)
4512 || reg_or_fp0_operand (operands[1], SFmode))"
4517 [(set_attr "type" "ilog,ild,ist")])
4520 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4521 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4522 "TARGET_FPREGS && ! TARGET_FIX
4523 && (register_operand (operands[0], DFmode)
4524 || reg_or_fp0_operand (operands[1], DFmode))"
4532 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4535 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4536 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4537 "TARGET_FPREGS && TARGET_FIX
4538 && (register_operand (operands[0], DFmode)
4539 || reg_or_fp0_operand (operands[1], DFmode))"
4549 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4552 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4553 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4555 && (register_operand (operands[0], DFmode)
4556 || reg_or_fp0_operand (operands[1], DFmode))"
4561 [(set_attr "type" "ilog,ild,ist")])
4563 ;; Subregs suck for register allocation. Pretend we can move TFmode
4564 ;; data between general registers until after reload.
4566 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4567 (match_operand:TF 1 "input_operand" "roG,r"))]
4568 "register_operand (operands[0], TFmode)
4569 || reg_or_fp0_operand (operands[1], TFmode)"
4573 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4574 (match_operand:TF 1 "input_operand" ""))]
4576 [(set (match_dup 0) (match_dup 2))
4577 (set (match_dup 1) (match_dup 3))]
4580 alpha_split_tfmode_pair (operands);
4581 if (rtx_equal_p (operands[0], operands[3]))
4584 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4585 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4589 (define_expand "movsf"
4590 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4591 (match_operand:SF 1 "general_operand" ""))]
4595 if (GET_CODE (operands[0]) == MEM
4596 && ! reg_or_fp0_operand (operands[1], SFmode))
4597 operands[1] = force_reg (SFmode, operands[1]);
4600 (define_expand "movdf"
4601 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4602 (match_operand:DF 1 "general_operand" ""))]
4606 if (GET_CODE (operands[0]) == MEM
4607 && ! reg_or_fp0_operand (operands[1], DFmode))
4608 operands[1] = force_reg (DFmode, operands[1]);
4611 (define_expand "movtf"
4612 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4613 (match_operand:TF 1 "general_operand" ""))]
4617 if (GET_CODE (operands[0]) == MEM
4618 && ! reg_or_fp0_operand (operands[1], TFmode))
4619 operands[1] = force_reg (TFmode, operands[1]);
4623 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4624 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4625 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4626 && (register_operand (operands[0], SImode)
4627 || reg_or_0_operand (operands[1], SImode))"
4637 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4640 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4641 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4642 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4643 && (register_operand (operands[0], SImode)
4644 || reg_or_0_operand (operands[1], SImode))"
4656 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4659 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4660 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4661 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4662 && (register_operand (operands[0], SImode)
4663 || reg_or_0_operand (operands[1], SImode))"
4674 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4677 [(set (match_operand:HI 0 "register_operand" "=r,r")
4678 (match_operand:HI 1 "input_operand" "rJ,n"))]
4680 && (register_operand (operands[0], HImode)
4681 || register_operand (operands[1], HImode))"
4685 [(set_attr "type" "ilog,iadd")])
4688 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4689 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4691 && (register_operand (operands[0], HImode)
4692 || reg_or_0_operand (operands[1], HImode))"
4698 [(set_attr "type" "ilog,iadd,ild,ist")])
4701 [(set (match_operand:QI 0 "register_operand" "=r,r")
4702 (match_operand:QI 1 "input_operand" "rJ,n"))]
4704 && (register_operand (operands[0], QImode)
4705 || register_operand (operands[1], QImode))"
4709 [(set_attr "type" "ilog,iadd")])
4712 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4713 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4715 && (register_operand (operands[0], QImode)
4716 || reg_or_0_operand (operands[1], QImode))"
4722 [(set_attr "type" "ilog,iadd,ild,ist")])
4724 ;; We do two major things here: handle mem->mem and construct long
4727 (define_expand "movsi"
4728 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4729 (match_operand:SI 1 "general_operand" ""))]
4733 if (GET_CODE (operands[0]) == MEM
4734 && ! reg_or_0_operand (operands[1], SImode))
4735 operands[1] = force_reg (SImode, operands[1]);
4737 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4739 else if (GET_CODE (operands[1]) == CONST_INT)
4742 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4743 if (rtx_equal_p (operands[0], operands[1]))
4748 ;; Split a load of a large constant into the appropriate two-insn
4752 [(set (match_operand:SI 0 "register_operand" "")
4753 (match_operand:SI 1 "const_int_operand" ""))]
4754 "! add_operand (operands[1], SImode)"
4755 [(set (match_dup 0) (match_dup 2))
4756 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4759 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4761 if (tem == operands[0])
4768 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4769 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4771 && (register_operand (operands[0], DImode)
4772 || reg_or_0_operand (operands[1], DImode))"
4783 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4786 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4787 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4789 && (register_operand (operands[0], DImode)
4790 || reg_or_0_operand (operands[1], DImode))"
4803 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4805 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4806 ;; memory, and construct long 32-bit constants.
4808 (define_expand "movdi"
4809 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4810 (match_operand:DI 1 "general_operand" ""))]
4816 if (GET_CODE (operands[0]) == MEM
4817 && ! reg_or_0_operand (operands[1], DImode))
4818 operands[1] = force_reg (DImode, operands[1]);
4820 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4822 else if (GET_CODE (operands[1]) == CONST_INT
4823 && (tem = alpha_emit_set_const (operands[0], DImode,
4824 INTVAL (operands[1]), 3)) != 0)
4826 if (rtx_equal_p (tem, operands[0]))
4831 else if (CONSTANT_P (operands[1]))
4833 if (TARGET_BUILD_CONSTANTS)
4835 HOST_WIDE_INT i0, i1;
4837 if (GET_CODE (operands[1]) == CONST_INT)
4839 i0 = INTVAL (operands[1]);
4842 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4844 #if HOST_BITS_PER_WIDE_INT >= 64
4845 i0 = CONST_DOUBLE_LOW (operands[1]);
4848 i0 = CONST_DOUBLE_LOW (operands[1]);
4849 i1 = CONST_DOUBLE_HIGH (operands[1]);
4855 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4856 if (rtx_equal_p (tem, operands[0]))
4863 operands[1] = force_const_mem (DImode, operands[1]);
4864 if (reload_in_progress)
4866 emit_move_insn (operands[0], XEXP (operands[1], 0));
4867 operands[1] = copy_rtx (operands[1]);
4868 XEXP (operands[1], 0) = operands[0];
4871 operands[1] = validize_mem (operands[1]);
4878 ;; Split a load of a large constant into the appropriate two-insn
4882 [(set (match_operand:DI 0 "register_operand" "")
4883 (match_operand:DI 1 "const_int_operand" ""))]
4884 "! add_operand (operands[1], DImode)"
4885 [(set (match_dup 0) (match_dup 2))
4886 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4889 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4891 if (tem == operands[0])
4897 ;; These are the partial-word cases.
4899 ;; First we have the code to load an aligned word. Operand 0 is the register
4900 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4901 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4902 ;; number of bits within the word that the value is. Operand 3 is an SImode
4903 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4904 ;; same register. It is allowed to conflict with operand 1 as well.
4906 (define_expand "aligned_loadqi"
4907 [(set (match_operand:SI 3 "register_operand" "")
4908 (match_operand:SI 1 "memory_operand" ""))
4909 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4910 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4912 (match_operand:DI 2 "const_int_operand" "")))]
4917 (define_expand "aligned_loadhi"
4918 [(set (match_operand:SI 3 "register_operand" "")
4919 (match_operand:SI 1 "memory_operand" ""))
4920 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4921 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4923 (match_operand:DI 2 "const_int_operand" "")))]
4928 ;; Similar for unaligned loads, where we use the sequence from the
4929 ;; Alpha Architecture manual.
4931 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4932 ;; operand 3 can overlap the input and output registers.
4934 (define_expand "unaligned_loadqi"
4935 [(set (match_operand:DI 2 "register_operand" "")
4936 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4938 (set (match_operand:DI 3 "register_operand" "")
4940 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4941 (zero_extract:DI (match_dup 2)
4943 (ashift:DI (match_dup 3) (const_int 3))))]
4947 (define_expand "unaligned_loadhi"
4948 [(set (match_operand:DI 2 "register_operand" "")
4949 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4951 (set (match_operand:DI 3 "register_operand" "")
4953 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4954 (zero_extract:DI (match_dup 2)
4956 (ashift:DI (match_dup 3) (const_int 3))))]
4960 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4961 ;; aligned SImode MEM. Operand 1 is the register containing the
4962 ;; byte or word to store. Operand 2 is the number of bits within the word that
4963 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4965 (define_expand "aligned_store"
4966 [(set (match_operand:SI 3 "register_operand" "")
4967 (match_operand:SI 0 "memory_operand" ""))
4968 (set (subreg:DI (match_dup 3) 0)
4969 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4970 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4971 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4972 (match_operand:DI 2 "const_int_operand" "")))
4973 (set (subreg:DI (match_dup 4) 0)
4974 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4975 (set (match_dup 0) (match_dup 4))]
4978 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4979 << INTVAL (operands[2])));
4982 ;; For the unaligned byte and halfword cases, we use code similar to that
4983 ;; in the ;; Architecture book, but reordered to lower the number of registers
4984 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4985 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4986 ;; be the same temporary, if desired. If the address is in a register,
4987 ;; operand 2 can be that register.
4989 (define_expand "unaligned_storeqi"
4990 [(set (match_operand:DI 3 "register_operand" "")
4991 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4993 (set (match_operand:DI 2 "register_operand" "")
4996 (and:DI (not:DI (ashift:DI (const_int 255)
4997 (ashift:DI (match_dup 2) (const_int 3))))
4999 (set (match_operand:DI 4 "register_operand" "")
5000 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5001 (ashift:DI (match_dup 2) (const_int 3))))
5002 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5003 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5008 (define_expand "unaligned_storehi"
5009 [(set (match_operand:DI 3 "register_operand" "")
5010 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5012 (set (match_operand:DI 2 "register_operand" "")
5015 (and:DI (not:DI (ashift:DI (const_int 65535)
5016 (ashift:DI (match_dup 2) (const_int 3))))
5018 (set (match_operand:DI 4 "register_operand" "")
5019 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5020 (ashift:DI (match_dup 2) (const_int 3))))
5021 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5022 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5027 ;; Here are the define_expand's for QI and HI moves that use the above
5028 ;; patterns. We have the normal sets, plus the ones that need scratch
5029 ;; registers for reload.
5031 (define_expand "movqi"
5032 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5033 (match_operand:QI 1 "general_operand" ""))]
5039 if (GET_CODE (operands[0]) == MEM
5040 && ! reg_or_0_operand (operands[1], QImode))
5041 operands[1] = force_reg (QImode, operands[1]);
5043 if (GET_CODE (operands[1]) == CONST_INT
5044 && ! input_operand (operands[1], QImode))
5046 operands[1] = alpha_emit_set_const (operands[0], QImode,
5047 INTVAL (operands[1]), 3);
5049 if (rtx_equal_p (operands[0], operands[1]))
5056 /* If the output is not a register, the input must be. */
5057 if (GET_CODE (operands[0]) == MEM)
5058 operands[1] = force_reg (QImode, operands[1]);
5060 /* Handle four memory cases, unaligned and aligned for either the input
5061 or the output. The only case where we can be called during reload is
5062 for aligned loads; all other cases require temporaries. */
5064 if (GET_CODE (operands[1]) == MEM
5065 || (GET_CODE (operands[1]) == SUBREG
5066 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5067 || (reload_in_progress && GET_CODE (operands[1]) == REG
5068 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5069 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5070 && GET_CODE (SUBREG_REG (operands[1])) == REG
5071 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5073 if (aligned_memory_operand (operands[1], QImode))
5075 if (reload_in_progress)
5077 emit_insn (gen_reload_inqi_help
5078 (operands[0], operands[1],
5079 gen_rtx_REG (SImode, REGNO (operands[0]))));
5083 rtx aligned_mem, bitnum;
5084 rtx scratch = gen_reg_rtx (SImode);
5086 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5088 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5094 /* Don't pass these as parameters since that makes the generated
5095 code depend on parameter evaluation order which will cause
5096 bootstrap failures. */
5098 rtx temp1 = gen_reg_rtx (DImode);
5099 rtx temp2 = gen_reg_rtx (DImode);
5101 = gen_unaligned_loadqi (operands[0],
5102 get_unaligned_address (operands[1], 0),
5105 alpha_set_memflags (seq, operands[1]);
5112 else if (GET_CODE (operands[0]) == MEM
5113 || (GET_CODE (operands[0]) == SUBREG
5114 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5115 || (reload_in_progress && GET_CODE (operands[0]) == REG
5116 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5117 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5118 && GET_CODE (SUBREG_REG (operands[0])) == REG
5119 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5121 if (aligned_memory_operand (operands[0], QImode))
5123 rtx aligned_mem, bitnum;
5124 rtx temp1 = gen_reg_rtx (SImode);
5125 rtx temp2 = gen_reg_rtx (SImode);
5127 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5129 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5134 rtx temp1 = gen_reg_rtx (DImode);
5135 rtx temp2 = gen_reg_rtx (DImode);
5136 rtx temp3 = gen_reg_rtx (DImode);
5138 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
5139 operands[1], temp1, temp2, temp3);
5141 alpha_set_memflags (seq, operands[0]);
5149 (define_expand "movhi"
5150 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5151 (match_operand:HI 1 "general_operand" ""))]
5157 if (GET_CODE (operands[0]) == MEM
5158 && ! reg_or_0_operand (operands[1], HImode))
5159 operands[1] = force_reg (HImode, operands[1]);
5161 if (GET_CODE (operands[1]) == CONST_INT
5162 && ! input_operand (operands[1], HImode))
5164 operands[1] = alpha_emit_set_const (operands[0], HImode,
5165 INTVAL (operands[1]), 3);
5167 if (rtx_equal_p (operands[0], operands[1]))
5174 /* If the output is not a register, the input must be. */
5175 if (GET_CODE (operands[0]) == MEM)
5176 operands[1] = force_reg (HImode, operands[1]);
5178 /* Handle four memory cases, unaligned and aligned for either the input
5179 or the output. The only case where we can be called during reload is
5180 for aligned loads; all other cases require temporaries. */
5182 if (GET_CODE (operands[1]) == MEM
5183 || (GET_CODE (operands[1]) == SUBREG
5184 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5185 || (reload_in_progress && GET_CODE (operands[1]) == REG
5186 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5187 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5188 && GET_CODE (SUBREG_REG (operands[1])) == REG
5189 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5191 if (aligned_memory_operand (operands[1], HImode))
5193 if (reload_in_progress)
5195 emit_insn (gen_reload_inhi_help
5196 (operands[0], operands[1],
5197 gen_rtx_REG (SImode, REGNO (operands[0]))));
5201 rtx aligned_mem, bitnum;
5202 rtx scratch = gen_reg_rtx (SImode);
5204 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5206 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5212 /* Don't pass these as parameters since that makes the generated
5213 code depend on parameter evaluation order which will cause
5214 bootstrap failures. */
5216 rtx temp1 = gen_reg_rtx (DImode);
5217 rtx temp2 = gen_reg_rtx (DImode);
5219 = gen_unaligned_loadhi (operands[0],
5220 get_unaligned_address (operands[1], 0),
5223 alpha_set_memflags (seq, operands[1]);
5230 else if (GET_CODE (operands[0]) == MEM
5231 || (GET_CODE (operands[0]) == SUBREG
5232 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5233 || (reload_in_progress && GET_CODE (operands[0]) == REG
5234 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5235 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5236 && GET_CODE (SUBREG_REG (operands[0])) == REG
5237 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5239 if (aligned_memory_operand (operands[0], HImode))
5241 rtx aligned_mem, bitnum;
5242 rtx temp1 = gen_reg_rtx (SImode);
5243 rtx temp2 = gen_reg_rtx (SImode);
5245 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5247 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5252 rtx temp1 = gen_reg_rtx (DImode);
5253 rtx temp2 = gen_reg_rtx (DImode);
5254 rtx temp3 = gen_reg_rtx (DImode);
5256 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
5257 operands[1], temp1, temp2, temp3);
5259 alpha_set_memflags (seq, operands[0]);
5268 ;; Here are the versions for reload. Note that in the unaligned cases
5269 ;; we know that the operand must not be a pseudo-register because stack
5270 ;; slots are always aligned references.
5272 (define_expand "reload_inqi"
5273 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5274 (match_operand:QI 1 "any_memory_operand" "m")
5275 (match_operand:TI 2 "register_operand" "=&r")])]
5281 if (GET_CODE (operands[1]) != MEM)
5284 if (aligned_memory_operand (operands[1], QImode))
5286 seq = gen_reload_inqi_help (operands[0], operands[1],
5287 gen_rtx_REG (SImode, REGNO (operands[2])));
5293 /* It is possible that one of the registers we got for operands[2]
5294 might coincide with that of operands[0] (which is why we made
5295 it TImode). Pick the other one to use as our scratch. */
5296 if (REGNO (operands[0]) == REGNO (operands[2]))
5297 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5299 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5301 addr = get_unaligned_address (operands[1], 0);
5302 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5303 gen_rtx_REG (DImode, REGNO (operands[0])));
5304 alpha_set_memflags (seq, operands[1]);
5310 (define_expand "reload_inhi"
5311 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5312 (match_operand:HI 1 "any_memory_operand" "m")
5313 (match_operand:TI 2 "register_operand" "=&r")])]
5319 if (GET_CODE (operands[1]) != MEM)
5322 if (aligned_memory_operand (operands[1], HImode))
5324 seq = gen_reload_inhi_help (operands[0], operands[1],
5325 gen_rtx_REG (SImode, REGNO (operands[2])));
5331 /* It is possible that one of the registers we got for operands[2]
5332 might coincide with that of operands[0] (which is why we made
5333 it TImode). Pick the other one to use as our scratch. */
5334 if (REGNO (operands[0]) == REGNO (operands[2]))
5335 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5337 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5339 addr = get_unaligned_address (operands[1], 0);
5340 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5341 gen_rtx_REG (DImode, REGNO (operands[0])));
5342 alpha_set_memflags (seq, operands[1]);
5348 (define_expand "reload_outqi"
5349 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5350 (match_operand:QI 1 "register_operand" "r")
5351 (match_operand:TI 2 "register_operand" "=&r")])]
5355 if (GET_CODE (operands[0]) != MEM)
5358 if (aligned_memory_operand (operands[0], QImode))
5360 emit_insn (gen_reload_outqi_help
5361 (operands[0], operands[1],
5362 gen_rtx_REG (SImode, REGNO (operands[2])),
5363 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5367 rtx addr = get_unaligned_address (operands[0], 0);
5368 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5369 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5370 rtx scratch3 = scratch1;
5373 if (GET_CODE (addr) == REG)
5376 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5377 scratch2, scratch3);
5378 alpha_set_memflags (seq, operands[0]);
5384 (define_expand "reload_outhi"
5385 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5386 (match_operand:HI 1 "register_operand" "r")
5387 (match_operand:TI 2 "register_operand" "=&r")])]
5391 if (GET_CODE (operands[0]) != MEM)
5394 if (aligned_memory_operand (operands[0], HImode))
5396 emit_insn (gen_reload_outhi_help
5397 (operands[0], operands[1],
5398 gen_rtx_REG (SImode, REGNO (operands[2])),
5399 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5403 rtx addr = get_unaligned_address (operands[0], 0);
5404 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5405 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5406 rtx scratch3 = scratch1;
5409 if (GET_CODE (addr) == REG)
5412 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5413 scratch2, scratch3);
5414 alpha_set_memflags (seq, operands[0]);
5420 ;; Helpers for the above. The way reload is structured, we can't
5421 ;; always get a proper address for a stack slot during reload_foo
5422 ;; expansion, so we must delay our address manipulations until after.
5424 (define_insn "reload_inqi_help"
5425 [(set (match_operand:QI 0 "register_operand" "=r")
5426 (match_operand:QI 1 "memory_operand" "m"))
5427 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5428 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5431 (define_insn "reload_inhi_help"
5432 [(set (match_operand:HI 0 "register_operand" "=r")
5433 (match_operand:HI 1 "memory_operand" "m"))
5434 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5435 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5438 (define_insn "reload_outqi_help"
5439 [(set (match_operand:QI 0 "memory_operand" "=m")
5440 (match_operand:QI 1 "register_operand" "r"))
5441 (clobber (match_operand:SI 2 "register_operand" "=r"))
5442 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5443 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5446 (define_insn "reload_outhi_help"
5447 [(set (match_operand:HI 0 "memory_operand" "=m")
5448 (match_operand:HI 1 "register_operand" "r"))
5449 (clobber (match_operand:SI 2 "register_operand" "=r"))
5450 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5451 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5455 [(set (match_operand:QI 0 "register_operand" "")
5456 (match_operand:QI 1 "memory_operand" ""))
5457 (clobber (match_operand:SI 2 "register_operand" ""))]
5458 "! TARGET_BWX && reload_completed"
5462 rtx aligned_mem, bitnum;
5463 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5464 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5470 [(set (match_operand:HI 0 "register_operand" "")
5471 (match_operand:HI 1 "memory_operand" ""))
5472 (clobber (match_operand:SI 2 "register_operand" ""))]
5473 "! TARGET_BWX && reload_completed"
5477 rtx aligned_mem, bitnum;
5478 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5479 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5485 [(set (match_operand:QI 0 "memory_operand" "")
5486 (match_operand:QI 1 "register_operand" ""))
5487 (clobber (match_operand:SI 2 "register_operand" ""))
5488 (clobber (match_operand:SI 3 "register_operand" ""))]
5489 "! TARGET_BWX && reload_completed"
5493 rtx aligned_mem, bitnum;
5494 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5495 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5496 operands[2], operands[3]));
5501 [(set (match_operand:HI 0 "memory_operand" "")
5502 (match_operand:HI 1 "register_operand" ""))
5503 (clobber (match_operand:SI 2 "register_operand" ""))
5504 (clobber (match_operand:SI 3 "register_operand" ""))]
5505 "! TARGET_BWX && reload_completed"
5509 rtx aligned_mem, bitnum;
5510 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5511 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5512 operands[2], operands[3]));
5516 ;; Bit field extract patterns which use ext[wlq][lh]
5518 (define_expand "extv"
5519 [(set (match_operand:DI 0 "register_operand" "")
5520 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5521 (match_operand:DI 2 "immediate_operand" "")
5522 (match_operand:DI 3 "immediate_operand" "")))]
5526 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5527 if (INTVAL (operands[3]) % 8 != 0
5528 || (INTVAL (operands[2]) != 16
5529 && INTVAL (operands[2]) != 32
5530 && INTVAL (operands[2]) != 64))
5533 /* From mips.md: extract_bit_field doesn't verify that our source
5534 matches the predicate, so we force it to be a MEM here. */
5535 if (GET_CODE (operands[1]) != MEM)
5538 alpha_expand_unaligned_load (operands[0], operands[1],
5539 INTVAL (operands[2]) / 8,
5540 INTVAL (operands[3]) / 8, 1);
5544 (define_expand "extzv"
5545 [(set (match_operand:DI 0 "register_operand" "")
5546 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5547 (match_operand:DI 2 "immediate_operand" "")
5548 (match_operand:DI 3 "immediate_operand" "")))]
5552 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5553 if (INTVAL (operands[3]) % 8 != 0
5554 || (INTVAL (operands[2]) != 8
5555 && INTVAL (operands[2]) != 16
5556 && INTVAL (operands[2]) != 32
5557 && INTVAL (operands[2]) != 64))
5560 if (GET_CODE (operands[1]) == MEM)
5562 /* Fail 8 bit fields, falling back on a simple byte load. */
5563 if (INTVAL (operands[2]) == 8)
5566 alpha_expand_unaligned_load (operands[0], operands[1],
5567 INTVAL (operands[2]) / 8,
5568 INTVAL (operands[3]) / 8, 0);
5573 (define_expand "insv"
5574 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5575 (match_operand:DI 1 "immediate_operand" "")
5576 (match_operand:DI 2 "immediate_operand" ""))
5577 (match_operand:DI 3 "register_operand" ""))]
5581 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5582 if (INTVAL (operands[2]) % 8 != 0
5583 || (INTVAL (operands[1]) != 16
5584 && INTVAL (operands[1]) != 32
5585 && INTVAL (operands[1]) != 64))
5588 /* From mips.md: store_bit_field doesn't verify that our source
5589 matches the predicate, so we force it to be a MEM here. */
5590 if (GET_CODE (operands[0]) != MEM)
5593 alpha_expand_unaligned_store (operands[0], operands[3],
5594 INTVAL (operands[1]) / 8,
5595 INTVAL (operands[2]) / 8);
5601 ;; Block move/clear, see alpha.c for more details.
5602 ;; Argument 0 is the destination
5603 ;; Argument 1 is the source
5604 ;; Argument 2 is the length
5605 ;; Argument 3 is the alignment
5607 (define_expand "movstrqi"
5608 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5609 (match_operand:BLK 1 "memory_operand" ""))
5610 (use (match_operand:DI 2 "immediate_operand" ""))
5611 (use (match_operand:DI 3 "immediate_operand" ""))])]
5615 if (alpha_expand_block_move (operands))
5621 (define_expand "clrstrqi"
5622 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5624 (use (match_operand:DI 1 "immediate_operand" ""))
5625 (use (match_operand:DI 2 "immediate_operand" ""))])]
5629 if (alpha_expand_block_clear (operands))
5635 ;; Subroutine of stack space allocation. Perform a stack probe.
5636 (define_expand "probe_stack"
5637 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5641 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5642 INTVAL (operands[0])));
5643 MEM_VOLATILE_P (operands[1]) = 1;
5645 operands[0] = const0_rtx;
5648 ;; This is how we allocate stack space. If we are allocating a
5649 ;; constant amount of space and we know it is less than 4096
5650 ;; bytes, we need do nothing.
5652 ;; If it is more than 4096 bytes, we need to probe the stack
5654 (define_expand "allocate_stack"
5656 (plus:DI (reg:DI 30)
5657 (match_operand:DI 1 "reg_or_cint_operand" "")))
5658 (set (match_operand:DI 0 "register_operand" "=r")
5663 if (GET_CODE (operands[1]) == CONST_INT
5664 && INTVAL (operands[1]) < 32768)
5666 if (INTVAL (operands[1]) >= 4096)
5668 /* We do this the same way as in the prologue and generate explicit
5669 probes. Then we update the stack by the constant. */
5673 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5674 while (probed + 8192 < INTVAL (operands[1]))
5675 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5677 if (probed + 4096 < INTVAL (operands[1]))
5678 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5681 operands[1] = GEN_INT (- INTVAL (operands[1]));
5682 operands[2] = virtual_stack_dynamic_rtx;
5687 rtx loop_label = gen_label_rtx ();
5688 rtx want = gen_reg_rtx (Pmode);
5689 rtx tmp = gen_reg_rtx (Pmode);
5692 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5693 force_reg (Pmode, operands[1])));
5694 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5696 if (GET_CODE (operands[1]) != CONST_INT)
5698 out_label = gen_label_rtx ();
5699 emit_insn (gen_cmpdi (want, tmp));
5700 emit_jump_insn (gen_bgeu (out_label));
5703 emit_label (loop_label);
5704 memref = gen_rtx_MEM (DImode, tmp);
5705 MEM_VOLATILE_P (memref) = 1;
5706 emit_move_insn (memref, const0_rtx);
5707 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5708 emit_insn (gen_cmpdi (tmp, want));
5709 emit_jump_insn (gen_bgtu (loop_label));
5711 memref = gen_rtx_MEM (DImode, want);
5712 MEM_VOLATILE_P (memref) = 1;
5713 emit_move_insn (memref, const0_rtx);
5716 emit_label (out_label);
5718 emit_move_insn (stack_pointer_rtx, want);
5719 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5724 ;; This is used by alpha_expand_prolog to do the same thing as above,
5725 ;; except we cannot at that time generate new basic blocks, so we hide
5726 ;; the loop in this one insn.
5728 (define_insn "prologue_stack_probe_loop"
5729 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5730 (match_operand:DI 1 "register_operand" "r")] 5)]
5734 operands[2] = gen_label_rtx ();
5735 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5736 CODE_LABEL_NUMBER (operands[2]));
5738 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5740 [(set_attr "length" "16")
5741 (set_attr "type" "multi")])
5743 (define_expand "prologue"
5744 [(clobber (const_int 0))]
5748 alpha_expand_prologue ();
5752 ;; These take care of emitting the ldgp insn in the prologue. This will be
5753 ;; an lda/ldah pair and we want to align them properly. So we have two
5754 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
5755 ;; and the second of which emits nothing. However, both are marked as type
5756 ;; IADD (the default) so the alignment code in alpha.c does the right thing
5759 (define_expand "prologue_ldgp"
5760 [(unspec_volatile [(const_int 0)] 9)
5761 (unspec_volatile [(const_int 0)] 10)]
5765 (define_insn "*prologue_ldgp_1"
5766 [(unspec_volatile [(const_int 0)] 9)]
5767 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5768 "ldgp $29,0($27)\\n$%~..ng:")
5770 (define_insn "*prologue_ldgp_2"
5771 [(unspec_volatile [(const_int 0)] 10)]
5772 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5775 ;; The _mcount profiling hook has special calling conventions, and
5776 ;; does not clobber all the registers that a normal call would. So
5777 ;; hide the fact this is a call at all.
5779 (define_insn "prologue_mcount"
5780 [(unspec_volatile [(const_int 0)] 8)]
5782 "lda $28,_mcount\;jsr $28,($28),_mcount"
5783 [(set_attr "type" "multi")
5784 (set_attr "length" "8")])
5786 (define_insn "init_fp"
5787 [(set (match_operand:DI 0 "register_operand" "=r")
5788 (match_operand:DI 1 "register_operand" "r"))
5789 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5793 (define_expand "epilogue"
5798 alpha_expand_epilogue ();
5801 (define_expand "sibcall_epilogue"
5803 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
5806 alpha_expand_epilogue ();
5810 (define_expand "eh_epilogue"
5811 [(use (match_operand:DI 0 "register_operand" "r"))
5812 (use (match_operand:DI 1 "register_operand" "r"))
5813 (use (match_operand:DI 2 "register_operand" "r"))]
5817 cfun->machine->eh_epilogue_sp_ofs = operands[1];
5818 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5820 rtx ra = gen_rtx_REG (Pmode, 26);
5821 emit_move_insn (ra, operands[2]);
5826 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5827 ;; the frame size into a register. We use this pattern to ensure
5828 ;; we get lda instead of addq.
5829 (define_insn "nt_lda"
5830 [(set (match_operand:DI 0 "register_operand" "=r")
5831 (unspec:DI [(match_dup 0)
5832 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5836 (define_expand "builtin_longjmp"
5837 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5838 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5841 /* The elements of the buffer are, in order: */
5842 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5843 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5844 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5845 rtx pv = gen_rtx_REG (Pmode, 27);
5847 /* This bit is the same as expand_builtin_longjmp. */
5848 emit_move_insn (hard_frame_pointer_rtx, fp);
5849 emit_move_insn (pv, lab);
5850 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5851 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5852 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5854 /* Load the label we are jumping through into $27 so that we know
5855 where to look for it when we get back to setjmp's function for
5856 restoring the gp. */
5857 emit_indirect_jump (pv);
5861 (define_insn "builtin_setjmp_receiver"
5862 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5863 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5864 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5865 [(set_attr "length" "8")
5866 (set_attr "type" "multi")])
5869 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5870 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5871 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5872 [(set_attr "length" "12")
5873 (set_attr "type" "multi")])
5875 (define_insn "exception_receiver"
5876 [(unspec_volatile [(const_int 0)] 7)]
5877 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5878 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5879 [(set_attr "length" "12")
5880 (set_attr "type" "multi")])
5882 (define_expand "nonlocal_goto_receiver"
5883 [(unspec_volatile [(const_int 0)] 1)
5884 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5885 (unspec_volatile [(const_int 0)] 1)
5890 (define_insn "arg_home"
5891 [(unspec [(const_int 0)] 0)
5906 (clobber (mem:BLK (const_int 0)))
5907 (clobber (reg:DI 24))
5908 (clobber (reg:DI 25))
5909 (clobber (reg:DI 0))]
5911 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5912 [(set_attr "length" "16")
5913 (set_attr "type" "multi")])
5915 ;; Close the trap shadow of preceeding instructions. This is generated
5918 (define_insn "trapb"
5919 [(unspec_volatile [(const_int 0)] 4)]
5922 [(set_attr "type" "misc")])
5924 ;; No-op instructions used by machine-dependant reorg to preserve
5925 ;; alignment for instruction issue.
5931 [(set_attr "type" "ilog")])
5937 [(set_attr "type" "fcpys")])
5944 (define_insn "realign"
5945 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5947 ".align %0 #realign")
5949 ;; The call patterns are at the end of the file because their
5950 ;; wildcard operand0 interferes with nice recognition.
5952 (define_insn "*call_value_osf_1"
5953 [(set (match_operand 0 "" "")
5954 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5955 (match_operand 2 "" "")))
5956 (clobber (reg:DI 27))
5957 (clobber (reg:DI 26))]
5958 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5960 jsr $26,($27),0\;ldgp $29,0($26)
5962 jsr $26,%1\;ldgp $29,0($26)"
5963 [(set_attr "type" "jsr")
5964 (set_attr "length" "12,*,16")])
5966 (define_insn "*sibcall_value_osf_1"
5967 [(set (match_operand 0 "" "")
5968 (call (mem:DI (match_operand:DI 1 "call_operand" "R,i"))
5969 (match_operand 2 "" "")))]
5970 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5974 [(set_attr "type" "jsr")
5975 (set_attr "length" "*,8")])
5977 (define_insn "*call_value_nt_1"
5978 [(set (match_operand 0 "" "")
5979 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5980 (match_operand 2 "" "")))
5981 (clobber (reg:DI 26))]
5987 [(set_attr "type" "jsr")
5988 (set_attr "length" "*,*,12")])
5990 (define_insn "*call_value_vms_1"
5991 [(set (match_operand 0 "" "")
5992 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
5993 (match_operand 2 "" "")))
5994 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
5997 (clobber (reg:DI 27))]
6000 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6001 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6002 [(set_attr "type" "jsr")
6003 (set_attr "length" "12,16")])
6005 ;; Peepholes go at the end.
6007 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
6008 ;; reload when converting fp->int.
6011 [(set (match_operand:SI 0 "hard_int_register_operand" "")
6012 (match_operand:SI 1 "memory_operand" ""))
6013 (set (match_operand:DI 2 "hard_int_register_operand" "")
6014 (sign_extend:DI (match_dup 0)))]
6015 "true_regnum (operands[0]) == true_regnum (operands[2])
6016 || peep2_reg_dead_p (2, operands[0])"
6018 (sign_extend:DI (match_dup 1)))]
6022 [(set (match_operand:SI 0 "hard_int_register_operand" "")
6023 (match_operand:SI 1 "hard_fp_register_operand" ""))
6024 (set (match_operand:DI 2 "hard_int_register_operand" "")
6025 (sign_extend:DI (match_dup 0)))]
6027 && (true_regnum (operands[0]) == true_regnum (operands[2])
6028 || peep2_reg_dead_p (2, operands[0]))"
6030 (sign_extend:DI (match_dup 1)))]
6034 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
6035 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
6036 (set (match_operand:DI 2 "hard_int_register_operand" "")
6038 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
6040 (sign_extend:DI (match_dup 1)))]