1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
45 ;; Processor type -- this attribute must exactly match the processor_type
46 ;; enumeration in alpha.h.
48 (define_attr "cpu" "ev4,ev5,ev6"
49 (const (symbol_ref "alpha_cpu")))
51 ;; Define an insn type attribute. This is used in function unit delay
52 ;; computations, among other purposes. For the most part, we use the names
53 ;; defined in the EV4 documentation, but add a few that we have to know about
57 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
58 (const_string "iadd"))
60 ;; Describe a user's asm statement.
61 (define_asm_attributes
62 [(set_attr "type" "multi")])
64 ;; Define the operand size an insn operates on. Used primarily by mul
65 ;; and div operations that have size dependant timings.
67 (define_attr "opsize" "si,di,udi" (const_string "di"))
69 ;; The TRAP_TYPE attribute marks instructions that may generate traps
70 ;; (which are imprecise and may need a trapb if software completion
73 (define_attr "trap" "no,yes" (const_string "no"))
75 ;; The length of an instruction sequence in bytes.
77 (define_attr "length" "" (const_int 4))
79 ;; On EV4 there are two classes of resources to consider: resources needed
80 ;; to issue, and resources needed to execute. IBUS[01] are in the first
81 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
82 ;; (There are a few other register-like resources, but ...)
84 ; First, describe all of the issue constraints with single cycle delays.
85 ; All insns need a bus, but all except loads require one or the other.
86 (define_function_unit "ev4_ibus0" 1 0
87 (and (eq_attr "cpu" "ev4")
88 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
91 (define_function_unit "ev4_ibus1" 1 0
92 (and (eq_attr "cpu" "ev4")
93 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
96 ; Memory delivers its result in three cycles. Actually return one and
97 ; take care of this in adjust_cost, since we want to handle user-defined
99 (define_function_unit "ev4_abox" 1 0
100 (and (eq_attr "cpu" "ev4")
101 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
104 ; Branches have no delay cost, but do tie up the unit for two cycles.
105 (define_function_unit "ev4_bbox" 1 1
106 (and (eq_attr "cpu" "ev4")
107 (eq_attr "type" "ibr,fbr,jsr"))
110 ; Arithmetic insns are normally have their results available after
111 ; two cycles. There are a number of exceptions. They are encoded in
112 ; ADJUST_COST. Some of the other insns have similar exceptions.
113 (define_function_unit "ev4_ebox" 1 0
114 (and (eq_attr "cpu" "ev4")
115 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
118 (define_function_unit "imul" 1 0
119 (and (eq_attr "cpu" "ev4")
120 (and (eq_attr "type" "imul")
121 (eq_attr "opsize" "si")))
124 (define_function_unit "imul" 1 0
125 (and (eq_attr "cpu" "ev4")
126 (and (eq_attr "type" "imul")
127 (eq_attr "opsize" "!si")))
130 (define_function_unit "ev4_fbox" 1 0
131 (and (eq_attr "cpu" "ev4")
132 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
135 (define_function_unit "fdiv" 1 0
136 (and (eq_attr "cpu" "ev4")
137 (and (eq_attr "type" "fdiv")
138 (eq_attr "opsize" "si")))
141 (define_function_unit "fdiv" 1 0
142 (and (eq_attr "cpu" "ev4")
143 (and (eq_attr "type" "fdiv")
144 (eq_attr "opsize" "di")))
147 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
149 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
150 ;; with the combined resource EBOX.
152 (define_function_unit "ev5_ebox" 2 0
153 (and (eq_attr "cpu" "ev5")
154 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
157 ; Memory takes at least 2 clocks. Return one from here and fix up with
158 ; user-defined latencies in adjust_cost.
159 (define_function_unit "ev5_ebox" 2 0
160 (and (eq_attr "cpu" "ev5")
161 (eq_attr "type" "ild,fld,ldsym"))
164 ; Loads can dual issue with one another, but loads and stores do not mix.
165 (define_function_unit "ev5_e0" 1 0
166 (and (eq_attr "cpu" "ev5")
167 (eq_attr "type" "ild,fld,ldsym"))
169 [(eq_attr "type" "ist,fst")])
171 ; Stores, shifts, multiplies can only issue to E0
172 (define_function_unit "ev5_e0" 1 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "ist,fst,shift,imul"))
177 ; Motion video insns also issue only to E0, and take two ticks.
178 (define_function_unit "ev5_e0" 1 0
179 (and (eq_attr "cpu" "ev5")
180 (eq_attr "type" "mvi"))
183 ; Conditional moves always take 2 ticks.
184 (define_function_unit "ev5_ebox" 2 0
185 (and (eq_attr "cpu" "ev5")
186 (eq_attr "type" "icmov"))
189 ; Branches can only issue to E1
190 (define_function_unit "ev5_e1" 1 0
191 (and (eq_attr "cpu" "ev5")
192 (eq_attr "type" "ibr,jsr"))
195 ; Multiplies also use the integer multiplier.
196 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
197 ; cycles before an integer multiplication completes."
198 (define_function_unit "imul" 1 0
199 (and (eq_attr "cpu" "ev5")
200 (and (eq_attr "type" "imul")
201 (eq_attr "opsize" "si")))
204 (define_function_unit "imul" 1 0
205 (and (eq_attr "cpu" "ev5")
206 (and (eq_attr "type" "imul")
207 (eq_attr "opsize" "di")))
210 (define_function_unit "imul" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (and (eq_attr "type" "imul")
213 (eq_attr "opsize" "udi")))
216 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
217 ;; on either so we have to play the game again.
219 (define_function_unit "ev5_fbox" 2 0
220 (and (eq_attr "cpu" "ev5")
221 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
224 (define_function_unit "ev5_fm" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "fmul"))
229 ; Add and cmov as you would expect; fbr never produces a result;
230 ; fdiv issues through fa to the divider,
231 (define_function_unit "ev5_fa" 1 0
232 (and (eq_attr "cpu" "ev5")
233 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
236 ; ??? How to: "No instruction can be issued to pipe FA exactly five
237 ; cycles before a floating point divide completes."
238 (define_function_unit "fdiv" 1 0
239 (and (eq_attr "cpu" "ev5")
240 (and (eq_attr "type" "fdiv")
241 (eq_attr "opsize" "si")))
242 15 15) ; 15 to 31 data dependant
244 (define_function_unit "fdiv" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "fdiv")
247 (eq_attr "opsize" "di")))
248 22 22) ; 22 to 60 data dependant
250 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
252 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
253 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
255 ;; Conditional moves decompose into two independant primitives, each
256 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
258 (define_function_unit "ev6_ebox" 4 0
259 (and (eq_attr "cpu" "ev6")
260 (eq_attr "type" "icmov"))
263 (define_function_unit "ev6_ebox" 4 0
264 (and (eq_attr "cpu" "ev6")
265 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
268 ;; Integer loads take at least 3 clocks, and only issue to lower units.
269 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
270 (define_function_unit "ev6_l" 2 0
271 (and (eq_attr "cpu" "ev6")
272 (eq_attr "type" "ild,ldsym,ist,fst"))
275 ;; FP loads take at least 4 clocks. Return two from here...
276 (define_function_unit "ev6_l" 2 0
277 (and (eq_attr "cpu" "ev6")
278 (eq_attr "type" "fld"))
281 ;; Motion video insns also issue only to U0, and take three ticks.
282 (define_function_unit "ev6_u0" 1 0
283 (and (eq_attr "cpu" "ev6")
284 (eq_attr "type" "mvi"))
287 (define_function_unit "ev6_u" 2 0
288 (and (eq_attr "cpu" "ev6")
289 (eq_attr "type" "mvi"))
292 ;; Shifts issue to either upper pipe.
293 (define_function_unit "ev6_u" 2 0
294 (and (eq_attr "cpu" "ev6")
295 (eq_attr "type" "shift"))
298 ;; Multiplies issue only to U1, and all take 7 ticks.
299 ;; Rather than create a new function unit just for U1, reuse IMUL
300 (define_function_unit "imul" 1 0
301 (and (eq_attr "cpu" "ev6")
302 (eq_attr "type" "imul"))
305 (define_function_unit "ev6_u" 2 0
306 (and (eq_attr "cpu" "ev6")
307 (eq_attr "type" "imul"))
310 ;; Branches issue to either upper pipe
311 (define_function_unit "ev6_u" 2 0
312 (and (eq_attr "cpu" "ev6")
313 (eq_attr "type" "ibr"))
316 ;; Calls only issue to L0.
317 (define_function_unit "ev6_l0" 1 0
318 (and (eq_attr "cpu" "ev6")
319 (eq_attr "type" "jsr"))
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "jsr"))
327 ;; Ftoi/itof only issue to lower pipes
328 (define_function_unit "ev6_l" 2 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "ftoi"))
333 (define_function_unit "ev6_l" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "itof"))
338 ;; For the FPU we are very similar to EV5, except there's no insn that
339 ;; can issue to fm & fa, so we get to leave that out.
341 (define_function_unit "ev6_fm" 1 0
342 (and (eq_attr "cpu" "ev6")
343 (eq_attr "type" "fmul"))
346 (define_function_unit "ev6_fa" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
351 (define_function_unit "ev6_fa" 1 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "fcmov"))
356 (define_function_unit "fdiv" 1 0
357 (and (eq_attr "cpu" "ev6")
358 (and (eq_attr "type" "fdiv")
359 (eq_attr "opsize" "si")))
362 (define_function_unit "fdiv" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (and (eq_attr "type" "fdiv")
365 (eq_attr "opsize" "di")))
368 (define_function_unit "fsqrt" 1 0
369 (and (eq_attr "cpu" "ev6")
370 (and (eq_attr "type" "fsqrt")
371 (eq_attr "opsize" "si")))
374 (define_function_unit "fsqrt" 1 0
375 (and (eq_attr "cpu" "ev6")
376 (and (eq_attr "type" "fsqrt")
377 (eq_attr "opsize" "di")))
380 ; ??? The FPU communicates with memory and the integer register file
381 ; via two fp store units. We need a slot in the fst immediately, and
382 ; a slot in LOW after the operand data is ready. At which point the
383 ; data may be moved either to the store queue or the integer register
384 ; file and the insn retired.
387 ;; First define the arithmetic insns. Note that the 32-bit forms also
390 ;; Handle 32-64 bit extension from memory to a floating point register
391 ;; specially, since this ocurrs frequently in int->double conversions.
393 ;; Note that while we must retain the =f case in the insn for reload's
394 ;; benefit, it should be eliminated after reload, so we should never emit
395 ;; code for that case. But we don't reject the possibility.
397 (define_expand "extendsidi2"
398 [(set (match_operand:DI 0 "register_operand" "")
399 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
404 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
406 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
412 lds %0,%1\;cvtlq %0,%0"
413 [(set_attr "type" "iadd,ild,fadd,fld")
414 (set_attr "length" "*,*,*,8")])
417 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
419 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
426 lds %0,%1\;cvtlq %0,%0"
427 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
428 (set_attr "length" "*,*,*,*,8")])
430 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
432 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
433 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
435 [(set (match_dup 2) (match_dup 1))
436 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
437 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
439 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
440 ;; generates better code. We have the anonymous addsi3 pattern below in
441 ;; case combine wants to make it.
442 (define_expand "addsi3"
443 [(set (match_operand:SI 0 "register_operand" "")
444 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
445 (match_operand:SI 2 "add_operand" "")))]
451 rtx op1 = gen_lowpart (DImode, operands[1]);
452 rtx op2 = gen_lowpart (DImode, operands[2]);
454 if (! cse_not_expected)
456 rtx tmp = gen_reg_rtx (DImode);
457 emit_insn (gen_adddi3 (tmp, op1, op2));
458 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
461 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
467 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
468 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
469 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
478 [(set (match_operand:SI 0 "register_operand" "")
479 (plus:SI (match_operand:SI 1 "register_operand" "")
480 (match_operand:SI 2 "const_int_operand" "")))]
481 "! add_operand (operands[2], SImode)"
482 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
483 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
486 HOST_WIDE_INT val = INTVAL (operands[2]);
487 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
488 HOST_WIDE_INT rest = val - low;
490 operands[3] = GEN_INT (rest);
491 operands[4] = GEN_INT (low);
495 [(set (match_operand:DI 0 "register_operand" "=r,r")
497 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
498 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
505 [(set (match_operand:DI 0 "register_operand" "")
507 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
508 (match_operand:SI 2 "const_int_operand" ""))))
509 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
510 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
511 && INTVAL (operands[2]) % 4 == 0"
512 [(set (match_dup 3) (match_dup 4))
513 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
518 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
524 operands[4] = GEN_INT (val);
525 operands[5] = GEN_INT (mult);
529 [(set (match_operand:DI 0 "register_operand" "")
531 (plus:SI (match_operator:SI 1 "comparison_operator"
532 [(match_operand 2 "" "")
533 (match_operand 3 "" "")])
534 (match_operand:SI 4 "add_operand" ""))))
535 (clobber (match_operand:DI 5 "register_operand" ""))]
537 [(set (match_dup 5) (match_dup 6))
538 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
541 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
542 operands[2], operands[3]);
543 operands[7] = gen_lowpart (SImode, operands[5]);
546 (define_expand "adddi3"
547 [(set (match_operand:DI 0 "register_operand" "")
548 (plus:DI (match_operand:DI 1 "register_operand" "")
549 (match_operand:DI 2 "add_operand" "")))]
553 ;; This pattern exists so that register elimination tries to canonize
554 ;; (plus (plus reg c1) c2).
557 [(set (match_operand:DI 0 "register_operand" "=r")
558 (match_operand:DI 1 "addition_operation" "p"))]
562 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
563 ;; With complications like
565 ;; The NT stack unwind code can't handle a subq to adjust the stack
566 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
567 ;; the exception handling code will loop if a subq is used and an
570 ;; The 19980616 change to emit prologues as RTL also confused some
571 ;; versions of GDB, which also interprets prologues. This has been
572 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
575 ;; and the fact that the three insns schedule exactly the same, it's
576 ;; just not worth the effort.
578 (define_insn "*adddi_2"
579 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
580 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
581 (match_operand:DI 2 "add_operand" "r,K,L")))]
588 ;; ??? Allow large constants when basing off the frame pointer or some
589 ;; virtual register that may eliminate to the frame pointer. This is
590 ;; done because register elimination offsets will change the hi/lo split,
591 ;; and if we split before reload, we will require additional instructions.
594 [(set (match_operand:DI 0 "register_operand" "=r")
595 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
596 (match_operand:DI 2 "const_int_operand" "n")))]
597 "REG_OK_FP_BASE_P (operands[1])
598 && INTVAL (operands[2]) >= 0
599 /* This is the largest constant an lda+ldah pair can add, minus
600 an upper bound on the displacement between SP and AP during
601 register elimination. See INITIAL_ELIMINATION_OFFSET. */
602 && INTVAL (operands[2])
604 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
605 - ALPHA_ROUND(current_function_outgoing_args_size)
606 - (ALPHA_ROUND (get_frame_size ()
607 + max_reg_num () * UNITS_PER_WORD
608 + current_function_pretend_args_size)
609 - current_function_pretend_args_size))"
612 ;; Don't do this if we are adjusting SP since we don't want to do it
613 ;; in two steps. Don't split FP sources for the reason listed above.
615 [(set (match_operand:DI 0 "register_operand" "")
616 (plus:DI (match_operand:DI 1 "register_operand" "")
617 (match_operand:DI 2 "const_int_operand" "")))]
618 "! add_operand (operands[2], DImode)
619 && operands[0] != stack_pointer_rtx
620 && operands[1] != frame_pointer_rtx
621 && operands[1] != arg_pointer_rtx"
622 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
623 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
626 HOST_WIDE_INT val = INTVAL (operands[2]);
627 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
628 HOST_WIDE_INT rest = val - low;
630 operands[4] = GEN_INT (low);
631 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
632 operands[3] = GEN_INT (rest);
633 else if (! no_new_pseudos)
635 operands[3] = gen_reg_rtx (DImode);
636 emit_move_insn (operands[3], operands[2]);
637 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
645 [(set (match_operand:SI 0 "register_operand" "=r,r")
646 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
647 (match_operand:SI 2 "const48_operand" "I,I"))
648 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
655 [(set (match_operand:DI 0 "register_operand" "=r,r")
657 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
658 (match_operand:SI 2 "const48_operand" "I,I"))
659 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
666 [(set (match_operand:DI 0 "register_operand" "")
668 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
669 [(match_operand 2 "" "")
670 (match_operand 3 "" "")])
671 (match_operand:SI 4 "const48_operand" ""))
672 (match_operand:SI 5 "sext_add_operand" ""))))
673 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
675 [(set (match_dup 6) (match_dup 7))
677 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
681 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
682 operands[2], operands[3]);
683 operands[8] = gen_lowpart (SImode, operands[6]);
687 [(set (match_operand:DI 0 "register_operand" "=r,r")
688 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
689 (match_operand:DI 2 "const48_operand" "I,I"))
690 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
696 (define_insn "negsi2"
697 [(set (match_operand:SI 0 "register_operand" "=r")
698 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
703 [(set (match_operand:DI 0 "register_operand" "=r")
704 (sign_extend:DI (neg:SI
705 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
709 (define_insn "negdi2"
710 [(set (match_operand:DI 0 "register_operand" "=r")
711 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
715 (define_expand "subsi3"
716 [(set (match_operand:SI 0 "register_operand" "")
717 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
718 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
724 rtx op1 = gen_lowpart (DImode, operands[1]);
725 rtx op2 = gen_lowpart (DImode, operands[2]);
727 if (! cse_not_expected)
729 rtx tmp = gen_reg_rtx (DImode);
730 emit_insn (gen_subdi3 (tmp, op1, op2));
731 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
734 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
740 [(set (match_operand:SI 0 "register_operand" "=r")
741 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
742 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
747 [(set (match_operand:DI 0 "register_operand" "=r")
748 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
749 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
753 (define_insn "subdi3"
754 [(set (match_operand:DI 0 "register_operand" "=r")
755 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
756 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
761 [(set (match_operand:SI 0 "register_operand" "=r")
762 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
763 (match_operand:SI 2 "const48_operand" "I"))
764 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
769 [(set (match_operand:DI 0 "register_operand" "=r")
771 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
772 (match_operand:SI 2 "const48_operand" "I"))
773 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
778 [(set (match_operand:DI 0 "register_operand" "=r")
779 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
780 (match_operand:DI 2 "const48_operand" "I"))
781 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
785 (define_insn "mulsi3"
786 [(set (match_operand:SI 0 "register_operand" "=r")
787 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
788 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
791 [(set_attr "type" "imul")
792 (set_attr "opsize" "si")])
795 [(set (match_operand:DI 0 "register_operand" "=r")
797 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
798 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
801 [(set_attr "type" "imul")
802 (set_attr "opsize" "si")])
804 (define_insn "muldi3"
805 [(set (match_operand:DI 0 "register_operand" "=r")
806 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
807 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
810 [(set_attr "type" "imul")])
812 (define_insn "umuldi3_highpart"
813 [(set (match_operand:DI 0 "register_operand" "=r")
816 (mult:TI (zero_extend:TI
817 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
819 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
823 [(set_attr "type" "imul")
824 (set_attr "opsize" "udi")])
827 [(set (match_operand:DI 0 "register_operand" "=r")
830 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
831 (match_operand:TI 2 "cint8_operand" "I"))
835 [(set_attr "type" "imul")
836 (set_attr "opsize" "udi")])
838 ;; The divide and remainder operations always take their inputs from
839 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
841 ;; ??? Force sign-extension here because some versions of OSF/1 don't
842 ;; do the right thing if the inputs are not properly sign-extended.
843 ;; But Linux, for instance, does not have this problem. Is it worth
844 ;; the complication here to eliminate the sign extension?
845 ;; Interix/NT has the same sign-extension problem.
847 (define_expand "divsi3"
849 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
851 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
852 (parallel [(set (reg:DI 27)
853 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
854 (clobber (reg:DI 23))
855 (clobber (reg:DI 28))])
856 (set (match_operand:SI 0 "nonimmediate_operand" "")
857 (subreg:SI (reg:DI 27) 0))]
861 (define_expand "udivsi3"
863 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
865 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
866 (parallel [(set (reg:DI 27)
867 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
868 (clobber (reg:DI 23))
869 (clobber (reg:DI 28))])
870 (set (match_operand:SI 0 "nonimmediate_operand" "")
871 (subreg:SI (reg:DI 27) 0))]
875 (define_expand "modsi3"
877 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
879 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
880 (parallel [(set (reg:DI 27)
881 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
882 (clobber (reg:DI 23))
883 (clobber (reg:DI 28))])
884 (set (match_operand:SI 0 "nonimmediate_operand" "")
885 (subreg:SI (reg:DI 27) 0))]
889 (define_expand "umodsi3"
891 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
893 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
894 (parallel [(set (reg:DI 27)
895 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
896 (clobber (reg:DI 23))
897 (clobber (reg:DI 28))])
898 (set (match_operand:SI 0 "nonimmediate_operand" "")
899 (subreg:SI (reg:DI 27) 0))]
903 (define_expand "divdi3"
904 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
905 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
906 (parallel [(set (reg:DI 27)
909 (clobber (reg:DI 23))
910 (clobber (reg:DI 28))])
911 (set (match_operand:DI 0 "nonimmediate_operand" "")
916 (define_expand "udivdi3"
917 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
918 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
919 (parallel [(set (reg:DI 27)
922 (clobber (reg:DI 23))
923 (clobber (reg:DI 28))])
924 (set (match_operand:DI 0 "nonimmediate_operand" "")
929 (define_expand "moddi3"
930 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
931 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
932 (parallel [(set (reg:DI 27)
935 (clobber (reg:DI 23))
936 (clobber (reg:DI 28))])
937 (set (match_operand:DI 0 "nonimmediate_operand" "")
942 (define_expand "umoddi3"
943 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
944 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
945 (parallel [(set (reg:DI 27)
948 (clobber (reg:DI 23))
949 (clobber (reg:DI 28))])
950 (set (match_operand:DI 0 "nonimmediate_operand" "")
955 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
956 ;; expanded by the assembler.
959 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
960 [(reg:DI 24) (reg:DI 25)])))
961 (clobber (reg:DI 23))
962 (clobber (reg:DI 28))]
965 [(set_attr "type" "jsr")
966 (set_attr "length" "8")])
970 (match_operator:DI 1 "divmod_operator"
971 [(reg:DI 24) (reg:DI 25)]))
972 (clobber (reg:DI 23))
973 (clobber (reg:DI 28))]
976 [(set_attr "type" "jsr")
977 (set_attr "length" "8")])
979 ;; Next are the basic logical operations. These only exist in DImode.
981 (define_insn "anddi3"
982 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
983 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
984 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
990 [(set_attr "type" "ilog,ilog,shift")])
992 ;; There are times when we can split an AND into two AND insns. This occurs
993 ;; when we can first clear any bytes and then clear anything else. For
994 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
995 ;; Only do this when running on 64-bit host since the computations are
996 ;; too messy otherwise.
999 [(set (match_operand:DI 0 "register_operand" "")
1000 (and:DI (match_operand:DI 1 "register_operand" "")
1001 (match_operand:DI 2 "const_int_operand" "")))]
1002 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1003 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1004 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1007 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1008 unsigned HOST_WIDE_INT mask2 = mask1;
1011 /* For each byte that isn't all zeros, make it all ones. */
1012 for (i = 0; i < 64; i += 8)
1013 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1014 mask1 |= (HOST_WIDE_INT) 0xff << i;
1016 /* Now turn on any bits we've just turned off. */
1019 operands[3] = GEN_INT (mask1);
1020 operands[4] = GEN_INT (mask2);
1023 (define_insn "zero_extendqihi2"
1024 [(set (match_operand:HI 0 "register_operand" "=r")
1025 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1028 [(set_attr "type" "ilog")])
1031 [(set (match_operand:SI 0 "register_operand" "=r,r")
1032 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1037 [(set_attr "type" "ilog,ild")])
1040 [(set (match_operand:SI 0 "register_operand" "=r")
1041 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1044 [(set_attr "type" "ilog")])
1046 (define_expand "zero_extendqisi2"
1047 [(set (match_operand:SI 0 "register_operand" "")
1048 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1053 [(set (match_operand:DI 0 "register_operand" "=r,r")
1054 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1059 [(set_attr "type" "ilog,ild")])
1062 [(set (match_operand:DI 0 "register_operand" "=r")
1063 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1066 [(set_attr "type" "ilog")])
1068 (define_expand "zero_extendqidi2"
1069 [(set (match_operand:DI 0 "register_operand" "")
1070 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1075 [(set (match_operand:SI 0 "register_operand" "=r,r")
1076 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1081 [(set_attr "type" "shift,ild")])
1084 [(set (match_operand:SI 0 "register_operand" "=r")
1085 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1088 [(set_attr "type" "shift")])
1090 (define_expand "zero_extendhisi2"
1091 [(set (match_operand:SI 0 "register_operand" "")
1092 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1097 [(set (match_operand:DI 0 "register_operand" "=r,r")
1098 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1103 [(set_attr "type" "shift,ild")])
1106 [(set (match_operand:DI 0 "register_operand" "=r")
1107 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1110 [(set_attr "type" "shift")])
1112 (define_expand "zero_extendhidi2"
1113 [(set (match_operand:DI 0 "register_operand" "")
1114 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1118 (define_insn "zero_extendsidi2"
1119 [(set (match_operand:DI 0 "register_operand" "=r")
1120 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1123 [(set_attr "type" "shift")])
1126 [(set (match_operand:DI 0 "register_operand" "=r")
1127 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1128 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1131 [(set_attr "type" "ilog")])
1133 (define_insn "iordi3"
1134 [(set (match_operand:DI 0 "register_operand" "=r,r")
1135 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1136 (match_operand:DI 2 "or_operand" "rI,N")))]
1141 [(set_attr "type" "ilog")])
1143 (define_insn "one_cmpldi2"
1144 [(set (match_operand:DI 0 "register_operand" "=r")
1145 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1148 [(set_attr "type" "ilog")])
1151 [(set (match_operand:DI 0 "register_operand" "=r")
1152 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1153 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1156 [(set_attr "type" "ilog")])
1158 (define_insn "xordi3"
1159 [(set (match_operand:DI 0 "register_operand" "=r,r")
1160 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1161 (match_operand:DI 2 "or_operand" "rI,N")))]
1166 [(set_attr "type" "ilog")])
1169 [(set (match_operand:DI 0 "register_operand" "=r")
1170 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1171 (match_operand:DI 2 "register_operand" "rI"))))]
1174 [(set_attr "type" "ilog")])
1176 ;; Handle the FFS insn iff we support CIX.
1178 ;; These didn't make it into EV6 pass 2 as planned. Instead they
1179 ;; cropped cttz/ctlz/ctpop from the old CIX and renamed it FIX for
1180 ;; "Square Root and Floating Point Convert Extension".
1182 ;; I'm assured that these insns will make it into EV67 (first pass
1183 ;; due Summer 1999), presumably with a new AMASK bit, and presumably
1184 ;; will still be named CIX.
1186 (define_expand "ffsdi2"
1188 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1190 (plus:DI (match_dup 2) (const_int 1)))
1191 (set (match_operand:DI 0 "register_operand" "")
1192 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1193 (const_int 0) (match_dup 3)))]
1197 operands[2] = gen_reg_rtx (DImode);
1198 operands[3] = gen_reg_rtx (DImode);
1202 [(set (match_operand:DI 0 "register_operand" "=r")
1203 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1206 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1207 ; reuse the existing type name.
1208 [(set_attr "type" "mvi")])
1210 ;; Next come the shifts and the various extract and insert operations.
1212 (define_insn "ashldi3"
1213 [(set (match_operand:DI 0 "register_operand" "=r,r")
1214 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1215 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1219 switch (which_alternative)
1222 if (operands[2] == const1_rtx)
1223 return \"addq %r1,%r1,%0\";
1225 return \"s%P2addq %r1,0,%0\";
1227 return \"sll %r1,%2,%0\";
1232 [(set_attr "type" "iadd,shift")])
1234 ;; ??? The following pattern is made by combine, but earlier phases
1235 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1236 ;; with this in a better way at some point.
1238 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1240 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1241 ;; (match_operand:DI 2 "const_int_operand" "P"))
1243 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1246 ;; if (operands[2] == const1_rtx)
1247 ;; return \"addl %r1,%r1,%0\";
1249 ;; return \"s%P2addl %r1,0,%0\";
1251 ;; [(set_attr "type" "iadd")])
1253 (define_insn "lshrdi3"
1254 [(set (match_operand:DI 0 "register_operand" "=r")
1255 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1256 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1259 [(set_attr "type" "shift")])
1261 (define_insn "ashrdi3"
1262 [(set (match_operand:DI 0 "register_operand" "=r")
1263 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1264 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1267 [(set_attr "type" "shift")])
1269 (define_expand "extendqihi2"
1271 (ashift:DI (match_operand:QI 1 "some_operand" "")
1273 (set (match_operand:HI 0 "register_operand" "")
1274 (ashiftrt:DI (match_dup 2)
1281 emit_insn (gen_extendqihi2x (operands[0],
1282 force_reg (QImode, operands[1])));
1286 /* If we have an unaligned MEM, extend to DImode (which we do
1287 specially) and then copy to the result. */
1288 if (unaligned_memory_operand (operands[1], HImode))
1290 rtx temp = gen_reg_rtx (DImode);
1292 emit_insn (gen_extendqidi2 (temp, operands[1]));
1293 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1297 operands[0] = gen_lowpart (DImode, operands[0]);
1298 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1299 operands[2] = gen_reg_rtx (DImode);
1302 (define_insn "extendqidi2x"
1303 [(set (match_operand:DI 0 "register_operand" "=r")
1304 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1307 [(set_attr "type" "shift")])
1309 (define_insn "extendhidi2x"
1310 [(set (match_operand:DI 0 "register_operand" "=r")
1311 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1314 [(set_attr "type" "shift")])
1316 (define_insn "extendqisi2x"
1317 [(set (match_operand:SI 0 "register_operand" "=r")
1318 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1321 [(set_attr "type" "shift")])
1323 (define_insn "extendhisi2x"
1324 [(set (match_operand:SI 0 "register_operand" "=r")
1325 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1328 [(set_attr "type" "shift")])
1330 (define_insn "extendqihi2x"
1331 [(set (match_operand:HI 0 "register_operand" "=r")
1332 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1335 [(set_attr "type" "shift")])
1337 (define_expand "extendqisi2"
1339 (ashift:DI (match_operand:QI 1 "some_operand" "")
1341 (set (match_operand:SI 0 "register_operand" "")
1342 (ashiftrt:DI (match_dup 2)
1349 emit_insn (gen_extendqisi2x (operands[0],
1350 force_reg (QImode, operands[1])));
1354 /* If we have an unaligned MEM, extend to a DImode form of
1355 the result (which we do specially). */
1356 if (unaligned_memory_operand (operands[1], QImode))
1358 rtx temp = gen_reg_rtx (DImode);
1360 emit_insn (gen_extendqidi2 (temp, operands[1]));
1361 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1365 operands[0] = gen_lowpart (DImode, operands[0]);
1366 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1367 operands[2] = gen_reg_rtx (DImode);
1370 (define_expand "extendqidi2"
1372 (ashift:DI (match_operand:QI 1 "some_operand" "")
1374 (set (match_operand:DI 0 "register_operand" "")
1375 (ashiftrt:DI (match_dup 2)
1382 emit_insn (gen_extendqidi2x (operands[0],
1383 force_reg (QImode, operands[1])));
1387 if (unaligned_memory_operand (operands[1], QImode))
1390 = gen_unaligned_extendqidi (operands[0],
1391 get_unaligned_address (operands[1], 1));
1393 alpha_set_memflags (seq, operands[1]);
1398 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1399 operands[2] = gen_reg_rtx (DImode);
1402 (define_expand "extendhisi2"
1404 (ashift:DI (match_operand:HI 1 "some_operand" "")
1406 (set (match_operand:SI 0 "register_operand" "")
1407 (ashiftrt:DI (match_dup 2)
1414 emit_insn (gen_extendhisi2x (operands[0],
1415 force_reg (HImode, operands[1])));
1419 /* If we have an unaligned MEM, extend to a DImode form of
1420 the result (which we do specially). */
1421 if (unaligned_memory_operand (operands[1], HImode))
1423 rtx temp = gen_reg_rtx (DImode);
1425 emit_insn (gen_extendhidi2 (temp, operands[1]));
1426 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1430 operands[0] = gen_lowpart (DImode, operands[0]);
1431 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1432 operands[2] = gen_reg_rtx (DImode);
1435 (define_expand "extendhidi2"
1437 (ashift:DI (match_operand:HI 1 "some_operand" "")
1439 (set (match_operand:DI 0 "register_operand" "")
1440 (ashiftrt:DI (match_dup 2)
1447 emit_insn (gen_extendhidi2x (operands[0],
1448 force_reg (HImode, operands[1])));
1452 if (unaligned_memory_operand (operands[1], HImode))
1455 = gen_unaligned_extendhidi (operands[0],
1456 get_unaligned_address (operands[1], 2));
1458 alpha_set_memflags (seq, operands[1]);
1463 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1464 operands[2] = gen_reg_rtx (DImode);
1467 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1468 ;; as a pattern saves one instruction. The code is similar to that for
1469 ;; the unaligned loads (see below).
1471 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1472 (define_expand "unaligned_extendqidi"
1473 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1475 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1478 (ashift:DI (match_dup 3)
1479 (minus:DI (const_int 64)
1481 (and:DI (match_dup 2) (const_int 7))
1483 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1484 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1487 { operands[2] = gen_reg_rtx (DImode);
1488 operands[3] = gen_reg_rtx (DImode);
1489 operands[4] = gen_reg_rtx (DImode);
1492 (define_expand "unaligned_extendhidi"
1493 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1495 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1498 (ashift:DI (match_dup 3)
1499 (minus:DI (const_int 64)
1501 (and:DI (match_dup 2) (const_int 7))
1503 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1504 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1507 { operands[2] = gen_reg_rtx (DImode);
1508 operands[3] = gen_reg_rtx (DImode);
1509 operands[4] = gen_reg_rtx (DImode);
1513 [(set (match_operand:DI 0 "register_operand" "=r")
1514 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1515 (match_operand:DI 2 "mode_width_operand" "n")
1516 (match_operand:DI 3 "mul8_operand" "I")))]
1518 "ext%M2l %r1,%s3,%0"
1519 [(set_attr "type" "shift")])
1521 (define_insn "extxl"
1522 [(set (match_operand:DI 0 "register_operand" "=r")
1523 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1524 (match_operand:DI 2 "mode_width_operand" "n")
1525 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1529 [(set_attr "type" "shift")])
1531 ;; Combine has some strange notion of preserving existing undefined behaviour
1532 ;; in shifts larger than a word size. So capture these patterns that it
1533 ;; should have turned into zero_extracts.
1536 [(set (match_operand:DI 0 "register_operand" "=r")
1537 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1538 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1540 (match_operand:DI 3 "mode_mask_operand" "n")))]
1543 [(set_attr "type" "shift")])
1546 [(set (match_operand:DI 0 "register_operand" "=r")
1547 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1548 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1552 [(set_attr "type" "shift")])
1554 (define_insn "extqh"
1555 [(set (match_operand:DI 0 "register_operand" "=r")
1557 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1558 (minus:DI (const_int 64)
1561 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1566 [(set_attr "type" "shift")])
1568 (define_insn "extlh"
1569 [(set (match_operand:DI 0 "register_operand" "=r")
1571 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1572 (const_int 2147483647))
1573 (minus:DI (const_int 64)
1576 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1581 [(set_attr "type" "shift")])
1583 (define_insn "extwh"
1584 [(set (match_operand:DI 0 "register_operand" "=r")
1586 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1588 (minus:DI (const_int 64)
1591 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1596 [(set_attr "type" "shift")])
1598 ;; This converts an extXl into an extXh with an appropriate adjustment
1599 ;; to the address calculation.
1602 ;; [(set (match_operand:DI 0 "register_operand" "")
1603 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1604 ;; (match_operand:DI 2 "mode_width_operand" "")
1605 ;; (ashift:DI (match_operand:DI 3 "" "")
1607 ;; (match_operand:DI 4 "const_int_operand" "")))
1608 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1609 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1610 ;; [(set (match_dup 5) (match_dup 6))
1611 ;; (set (match_dup 0)
1612 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1613 ;; (ashift:DI (plus:DI (match_dup 5)
1619 ;; operands[6] = plus_constant (operands[3],
1620 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1621 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1625 [(set (match_operand:DI 0 "register_operand" "=r")
1626 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1627 (match_operand:DI 2 "mul8_operand" "I")))]
1630 [(set_attr "type" "shift")])
1633 [(set (match_operand:DI 0 "register_operand" "=r")
1634 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1635 (match_operand:DI 2 "mul8_operand" "I")))]
1638 [(set_attr "type" "shift")])
1641 [(set (match_operand:DI 0 "register_operand" "=r")
1642 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1643 (match_operand:DI 2 "mul8_operand" "I")))]
1646 [(set_attr "type" "shift")])
1648 (define_insn "insbl"
1649 [(set (match_operand:DI 0 "register_operand" "=r")
1650 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1651 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1655 [(set_attr "type" "shift")])
1657 (define_insn "inswl"
1658 [(set (match_operand:DI 0 "register_operand" "=r")
1659 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1660 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1664 [(set_attr "type" "shift")])
1666 (define_insn "insll"
1667 [(set (match_operand:DI 0 "register_operand" "=r")
1668 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1669 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1673 [(set_attr "type" "shift")])
1675 (define_insn "insql"
1676 [(set (match_operand:DI 0 "register_operand" "=r")
1677 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1678 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1682 [(set_attr "type" "shift")])
1684 ;; Combine has this sometimes habit of moving the and outside of the
1685 ;; shift, making life more interesting.
1688 [(set (match_operand:DI 0 "register_operand" "=r")
1689 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1690 (match_operand:DI 2 "mul8_operand" "I"))
1691 (match_operand:DI 3 "immediate_operand" "i")))]
1692 "HOST_BITS_PER_WIDE_INT == 64
1693 && GET_CODE (operands[3]) == CONST_INT
1694 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1695 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1696 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1697 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1698 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1699 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1702 #if HOST_BITS_PER_WIDE_INT == 64
1703 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1704 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1705 return \"insbl %1,%s2,%0\";
1706 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1707 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1708 return \"inswl %1,%s2,%0\";
1709 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1710 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1711 return \"insll %1,%s2,%0\";
1715 [(set_attr "type" "shift")])
1717 ;; We do not include the insXh insns because they are complex to express
1718 ;; and it does not appear that we would ever want to generate them.
1720 ;; Since we need them for block moves, though, cop out and use unspec.
1722 (define_insn "insxh"
1723 [(set (match_operand:DI 0 "register_operand" "=r")
1724 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1725 (match_operand:DI 2 "mode_width_operand" "n")
1726 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1729 [(set_attr "type" "shift")])
1731 (define_insn "mskxl"
1732 [(set (match_operand:DI 0 "register_operand" "=r")
1733 (and:DI (not:DI (ashift:DI
1734 (match_operand:DI 2 "mode_mask_operand" "n")
1736 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1738 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1741 [(set_attr "type" "shift")])
1743 ;; We do not include the mskXh insns because it does not appear we would
1744 ;; ever generate one.
1746 ;; Again, we do for block moves and we use unspec again.
1748 (define_insn "mskxh"
1749 [(set (match_operand:DI 0 "register_operand" "=r")
1750 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1751 (match_operand:DI 2 "mode_width_operand" "n")
1752 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1755 [(set_attr "type" "shift")])
1757 ;; Floating-point operations. All the double-precision insns can extend
1758 ;; from single, so indicate that. The exception are the ones that simply
1759 ;; play with the sign bits; it's not clear what to do there.
1761 (define_insn "abssf2"
1762 [(set (match_operand:SF 0 "register_operand" "=f")
1763 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1766 [(set_attr "type" "fcpys")])
1768 (define_insn "absdf2"
1769 [(set (match_operand:DF 0 "register_operand" "=f")
1770 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1773 [(set_attr "type" "fcpys")])
1775 (define_expand "abstf2"
1776 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1777 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1778 (use (match_dup 2))])]
1779 "TARGET_HAS_XFLOATING_LIBS"
1782 #if HOST_BITS_PER_WIDE_INT >= 64
1783 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1785 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1790 [(set (match_operand:TF 0 "register_operand" "=r")
1791 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1792 (use (match_operand:DI 2 "register_operand" "=r"))]
1793 "TARGET_HAS_XFLOATING_LIBS"
1797 [(set (match_operand:TF 0 "register_operand" "")
1798 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1799 (use (match_operand:DI 4 "register_operand" ""))]
1807 alpha_split_tfmode_pair (operands);
1810 if (rtx_equal_p (operands[0], operands[2]))
1812 else if (rtx_equal_p (operands[1], operands[2]))
1816 emit_move_insn (operands[0], operands[2]);
1818 tmp = gen_rtx_NOT (DImode, operands[4]);
1819 tmp = gen_rtx_AND (DImode, tmp, operands[3]);
1820 emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
1823 emit_move_insn (operands[0], operands[2]);
1827 (define_insn "negsf2"
1828 [(set (match_operand:SF 0 "register_operand" "=f")
1829 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1832 [(set_attr "type" "fadd")])
1834 (define_insn "negdf2"
1835 [(set (match_operand:DF 0 "register_operand" "=f")
1836 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1839 [(set_attr "type" "fadd")])
1841 (define_expand "negtf2"
1842 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1843 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1844 (use (match_dup 2))])]
1845 "TARGET_HAS_XFLOATING_LIBS"
1848 #if HOST_BITS_PER_WIDE_INT >= 64
1849 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1851 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1856 [(set (match_operand:TF 0 "register_operand" "=r")
1857 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1858 (use (match_operand:DI 2 "register_operand" "=r"))]
1859 "TARGET_HAS_XFLOATING_LIBS"
1863 [(set (match_operand:TF 0 "register_operand" "")
1864 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1865 (use (match_operand:DI 4 "register_operand" ""))]
1872 alpha_split_tfmode_pair (operands);
1875 if (rtx_equal_p (operands[0], operands[2]))
1877 else if (rtx_equal_p (operands[1], operands[2]))
1881 emit_move_insn (operands[0], operands[2]);
1883 emit_insn (gen_xordi3 (operands[1], operands[3], operands[4]));
1886 emit_move_insn (operands[0], operands[2]);
1891 [(set (match_operand:SF 0 "register_operand" "=&f")
1892 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1893 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1894 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1895 "add%,%)%& %R1,%R2,%0"
1896 [(set_attr "type" "fadd")
1897 (set_attr "trap" "yes")])
1899 (define_insn "addsf3"
1900 [(set (match_operand:SF 0 "register_operand" "=f")
1901 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1902 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1904 "add%,%)%& %R1,%R2,%0"
1905 [(set_attr "type" "fadd")
1906 (set_attr "trap" "yes")])
1909 [(set (match_operand:DF 0 "register_operand" "=&f")
1910 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1911 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1912 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1913 "add%-%)%& %R1,%R2,%0"
1914 [(set_attr "type" "fadd")
1915 (set_attr "trap" "yes")])
1917 (define_insn "adddf3"
1918 [(set (match_operand:DF 0 "register_operand" "=f")
1919 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1920 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1922 "add%-%)%& %R1,%R2,%0"
1923 [(set_attr "type" "fadd")
1924 (set_attr "trap" "yes")])
1927 [(set (match_operand:DF 0 "register_operand" "=f")
1928 (plus:DF (float_extend:DF
1929 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1930 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1931 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1932 "add%-%)%& %R1,%R2,%0"
1933 [(set_attr "type" "fadd")
1934 (set_attr "trap" "yes")])
1937 [(set (match_operand:DF 0 "register_operand" "=f")
1938 (plus:DF (float_extend:DF
1939 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1941 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1942 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1943 "add%-%)%& %R1,%R2,%0"
1944 [(set_attr "type" "fadd")
1945 (set_attr "trap" "yes")])
1947 (define_expand "addtf3"
1948 [(use (match_operand 0 "register_operand" ""))
1949 (use (match_operand 1 "general_operand" ""))
1950 (use (match_operand 2 "general_operand" ""))]
1951 "TARGET_HAS_XFLOATING_LIBS"
1952 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
1954 ;; Define conversion operators between DFmode and SImode, using the cvtql
1955 ;; instruction. To allow combine et al to do useful things, we keep the
1956 ;; operation as a unit until after reload, at which point we split the
1959 ;; Note that we (attempt to) only consider this optimization when the
1960 ;; ultimate destination is memory. If we will be doing further integer
1961 ;; processing, it is cheaper to do the truncation in the int regs.
1963 (define_insn "*cvtql"
1964 [(set (match_operand:SI 0 "register_operand" "=f")
1965 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1968 [(set_attr "type" "fadd")
1969 (set_attr "trap" "yes")])
1972 [(set (match_operand:SI 0 "memory_operand" "")
1973 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1974 (clobber (match_scratch:DI 2 ""))
1975 (clobber (match_scratch:SI 3 ""))]
1976 "TARGET_FP && reload_completed"
1977 [(set (match_dup 2) (fix:DI (match_dup 1)))
1978 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1979 (set (match_dup 0) (match_dup 3))]
1983 [(set (match_operand:SI 0 "memory_operand" "")
1984 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1985 (clobber (match_scratch:DI 2 ""))]
1986 "TARGET_FP && reload_completed"
1987 [(set (match_dup 2) (fix:DI (match_dup 1)))
1988 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1989 (set (match_dup 0) (match_dup 3))]
1990 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1991 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1994 [(set (match_operand:SI 0 "memory_operand" "=m")
1995 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1996 (clobber (match_scratch:DI 2 "=&f"))
1997 (clobber (match_scratch:SI 3 "=&f"))]
1998 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2000 [(set_attr "type" "fadd")
2001 (set_attr "trap" "yes")])
2004 [(set (match_operand:SI 0 "memory_operand" "=m")
2005 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2006 (clobber (match_scratch:DI 2 "=f"))]
2007 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2009 [(set_attr "type" "fadd")
2010 (set_attr "trap" "yes")])
2013 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2014 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2015 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2017 [(set_attr "type" "fadd")
2018 (set_attr "trap" "yes")])
2020 (define_insn "fix_truncdfdi2"
2021 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2022 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2025 [(set_attr "type" "fadd")
2026 (set_attr "trap" "yes")])
2028 ;; Likewise between SFmode and SImode.
2031 [(set (match_operand:SI 0 "memory_operand" "")
2032 (subreg:SI (fix:DI (float_extend:DF
2033 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2034 (clobber (match_scratch:DI 2 ""))
2035 (clobber (match_scratch:SI 3 ""))]
2036 "TARGET_FP && reload_completed"
2037 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2038 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2039 (set (match_dup 0) (match_dup 3))]
2043 [(set (match_operand:SI 0 "memory_operand" "")
2044 (subreg:SI (fix:DI (float_extend:DF
2045 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2046 (clobber (match_scratch:DI 2 ""))]
2047 "TARGET_FP && reload_completed"
2048 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2049 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2050 (set (match_dup 0) (match_dup 3))]
2051 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2052 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2055 [(set (match_operand:SI 0 "memory_operand" "=m")
2056 (subreg:SI (fix:DI (float_extend:DF
2057 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2058 (clobber (match_scratch:DI 2 "=&f"))
2059 (clobber (match_scratch:SI 3 "=&f"))]
2060 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2062 [(set_attr "type" "fadd")
2063 (set_attr "trap" "yes")])
2066 [(set (match_operand:SI 0 "memory_operand" "=m")
2067 (subreg:SI (fix:DI (float_extend:DF
2068 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2069 (clobber (match_scratch:DI 2 "=f"))]
2070 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2072 [(set_attr "type" "fadd")
2073 (set_attr "trap" "yes")])
2076 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2077 (fix:DI (float_extend:DF
2078 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2079 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2081 [(set_attr "type" "fadd")
2082 (set_attr "trap" "yes")])
2084 (define_insn "fix_truncsfdi2"
2085 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2086 (fix:DI (float_extend:DF
2087 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2090 [(set_attr "type" "fadd")
2091 (set_attr "trap" "yes")])
2093 (define_expand "fix_trunctfdi2"
2094 [(use (match_operand:DI 0 "register_operand" ""))
2095 (use (match_operand:TF 1 "general_operand" ""))]
2096 "TARGET_HAS_XFLOATING_LIBS"
2097 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2100 [(set (match_operand:SF 0 "register_operand" "=&f")
2101 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2102 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2104 [(set_attr "type" "fadd")
2105 (set_attr "trap" "yes")])
2107 (define_insn "floatdisf2"
2108 [(set (match_operand:SF 0 "register_operand" "=f")
2109 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2112 [(set_attr "type" "fadd")
2113 (set_attr "trap" "yes")])
2116 [(set (match_operand:DF 0 "register_operand" "=&f")
2117 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2118 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2120 [(set_attr "type" "fadd")
2121 (set_attr "trap" "yes")])
2123 (define_insn "floatdidf2"
2124 [(set (match_operand:DF 0 "register_operand" "=f")
2125 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2128 [(set_attr "type" "fadd")
2129 (set_attr "trap" "yes")])
2131 (define_expand "floatditf2"
2132 [(use (match_operand:TF 0 "register_operand" ""))
2133 (use (match_operand:DI 1 "general_operand" ""))]
2134 "TARGET_HAS_XFLOATING_LIBS"
2135 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2137 (define_expand "floatunsdisf2"
2138 [(use (match_operand:SF 0 "register_operand" ""))
2139 (use (match_operand:DI 1 "register_operand" ""))]
2141 "alpha_emit_floatuns (operands); DONE;")
2143 (define_expand "floatunsdidf2"
2144 [(use (match_operand:DF 0 "register_operand" ""))
2145 (use (match_operand:DI 1 "register_operand" ""))]
2147 "alpha_emit_floatuns (operands); DONE;")
2149 (define_expand "floatunsditf2"
2150 [(use (match_operand:TF 0 "register_operand" ""))
2151 (use (match_operand:DI 1 "general_operand" ""))]
2152 "TARGET_HAS_XFLOATING_LIBS"
2153 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2155 (define_expand "extendsfdf2"
2156 [(set (match_operand:DF 0 "register_operand" "")
2157 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2161 if (alpha_fptm >= ALPHA_FPTM_SU)
2162 operands[1] = force_reg (SFmode, operands[1]);
2166 [(set (match_operand:DF 0 "register_operand" "=&f")
2167 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2168 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2170 [(set_attr "type" "fadd")
2171 (set_attr "trap" "yes")])
2174 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2175 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2176 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2181 [(set_attr "type" "fcpys,fld,fst")])
2183 (define_expand "extendsftf2"
2184 [(use (match_operand:TF 0 "register_operand" ""))
2185 (use (match_operand:SF 1 "general_operand" ""))]
2186 "TARGET_HAS_XFLOATING_LIBS"
2189 rtx tmp = gen_reg_rtx (DFmode);
2190 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2191 emit_insn (gen_extenddftf2 (operands[0], tmp));
2195 (define_expand "extenddftf2"
2196 [(use (match_operand:TF 0 "register_operand" ""))
2197 (use (match_operand:DF 1 "general_operand" ""))]
2198 "TARGET_HAS_XFLOATING_LIBS"
2199 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2202 [(set (match_operand:SF 0 "register_operand" "=&f")
2203 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2204 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2205 "cvt%-%,%)%& %R1,%0"
2206 [(set_attr "type" "fadd")
2207 (set_attr "trap" "yes")])
2209 (define_insn "truncdfsf2"
2210 [(set (match_operand:SF 0 "register_operand" "=f")
2211 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2213 "cvt%-%,%)%& %R1,%0"
2214 [(set_attr "type" "fadd")
2215 (set_attr "trap" "yes")])
2217 (define_expand "trunctfdf2"
2218 [(use (match_operand:DF 0 "register_operand" ""))
2219 (use (match_operand:TF 1 "general_operand" ""))]
2220 "TARGET_HAS_XFLOATING_LIBS"
2221 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2223 (define_expand "trunctfsf2"
2224 [(use (match_operand:SF 0 "register_operand" ""))
2225 (use (match_operand:TF 1 "general_operand" ""))]
2226 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2229 rtx tmpf, sticky, arg, lo, hi;
2231 tmpf = gen_reg_rtx (DFmode);
2232 sticky = gen_reg_rtx (DImode);
2233 arg = copy_to_mode_reg (TFmode, operands[1]);
2234 lo = gen_lowpart (DImode, arg);
2235 hi = gen_highpart (DImode, arg);
2237 /* Convert the low word of the TFmode value into a sticky rounding bit,
2238 then or it into the low bit of the high word. This leaves the sticky
2239 bit at bit 48 of the fraction, which is representable in DFmode,
2240 which prevents rounding error in the final conversion to SFmode. */
2242 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2243 gen_rtx_NE (DImode, lo, const0_rtx)));
2244 emit_insn (gen_iordi3 (hi, hi, sticky));
2245 emit_insn (gen_trunctfdf2 (tmpf, arg));
2246 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2251 [(set (match_operand:SF 0 "register_operand" "=&f")
2252 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2253 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2254 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2255 "div%,%)%& %R1,%R2,%0"
2256 [(set_attr "type" "fdiv")
2257 (set_attr "opsize" "si")
2258 (set_attr "trap" "yes")])
2260 (define_insn "divsf3"
2261 [(set (match_operand:SF 0 "register_operand" "=f")
2262 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2263 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2265 "div%,%)%& %R1,%R2,%0"
2266 [(set_attr "type" "fdiv")
2267 (set_attr "opsize" "si")
2268 (set_attr "trap" "yes")])
2271 [(set (match_operand:DF 0 "register_operand" "=&f")
2272 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2273 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2274 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2275 "div%-%)%& %R1,%R2,%0"
2276 [(set_attr "type" "fdiv")
2277 (set_attr "trap" "yes")])
2279 (define_insn "divdf3"
2280 [(set (match_operand:DF 0 "register_operand" "=f")
2281 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2282 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2284 "div%-%)%& %R1,%R2,%0"
2285 [(set_attr "type" "fdiv")
2286 (set_attr "trap" "yes")])
2289 [(set (match_operand:DF 0 "register_operand" "=f")
2290 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2291 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2292 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2293 "div%-%)%& %R1,%R2,%0"
2294 [(set_attr "type" "fdiv")
2295 (set_attr "trap" "yes")])
2298 [(set (match_operand:DF 0 "register_operand" "=f")
2299 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2301 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2302 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2303 "div%-%)%& %R1,%R2,%0"
2304 [(set_attr "type" "fdiv")
2305 (set_attr "trap" "yes")])
2308 [(set (match_operand:DF 0 "register_operand" "=f")
2309 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2310 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2311 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2312 "div%-%)%& %R1,%R2,%0"
2313 [(set_attr "type" "fdiv")
2314 (set_attr "trap" "yes")])
2316 (define_expand "divtf3"
2317 [(use (match_operand 0 "register_operand" ""))
2318 (use (match_operand 1 "general_operand" ""))
2319 (use (match_operand 2 "general_operand" ""))]
2320 "TARGET_HAS_XFLOATING_LIBS"
2321 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2324 [(set (match_operand:SF 0 "register_operand" "=&f")
2325 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2326 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2327 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2328 "mul%,%)%& %R1,%R2,%0"
2329 [(set_attr "type" "fmul")
2330 (set_attr "trap" "yes")])
2332 (define_insn "mulsf3"
2333 [(set (match_operand:SF 0 "register_operand" "=f")
2334 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2335 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2337 "mul%,%)%& %R1,%R2,%0"
2338 [(set_attr "type" "fmul")
2339 (set_attr "trap" "yes")])
2342 [(set (match_operand:DF 0 "register_operand" "=&f")
2343 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2344 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2345 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2346 "mul%-%)%& %R1,%R2,%0"
2347 [(set_attr "type" "fmul")
2348 (set_attr "trap" "yes")])
2350 (define_insn "muldf3"
2351 [(set (match_operand:DF 0 "register_operand" "=f")
2352 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2353 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2355 "mul%-%)%& %R1,%R2,%0"
2356 [(set_attr "type" "fmul")
2357 (set_attr "trap" "yes")])
2360 [(set (match_operand:DF 0 "register_operand" "=f")
2361 (mult:DF (float_extend:DF
2362 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2363 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2364 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2365 "mul%-%)%& %R1,%R2,%0"
2366 [(set_attr "type" "fmul")
2367 (set_attr "trap" "yes")])
2370 [(set (match_operand:DF 0 "register_operand" "=f")
2371 (mult:DF (float_extend:DF
2372 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2374 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2375 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2376 "mul%-%)%& %R1,%R2,%0"
2377 [(set_attr "type" "fmul")
2378 (set_attr "trap" "yes")])
2380 (define_expand "multf3"
2381 [(use (match_operand 0 "register_operand" ""))
2382 (use (match_operand 1 "general_operand" ""))
2383 (use (match_operand 2 "general_operand" ""))]
2384 "TARGET_HAS_XFLOATING_LIBS"
2385 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2388 [(set (match_operand:SF 0 "register_operand" "=&f")
2389 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2390 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2391 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2392 "sub%,%)%& %R1,%R2,%0"
2393 [(set_attr "type" "fadd")
2394 (set_attr "trap" "yes")])
2396 (define_insn "subsf3"
2397 [(set (match_operand:SF 0 "register_operand" "=f")
2398 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2399 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2401 "sub%,%)%& %R1,%R2,%0"
2402 [(set_attr "type" "fadd")
2403 (set_attr "trap" "yes")])
2406 [(set (match_operand:DF 0 "register_operand" "=&f")
2407 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2408 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2409 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2410 "sub%-%)%& %R1,%R2,%0"
2411 [(set_attr "type" "fadd")
2412 (set_attr "trap" "yes")])
2414 (define_insn "subdf3"
2415 [(set (match_operand:DF 0 "register_operand" "=f")
2416 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2417 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2419 "sub%-%)%& %R1,%R2,%0"
2420 [(set_attr "type" "fadd")
2421 (set_attr "trap" "yes")])
2424 [(set (match_operand:DF 0 "register_operand" "=f")
2425 (minus:DF (float_extend:DF
2426 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2427 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2428 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2429 "sub%-%)%& %R1,%R2,%0"
2430 [(set_attr "type" "fadd")
2431 (set_attr "trap" "yes")])
2434 [(set (match_operand:DF 0 "register_operand" "=f")
2435 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2437 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2438 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2439 "sub%-%)%& %R1,%R2,%0"
2440 [(set_attr "type" "fadd")
2441 (set_attr "trap" "yes")])
2444 [(set (match_operand:DF 0 "register_operand" "=f")
2445 (minus:DF (float_extend:DF
2446 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2448 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2449 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2450 "sub%-%)%& %R1,%R2,%0"
2451 [(set_attr "type" "fadd")
2452 (set_attr "trap" "yes")])
2454 (define_expand "subtf3"
2455 [(use (match_operand 0 "register_operand" ""))
2456 (use (match_operand 1 "general_operand" ""))
2457 (use (match_operand 2 "general_operand" ""))]
2458 "TARGET_HAS_XFLOATING_LIBS"
2459 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2462 [(set (match_operand:SF 0 "register_operand" "=&f")
2463 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2464 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2466 [(set_attr "type" "fsqrt")
2467 (set_attr "opsize" "si")
2468 (set_attr "trap" "yes")])
2470 (define_insn "sqrtsf2"
2471 [(set (match_operand:SF 0 "register_operand" "=f")
2472 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2473 "TARGET_FP && TARGET_FIX"
2475 [(set_attr "type" "fsqrt")
2476 (set_attr "opsize" "si")
2477 (set_attr "trap" "yes")])
2480 [(set (match_operand:DF 0 "register_operand" "=&f")
2481 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2482 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2484 [(set_attr "type" "fsqrt")
2485 (set_attr "trap" "yes")])
2487 (define_insn "sqrtdf2"
2488 [(set (match_operand:DF 0 "register_operand" "=f")
2489 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2490 "TARGET_FP && TARGET_FIX"
2492 [(set_attr "type" "fsqrt")
2493 (set_attr "trap" "yes")])
2495 ;; Next are all the integer comparisons, and conditional moves and branches
2496 ;; and some of the related define_expand's and define_split's.
2498 (define_insn "*setne_internal"
2499 [(set (match_operand 0 "register_operand" "=r")
2500 (ne (match_operand:DI 1 "reg_or_8bit_operand" "rI")
2502 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2503 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2504 && GET_MODE (operands[0]) == GET_MODE (SET_SRC (PATTERN (insn)))"
2506 [(set_attr "type" "icmp")])
2508 (define_insn "*setcc_internal"
2509 [(set (match_operand 0 "register_operand" "=r")
2510 (match_operator 1 "alpha_comparison_operator"
2511 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2512 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2513 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2514 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2515 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2517 [(set_attr "type" "icmp")])
2519 (define_insn "*setcc_swapped_internal"
2520 [(set (match_operand 0 "register_operand" "=r")
2521 (match_operator 1 "alpha_swapped_comparison_operator"
2522 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2523 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2524 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2525 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2526 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2528 [(set_attr "type" "icmp")])
2530 ;; The mode folding trick can't be used with const_int operands, since
2531 ;; reload needs to know the proper mode.
2533 (define_insn "*movqicc_internal"
2534 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2536 (match_operator 2 "signed_comparison_operator"
2537 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2538 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2539 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2540 (match_operand:QI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2541 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2547 [(set_attr "type" "icmov")])
2549 (define_insn "*movhicc_internal"
2550 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2552 (match_operator 2 "signed_comparison_operator"
2553 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2554 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2555 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2556 (match_operand:HI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2557 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2563 [(set_attr "type" "icmov")])
2565 (define_insn "*movsicc_internal"
2566 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2568 (match_operator 2 "signed_comparison_operator"
2569 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2570 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2571 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2572 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2573 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2579 [(set_attr "type" "icmov")])
2581 (define_insn "*movdicc_internal"
2582 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2584 (match_operator 2 "signed_comparison_operator"
2585 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2586 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2587 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2588 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2589 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2595 [(set_attr "type" "icmov")])
2597 (define_insn "*movqicc_lbc"
2598 [(set (match_operand:QI 0 "register_operand" "=r,r")
2600 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2604 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2605 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2610 [(set_attr "type" "icmov")])
2612 (define_insn "*movhicc_lbc"
2613 [(set (match_operand:HI 0 "register_operand" "=r,r")
2615 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2619 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2620 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2625 [(set_attr "type" "icmov")])
2627 (define_insn "*movsicc_lbc"
2628 [(set (match_operand:SI 0 "register_operand" "=r,r")
2630 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2634 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2635 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2640 [(set_attr "type" "icmov")])
2642 (define_insn "*movdicc_lbc"
2643 [(set (match_operand:DI 0 "register_operand" "=r,r")
2645 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2649 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2650 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2655 [(set_attr "type" "icmov")])
2657 (define_insn "*movqicc_lbs"
2658 [(set (match_operand:QI 0 "register_operand" "=r,r")
2660 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2664 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2665 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2670 [(set_attr "type" "icmov")])
2672 (define_insn "*movhicc_lbs"
2673 [(set (match_operand:HI 0 "register_operand" "=r,r")
2675 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2679 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2680 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2685 [(set_attr "type" "icmov")])
2687 (define_insn "*movsicc_lbs"
2688 [(set (match_operand:SI 0 "register_operand" "=r,r")
2690 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2694 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2695 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2700 [(set_attr "type" "icmov")])
2702 (define_insn "*movdicc_lbs"
2703 [(set (match_operand:DI 0 "register_operand" "=r,r")
2705 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2709 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2710 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2715 [(set_attr "type" "icmov")])
2717 ;; For ABS, we have two choices, depending on whether the input and output
2718 ;; registers are the same or not.
2719 (define_expand "absdi2"
2720 [(set (match_operand:DI 0 "register_operand" "")
2721 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2724 { if (rtx_equal_p (operands[0], operands[1]))
2725 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2727 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2732 (define_expand "absdi2_same"
2733 [(set (match_operand:DI 1 "register_operand" "")
2734 (neg:DI (match_operand:DI 0 "register_operand" "")))
2736 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2742 (define_expand "absdi2_diff"
2743 [(set (match_operand:DI 0 "register_operand" "")
2744 (neg:DI (match_operand:DI 1 "register_operand" "")))
2746 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2753 [(set (match_operand:DI 0 "register_operand" "")
2754 (abs:DI (match_dup 0)))
2755 (clobber (match_operand:DI 2 "register_operand" ""))]
2757 [(set (match_dup 1) (neg:DI (match_dup 0)))
2758 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2759 (match_dup 0) (match_dup 1)))]
2763 [(set (match_operand:DI 0 "register_operand" "")
2764 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2765 "! rtx_equal_p (operands[0], operands[1])"
2766 [(set (match_dup 0) (neg:DI (match_dup 1)))
2767 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2768 (match_dup 0) (match_dup 1)))]
2772 [(set (match_operand:DI 0 "register_operand" "")
2773 (neg:DI (abs:DI (match_dup 0))))
2774 (clobber (match_operand:DI 2 "register_operand" ""))]
2776 [(set (match_dup 1) (neg:DI (match_dup 0)))
2777 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2778 (match_dup 0) (match_dup 1)))]
2782 [(set (match_operand:DI 0 "register_operand" "")
2783 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2784 "! rtx_equal_p (operands[0], operands[1])"
2785 [(set (match_dup 0) (neg:DI (match_dup 1)))
2786 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2787 (match_dup 0) (match_dup 1)))]
2790 (define_insn "sminqi3"
2791 [(set (match_operand:QI 0 "register_operand" "=r")
2792 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2793 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2796 [(set_attr "type" "mvi")])
2798 (define_insn "uminqi3"
2799 [(set (match_operand:QI 0 "register_operand" "=r")
2800 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2801 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2804 [(set_attr "type" "mvi")])
2806 (define_insn "smaxqi3"
2807 [(set (match_operand:QI 0 "register_operand" "=r")
2808 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2809 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2812 [(set_attr "type" "mvi")])
2814 (define_insn "umaxqi3"
2815 [(set (match_operand:QI 0 "register_operand" "=r")
2816 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2817 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2820 [(set_attr "type" "mvi")])
2822 (define_insn "sminhi3"
2823 [(set (match_operand:HI 0 "register_operand" "=r")
2824 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2825 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2828 [(set_attr "type" "mvi")])
2830 (define_insn "uminhi3"
2831 [(set (match_operand:HI 0 "register_operand" "=r")
2832 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2833 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2836 [(set_attr "type" "mvi")])
2838 (define_insn "smaxhi3"
2839 [(set (match_operand:HI 0 "register_operand" "=r")
2840 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2841 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2844 [(set_attr "type" "mvi")])
2846 (define_insn "umaxhi3"
2847 [(set (match_operand:HI 0 "register_operand" "=r")
2848 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2849 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2852 [(set_attr "type" "shift")])
2854 (define_expand "smaxdi3"
2856 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2857 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2858 (set (match_operand:DI 0 "register_operand" "")
2859 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2860 (match_dup 1) (match_dup 2)))]
2863 { operands[3] = gen_reg_rtx (DImode);
2867 [(set (match_operand:DI 0 "register_operand" "")
2868 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2869 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2870 (clobber (match_operand:DI 3 "register_operand" ""))]
2871 "operands[2] != const0_rtx"
2872 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2873 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2874 (match_dup 1) (match_dup 2)))]
2878 [(set (match_operand:DI 0 "register_operand" "=r")
2879 (smax:DI (match_operand:DI 1 "register_operand" "0")
2883 [(set_attr "type" "icmov")])
2885 (define_expand "smindi3"
2887 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2888 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2889 (set (match_operand:DI 0 "register_operand" "")
2890 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2891 (match_dup 1) (match_dup 2)))]
2894 { operands[3] = gen_reg_rtx (DImode);
2898 [(set (match_operand:DI 0 "register_operand" "")
2899 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2900 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2901 (clobber (match_operand:DI 3 "register_operand" ""))]
2902 "operands[2] != const0_rtx"
2903 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2904 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2905 (match_dup 1) (match_dup 2)))]
2909 [(set (match_operand:DI 0 "register_operand" "=r")
2910 (smin:DI (match_operand:DI 1 "register_operand" "0")
2914 [(set_attr "type" "icmov")])
2916 (define_expand "umaxdi3"
2918 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2919 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2920 (set (match_operand:DI 0 "register_operand" "")
2921 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2922 (match_dup 1) (match_dup 2)))]
2925 { operands[3] = gen_reg_rtx (DImode);
2929 [(set (match_operand:DI 0 "register_operand" "")
2930 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2931 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2932 (clobber (match_operand:DI 3 "register_operand" ""))]
2933 "operands[2] != const0_rtx"
2934 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2935 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2936 (match_dup 1) (match_dup 2)))]
2939 (define_expand "umindi3"
2941 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2942 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2943 (set (match_operand:DI 0 "register_operand" "")
2944 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2945 (match_dup 1) (match_dup 2)))]
2948 { operands[3] = gen_reg_rtx (DImode);
2952 [(set (match_operand:DI 0 "register_operand" "")
2953 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2954 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2955 (clobber (match_operand:DI 3 "register_operand" ""))]
2956 "operands[2] != const0_rtx"
2957 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2958 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2959 (match_dup 1) (match_dup 2)))]
2965 (match_operator 1 "signed_comparison_operator"
2966 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2968 (label_ref (match_operand 0 "" ""))
2972 [(set_attr "type" "ibr")])
2977 (match_operator 1 "signed_comparison_operator"
2979 (match_operand:DI 2 "register_operand" "r")])
2980 (label_ref (match_operand 0 "" ""))
2984 [(set_attr "type" "ibr")])
2989 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2993 (label_ref (match_operand 0 "" ""))
2997 [(set_attr "type" "ibr")])
3002 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3006 (label_ref (match_operand 0 "" ""))
3010 [(set_attr "type" "ibr")])
3016 (match_operator 1 "comparison_operator"
3017 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3019 (match_operand:DI 3 "const_int_operand" ""))
3021 (label_ref (match_operand 0 "" ""))
3023 (clobber (match_operand:DI 4 "register_operand" ""))])]
3024 "INTVAL (operands[3]) != 0"
3026 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3028 (if_then_else (match_op_dup 1
3029 [(zero_extract:DI (match_dup 4)
3033 (label_ref (match_dup 0))
3037 ;; The following are the corresponding floating-point insns. Recall
3038 ;; we need to have variants that expand the arguments from SFmode
3041 (define_insn "*cmpdf_tp"
3042 [(set (match_operand:DF 0 "register_operand" "=&f")
3043 (match_operator:DF 1 "alpha_fp_comparison_operator"
3044 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3045 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3046 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3047 "cmp%-%C1%' %R2,%R3,%0"
3048 [(set_attr "type" "fadd")
3049 (set_attr "trap" "yes")])
3051 (define_insn "*cmpdf_no_tp"
3052 [(set (match_operand:DF 0 "register_operand" "=f")
3053 (match_operator:DF 1 "alpha_fp_comparison_operator"
3054 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3055 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3056 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3057 "cmp%-%C1%' %R2,%R3,%0"
3058 [(set_attr "type" "fadd")
3059 (set_attr "trap" "yes")])
3062 [(set (match_operand:DF 0 "register_operand" "=&f")
3063 (match_operator:DF 1 "alpha_fp_comparison_operator"
3065 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3066 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3067 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3068 "cmp%-%C1%' %R2,%R3,%0"
3069 [(set_attr "type" "fadd")
3070 (set_attr "trap" "yes")])
3073 [(set (match_operand:DF 0 "register_operand" "=f")
3074 (match_operator:DF 1 "alpha_fp_comparison_operator"
3076 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3077 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3078 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3079 "cmp%-%C1%' %R2,%R3,%0"
3080 [(set_attr "type" "fadd")
3081 (set_attr "trap" "yes")])
3084 [(set (match_operand:DF 0 "register_operand" "=&f")
3085 (match_operator:DF 1 "alpha_fp_comparison_operator"
3086 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3088 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3089 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3090 "cmp%-%C1%' %R2,%R3,%0"
3091 [(set_attr "type" "fadd")
3092 (set_attr "trap" "yes")])
3095 [(set (match_operand:DF 0 "register_operand" "=f")
3096 (match_operator:DF 1 "alpha_fp_comparison_operator"
3097 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3099 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3100 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3101 "cmp%-%C1%' %R2,%R3,%0"
3102 [(set_attr "type" "fadd")
3103 (set_attr "trap" "yes")])
3106 [(set (match_operand:DF 0 "register_operand" "=&f")
3107 (match_operator:DF 1 "alpha_fp_comparison_operator"
3109 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3111 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3112 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3113 "cmp%-%C1%' %R2,%R3,%0"
3114 [(set_attr "type" "fadd")
3115 (set_attr "trap" "yes")])
3118 [(set (match_operand:DF 0 "register_operand" "=f")
3119 (match_operator:DF 1 "alpha_fp_comparison_operator"
3121 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3123 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3124 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3125 "cmp%-%C1%' %R2,%R3,%0"
3126 [(set_attr "type" "fadd")
3127 (set_attr "trap" "yes")])
3130 [(set (match_operand:DF 0 "register_operand" "=f,f")
3132 (match_operator 3 "signed_comparison_operator"
3133 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3134 (match_operand:DF 2 "fp0_operand" "G,G")])
3135 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3136 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3140 fcmov%D3 %R4,%R5,%0"
3141 [(set_attr "type" "fcmov")])
3144 [(set (match_operand:SF 0 "register_operand" "=f,f")
3146 (match_operator 3 "signed_comparison_operator"
3147 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3148 (match_operand:DF 2 "fp0_operand" "G,G")])
3149 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3150 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3154 fcmov%D3 %R4,%R5,%0"
3155 [(set_attr "type" "fcmov")])
3158 [(set (match_operand:DF 0 "register_operand" "=f,f")
3160 (match_operator 3 "signed_comparison_operator"
3161 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3162 (match_operand:DF 2 "fp0_operand" "G,G")])
3163 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3164 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3168 fcmov%D3 %R4,%R5,%0"
3169 [(set_attr "type" "fcmov")])
3172 [(set (match_operand:DF 0 "register_operand" "=f,f")
3174 (match_operator 3 "signed_comparison_operator"
3176 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3177 (match_operand:DF 2 "fp0_operand" "G,G")])
3178 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3179 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3183 fcmov%D3 %R4,%R5,%0"
3184 [(set_attr "type" "fcmov")])
3187 [(set (match_operand:SF 0 "register_operand" "=f,f")
3189 (match_operator 3 "signed_comparison_operator"
3191 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3192 (match_operand:DF 2 "fp0_operand" "G,G")])
3193 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3194 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3198 fcmov%D3 %R4,%R5,%0"
3199 [(set_attr "type" "fcmov")])
3202 [(set (match_operand:DF 0 "register_operand" "=f,f")
3204 (match_operator 3 "signed_comparison_operator"
3206 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3207 (match_operand:DF 2 "fp0_operand" "G,G")])
3208 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3209 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3213 fcmov%D3 %R4,%R5,%0"
3214 [(set_attr "type" "fcmov")])
3216 (define_expand "maxdf3"
3218 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3219 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3220 (set (match_operand:DF 0 "register_operand" "")
3221 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3222 (match_dup 1) (match_dup 2)))]
3225 { operands[3] = gen_reg_rtx (DFmode);
3226 operands[4] = CONST0_RTX (DFmode);
3229 (define_expand "mindf3"
3231 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3232 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3233 (set (match_operand:DF 0 "register_operand" "")
3234 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3235 (match_dup 1) (match_dup 2)))]
3238 { operands[3] = gen_reg_rtx (DFmode);
3239 operands[4] = CONST0_RTX (DFmode);
3242 (define_expand "maxsf3"
3244 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3245 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3246 (set (match_operand:SF 0 "register_operand" "")
3247 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3248 (match_dup 1) (match_dup 2)))]
3251 { operands[3] = gen_reg_rtx (DFmode);
3252 operands[4] = CONST0_RTX (DFmode);
3255 (define_expand "minsf3"
3257 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3258 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3259 (set (match_operand:SF 0 "register_operand" "")
3260 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3261 (match_dup 1) (match_dup 2)))]
3264 { operands[3] = gen_reg_rtx (DFmode);
3265 operands[4] = CONST0_RTX (DFmode);
3271 (match_operator 1 "signed_comparison_operator"
3272 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3273 (match_operand:DF 3 "fp0_operand" "G")])
3274 (label_ref (match_operand 0 "" ""))
3278 [(set_attr "type" "fbr")])
3283 (match_operator 1 "signed_comparison_operator"
3285 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3286 (match_operand:DF 3 "fp0_operand" "G")])
3287 (label_ref (match_operand 0 "" ""))
3291 [(set_attr "type" "fbr")])
3293 ;; These are the main define_expand's used to make conditional branches
3296 (define_expand "cmpdf"
3297 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3298 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3302 alpha_compare.op0 = operands[0];
3303 alpha_compare.op1 = operands[1];
3304 alpha_compare.fp_p = 1;
3308 (define_expand "cmptf"
3309 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3310 (match_operand:TF 1 "general_operand" "")))]
3311 "TARGET_HAS_XFLOATING_LIBS"
3314 alpha_compare.op0 = operands[0];
3315 alpha_compare.op1 = operands[1];
3316 alpha_compare.fp_p = 1;
3320 (define_expand "cmpdi"
3321 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3322 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3326 alpha_compare.op0 = operands[0];
3327 alpha_compare.op1 = operands[1];
3328 alpha_compare.fp_p = 0;
3332 (define_expand "beq"
3334 (if_then_else (match_dup 1)
3335 (label_ref (match_operand 0 "" ""))
3338 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3340 (define_expand "bne"
3342 (if_then_else (match_dup 1)
3343 (label_ref (match_operand 0 "" ""))
3346 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3348 (define_expand "blt"
3350 (if_then_else (match_dup 1)
3351 (label_ref (match_operand 0 "" ""))
3354 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3356 (define_expand "ble"
3358 (if_then_else (match_dup 1)
3359 (label_ref (match_operand 0 "" ""))
3362 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3364 (define_expand "bgt"
3366 (if_then_else (match_dup 1)
3367 (label_ref (match_operand 0 "" ""))
3370 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3372 (define_expand "bge"
3374 (if_then_else (match_dup 1)
3375 (label_ref (match_operand 0 "" ""))
3378 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3380 (define_expand "bltu"
3382 (if_then_else (match_dup 1)
3383 (label_ref (match_operand 0 "" ""))
3386 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3388 (define_expand "bleu"
3390 (if_then_else (match_dup 1)
3391 (label_ref (match_operand 0 "" ""))
3394 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3396 (define_expand "bgtu"
3398 (if_then_else (match_dup 1)
3399 (label_ref (match_operand 0 "" ""))
3402 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3404 (define_expand "bgeu"
3406 (if_then_else (match_dup 1)
3407 (label_ref (match_operand 0 "" ""))
3410 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3412 (define_expand "bunordered"
3414 (if_then_else (match_dup 1)
3415 (label_ref (match_operand 0 "" ""))
3418 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3420 (define_expand "bordered"
3422 (if_then_else (match_dup 1)
3423 (label_ref (match_operand 0 "" ""))
3426 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3428 (define_expand "seq"
3429 [(set (match_operand:DI 0 "register_operand" "")
3434 if (alpha_compare.fp_p)
3437 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3438 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3441 (define_expand "sne"
3442 [(set (match_operand:DI 0 "register_operand" "")
3444 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3448 if (alpha_compare.fp_p)
3451 if (alpha_compare.op1 == const0_rtx)
3453 operands[1] = gen_rtx_NE (DImode, alpha_compare.op0, alpha_compare.op1);
3454 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3455 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3459 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3460 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3463 (define_expand "slt"
3464 [(set (match_operand:DI 0 "register_operand" "")
3469 if (alpha_compare.fp_p)
3472 operands[1] = gen_rtx_LT (DImode, alpha_compare.op0, alpha_compare.op1);
3473 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3476 (define_expand "sle"
3477 [(set (match_operand:DI 0 "register_operand" "")
3482 if (alpha_compare.fp_p)
3485 operands[1] = gen_rtx_LE (DImode, alpha_compare.op0, alpha_compare.op1);
3486 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3489 (define_expand "sgt"
3490 [(set (match_operand:DI 0 "register_operand" "")
3495 if (alpha_compare.fp_p)
3498 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare.op1),
3500 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3503 (define_expand "sge"
3504 [(set (match_operand:DI 0 "register_operand" "")
3509 if (alpha_compare.fp_p)
3512 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare.op1),
3514 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3517 (define_expand "sltu"
3518 [(set (match_operand:DI 0 "register_operand" "")
3523 if (alpha_compare.fp_p)
3526 operands[1] = gen_rtx_LTU (DImode, alpha_compare.op0, alpha_compare.op1);
3527 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3530 (define_expand "sleu"
3531 [(set (match_operand:DI 0 "register_operand" "")
3536 if (alpha_compare.fp_p)
3539 operands[1] = gen_rtx_LEU (DImode, alpha_compare.op0, alpha_compare.op1);
3540 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3543 (define_expand "sgtu"
3544 [(set (match_operand:DI 0 "register_operand" "")
3549 if (alpha_compare.fp_p)
3552 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare.op1),
3554 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3557 (define_expand "sgeu"
3558 [(set (match_operand:DI 0 "register_operand" "")
3563 if (alpha_compare.fp_p)
3566 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare.op1),
3568 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3571 ;; These are the main define_expand's used to make conditional moves.
3573 (define_expand "movsicc"
3574 [(set (match_operand:SI 0 "register_operand" "")
3575 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3576 (match_operand:SI 2 "reg_or_8bit_operand" "")
3577 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3581 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3585 (define_expand "movdicc"
3586 [(set (match_operand:DI 0 "register_operand" "")
3587 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3588 (match_operand:DI 2 "reg_or_8bit_operand" "")
3589 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3593 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3597 (define_expand "movsfcc"
3598 [(set (match_operand:SF 0 "register_operand" "")
3599 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3600 (match_operand:SF 2 "reg_or_8bit_operand" "")
3601 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3605 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3609 (define_expand "movdfcc"
3610 [(set (match_operand:DF 0 "register_operand" "")
3611 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3612 (match_operand:DF 2 "reg_or_8bit_operand" "")
3613 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3617 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3621 ;; These define_split definitions are used in cases when comparisons have
3622 ;; not be stated in the correct way and we need to reverse the second
3623 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3624 ;; comparison that tests the result being reversed. We have one define_split
3625 ;; for each use of a comparison. They do not match valid insns and need
3626 ;; not generate valid insns.
3628 ;; We can also handle equality comparisons (and inequality comparisons in
3629 ;; cases where the resulting add cannot overflow) by doing an add followed by
3630 ;; a comparison with zero. This is faster since the addition takes one
3631 ;; less cycle than a compare when feeding into a conditional move.
3632 ;; For this case, we also have an SImode pattern since we can merge the add
3633 ;; and sign extend and the order doesn't matter.
3635 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3636 ;; operation could have been generated.
3639 [(set (match_operand:DI 0 "register_operand" "")
3641 (match_operator 1 "comparison_operator"
3642 [(match_operand:DI 2 "reg_or_0_operand" "")
3643 (match_operand:DI 3 "reg_or_cint_operand" "")])
3644 (match_operand:DI 4 "reg_or_cint_operand" "")
3645 (match_operand:DI 5 "reg_or_cint_operand" "")))
3646 (clobber (match_operand:DI 6 "register_operand" ""))]
3647 "operands[3] != const0_rtx"
3648 [(set (match_dup 6) (match_dup 7))
3650 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3652 { enum rtx_code code = GET_CODE (operands[1]);
3653 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3655 /* If we are comparing for equality with a constant and that constant
3656 appears in the arm when the register equals the constant, use the
3657 register since that is more likely to match (and to produce better code
3660 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3661 && rtx_equal_p (operands[4], operands[3]))
3662 operands[4] = operands[2];
3664 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3665 && rtx_equal_p (operands[5], operands[3]))
3666 operands[5] = operands[2];
3668 if (code == NE || code == EQ
3669 || (extended_count (operands[2], DImode, unsignedp) >= 1
3670 && extended_count (operands[3], DImode, unsignedp) >= 1))
3672 if (GET_CODE (operands[3]) == CONST_INT)
3673 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3674 GEN_INT (- INTVAL (operands[3])));
3676 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3678 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3681 else if (code == EQ || code == LE || code == LT
3682 || code == LEU || code == LTU)
3684 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3685 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3689 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3690 operands[2], operands[3]);
3691 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3696 [(set (match_operand:DI 0 "register_operand" "")
3698 (match_operator 1 "comparison_operator"
3699 [(match_operand:SI 2 "reg_or_0_operand" "")
3700 (match_operand:SI 3 "reg_or_cint_operand" "")])
3701 (match_operand:DI 4 "reg_or_8bit_operand" "")
3702 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3703 (clobber (match_operand:DI 6 "register_operand" ""))]
3704 "operands[3] != const0_rtx
3705 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3706 [(set (match_dup 6) (match_dup 7))
3708 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3710 { enum rtx_code code = GET_CODE (operands[1]);
3711 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3714 if ((code != NE && code != EQ
3715 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3716 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3719 if (GET_CODE (operands[3]) == CONST_INT)
3720 tem = gen_rtx_PLUS (SImode, operands[2],
3721 GEN_INT (- INTVAL (operands[3])));
3723 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3725 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3726 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3727 operands[6], const0_rtx);
3733 (match_operator 1 "comparison_operator"
3734 [(match_operand:DI 2 "reg_or_0_operand" "")
3735 (match_operand:DI 3 "reg_or_cint_operand" "")])
3736 (label_ref (match_operand 0 "" ""))
3738 (clobber (match_operand:DI 4 "register_operand" ""))]
3739 "operands[3] != const0_rtx"
3740 [(set (match_dup 4) (match_dup 5))
3741 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3743 { enum rtx_code code = GET_CODE (operands[1]);
3744 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3746 if (code == NE || code == EQ
3747 || (extended_count (operands[2], DImode, unsignedp) >= 1
3748 && extended_count (operands[3], DImode, unsignedp) >= 1))
3750 if (GET_CODE (operands[3]) == CONST_INT)
3751 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3752 GEN_INT (- INTVAL (operands[3])));
3754 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3756 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3759 else if (code == EQ || code == LE || code == LT
3760 || code == LEU || code == LTU)
3762 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3763 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3767 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3768 operands[2], operands[3]);
3769 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3776 (match_operator 1 "comparison_operator"
3777 [(match_operand:SI 2 "reg_or_0_operand" "")
3778 (match_operand:SI 3 "const_int_operand" "")])
3779 (label_ref (match_operand 0 "" ""))
3781 (clobber (match_operand:DI 4 "register_operand" ""))]
3782 "operands[3] != const0_rtx
3783 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3784 [(set (match_dup 4) (match_dup 5))
3785 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3789 if (GET_CODE (operands[3]) == CONST_INT)
3790 tem = gen_rtx_PLUS (SImode, operands[2],
3791 GEN_INT (- INTVAL (operands[3])));
3793 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3795 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3796 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3797 operands[4], const0_rtx);
3800 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3801 ;; This eliminates one, and sometimes two, insns when the AND can be done
3804 [(set (match_operand:DI 0 "register_operand" "")
3805 (match_operator:DI 1 "comparison_operator"
3806 [(match_operand:DI 2 "register_operand" "")
3807 (match_operand:DI 3 "const_int_operand" "")]))
3808 (clobber (match_operand:DI 4 "register_operand" ""))]
3809 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3810 && (GET_CODE (operands[1]) == GTU
3811 || GET_CODE (operands[1]) == LEU
3812 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3813 && extended_count (operands[2], DImode, 1) > 0))"
3814 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3815 (set (match_dup 0) (match_dup 6))]
3818 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3819 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3820 || GET_CODE (operands[1]) == GT)
3822 DImode, operands[4], const0_rtx);
3825 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3826 ;; work differently, so we have different patterns for each.
3828 (define_expand "call"
3829 [(use (match_operand:DI 0 "" ""))
3830 (use (match_operand 1 "" ""))
3831 (use (match_operand 2 "" ""))
3832 (use (match_operand 3 "" ""))]
3835 { if (TARGET_WINDOWS_NT)
3836 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3837 else if (TARGET_OPEN_VMS)
3838 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3840 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3845 (define_expand "sibcall"
3846 [(call (mem:DI (match_operand 0 "" ""))
3847 (match_operand 1 "" ""))]
3848 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
3851 if (GET_CODE (operands[0]) != MEM)
3853 operands[0] = XEXP (operands[0], 0);
3856 (define_expand "call_osf"
3857 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3858 (match_operand 1 "" ""))
3859 (clobber (reg:DI 27))
3860 (clobber (reg:DI 26))])]
3863 { if (GET_CODE (operands[0]) != MEM)
3866 operands[0] = XEXP (operands[0], 0);
3868 if (GET_CODE (operands[0]) != SYMBOL_REF
3869 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3871 rtx tem = gen_rtx_REG (DImode, 27);
3872 emit_move_insn (tem, operands[0]);
3877 (define_expand "call_nt"
3878 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3879 (match_operand 1 "" ""))
3880 (clobber (reg:DI 26))])]
3883 { if (GET_CODE (operands[0]) != MEM)
3886 operands[0] = XEXP (operands[0], 0);
3887 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3888 operands[0] = force_reg (DImode, operands[0]);
3892 ;; call openvms/alpha
3893 ;; op 0: symbol ref for called function
3894 ;; op 1: next_arg_reg (argument information value for R25)
3896 (define_expand "call_vms"
3897 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3898 (match_operand 1 "" ""))
3902 (clobber (reg:DI 27))])]
3905 { if (GET_CODE (operands[0]) != MEM)
3908 operands[0] = XEXP (operands[0], 0);
3910 /* Always load AI with argument information, then handle symbolic and
3911 indirect call differently. Load RA and set operands[2] to PV in
3914 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3915 if (GET_CODE (operands[0]) == SYMBOL_REF)
3917 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
3919 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3921 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3925 emit_move_insn (gen_rtx_REG (Pmode, 26),
3926 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3927 operands[2] = operands[0];
3932 (define_expand "call_value"
3933 [(use (match_operand 0 "" ""))
3934 (use (match_operand:DI 1 "" ""))
3935 (use (match_operand 2 "" ""))
3936 (use (match_operand 3 "" ""))
3937 (use (match_operand 4 "" ""))]
3940 { if (TARGET_WINDOWS_NT)
3941 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3942 else if (TARGET_OPEN_VMS)
3943 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3946 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3951 (define_expand "sibcall_value"
3952 [(set (match_operand 0 "" "")
3953 (call (mem:DI (match_operand 1 "" ""))
3954 (match_operand 2 "" "")))]
3955 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
3958 if (GET_CODE (operands[1]) != MEM)
3960 operands[1] = XEXP (operands[1], 0);
3963 (define_expand "call_value_osf"
3964 [(parallel [(set (match_operand 0 "" "")
3965 (call (mem:DI (match_operand 1 "" ""))
3966 (match_operand 2 "" "")))
3967 (clobber (reg:DI 27))
3968 (clobber (reg:DI 26))])]
3971 { if (GET_CODE (operands[1]) != MEM)
3974 operands[1] = XEXP (operands[1], 0);
3976 if (GET_CODE (operands[1]) != SYMBOL_REF
3977 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3979 rtx tem = gen_rtx_REG (DImode, 27);
3980 emit_move_insn (tem, operands[1]);
3985 (define_expand "call_value_nt"
3986 [(parallel [(set (match_operand 0 "" "")
3987 (call (mem:DI (match_operand 1 "" ""))
3988 (match_operand 2 "" "")))
3989 (clobber (reg:DI 26))])]
3992 { if (GET_CODE (operands[1]) != MEM)
3995 operands[1] = XEXP (operands[1], 0);
3996 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
3997 operands[1] = force_reg (DImode, operands[1]);
4000 (define_expand "call_value_vms"
4001 [(parallel [(set (match_operand 0 "" "")
4002 (call (mem:DI (match_operand:DI 1 "" ""))
4003 (match_operand 2 "" "")))
4007 (clobber (reg:DI 27))])]
4010 { if (GET_CODE (operands[1]) != MEM)
4013 operands[1] = XEXP (operands[1], 0);
4015 /* Always load AI with argument information, then handle symbolic and
4016 indirect call differently. Load RA and set operands[3] to PV in
4019 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4020 if (GET_CODE (operands[1]) == SYMBOL_REF)
4022 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4024 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4026 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4030 emit_move_insn (gen_rtx_REG (Pmode, 26),
4031 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4032 operands[3] = operands[1];
4036 (define_insn "*call_osf_1"
4037 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4038 (match_operand 1 "" ""))
4039 (clobber (reg:DI 27))
4040 (clobber (reg:DI 26))]
4041 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4043 jsr $26,($27),0\;ldgp $29,0($26)
4045 jsr $26,%0\;ldgp $29,0($26)"
4046 [(set_attr "type" "jsr")
4047 (set_attr "length" "12,*,16")])
4049 (define_insn "*sibcall_osf_1"
4050 [(call (mem:DI (match_operand:DI 0 "call_operand" "R,i"))
4051 (match_operand 1 "" ""))]
4052 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4056 [(set_attr "type" "jsr")
4057 (set_attr "length" "*,8")])
4059 (define_insn "*call_nt_1"
4060 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4061 (match_operand 1 "" ""))
4062 (clobber (reg:DI 26))]
4068 [(set_attr "type" "jsr")
4069 (set_attr "length" "*,*,12")])
4071 (define_insn "*call_vms_1"
4072 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
4073 (match_operand 1 "" ""))
4074 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4077 (clobber (reg:DI 27))]
4080 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4081 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4082 [(set_attr "type" "jsr")
4083 (set_attr "length" "12,16")])
4085 ;; Call subroutine returning any type.
4087 (define_expand "untyped_call"
4088 [(parallel [(call (match_operand 0 "" "")
4090 (match_operand 1 "" "")
4091 (match_operand 2 "" "")])]
4097 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4099 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4101 rtx set = XVECEXP (operands[2], 0, i);
4102 emit_move_insn (SET_DEST (set), SET_SRC (set));
4105 /* The optimizer does not know that the call sets the function value
4106 registers we stored in the result block. We avoid problems by
4107 claiming that all hard registers are used and clobbered at this
4109 emit_insn (gen_blockage ());
4114 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4115 ;; all of memory. This blocks insns from being moved across this point.
4117 (define_insn "blockage"
4118 [(unspec_volatile [(const_int 0)] 1)]
4121 [(set_attr "length" "0")])
4125 (label_ref (match_operand 0 "" "")))]
4128 [(set_attr "type" "ibr")])
4130 (define_expand "return"
4135 (define_insn "*return_internal"
4139 [(set_attr "type" "ibr")])
4141 (define_insn "indirect_jump"
4142 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4145 [(set_attr "type" "ibr")])
4147 (define_expand "tablejump"
4148 [(use (match_operand:SI 0 "register_operand" ""))
4149 (use (match_operand:SI 1 "" ""))]
4153 if (TARGET_WINDOWS_NT)
4154 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4155 else if (TARGET_OPEN_VMS)
4156 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4158 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4163 (define_expand "tablejump_osf"
4165 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4166 (parallel [(set (pc)
4167 (plus:DI (match_dup 3)
4168 (label_ref (match_operand 1 "" ""))))
4169 (clobber (match_scratch:DI 2 "=r"))])]
4172 { operands[3] = gen_reg_rtx (DImode); }")
4174 (define_expand "tablejump_nt"
4176 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4177 (parallel [(set (pc)
4179 (use (label_ref (match_operand 1 "" "")))])]
4182 { operands[3] = gen_reg_rtx (DImode); }")
4185 ;; tablejump, openVMS way
4187 ;; op 1: label preceding jump-table
4189 (define_expand "tablejump_vms"
4191 (match_operand:DI 0 "register_operand" ""))
4193 (plus:DI (match_dup 2)
4194 (label_ref (match_operand 1 "" ""))))]
4197 { operands[2] = gen_reg_rtx (DImode); }")
4201 (plus (match_operand:DI 0 "register_operand" "r")
4202 (label_ref (match_operand 1 "" ""))))
4203 (clobber (match_scratch:DI 2 "=r"))]
4204 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
4205 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4206 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4208 { rtx best_label = 0;
4209 rtx jump_table_insn = next_active_insn (operands[1]);
4211 if (GET_CODE (jump_table_insn) == JUMP_INSN
4212 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4214 rtx jump_table = PATTERN (jump_table_insn);
4215 int n_labels = XVECLEN (jump_table, 1);
4216 int best_count = -1;
4219 for (i = 0; i < n_labels; i++)
4223 for (j = i + 1; j < n_labels; j++)
4224 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4225 == XEXP (XVECEXP (jump_table, 1, j), 0))
4228 if (count > best_count)
4229 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4235 operands[3] = best_label;
4236 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
4239 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
4241 [(set_attr "type" "ibr")
4242 (set_attr "length" "8")])
4246 (match_operand:DI 0 "register_operand" "r"))
4247 (use (label_ref (match_operand 1 "" "")))]
4248 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
4249 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4250 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4252 { rtx best_label = 0;
4253 rtx jump_table_insn = next_active_insn (operands[1]);
4255 if (GET_CODE (jump_table_insn) == JUMP_INSN
4256 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4258 rtx jump_table = PATTERN (jump_table_insn);
4259 int n_labels = XVECLEN (jump_table, 1);
4260 int best_count = -1;
4263 for (i = 0; i < n_labels; i++)
4267 for (j = i + 1; j < n_labels; j++)
4268 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4269 == XEXP (XVECEXP (jump_table, 1, j), 0))
4272 if (count > best_count)
4273 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4279 operands[2] = best_label;
4280 return \"jmp $31,(%0),%2\";
4283 return \"jmp $31,(%0),0\";
4285 [(set_attr "type" "ibr")])
4288 ;; op 0 is table offset
4289 ;; op 1 is table label
4294 (plus (match_operand:DI 0 "register_operand" "r")
4295 (label_ref (match_operand 1 "" ""))))]
4298 [(set_attr "type" "ibr")])
4300 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4301 ;; want to have to include pal.h in our .s file.
4303 ;; Technically the type for call_pal is jsr, but we use that for determining
4304 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4307 [(unspec_volatile [(const_int 0)] 0)]
4310 [(set_attr "type" "ibr")])
4312 ;; Finally, we have the basic data motion insns. The byte and word insns
4313 ;; are done via define_expand. Start with the floating-point insns, since
4314 ;; they are simpler.
4317 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4318 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4319 "TARGET_FPREGS && ! TARGET_FIX
4320 && (register_operand (operands[0], SFmode)
4321 || reg_or_fp0_operand (operands[1], SFmode))"
4329 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4332 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4333 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4334 "TARGET_FPREGS && TARGET_FIX
4335 && (register_operand (operands[0], SFmode)
4336 || reg_or_fp0_operand (operands[1], SFmode))"
4346 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4349 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4350 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4352 && (register_operand (operands[0], SFmode)
4353 || reg_or_fp0_operand (operands[1], SFmode))"
4358 [(set_attr "type" "ilog,ild,ist")])
4361 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4362 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4363 "TARGET_FPREGS && ! TARGET_FIX
4364 && (register_operand (operands[0], DFmode)
4365 || reg_or_fp0_operand (operands[1], DFmode))"
4373 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4376 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4377 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4378 "TARGET_FPREGS && TARGET_FIX
4379 && (register_operand (operands[0], DFmode)
4380 || reg_or_fp0_operand (operands[1], DFmode))"
4390 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4393 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4394 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4396 && (register_operand (operands[0], DFmode)
4397 || reg_or_fp0_operand (operands[1], DFmode))"
4402 [(set_attr "type" "ilog,ild,ist")])
4404 ;; Subregs suck for register allocation. Pretend we can move TFmode
4405 ;; data between general registers until after reload.
4407 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4408 (match_operand:TF 1 "input_operand" "roG,r"))]
4409 "register_operand (operands[0], TFmode)
4410 || reg_or_fp0_operand (operands[1], TFmode)"
4414 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4415 (match_operand:TF 1 "input_operand" ""))]
4417 [(set (match_dup 0) (match_dup 2))
4418 (set (match_dup 1) (match_dup 3))]
4421 alpha_split_tfmode_pair (operands);
4422 if (rtx_equal_p (operands[0], operands[3]))
4425 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4426 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4430 (define_expand "movsf"
4431 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4432 (match_operand:SF 1 "general_operand" ""))]
4436 if (GET_CODE (operands[0]) == MEM
4437 && ! reg_or_fp0_operand (operands[1], SFmode))
4438 operands[1] = force_reg (SFmode, operands[1]);
4441 (define_expand "movdf"
4442 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4443 (match_operand:DF 1 "general_operand" ""))]
4447 if (GET_CODE (operands[0]) == MEM
4448 && ! reg_or_fp0_operand (operands[1], DFmode))
4449 operands[1] = force_reg (DFmode, operands[1]);
4452 (define_expand "movtf"
4453 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4454 (match_operand:TF 1 "general_operand" ""))]
4458 if (GET_CODE (operands[0]) == MEM
4459 && ! reg_or_fp0_operand (operands[1], TFmode))
4460 operands[1] = force_reg (TFmode, operands[1]);
4464 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4465 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4466 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4467 && (register_operand (operands[0], SImode)
4468 || reg_or_0_operand (operands[1], SImode))"
4478 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4481 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4482 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4483 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4484 && (register_operand (operands[0], SImode)
4485 || reg_or_0_operand (operands[1], SImode))"
4497 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4500 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4501 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4502 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4503 && (register_operand (operands[0], SImode)
4504 || reg_or_0_operand (operands[1], SImode))"
4515 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4518 [(set (match_operand:HI 0 "register_operand" "=r,r")
4519 (match_operand:HI 1 "input_operand" "rJ,n"))]
4521 && (register_operand (operands[0], HImode)
4522 || register_operand (operands[1], HImode))"
4526 [(set_attr "type" "ilog,iadd")])
4529 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4530 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4532 && (register_operand (operands[0], HImode)
4533 || reg_or_0_operand (operands[1], HImode))"
4539 [(set_attr "type" "ilog,iadd,ild,ist")])
4542 [(set (match_operand:QI 0 "register_operand" "=r,r")
4543 (match_operand:QI 1 "input_operand" "rJ,n"))]
4545 && (register_operand (operands[0], QImode)
4546 || register_operand (operands[1], QImode))"
4550 [(set_attr "type" "ilog,iadd")])
4553 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4554 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4556 && (register_operand (operands[0], QImode)
4557 || reg_or_0_operand (operands[1], QImode))"
4563 [(set_attr "type" "ilog,iadd,ild,ist")])
4565 ;; We do two major things here: handle mem->mem and construct long
4568 (define_expand "movsi"
4569 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4570 (match_operand:SI 1 "general_operand" ""))]
4574 if (GET_CODE (operands[0]) == MEM
4575 && ! reg_or_0_operand (operands[1], SImode))
4576 operands[1] = force_reg (SImode, operands[1]);
4578 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4580 else if (GET_CODE (operands[1]) == CONST_INT)
4583 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4584 if (rtx_equal_p (operands[0], operands[1]))
4589 ;; Split a load of a large constant into the appropriate two-insn
4593 [(set (match_operand:SI 0 "register_operand" "")
4594 (match_operand:SI 1 "const_int_operand" ""))]
4595 "! add_operand (operands[1], SImode)"
4596 [(set (match_dup 0) (match_dup 2))
4597 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4600 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4602 if (tem == operands[0])
4609 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4610 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4612 && (register_operand (operands[0], DImode)
4613 || reg_or_0_operand (operands[1], DImode))"
4624 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4627 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4628 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4630 && (register_operand (operands[0], DImode)
4631 || reg_or_0_operand (operands[1], DImode))"
4644 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4646 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4647 ;; memory, and construct long 32-bit constants.
4649 (define_expand "movdi"
4650 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4651 (match_operand:DI 1 "general_operand" ""))]
4657 if (GET_CODE (operands[0]) == MEM
4658 && ! reg_or_0_operand (operands[1], DImode))
4659 operands[1] = force_reg (DImode, operands[1]);
4661 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4663 else if (GET_CODE (operands[1]) == CONST_INT
4664 && (tem = alpha_emit_set_const (operands[0], DImode,
4665 INTVAL (operands[1]), 3)) != 0)
4667 if (rtx_equal_p (tem, operands[0]))
4672 else if (CONSTANT_P (operands[1]))
4674 if (TARGET_BUILD_CONSTANTS)
4676 HOST_WIDE_INT i0, i1;
4678 if (GET_CODE (operands[1]) == CONST_INT)
4680 i0 = INTVAL (operands[1]);
4683 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4685 #if HOST_BITS_PER_WIDE_INT >= 64
4686 i0 = CONST_DOUBLE_LOW (operands[1]);
4689 i0 = CONST_DOUBLE_LOW (operands[1]);
4690 i1 = CONST_DOUBLE_HIGH (operands[1]);
4696 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4697 if (rtx_equal_p (tem, operands[0]))
4704 operands[1] = force_const_mem (DImode, operands[1]);
4705 if (reload_in_progress)
4707 emit_move_insn (operands[0], XEXP (operands[1], 0));
4708 operands[1] = copy_rtx (operands[1]);
4709 XEXP (operands[1], 0) = operands[0];
4712 operands[1] = validize_mem (operands[1]);
4719 ;; Split a load of a large constant into the appropriate two-insn
4723 [(set (match_operand:DI 0 "register_operand" "")
4724 (match_operand:DI 1 "const_int_operand" ""))]
4725 "! add_operand (operands[1], DImode)"
4726 [(set (match_dup 0) (match_dup 2))
4727 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4730 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4732 if (tem == operands[0])
4738 ;; These are the partial-word cases.
4740 ;; First we have the code to load an aligned word. Operand 0 is the register
4741 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4742 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4743 ;; number of bits within the word that the value is. Operand 3 is an SImode
4744 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4745 ;; same register. It is allowed to conflict with operand 1 as well.
4747 (define_expand "aligned_loadqi"
4748 [(set (match_operand:SI 3 "register_operand" "")
4749 (match_operand:SI 1 "memory_operand" ""))
4750 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4751 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4753 (match_operand:DI 2 "const_int_operand" "")))]
4758 (define_expand "aligned_loadhi"
4759 [(set (match_operand:SI 3 "register_operand" "")
4760 (match_operand:SI 1 "memory_operand" ""))
4761 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4762 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4764 (match_operand:DI 2 "const_int_operand" "")))]
4769 ;; Similar for unaligned loads, where we use the sequence from the
4770 ;; Alpha Architecture manual.
4772 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4773 ;; operand 3 can overlap the input and output registers.
4775 (define_expand "unaligned_loadqi"
4776 [(set (match_operand:DI 2 "register_operand" "")
4777 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4779 (set (match_operand:DI 3 "register_operand" "")
4781 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4782 (zero_extract:DI (match_dup 2)
4784 (ashift:DI (match_dup 3) (const_int 3))))]
4788 (define_expand "unaligned_loadhi"
4789 [(set (match_operand:DI 2 "register_operand" "")
4790 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4792 (set (match_operand:DI 3 "register_operand" "")
4794 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4795 (zero_extract:DI (match_dup 2)
4797 (ashift:DI (match_dup 3) (const_int 3))))]
4801 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4802 ;; aligned SImode MEM. Operand 1 is the register containing the
4803 ;; byte or word to store. Operand 2 is the number of bits within the word that
4804 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4806 (define_expand "aligned_store"
4807 [(set (match_operand:SI 3 "register_operand" "")
4808 (match_operand:SI 0 "memory_operand" ""))
4809 (set (subreg:DI (match_dup 3) 0)
4810 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4811 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4812 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4813 (match_operand:DI 2 "const_int_operand" "")))
4814 (set (subreg:DI (match_dup 4) 0)
4815 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4816 (set (match_dup 0) (match_dup 4))]
4819 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4820 << INTVAL (operands[2])));
4823 ;; For the unaligned byte and halfword cases, we use code similar to that
4824 ;; in the ;; Architecture book, but reordered to lower the number of registers
4825 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4826 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4827 ;; be the same temporary, if desired. If the address is in a register,
4828 ;; operand 2 can be that register.
4830 (define_expand "unaligned_storeqi"
4831 [(set (match_operand:DI 3 "register_operand" "")
4832 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4834 (set (match_operand:DI 2 "register_operand" "")
4837 (and:DI (not:DI (ashift:DI (const_int 255)
4838 (ashift:DI (match_dup 2) (const_int 3))))
4840 (set (match_operand:DI 4 "register_operand" "")
4841 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4842 (ashift:DI (match_dup 2) (const_int 3))))
4843 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4844 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4849 (define_expand "unaligned_storehi"
4850 [(set (match_operand:DI 3 "register_operand" "")
4851 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4853 (set (match_operand:DI 2 "register_operand" "")
4856 (and:DI (not:DI (ashift:DI (const_int 65535)
4857 (ashift:DI (match_dup 2) (const_int 3))))
4859 (set (match_operand:DI 4 "register_operand" "")
4860 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4861 (ashift:DI (match_dup 2) (const_int 3))))
4862 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4863 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4868 ;; Here are the define_expand's for QI and HI moves that use the above
4869 ;; patterns. We have the normal sets, plus the ones that need scratch
4870 ;; registers for reload.
4872 (define_expand "movqi"
4873 [(set (match_operand:QI 0 "nonimmediate_operand" "")
4874 (match_operand:QI 1 "general_operand" ""))]
4880 if (GET_CODE (operands[0]) == MEM
4881 && ! reg_or_0_operand (operands[1], QImode))
4882 operands[1] = force_reg (QImode, operands[1]);
4884 if (GET_CODE (operands[1]) == CONST_INT
4885 && ! input_operand (operands[1], QImode))
4887 operands[1] = alpha_emit_set_const (operands[0], QImode,
4888 INTVAL (operands[1]), 3);
4890 if (rtx_equal_p (operands[0], operands[1]))
4897 /* If the output is not a register, the input must be. */
4898 if (GET_CODE (operands[0]) == MEM)
4899 operands[1] = force_reg (QImode, operands[1]);
4901 /* Handle four memory cases, unaligned and aligned for either the input
4902 or the output. The only case where we can be called during reload is
4903 for aligned loads; all other cases require temporaries. */
4905 if (GET_CODE (operands[1]) == MEM
4906 || (GET_CODE (operands[1]) == SUBREG
4907 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4908 || (reload_in_progress && GET_CODE (operands[1]) == REG
4909 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4910 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4911 && GET_CODE (SUBREG_REG (operands[1])) == REG
4912 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4914 if (aligned_memory_operand (operands[1], QImode))
4916 if (reload_in_progress)
4918 emit_insn (gen_reload_inqi_help
4919 (operands[0], operands[1],
4920 gen_rtx_REG (SImode, REGNO (operands[0]))));
4924 rtx aligned_mem, bitnum;
4925 rtx scratch = gen_reg_rtx (SImode);
4927 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4929 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4935 /* Don't pass these as parameters since that makes the generated
4936 code depend on parameter evaluation order which will cause
4937 bootstrap failures. */
4939 rtx temp1 = gen_reg_rtx (DImode);
4940 rtx temp2 = gen_reg_rtx (DImode);
4942 = gen_unaligned_loadqi (operands[0],
4943 get_unaligned_address (operands[1], 0),
4946 alpha_set_memflags (seq, operands[1]);
4953 else if (GET_CODE (operands[0]) == MEM
4954 || (GET_CODE (operands[0]) == SUBREG
4955 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4956 || (reload_in_progress && GET_CODE (operands[0]) == REG
4957 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4958 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4959 && GET_CODE (SUBREG_REG (operands[0])) == REG
4960 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4962 if (aligned_memory_operand (operands[0], QImode))
4964 rtx aligned_mem, bitnum;
4965 rtx temp1 = gen_reg_rtx (SImode);
4966 rtx temp2 = gen_reg_rtx (SImode);
4968 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4970 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4975 rtx temp1 = gen_reg_rtx (DImode);
4976 rtx temp2 = gen_reg_rtx (DImode);
4977 rtx temp3 = gen_reg_rtx (DImode);
4979 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4980 operands[1], temp1, temp2, temp3);
4982 alpha_set_memflags (seq, operands[0]);
4990 (define_expand "movhi"
4991 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4992 (match_operand:HI 1 "general_operand" ""))]
4998 if (GET_CODE (operands[0]) == MEM
4999 && ! reg_or_0_operand (operands[1], HImode))
5000 operands[1] = force_reg (HImode, operands[1]);
5002 if (GET_CODE (operands[1]) == CONST_INT
5003 && ! input_operand (operands[1], HImode))
5005 operands[1] = alpha_emit_set_const (operands[0], HImode,
5006 INTVAL (operands[1]), 3);
5008 if (rtx_equal_p (operands[0], operands[1]))
5015 /* If the output is not a register, the input must be. */
5016 if (GET_CODE (operands[0]) == MEM)
5017 operands[1] = force_reg (HImode, operands[1]);
5019 /* Handle four memory cases, unaligned and aligned for either the input
5020 or the output. The only case where we can be called during reload is
5021 for aligned loads; all other cases require temporaries. */
5023 if (GET_CODE (operands[1]) == MEM
5024 || (GET_CODE (operands[1]) == SUBREG
5025 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5026 || (reload_in_progress && GET_CODE (operands[1]) == REG
5027 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5028 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5029 && GET_CODE (SUBREG_REG (operands[1])) == REG
5030 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5032 if (aligned_memory_operand (operands[1], HImode))
5034 if (reload_in_progress)
5036 emit_insn (gen_reload_inhi_help
5037 (operands[0], operands[1],
5038 gen_rtx_REG (SImode, REGNO (operands[0]))));
5042 rtx aligned_mem, bitnum;
5043 rtx scratch = gen_reg_rtx (SImode);
5045 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5047 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5053 /* Don't pass these as parameters since that makes the generated
5054 code depend on parameter evaluation order which will cause
5055 bootstrap failures. */
5057 rtx temp1 = gen_reg_rtx (DImode);
5058 rtx temp2 = gen_reg_rtx (DImode);
5060 = gen_unaligned_loadhi (operands[0],
5061 get_unaligned_address (operands[1], 0),
5064 alpha_set_memflags (seq, operands[1]);
5071 else if (GET_CODE (operands[0]) == MEM
5072 || (GET_CODE (operands[0]) == SUBREG
5073 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5074 || (reload_in_progress && GET_CODE (operands[0]) == REG
5075 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5076 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5077 && GET_CODE (SUBREG_REG (operands[0])) == REG
5078 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5080 if (aligned_memory_operand (operands[0], HImode))
5082 rtx aligned_mem, bitnum;
5083 rtx temp1 = gen_reg_rtx (SImode);
5084 rtx temp2 = gen_reg_rtx (SImode);
5086 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5088 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5093 rtx temp1 = gen_reg_rtx (DImode);
5094 rtx temp2 = gen_reg_rtx (DImode);
5095 rtx temp3 = gen_reg_rtx (DImode);
5097 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
5098 operands[1], temp1, temp2, temp3);
5100 alpha_set_memflags (seq, operands[0]);
5109 ;; Here are the versions for reload. Note that in the unaligned cases
5110 ;; we know that the operand must not be a pseudo-register because stack
5111 ;; slots are always aligned references.
5113 (define_expand "reload_inqi"
5114 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5115 (match_operand:QI 1 "any_memory_operand" "m")
5116 (match_operand:TI 2 "register_operand" "=&r")])]
5122 if (GET_CODE (operands[1]) != MEM)
5125 if (aligned_memory_operand (operands[1], QImode))
5127 seq = gen_reload_inqi_help (operands[0], operands[1],
5128 gen_rtx_REG (SImode, REGNO (operands[2])));
5134 /* It is possible that one of the registers we got for operands[2]
5135 might coincide with that of operands[0] (which is why we made
5136 it TImode). Pick the other one to use as our scratch. */
5137 if (REGNO (operands[0]) == REGNO (operands[2]))
5138 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5140 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5142 addr = get_unaligned_address (operands[1], 0);
5143 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5144 gen_rtx_REG (DImode, REGNO (operands[0])));
5145 alpha_set_memflags (seq, operands[1]);
5151 (define_expand "reload_inhi"
5152 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5153 (match_operand:HI 1 "any_memory_operand" "m")
5154 (match_operand:TI 2 "register_operand" "=&r")])]
5160 if (GET_CODE (operands[1]) != MEM)
5163 if (aligned_memory_operand (operands[1], HImode))
5165 seq = gen_reload_inhi_help (operands[0], operands[1],
5166 gen_rtx_REG (SImode, REGNO (operands[2])));
5172 /* It is possible that one of the registers we got for operands[2]
5173 might coincide with that of operands[0] (which is why we made
5174 it TImode). Pick the other one to use as our scratch. */
5175 if (REGNO (operands[0]) == REGNO (operands[2]))
5176 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5178 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5180 addr = get_unaligned_address (operands[1], 0);
5181 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5182 gen_rtx_REG (DImode, REGNO (operands[0])));
5183 alpha_set_memflags (seq, operands[1]);
5189 (define_expand "reload_outqi"
5190 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5191 (match_operand:QI 1 "register_operand" "r")
5192 (match_operand:TI 2 "register_operand" "=&r")])]
5196 if (GET_CODE (operands[0]) != MEM)
5199 if (aligned_memory_operand (operands[0], QImode))
5201 emit_insn (gen_reload_outqi_help
5202 (operands[0], operands[1],
5203 gen_rtx_REG (SImode, REGNO (operands[2])),
5204 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5208 rtx addr = get_unaligned_address (operands[0], 0);
5209 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5210 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5211 rtx scratch3 = scratch1;
5214 if (GET_CODE (addr) == REG)
5217 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5218 scratch2, scratch3);
5219 alpha_set_memflags (seq, operands[0]);
5225 (define_expand "reload_outhi"
5226 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5227 (match_operand:HI 1 "register_operand" "r")
5228 (match_operand:TI 2 "register_operand" "=&r")])]
5232 if (GET_CODE (operands[0]) != MEM)
5235 if (aligned_memory_operand (operands[0], HImode))
5237 emit_insn (gen_reload_outhi_help
5238 (operands[0], operands[1],
5239 gen_rtx_REG (SImode, REGNO (operands[2])),
5240 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5244 rtx addr = get_unaligned_address (operands[0], 0);
5245 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5246 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5247 rtx scratch3 = scratch1;
5250 if (GET_CODE (addr) == REG)
5253 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5254 scratch2, scratch3);
5255 alpha_set_memflags (seq, operands[0]);
5261 ;; Helpers for the above. The way reload is structured, we can't
5262 ;; always get a proper address for a stack slot during reload_foo
5263 ;; expansion, so we must delay our address manipulations until after.
5265 (define_insn "reload_inqi_help"
5266 [(set (match_operand:QI 0 "register_operand" "=r")
5267 (match_operand:QI 1 "memory_operand" "m"))
5268 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5269 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5272 (define_insn "reload_inhi_help"
5273 [(set (match_operand:HI 0 "register_operand" "=r")
5274 (match_operand:HI 1 "memory_operand" "m"))
5275 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5276 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5279 (define_insn "reload_outqi_help"
5280 [(set (match_operand:QI 0 "memory_operand" "=m")
5281 (match_operand:QI 1 "register_operand" "r"))
5282 (clobber (match_operand:SI 2 "register_operand" "=r"))
5283 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5284 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5287 (define_insn "reload_outhi_help"
5288 [(set (match_operand:HI 0 "memory_operand" "=m")
5289 (match_operand:HI 1 "register_operand" "r"))
5290 (clobber (match_operand:SI 2 "register_operand" "=r"))
5291 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5292 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5296 [(set (match_operand:QI 0 "register_operand" "")
5297 (match_operand:QI 1 "memory_operand" ""))
5298 (clobber (match_operand:SI 2 "register_operand" ""))]
5299 "! TARGET_BWX && reload_completed"
5303 rtx aligned_mem, bitnum;
5304 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5305 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5311 [(set (match_operand:HI 0 "register_operand" "")
5312 (match_operand:HI 1 "memory_operand" ""))
5313 (clobber (match_operand:SI 2 "register_operand" ""))]
5314 "! TARGET_BWX && reload_completed"
5318 rtx aligned_mem, bitnum;
5319 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5320 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5326 [(set (match_operand:QI 0 "memory_operand" "")
5327 (match_operand:QI 1 "register_operand" ""))
5328 (clobber (match_operand:SI 2 "register_operand" ""))
5329 (clobber (match_operand:SI 3 "register_operand" ""))]
5330 "! TARGET_BWX && reload_completed"
5334 rtx aligned_mem, bitnum;
5335 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5336 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5337 operands[2], operands[3]));
5342 [(set (match_operand:HI 0 "memory_operand" "")
5343 (match_operand:HI 1 "register_operand" ""))
5344 (clobber (match_operand:SI 2 "register_operand" ""))
5345 (clobber (match_operand:SI 3 "register_operand" ""))]
5346 "! TARGET_BWX && reload_completed"
5350 rtx aligned_mem, bitnum;
5351 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5352 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5353 operands[2], operands[3]));
5357 ;; Bit field extract patterns which use ext[wlq][lh]
5359 (define_expand "extv"
5360 [(set (match_operand:DI 0 "register_operand" "")
5361 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5362 (match_operand:DI 2 "immediate_operand" "")
5363 (match_operand:DI 3 "immediate_operand" "")))]
5367 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5368 if (INTVAL (operands[3]) % 8 != 0
5369 || (INTVAL (operands[2]) != 16
5370 && INTVAL (operands[2]) != 32
5371 && INTVAL (operands[2]) != 64))
5374 /* From mips.md: extract_bit_field doesn't verify that our source
5375 matches the predicate, so we force it to be a MEM here. */
5376 if (GET_CODE (operands[1]) != MEM)
5379 alpha_expand_unaligned_load (operands[0], operands[1],
5380 INTVAL (operands[2]) / 8,
5381 INTVAL (operands[3]) / 8, 1);
5385 (define_expand "extzv"
5386 [(set (match_operand:DI 0 "register_operand" "")
5387 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5388 (match_operand:DI 2 "immediate_operand" "")
5389 (match_operand:DI 3 "immediate_operand" "")))]
5393 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5394 if (INTVAL (operands[3]) % 8 != 0
5395 || (INTVAL (operands[2]) != 8
5396 && INTVAL (operands[2]) != 16
5397 && INTVAL (operands[2]) != 32
5398 && INTVAL (operands[2]) != 64))
5401 if (GET_CODE (operands[1]) == MEM)
5403 /* Fail 8 bit fields, falling back on a simple byte load. */
5404 if (INTVAL (operands[2]) == 8)
5407 alpha_expand_unaligned_load (operands[0], operands[1],
5408 INTVAL (operands[2]) / 8,
5409 INTVAL (operands[3]) / 8, 0);
5414 (define_expand "insv"
5415 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5416 (match_operand:DI 1 "immediate_operand" "")
5417 (match_operand:DI 2 "immediate_operand" ""))
5418 (match_operand:DI 3 "register_operand" ""))]
5422 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5423 if (INTVAL (operands[2]) % 8 != 0
5424 || (INTVAL (operands[1]) != 16
5425 && INTVAL (operands[1]) != 32
5426 && INTVAL (operands[1]) != 64))
5429 /* From mips.md: store_bit_field doesn't verify that our source
5430 matches the predicate, so we force it to be a MEM here. */
5431 if (GET_CODE (operands[0]) != MEM)
5434 alpha_expand_unaligned_store (operands[0], operands[3],
5435 INTVAL (operands[1]) / 8,
5436 INTVAL (operands[2]) / 8);
5442 ;; Block move/clear, see alpha.c for more details.
5443 ;; Argument 0 is the destination
5444 ;; Argument 1 is the source
5445 ;; Argument 2 is the length
5446 ;; Argument 3 is the alignment
5448 (define_expand "movstrqi"
5449 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5450 (match_operand:BLK 1 "memory_operand" ""))
5451 (use (match_operand:DI 2 "immediate_operand" ""))
5452 (use (match_operand:DI 3 "immediate_operand" ""))])]
5456 if (alpha_expand_block_move (operands))
5462 (define_expand "clrstrqi"
5463 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5465 (use (match_operand:DI 1 "immediate_operand" ""))
5466 (use (match_operand:DI 2 "immediate_operand" ""))])]
5470 if (alpha_expand_block_clear (operands))
5476 ;; Subroutine of stack space allocation. Perform a stack probe.
5477 (define_expand "probe_stack"
5478 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5482 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5483 INTVAL (operands[0])));
5484 MEM_VOLATILE_P (operands[1]) = 1;
5486 operands[0] = const0_rtx;
5489 ;; This is how we allocate stack space. If we are allocating a
5490 ;; constant amount of space and we know it is less than 4096
5491 ;; bytes, we need do nothing.
5493 ;; If it is more than 4096 bytes, we need to probe the stack
5495 (define_expand "allocate_stack"
5497 (plus:DI (reg:DI 30)
5498 (match_operand:DI 1 "reg_or_cint_operand" "")))
5499 (set (match_operand:DI 0 "register_operand" "=r")
5504 if (GET_CODE (operands[1]) == CONST_INT
5505 && INTVAL (operands[1]) < 32768)
5507 if (INTVAL (operands[1]) >= 4096)
5509 /* We do this the same way as in the prologue and generate explicit
5510 probes. Then we update the stack by the constant. */
5514 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5515 while (probed + 8192 < INTVAL (operands[1]))
5516 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5518 if (probed + 4096 < INTVAL (operands[1]))
5519 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5522 operands[1] = GEN_INT (- INTVAL (operands[1]));
5523 operands[2] = virtual_stack_dynamic_rtx;
5528 rtx loop_label = gen_label_rtx ();
5529 rtx want = gen_reg_rtx (Pmode);
5530 rtx tmp = gen_reg_rtx (Pmode);
5533 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5534 force_reg (Pmode, operands[1])));
5535 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5537 if (GET_CODE (operands[1]) != CONST_INT)
5539 out_label = gen_label_rtx ();
5540 emit_insn (gen_cmpdi (want, tmp));
5541 emit_jump_insn (gen_bgeu (out_label));
5544 emit_label (loop_label);
5545 memref = gen_rtx_MEM (DImode, tmp);
5546 MEM_VOLATILE_P (memref) = 1;
5547 emit_move_insn (memref, const0_rtx);
5548 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5549 emit_insn (gen_cmpdi (tmp, want));
5550 emit_jump_insn (gen_bgtu (loop_label));
5552 memref = gen_rtx_MEM (DImode, want);
5553 MEM_VOLATILE_P (memref) = 1;
5554 emit_move_insn (memref, const0_rtx);
5557 emit_label (out_label);
5559 emit_move_insn (stack_pointer_rtx, want);
5560 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5565 ;; This is used by alpha_expand_prolog to do the same thing as above,
5566 ;; except we cannot at that time generate new basic blocks, so we hide
5567 ;; the loop in this one insn.
5569 (define_insn "prologue_stack_probe_loop"
5570 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5571 (match_operand:DI 1 "register_operand" "r")] 5)]
5575 operands[2] = gen_label_rtx ();
5576 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5577 CODE_LABEL_NUMBER (operands[2]));
5579 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5581 [(set_attr "length" "16")
5582 (set_attr "type" "multi")])
5584 (define_expand "prologue"
5585 [(clobber (const_int 0))]
5589 alpha_expand_prologue ();
5593 ;; These take care of emitting the ldgp insn in the prologue. This will be
5594 ;; an lda/ldah pair and we want to align them properly. So we have two
5595 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
5596 ;; and the second of which emits nothing. However, both are marked as type
5597 ;; IADD (the default) so the alignment code in alpha.c does the right thing
5600 (define_expand "prologue_ldgp"
5601 [(unspec_volatile [(const_int 0)] 9)
5602 (unspec_volatile [(const_int 0)] 10)]
5606 (define_insn "*prologue_ldgp_1"
5607 [(unspec_volatile [(const_int 0)] 9)]
5608 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5609 "ldgp $29,0($27)\\n$%~..ng:")
5611 (define_insn "*prologue_ldgp_2"
5612 [(unspec_volatile [(const_int 0)] 10)]
5613 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5616 (define_insn "init_fp"
5617 [(set (match_operand:DI 0 "register_operand" "=r")
5618 (match_operand:DI 1 "register_operand" "r"))
5619 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5623 (define_expand "epilogue"
5628 alpha_expand_epilogue ();
5631 (define_expand "sibcall_epilogue"
5633 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
5636 alpha_expand_epilogue ();
5640 (define_expand "eh_epilogue"
5641 [(use (match_operand:DI 0 "register_operand" "r"))
5642 (use (match_operand:DI 1 "register_operand" "r"))
5643 (use (match_operand:DI 2 "register_operand" "r"))]
5647 cfun->machine->eh_epilogue_sp_ofs = operands[1];
5648 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5650 rtx ra = gen_rtx_REG (Pmode, 26);
5651 emit_move_insn (ra, operands[2]);
5656 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5657 ;; the frame size into a register. We use this pattern to ensure
5658 ;; we get lda instead of addq.
5659 (define_insn "nt_lda"
5660 [(set (match_operand:DI 0 "register_operand" "=r")
5661 (unspec:DI [(match_dup 0)
5662 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5666 (define_expand "builtin_longjmp"
5667 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5668 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5671 /* The elements of the buffer are, in order: */
5672 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5673 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5674 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5675 rtx pv = gen_rtx_REG (Pmode, 27);
5677 /* This bit is the same as expand_builtin_longjmp. */
5678 emit_move_insn (hard_frame_pointer_rtx, fp);
5679 emit_move_insn (pv, lab);
5680 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5681 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5682 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5684 /* Load the label we are jumping through into $27 so that we know
5685 where to look for it when we get back to setjmp's function for
5686 restoring the gp. */
5687 emit_indirect_jump (pv);
5691 (define_insn "builtin_setjmp_receiver"
5692 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5693 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5694 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5695 [(set_attr "length" "8")
5696 (set_attr "type" "multi")])
5699 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5700 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5701 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5702 [(set_attr "length" "12")
5703 (set_attr "type" "multi")])
5705 (define_insn "exception_receiver"
5706 [(unspec_volatile [(const_int 0)] 7)]
5707 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5708 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5709 [(set_attr "length" "12")
5710 (set_attr "type" "multi")])
5712 (define_expand "nonlocal_goto_receiver"
5713 [(unspec_volatile [(const_int 0)] 1)
5714 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5715 (unspec_volatile [(const_int 0)] 1)
5720 (define_insn "arg_home"
5721 [(unspec [(const_int 0)] 0)
5736 (clobber (mem:BLK (const_int 0)))
5737 (clobber (reg:DI 24))
5738 (clobber (reg:DI 25))
5739 (clobber (reg:DI 0))]
5741 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5742 [(set_attr "length" "16")
5743 (set_attr "type" "multi")])
5745 ;; Close the trap shadow of preceeding instructions. This is generated
5748 (define_insn "trapb"
5749 [(unspec_volatile [(const_int 0)] 4)]
5752 [(set_attr "type" "misc")])
5754 ;; No-op instructions used by machine-dependant reorg to preserve
5755 ;; alignment for instruction issue.
5761 [(set_attr "type" "ilog")])
5767 [(set_attr "type" "fcpys")])
5774 (define_insn "realign"
5775 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5777 ".align %0 #realign")
5779 ;; The call patterns are at the end of the file because their
5780 ;; wildcard operand0 interferes with nice recognition.
5782 (define_insn "*call_value_osf_1"
5783 [(set (match_operand 0 "" "")
5784 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5785 (match_operand 2 "" "")))
5786 (clobber (reg:DI 27))
5787 (clobber (reg:DI 26))]
5788 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5790 jsr $26,($27),0\;ldgp $29,0($26)
5792 jsr $26,%1\;ldgp $29,0($26)"
5793 [(set_attr "type" "jsr")
5794 (set_attr "length" "12,*,16")])
5796 (define_insn "*sibcall_value_osf_1"
5797 [(set (match_operand 0 "" "")
5798 (call (mem:DI (match_operand:DI 1 "call_operand" "R,i"))
5799 (match_operand 2 "" "")))]
5800 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5804 [(set_attr "type" "jsr")
5805 (set_attr "length" "*,8")])
5807 (define_insn "*call_value_nt_1"
5808 [(set (match_operand 0 "" "")
5809 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5810 (match_operand 2 "" "")))
5811 (clobber (reg:DI 26))]
5817 [(set_attr "type" "jsr")
5818 (set_attr "length" "*,*,12")])
5820 (define_insn "*call_value_vms_1"
5821 [(set (match_operand 0 "" "")
5822 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
5823 (match_operand 2 "" "")))
5824 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
5827 (clobber (reg:DI 27))]
5830 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
5831 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
5832 [(set_attr "type" "jsr")
5833 (set_attr "length" "12,16")])
5835 ;; Peepholes go at the end.
5837 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5838 ;; reload when converting fp->int.
5841 [(set (match_operand:SI 0 "hard_int_register_operand" "")
5842 (match_operand:SI 1 "memory_operand" ""))
5843 (set (match_operand:DI 2 "hard_int_register_operand" "")
5844 (sign_extend:DI (match_dup 0)))]
5845 "true_regnum (operands[0]) == true_regnum (operands[2])
5846 || peep2_reg_dead_p (2, operands[0])"
5848 (sign_extend:DI (match_dup 1)))]
5852 [(set (match_operand:SI 0 "hard_int_register_operand" "")
5853 (match_operand:SI 1 "hard_fp_register_operand" ""))
5854 (set (match_operand:DI 2 "hard_int_register_operand" "")
5855 (sign_extend:DI (match_dup 0)))]
5857 && (true_regnum (operands[0]) == true_regnum (operands[2])
5858 || peep2_reg_dead_p (2, operands[0]))"
5860 (sign_extend:DI (match_dup 1)))]
5864 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
5865 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
5866 (set (match_operand:DI 2 "hard_int_register_operand" "")
5868 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
5870 (sign_extend:DI (match_dup 1)))]