1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
48 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
49 (UNSPECV_LONGJMP 3) ; builtin_longjmp
51 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
53 (UNSPECV_EHR 7) ; exception_receiver
57 (UNSPECV_PLDGP2 11) ; prologue ldgp
60 ;; Where necessary, the suffixes _le and _be are used to distinguish between
61 ;; little-endian and big-endian patterns.
63 ;; Note that the Unicos/Mk assembler does not support the following
64 ;; opcodes: mov, fmov, nop, fnop, unop.
66 ;; Processor type -- this attribute must exactly match the processor_type
67 ;; enumeration in alpha.h.
69 (define_attr "cpu" "ev4,ev5,ev6"
70 (const (symbol_ref "alpha_cpu")))
72 ;; Define an insn type attribute. This is used in function unit delay
73 ;; computations, among other purposes. For the most part, we use the names
74 ;; defined in the EV4 documentation, but add a few that we have to know about
78 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
79 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
80 (const_string "iadd"))
82 ;; Describe a user's asm statement.
83 (define_asm_attributes
84 [(set_attr "type" "multi")])
86 ;; Define the operand size an insn operates on. Used primarily by mul
87 ;; and div operations that have size dependant timings.
89 (define_attr "opsize" "si,di,udi"
92 ;; The TRAP attribute marks instructions that may generate traps
93 ;; (which are imprecise and may need a trapb if software completion
96 (define_attr "trap" "no,yes"
99 ;; The ROUND_SUFFIX attribute marks which instructions require a
100 ;; rounding-mode suffix. The value NONE indicates no suffix,
101 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
103 (define_attr "round_suffix" "none,normal,c"
104 (const_string "none"))
106 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
108 ;; SU accepts only /su (cmpt et al)
109 ;; SUI accepts only /sui (cvtqt and cvtqs)
110 ;; V_SV accepts /v and /sv (cvtql only)
111 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
112 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
114 ;; The actual suffix emitted is controled by alpha_fptm.
116 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
117 (const_string "none"))
119 ;; The length of an instruction sequence in bytes.
121 (define_attr "length" ""
124 ;; On EV4 there are two classes of resources to consider: resources needed
125 ;; to issue, and resources needed to execute. IBUS[01] are in the first
126 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
127 ;; (There are a few other register-like resources, but ...)
129 ; First, describe all of the issue constraints with single cycle delays.
130 ; All insns need a bus, but all except loads require one or the other.
131 (define_function_unit "ev4_ibus0" 1 0
132 (and (eq_attr "cpu" "ev4")
133 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
136 (define_function_unit "ev4_ibus1" 1 0
137 (and (eq_attr "cpu" "ev4")
138 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
141 ; Memory delivers its result in three cycles. Actually return one and
142 ; take care of this in adjust_cost, since we want to handle user-defined
144 (define_function_unit "ev4_abox" 1 0
145 (and (eq_attr "cpu" "ev4")
146 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
149 ; Branches have no delay cost, but do tie up the unit for two cycles.
150 (define_function_unit "ev4_bbox" 1 1
151 (and (eq_attr "cpu" "ev4")
152 (eq_attr "type" "ibr,fbr,jsr"))
155 ; Arithmetic insns are normally have their results available after
156 ; two cycles. There are a number of exceptions. They are encoded in
157 ; ADJUST_COST. Some of the other insns have similar exceptions.
158 (define_function_unit "ev4_ebox" 1 0
159 (and (eq_attr "cpu" "ev4")
160 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
163 (define_function_unit "imul" 1 0
164 (and (eq_attr "cpu" "ev4")
165 (and (eq_attr "type" "imul")
166 (eq_attr "opsize" "si")))
169 (define_function_unit "imul" 1 0
170 (and (eq_attr "cpu" "ev4")
171 (and (eq_attr "type" "imul")
172 (eq_attr "opsize" "!si")))
175 (define_function_unit "ev4_fbox" 1 0
176 (and (eq_attr "cpu" "ev4")
177 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
180 (define_function_unit "fdiv" 1 0
181 (and (eq_attr "cpu" "ev4")
182 (and (eq_attr "type" "fdiv")
183 (eq_attr "opsize" "si")))
186 (define_function_unit "fdiv" 1 0
187 (and (eq_attr "cpu" "ev4")
188 (and (eq_attr "type" "fdiv")
189 (eq_attr "opsize" "di")))
192 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
194 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
195 ;; with the combined resource EBOX.
197 (define_function_unit "ev5_ebox" 2 0
198 (and (eq_attr "cpu" "ev5")
199 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
202 ; Memory takes at least 2 clocks. Return one from here and fix up with
203 ; user-defined latencies in adjust_cost.
204 (define_function_unit "ev5_ebox" 2 0
205 (and (eq_attr "cpu" "ev5")
206 (eq_attr "type" "ild,fld,ldsym"))
209 ; Loads can dual issue with one another, but loads and stores do not mix.
210 (define_function_unit "ev5_e0" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (eq_attr "type" "ild,fld,ldsym"))
214 [(eq_attr "type" "ist,fst")])
216 ; Stores, shifts, multiplies can only issue to E0
217 (define_function_unit "ev5_e0" 1 0
218 (and (eq_attr "cpu" "ev5")
219 (eq_attr "type" "ist,fst,shift,imul"))
222 ; Motion video insns also issue only to E0, and take two ticks.
223 (define_function_unit "ev5_e0" 1 0
224 (and (eq_attr "cpu" "ev5")
225 (eq_attr "type" "mvi"))
228 ; Conditional moves always take 2 ticks.
229 (define_function_unit "ev5_ebox" 2 0
230 (and (eq_attr "cpu" "ev5")
231 (eq_attr "type" "icmov"))
234 ; Branches can only issue to E1
235 (define_function_unit "ev5_e1" 1 0
236 (and (eq_attr "cpu" "ev5")
237 (eq_attr "type" "ibr,jsr"))
240 ; Multiplies also use the integer multiplier.
241 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
242 ; cycles before an integer multiplication completes."
243 (define_function_unit "imul" 1 0
244 (and (eq_attr "cpu" "ev5")
245 (and (eq_attr "type" "imul")
246 (eq_attr "opsize" "si")))
249 (define_function_unit "imul" 1 0
250 (and (eq_attr "cpu" "ev5")
251 (and (eq_attr "type" "imul")
252 (eq_attr "opsize" "di")))
255 (define_function_unit "imul" 1 0
256 (and (eq_attr "cpu" "ev5")
257 (and (eq_attr "type" "imul")
258 (eq_attr "opsize" "udi")))
261 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
262 ;; on either so we have to play the game again.
264 (define_function_unit "ev5_fbox" 2 0
265 (and (eq_attr "cpu" "ev5")
266 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
269 (define_function_unit "ev5_fm" 1 0
270 (and (eq_attr "cpu" "ev5")
271 (eq_attr "type" "fmul"))
274 ; Add and cmov as you would expect; fbr never produces a result;
275 ; fdiv issues through fa to the divider,
276 (define_function_unit "ev5_fa" 1 0
277 (and (eq_attr "cpu" "ev5")
278 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
281 ; ??? How to: "No instruction can be issued to pipe FA exactly five
282 ; cycles before a floating point divide completes."
283 (define_function_unit "fdiv" 1 0
284 (and (eq_attr "cpu" "ev5")
285 (and (eq_attr "type" "fdiv")
286 (eq_attr "opsize" "si")))
287 15 15) ; 15 to 31 data dependant
289 (define_function_unit "fdiv" 1 0
290 (and (eq_attr "cpu" "ev5")
291 (and (eq_attr "type" "fdiv")
292 (eq_attr "opsize" "di")))
293 22 22) ; 22 to 60 data dependant
295 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
297 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
298 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
300 ;; Conditional moves decompose into two independant primitives, each
301 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
303 (define_function_unit "ev6_ebox" 4 0
304 (and (eq_attr "cpu" "ev6")
305 (eq_attr "type" "icmov"))
308 (define_function_unit "ev6_ebox" 4 0
309 (and (eq_attr "cpu" "ev6")
310 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
313 ;; Integer loads take at least 3 clocks, and only issue to lower units.
314 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
315 (define_function_unit "ev6_l" 2 0
316 (and (eq_attr "cpu" "ev6")
317 (eq_attr "type" "ild,ldsym,ist,fst"))
320 ;; FP loads take at least 4 clocks. Return two from here...
321 (define_function_unit "ev6_l" 2 0
322 (and (eq_attr "cpu" "ev6")
323 (eq_attr "type" "fld"))
326 ;; Motion video insns also issue only to U0, and take three ticks.
327 (define_function_unit "ev6_u0" 1 0
328 (and (eq_attr "cpu" "ev6")
329 (eq_attr "type" "mvi"))
332 (define_function_unit "ev6_u" 2 0
333 (and (eq_attr "cpu" "ev6")
334 (eq_attr "type" "mvi"))
337 ;; Shifts issue to either upper pipe.
338 (define_function_unit "ev6_u" 2 0
339 (and (eq_attr "cpu" "ev6")
340 (eq_attr "type" "shift"))
343 ;; Multiplies issue only to U1, and all take 7 ticks.
344 ;; Rather than create a new function unit just for U1, reuse IMUL
345 (define_function_unit "imul" 1 0
346 (and (eq_attr "cpu" "ev6")
347 (eq_attr "type" "imul"))
350 (define_function_unit "ev6_u" 2 0
351 (and (eq_attr "cpu" "ev6")
352 (eq_attr "type" "imul"))
355 ;; Branches issue to either upper pipe
356 (define_function_unit "ev6_u" 2 0
357 (and (eq_attr "cpu" "ev6")
358 (eq_attr "type" "ibr"))
361 ;; Calls only issue to L0.
362 (define_function_unit "ev6_l0" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (eq_attr "type" "jsr"))
367 (define_function_unit "ev6_l" 2 0
368 (and (eq_attr "cpu" "ev6")
369 (eq_attr "type" "jsr"))
372 ;; Ftoi/itof only issue to lower pipes
373 (define_function_unit "ev6_l" 2 0
374 (and (eq_attr "cpu" "ev6")
375 (eq_attr "type" "ftoi"))
378 (define_function_unit "ev6_l" 2 0
379 (and (eq_attr "cpu" "ev6")
380 (eq_attr "type" "itof"))
383 ;; For the FPU we are very similar to EV5, except there's no insn that
384 ;; can issue to fm & fa, so we get to leave that out.
386 (define_function_unit "ev6_fm" 1 0
387 (and (eq_attr "cpu" "ev6")
388 (eq_attr "type" "fmul"))
391 (define_function_unit "ev6_fa" 1 0
392 (and (eq_attr "cpu" "ev6")
393 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
396 (define_function_unit "ev6_fa" 1 0
397 (and (eq_attr "cpu" "ev6")
398 (eq_attr "type" "fcmov"))
401 (define_function_unit "fdiv" 1 0
402 (and (eq_attr "cpu" "ev6")
403 (and (eq_attr "type" "fdiv")
404 (eq_attr "opsize" "si")))
407 (define_function_unit "fdiv" 1 0
408 (and (eq_attr "cpu" "ev6")
409 (and (eq_attr "type" "fdiv")
410 (eq_attr "opsize" "di")))
413 (define_function_unit "fsqrt" 1 0
414 (and (eq_attr "cpu" "ev6")
415 (and (eq_attr "type" "fsqrt")
416 (eq_attr "opsize" "si")))
419 (define_function_unit "fsqrt" 1 0
420 (and (eq_attr "cpu" "ev6")
421 (and (eq_attr "type" "fsqrt")
422 (eq_attr "opsize" "di")))
425 ; ??? The FPU communicates with memory and the integer register file
426 ; via two fp store units. We need a slot in the fst immediately, and
427 ; a slot in LOW after the operand data is ready. At which point the
428 ; data may be moved either to the store queue or the integer register
429 ; file and the insn retired.
432 ;; First define the arithmetic insns. Note that the 32-bit forms also
435 ;; Handle 32-64 bit extension from memory to a floating point register
436 ;; specially, since this ocurrs frequently in int->double conversions.
438 ;; Note that while we must retain the =f case in the insn for reload's
439 ;; benefit, it should be eliminated after reload, so we should never emit
440 ;; code for that case. But we don't reject the possibility.
442 (define_expand "extendsidi2"
443 [(set (match_operand:DI 0 "register_operand" "")
444 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
448 (define_insn "*extendsidi2_nofix"
449 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
451 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
457 lds %0,%1\;cvtlq %0,%0"
458 [(set_attr "type" "iadd,ild,fadd,fld")
459 (set_attr "length" "*,*,*,8")])
461 (define_insn "*extendsidi2_fix"
462 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
464 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
471 lds %0,%1\;cvtlq %0,%0"
472 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
473 (set_attr "length" "*,*,*,*,8")])
475 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
477 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
478 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
480 [(set (match_dup 2) (match_dup 1))
481 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
482 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
484 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
485 ;; reload when converting fp->int.
488 [(set (match_operand:SI 0 "hard_int_register_operand" "")
489 (match_operand:SI 1 "memory_operand" ""))
490 (set (match_operand:DI 2 "hard_int_register_operand" "")
491 (sign_extend:DI (match_dup 0)))]
492 "true_regnum (operands[0]) == true_regnum (operands[2])
493 || peep2_reg_dead_p (2, operands[0])"
495 (sign_extend:DI (match_dup 1)))]
499 [(set (match_operand:SI 0 "hard_int_register_operand" "")
500 (match_operand:SI 1 "hard_fp_register_operand" ""))
501 (set (match_operand:DI 2 "hard_int_register_operand" "")
502 (sign_extend:DI (match_dup 0)))]
504 && (true_regnum (operands[0]) == true_regnum (operands[2])
505 || peep2_reg_dead_p (2, operands[0]))"
507 (sign_extend:DI (match_dup 1)))]
511 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
512 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
513 (set (match_operand:DI 2 "hard_int_register_operand" "")
515 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
517 (sign_extend:DI (match_dup 1)))]
520 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
521 ;; generates better code. We have the anonymous addsi3 pattern below in
522 ;; case combine wants to make it.
523 (define_expand "addsi3"
524 [(set (match_operand:SI 0 "register_operand" "")
525 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
526 (match_operand:SI 2 "add_operand" "")))]
531 rtx op1 = gen_lowpart (DImode, operands[1]);
532 rtx op2 = gen_lowpart (DImode, operands[2]);
534 if (! cse_not_expected)
536 rtx tmp = gen_reg_rtx (DImode);
537 emit_insn (gen_adddi3 (tmp, op1, op2));
538 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
541 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
546 (define_insn "*addsi_internal"
547 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
548 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
549 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
558 [(set (match_operand:SI 0 "register_operand" "")
559 (plus:SI (match_operand:SI 1 "register_operand" "")
560 (match_operand:SI 2 "const_int_operand" "")))]
561 "! add_operand (operands[2], SImode)"
562 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
563 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
565 HOST_WIDE_INT val = INTVAL (operands[2]);
566 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
567 HOST_WIDE_INT rest = val - low;
569 operands[3] = GEN_INT (rest);
570 operands[4] = GEN_INT (low);
573 (define_insn "*addsi_se"
574 [(set (match_operand:DI 0 "register_operand" "=r,r")
576 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
577 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
584 [(set (match_operand:DI 0 "register_operand" "")
586 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
587 (match_operand:SI 2 "const_int_operand" ""))))
588 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
589 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
590 && INTVAL (operands[2]) % 4 == 0"
591 [(set (match_dup 3) (match_dup 4))
592 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
596 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
602 operands[4] = GEN_INT (val);
603 operands[5] = GEN_INT (mult);
607 [(set (match_operand:DI 0 "register_operand" "")
609 (plus:SI (match_operator:SI 1 "comparison_operator"
610 [(match_operand 2 "" "")
611 (match_operand 3 "" "")])
612 (match_operand:SI 4 "add_operand" ""))))
613 (clobber (match_operand:DI 5 "register_operand" ""))]
615 [(set (match_dup 5) (match_dup 6))
616 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
618 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
619 operands[2], operands[3]);
620 operands[7] = gen_lowpart (SImode, operands[5]);
623 (define_insn "addvsi3"
624 [(set (match_operand:SI 0 "register_operand" "=r,r")
625 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
626 (match_operand:SI 2 "sext_add_operand" "rI,O")))
627 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
628 (sign_extend:DI (match_dup 2)))
629 (sign_extend:DI (plus:SI (match_dup 1)
637 (define_expand "adddi3"
638 [(set (match_operand:DI 0 "register_operand" "")
639 (plus:DI (match_operand:DI 1 "register_operand" "")
640 (match_operand:DI 2 "add_operand" "")))]
644 (define_insn "*adddi_er_high_l"
645 [(set (match_operand:DI 0 "register_operand" "=r")
646 (plus:DI (match_operand:DI 1 "register_operand" "r")
647 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
648 "TARGET_EXPLICIT_RELOCS"
649 "ldah %0,%2(%1)\t\t!gprelhigh")
651 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
652 ;; With complications like
654 ;; The NT stack unwind code can't handle a subq to adjust the stack
655 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
656 ;; the exception handling code will loop if a subq is used and an
659 ;; The 19980616 change to emit prologues as RTL also confused some
660 ;; versions of GDB, which also interprets prologues. This has been
661 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
664 ;; and the fact that the three insns schedule exactly the same, it's
665 ;; just not worth the effort.
667 (define_insn "*adddi_internal"
668 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
669 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
670 (match_operand:DI 2 "add_operand" "r,K,L")))]
677 ;; ??? Allow large constants when basing off the frame pointer or some
678 ;; virtual register that may eliminate to the frame pointer. This is
679 ;; done because register elimination offsets will change the hi/lo split,
680 ;; and if we split before reload, we will require additional instructions.
682 (define_insn "*adddi_fp_hack"
683 [(set (match_operand:DI 0 "register_operand" "=r")
684 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
685 (match_operand:DI 2 "const_int_operand" "n")))]
686 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
687 && INTVAL (operands[2]) >= 0
688 /* This is the largest constant an lda+ldah pair can add, minus
689 an upper bound on the displacement between SP and AP during
690 register elimination. See INITIAL_ELIMINATION_OFFSET. */
691 && INTVAL (operands[2])
693 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
694 - ALPHA_ROUND(current_function_outgoing_args_size)
695 - (ALPHA_ROUND (get_frame_size ()
696 + max_reg_num () * UNITS_PER_WORD
697 + current_function_pretend_args_size)
698 - current_function_pretend_args_size))"
701 ;; Don't do this if we are adjusting SP since we don't want to do it
702 ;; in two steps. Don't split FP sources for the reason listed above.
704 [(set (match_operand:DI 0 "register_operand" "")
705 (plus:DI (match_operand:DI 1 "register_operand" "")
706 (match_operand:DI 2 "const_int_operand" "")))]
707 "! add_operand (operands[2], DImode)
708 && operands[0] != stack_pointer_rtx
709 && operands[1] != frame_pointer_rtx
710 && operands[1] != arg_pointer_rtx"
711 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
712 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
714 HOST_WIDE_INT val = INTVAL (operands[2]);
715 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
716 HOST_WIDE_INT rest = val - low;
718 operands[4] = GEN_INT (low);
719 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
720 operands[3] = GEN_INT (rest);
721 else if (! no_new_pseudos)
723 operands[3] = gen_reg_rtx (DImode);
724 emit_move_insn (operands[3], operands[2]);
725 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
732 (define_insn "*saddl"
733 [(set (match_operand:SI 0 "register_operand" "=r,r")
734 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
735 (match_operand:SI 2 "const48_operand" "I,I"))
736 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
742 (define_insn "*saddl_se"
743 [(set (match_operand:DI 0 "register_operand" "=r,r")
745 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
746 (match_operand:SI 2 "const48_operand" "I,I"))
747 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
754 [(set (match_operand:DI 0 "register_operand" "")
756 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
757 [(match_operand 2 "" "")
758 (match_operand 3 "" "")])
759 (match_operand:SI 4 "const48_operand" ""))
760 (match_operand:SI 5 "sext_add_operand" ""))))
761 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
763 [(set (match_dup 6) (match_dup 7))
765 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
768 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
769 operands[2], operands[3]);
770 operands[8] = gen_lowpart (SImode, operands[6]);
773 (define_insn "*saddq"
774 [(set (match_operand:DI 0 "register_operand" "=r,r")
775 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
776 (match_operand:DI 2 "const48_operand" "I,I"))
777 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
783 (define_insn "addvdi3"
784 [(set (match_operand:DI 0 "register_operand" "=r,r")
785 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
786 (match_operand:DI 2 "sext_add_operand" "rI,O")))
787 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
788 (sign_extend:TI (match_dup 2)))
789 (sign_extend:TI (plus:DI (match_dup 1)
797 (define_insn "negsi2"
798 [(set (match_operand:SI 0 "register_operand" "=r")
799 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
803 (define_insn "*negsi_se"
804 [(set (match_operand:DI 0 "register_operand" "=r")
805 (sign_extend:DI (neg:SI
806 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
810 (define_insn "negvsi2"
811 [(set (match_operand:SI 0 "register_operand" "=r")
812 (neg:SI (match_operand:SI 1 "register_operand" "r")))
813 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
814 (sign_extend:DI (neg:SI (match_dup 1))))
819 (define_insn "negdi2"
820 [(set (match_operand:DI 0 "register_operand" "=r")
821 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
825 (define_insn "negvdi2"
826 [(set (match_operand:DI 0 "register_operand" "=r")
827 (neg:DI (match_operand:DI 1 "register_operand" "r")))
828 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
829 (sign_extend:TI (neg:DI (match_dup 1))))
834 (define_expand "subsi3"
835 [(set (match_operand:SI 0 "register_operand" "")
836 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
837 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
842 rtx op1 = gen_lowpart (DImode, operands[1]);
843 rtx op2 = gen_lowpart (DImode, operands[2]);
845 if (! cse_not_expected)
847 rtx tmp = gen_reg_rtx (DImode);
848 emit_insn (gen_subdi3 (tmp, op1, op2));
849 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
852 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
857 (define_insn "*subsi_internal"
858 [(set (match_operand:SI 0 "register_operand" "=r")
859 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
860 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
864 (define_insn "*subsi_se"
865 [(set (match_operand:DI 0 "register_operand" "=r")
866 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
867 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
871 (define_insn "subvsi3"
872 [(set (match_operand:SI 0 "register_operand" "=r")
873 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
874 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
875 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
876 (sign_extend:DI (match_dup 2)))
877 (sign_extend:DI (minus:SI (match_dup 1)
883 (define_insn "subdi3"
884 [(set (match_operand:DI 0 "register_operand" "=r")
885 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
886 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
890 (define_insn "*ssubl"
891 [(set (match_operand:SI 0 "register_operand" "=r")
892 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
893 (match_operand:SI 2 "const48_operand" "I"))
894 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
898 (define_insn "*ssubl_se"
899 [(set (match_operand:DI 0 "register_operand" "=r")
901 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
902 (match_operand:SI 2 "const48_operand" "I"))
903 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
907 (define_insn "*ssubq"
908 [(set (match_operand:DI 0 "register_operand" "=r")
909 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
910 (match_operand:DI 2 "const48_operand" "I"))
911 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
915 (define_insn "subvdi3"
916 [(set (match_operand:DI 0 "register_operand" "=r")
917 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
918 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
919 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
920 (sign_extend:TI (match_dup 2)))
921 (sign_extend:TI (minus:DI (match_dup 1)
927 ;; The Unicos/Mk assembler doesn't support mull.
929 (define_insn "mulsi3"
930 [(set (match_operand:SI 0 "register_operand" "=r")
931 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
932 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
933 "!TARGET_ABI_UNICOSMK"
935 [(set_attr "type" "imul")
936 (set_attr "opsize" "si")])
938 (define_insn "*mulsi_se"
939 [(set (match_operand:DI 0 "register_operand" "=r")
941 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
942 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
943 "!TARGET_ABI_UNICOSMK"
945 [(set_attr "type" "imul")
946 (set_attr "opsize" "si")])
948 (define_insn "mulvsi3"
949 [(set (match_operand:SI 0 "register_operand" "=r")
950 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
951 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
952 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
953 (sign_extend:DI (match_dup 2)))
954 (sign_extend:DI (mult:SI (match_dup 1)
957 "!TARGET_ABI_UNICOSMK"
959 [(set_attr "type" "imul")
960 (set_attr "opsize" "si")])
962 (define_insn "muldi3"
963 [(set (match_operand:DI 0 "register_operand" "=r")
964 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
965 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
968 [(set_attr "type" "imul")])
970 (define_insn "mulvdi3"
971 [(set (match_operand:DI 0 "register_operand" "=r")
972 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
973 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
974 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
975 (sign_extend:TI (match_dup 2)))
976 (sign_extend:TI (mult:DI (match_dup 1)
981 [(set_attr "type" "imul")])
983 (define_insn "umuldi3_highpart"
984 [(set (match_operand:DI 0 "register_operand" "=r")
987 (mult:TI (zero_extend:TI
988 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
990 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
994 [(set_attr "type" "imul")
995 (set_attr "opsize" "udi")])
997 (define_insn "*umuldi3_highpart_const"
998 [(set (match_operand:DI 0 "register_operand" "=r")
1001 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
1002 (match_operand:TI 2 "cint8_operand" "I"))
1006 [(set_attr "type" "imul")
1007 (set_attr "opsize" "udi")])
1009 ;; The divide and remainder operations take their inputs from r24 and
1010 ;; r25, put their output in r27, and clobber r23 and r28 on all
1011 ;; systems except Unicos/Mk. On Unicos, the standard library provides
1012 ;; subroutines which use the standard calling convention and work on
1015 ;; ??? Force sign-extension here because some versions of OSF/1 and
1016 ;; Interix/NT don't do the right thing if the inputs are not properly
1017 ;; sign-extended. But Linux, for instance, does not have this
1018 ;; problem. Is it worth the complication here to eliminate the sign
1021 (define_expand "divsi3"
1023 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1025 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1026 (parallel [(set (match_dup 5)
1027 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
1028 (clobber (reg:DI 23))
1029 (clobber (reg:DI 28))])
1030 (set (match_operand:SI 0 "nonimmediate_operand" "")
1031 (subreg:SI (match_dup 5) 0))]
1032 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1034 operands[3] = gen_reg_rtx (DImode);
1035 operands[4] = gen_reg_rtx (DImode);
1036 operands[5] = gen_reg_rtx (DImode);
1039 (define_expand "udivsi3"
1041 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1043 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1044 (parallel [(set (match_dup 5)
1045 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
1046 (clobber (reg:DI 23))
1047 (clobber (reg:DI 28))])
1048 (set (match_operand:SI 0 "nonimmediate_operand" "")
1049 (subreg:SI (match_dup 5) 0))]
1050 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1052 operands[3] = gen_reg_rtx (DImode);
1053 operands[4] = gen_reg_rtx (DImode);
1054 operands[5] = gen_reg_rtx (DImode);
1057 (define_expand "modsi3"
1059 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1061 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1062 (parallel [(set (match_dup 5)
1063 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
1064 (clobber (reg:DI 23))
1065 (clobber (reg:DI 28))])
1066 (set (match_operand:SI 0 "nonimmediate_operand" "")
1067 (subreg:SI (match_dup 5) 0))]
1068 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1070 operands[3] = gen_reg_rtx (DImode);
1071 operands[4] = gen_reg_rtx (DImode);
1072 operands[5] = gen_reg_rtx (DImode);
1075 (define_expand "umodsi3"
1077 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1079 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1080 (parallel [(set (match_dup 5)
1081 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
1082 (clobber (reg:DI 23))
1083 (clobber (reg:DI 28))])
1084 (set (match_operand:SI 0 "nonimmediate_operand" "")
1085 (subreg:SI (match_dup 5) 0))]
1086 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1088 operands[3] = gen_reg_rtx (DImode);
1089 operands[4] = gen_reg_rtx (DImode);
1090 operands[5] = gen_reg_rtx (DImode);
1093 (define_expand "divdi3"
1094 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1095 (div:DI (match_operand:DI 1 "register_operand" "")
1096 (match_operand:DI 2 "register_operand" "")))
1097 (clobber (reg:DI 23))
1098 (clobber (reg:DI 28))])]
1099 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1102 (define_expand "udivdi3"
1103 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1104 (udiv:DI (match_operand:DI 1 "register_operand" "")
1105 (match_operand:DI 2 "register_operand" "")))
1106 (clobber (reg:DI 23))
1107 (clobber (reg:DI 28))])]
1108 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1111 (define_expand "moddi3"
1112 [(use (match_operand:DI 0 "register_operand" ""))
1113 (use (match_operand:DI 1 "register_operand" ""))
1114 (use (match_operand:DI 2 "register_operand" ""))]
1115 "!TARGET_ABI_OPEN_VMS"
1117 if (TARGET_ABI_UNICOSMK)
1118 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
1120 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
1124 (define_expand "moddi3_dft"
1125 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1126 (mod:DI (match_operand:DI 1 "register_operand" "")
1127 (match_operand:DI 2 "register_operand" "")))
1128 (clobber (reg:DI 23))
1129 (clobber (reg:DI 28))])]
1130 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1133 ;; On Unicos/Mk, we do as the system's C compiler does:
1134 ;; compute the quotient, multiply and subtract.
1136 (define_expand "moddi3_umk"
1137 [(use (match_operand:DI 0 "register_operand" ""))
1138 (use (match_operand:DI 1 "register_operand" ""))
1139 (use (match_operand:DI 2 "register_operand" ""))]
1140 "TARGET_ABI_UNICOSMK"
1142 rtx div, mul = gen_reg_rtx (DImode);
1144 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
1145 NULL_RTX, 0, OPTAB_LIB);
1146 div = force_reg (DImode, div);
1147 emit_insn (gen_muldi3 (mul, operands[2], div));
1148 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1152 (define_expand "umoddi3"
1153 [(use (match_operand:DI 0 "register_operand" ""))
1154 (use (match_operand:DI 1 "register_operand" ""))
1155 (use (match_operand:DI 2 "register_operand" ""))]
1156 "! TARGET_ABI_OPEN_VMS"
1158 if (TARGET_ABI_UNICOSMK)
1159 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
1161 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
1165 (define_expand "umoddi3_dft"
1166 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1167 (umod:DI (match_operand:DI 1 "register_operand" "")
1168 (match_operand:DI 2 "register_operand" "")))
1169 (clobber (reg:DI 23))
1170 (clobber (reg:DI 28))])]
1171 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1174 (define_expand "umoddi3_umk"
1175 [(use (match_operand:DI 0 "register_operand" ""))
1176 (use (match_operand:DI 1 "register_operand" ""))
1177 (use (match_operand:DI 2 "register_operand" ""))]
1178 "TARGET_ABI_UNICOSMK"
1180 rtx div, mul = gen_reg_rtx (DImode);
1182 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
1183 NULL_RTX, 1, OPTAB_LIB);
1184 div = force_reg (DImode, div);
1185 emit_insn (gen_muldi3 (mul, operands[2], div));
1186 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1190 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1191 ;; expanded by the assembler.
1193 (define_insn "*divmodsi_internal_er"
1194 [(set (match_operand:DI 0 "register_operand" "=c")
1195 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1196 [(match_operand:DI 1 "register_operand" "a")
1197 (match_operand:DI 2 "register_operand" "b")])))
1198 (clobber (reg:DI 23))
1199 (clobber (reg:DI 28))]
1200 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1201 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1202 [(set_attr "type" "jsr")
1203 (set_attr "length" "8")])
1205 (define_insn "*divmodsi_internal"
1206 [(set (match_operand:DI 0 "register_operand" "=c")
1207 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1208 [(match_operand:DI 1 "register_operand" "a")
1209 (match_operand:DI 2 "register_operand" "b")])))
1210 (clobber (reg:DI 23))
1211 (clobber (reg:DI 28))]
1212 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1214 [(set_attr "type" "jsr")
1215 (set_attr "length" "8")])
1217 (define_insn "*divmoddi_internal_er"
1218 [(set (match_operand:DI 0 "register_operand" "=c")
1219 (match_operator:DI 3 "divmod_operator"
1220 [(match_operand:DI 1 "register_operand" "a")
1221 (match_operand:DI 2 "register_operand" "b")]))
1222 (clobber (reg:DI 23))
1223 (clobber (reg:DI 28))]
1224 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1225 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1226 [(set_attr "type" "jsr")
1227 (set_attr "length" "8")])
1229 (define_insn "*divmoddi_internal"
1230 [(set (match_operand:DI 0 "register_operand" "=c")
1231 (match_operator:DI 3 "divmod_operator"
1232 [(match_operand:DI 1 "register_operand" "a")
1233 (match_operand:DI 2 "register_operand" "b")]))
1234 (clobber (reg:DI 23))
1235 (clobber (reg:DI 28))]
1236 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1238 [(set_attr "type" "jsr")
1239 (set_attr "length" "8")])
1241 ;; Next are the basic logical operations. These only exist in DImode.
1243 (define_insn "anddi3"
1244 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1245 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1246 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1252 [(set_attr "type" "ilog,ilog,shift")])
1254 ;; There are times when we can split an AND into two AND insns. This occurs
1255 ;; when we can first clear any bytes and then clear anything else. For
1256 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1257 ;; Only do this when running on 64-bit host since the computations are
1258 ;; too messy otherwise.
1261 [(set (match_operand:DI 0 "register_operand" "")
1262 (and:DI (match_operand:DI 1 "register_operand" "")
1263 (match_operand:DI 2 "const_int_operand" "")))]
1264 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1265 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1266 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1268 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1269 unsigned HOST_WIDE_INT mask2 = mask1;
1272 /* For each byte that isn't all zeros, make it all ones. */
1273 for (i = 0; i < 64; i += 8)
1274 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1275 mask1 |= (HOST_WIDE_INT) 0xff << i;
1277 /* Now turn on any bits we've just turned off. */
1280 operands[3] = GEN_INT (mask1);
1281 operands[4] = GEN_INT (mask2);
1284 (define_expand "zero_extendqihi2"
1285 [(set (match_operand:HI 0 "register_operand" "")
1286 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1290 operands[1] = force_reg (QImode, operands[1]);
1293 (define_insn "*zero_extendqihi2_bwx"
1294 [(set (match_operand:HI 0 "register_operand" "=r,r")
1295 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1300 [(set_attr "type" "ilog,ild")])
1302 (define_insn "*zero_extendqihi2_nobwx"
1303 [(set (match_operand:HI 0 "register_operand" "=r")
1304 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1307 [(set_attr "type" "ilog")])
1309 (define_expand "zero_extendqisi2"
1310 [(set (match_operand:SI 0 "register_operand" "")
1311 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1315 operands[1] = force_reg (QImode, operands[1]);
1318 (define_insn "*zero_extendqisi2_bwx"
1319 [(set (match_operand:SI 0 "register_operand" "=r,r")
1320 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1325 [(set_attr "type" "ilog,ild")])
1327 (define_insn "*zero_extendqisi2_nobwx"
1328 [(set (match_operand:SI 0 "register_operand" "=r")
1329 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1332 [(set_attr "type" "ilog")])
1334 (define_expand "zero_extendqidi2"
1335 [(set (match_operand:DI 0 "register_operand" "")
1336 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1340 operands[1] = force_reg (QImode, operands[1]);
1343 (define_insn "*zero_extendqidi2_bwx"
1344 [(set (match_operand:DI 0 "register_operand" "=r,r")
1345 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1350 [(set_attr "type" "ilog,ild")])
1352 (define_insn "*zero_extendqidi2_nobwx"
1353 [(set (match_operand:DI 0 "register_operand" "=r")
1354 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1357 [(set_attr "type" "ilog")])
1359 (define_expand "zero_extendhisi2"
1360 [(set (match_operand:SI 0 "register_operand" "")
1361 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1365 operands[1] = force_reg (HImode, operands[1]);
1368 (define_insn "*zero_extendhisi2_bwx"
1369 [(set (match_operand:SI 0 "register_operand" "=r,r")
1370 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1375 [(set_attr "type" "shift,ild")])
1377 (define_insn "*zero_extendhisi2_nobwx"
1378 [(set (match_operand:SI 0 "register_operand" "=r")
1379 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1382 [(set_attr "type" "shift")])
1384 (define_expand "zero_extendhidi2"
1385 [(set (match_operand:DI 0 "register_operand" "")
1386 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1390 operands[1] = force_reg (HImode, operands[1]);
1393 (define_insn "*zero_extendhidi2_bwx"
1394 [(set (match_operand:DI 0 "register_operand" "=r,r")
1395 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1400 [(set_attr "type" "shift,ild")])
1402 (define_insn "*zero_extendhidi2_nobwx"
1403 [(set (match_operand:DI 0 "register_operand" "=r")
1404 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1407 [(set_attr "type" "shift")])
1409 (define_insn "zero_extendsidi2"
1410 [(set (match_operand:DI 0 "register_operand" "=r")
1411 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1414 [(set_attr "type" "shift")])
1416 (define_insn "andnotdi3"
1417 [(set (match_operand:DI 0 "register_operand" "=r")
1418 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1419 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1422 [(set_attr "type" "ilog")])
1424 (define_insn "iordi3"
1425 [(set (match_operand:DI 0 "register_operand" "=r,r")
1426 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1427 (match_operand:DI 2 "or_operand" "rI,N")))]
1432 [(set_attr "type" "ilog")])
1434 (define_insn "one_cmpldi2"
1435 [(set (match_operand:DI 0 "register_operand" "=r")
1436 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1439 [(set_attr "type" "ilog")])
1441 (define_insn "*iornot"
1442 [(set (match_operand:DI 0 "register_operand" "=r")
1443 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1444 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1447 [(set_attr "type" "ilog")])
1449 (define_insn "xordi3"
1450 [(set (match_operand:DI 0 "register_operand" "=r,r")
1451 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1452 (match_operand:DI 2 "or_operand" "rI,N")))]
1457 [(set_attr "type" "ilog")])
1459 (define_insn "*xornot"
1460 [(set (match_operand:DI 0 "register_operand" "=r")
1461 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1462 (match_operand:DI 2 "register_operand" "rI"))))]
1465 [(set_attr "type" "ilog")])
1467 ;; Handle the FFS insn iff we support CIX.
1469 (define_expand "ffsdi2"
1471 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1473 (plus:DI (match_dup 2) (const_int 1)))
1474 (set (match_operand:DI 0 "register_operand" "")
1475 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1476 (const_int 0) (match_dup 3)))]
1479 operands[2] = gen_reg_rtx (DImode);
1480 operands[3] = gen_reg_rtx (DImode);
1483 (define_insn "*cttz"
1484 [(set (match_operand:DI 0 "register_operand" "=r")
1485 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1488 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1489 ; reuse the existing type name.
1490 [(set_attr "type" "mvi")])
1492 ;; Next come the shifts and the various extract and insert operations.
1494 (define_insn "ashldi3"
1495 [(set (match_operand:DI 0 "register_operand" "=r,r")
1496 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1497 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1500 switch (which_alternative)
1503 if (operands[2] == const1_rtx)
1504 return "addq %r1,%r1,%0";
1506 return "s%P2addq %r1,0,%0";
1508 return "sll %r1,%2,%0";
1513 [(set_attr "type" "iadd,shift")])
1515 ;; ??? The following pattern is made by combine, but earlier phases
1516 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1517 ;; with this in a better way at some point.
1519 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1521 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1522 ;; (match_operand:DI 2 "const_int_operand" "P"))
1524 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1526 ;; if (operands[2] == const1_rtx)
1527 ;; return "addl %r1,%r1,%0";
1529 ;; return "s%P2addl %r1,0,%0";
1531 ;; [(set_attr "type" "iadd")])
1533 (define_insn "lshrdi3"
1534 [(set (match_operand:DI 0 "register_operand" "=r")
1535 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1536 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1539 [(set_attr "type" "shift")])
1541 (define_insn "ashrdi3"
1542 [(set (match_operand:DI 0 "register_operand" "=r")
1543 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1544 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1547 [(set_attr "type" "shift")])
1549 (define_expand "extendqihi2"
1551 (ashift:DI (match_operand:QI 1 "some_operand" "")
1553 (set (match_operand:HI 0 "register_operand" "")
1554 (ashiftrt:DI (match_dup 2)
1560 emit_insn (gen_extendqihi2x (operands[0],
1561 force_reg (QImode, operands[1])));
1565 /* If we have an unaligned MEM, extend to DImode (which we do
1566 specially) and then copy to the result. */
1567 if (unaligned_memory_operand (operands[1], HImode))
1569 rtx temp = gen_reg_rtx (DImode);
1571 emit_insn (gen_extendqidi2 (temp, operands[1]));
1572 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1576 operands[0] = gen_lowpart (DImode, operands[0]);
1577 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1578 operands[2] = gen_reg_rtx (DImode);
1581 (define_insn "extendqidi2x"
1582 [(set (match_operand:DI 0 "register_operand" "=r")
1583 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1586 [(set_attr "type" "shift")])
1588 (define_insn "extendhidi2x"
1589 [(set (match_operand:DI 0 "register_operand" "=r")
1590 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1593 [(set_attr "type" "shift")])
1595 (define_insn "extendqisi2x"
1596 [(set (match_operand:SI 0 "register_operand" "=r")
1597 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1600 [(set_attr "type" "shift")])
1602 (define_insn "extendhisi2x"
1603 [(set (match_operand:SI 0 "register_operand" "=r")
1604 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1607 [(set_attr "type" "shift")])
1609 (define_insn "extendqihi2x"
1610 [(set (match_operand:HI 0 "register_operand" "=r")
1611 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1614 [(set_attr "type" "shift")])
1616 (define_expand "extendqisi2"
1618 (ashift:DI (match_operand:QI 1 "some_operand" "")
1620 (set (match_operand:SI 0 "register_operand" "")
1621 (ashiftrt:DI (match_dup 2)
1627 emit_insn (gen_extendqisi2x (operands[0],
1628 force_reg (QImode, operands[1])));
1632 /* If we have an unaligned MEM, extend to a DImode form of
1633 the result (which we do specially). */
1634 if (unaligned_memory_operand (operands[1], QImode))
1636 rtx temp = gen_reg_rtx (DImode);
1638 emit_insn (gen_extendqidi2 (temp, operands[1]));
1639 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1643 operands[0] = gen_lowpart (DImode, operands[0]);
1644 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1645 operands[2] = gen_reg_rtx (DImode);
1648 (define_expand "extendqidi2"
1650 (ashift:DI (match_operand:QI 1 "some_operand" "")
1652 (set (match_operand:DI 0 "register_operand" "")
1653 (ashiftrt:DI (match_dup 2)
1659 emit_insn (gen_extendqidi2x (operands[0],
1660 force_reg (QImode, operands[1])));
1664 if (unaligned_memory_operand (operands[1], QImode))
1667 = gen_unaligned_extendqidi (operands[0],
1668 get_unaligned_address (operands[1], 1));
1670 alpha_set_memflags (seq, operands[1]);
1675 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1676 operands[2] = gen_reg_rtx (DImode);
1679 (define_expand "extendhisi2"
1681 (ashift:DI (match_operand:HI 1 "some_operand" "")
1683 (set (match_operand:SI 0 "register_operand" "")
1684 (ashiftrt:DI (match_dup 2)
1690 emit_insn (gen_extendhisi2x (operands[0],
1691 force_reg (HImode, operands[1])));
1695 /* If we have an unaligned MEM, extend to a DImode form of
1696 the result (which we do specially). */
1697 if (unaligned_memory_operand (operands[1], HImode))
1699 rtx temp = gen_reg_rtx (DImode);
1701 emit_insn (gen_extendhidi2 (temp, operands[1]));
1702 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1706 operands[0] = gen_lowpart (DImode, operands[0]);
1707 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1708 operands[2] = gen_reg_rtx (DImode);
1711 (define_expand "extendhidi2"
1713 (ashift:DI (match_operand:HI 1 "some_operand" "")
1715 (set (match_operand:DI 0 "register_operand" "")
1716 (ashiftrt:DI (match_dup 2)
1722 emit_insn (gen_extendhidi2x (operands[0],
1723 force_reg (HImode, operands[1])));
1727 if (unaligned_memory_operand (operands[1], HImode))
1730 = gen_unaligned_extendhidi (operands[0],
1731 get_unaligned_address (operands[1], 2));
1733 alpha_set_memflags (seq, operands[1]);
1738 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1739 operands[2] = gen_reg_rtx (DImode);
1742 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1743 ;; as a pattern saves one instruction. The code is similar to that for
1744 ;; the unaligned loads (see below).
1746 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1747 (define_expand "unaligned_extendqidi"
1748 [(use (match_operand:QI 0 "register_operand" ""))
1749 (use (match_operand:DI 1 "address_operand" ""))]
1752 if (WORDS_BIG_ENDIAN)
1753 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1755 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1759 (define_expand "unaligned_extendqidi_le"
1760 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1762 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1765 (ashift:DI (match_dup 3)
1766 (minus:DI (const_int 64)
1768 (and:DI (match_dup 2) (const_int 7))
1770 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1771 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1772 "! WORDS_BIG_ENDIAN"
1774 operands[2] = gen_reg_rtx (DImode);
1775 operands[3] = gen_reg_rtx (DImode);
1776 operands[4] = gen_reg_rtx (DImode);
1779 (define_expand "unaligned_extendqidi_be"
1780 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1781 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1783 (mem:DI (and:DI (match_dup 3)
1785 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1787 (ashift:DI (match_dup 4)
1790 (plus:DI (match_dup 5) (const_int 1))
1793 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1794 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1797 operands[2] = gen_reg_rtx (DImode);
1798 operands[3] = gen_reg_rtx (DImode);
1799 operands[4] = gen_reg_rtx (DImode);
1800 operands[5] = gen_reg_rtx (DImode);
1801 operands[6] = gen_reg_rtx (DImode);
1804 (define_expand "unaligned_extendhidi"
1805 [(use (match_operand:QI 0 "register_operand" ""))
1806 (use (match_operand:DI 1 "address_operand" ""))]
1809 if (WORDS_BIG_ENDIAN)
1810 emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
1812 emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
1816 (define_expand "unaligned_extendhidi_le"
1817 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1819 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1822 (ashift:DI (match_dup 3)
1823 (minus:DI (const_int 64)
1825 (and:DI (match_dup 2) (const_int 7))
1827 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1828 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1829 "! WORDS_BIG_ENDIAN"
1831 operands[2] = gen_reg_rtx (DImode);
1832 operands[3] = gen_reg_rtx (DImode);
1833 operands[4] = gen_reg_rtx (DImode);
1836 (define_expand "unaligned_extendhidi_be"
1837 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1838 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1840 (mem:DI (and:DI (match_dup 3)
1842 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1844 (ashift:DI (match_dup 4)
1847 (plus:DI (match_dup 5) (const_int 1))
1850 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1851 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1854 operands[2] = gen_reg_rtx (DImode);
1855 operands[3] = gen_reg_rtx (DImode);
1856 operands[4] = gen_reg_rtx (DImode);
1857 operands[5] = gen_reg_rtx (DImode);
1858 operands[6] = gen_reg_rtx (DImode);
1861 (define_insn "*extxl_const"
1862 [(set (match_operand:DI 0 "register_operand" "=r")
1863 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1864 (match_operand:DI 2 "mode_width_operand" "n")
1865 (match_operand:DI 3 "mul8_operand" "I")))]
1867 "ext%M2l %r1,%s3,%0"
1868 [(set_attr "type" "shift")])
1870 (define_insn "extxl_le"
1871 [(set (match_operand:DI 0 "register_operand" "=r")
1872 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1873 (match_operand:DI 2 "mode_width_operand" "n")
1874 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1876 "! WORDS_BIG_ENDIAN"
1878 [(set_attr "type" "shift")])
1880 (define_insn "extxl_be"
1881 [(set (match_operand:DI 0 "register_operand" "=r")
1882 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1883 (match_operand:DI 2 "mode_width_operand" "n")
1887 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1891 [(set_attr "type" "shift")])
1893 ;; Combine has some strange notion of preserving existing undefined behaviour
1894 ;; in shifts larger than a word size. So capture these patterns that it
1895 ;; should have turned into zero_extracts.
1897 (define_insn "*extxl_1_le"
1898 [(set (match_operand:DI 0 "register_operand" "=r")
1899 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1900 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1902 (match_operand:DI 3 "mode_mask_operand" "n")))]
1903 "! WORDS_BIG_ENDIAN"
1905 [(set_attr "type" "shift")])
1907 (define_insn "*extxl_1_be"
1908 [(set (match_operand:DI 0 "register_operand" "=r")
1909 (and:DI (lshiftrt:DI
1910 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1911 (minus:DI (const_int 56)
1912 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1914 (match_operand:DI 3 "mode_mask_operand" "n")))]
1917 [(set_attr "type" "shift")])
1919 (define_insn "*extql_2_le"
1920 [(set (match_operand:DI 0 "register_operand" "=r")
1921 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1922 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1924 "! WORDS_BIG_ENDIAN"
1926 [(set_attr "type" "shift")])
1928 (define_insn "*extql_2_be"
1929 [(set (match_operand:DI 0 "register_operand" "=r")
1931 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1932 (minus:DI (const_int 56)
1934 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1938 [(set_attr "type" "shift")])
1940 (define_insn "extqh_le"
1941 [(set (match_operand:DI 0 "register_operand" "=r")
1943 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1944 (minus:DI (const_int 64)
1947 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1950 "! WORDS_BIG_ENDIAN"
1952 [(set_attr "type" "shift")])
1954 (define_insn "extqh_be"
1955 [(set (match_operand:DI 0 "register_operand" "=r")
1957 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1960 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1966 [(set_attr "type" "shift")])
1968 (define_insn "extlh_le"
1969 [(set (match_operand:DI 0 "register_operand" "=r")
1971 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1972 (const_int 2147483647))
1973 (minus:DI (const_int 64)
1976 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1979 "! WORDS_BIG_ENDIAN"
1981 [(set_attr "type" "shift")])
1983 (define_insn "extlh_be"
1984 [(set (match_operand:DI 0 "register_operand" "=r")
1987 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1991 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1995 (const_int 2147483647)))]
1998 [(set_attr "type" "shift")])
2000 (define_insn "extwh_le"
2001 [(set (match_operand:DI 0 "register_operand" "=r")
2003 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2005 (minus:DI (const_int 64)
2008 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2011 "! WORDS_BIG_ENDIAN"
2013 [(set_attr "type" "shift")])
2015 (define_insn "extwh_be"
2016 [(set (match_operand:DI 0 "register_operand" "=r")
2018 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2022 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2026 (const_int 65535)))]
2029 [(set_attr "type" "shift")])
2031 ;; This converts an extXl into an extXh with an appropriate adjustment
2032 ;; to the address calculation.
2035 ;; [(set (match_operand:DI 0 "register_operand" "")
2036 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2037 ;; (match_operand:DI 2 "mode_width_operand" "")
2038 ;; (ashift:DI (match_operand:DI 3 "" "")
2040 ;; (match_operand:DI 4 "const_int_operand" "")))
2041 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2042 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2043 ;; [(set (match_dup 5) (match_dup 6))
2044 ;; (set (match_dup 0)
2045 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2046 ;; (ashift:DI (plus:DI (match_dup 5)
2052 ;; operands[6] = plus_constant (operands[3],
2053 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2054 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2057 (define_insn "*insbl_const"
2058 [(set (match_operand:DI 0 "register_operand" "=r")
2059 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2060 (match_operand:DI 2 "mul8_operand" "I")))]
2063 [(set_attr "type" "shift")])
2065 (define_insn "*inswl_const"
2066 [(set (match_operand:DI 0 "register_operand" "=r")
2067 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2068 (match_operand:DI 2 "mul8_operand" "I")))]
2071 [(set_attr "type" "shift")])
2073 (define_insn "*insll_const"
2074 [(set (match_operand:DI 0 "register_operand" "=r")
2075 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2076 (match_operand:DI 2 "mul8_operand" "I")))]
2079 [(set_attr "type" "shift")])
2081 (define_insn "insbl_le"
2082 [(set (match_operand:DI 0 "register_operand" "=r")
2083 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2084 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2086 "! WORDS_BIG_ENDIAN"
2088 [(set_attr "type" "shift")])
2090 (define_insn "insbl_be"
2091 [(set (match_operand:DI 0 "register_operand" "=r")
2092 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2093 (minus:DI (const_int 56)
2094 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2098 [(set_attr "type" "shift")])
2100 (define_insn "inswl_le"
2101 [(set (match_operand:DI 0 "register_operand" "=r")
2102 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2103 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2105 "! WORDS_BIG_ENDIAN"
2107 [(set_attr "type" "shift")])
2109 (define_insn "inswl_be"
2110 [(set (match_operand:DI 0 "register_operand" "=r")
2111 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2112 (minus:DI (const_int 56)
2113 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2117 [(set_attr "type" "shift")])
2119 (define_insn "insll_le"
2120 [(set (match_operand:DI 0 "register_operand" "=r")
2121 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2122 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2124 "! WORDS_BIG_ENDIAN"
2126 [(set_attr "type" "shift")])
2128 (define_insn "insll_be"
2129 [(set (match_operand:DI 0 "register_operand" "=r")
2130 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2131 (minus:DI (const_int 56)
2132 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2136 [(set_attr "type" "shift")])
2138 (define_insn "insql_le"
2139 [(set (match_operand:DI 0 "register_operand" "=r")
2140 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2141 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2143 "! WORDS_BIG_ENDIAN"
2145 [(set_attr "type" "shift")])
2147 (define_insn "insql_be"
2148 [(set (match_operand:DI 0 "register_operand" "=r")
2149 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2150 (minus:DI (const_int 56)
2151 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2155 [(set_attr "type" "shift")])
2157 ;; Combine has this sometimes habit of moving the and outside of the
2158 ;; shift, making life more interesting.
2160 (define_insn "*insxl"
2161 [(set (match_operand:DI 0 "register_operand" "=r")
2162 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2163 (match_operand:DI 2 "mul8_operand" "I"))
2164 (match_operand:DI 3 "immediate_operand" "i")))]
2165 "HOST_BITS_PER_WIDE_INT == 64
2166 && GET_CODE (operands[3]) == CONST_INT
2167 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2168 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2169 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2170 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2171 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2172 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2174 #if HOST_BITS_PER_WIDE_INT == 64
2175 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2176 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2177 return "insbl %1,%s2,%0";
2178 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2179 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2180 return "inswl %1,%s2,%0";
2181 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2182 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2183 return "insll %1,%s2,%0";
2187 [(set_attr "type" "shift")])
2189 ;; We do not include the insXh insns because they are complex to express
2190 ;; and it does not appear that we would ever want to generate them.
2192 ;; Since we need them for block moves, though, cop out and use unspec.
2194 (define_insn "insxh"
2195 [(set (match_operand:DI 0 "register_operand" "=r")
2196 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2197 (match_operand:DI 2 "mode_width_operand" "n")
2198 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2202 [(set_attr "type" "shift")])
2204 (define_insn "mskxl_le"
2205 [(set (match_operand:DI 0 "register_operand" "=r")
2206 (and:DI (not:DI (ashift:DI
2207 (match_operand:DI 2 "mode_mask_operand" "n")
2209 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2211 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2212 "! WORDS_BIG_ENDIAN"
2214 [(set_attr "type" "shift")])
2216 (define_insn "mskxl_be"
2217 [(set (match_operand:DI 0 "register_operand" "=r")
2218 (and:DI (not:DI (ashift:DI
2219 (match_operand:DI 2 "mode_mask_operand" "n")
2220 (minus:DI (const_int 56)
2222 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2224 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2227 [(set_attr "type" "shift")])
2229 ;; We do not include the mskXh insns because it does not appear we would
2230 ;; ever generate one.
2232 ;; Again, we do for block moves and we use unspec again.
2234 (define_insn "mskxh"
2235 [(set (match_operand:DI 0 "register_operand" "=r")
2236 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2237 (match_operand:DI 2 "mode_width_operand" "n")
2238 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2242 [(set_attr "type" "shift")])
2244 ;; Prefer AND + NE over LSHIFTRT + AND.
2246 (define_insn_and_split "*ze_and_ne"
2247 [(set (match_operand:DI 0 "register_operand" "=r")
2248 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2250 (match_operand 2 "const_int_operand" "I")))]
2251 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2253 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2255 (and:DI (match_dup 1) (match_dup 3)))
2257 (ne:DI (match_dup 0) (const_int 0)))]
2258 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2260 ;; Floating-point operations. All the double-precision insns can extend
2261 ;; from single, so indicate that. The exception are the ones that simply
2262 ;; play with the sign bits; it's not clear what to do there.
2264 (define_insn "abssf2"
2265 [(set (match_operand:SF 0 "register_operand" "=f")
2266 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2269 [(set_attr "type" "fcpys")])
2271 (define_insn "*nabssf2"
2272 [(set (match_operand:SF 0 "register_operand" "=f")
2273 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2276 [(set_attr "type" "fadd")])
2278 (define_insn "absdf2"
2279 [(set (match_operand:DF 0 "register_operand" "=f")
2280 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2283 [(set_attr "type" "fcpys")])
2285 (define_insn "*nabsdf2"
2286 [(set (match_operand:DF 0 "register_operand" "=f")
2287 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2290 [(set_attr "type" "fadd")])
2292 (define_expand "abstf2"
2293 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2294 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2295 (use (match_dup 2))])]
2296 "TARGET_HAS_XFLOATING_LIBS"
2298 #if HOST_BITS_PER_WIDE_INT >= 64
2299 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2301 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2305 (define_insn_and_split "*abstf_internal"
2306 [(set (match_operand:TF 0 "register_operand" "=r")
2307 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2308 (use (match_operand:DI 2 "register_operand" "r"))]
2309 "TARGET_HAS_XFLOATING_LIBS"
2311 "&& reload_completed"
2313 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2315 (define_insn "negsf2"
2316 [(set (match_operand:SF 0 "register_operand" "=f")
2317 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2320 [(set_attr "type" "fadd")])
2322 (define_insn "negdf2"
2323 [(set (match_operand:DF 0 "register_operand" "=f")
2324 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2327 [(set_attr "type" "fadd")])
2329 (define_expand "negtf2"
2330 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2331 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2332 (use (match_dup 2))])]
2333 "TARGET_HAS_XFLOATING_LIBS"
2335 #if HOST_BITS_PER_WIDE_INT >= 64
2336 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2338 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2342 (define_insn_and_split "*negtf_internal"
2343 [(set (match_operand:TF 0 "register_operand" "=r")
2344 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2345 (use (match_operand:DI 2 "register_operand" "r"))]
2346 "TARGET_HAS_XFLOATING_LIBS"
2348 "&& reload_completed"
2350 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2352 (define_insn "*addsf_ieee"
2353 [(set (match_operand:SF 0 "register_operand" "=&f")
2354 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2355 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2356 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2357 "add%,%/ %R1,%R2,%0"
2358 [(set_attr "type" "fadd")
2359 (set_attr "trap" "yes")
2360 (set_attr "round_suffix" "normal")
2361 (set_attr "trap_suffix" "u_su_sui")])
2363 (define_insn "addsf3"
2364 [(set (match_operand:SF 0 "register_operand" "=f")
2365 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2366 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2368 "add%,%/ %R1,%R2,%0"
2369 [(set_attr "type" "fadd")
2370 (set_attr "trap" "yes")
2371 (set_attr "round_suffix" "normal")
2372 (set_attr "trap_suffix" "u_su_sui")])
2374 (define_insn "*adddf_ieee"
2375 [(set (match_operand:DF 0 "register_operand" "=&f")
2376 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2377 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2378 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2379 "add%-%/ %R1,%R2,%0"
2380 [(set_attr "type" "fadd")
2381 (set_attr "trap" "yes")
2382 (set_attr "round_suffix" "normal")
2383 (set_attr "trap_suffix" "u_su_sui")])
2385 (define_insn "adddf3"
2386 [(set (match_operand:DF 0 "register_operand" "=f")
2387 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2388 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2390 "add%-%/ %R1,%R2,%0"
2391 [(set_attr "type" "fadd")
2392 (set_attr "trap" "yes")
2393 (set_attr "round_suffix" "normal")
2394 (set_attr "trap_suffix" "u_su_sui")])
2396 (define_insn "*adddf_ext1"
2397 [(set (match_operand:DF 0 "register_operand" "=f")
2398 (plus:DF (float_extend:DF
2399 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2400 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2401 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2402 "add%-%/ %R1,%R2,%0"
2403 [(set_attr "type" "fadd")
2404 (set_attr "trap" "yes")
2405 (set_attr "round_suffix" "normal")
2406 (set_attr "trap_suffix" "u_su_sui")])
2408 (define_insn "*adddf_ext2"
2409 [(set (match_operand:DF 0 "register_operand" "=f")
2410 (plus:DF (float_extend:DF
2411 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2413 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2414 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2415 "add%-%/ %R1,%R2,%0"
2416 [(set_attr "type" "fadd")
2417 (set_attr "trap" "yes")
2418 (set_attr "round_suffix" "normal")
2419 (set_attr "trap_suffix" "u_su_sui")])
2421 (define_expand "addtf3"
2422 [(use (match_operand 0 "register_operand" ""))
2423 (use (match_operand 1 "general_operand" ""))
2424 (use (match_operand 2 "general_operand" ""))]
2425 "TARGET_HAS_XFLOATING_LIBS"
2426 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2428 ;; Define conversion operators between DFmode and SImode, using the cvtql
2429 ;; instruction. To allow combine et al to do useful things, we keep the
2430 ;; operation as a unit until after reload, at which point we split the
2433 ;; Note that we (attempt to) only consider this optimization when the
2434 ;; ultimate destination is memory. If we will be doing further integer
2435 ;; processing, it is cheaper to do the truncation in the int regs.
2437 (define_insn "*cvtql"
2438 [(set (match_operand:SI 0 "register_operand" "=f")
2439 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2443 [(set_attr "type" "fadd")
2444 (set_attr "trap" "yes")
2445 (set_attr "trap_suffix" "v_sv")])
2447 (define_insn_and_split "*fix_truncdfsi_ieee"
2448 [(set (match_operand:SI 0 "memory_operand" "=m")
2449 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2450 (clobber (match_scratch:DI 2 "=&f"))
2451 (clobber (match_scratch:SI 3 "=&f"))]
2452 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2454 "&& reload_completed"
2455 [(set (match_dup 2) (fix:DI (match_dup 1)))
2456 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2457 (set (match_dup 0) (match_dup 3))]
2459 [(set_attr "type" "fadd")
2460 (set_attr "trap" "yes")])
2462 (define_insn_and_split "*fix_truncdfsi_internal"
2463 [(set (match_operand:SI 0 "memory_operand" "=m")
2464 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2465 (clobber (match_scratch:DI 2 "=f"))]
2466 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2468 "&& reload_completed"
2469 [(set (match_dup 2) (fix:DI (match_dup 1)))
2470 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2471 (set (match_dup 0) (match_dup 3))]
2472 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2473 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2474 [(set_attr "type" "fadd")
2475 (set_attr "trap" "yes")])
2477 (define_insn "*fix_truncdfdi_ieee"
2478 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2479 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2480 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2482 [(set_attr "type" "fadd")
2483 (set_attr "trap" "yes")
2484 (set_attr "round_suffix" "c")
2485 (set_attr "trap_suffix" "v_sv_svi")])
2487 (define_insn "fix_truncdfdi2"
2488 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2489 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2492 [(set_attr "type" "fadd")
2493 (set_attr "trap" "yes")
2494 (set_attr "round_suffix" "c")
2495 (set_attr "trap_suffix" "v_sv_svi")])
2497 ;; Likewise between SFmode and SImode.
2499 (define_insn_and_split "*fix_truncsfsi_ieee"
2500 [(set (match_operand:SI 0 "memory_operand" "=m")
2501 (subreg:SI (fix:DI (float_extend:DF
2502 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2503 (clobber (match_scratch:DI 2 "=&f"))
2504 (clobber (match_scratch:SI 3 "=&f"))]
2505 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2507 "&& reload_completed"
2508 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2509 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2510 (set (match_dup 0) (match_dup 3))]
2512 [(set_attr "type" "fadd")
2513 (set_attr "trap" "yes")])
2515 (define_insn_and_split "*fix_truncsfsi_internal"
2516 [(set (match_operand:SI 0 "memory_operand" "=m")
2517 (subreg:SI (fix:DI (float_extend:DF
2518 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2519 (clobber (match_scratch:DI 2 "=f"))]
2520 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2522 "&& reload_completed"
2523 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2524 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2525 (set (match_dup 0) (match_dup 3))]
2526 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2527 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2528 [(set_attr "type" "fadd")
2529 (set_attr "trap" "yes")])
2531 (define_insn "*fix_truncsfdi_ieee"
2532 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2533 (fix:DI (float_extend:DF
2534 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2535 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2537 [(set_attr "type" "fadd")
2538 (set_attr "trap" "yes")
2539 (set_attr "round_suffix" "c")
2540 (set_attr "trap_suffix" "v_sv_svi")])
2542 (define_insn "fix_truncsfdi2"
2543 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2544 (fix:DI (float_extend:DF
2545 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2548 [(set_attr "type" "fadd")
2549 (set_attr "trap" "yes")
2550 (set_attr "round_suffix" "c")
2551 (set_attr "trap_suffix" "v_sv_svi")])
2553 (define_expand "fix_trunctfdi2"
2554 [(use (match_operand:DI 0 "register_operand" ""))
2555 (use (match_operand:TF 1 "general_operand" ""))]
2556 "TARGET_HAS_XFLOATING_LIBS"
2557 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2559 (define_insn "*floatdisf_ieee"
2560 [(set (match_operand:SF 0 "register_operand" "=&f")
2561 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2562 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2564 [(set_attr "type" "fadd")
2565 (set_attr "trap" "yes")
2566 (set_attr "round_suffix" "normal")
2567 (set_attr "trap_suffix" "sui")])
2569 (define_insn "floatdisf2"
2570 [(set (match_operand:SF 0 "register_operand" "=f")
2571 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2574 [(set_attr "type" "fadd")
2575 (set_attr "trap" "yes")
2576 (set_attr "round_suffix" "normal")
2577 (set_attr "trap_suffix" "sui")])
2579 (define_insn "*floatdidf_ieee"
2580 [(set (match_operand:DF 0 "register_operand" "=&f")
2581 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2582 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2584 [(set_attr "type" "fadd")
2585 (set_attr "trap" "yes")
2586 (set_attr "round_suffix" "normal")
2587 (set_attr "trap_suffix" "sui")])
2589 (define_insn "floatdidf2"
2590 [(set (match_operand:DF 0 "register_operand" "=f")
2591 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2594 [(set_attr "type" "fadd")
2595 (set_attr "trap" "yes")
2596 (set_attr "round_suffix" "normal")
2597 (set_attr "trap_suffix" "sui")])
2599 (define_expand "floatditf2"
2600 [(use (match_operand:TF 0 "register_operand" ""))
2601 (use (match_operand:DI 1 "general_operand" ""))]
2602 "TARGET_HAS_XFLOATING_LIBS"
2603 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2605 (define_expand "floatunsdisf2"
2606 [(use (match_operand:SF 0 "register_operand" ""))
2607 (use (match_operand:DI 1 "register_operand" ""))]
2609 "alpha_emit_floatuns (operands); DONE;")
2611 (define_expand "floatunsdidf2"
2612 [(use (match_operand:DF 0 "register_operand" ""))
2613 (use (match_operand:DI 1 "register_operand" ""))]
2615 "alpha_emit_floatuns (operands); DONE;")
2617 (define_expand "floatunsditf2"
2618 [(use (match_operand:TF 0 "register_operand" ""))
2619 (use (match_operand:DI 1 "general_operand" ""))]
2620 "TARGET_HAS_XFLOATING_LIBS"
2621 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2623 (define_expand "extendsfdf2"
2624 [(set (match_operand:DF 0 "register_operand" "")
2625 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2628 if (alpha_fptm >= ALPHA_FPTM_SU)
2629 operands[1] = force_reg (SFmode, operands[1]);
2632 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2633 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2635 (define_insn "*extendsfdf2_ieee"
2636 [(set (match_operand:DF 0 "register_operand" "=&f")
2637 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2638 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2640 [(set_attr "type" "fadd")
2641 (set_attr "trap" "yes")])
2643 (define_insn "*extendsfdf2_internal"
2644 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2645 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2646 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2651 [(set_attr "type" "fcpys,fld,fst")])
2653 (define_expand "extendsftf2"
2654 [(use (match_operand:TF 0 "register_operand" ""))
2655 (use (match_operand:SF 1 "general_operand" ""))]
2656 "TARGET_HAS_XFLOATING_LIBS"
2658 rtx tmp = gen_reg_rtx (DFmode);
2659 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2660 emit_insn (gen_extenddftf2 (operands[0], tmp));
2664 (define_expand "extenddftf2"
2665 [(use (match_operand:TF 0 "register_operand" ""))
2666 (use (match_operand:DF 1 "general_operand" ""))]
2667 "TARGET_HAS_XFLOATING_LIBS"
2668 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2670 (define_insn "*truncdfsf2_ieee"
2671 [(set (match_operand:SF 0 "register_operand" "=&f")
2672 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2673 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2675 [(set_attr "type" "fadd")
2676 (set_attr "trap" "yes")
2677 (set_attr "round_suffix" "normal")
2678 (set_attr "trap_suffix" "u_su_sui")])
2680 (define_insn "truncdfsf2"
2681 [(set (match_operand:SF 0 "register_operand" "=f")
2682 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2685 [(set_attr "type" "fadd")
2686 (set_attr "trap" "yes")
2687 (set_attr "round_suffix" "normal")
2688 (set_attr "trap_suffix" "u_su_sui")])
2690 (define_expand "trunctfdf2"
2691 [(use (match_operand:DF 0 "register_operand" ""))
2692 (use (match_operand:TF 1 "general_operand" ""))]
2693 "TARGET_HAS_XFLOATING_LIBS"
2694 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2696 (define_expand "trunctfsf2"
2697 [(use (match_operand:SF 0 "register_operand" ""))
2698 (use (match_operand:TF 1 "general_operand" ""))]
2699 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2701 rtx tmpf, sticky, arg, lo, hi;
2703 tmpf = gen_reg_rtx (DFmode);
2704 sticky = gen_reg_rtx (DImode);
2705 arg = copy_to_mode_reg (TFmode, operands[1]);
2706 lo = gen_lowpart (DImode, arg);
2707 hi = gen_highpart (DImode, arg);
2709 /* Convert the low word of the TFmode value into a sticky rounding bit,
2710 then or it into the low bit of the high word. This leaves the sticky
2711 bit at bit 48 of the fraction, which is representable in DFmode,
2712 which prevents rounding error in the final conversion to SFmode. */
2714 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2715 gen_rtx_NE (DImode, lo, const0_rtx)));
2716 emit_insn (gen_iordi3 (hi, hi, sticky));
2717 emit_insn (gen_trunctfdf2 (tmpf, arg));
2718 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2722 (define_insn "*divsf3_ieee"
2723 [(set (match_operand:SF 0 "register_operand" "=&f")
2724 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2725 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2726 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2727 "div%,%/ %R1,%R2,%0"
2728 [(set_attr "type" "fdiv")
2729 (set_attr "opsize" "si")
2730 (set_attr "trap" "yes")
2731 (set_attr "round_suffix" "normal")
2732 (set_attr "trap_suffix" "u_su_sui")])
2734 (define_insn "divsf3"
2735 [(set (match_operand:SF 0 "register_operand" "=f")
2736 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2737 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2739 "div%,%/ %R1,%R2,%0"
2740 [(set_attr "type" "fdiv")
2741 (set_attr "opsize" "si")
2742 (set_attr "trap" "yes")
2743 (set_attr "round_suffix" "normal")
2744 (set_attr "trap_suffix" "u_su_sui")])
2746 (define_insn "*divdf3_ieee"
2747 [(set (match_operand:DF 0 "register_operand" "=&f")
2748 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2749 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2750 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2751 "div%-%/ %R1,%R2,%0"
2752 [(set_attr "type" "fdiv")
2753 (set_attr "trap" "yes")
2754 (set_attr "round_suffix" "normal")
2755 (set_attr "trap_suffix" "u_su_sui")])
2757 (define_insn "divdf3"
2758 [(set (match_operand:DF 0 "register_operand" "=f")
2759 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2760 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2762 "div%-%/ %R1,%R2,%0"
2763 [(set_attr "type" "fdiv")
2764 (set_attr "trap" "yes")
2765 (set_attr "round_suffix" "normal")
2766 (set_attr "trap_suffix" "u_su_sui")])
2768 (define_insn "*divdf_ext1"
2769 [(set (match_operand:DF 0 "register_operand" "=f")
2770 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2771 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2772 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2773 "div%-%/ %R1,%R2,%0"
2774 [(set_attr "type" "fdiv")
2775 (set_attr "trap" "yes")
2776 (set_attr "round_suffix" "normal")
2777 (set_attr "trap_suffix" "u_su_sui")])
2779 (define_insn "*divdf_ext2"
2780 [(set (match_operand:DF 0 "register_operand" "=f")
2781 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2783 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2784 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2785 "div%-%/ %R1,%R2,%0"
2786 [(set_attr "type" "fdiv")
2787 (set_attr "trap" "yes")
2788 (set_attr "round_suffix" "normal")
2789 (set_attr "trap_suffix" "u_su_sui")])
2791 (define_insn "*divdf_ext3"
2792 [(set (match_operand:DF 0 "register_operand" "=f")
2793 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2794 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2795 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2796 "div%-%/ %R1,%R2,%0"
2797 [(set_attr "type" "fdiv")
2798 (set_attr "trap" "yes")
2799 (set_attr "round_suffix" "normal")
2800 (set_attr "trap_suffix" "u_su_sui")])
2802 (define_expand "divtf3"
2803 [(use (match_operand 0 "register_operand" ""))
2804 (use (match_operand 1 "general_operand" ""))
2805 (use (match_operand 2 "general_operand" ""))]
2806 "TARGET_HAS_XFLOATING_LIBS"
2807 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2809 (define_insn "*mulsf3_ieee"
2810 [(set (match_operand:SF 0 "register_operand" "=&f")
2811 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2812 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2813 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2814 "mul%,%/ %R1,%R2,%0"
2815 [(set_attr "type" "fmul")
2816 (set_attr "trap" "yes")
2817 (set_attr "round_suffix" "normal")
2818 (set_attr "trap_suffix" "u_su_sui")])
2820 (define_insn "mulsf3"
2821 [(set (match_operand:SF 0 "register_operand" "=f")
2822 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2823 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2825 "mul%,%/ %R1,%R2,%0"
2826 [(set_attr "type" "fmul")
2827 (set_attr "trap" "yes")
2828 (set_attr "round_suffix" "normal")
2829 (set_attr "trap_suffix" "u_su_sui")])
2831 (define_insn "*muldf3_ieee"
2832 [(set (match_operand:DF 0 "register_operand" "=&f")
2833 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2834 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2835 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2836 "mul%-%/ %R1,%R2,%0"
2837 [(set_attr "type" "fmul")
2838 (set_attr "trap" "yes")
2839 (set_attr "round_suffix" "normal")
2840 (set_attr "trap_suffix" "u_su_sui")])
2842 (define_insn "muldf3"
2843 [(set (match_operand:DF 0 "register_operand" "=f")
2844 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2845 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2847 "mul%-%/ %R1,%R2,%0"
2848 [(set_attr "type" "fmul")
2849 (set_attr "trap" "yes")
2850 (set_attr "round_suffix" "normal")
2851 (set_attr "trap_suffix" "u_su_sui")])
2853 (define_insn "*muldf_ext1"
2854 [(set (match_operand:DF 0 "register_operand" "=f")
2855 (mult:DF (float_extend:DF
2856 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2857 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2858 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2859 "mul%-%/ %R1,%R2,%0"
2860 [(set_attr "type" "fmul")
2861 (set_attr "trap" "yes")
2862 (set_attr "round_suffix" "normal")
2863 (set_attr "trap_suffix" "u_su_sui")])
2865 (define_insn "*muldf_ext2"
2866 [(set (match_operand:DF 0 "register_operand" "=f")
2867 (mult:DF (float_extend:DF
2868 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2870 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2871 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2872 "mul%-%/ %R1,%R2,%0"
2873 [(set_attr "type" "fmul")
2874 (set_attr "trap" "yes")
2875 (set_attr "round_suffix" "normal")
2876 (set_attr "trap_suffix" "u_su_sui")])
2878 (define_expand "multf3"
2879 [(use (match_operand 0 "register_operand" ""))
2880 (use (match_operand 1 "general_operand" ""))
2881 (use (match_operand 2 "general_operand" ""))]
2882 "TARGET_HAS_XFLOATING_LIBS"
2883 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2885 (define_insn "*subsf3_ieee"
2886 [(set (match_operand:SF 0 "register_operand" "=&f")
2887 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2888 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2889 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2890 "sub%,%/ %R1,%R2,%0"
2891 [(set_attr "type" "fadd")
2892 (set_attr "trap" "yes")
2893 (set_attr "round_suffix" "normal")
2894 (set_attr "trap_suffix" "u_su_sui")])
2896 (define_insn "subsf3"
2897 [(set (match_operand:SF 0 "register_operand" "=f")
2898 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2899 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2901 "sub%,%/ %R1,%R2,%0"
2902 [(set_attr "type" "fadd")
2903 (set_attr "trap" "yes")
2904 (set_attr "round_suffix" "normal")
2905 (set_attr "trap_suffix" "u_su_sui")])
2907 (define_insn "*subdf3_ieee"
2908 [(set (match_operand:DF 0 "register_operand" "=&f")
2909 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2910 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2911 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2912 "sub%-%/ %R1,%R2,%0"
2913 [(set_attr "type" "fadd")
2914 (set_attr "trap" "yes")
2915 (set_attr "round_suffix" "normal")
2916 (set_attr "trap_suffix" "u_su_sui")])
2918 (define_insn "subdf3"
2919 [(set (match_operand:DF 0 "register_operand" "=f")
2920 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2921 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2923 "sub%-%/ %R1,%R2,%0"
2924 [(set_attr "type" "fadd")
2925 (set_attr "trap" "yes")
2926 (set_attr "round_suffix" "normal")
2927 (set_attr "trap_suffix" "u_su_sui")])
2929 (define_insn "*subdf_ext1"
2930 [(set (match_operand:DF 0 "register_operand" "=f")
2931 (minus:DF (float_extend:DF
2932 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2933 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2934 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2935 "sub%-%/ %R1,%R2,%0"
2936 [(set_attr "type" "fadd")
2937 (set_attr "trap" "yes")
2938 (set_attr "round_suffix" "normal")
2939 (set_attr "trap_suffix" "u_su_sui")])
2941 (define_insn "*subdf_ext2"
2942 [(set (match_operand:DF 0 "register_operand" "=f")
2943 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2945 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2946 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2947 "sub%-%/ %R1,%R2,%0"
2948 [(set_attr "type" "fadd")
2949 (set_attr "trap" "yes")
2950 (set_attr "round_suffix" "normal")
2951 (set_attr "trap_suffix" "u_su_sui")])
2953 (define_insn "*subdf_ext3"
2954 [(set (match_operand:DF 0 "register_operand" "=f")
2955 (minus:DF (float_extend:DF
2956 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2958 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2959 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2960 "sub%-%/ %R1,%R2,%0"
2961 [(set_attr "type" "fadd")
2962 (set_attr "trap" "yes")
2963 (set_attr "round_suffix" "normal")
2964 (set_attr "trap_suffix" "u_su_sui")])
2966 (define_expand "subtf3"
2967 [(use (match_operand 0 "register_operand" ""))
2968 (use (match_operand 1 "general_operand" ""))
2969 (use (match_operand 2 "general_operand" ""))]
2970 "TARGET_HAS_XFLOATING_LIBS"
2971 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2973 (define_insn "*sqrtsf2_ieee"
2974 [(set (match_operand:SF 0 "register_operand" "=&f")
2975 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2976 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2978 [(set_attr "type" "fsqrt")
2979 (set_attr "opsize" "si")
2980 (set_attr "trap" "yes")
2981 (set_attr "round_suffix" "normal")
2982 (set_attr "trap_suffix" "u_su_sui")])
2984 (define_insn "sqrtsf2"
2985 [(set (match_operand:SF 0 "register_operand" "=f")
2986 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2987 "TARGET_FP && TARGET_FIX"
2989 [(set_attr "type" "fsqrt")
2990 (set_attr "opsize" "si")
2991 (set_attr "trap" "yes")
2992 (set_attr "round_suffix" "normal")
2993 (set_attr "trap_suffix" "u_su_sui")])
2995 (define_insn "*sqrtdf2_ieee"
2996 [(set (match_operand:DF 0 "register_operand" "=&f")
2997 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2998 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3000 [(set_attr "type" "fsqrt")
3001 (set_attr "trap" "yes")
3002 (set_attr "round_suffix" "normal")
3003 (set_attr "trap_suffix" "u_su_sui")])
3005 (define_insn "sqrtdf2"
3006 [(set (match_operand:DF 0 "register_operand" "=f")
3007 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3008 "TARGET_FP && TARGET_FIX"
3010 [(set_attr "type" "fsqrt")
3011 (set_attr "trap" "yes")
3012 (set_attr "round_suffix" "normal")
3013 (set_attr "trap_suffix" "u_su_sui")])
3015 ;; Next are all the integer comparisons, and conditional moves and branches
3016 ;; and some of the related define_expand's and define_split's.
3018 (define_insn "*setcc_internal"
3019 [(set (match_operand 0 "register_operand" "=r")
3020 (match_operator 1 "alpha_comparison_operator"
3021 [(match_operand:DI 2 "register_operand" "r")
3022 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3023 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3024 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3025 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3027 [(set_attr "type" "icmp")])
3029 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3030 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3032 (define_insn "*setcc_swapped_internal"
3033 [(set (match_operand 0 "register_operand" "=r")
3034 (match_operator 1 "alpha_swapped_comparison_operator"
3035 [(match_operand:DI 2 "register_operand" "r")
3036 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3037 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3038 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3039 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3041 [(set_attr "type" "icmp")])
3043 ;; Use match_operator rather than ne directly so that we can match
3044 ;; multiple integer modes.
3045 (define_insn "*setne_internal"
3046 [(set (match_operand 0 "register_operand" "=r")
3047 (match_operator 1 "signed_comparison_operator"
3048 [(match_operand:DI 2 "register_operand" "r")
3050 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3051 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3052 && GET_CODE (operands[1]) == NE
3053 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3055 [(set_attr "type" "icmp")])
3057 ;; The mode folding trick can't be used with const_int operands, since
3058 ;; reload needs to know the proper mode.
3060 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3061 ;; in order to create more pairs of constants. As long as we're allowing
3062 ;; two constants at the same time, and will have to reload one of them...
3064 (define_insn "*movqicc_internal"
3065 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3067 (match_operator 2 "signed_comparison_operator"
3068 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3069 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3070 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3071 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3072 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3078 [(set_attr "type" "icmov")])
3080 (define_insn "*movhicc_internal"
3081 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3083 (match_operator 2 "signed_comparison_operator"
3084 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3085 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3086 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3087 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3088 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3094 [(set_attr "type" "icmov")])
3096 (define_insn "*movsicc_internal"
3097 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3099 (match_operator 2 "signed_comparison_operator"
3100 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3101 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3102 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3103 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3104 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3110 [(set_attr "type" "icmov")])
3112 (define_insn "*movdicc_internal"
3113 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3115 (match_operator 2 "signed_comparison_operator"
3116 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3117 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3118 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3119 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3120 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3126 [(set_attr "type" "icmov")])
3128 (define_insn "*movqicc_lbc"
3129 [(set (match_operand:QI 0 "register_operand" "=r,r")
3131 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3135 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3136 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3141 [(set_attr "type" "icmov")])
3143 (define_insn "*movhicc_lbc"
3144 [(set (match_operand:HI 0 "register_operand" "=r,r")
3146 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3150 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3151 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3156 [(set_attr "type" "icmov")])
3158 (define_insn "*movsicc_lbc"
3159 [(set (match_operand:SI 0 "register_operand" "=r,r")
3161 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3165 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3166 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3171 [(set_attr "type" "icmov")])
3173 (define_insn "*movdicc_lbc"
3174 [(set (match_operand:DI 0 "register_operand" "=r,r")
3176 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3180 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3181 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3186 [(set_attr "type" "icmov")])
3188 (define_insn "*movqicc_lbs"
3189 [(set (match_operand:QI 0 "register_operand" "=r,r")
3191 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3195 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3196 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3201 [(set_attr "type" "icmov")])
3203 (define_insn "*movhicc_lbs"
3204 [(set (match_operand:HI 0 "register_operand" "=r,r")
3206 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3210 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3211 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3216 [(set_attr "type" "icmov")])
3218 (define_insn "*movsicc_lbs"
3219 [(set (match_operand:SI 0 "register_operand" "=r,r")
3221 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3225 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3226 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3231 [(set_attr "type" "icmov")])
3233 (define_insn "*movdicc_lbs"
3234 [(set (match_operand:DI 0 "register_operand" "=r,r")
3236 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3240 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3241 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3246 [(set_attr "type" "icmov")])
3248 ;; For ABS, we have two choices, depending on whether the input and output
3249 ;; registers are the same or not.
3250 (define_expand "absdi2"
3251 [(set (match_operand:DI 0 "register_operand" "")
3252 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3255 if (rtx_equal_p (operands[0], operands[1]))
3256 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3258 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3262 (define_expand "absdi2_same"
3263 [(set (match_operand:DI 1 "register_operand" "")
3264 (neg:DI (match_operand:DI 0 "register_operand" "")))
3266 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3272 (define_expand "absdi2_diff"
3273 [(set (match_operand:DI 0 "register_operand" "")
3274 (neg:DI (match_operand:DI 1 "register_operand" "")))
3276 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3283 [(set (match_operand:DI 0 "register_operand" "")
3284 (abs:DI (match_dup 0)))
3285 (clobber (match_operand:DI 1 "register_operand" ""))]
3287 [(set (match_dup 1) (neg:DI (match_dup 0)))
3288 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3289 (match_dup 0) (match_dup 1)))]
3293 [(set (match_operand:DI 0 "register_operand" "")
3294 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3295 "! rtx_equal_p (operands[0], operands[1])"
3296 [(set (match_dup 0) (neg:DI (match_dup 1)))
3297 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3298 (match_dup 0) (match_dup 1)))]
3302 [(set (match_operand:DI 0 "register_operand" "")
3303 (neg:DI (abs:DI (match_dup 0))))
3304 (clobber (match_operand:DI 1 "register_operand" ""))]
3306 [(set (match_dup 1) (neg:DI (match_dup 0)))
3307 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3308 (match_dup 0) (match_dup 1)))]
3312 [(set (match_operand:DI 0 "register_operand" "")
3313 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3314 "! rtx_equal_p (operands[0], operands[1])"
3315 [(set (match_dup 0) (neg:DI (match_dup 1)))
3316 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3317 (match_dup 0) (match_dup 1)))]
3320 (define_insn "sminqi3"
3321 [(set (match_operand:QI 0 "register_operand" "=r")
3322 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3323 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3326 [(set_attr "type" "mvi")])
3328 (define_insn "uminqi3"
3329 [(set (match_operand:QI 0 "register_operand" "=r")
3330 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3331 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3334 [(set_attr "type" "mvi")])
3336 (define_insn "smaxqi3"
3337 [(set (match_operand:QI 0 "register_operand" "=r")
3338 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3339 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3342 [(set_attr "type" "mvi")])
3344 (define_insn "umaxqi3"
3345 [(set (match_operand:QI 0 "register_operand" "=r")
3346 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3347 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3350 [(set_attr "type" "mvi")])
3352 (define_insn "sminhi3"
3353 [(set (match_operand:HI 0 "register_operand" "=r")
3354 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3355 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3358 [(set_attr "type" "mvi")])
3360 (define_insn "uminhi3"
3361 [(set (match_operand:HI 0 "register_operand" "=r")
3362 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3363 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3366 [(set_attr "type" "mvi")])
3368 (define_insn "smaxhi3"
3369 [(set (match_operand:HI 0 "register_operand" "=r")
3370 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3371 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3374 [(set_attr "type" "mvi")])
3376 (define_insn "umaxhi3"
3377 [(set (match_operand:HI 0 "register_operand" "=r")
3378 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3379 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3382 [(set_attr "type" "shift")])
3384 (define_expand "smaxdi3"
3386 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3387 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3388 (set (match_operand:DI 0 "register_operand" "")
3389 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3390 (match_dup 1) (match_dup 2)))]
3392 { operands[3] = gen_reg_rtx (DImode); })
3395 [(set (match_operand:DI 0 "register_operand" "")
3396 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3397 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3398 (clobber (match_operand:DI 3 "register_operand" ""))]
3399 "operands[2] != const0_rtx"
3400 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3401 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3402 (match_dup 1) (match_dup 2)))]
3405 (define_insn "*smax_const0"
3406 [(set (match_operand:DI 0 "register_operand" "=r")
3407 (smax:DI (match_operand:DI 1 "register_operand" "0")
3411 [(set_attr "type" "icmov")])
3413 (define_expand "smindi3"
3415 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3416 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3417 (set (match_operand:DI 0 "register_operand" "")
3418 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3419 (match_dup 1) (match_dup 2)))]
3421 { operands[3] = gen_reg_rtx (DImode); })
3424 [(set (match_operand:DI 0 "register_operand" "")
3425 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3426 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3427 (clobber (match_operand:DI 3 "register_operand" ""))]
3428 "operands[2] != const0_rtx"
3429 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3430 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3431 (match_dup 1) (match_dup 2)))]
3434 (define_insn "*smin_const0"
3435 [(set (match_operand:DI 0 "register_operand" "=r")
3436 (smin:DI (match_operand:DI 1 "register_operand" "0")
3440 [(set_attr "type" "icmov")])
3442 (define_expand "umaxdi3"
3444 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3445 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3446 (set (match_operand:DI 0 "register_operand" "")
3447 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3448 (match_dup 1) (match_dup 2)))]
3450 "operands[3] = gen_reg_rtx (DImode);")
3453 [(set (match_operand:DI 0 "register_operand" "")
3454 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3455 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3456 (clobber (match_operand:DI 3 "register_operand" ""))]
3457 "operands[2] != const0_rtx"
3458 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3459 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3460 (match_dup 1) (match_dup 2)))]
3463 (define_expand "umindi3"
3465 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3466 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3467 (set (match_operand:DI 0 "register_operand" "")
3468 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3469 (match_dup 1) (match_dup 2)))]
3471 "operands[3] = gen_reg_rtx (DImode);")
3474 [(set (match_operand:DI 0 "register_operand" "")
3475 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3476 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3477 (clobber (match_operand:DI 3 "register_operand" ""))]
3478 "operands[2] != const0_rtx"
3479 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3480 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3481 (match_dup 1) (match_dup 2)))]
3484 (define_insn "*bcc_normal"
3487 (match_operator 1 "signed_comparison_operator"
3488 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3490 (label_ref (match_operand 0 "" ""))
3494 [(set_attr "type" "ibr")])
3496 (define_insn "*bcc_reverse"
3499 (match_operator 1 "signed_comparison_operator"
3500 [(match_operand:DI 2 "register_operand" "r")
3504 (label_ref (match_operand 0 "" ""))))]
3507 [(set_attr "type" "ibr")])
3509 (define_insn "*blbs_normal"
3512 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3516 (label_ref (match_operand 0 "" ""))
3520 [(set_attr "type" "ibr")])
3522 (define_insn "*blbc_normal"
3525 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3529 (label_ref (match_operand 0 "" ""))
3533 [(set_attr "type" "ibr")])
3539 (match_operator 1 "comparison_operator"
3540 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3542 (match_operand:DI 3 "const_int_operand" ""))
3544 (label_ref (match_operand 0 "" ""))
3546 (clobber (match_operand:DI 4 "register_operand" ""))])]
3547 "INTVAL (operands[3]) != 0"
3549 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3551 (if_then_else (match_op_dup 1
3552 [(zero_extract:DI (match_dup 4)
3556 (label_ref (match_dup 0))
3560 ;; The following are the corresponding floating-point insns. Recall
3561 ;; we need to have variants that expand the arguments from SFmode
3564 (define_insn "*cmpdf_ieee"
3565 [(set (match_operand:DF 0 "register_operand" "=&f")
3566 (match_operator:DF 1 "alpha_fp_comparison_operator"
3567 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3568 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3569 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3570 "cmp%-%C1%/ %R2,%R3,%0"
3571 [(set_attr "type" "fadd")
3572 (set_attr "trap" "yes")
3573 (set_attr "trap_suffix" "su")])
3575 (define_insn "*cmpdf_internal"
3576 [(set (match_operand:DF 0 "register_operand" "=f")
3577 (match_operator:DF 1 "alpha_fp_comparison_operator"
3578 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3579 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3580 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3581 "cmp%-%C1%/ %R2,%R3,%0"
3582 [(set_attr "type" "fadd")
3583 (set_attr "trap" "yes")
3584 (set_attr "trap_suffix" "su")])
3586 (define_insn "*cmpdf_ieee_ext1"
3587 [(set (match_operand:DF 0 "register_operand" "=&f")
3588 (match_operator:DF 1 "alpha_fp_comparison_operator"
3590 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3591 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3592 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3593 "cmp%-%C1%/ %R2,%R3,%0"
3594 [(set_attr "type" "fadd")
3595 (set_attr "trap" "yes")
3596 (set_attr "trap_suffix" "su")])
3598 (define_insn "*cmpdf_ext1"
3599 [(set (match_operand:DF 0 "register_operand" "=f")
3600 (match_operator:DF 1 "alpha_fp_comparison_operator"
3602 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3603 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3604 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3605 "cmp%-%C1%/ %R2,%R3,%0"
3606 [(set_attr "type" "fadd")
3607 (set_attr "trap" "yes")
3608 (set_attr "trap_suffix" "su")])
3610 (define_insn "*cmpdf_ieee_ext2"
3611 [(set (match_operand:DF 0 "register_operand" "=&f")
3612 (match_operator:DF 1 "alpha_fp_comparison_operator"
3613 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3615 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3616 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3617 "cmp%-%C1%/ %R2,%R3,%0"
3618 [(set_attr "type" "fadd")
3619 (set_attr "trap" "yes")
3620 (set_attr "trap_suffix" "su")])
3622 (define_insn "*cmpdf_ext2"
3623 [(set (match_operand:DF 0 "register_operand" "=f")
3624 (match_operator:DF 1 "alpha_fp_comparison_operator"
3625 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3627 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3628 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3629 "cmp%-%C1%/ %R2,%R3,%0"
3630 [(set_attr "type" "fadd")
3631 (set_attr "trap" "yes")
3632 (set_attr "trap_suffix" "su")])
3634 (define_insn "*cmpdf_ieee_ext3"
3635 [(set (match_operand:DF 0 "register_operand" "=&f")
3636 (match_operator:DF 1 "alpha_fp_comparison_operator"
3638 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3640 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3641 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3642 "cmp%-%C1%/ %R2,%R3,%0"
3643 [(set_attr "type" "fadd")
3644 (set_attr "trap" "yes")
3645 (set_attr "trap_suffix" "su")])
3647 (define_insn "*cmpdf_ext3"
3648 [(set (match_operand:DF 0 "register_operand" "=f")
3649 (match_operator:DF 1 "alpha_fp_comparison_operator"
3651 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3653 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3654 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3655 "cmp%-%C1%/ %R2,%R3,%0"
3656 [(set_attr "type" "fadd")
3657 (set_attr "trap" "yes")
3658 (set_attr "trap_suffix" "su")])
3660 (define_insn "*movdfcc_internal"
3661 [(set (match_operand:DF 0 "register_operand" "=f,f")
3663 (match_operator 3 "signed_comparison_operator"
3664 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3665 (match_operand:DF 2 "fp0_operand" "G,G")])
3666 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3667 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3671 fcmov%D3 %R4,%R5,%0"
3672 [(set_attr "type" "fcmov")])
3674 (define_insn "*movsfcc_internal"
3675 [(set (match_operand:SF 0 "register_operand" "=f,f")
3677 (match_operator 3 "signed_comparison_operator"
3678 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3679 (match_operand:DF 2 "fp0_operand" "G,G")])
3680 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3681 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3685 fcmov%D3 %R4,%R5,%0"
3686 [(set_attr "type" "fcmov")])
3688 (define_insn "*movdfcc_ext1"
3689 [(set (match_operand:DF 0 "register_operand" "=f,f")
3691 (match_operator 3 "signed_comparison_operator"
3692 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3693 (match_operand:DF 2 "fp0_operand" "G,G")])
3694 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3695 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3699 fcmov%D3 %R4,%R5,%0"
3700 [(set_attr "type" "fcmov")])
3702 (define_insn "*movdfcc_ext2"
3703 [(set (match_operand:DF 0 "register_operand" "=f,f")
3705 (match_operator 3 "signed_comparison_operator"
3707 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3708 (match_operand:DF 2 "fp0_operand" "G,G")])
3709 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3710 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3714 fcmov%D3 %R4,%R5,%0"
3715 [(set_attr "type" "fcmov")])
3717 (define_insn "*movdfcc_ext3"
3718 [(set (match_operand:SF 0 "register_operand" "=f,f")
3720 (match_operator 3 "signed_comparison_operator"
3722 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3723 (match_operand:DF 2 "fp0_operand" "G,G")])
3724 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3725 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3729 fcmov%D3 %R4,%R5,%0"
3730 [(set_attr "type" "fcmov")])
3732 (define_insn "*movdfcc_ext4"
3733 [(set (match_operand:DF 0 "register_operand" "=f,f")
3735 (match_operator 3 "signed_comparison_operator"
3737 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3738 (match_operand:DF 2 "fp0_operand" "G,G")])
3739 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3740 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3744 fcmov%D3 %R4,%R5,%0"
3745 [(set_attr "type" "fcmov")])
3747 (define_expand "maxdf3"
3749 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3750 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3751 (set (match_operand:DF 0 "register_operand" "")
3752 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3753 (match_dup 1) (match_dup 2)))]
3756 operands[3] = gen_reg_rtx (DFmode);
3757 operands[4] = CONST0_RTX (DFmode);
3760 (define_expand "mindf3"
3762 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3763 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3764 (set (match_operand:DF 0 "register_operand" "")
3765 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3766 (match_dup 1) (match_dup 2)))]
3769 operands[3] = gen_reg_rtx (DFmode);
3770 operands[4] = CONST0_RTX (DFmode);
3773 (define_expand "maxsf3"
3775 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3776 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3777 (set (match_operand:SF 0 "register_operand" "")
3778 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3779 (match_dup 1) (match_dup 2)))]
3782 operands[3] = gen_reg_rtx (DFmode);
3783 operands[4] = CONST0_RTX (DFmode);
3786 (define_expand "minsf3"
3788 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3789 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3790 (set (match_operand:SF 0 "register_operand" "")
3791 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3792 (match_dup 1) (match_dup 2)))]
3795 operands[3] = gen_reg_rtx (DFmode);
3796 operands[4] = CONST0_RTX (DFmode);
3799 (define_insn "*fbcc_normal"
3802 (match_operator 1 "signed_comparison_operator"
3803 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3804 (match_operand:DF 3 "fp0_operand" "G")])
3805 (label_ref (match_operand 0 "" ""))
3809 [(set_attr "type" "fbr")])
3811 (define_insn "*fbcc_ext_normal"
3814 (match_operator 1 "signed_comparison_operator"
3816 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3817 (match_operand:DF 3 "fp0_operand" "G")])
3818 (label_ref (match_operand 0 "" ""))
3822 [(set_attr "type" "fbr")])
3824 ;; These are the main define_expand's used to make conditional branches
3827 (define_expand "cmpdf"
3828 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3829 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3832 alpha_compare.op0 = operands[0];
3833 alpha_compare.op1 = operands[1];
3834 alpha_compare.fp_p = 1;
3838 (define_expand "cmptf"
3839 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3840 (match_operand:TF 1 "general_operand" "")))]
3841 "TARGET_HAS_XFLOATING_LIBS"
3843 alpha_compare.op0 = operands[0];
3844 alpha_compare.op1 = operands[1];
3845 alpha_compare.fp_p = 1;
3849 (define_expand "cmpdi"
3850 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3851 (match_operand:DI 1 "general_operand" "")))]
3854 alpha_compare.op0 = operands[0];
3855 alpha_compare.op1 = operands[1];
3856 alpha_compare.fp_p = 0;
3860 (define_expand "beq"
3862 (if_then_else (match_dup 1)
3863 (label_ref (match_operand 0 "" ""))
3866 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3868 (define_expand "bne"
3870 (if_then_else (match_dup 1)
3871 (label_ref (match_operand 0 "" ""))
3874 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3876 (define_expand "blt"
3878 (if_then_else (match_dup 1)
3879 (label_ref (match_operand 0 "" ""))
3882 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3884 (define_expand "ble"
3886 (if_then_else (match_dup 1)
3887 (label_ref (match_operand 0 "" ""))
3890 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3892 (define_expand "bgt"
3894 (if_then_else (match_dup 1)
3895 (label_ref (match_operand 0 "" ""))
3898 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3900 (define_expand "bge"
3902 (if_then_else (match_dup 1)
3903 (label_ref (match_operand 0 "" ""))
3906 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3908 (define_expand "bltu"
3910 (if_then_else (match_dup 1)
3911 (label_ref (match_operand 0 "" ""))
3914 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3916 (define_expand "bleu"
3918 (if_then_else (match_dup 1)
3919 (label_ref (match_operand 0 "" ""))
3922 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3924 (define_expand "bgtu"
3926 (if_then_else (match_dup 1)
3927 (label_ref (match_operand 0 "" ""))
3930 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3932 (define_expand "bgeu"
3934 (if_then_else (match_dup 1)
3935 (label_ref (match_operand 0 "" ""))
3938 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3940 (define_expand "bunordered"
3942 (if_then_else (match_dup 1)
3943 (label_ref (match_operand 0 "" ""))
3946 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3948 (define_expand "bordered"
3950 (if_then_else (match_dup 1)
3951 (label_ref (match_operand 0 "" ""))
3954 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3956 (define_expand "seq"
3957 [(set (match_operand:DI 0 "register_operand" "")
3960 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3962 (define_expand "sne"
3963 [(set (match_operand:DI 0 "register_operand" "")
3966 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3968 (define_expand "slt"
3969 [(set (match_operand:DI 0 "register_operand" "")
3972 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3974 (define_expand "sle"
3975 [(set (match_operand:DI 0 "register_operand" "")
3978 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3980 (define_expand "sgt"
3981 [(set (match_operand:DI 0 "register_operand" "")
3984 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3986 (define_expand "sge"
3987 [(set (match_operand:DI 0 "register_operand" "")
3990 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3992 (define_expand "sltu"
3993 [(set (match_operand:DI 0 "register_operand" "")
3996 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3998 (define_expand "sleu"
3999 [(set (match_operand:DI 0 "register_operand" "")
4002 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4004 (define_expand "sgtu"
4005 [(set (match_operand:DI 0 "register_operand" "")
4008 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4010 (define_expand "sgeu"
4011 [(set (match_operand:DI 0 "register_operand" "")
4014 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4016 (define_expand "sunordered"
4017 [(set (match_operand:DI 0 "register_operand" "")
4020 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4022 (define_expand "sordered"
4023 [(set (match_operand:DI 0 "register_operand" "")
4026 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4028 ;; These are the main define_expand's used to make conditional moves.
4030 (define_expand "movsicc"
4031 [(set (match_operand:SI 0 "register_operand" "")
4032 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4033 (match_operand:SI 2 "reg_or_8bit_operand" "")
4034 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4037 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4041 (define_expand "movdicc"
4042 [(set (match_operand:DI 0 "register_operand" "")
4043 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4044 (match_operand:DI 2 "reg_or_8bit_operand" "")
4045 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4048 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4052 (define_expand "movsfcc"
4053 [(set (match_operand:SF 0 "register_operand" "")
4054 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4055 (match_operand:SF 2 "reg_or_8bit_operand" "")
4056 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4059 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4063 (define_expand "movdfcc"
4064 [(set (match_operand:DF 0 "register_operand" "")
4065 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4066 (match_operand:DF 2 "reg_or_8bit_operand" "")
4067 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4070 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4074 ;; These define_split definitions are used in cases when comparisons have
4075 ;; not be stated in the correct way and we need to reverse the second
4076 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4077 ;; comparison that tests the result being reversed. We have one define_split
4078 ;; for each use of a comparison. They do not match valid insns and need
4079 ;; not generate valid insns.
4081 ;; We can also handle equality comparisons (and inequality comparisons in
4082 ;; cases where the resulting add cannot overflow) by doing an add followed by
4083 ;; a comparison with zero. This is faster since the addition takes one
4084 ;; less cycle than a compare when feeding into a conditional move.
4085 ;; For this case, we also have an SImode pattern since we can merge the add
4086 ;; and sign extend and the order doesn't matter.
4088 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4089 ;; operation could have been generated.
4092 [(set (match_operand:DI 0 "register_operand" "")
4094 (match_operator 1 "comparison_operator"
4095 [(match_operand:DI 2 "reg_or_0_operand" "")
4096 (match_operand:DI 3 "reg_or_cint_operand" "")])
4097 (match_operand:DI 4 "reg_or_cint_operand" "")
4098 (match_operand:DI 5 "reg_or_cint_operand" "")))
4099 (clobber (match_operand:DI 6 "register_operand" ""))]
4100 "operands[3] != const0_rtx"
4101 [(set (match_dup 6) (match_dup 7))
4103 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4105 enum rtx_code code = GET_CODE (operands[1]);
4106 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4108 /* If we are comparing for equality with a constant and that constant
4109 appears in the arm when the register equals the constant, use the
4110 register since that is more likely to match (and to produce better code
4113 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4114 && rtx_equal_p (operands[4], operands[3]))
4115 operands[4] = operands[2];
4117 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4118 && rtx_equal_p (operands[5], operands[3]))
4119 operands[5] = operands[2];
4121 if (code == NE || code == EQ
4122 || (extended_count (operands[2], DImode, unsignedp) >= 1
4123 && extended_count (operands[3], DImode, unsignedp) >= 1))
4125 if (GET_CODE (operands[3]) == CONST_INT)
4126 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4127 GEN_INT (- INTVAL (operands[3])));
4129 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4131 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4134 else if (code == EQ || code == LE || code == LT
4135 || code == LEU || code == LTU)
4137 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4138 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4142 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4143 operands[2], operands[3]);
4144 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4149 [(set (match_operand:DI 0 "register_operand" "")
4151 (match_operator 1 "comparison_operator"
4152 [(match_operand:SI 2 "reg_or_0_operand" "")
4153 (match_operand:SI 3 "reg_or_cint_operand" "")])
4154 (match_operand:DI 4 "reg_or_8bit_operand" "")
4155 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4156 (clobber (match_operand:DI 6 "register_operand" ""))]
4157 "operands[3] != const0_rtx
4158 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4159 [(set (match_dup 6) (match_dup 7))
4161 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4163 enum rtx_code code = GET_CODE (operands[1]);
4164 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4167 if ((code != NE && code != EQ
4168 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4169 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4172 if (GET_CODE (operands[3]) == CONST_INT)
4173 tem = gen_rtx_PLUS (SImode, operands[2],
4174 GEN_INT (- INTVAL (operands[3])));
4176 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4178 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4179 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4180 operands[6], const0_rtx);
4186 (match_operator 1 "comparison_operator"
4187 [(match_operand:DI 2 "reg_or_0_operand" "")
4188 (match_operand:DI 3 "reg_or_cint_operand" "")])
4189 (label_ref (match_operand 0 "" ""))
4191 (clobber (match_operand:DI 4 "register_operand" ""))]
4192 "operands[3] != const0_rtx"
4193 [(set (match_dup 4) (match_dup 5))
4194 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4196 enum rtx_code code = GET_CODE (operands[1]);
4197 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4199 if (code == NE || code == EQ
4200 || (extended_count (operands[2], DImode, unsignedp) >= 1
4201 && extended_count (operands[3], DImode, unsignedp) >= 1))
4203 if (GET_CODE (operands[3]) == CONST_INT)
4204 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4205 GEN_INT (- INTVAL (operands[3])));
4207 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4209 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4212 else if (code == EQ || code == LE || code == LT
4213 || code == LEU || code == LTU)
4215 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4216 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4220 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4221 operands[2], operands[3]);
4222 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4229 (match_operator 1 "comparison_operator"
4230 [(match_operand:SI 2 "reg_or_0_operand" "")
4231 (match_operand:SI 3 "const_int_operand" "")])
4232 (label_ref (match_operand 0 "" ""))
4234 (clobber (match_operand:DI 4 "register_operand" ""))]
4235 "operands[3] != const0_rtx
4236 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4237 [(set (match_dup 4) (match_dup 5))
4238 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4242 if (GET_CODE (operands[3]) == CONST_INT)
4243 tem = gen_rtx_PLUS (SImode, operands[2],
4244 GEN_INT (- INTVAL (operands[3])));
4246 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4248 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4249 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4250 operands[4], const0_rtx);
4253 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4254 ;; This eliminates one, and sometimes two, insns when the AND can be done
4257 [(set (match_operand:DI 0 "register_operand" "")
4258 (match_operator:DI 1 "comparison_operator"
4259 [(match_operand:DI 2 "register_operand" "")
4260 (match_operand:DI 3 "const_int_operand" "")]))
4261 (clobber (match_operand:DI 4 "register_operand" ""))]
4262 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4263 && (GET_CODE (operands[1]) == GTU
4264 || GET_CODE (operands[1]) == LEU
4265 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4266 && extended_count (operands[2], DImode, 1) > 0))"
4267 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4268 (set (match_dup 0) (match_dup 6))]
4270 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4271 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4272 || GET_CODE (operands[1]) == GT)
4274 DImode, operands[4], const0_rtx);
4277 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4280 [(set (match_operand 0 "register_operand" "")
4281 (if_then_else (match_operator 1 "signed_comparison_operator"
4282 [(match_operand:DI 2 "reg_or_0_operand" "")
4284 (match_operand 3 "const_int_operand" "")
4285 (match_operand 4 "const_int_operand" "")))]
4289 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4290 operands[2], operands[3], operands[4]))
4296 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4297 ;; Oh well, we match it in movcc, so it must be partially our fault.
4299 [(set (match_operand 0 "register_operand" "")
4300 (if_then_else (match_operator 1 "signed_comparison_operator"
4302 (match_operand:DI 2 "reg_or_0_operand" "")])
4303 (match_operand 3 "const_int_operand" "")
4304 (match_operand 4 "const_int_operand" "")))]
4308 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4309 operands[0], operands[2], operands[3],
4316 (define_insn_and_split "*cmp_sadd_di"
4317 [(set (match_operand:DI 0 "register_operand" "=r")
4318 (plus:DI (if_then_else:DI
4319 (match_operator 1 "alpha_zero_comparison_operator"
4320 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4322 (match_operand:DI 3 "const48_operand" "I")
4324 (match_operand:DI 4 "sext_add_operand" "rIO")))
4325 (clobber (match_scratch:DI 5 "=r"))]
4328 "! no_new_pseudos || reload_completed"
4330 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4332 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4335 if (! no_new_pseudos)
4336 operands[5] = gen_reg_rtx (DImode);
4337 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4338 operands[5] = operands[0];
4341 (define_insn_and_split "*cmp_sadd_si"
4342 [(set (match_operand:SI 0 "register_operand" "=r")
4343 (plus:SI (if_then_else:SI
4344 (match_operator 1 "alpha_zero_comparison_operator"
4345 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4347 (match_operand:SI 3 "const48_operand" "I")
4349 (match_operand:SI 4 "sext_add_operand" "rIO")))
4350 (clobber (match_scratch:SI 5 "=r"))]
4353 "! no_new_pseudos || reload_completed"
4355 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4357 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4360 if (! no_new_pseudos)
4361 operands[5] = gen_reg_rtx (DImode);
4362 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4363 operands[5] = operands[0];
4366 (define_insn_and_split "*cmp_sadd_sidi"
4367 [(set (match_operand:DI 0 "register_operand" "=r")
4369 (plus:SI (if_then_else:SI
4370 (match_operator 1 "alpha_zero_comparison_operator"
4371 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4373 (match_operand:SI 3 "const48_operand" "I")
4375 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4376 (clobber (match_scratch:SI 5 "=r"))]
4379 "! no_new_pseudos || reload_completed"
4381 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4383 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4386 if (! no_new_pseudos)
4387 operands[5] = gen_reg_rtx (DImode);
4388 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4389 operands[5] = operands[0];
4392 (define_insn_and_split "*cmp_ssub_di"
4393 [(set (match_operand:DI 0 "register_operand" "=r")
4394 (minus:DI (if_then_else:DI
4395 (match_operator 1 "alpha_zero_comparison_operator"
4396 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4398 (match_operand:DI 3 "const48_operand" "I")
4400 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4401 (clobber (match_scratch:DI 5 "=r"))]
4404 "! no_new_pseudos || reload_completed"
4406 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4408 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4411 if (! no_new_pseudos)
4412 operands[5] = gen_reg_rtx (DImode);
4413 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4414 operands[5] = operands[0];
4417 (define_insn_and_split "*cmp_ssub_si"
4418 [(set (match_operand:SI 0 "register_operand" "=r")
4419 (minus:SI (if_then_else:SI
4420 (match_operator 1 "alpha_zero_comparison_operator"
4421 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4423 (match_operand:SI 3 "const48_operand" "I")
4425 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4426 (clobber (match_scratch:SI 5 "=r"))]
4429 "! no_new_pseudos || reload_completed"
4431 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4433 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4436 if (! no_new_pseudos)
4437 operands[5] = gen_reg_rtx (DImode);
4438 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4439 operands[5] = operands[0];
4442 (define_insn_and_split "*cmp_ssub_sidi"
4443 [(set (match_operand:DI 0 "register_operand" "=r")
4445 (minus:SI (if_then_else:SI
4446 (match_operator 1 "alpha_zero_comparison_operator"
4447 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4449 (match_operand:SI 3 "const48_operand" "I")
4451 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4452 (clobber (match_scratch:SI 5 "=r"))]
4455 "! no_new_pseudos || reload_completed"
4457 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4459 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4462 if (! no_new_pseudos)
4463 operands[5] = gen_reg_rtx (DImode);
4464 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4465 operands[5] = operands[0];
4468 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4469 ;; work differently, so we have different patterns for each.
4471 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4472 ;; call. The CIW contains information about arguments passed in registers
4473 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4474 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4475 ;; in the presence of inlining since the CIWs for calls performed by the
4476 ;; inlined function must be stored in the SSIB of the function it is inlined
4477 ;; into as well. We encode the CIW in an unspec and append it to the list
4478 ;; of the CIWs for the current function only when the instruction for loading
4479 ;; $25 is generated.
4481 (define_expand "call"
4482 [(use (match_operand:DI 0 "" ""))
4483 (use (match_operand 1 "" ""))
4484 (use (match_operand 2 "" ""))
4485 (use (match_operand 3 "" ""))]
4488 if (TARGET_ABI_WINDOWS_NT)
4489 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4490 else if (TARGET_ABI_OPEN_VMS)
4491 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4492 else if (TARGET_ABI_UNICOSMK)
4493 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4495 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4499 (define_expand "sibcall"
4500 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4501 (match_operand 1 "" ""))
4502 (use (reg:DI 29))])]
4505 if (GET_CODE (operands[0]) != MEM)
4507 operands[0] = XEXP (operands[0], 0);
4510 (define_expand "call_osf"
4511 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4512 (match_operand 1 "" ""))
4514 (clobber (reg:DI 26))])]
4517 if (GET_CODE (operands[0]) != MEM)
4520 operands[0] = XEXP (operands[0], 0);
4521 if (! call_operand (operands[0], Pmode))
4523 rtx pv = gen_rtx_REG (Pmode, 27);
4524 emit_move_insn (pv, operands[0]);
4529 (define_expand "call_nt"
4530 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4531 (match_operand 1 "" ""))
4532 (clobber (reg:DI 26))])]
4535 if (GET_CODE (operands[0]) != MEM)
4538 operands[0] = XEXP (operands[0], 0);
4539 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4540 operands[0] = force_reg (DImode, operands[0]);
4543 ;; Calls on Unicos/Mk are always indirect.
4544 ;; op 0: symbol ref for called function
4545 ;; op 1: CIW for $25 represented by an unspec
4547 (define_expand "call_umk"
4548 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4549 (match_operand 1 "" ""))
4551 (clobber (reg:DI 26))])]
4554 if (GET_CODE (operands[0]) != MEM)
4557 /* Always load the address of the called function into a register;
4558 load the CIW in $25. */
4560 operands[0] = XEXP (operands[0], 0);
4561 if (GET_CODE (operands[0]) != REG)
4562 operands[0] = force_reg (DImode, operands[0]);
4564 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4568 ;; call openvms/alpha
4569 ;; op 0: symbol ref for called function
4570 ;; op 1: next_arg_reg (argument information value for R25)
4572 (define_expand "call_vms"
4573 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4574 (match_operand 1 "" ""))
4578 (clobber (reg:DI 27))])]
4581 if (GET_CODE (operands[0]) != MEM)
4584 operands[0] = XEXP (operands[0], 0);
4586 /* Always load AI with argument information, then handle symbolic and
4587 indirect call differently. Load RA and set operands[2] to PV in
4590 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4591 if (GET_CODE (operands[0]) == SYMBOL_REF)
4593 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4595 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4597 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4601 emit_move_insn (gen_rtx_REG (Pmode, 26),
4602 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4603 operands[2] = operands[0];
4608 (define_expand "call_value"
4609 [(use (match_operand 0 "" ""))
4610 (use (match_operand:DI 1 "" ""))
4611 (use (match_operand 2 "" ""))
4612 (use (match_operand 3 "" ""))
4613 (use (match_operand 4 "" ""))]
4616 if (TARGET_ABI_WINDOWS_NT)
4617 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4618 else if (TARGET_ABI_OPEN_VMS)
4619 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4621 else if (TARGET_ABI_UNICOSMK)
4622 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4625 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4630 (define_expand "sibcall_value"
4631 [(parallel [(set (match_operand 0 "" "")
4632 (call (mem:DI (match_operand 1 "" ""))
4633 (match_operand 2 "" "")))
4634 (use (reg:DI 29))])]
4637 if (GET_CODE (operands[1]) != MEM)
4639 operands[1] = XEXP (operands[1], 0);
4642 (define_expand "call_value_osf"
4643 [(parallel [(set (match_operand 0 "" "")
4644 (call (mem:DI (match_operand 1 "" ""))
4645 (match_operand 2 "" "")))
4647 (clobber (reg:DI 26))])]
4650 if (GET_CODE (operands[1]) != MEM)
4653 operands[1] = XEXP (operands[1], 0);
4654 if (! call_operand (operands[1], Pmode))
4656 rtx pv = gen_rtx_REG (Pmode, 27);
4657 emit_move_insn (pv, operands[1]);
4662 (define_expand "call_value_nt"
4663 [(parallel [(set (match_operand 0 "" "")
4664 (call (mem:DI (match_operand 1 "" ""))
4665 (match_operand 2 "" "")))
4666 (clobber (reg:DI 26))])]
4669 if (GET_CODE (operands[1]) != MEM)
4672 operands[1] = XEXP (operands[1], 0);
4673 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4674 operands[1] = force_reg (DImode, operands[1]);
4677 (define_expand "call_value_vms"
4678 [(parallel [(set (match_operand 0 "" "")
4679 (call (mem:DI (match_operand:DI 1 "" ""))
4680 (match_operand 2 "" "")))
4684 (clobber (reg:DI 27))])]
4687 if (GET_CODE (operands[1]) != MEM)
4690 operands[1] = XEXP (operands[1], 0);
4692 /* Always load AI with argument information, then handle symbolic and
4693 indirect call differently. Load RA and set operands[3] to PV in
4696 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4697 if (GET_CODE (operands[1]) == SYMBOL_REF)
4699 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4701 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4703 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4707 emit_move_insn (gen_rtx_REG (Pmode, 26),
4708 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4709 operands[3] = operands[1];
4713 (define_expand "call_value_umk"
4714 [(parallel [(set (match_operand 0 "" "")
4715 (call (mem:DI (match_operand 1 "" ""))
4716 (match_operand 2 "" "")))
4718 (clobber (reg:DI 26))])]
4721 if (GET_CODE (operands[1]) != MEM)
4724 operands[1] = XEXP (operands[1], 0);
4725 if (GET_CODE (operands[1]) != REG)
4726 operands[1] = force_reg (DImode, operands[1]);
4728 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4731 (define_insn "*call_osf_1_er"
4732 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4733 (match_operand 1 "" ""))
4735 (clobber (reg:DI 26))]
4736 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4738 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4740 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4741 [(set_attr "type" "jsr")
4742 (set_attr "length" "12,*,16")])
4744 ;; We must use peep2 instead of a split because we need accurate life
4745 ;; information for $gp. Consider the case of { bar(); while (1); }.
4747 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4748 (match_operand 1 "" ""))
4750 (clobber (reg:DI 26))])]
4751 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4752 && ! current_file_function_operand (operands[0], Pmode)
4753 && peep2_regno_dead_p (1, 29)"
4754 [(parallel [(call (mem:DI (match_dup 2))
4756 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4757 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4758 (use (match_dup 0))])]
4760 if (CONSTANT_P (operands[0]))
4762 operands[2] = gen_rtx_REG (Pmode, 27);
4763 emit_move_insn (operands[2], operands[0]);
4767 operands[2] = operands[0];
4768 operands[0] = const0_rtx;
4773 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4774 (match_operand 1 "" ""))
4776 (clobber (reg:DI 26))])]
4777 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4778 && ! current_file_function_operand (operands[0], Pmode)
4779 && ! peep2_regno_dead_p (1, 29)"
4780 [(parallel [(call (mem:DI (match_dup 2))
4782 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4783 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4784 (use (match_dup 0))])
4786 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4788 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4790 if (CONSTANT_P (operands[0]))
4792 operands[2] = gen_rtx_REG (Pmode, 27);
4793 emit_move_insn (operands[2], operands[0]);
4797 operands[2] = operands[0];
4798 operands[0] = const0_rtx;
4800 operands[3] = GEN_INT (alpha_next_sequence_number++);
4803 ;; We add a blockage unspec_volatile to prevent insns from moving down
4804 ;; from above the call to in between the call and the ldah gpdisp.
4806 (define_insn "*call_osf_2_er"
4807 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4808 (match_operand 1 "" ""))
4809 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4810 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4811 (use (match_operand 2 "" ""))]
4812 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4814 [(set_attr "type" "jsr")])
4816 (define_insn "*call_osf_1_noreturn"
4817 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4818 (match_operand 1 "" ""))
4820 (clobber (reg:DI 26))]
4821 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4822 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4827 [(set_attr "type" "jsr")
4828 (set_attr "length" "*,*,8")])
4830 (define_insn "*call_osf_1"
4831 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4832 (match_operand 1 "" ""))
4834 (clobber (reg:DI 26))]
4835 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4837 jsr $26,($27),0\;ldgp $29,0($26)
4839 jsr $26,%0\;ldgp $29,0($26)"
4840 [(set_attr "type" "jsr")
4841 (set_attr "length" "12,*,16")])
4843 ;; Need 's' alternative for OSF/1, which implements profiling via linker
4844 ;; tricks. Note that the DEC assembler expands "jmp foo" with $at, which
4845 ;; doesn't do what we want.
4846 (define_insn "*sibcall_osf_1"
4847 [(call (mem:DI (match_operand:DI 0 "current_file_function_operand" "R,s"))
4848 (match_operand 1 "" ""))
4853 lda $27,%0\;jmp $31,($27),%0"
4854 [(set_attr "type" "jsr")
4855 (set_attr "length" "*,8")])
4857 (define_insn "*call_nt_1"
4858 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4859 (match_operand 1 "" ""))
4860 (clobber (reg:DI 26))]
4861 "TARGET_ABI_WINDOWS_NT"
4866 [(set_attr "type" "jsr")
4867 (set_attr "length" "*,*,12")])
4869 (define_insn "*call_vms_1"
4870 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4871 (match_operand 1 "" ""))
4872 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4875 (clobber (reg:DI 27))]
4876 "TARGET_ABI_OPEN_VMS"
4878 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4879 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4880 [(set_attr "type" "jsr")
4881 (set_attr "length" "12,16")])
4883 (define_insn "*call_umk_1"
4884 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4885 (match_operand 1 "" ""))
4887 (clobber (reg:DI 26))]
4888 "TARGET_ABI_UNICOSMK"
4890 [(set_attr "type" "jsr")])
4892 ;; Call subroutine returning any type.
4894 (define_expand "untyped_call"
4895 [(parallel [(call (match_operand 0 "" "")
4897 (match_operand 1 "" "")
4898 (match_operand 2 "" "")])]
4903 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4905 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4907 rtx set = XVECEXP (operands[2], 0, i);
4908 emit_move_insn (SET_DEST (set), SET_SRC (set));
4911 /* The optimizer does not know that the call sets the function value
4912 registers we stored in the result block. We avoid problems by
4913 claiming that all hard registers are used and clobbered at this
4915 emit_insn (gen_blockage ());
4920 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4921 ;; all of memory. This blocks insns from being moved across this point.
4923 (define_insn "blockage"
4924 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4927 [(set_attr "length" "0")])
4931 (label_ref (match_operand 0 "" "")))]
4934 [(set_attr "type" "ibr")])
4936 (define_expand "return"
4941 (define_insn "*return_internal"
4945 [(set_attr "type" "ibr")])
4947 (define_insn "indirect_jump"
4948 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4951 [(set_attr "type" "ibr")])
4953 (define_expand "tablejump"
4954 [(parallel [(set (pc)
4955 (match_operand 0 "register_operand" ""))
4956 (use (label_ref:DI (match_operand 1 "" "")))])]
4959 if (TARGET_ABI_WINDOWS_NT)
4961 rtx dest = gen_reg_rtx (DImode);
4962 emit_insn (gen_extendsidi2 (dest, operands[0]));
4965 else if (TARGET_ABI_OSF)
4967 rtx dest = gen_reg_rtx (DImode);
4968 emit_insn (gen_extendsidi2 (dest, operands[0]));
4969 emit_insn (gen_adddi3 (dest, gen_rtx_REG (DImode, 29), dest));
4974 (define_insn "*tablejump_osf_nt_internal"
4976 (match_operand:DI 0 "register_operand" "r"))
4977 (use (label_ref:DI (match_operand 1 "" "")))]
4978 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4979 && alpha_tablejump_addr_vec (insn)"
4981 operands[2] = alpha_tablejump_best_label (insn);
4982 return "jmp $31,(%0),%2";
4984 [(set_attr "type" "ibr")])
4986 (define_insn "*tablejump_internal"
4988 (match_operand:DI 0 "register_operand" "r"))
4989 (use (label_ref (match_operand 1 "" "")))]
4992 [(set_attr "type" "ibr")])
4994 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4995 ;; want to have to include pal.h in our .s file.
4997 ;; Technically the type for call_pal is jsr, but we use that for determining
4998 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5001 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5004 [(set_attr "type" "ibr")])
5006 ;; Finally, we have the basic data motion insns. The byte and word insns
5007 ;; are done via define_expand. Start with the floating-point insns, since
5008 ;; they are simpler.
5010 (define_insn "*movsf_nofix"
5011 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5012 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5013 "TARGET_FPREGS && ! TARGET_FIX
5014 && (register_operand (operands[0], SFmode)
5015 || reg_or_fp0_operand (operands[1], SFmode))"
5023 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5025 (define_insn "*movsf_fix"
5026 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5027 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5028 "TARGET_FPREGS && TARGET_FIX
5029 && (register_operand (operands[0], SFmode)
5030 || reg_or_fp0_operand (operands[1], SFmode))"
5040 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5042 (define_insn "*movsf_nofp"
5043 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5044 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5046 && (register_operand (operands[0], SFmode)
5047 || reg_or_fp0_operand (operands[1], SFmode))"
5052 [(set_attr "type" "ilog,ild,ist")])
5054 (define_insn "*movdf_nofix"
5055 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5056 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5057 "TARGET_FPREGS && ! TARGET_FIX
5058 && (register_operand (operands[0], DFmode)
5059 || reg_or_fp0_operand (operands[1], DFmode))"
5067 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5069 (define_insn "*movdf_fix"
5070 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5071 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5072 "TARGET_FPREGS && TARGET_FIX
5073 && (register_operand (operands[0], DFmode)
5074 || reg_or_fp0_operand (operands[1], DFmode))"
5084 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5086 (define_insn "*movdf_nofp"
5087 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5088 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5090 && (register_operand (operands[0], DFmode)
5091 || reg_or_fp0_operand (operands[1], DFmode))"
5096 [(set_attr "type" "ilog,ild,ist")])
5098 ;; Subregs suck for register allocation. Pretend we can move TFmode
5099 ;; data between general registers until after reload.
5101 (define_insn_and_split "*movtf_internal"
5102 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5103 (match_operand:TF 1 "input_operand" "roG,rG"))]
5104 "register_operand (operands[0], TFmode)
5105 || reg_or_fp0_operand (operands[1], TFmode)"
5108 [(set (match_dup 0) (match_dup 2))
5109 (set (match_dup 1) (match_dup 3))]
5111 alpha_split_tfmode_pair (operands);
5112 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5115 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5116 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5120 (define_expand "movsf"
5121 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5122 (match_operand:SF 1 "general_operand" ""))]
5125 if (GET_CODE (operands[0]) == MEM
5126 && ! reg_or_fp0_operand (operands[1], SFmode))
5127 operands[1] = force_reg (SFmode, operands[1]);
5130 (define_expand "movdf"
5131 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5132 (match_operand:DF 1 "general_operand" ""))]
5135 if (GET_CODE (operands[0]) == MEM
5136 && ! reg_or_fp0_operand (operands[1], DFmode))
5137 operands[1] = force_reg (DFmode, operands[1]);
5140 (define_expand "movtf"
5141 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5142 (match_operand:TF 1 "general_operand" ""))]
5145 if (GET_CODE (operands[0]) == MEM
5146 && ! reg_or_fp0_operand (operands[1], TFmode))
5147 operands[1] = force_reg (TFmode, operands[1]);
5150 (define_insn "*movsi_nofix"
5151 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5152 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5153 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5154 && (register_operand (operands[0], SImode)
5155 || reg_or_0_operand (operands[1], SImode))"
5165 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5167 (define_insn "*movsi_fix"
5168 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5169 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5170 "TARGET_ABI_OSF && TARGET_FIX
5171 && (register_operand (operands[0], SImode)
5172 || reg_or_0_operand (operands[1], SImode))"
5184 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5186 (define_insn "*movsi_nt_vms"
5187 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5188 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5189 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5190 && (register_operand (operands[0], SImode)
5191 || reg_or_0_operand (operands[1], SImode))"
5202 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5204 (define_insn "*movhi_nobwx"
5205 [(set (match_operand:HI 0 "register_operand" "=r,r")
5206 (match_operand:HI 1 "input_operand" "rJ,n"))]
5208 && (register_operand (operands[0], HImode)
5209 || register_operand (operands[1], HImode))"
5213 [(set_attr "type" "ilog,iadd")])
5215 (define_insn "*movhi_bwx"
5216 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5217 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5219 && (register_operand (operands[0], HImode)
5220 || reg_or_0_operand (operands[1], HImode))"
5226 [(set_attr "type" "ilog,iadd,ild,ist")])
5228 (define_insn "*movqi_nobwx"
5229 [(set (match_operand:QI 0 "register_operand" "=r,r")
5230 (match_operand:QI 1 "input_operand" "rJ,n"))]
5232 && (register_operand (operands[0], QImode)
5233 || register_operand (operands[1], QImode))"
5237 [(set_attr "type" "ilog,iadd")])
5239 (define_insn "*movqi_bwx"
5240 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5241 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5243 && (register_operand (operands[0], QImode)
5244 || reg_or_0_operand (operands[1], QImode))"
5250 [(set_attr "type" "ilog,iadd,ild,ist")])
5252 ;; We do two major things here: handle mem->mem and construct long
5255 (define_expand "movsi"
5256 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5257 (match_operand:SI 1 "general_operand" ""))]
5260 if (alpha_expand_mov (SImode, operands))
5264 ;; Split a load of a large constant into the appropriate two-insn
5268 [(set (match_operand:SI 0 "register_operand" "")
5269 (match_operand:SI 1 "const_int_operand" ""))]
5270 "! add_operand (operands[1], SImode)"
5271 [(set (match_dup 0) (match_dup 2))
5272 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5275 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5277 if (tem == operands[0])
5283 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5284 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5285 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5286 ;; notes and update LABEL_NUSES because this is not done automatically.
5287 ;; Labels may be incorrectly deleted if we don't do this.
5289 ;; Describing what the individual instructions do correctly is too complicated
5290 ;; so use UNSPECs for each of the three parts of an address.
5293 [(set (match_operand:DI 0 "register_operand" "")
5294 (match_operand:DI 1 "symbolic_operand" ""))]
5295 "TARGET_ABI_UNICOSMK && reload_completed"
5298 rtx insn1, insn2, insn3;
5300 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5301 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5302 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5303 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5304 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5306 if (GET_CODE (operands[1]) == LABEL_REF)
5310 label = XEXP (operands[1], 0);
5311 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5313 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5315 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5317 LABEL_NUSES (label) += 3;
5322 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5324 (define_insn "umk_laum"
5325 [(set (match_operand:DI 0 "register_operand" "=r")
5326 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5328 "TARGET_ABI_UNICOSMK"
5330 [(set_attr "type" "iadd")])
5332 (define_insn "umk_lalm"
5333 [(set (match_operand:DI 0 "register_operand" "=r")
5334 (plus:DI (match_operand:DI 1 "register_operand" "r")
5335 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5337 "TARGET_ABI_UNICOSMK"
5339 [(set_attr "type" "iadd")])
5341 (define_insn "umk_lal"
5342 [(set (match_operand:DI 0 "register_operand" "=r")
5343 (plus:DI (match_operand:DI 1 "register_operand" "r")
5344 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5346 "TARGET_ABI_UNICOSMK"
5348 [(set_attr "type" "iadd")])
5350 ;; Add a new call information word to the current function's list of CIWs
5351 ;; and load its index into $25. Doing it here ensures that the CIW will be
5352 ;; associated with the correct function even in the presence of inlining.
5354 (define_insn "*umk_load_ciw"
5356 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5357 "TARGET_ABI_UNICOSMK"
5359 operands[0] = unicosmk_add_call_info_word (operands[0]);
5360 return "lda $25,%0";
5362 [(set_attr "type" "iadd")])
5364 (define_insn "*movdi_er_low_l"
5365 [(set (match_operand:DI 0 "register_operand" "=r")
5366 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5367 (match_operand:DI 2 "local_symbolic_operand" "")))]
5368 "TARGET_EXPLICIT_RELOCS"
5370 if (true_regnum (operands[1]) == 29)
5371 return "lda %0,%2(%1)\t\t!gprel";
5373 return "lda %0,%2(%1)\t\t!gprellow";
5376 (define_insn "movdi_er_high_g"
5377 [(set (match_operand:DI 0 "register_operand" "=r")
5378 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5379 (match_operand:DI 2 "global_symbolic_operand" "")
5380 (match_operand 3 "const_int_operand" "")]
5382 "TARGET_EXPLICIT_RELOCS"
5383 "ldq %0,%2(%1)\t\t!literal"
5384 [(set_attr "type" "ldsym")])
5386 (define_insn "*movdi_er_nofix"
5387 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
5388 (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f"))]
5389 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5390 && (register_operand (operands[0], DImode)
5391 || reg_or_0_operand (operands[1], DImode))"
5402 [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst")])
5404 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5405 ;; have been split up by the rules above but we shouldn't reject the
5406 ;; possibility of them getting through.
5408 (define_insn "*movdi_nofix"
5409 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5410 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5412 && (register_operand (operands[0], DImode)
5413 || reg_or_0_operand (operands[1], DImode))"
5418 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5425 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5426 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5428 (define_insn "*movdi_er_fix"
5429 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5430 (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f,*f,r"))]
5431 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5432 && (register_operand (operands[0], DImode)
5433 || reg_or_0_operand (operands[1], DImode))"
5446 [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5448 (define_insn "*movdi_fix"
5449 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5450 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5451 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5452 && (register_operand (operands[0], DImode)
5453 || reg_or_0_operand (operands[1], DImode))"
5466 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5468 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5469 ;; often appears dead to the life analysis code, at which point we
5470 ;; abort for emitting dead prologue instructions. Force this live.
5472 (define_insn "force_movdi"
5473 [(set (match_operand:DI 0 "register_operand" "=r")
5474 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5475 UNSPECV_FORCE_MOV))]
5478 [(set_attr "type" "ilog")])
5480 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5481 ;; memory, and construct long 32-bit constants.
5483 (define_expand "movdi"
5484 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5485 (match_operand:DI 1 "general_operand" ""))]
5488 if (alpha_expand_mov (DImode, operands))
5492 ;; Split a load of a large constant into the appropriate two-insn
5496 [(set (match_operand:DI 0 "register_operand" "")
5497 (match_operand:DI 1 "const_int_operand" ""))]
5498 "! add_operand (operands[1], DImode)"
5499 [(set (match_dup 0) (match_dup 2))
5500 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5503 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5505 if (tem == operands[0])
5511 ;; These are the partial-word cases.
5513 ;; First we have the code to load an aligned word. Operand 0 is the register
5514 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5515 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5516 ;; number of bits within the word that the value is. Operand 3 is an SImode
5517 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5518 ;; same register. It is allowed to conflict with operand 1 as well.
5520 (define_expand "aligned_loadqi"
5521 [(set (match_operand:SI 3 "register_operand" "")
5522 (match_operand:SI 1 "memory_operand" ""))
5523 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5524 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5526 (match_operand:DI 2 "const_int_operand" "")))]
5531 (define_expand "aligned_loadhi"
5532 [(set (match_operand:SI 3 "register_operand" "")
5533 (match_operand:SI 1 "memory_operand" ""))
5534 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5535 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5537 (match_operand:DI 2 "const_int_operand" "")))]
5542 ;; Similar for unaligned loads, where we use the sequence from the
5543 ;; Alpha Architecture manual. We have to distinguish between little-endian
5544 ;; and big-endian systems as the sequences are different.
5546 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5547 ;; operand 3 can overlap the input and output registers.
5549 (define_expand "unaligned_loadqi"
5550 [(use (match_operand:QI 0 "register_operand" ""))
5551 (use (match_operand:DI 1 "address_operand" ""))
5552 (use (match_operand:DI 2 "register_operand" ""))
5553 (use (match_operand:DI 3 "register_operand" ""))]
5556 if (WORDS_BIG_ENDIAN)
5557 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5558 operands[2], operands[3]));
5560 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5561 operands[2], operands[3]));
5565 (define_expand "unaligned_loadqi_le"
5566 [(set (match_operand:DI 2 "register_operand" "")
5567 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5569 (set (match_operand:DI 3 "register_operand" "")
5571 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5572 (zero_extract:DI (match_dup 2)
5574 (ashift:DI (match_dup 3) (const_int 3))))]
5575 "! WORDS_BIG_ENDIAN"
5578 (define_expand "unaligned_loadqi_be"
5579 [(set (match_operand:DI 2 "register_operand" "")
5580 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5582 (set (match_operand:DI 3 "register_operand" "")
5584 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5585 (zero_extract:DI (match_dup 2)
5589 (ashift:DI (match_dup 3) (const_int 3)))))]
5593 (define_expand "unaligned_loadhi"
5594 [(use (match_operand:QI 0 "register_operand" ""))
5595 (use (match_operand:DI 1 "address_operand" ""))
5596 (use (match_operand:DI 2 "register_operand" ""))
5597 (use (match_operand:DI 3 "register_operand" ""))]
5600 if (WORDS_BIG_ENDIAN)
5601 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5602 operands[2], operands[3]));
5604 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5605 operands[2], operands[3]));
5609 (define_expand "unaligned_loadhi_le"
5610 [(set (match_operand:DI 2 "register_operand" "")
5611 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5613 (set (match_operand:DI 3 "register_operand" "")
5615 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5616 (zero_extract:DI (match_dup 2)
5618 (ashift:DI (match_dup 3) (const_int 3))))]
5619 "! WORDS_BIG_ENDIAN"
5622 (define_expand "unaligned_loadhi_be"
5623 [(set (match_operand:DI 2 "register_operand" "")
5624 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5626 (set (match_operand:DI 3 "register_operand" "")
5627 (plus:DI (match_dup 1) (const_int 1)))
5628 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5629 (zero_extract:DI (match_dup 2)
5633 (ashift:DI (match_dup 3) (const_int 3)))))]
5637 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5638 ;; aligned SImode MEM. Operand 1 is the register containing the
5639 ;; byte or word to store. Operand 2 is the number of bits within the word that
5640 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5642 (define_expand "aligned_store"
5643 [(set (match_operand:SI 3 "register_operand" "")
5644 (match_operand:SI 0 "memory_operand" ""))
5645 (set (subreg:DI (match_dup 3) 0)
5646 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5647 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5648 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5649 (match_operand:DI 2 "const_int_operand" "")))
5650 (set (subreg:DI (match_dup 4) 0)
5651 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5652 (set (match_dup 0) (match_dup 4))]
5655 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5656 << INTVAL (operands[2])));
5659 ;; For the unaligned byte and halfword cases, we use code similar to that
5660 ;; in the ;; Architecture book, but reordered to lower the number of registers
5661 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5662 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5663 ;; be the same temporary, if desired. If the address is in a register,
5664 ;; operand 2 can be that register.
5666 (define_expand "unaligned_storeqi"
5667 [(use (match_operand:DI 0 "address_operand" ""))
5668 (use (match_operand:QI 1 "register_operand" ""))
5669 (use (match_operand:DI 2 "register_operand" ""))
5670 (use (match_operand:DI 3 "register_operand" ""))
5671 (use (match_operand:DI 4 "register_operand" ""))]
5674 if (WORDS_BIG_ENDIAN)
5675 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5676 operands[2], operands[3],
5679 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5680 operands[2], operands[3],
5685 (define_expand "unaligned_storeqi_le"
5686 [(set (match_operand:DI 3 "register_operand" "")
5687 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5689 (set (match_operand:DI 2 "register_operand" "")
5692 (and:DI (not:DI (ashift:DI (const_int 255)
5693 (ashift:DI (match_dup 2) (const_int 3))))
5695 (set (match_operand:DI 4 "register_operand" "")
5696 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5697 (ashift:DI (match_dup 2) (const_int 3))))
5698 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5699 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5701 "! WORDS_BIG_ENDIAN"
5704 (define_expand "unaligned_storeqi_be"
5705 [(set (match_operand:DI 3 "register_operand" "")
5706 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5708 (set (match_operand:DI 2 "register_operand" "")
5711 (and:DI (not:DI (ashift:DI (const_int 255)
5712 (minus:DI (const_int 56)
5713 (ashift:DI (match_dup 2) (const_int 3)))))
5715 (set (match_operand:DI 4 "register_operand" "")
5716 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5717 (minus:DI (const_int 56)
5718 (ashift:DI (match_dup 2) (const_int 3)))))
5719 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5720 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5725 (define_expand "unaligned_storehi"
5726 [(use (match_operand:DI 0 "address_operand" ""))
5727 (use (match_operand:HI 1 "register_operand" ""))
5728 (use (match_operand:DI 2 "register_operand" ""))
5729 (use (match_operand:DI 3 "register_operand" ""))
5730 (use (match_operand:DI 4 "register_operand" ""))]
5733 if (WORDS_BIG_ENDIAN)
5734 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5735 operands[2], operands[3],
5738 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5739 operands[2], operands[3],
5744 (define_expand "unaligned_storehi_le"
5745 [(set (match_operand:DI 3 "register_operand" "")
5746 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5748 (set (match_operand:DI 2 "register_operand" "")
5751 (and:DI (not:DI (ashift:DI (const_int 65535)
5752 (ashift:DI (match_dup 2) (const_int 3))))
5754 (set (match_operand:DI 4 "register_operand" "")
5755 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5756 (ashift:DI (match_dup 2) (const_int 3))))
5757 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5758 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5760 "! WORDS_BIG_ENDIAN"
5763 (define_expand "unaligned_storehi_be"
5764 [(set (match_operand:DI 3 "register_operand" "")
5765 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5767 (set (match_operand:DI 2 "register_operand" "")
5768 (plus:DI (match_dup 0) (const_int 1)))
5770 (and:DI (not:DI (ashift:DI
5772 (minus:DI (const_int 56)
5773 (ashift:DI (match_dup 2) (const_int 3)))))
5775 (set (match_operand:DI 4 "register_operand" "")
5776 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5777 (minus:DI (const_int 56)
5778 (ashift:DI (match_dup 2) (const_int 3)))))
5779 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5780 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5785 ;; Here are the define_expand's for QI and HI moves that use the above
5786 ;; patterns. We have the normal sets, plus the ones that need scratch
5787 ;; registers for reload.
5789 (define_expand "movqi"
5790 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5791 (match_operand:QI 1 "general_operand" ""))]
5795 ? alpha_expand_mov (QImode, operands)
5796 : alpha_expand_mov_nobwx (QImode, operands))
5800 (define_expand "movhi"
5801 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5802 (match_operand:HI 1 "general_operand" ""))]
5806 ? alpha_expand_mov (HImode, operands)
5807 : alpha_expand_mov_nobwx (HImode, operands))
5811 ;; Here are the versions for reload. Note that in the unaligned cases
5812 ;; we know that the operand must not be a pseudo-register because stack
5813 ;; slots are always aligned references.
5815 (define_expand "reload_inqi"
5816 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5817 (match_operand:QI 1 "any_memory_operand" "m")
5818 (match_operand:TI 2 "register_operand" "=&r")])]
5823 if (GET_CODE (operands[1]) != MEM)
5826 if (aligned_memory_operand (operands[1], QImode))
5828 seq = gen_reload_inqi_help (operands[0], operands[1],
5829 gen_rtx_REG (SImode, REGNO (operands[2])));
5835 /* It is possible that one of the registers we got for operands[2]
5836 might coincide with that of operands[0] (which is why we made
5837 it TImode). Pick the other one to use as our scratch. */
5838 if (REGNO (operands[0]) == REGNO (operands[2]))
5839 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5841 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5843 addr = get_unaligned_address (operands[1], 0);
5844 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5845 gen_rtx_REG (DImode, REGNO (operands[0])));
5846 alpha_set_memflags (seq, operands[1]);
5852 (define_expand "reload_inhi"
5853 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5854 (match_operand:HI 1 "any_memory_operand" "m")
5855 (match_operand:TI 2 "register_operand" "=&r")])]
5860 if (GET_CODE (operands[1]) != MEM)
5863 if (aligned_memory_operand (operands[1], HImode))
5865 seq = gen_reload_inhi_help (operands[0], operands[1],
5866 gen_rtx_REG (SImode, REGNO (operands[2])));
5872 /* It is possible that one of the registers we got for operands[2]
5873 might coincide with that of operands[0] (which is why we made
5874 it TImode). Pick the other one to use as our scratch. */
5875 if (REGNO (operands[0]) == REGNO (operands[2]))
5876 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5878 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5880 addr = get_unaligned_address (operands[1], 0);
5881 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5882 gen_rtx_REG (DImode, REGNO (operands[0])));
5883 alpha_set_memflags (seq, operands[1]);
5889 (define_expand "reload_outqi"
5890 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5891 (match_operand:QI 1 "register_operand" "r")
5892 (match_operand:TI 2 "register_operand" "=&r")])]
5895 if (GET_CODE (operands[0]) != MEM)
5898 if (aligned_memory_operand (operands[0], QImode))
5900 emit_insn (gen_reload_outqi_help
5901 (operands[0], operands[1],
5902 gen_rtx_REG (SImode, REGNO (operands[2])),
5903 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5907 rtx addr = get_unaligned_address (operands[0], 0);
5908 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5909 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5910 rtx scratch3 = scratch1;
5913 if (GET_CODE (addr) == REG)
5916 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5917 scratch2, scratch3);
5918 alpha_set_memflags (seq, operands[0]);
5924 (define_expand "reload_outhi"
5925 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5926 (match_operand:HI 1 "register_operand" "r")
5927 (match_operand:TI 2 "register_operand" "=&r")])]
5930 if (GET_CODE (operands[0]) != MEM)
5933 if (aligned_memory_operand (operands[0], HImode))
5935 emit_insn (gen_reload_outhi_help
5936 (operands[0], operands[1],
5937 gen_rtx_REG (SImode, REGNO (operands[2])),
5938 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5942 rtx addr = get_unaligned_address (operands[0], 0);
5943 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5944 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5945 rtx scratch3 = scratch1;
5948 if (GET_CODE (addr) == REG)
5951 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5952 scratch2, scratch3);
5953 alpha_set_memflags (seq, operands[0]);
5959 ;; Helpers for the above. The way reload is structured, we can't
5960 ;; always get a proper address for a stack slot during reload_foo
5961 ;; expansion, so we must delay our address manipulations until after.
5963 (define_insn "reload_inqi_help"
5964 [(set (match_operand:QI 0 "register_operand" "=r")
5965 (match_operand:QI 1 "memory_operand" "m"))
5966 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5967 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5970 (define_insn "reload_inhi_help"
5971 [(set (match_operand:HI 0 "register_operand" "=r")
5972 (match_operand:HI 1 "memory_operand" "m"))
5973 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5974 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5977 (define_insn "reload_outqi_help"
5978 [(set (match_operand:QI 0 "memory_operand" "=m")
5979 (match_operand:QI 1 "register_operand" "r"))
5980 (clobber (match_operand:SI 2 "register_operand" "=r"))
5981 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5982 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5985 (define_insn "reload_outhi_help"
5986 [(set (match_operand:HI 0 "memory_operand" "=m")
5987 (match_operand:HI 1 "register_operand" "r"))
5988 (clobber (match_operand:SI 2 "register_operand" "=r"))
5989 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5990 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5994 [(set (match_operand:QI 0 "register_operand" "")
5995 (match_operand:QI 1 "memory_operand" ""))
5996 (clobber (match_operand:SI 2 "register_operand" ""))]
5997 "! TARGET_BWX && reload_completed"
6000 rtx aligned_mem, bitnum;
6001 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6003 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6009 [(set (match_operand:HI 0 "register_operand" "")
6010 (match_operand:HI 1 "memory_operand" ""))
6011 (clobber (match_operand:SI 2 "register_operand" ""))]
6012 "! TARGET_BWX && reload_completed"
6015 rtx aligned_mem, bitnum;
6016 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6018 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6024 [(set (match_operand:QI 0 "memory_operand" "")
6025 (match_operand:QI 1 "register_operand" ""))
6026 (clobber (match_operand:SI 2 "register_operand" ""))
6027 (clobber (match_operand:SI 3 "register_operand" ""))]
6028 "! TARGET_BWX && reload_completed"
6031 rtx aligned_mem, bitnum;
6032 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6033 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6034 operands[2], operands[3]));
6039 [(set (match_operand:HI 0 "memory_operand" "")
6040 (match_operand:HI 1 "register_operand" ""))
6041 (clobber (match_operand:SI 2 "register_operand" ""))
6042 (clobber (match_operand:SI 3 "register_operand" ""))]
6043 "! TARGET_BWX && reload_completed"
6046 rtx aligned_mem, bitnum;
6047 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6048 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6049 operands[2], operands[3]));
6053 ;; Bit field extract patterns which use ext[wlq][lh]
6055 (define_expand "extv"
6056 [(set (match_operand:DI 0 "register_operand" "")
6057 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6058 (match_operand:DI 2 "immediate_operand" "")
6059 (match_operand:DI 3 "immediate_operand" "")))]
6064 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6065 if (INTVAL (operands[3]) % 8 != 0
6066 || (INTVAL (operands[2]) != 16
6067 && INTVAL (operands[2]) != 32
6068 && INTVAL (operands[2]) != 64))
6071 /* From mips.md: extract_bit_field doesn't verify that our source
6072 matches the predicate, so we force it to be a MEM here. */
6073 if (GET_CODE (operands[1]) != MEM)
6076 /* The bit number is relative to the mode of operand 1 which is
6077 usually QImode (this might actually be a bug in expmed.c). Note
6078 that the bit number is negative in big-endian mode in this case.
6079 We have to convert that to the offset. */
6080 if (WORDS_BIG_ENDIAN)
6081 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6082 - INTVAL (operands[2]) - INTVAL (operands[3]);
6084 ofs = INTVAL (operands[3]);
6088 alpha_expand_unaligned_load (operands[0], operands[1],
6089 INTVAL (operands[2]) / 8,
6094 (define_expand "extzv"
6095 [(set (match_operand:DI 0 "register_operand" "")
6096 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6097 (match_operand:DI 2 "immediate_operand" "")
6098 (match_operand:DI 3 "immediate_operand" "")))]
6101 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6102 if (INTVAL (operands[3]) % 8 != 0
6103 || (INTVAL (operands[2]) != 8
6104 && INTVAL (operands[2]) != 16
6105 && INTVAL (operands[2]) != 32
6106 && INTVAL (operands[2]) != 64))
6109 if (GET_CODE (operands[1]) == MEM)
6113 /* Fail 8 bit fields, falling back on a simple byte load. */
6114 if (INTVAL (operands[2]) == 8)
6117 /* The bit number is relative to the mode of operand 1 which is
6118 usually QImode (this might actually be a bug in expmed.c). Note
6119 that the bit number is negative in big-endian mode in this case.
6120 We have to convert that to the offset. */
6121 if (WORDS_BIG_ENDIAN)
6122 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6123 - INTVAL (operands[2]) - INTVAL (operands[3]);
6125 ofs = INTVAL (operands[3]);
6129 alpha_expand_unaligned_load (operands[0], operands[1],
6130 INTVAL (operands[2]) / 8,
6136 (define_expand "insv"
6137 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6138 (match_operand:DI 1 "immediate_operand" "")
6139 (match_operand:DI 2 "immediate_operand" ""))
6140 (match_operand:DI 3 "register_operand" ""))]
6145 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6146 if (INTVAL (operands[2]) % 8 != 0
6147 || (INTVAL (operands[1]) != 16
6148 && INTVAL (operands[1]) != 32
6149 && INTVAL (operands[1]) != 64))
6152 /* From mips.md: store_bit_field doesn't verify that our source
6153 matches the predicate, so we force it to be a MEM here. */
6154 if (GET_CODE (operands[0]) != MEM)
6157 /* The bit number is relative to the mode of operand 1 which is
6158 usually QImode (this might actually be a bug in expmed.c). Note
6159 that the bit number is negative in big-endian mode in this case.
6160 We have to convert that to the offset. */
6161 if (WORDS_BIG_ENDIAN)
6162 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6163 - INTVAL (operands[1]) - INTVAL (operands[2]);
6165 ofs = INTVAL (operands[2]);
6169 alpha_expand_unaligned_store (operands[0], operands[3],
6170 INTVAL (operands[1]) / 8, ofs);
6174 ;; Block move/clear, see alpha.c for more details.
6175 ;; Argument 0 is the destination
6176 ;; Argument 1 is the source
6177 ;; Argument 2 is the length
6178 ;; Argument 3 is the alignment
6180 (define_expand "movstrqi"
6181 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6182 (match_operand:BLK 1 "memory_operand" ""))
6183 (use (match_operand:DI 2 "immediate_operand" ""))
6184 (use (match_operand:DI 3 "immediate_operand" ""))])]
6187 if (alpha_expand_block_move (operands))
6193 (define_expand "clrstrqi"
6194 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6196 (use (match_operand:DI 1 "immediate_operand" ""))
6197 (use (match_operand:DI 2 "immediate_operand" ""))])]
6200 if (alpha_expand_block_clear (operands))
6206 ;; Subroutine of stack space allocation. Perform a stack probe.
6207 (define_expand "probe_stack"
6208 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6211 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6212 INTVAL (operands[0])));
6213 MEM_VOLATILE_P (operands[1]) = 1;
6215 operands[0] = const0_rtx;
6218 ;; This is how we allocate stack space. If we are allocating a
6219 ;; constant amount of space and we know it is less than 4096
6220 ;; bytes, we need do nothing.
6222 ;; If it is more than 4096 bytes, we need to probe the stack
6224 (define_expand "allocate_stack"
6226 (plus:DI (reg:DI 30)
6227 (match_operand:DI 1 "reg_or_cint_operand" "")))
6228 (set (match_operand:DI 0 "register_operand" "=r")
6232 if (GET_CODE (operands[1]) == CONST_INT
6233 && INTVAL (operands[1]) < 32768)
6235 if (INTVAL (operands[1]) >= 4096)
6237 /* We do this the same way as in the prologue and generate explicit
6238 probes. Then we update the stack by the constant. */
6242 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6243 while (probed + 8192 < INTVAL (operands[1]))
6244 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6246 if (probed + 4096 < INTVAL (operands[1]))
6247 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6250 operands[1] = GEN_INT (- INTVAL (operands[1]));
6251 operands[2] = virtual_stack_dynamic_rtx;
6256 rtx loop_label = gen_label_rtx ();
6257 rtx want = gen_reg_rtx (Pmode);
6258 rtx tmp = gen_reg_rtx (Pmode);
6261 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6262 force_reg (Pmode, operands[1])));
6263 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6265 if (GET_CODE (operands[1]) != CONST_INT)
6267 out_label = gen_label_rtx ();
6268 emit_insn (gen_cmpdi (want, tmp));
6269 emit_jump_insn (gen_bgeu (out_label));
6272 emit_label (loop_label);
6273 memref = gen_rtx_MEM (DImode, tmp);
6274 MEM_VOLATILE_P (memref) = 1;
6275 emit_move_insn (memref, const0_rtx);
6276 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6277 emit_insn (gen_cmpdi (tmp, want));
6278 emit_jump_insn (gen_bgtu (loop_label));
6280 memref = gen_rtx_MEM (DImode, want);
6281 MEM_VOLATILE_P (memref) = 1;
6282 emit_move_insn (memref, const0_rtx);
6285 emit_label (out_label);
6287 emit_move_insn (stack_pointer_rtx, want);
6288 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6293 ;; This is used by alpha_expand_prolog to do the same thing as above,
6294 ;; except we cannot at that time generate new basic blocks, so we hide
6295 ;; the loop in this one insn.
6297 (define_insn "prologue_stack_probe_loop"
6298 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6299 (match_operand:DI 1 "register_operand" "r")]
6303 operands[2] = gen_label_rtx ();
6304 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6305 CODE_LABEL_NUMBER (operands[2]));
6307 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6309 [(set_attr "length" "16")
6310 (set_attr "type" "multi")])
6312 (define_expand "prologue"
6313 [(clobber (const_int 0))]
6316 alpha_expand_prologue ();
6320 ;; These take care of emitting the ldgp insn in the prologue. This will be
6321 ;; an lda/ldah pair and we want to align them properly. So we have two
6322 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6323 ;; and the second of which emits nothing. However, both are marked as type
6324 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6327 (define_expand "prologue_ldgp"
6329 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6331 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6334 operands[0] = pic_offset_table_rtx;
6335 operands[1] = gen_rtx_REG (Pmode, 27);
6336 operands[2] = (TARGET_EXPLICIT_RELOCS
6337 ? GEN_INT (alpha_next_sequence_number++)
6341 (define_insn "*ldgp_er_1"
6342 [(set (match_operand:DI 0 "register_operand" "=r")
6343 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6344 (match_operand 2 "const_int_operand" "")]
6346 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6347 "ldah %0,0(%1)\t\t!gpdisp!%2")
6349 (define_insn "*ldgp_er_2"
6350 [(set (match_operand:DI 0 "register_operand" "=r")
6351 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6352 (match_operand 2 "const_int_operand" "")]
6354 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6355 "lda %0,0(%1)\t\t!gpdisp!%2")
6357 (define_insn "*prologue_ldgp_er_2"
6358 [(set (match_operand:DI 0 "register_operand" "=r")
6359 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6360 (match_operand 2 "const_int_operand" "")]
6362 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6363 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6365 (define_insn "*prologue_ldgp_1"
6366 [(set (match_operand:DI 0 "register_operand" "=r")
6367 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6368 (match_operand 2 "const_int_operand" "")]
6371 "ldgp %0,0(%1)\n$%~..ng:")
6373 (define_insn "*prologue_ldgp_2"
6374 [(set (match_operand:DI 0 "register_operand" "=r")
6375 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6376 (match_operand 2 "const_int_operand" "")]
6381 ;; The _mcount profiling hook has special calling conventions, and
6382 ;; does not clobber all the registers that a normal call would. So
6383 ;; hide the fact this is a call at all.
6385 (define_insn "prologue_mcount"
6386 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6388 "lda $28,_mcount\;jsr $28,($28),_mcount"
6389 [(set_attr "type" "multi")
6390 (set_attr "length" "8")])
6392 (define_insn "init_fp"
6393 [(set (match_operand:DI 0 "register_operand" "=r")
6394 (match_operand:DI 1 "register_operand" "r"))
6395 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6399 (define_expand "epilogue"
6403 alpha_expand_epilogue ();
6406 (define_expand "sibcall_epilogue"
6410 alpha_expand_epilogue ();
6414 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6415 ;; the frame size into a register. We use this pattern to ensure
6416 ;; we get lda instead of addq.
6417 (define_insn "nt_lda"
6418 [(set (match_operand:DI 0 "register_operand" "=r")
6419 (unspec:DI [(match_dup 0)
6420 (match_operand:DI 1 "const_int_operand" "n")]
6425 (define_expand "builtin_longjmp"
6426 [(use (match_operand:DI 0 "register_operand" "r"))]
6429 /* The elements of the buffer are, in order: */
6430 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6431 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6432 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6433 rtx pv = gen_rtx_REG (Pmode, 27);
6435 /* This bit is the same as expand_builtin_longjmp. */
6436 emit_move_insn (hard_frame_pointer_rtx, fp);
6437 emit_move_insn (pv, lab);
6438 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6439 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6440 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6442 /* Load the label we are jumping through into $27 so that we know
6443 where to look for it when we get back to setjmp's function for
6444 restoring the gp. */
6445 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6450 ;; This is effectively a copy of indirect_jump, but constrained such
6451 ;; that register renaming cannot foil our cunning plan with $27.
6452 (define_insn "builtin_longjmp_internal"
6454 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6458 [(set_attr "type" "ibr")])
6460 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6461 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6462 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6463 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6465 (define_insn "*builtin_setjmp_receiver_er_1"
6466 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6467 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6468 "br $27,$LSJ%=\n$LSJ%=:"
6469 [(set_attr "type" "ibr")])
6472 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6473 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6474 && prev_nonnote_insn (insn) == operands[0]"
6478 (define_insn "*builtin_setjmp_receiver_1"
6479 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6481 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6482 [(set_attr "length" "12")
6483 (set_attr "type" "multi")])
6485 (define_expand "builtin_setjmp_receiver_er"
6486 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6488 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6490 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6493 operands[1] = pic_offset_table_rtx;
6494 operands[2] = gen_rtx_REG (Pmode, 27);
6495 operands[3] = GEN_INT (alpha_next_sequence_number++);
6498 (define_expand "builtin_setjmp_receiver"
6499 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6502 if (TARGET_EXPLICIT_RELOCS)
6504 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6509 (define_expand "exception_receiver_er"
6511 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6513 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6516 operands[0] = pic_offset_table_rtx;
6517 operands[1] = gen_rtx_REG (Pmode, 26);
6518 operands[2] = GEN_INT (alpha_next_sequence_number++);
6521 (define_expand "exception_receiver"
6522 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6525 if (TARGET_LD_BUGGY_LDGP)
6526 operands[0] = alpha_gp_save_rtx ();
6527 else if (TARGET_EXPLICIT_RELOCS)
6529 emit_insn (gen_exception_receiver_er ());
6533 operands[0] = const0_rtx;
6536 (define_insn "*exception_receiver_1"
6537 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6538 "! TARGET_LD_BUGGY_LDGP"
6540 [(set_attr "length" "8")
6541 (set_attr "type" "multi")])
6543 (define_insn "*exception_receiver_2"
6544 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
6546 "TARGET_LD_BUGGY_LDGP"
6550 [(set_attr "type" "ilog,ild")])
6552 (define_expand "nonlocal_goto_receiver"
6553 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6554 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6555 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6557 "TARGET_ABI_OPEN_VMS"
6560 (define_insn "arg_home"
6561 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6576 (clobber (mem:BLK (const_int 0)))
6577 (clobber (reg:DI 24))
6578 (clobber (reg:DI 25))
6579 (clobber (reg:DI 0))]
6580 "TARGET_ABI_OPEN_VMS"
6581 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6582 [(set_attr "length" "16")
6583 (set_attr "type" "multi")])
6585 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6587 (define_expand "umk_mismatch_args"
6588 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6589 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6590 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6591 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6594 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6595 "TARGET_ABI_UNICOSMK"
6597 operands[1] = gen_reg_rtx (DImode);
6598 operands[2] = gen_reg_rtx (DImode);
6599 operands[3] = gen_reg_rtx (DImode);
6602 (define_insn "arg_home_umk"
6603 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6618 (clobber (mem:BLK (const_int 0)))
6620 (clobber (reg:DI 22))
6621 (clobber (reg:DI 23))
6622 (clobber (reg:DI 24))
6623 (clobber (reg:DI 0))
6624 (clobber (reg:DI 1))
6625 (clobber (reg:DI 2))
6626 (clobber (reg:DI 3))
6627 (clobber (reg:DI 4))
6628 (clobber (reg:DI 5))
6629 (clobber (reg:DI 6))
6630 (clobber (reg:DI 7))
6631 (clobber (reg:DI 8))])]
6632 "TARGET_ABI_UNICOSMK"
6633 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6634 [(set_attr "length" "16")
6635 (set_attr "type" "multi")])
6637 ;; Close the trap shadow of preceeding instructions. This is generated
6640 (define_insn "trapb"
6641 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6644 [(set_attr "type" "misc")])
6646 ;; No-op instructions used by machine-dependant reorg to preserve
6647 ;; alignment for instruction issue.
6648 ;; The Unicos/Mk assembler does not support these opcodes.
6654 [(set_attr "type" "ilog")])
6659 "cpys $f31,$f31,$f31"
6660 [(set_attr "type" "fcpys")])
6667 ;; On Unicos/Mk we use a macro for aligning code.
6669 (define_insn "realign"
6670 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6674 if (TARGET_ABI_UNICOSMK)
6675 return "gcc@code@align %0";
6677 return ".align %0 #realign";
6680 ;; The call patterns are at the end of the file because their
6681 ;; wildcard operand0 interferes with nice recognition.
6683 (define_insn "*call_value_osf_1_er"
6684 [(set (match_operand 0 "" "")
6685 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6686 (match_operand 2 "" "")))
6688 (clobber (reg:DI 26))]
6689 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6691 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6693 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6694 [(set_attr "type" "jsr")
6695 (set_attr "length" "12,*,16")])
6697 ;; We must use peep2 instead of a split because we need accurate life
6698 ;; information for $gp. Consider the case of { bar(); while (1); }.
6700 [(parallel [(set (match_operand 0 "" "")
6701 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6702 (match_operand 2 "" "")))
6704 (clobber (reg:DI 26))])]
6705 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6706 && ! current_file_function_operand (operands[0], Pmode)
6707 && peep2_regno_dead_p (1, 29)"
6708 [(parallel [(set (match_dup 0)
6709 (call (mem:DI (match_dup 3))
6711 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6712 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6713 (use (match_dup 1))])]
6715 if (CONSTANT_P (operands[1]))
6717 operands[3] = gen_rtx_REG (Pmode, 27);
6718 emit_move_insn (operands[3], operands[1]);
6722 operands[3] = operands[1];
6723 operands[1] = const0_rtx;
6728 [(parallel [(set (match_operand 0 "" "")
6729 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6730 (match_operand 2 "" "")))
6732 (clobber (reg:DI 26))])]
6733 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6734 && ! current_file_function_operand (operands[0], Pmode)
6735 && ! peep2_regno_dead_p (1, 29)"
6736 [(parallel [(set (match_dup 0)
6737 (call (mem:DI (match_dup 3))
6739 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6740 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6741 (use (match_dup 1))])
6743 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6745 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6747 if (CONSTANT_P (operands[1]))
6749 operands[3] = gen_rtx_REG (Pmode, 27);
6750 emit_move_insn (operands[3], operands[1]);
6754 operands[3] = operands[1];
6755 operands[1] = const0_rtx;
6757 operands[4] = GEN_INT (alpha_next_sequence_number++);
6760 ;; We add a blockage unspec_volatile to prevent insns from moving down
6761 ;; from above the call to in between the call and the ldah gpdisp.
6762 (define_insn "*call_value_osf_2_er"
6763 [(set (match_operand 0 "" "")
6764 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6765 (match_operand 2 "" "")))
6767 (plus:DI (pc) (const_int 4)))
6768 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6769 (use (match_operand 3 "" ""))]
6770 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6772 [(set_attr "type" "jsr")])
6774 (define_insn "*call_value_osf_1_noreturn"
6775 [(set (match_operand 0 "" "")
6776 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6777 (match_operand 2 "" "")))
6779 (clobber (reg:DI 26))]
6780 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6781 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6786 [(set_attr "type" "jsr")
6787 (set_attr "length" "*,*,8")])
6789 (define_insn "*call_value_osf_1"
6790 [(set (match_operand 0 "" "")
6791 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6792 (match_operand 2 "" "")))
6794 (clobber (reg:DI 26))]
6795 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6797 jsr $26,($27),0\;ldgp $29,0($26)
6799 jsr $26,%1\;ldgp $29,0($26)"
6800 [(set_attr "type" "jsr")
6801 (set_attr "length" "12,*,16")])
6803 ;; Need 's' alternative for OSF/1, which implements profiling
6804 ;; via linker tricks.
6805 (define_insn "*sibcall_value_osf_1"
6806 [(set (match_operand 0 "" "")
6807 (call (mem:DI (match_operand:DI 1 "current_file_function_operand" "R,s"))
6808 (match_operand 2 "" "")))
6813 lda $27,%1\;jmp $31,($27),%1"
6814 [(set_attr "type" "jsr")
6815 (set_attr "length" "*,8")])
6817 (define_insn "*call_value_nt_1"
6818 [(set (match_operand 0 "" "")
6819 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
6820 (match_operand 2 "" "")))
6821 (clobber (reg:DI 26))]
6822 "TARGET_ABI_WINDOWS_NT"
6827 [(set_attr "type" "jsr")
6828 (set_attr "length" "*,*,12")])
6830 (define_insn "*call_value_vms_1"
6831 [(set (match_operand 0 "" "")
6832 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
6833 (match_operand 2 "" "")))
6834 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6837 (clobber (reg:DI 27))]
6838 "TARGET_ABI_OPEN_VMS"
6840 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6841 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6842 [(set_attr "type" "jsr")
6843 (set_attr "length" "12,16")])
6845 (define_insn "*call_value_umk"
6846 [(set (match_operand 0 "" "")
6847 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
6848 (match_operand 2 "" "")))
6850 (clobber (reg:DI 26))]
6851 "TARGET_ABI_UNICOSMK"
6853 [(set_attr "type" "jsr")])