1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
49 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
50 (UNSPECV_LONGJMP 3) ; builtin_longjmp
52 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
54 (UNSPECV_EHR 7) ; exception_receiver
58 (UNSPECV_PLDGP2 11) ; prologue ldgp
61 ;; Where necessary, the suffixes _le and _be are used to distinguish between
62 ;; little-endian and big-endian patterns.
64 ;; Note that the Unicos/Mk assembler does not support the following
65 ;; opcodes: mov, fmov, nop, fnop, unop.
67 ;; Processor type -- this attribute must exactly match the processor_type
68 ;; enumeration in alpha.h.
70 (define_attr "cpu" "ev4,ev5,ev6"
71 (const (symbol_ref "alpha_cpu")))
73 ;; Define an insn type attribute. This is used in function unit delay
74 ;; computations, among other purposes. For the most part, we use the names
75 ;; defined in the EV4 documentation, but add a few that we have to know about
79 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
80 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
81 (const_string "iadd"))
83 ;; Describe a user's asm statement.
84 (define_asm_attributes
85 [(set_attr "type" "multi")])
87 ;; Define the operand size an insn operates on. Used primarily by mul
88 ;; and div operations that have size dependent timings.
90 (define_attr "opsize" "si,di,udi"
93 ;; The TRAP attribute marks instructions that may generate traps
94 ;; (which are imprecise and may need a trapb if software completion
97 (define_attr "trap" "no,yes"
100 ;; The ROUND_SUFFIX attribute marks which instructions require a
101 ;; rounding-mode suffix. The value NONE indicates no suffix,
102 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
104 (define_attr "round_suffix" "none,normal,c"
105 (const_string "none"))
107 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
109 ;; SU accepts only /su (cmpt et al)
110 ;; SUI accepts only /sui (cvtqt and cvtqs)
111 ;; V_SV accepts /v and /sv (cvtql only)
112 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
113 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
115 ;; The actual suffix emitted is controled by alpha_fptm.
117 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
118 (const_string "none"))
120 ;; The length of an instruction sequence in bytes.
122 (define_attr "length" ""
125 ;; On EV4 there are two classes of resources to consider: resources needed
126 ;; to issue, and resources needed to execute. IBUS[01] are in the first
127 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
128 ;; (There are a few other register-like resources, but ...)
130 ; First, describe all of the issue constraints with single cycle delays.
131 ; All insns need a bus, but all except loads require one or the other.
132 (define_function_unit "ev4_ibus0" 1 0
133 (and (eq_attr "cpu" "ev4")
134 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
137 (define_function_unit "ev4_ibus1" 1 0
138 (and (eq_attr "cpu" "ev4")
139 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
142 ; Memory delivers its result in three cycles. Actually return one and
143 ; take care of this in adjust_cost, since we want to handle user-defined
145 (define_function_unit "ev4_abox" 1 0
146 (and (eq_attr "cpu" "ev4")
147 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
150 ; Branches have no delay cost, but do tie up the unit for two cycles.
151 (define_function_unit "ev4_bbox" 1 1
152 (and (eq_attr "cpu" "ev4")
153 (eq_attr "type" "ibr,fbr,jsr"))
156 ; Arithmetic insns are normally have their results available after
157 ; two cycles. There are a number of exceptions. They are encoded in
158 ; ADJUST_COST. Some of the other insns have similar exceptions.
159 (define_function_unit "ev4_ebox" 1 0
160 (and (eq_attr "cpu" "ev4")
161 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
164 (define_function_unit "imul" 1 0
165 (and (eq_attr "cpu" "ev4")
166 (and (eq_attr "type" "imul")
167 (eq_attr "opsize" "si")))
170 (define_function_unit "imul" 1 0
171 (and (eq_attr "cpu" "ev4")
172 (and (eq_attr "type" "imul")
173 (eq_attr "opsize" "!si")))
176 (define_function_unit "ev4_fbox" 1 0
177 (and (eq_attr "cpu" "ev4")
178 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
181 (define_function_unit "fdiv" 1 0
182 (and (eq_attr "cpu" "ev4")
183 (and (eq_attr "type" "fdiv")
184 (eq_attr "opsize" "si")))
187 (define_function_unit "fdiv" 1 0
188 (and (eq_attr "cpu" "ev4")
189 (and (eq_attr "type" "fdiv")
190 (eq_attr "opsize" "di")))
193 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
195 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
196 ;; with the combined resource EBOX.
198 (define_function_unit "ev5_ebox" 2 0
199 (and (eq_attr "cpu" "ev5")
200 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
203 ; Memory takes at least 2 clocks. Return one from here and fix up with
204 ; user-defined latencies in adjust_cost.
205 (define_function_unit "ev5_ebox" 2 0
206 (and (eq_attr "cpu" "ev5")
207 (eq_attr "type" "ild,fld,ldsym"))
210 ; Loads can dual issue with one another, but loads and stores do not mix.
211 (define_function_unit "ev5_e0" 1 0
212 (and (eq_attr "cpu" "ev5")
213 (eq_attr "type" "ild,fld,ldsym"))
215 [(eq_attr "type" "ist,fst")])
217 ; Stores, shifts, multiplies can only issue to E0
218 (define_function_unit "ev5_e0" 1 0
219 (and (eq_attr "cpu" "ev5")
220 (eq_attr "type" "ist,fst,shift,imul"))
223 ; Motion video insns also issue only to E0, and take two ticks.
224 (define_function_unit "ev5_e0" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "mvi"))
229 ; Conditional moves always take 2 ticks.
230 (define_function_unit "ev5_ebox" 2 0
231 (and (eq_attr "cpu" "ev5")
232 (eq_attr "type" "icmov"))
235 ; Branches can only issue to E1
236 (define_function_unit "ev5_e1" 1 0
237 (and (eq_attr "cpu" "ev5")
238 (eq_attr "type" "ibr,jsr"))
241 ; Multiplies also use the integer multiplier.
242 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
243 ; cycles before an integer multiplication completes."
244 (define_function_unit "imul" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "imul")
247 (eq_attr "opsize" "si")))
250 (define_function_unit "imul" 1 0
251 (and (eq_attr "cpu" "ev5")
252 (and (eq_attr "type" "imul")
253 (eq_attr "opsize" "di")))
256 (define_function_unit "imul" 1 0
257 (and (eq_attr "cpu" "ev5")
258 (and (eq_attr "type" "imul")
259 (eq_attr "opsize" "udi")))
262 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
263 ;; on either so we have to play the game again.
265 (define_function_unit "ev5_fbox" 2 0
266 (and (eq_attr "cpu" "ev5")
267 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
270 (define_function_unit "ev5_fm" 1 0
271 (and (eq_attr "cpu" "ev5")
272 (eq_attr "type" "fmul"))
275 ; Add and cmov as you would expect; fbr never produces a result;
276 ; fdiv issues through fa to the divider,
277 (define_function_unit "ev5_fa" 1 0
278 (and (eq_attr "cpu" "ev5")
279 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
282 ; ??? How to: "No instruction can be issued to pipe FA exactly five
283 ; cycles before a floating point divide completes."
284 (define_function_unit "fdiv" 1 0
285 (and (eq_attr "cpu" "ev5")
286 (and (eq_attr "type" "fdiv")
287 (eq_attr "opsize" "si")))
288 15 15) ; 15 to 31 data dependent
290 (define_function_unit "fdiv" 1 0
291 (and (eq_attr "cpu" "ev5")
292 (and (eq_attr "type" "fdiv")
293 (eq_attr "opsize" "di")))
294 22 22) ; 22 to 60 data dependent
296 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
298 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
299 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
301 ;; Conditional moves decompose into two independent primitives, each
302 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
304 (define_function_unit "ev6_ebox" 4 0
305 (and (eq_attr "cpu" "ev6")
306 (eq_attr "type" "icmov"))
309 (define_function_unit "ev6_ebox" 4 0
310 (and (eq_attr "cpu" "ev6")
311 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
314 ;; Integer loads take at least 3 clocks, and only issue to lower units.
315 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
316 (define_function_unit "ev6_l" 2 0
317 (and (eq_attr "cpu" "ev6")
318 (eq_attr "type" "ild,ldsym,ist,fst"))
321 ;; FP loads take at least 4 clocks. Return two from here...
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "fld"))
327 ;; Motion video insns also issue only to U0, and take three ticks.
328 (define_function_unit "ev6_u0" 1 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "mvi"))
333 (define_function_unit "ev6_u" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "mvi"))
338 ;; Shifts issue to either upper pipe.
339 (define_function_unit "ev6_u" 2 0
340 (and (eq_attr "cpu" "ev6")
341 (eq_attr "type" "shift"))
344 ;; Multiplies issue only to U1, and all take 7 ticks.
345 ;; Rather than create a new function unit just for U1, reuse IMUL
346 (define_function_unit "imul" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "imul"))
351 (define_function_unit "ev6_u" 2 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "imul"))
356 ;; Branches issue to either upper pipe
357 (define_function_unit "ev6_u" 2 0
358 (and (eq_attr "cpu" "ev6")
359 (eq_attr "type" "ibr"))
362 ;; Calls only issue to L0.
363 (define_function_unit "ev6_l0" 1 0
364 (and (eq_attr "cpu" "ev6")
365 (eq_attr "type" "jsr"))
368 (define_function_unit "ev6_l" 2 0
369 (and (eq_attr "cpu" "ev6")
370 (eq_attr "type" "jsr"))
373 ;; Ftoi/itof only issue to lower pipes
374 (define_function_unit "ev6_l" 2 0
375 (and (eq_attr "cpu" "ev6")
376 (eq_attr "type" "ftoi"))
379 (define_function_unit "ev6_l" 2 0
380 (and (eq_attr "cpu" "ev6")
381 (eq_attr "type" "itof"))
384 ;; For the FPU we are very similar to EV5, except there's no insn that
385 ;; can issue to fm & fa, so we get to leave that out.
387 (define_function_unit "ev6_fm" 1 0
388 (and (eq_attr "cpu" "ev6")
389 (eq_attr "type" "fmul"))
392 (define_function_unit "ev6_fa" 1 0
393 (and (eq_attr "cpu" "ev6")
394 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
397 (define_function_unit "ev6_fa" 1 0
398 (and (eq_attr "cpu" "ev6")
399 (eq_attr "type" "fcmov"))
402 (define_function_unit "fdiv" 1 0
403 (and (eq_attr "cpu" "ev6")
404 (and (eq_attr "type" "fdiv")
405 (eq_attr "opsize" "si")))
408 (define_function_unit "fdiv" 1 0
409 (and (eq_attr "cpu" "ev6")
410 (and (eq_attr "type" "fdiv")
411 (eq_attr "opsize" "di")))
414 (define_function_unit "fsqrt" 1 0
415 (and (eq_attr "cpu" "ev6")
416 (and (eq_attr "type" "fsqrt")
417 (eq_attr "opsize" "si")))
420 (define_function_unit "fsqrt" 1 0
421 (and (eq_attr "cpu" "ev6")
422 (and (eq_attr "type" "fsqrt")
423 (eq_attr "opsize" "di")))
426 ; ??? The FPU communicates with memory and the integer register file
427 ; via two fp store units. We need a slot in the fst immediately, and
428 ; a slot in LOW after the operand data is ready. At which point the
429 ; data may be moved either to the store queue or the integer register
430 ; file and the insn retired.
433 ;; First define the arithmetic insns. Note that the 32-bit forms also
436 ;; Handle 32-64 bit extension from memory to a floating point register
437 ;; specially, since this occurs frequently in int->double conversions.
439 ;; Note that while we must retain the =f case in the insn for reload's
440 ;; benefit, it should be eliminated after reload, so we should never emit
441 ;; code for that case. But we don't reject the possibility.
443 (define_expand "extendsidi2"
444 [(set (match_operand:DI 0 "register_operand" "")
445 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
449 (define_insn "*extendsidi2_nofix"
450 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
452 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
458 lds %0,%1\;cvtlq %0,%0"
459 [(set_attr "type" "iadd,ild,fadd,fld")
460 (set_attr "length" "*,*,*,8")])
462 (define_insn "*extendsidi2_fix"
463 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
465 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
472 lds %0,%1\;cvtlq %0,%0"
473 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
474 (set_attr "length" "*,*,*,*,8")])
476 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
478 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
479 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
481 [(set (match_dup 2) (match_dup 1))
482 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
483 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
485 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
486 ;; reload when converting fp->int.
489 [(set (match_operand:SI 0 "hard_int_register_operand" "")
490 (match_operand:SI 1 "memory_operand" ""))
491 (set (match_operand:DI 2 "hard_int_register_operand" "")
492 (sign_extend:DI (match_dup 0)))]
493 "true_regnum (operands[0]) == true_regnum (operands[2])
494 || peep2_reg_dead_p (2, operands[0])"
496 (sign_extend:DI (match_dup 1)))]
500 [(set (match_operand:SI 0 "hard_int_register_operand" "")
501 (match_operand:SI 1 "hard_fp_register_operand" ""))
502 (set (match_operand:DI 2 "hard_int_register_operand" "")
503 (sign_extend:DI (match_dup 0)))]
505 && (true_regnum (operands[0]) == true_regnum (operands[2])
506 || peep2_reg_dead_p (2, operands[0]))"
508 (sign_extend:DI (match_dup 1)))]
512 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
513 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
514 (set (match_operand:DI 2 "hard_int_register_operand" "")
516 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
518 (sign_extend:DI (match_dup 1)))]
521 ;; Don't say we have addsi3 if optimizing. This generates better code. We
522 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
523 (define_expand "addsi3"
524 [(set (match_operand:SI 0 "register_operand" "")
525 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
526 (match_operand:SI 2 "add_operand" "")))]
530 (define_insn "*addsi_internal"
531 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
532 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
533 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
542 [(set (match_operand:SI 0 "register_operand" "")
543 (plus:SI (match_operand:SI 1 "register_operand" "")
544 (match_operand:SI 2 "const_int_operand" "")))]
545 "! add_operand (operands[2], SImode)"
546 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
547 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
549 HOST_WIDE_INT val = INTVAL (operands[2]);
550 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
551 HOST_WIDE_INT rest = val - low;
553 operands[3] = GEN_INT (rest);
554 operands[4] = GEN_INT (low);
557 (define_insn "*addsi_se"
558 [(set (match_operand:DI 0 "register_operand" "=r,r")
560 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
561 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
568 [(set (match_operand:DI 0 "register_operand" "")
570 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
571 (match_operand:SI 2 "const_int_operand" ""))))
572 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
573 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
574 && INTVAL (operands[2]) % 4 == 0"
575 [(set (match_dup 3) (match_dup 4))
576 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
580 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
586 operands[4] = GEN_INT (val);
587 operands[5] = GEN_INT (mult);
591 [(set (match_operand:DI 0 "register_operand" "")
593 (plus:SI (match_operator:SI 1 "comparison_operator"
594 [(match_operand 2 "" "")
595 (match_operand 3 "" "")])
596 (match_operand:SI 4 "add_operand" ""))))
597 (clobber (match_operand:DI 5 "register_operand" ""))]
599 [(set (match_dup 5) (match_dup 6))
600 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
602 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
603 operands[2], operands[3]);
604 operands[7] = gen_lowpart (SImode, operands[5]);
607 (define_insn "addvsi3"
608 [(set (match_operand:SI 0 "register_operand" "=r,r")
609 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
610 (match_operand:SI 2 "sext_add_operand" "rI,O")))
611 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
612 (sign_extend:DI (match_dup 2)))
613 (sign_extend:DI (plus:SI (match_dup 1)
621 (define_expand "adddi3"
622 [(set (match_operand:DI 0 "register_operand" "")
623 (plus:DI (match_operand:DI 1 "register_operand" "")
624 (match_operand:DI 2 "add_operand" "")))]
628 (define_insn "*adddi_er_high_l"
629 [(set (match_operand:DI 0 "register_operand" "=r")
630 (plus:DI (match_operand:DI 1 "register_operand" "r")
631 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
632 "TARGET_EXPLICIT_RELOCS"
633 "ldah %0,%2(%1)\t\t!gprelhigh")
636 [(set (match_operand:DI 0 "register_operand" "")
637 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
638 "TARGET_EXPLICIT_RELOCS && reload_completed"
640 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
641 "operands[2] = pic_offset_table_rtx;")
643 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
644 ;; With complications like
646 ;; The NT stack unwind code can't handle a subq to adjust the stack
647 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
648 ;; the exception handling code will loop if a subq is used and an
651 ;; The 19980616 change to emit prologues as RTL also confused some
652 ;; versions of GDB, which also interprets prologues. This has been
653 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
656 ;; and the fact that the three insns schedule exactly the same, it's
657 ;; just not worth the effort.
659 (define_insn "*adddi_internal"
660 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
661 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
662 (match_operand:DI 2 "add_operand" "r,K,L")))]
669 ;; ??? Allow large constants when basing off the frame pointer or some
670 ;; virtual register that may eliminate to the frame pointer. This is
671 ;; done because register elimination offsets will change the hi/lo split,
672 ;; and if we split before reload, we will require additional instructions.
674 (define_insn "*adddi_fp_hack"
675 [(set (match_operand:DI 0 "register_operand" "=r")
676 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
677 (match_operand:DI 2 "const_int_operand" "n")))]
678 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
679 && INTVAL (operands[2]) >= 0
680 /* This is the largest constant an lda+ldah pair can add, minus
681 an upper bound on the displacement between SP and AP during
682 register elimination. See INITIAL_ELIMINATION_OFFSET. */
683 && INTVAL (operands[2])
685 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
686 - ALPHA_ROUND(current_function_outgoing_args_size)
687 - (ALPHA_ROUND (get_frame_size ()
688 + max_reg_num () * UNITS_PER_WORD
689 + current_function_pretend_args_size)
690 - current_function_pretend_args_size))"
693 ;; Don't do this if we are adjusting SP since we don't want to do it
694 ;; in two steps. Don't split FP sources for the reason listed above.
696 [(set (match_operand:DI 0 "register_operand" "")
697 (plus:DI (match_operand:DI 1 "register_operand" "")
698 (match_operand:DI 2 "const_int_operand" "")))]
699 "! add_operand (operands[2], DImode)
700 && operands[0] != stack_pointer_rtx
701 && operands[1] != frame_pointer_rtx
702 && operands[1] != arg_pointer_rtx"
703 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
704 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
706 HOST_WIDE_INT val = INTVAL (operands[2]);
707 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
708 HOST_WIDE_INT rest = val - low;
710 operands[4] = GEN_INT (low);
711 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
712 operands[3] = GEN_INT (rest);
713 else if (! no_new_pseudos)
715 operands[3] = gen_reg_rtx (DImode);
716 emit_move_insn (operands[3], operands[2]);
717 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
724 (define_insn "*saddl"
725 [(set (match_operand:SI 0 "register_operand" "=r,r")
726 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
727 (match_operand:SI 2 "const48_operand" "I,I"))
728 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
734 (define_insn "*saddl_se"
735 [(set (match_operand:DI 0 "register_operand" "=r,r")
737 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
738 (match_operand:SI 2 "const48_operand" "I,I"))
739 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
746 [(set (match_operand:DI 0 "register_operand" "")
748 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
749 [(match_operand 2 "" "")
750 (match_operand 3 "" "")])
751 (match_operand:SI 4 "const48_operand" ""))
752 (match_operand:SI 5 "sext_add_operand" ""))))
753 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
755 [(set (match_dup 6) (match_dup 7))
757 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
760 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
761 operands[2], operands[3]);
762 operands[8] = gen_lowpart (SImode, operands[6]);
765 (define_insn "*saddq"
766 [(set (match_operand:DI 0 "register_operand" "=r,r")
767 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
768 (match_operand:DI 2 "const48_operand" "I,I"))
769 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
775 (define_insn "addvdi3"
776 [(set (match_operand:DI 0 "register_operand" "=r,r")
777 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
778 (match_operand:DI 2 "sext_add_operand" "rI,O")))
779 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
780 (sign_extend:TI (match_dup 2)))
781 (sign_extend:TI (plus:DI (match_dup 1)
789 (define_insn "negsi2"
790 [(set (match_operand:SI 0 "register_operand" "=r")
791 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
795 (define_insn "*negsi_se"
796 [(set (match_operand:DI 0 "register_operand" "=r")
797 (sign_extend:DI (neg:SI
798 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
802 (define_insn "negvsi2"
803 [(set (match_operand:SI 0 "register_operand" "=r")
804 (neg:SI (match_operand:SI 1 "register_operand" "r")))
805 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
806 (sign_extend:DI (neg:SI (match_dup 1))))
811 (define_insn "negdi2"
812 [(set (match_operand:DI 0 "register_operand" "=r")
813 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
817 (define_insn "negvdi2"
818 [(set (match_operand:DI 0 "register_operand" "=r")
819 (neg:DI (match_operand:DI 1 "register_operand" "r")))
820 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
821 (sign_extend:TI (neg:DI (match_dup 1))))
826 (define_expand "subsi3"
827 [(set (match_operand:SI 0 "register_operand" "")
828 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
829 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
833 (define_insn "*subsi_internal"
834 [(set (match_operand:SI 0 "register_operand" "=r")
835 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
836 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
840 (define_insn "*subsi_se"
841 [(set (match_operand:DI 0 "register_operand" "=r")
842 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
843 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
847 (define_insn "subvsi3"
848 [(set (match_operand:SI 0 "register_operand" "=r")
849 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
850 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
851 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
852 (sign_extend:DI (match_dup 2)))
853 (sign_extend:DI (minus:SI (match_dup 1)
859 (define_insn "subdi3"
860 [(set (match_operand:DI 0 "register_operand" "=r")
861 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
862 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
866 (define_insn "*ssubl"
867 [(set (match_operand:SI 0 "register_operand" "=r")
868 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
869 (match_operand:SI 2 "const48_operand" "I"))
870 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
874 (define_insn "*ssubl_se"
875 [(set (match_operand:DI 0 "register_operand" "=r")
877 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
878 (match_operand:SI 2 "const48_operand" "I"))
879 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
883 (define_insn "*ssubq"
884 [(set (match_operand:DI 0 "register_operand" "=r")
885 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
886 (match_operand:DI 2 "const48_operand" "I"))
887 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
891 (define_insn "subvdi3"
892 [(set (match_operand:DI 0 "register_operand" "=r")
893 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
894 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
895 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
896 (sign_extend:TI (match_dup 2)))
897 (sign_extend:TI (minus:DI (match_dup 1)
903 ;; The Unicos/Mk assembler doesn't support mull.
905 (define_insn "mulsi3"
906 [(set (match_operand:SI 0 "register_operand" "=r")
907 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
908 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
909 "!TARGET_ABI_UNICOSMK"
911 [(set_attr "type" "imul")
912 (set_attr "opsize" "si")])
914 (define_insn "*mulsi_se"
915 [(set (match_operand:DI 0 "register_operand" "=r")
917 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
918 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
919 "!TARGET_ABI_UNICOSMK"
921 [(set_attr "type" "imul")
922 (set_attr "opsize" "si")])
924 (define_insn "mulvsi3"
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
927 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
928 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
929 (sign_extend:DI (match_dup 2)))
930 (sign_extend:DI (mult:SI (match_dup 1)
933 "!TARGET_ABI_UNICOSMK"
935 [(set_attr "type" "imul")
936 (set_attr "opsize" "si")])
938 (define_insn "muldi3"
939 [(set (match_operand:DI 0 "register_operand" "=r")
940 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
941 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
944 [(set_attr "type" "imul")])
946 (define_insn "mulvdi3"
947 [(set (match_operand:DI 0 "register_operand" "=r")
948 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
949 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
950 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
951 (sign_extend:TI (match_dup 2)))
952 (sign_extend:TI (mult:DI (match_dup 1)
957 [(set_attr "type" "imul")])
959 (define_insn "umuldi3_highpart"
960 [(set (match_operand:DI 0 "register_operand" "=r")
963 (mult:TI (zero_extend:TI
964 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
966 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
970 [(set_attr "type" "imul")
971 (set_attr "opsize" "udi")])
973 (define_insn "*umuldi3_highpart_const"
974 [(set (match_operand:DI 0 "register_operand" "=r")
977 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
978 (match_operand:TI 2 "cint8_operand" "I"))
982 [(set_attr "type" "imul")
983 (set_attr "opsize" "udi")])
985 ;; The divide and remainder operations take their inputs from r24 and
986 ;; r25, put their output in r27, and clobber r23 and r28 on all
987 ;; systems except Unicos/Mk. On Unicos, the standard library provides
988 ;; subroutines which use the standard calling convention and work on
991 ;; ??? Force sign-extension here because some versions of OSF/1 and
992 ;; Interix/NT don't do the right thing if the inputs are not properly
993 ;; sign-extended. But Linux, for instance, does not have this
994 ;; problem. Is it worth the complication here to eliminate the sign
997 (define_expand "divsi3"
999 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1001 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1002 (parallel [(set (match_dup 5)
1003 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
1004 (clobber (reg:DI 23))
1005 (clobber (reg:DI 28))])
1006 (set (match_operand:SI 0 "nonimmediate_operand" "")
1007 (subreg:SI (match_dup 5) 0))]
1008 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1010 operands[3] = gen_reg_rtx (DImode);
1011 operands[4] = gen_reg_rtx (DImode);
1012 operands[5] = gen_reg_rtx (DImode);
1015 (define_expand "udivsi3"
1017 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1019 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1020 (parallel [(set (match_dup 5)
1021 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
1022 (clobber (reg:DI 23))
1023 (clobber (reg:DI 28))])
1024 (set (match_operand:SI 0 "nonimmediate_operand" "")
1025 (subreg:SI (match_dup 5) 0))]
1026 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1028 operands[3] = gen_reg_rtx (DImode);
1029 operands[4] = gen_reg_rtx (DImode);
1030 operands[5] = gen_reg_rtx (DImode);
1033 (define_expand "modsi3"
1035 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1037 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1038 (parallel [(set (match_dup 5)
1039 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
1040 (clobber (reg:DI 23))
1041 (clobber (reg:DI 28))])
1042 (set (match_operand:SI 0 "nonimmediate_operand" "")
1043 (subreg:SI (match_dup 5) 0))]
1044 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1046 operands[3] = gen_reg_rtx (DImode);
1047 operands[4] = gen_reg_rtx (DImode);
1048 operands[5] = gen_reg_rtx (DImode);
1051 (define_expand "umodsi3"
1053 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1055 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1056 (parallel [(set (match_dup 5)
1057 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
1058 (clobber (reg:DI 23))
1059 (clobber (reg:DI 28))])
1060 (set (match_operand:SI 0 "nonimmediate_operand" "")
1061 (subreg:SI (match_dup 5) 0))]
1062 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1064 operands[3] = gen_reg_rtx (DImode);
1065 operands[4] = gen_reg_rtx (DImode);
1066 operands[5] = gen_reg_rtx (DImode);
1069 (define_expand "divdi3"
1070 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1071 (div:DI (match_operand:DI 1 "register_operand" "")
1072 (match_operand:DI 2 "register_operand" "")))
1073 (clobber (reg:DI 23))
1074 (clobber (reg:DI 28))])]
1075 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1078 (define_expand "udivdi3"
1079 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1080 (udiv:DI (match_operand:DI 1 "register_operand" "")
1081 (match_operand:DI 2 "register_operand" "")))
1082 (clobber (reg:DI 23))
1083 (clobber (reg:DI 28))])]
1084 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1087 (define_expand "moddi3"
1088 [(use (match_operand:DI 0 "register_operand" ""))
1089 (use (match_operand:DI 1 "register_operand" ""))
1090 (use (match_operand:DI 2 "register_operand" ""))]
1091 "!TARGET_ABI_OPEN_VMS"
1093 if (TARGET_ABI_UNICOSMK)
1094 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
1096 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
1100 (define_expand "moddi3_dft"
1101 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1102 (mod:DI (match_operand:DI 1 "register_operand" "")
1103 (match_operand:DI 2 "register_operand" "")))
1104 (clobber (reg:DI 23))
1105 (clobber (reg:DI 28))])]
1106 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1109 ;; On Unicos/Mk, we do as the system's C compiler does:
1110 ;; compute the quotient, multiply and subtract.
1112 (define_expand "moddi3_umk"
1113 [(use (match_operand:DI 0 "register_operand" ""))
1114 (use (match_operand:DI 1 "register_operand" ""))
1115 (use (match_operand:DI 2 "register_operand" ""))]
1116 "TARGET_ABI_UNICOSMK"
1118 rtx div, mul = gen_reg_rtx (DImode);
1120 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
1121 NULL_RTX, 0, OPTAB_LIB);
1122 div = force_reg (DImode, div);
1123 emit_insn (gen_muldi3 (mul, operands[2], div));
1124 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1128 (define_expand "umoddi3"
1129 [(use (match_operand:DI 0 "register_operand" ""))
1130 (use (match_operand:DI 1 "register_operand" ""))
1131 (use (match_operand:DI 2 "register_operand" ""))]
1132 "! TARGET_ABI_OPEN_VMS"
1134 if (TARGET_ABI_UNICOSMK)
1135 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
1137 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
1141 (define_expand "umoddi3_dft"
1142 [(parallel [(set (match_operand:DI 0 "register_operand" "")
1143 (umod:DI (match_operand:DI 1 "register_operand" "")
1144 (match_operand:DI 2 "register_operand" "")))
1145 (clobber (reg:DI 23))
1146 (clobber (reg:DI 28))])]
1147 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1150 (define_expand "umoddi3_umk"
1151 [(use (match_operand:DI 0 "register_operand" ""))
1152 (use (match_operand:DI 1 "register_operand" ""))
1153 (use (match_operand:DI 2 "register_operand" ""))]
1154 "TARGET_ABI_UNICOSMK"
1156 rtx div, mul = gen_reg_rtx (DImode);
1158 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
1159 NULL_RTX, 1, OPTAB_LIB);
1160 div = force_reg (DImode, div);
1161 emit_insn (gen_muldi3 (mul, operands[2], div));
1162 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
1166 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1167 ;; expanded by the assembler.
1169 (define_insn_and_split "*divmodsi_internal_er"
1170 [(set (match_operand:DI 0 "register_operand" "=c")
1171 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1172 [(match_operand:DI 1 "register_operand" "a")
1173 (match_operand:DI 2 "register_operand" "b")])))
1174 (clobber (reg:DI 23))
1175 (clobber (reg:DI 28))]
1176 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1177 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1178 "&& reload_completed"
1179 [(parallel [(set (match_dup 0)
1180 (sign_extend:DI (match_dup 3)))
1183 (clobber (reg:DI 23))
1184 (clobber (reg:DI 28))])]
1187 switch (GET_CODE (operands[3]))
1204 operands[4] = GEN_INT (alpha_next_sequence_number++);
1205 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1206 gen_rtx_SYMBOL_REF (DImode, str),
1209 [(set_attr "type" "jsr")
1210 (set_attr "length" "8")])
1212 (define_insn "*divmodsi_internal_er_1"
1213 [(set (match_operand:DI 0 "register_operand" "=c")
1214 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1215 [(match_operand:DI 1 "register_operand" "a")
1216 (match_operand:DI 2 "register_operand" "b")])))
1217 (use (match_operand:DI 4 "register_operand" "c"))
1218 (use (match_operand 5 "const_int_operand" ""))
1219 (clobber (reg:DI 23))
1220 (clobber (reg:DI 28))]
1221 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1222 "jsr $23,($27),__%E3%J5"
1223 [(set_attr "type" "jsr")
1224 (set_attr "length" "4")])
1226 (define_insn "*divmodsi_internal"
1227 [(set (match_operand:DI 0 "register_operand" "=c")
1228 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1229 [(match_operand:DI 1 "register_operand" "a")
1230 (match_operand:DI 2 "register_operand" "b")])))
1231 (clobber (reg:DI 23))
1232 (clobber (reg:DI 28))]
1233 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1235 [(set_attr "type" "jsr")
1236 (set_attr "length" "8")])
1238 (define_insn_and_split "*divmoddi_internal_er"
1239 [(set (match_operand:DI 0 "register_operand" "=c")
1240 (match_operator:DI 3 "divmod_operator"
1241 [(match_operand:DI 1 "register_operand" "a")
1242 (match_operand:DI 2 "register_operand" "b")]))
1243 (clobber (reg:DI 23))
1244 (clobber (reg:DI 28))]
1245 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1246 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1247 "&& reload_completed"
1248 [(parallel [(set (match_dup 0) (match_dup 3))
1251 (clobber (reg:DI 23))
1252 (clobber (reg:DI 28))])]
1255 switch (GET_CODE (operands[3]))
1272 operands[4] = GEN_INT (alpha_next_sequence_number++);
1273 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1274 gen_rtx_SYMBOL_REF (DImode, str),
1277 [(set_attr "type" "jsr")
1278 (set_attr "length" "8")])
1280 (define_insn "*divmoddi_internal_er_1"
1281 [(set (match_operand:DI 0 "register_operand" "=c")
1282 (match_operator:DI 3 "divmod_operator"
1283 [(match_operand:DI 1 "register_operand" "a")
1284 (match_operand:DI 2 "register_operand" "b")]))
1285 (use (match_operand:DI 4 "register_operand" "c"))
1286 (use (match_operand 5 "const_int_operand" ""))
1287 (clobber (reg:DI 23))
1288 (clobber (reg:DI 28))]
1289 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1290 "jsr $23,($27),__%E3%J5"
1291 [(set_attr "type" "jsr")
1292 (set_attr "length" "4")])
1294 (define_insn "*divmoddi_internal"
1295 [(set (match_operand:DI 0 "register_operand" "=c")
1296 (match_operator:DI 3 "divmod_operator"
1297 [(match_operand:DI 1 "register_operand" "a")
1298 (match_operand:DI 2 "register_operand" "b")]))
1299 (clobber (reg:DI 23))
1300 (clobber (reg:DI 28))]
1301 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1303 [(set_attr "type" "jsr")
1304 (set_attr "length" "8")])
1306 ;; Next are the basic logical operations. These only exist in DImode.
1308 (define_insn "anddi3"
1309 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1310 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1311 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1317 [(set_attr "type" "ilog,ilog,shift")])
1319 ;; There are times when we can split an AND into two AND insns. This occurs
1320 ;; when we can first clear any bytes and then clear anything else. For
1321 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1322 ;; Only do this when running on 64-bit host since the computations are
1323 ;; too messy otherwise.
1326 [(set (match_operand:DI 0 "register_operand" "")
1327 (and:DI (match_operand:DI 1 "register_operand" "")
1328 (match_operand:DI 2 "const_int_operand" "")))]
1329 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1330 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1331 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1333 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1334 unsigned HOST_WIDE_INT mask2 = mask1;
1337 /* For each byte that isn't all zeros, make it all ones. */
1338 for (i = 0; i < 64; i += 8)
1339 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1340 mask1 |= (HOST_WIDE_INT) 0xff << i;
1342 /* Now turn on any bits we've just turned off. */
1345 operands[3] = GEN_INT (mask1);
1346 operands[4] = GEN_INT (mask2);
1349 (define_expand "zero_extendqihi2"
1350 [(set (match_operand:HI 0 "register_operand" "")
1351 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1355 operands[1] = force_reg (QImode, operands[1]);
1358 (define_insn "*zero_extendqihi2_bwx"
1359 [(set (match_operand:HI 0 "register_operand" "=r,r")
1360 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1365 [(set_attr "type" "ilog,ild")])
1367 (define_insn "*zero_extendqihi2_nobwx"
1368 [(set (match_operand:HI 0 "register_operand" "=r")
1369 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1372 [(set_attr "type" "ilog")])
1374 (define_expand "zero_extendqisi2"
1375 [(set (match_operand:SI 0 "register_operand" "")
1376 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1380 operands[1] = force_reg (QImode, operands[1]);
1383 (define_insn "*zero_extendqisi2_bwx"
1384 [(set (match_operand:SI 0 "register_operand" "=r,r")
1385 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1390 [(set_attr "type" "ilog,ild")])
1392 (define_insn "*zero_extendqisi2_nobwx"
1393 [(set (match_operand:SI 0 "register_operand" "=r")
1394 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1397 [(set_attr "type" "ilog")])
1399 (define_expand "zero_extendqidi2"
1400 [(set (match_operand:DI 0 "register_operand" "")
1401 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1405 operands[1] = force_reg (QImode, operands[1]);
1408 (define_insn "*zero_extendqidi2_bwx"
1409 [(set (match_operand:DI 0 "register_operand" "=r,r")
1410 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1415 [(set_attr "type" "ilog,ild")])
1417 (define_insn "*zero_extendqidi2_nobwx"
1418 [(set (match_operand:DI 0 "register_operand" "=r")
1419 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1422 [(set_attr "type" "ilog")])
1424 (define_expand "zero_extendhisi2"
1425 [(set (match_operand:SI 0 "register_operand" "")
1426 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1430 operands[1] = force_reg (HImode, operands[1]);
1433 (define_insn "*zero_extendhisi2_bwx"
1434 [(set (match_operand:SI 0 "register_operand" "=r,r")
1435 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1440 [(set_attr "type" "shift,ild")])
1442 (define_insn "*zero_extendhisi2_nobwx"
1443 [(set (match_operand:SI 0 "register_operand" "=r")
1444 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1447 [(set_attr "type" "shift")])
1449 (define_expand "zero_extendhidi2"
1450 [(set (match_operand:DI 0 "register_operand" "")
1451 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1455 operands[1] = force_reg (HImode, operands[1]);
1458 (define_insn "*zero_extendhidi2_bwx"
1459 [(set (match_operand:DI 0 "register_operand" "=r,r")
1460 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1465 [(set_attr "type" "shift,ild")])
1467 (define_insn "*zero_extendhidi2_nobwx"
1468 [(set (match_operand:DI 0 "register_operand" "=r")
1469 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1472 [(set_attr "type" "shift")])
1474 (define_insn "zero_extendsidi2"
1475 [(set (match_operand:DI 0 "register_operand" "=r")
1476 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1479 [(set_attr "type" "shift")])
1481 (define_insn "andnotdi3"
1482 [(set (match_operand:DI 0 "register_operand" "=r")
1483 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1484 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1487 [(set_attr "type" "ilog")])
1489 (define_insn "iordi3"
1490 [(set (match_operand:DI 0 "register_operand" "=r,r")
1491 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1492 (match_operand:DI 2 "or_operand" "rI,N")))]
1497 [(set_attr "type" "ilog")])
1499 (define_insn "one_cmpldi2"
1500 [(set (match_operand:DI 0 "register_operand" "=r")
1501 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1504 [(set_attr "type" "ilog")])
1506 (define_insn "*iornot"
1507 [(set (match_operand:DI 0 "register_operand" "=r")
1508 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1509 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1512 [(set_attr "type" "ilog")])
1514 (define_insn "xordi3"
1515 [(set (match_operand:DI 0 "register_operand" "=r,r")
1516 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1517 (match_operand:DI 2 "or_operand" "rI,N")))]
1522 [(set_attr "type" "ilog")])
1524 (define_insn "*xornot"
1525 [(set (match_operand:DI 0 "register_operand" "=r")
1526 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1527 (match_operand:DI 2 "register_operand" "rI"))))]
1530 [(set_attr "type" "ilog")])
1532 ;; Handle the FFS insn iff we support CIX.
1534 (define_expand "ffsdi2"
1536 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1538 (plus:DI (match_dup 2) (const_int 1)))
1539 (set (match_operand:DI 0 "register_operand" "")
1540 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1541 (const_int 0) (match_dup 3)))]
1544 operands[2] = gen_reg_rtx (DImode);
1545 operands[3] = gen_reg_rtx (DImode);
1548 (define_insn "*cttz"
1549 [(set (match_operand:DI 0 "register_operand" "=r")
1550 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1553 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1554 ; reuse the existing type name.
1555 [(set_attr "type" "mvi")])
1557 ;; Next come the shifts and the various extract and insert operations.
1559 (define_insn "ashldi3"
1560 [(set (match_operand:DI 0 "register_operand" "=r,r")
1561 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1562 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1565 switch (which_alternative)
1568 if (operands[2] == const1_rtx)
1569 return "addq %r1,%r1,%0";
1571 return "s%P2addq %r1,0,%0";
1573 return "sll %r1,%2,%0";
1578 [(set_attr "type" "iadd,shift")])
1580 ;; ??? The following pattern is made by combine, but earlier phases
1581 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1582 ;; with this in a better way at some point.
1584 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1586 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1587 ;; (match_operand:DI 2 "const_int_operand" "P"))
1589 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1591 ;; if (operands[2] == const1_rtx)
1592 ;; return "addl %r1,%r1,%0";
1594 ;; return "s%P2addl %r1,0,%0";
1596 ;; [(set_attr "type" "iadd")])
1598 (define_insn "lshrdi3"
1599 [(set (match_operand:DI 0 "register_operand" "=r")
1600 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1601 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1604 [(set_attr "type" "shift")])
1606 (define_insn "ashrdi3"
1607 [(set (match_operand:DI 0 "register_operand" "=r")
1608 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1609 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1612 [(set_attr "type" "shift")])
1614 (define_expand "extendqihi2"
1616 (ashift:DI (match_operand:QI 1 "some_operand" "")
1618 (set (match_operand:HI 0 "register_operand" "")
1619 (ashiftrt:DI (match_dup 2)
1625 emit_insn (gen_extendqihi2x (operands[0],
1626 force_reg (QImode, operands[1])));
1630 /* If we have an unaligned MEM, extend to DImode (which we do
1631 specially) and then copy to the result. */
1632 if (unaligned_memory_operand (operands[1], HImode))
1634 rtx temp = gen_reg_rtx (DImode);
1636 emit_insn (gen_extendqidi2 (temp, operands[1]));
1637 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1641 operands[0] = gen_lowpart (DImode, operands[0]);
1642 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1643 operands[2] = gen_reg_rtx (DImode);
1646 (define_insn "extendqidi2x"
1647 [(set (match_operand:DI 0 "register_operand" "=r")
1648 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1651 [(set_attr "type" "shift")])
1653 (define_insn "extendhidi2x"
1654 [(set (match_operand:DI 0 "register_operand" "=r")
1655 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1658 [(set_attr "type" "shift")])
1660 (define_insn "extendqisi2x"
1661 [(set (match_operand:SI 0 "register_operand" "=r")
1662 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1665 [(set_attr "type" "shift")])
1667 (define_insn "extendhisi2x"
1668 [(set (match_operand:SI 0 "register_operand" "=r")
1669 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1672 [(set_attr "type" "shift")])
1674 (define_insn "extendqihi2x"
1675 [(set (match_operand:HI 0 "register_operand" "=r")
1676 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1679 [(set_attr "type" "shift")])
1681 (define_expand "extendqisi2"
1683 (ashift:DI (match_operand:QI 1 "some_operand" "")
1685 (set (match_operand:SI 0 "register_operand" "")
1686 (ashiftrt:DI (match_dup 2)
1692 emit_insn (gen_extendqisi2x (operands[0],
1693 force_reg (QImode, operands[1])));
1697 /* If we have an unaligned MEM, extend to a DImode form of
1698 the result (which we do specially). */
1699 if (unaligned_memory_operand (operands[1], QImode))
1701 rtx temp = gen_reg_rtx (DImode);
1703 emit_insn (gen_extendqidi2 (temp, operands[1]));
1704 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1708 operands[0] = gen_lowpart (DImode, operands[0]);
1709 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1710 operands[2] = gen_reg_rtx (DImode);
1713 (define_expand "extendqidi2"
1715 (ashift:DI (match_operand:QI 1 "some_operand" "")
1717 (set (match_operand:DI 0 "register_operand" "")
1718 (ashiftrt:DI (match_dup 2)
1724 emit_insn (gen_extendqidi2x (operands[0],
1725 force_reg (QImode, operands[1])));
1729 if (unaligned_memory_operand (operands[1], QImode))
1732 = gen_unaligned_extendqidi (operands[0],
1733 get_unaligned_address (operands[1], 1));
1735 alpha_set_memflags (seq, operands[1]);
1740 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1741 operands[2] = gen_reg_rtx (DImode);
1744 (define_expand "extendhisi2"
1746 (ashift:DI (match_operand:HI 1 "some_operand" "")
1748 (set (match_operand:SI 0 "register_operand" "")
1749 (ashiftrt:DI (match_dup 2)
1755 emit_insn (gen_extendhisi2x (operands[0],
1756 force_reg (HImode, operands[1])));
1760 /* If we have an unaligned MEM, extend to a DImode form of
1761 the result (which we do specially). */
1762 if (unaligned_memory_operand (operands[1], HImode))
1764 rtx temp = gen_reg_rtx (DImode);
1766 emit_insn (gen_extendhidi2 (temp, operands[1]));
1767 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1771 operands[0] = gen_lowpart (DImode, operands[0]);
1772 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1773 operands[2] = gen_reg_rtx (DImode);
1776 (define_expand "extendhidi2"
1778 (ashift:DI (match_operand:HI 1 "some_operand" "")
1780 (set (match_operand:DI 0 "register_operand" "")
1781 (ashiftrt:DI (match_dup 2)
1787 emit_insn (gen_extendhidi2x (operands[0],
1788 force_reg (HImode, operands[1])));
1792 if (unaligned_memory_operand (operands[1], HImode))
1795 = gen_unaligned_extendhidi (operands[0],
1796 get_unaligned_address (operands[1], 2));
1798 alpha_set_memflags (seq, operands[1]);
1803 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1804 operands[2] = gen_reg_rtx (DImode);
1807 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1808 ;; as a pattern saves one instruction. The code is similar to that for
1809 ;; the unaligned loads (see below).
1811 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1812 (define_expand "unaligned_extendqidi"
1813 [(use (match_operand:QI 0 "register_operand" ""))
1814 (use (match_operand:DI 1 "address_operand" ""))]
1817 if (WORDS_BIG_ENDIAN)
1818 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1820 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1824 (define_expand "unaligned_extendqidi_le"
1825 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1827 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1830 (ashift:DI (match_dup 3)
1831 (minus:DI (const_int 64)
1833 (and:DI (match_dup 2) (const_int 7))
1835 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1836 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1837 "! WORDS_BIG_ENDIAN"
1839 operands[2] = gen_reg_rtx (DImode);
1840 operands[3] = gen_reg_rtx (DImode);
1841 operands[4] = gen_reg_rtx (DImode);
1844 (define_expand "unaligned_extendqidi_be"
1845 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1846 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1848 (mem:DI (and:DI (match_dup 3)
1850 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1852 (ashift:DI (match_dup 4)
1855 (plus:DI (match_dup 5) (const_int 1))
1858 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1859 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1862 operands[2] = gen_reg_rtx (DImode);
1863 operands[3] = gen_reg_rtx (DImode);
1864 operands[4] = gen_reg_rtx (DImode);
1865 operands[5] = gen_reg_rtx (DImode);
1866 operands[6] = gen_reg_rtx (DImode);
1869 (define_expand "unaligned_extendhidi"
1870 [(use (match_operand:QI 0 "register_operand" ""))
1871 (use (match_operand:DI 1 "address_operand" ""))]
1874 operands[0] = gen_lowpart (DImode, operands[0]);
1875 emit_insn ((WORDS_BIG_ENDIAN
1876 ? gen_unaligned_extendhidi_be
1877 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1881 (define_expand "unaligned_extendhidi_le"
1882 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1884 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1887 (ashift:DI (match_dup 3)
1888 (minus:DI (const_int 64)
1890 (and:DI (match_dup 2) (const_int 7))
1892 (set (match_operand:DI 0 "register_operand" "")
1893 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1894 "! WORDS_BIG_ENDIAN"
1896 operands[2] = gen_reg_rtx (DImode);
1897 operands[3] = gen_reg_rtx (DImode);
1898 operands[4] = gen_reg_rtx (DImode);
1901 (define_expand "unaligned_extendhidi_be"
1902 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1903 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1905 (mem:DI (and:DI (match_dup 3)
1907 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1909 (ashift:DI (match_dup 4)
1912 (plus:DI (match_dup 5) (const_int 1))
1915 (set (match_operand:DI 0 "register_operand" "")
1916 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1919 operands[2] = gen_reg_rtx (DImode);
1920 operands[3] = gen_reg_rtx (DImode);
1921 operands[4] = gen_reg_rtx (DImode);
1922 operands[5] = gen_reg_rtx (DImode);
1923 operands[6] = gen_reg_rtx (DImode);
1926 (define_insn "*extxl_const"
1927 [(set (match_operand:DI 0 "register_operand" "=r")
1928 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1929 (match_operand:DI 2 "mode_width_operand" "n")
1930 (match_operand:DI 3 "mul8_operand" "I")))]
1932 "ext%M2l %r1,%s3,%0"
1933 [(set_attr "type" "shift")])
1935 (define_insn "extxl_le"
1936 [(set (match_operand:DI 0 "register_operand" "=r")
1937 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1938 (match_operand:DI 2 "mode_width_operand" "n")
1939 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1941 "! WORDS_BIG_ENDIAN"
1943 [(set_attr "type" "shift")])
1945 (define_insn "extxl_be"
1946 [(set (match_operand:DI 0 "register_operand" "=r")
1947 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1948 (match_operand:DI 2 "mode_width_operand" "n")
1952 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1956 [(set_attr "type" "shift")])
1958 ;; Combine has some strange notion of preserving existing undefined behaviour
1959 ;; in shifts larger than a word size. So capture these patterns that it
1960 ;; should have turned into zero_extracts.
1962 (define_insn "*extxl_1_le"
1963 [(set (match_operand:DI 0 "register_operand" "=r")
1964 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1965 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1967 (match_operand:DI 3 "mode_mask_operand" "n")))]
1968 "! WORDS_BIG_ENDIAN"
1970 [(set_attr "type" "shift")])
1972 (define_insn "*extxl_1_be"
1973 [(set (match_operand:DI 0 "register_operand" "=r")
1974 (and:DI (lshiftrt:DI
1975 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1976 (minus:DI (const_int 56)
1977 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1979 (match_operand:DI 3 "mode_mask_operand" "n")))]
1982 [(set_attr "type" "shift")])
1984 (define_insn "*extql_2_le"
1985 [(set (match_operand:DI 0 "register_operand" "=r")
1986 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1987 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1989 "! WORDS_BIG_ENDIAN"
1991 [(set_attr "type" "shift")])
1993 (define_insn "*extql_2_be"
1994 [(set (match_operand:DI 0 "register_operand" "=r")
1996 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1997 (minus:DI (const_int 56)
1999 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2003 [(set_attr "type" "shift")])
2005 (define_insn "extqh_le"
2006 [(set (match_operand:DI 0 "register_operand" "=r")
2008 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2009 (minus:DI (const_int 64)
2012 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2015 "! WORDS_BIG_ENDIAN"
2017 [(set_attr "type" "shift")])
2019 (define_insn "extqh_be"
2020 [(set (match_operand:DI 0 "register_operand" "=r")
2022 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2025 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2031 [(set_attr "type" "shift")])
2033 (define_insn "extlh_le"
2034 [(set (match_operand:DI 0 "register_operand" "=r")
2036 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2037 (const_int 2147483647))
2038 (minus:DI (const_int 64)
2041 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2044 "! WORDS_BIG_ENDIAN"
2046 [(set_attr "type" "shift")])
2048 (define_insn "extlh_be"
2049 [(set (match_operand:DI 0 "register_operand" "=r")
2052 (match_operand:DI 1 "reg_or_0_operand" "rJ")
2056 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2060 (const_int 2147483647)))]
2063 [(set_attr "type" "shift")])
2065 (define_insn "extwh_le"
2066 [(set (match_operand:DI 0 "register_operand" "=r")
2068 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2070 (minus:DI (const_int 64)
2073 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2076 "! WORDS_BIG_ENDIAN"
2078 [(set_attr "type" "shift")])
2080 (define_insn "extwh_be"
2081 [(set (match_operand:DI 0 "register_operand" "=r")
2083 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2087 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2091 (const_int 65535)))]
2094 [(set_attr "type" "shift")])
2096 ;; This converts an extXl into an extXh with an appropriate adjustment
2097 ;; to the address calculation.
2100 ;; [(set (match_operand:DI 0 "register_operand" "")
2101 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2102 ;; (match_operand:DI 2 "mode_width_operand" "")
2103 ;; (ashift:DI (match_operand:DI 3 "" "")
2105 ;; (match_operand:DI 4 "const_int_operand" "")))
2106 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2107 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2108 ;; [(set (match_dup 5) (match_dup 6))
2109 ;; (set (match_dup 0)
2110 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2111 ;; (ashift:DI (plus:DI (match_dup 5)
2117 ;; operands[6] = plus_constant (operands[3],
2118 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2119 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2122 (define_insn "*insbl_const"
2123 [(set (match_operand:DI 0 "register_operand" "=r")
2124 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2125 (match_operand:DI 2 "mul8_operand" "I")))]
2128 [(set_attr "type" "shift")])
2130 (define_insn "*inswl_const"
2131 [(set (match_operand:DI 0 "register_operand" "=r")
2132 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2133 (match_operand:DI 2 "mul8_operand" "I")))]
2136 [(set_attr "type" "shift")])
2138 (define_insn "*insll_const"
2139 [(set (match_operand:DI 0 "register_operand" "=r")
2140 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2141 (match_operand:DI 2 "mul8_operand" "I")))]
2144 [(set_attr "type" "shift")])
2146 (define_insn "insbl_le"
2147 [(set (match_operand:DI 0 "register_operand" "=r")
2148 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2149 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2151 "! WORDS_BIG_ENDIAN"
2153 [(set_attr "type" "shift")])
2155 (define_insn "insbl_be"
2156 [(set (match_operand:DI 0 "register_operand" "=r")
2157 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2158 (minus:DI (const_int 56)
2159 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2163 [(set_attr "type" "shift")])
2165 (define_insn "inswl_le"
2166 [(set (match_operand:DI 0 "register_operand" "=r")
2167 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2168 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2170 "! WORDS_BIG_ENDIAN"
2172 [(set_attr "type" "shift")])
2174 (define_insn "inswl_be"
2175 [(set (match_operand:DI 0 "register_operand" "=r")
2176 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2177 (minus:DI (const_int 56)
2178 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2182 [(set_attr "type" "shift")])
2184 (define_insn "insll_le"
2185 [(set (match_operand:DI 0 "register_operand" "=r")
2186 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2187 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2189 "! WORDS_BIG_ENDIAN"
2191 [(set_attr "type" "shift")])
2193 (define_insn "insll_be"
2194 [(set (match_operand:DI 0 "register_operand" "=r")
2195 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2196 (minus:DI (const_int 56)
2197 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2201 [(set_attr "type" "shift")])
2203 (define_insn "insql_le"
2204 [(set (match_operand:DI 0 "register_operand" "=r")
2205 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2206 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2208 "! WORDS_BIG_ENDIAN"
2210 [(set_attr "type" "shift")])
2212 (define_insn "insql_be"
2213 [(set (match_operand:DI 0 "register_operand" "=r")
2214 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2215 (minus:DI (const_int 56)
2216 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2220 [(set_attr "type" "shift")])
2222 ;; Combine has this sometimes habit of moving the and outside of the
2223 ;; shift, making life more interesting.
2225 (define_insn "*insxl"
2226 [(set (match_operand:DI 0 "register_operand" "=r")
2227 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2228 (match_operand:DI 2 "mul8_operand" "I"))
2229 (match_operand:DI 3 "immediate_operand" "i")))]
2230 "HOST_BITS_PER_WIDE_INT == 64
2231 && GET_CODE (operands[3]) == CONST_INT
2232 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2233 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2234 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2235 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2236 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2237 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2239 #if HOST_BITS_PER_WIDE_INT == 64
2240 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2241 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2242 return "insbl %1,%s2,%0";
2243 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2244 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2245 return "inswl %1,%s2,%0";
2246 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2247 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2248 return "insll %1,%s2,%0";
2252 [(set_attr "type" "shift")])
2254 ;; We do not include the insXh insns because they are complex to express
2255 ;; and it does not appear that we would ever want to generate them.
2257 ;; Since we need them for block moves, though, cop out and use unspec.
2259 (define_insn "insxh"
2260 [(set (match_operand:DI 0 "register_operand" "=r")
2261 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2262 (match_operand:DI 2 "mode_width_operand" "n")
2263 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2267 [(set_attr "type" "shift")])
2269 (define_insn "mskxl_le"
2270 [(set (match_operand:DI 0 "register_operand" "=r")
2271 (and:DI (not:DI (ashift:DI
2272 (match_operand:DI 2 "mode_mask_operand" "n")
2274 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2276 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2277 "! WORDS_BIG_ENDIAN"
2279 [(set_attr "type" "shift")])
2281 (define_insn "mskxl_be"
2282 [(set (match_operand:DI 0 "register_operand" "=r")
2283 (and:DI (not:DI (ashift:DI
2284 (match_operand:DI 2 "mode_mask_operand" "n")
2285 (minus:DI (const_int 56)
2287 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2289 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2292 [(set_attr "type" "shift")])
2294 ;; We do not include the mskXh insns because it does not appear we would
2295 ;; ever generate one.
2297 ;; Again, we do for block moves and we use unspec again.
2299 (define_insn "mskxh"
2300 [(set (match_operand:DI 0 "register_operand" "=r")
2301 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2302 (match_operand:DI 2 "mode_width_operand" "n")
2303 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2307 [(set_attr "type" "shift")])
2309 ;; Prefer AND + NE over LSHIFTRT + AND.
2311 (define_insn_and_split "*ze_and_ne"
2312 [(set (match_operand:DI 0 "register_operand" "=r")
2313 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2315 (match_operand 2 "const_int_operand" "I")))]
2316 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2318 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2320 (and:DI (match_dup 1) (match_dup 3)))
2322 (ne:DI (match_dup 0) (const_int 0)))]
2323 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2325 ;; Floating-point operations. All the double-precision insns can extend
2326 ;; from single, so indicate that. The exception are the ones that simply
2327 ;; play with the sign bits; it's not clear what to do there.
2329 (define_insn "abssf2"
2330 [(set (match_operand:SF 0 "register_operand" "=f")
2331 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2334 [(set_attr "type" "fcpys")])
2336 (define_insn "*nabssf2"
2337 [(set (match_operand:SF 0 "register_operand" "=f")
2338 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2341 [(set_attr "type" "fadd")])
2343 (define_insn "absdf2"
2344 [(set (match_operand:DF 0 "register_operand" "=f")
2345 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2348 [(set_attr "type" "fcpys")])
2350 (define_insn "*nabsdf2"
2351 [(set (match_operand:DF 0 "register_operand" "=f")
2352 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2355 [(set_attr "type" "fadd")])
2357 (define_expand "abstf2"
2358 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2359 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2360 (use (match_dup 2))])]
2361 "TARGET_HAS_XFLOATING_LIBS"
2363 #if HOST_BITS_PER_WIDE_INT >= 64
2364 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2366 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2370 (define_insn_and_split "*abstf_internal"
2371 [(set (match_operand:TF 0 "register_operand" "=r")
2372 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2373 (use (match_operand:DI 2 "register_operand" "r"))]
2374 "TARGET_HAS_XFLOATING_LIBS"
2376 "&& reload_completed"
2378 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2380 (define_insn "negsf2"
2381 [(set (match_operand:SF 0 "register_operand" "=f")
2382 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2385 [(set_attr "type" "fadd")])
2387 (define_insn "negdf2"
2388 [(set (match_operand:DF 0 "register_operand" "=f")
2389 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2392 [(set_attr "type" "fadd")])
2394 (define_expand "negtf2"
2395 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2396 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2397 (use (match_dup 2))])]
2398 "TARGET_HAS_XFLOATING_LIBS"
2400 #if HOST_BITS_PER_WIDE_INT >= 64
2401 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2403 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2407 (define_insn_and_split "*negtf_internal"
2408 [(set (match_operand:TF 0 "register_operand" "=r")
2409 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2410 (use (match_operand:DI 2 "register_operand" "r"))]
2411 "TARGET_HAS_XFLOATING_LIBS"
2413 "&& reload_completed"
2415 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2417 (define_insn "*addsf_ieee"
2418 [(set (match_operand:SF 0 "register_operand" "=&f")
2419 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2420 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2421 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2422 "add%,%/ %R1,%R2,%0"
2423 [(set_attr "type" "fadd")
2424 (set_attr "trap" "yes")
2425 (set_attr "round_suffix" "normal")
2426 (set_attr "trap_suffix" "u_su_sui")])
2428 (define_insn "addsf3"
2429 [(set (match_operand:SF 0 "register_operand" "=f")
2430 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2431 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2433 "add%,%/ %R1,%R2,%0"
2434 [(set_attr "type" "fadd")
2435 (set_attr "trap" "yes")
2436 (set_attr "round_suffix" "normal")
2437 (set_attr "trap_suffix" "u_su_sui")])
2439 (define_insn "*adddf_ieee"
2440 [(set (match_operand:DF 0 "register_operand" "=&f")
2441 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2442 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2443 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2444 "add%-%/ %R1,%R2,%0"
2445 [(set_attr "type" "fadd")
2446 (set_attr "trap" "yes")
2447 (set_attr "round_suffix" "normal")
2448 (set_attr "trap_suffix" "u_su_sui")])
2450 (define_insn "adddf3"
2451 [(set (match_operand:DF 0 "register_operand" "=f")
2452 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2453 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2455 "add%-%/ %R1,%R2,%0"
2456 [(set_attr "type" "fadd")
2457 (set_attr "trap" "yes")
2458 (set_attr "round_suffix" "normal")
2459 (set_attr "trap_suffix" "u_su_sui")])
2461 (define_insn "*adddf_ext1"
2462 [(set (match_operand:DF 0 "register_operand" "=f")
2463 (plus:DF (float_extend:DF
2464 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2465 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2466 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2467 "add%-%/ %R1,%R2,%0"
2468 [(set_attr "type" "fadd")
2469 (set_attr "trap" "yes")
2470 (set_attr "round_suffix" "normal")
2471 (set_attr "trap_suffix" "u_su_sui")])
2473 (define_insn "*adddf_ext2"
2474 [(set (match_operand:DF 0 "register_operand" "=f")
2475 (plus:DF (float_extend:DF
2476 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2478 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2479 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2480 "add%-%/ %R1,%R2,%0"
2481 [(set_attr "type" "fadd")
2482 (set_attr "trap" "yes")
2483 (set_attr "round_suffix" "normal")
2484 (set_attr "trap_suffix" "u_su_sui")])
2486 (define_expand "addtf3"
2487 [(use (match_operand 0 "register_operand" ""))
2488 (use (match_operand 1 "general_operand" ""))
2489 (use (match_operand 2 "general_operand" ""))]
2490 "TARGET_HAS_XFLOATING_LIBS"
2491 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2493 ;; Define conversion operators between DFmode and SImode, using the cvtql
2494 ;; instruction. To allow combine et al to do useful things, we keep the
2495 ;; operation as a unit until after reload, at which point we split the
2498 ;; Note that we (attempt to) only consider this optimization when the
2499 ;; ultimate destination is memory. If we will be doing further integer
2500 ;; processing, it is cheaper to do the truncation in the int regs.
2502 (define_insn "*cvtql"
2503 [(set (match_operand:SI 0 "register_operand" "=f")
2504 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2508 [(set_attr "type" "fadd")
2509 (set_attr "trap" "yes")
2510 (set_attr "trap_suffix" "v_sv")])
2512 (define_insn_and_split "*fix_truncdfsi_ieee"
2513 [(set (match_operand:SI 0 "memory_operand" "=m")
2514 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2515 (clobber (match_scratch:DI 2 "=&f"))
2516 (clobber (match_scratch:SI 3 "=&f"))]
2517 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2519 "&& reload_completed"
2520 [(set (match_dup 2) (fix:DI (match_dup 1)))
2521 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2522 (set (match_dup 0) (match_dup 3))]
2524 [(set_attr "type" "fadd")
2525 (set_attr "trap" "yes")])
2527 (define_insn_and_split "*fix_truncdfsi_internal"
2528 [(set (match_operand:SI 0 "memory_operand" "=m")
2529 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2530 (clobber (match_scratch:DI 2 "=f"))]
2531 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2533 "&& reload_completed"
2534 [(set (match_dup 2) (fix:DI (match_dup 1)))
2535 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2536 (set (match_dup 0) (match_dup 3))]
2537 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2538 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2539 [(set_attr "type" "fadd")
2540 (set_attr "trap" "yes")])
2542 (define_insn "*fix_truncdfdi_ieee"
2543 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2544 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2545 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2547 [(set_attr "type" "fadd")
2548 (set_attr "trap" "yes")
2549 (set_attr "round_suffix" "c")
2550 (set_attr "trap_suffix" "v_sv_svi")])
2552 (define_insn "fix_truncdfdi2"
2553 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2554 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2557 [(set_attr "type" "fadd")
2558 (set_attr "trap" "yes")
2559 (set_attr "round_suffix" "c")
2560 (set_attr "trap_suffix" "v_sv_svi")])
2562 ;; Likewise between SFmode and SImode.
2564 (define_insn_and_split "*fix_truncsfsi_ieee"
2565 [(set (match_operand:SI 0 "memory_operand" "=m")
2566 (subreg:SI (fix:DI (float_extend:DF
2567 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2568 (clobber (match_scratch:DI 2 "=&f"))
2569 (clobber (match_scratch:SI 3 "=&f"))]
2570 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2572 "&& reload_completed"
2573 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2574 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2575 (set (match_dup 0) (match_dup 3))]
2577 [(set_attr "type" "fadd")
2578 (set_attr "trap" "yes")])
2580 (define_insn_and_split "*fix_truncsfsi_internal"
2581 [(set (match_operand:SI 0 "memory_operand" "=m")
2582 (subreg:SI (fix:DI (float_extend:DF
2583 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2584 (clobber (match_scratch:DI 2 "=f"))]
2585 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2587 "&& reload_completed"
2588 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2589 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2590 (set (match_dup 0) (match_dup 3))]
2591 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2592 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2593 [(set_attr "type" "fadd")
2594 (set_attr "trap" "yes")])
2596 (define_insn "*fix_truncsfdi_ieee"
2597 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2598 (fix:DI (float_extend:DF
2599 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2600 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2602 [(set_attr "type" "fadd")
2603 (set_attr "trap" "yes")
2604 (set_attr "round_suffix" "c")
2605 (set_attr "trap_suffix" "v_sv_svi")])
2607 (define_insn "fix_truncsfdi2"
2608 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2609 (fix:DI (float_extend:DF
2610 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2613 [(set_attr "type" "fadd")
2614 (set_attr "trap" "yes")
2615 (set_attr "round_suffix" "c")
2616 (set_attr "trap_suffix" "v_sv_svi")])
2618 (define_expand "fix_trunctfdi2"
2619 [(use (match_operand:DI 0 "register_operand" ""))
2620 (use (match_operand:TF 1 "general_operand" ""))]
2621 "TARGET_HAS_XFLOATING_LIBS"
2622 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2624 (define_insn "*floatdisf_ieee"
2625 [(set (match_operand:SF 0 "register_operand" "=&f")
2626 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2627 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2629 [(set_attr "type" "fadd")
2630 (set_attr "trap" "yes")
2631 (set_attr "round_suffix" "normal")
2632 (set_attr "trap_suffix" "sui")])
2634 (define_insn "floatdisf2"
2635 [(set (match_operand:SF 0 "register_operand" "=f")
2636 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2639 [(set_attr "type" "fadd")
2640 (set_attr "trap" "yes")
2641 (set_attr "round_suffix" "normal")
2642 (set_attr "trap_suffix" "sui")])
2644 (define_insn "*floatdidf_ieee"
2645 [(set (match_operand:DF 0 "register_operand" "=&f")
2646 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2647 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2649 [(set_attr "type" "fadd")
2650 (set_attr "trap" "yes")
2651 (set_attr "round_suffix" "normal")
2652 (set_attr "trap_suffix" "sui")])
2654 (define_insn "floatdidf2"
2655 [(set (match_operand:DF 0 "register_operand" "=f")
2656 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2659 [(set_attr "type" "fadd")
2660 (set_attr "trap" "yes")
2661 (set_attr "round_suffix" "normal")
2662 (set_attr "trap_suffix" "sui")])
2664 (define_expand "floatditf2"
2665 [(use (match_operand:TF 0 "register_operand" ""))
2666 (use (match_operand:DI 1 "general_operand" ""))]
2667 "TARGET_HAS_XFLOATING_LIBS"
2668 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2670 (define_expand "floatunsdisf2"
2671 [(use (match_operand:SF 0 "register_operand" ""))
2672 (use (match_operand:DI 1 "register_operand" ""))]
2674 "alpha_emit_floatuns (operands); DONE;")
2676 (define_expand "floatunsdidf2"
2677 [(use (match_operand:DF 0 "register_operand" ""))
2678 (use (match_operand:DI 1 "register_operand" ""))]
2680 "alpha_emit_floatuns (operands); DONE;")
2682 (define_expand "floatunsditf2"
2683 [(use (match_operand:TF 0 "register_operand" ""))
2684 (use (match_operand:DI 1 "general_operand" ""))]
2685 "TARGET_HAS_XFLOATING_LIBS"
2686 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2688 (define_expand "extendsfdf2"
2689 [(set (match_operand:DF 0 "register_operand" "")
2690 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2693 if (alpha_fptm >= ALPHA_FPTM_SU)
2694 operands[1] = force_reg (SFmode, operands[1]);
2697 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2698 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2700 (define_insn "*extendsfdf2_ieee"
2701 [(set (match_operand:DF 0 "register_operand" "=&f")
2702 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2703 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2705 [(set_attr "type" "fadd")
2706 (set_attr "trap" "yes")])
2708 (define_insn "*extendsfdf2_internal"
2709 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2710 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2711 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2716 [(set_attr "type" "fcpys,fld,fst")])
2718 (define_expand "extendsftf2"
2719 [(use (match_operand:TF 0 "register_operand" ""))
2720 (use (match_operand:SF 1 "general_operand" ""))]
2721 "TARGET_HAS_XFLOATING_LIBS"
2723 rtx tmp = gen_reg_rtx (DFmode);
2724 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2725 emit_insn (gen_extenddftf2 (operands[0], tmp));
2729 (define_expand "extenddftf2"
2730 [(use (match_operand:TF 0 "register_operand" ""))
2731 (use (match_operand:DF 1 "general_operand" ""))]
2732 "TARGET_HAS_XFLOATING_LIBS"
2733 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2735 (define_insn "*truncdfsf2_ieee"
2736 [(set (match_operand:SF 0 "register_operand" "=&f")
2737 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2738 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2740 [(set_attr "type" "fadd")
2741 (set_attr "trap" "yes")
2742 (set_attr "round_suffix" "normal")
2743 (set_attr "trap_suffix" "u_su_sui")])
2745 (define_insn "truncdfsf2"
2746 [(set (match_operand:SF 0 "register_operand" "=f")
2747 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2750 [(set_attr "type" "fadd")
2751 (set_attr "trap" "yes")
2752 (set_attr "round_suffix" "normal")
2753 (set_attr "trap_suffix" "u_su_sui")])
2755 (define_expand "trunctfdf2"
2756 [(use (match_operand:DF 0 "register_operand" ""))
2757 (use (match_operand:TF 1 "general_operand" ""))]
2758 "TARGET_HAS_XFLOATING_LIBS"
2759 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2761 (define_expand "trunctfsf2"
2762 [(use (match_operand:SF 0 "register_operand" ""))
2763 (use (match_operand:TF 1 "general_operand" ""))]
2764 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2766 rtx tmpf, sticky, arg, lo, hi;
2768 tmpf = gen_reg_rtx (DFmode);
2769 sticky = gen_reg_rtx (DImode);
2770 arg = copy_to_mode_reg (TFmode, operands[1]);
2771 lo = gen_lowpart (DImode, arg);
2772 hi = gen_highpart (DImode, arg);
2774 /* Convert the low word of the TFmode value into a sticky rounding bit,
2775 then or it into the low bit of the high word. This leaves the sticky
2776 bit at bit 48 of the fraction, which is representable in DFmode,
2777 which prevents rounding error in the final conversion to SFmode. */
2779 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2780 gen_rtx_NE (DImode, lo, const0_rtx)));
2781 emit_insn (gen_iordi3 (hi, hi, sticky));
2782 emit_insn (gen_trunctfdf2 (tmpf, arg));
2783 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2787 (define_insn "*divsf3_ieee"
2788 [(set (match_operand:SF 0 "register_operand" "=&f")
2789 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2790 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2791 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2792 "div%,%/ %R1,%R2,%0"
2793 [(set_attr "type" "fdiv")
2794 (set_attr "opsize" "si")
2795 (set_attr "trap" "yes")
2796 (set_attr "round_suffix" "normal")
2797 (set_attr "trap_suffix" "u_su_sui")])
2799 (define_insn "divsf3"
2800 [(set (match_operand:SF 0 "register_operand" "=f")
2801 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2802 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2804 "div%,%/ %R1,%R2,%0"
2805 [(set_attr "type" "fdiv")
2806 (set_attr "opsize" "si")
2807 (set_attr "trap" "yes")
2808 (set_attr "round_suffix" "normal")
2809 (set_attr "trap_suffix" "u_su_sui")])
2811 (define_insn "*divdf3_ieee"
2812 [(set (match_operand:DF 0 "register_operand" "=&f")
2813 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2814 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2815 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2816 "div%-%/ %R1,%R2,%0"
2817 [(set_attr "type" "fdiv")
2818 (set_attr "trap" "yes")
2819 (set_attr "round_suffix" "normal")
2820 (set_attr "trap_suffix" "u_su_sui")])
2822 (define_insn "divdf3"
2823 [(set (match_operand:DF 0 "register_operand" "=f")
2824 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2825 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2827 "div%-%/ %R1,%R2,%0"
2828 [(set_attr "type" "fdiv")
2829 (set_attr "trap" "yes")
2830 (set_attr "round_suffix" "normal")
2831 (set_attr "trap_suffix" "u_su_sui")])
2833 (define_insn "*divdf_ext1"
2834 [(set (match_operand:DF 0 "register_operand" "=f")
2835 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2836 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2837 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2838 "div%-%/ %R1,%R2,%0"
2839 [(set_attr "type" "fdiv")
2840 (set_attr "trap" "yes")
2841 (set_attr "round_suffix" "normal")
2842 (set_attr "trap_suffix" "u_su_sui")])
2844 (define_insn "*divdf_ext2"
2845 [(set (match_operand:DF 0 "register_operand" "=f")
2846 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2848 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2849 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2850 "div%-%/ %R1,%R2,%0"
2851 [(set_attr "type" "fdiv")
2852 (set_attr "trap" "yes")
2853 (set_attr "round_suffix" "normal")
2854 (set_attr "trap_suffix" "u_su_sui")])
2856 (define_insn "*divdf_ext3"
2857 [(set (match_operand:DF 0 "register_operand" "=f")
2858 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2859 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2860 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2861 "div%-%/ %R1,%R2,%0"
2862 [(set_attr "type" "fdiv")
2863 (set_attr "trap" "yes")
2864 (set_attr "round_suffix" "normal")
2865 (set_attr "trap_suffix" "u_su_sui")])
2867 (define_expand "divtf3"
2868 [(use (match_operand 0 "register_operand" ""))
2869 (use (match_operand 1 "general_operand" ""))
2870 (use (match_operand 2 "general_operand" ""))]
2871 "TARGET_HAS_XFLOATING_LIBS"
2872 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2874 (define_insn "*mulsf3_ieee"
2875 [(set (match_operand:SF 0 "register_operand" "=&f")
2876 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2877 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2878 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2879 "mul%,%/ %R1,%R2,%0"
2880 [(set_attr "type" "fmul")
2881 (set_attr "trap" "yes")
2882 (set_attr "round_suffix" "normal")
2883 (set_attr "trap_suffix" "u_su_sui")])
2885 (define_insn "mulsf3"
2886 [(set (match_operand:SF 0 "register_operand" "=f")
2887 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2888 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2890 "mul%,%/ %R1,%R2,%0"
2891 [(set_attr "type" "fmul")
2892 (set_attr "trap" "yes")
2893 (set_attr "round_suffix" "normal")
2894 (set_attr "trap_suffix" "u_su_sui")])
2896 (define_insn "*muldf3_ieee"
2897 [(set (match_operand:DF 0 "register_operand" "=&f")
2898 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2899 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2900 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2901 "mul%-%/ %R1,%R2,%0"
2902 [(set_attr "type" "fmul")
2903 (set_attr "trap" "yes")
2904 (set_attr "round_suffix" "normal")
2905 (set_attr "trap_suffix" "u_su_sui")])
2907 (define_insn "muldf3"
2908 [(set (match_operand:DF 0 "register_operand" "=f")
2909 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2910 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2912 "mul%-%/ %R1,%R2,%0"
2913 [(set_attr "type" "fmul")
2914 (set_attr "trap" "yes")
2915 (set_attr "round_suffix" "normal")
2916 (set_attr "trap_suffix" "u_su_sui")])
2918 (define_insn "*muldf_ext1"
2919 [(set (match_operand:DF 0 "register_operand" "=f")
2920 (mult:DF (float_extend:DF
2921 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2922 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2923 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2924 "mul%-%/ %R1,%R2,%0"
2925 [(set_attr "type" "fmul")
2926 (set_attr "trap" "yes")
2927 (set_attr "round_suffix" "normal")
2928 (set_attr "trap_suffix" "u_su_sui")])
2930 (define_insn "*muldf_ext2"
2931 [(set (match_operand:DF 0 "register_operand" "=f")
2932 (mult:DF (float_extend:DF
2933 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2935 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2936 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2937 "mul%-%/ %R1,%R2,%0"
2938 [(set_attr "type" "fmul")
2939 (set_attr "trap" "yes")
2940 (set_attr "round_suffix" "normal")
2941 (set_attr "trap_suffix" "u_su_sui")])
2943 (define_expand "multf3"
2944 [(use (match_operand 0 "register_operand" ""))
2945 (use (match_operand 1 "general_operand" ""))
2946 (use (match_operand 2 "general_operand" ""))]
2947 "TARGET_HAS_XFLOATING_LIBS"
2948 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2950 (define_insn "*subsf3_ieee"
2951 [(set (match_operand:SF 0 "register_operand" "=&f")
2952 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2953 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2954 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2955 "sub%,%/ %R1,%R2,%0"
2956 [(set_attr "type" "fadd")
2957 (set_attr "trap" "yes")
2958 (set_attr "round_suffix" "normal")
2959 (set_attr "trap_suffix" "u_su_sui")])
2961 (define_insn "subsf3"
2962 [(set (match_operand:SF 0 "register_operand" "=f")
2963 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2964 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2966 "sub%,%/ %R1,%R2,%0"
2967 [(set_attr "type" "fadd")
2968 (set_attr "trap" "yes")
2969 (set_attr "round_suffix" "normal")
2970 (set_attr "trap_suffix" "u_su_sui")])
2972 (define_insn "*subdf3_ieee"
2973 [(set (match_operand:DF 0 "register_operand" "=&f")
2974 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2975 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2976 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2977 "sub%-%/ %R1,%R2,%0"
2978 [(set_attr "type" "fadd")
2979 (set_attr "trap" "yes")
2980 (set_attr "round_suffix" "normal")
2981 (set_attr "trap_suffix" "u_su_sui")])
2983 (define_insn "subdf3"
2984 [(set (match_operand:DF 0 "register_operand" "=f")
2985 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2986 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2988 "sub%-%/ %R1,%R2,%0"
2989 [(set_attr "type" "fadd")
2990 (set_attr "trap" "yes")
2991 (set_attr "round_suffix" "normal")
2992 (set_attr "trap_suffix" "u_su_sui")])
2994 (define_insn "*subdf_ext1"
2995 [(set (match_operand:DF 0 "register_operand" "=f")
2996 (minus:DF (float_extend:DF
2997 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2998 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2999 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3000 "sub%-%/ %R1,%R2,%0"
3001 [(set_attr "type" "fadd")
3002 (set_attr "trap" "yes")
3003 (set_attr "round_suffix" "normal")
3004 (set_attr "trap_suffix" "u_su_sui")])
3006 (define_insn "*subdf_ext2"
3007 [(set (match_operand:DF 0 "register_operand" "=f")
3008 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
3010 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3011 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3012 "sub%-%/ %R1,%R2,%0"
3013 [(set_attr "type" "fadd")
3014 (set_attr "trap" "yes")
3015 (set_attr "round_suffix" "normal")
3016 (set_attr "trap_suffix" "u_su_sui")])
3018 (define_insn "*subdf_ext3"
3019 [(set (match_operand:DF 0 "register_operand" "=f")
3020 (minus:DF (float_extend:DF
3021 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
3023 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
3024 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3025 "sub%-%/ %R1,%R2,%0"
3026 [(set_attr "type" "fadd")
3027 (set_attr "trap" "yes")
3028 (set_attr "round_suffix" "normal")
3029 (set_attr "trap_suffix" "u_su_sui")])
3031 (define_expand "subtf3"
3032 [(use (match_operand 0 "register_operand" ""))
3033 (use (match_operand 1 "general_operand" ""))
3034 (use (match_operand 2 "general_operand" ""))]
3035 "TARGET_HAS_XFLOATING_LIBS"
3036 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3038 (define_insn "*sqrtsf2_ieee"
3039 [(set (match_operand:SF 0 "register_operand" "=&f")
3040 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3041 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3043 [(set_attr "type" "fsqrt")
3044 (set_attr "opsize" "si")
3045 (set_attr "trap" "yes")
3046 (set_attr "round_suffix" "normal")
3047 (set_attr "trap_suffix" "u_su_sui")])
3049 (define_insn "sqrtsf2"
3050 [(set (match_operand:SF 0 "register_operand" "=f")
3051 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
3052 "TARGET_FP && TARGET_FIX"
3054 [(set_attr "type" "fsqrt")
3055 (set_attr "opsize" "si")
3056 (set_attr "trap" "yes")
3057 (set_attr "round_suffix" "normal")
3058 (set_attr "trap_suffix" "u_su_sui")])
3060 (define_insn "*sqrtdf2_ieee"
3061 [(set (match_operand:DF 0 "register_operand" "=&f")
3062 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3063 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3065 [(set_attr "type" "fsqrt")
3066 (set_attr "trap" "yes")
3067 (set_attr "round_suffix" "normal")
3068 (set_attr "trap_suffix" "u_su_sui")])
3070 (define_insn "sqrtdf2"
3071 [(set (match_operand:DF 0 "register_operand" "=f")
3072 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3073 "TARGET_FP && TARGET_FIX"
3075 [(set_attr "type" "fsqrt")
3076 (set_attr "trap" "yes")
3077 (set_attr "round_suffix" "normal")
3078 (set_attr "trap_suffix" "u_su_sui")])
3080 ;; Next are all the integer comparisons, and conditional moves and branches
3081 ;; and some of the related define_expand's and define_split's.
3083 (define_insn "*setcc_internal"
3084 [(set (match_operand 0 "register_operand" "=r")
3085 (match_operator 1 "alpha_comparison_operator"
3086 [(match_operand:DI 2 "register_operand" "r")
3087 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3088 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3089 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3090 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3092 [(set_attr "type" "icmp")])
3094 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3095 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3097 (define_insn "*setcc_swapped_internal"
3098 [(set (match_operand 0 "register_operand" "=r")
3099 (match_operator 1 "alpha_swapped_comparison_operator"
3100 [(match_operand:DI 2 "register_operand" "r")
3101 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3102 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3103 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3104 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3106 [(set_attr "type" "icmp")])
3108 ;; Use match_operator rather than ne directly so that we can match
3109 ;; multiple integer modes.
3110 (define_insn "*setne_internal"
3111 [(set (match_operand 0 "register_operand" "=r")
3112 (match_operator 1 "signed_comparison_operator"
3113 [(match_operand:DI 2 "register_operand" "r")
3115 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3116 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3117 && GET_CODE (operands[1]) == NE
3118 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3120 [(set_attr "type" "icmp")])
3122 ;; The mode folding trick can't be used with const_int operands, since
3123 ;; reload needs to know the proper mode.
3125 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3126 ;; in order to create more pairs of constants. As long as we're allowing
3127 ;; two constants at the same time, and will have to reload one of them...
3129 (define_insn "*movqicc_internal"
3130 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3132 (match_operator 2 "signed_comparison_operator"
3133 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3134 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3135 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3136 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3137 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3143 [(set_attr "type" "icmov")])
3145 (define_insn "*movhicc_internal"
3146 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3148 (match_operator 2 "signed_comparison_operator"
3149 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3150 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3151 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3152 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3153 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3159 [(set_attr "type" "icmov")])
3161 (define_insn "*movsicc_internal"
3162 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3164 (match_operator 2 "signed_comparison_operator"
3165 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3166 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3167 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3168 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3169 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3175 [(set_attr "type" "icmov")])
3177 (define_insn "*movdicc_internal"
3178 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3180 (match_operator 2 "signed_comparison_operator"
3181 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3182 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3183 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3184 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3185 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3191 [(set_attr "type" "icmov")])
3193 (define_insn "*movqicc_lbc"
3194 [(set (match_operand:QI 0 "register_operand" "=r,r")
3196 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3200 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3201 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3206 [(set_attr "type" "icmov")])
3208 (define_insn "*movhicc_lbc"
3209 [(set (match_operand:HI 0 "register_operand" "=r,r")
3211 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3215 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3216 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3221 [(set_attr "type" "icmov")])
3223 (define_insn "*movsicc_lbc"
3224 [(set (match_operand:SI 0 "register_operand" "=r,r")
3226 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3230 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3231 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3236 [(set_attr "type" "icmov")])
3238 (define_insn "*movdicc_lbc"
3239 [(set (match_operand:DI 0 "register_operand" "=r,r")
3241 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3245 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3246 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3251 [(set_attr "type" "icmov")])
3253 (define_insn "*movqicc_lbs"
3254 [(set (match_operand:QI 0 "register_operand" "=r,r")
3256 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3260 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3261 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3266 [(set_attr "type" "icmov")])
3268 (define_insn "*movhicc_lbs"
3269 [(set (match_operand:HI 0 "register_operand" "=r,r")
3271 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3275 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3276 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3281 [(set_attr "type" "icmov")])
3283 (define_insn "*movsicc_lbs"
3284 [(set (match_operand:SI 0 "register_operand" "=r,r")
3286 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3290 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3291 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3296 [(set_attr "type" "icmov")])
3298 (define_insn "*movdicc_lbs"
3299 [(set (match_operand:DI 0 "register_operand" "=r,r")
3301 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3305 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3306 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3311 [(set_attr "type" "icmov")])
3313 ;; For ABS, we have two choices, depending on whether the input and output
3314 ;; registers are the same or not.
3315 (define_expand "absdi2"
3316 [(set (match_operand:DI 0 "register_operand" "")
3317 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3320 if (rtx_equal_p (operands[0], operands[1]))
3321 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3323 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3327 (define_expand "absdi2_same"
3328 [(set (match_operand:DI 1 "register_operand" "")
3329 (neg:DI (match_operand:DI 0 "register_operand" "")))
3331 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3337 (define_expand "absdi2_diff"
3338 [(set (match_operand:DI 0 "register_operand" "")
3339 (neg:DI (match_operand:DI 1 "register_operand" "")))
3341 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3348 [(set (match_operand:DI 0 "register_operand" "")
3349 (abs:DI (match_dup 0)))
3350 (clobber (match_operand:DI 1 "register_operand" ""))]
3352 [(set (match_dup 1) (neg:DI (match_dup 0)))
3353 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3354 (match_dup 0) (match_dup 1)))]
3358 [(set (match_operand:DI 0 "register_operand" "")
3359 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3360 "! rtx_equal_p (operands[0], operands[1])"
3361 [(set (match_dup 0) (neg:DI (match_dup 1)))
3362 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3363 (match_dup 0) (match_dup 1)))]
3367 [(set (match_operand:DI 0 "register_operand" "")
3368 (neg:DI (abs:DI (match_dup 0))))
3369 (clobber (match_operand:DI 1 "register_operand" ""))]
3371 [(set (match_dup 1) (neg:DI (match_dup 0)))
3372 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3373 (match_dup 0) (match_dup 1)))]
3377 [(set (match_operand:DI 0 "register_operand" "")
3378 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3379 "! rtx_equal_p (operands[0], operands[1])"
3380 [(set (match_dup 0) (neg:DI (match_dup 1)))
3381 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3382 (match_dup 0) (match_dup 1)))]
3385 (define_insn "sminqi3"
3386 [(set (match_operand:QI 0 "register_operand" "=r")
3387 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3388 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3391 [(set_attr "type" "mvi")])
3393 (define_insn "uminqi3"
3394 [(set (match_operand:QI 0 "register_operand" "=r")
3395 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3396 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3399 [(set_attr "type" "mvi")])
3401 (define_insn "smaxqi3"
3402 [(set (match_operand:QI 0 "register_operand" "=r")
3403 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3404 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3407 [(set_attr "type" "mvi")])
3409 (define_insn "umaxqi3"
3410 [(set (match_operand:QI 0 "register_operand" "=r")
3411 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3412 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3415 [(set_attr "type" "mvi")])
3417 (define_insn "sminhi3"
3418 [(set (match_operand:HI 0 "register_operand" "=r")
3419 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3420 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3423 [(set_attr "type" "mvi")])
3425 (define_insn "uminhi3"
3426 [(set (match_operand:HI 0 "register_operand" "=r")
3427 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3428 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3431 [(set_attr "type" "mvi")])
3433 (define_insn "smaxhi3"
3434 [(set (match_operand:HI 0 "register_operand" "=r")
3435 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3436 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3439 [(set_attr "type" "mvi")])
3441 (define_insn "umaxhi3"
3442 [(set (match_operand:HI 0 "register_operand" "=r")
3443 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3444 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3447 [(set_attr "type" "shift")])
3449 (define_expand "smaxdi3"
3451 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3452 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3453 (set (match_operand:DI 0 "register_operand" "")
3454 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3455 (match_dup 1) (match_dup 2)))]
3457 { operands[3] = gen_reg_rtx (DImode); })
3460 [(set (match_operand:DI 0 "register_operand" "")
3461 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3462 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3463 (clobber (match_operand:DI 3 "register_operand" ""))]
3464 "operands[2] != const0_rtx"
3465 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3466 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3467 (match_dup 1) (match_dup 2)))]
3470 (define_insn "*smax_const0"
3471 [(set (match_operand:DI 0 "register_operand" "=r")
3472 (smax:DI (match_operand:DI 1 "register_operand" "0")
3476 [(set_attr "type" "icmov")])
3478 (define_expand "smindi3"
3480 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3481 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3482 (set (match_operand:DI 0 "register_operand" "")
3483 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3484 (match_dup 1) (match_dup 2)))]
3486 { operands[3] = gen_reg_rtx (DImode); })
3489 [(set (match_operand:DI 0 "register_operand" "")
3490 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3491 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3492 (clobber (match_operand:DI 3 "register_operand" ""))]
3493 "operands[2] != const0_rtx"
3494 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3495 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3496 (match_dup 1) (match_dup 2)))]
3499 (define_insn "*smin_const0"
3500 [(set (match_operand:DI 0 "register_operand" "=r")
3501 (smin:DI (match_operand:DI 1 "register_operand" "0")
3505 [(set_attr "type" "icmov")])
3507 (define_expand "umaxdi3"
3509 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3510 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3511 (set (match_operand:DI 0 "register_operand" "")
3512 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3513 (match_dup 1) (match_dup 2)))]
3515 "operands[3] = gen_reg_rtx (DImode);")
3518 [(set (match_operand:DI 0 "register_operand" "")
3519 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3520 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3521 (clobber (match_operand:DI 3 "register_operand" ""))]
3522 "operands[2] != const0_rtx"
3523 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3524 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3525 (match_dup 1) (match_dup 2)))]
3528 (define_expand "umindi3"
3530 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3531 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3532 (set (match_operand:DI 0 "register_operand" "")
3533 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3534 (match_dup 1) (match_dup 2)))]
3536 "operands[3] = gen_reg_rtx (DImode);")
3539 [(set (match_operand:DI 0 "register_operand" "")
3540 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3541 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3542 (clobber (match_operand:DI 3 "register_operand" ""))]
3543 "operands[2] != const0_rtx"
3544 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3545 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3546 (match_dup 1) (match_dup 2)))]
3549 (define_insn "*bcc_normal"
3552 (match_operator 1 "signed_comparison_operator"
3553 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3555 (label_ref (match_operand 0 "" ""))
3559 [(set_attr "type" "ibr")])
3561 (define_insn "*bcc_reverse"
3564 (match_operator 1 "signed_comparison_operator"
3565 [(match_operand:DI 2 "register_operand" "r")
3569 (label_ref (match_operand 0 "" ""))))]
3572 [(set_attr "type" "ibr")])
3574 (define_insn "*blbs_normal"
3577 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3581 (label_ref (match_operand 0 "" ""))
3585 [(set_attr "type" "ibr")])
3587 (define_insn "*blbc_normal"
3590 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3594 (label_ref (match_operand 0 "" ""))
3598 [(set_attr "type" "ibr")])
3604 (match_operator 1 "comparison_operator"
3605 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3607 (match_operand:DI 3 "const_int_operand" ""))
3609 (label_ref (match_operand 0 "" ""))
3611 (clobber (match_operand:DI 4 "register_operand" ""))])]
3612 "INTVAL (operands[3]) != 0"
3614 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3616 (if_then_else (match_op_dup 1
3617 [(zero_extract:DI (match_dup 4)
3621 (label_ref (match_dup 0))
3625 ;; The following are the corresponding floating-point insns. Recall
3626 ;; we need to have variants that expand the arguments from SFmode
3629 (define_insn "*cmpdf_ieee"
3630 [(set (match_operand:DF 0 "register_operand" "=&f")
3631 (match_operator:DF 1 "alpha_fp_comparison_operator"
3632 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3633 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3634 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3635 "cmp%-%C1%/ %R2,%R3,%0"
3636 [(set_attr "type" "fadd")
3637 (set_attr "trap" "yes")
3638 (set_attr "trap_suffix" "su")])
3640 (define_insn "*cmpdf_internal"
3641 [(set (match_operand:DF 0 "register_operand" "=f")
3642 (match_operator:DF 1 "alpha_fp_comparison_operator"
3643 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3644 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3645 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3646 "cmp%-%C1%/ %R2,%R3,%0"
3647 [(set_attr "type" "fadd")
3648 (set_attr "trap" "yes")
3649 (set_attr "trap_suffix" "su")])
3651 (define_insn "*cmpdf_ieee_ext1"
3652 [(set (match_operand:DF 0 "register_operand" "=&f")
3653 (match_operator:DF 1 "alpha_fp_comparison_operator"
3655 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3656 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3657 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3658 "cmp%-%C1%/ %R2,%R3,%0"
3659 [(set_attr "type" "fadd")
3660 (set_attr "trap" "yes")
3661 (set_attr "trap_suffix" "su")])
3663 (define_insn "*cmpdf_ext1"
3664 [(set (match_operand:DF 0 "register_operand" "=f")
3665 (match_operator:DF 1 "alpha_fp_comparison_operator"
3667 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3668 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3669 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3670 "cmp%-%C1%/ %R2,%R3,%0"
3671 [(set_attr "type" "fadd")
3672 (set_attr "trap" "yes")
3673 (set_attr "trap_suffix" "su")])
3675 (define_insn "*cmpdf_ieee_ext2"
3676 [(set (match_operand:DF 0 "register_operand" "=&f")
3677 (match_operator:DF 1 "alpha_fp_comparison_operator"
3678 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3680 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3681 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3682 "cmp%-%C1%/ %R2,%R3,%0"
3683 [(set_attr "type" "fadd")
3684 (set_attr "trap" "yes")
3685 (set_attr "trap_suffix" "su")])
3687 (define_insn "*cmpdf_ext2"
3688 [(set (match_operand:DF 0 "register_operand" "=f")
3689 (match_operator:DF 1 "alpha_fp_comparison_operator"
3690 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3692 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3693 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3694 "cmp%-%C1%/ %R2,%R3,%0"
3695 [(set_attr "type" "fadd")
3696 (set_attr "trap" "yes")
3697 (set_attr "trap_suffix" "su")])
3699 (define_insn "*cmpdf_ieee_ext3"
3700 [(set (match_operand:DF 0 "register_operand" "=&f")
3701 (match_operator:DF 1 "alpha_fp_comparison_operator"
3703 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3705 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3706 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3707 "cmp%-%C1%/ %R2,%R3,%0"
3708 [(set_attr "type" "fadd")
3709 (set_attr "trap" "yes")
3710 (set_attr "trap_suffix" "su")])
3712 (define_insn "*cmpdf_ext3"
3713 [(set (match_operand:DF 0 "register_operand" "=f")
3714 (match_operator:DF 1 "alpha_fp_comparison_operator"
3716 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3718 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3719 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3720 "cmp%-%C1%/ %R2,%R3,%0"
3721 [(set_attr "type" "fadd")
3722 (set_attr "trap" "yes")
3723 (set_attr "trap_suffix" "su")])
3725 (define_insn "*movdfcc_internal"
3726 [(set (match_operand:DF 0 "register_operand" "=f,f")
3728 (match_operator 3 "signed_comparison_operator"
3729 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3730 (match_operand:DF 2 "fp0_operand" "G,G")])
3731 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3732 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3736 fcmov%D3 %R4,%R5,%0"
3737 [(set_attr "type" "fcmov")])
3739 (define_insn "*movsfcc_internal"
3740 [(set (match_operand:SF 0 "register_operand" "=f,f")
3742 (match_operator 3 "signed_comparison_operator"
3743 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3744 (match_operand:DF 2 "fp0_operand" "G,G")])
3745 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3746 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3750 fcmov%D3 %R4,%R5,%0"
3751 [(set_attr "type" "fcmov")])
3753 (define_insn "*movdfcc_ext1"
3754 [(set (match_operand:DF 0 "register_operand" "=f,f")
3756 (match_operator 3 "signed_comparison_operator"
3757 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3758 (match_operand:DF 2 "fp0_operand" "G,G")])
3759 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3760 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3764 fcmov%D3 %R4,%R5,%0"
3765 [(set_attr "type" "fcmov")])
3767 (define_insn "*movdfcc_ext2"
3768 [(set (match_operand:DF 0 "register_operand" "=f,f")
3770 (match_operator 3 "signed_comparison_operator"
3772 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3773 (match_operand:DF 2 "fp0_operand" "G,G")])
3774 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3775 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3779 fcmov%D3 %R4,%R5,%0"
3780 [(set_attr "type" "fcmov")])
3782 (define_insn "*movdfcc_ext3"
3783 [(set (match_operand:SF 0 "register_operand" "=f,f")
3785 (match_operator 3 "signed_comparison_operator"
3787 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3788 (match_operand:DF 2 "fp0_operand" "G,G")])
3789 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3790 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3794 fcmov%D3 %R4,%R5,%0"
3795 [(set_attr "type" "fcmov")])
3797 (define_insn "*movdfcc_ext4"
3798 [(set (match_operand:DF 0 "register_operand" "=f,f")
3800 (match_operator 3 "signed_comparison_operator"
3802 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3803 (match_operand:DF 2 "fp0_operand" "G,G")])
3804 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3805 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3809 fcmov%D3 %R4,%R5,%0"
3810 [(set_attr "type" "fcmov")])
3812 (define_expand "maxdf3"
3814 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3815 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3816 (set (match_operand:DF 0 "register_operand" "")
3817 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3818 (match_dup 1) (match_dup 2)))]
3821 operands[3] = gen_reg_rtx (DFmode);
3822 operands[4] = CONST0_RTX (DFmode);
3825 (define_expand "mindf3"
3827 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3828 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3829 (set (match_operand:DF 0 "register_operand" "")
3830 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3831 (match_dup 1) (match_dup 2)))]
3834 operands[3] = gen_reg_rtx (DFmode);
3835 operands[4] = CONST0_RTX (DFmode);
3838 (define_expand "maxsf3"
3840 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3841 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3842 (set (match_operand:SF 0 "register_operand" "")
3843 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3844 (match_dup 1) (match_dup 2)))]
3847 operands[3] = gen_reg_rtx (DFmode);
3848 operands[4] = CONST0_RTX (DFmode);
3851 (define_expand "minsf3"
3853 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3854 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3855 (set (match_operand:SF 0 "register_operand" "")
3856 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3857 (match_dup 1) (match_dup 2)))]
3860 operands[3] = gen_reg_rtx (DFmode);
3861 operands[4] = CONST0_RTX (DFmode);
3864 (define_insn "*fbcc_normal"
3867 (match_operator 1 "signed_comparison_operator"
3868 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3869 (match_operand:DF 3 "fp0_operand" "G")])
3870 (label_ref (match_operand 0 "" ""))
3874 [(set_attr "type" "fbr")])
3876 (define_insn "*fbcc_ext_normal"
3879 (match_operator 1 "signed_comparison_operator"
3881 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3882 (match_operand:DF 3 "fp0_operand" "G")])
3883 (label_ref (match_operand 0 "" ""))
3887 [(set_attr "type" "fbr")])
3889 ;; These are the main define_expand's used to make conditional branches
3892 (define_expand "cmpdf"
3893 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3894 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3897 alpha_compare.op0 = operands[0];
3898 alpha_compare.op1 = operands[1];
3899 alpha_compare.fp_p = 1;
3903 (define_expand "cmptf"
3904 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3905 (match_operand:TF 1 "general_operand" "")))]
3906 "TARGET_HAS_XFLOATING_LIBS"
3908 alpha_compare.op0 = operands[0];
3909 alpha_compare.op1 = operands[1];
3910 alpha_compare.fp_p = 1;
3914 (define_expand "cmpdi"
3915 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3916 (match_operand:DI 1 "general_operand" "")))]
3919 alpha_compare.op0 = operands[0];
3920 alpha_compare.op1 = operands[1];
3921 alpha_compare.fp_p = 0;
3925 (define_expand "beq"
3927 (if_then_else (match_dup 1)
3928 (label_ref (match_operand 0 "" ""))
3931 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3933 (define_expand "bne"
3935 (if_then_else (match_dup 1)
3936 (label_ref (match_operand 0 "" ""))
3939 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3941 (define_expand "blt"
3943 (if_then_else (match_dup 1)
3944 (label_ref (match_operand 0 "" ""))
3947 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3949 (define_expand "ble"
3951 (if_then_else (match_dup 1)
3952 (label_ref (match_operand 0 "" ""))
3955 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3957 (define_expand "bgt"
3959 (if_then_else (match_dup 1)
3960 (label_ref (match_operand 0 "" ""))
3963 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3965 (define_expand "bge"
3967 (if_then_else (match_dup 1)
3968 (label_ref (match_operand 0 "" ""))
3971 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3973 (define_expand "bltu"
3975 (if_then_else (match_dup 1)
3976 (label_ref (match_operand 0 "" ""))
3979 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3981 (define_expand "bleu"
3983 (if_then_else (match_dup 1)
3984 (label_ref (match_operand 0 "" ""))
3987 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3989 (define_expand "bgtu"
3991 (if_then_else (match_dup 1)
3992 (label_ref (match_operand 0 "" ""))
3995 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3997 (define_expand "bgeu"
3999 (if_then_else (match_dup 1)
4000 (label_ref (match_operand 0 "" ""))
4003 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4005 (define_expand "bunordered"
4007 (if_then_else (match_dup 1)
4008 (label_ref (match_operand 0 "" ""))
4011 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4013 (define_expand "bordered"
4015 (if_then_else (match_dup 1)
4016 (label_ref (match_operand 0 "" ""))
4019 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4021 (define_expand "seq"
4022 [(set (match_operand:DI 0 "register_operand" "")
4025 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4027 (define_expand "sne"
4028 [(set (match_operand:DI 0 "register_operand" "")
4031 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4033 (define_expand "slt"
4034 [(set (match_operand:DI 0 "register_operand" "")
4037 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4039 (define_expand "sle"
4040 [(set (match_operand:DI 0 "register_operand" "")
4043 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4045 (define_expand "sgt"
4046 [(set (match_operand:DI 0 "register_operand" "")
4049 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4051 (define_expand "sge"
4052 [(set (match_operand:DI 0 "register_operand" "")
4055 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4057 (define_expand "sltu"
4058 [(set (match_operand:DI 0 "register_operand" "")
4061 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4063 (define_expand "sleu"
4064 [(set (match_operand:DI 0 "register_operand" "")
4067 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4069 (define_expand "sgtu"
4070 [(set (match_operand:DI 0 "register_operand" "")
4073 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4075 (define_expand "sgeu"
4076 [(set (match_operand:DI 0 "register_operand" "")
4079 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4081 (define_expand "sunordered"
4082 [(set (match_operand:DI 0 "register_operand" "")
4085 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4087 (define_expand "sordered"
4088 [(set (match_operand:DI 0 "register_operand" "")
4091 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4093 ;; These are the main define_expand's used to make conditional moves.
4095 (define_expand "movsicc"
4096 [(set (match_operand:SI 0 "register_operand" "")
4097 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4098 (match_operand:SI 2 "reg_or_8bit_operand" "")
4099 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4102 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4106 (define_expand "movdicc"
4107 [(set (match_operand:DI 0 "register_operand" "")
4108 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4109 (match_operand:DI 2 "reg_or_8bit_operand" "")
4110 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4113 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4117 (define_expand "movsfcc"
4118 [(set (match_operand:SF 0 "register_operand" "")
4119 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4120 (match_operand:SF 2 "reg_or_8bit_operand" "")
4121 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4124 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4128 (define_expand "movdfcc"
4129 [(set (match_operand:DF 0 "register_operand" "")
4130 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4131 (match_operand:DF 2 "reg_or_8bit_operand" "")
4132 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4135 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4139 ;; These define_split definitions are used in cases when comparisons have
4140 ;; not be stated in the correct way and we need to reverse the second
4141 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4142 ;; comparison that tests the result being reversed. We have one define_split
4143 ;; for each use of a comparison. They do not match valid insns and need
4144 ;; not generate valid insns.
4146 ;; We can also handle equality comparisons (and inequality comparisons in
4147 ;; cases where the resulting add cannot overflow) by doing an add followed by
4148 ;; a comparison with zero. This is faster since the addition takes one
4149 ;; less cycle than a compare when feeding into a conditional move.
4150 ;; For this case, we also have an SImode pattern since we can merge the add
4151 ;; and sign extend and the order doesn't matter.
4153 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4154 ;; operation could have been generated.
4157 [(set (match_operand:DI 0 "register_operand" "")
4159 (match_operator 1 "comparison_operator"
4160 [(match_operand:DI 2 "reg_or_0_operand" "")
4161 (match_operand:DI 3 "reg_or_cint_operand" "")])
4162 (match_operand:DI 4 "reg_or_cint_operand" "")
4163 (match_operand:DI 5 "reg_or_cint_operand" "")))
4164 (clobber (match_operand:DI 6 "register_operand" ""))]
4165 "operands[3] != const0_rtx"
4166 [(set (match_dup 6) (match_dup 7))
4168 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4170 enum rtx_code code = GET_CODE (operands[1]);
4171 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4173 /* If we are comparing for equality with a constant and that constant
4174 appears in the arm when the register equals the constant, use the
4175 register since that is more likely to match (and to produce better code
4178 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4179 && rtx_equal_p (operands[4], operands[3]))
4180 operands[4] = operands[2];
4182 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4183 && rtx_equal_p (operands[5], operands[3]))
4184 operands[5] = operands[2];
4186 if (code == NE || code == EQ
4187 || (extended_count (operands[2], DImode, unsignedp) >= 1
4188 && extended_count (operands[3], DImode, unsignedp) >= 1))
4190 if (GET_CODE (operands[3]) == CONST_INT)
4191 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4192 GEN_INT (- INTVAL (operands[3])));
4194 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4196 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4199 else if (code == EQ || code == LE || code == LT
4200 || code == LEU || code == LTU)
4202 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4203 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4207 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4208 operands[2], operands[3]);
4209 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4214 [(set (match_operand:DI 0 "register_operand" "")
4216 (match_operator 1 "comparison_operator"
4217 [(match_operand:SI 2 "reg_or_0_operand" "")
4218 (match_operand:SI 3 "reg_or_cint_operand" "")])
4219 (match_operand:DI 4 "reg_or_8bit_operand" "")
4220 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4221 (clobber (match_operand:DI 6 "register_operand" ""))]
4222 "operands[3] != const0_rtx
4223 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4224 [(set (match_dup 6) (match_dup 7))
4226 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4228 enum rtx_code code = GET_CODE (operands[1]);
4229 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4232 if ((code != NE && code != EQ
4233 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4234 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4237 if (GET_CODE (operands[3]) == CONST_INT)
4238 tem = gen_rtx_PLUS (SImode, operands[2],
4239 GEN_INT (- INTVAL (operands[3])));
4241 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4243 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4244 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4245 operands[6], const0_rtx);
4251 (match_operator 1 "comparison_operator"
4252 [(match_operand:DI 2 "reg_or_0_operand" "")
4253 (match_operand:DI 3 "reg_or_cint_operand" "")])
4254 (label_ref (match_operand 0 "" ""))
4256 (clobber (match_operand:DI 4 "register_operand" ""))]
4257 "operands[3] != const0_rtx"
4258 [(set (match_dup 4) (match_dup 5))
4259 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4261 enum rtx_code code = GET_CODE (operands[1]);
4262 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4264 if (code == NE || code == EQ
4265 || (extended_count (operands[2], DImode, unsignedp) >= 1
4266 && extended_count (operands[3], DImode, unsignedp) >= 1))
4268 if (GET_CODE (operands[3]) == CONST_INT)
4269 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4270 GEN_INT (- INTVAL (operands[3])));
4272 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4274 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4277 else if (code == EQ || code == LE || code == LT
4278 || code == LEU || code == LTU)
4280 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4281 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4285 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4286 operands[2], operands[3]);
4287 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4294 (match_operator 1 "comparison_operator"
4295 [(match_operand:SI 2 "reg_or_0_operand" "")
4296 (match_operand:SI 3 "const_int_operand" "")])
4297 (label_ref (match_operand 0 "" ""))
4299 (clobber (match_operand:DI 4 "register_operand" ""))]
4300 "operands[3] != const0_rtx
4301 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4302 [(set (match_dup 4) (match_dup 5))
4303 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4307 if (GET_CODE (operands[3]) == CONST_INT)
4308 tem = gen_rtx_PLUS (SImode, operands[2],
4309 GEN_INT (- INTVAL (operands[3])));
4311 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4313 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4314 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4315 operands[4], const0_rtx);
4318 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4319 ;; This eliminates one, and sometimes two, insns when the AND can be done
4322 [(set (match_operand:DI 0 "register_operand" "")
4323 (match_operator:DI 1 "comparison_operator"
4324 [(match_operand:DI 2 "register_operand" "")
4325 (match_operand:DI 3 "const_int_operand" "")]))
4326 (clobber (match_operand:DI 4 "register_operand" ""))]
4327 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4328 && (GET_CODE (operands[1]) == GTU
4329 || GET_CODE (operands[1]) == LEU
4330 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4331 && extended_count (operands[2], DImode, 1) > 0))"
4332 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4333 (set (match_dup 0) (match_dup 6))]
4335 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4336 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4337 || GET_CODE (operands[1]) == GT)
4339 DImode, operands[4], const0_rtx);
4342 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4345 [(set (match_operand 0 "register_operand" "")
4346 (if_then_else (match_operator 1 "signed_comparison_operator"
4347 [(match_operand:DI 2 "reg_or_0_operand" "")
4349 (match_operand 3 "const_int_operand" "")
4350 (match_operand 4 "const_int_operand" "")))]
4354 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4355 operands[2], operands[3], operands[4]))
4361 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4362 ;; Oh well, we match it in movcc, so it must be partially our fault.
4364 [(set (match_operand 0 "register_operand" "")
4365 (if_then_else (match_operator 1 "signed_comparison_operator"
4367 (match_operand:DI 2 "reg_or_0_operand" "")])
4368 (match_operand 3 "const_int_operand" "")
4369 (match_operand 4 "const_int_operand" "")))]
4373 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4374 operands[0], operands[2], operands[3],
4381 (define_insn_and_split "*cmp_sadd_di"
4382 [(set (match_operand:DI 0 "register_operand" "=r")
4383 (plus:DI (if_then_else:DI
4384 (match_operator 1 "alpha_zero_comparison_operator"
4385 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4387 (match_operand:DI 3 "const48_operand" "I")
4389 (match_operand:DI 4 "sext_add_operand" "rIO")))
4390 (clobber (match_scratch:DI 5 "=r"))]
4393 "! no_new_pseudos || reload_completed"
4395 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4397 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4400 if (! no_new_pseudos)
4401 operands[5] = gen_reg_rtx (DImode);
4402 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4403 operands[5] = operands[0];
4406 (define_insn_and_split "*cmp_sadd_si"
4407 [(set (match_operand:SI 0 "register_operand" "=r")
4408 (plus:SI (if_then_else:SI
4409 (match_operator 1 "alpha_zero_comparison_operator"
4410 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4412 (match_operand:SI 3 "const48_operand" "I")
4414 (match_operand:SI 4 "sext_add_operand" "rIO")))
4415 (clobber (match_scratch:SI 5 "=r"))]
4418 "! no_new_pseudos || reload_completed"
4420 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4422 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4425 if (! no_new_pseudos)
4426 operands[5] = gen_reg_rtx (DImode);
4427 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4428 operands[5] = operands[0];
4431 (define_insn_and_split "*cmp_sadd_sidi"
4432 [(set (match_operand:DI 0 "register_operand" "=r")
4434 (plus:SI (if_then_else:SI
4435 (match_operator 1 "alpha_zero_comparison_operator"
4436 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4438 (match_operand:SI 3 "const48_operand" "I")
4440 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4441 (clobber (match_scratch:SI 5 "=r"))]
4444 "! no_new_pseudos || reload_completed"
4446 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4448 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4451 if (! no_new_pseudos)
4452 operands[5] = gen_reg_rtx (DImode);
4453 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4454 operands[5] = operands[0];
4457 (define_insn_and_split "*cmp_ssub_di"
4458 [(set (match_operand:DI 0 "register_operand" "=r")
4459 (minus:DI (if_then_else:DI
4460 (match_operator 1 "alpha_zero_comparison_operator"
4461 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4463 (match_operand:DI 3 "const48_operand" "I")
4465 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4466 (clobber (match_scratch:DI 5 "=r"))]
4469 "! no_new_pseudos || reload_completed"
4471 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4473 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4476 if (! no_new_pseudos)
4477 operands[5] = gen_reg_rtx (DImode);
4478 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4479 operands[5] = operands[0];
4482 (define_insn_and_split "*cmp_ssub_si"
4483 [(set (match_operand:SI 0 "register_operand" "=r")
4484 (minus:SI (if_then_else:SI
4485 (match_operator 1 "alpha_zero_comparison_operator"
4486 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4488 (match_operand:SI 3 "const48_operand" "I")
4490 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4491 (clobber (match_scratch:SI 5 "=r"))]
4494 "! no_new_pseudos || reload_completed"
4496 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4498 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4501 if (! no_new_pseudos)
4502 operands[5] = gen_reg_rtx (DImode);
4503 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4504 operands[5] = operands[0];
4507 (define_insn_and_split "*cmp_ssub_sidi"
4508 [(set (match_operand:DI 0 "register_operand" "=r")
4510 (minus:SI (if_then_else:SI
4511 (match_operator 1 "alpha_zero_comparison_operator"
4512 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4514 (match_operand:SI 3 "const48_operand" "I")
4516 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4517 (clobber (match_scratch:SI 5 "=r"))]
4520 "! no_new_pseudos || reload_completed"
4522 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4524 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4527 if (! no_new_pseudos)
4528 operands[5] = gen_reg_rtx (DImode);
4529 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4530 operands[5] = operands[0];
4533 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4534 ;; work differently, so we have different patterns for each.
4536 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4537 ;; call. The CIW contains information about arguments passed in registers
4538 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4539 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4540 ;; in the presence of inlining since the CIWs for calls performed by the
4541 ;; inlined function must be stored in the SSIB of the function it is inlined
4542 ;; into as well. We encode the CIW in an unspec and append it to the list
4543 ;; of the CIWs for the current function only when the instruction for loading
4544 ;; $25 is generated.
4546 (define_expand "call"
4547 [(use (match_operand:DI 0 "" ""))
4548 (use (match_operand 1 "" ""))
4549 (use (match_operand 2 "" ""))
4550 (use (match_operand 3 "" ""))]
4553 if (TARGET_ABI_WINDOWS_NT)
4554 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4555 else if (TARGET_ABI_OPEN_VMS)
4556 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4557 else if (TARGET_ABI_UNICOSMK)
4558 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4560 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4564 (define_expand "sibcall"
4565 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4566 (match_operand 1 "" ""))
4567 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4570 if (GET_CODE (operands[0]) != MEM)
4572 operands[0] = XEXP (operands[0], 0);
4575 (define_expand "call_osf"
4576 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4577 (match_operand 1 "" ""))
4579 (clobber (reg:DI 26))])]
4582 if (GET_CODE (operands[0]) != MEM)
4585 operands[0] = XEXP (operands[0], 0);
4586 if (! call_operand (operands[0], Pmode))
4587 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4590 (define_expand "call_nt"
4591 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4592 (match_operand 1 "" ""))
4593 (clobber (reg:DI 26))])]
4596 if (GET_CODE (operands[0]) != MEM)
4599 operands[0] = XEXP (operands[0], 0);
4600 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4601 operands[0] = force_reg (DImode, operands[0]);
4604 ;; Calls on Unicos/Mk are always indirect.
4605 ;; op 0: symbol ref for called function
4606 ;; op 1: CIW for $25 represented by an unspec
4608 (define_expand "call_umk"
4609 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4610 (match_operand 1 "" ""))
4612 (clobber (reg:DI 26))])]
4615 if (GET_CODE (operands[0]) != MEM)
4618 /* Always load the address of the called function into a register;
4619 load the CIW in $25. */
4621 operands[0] = XEXP (operands[0], 0);
4622 if (GET_CODE (operands[0]) != REG)
4623 operands[0] = force_reg (DImode, operands[0]);
4625 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4629 ;; call openvms/alpha
4630 ;; op 0: symbol ref for called function
4631 ;; op 1: next_arg_reg (argument information value for R25)
4633 (define_expand "call_vms"
4634 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4635 (match_operand 1 "" ""))
4639 (clobber (reg:DI 27))])]
4642 if (GET_CODE (operands[0]) != MEM)
4645 operands[0] = XEXP (operands[0], 0);
4647 /* Always load AI with argument information, then handle symbolic and
4648 indirect call differently. Load RA and set operands[2] to PV in
4651 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4652 if (GET_CODE (operands[0]) == SYMBOL_REF)
4654 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4656 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4658 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4662 emit_move_insn (gen_rtx_REG (Pmode, 26),
4663 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4664 operands[2] = operands[0];
4669 (define_expand "call_value"
4670 [(use (match_operand 0 "" ""))
4671 (use (match_operand:DI 1 "" ""))
4672 (use (match_operand 2 "" ""))
4673 (use (match_operand 3 "" ""))
4674 (use (match_operand 4 "" ""))]
4677 if (TARGET_ABI_WINDOWS_NT)
4678 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4679 else if (TARGET_ABI_OPEN_VMS)
4680 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4682 else if (TARGET_ABI_UNICOSMK)
4683 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4686 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4691 (define_expand "sibcall_value"
4692 [(parallel [(set (match_operand 0 "" "")
4693 (call (mem:DI (match_operand 1 "" ""))
4694 (match_operand 2 "" "")))
4695 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4698 if (GET_CODE (operands[1]) != MEM)
4700 operands[1] = XEXP (operands[1], 0);
4703 (define_expand "call_value_osf"
4704 [(parallel [(set (match_operand 0 "" "")
4705 (call (mem:DI (match_operand 1 "" ""))
4706 (match_operand 2 "" "")))
4708 (clobber (reg:DI 26))])]
4711 if (GET_CODE (operands[1]) != MEM)
4714 operands[1] = XEXP (operands[1], 0);
4715 if (! call_operand (operands[1], Pmode))
4716 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4719 (define_expand "call_value_nt"
4720 [(parallel [(set (match_operand 0 "" "")
4721 (call (mem:DI (match_operand 1 "" ""))
4722 (match_operand 2 "" "")))
4723 (clobber (reg:DI 26))])]
4726 if (GET_CODE (operands[1]) != MEM)
4729 operands[1] = XEXP (operands[1], 0);
4730 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4731 operands[1] = force_reg (DImode, operands[1]);
4734 (define_expand "call_value_vms"
4735 [(parallel [(set (match_operand 0 "" "")
4736 (call (mem:DI (match_operand:DI 1 "" ""))
4737 (match_operand 2 "" "")))
4741 (clobber (reg:DI 27))])]
4744 if (GET_CODE (operands[1]) != MEM)
4747 operands[1] = XEXP (operands[1], 0);
4749 /* Always load AI with argument information, then handle symbolic and
4750 indirect call differently. Load RA and set operands[3] to PV in
4753 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4754 if (GET_CODE (operands[1]) == SYMBOL_REF)
4756 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4758 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4760 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4764 emit_move_insn (gen_rtx_REG (Pmode, 26),
4765 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4766 operands[3] = operands[1];
4770 (define_expand "call_value_umk"
4771 [(parallel [(set (match_operand 0 "" "")
4772 (call (mem:DI (match_operand 1 "" ""))
4773 (match_operand 2 "" "")))
4775 (clobber (reg:DI 26))])]
4778 if (GET_CODE (operands[1]) != MEM)
4781 operands[1] = XEXP (operands[1], 0);
4782 if (GET_CODE (operands[1]) != REG)
4783 operands[1] = force_reg (DImode, operands[1]);
4785 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4788 (define_insn "*call_osf_1_er"
4789 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4790 (match_operand 1 "" ""))
4792 (clobber (reg:DI 26))]
4793 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4795 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4797 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4798 [(set_attr "type" "jsr")
4799 (set_attr "length" "12,*,16")])
4801 ;; We must use peep2 instead of a split because we need accurate life
4802 ;; information for $gp. Consider the case of { bar(); while (1); }.
4804 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4805 (match_operand 1 "" ""))
4807 (clobber (reg:DI 26))])]
4808 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4809 && ! current_file_function_operand (operands[0], Pmode)
4810 && peep2_regno_dead_p (1, 29)"
4811 [(parallel [(call (mem:DI (match_dup 2))
4813 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4814 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4816 (use (match_dup 3))])]
4818 if (CONSTANT_P (operands[0]))
4820 operands[2] = gen_rtx_REG (Pmode, 27);
4821 operands[3] = GEN_INT (alpha_next_sequence_number++);
4822 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4823 operands[0], operands[3]));
4827 operands[2] = operands[0];
4828 operands[0] = const0_rtx;
4829 operands[3] = const0_rtx;
4834 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4835 (match_operand 1 "" ""))
4837 (clobber (reg:DI 26))])]
4838 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4839 && ! current_file_function_operand (operands[0], Pmode)
4840 && ! peep2_regno_dead_p (1, 29)"
4841 [(parallel [(call (mem:DI (match_dup 2))
4843 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4844 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4846 (use (match_dup 4))])
4848 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4850 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4852 if (CONSTANT_P (operands[0]))
4854 operands[2] = gen_rtx_REG (Pmode, 27);
4855 operands[4] = GEN_INT (alpha_next_sequence_number++);
4856 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4857 operands[0], operands[4]));
4861 operands[2] = operands[0];
4862 operands[0] = const0_rtx;
4863 operands[4] = const0_rtx;
4865 operands[3] = GEN_INT (alpha_next_sequence_number++);
4868 ;; We add a blockage unspec_volatile to prevent insns from moving down
4869 ;; from above the call to in between the call and the ldah gpdisp.
4871 (define_insn "*call_osf_2_er"
4872 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4873 (match_operand 1 "" ""))
4874 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4875 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4876 (use (match_operand 2 "" ""))
4877 (use (match_operand 3 "const_int_operand" ""))]
4878 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4879 "jsr $26,(%0),%2%J3"
4880 [(set_attr "type" "jsr")])
4882 (define_insn "*call_osf_1_noreturn"
4883 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4884 (match_operand 1 "" ""))
4886 (clobber (reg:DI 26))]
4887 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4888 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4893 [(set_attr "type" "jsr")
4894 (set_attr "length" "*,*,8")])
4896 (define_insn "*call_osf_1"
4897 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4898 (match_operand 1 "" ""))
4900 (clobber (reg:DI 26))]
4901 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4903 jsr $26,($27),0\;ldgp $29,0($26)
4905 jsr $26,%0\;ldgp $29,0($26)"
4906 [(set_attr "type" "jsr")
4907 (set_attr "length" "12,*,16")])
4909 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4910 ;; doesn't do what we want.
4911 (define_insn "*sibcall_osf_1_er"
4912 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4913 (match_operand 1 "" ""))
4914 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4915 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4918 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4919 [(set_attr "type" "jsr")
4920 (set_attr "length" "*,8")])
4922 (define_insn "*sibcall_osf_1"
4923 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4924 (match_operand 1 "" ""))
4925 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4926 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4929 lda $27,%0\;jmp $31,($27),%0"
4930 [(set_attr "type" "jsr")
4931 (set_attr "length" "*,8")])
4933 (define_insn "*call_nt_1"
4934 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4935 (match_operand 1 "" ""))
4936 (clobber (reg:DI 26))]
4937 "TARGET_ABI_WINDOWS_NT"
4942 [(set_attr "type" "jsr")
4943 (set_attr "length" "*,*,12")])
4945 (define_insn "*call_vms_1"
4946 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4947 (match_operand 1 "" ""))
4948 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4951 (clobber (reg:DI 27))]
4952 "TARGET_ABI_OPEN_VMS"
4954 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4955 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4956 [(set_attr "type" "jsr")
4957 (set_attr "length" "12,16")])
4959 (define_insn "*call_umk_1"
4960 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4961 (match_operand 1 "" ""))
4963 (clobber (reg:DI 26))]
4964 "TARGET_ABI_UNICOSMK"
4966 [(set_attr "type" "jsr")])
4968 ;; Call subroutine returning any type.
4970 (define_expand "untyped_call"
4971 [(parallel [(call (match_operand 0 "" "")
4973 (match_operand 1 "" "")
4974 (match_operand 2 "" "")])]
4979 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4981 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4983 rtx set = XVECEXP (operands[2], 0, i);
4984 emit_move_insn (SET_DEST (set), SET_SRC (set));
4987 /* The optimizer does not know that the call sets the function value
4988 registers we stored in the result block. We avoid problems by
4989 claiming that all hard registers are used and clobbered at this
4991 emit_insn (gen_blockage ());
4996 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4997 ;; all of memory. This blocks insns from being moved across this point.
4999 (define_insn "blockage"
5000 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5003 [(set_attr "length" "0")])
5007 (label_ref (match_operand 0 "" "")))]
5010 [(set_attr "type" "ibr")])
5012 (define_expand "return"
5017 (define_insn "*return_internal"
5021 [(set_attr "type" "ibr")])
5023 (define_insn "indirect_jump"
5024 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
5027 [(set_attr "type" "ibr")])
5029 (define_expand "tablejump"
5030 [(parallel [(set (pc)
5031 (match_operand 0 "register_operand" ""))
5032 (use (label_ref:DI (match_operand 1 "" "")))])]
5035 if (TARGET_ABI_WINDOWS_NT)
5037 rtx dest = gen_reg_rtx (DImode);
5038 emit_insn (gen_extendsidi2 (dest, operands[0]));
5041 else if (TARGET_ABI_OSF)
5043 rtx dest = gen_reg_rtx (DImode);
5044 emit_insn (gen_extendsidi2 (dest, operands[0]));
5045 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
5050 (define_insn "*tablejump_osf_nt_internal"
5052 (match_operand:DI 0 "register_operand" "r"))
5053 (use (label_ref:DI (match_operand 1 "" "")))]
5054 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5055 && alpha_tablejump_addr_vec (insn)"
5057 operands[2] = alpha_tablejump_best_label (insn);
5058 return "jmp $31,(%0),%2";
5060 [(set_attr "type" "ibr")])
5062 (define_insn "*tablejump_internal"
5064 (match_operand:DI 0 "register_operand" "r"))
5065 (use (label_ref (match_operand 1 "" "")))]
5068 [(set_attr "type" "ibr")])
5070 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5071 ;; want to have to include pal.h in our .s file.
5073 ;; Technically the type for call_pal is jsr, but we use that for determining
5074 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5077 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5080 [(set_attr "type" "ibr")])
5082 ;; Finally, we have the basic data motion insns. The byte and word insns
5083 ;; are done via define_expand. Start with the floating-point insns, since
5084 ;; they are simpler.
5086 (define_insn "*movsf_nofix"
5087 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5088 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5089 "TARGET_FPREGS && ! TARGET_FIX
5090 && (register_operand (operands[0], SFmode)
5091 || reg_or_fp0_operand (operands[1], SFmode))"
5099 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5101 (define_insn "*movsf_fix"
5102 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5103 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5104 "TARGET_FPREGS && TARGET_FIX
5105 && (register_operand (operands[0], SFmode)
5106 || reg_or_fp0_operand (operands[1], SFmode))"
5116 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5118 (define_insn "*movsf_nofp"
5119 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5120 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5122 && (register_operand (operands[0], SFmode)
5123 || reg_or_fp0_operand (operands[1], SFmode))"
5128 [(set_attr "type" "ilog,ild,ist")])
5130 (define_insn "*movdf_nofix"
5131 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5132 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5133 "TARGET_FPREGS && ! TARGET_FIX
5134 && (register_operand (operands[0], DFmode)
5135 || reg_or_fp0_operand (operands[1], DFmode))"
5143 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5145 (define_insn "*movdf_fix"
5146 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5147 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5148 "TARGET_FPREGS && TARGET_FIX
5149 && (register_operand (operands[0], DFmode)
5150 || reg_or_fp0_operand (operands[1], DFmode))"
5160 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5162 (define_insn "*movdf_nofp"
5163 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5164 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5166 && (register_operand (operands[0], DFmode)
5167 || reg_or_fp0_operand (operands[1], DFmode))"
5172 [(set_attr "type" "ilog,ild,ist")])
5174 ;; Subregs suck for register allocation. Pretend we can move TFmode
5175 ;; data between general registers until after reload.
5177 (define_insn_and_split "*movtf_internal"
5178 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5179 (match_operand:TF 1 "input_operand" "roG,rG"))]
5180 "register_operand (operands[0], TFmode)
5181 || reg_or_fp0_operand (operands[1], TFmode)"
5184 [(set (match_dup 0) (match_dup 2))
5185 (set (match_dup 1) (match_dup 3))]
5187 alpha_split_tfmode_pair (operands);
5188 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5191 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5192 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5196 (define_expand "movsf"
5197 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5198 (match_operand:SF 1 "general_operand" ""))]
5201 if (GET_CODE (operands[0]) == MEM
5202 && ! reg_or_fp0_operand (operands[1], SFmode))
5203 operands[1] = force_reg (SFmode, operands[1]);
5206 (define_expand "movdf"
5207 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5208 (match_operand:DF 1 "general_operand" ""))]
5211 if (GET_CODE (operands[0]) == MEM
5212 && ! reg_or_fp0_operand (operands[1], DFmode))
5213 operands[1] = force_reg (DFmode, operands[1]);
5216 (define_expand "movtf"
5217 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5218 (match_operand:TF 1 "general_operand" ""))]
5221 if (GET_CODE (operands[0]) == MEM
5222 && ! reg_or_fp0_operand (operands[1], TFmode))
5223 operands[1] = force_reg (TFmode, operands[1]);
5226 (define_insn "*movsi_nofix"
5227 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5228 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5229 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5230 && (register_operand (operands[0], SImode)
5231 || reg_or_0_operand (operands[1], SImode))"
5241 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5243 (define_insn "*movsi_fix"
5244 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5245 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5246 "TARGET_ABI_OSF && TARGET_FIX
5247 && (register_operand (operands[0], SImode)
5248 || reg_or_0_operand (operands[1], SImode))"
5260 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5262 (define_insn "*movsi_nt_vms_nofix"
5263 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5264 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5265 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5267 && (register_operand (operands[0], SImode)
5268 || reg_or_0_operand (operands[1], SImode))"
5279 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5281 (define_insn "*movsi_nt_vms_fix"
5282 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5283 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5284 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5286 && (register_operand (operands[0], SImode)
5287 || reg_or_0_operand (operands[1], SImode))"
5300 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5302 (define_insn "*movhi_nobwx"
5303 [(set (match_operand:HI 0 "register_operand" "=r,r")
5304 (match_operand:HI 1 "input_operand" "rJ,n"))]
5306 && (register_operand (operands[0], HImode)
5307 || register_operand (operands[1], HImode))"
5311 [(set_attr "type" "ilog,iadd")])
5313 (define_insn "*movhi_bwx"
5314 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5315 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5317 && (register_operand (operands[0], HImode)
5318 || reg_or_0_operand (operands[1], HImode))"
5324 [(set_attr "type" "ilog,iadd,ild,ist")])
5326 (define_insn "*movqi_nobwx"
5327 [(set (match_operand:QI 0 "register_operand" "=r,r")
5328 (match_operand:QI 1 "input_operand" "rJ,n"))]
5330 && (register_operand (operands[0], QImode)
5331 || register_operand (operands[1], QImode))"
5335 [(set_attr "type" "ilog,iadd")])
5337 (define_insn "*movqi_bwx"
5338 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5339 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5341 && (register_operand (operands[0], QImode)
5342 || reg_or_0_operand (operands[1], QImode))"
5348 [(set_attr "type" "ilog,iadd,ild,ist")])
5350 ;; We do two major things here: handle mem->mem and construct long
5353 (define_expand "movsi"
5354 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5355 (match_operand:SI 1 "general_operand" ""))]
5358 if (alpha_expand_mov (SImode, operands))
5362 ;; Split a load of a large constant into the appropriate two-insn
5366 [(set (match_operand:SI 0 "register_operand" "")
5367 (match_operand:SI 1 "const_int_operand" ""))]
5368 "! add_operand (operands[1], SImode)"
5369 [(set (match_dup 0) (match_dup 2))
5370 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5373 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5375 if (tem == operands[0])
5381 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5382 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5383 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5384 ;; notes and update LABEL_NUSES because this is not done automatically.
5385 ;; Labels may be incorrectly deleted if we don't do this.
5387 ;; Describing what the individual instructions do correctly is too complicated
5388 ;; so use UNSPECs for each of the three parts of an address.
5391 [(set (match_operand:DI 0 "register_operand" "")
5392 (match_operand:DI 1 "symbolic_operand" ""))]
5393 "TARGET_ABI_UNICOSMK && reload_completed"
5396 rtx insn1, insn2, insn3;
5398 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5399 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5400 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5401 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5402 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5404 if (GET_CODE (operands[1]) == LABEL_REF)
5408 label = XEXP (operands[1], 0);
5409 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5411 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5413 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5415 LABEL_NUSES (label) += 3;
5420 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5422 (define_insn "umk_laum"
5423 [(set (match_operand:DI 0 "register_operand" "=r")
5424 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5426 "TARGET_ABI_UNICOSMK"
5428 [(set_attr "type" "iadd")])
5430 (define_insn "umk_lalm"
5431 [(set (match_operand:DI 0 "register_operand" "=r")
5432 (plus:DI (match_operand:DI 1 "register_operand" "r")
5433 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5435 "TARGET_ABI_UNICOSMK"
5437 [(set_attr "type" "iadd")])
5439 (define_insn "umk_lal"
5440 [(set (match_operand:DI 0 "register_operand" "=r")
5441 (plus:DI (match_operand:DI 1 "register_operand" "r")
5442 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5444 "TARGET_ABI_UNICOSMK"
5446 [(set_attr "type" "iadd")])
5448 ;; Add a new call information word to the current function's list of CIWs
5449 ;; and load its index into $25. Doing it here ensures that the CIW will be
5450 ;; associated with the correct function even in the presence of inlining.
5452 (define_insn "*umk_load_ciw"
5454 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5455 "TARGET_ABI_UNICOSMK"
5457 operands[0] = unicosmk_add_call_info_word (operands[0]);
5458 return "lda $25,%0";
5460 [(set_attr "type" "iadd")])
5462 (define_insn "*movdi_er_low_l"
5463 [(set (match_operand:DI 0 "register_operand" "=r")
5464 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5465 (match_operand:DI 2 "local_symbolic_operand" "")))]
5466 "TARGET_EXPLICIT_RELOCS"
5468 if (true_regnum (operands[1]) == 29)
5469 return "lda %0,%2(%1)\t\t!gprel";
5471 return "lda %0,%2(%1)\t\t!gprellow";
5475 [(set (match_operand:DI 0 "register_operand" "")
5476 (match_operand:DI 1 "small_symbolic_operand" ""))]
5477 "TARGET_EXPLICIT_RELOCS && reload_completed"
5479 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5480 "operands[2] = pic_offset_table_rtx;")
5483 [(set (match_operand:DI 0 "register_operand" "")
5484 (match_operand:DI 1 "local_symbolic_operand" ""))]
5485 "TARGET_EXPLICIT_RELOCS && reload_completed"
5487 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5489 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5490 "operands[2] = pic_offset_table_rtx;")
5493 [(match_operand 0 "some_small_symbolic_operand" "")]
5494 "TARGET_EXPLICIT_RELOCS && reload_completed"
5496 "operands[0] = split_small_symbolic_operand (operands[0]);")
5498 (define_insn "movdi_er_high_g"
5499 [(set (match_operand:DI 0 "register_operand" "=r")
5500 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5501 (match_operand:DI 2 "global_symbolic_operand" "")
5502 (match_operand 3 "const_int_operand" "")]
5504 "TARGET_EXPLICIT_RELOCS"
5506 if (INTVAL (operands[3]) == 0)
5507 return "ldq %0,%2(%1)\t\t!literal";
5509 return "ldq %0,%2(%1)\t\t!literal!%3";
5511 [(set_attr "type" "ldsym")])
5514 [(set (match_operand:DI 0 "register_operand" "")
5515 (match_operand:DI 1 "global_symbolic_operand" ""))]
5516 "TARGET_EXPLICIT_RELOCS && reload_completed"
5518 (unspec:DI [(match_dup 2)
5520 (const_int 0)] UNSPEC_LITERAL))]
5521 "operands[2] = pic_offset_table_rtx;")
5523 (define_insn "*movdi_er_nofix"
5524 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5525 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5526 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5527 && (register_operand (operands[0], DImode)
5528 || reg_or_0_operand (operands[1], DImode))"
5540 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5542 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5543 ;; have been split up by the rules above but we shouldn't reject the
5544 ;; possibility of them getting through.
5546 (define_insn "*movdi_nofix"
5547 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5548 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5550 && (register_operand (operands[0], DImode)
5551 || reg_or_0_operand (operands[1], DImode))"
5556 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5563 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5564 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5566 (define_insn "*movdi_er_fix"
5567 [(set (match_operand:DI 0 "nonimmediate_operand"
5568 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5569 (match_operand:DI 1 "input_operand"
5570 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5571 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5572 && (register_operand (operands[0], DImode)
5573 || reg_or_0_operand (operands[1], DImode))"
5587 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5589 (define_insn "*movdi_fix"
5590 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5591 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5592 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5593 && (register_operand (operands[0], DImode)
5594 || reg_or_0_operand (operands[1], DImode))"
5607 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5609 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5610 ;; often appears dead to the life analysis code, at which point we
5611 ;; abort for emitting dead prologue instructions. Force this live.
5613 (define_insn "force_movdi"
5614 [(set (match_operand:DI 0 "register_operand" "=r")
5615 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5616 UNSPECV_FORCE_MOV))]
5619 [(set_attr "type" "ilog")])
5621 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5622 ;; memory, and construct long 32-bit constants.
5624 (define_expand "movdi"
5625 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5626 (match_operand:DI 1 "general_operand" ""))]
5629 if (alpha_expand_mov (DImode, operands))
5633 ;; Split a load of a large constant into the appropriate two-insn
5637 [(set (match_operand:DI 0 "register_operand" "")
5638 (match_operand:DI 1 "const_int_operand" ""))]
5639 "! add_operand (operands[1], DImode)"
5640 [(set (match_dup 0) (match_dup 2))
5641 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5644 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5646 if (tem == operands[0])
5652 ;; These are the partial-word cases.
5654 ;; First we have the code to load an aligned word. Operand 0 is the register
5655 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5656 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5657 ;; number of bits within the word that the value is. Operand 3 is an SImode
5658 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5659 ;; same register. It is allowed to conflict with operand 1 as well.
5661 (define_expand "aligned_loadqi"
5662 [(set (match_operand:SI 3 "register_operand" "")
5663 (match_operand:SI 1 "memory_operand" ""))
5664 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5665 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5667 (match_operand:DI 2 "const_int_operand" "")))]
5672 (define_expand "aligned_loadhi"
5673 [(set (match_operand:SI 3 "register_operand" "")
5674 (match_operand:SI 1 "memory_operand" ""))
5675 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5676 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5678 (match_operand:DI 2 "const_int_operand" "")))]
5683 ;; Similar for unaligned loads, where we use the sequence from the
5684 ;; Alpha Architecture manual. We have to distinguish between little-endian
5685 ;; and big-endian systems as the sequences are different.
5687 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5688 ;; operand 3 can overlap the input and output registers.
5690 (define_expand "unaligned_loadqi"
5691 [(use (match_operand:QI 0 "register_operand" ""))
5692 (use (match_operand:DI 1 "address_operand" ""))
5693 (use (match_operand:DI 2 "register_operand" ""))
5694 (use (match_operand:DI 3 "register_operand" ""))]
5697 if (WORDS_BIG_ENDIAN)
5698 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5699 operands[2], operands[3]));
5701 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5702 operands[2], operands[3]));
5706 (define_expand "unaligned_loadqi_le"
5707 [(set (match_operand:DI 2 "register_operand" "")
5708 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5710 (set (match_operand:DI 3 "register_operand" "")
5712 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5713 (zero_extract:DI (match_dup 2)
5715 (ashift:DI (match_dup 3) (const_int 3))))]
5716 "! WORDS_BIG_ENDIAN"
5719 (define_expand "unaligned_loadqi_be"
5720 [(set (match_operand:DI 2 "register_operand" "")
5721 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5723 (set (match_operand:DI 3 "register_operand" "")
5725 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5726 (zero_extract:DI (match_dup 2)
5730 (ashift:DI (match_dup 3) (const_int 3)))))]
5734 (define_expand "unaligned_loadhi"
5735 [(use (match_operand:QI 0 "register_operand" ""))
5736 (use (match_operand:DI 1 "address_operand" ""))
5737 (use (match_operand:DI 2 "register_operand" ""))
5738 (use (match_operand:DI 3 "register_operand" ""))]
5741 if (WORDS_BIG_ENDIAN)
5742 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5743 operands[2], operands[3]));
5745 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5746 operands[2], operands[3]));
5750 (define_expand "unaligned_loadhi_le"
5751 [(set (match_operand:DI 2 "register_operand" "")
5752 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5754 (set (match_operand:DI 3 "register_operand" "")
5756 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5757 (zero_extract:DI (match_dup 2)
5759 (ashift:DI (match_dup 3) (const_int 3))))]
5760 "! WORDS_BIG_ENDIAN"
5763 (define_expand "unaligned_loadhi_be"
5764 [(set (match_operand:DI 2 "register_operand" "")
5765 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5767 (set (match_operand:DI 3 "register_operand" "")
5768 (plus:DI (match_dup 1) (const_int 1)))
5769 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5770 (zero_extract:DI (match_dup 2)
5774 (ashift:DI (match_dup 3) (const_int 3)))))]
5778 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5779 ;; aligned SImode MEM. Operand 1 is the register containing the
5780 ;; byte or word to store. Operand 2 is the number of bits within the word that
5781 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5783 (define_expand "aligned_store"
5784 [(set (match_operand:SI 3 "register_operand" "")
5785 (match_operand:SI 0 "memory_operand" ""))
5786 (set (subreg:DI (match_dup 3) 0)
5787 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5788 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5789 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5790 (match_operand:DI 2 "const_int_operand" "")))
5791 (set (subreg:DI (match_dup 4) 0)
5792 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5793 (set (match_dup 0) (match_dup 4))]
5796 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5797 << INTVAL (operands[2])));
5800 ;; For the unaligned byte and halfword cases, we use code similar to that
5801 ;; in the ;; Architecture book, but reordered to lower the number of registers
5802 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5803 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5804 ;; be the same temporary, if desired. If the address is in a register,
5805 ;; operand 2 can be that register.
5807 (define_expand "unaligned_storeqi"
5808 [(use (match_operand:DI 0 "address_operand" ""))
5809 (use (match_operand:QI 1 "register_operand" ""))
5810 (use (match_operand:DI 2 "register_operand" ""))
5811 (use (match_operand:DI 3 "register_operand" ""))
5812 (use (match_operand:DI 4 "register_operand" ""))]
5815 if (WORDS_BIG_ENDIAN)
5816 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5817 operands[2], operands[3],
5820 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5821 operands[2], operands[3],
5826 (define_expand "unaligned_storeqi_le"
5827 [(set (match_operand:DI 3 "register_operand" "")
5828 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5830 (set (match_operand:DI 2 "register_operand" "")
5833 (and:DI (not:DI (ashift:DI (const_int 255)
5834 (ashift:DI (match_dup 2) (const_int 3))))
5836 (set (match_operand:DI 4 "register_operand" "")
5837 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5838 (ashift:DI (match_dup 2) (const_int 3))))
5839 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5840 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5842 "! WORDS_BIG_ENDIAN"
5845 (define_expand "unaligned_storeqi_be"
5846 [(set (match_operand:DI 3 "register_operand" "")
5847 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5849 (set (match_operand:DI 2 "register_operand" "")
5852 (and:DI (not:DI (ashift:DI (const_int 255)
5853 (minus:DI (const_int 56)
5854 (ashift:DI (match_dup 2) (const_int 3)))))
5856 (set (match_operand:DI 4 "register_operand" "")
5857 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5858 (minus:DI (const_int 56)
5859 (ashift:DI (match_dup 2) (const_int 3)))))
5860 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5861 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5866 (define_expand "unaligned_storehi"
5867 [(use (match_operand:DI 0 "address_operand" ""))
5868 (use (match_operand:HI 1 "register_operand" ""))
5869 (use (match_operand:DI 2 "register_operand" ""))
5870 (use (match_operand:DI 3 "register_operand" ""))
5871 (use (match_operand:DI 4 "register_operand" ""))]
5874 if (WORDS_BIG_ENDIAN)
5875 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5876 operands[2], operands[3],
5879 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5880 operands[2], operands[3],
5885 (define_expand "unaligned_storehi_le"
5886 [(set (match_operand:DI 3 "register_operand" "")
5887 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5889 (set (match_operand:DI 2 "register_operand" "")
5892 (and:DI (not:DI (ashift:DI (const_int 65535)
5893 (ashift:DI (match_dup 2) (const_int 3))))
5895 (set (match_operand:DI 4 "register_operand" "")
5896 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5897 (ashift:DI (match_dup 2) (const_int 3))))
5898 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5899 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5901 "! WORDS_BIG_ENDIAN"
5904 (define_expand "unaligned_storehi_be"
5905 [(set (match_operand:DI 3 "register_operand" "")
5906 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5908 (set (match_operand:DI 2 "register_operand" "")
5909 (plus:DI (match_dup 0) (const_int 1)))
5911 (and:DI (not:DI (ashift:DI
5913 (minus:DI (const_int 56)
5914 (ashift:DI (match_dup 2) (const_int 3)))))
5916 (set (match_operand:DI 4 "register_operand" "")
5917 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5918 (minus:DI (const_int 56)
5919 (ashift:DI (match_dup 2) (const_int 3)))))
5920 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5921 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5926 ;; Here are the define_expand's for QI and HI moves that use the above
5927 ;; patterns. We have the normal sets, plus the ones that need scratch
5928 ;; registers for reload.
5930 (define_expand "movqi"
5931 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5932 (match_operand:QI 1 "general_operand" ""))]
5936 ? alpha_expand_mov (QImode, operands)
5937 : alpha_expand_mov_nobwx (QImode, operands))
5941 (define_expand "movhi"
5942 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5943 (match_operand:HI 1 "general_operand" ""))]
5947 ? alpha_expand_mov (HImode, operands)
5948 : alpha_expand_mov_nobwx (HImode, operands))
5952 ;; Here are the versions for reload. Note that in the unaligned cases
5953 ;; we know that the operand must not be a pseudo-register because stack
5954 ;; slots are always aligned references.
5956 (define_expand "reload_inqi"
5957 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5958 (match_operand:QI 1 "any_memory_operand" "m")
5959 (match_operand:TI 2 "register_operand" "=&r")])]
5964 if (GET_CODE (operands[1]) != MEM)
5967 if (aligned_memory_operand (operands[1], QImode))
5969 seq = gen_reload_inqi_help (operands[0], operands[1],
5970 gen_rtx_REG (SImode, REGNO (operands[2])));
5976 /* It is possible that one of the registers we got for operands[2]
5977 might coincide with that of operands[0] (which is why we made
5978 it TImode). Pick the other one to use as our scratch. */
5979 if (REGNO (operands[0]) == REGNO (operands[2]))
5980 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5982 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5984 addr = get_unaligned_address (operands[1], 0);
5985 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5986 gen_rtx_REG (DImode, REGNO (operands[0])));
5987 alpha_set_memflags (seq, operands[1]);
5993 (define_expand "reload_inhi"
5994 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5995 (match_operand:HI 1 "any_memory_operand" "m")
5996 (match_operand:TI 2 "register_operand" "=&r")])]
6001 if (GET_CODE (operands[1]) != MEM)
6004 if (aligned_memory_operand (operands[1], HImode))
6006 seq = gen_reload_inhi_help (operands[0], operands[1],
6007 gen_rtx_REG (SImode, REGNO (operands[2])));
6013 /* It is possible that one of the registers we got for operands[2]
6014 might coincide with that of operands[0] (which is why we made
6015 it TImode). Pick the other one to use as our scratch. */
6016 if (REGNO (operands[0]) == REGNO (operands[2]))
6017 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6019 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6021 addr = get_unaligned_address (operands[1], 0);
6022 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
6023 gen_rtx_REG (DImode, REGNO (operands[0])));
6024 alpha_set_memflags (seq, operands[1]);
6030 (define_expand "reload_outqi"
6031 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6032 (match_operand:QI 1 "register_operand" "r")
6033 (match_operand:TI 2 "register_operand" "=&r")])]
6036 if (GET_CODE (operands[0]) != MEM)
6039 if (aligned_memory_operand (operands[0], QImode))
6041 emit_insn (gen_reload_outqi_help
6042 (operands[0], operands[1],
6043 gen_rtx_REG (SImode, REGNO (operands[2])),
6044 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6048 rtx addr = get_unaligned_address (operands[0], 0);
6049 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6050 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6051 rtx scratch3 = scratch1;
6054 if (GET_CODE (addr) == REG)
6057 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6058 scratch2, scratch3);
6059 alpha_set_memflags (seq, operands[0]);
6065 (define_expand "reload_outhi"
6066 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6067 (match_operand:HI 1 "register_operand" "r")
6068 (match_operand:TI 2 "register_operand" "=&r")])]
6071 if (GET_CODE (operands[0]) != MEM)
6074 if (aligned_memory_operand (operands[0], HImode))
6076 emit_insn (gen_reload_outhi_help
6077 (operands[0], operands[1],
6078 gen_rtx_REG (SImode, REGNO (operands[2])),
6079 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6083 rtx addr = get_unaligned_address (operands[0], 0);
6084 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6085 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6086 rtx scratch3 = scratch1;
6089 if (GET_CODE (addr) == REG)
6092 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6093 scratch2, scratch3);
6094 alpha_set_memflags (seq, operands[0]);
6100 ;; Helpers for the above. The way reload is structured, we can't
6101 ;; always get a proper address for a stack slot during reload_foo
6102 ;; expansion, so we must delay our address manipulations until after.
6104 (define_insn "reload_inqi_help"
6105 [(set (match_operand:QI 0 "register_operand" "=r")
6106 (match_operand:QI 1 "memory_operand" "m"))
6107 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6108 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6111 (define_insn "reload_inhi_help"
6112 [(set (match_operand:HI 0 "register_operand" "=r")
6113 (match_operand:HI 1 "memory_operand" "m"))
6114 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6115 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6118 (define_insn "reload_outqi_help"
6119 [(set (match_operand:QI 0 "memory_operand" "=m")
6120 (match_operand:QI 1 "register_operand" "r"))
6121 (clobber (match_operand:SI 2 "register_operand" "=r"))
6122 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6123 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6126 (define_insn "reload_outhi_help"
6127 [(set (match_operand:HI 0 "memory_operand" "=m")
6128 (match_operand:HI 1 "register_operand" "r"))
6129 (clobber (match_operand:SI 2 "register_operand" "=r"))
6130 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6131 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6135 [(set (match_operand:QI 0 "register_operand" "")
6136 (match_operand:QI 1 "memory_operand" ""))
6137 (clobber (match_operand:SI 2 "register_operand" ""))]
6138 "! TARGET_BWX && reload_completed"
6141 rtx aligned_mem, bitnum;
6142 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6144 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6150 [(set (match_operand:HI 0 "register_operand" "")
6151 (match_operand:HI 1 "memory_operand" ""))
6152 (clobber (match_operand:SI 2 "register_operand" ""))]
6153 "! TARGET_BWX && reload_completed"
6156 rtx aligned_mem, bitnum;
6157 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6159 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6165 [(set (match_operand:QI 0 "memory_operand" "")
6166 (match_operand:QI 1 "register_operand" ""))
6167 (clobber (match_operand:SI 2 "register_operand" ""))
6168 (clobber (match_operand:SI 3 "register_operand" ""))]
6169 "! TARGET_BWX && reload_completed"
6172 rtx aligned_mem, bitnum;
6173 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6174 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6175 operands[2], operands[3]));
6180 [(set (match_operand:HI 0 "memory_operand" "")
6181 (match_operand:HI 1 "register_operand" ""))
6182 (clobber (match_operand:SI 2 "register_operand" ""))
6183 (clobber (match_operand:SI 3 "register_operand" ""))]
6184 "! TARGET_BWX && reload_completed"
6187 rtx aligned_mem, bitnum;
6188 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6189 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6190 operands[2], operands[3]));
6194 ;; Bit field extract patterns which use ext[wlq][lh]
6196 (define_expand "extv"
6197 [(set (match_operand:DI 0 "register_operand" "")
6198 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6199 (match_operand:DI 2 "immediate_operand" "")
6200 (match_operand:DI 3 "immediate_operand" "")))]
6205 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6206 if (INTVAL (operands[3]) % 8 != 0
6207 || (INTVAL (operands[2]) != 16
6208 && INTVAL (operands[2]) != 32
6209 && INTVAL (operands[2]) != 64))
6212 /* From mips.md: extract_bit_field doesn't verify that our source
6213 matches the predicate, so we force it to be a MEM here. */
6214 if (GET_CODE (operands[1]) != MEM)
6217 /* The bit number is relative to the mode of operand 1 which is
6218 usually QImode (this might actually be a bug in expmed.c). Note
6219 that the bit number is negative in big-endian mode in this case.
6220 We have to convert that to the offset. */
6221 if (WORDS_BIG_ENDIAN)
6222 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6223 - INTVAL (operands[2]) - INTVAL (operands[3]);
6225 ofs = INTVAL (operands[3]);
6229 alpha_expand_unaligned_load (operands[0], operands[1],
6230 INTVAL (operands[2]) / 8,
6235 (define_expand "extzv"
6236 [(set (match_operand:DI 0 "register_operand" "")
6237 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6238 (match_operand:DI 2 "immediate_operand" "")
6239 (match_operand:DI 3 "immediate_operand" "")))]
6242 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6243 if (INTVAL (operands[3]) % 8 != 0
6244 || (INTVAL (operands[2]) != 8
6245 && INTVAL (operands[2]) != 16
6246 && INTVAL (operands[2]) != 32
6247 && INTVAL (operands[2]) != 64))
6250 if (GET_CODE (operands[1]) == MEM)
6254 /* Fail 8 bit fields, falling back on a simple byte load. */
6255 if (INTVAL (operands[2]) == 8)
6258 /* The bit number is relative to the mode of operand 1 which is
6259 usually QImode (this might actually be a bug in expmed.c). Note
6260 that the bit number is negative in big-endian mode in this case.
6261 We have to convert that to the offset. */
6262 if (WORDS_BIG_ENDIAN)
6263 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6264 - INTVAL (operands[2]) - INTVAL (operands[3]);
6266 ofs = INTVAL (operands[3]);
6270 alpha_expand_unaligned_load (operands[0], operands[1],
6271 INTVAL (operands[2]) / 8,
6277 (define_expand "insv"
6278 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6279 (match_operand:DI 1 "immediate_operand" "")
6280 (match_operand:DI 2 "immediate_operand" ""))
6281 (match_operand:DI 3 "register_operand" ""))]
6286 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6287 if (INTVAL (operands[2]) % 8 != 0
6288 || (INTVAL (operands[1]) != 16
6289 && INTVAL (operands[1]) != 32
6290 && INTVAL (operands[1]) != 64))
6293 /* From mips.md: store_bit_field doesn't verify that our source
6294 matches the predicate, so we force it to be a MEM here. */
6295 if (GET_CODE (operands[0]) != MEM)
6298 /* The bit number is relative to the mode of operand 1 which is
6299 usually QImode (this might actually be a bug in expmed.c). Note
6300 that the bit number is negative in big-endian mode in this case.
6301 We have to convert that to the offset. */
6302 if (WORDS_BIG_ENDIAN)
6303 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6304 - INTVAL (operands[1]) - INTVAL (operands[2]);
6306 ofs = INTVAL (operands[2]);
6310 alpha_expand_unaligned_store (operands[0], operands[3],
6311 INTVAL (operands[1]) / 8, ofs);
6315 ;; Block move/clear, see alpha.c for more details.
6316 ;; Argument 0 is the destination
6317 ;; Argument 1 is the source
6318 ;; Argument 2 is the length
6319 ;; Argument 3 is the alignment
6321 (define_expand "movstrqi"
6322 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6323 (match_operand:BLK 1 "memory_operand" ""))
6324 (use (match_operand:DI 2 "immediate_operand" ""))
6325 (use (match_operand:DI 3 "immediate_operand" ""))])]
6328 if (alpha_expand_block_move (operands))
6334 (define_expand "clrstrqi"
6335 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6337 (use (match_operand:DI 1 "immediate_operand" ""))
6338 (use (match_operand:DI 2 "immediate_operand" ""))])]
6341 if (alpha_expand_block_clear (operands))
6347 ;; Subroutine of stack space allocation. Perform a stack probe.
6348 (define_expand "probe_stack"
6349 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6352 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6353 INTVAL (operands[0])));
6354 MEM_VOLATILE_P (operands[1]) = 1;
6356 operands[0] = const0_rtx;
6359 ;; This is how we allocate stack space. If we are allocating a
6360 ;; constant amount of space and we know it is less than 4096
6361 ;; bytes, we need do nothing.
6363 ;; If it is more than 4096 bytes, we need to probe the stack
6365 (define_expand "allocate_stack"
6367 (plus:DI (reg:DI 30)
6368 (match_operand:DI 1 "reg_or_cint_operand" "")))
6369 (set (match_operand:DI 0 "register_operand" "=r")
6373 if (GET_CODE (operands[1]) == CONST_INT
6374 && INTVAL (operands[1]) < 32768)
6376 if (INTVAL (operands[1]) >= 4096)
6378 /* We do this the same way as in the prologue and generate explicit
6379 probes. Then we update the stack by the constant. */
6383 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6384 while (probed + 8192 < INTVAL (operands[1]))
6385 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6387 if (probed + 4096 < INTVAL (operands[1]))
6388 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6391 operands[1] = GEN_INT (- INTVAL (operands[1]));
6392 operands[2] = virtual_stack_dynamic_rtx;
6397 rtx loop_label = gen_label_rtx ();
6398 rtx want = gen_reg_rtx (Pmode);
6399 rtx tmp = gen_reg_rtx (Pmode);
6402 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6403 force_reg (Pmode, operands[1])));
6404 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6406 if (GET_CODE (operands[1]) != CONST_INT)
6408 out_label = gen_label_rtx ();
6409 emit_insn (gen_cmpdi (want, tmp));
6410 emit_jump_insn (gen_bgeu (out_label));
6413 emit_label (loop_label);
6414 memref = gen_rtx_MEM (DImode, tmp);
6415 MEM_VOLATILE_P (memref) = 1;
6416 emit_move_insn (memref, const0_rtx);
6417 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6418 emit_insn (gen_cmpdi (tmp, want));
6419 emit_jump_insn (gen_bgtu (loop_label));
6421 memref = gen_rtx_MEM (DImode, want);
6422 MEM_VOLATILE_P (memref) = 1;
6423 emit_move_insn (memref, const0_rtx);
6426 emit_label (out_label);
6428 emit_move_insn (stack_pointer_rtx, want);
6429 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6434 ;; This is used by alpha_expand_prolog to do the same thing as above,
6435 ;; except we cannot at that time generate new basic blocks, so we hide
6436 ;; the loop in this one insn.
6438 (define_insn "prologue_stack_probe_loop"
6439 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6440 (match_operand:DI 1 "register_operand" "r")]
6444 operands[2] = gen_label_rtx ();
6445 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6446 CODE_LABEL_NUMBER (operands[2]));
6448 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6450 [(set_attr "length" "16")
6451 (set_attr "type" "multi")])
6453 (define_expand "prologue"
6454 [(clobber (const_int 0))]
6457 alpha_expand_prologue ();
6461 ;; These take care of emitting the ldgp insn in the prologue. This will be
6462 ;; an lda/ldah pair and we want to align them properly. So we have two
6463 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6464 ;; and the second of which emits nothing. However, both are marked as type
6465 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6468 (define_expand "prologue_ldgp"
6470 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6472 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6475 operands[0] = pic_offset_table_rtx;
6476 operands[1] = gen_rtx_REG (Pmode, 27);
6477 operands[2] = (TARGET_EXPLICIT_RELOCS
6478 ? GEN_INT (alpha_next_sequence_number++)
6482 (define_insn "*ldgp_er_1"
6483 [(set (match_operand:DI 0 "register_operand" "=r")
6484 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6485 (match_operand 2 "const_int_operand" "")]
6487 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6488 "ldah %0,0(%1)\t\t!gpdisp!%2")
6490 (define_insn "*ldgp_er_2"
6491 [(set (match_operand:DI 0 "register_operand" "=r")
6492 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6493 (match_operand 2 "const_int_operand" "")]
6495 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6496 "lda %0,0(%1)\t\t!gpdisp!%2")
6498 (define_insn "*prologue_ldgp_er_2"
6499 [(set (match_operand:DI 0 "register_operand" "=r")
6500 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6501 (match_operand 2 "const_int_operand" "")]
6503 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6504 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6506 (define_insn "*prologue_ldgp_1"
6507 [(set (match_operand:DI 0 "register_operand" "=r")
6508 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6509 (match_operand 2 "const_int_operand" "")]
6512 "ldgp %0,0(%1)\n$%~..ng:")
6514 (define_insn "*prologue_ldgp_2"
6515 [(set (match_operand:DI 0 "register_operand" "=r")
6516 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6517 (match_operand 2 "const_int_operand" "")]
6522 ;; The _mcount profiling hook has special calling conventions, and
6523 ;; does not clobber all the registers that a normal call would. So
6524 ;; hide the fact this is a call at all.
6526 (define_insn "prologue_mcount"
6527 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6530 if (TARGET_EXPLICIT_RELOCS)
6531 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6532 cannot be called via the PLT. */
6533 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6535 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6537 [(set_attr "type" "multi")
6538 (set_attr "length" "8")])
6540 (define_insn "init_fp"
6541 [(set (match_operand:DI 0 "register_operand" "=r")
6542 (match_operand:DI 1 "register_operand" "r"))
6543 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6547 (define_expand "epilogue"
6551 alpha_expand_epilogue ();
6554 (define_expand "sibcall_epilogue"
6558 alpha_expand_epilogue ();
6562 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6563 ;; the frame size into a register. We use this pattern to ensure
6564 ;; we get lda instead of addq.
6565 (define_insn "nt_lda"
6566 [(set (match_operand:DI 0 "register_operand" "=r")
6567 (unspec:DI [(match_dup 0)
6568 (match_operand:DI 1 "const_int_operand" "n")]
6573 (define_expand "builtin_longjmp"
6574 [(use (match_operand:DI 0 "register_operand" "r"))]
6577 /* The elements of the buffer are, in order: */
6578 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6579 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6580 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6581 rtx pv = gen_rtx_REG (Pmode, 27);
6583 /* This bit is the same as expand_builtin_longjmp. */
6584 emit_move_insn (hard_frame_pointer_rtx, fp);
6585 emit_move_insn (pv, lab);
6586 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6587 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6588 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6590 /* Load the label we are jumping through into $27 so that we know
6591 where to look for it when we get back to setjmp's function for
6592 restoring the gp. */
6593 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6598 ;; This is effectively a copy of indirect_jump, but constrained such
6599 ;; that register renaming cannot foil our cunning plan with $27.
6600 (define_insn "builtin_longjmp_internal"
6602 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6606 [(set_attr "type" "ibr")])
6608 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6609 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6610 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6611 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6613 (define_insn "*builtin_setjmp_receiver_er_1"
6614 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6615 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6616 "br $27,$LSJ%=\n$LSJ%=:"
6617 [(set_attr "type" "ibr")])
6620 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6621 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6622 && prev_nonnote_insn (insn) == operands[0]"
6626 (define_insn "*builtin_setjmp_receiver_1"
6627 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6629 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6630 [(set_attr "length" "12")
6631 (set_attr "type" "multi")])
6633 (define_expand "builtin_setjmp_receiver_er"
6634 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6636 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6638 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6641 operands[1] = pic_offset_table_rtx;
6642 operands[2] = gen_rtx_REG (Pmode, 27);
6643 operands[3] = GEN_INT (alpha_next_sequence_number++);
6646 (define_expand "builtin_setjmp_receiver"
6647 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6650 if (TARGET_EXPLICIT_RELOCS)
6652 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6657 (define_expand "exception_receiver_er"
6659 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6661 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6664 operands[0] = pic_offset_table_rtx;
6665 operands[1] = gen_rtx_REG (Pmode, 26);
6666 operands[2] = GEN_INT (alpha_next_sequence_number++);
6669 (define_expand "exception_receiver"
6670 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6673 if (TARGET_LD_BUGGY_LDGP)
6674 operands[0] = alpha_gp_save_rtx ();
6675 else if (TARGET_EXPLICIT_RELOCS)
6677 emit_insn (gen_exception_receiver_er ());
6681 operands[0] = const0_rtx;
6684 (define_insn "*exception_receiver_1"
6685 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6686 "! TARGET_LD_BUGGY_LDGP"
6688 [(set_attr "length" "8")
6689 (set_attr "type" "multi")])
6691 (define_insn "*exception_receiver_2"
6692 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
6694 "TARGET_LD_BUGGY_LDGP"
6698 [(set_attr "type" "ilog,ild")])
6700 (define_expand "nonlocal_goto_receiver"
6701 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6702 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6703 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6705 "TARGET_ABI_OPEN_VMS"
6708 (define_insn "arg_home"
6709 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6724 (clobber (mem:BLK (const_int 0)))
6725 (clobber (reg:DI 24))
6726 (clobber (reg:DI 25))
6727 (clobber (reg:DI 0))]
6728 "TARGET_ABI_OPEN_VMS"
6729 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6730 [(set_attr "length" "16")
6731 (set_attr "type" "multi")])
6733 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6735 (define_expand "umk_mismatch_args"
6736 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6737 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6738 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6739 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6742 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6743 "TARGET_ABI_UNICOSMK"
6745 operands[1] = gen_reg_rtx (DImode);
6746 operands[2] = gen_reg_rtx (DImode);
6747 operands[3] = gen_reg_rtx (DImode);
6750 (define_insn "arg_home_umk"
6751 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6766 (clobber (mem:BLK (const_int 0)))
6768 (clobber (reg:DI 22))
6769 (clobber (reg:DI 23))
6770 (clobber (reg:DI 24))
6771 (clobber (reg:DI 0))
6772 (clobber (reg:DI 1))
6773 (clobber (reg:DI 2))
6774 (clobber (reg:DI 3))
6775 (clobber (reg:DI 4))
6776 (clobber (reg:DI 5))
6777 (clobber (reg:DI 6))
6778 (clobber (reg:DI 7))
6779 (clobber (reg:DI 8))])]
6780 "TARGET_ABI_UNICOSMK"
6781 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6782 [(set_attr "length" "16")
6783 (set_attr "type" "multi")])
6787 ;; On EV4, these instructions are nops -- no load occurs.
6789 ;; On EV5, these instructions act as a normal load, and thus can trap
6790 ;; if the address is invalid. The OS may (or may not) handle this in
6791 ;; the entMM fault handler and suppress the fault. If so, then this
6792 ;; has the effect of a read prefetch instruction.
6794 ;; On EV6, these become official prefetch instructions.
6796 (define_insn "prefetch"
6797 [(prefetch (match_operand:DI 0 "address_operand" "p")
6798 (match_operand:DI 1 "const_int_operand" "n")
6799 (match_operand:DI 2 "const_int_operand" "n"))]
6800 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6802 /* Interpret "no temporal locality" as this data should be evicted once
6803 it is used. The "evict next" alternatives load the data into the cache
6804 and leave the LRU eviction counter pointing to that block. */
6805 static const char * const alt[2][2] = {
6807 "lds $f31,%a0", /* read, evict next */
6808 "ldl $31,%a0", /* read, evict last */
6811 "ldt $f31,%a0", /* write, evict next */
6812 "ldq $31,%a0", /* write, evict last */
6816 bool write = INTVAL (operands[1]) != 0;
6817 bool lru = INTVAL (operands[2]) != 0;
6819 return alt[write][lru];
6821 [(set_attr "type" "ild")])
6823 ;; Close the trap shadow of preceding instructions. This is generated
6826 (define_insn "trapb"
6827 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6830 [(set_attr "type" "misc")])
6832 ;; No-op instructions used by machine-dependent reorg to preserve
6833 ;; alignment for instruction issue.
6834 ;; The Unicos/Mk assembler does not support these opcodes.
6840 [(set_attr "type" "ilog")])
6845 "cpys $f31,$f31,$f31"
6846 [(set_attr "type" "fcpys")])
6853 ;; On Unicos/Mk we use a macro for aligning code.
6855 (define_insn "realign"
6856 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6860 if (TARGET_ABI_UNICOSMK)
6861 return "gcc@code@align %0";
6863 return ".align %0 #realign";
6866 ;; The call patterns are at the end of the file because their
6867 ;; wildcard operand0 interferes with nice recognition.
6869 (define_insn "*call_value_osf_1_er"
6870 [(set (match_operand 0 "" "")
6871 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6872 (match_operand 2 "" "")))
6874 (clobber (reg:DI 26))]
6875 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6877 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6879 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6880 [(set_attr "type" "jsr")
6881 (set_attr "length" "12,*,16")])
6883 ;; We must use peep2 instead of a split because we need accurate life
6884 ;; information for $gp. Consider the case of { bar(); while (1); }.
6886 [(parallel [(set (match_operand 0 "" "")
6887 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6888 (match_operand 2 "" "")))
6890 (clobber (reg:DI 26))])]
6891 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6892 && ! current_file_function_operand (operands[1], Pmode)
6893 && peep2_regno_dead_p (1, 29)"
6894 [(parallel [(set (match_dup 0)
6895 (call (mem:DI (match_dup 3))
6897 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6898 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6900 (use (match_dup 4))])]
6902 if (CONSTANT_P (operands[1]))
6904 operands[3] = gen_rtx_REG (Pmode, 27);
6905 operands[4] = GEN_INT (alpha_next_sequence_number++);
6906 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6907 operands[1], operands[4]));
6911 operands[3] = operands[1];
6912 operands[1] = const0_rtx;
6913 operands[4] = const0_rtx;
6918 [(parallel [(set (match_operand 0 "" "")
6919 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6920 (match_operand 2 "" "")))
6922 (clobber (reg:DI 26))])]
6923 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6924 && ! current_file_function_operand (operands[1], Pmode)
6925 && ! peep2_regno_dead_p (1, 29)"
6926 [(parallel [(set (match_dup 0)
6927 (call (mem:DI (match_dup 3))
6929 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6930 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6932 (use (match_dup 5))])
6934 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6936 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6938 if (CONSTANT_P (operands[1]))
6940 operands[3] = gen_rtx_REG (Pmode, 27);
6941 operands[5] = GEN_INT (alpha_next_sequence_number++);
6942 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6943 operands[1], operands[5]));
6947 operands[3] = operands[1];
6948 operands[1] = const0_rtx;
6949 operands[5] = const0_rtx;
6951 operands[4] = GEN_INT (alpha_next_sequence_number++);
6954 ;; We add a blockage unspec_volatile to prevent insns from moving down
6955 ;; from above the call to in between the call and the ldah gpdisp.
6956 (define_insn "*call_value_osf_2_er"
6957 [(set (match_operand 0 "" "")
6958 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6959 (match_operand 2 "" "")))
6961 (plus:DI (pc) (const_int 4)))
6962 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6963 (use (match_operand 3 "" ""))
6964 (use (match_operand 4 "const_int_operand" ""))]
6965 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6966 "jsr $26,(%1),%3%J4"
6967 [(set_attr "type" "jsr")])
6969 (define_insn "*call_value_osf_1_noreturn"
6970 [(set (match_operand 0 "" "")
6971 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6972 (match_operand 2 "" "")))
6974 (clobber (reg:DI 26))]
6975 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6976 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6981 [(set_attr "type" "jsr")
6982 (set_attr "length" "*,*,8")])
6984 (define_insn "*call_value_osf_1"
6985 [(set (match_operand 0 "" "")
6986 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6987 (match_operand 2 "" "")))
6989 (clobber (reg:DI 26))]
6990 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6992 jsr $26,($27),0\;ldgp $29,0($26)
6994 jsr $26,%1\;ldgp $29,0($26)"
6995 [(set_attr "type" "jsr")
6996 (set_attr "length" "12,*,16")])
6998 (define_insn "*sibcall_value_osf_1_er"
6999 [(set (match_operand 0 "" "")
7000 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7001 (match_operand 2 "" "")))
7002 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7003 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7006 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7007 [(set_attr "type" "jsr")
7008 (set_attr "length" "*,8")])
7010 (define_insn "*sibcall_value_osf_1"
7011 [(set (match_operand 0 "" "")
7012 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7013 (match_operand 2 "" "")))
7014 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7015 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7018 lda $27,%1\;jmp $31,($27),%1"
7019 [(set_attr "type" "jsr")
7020 (set_attr "length" "*,8")])
7022 (define_insn "*call_value_nt_1"
7023 [(set (match_operand 0 "" "")
7024 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7025 (match_operand 2 "" "")))
7026 (clobber (reg:DI 26))]
7027 "TARGET_ABI_WINDOWS_NT"
7032 [(set_attr "type" "jsr")
7033 (set_attr "length" "*,*,12")])
7035 (define_insn "*call_value_vms_1"
7036 [(set (match_operand 0 "" "")
7037 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7038 (match_operand 2 "" "")))
7039 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
7042 (clobber (reg:DI 27))]
7043 "TARGET_ABI_OPEN_VMS"
7045 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
7046 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
7047 [(set_attr "type" "jsr")
7048 (set_attr "length" "12,16")])
7050 (define_insn "*call_value_umk"
7051 [(set (match_operand 0 "" "")
7052 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
7053 (match_operand 2 "" "")))
7055 (clobber (reg:DI 26))]
7056 "TARGET_ABI_UNICOSMK"
7058 [(set_attr "type" "jsr")])