1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
45 ;; Processor type -- this attribute must exactly match the processor_type
46 ;; enumeration in alpha.h.
48 (define_attr "cpu" "ev4,ev5,ev6"
49 (const (symbol_ref "alpha_cpu")))
51 ;; Define an insn type attribute. This is used in function unit delay
52 ;; computations, among other purposes. For the most part, we use the names
53 ;; defined in the EV4 documentation, but add a few that we have to know about
57 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
58 (const_string "iadd"))
60 ;; Describe a user's asm statement.
61 (define_asm_attributes
62 [(set_attr "type" "multi")])
64 ;; Define the operand size an insn operates on. Used primarily by mul
65 ;; and div operations that have size dependant timings.
67 (define_attr "opsize" "si,di,udi" (const_string "di"))
69 ;; The TRAP_TYPE attribute marks instructions that may generate traps
70 ;; (which are imprecise and may need a trapb if software completion
73 (define_attr "trap" "no,yes" (const_string "no"))
75 ;; The length of an instruction sequence in bytes.
77 (define_attr "length" "" (const_int 4))
79 ;; On EV4 there are two classes of resources to consider: resources needed
80 ;; to issue, and resources needed to execute. IBUS[01] are in the first
81 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
82 ;; (There are a few other register-like resources, but ...)
84 ; First, describe all of the issue constraints with single cycle delays.
85 ; All insns need a bus, but all except loads require one or the other.
86 (define_function_unit "ev4_ibus0" 1 0
87 (and (eq_attr "cpu" "ev4")
88 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
91 (define_function_unit "ev4_ibus1" 1 0
92 (and (eq_attr "cpu" "ev4")
93 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
96 ; Memory delivers its result in three cycles. Actually return one and
97 ; take care of this in adjust_cost, since we want to handle user-defined
99 (define_function_unit "ev4_abox" 1 0
100 (and (eq_attr "cpu" "ev4")
101 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
104 ; Branches have no delay cost, but do tie up the unit for two cycles.
105 (define_function_unit "ev4_bbox" 1 1
106 (and (eq_attr "cpu" "ev4")
107 (eq_attr "type" "ibr,fbr,jsr"))
110 ; Arithmetic insns are normally have their results available after
111 ; two cycles. There are a number of exceptions. They are encoded in
112 ; ADJUST_COST. Some of the other insns have similar exceptions.
113 (define_function_unit "ev4_ebox" 1 0
114 (and (eq_attr "cpu" "ev4")
115 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
118 (define_function_unit "imul" 1 0
119 (and (eq_attr "cpu" "ev4")
120 (and (eq_attr "type" "imul")
121 (eq_attr "opsize" "si")))
124 (define_function_unit "imul" 1 0
125 (and (eq_attr "cpu" "ev4")
126 (and (eq_attr "type" "imul")
127 (eq_attr "opsize" "!si")))
130 (define_function_unit "ev4_fbox" 1 0
131 (and (eq_attr "cpu" "ev4")
132 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
135 (define_function_unit "fdiv" 1 0
136 (and (eq_attr "cpu" "ev4")
137 (and (eq_attr "type" "fdiv")
138 (eq_attr "opsize" "si")))
141 (define_function_unit "fdiv" 1 0
142 (and (eq_attr "cpu" "ev4")
143 (and (eq_attr "type" "fdiv")
144 (eq_attr "opsize" "di")))
147 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
149 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
150 ;; with the combined resource EBOX.
152 (define_function_unit "ev5_ebox" 2 0
153 (and (eq_attr "cpu" "ev5")
154 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
157 ; Memory takes at least 2 clocks. Return one from here and fix up with
158 ; user-defined latencies in adjust_cost.
159 (define_function_unit "ev5_ebox" 2 0
160 (and (eq_attr "cpu" "ev5")
161 (eq_attr "type" "ild,fld,ldsym"))
164 ; Loads can dual issue with one another, but loads and stores do not mix.
165 (define_function_unit "ev5_e0" 1 0
166 (and (eq_attr "cpu" "ev5")
167 (eq_attr "type" "ild,fld,ldsym"))
169 [(eq_attr "type" "ist,fst")])
171 ; Stores, shifts, multiplies can only issue to E0
172 (define_function_unit "ev5_e0" 1 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "ist,fst,shift,imul"))
177 ; Motion video insns also issue only to E0, and take two ticks.
178 (define_function_unit "ev5_e0" 1 0
179 (and (eq_attr "cpu" "ev5")
180 (eq_attr "type" "mvi"))
183 ; Conditional moves always take 2 ticks.
184 (define_function_unit "ev5_ebox" 2 0
185 (and (eq_attr "cpu" "ev5")
186 (eq_attr "type" "icmov"))
189 ; Branches can only issue to E1
190 (define_function_unit "ev5_e1" 1 0
191 (and (eq_attr "cpu" "ev5")
192 (eq_attr "type" "ibr,jsr"))
195 ; Multiplies also use the integer multiplier.
196 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
197 ; cycles before an integer multiplication completes."
198 (define_function_unit "imul" 1 0
199 (and (eq_attr "cpu" "ev5")
200 (and (eq_attr "type" "imul")
201 (eq_attr "opsize" "si")))
204 (define_function_unit "imul" 1 0
205 (and (eq_attr "cpu" "ev5")
206 (and (eq_attr "type" "imul")
207 (eq_attr "opsize" "di")))
210 (define_function_unit "imul" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (and (eq_attr "type" "imul")
213 (eq_attr "opsize" "udi")))
216 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
217 ;; on either so we have to play the game again.
219 (define_function_unit "ev5_fbox" 2 0
220 (and (eq_attr "cpu" "ev5")
221 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
224 (define_function_unit "ev5_fm" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "fmul"))
229 ; Add and cmov as you would expect; fbr never produces a result;
230 ; fdiv issues through fa to the divider,
231 (define_function_unit "ev5_fa" 1 0
232 (and (eq_attr "cpu" "ev5")
233 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
236 ; ??? How to: "No instruction can be issued to pipe FA exactly five
237 ; cycles before a floating point divide completes."
238 (define_function_unit "fdiv" 1 0
239 (and (eq_attr "cpu" "ev5")
240 (and (eq_attr "type" "fdiv")
241 (eq_attr "opsize" "si")))
242 15 15) ; 15 to 31 data dependant
244 (define_function_unit "fdiv" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "fdiv")
247 (eq_attr "opsize" "di")))
248 22 22) ; 22 to 60 data dependant
250 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
252 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
253 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
255 ;; Conditional moves decompose into two independant primitives, each
256 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
258 (define_function_unit "ev6_ebox" 4 0
259 (and (eq_attr "cpu" "ev6")
260 (eq_attr "type" "icmov"))
263 (define_function_unit "ev6_ebox" 4 0
264 (and (eq_attr "cpu" "ev6")
265 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
268 ;; Integer loads take at least 3 clocks, and only issue to lower units.
269 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
270 (define_function_unit "ev6_l" 2 0
271 (and (eq_attr "cpu" "ev6")
272 (eq_attr "type" "ild,ldsym,ist,fst"))
275 ;; FP loads take at least 4 clocks. Return two from here...
276 (define_function_unit "ev6_l" 2 0
277 (and (eq_attr "cpu" "ev6")
278 (eq_attr "type" "fld"))
281 ;; Motion video insns also issue only to U0, and take three ticks.
282 (define_function_unit "ev6_u0" 1 0
283 (and (eq_attr "cpu" "ev6")
284 (eq_attr "type" "mvi"))
287 (define_function_unit "ev6_u" 2 0
288 (and (eq_attr "cpu" "ev6")
289 (eq_attr "type" "mvi"))
292 ;; Shifts issue to either upper pipe.
293 (define_function_unit "ev6_u" 2 0
294 (and (eq_attr "cpu" "ev6")
295 (eq_attr "type" "shift"))
298 ;; Multiplies issue only to U1, and all take 7 ticks.
299 ;; Rather than create a new function unit just for U1, reuse IMUL
300 (define_function_unit "imul" 1 0
301 (and (eq_attr "cpu" "ev6")
302 (eq_attr "type" "imul"))
305 (define_function_unit "ev6_u" 2 0
306 (and (eq_attr "cpu" "ev6")
307 (eq_attr "type" "imul"))
310 ;; Branches issue to either upper pipe
311 (define_function_unit "ev6_u" 2 0
312 (and (eq_attr "cpu" "ev6")
313 (eq_attr "type" "ibr"))
316 ;; Calls only issue to L0.
317 (define_function_unit "ev6_l0" 1 0
318 (and (eq_attr "cpu" "ev6")
319 (eq_attr "type" "jsr"))
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "jsr"))
327 ;; Ftoi/itof only issue to lower pipes
328 (define_function_unit "ev6_l" 2 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "ftoi"))
333 (define_function_unit "ev6_l" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "itof"))
338 ;; For the FPU we are very similar to EV5, except there's no insn that
339 ;; can issue to fm & fa, so we get to leave that out.
341 (define_function_unit "ev6_fm" 1 0
342 (and (eq_attr "cpu" "ev6")
343 (eq_attr "type" "fmul"))
346 (define_function_unit "ev6_fa" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
351 (define_function_unit "ev6_fa" 1 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "fcmov"))
356 (define_function_unit "fdiv" 1 0
357 (and (eq_attr "cpu" "ev6")
358 (and (eq_attr "type" "fdiv")
359 (eq_attr "opsize" "si")))
362 (define_function_unit "fdiv" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (and (eq_attr "type" "fdiv")
365 (eq_attr "opsize" "di")))
368 (define_function_unit "fsqrt" 1 0
369 (and (eq_attr "cpu" "ev6")
370 (and (eq_attr "type" "fsqrt")
371 (eq_attr "opsize" "si")))
374 (define_function_unit "fsqrt" 1 0
375 (and (eq_attr "cpu" "ev6")
376 (and (eq_attr "type" "fsqrt")
377 (eq_attr "opsize" "di")))
380 ; ??? The FPU communicates with memory and the integer register file
381 ; via two fp store units. We need a slot in the fst immediately, and
382 ; a slot in LOW after the operand data is ready. At which point the
383 ; data may be moved either to the store queue or the integer register
384 ; file and the insn retired.
387 ;; First define the arithmetic insns. Note that the 32-bit forms also
390 ;; Handle 32-64 bit extension from memory to a floating point register
391 ;; specially, since this ocurrs frequently in int->double conversions.
393 ;; Note that while we must retain the =f case in the insn for reload's
394 ;; benefit, it should be eliminated after reload, so we should never emit
395 ;; code for that case. But we don't reject the possibility.
397 (define_expand "extendsidi2"
398 [(set (match_operand:DI 0 "register_operand" "")
399 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
404 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
406 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
412 lds %0,%1\;cvtlq %0,%0"
413 [(set_attr "type" "iadd,ild,fadd,fld")
414 (set_attr "length" "*,*,*,8")])
417 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
419 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
426 lds %0,%1\;cvtlq %0,%0"
427 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
428 (set_attr "length" "*,*,*,*,8")])
430 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
432 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
433 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
435 [(set (match_dup 2) (match_dup 1))
436 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
437 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
439 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
440 ;; generates better code. We have the anonymous addsi3 pattern below in
441 ;; case combine wants to make it.
442 (define_expand "addsi3"
443 [(set (match_operand:SI 0 "register_operand" "")
444 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
445 (match_operand:SI 2 "add_operand" "")))]
451 rtx op1 = gen_lowpart (DImode, operands[1]);
452 rtx op2 = gen_lowpart (DImode, operands[2]);
454 if (! cse_not_expected)
456 rtx tmp = gen_reg_rtx (DImode);
457 emit_insn (gen_adddi3 (tmp, op1, op2));
458 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
461 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
467 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
468 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
469 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
478 [(set (match_operand:SI 0 "register_operand" "")
479 (plus:SI (match_operand:SI 1 "register_operand" "")
480 (match_operand:SI 2 "const_int_operand" "")))]
481 "! add_operand (operands[2], SImode)"
482 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
483 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
486 HOST_WIDE_INT val = INTVAL (operands[2]);
487 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
488 HOST_WIDE_INT rest = val - low;
490 operands[3] = GEN_INT (rest);
491 operands[4] = GEN_INT (low);
495 [(set (match_operand:DI 0 "register_operand" "=r,r")
497 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
498 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
505 [(set (match_operand:DI 0 "register_operand" "")
507 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
508 (match_operand:SI 2 "const_int_operand" ""))))
509 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
510 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
511 && INTVAL (operands[2]) % 4 == 0"
512 [(set (match_dup 3) (match_dup 4))
513 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
518 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
524 operands[4] = GEN_INT (val);
525 operands[5] = GEN_INT (mult);
529 [(set (match_operand:DI 0 "register_operand" "")
531 (plus:SI (match_operator:SI 1 "comparison_operator"
532 [(match_operand 2 "" "")
533 (match_operand 3 "" "")])
534 (match_operand:SI 4 "add_operand" ""))))
535 (clobber (match_operand:DI 5 "register_operand" ""))]
537 [(set (match_dup 5) (match_dup 6))
538 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
541 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
542 operands[2], operands[3]);
543 operands[7] = gen_lowpart (SImode, operands[5]);
546 (define_expand "adddi3"
547 [(set (match_operand:DI 0 "register_operand" "")
548 (plus:DI (match_operand:DI 1 "register_operand" "")
549 (match_operand:DI 2 "add_operand" "")))]
553 ;; This pattern exists so that register elimination tries to canonize
554 ;; (plus (plus reg c1) c2).
557 [(set (match_operand:DI 0 "register_operand" "=r")
558 (match_operand:DI 1 "addition_operation" "p"))]
562 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
563 ;; With complications like
565 ;; The NT stack unwind code can't handle a subq to adjust the stack
566 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
567 ;; the exception handling code will loop if a subq is used and an
570 ;; The 19980616 change to emit prologues as RTL also confused some
571 ;; versions of GDB, which also interprets prologues. This has been
572 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
575 ;; and the fact that the three insns schedule exactly the same, it's
576 ;; just not worth the effort.
578 (define_insn "*adddi_2"
579 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
580 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
581 (match_operand:DI 2 "add_operand" "r,K,L")))]
588 ;; ??? Allow large constants when basing off the frame pointer or some
589 ;; virtual register that may eliminate to the frame pointer. This is
590 ;; done because register elimination offsets will change the hi/lo split,
591 ;; and if we split before reload, we will require additional instructions.
594 [(set (match_operand:DI 0 "register_operand" "=r")
595 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
596 (match_operand:DI 2 "const_int_operand" "n")))]
597 "REG_OK_FP_BASE_P (operands[1])
598 && INTVAL (operands[2]) >= 0
599 /* This is the largest constant an lda+ldah pair can add, minus
600 an upper bound on the displacement between SP and AP during
601 register elimination. See INITIAL_ELIMINATION_OFFSET. */
602 && INTVAL (operands[2])
604 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
605 - ALPHA_ROUND(current_function_outgoing_args_size)
606 - (ALPHA_ROUND (get_frame_size ()
607 + max_reg_num () * UNITS_PER_WORD
608 + current_function_pretend_args_size)
609 - current_function_pretend_args_size))"
612 ;; Don't do this if we are adjusting SP since we don't want to do it
613 ;; in two steps. Don't split FP sources for the reason listed above.
615 [(set (match_operand:DI 0 "register_operand" "")
616 (plus:DI (match_operand:DI 1 "register_operand" "")
617 (match_operand:DI 2 "const_int_operand" "")))]
618 "! add_operand (operands[2], DImode)
619 && operands[0] != stack_pointer_rtx
620 && operands[1] != frame_pointer_rtx
621 && operands[1] != arg_pointer_rtx"
622 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
623 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
626 HOST_WIDE_INT val = INTVAL (operands[2]);
627 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
628 HOST_WIDE_INT rest = val - low;
630 operands[4] = GEN_INT (low);
631 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
632 operands[3] = GEN_INT (rest);
633 else if (! no_new_pseudos)
635 operands[3] = gen_reg_rtx (DImode);
636 emit_move_insn (operands[3], operands[2]);
637 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
645 [(set (match_operand:SI 0 "register_operand" "=r,r")
646 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
647 (match_operand:SI 2 "const48_operand" "I,I"))
648 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
655 [(set (match_operand:DI 0 "register_operand" "=r,r")
657 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
658 (match_operand:SI 2 "const48_operand" "I,I"))
659 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
666 [(set (match_operand:DI 0 "register_operand" "")
668 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
669 [(match_operand 2 "" "")
670 (match_operand 3 "" "")])
671 (match_operand:SI 4 "const48_operand" ""))
672 (match_operand:SI 5 "sext_add_operand" ""))))
673 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
675 [(set (match_dup 6) (match_dup 7))
677 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
681 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
682 operands[2], operands[3]);
683 operands[8] = gen_lowpart (SImode, operands[6]);
687 [(set (match_operand:DI 0 "register_operand" "=r,r")
688 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
689 (match_operand:DI 2 "const48_operand" "I,I"))
690 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
696 (define_insn "negsi2"
697 [(set (match_operand:SI 0 "register_operand" "=r")
698 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
703 [(set (match_operand:DI 0 "register_operand" "=r")
704 (sign_extend:DI (neg:SI
705 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
709 (define_insn "negdi2"
710 [(set (match_operand:DI 0 "register_operand" "=r")
711 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
715 (define_expand "subsi3"
716 [(set (match_operand:SI 0 "register_operand" "")
717 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
718 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
724 rtx op1 = gen_lowpart (DImode, operands[1]);
725 rtx op2 = gen_lowpart (DImode, operands[2]);
727 if (! cse_not_expected)
729 rtx tmp = gen_reg_rtx (DImode);
730 emit_insn (gen_subdi3 (tmp, op1, op2));
731 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
734 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
740 [(set (match_operand:SI 0 "register_operand" "=r")
741 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
742 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
747 [(set (match_operand:DI 0 "register_operand" "=r")
748 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
749 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
753 (define_insn "subdi3"
754 [(set (match_operand:DI 0 "register_operand" "=r")
755 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
756 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
761 [(set (match_operand:SI 0 "register_operand" "=r")
762 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
763 (match_operand:SI 2 "const48_operand" "I"))
764 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
769 [(set (match_operand:DI 0 "register_operand" "=r")
771 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
772 (match_operand:SI 2 "const48_operand" "I"))
773 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
778 [(set (match_operand:DI 0 "register_operand" "=r")
779 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
780 (match_operand:DI 2 "const48_operand" "I"))
781 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
785 (define_insn "mulsi3"
786 [(set (match_operand:SI 0 "register_operand" "=r")
787 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
788 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
791 [(set_attr "type" "imul")
792 (set_attr "opsize" "si")])
795 [(set (match_operand:DI 0 "register_operand" "=r")
797 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
798 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
801 [(set_attr "type" "imul")
802 (set_attr "opsize" "si")])
804 (define_insn "muldi3"
805 [(set (match_operand:DI 0 "register_operand" "=r")
806 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
807 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
810 [(set_attr "type" "imul")])
812 (define_insn "umuldi3_highpart"
813 [(set (match_operand:DI 0 "register_operand" "=r")
816 (mult:TI (zero_extend:TI
817 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
819 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
823 [(set_attr "type" "imul")
824 (set_attr "opsize" "udi")])
827 [(set (match_operand:DI 0 "register_operand" "=r")
830 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
831 (match_operand:TI 2 "cint8_operand" "I"))
835 [(set_attr "type" "imul")
836 (set_attr "opsize" "udi")])
838 ;; The divide and remainder operations always take their inputs from
839 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
841 ;; ??? Force sign-extension here because some versions of OSF/1 don't
842 ;; do the right thing if the inputs are not properly sign-extended.
843 ;; But Linux, for instance, does not have this problem. Is it worth
844 ;; the complication here to eliminate the sign extension?
845 ;; Interix/NT has the same sign-extension problem.
847 (define_expand "divsi3"
849 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
851 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
852 (parallel [(set (reg:DI 27)
853 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
854 (clobber (reg:DI 23))
855 (clobber (reg:DI 28))])
856 (set (match_operand:SI 0 "nonimmediate_operand" "")
857 (subreg:SI (reg:DI 27) 0))]
861 (define_expand "udivsi3"
863 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
865 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
866 (parallel [(set (reg:DI 27)
867 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
868 (clobber (reg:DI 23))
869 (clobber (reg:DI 28))])
870 (set (match_operand:SI 0 "nonimmediate_operand" "")
871 (subreg:SI (reg:DI 27) 0))]
875 (define_expand "modsi3"
877 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
879 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
880 (parallel [(set (reg:DI 27)
881 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
882 (clobber (reg:DI 23))
883 (clobber (reg:DI 28))])
884 (set (match_operand:SI 0 "nonimmediate_operand" "")
885 (subreg:SI (reg:DI 27) 0))]
889 (define_expand "umodsi3"
891 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
893 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
894 (parallel [(set (reg:DI 27)
895 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
896 (clobber (reg:DI 23))
897 (clobber (reg:DI 28))])
898 (set (match_operand:SI 0 "nonimmediate_operand" "")
899 (subreg:SI (reg:DI 27) 0))]
903 (define_expand "divdi3"
904 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
905 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
906 (parallel [(set (reg:DI 27)
909 (clobber (reg:DI 23))
910 (clobber (reg:DI 28))])
911 (set (match_operand:DI 0 "nonimmediate_operand" "")
916 (define_expand "udivdi3"
917 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
918 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
919 (parallel [(set (reg:DI 27)
922 (clobber (reg:DI 23))
923 (clobber (reg:DI 28))])
924 (set (match_operand:DI 0 "nonimmediate_operand" "")
929 (define_expand "moddi3"
930 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
931 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
932 (parallel [(set (reg:DI 27)
935 (clobber (reg:DI 23))
936 (clobber (reg:DI 28))])
937 (set (match_operand:DI 0 "nonimmediate_operand" "")
942 (define_expand "umoddi3"
943 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
944 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
945 (parallel [(set (reg:DI 27)
948 (clobber (reg:DI 23))
949 (clobber (reg:DI 28))])
950 (set (match_operand:DI 0 "nonimmediate_operand" "")
955 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
956 ;; expanded by the assembler.
959 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
960 [(reg:DI 24) (reg:DI 25)])))
961 (clobber (reg:DI 23))
962 (clobber (reg:DI 28))]
965 [(set_attr "type" "jsr")
966 (set_attr "length" "8")])
970 (match_operator:DI 1 "divmod_operator"
971 [(reg:DI 24) (reg:DI 25)]))
972 (clobber (reg:DI 23))
973 (clobber (reg:DI 28))]
976 [(set_attr "type" "jsr")
977 (set_attr "length" "8")])
979 ;; Next are the basic logical operations. These only exist in DImode.
981 (define_insn "anddi3"
982 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
983 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
984 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
990 [(set_attr "type" "ilog,ilog,shift")])
992 ;; There are times when we can split an AND into two AND insns. This occurs
993 ;; when we can first clear any bytes and then clear anything else. For
994 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
995 ;; Only do this when running on 64-bit host since the computations are
996 ;; too messy otherwise.
999 [(set (match_operand:DI 0 "register_operand" "")
1000 (and:DI (match_operand:DI 1 "register_operand" "")
1001 (match_operand:DI 2 "const_int_operand" "")))]
1002 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1003 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1004 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1007 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1008 unsigned HOST_WIDE_INT mask2 = mask1;
1011 /* For each byte that isn't all zeros, make it all ones. */
1012 for (i = 0; i < 64; i += 8)
1013 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1014 mask1 |= (HOST_WIDE_INT) 0xff << i;
1016 /* Now turn on any bits we've just turned off. */
1019 operands[3] = GEN_INT (mask1);
1020 operands[4] = GEN_INT (mask2);
1023 (define_insn "zero_extendqihi2"
1024 [(set (match_operand:HI 0 "register_operand" "=r")
1025 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1028 [(set_attr "type" "ilog")])
1031 [(set (match_operand:SI 0 "register_operand" "=r,r")
1032 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1037 [(set_attr "type" "ilog,ild")])
1040 [(set (match_operand:SI 0 "register_operand" "=r")
1041 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1044 [(set_attr "type" "ilog")])
1046 (define_expand "zero_extendqisi2"
1047 [(set (match_operand:SI 0 "register_operand" "")
1048 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1053 [(set (match_operand:DI 0 "register_operand" "=r,r")
1054 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1059 [(set_attr "type" "ilog,ild")])
1062 [(set (match_operand:DI 0 "register_operand" "=r")
1063 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1066 [(set_attr "type" "ilog")])
1068 (define_expand "zero_extendqidi2"
1069 [(set (match_operand:DI 0 "register_operand" "")
1070 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1075 [(set (match_operand:SI 0 "register_operand" "=r,r")
1076 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1081 [(set_attr "type" "shift,ild")])
1084 [(set (match_operand:SI 0 "register_operand" "=r")
1085 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1088 [(set_attr "type" "shift")])
1090 (define_expand "zero_extendhisi2"
1091 [(set (match_operand:SI 0 "register_operand" "")
1092 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1097 [(set (match_operand:DI 0 "register_operand" "=r,r")
1098 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1103 [(set_attr "type" "shift,ild")])
1106 [(set (match_operand:DI 0 "register_operand" "=r")
1107 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1110 [(set_attr "type" "shift")])
1112 (define_expand "zero_extendhidi2"
1113 [(set (match_operand:DI 0 "register_operand" "")
1114 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1118 (define_insn "zero_extendsidi2"
1119 [(set (match_operand:DI 0 "register_operand" "=r")
1120 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1123 [(set_attr "type" "shift")])
1126 [(set (match_operand:DI 0 "register_operand" "=r")
1127 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1128 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1131 [(set_attr "type" "ilog")])
1133 (define_insn "iordi3"
1134 [(set (match_operand:DI 0 "register_operand" "=r,r")
1135 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1136 (match_operand:DI 2 "or_operand" "rI,N")))]
1141 [(set_attr "type" "ilog")])
1143 (define_insn "one_cmpldi2"
1144 [(set (match_operand:DI 0 "register_operand" "=r")
1145 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1148 [(set_attr "type" "ilog")])
1151 [(set (match_operand:DI 0 "register_operand" "=r")
1152 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1153 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1156 [(set_attr "type" "ilog")])
1158 (define_insn "xordi3"
1159 [(set (match_operand:DI 0 "register_operand" "=r,r")
1160 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1161 (match_operand:DI 2 "or_operand" "rI,N")))]
1166 [(set_attr "type" "ilog")])
1169 [(set (match_operand:DI 0 "register_operand" "=r")
1170 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1171 (match_operand:DI 2 "register_operand" "rI"))))]
1174 [(set_attr "type" "ilog")])
1176 ;; Handle the FFS insn iff we support CIX.
1178 ;; These didn't make it into EV6 pass 2 as planned. Instead they
1179 ;; cropped cttz/ctlz/ctpop from the old CIX and renamed it FIX for
1180 ;; "Square Root and Floating Point Convert Extension".
1182 ;; I'm assured that these insns will make it into EV67 (first pass
1183 ;; due Summer 1999), presumably with a new AMASK bit, and presumably
1184 ;; will still be named CIX.
1186 (define_expand "ffsdi2"
1188 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1190 (plus:DI (match_dup 2) (const_int 1)))
1191 (set (match_operand:DI 0 "register_operand" "")
1192 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1193 (const_int 0) (match_dup 3)))]
1197 operands[2] = gen_reg_rtx (DImode);
1198 operands[3] = gen_reg_rtx (DImode);
1202 [(set (match_operand:DI 0 "register_operand" "=r")
1203 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1206 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1207 ; reuse the existing type name.
1208 [(set_attr "type" "mvi")])
1210 ;; Next come the shifts and the various extract and insert operations.
1212 (define_insn "ashldi3"
1213 [(set (match_operand:DI 0 "register_operand" "=r,r")
1214 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1215 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1219 switch (which_alternative)
1222 if (operands[2] == const1_rtx)
1223 return \"addq %r1,%r1,%0\";
1225 return \"s%P2addq %r1,0,%0\";
1227 return \"sll %r1,%2,%0\";
1232 [(set_attr "type" "iadd,shift")])
1234 ;; ??? The following pattern is made by combine, but earlier phases
1235 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1236 ;; with this in a better way at some point.
1238 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1240 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1241 ;; (match_operand:DI 2 "const_int_operand" "P"))
1243 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1246 ;; if (operands[2] == const1_rtx)
1247 ;; return \"addl %r1,%r1,%0\";
1249 ;; return \"s%P2addl %r1,0,%0\";
1251 ;; [(set_attr "type" "iadd")])
1253 (define_insn "lshrdi3"
1254 [(set (match_operand:DI 0 "register_operand" "=r")
1255 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1256 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1259 [(set_attr "type" "shift")])
1261 (define_insn "ashrdi3"
1262 [(set (match_operand:DI 0 "register_operand" "=r")
1263 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1264 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1267 [(set_attr "type" "shift")])
1269 (define_expand "extendqihi2"
1271 (ashift:DI (match_operand:QI 1 "some_operand" "")
1273 (set (match_operand:HI 0 "register_operand" "")
1274 (ashiftrt:DI (match_dup 2)
1281 emit_insn (gen_extendqihi2x (operands[0],
1282 force_reg (QImode, operands[1])));
1286 /* If we have an unaligned MEM, extend to DImode (which we do
1287 specially) and then copy to the result. */
1288 if (unaligned_memory_operand (operands[1], HImode))
1290 rtx temp = gen_reg_rtx (DImode);
1292 emit_insn (gen_extendqidi2 (temp, operands[1]));
1293 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1297 operands[0] = gen_lowpart (DImode, operands[0]);
1298 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1299 operands[2] = gen_reg_rtx (DImode);
1302 (define_insn "extendqidi2x"
1303 [(set (match_operand:DI 0 "register_operand" "=r")
1304 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1307 [(set_attr "type" "shift")])
1309 (define_insn "extendhidi2x"
1310 [(set (match_operand:DI 0 "register_operand" "=r")
1311 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1314 [(set_attr "type" "shift")])
1316 (define_insn "extendqisi2x"
1317 [(set (match_operand:SI 0 "register_operand" "=r")
1318 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1321 [(set_attr "type" "shift")])
1323 (define_insn "extendhisi2x"
1324 [(set (match_operand:SI 0 "register_operand" "=r")
1325 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1328 [(set_attr "type" "shift")])
1330 (define_insn "extendqihi2x"
1331 [(set (match_operand:HI 0 "register_operand" "=r")
1332 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1335 [(set_attr "type" "shift")])
1337 (define_expand "extendqisi2"
1339 (ashift:DI (match_operand:QI 1 "some_operand" "")
1341 (set (match_operand:SI 0 "register_operand" "")
1342 (ashiftrt:DI (match_dup 2)
1349 emit_insn (gen_extendqisi2x (operands[0],
1350 force_reg (QImode, operands[1])));
1354 /* If we have an unaligned MEM, extend to a DImode form of
1355 the result (which we do specially). */
1356 if (unaligned_memory_operand (operands[1], QImode))
1358 rtx temp = gen_reg_rtx (DImode);
1360 emit_insn (gen_extendqidi2 (temp, operands[1]));
1361 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1365 operands[0] = gen_lowpart (DImode, operands[0]);
1366 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1367 operands[2] = gen_reg_rtx (DImode);
1370 (define_expand "extendqidi2"
1372 (ashift:DI (match_operand:QI 1 "some_operand" "")
1374 (set (match_operand:DI 0 "register_operand" "")
1375 (ashiftrt:DI (match_dup 2)
1382 emit_insn (gen_extendqidi2x (operands[0],
1383 force_reg (QImode, operands[1])));
1387 if (unaligned_memory_operand (operands[1], QImode))
1390 = gen_unaligned_extendqidi (operands[0],
1391 get_unaligned_address (operands[1], 1));
1393 alpha_set_memflags (seq, operands[1]);
1398 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1399 operands[2] = gen_reg_rtx (DImode);
1402 (define_expand "extendhisi2"
1404 (ashift:DI (match_operand:HI 1 "some_operand" "")
1406 (set (match_operand:SI 0 "register_operand" "")
1407 (ashiftrt:DI (match_dup 2)
1414 emit_insn (gen_extendhisi2x (operands[0],
1415 force_reg (HImode, operands[1])));
1419 /* If we have an unaligned MEM, extend to a DImode form of
1420 the result (which we do specially). */
1421 if (unaligned_memory_operand (operands[1], HImode))
1423 rtx temp = gen_reg_rtx (DImode);
1425 emit_insn (gen_extendhidi2 (temp, operands[1]));
1426 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1430 operands[0] = gen_lowpart (DImode, operands[0]);
1431 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1432 operands[2] = gen_reg_rtx (DImode);
1435 (define_expand "extendhidi2"
1437 (ashift:DI (match_operand:HI 1 "some_operand" "")
1439 (set (match_operand:DI 0 "register_operand" "")
1440 (ashiftrt:DI (match_dup 2)
1447 emit_insn (gen_extendhidi2x (operands[0],
1448 force_reg (HImode, operands[1])));
1452 if (unaligned_memory_operand (operands[1], HImode))
1455 = gen_unaligned_extendhidi (operands[0],
1456 get_unaligned_address (operands[1], 2));
1458 alpha_set_memflags (seq, operands[1]);
1463 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1464 operands[2] = gen_reg_rtx (DImode);
1467 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1468 ;; as a pattern saves one instruction. The code is similar to that for
1469 ;; the unaligned loads (see below).
1471 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1472 (define_expand "unaligned_extendqidi"
1473 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1475 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1478 (ashift:DI (match_dup 3)
1479 (minus:DI (const_int 64)
1481 (and:DI (match_dup 2) (const_int 7))
1483 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1484 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1487 { operands[2] = gen_reg_rtx (DImode);
1488 operands[3] = gen_reg_rtx (DImode);
1489 operands[4] = gen_reg_rtx (DImode);
1492 (define_expand "unaligned_extendhidi"
1493 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1495 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1498 (ashift:DI (match_dup 3)
1499 (minus:DI (const_int 64)
1501 (and:DI (match_dup 2) (const_int 7))
1503 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1504 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1507 { operands[2] = gen_reg_rtx (DImode);
1508 operands[3] = gen_reg_rtx (DImode);
1509 operands[4] = gen_reg_rtx (DImode);
1513 [(set (match_operand:DI 0 "register_operand" "=r")
1514 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1515 (match_operand:DI 2 "mode_width_operand" "n")
1516 (match_operand:DI 3 "mul8_operand" "I")))]
1518 "ext%M2l %r1,%s3,%0"
1519 [(set_attr "type" "shift")])
1521 (define_insn "extxl"
1522 [(set (match_operand:DI 0 "register_operand" "=r")
1523 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1524 (match_operand:DI 2 "mode_width_operand" "n")
1525 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1529 [(set_attr "type" "shift")])
1531 ;; Combine has some strange notion of preserving existing undefined behaviour
1532 ;; in shifts larger than a word size. So capture these patterns that it
1533 ;; should have turned into zero_extracts.
1536 [(set (match_operand:DI 0 "register_operand" "=r")
1537 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1538 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1540 (match_operand:DI 3 "mode_mask_operand" "n")))]
1543 [(set_attr "type" "shift")])
1546 [(set (match_operand:DI 0 "register_operand" "=r")
1547 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1548 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1552 [(set_attr "type" "shift")])
1554 (define_insn "extqh"
1555 [(set (match_operand:DI 0 "register_operand" "=r")
1557 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1558 (minus:DI (const_int 64)
1561 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1566 [(set_attr "type" "shift")])
1568 (define_insn "extlh"
1569 [(set (match_operand:DI 0 "register_operand" "=r")
1571 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1572 (const_int 2147483647))
1573 (minus:DI (const_int 64)
1576 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1581 [(set_attr "type" "shift")])
1583 (define_insn "extwh"
1584 [(set (match_operand:DI 0 "register_operand" "=r")
1586 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1588 (minus:DI (const_int 64)
1591 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1596 [(set_attr "type" "shift")])
1598 ;; This converts an extXl into an extXh with an appropriate adjustment
1599 ;; to the address calculation.
1602 ;; [(set (match_operand:DI 0 "register_operand" "")
1603 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1604 ;; (match_operand:DI 2 "mode_width_operand" "")
1605 ;; (ashift:DI (match_operand:DI 3 "" "")
1607 ;; (match_operand:DI 4 "const_int_operand" "")))
1608 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1609 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1610 ;; [(set (match_dup 5) (match_dup 6))
1611 ;; (set (match_dup 0)
1612 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1613 ;; (ashift:DI (plus:DI (match_dup 5)
1619 ;; operands[6] = plus_constant (operands[3],
1620 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1621 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1625 [(set (match_operand:DI 0 "register_operand" "=r")
1626 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1627 (match_operand:DI 2 "mul8_operand" "I")))]
1630 [(set_attr "type" "shift")])
1633 [(set (match_operand:DI 0 "register_operand" "=r")
1634 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1635 (match_operand:DI 2 "mul8_operand" "I")))]
1638 [(set_attr "type" "shift")])
1641 [(set (match_operand:DI 0 "register_operand" "=r")
1642 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1643 (match_operand:DI 2 "mul8_operand" "I")))]
1646 [(set_attr "type" "shift")])
1648 (define_insn "insbl"
1649 [(set (match_operand:DI 0 "register_operand" "=r")
1650 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1651 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1655 [(set_attr "type" "shift")])
1657 (define_insn "inswl"
1658 [(set (match_operand:DI 0 "register_operand" "=r")
1659 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1660 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1664 [(set_attr "type" "shift")])
1666 (define_insn "insll"
1667 [(set (match_operand:DI 0 "register_operand" "=r")
1668 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1669 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1673 [(set_attr "type" "shift")])
1675 (define_insn "insql"
1676 [(set (match_operand:DI 0 "register_operand" "=r")
1677 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1678 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1682 [(set_attr "type" "shift")])
1684 ;; Combine has this sometimes habit of moving the and outside of the
1685 ;; shift, making life more interesting.
1688 [(set (match_operand:DI 0 "register_operand" "=r")
1689 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1690 (match_operand:DI 2 "mul8_operand" "I"))
1691 (match_operand:DI 3 "immediate_operand" "i")))]
1692 "HOST_BITS_PER_WIDE_INT == 64
1693 && GET_CODE (operands[3]) == CONST_INT
1694 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1695 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1696 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1697 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1698 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1699 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1702 #if HOST_BITS_PER_WIDE_INT == 64
1703 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1704 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1705 return \"insbl %1,%s2,%0\";
1706 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1707 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1708 return \"inswl %1,%s2,%0\";
1709 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1710 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1711 return \"insll %1,%s2,%0\";
1715 [(set_attr "type" "shift")])
1717 ;; We do not include the insXh insns because they are complex to express
1718 ;; and it does not appear that we would ever want to generate them.
1720 ;; Since we need them for block moves, though, cop out and use unspec.
1722 (define_insn "insxh"
1723 [(set (match_operand:DI 0 "register_operand" "=r")
1724 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1725 (match_operand:DI 2 "mode_width_operand" "n")
1726 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1729 [(set_attr "type" "shift")])
1731 (define_insn "mskxl"
1732 [(set (match_operand:DI 0 "register_operand" "=r")
1733 (and:DI (not:DI (ashift:DI
1734 (match_operand:DI 2 "mode_mask_operand" "n")
1736 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1738 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1741 [(set_attr "type" "shift")])
1743 ;; We do not include the mskXh insns because it does not appear we would
1744 ;; ever generate one.
1746 ;; Again, we do for block moves and we use unspec again.
1748 (define_insn "mskxh"
1749 [(set (match_operand:DI 0 "register_operand" "=r")
1750 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1751 (match_operand:DI 2 "mode_width_operand" "n")
1752 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1755 [(set_attr "type" "shift")])
1757 ;; Floating-point operations. All the double-precision insns can extend
1758 ;; from single, so indicate that. The exception are the ones that simply
1759 ;; play with the sign bits; it's not clear what to do there.
1761 (define_insn "abssf2"
1762 [(set (match_operand:SF 0 "register_operand" "=f")
1763 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1766 [(set_attr "type" "fcpys")])
1768 (define_insn "absdf2"
1769 [(set (match_operand:DF 0 "register_operand" "=f")
1770 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1773 [(set_attr "type" "fcpys")])
1775 (define_expand "abstf2"
1776 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1777 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1778 (use (match_dup 2))])]
1779 "TARGET_HAS_XFLOATING_LIBS"
1782 #if HOST_BITS_PER_WIDE_INT >= 64
1783 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1785 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1790 [(set (match_operand:TF 0 "register_operand" "=r")
1791 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1792 (use (match_operand:DI 2 "register_operand" "=r"))]
1793 "TARGET_HAS_XFLOATING_LIBS"
1797 [(set (match_operand:TF 0 "register_operand" "")
1798 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1799 (use (match_operand:DI 4 "register_operand" ""))]
1807 alpha_split_tfmode_pair (operands);
1810 if (rtx_equal_p (operands[0], operands[2]))
1812 else if (rtx_equal_p (operands[1], operands[2]))
1816 emit_move_insn (operands[0], operands[2]);
1818 tmp = gen_rtx_NOT (DImode, operands[4]);
1819 tmp = gen_rtx_AND (DImode, tmp, operands[3]);
1820 emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
1823 emit_move_insn (operands[0], operands[2]);
1827 (define_insn "negsf2"
1828 [(set (match_operand:SF 0 "register_operand" "=f")
1829 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1832 [(set_attr "type" "fadd")])
1834 (define_insn "negdf2"
1835 [(set (match_operand:DF 0 "register_operand" "=f")
1836 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1839 [(set_attr "type" "fadd")])
1841 (define_expand "negtf2"
1842 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1843 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1844 (use (match_dup 2))])]
1845 "TARGET_HAS_XFLOATING_LIBS"
1848 #if HOST_BITS_PER_WIDE_INT >= 64
1849 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1851 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1856 [(set (match_operand:TF 0 "register_operand" "=r")
1857 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1858 (use (match_operand:DI 2 "register_operand" "=r"))]
1859 "TARGET_HAS_XFLOATING_LIBS"
1863 [(set (match_operand:TF 0 "register_operand" "")
1864 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1865 (use (match_operand:DI 4 "register_operand" ""))]
1872 alpha_split_tfmode_pair (operands);
1875 if (rtx_equal_p (operands[0], operands[2]))
1877 else if (rtx_equal_p (operands[1], operands[2]))
1881 emit_move_insn (operands[0], operands[2]);
1883 emit_insn (gen_xordi3 (operands[1], operands[3], operands[4]));
1886 emit_move_insn (operands[0], operands[2]);
1891 [(set (match_operand:SF 0 "register_operand" "=&f")
1892 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1893 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1894 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1895 "add%,%)%& %R1,%R2,%0"
1896 [(set_attr "type" "fadd")
1897 (set_attr "trap" "yes")])
1899 (define_insn "addsf3"
1900 [(set (match_operand:SF 0 "register_operand" "=f")
1901 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1902 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1904 "add%,%)%& %R1,%R2,%0"
1905 [(set_attr "type" "fadd")
1906 (set_attr "trap" "yes")])
1909 [(set (match_operand:DF 0 "register_operand" "=&f")
1910 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1911 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1912 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1913 "add%-%)%& %R1,%R2,%0"
1914 [(set_attr "type" "fadd")
1915 (set_attr "trap" "yes")])
1917 (define_insn "adddf3"
1918 [(set (match_operand:DF 0 "register_operand" "=f")
1919 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1920 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1922 "add%-%)%& %R1,%R2,%0"
1923 [(set_attr "type" "fadd")
1924 (set_attr "trap" "yes")])
1927 [(set (match_operand:DF 0 "register_operand" "=f")
1928 (plus:DF (float_extend:DF
1929 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1930 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1931 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1932 "add%-%)%& %R1,%R2,%0"
1933 [(set_attr "type" "fadd")
1934 (set_attr "trap" "yes")])
1937 [(set (match_operand:DF 0 "register_operand" "=f")
1938 (plus:DF (float_extend:DF
1939 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1941 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1942 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1943 "add%-%)%& %R1,%R2,%0"
1944 [(set_attr "type" "fadd")
1945 (set_attr "trap" "yes")])
1947 (define_expand "addtf3"
1948 [(use (match_operand 0 "register_operand" ""))
1949 (use (match_operand 1 "general_operand" ""))
1950 (use (match_operand 2 "general_operand" ""))]
1951 "TARGET_HAS_XFLOATING_LIBS"
1952 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
1954 ;; Define conversion operators between DFmode and SImode, using the cvtql
1955 ;; instruction. To allow combine et al to do useful things, we keep the
1956 ;; operation as a unit until after reload, at which point we split the
1959 ;; Note that we (attempt to) only consider this optimization when the
1960 ;; ultimate destination is memory. If we will be doing further integer
1961 ;; processing, it is cheaper to do the truncation in the int regs.
1963 (define_insn "*cvtql"
1964 [(set (match_operand:SI 0 "register_operand" "=f")
1965 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1968 [(set_attr "type" "fadd")
1969 (set_attr "trap" "yes")])
1972 [(set (match_operand:SI 0 "memory_operand" "")
1973 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1974 (clobber (match_scratch:DI 2 ""))
1975 (clobber (match_scratch:SI 3 ""))]
1976 "TARGET_FP && reload_completed"
1977 [(set (match_dup 2) (fix:DI (match_dup 1)))
1978 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1979 (set (match_dup 0) (match_dup 3))]
1983 [(set (match_operand:SI 0 "memory_operand" "")
1984 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1985 (clobber (match_scratch:DI 2 ""))]
1986 "TARGET_FP && reload_completed"
1987 [(set (match_dup 2) (fix:DI (match_dup 1)))
1988 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1989 (set (match_dup 0) (match_dup 3))]
1990 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1991 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1994 [(set (match_operand:SI 0 "memory_operand" "=m")
1995 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1996 (clobber (match_scratch:DI 2 "=&f"))
1997 (clobber (match_scratch:SI 3 "=&f"))]
1998 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2000 [(set_attr "type" "fadd")
2001 (set_attr "trap" "yes")])
2004 [(set (match_operand:SI 0 "memory_operand" "=m")
2005 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2006 (clobber (match_scratch:DI 2 "=f"))]
2007 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2009 [(set_attr "type" "fadd")
2010 (set_attr "trap" "yes")])
2013 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2014 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2015 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2017 [(set_attr "type" "fadd")
2018 (set_attr "trap" "yes")])
2020 (define_insn "fix_truncdfdi2"
2021 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2022 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2025 [(set_attr "type" "fadd")
2026 (set_attr "trap" "yes")])
2028 ;; Likewise between SFmode and SImode.
2031 [(set (match_operand:SI 0 "memory_operand" "")
2032 (subreg:SI (fix:DI (float_extend:DF
2033 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2034 (clobber (match_scratch:DI 2 ""))
2035 (clobber (match_scratch:SI 3 ""))]
2036 "TARGET_FP && reload_completed"
2037 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2038 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2039 (set (match_dup 0) (match_dup 3))]
2043 [(set (match_operand:SI 0 "memory_operand" "")
2044 (subreg:SI (fix:DI (float_extend:DF
2045 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
2046 (clobber (match_scratch:DI 2 ""))]
2047 "TARGET_FP && reload_completed"
2048 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2049 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2050 (set (match_dup 0) (match_dup 3))]
2051 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2052 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2055 [(set (match_operand:SI 0 "memory_operand" "=m")
2056 (subreg:SI (fix:DI (float_extend:DF
2057 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2058 (clobber (match_scratch:DI 2 "=&f"))
2059 (clobber (match_scratch:SI 3 "=&f"))]
2060 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2062 [(set_attr "type" "fadd")
2063 (set_attr "trap" "yes")])
2066 [(set (match_operand:SI 0 "memory_operand" "=m")
2067 (subreg:SI (fix:DI (float_extend:DF
2068 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2069 (clobber (match_scratch:DI 2 "=f"))]
2070 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2072 [(set_attr "type" "fadd")
2073 (set_attr "trap" "yes")])
2076 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2077 (fix:DI (float_extend:DF
2078 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2079 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2081 [(set_attr "type" "fadd")
2082 (set_attr "trap" "yes")])
2084 (define_insn "fix_truncsfdi2"
2085 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2086 (fix:DI (float_extend:DF
2087 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2090 [(set_attr "type" "fadd")
2091 (set_attr "trap" "yes")])
2093 (define_expand "fix_trunctfdi2"
2094 [(use (match_operand:DI 0 "register_operand" ""))
2095 (use (match_operand:TF 1 "general_operand" ""))]
2096 "TARGET_HAS_XFLOATING_LIBS"
2097 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2100 [(set (match_operand:SF 0 "register_operand" "=&f")
2101 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2102 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2104 [(set_attr "type" "fadd")
2105 (set_attr "trap" "yes")])
2107 (define_insn "floatdisf2"
2108 [(set (match_operand:SF 0 "register_operand" "=f")
2109 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2112 [(set_attr "type" "fadd")
2113 (set_attr "trap" "yes")])
2116 [(set (match_operand:DF 0 "register_operand" "=&f")
2117 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2118 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2120 [(set_attr "type" "fadd")
2121 (set_attr "trap" "yes")])
2123 (define_insn "floatdidf2"
2124 [(set (match_operand:DF 0 "register_operand" "=f")
2125 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2128 [(set_attr "type" "fadd")
2129 (set_attr "trap" "yes")])
2131 (define_expand "floatditf2"
2132 [(use (match_operand:TF 0 "register_operand" ""))
2133 (use (match_operand:DI 1 "general_operand" ""))]
2134 "TARGET_HAS_XFLOATING_LIBS"
2135 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2137 (define_expand "floatunsdisf2"
2138 [(use (match_operand:SF 0 "register_operand" ""))
2139 (use (match_operand:DI 1 "register_operand" ""))]
2141 "alpha_emit_floatuns (operands); DONE;")
2143 (define_expand "floatunsdidf2"
2144 [(use (match_operand:DF 0 "register_operand" ""))
2145 (use (match_operand:DI 1 "register_operand" ""))]
2147 "alpha_emit_floatuns (operands); DONE;")
2149 (define_expand "floatunsditf2"
2150 [(use (match_operand:TF 0 "register_operand" ""))
2151 (use (match_operand:DI 1 "general_operand" ""))]
2152 "TARGET_HAS_XFLOATING_LIBS"
2153 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2155 (define_expand "extendsfdf2"
2156 [(set (match_operand:DF 0 "register_operand" "")
2157 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2161 if (alpha_fptm >= ALPHA_FPTM_SU)
2162 operands[1] = force_reg (SFmode, operands[1]);
2166 [(set (match_operand:DF 0 "register_operand" "=&f")
2167 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2168 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2170 [(set_attr "type" "fadd")
2171 (set_attr "trap" "yes")])
2174 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2175 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2176 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2181 [(set_attr "type" "fcpys,fld,fst")])
2183 (define_expand "extendsftf2"
2184 [(use (match_operand:TF 0 "register_operand" ""))
2185 (use (match_operand:SF 1 "general_operand" ""))]
2186 "TARGET_HAS_XFLOATING_LIBS"
2189 rtx tmp = gen_reg_rtx (DFmode);
2190 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2191 emit_insn (gen_extenddftf2 (operands[0], tmp));
2195 (define_expand "extenddftf2"
2196 [(use (match_operand:TF 0 "register_operand" ""))
2197 (use (match_operand:DF 1 "general_operand" ""))]
2198 "TARGET_HAS_XFLOATING_LIBS"
2199 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2202 [(set (match_operand:SF 0 "register_operand" "=&f")
2203 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2204 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2205 "cvt%-%,%)%& %R1,%0"
2206 [(set_attr "type" "fadd")
2207 (set_attr "trap" "yes")])
2209 (define_insn "truncdfsf2"
2210 [(set (match_operand:SF 0 "register_operand" "=f")
2211 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2213 "cvt%-%,%)%& %R1,%0"
2214 [(set_attr "type" "fadd")
2215 (set_attr "trap" "yes")])
2217 (define_expand "trunctfdf2"
2218 [(use (match_operand:DF 0 "register_operand" ""))
2219 (use (match_operand:TF 1 "general_operand" ""))]
2220 "TARGET_HAS_XFLOATING_LIBS"
2221 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2223 (define_expand "trunctfsf2"
2224 [(use (match_operand:SF 0 "register_operand" ""))
2225 (use (match_operand:TF 1 "general_operand" ""))]
2226 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2229 rtx tmpf, sticky, arg, lo, hi;
2231 tmpf = gen_reg_rtx (DFmode);
2232 sticky = gen_reg_rtx (DImode);
2233 arg = copy_to_mode_reg (TFmode, operands[1]);
2234 lo = gen_lowpart (DImode, arg);
2235 hi = gen_highpart (DImode, arg);
2237 /* Convert the low word of the TFmode value into a sticky rounding bit,
2238 then or it into the low bit of the high word. This leaves the sticky
2239 bit at bit 48 of the fraction, which is representable in DFmode,
2240 which prevents rounding error in the final conversion to SFmode. */
2242 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2243 gen_rtx_NE (DImode, lo, const0_rtx)));
2244 emit_insn (gen_iordi3 (hi, hi, sticky));
2245 emit_insn (gen_trunctfdf2 (tmpf, arg));
2246 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2251 [(set (match_operand:SF 0 "register_operand" "=&f")
2252 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2253 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2254 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2255 "div%,%)%& %R1,%R2,%0"
2256 [(set_attr "type" "fdiv")
2257 (set_attr "opsize" "si")
2258 (set_attr "trap" "yes")])
2260 (define_insn "divsf3"
2261 [(set (match_operand:SF 0 "register_operand" "=f")
2262 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2263 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2265 "div%,%)%& %R1,%R2,%0"
2266 [(set_attr "type" "fdiv")
2267 (set_attr "opsize" "si")
2268 (set_attr "trap" "yes")])
2271 [(set (match_operand:DF 0 "register_operand" "=&f")
2272 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2273 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2274 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2275 "div%-%)%& %R1,%R2,%0"
2276 [(set_attr "type" "fdiv")
2277 (set_attr "trap" "yes")])
2279 (define_insn "divdf3"
2280 [(set (match_operand:DF 0 "register_operand" "=f")
2281 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2282 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2284 "div%-%)%& %R1,%R2,%0"
2285 [(set_attr "type" "fdiv")
2286 (set_attr "trap" "yes")])
2289 [(set (match_operand:DF 0 "register_operand" "=f")
2290 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2291 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2292 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2293 "div%-%)%& %R1,%R2,%0"
2294 [(set_attr "type" "fdiv")
2295 (set_attr "trap" "yes")])
2298 [(set (match_operand:DF 0 "register_operand" "=f")
2299 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2301 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2302 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2303 "div%-%)%& %R1,%R2,%0"
2304 [(set_attr "type" "fdiv")
2305 (set_attr "trap" "yes")])
2308 [(set (match_operand:DF 0 "register_operand" "=f")
2309 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2310 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2311 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2312 "div%-%)%& %R1,%R2,%0"
2313 [(set_attr "type" "fdiv")
2314 (set_attr "trap" "yes")])
2316 (define_expand "divtf3"
2317 [(use (match_operand 0 "register_operand" ""))
2318 (use (match_operand 1 "general_operand" ""))
2319 (use (match_operand 2 "general_operand" ""))]
2320 "TARGET_HAS_XFLOATING_LIBS"
2321 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2324 [(set (match_operand:SF 0 "register_operand" "=&f")
2325 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2326 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2327 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2328 "mul%,%)%& %R1,%R2,%0"
2329 [(set_attr "type" "fmul")
2330 (set_attr "trap" "yes")])
2332 (define_insn "mulsf3"
2333 [(set (match_operand:SF 0 "register_operand" "=f")
2334 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2335 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2337 "mul%,%)%& %R1,%R2,%0"
2338 [(set_attr "type" "fmul")
2339 (set_attr "trap" "yes")])
2342 [(set (match_operand:DF 0 "register_operand" "=&f")
2343 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2344 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2345 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2346 "mul%-%)%& %R1,%R2,%0"
2347 [(set_attr "type" "fmul")
2348 (set_attr "trap" "yes")])
2350 (define_insn "muldf3"
2351 [(set (match_operand:DF 0 "register_operand" "=f")
2352 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2353 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2355 "mul%-%)%& %R1,%R2,%0"
2356 [(set_attr "type" "fmul")
2357 (set_attr "trap" "yes")])
2360 [(set (match_operand:DF 0 "register_operand" "=f")
2361 (mult:DF (float_extend:DF
2362 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2363 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2364 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2365 "mul%-%)%& %R1,%R2,%0"
2366 [(set_attr "type" "fmul")
2367 (set_attr "trap" "yes")])
2370 [(set (match_operand:DF 0 "register_operand" "=f")
2371 (mult:DF (float_extend:DF
2372 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2374 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2375 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2376 "mul%-%)%& %R1,%R2,%0"
2377 [(set_attr "type" "fmul")
2378 (set_attr "trap" "yes")])
2380 (define_expand "multf3"
2381 [(use (match_operand 0 "register_operand" ""))
2382 (use (match_operand 1 "general_operand" ""))
2383 (use (match_operand 2 "general_operand" ""))]
2384 "TARGET_HAS_XFLOATING_LIBS"
2385 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2388 [(set (match_operand:SF 0 "register_operand" "=&f")
2389 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2390 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2391 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2392 "sub%,%)%& %R1,%R2,%0"
2393 [(set_attr "type" "fadd")
2394 (set_attr "trap" "yes")])
2396 (define_insn "subsf3"
2397 [(set (match_operand:SF 0 "register_operand" "=f")
2398 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2399 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2401 "sub%,%)%& %R1,%R2,%0"
2402 [(set_attr "type" "fadd")
2403 (set_attr "trap" "yes")])
2406 [(set (match_operand:DF 0 "register_operand" "=&f")
2407 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2408 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2409 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2410 "sub%-%)%& %R1,%R2,%0"
2411 [(set_attr "type" "fadd")
2412 (set_attr "trap" "yes")])
2414 (define_insn "subdf3"
2415 [(set (match_operand:DF 0 "register_operand" "=f")
2416 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2417 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2419 "sub%-%)%& %R1,%R2,%0"
2420 [(set_attr "type" "fadd")
2421 (set_attr "trap" "yes")])
2424 [(set (match_operand:DF 0 "register_operand" "=f")
2425 (minus:DF (float_extend:DF
2426 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2427 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2428 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2429 "sub%-%)%& %R1,%R2,%0"
2430 [(set_attr "type" "fadd")
2431 (set_attr "trap" "yes")])
2434 [(set (match_operand:DF 0 "register_operand" "=f")
2435 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2437 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2438 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2439 "sub%-%)%& %R1,%R2,%0"
2440 [(set_attr "type" "fadd")
2441 (set_attr "trap" "yes")])
2444 [(set (match_operand:DF 0 "register_operand" "=f")
2445 (minus:DF (float_extend:DF
2446 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2448 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2449 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2450 "sub%-%)%& %R1,%R2,%0"
2451 [(set_attr "type" "fadd")
2452 (set_attr "trap" "yes")])
2454 (define_expand "subtf3"
2455 [(use (match_operand 0 "register_operand" ""))
2456 (use (match_operand 1 "general_operand" ""))
2457 (use (match_operand 2 "general_operand" ""))]
2458 "TARGET_HAS_XFLOATING_LIBS"
2459 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2462 [(set (match_operand:SF 0 "register_operand" "=&f")
2463 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2464 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2466 [(set_attr "type" "fsqrt")
2467 (set_attr "opsize" "si")
2468 (set_attr "trap" "yes")])
2470 (define_insn "sqrtsf2"
2471 [(set (match_operand:SF 0 "register_operand" "=f")
2472 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2473 "TARGET_FP && TARGET_FIX"
2475 [(set_attr "type" "fsqrt")
2476 (set_attr "opsize" "si")
2477 (set_attr "trap" "yes")])
2480 [(set (match_operand:DF 0 "register_operand" "=&f")
2481 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2482 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2484 [(set_attr "type" "fsqrt")
2485 (set_attr "trap" "yes")])
2487 (define_insn "sqrtdf2"
2488 [(set (match_operand:DF 0 "register_operand" "=f")
2489 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2490 "TARGET_FP && TARGET_FIX"
2492 [(set_attr "type" "fsqrt")
2493 (set_attr "trap" "yes")])
2495 ;; Next are all the integer comparisons, and conditional moves and branches
2496 ;; and some of the related define_expand's and define_split's.
2499 [(set (match_operand:DI 0 "register_operand" "=r")
2500 (ne:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")
2504 [(set_attr "type" "icmp")])
2507 [(set (match_operand:DI 0 "register_operand" "=r")
2508 (match_operator:DI 1 "alpha_comparison_operator"
2509 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2510 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2513 [(set_attr "type" "icmp")])
2516 [(set (match_operand:DI 0 "register_operand" "=r")
2517 (match_operator:DI 1 "alpha_swapped_comparison_operator"
2518 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2519 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2522 [(set_attr "type" "icmp")])
2524 ;; This pattern exists so conditional moves of SImode values are handled.
2525 ;; Comparisons are still done in DImode though.
2528 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2530 (match_operator 2 "signed_comparison_operator"
2531 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2532 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2533 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2534 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2535 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2541 [(set_attr "type" "icmov")])
2544 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2546 (match_operator 2 "signed_comparison_operator"
2547 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2548 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2549 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2550 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2551 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2557 [(set_attr "type" "icmov")])
2560 [(set (match_operand:DI 0 "register_operand" "=r,r")
2562 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2566 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2567 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2572 [(set_attr "type" "icmov")])
2575 [(set (match_operand:DI 0 "register_operand" "=r,r")
2577 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2581 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2582 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2587 [(set_attr "type" "icmov")])
2589 ;; For ABS, we have two choices, depending on whether the input and output
2590 ;; registers are the same or not.
2591 (define_expand "absdi2"
2592 [(set (match_operand:DI 0 "register_operand" "")
2593 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2596 { if (rtx_equal_p (operands[0], operands[1]))
2597 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2599 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2604 (define_expand "absdi2_same"
2605 [(set (match_operand:DI 1 "register_operand" "")
2606 (neg:DI (match_operand:DI 0 "register_operand" "")))
2608 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2614 (define_expand "absdi2_diff"
2615 [(set (match_operand:DI 0 "register_operand" "")
2616 (neg:DI (match_operand:DI 1 "register_operand" "")))
2618 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2625 [(set (match_operand:DI 0 "register_operand" "")
2626 (abs:DI (match_dup 0)))
2627 (clobber (match_operand:DI 2 "register_operand" ""))]
2629 [(set (match_dup 1) (neg:DI (match_dup 0)))
2630 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2631 (match_dup 0) (match_dup 1)))]
2635 [(set (match_operand:DI 0 "register_operand" "")
2636 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2637 "! rtx_equal_p (operands[0], operands[1])"
2638 [(set (match_dup 0) (neg:DI (match_dup 1)))
2639 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2640 (match_dup 0) (match_dup 1)))]
2644 [(set (match_operand:DI 0 "register_operand" "")
2645 (neg:DI (abs:DI (match_dup 0))))
2646 (clobber (match_operand:DI 2 "register_operand" ""))]
2648 [(set (match_dup 1) (neg:DI (match_dup 0)))
2649 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2650 (match_dup 0) (match_dup 1)))]
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2656 "! rtx_equal_p (operands[0], operands[1])"
2657 [(set (match_dup 0) (neg:DI (match_dup 1)))
2658 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2659 (match_dup 0) (match_dup 1)))]
2662 (define_insn "sminqi3"
2663 [(set (match_operand:QI 0 "register_operand" "=r")
2664 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2665 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2668 [(set_attr "type" "mvi")])
2670 (define_insn "uminqi3"
2671 [(set (match_operand:QI 0 "register_operand" "=r")
2672 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2673 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2676 [(set_attr "type" "mvi")])
2678 (define_insn "smaxqi3"
2679 [(set (match_operand:QI 0 "register_operand" "=r")
2680 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2681 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2684 [(set_attr "type" "mvi")])
2686 (define_insn "umaxqi3"
2687 [(set (match_operand:QI 0 "register_operand" "=r")
2688 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2689 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2692 [(set_attr "type" "mvi")])
2694 (define_insn "sminhi3"
2695 [(set (match_operand:HI 0 "register_operand" "=r")
2696 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2697 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2700 [(set_attr "type" "mvi")])
2702 (define_insn "uminhi3"
2703 [(set (match_operand:HI 0 "register_operand" "=r")
2704 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2705 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2708 [(set_attr "type" "mvi")])
2710 (define_insn "smaxhi3"
2711 [(set (match_operand:HI 0 "register_operand" "=r")
2712 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2713 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2716 [(set_attr "type" "mvi")])
2718 (define_insn "umaxhi3"
2719 [(set (match_operand:HI 0 "register_operand" "=r")
2720 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2721 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2724 [(set_attr "type" "shift")])
2726 (define_expand "smaxdi3"
2728 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2729 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2730 (set (match_operand:DI 0 "register_operand" "")
2731 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2732 (match_dup 1) (match_dup 2)))]
2735 { operands[3] = gen_reg_rtx (DImode);
2739 [(set (match_operand:DI 0 "register_operand" "")
2740 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2741 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2742 (clobber (match_operand:DI 3 "register_operand" ""))]
2743 "operands[2] != const0_rtx"
2744 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2745 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2746 (match_dup 1) (match_dup 2)))]
2750 [(set (match_operand:DI 0 "register_operand" "=r")
2751 (smax:DI (match_operand:DI 1 "register_operand" "0")
2755 [(set_attr "type" "icmov")])
2757 (define_expand "smindi3"
2759 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2760 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2761 (set (match_operand:DI 0 "register_operand" "")
2762 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2763 (match_dup 1) (match_dup 2)))]
2766 { operands[3] = gen_reg_rtx (DImode);
2770 [(set (match_operand:DI 0 "register_operand" "")
2771 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2772 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2773 (clobber (match_operand:DI 3 "register_operand" ""))]
2774 "operands[2] != const0_rtx"
2775 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2776 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2777 (match_dup 1) (match_dup 2)))]
2781 [(set (match_operand:DI 0 "register_operand" "=r")
2782 (smin:DI (match_operand:DI 1 "register_operand" "0")
2786 [(set_attr "type" "icmov")])
2788 (define_expand "umaxdi3"
2790 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2791 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2792 (set (match_operand:DI 0 "register_operand" "")
2793 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2794 (match_dup 1) (match_dup 2)))]
2797 { operands[3] = gen_reg_rtx (DImode);
2801 [(set (match_operand:DI 0 "register_operand" "")
2802 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2803 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2804 (clobber (match_operand:DI 3 "register_operand" ""))]
2805 "operands[2] != const0_rtx"
2806 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2807 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2808 (match_dup 1) (match_dup 2)))]
2811 (define_expand "umindi3"
2813 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2814 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2815 (set (match_operand:DI 0 "register_operand" "")
2816 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2817 (match_dup 1) (match_dup 2)))]
2820 { operands[3] = gen_reg_rtx (DImode);
2824 [(set (match_operand:DI 0 "register_operand" "")
2825 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2826 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2827 (clobber (match_operand:DI 3 "register_operand" ""))]
2828 "operands[2] != const0_rtx"
2829 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2830 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2831 (match_dup 1) (match_dup 2)))]
2837 (match_operator 1 "signed_comparison_operator"
2838 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2840 (label_ref (match_operand 0 "" ""))
2844 [(set_attr "type" "ibr")])
2849 (match_operator 1 "signed_comparison_operator"
2851 (match_operand:DI 2 "register_operand" "r")])
2852 (label_ref (match_operand 0 "" ""))
2856 [(set_attr "type" "ibr")])
2861 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2865 (label_ref (match_operand 0 "" ""))
2869 [(set_attr "type" "ibr")])
2874 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2878 (label_ref (match_operand 0 "" ""))
2882 [(set_attr "type" "ibr")])
2888 (match_operator 1 "comparison_operator"
2889 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2891 (match_operand:DI 3 "const_int_operand" ""))
2893 (label_ref (match_operand 0 "" ""))
2895 (clobber (match_operand:DI 4 "register_operand" ""))])]
2896 "INTVAL (operands[3]) != 0"
2898 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2900 (if_then_else (match_op_dup 1
2901 [(zero_extract:DI (match_dup 4)
2905 (label_ref (match_dup 0))
2909 ;; The following are the corresponding floating-point insns. Recall
2910 ;; we need to have variants that expand the arguments from SFmode
2913 (define_insn "*cmpdf_tp"
2914 [(set (match_operand:DF 0 "register_operand" "=&f")
2915 (match_operator:DF 1 "alpha_fp_comparison_operator"
2916 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2917 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2918 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2919 "cmp%-%C1%' %R2,%R3,%0"
2920 [(set_attr "type" "fadd")
2921 (set_attr "trap" "yes")])
2923 (define_insn "*cmpdf_no_tp"
2924 [(set (match_operand:DF 0 "register_operand" "=f")
2925 (match_operator:DF 1 "alpha_fp_comparison_operator"
2926 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2927 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2928 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2929 "cmp%-%C1%' %R2,%R3,%0"
2930 [(set_attr "type" "fadd")
2931 (set_attr "trap" "yes")])
2934 [(set (match_operand:DF 0 "register_operand" "=&f")
2935 (match_operator:DF 1 "alpha_fp_comparison_operator"
2937 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2938 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2939 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2940 "cmp%-%C1%' %R2,%R3,%0"
2941 [(set_attr "type" "fadd")
2942 (set_attr "trap" "yes")])
2945 [(set (match_operand:DF 0 "register_operand" "=f")
2946 (match_operator:DF 1 "alpha_fp_comparison_operator"
2948 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2949 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2950 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2951 "cmp%-%C1%' %R2,%R3,%0"
2952 [(set_attr "type" "fadd")
2953 (set_attr "trap" "yes")])
2956 [(set (match_operand:DF 0 "register_operand" "=&f")
2957 (match_operator:DF 1 "alpha_fp_comparison_operator"
2958 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2960 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2961 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2962 "cmp%-%C1%' %R2,%R3,%0"
2963 [(set_attr "type" "fadd")
2964 (set_attr "trap" "yes")])
2967 [(set (match_operand:DF 0 "register_operand" "=f")
2968 (match_operator:DF 1 "alpha_fp_comparison_operator"
2969 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2971 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2972 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2973 "cmp%-%C1%' %R2,%R3,%0"
2974 [(set_attr "type" "fadd")
2975 (set_attr "trap" "yes")])
2978 [(set (match_operand:DF 0 "register_operand" "=&f")
2979 (match_operator:DF 1 "alpha_fp_comparison_operator"
2981 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2983 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2984 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2985 "cmp%-%C1%' %R2,%R3,%0"
2986 [(set_attr "type" "fadd")
2987 (set_attr "trap" "yes")])
2990 [(set (match_operand:DF 0 "register_operand" "=f")
2991 (match_operator:DF 1 "alpha_fp_comparison_operator"
2993 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2995 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2996 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2997 "cmp%-%C1%' %R2,%R3,%0"
2998 [(set_attr "type" "fadd")
2999 (set_attr "trap" "yes")])
3002 [(set (match_operand:DF 0 "register_operand" "=f,f")
3004 (match_operator 3 "signed_comparison_operator"
3005 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3006 (match_operand:DF 2 "fp0_operand" "G,G")])
3007 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3008 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3012 fcmov%D3 %R4,%R5,%0"
3013 [(set_attr "type" "fcmov")])
3016 [(set (match_operand:SF 0 "register_operand" "=f,f")
3018 (match_operator 3 "signed_comparison_operator"
3019 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3020 (match_operand:DF 2 "fp0_operand" "G,G")])
3021 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3022 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3026 fcmov%D3 %R4,%R5,%0"
3027 [(set_attr "type" "fcmov")])
3030 [(set (match_operand:DF 0 "register_operand" "=f,f")
3032 (match_operator 3 "signed_comparison_operator"
3033 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3034 (match_operand:DF 2 "fp0_operand" "G,G")])
3035 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3036 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3040 fcmov%D3 %R4,%R5,%0"
3041 [(set_attr "type" "fcmov")])
3044 [(set (match_operand:DF 0 "register_operand" "=f,f")
3046 (match_operator 3 "signed_comparison_operator"
3048 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3049 (match_operand:DF 2 "fp0_operand" "G,G")])
3050 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3051 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3055 fcmov%D3 %R4,%R5,%0"
3056 [(set_attr "type" "fcmov")])
3059 [(set (match_operand:SF 0 "register_operand" "=f,f")
3061 (match_operator 3 "signed_comparison_operator"
3063 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3064 (match_operand:DF 2 "fp0_operand" "G,G")])
3065 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3066 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3070 fcmov%D3 %R4,%R5,%0"
3071 [(set_attr "type" "fcmov")])
3074 [(set (match_operand:DF 0 "register_operand" "=f,f")
3076 (match_operator 3 "signed_comparison_operator"
3078 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3079 (match_operand:DF 2 "fp0_operand" "G,G")])
3080 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3081 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3085 fcmov%D3 %R4,%R5,%0"
3086 [(set_attr "type" "fcmov")])
3088 (define_expand "maxdf3"
3090 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3091 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3092 (set (match_operand:DF 0 "register_operand" "")
3093 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3094 (match_dup 1) (match_dup 2)))]
3097 { operands[3] = gen_reg_rtx (DFmode);
3098 operands[4] = CONST0_RTX (DFmode);
3101 (define_expand "mindf3"
3103 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3104 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3105 (set (match_operand:DF 0 "register_operand" "")
3106 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3107 (match_dup 1) (match_dup 2)))]
3110 { operands[3] = gen_reg_rtx (DFmode);
3111 operands[4] = CONST0_RTX (DFmode);
3114 (define_expand "maxsf3"
3116 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3117 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3118 (set (match_operand:SF 0 "register_operand" "")
3119 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3120 (match_dup 1) (match_dup 2)))]
3123 { operands[3] = gen_reg_rtx (DFmode);
3124 operands[4] = CONST0_RTX (DFmode);
3127 (define_expand "minsf3"
3129 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3130 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3131 (set (match_operand:SF 0 "register_operand" "")
3132 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3133 (match_dup 1) (match_dup 2)))]
3136 { operands[3] = gen_reg_rtx (DFmode);
3137 operands[4] = CONST0_RTX (DFmode);
3143 (match_operator 1 "signed_comparison_operator"
3144 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3145 (match_operand:DF 3 "fp0_operand" "G")])
3146 (label_ref (match_operand 0 "" ""))
3150 [(set_attr "type" "fbr")])
3155 (match_operator 1 "signed_comparison_operator"
3157 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3158 (match_operand:DF 3 "fp0_operand" "G")])
3159 (label_ref (match_operand 0 "" ""))
3163 [(set_attr "type" "fbr")])
3165 ;; These are the main define_expand's used to make conditional branches
3168 (define_expand "cmpdf"
3169 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3170 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3174 alpha_compare.op0 = operands[0];
3175 alpha_compare.op1 = operands[1];
3176 alpha_compare.fp_p = 1;
3180 (define_expand "cmptf"
3181 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3182 (match_operand:TF 1 "general_operand" "")))]
3183 "TARGET_HAS_XFLOATING_LIBS"
3186 alpha_compare.op0 = operands[0];
3187 alpha_compare.op1 = operands[1];
3188 alpha_compare.fp_p = 1;
3192 (define_expand "cmpdi"
3193 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3194 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3198 alpha_compare.op0 = operands[0];
3199 alpha_compare.op1 = operands[1];
3200 alpha_compare.fp_p = 0;
3204 (define_expand "beq"
3206 (if_then_else (match_dup 1)
3207 (label_ref (match_operand 0 "" ""))
3210 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3212 (define_expand "bne"
3214 (if_then_else (match_dup 1)
3215 (label_ref (match_operand 0 "" ""))
3218 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3220 (define_expand "blt"
3222 (if_then_else (match_dup 1)
3223 (label_ref (match_operand 0 "" ""))
3226 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3228 (define_expand "ble"
3230 (if_then_else (match_dup 1)
3231 (label_ref (match_operand 0 "" ""))
3234 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3236 (define_expand "bgt"
3238 (if_then_else (match_dup 1)
3239 (label_ref (match_operand 0 "" ""))
3242 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3244 (define_expand "bge"
3246 (if_then_else (match_dup 1)
3247 (label_ref (match_operand 0 "" ""))
3250 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3252 (define_expand "bltu"
3254 (if_then_else (match_dup 1)
3255 (label_ref (match_operand 0 "" ""))
3258 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3260 (define_expand "bleu"
3262 (if_then_else (match_dup 1)
3263 (label_ref (match_operand 0 "" ""))
3266 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3268 (define_expand "bgtu"
3270 (if_then_else (match_dup 1)
3271 (label_ref (match_operand 0 "" ""))
3274 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3276 (define_expand "bgeu"
3278 (if_then_else (match_dup 1)
3279 (label_ref (match_operand 0 "" ""))
3282 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3284 (define_expand "bunordered"
3286 (if_then_else (match_dup 1)
3287 (label_ref (match_operand 0 "" ""))
3290 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3292 (define_expand "bordered"
3294 (if_then_else (match_dup 1)
3295 (label_ref (match_operand 0 "" ""))
3298 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3300 (define_expand "seq"
3301 [(set (match_operand:DI 0 "register_operand" "")
3306 if (alpha_compare.fp_p)
3309 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3310 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3313 (define_expand "sne"
3314 [(set (match_operand:DI 0 "register_operand" "")
3316 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3320 if (alpha_compare.fp_p)
3323 if (alpha_compare.op1 == const0_rtx)
3325 operands[1] = gen_rtx_NE (DImode, alpha_compare.op0, alpha_compare.op1);
3326 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3327 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3331 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3332 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3335 (define_expand "slt"
3336 [(set (match_operand:DI 0 "register_operand" "")
3341 if (alpha_compare.fp_p)
3344 operands[1] = gen_rtx_LT (DImode, alpha_compare.op0, alpha_compare.op1);
3345 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3348 (define_expand "sle"
3349 [(set (match_operand:DI 0 "register_operand" "")
3354 if (alpha_compare.fp_p)
3357 operands[1] = gen_rtx_LE (DImode, alpha_compare.op0, alpha_compare.op1);
3358 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3361 (define_expand "sgt"
3362 [(set (match_operand:DI 0 "register_operand" "")
3367 if (alpha_compare.fp_p)
3370 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare.op1),
3372 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3375 (define_expand "sge"
3376 [(set (match_operand:DI 0 "register_operand" "")
3381 if (alpha_compare.fp_p)
3384 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare.op1),
3386 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3389 (define_expand "sltu"
3390 [(set (match_operand:DI 0 "register_operand" "")
3395 if (alpha_compare.fp_p)
3398 operands[1] = gen_rtx_LTU (DImode, alpha_compare.op0, alpha_compare.op1);
3399 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3402 (define_expand "sleu"
3403 [(set (match_operand:DI 0 "register_operand" "")
3408 if (alpha_compare.fp_p)
3411 operands[1] = gen_rtx_LEU (DImode, alpha_compare.op0, alpha_compare.op1);
3412 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3415 (define_expand "sgtu"
3416 [(set (match_operand:DI 0 "register_operand" "")
3421 if (alpha_compare.fp_p)
3424 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare.op1),
3426 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3429 (define_expand "sgeu"
3430 [(set (match_operand:DI 0 "register_operand" "")
3435 if (alpha_compare.fp_p)
3438 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare.op1),
3440 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3443 ;; These are the main define_expand's used to make conditional moves.
3445 (define_expand "movsicc"
3446 [(set (match_operand:SI 0 "register_operand" "")
3447 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3448 (match_operand:SI 2 "reg_or_8bit_operand" "")
3449 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3453 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3457 (define_expand "movdicc"
3458 [(set (match_operand:DI 0 "register_operand" "")
3459 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3460 (match_operand:DI 2 "reg_or_8bit_operand" "")
3461 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3465 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3469 (define_expand "movsfcc"
3470 [(set (match_operand:SF 0 "register_operand" "")
3471 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3472 (match_operand:SF 2 "reg_or_8bit_operand" "")
3473 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3477 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3481 (define_expand "movdfcc"
3482 [(set (match_operand:DF 0 "register_operand" "")
3483 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3484 (match_operand:DF 2 "reg_or_8bit_operand" "")
3485 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3489 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3493 ;; These define_split definitions are used in cases when comparisons have
3494 ;; not be stated in the correct way and we need to reverse the second
3495 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3496 ;; comparison that tests the result being reversed. We have one define_split
3497 ;; for each use of a comparison. They do not match valid insns and need
3498 ;; not generate valid insns.
3500 ;; We can also handle equality comparisons (and inequality comparisons in
3501 ;; cases where the resulting add cannot overflow) by doing an add followed by
3502 ;; a comparison with zero. This is faster since the addition takes one
3503 ;; less cycle than a compare when feeding into a conditional move.
3504 ;; For this case, we also have an SImode pattern since we can merge the add
3505 ;; and sign extend and the order doesn't matter.
3507 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3508 ;; operation could have been generated.
3511 [(set (match_operand:DI 0 "register_operand" "")
3513 (match_operator 1 "comparison_operator"
3514 [(match_operand:DI 2 "reg_or_0_operand" "")
3515 (match_operand:DI 3 "reg_or_cint_operand" "")])
3516 (match_operand:DI 4 "reg_or_cint_operand" "")
3517 (match_operand:DI 5 "reg_or_cint_operand" "")))
3518 (clobber (match_operand:DI 6 "register_operand" ""))]
3519 "operands[3] != const0_rtx"
3520 [(set (match_dup 6) (match_dup 7))
3522 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3524 { enum rtx_code code = GET_CODE (operands[1]);
3525 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3527 /* If we are comparing for equality with a constant and that constant
3528 appears in the arm when the register equals the constant, use the
3529 register since that is more likely to match (and to produce better code
3532 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3533 && rtx_equal_p (operands[4], operands[3]))
3534 operands[4] = operands[2];
3536 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3537 && rtx_equal_p (operands[5], operands[3]))
3538 operands[5] = operands[2];
3540 if (code == NE || code == EQ
3541 || (extended_count (operands[2], DImode, unsignedp) >= 1
3542 && extended_count (operands[3], DImode, unsignedp) >= 1))
3544 if (GET_CODE (operands[3]) == CONST_INT)
3545 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3546 GEN_INT (- INTVAL (operands[3])));
3548 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3550 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3553 else if (code == EQ || code == LE || code == LT
3554 || code == LEU || code == LTU)
3556 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3557 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3561 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3562 operands[2], operands[3]);
3563 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3568 [(set (match_operand:DI 0 "register_operand" "")
3570 (match_operator 1 "comparison_operator"
3571 [(match_operand:SI 2 "reg_or_0_operand" "")
3572 (match_operand:SI 3 "reg_or_cint_operand" "")])
3573 (match_operand:DI 4 "reg_or_8bit_operand" "")
3574 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3575 (clobber (match_operand:DI 6 "register_operand" ""))]
3576 "operands[3] != const0_rtx
3577 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3578 [(set (match_dup 6) (match_dup 7))
3580 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3582 { enum rtx_code code = GET_CODE (operands[1]);
3583 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3586 if ((code != NE && code != EQ
3587 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3588 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3591 if (GET_CODE (operands[3]) == CONST_INT)
3592 tem = gen_rtx_PLUS (SImode, operands[2],
3593 GEN_INT (- INTVAL (operands[3])));
3595 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3597 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3598 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3599 operands[6], const0_rtx);
3605 (match_operator 1 "comparison_operator"
3606 [(match_operand:DI 2 "reg_or_0_operand" "")
3607 (match_operand:DI 3 "reg_or_cint_operand" "")])
3608 (label_ref (match_operand 0 "" ""))
3610 (clobber (match_operand:DI 4 "register_operand" ""))]
3611 "operands[3] != const0_rtx"
3612 [(set (match_dup 4) (match_dup 5))
3613 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3615 { enum rtx_code code = GET_CODE (operands[1]);
3616 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3618 if (code == NE || code == EQ
3619 || (extended_count (operands[2], DImode, unsignedp) >= 1
3620 && extended_count (operands[3], DImode, unsignedp) >= 1))
3622 if (GET_CODE (operands[3]) == CONST_INT)
3623 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3624 GEN_INT (- INTVAL (operands[3])));
3626 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3628 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3631 else if (code == EQ || code == LE || code == LT
3632 || code == LEU || code == LTU)
3634 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3635 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3639 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3640 operands[2], operands[3]);
3641 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3648 (match_operator 1 "comparison_operator"
3649 [(match_operand:SI 2 "reg_or_0_operand" "")
3650 (match_operand:SI 3 "const_int_operand" "")])
3651 (label_ref (match_operand 0 "" ""))
3653 (clobber (match_operand:DI 4 "register_operand" ""))]
3654 "operands[3] != const0_rtx
3655 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3656 [(set (match_dup 4) (match_dup 5))
3657 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3661 if (GET_CODE (operands[3]) == CONST_INT)
3662 tem = gen_rtx_PLUS (SImode, operands[2],
3663 GEN_INT (- INTVAL (operands[3])));
3665 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3667 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3668 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3669 operands[4], const0_rtx);
3672 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3673 ;; This eliminates one, and sometimes two, insns when the AND can be done
3676 [(set (match_operand:DI 0 "register_operand" "")
3677 (match_operator:DI 1 "comparison_operator"
3678 [(match_operand:DI 2 "register_operand" "")
3679 (match_operand:DI 3 "const_int_operand" "")]))
3680 (clobber (match_operand:DI 4 "register_operand" ""))]
3681 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3682 && (GET_CODE (operands[1]) == GTU
3683 || GET_CODE (operands[1]) == LEU
3684 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3685 && extended_count (operands[2], DImode, 1) > 0))"
3686 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3687 (set (match_dup 0) (match_dup 6))]
3690 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3691 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3692 || GET_CODE (operands[1]) == GT)
3694 DImode, operands[4], const0_rtx);
3697 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3698 ;; work differently, so we have different patterns for each.
3700 (define_expand "call"
3701 [(use (match_operand:DI 0 "" ""))
3702 (use (match_operand 1 "" ""))
3703 (use (match_operand 2 "" ""))
3704 (use (match_operand 3 "" ""))]
3707 { if (TARGET_WINDOWS_NT)
3708 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3709 else if (TARGET_OPEN_VMS)
3710 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3712 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3717 (define_expand "sibcall"
3718 [(call (mem:DI (match_operand 0 "" ""))
3719 (match_operand 1 "" ""))]
3720 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
3723 if (GET_CODE (operands[0]) != MEM)
3725 operands[0] = XEXP (operands[0], 0);
3728 (define_expand "call_osf"
3729 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3730 (match_operand 1 "" ""))
3731 (clobber (reg:DI 27))
3732 (clobber (reg:DI 26))])]
3735 { if (GET_CODE (operands[0]) != MEM)
3738 operands[0] = XEXP (operands[0], 0);
3740 if (GET_CODE (operands[0]) != SYMBOL_REF
3741 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3743 rtx tem = gen_rtx_REG (DImode, 27);
3744 emit_move_insn (tem, operands[0]);
3749 (define_expand "call_nt"
3750 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3751 (match_operand 1 "" ""))
3752 (clobber (reg:DI 26))])]
3755 { if (GET_CODE (operands[0]) != MEM)
3758 operands[0] = XEXP (operands[0], 0);
3759 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3760 operands[0] = force_reg (DImode, operands[0]);
3764 ;; call openvms/alpha
3765 ;; op 0: symbol ref for called function
3766 ;; op 1: next_arg_reg (argument information value for R25)
3768 (define_expand "call_vms"
3769 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3770 (match_operand 1 "" ""))
3774 (clobber (reg:DI 27))])]
3777 { if (GET_CODE (operands[0]) != MEM)
3780 operands[0] = XEXP (operands[0], 0);
3782 /* Always load AI with argument information, then handle symbolic and
3783 indirect call differently. Load RA and set operands[2] to PV in
3786 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3787 if (GET_CODE (operands[0]) == SYMBOL_REF)
3789 extern char *savealloc ();
3790 const char *symbol = XSTR (operands[0], 0);
3796 linksym = savealloc (strlen (symbol) + 6);
3798 alpha_need_linkage (symbol, 0);
3801 strcpy (linksym+1, symbol);
3802 strcat (linksym, \"..lk\");
3803 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3805 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3808 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3812 emit_move_insn (gen_rtx_REG (Pmode, 26),
3813 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3815 operands[2] = operands[0];
3820 (define_expand "call_value"
3821 [(use (match_operand 0 "" ""))
3822 (use (match_operand:DI 1 "" ""))
3823 (use (match_operand 2 "" ""))
3824 (use (match_operand 3 "" ""))
3825 (use (match_operand 4 "" ""))]
3828 { if (TARGET_WINDOWS_NT)
3829 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3830 else if (TARGET_OPEN_VMS)
3831 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3834 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3839 (define_expand "sibcall_value"
3840 [(set (match_operand 0 "" "")
3841 (call (mem:DI (match_operand 1 "" ""))
3842 (match_operand 2 "" "")))]
3843 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
3846 if (GET_CODE (operands[1]) != MEM)
3848 operands[1] = XEXP (operands[1], 0);
3851 (define_expand "call_value_osf"
3852 [(parallel [(set (match_operand 0 "" "")
3853 (call (mem:DI (match_operand 1 "" ""))
3854 (match_operand 2 "" "")))
3855 (clobber (reg:DI 27))
3856 (clobber (reg:DI 26))])]
3859 { if (GET_CODE (operands[1]) != MEM)
3862 operands[1] = XEXP (operands[1], 0);
3864 if (GET_CODE (operands[1]) != SYMBOL_REF
3865 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3867 rtx tem = gen_rtx_REG (DImode, 27);
3868 emit_move_insn (tem, operands[1]);
3873 (define_expand "call_value_nt"
3874 [(parallel [(set (match_operand 0 "" "")
3875 (call (mem:DI (match_operand 1 "" ""))
3876 (match_operand 2 "" "")))
3877 (clobber (reg:DI 26))])]
3880 { if (GET_CODE (operands[1]) != MEM)
3883 operands[1] = XEXP (operands[1], 0);
3884 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
3885 operands[1] = force_reg (DImode, operands[1]);
3888 (define_expand "call_value_vms"
3889 [(parallel [(set (match_operand 0 "" "")
3890 (call (mem:DI (match_operand:DI 1 "" ""))
3891 (match_operand 2 "" "")))
3895 (clobber (reg:DI 27))])]
3898 { if (GET_CODE (operands[1]) != MEM)
3901 operands[1] = XEXP (operands[1], 0);
3903 /* Always load AI with argument information, then handle symbolic and
3904 indirect call differently. Load RA and set operands[3] to PV in
3907 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3908 if (GET_CODE (operands[1]) == SYMBOL_REF)
3910 extern char *savealloc ();
3911 const char *symbol = XSTR (operands[1], 0);
3917 linksym = savealloc (strlen (symbol) + 6);
3919 alpha_need_linkage (symbol, 0);
3921 strcpy (linksym+1, symbol);
3922 strcat (linksym, \"..lk\");
3923 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3925 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3928 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3932 emit_move_insn (gen_rtx_REG (Pmode, 26),
3933 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
3935 operands[3] = operands[1];
3939 (define_insn "*call_osf_1"
3940 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3941 (match_operand 1 "" ""))
3942 (clobber (reg:DI 27))
3943 (clobber (reg:DI 26))]
3944 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3946 jsr $26,($27),0\;ldgp $29,0($26)
3948 jsr $26,%0\;ldgp $29,0($26)"
3949 [(set_attr "type" "jsr")
3950 (set_attr "length" "12,*,16")])
3952 (define_insn "*sibcall_osf_1"
3953 [(call (mem:DI (match_operand:DI 0 "call_operand" "R,i"))
3954 (match_operand 1 "" ""))]
3955 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3959 [(set_attr "type" "jsr")
3960 (set_attr "length" "*,8")])
3962 (define_insn "*call_nt_1"
3963 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3964 (match_operand 1 "" ""))
3965 (clobber (reg:DI 26))]
3971 [(set_attr "type" "jsr")
3972 (set_attr "length" "*,*,12")])
3974 (define_insn "*call_vms_1"
3975 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3976 (match_operand 1 "" ""))
3977 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
3980 (clobber (reg:DI 27))]
3983 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
3984 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3985 [(set_attr "type" "jsr")
3986 (set_attr "length" "12,16")])
3988 ;; Call subroutine returning any type.
3990 (define_expand "untyped_call"
3991 [(parallel [(call (match_operand 0 "" "")
3993 (match_operand 1 "" "")
3994 (match_operand 2 "" "")])]
4000 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4002 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4004 rtx set = XVECEXP (operands[2], 0, i);
4005 emit_move_insn (SET_DEST (set), SET_SRC (set));
4008 /* The optimizer does not know that the call sets the function value
4009 registers we stored in the result block. We avoid problems by
4010 claiming that all hard registers are used and clobbered at this
4012 emit_insn (gen_blockage ());
4017 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4018 ;; all of memory. This blocks insns from being moved across this point.
4020 (define_insn "blockage"
4021 [(unspec_volatile [(const_int 0)] 1)]
4024 [(set_attr "length" "0")])
4028 (label_ref (match_operand 0 "" "")))]
4031 [(set_attr "type" "ibr")])
4033 (define_expand "return"
4038 (define_insn "*return_internal"
4042 [(set_attr "type" "ibr")])
4044 (define_insn "indirect_jump"
4045 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4048 [(set_attr "type" "ibr")])
4050 (define_expand "tablejump"
4051 [(use (match_operand:SI 0 "register_operand" ""))
4052 (use (match_operand:SI 1 "" ""))]
4056 if (TARGET_WINDOWS_NT)
4057 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4058 else if (TARGET_OPEN_VMS)
4059 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4061 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4066 (define_expand "tablejump_osf"
4068 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4069 (parallel [(set (pc)
4070 (plus:DI (match_dup 3)
4071 (label_ref (match_operand 1 "" ""))))
4072 (clobber (match_scratch:DI 2 "=r"))])]
4075 { operands[3] = gen_reg_rtx (DImode); }")
4077 (define_expand "tablejump_nt"
4079 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4080 (parallel [(set (pc)
4082 (use (label_ref (match_operand 1 "" "")))])]
4085 { operands[3] = gen_reg_rtx (DImode); }")
4088 ;; tablejump, openVMS way
4090 ;; op 1: label preceding jump-table
4092 (define_expand "tablejump_vms"
4094 (match_operand:DI 0 "register_operand" ""))
4096 (plus:DI (match_dup 2)
4097 (label_ref (match_operand 1 "" ""))))]
4100 { operands[2] = gen_reg_rtx (DImode); }")
4104 (plus (match_operand:DI 0 "register_operand" "r")
4105 (label_ref (match_operand 1 "" ""))))
4106 (clobber (match_scratch:DI 2 "=r"))]
4107 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
4108 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4109 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4111 { rtx best_label = 0;
4112 rtx jump_table_insn = next_active_insn (operands[1]);
4114 if (GET_CODE (jump_table_insn) == JUMP_INSN
4115 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4117 rtx jump_table = PATTERN (jump_table_insn);
4118 int n_labels = XVECLEN (jump_table, 1);
4119 int best_count = -1;
4122 for (i = 0; i < n_labels; i++)
4126 for (j = i + 1; j < n_labels; j++)
4127 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4128 == XEXP (XVECEXP (jump_table, 1, j), 0))
4131 if (count > best_count)
4132 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4138 operands[3] = best_label;
4139 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
4142 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
4144 [(set_attr "type" "ibr")
4145 (set_attr "length" "8")])
4149 (match_operand:DI 0 "register_operand" "r"))
4150 (use (label_ref (match_operand 1 "" "")))]
4151 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
4152 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4153 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4155 { rtx best_label = 0;
4156 rtx jump_table_insn = next_active_insn (operands[1]);
4158 if (GET_CODE (jump_table_insn) == JUMP_INSN
4159 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4161 rtx jump_table = PATTERN (jump_table_insn);
4162 int n_labels = XVECLEN (jump_table, 1);
4163 int best_count = -1;
4166 for (i = 0; i < n_labels; i++)
4170 for (j = i + 1; j < n_labels; j++)
4171 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4172 == XEXP (XVECEXP (jump_table, 1, j), 0))
4175 if (count > best_count)
4176 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4182 operands[2] = best_label;
4183 return \"jmp $31,(%0),%2\";
4186 return \"jmp $31,(%0),0\";
4188 [(set_attr "type" "ibr")])
4191 ;; op 0 is table offset
4192 ;; op 1 is table label
4197 (plus (match_operand:DI 0 "register_operand" "r")
4198 (label_ref (match_operand 1 "" ""))))]
4201 [(set_attr "type" "ibr")])
4203 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4204 ;; want to have to include pal.h in our .s file.
4206 ;; Technically the type for call_pal is jsr, but we use that for determining
4207 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4210 [(unspec_volatile [(const_int 0)] 0)]
4213 [(set_attr "type" "ibr")])
4215 ;; Finally, we have the basic data motion insns. The byte and word insns
4216 ;; are done via define_expand. Start with the floating-point insns, since
4217 ;; they are simpler.
4220 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4221 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4222 "TARGET_FPREGS && ! TARGET_FIX
4223 && (register_operand (operands[0], SFmode)
4224 || reg_or_fp0_operand (operands[1], SFmode))"
4232 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4235 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4236 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4237 "TARGET_FPREGS && TARGET_FIX
4238 && (register_operand (operands[0], SFmode)
4239 || reg_or_fp0_operand (operands[1], SFmode))"
4249 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4252 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4253 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4255 && (register_operand (operands[0], SFmode)
4256 || reg_or_fp0_operand (operands[1], SFmode))"
4261 [(set_attr "type" "ilog,ild,ist")])
4264 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4265 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4266 "TARGET_FPREGS && ! TARGET_FIX
4267 && (register_operand (operands[0], DFmode)
4268 || reg_or_fp0_operand (operands[1], DFmode))"
4276 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4279 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4280 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4281 "TARGET_FPREGS && TARGET_FIX
4282 && (register_operand (operands[0], DFmode)
4283 || reg_or_fp0_operand (operands[1], DFmode))"
4293 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4296 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4297 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4299 && (register_operand (operands[0], DFmode)
4300 || reg_or_fp0_operand (operands[1], DFmode))"
4305 [(set_attr "type" "ilog,ild,ist")])
4307 ;; Subregs suck for register allocation. Pretend we can move TFmode
4308 ;; data between general registers until after reload.
4310 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4311 (match_operand:TF 1 "input_operand" "roG,r"))]
4312 "register_operand (operands[0], TFmode)
4313 || reg_or_fp0_operand (operands[1], TFmode)"
4317 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4318 (match_operand:TF 1 "input_operand" ""))]
4320 [(set (match_dup 0) (match_dup 2))
4321 (set (match_dup 1) (match_dup 3))]
4324 alpha_split_tfmode_pair (operands);
4325 if (rtx_equal_p (operands[0], operands[3]))
4328 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4329 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4333 (define_expand "movsf"
4334 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4335 (match_operand:SF 1 "general_operand" ""))]
4339 if (GET_CODE (operands[0]) == MEM
4340 && ! reg_or_fp0_operand (operands[1], SFmode))
4341 operands[1] = force_reg (SFmode, operands[1]);
4344 (define_expand "movdf"
4345 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4346 (match_operand:DF 1 "general_operand" ""))]
4350 if (GET_CODE (operands[0]) == MEM
4351 && ! reg_or_fp0_operand (operands[1], DFmode))
4352 operands[1] = force_reg (DFmode, operands[1]);
4355 (define_expand "movtf"
4356 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4357 (match_operand:TF 1 "general_operand" ""))]
4361 if (GET_CODE (operands[0]) == MEM
4362 && ! reg_or_fp0_operand (operands[1], TFmode))
4363 operands[1] = force_reg (TFmode, operands[1]);
4367 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4368 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4369 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4370 && (register_operand (operands[0], SImode)
4371 || reg_or_0_operand (operands[1], SImode))"
4381 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4384 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4385 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4386 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4387 && (register_operand (operands[0], SImode)
4388 || reg_or_0_operand (operands[1], SImode))"
4400 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4403 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4404 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4405 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4406 && (register_operand (operands[0], SImode)
4407 || reg_or_0_operand (operands[1], SImode))"
4418 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4421 [(set (match_operand:HI 0 "register_operand" "=r,r")
4422 (match_operand:HI 1 "input_operand" "rJ,n"))]
4424 && (register_operand (operands[0], HImode)
4425 || register_operand (operands[1], HImode))"
4429 [(set_attr "type" "ilog,iadd")])
4432 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4433 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4435 && (register_operand (operands[0], HImode)
4436 || reg_or_0_operand (operands[1], HImode))"
4442 [(set_attr "type" "ilog,iadd,ild,ist")])
4445 [(set (match_operand:QI 0 "register_operand" "=r,r")
4446 (match_operand:QI 1 "input_operand" "rJ,n"))]
4448 && (register_operand (operands[0], QImode)
4449 || register_operand (operands[1], QImode))"
4453 [(set_attr "type" "ilog,iadd")])
4456 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4457 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4459 && (register_operand (operands[0], QImode)
4460 || reg_or_0_operand (operands[1], QImode))"
4466 [(set_attr "type" "ilog,iadd,ild,ist")])
4468 ;; We do two major things here: handle mem->mem and construct long
4471 (define_expand "movsi"
4472 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4473 (match_operand:SI 1 "general_operand" ""))]
4477 if (GET_CODE (operands[0]) == MEM
4478 && ! reg_or_0_operand (operands[1], SImode))
4479 operands[1] = force_reg (SImode, operands[1]);
4481 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4483 else if (GET_CODE (operands[1]) == CONST_INT)
4486 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4487 if (rtx_equal_p (operands[0], operands[1]))
4492 ;; Split a load of a large constant into the appropriate two-insn
4496 [(set (match_operand:SI 0 "register_operand" "")
4497 (match_operand:SI 1 "const_int_operand" ""))]
4498 "! add_operand (operands[1], SImode)"
4499 [(set (match_dup 0) (match_dup 2))
4500 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4503 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4505 if (tem == operands[0])
4512 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4513 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4515 && (register_operand (operands[0], DImode)
4516 || reg_or_0_operand (operands[1], DImode))"
4527 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4530 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4531 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4533 && (register_operand (operands[0], DImode)
4534 || reg_or_0_operand (operands[1], DImode))"
4547 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4549 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4550 ;; memory, and construct long 32-bit constants.
4552 (define_expand "movdi"
4553 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4554 (match_operand:DI 1 "general_operand" ""))]
4560 if (GET_CODE (operands[0]) == MEM
4561 && ! reg_or_0_operand (operands[1], DImode))
4562 operands[1] = force_reg (DImode, operands[1]);
4564 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4566 else if (GET_CODE (operands[1]) == CONST_INT
4567 && (tem = alpha_emit_set_const (operands[0], DImode,
4568 INTVAL (operands[1]), 3)) != 0)
4570 if (rtx_equal_p (tem, operands[0]))
4575 else if (CONSTANT_P (operands[1]))
4577 if (TARGET_BUILD_CONSTANTS)
4579 HOST_WIDE_INT i0, i1;
4581 if (GET_CODE (operands[1]) == CONST_INT)
4583 i0 = INTVAL (operands[1]);
4586 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4588 #if HOST_BITS_PER_WIDE_INT >= 64
4589 i0 = CONST_DOUBLE_LOW (operands[1]);
4592 i0 = CONST_DOUBLE_LOW (operands[1]);
4593 i1 = CONST_DOUBLE_HIGH (operands[1]);
4599 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4600 if (rtx_equal_p (tem, operands[0]))
4607 operands[1] = force_const_mem (DImode, operands[1]);
4608 if (reload_in_progress)
4610 emit_move_insn (operands[0], XEXP (operands[1], 0));
4611 operands[1] = copy_rtx (operands[1]);
4612 XEXP (operands[1], 0) = operands[0];
4615 operands[1] = validize_mem (operands[1]);
4622 ;; Split a load of a large constant into the appropriate two-insn
4626 [(set (match_operand:DI 0 "register_operand" "")
4627 (match_operand:DI 1 "const_int_operand" ""))]
4628 "! add_operand (operands[1], DImode)"
4629 [(set (match_dup 0) (match_dup 2))
4630 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4633 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4635 if (tem == operands[0])
4641 ;; These are the partial-word cases.
4643 ;; First we have the code to load an aligned word. Operand 0 is the register
4644 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4645 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4646 ;; number of bits within the word that the value is. Operand 3 is an SImode
4647 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4648 ;; same register. It is allowed to conflict with operand 1 as well.
4650 (define_expand "aligned_loadqi"
4651 [(set (match_operand:SI 3 "register_operand" "")
4652 (match_operand:SI 1 "memory_operand" ""))
4653 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4654 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4656 (match_operand:DI 2 "const_int_operand" "")))]
4661 (define_expand "aligned_loadhi"
4662 [(set (match_operand:SI 3 "register_operand" "")
4663 (match_operand:SI 1 "memory_operand" ""))
4664 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4665 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4667 (match_operand:DI 2 "const_int_operand" "")))]
4672 ;; Similar for unaligned loads, where we use the sequence from the
4673 ;; Alpha Architecture manual.
4675 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4676 ;; operand 3 can overlap the input and output registers.
4678 (define_expand "unaligned_loadqi"
4679 [(set (match_operand:DI 2 "register_operand" "")
4680 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4682 (set (match_operand:DI 3 "register_operand" "")
4684 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4685 (zero_extract:DI (match_dup 2)
4687 (ashift:DI (match_dup 3) (const_int 3))))]
4691 (define_expand "unaligned_loadhi"
4692 [(set (match_operand:DI 2 "register_operand" "")
4693 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4695 (set (match_operand:DI 3 "register_operand" "")
4697 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4698 (zero_extract:DI (match_dup 2)
4700 (ashift:DI (match_dup 3) (const_int 3))))]
4704 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4705 ;; aligned SImode MEM. Operand 1 is the register containing the
4706 ;; byte or word to store. Operand 2 is the number of bits within the word that
4707 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4709 (define_expand "aligned_store"
4710 [(set (match_operand:SI 3 "register_operand" "")
4711 (match_operand:SI 0 "memory_operand" ""))
4712 (set (subreg:DI (match_dup 3) 0)
4713 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4714 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4715 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4716 (match_operand:DI 2 "const_int_operand" "")))
4717 (set (subreg:DI (match_dup 4) 0)
4718 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4719 (set (match_dup 0) (match_dup 4))]
4722 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4723 << INTVAL (operands[2])));
4726 ;; For the unaligned byte and halfword cases, we use code similar to that
4727 ;; in the ;; Architecture book, but reordered to lower the number of registers
4728 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4729 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4730 ;; be the same temporary, if desired. If the address is in a register,
4731 ;; operand 2 can be that register.
4733 (define_expand "unaligned_storeqi"
4734 [(set (match_operand:DI 3 "register_operand" "")
4735 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4737 (set (match_operand:DI 2 "register_operand" "")
4740 (and:DI (not:DI (ashift:DI (const_int 255)
4741 (ashift:DI (match_dup 2) (const_int 3))))
4743 (set (match_operand:DI 4 "register_operand" "")
4744 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4745 (ashift:DI (match_dup 2) (const_int 3))))
4746 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4747 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4752 (define_expand "unaligned_storehi"
4753 [(set (match_operand:DI 3 "register_operand" "")
4754 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4756 (set (match_operand:DI 2 "register_operand" "")
4759 (and:DI (not:DI (ashift:DI (const_int 65535)
4760 (ashift:DI (match_dup 2) (const_int 3))))
4762 (set (match_operand:DI 4 "register_operand" "")
4763 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4764 (ashift:DI (match_dup 2) (const_int 3))))
4765 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4766 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4771 ;; Here are the define_expand's for QI and HI moves that use the above
4772 ;; patterns. We have the normal sets, plus the ones that need scratch
4773 ;; registers for reload.
4775 (define_expand "movqi"
4776 [(set (match_operand:QI 0 "nonimmediate_operand" "")
4777 (match_operand:QI 1 "general_operand" ""))]
4783 if (GET_CODE (operands[0]) == MEM
4784 && ! reg_or_0_operand (operands[1], QImode))
4785 operands[1] = force_reg (QImode, operands[1]);
4787 if (GET_CODE (operands[1]) == CONST_INT
4788 && ! input_operand (operands[1], QImode))
4790 operands[1] = alpha_emit_set_const (operands[0], QImode,
4791 INTVAL (operands[1]), 3);
4793 if (rtx_equal_p (operands[0], operands[1]))
4800 /* If the output is not a register, the input must be. */
4801 if (GET_CODE (operands[0]) == MEM)
4802 operands[1] = force_reg (QImode, operands[1]);
4804 /* Handle four memory cases, unaligned and aligned for either the input
4805 or the output. The only case where we can be called during reload is
4806 for aligned loads; all other cases require temporaries. */
4808 if (GET_CODE (operands[1]) == MEM
4809 || (GET_CODE (operands[1]) == SUBREG
4810 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4811 || (reload_in_progress && GET_CODE (operands[1]) == REG
4812 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4813 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4814 && GET_CODE (SUBREG_REG (operands[1])) == REG
4815 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4817 if (aligned_memory_operand (operands[1], QImode))
4819 if (reload_in_progress)
4821 emit_insn (gen_reload_inqi_help
4822 (operands[0], operands[1],
4823 gen_rtx_REG (SImode, REGNO (operands[0]))));
4827 rtx aligned_mem, bitnum;
4828 rtx scratch = gen_reg_rtx (SImode);
4830 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4832 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4838 /* Don't pass these as parameters since that makes the generated
4839 code depend on parameter evaluation order which will cause
4840 bootstrap failures. */
4842 rtx temp1 = gen_reg_rtx (DImode);
4843 rtx temp2 = gen_reg_rtx (DImode);
4845 = gen_unaligned_loadqi (operands[0],
4846 get_unaligned_address (operands[1], 0),
4849 alpha_set_memflags (seq, operands[1]);
4856 else if (GET_CODE (operands[0]) == MEM
4857 || (GET_CODE (operands[0]) == SUBREG
4858 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4859 || (reload_in_progress && GET_CODE (operands[0]) == REG
4860 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4861 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4862 && GET_CODE (SUBREG_REG (operands[0])) == REG
4863 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4865 if (aligned_memory_operand (operands[0], QImode))
4867 rtx aligned_mem, bitnum;
4868 rtx temp1 = gen_reg_rtx (SImode);
4869 rtx temp2 = gen_reg_rtx (SImode);
4871 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4873 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4878 rtx temp1 = gen_reg_rtx (DImode);
4879 rtx temp2 = gen_reg_rtx (DImode);
4880 rtx temp3 = gen_reg_rtx (DImode);
4882 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4883 operands[1], temp1, temp2, temp3);
4885 alpha_set_memflags (seq, operands[0]);
4893 (define_expand "movhi"
4894 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4895 (match_operand:HI 1 "general_operand" ""))]
4901 if (GET_CODE (operands[0]) == MEM
4902 && ! reg_or_0_operand (operands[1], HImode))
4903 operands[1] = force_reg (HImode, operands[1]);
4905 if (GET_CODE (operands[1]) == CONST_INT
4906 && ! input_operand (operands[1], HImode))
4908 operands[1] = alpha_emit_set_const (operands[0], HImode,
4909 INTVAL (operands[1]), 3);
4911 if (rtx_equal_p (operands[0], operands[1]))
4918 /* If the output is not a register, the input must be. */
4919 if (GET_CODE (operands[0]) == MEM)
4920 operands[1] = force_reg (HImode, operands[1]);
4922 /* Handle four memory cases, unaligned and aligned for either the input
4923 or the output. The only case where we can be called during reload is
4924 for aligned loads; all other cases require temporaries. */
4926 if (GET_CODE (operands[1]) == MEM
4927 || (GET_CODE (operands[1]) == SUBREG
4928 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4929 || (reload_in_progress && GET_CODE (operands[1]) == REG
4930 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4931 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4932 && GET_CODE (SUBREG_REG (operands[1])) == REG
4933 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4935 if (aligned_memory_operand (operands[1], HImode))
4937 if (reload_in_progress)
4939 emit_insn (gen_reload_inhi_help
4940 (operands[0], operands[1],
4941 gen_rtx_REG (SImode, REGNO (operands[0]))));
4945 rtx aligned_mem, bitnum;
4946 rtx scratch = gen_reg_rtx (SImode);
4948 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4950 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4956 /* Don't pass these as parameters since that makes the generated
4957 code depend on parameter evaluation order which will cause
4958 bootstrap failures. */
4960 rtx temp1 = gen_reg_rtx (DImode);
4961 rtx temp2 = gen_reg_rtx (DImode);
4963 = gen_unaligned_loadhi (operands[0],
4964 get_unaligned_address (operands[1], 0),
4967 alpha_set_memflags (seq, operands[1]);
4974 else if (GET_CODE (operands[0]) == MEM
4975 || (GET_CODE (operands[0]) == SUBREG
4976 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4977 || (reload_in_progress && GET_CODE (operands[0]) == REG
4978 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4979 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4980 && GET_CODE (SUBREG_REG (operands[0])) == REG
4981 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4983 if (aligned_memory_operand (operands[0], HImode))
4985 rtx aligned_mem, bitnum;
4986 rtx temp1 = gen_reg_rtx (SImode);
4987 rtx temp2 = gen_reg_rtx (SImode);
4989 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4991 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4996 rtx temp1 = gen_reg_rtx (DImode);
4997 rtx temp2 = gen_reg_rtx (DImode);
4998 rtx temp3 = gen_reg_rtx (DImode);
5000 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
5001 operands[1], temp1, temp2, temp3);
5003 alpha_set_memflags (seq, operands[0]);
5012 ;; Here are the versions for reload. Note that in the unaligned cases
5013 ;; we know that the operand must not be a pseudo-register because stack
5014 ;; slots are always aligned references.
5016 (define_expand "reload_inqi"
5017 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5018 (match_operand:QI 1 "any_memory_operand" "m")
5019 (match_operand:TI 2 "register_operand" "=&r")])]
5025 if (GET_CODE (operands[1]) != MEM)
5028 if (aligned_memory_operand (operands[1], QImode))
5030 seq = gen_reload_inqi_help (operands[0], operands[1],
5031 gen_rtx_REG (SImode, REGNO (operands[2])));
5037 /* It is possible that one of the registers we got for operands[2]
5038 might coincide with that of operands[0] (which is why we made
5039 it TImode). Pick the other one to use as our scratch. */
5040 if (REGNO (operands[0]) == REGNO (operands[2]))
5041 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5043 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5045 addr = get_unaligned_address (operands[1], 0);
5046 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5047 gen_rtx_REG (DImode, REGNO (operands[0])));
5048 alpha_set_memflags (seq, operands[1]);
5054 (define_expand "reload_inhi"
5055 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5056 (match_operand:HI 1 "any_memory_operand" "m")
5057 (match_operand:TI 2 "register_operand" "=&r")])]
5063 if (GET_CODE (operands[1]) != MEM)
5066 if (aligned_memory_operand (operands[1], HImode))
5068 seq = gen_reload_inhi_help (operands[0], operands[1],
5069 gen_rtx_REG (SImode, REGNO (operands[2])));
5075 /* It is possible that one of the registers we got for operands[2]
5076 might coincide with that of operands[0] (which is why we made
5077 it TImode). Pick the other one to use as our scratch. */
5078 if (REGNO (operands[0]) == REGNO (operands[2]))
5079 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5081 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5083 addr = get_unaligned_address (operands[1], 0);
5084 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5085 gen_rtx_REG (DImode, REGNO (operands[0])));
5086 alpha_set_memflags (seq, operands[1]);
5092 (define_expand "reload_outqi"
5093 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5094 (match_operand:QI 1 "register_operand" "r")
5095 (match_operand:TI 2 "register_operand" "=&r")])]
5099 if (GET_CODE (operands[0]) != MEM)
5102 if (aligned_memory_operand (operands[0], QImode))
5104 emit_insn (gen_reload_outqi_help
5105 (operands[0], operands[1],
5106 gen_rtx_REG (SImode, REGNO (operands[2])),
5107 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5111 rtx addr = get_unaligned_address (operands[0], 0);
5112 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5113 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5114 rtx scratch3 = scratch1;
5117 if (GET_CODE (addr) == REG)
5120 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5121 scratch2, scratch3);
5122 alpha_set_memflags (seq, operands[0]);
5128 (define_expand "reload_outhi"
5129 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5130 (match_operand:HI 1 "register_operand" "r")
5131 (match_operand:TI 2 "register_operand" "=&r")])]
5135 if (GET_CODE (operands[0]) != MEM)
5138 if (aligned_memory_operand (operands[0], HImode))
5140 emit_insn (gen_reload_outhi_help
5141 (operands[0], operands[1],
5142 gen_rtx_REG (SImode, REGNO (operands[2])),
5143 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5147 rtx addr = get_unaligned_address (operands[0], 0);
5148 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5149 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5150 rtx scratch3 = scratch1;
5153 if (GET_CODE (addr) == REG)
5156 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5157 scratch2, scratch3);
5158 alpha_set_memflags (seq, operands[0]);
5164 ;; Helpers for the above. The way reload is structured, we can't
5165 ;; always get a proper address for a stack slot during reload_foo
5166 ;; expansion, so we must delay our address manipulations until after.
5168 (define_insn "reload_inqi_help"
5169 [(set (match_operand:QI 0 "register_operand" "=r")
5170 (match_operand:QI 1 "memory_operand" "m"))
5171 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5172 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5175 (define_insn "reload_inhi_help"
5176 [(set (match_operand:HI 0 "register_operand" "=r")
5177 (match_operand:HI 1 "memory_operand" "m"))
5178 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5179 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5182 (define_insn "reload_outqi_help"
5183 [(set (match_operand:QI 0 "memory_operand" "=m")
5184 (match_operand:QI 1 "register_operand" "r"))
5185 (clobber (match_operand:SI 2 "register_operand" "=r"))
5186 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5187 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5190 (define_insn "reload_outhi_help"
5191 [(set (match_operand:HI 0 "memory_operand" "=m")
5192 (match_operand:HI 1 "register_operand" "r"))
5193 (clobber (match_operand:SI 2 "register_operand" "=r"))
5194 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5195 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5199 [(set (match_operand:QI 0 "register_operand" "")
5200 (match_operand:QI 1 "memory_operand" ""))
5201 (clobber (match_operand:SI 2 "register_operand" ""))]
5202 "! TARGET_BWX && reload_completed"
5206 rtx aligned_mem, bitnum;
5207 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5208 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5214 [(set (match_operand:HI 0 "register_operand" "")
5215 (match_operand:HI 1 "memory_operand" ""))
5216 (clobber (match_operand:SI 2 "register_operand" ""))]
5217 "! TARGET_BWX && reload_completed"
5221 rtx aligned_mem, bitnum;
5222 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5223 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5229 [(set (match_operand:QI 0 "memory_operand" "")
5230 (match_operand:QI 1 "register_operand" ""))
5231 (clobber (match_operand:SI 2 "register_operand" ""))
5232 (clobber (match_operand:SI 3 "register_operand" ""))]
5233 "! TARGET_BWX && reload_completed"
5237 rtx aligned_mem, bitnum;
5238 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5239 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5240 operands[2], operands[3]));
5245 [(set (match_operand:HI 0 "memory_operand" "")
5246 (match_operand:HI 1 "register_operand" ""))
5247 (clobber (match_operand:SI 2 "register_operand" ""))
5248 (clobber (match_operand:SI 3 "register_operand" ""))]
5249 "! TARGET_BWX && reload_completed"
5253 rtx aligned_mem, bitnum;
5254 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5255 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5256 operands[2], operands[3]));
5260 ;; Bit field extract patterns which use ext[wlq][lh]
5262 (define_expand "extv"
5263 [(set (match_operand:DI 0 "register_operand" "")
5264 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5265 (match_operand:DI 2 "immediate_operand" "")
5266 (match_operand:DI 3 "immediate_operand" "")))]
5270 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5271 if (INTVAL (operands[3]) % 8 != 0
5272 || (INTVAL (operands[2]) != 16
5273 && INTVAL (operands[2]) != 32
5274 && INTVAL (operands[2]) != 64))
5277 /* From mips.md: extract_bit_field doesn't verify that our source
5278 matches the predicate, so we force it to be a MEM here. */
5279 if (GET_CODE (operands[1]) != MEM)
5282 alpha_expand_unaligned_load (operands[0], operands[1],
5283 INTVAL (operands[2]) / 8,
5284 INTVAL (operands[3]) / 8, 1);
5288 (define_expand "extzv"
5289 [(set (match_operand:DI 0 "register_operand" "")
5290 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5291 (match_operand:DI 2 "immediate_operand" "")
5292 (match_operand:DI 3 "immediate_operand" "")))]
5296 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5297 if (INTVAL (operands[3]) % 8 != 0
5298 || (INTVAL (operands[2]) != 8
5299 && INTVAL (operands[2]) != 16
5300 && INTVAL (operands[2]) != 32
5301 && INTVAL (operands[2]) != 64))
5304 if (GET_CODE (operands[1]) == MEM)
5306 /* Fail 8 bit fields, falling back on a simple byte load. */
5307 if (INTVAL (operands[2]) == 8)
5310 alpha_expand_unaligned_load (operands[0], operands[1],
5311 INTVAL (operands[2]) / 8,
5312 INTVAL (operands[3]) / 8, 0);
5317 (define_expand "insv"
5318 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5319 (match_operand:DI 1 "immediate_operand" "")
5320 (match_operand:DI 2 "immediate_operand" ""))
5321 (match_operand:DI 3 "register_operand" ""))]
5325 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5326 if (INTVAL (operands[2]) % 8 != 0
5327 || (INTVAL (operands[1]) != 16
5328 && INTVAL (operands[1]) != 32
5329 && INTVAL (operands[1]) != 64))
5332 /* From mips.md: store_bit_field doesn't verify that our source
5333 matches the predicate, so we force it to be a MEM here. */
5334 if (GET_CODE (operands[0]) != MEM)
5337 alpha_expand_unaligned_store (operands[0], operands[3],
5338 INTVAL (operands[1]) / 8,
5339 INTVAL (operands[2]) / 8);
5345 ;; Block move/clear, see alpha.c for more details.
5346 ;; Argument 0 is the destination
5347 ;; Argument 1 is the source
5348 ;; Argument 2 is the length
5349 ;; Argument 3 is the alignment
5351 (define_expand "movstrqi"
5352 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5353 (match_operand:BLK 1 "memory_operand" ""))
5354 (use (match_operand:DI 2 "immediate_operand" ""))
5355 (use (match_operand:DI 3 "immediate_operand" ""))])]
5359 if (alpha_expand_block_move (operands))
5365 (define_expand "clrstrqi"
5366 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5368 (use (match_operand:DI 1 "immediate_operand" ""))
5369 (use (match_operand:DI 2 "immediate_operand" ""))])]
5373 if (alpha_expand_block_clear (operands))
5379 ;; Subroutine of stack space allocation. Perform a stack probe.
5380 (define_expand "probe_stack"
5381 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5385 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5386 INTVAL (operands[0])));
5387 MEM_VOLATILE_P (operands[1]) = 1;
5389 operands[0] = const0_rtx;
5392 ;; This is how we allocate stack space. If we are allocating a
5393 ;; constant amount of space and we know it is less than 4096
5394 ;; bytes, we need do nothing.
5396 ;; If it is more than 4096 bytes, we need to probe the stack
5398 (define_expand "allocate_stack"
5400 (plus:DI (reg:DI 30)
5401 (match_operand:DI 1 "reg_or_cint_operand" "")))
5402 (set (match_operand:DI 0 "register_operand" "=r")
5407 if (GET_CODE (operands[1]) == CONST_INT
5408 && INTVAL (operands[1]) < 32768)
5410 if (INTVAL (operands[1]) >= 4096)
5412 /* We do this the same way as in the prologue and generate explicit
5413 probes. Then we update the stack by the constant. */
5417 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5418 while (probed + 8192 < INTVAL (operands[1]))
5419 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5421 if (probed + 4096 < INTVAL (operands[1]))
5422 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5425 operands[1] = GEN_INT (- INTVAL (operands[1]));
5426 operands[2] = virtual_stack_dynamic_rtx;
5431 rtx loop_label = gen_label_rtx ();
5432 rtx want = gen_reg_rtx (Pmode);
5433 rtx tmp = gen_reg_rtx (Pmode);
5436 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5437 force_reg (Pmode, operands[1])));
5438 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5440 if (GET_CODE (operands[1]) != CONST_INT)
5442 out_label = gen_label_rtx ();
5443 emit_insn (gen_cmpdi (want, tmp));
5444 emit_jump_insn (gen_bgeu (out_label));
5447 emit_label (loop_label);
5448 memref = gen_rtx_MEM (DImode, tmp);
5449 MEM_VOLATILE_P (memref) = 1;
5450 emit_move_insn (memref, const0_rtx);
5451 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5452 emit_insn (gen_cmpdi (tmp, want));
5453 emit_jump_insn (gen_bgtu (loop_label));
5455 memref = gen_rtx_MEM (DImode, want);
5456 MEM_VOLATILE_P (memref) = 1;
5457 emit_move_insn (memref, const0_rtx);
5460 emit_label (out_label);
5462 emit_move_insn (stack_pointer_rtx, want);
5463 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5468 ;; This is used by alpha_expand_prolog to do the same thing as above,
5469 ;; except we cannot at that time generate new basic blocks, so we hide
5470 ;; the loop in this one insn.
5472 (define_insn "prologue_stack_probe_loop"
5473 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5474 (match_operand:DI 1 "register_operand" "r")] 5)]
5478 operands[2] = gen_label_rtx ();
5479 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5480 CODE_LABEL_NUMBER (operands[2]));
5482 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5484 [(set_attr "length" "16")
5485 (set_attr "type" "multi")])
5487 (define_expand "prologue"
5488 [(clobber (const_int 0))]
5492 alpha_expand_prologue ();
5496 ;; These take care of emitting the ldgp insn in the prologue. This will be
5497 ;; an lda/ldah pair and we want to align them properly. So we have two
5498 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
5499 ;; and the second of which emits nothing. However, both are marked as type
5500 ;; IADD (the default) so the alignment code in alpha.c does the right thing
5503 (define_expand "prologue_ldgp"
5504 [(unspec_volatile [(const_int 0)] 9)
5505 (unspec_volatile [(const_int 0)] 10)]
5509 (define_insn "*prologue_ldgp_1"
5510 [(unspec_volatile [(const_int 0)] 9)]
5511 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5512 "ldgp $29,0($27)\\n$%~..ng:")
5514 (define_insn "*prologue_ldgp_2"
5515 [(unspec_volatile [(const_int 0)] 10)]
5516 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5519 (define_insn "init_fp"
5520 [(set (match_operand:DI 0 "register_operand" "=r")
5521 (match_operand:DI 1 "register_operand" "r"))
5522 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5526 (define_expand "epilogue"
5531 alpha_expand_epilogue ();
5534 (define_expand "sibcall_epilogue"
5536 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
5539 alpha_expand_epilogue ();
5543 (define_expand "eh_epilogue"
5544 [(use (match_operand:DI 0 "register_operand" "r"))
5545 (use (match_operand:DI 1 "register_operand" "r"))
5546 (use (match_operand:DI 2 "register_operand" "r"))]
5550 cfun->machine->eh_epilogue_sp_ofs = operands[1];
5551 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5553 rtx ra = gen_rtx_REG (Pmode, 26);
5554 emit_move_insn (ra, operands[2]);
5559 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5560 ;; the frame size into a register. We use this pattern to ensure
5561 ;; we get lda instead of addq.
5562 (define_insn "nt_lda"
5563 [(set (match_operand:DI 0 "register_operand" "=r")
5564 (unspec:DI [(match_dup 0)
5565 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5569 (define_expand "builtin_longjmp"
5570 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5571 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5574 /* The elements of the buffer are, in order: */
5575 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5576 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5577 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5578 rtx pv = gen_rtx_REG (Pmode, 27);
5580 /* This bit is the same as expand_builtin_longjmp. */
5581 emit_move_insn (hard_frame_pointer_rtx, fp);
5582 emit_move_insn (pv, lab);
5583 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5584 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5585 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5587 /* Load the label we are jumping through into $27 so that we know
5588 where to look for it when we get back to setjmp's function for
5589 restoring the gp. */
5590 emit_indirect_jump (pv);
5594 (define_insn "builtin_setjmp_receiver"
5595 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5596 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5597 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5598 [(set_attr "length" "8")
5599 (set_attr "type" "multi")])
5602 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5603 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5604 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5605 [(set_attr "length" "12")
5606 (set_attr "type" "multi")])
5608 (define_insn "exception_receiver"
5609 [(unspec_volatile [(const_int 0)] 7)]
5610 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5611 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5612 [(set_attr "length" "12")
5613 (set_attr "type" "multi")])
5615 (define_expand "nonlocal_goto_receiver"
5616 [(unspec_volatile [(const_int 0)] 1)
5617 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5618 (unspec_volatile [(const_int 0)] 1)
5623 (define_insn "arg_home"
5624 [(unspec [(const_int 0)] 0)
5639 (clobber (mem:BLK (const_int 0)))
5640 (clobber (reg:DI 24))
5641 (clobber (reg:DI 25))
5642 (clobber (reg:DI 0))]
5644 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5645 [(set_attr "length" "16")
5646 (set_attr "type" "multi")])
5648 ;; Close the trap shadow of preceeding instructions. This is generated
5651 (define_insn "trapb"
5652 [(unspec_volatile [(const_int 0)] 4)]
5655 [(set_attr "type" "misc")])
5657 ;; No-op instructions used by machine-dependant reorg to preserve
5658 ;; alignment for instruction issue.
5664 [(set_attr "type" "ilog")])
5670 [(set_attr "type" "fcpys")])
5677 (define_insn "realign"
5678 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5680 ".align %0 #realign")
5682 ;; The call patterns are at the end of the file because their
5683 ;; wildcard operand0 interferes with nice recognition.
5685 (define_insn "*call_value_osf_1"
5686 [(set (match_operand 0 "" "")
5687 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5688 (match_operand 2 "" "")))
5689 (clobber (reg:DI 27))
5690 (clobber (reg:DI 26))]
5691 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5693 jsr $26,($27),0\;ldgp $29,0($26)
5695 jsr $26,%1\;ldgp $29,0($26)"
5696 [(set_attr "type" "jsr")
5697 (set_attr "length" "12,*,16")])
5699 (define_insn "*sibcall_value_osf_1"
5700 [(set (match_operand 0 "" "")
5701 (call (mem:DI (match_operand:DI 1 "call_operand" "R,i"))
5702 (match_operand 2 "" "")))]
5703 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5707 [(set_attr "type" "jsr")
5708 (set_attr "length" "*,8")])
5710 (define_insn "*call_value_nt_1"
5711 [(set (match_operand 0 "" "")
5712 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5713 (match_operand 2 "" "")))
5714 (clobber (reg:DI 26))]
5720 [(set_attr "type" "jsr")
5721 (set_attr "length" "*,*,12")])
5723 (define_insn "*call_value_vms_1"
5724 [(set (match_operand 0 "" "")
5725 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
5726 (match_operand 2 "" "")))
5727 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
5730 (clobber (reg:DI 27))]
5733 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
5734 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
5735 [(set_attr "type" "jsr")
5736 (set_attr "length" "12,16")])
5738 ;; Peepholes go at the end.
5740 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5741 ;; reload when converting fp->int.
5744 [(set (match_operand:SI 0 "register_operand" "=r")
5745 (match_operand:SI 1 "memory_operand" "m"))
5746 (set (match_operand:DI 2 "register_operand" "=r")
5747 (sign_extend:DI (match_dup 0)))]
5748 "dead_or_set_p (next_nonnote_insn (insn), operands[0])"
5750 (sign_extend:DI (match_dup 1)))]
5754 [(set (match_operand:SI 0 "register_operand" "=r")
5755 (match_operand:SI 1 "hard_fp_register_operand" "f"))
5756 (set (match_operand:DI 2 "register_operand" "=r")
5757 (sign_extend:DI (match_dup 0)))]
5758 "TARGET_FIX && dead_or_set_p (next_nonnote_insn (insn), operands[0])"
5760 (sign_extend:DI (match_dup 1)))]