1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
69 (UNSPECV_LONGJMP 3) ; builtin_longjmp
71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
73 (UNSPECV_EHR 7) ; exception_receiver
77 (UNSPECV_PLDGP2 11) ; prologue ldgp
82 ;; Where necessary, the suffixes _le and _be are used to distinguish between
83 ;; little-endian and big-endian patterns.
85 ;; Note that the Unicos/Mk assembler does not support the following
86 ;; opcodes: mov, fmov, nop, fnop, unop.
88 ;; Processor type -- this attribute must exactly match the processor_type
89 ;; enumeration in alpha.h.
91 (define_attr "cpu" "ev4,ev5,ev6"
92 (const (symbol_ref "alpha_cpu")))
94 ;; Define an insn type attribute. This is used in function unit delay
95 ;; computations, among other purposes. For the most part, we use the names
96 ;; defined in the EV4 documentation, but add a few that we have to know about
100 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
101 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
102 (const_string "iadd"))
104 ;; Describe a user's asm statement.
105 (define_asm_attributes
106 [(set_attr "type" "multi")])
108 ;; Define the operand size an insn operates on. Used primarily by mul
109 ;; and div operations that have size dependent timings.
111 (define_attr "opsize" "si,di,udi"
114 ;; The TRAP attribute marks instructions that may generate traps
115 ;; (which are imprecise and may need a trapb if software completion
118 (define_attr "trap" "no,yes"
121 ;; The ROUND_SUFFIX attribute marks which instructions require a
122 ;; rounding-mode suffix. The value NONE indicates no suffix,
123 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
125 (define_attr "round_suffix" "none,normal,c"
126 (const_string "none"))
128 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
130 ;; SU accepts only /su (cmpt et al)
131 ;; SUI accepts only /sui (cvtqt and cvtqs)
132 ;; V_SV accepts /v and /sv (cvtql only)
133 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
134 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
136 ;; The actual suffix emitted is controled by alpha_fptm.
138 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
139 (const_string "none"))
141 ;; The length of an instruction sequence in bytes.
143 (define_attr "length" ""
146 ;; The USEGP attribute marks instructions that have relocations that use
149 (define_attr "usegp" "no,yes"
150 (cond [(eq_attr "type" "ldsym,jsr")
152 (eq_attr "type" "ild,fld,ist,fst")
153 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
155 (const_string "no")))
158 ;; Include scheduling descriptions.
164 ;; First define the arithmetic insns. Note that the 32-bit forms also
167 ;; Handle 32-64 bit extension from memory to a floating point register
168 ;; specially, since this occurs frequently in int->double conversions.
170 ;; Note that while we must retain the =f case in the insn for reload's
171 ;; benefit, it should be eliminated after reload, so we should never emit
172 ;; code for that case. But we don't reject the possibility.
174 (define_expand "extendsidi2"
175 [(set (match_operand:DI 0 "register_operand" "")
176 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
180 (define_insn "*extendsidi2_nofix"
181 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
183 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
189 lds %0,%1\;cvtlq %0,%0"
190 [(set_attr "type" "iadd,ild,fadd,fld")
191 (set_attr "length" "*,*,*,8")])
193 (define_insn "*extendsidi2_fix"
194 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
196 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
203 lds %0,%1\;cvtlq %0,%0"
204 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
205 (set_attr "length" "*,*,*,*,8")])
207 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
209 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
210 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
212 [(set (match_dup 2) (match_dup 1))
213 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
214 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
216 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
217 ;; reload when converting fp->int.
220 [(set (match_operand:SI 0 "hard_int_register_operand" "")
221 (match_operand:SI 1 "memory_operand" ""))
222 (set (match_operand:DI 2 "hard_int_register_operand" "")
223 (sign_extend:DI (match_dup 0)))]
224 "true_regnum (operands[0]) == true_regnum (operands[2])
225 || peep2_reg_dead_p (2, operands[0])"
227 (sign_extend:DI (match_dup 1)))]
231 [(set (match_operand:SI 0 "hard_int_register_operand" "")
232 (match_operand:SI 1 "hard_fp_register_operand" ""))
233 (set (match_operand:DI 2 "hard_int_register_operand" "")
234 (sign_extend:DI (match_dup 0)))]
236 && (true_regnum (operands[0]) == true_regnum (operands[2])
237 || peep2_reg_dead_p (2, operands[0]))"
239 (sign_extend:DI (match_dup 1)))]
243 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
244 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
245 (set (match_operand:DI 2 "hard_int_register_operand" "")
247 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
249 (sign_extend:DI (match_dup 1)))]
252 ;; Don't say we have addsi3 if optimizing. This generates better code. We
253 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
254 (define_expand "addsi3"
255 [(set (match_operand:SI 0 "register_operand" "")
256 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
257 (match_operand:SI 2 "add_operand" "")))]
261 (define_insn "*addsi_internal"
262 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
263 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
264 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
273 [(set (match_operand:SI 0 "register_operand" "")
274 (plus:SI (match_operand:SI 1 "register_operand" "")
275 (match_operand:SI 2 "const_int_operand" "")))]
276 "! add_operand (operands[2], SImode)"
277 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
278 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
280 HOST_WIDE_INT val = INTVAL (operands[2]);
281 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
282 HOST_WIDE_INT rest = val - low;
284 operands[3] = GEN_INT (rest);
285 operands[4] = GEN_INT (low);
288 (define_insn "*addsi_se"
289 [(set (match_operand:DI 0 "register_operand" "=r,r")
291 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
292 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
298 (define_insn "*addsi_se2"
299 [(set (match_operand:DI 0 "register_operand" "=r,r")
301 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
302 (match_operand:DI 2 "sext_add_operand" "rI,O"))
310 [(set (match_operand:DI 0 "register_operand" "")
312 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
313 (match_operand:SI 2 "const_int_operand" ""))))
314 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
315 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
316 && INTVAL (operands[2]) % 4 == 0"
317 [(set (match_dup 3) (match_dup 4))
318 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
322 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
328 operands[4] = GEN_INT (val);
329 operands[5] = GEN_INT (mult);
333 [(set (match_operand:DI 0 "register_operand" "")
335 (plus:SI (match_operator:SI 1 "comparison_operator"
336 [(match_operand 2 "" "")
337 (match_operand 3 "" "")])
338 (match_operand:SI 4 "add_operand" ""))))
339 (clobber (match_operand:DI 5 "register_operand" ""))]
341 [(set (match_dup 5) (match_dup 6))
342 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
344 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
345 operands[2], operands[3]);
346 operands[7] = gen_lowpart (SImode, operands[5]);
349 (define_insn "addvsi3"
350 [(set (match_operand:SI 0 "register_operand" "=r,r")
351 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
352 (match_operand:SI 2 "sext_add_operand" "rI,O")))
353 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
354 (sign_extend:DI (match_dup 2)))
355 (sign_extend:DI (plus:SI (match_dup 1)
363 (define_expand "adddi3"
364 [(set (match_operand:DI 0 "register_operand" "")
365 (plus:DI (match_operand:DI 1 "register_operand" "")
366 (match_operand:DI 2 "add_operand" "")))]
370 (define_insn "*adddi_er_lo16_dtp"
371 [(set (match_operand:DI 0 "register_operand" "=r")
372 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
373 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
375 "lda %0,%2(%1)\t\t!dtprel")
377 (define_insn "*adddi_er_hi32_dtp"
378 [(set (match_operand:DI 0 "register_operand" "=r")
379 (plus:DI (match_operand:DI 1 "register_operand" "r")
380 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
382 "ldah %0,%2(%1)\t\t!dtprelhi")
384 (define_insn "*adddi_er_lo32_dtp"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
387 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
389 "lda %0,%2(%1)\t\t!dtprello")
391 (define_insn "*adddi_er_lo16_tp"
392 [(set (match_operand:DI 0 "register_operand" "=r")
393 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
394 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
396 "lda %0,%2(%1)\t\t!tprel")
398 (define_insn "*adddi_er_hi32_tp"
399 [(set (match_operand:DI 0 "register_operand" "=r")
400 (plus:DI (match_operand:DI 1 "register_operand" "r")
401 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
403 "ldah %0,%2(%1)\t\t!tprelhi")
405 (define_insn "*adddi_er_lo32_tp"
406 [(set (match_operand:DI 0 "register_operand" "=r")
407 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
408 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
410 "lda %0,%2(%1)\t\t!tprello")
412 (define_insn "*adddi_er_high_l"
413 [(set (match_operand:DI 0 "register_operand" "=r")
414 (plus:DI (match_operand:DI 1 "register_operand" "r")
415 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
416 "TARGET_EXPLICIT_RELOCS && reload_completed"
417 "ldah %0,%2(%1)\t\t!gprelhigh"
418 [(set_attr "usegp" "yes")])
421 [(set (match_operand:DI 0 "register_operand" "")
422 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
423 "TARGET_EXPLICIT_RELOCS && reload_completed"
425 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
426 "operands[2] = pic_offset_table_rtx;")
428 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
429 ;; With complications like
431 ;; The NT stack unwind code can't handle a subq to adjust the stack
432 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
433 ;; the exception handling code will loop if a subq is used and an
436 ;; The 19980616 change to emit prologues as RTL also confused some
437 ;; versions of GDB, which also interprets prologues. This has been
438 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
441 ;; and the fact that the three insns schedule exactly the same, it's
442 ;; just not worth the effort.
444 (define_insn "*adddi_internal"
445 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
446 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
447 (match_operand:DI 2 "add_operand" "r,K,L")))]
454 ;; ??? Allow large constants when basing off the frame pointer or some
455 ;; virtual register that may eliminate to the frame pointer. This is
456 ;; done because register elimination offsets will change the hi/lo split,
457 ;; and if we split before reload, we will require additional instructions.
459 (define_insn "*adddi_fp_hack"
460 [(set (match_operand:DI 0 "register_operand" "=r")
461 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
462 (match_operand:DI 2 "const_int_operand" "n")))]
463 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
464 && INTVAL (operands[2]) >= 0
465 /* This is the largest constant an lda+ldah pair can add, minus
466 an upper bound on the displacement between SP and AP during
467 register elimination. See INITIAL_ELIMINATION_OFFSET. */
468 && INTVAL (operands[2])
470 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
471 - ALPHA_ROUND(current_function_outgoing_args_size)
472 - (ALPHA_ROUND (get_frame_size ()
473 + max_reg_num () * UNITS_PER_WORD
474 + current_function_pretend_args_size)
475 - current_function_pretend_args_size))"
478 ;; Don't do this if we are adjusting SP since we don't want to do it
479 ;; in two steps. Don't split FP sources for the reason listed above.
481 [(set (match_operand:DI 0 "register_operand" "")
482 (plus:DI (match_operand:DI 1 "register_operand" "")
483 (match_operand:DI 2 "const_int_operand" "")))]
484 "! add_operand (operands[2], DImode)
485 && operands[0] != stack_pointer_rtx
486 && operands[1] != frame_pointer_rtx
487 && operands[1] != arg_pointer_rtx"
488 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
489 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
491 HOST_WIDE_INT val = INTVAL (operands[2]);
492 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
493 HOST_WIDE_INT rest = val - low;
495 operands[4] = GEN_INT (low);
496 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
497 operands[3] = GEN_INT (rest);
498 else if (! no_new_pseudos)
500 operands[3] = gen_reg_rtx (DImode);
501 emit_move_insn (operands[3], operands[2]);
502 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
509 (define_insn "*saddl"
510 [(set (match_operand:SI 0 "register_operand" "=r,r")
511 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
512 (match_operand:SI 2 "const48_operand" "I,I"))
513 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
519 (define_insn "*saddl_se"
520 [(set (match_operand:DI 0 "register_operand" "=r,r")
522 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
523 (match_operand:SI 2 "const48_operand" "I,I"))
524 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
531 [(set (match_operand:DI 0 "register_operand" "")
533 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
534 [(match_operand 2 "" "")
535 (match_operand 3 "" "")])
536 (match_operand:SI 4 "const48_operand" ""))
537 (match_operand:SI 5 "sext_add_operand" ""))))
538 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
540 [(set (match_dup 6) (match_dup 7))
542 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
545 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
546 operands[2], operands[3]);
547 operands[8] = gen_lowpart (SImode, operands[6]);
550 (define_insn "*saddq"
551 [(set (match_operand:DI 0 "register_operand" "=r,r")
552 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
553 (match_operand:DI 2 "const48_operand" "I,I"))
554 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
560 (define_insn "addvdi3"
561 [(set (match_operand:DI 0 "register_operand" "=r,r")
562 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
563 (match_operand:DI 2 "sext_add_operand" "rI,O")))
564 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
565 (sign_extend:TI (match_dup 2)))
566 (sign_extend:TI (plus:DI (match_dup 1)
574 (define_insn "negsi2"
575 [(set (match_operand:SI 0 "register_operand" "=r")
576 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
580 (define_insn "*negsi_se"
581 [(set (match_operand:DI 0 "register_operand" "=r")
582 (sign_extend:DI (neg:SI
583 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
587 (define_insn "negvsi2"
588 [(set (match_operand:SI 0 "register_operand" "=r")
589 (neg:SI (match_operand:SI 1 "register_operand" "r")))
590 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
591 (sign_extend:DI (neg:SI (match_dup 1))))
596 (define_insn "negdi2"
597 [(set (match_operand:DI 0 "register_operand" "=r")
598 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
602 (define_insn "negvdi2"
603 [(set (match_operand:DI 0 "register_operand" "=r")
604 (neg:DI (match_operand:DI 1 "register_operand" "r")))
605 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
606 (sign_extend:TI (neg:DI (match_dup 1))))
611 (define_expand "subsi3"
612 [(set (match_operand:SI 0 "register_operand" "")
613 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
614 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
618 (define_insn "*subsi_internal"
619 [(set (match_operand:SI 0 "register_operand" "=r")
620 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
621 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
625 (define_insn "*subsi_se"
626 [(set (match_operand:DI 0 "register_operand" "=r")
627 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
628 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
632 (define_insn "*subsi_se2"
633 [(set (match_operand:DI 0 "register_operand" "=r")
635 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
636 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
641 (define_insn "subvsi3"
642 [(set (match_operand:SI 0 "register_operand" "=r")
643 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
644 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
645 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
646 (sign_extend:DI (match_dup 2)))
647 (sign_extend:DI (minus:SI (match_dup 1)
653 (define_insn "subdi3"
654 [(set (match_operand:DI 0 "register_operand" "=r")
655 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
656 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
660 (define_insn "*ssubl"
661 [(set (match_operand:SI 0 "register_operand" "=r")
662 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
663 (match_operand:SI 2 "const48_operand" "I"))
664 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
668 (define_insn "*ssubl_se"
669 [(set (match_operand:DI 0 "register_operand" "=r")
671 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
672 (match_operand:SI 2 "const48_operand" "I"))
673 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
677 (define_insn "*ssubq"
678 [(set (match_operand:DI 0 "register_operand" "=r")
679 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
680 (match_operand:DI 2 "const48_operand" "I"))
681 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
685 (define_insn "subvdi3"
686 [(set (match_operand:DI 0 "register_operand" "=r")
687 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
688 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
689 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
690 (sign_extend:TI (match_dup 2)))
691 (sign_extend:TI (minus:DI (match_dup 1)
697 ;; The Unicos/Mk assembler doesn't support mull.
699 (define_insn "mulsi3"
700 [(set (match_operand:SI 0 "register_operand" "=r")
701 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
702 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
703 "!TARGET_ABI_UNICOSMK"
705 [(set_attr "type" "imul")
706 (set_attr "opsize" "si")])
708 (define_insn "*mulsi_se"
709 [(set (match_operand:DI 0 "register_operand" "=r")
711 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
712 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
713 "!TARGET_ABI_UNICOSMK"
715 [(set_attr "type" "imul")
716 (set_attr "opsize" "si")])
718 (define_insn "mulvsi3"
719 [(set (match_operand:SI 0 "register_operand" "=r")
720 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
721 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
722 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
723 (sign_extend:DI (match_dup 2)))
724 (sign_extend:DI (mult:SI (match_dup 1)
727 "!TARGET_ABI_UNICOSMK"
729 [(set_attr "type" "imul")
730 (set_attr "opsize" "si")])
732 (define_insn "muldi3"
733 [(set (match_operand:DI 0 "register_operand" "=r")
734 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
735 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
738 [(set_attr "type" "imul")])
740 (define_insn "mulvdi3"
741 [(set (match_operand:DI 0 "register_operand" "=r")
742 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
743 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
744 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
745 (sign_extend:TI (match_dup 2)))
746 (sign_extend:TI (mult:DI (match_dup 1)
751 [(set_attr "type" "imul")])
753 (define_insn "umuldi3_highpart"
754 [(set (match_operand:DI 0 "register_operand" "=r")
757 (mult:TI (zero_extend:TI
758 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
760 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
764 [(set_attr "type" "imul")
765 (set_attr "opsize" "udi")])
767 (define_insn "*umuldi3_highpart_const"
768 [(set (match_operand:DI 0 "register_operand" "=r")
771 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
772 (match_operand:TI 2 "cint8_operand" "I"))
776 [(set_attr "type" "imul")
777 (set_attr "opsize" "udi")])
779 ;; The divide and remainder operations take their inputs from r24 and
780 ;; r25, put their output in r27, and clobber r23 and r28 on all
781 ;; systems except Unicos/Mk. On Unicos, the standard library provides
782 ;; subroutines which use the standard calling convention and work on
785 ;; ??? Force sign-extension here because some versions of OSF/1 and
786 ;; Interix/NT don't do the right thing if the inputs are not properly
787 ;; sign-extended. But Linux, for instance, does not have this
788 ;; problem. Is it worth the complication here to eliminate the sign
791 (define_expand "divsi3"
793 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
795 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
796 (parallel [(set (match_dup 5)
797 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
798 (clobber (reg:DI 23))
799 (clobber (reg:DI 28))])
800 (set (match_operand:SI 0 "nonimmediate_operand" "")
801 (subreg:SI (match_dup 5) 0))]
802 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
804 operands[3] = gen_reg_rtx (DImode);
805 operands[4] = gen_reg_rtx (DImode);
806 operands[5] = gen_reg_rtx (DImode);
809 (define_expand "udivsi3"
811 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
813 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
814 (parallel [(set (match_dup 5)
815 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
816 (clobber (reg:DI 23))
817 (clobber (reg:DI 28))])
818 (set (match_operand:SI 0 "nonimmediate_operand" "")
819 (subreg:SI (match_dup 5) 0))]
820 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
822 operands[3] = gen_reg_rtx (DImode);
823 operands[4] = gen_reg_rtx (DImode);
824 operands[5] = gen_reg_rtx (DImode);
827 (define_expand "modsi3"
829 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
831 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
832 (parallel [(set (match_dup 5)
833 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
834 (clobber (reg:DI 23))
835 (clobber (reg:DI 28))])
836 (set (match_operand:SI 0 "nonimmediate_operand" "")
837 (subreg:SI (match_dup 5) 0))]
838 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
840 operands[3] = gen_reg_rtx (DImode);
841 operands[4] = gen_reg_rtx (DImode);
842 operands[5] = gen_reg_rtx (DImode);
845 (define_expand "umodsi3"
847 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
849 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
850 (parallel [(set (match_dup 5)
851 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
852 (clobber (reg:DI 23))
853 (clobber (reg:DI 28))])
854 (set (match_operand:SI 0 "nonimmediate_operand" "")
855 (subreg:SI (match_dup 5) 0))]
856 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
858 operands[3] = gen_reg_rtx (DImode);
859 operands[4] = gen_reg_rtx (DImode);
860 operands[5] = gen_reg_rtx (DImode);
863 (define_expand "divdi3"
864 [(parallel [(set (match_operand:DI 0 "register_operand" "")
865 (div:DI (match_operand:DI 1 "register_operand" "")
866 (match_operand:DI 2 "register_operand" "")))
867 (clobber (reg:DI 23))
868 (clobber (reg:DI 28))])]
869 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
872 (define_expand "udivdi3"
873 [(parallel [(set (match_operand:DI 0 "register_operand" "")
874 (udiv:DI (match_operand:DI 1 "register_operand" "")
875 (match_operand:DI 2 "register_operand" "")))
876 (clobber (reg:DI 23))
877 (clobber (reg:DI 28))])]
878 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
881 (define_expand "moddi3"
882 [(use (match_operand:DI 0 "register_operand" ""))
883 (use (match_operand:DI 1 "register_operand" ""))
884 (use (match_operand:DI 2 "register_operand" ""))]
885 "!TARGET_ABI_OPEN_VMS"
887 if (TARGET_ABI_UNICOSMK)
888 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
890 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
894 (define_expand "moddi3_dft"
895 [(parallel [(set (match_operand:DI 0 "register_operand" "")
896 (mod:DI (match_operand:DI 1 "register_operand" "")
897 (match_operand:DI 2 "register_operand" "")))
898 (clobber (reg:DI 23))
899 (clobber (reg:DI 28))])]
900 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
903 ;; On Unicos/Mk, we do as the system's C compiler does:
904 ;; compute the quotient, multiply and subtract.
906 (define_expand "moddi3_umk"
907 [(use (match_operand:DI 0 "register_operand" ""))
908 (use (match_operand:DI 1 "register_operand" ""))
909 (use (match_operand:DI 2 "register_operand" ""))]
910 "TARGET_ABI_UNICOSMK"
912 rtx div, mul = gen_reg_rtx (DImode);
914 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
915 NULL_RTX, 0, OPTAB_LIB);
916 div = force_reg (DImode, div);
917 emit_insn (gen_muldi3 (mul, operands[2], div));
918 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
922 (define_expand "umoddi3"
923 [(use (match_operand:DI 0 "register_operand" ""))
924 (use (match_operand:DI 1 "register_operand" ""))
925 (use (match_operand:DI 2 "register_operand" ""))]
926 "! TARGET_ABI_OPEN_VMS"
928 if (TARGET_ABI_UNICOSMK)
929 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
931 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
935 (define_expand "umoddi3_dft"
936 [(parallel [(set (match_operand:DI 0 "register_operand" "")
937 (umod:DI (match_operand:DI 1 "register_operand" "")
938 (match_operand:DI 2 "register_operand" "")))
939 (clobber (reg:DI 23))
940 (clobber (reg:DI 28))])]
941 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
944 (define_expand "umoddi3_umk"
945 [(use (match_operand:DI 0 "register_operand" ""))
946 (use (match_operand:DI 1 "register_operand" ""))
947 (use (match_operand:DI 2 "register_operand" ""))]
948 "TARGET_ABI_UNICOSMK"
950 rtx div, mul = gen_reg_rtx (DImode);
952 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
953 NULL_RTX, 1, OPTAB_LIB);
954 div = force_reg (DImode, div);
955 emit_insn (gen_muldi3 (mul, operands[2], div));
956 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
960 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
961 ;; expanded by the assembler.
963 (define_insn_and_split "*divmodsi_internal_er"
964 [(set (match_operand:DI 0 "register_operand" "=c")
965 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
966 [(match_operand:DI 1 "register_operand" "a")
967 (match_operand:DI 2 "register_operand" "b")])))
968 (clobber (reg:DI 23))
969 (clobber (reg:DI 28))]
970 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
971 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
972 "&& reload_completed"
973 [(parallel [(set (match_dup 0)
974 (sign_extend:DI (match_dup 3)))
977 (clobber (reg:DI 23))
978 (clobber (reg:DI 28))])]
981 switch (GET_CODE (operands[3]))
998 operands[4] = GEN_INT (alpha_next_sequence_number++);
999 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1000 gen_rtx_SYMBOL_REF (DImode, str),
1003 [(set_attr "type" "jsr")
1004 (set_attr "length" "8")])
1006 (define_insn "*divmodsi_internal_er_1"
1007 [(set (match_operand:DI 0 "register_operand" "=c")
1008 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1009 [(match_operand:DI 1 "register_operand" "a")
1010 (match_operand:DI 2 "register_operand" "b")])))
1011 (use (match_operand:DI 4 "register_operand" "c"))
1012 (use (match_operand 5 "const_int_operand" ""))
1013 (clobber (reg:DI 23))
1014 (clobber (reg:DI 28))]
1015 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1016 "jsr $23,($27),__%E3%J5"
1017 [(set_attr "type" "jsr")
1018 (set_attr "length" "4")])
1020 (define_insn "*divmodsi_internal"
1021 [(set (match_operand:DI 0 "register_operand" "=c")
1022 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1023 [(match_operand:DI 1 "register_operand" "a")
1024 (match_operand:DI 2 "register_operand" "b")])))
1025 (clobber (reg:DI 23))
1026 (clobber (reg:DI 28))]
1027 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1029 [(set_attr "type" "jsr")
1030 (set_attr "length" "8")])
1032 (define_insn_and_split "*divmoddi_internal_er"
1033 [(set (match_operand:DI 0 "register_operand" "=c")
1034 (match_operator:DI 3 "divmod_operator"
1035 [(match_operand:DI 1 "register_operand" "a")
1036 (match_operand:DI 2 "register_operand" "b")]))
1037 (clobber (reg:DI 23))
1038 (clobber (reg:DI 28))]
1039 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1040 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1041 "&& reload_completed"
1042 [(parallel [(set (match_dup 0) (match_dup 3))
1045 (clobber (reg:DI 23))
1046 (clobber (reg:DI 28))])]
1049 switch (GET_CODE (operands[3]))
1066 operands[4] = GEN_INT (alpha_next_sequence_number++);
1067 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1068 gen_rtx_SYMBOL_REF (DImode, str),
1071 [(set_attr "type" "jsr")
1072 (set_attr "length" "8")])
1074 (define_insn "*divmoddi_internal_er_1"
1075 [(set (match_operand:DI 0 "register_operand" "=c")
1076 (match_operator:DI 3 "divmod_operator"
1077 [(match_operand:DI 1 "register_operand" "a")
1078 (match_operand:DI 2 "register_operand" "b")]))
1079 (use (match_operand:DI 4 "register_operand" "c"))
1080 (use (match_operand 5 "const_int_operand" ""))
1081 (clobber (reg:DI 23))
1082 (clobber (reg:DI 28))]
1083 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1084 "jsr $23,($27),__%E3%J5"
1085 [(set_attr "type" "jsr")
1086 (set_attr "length" "4")])
1088 (define_insn "*divmoddi_internal"
1089 [(set (match_operand:DI 0 "register_operand" "=c")
1090 (match_operator:DI 3 "divmod_operator"
1091 [(match_operand:DI 1 "register_operand" "a")
1092 (match_operand:DI 2 "register_operand" "b")]))
1093 (clobber (reg:DI 23))
1094 (clobber (reg:DI 28))]
1095 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1097 [(set_attr "type" "jsr")
1098 (set_attr "length" "8")])
1100 ;; Next are the basic logical operations. These only exist in DImode.
1102 (define_insn "anddi3"
1103 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1104 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1105 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1111 [(set_attr "type" "ilog,ilog,shift")])
1113 ;; There are times when we can split an AND into two AND insns. This occurs
1114 ;; when we can first clear any bytes and then clear anything else. For
1115 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1116 ;; Only do this when running on 64-bit host since the computations are
1117 ;; too messy otherwise.
1120 [(set (match_operand:DI 0 "register_operand" "")
1121 (and:DI (match_operand:DI 1 "register_operand" "")
1122 (match_operand:DI 2 "const_int_operand" "")))]
1123 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1124 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1125 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1127 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1128 unsigned HOST_WIDE_INT mask2 = mask1;
1131 /* For each byte that isn't all zeros, make it all ones. */
1132 for (i = 0; i < 64; i += 8)
1133 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1134 mask1 |= (HOST_WIDE_INT) 0xff << i;
1136 /* Now turn on any bits we've just turned off. */
1139 operands[3] = GEN_INT (mask1);
1140 operands[4] = GEN_INT (mask2);
1143 (define_expand "zero_extendqihi2"
1144 [(set (match_operand:HI 0 "register_operand" "")
1145 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1149 operands[1] = force_reg (QImode, operands[1]);
1152 (define_insn "*zero_extendqihi2_bwx"
1153 [(set (match_operand:HI 0 "register_operand" "=r,r")
1154 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1159 [(set_attr "type" "ilog,ild")])
1161 (define_insn "*zero_extendqihi2_nobwx"
1162 [(set (match_operand:HI 0 "register_operand" "=r")
1163 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1166 [(set_attr "type" "ilog")])
1168 (define_expand "zero_extendqisi2"
1169 [(set (match_operand:SI 0 "register_operand" "")
1170 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1174 operands[1] = force_reg (QImode, operands[1]);
1177 (define_insn "*zero_extendqisi2_bwx"
1178 [(set (match_operand:SI 0 "register_operand" "=r,r")
1179 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1184 [(set_attr "type" "ilog,ild")])
1186 (define_insn "*zero_extendqisi2_nobwx"
1187 [(set (match_operand:SI 0 "register_operand" "=r")
1188 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1191 [(set_attr "type" "ilog")])
1193 (define_expand "zero_extendqidi2"
1194 [(set (match_operand:DI 0 "register_operand" "")
1195 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1199 operands[1] = force_reg (QImode, operands[1]);
1202 (define_insn "*zero_extendqidi2_bwx"
1203 [(set (match_operand:DI 0 "register_operand" "=r,r")
1204 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1209 [(set_attr "type" "ilog,ild")])
1211 (define_insn "*zero_extendqidi2_nobwx"
1212 [(set (match_operand:DI 0 "register_operand" "=r")
1213 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1216 [(set_attr "type" "ilog")])
1218 (define_expand "zero_extendhisi2"
1219 [(set (match_operand:SI 0 "register_operand" "")
1220 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1224 operands[1] = force_reg (HImode, operands[1]);
1227 (define_insn "*zero_extendhisi2_bwx"
1228 [(set (match_operand:SI 0 "register_operand" "=r,r")
1229 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1234 [(set_attr "type" "shift,ild")])
1236 (define_insn "*zero_extendhisi2_nobwx"
1237 [(set (match_operand:SI 0 "register_operand" "=r")
1238 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1241 [(set_attr "type" "shift")])
1243 (define_expand "zero_extendhidi2"
1244 [(set (match_operand:DI 0 "register_operand" "")
1245 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1249 operands[1] = force_reg (HImode, operands[1]);
1252 (define_insn "*zero_extendhidi2_bwx"
1253 [(set (match_operand:DI 0 "register_operand" "=r,r")
1254 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1259 [(set_attr "type" "shift,ild")])
1261 (define_insn "*zero_extendhidi2_nobwx"
1262 [(set (match_operand:DI 0 "register_operand" "=r")
1263 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1266 [(set_attr "type" "shift")])
1268 (define_insn "zero_extendsidi2"
1269 [(set (match_operand:DI 0 "register_operand" "=r")
1270 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1273 [(set_attr "type" "shift")])
1275 (define_insn "andnotdi3"
1276 [(set (match_operand:DI 0 "register_operand" "=r")
1277 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1278 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1281 [(set_attr "type" "ilog")])
1283 (define_insn "iordi3"
1284 [(set (match_operand:DI 0 "register_operand" "=r,r")
1285 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1286 (match_operand:DI 2 "or_operand" "rI,N")))]
1291 [(set_attr "type" "ilog")])
1293 (define_insn "one_cmpldi2"
1294 [(set (match_operand:DI 0 "register_operand" "=r")
1295 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1298 [(set_attr "type" "ilog")])
1300 (define_insn "*iornot"
1301 [(set (match_operand:DI 0 "register_operand" "=r")
1302 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1303 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1306 [(set_attr "type" "ilog")])
1308 (define_insn "xordi3"
1309 [(set (match_operand:DI 0 "register_operand" "=r,r")
1310 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1311 (match_operand:DI 2 "or_operand" "rI,N")))]
1316 [(set_attr "type" "ilog")])
1318 (define_insn "*xornot"
1319 [(set (match_operand:DI 0 "register_operand" "=r")
1320 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1321 (match_operand:DI 2 "register_operand" "rI"))))]
1324 [(set_attr "type" "ilog")])
1326 ;; Handle FFS and related insns iff we support CIX.
1328 (define_expand "ffsdi2"
1330 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1332 (plus:DI (match_dup 2) (const_int 1)))
1333 (set (match_operand:DI 0 "register_operand" "")
1334 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1335 (const_int 0) (match_dup 3)))]
1338 operands[2] = gen_reg_rtx (DImode);
1339 operands[3] = gen_reg_rtx (DImode);
1342 (define_insn "*cttz"
1343 [(set (match_operand:DI 0 "register_operand" "=r")
1344 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1347 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1348 ; reuse the existing type name.
1349 [(set_attr "type" "mvi")])
1351 (define_insn "clzdi2"
1352 [(set (match_operand:DI 0 "register_operand" "=r")
1353 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1356 [(set_attr "type" "mvi")])
1358 (define_insn "ctzdi2"
1359 [(set (match_operand:DI 0 "register_operand" "=r")
1360 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1363 [(set_attr "type" "mvi")])
1365 (define_insn "popcountdi2"
1366 [(set (match_operand:DI 0 "register_operand" "=r")
1367 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1370 [(set_attr "type" "mvi")])
1372 ;; Next come the shifts and the various extract and insert operations.
1374 (define_insn "ashldi3"
1375 [(set (match_operand:DI 0 "register_operand" "=r,r")
1376 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1377 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1380 switch (which_alternative)
1383 if (operands[2] == const1_rtx)
1384 return "addq %r1,%r1,%0";
1386 return "s%P2addq %r1,0,%0";
1388 return "sll %r1,%2,%0";
1393 [(set_attr "type" "iadd,shift")])
1395 (define_insn "*ashldi_se"
1396 [(set (match_operand:DI 0 "register_operand" "=r")
1398 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1399 (match_operand:DI 2 "const_int_operand" "P"))
1401 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1403 if (operands[2] == const1_rtx)
1404 return "addl %r1,%r1,%0";
1406 return "s%P2addl %r1,0,%0";
1408 [(set_attr "type" "iadd")])
1410 (define_insn "lshrdi3"
1411 [(set (match_operand:DI 0 "register_operand" "=r")
1412 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1413 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1416 [(set_attr "type" "shift")])
1418 (define_insn "ashrdi3"
1419 [(set (match_operand:DI 0 "register_operand" "=r")
1420 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1421 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1424 [(set_attr "type" "shift")])
1426 (define_expand "extendqihi2"
1428 (ashift:DI (match_operand:QI 1 "some_operand" "")
1430 (set (match_operand:HI 0 "register_operand" "")
1431 (ashiftrt:DI (match_dup 2)
1437 emit_insn (gen_extendqihi2x (operands[0],
1438 force_reg (QImode, operands[1])));
1442 /* If we have an unaligned MEM, extend to DImode (which we do
1443 specially) and then copy to the result. */
1444 if (unaligned_memory_operand (operands[1], HImode))
1446 rtx temp = gen_reg_rtx (DImode);
1448 emit_insn (gen_extendqidi2 (temp, operands[1]));
1449 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1453 operands[0] = gen_lowpart (DImode, operands[0]);
1454 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1455 operands[2] = gen_reg_rtx (DImode);
1458 (define_insn "extendqidi2x"
1459 [(set (match_operand:DI 0 "register_operand" "=r")
1460 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1463 [(set_attr "type" "shift")])
1465 (define_insn "extendhidi2x"
1466 [(set (match_operand:DI 0 "register_operand" "=r")
1467 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1470 [(set_attr "type" "shift")])
1472 (define_insn "extendqisi2x"
1473 [(set (match_operand:SI 0 "register_operand" "=r")
1474 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1477 [(set_attr "type" "shift")])
1479 (define_insn "extendhisi2x"
1480 [(set (match_operand:SI 0 "register_operand" "=r")
1481 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1484 [(set_attr "type" "shift")])
1486 (define_insn "extendqihi2x"
1487 [(set (match_operand:HI 0 "register_operand" "=r")
1488 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1491 [(set_attr "type" "shift")])
1493 (define_expand "extendqisi2"
1495 (ashift:DI (match_operand:QI 1 "some_operand" "")
1497 (set (match_operand:SI 0 "register_operand" "")
1498 (ashiftrt:DI (match_dup 2)
1504 emit_insn (gen_extendqisi2x (operands[0],
1505 force_reg (QImode, operands[1])));
1509 /* If we have an unaligned MEM, extend to a DImode form of
1510 the result (which we do specially). */
1511 if (unaligned_memory_operand (operands[1], QImode))
1513 rtx temp = gen_reg_rtx (DImode);
1515 emit_insn (gen_extendqidi2 (temp, operands[1]));
1516 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1520 operands[0] = gen_lowpart (DImode, operands[0]);
1521 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1522 operands[2] = gen_reg_rtx (DImode);
1525 (define_expand "extendqidi2"
1527 (ashift:DI (match_operand:QI 1 "some_operand" "")
1529 (set (match_operand:DI 0 "register_operand" "")
1530 (ashiftrt:DI (match_dup 2)
1536 emit_insn (gen_extendqidi2x (operands[0],
1537 force_reg (QImode, operands[1])));
1541 if (unaligned_memory_operand (operands[1], QImode))
1544 = gen_unaligned_extendqidi (operands[0],
1545 get_unaligned_address (operands[1], 1));
1547 alpha_set_memflags (seq, operands[1]);
1552 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1553 operands[2] = gen_reg_rtx (DImode);
1556 (define_expand "extendhisi2"
1558 (ashift:DI (match_operand:HI 1 "some_operand" "")
1560 (set (match_operand:SI 0 "register_operand" "")
1561 (ashiftrt:DI (match_dup 2)
1567 emit_insn (gen_extendhisi2x (operands[0],
1568 force_reg (HImode, operands[1])));
1572 /* If we have an unaligned MEM, extend to a DImode form of
1573 the result (which we do specially). */
1574 if (unaligned_memory_operand (operands[1], HImode))
1576 rtx temp = gen_reg_rtx (DImode);
1578 emit_insn (gen_extendhidi2 (temp, operands[1]));
1579 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1583 operands[0] = gen_lowpart (DImode, operands[0]);
1584 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1585 operands[2] = gen_reg_rtx (DImode);
1588 (define_expand "extendhidi2"
1590 (ashift:DI (match_operand:HI 1 "some_operand" "")
1592 (set (match_operand:DI 0 "register_operand" "")
1593 (ashiftrt:DI (match_dup 2)
1599 emit_insn (gen_extendhidi2x (operands[0],
1600 force_reg (HImode, operands[1])));
1604 if (unaligned_memory_operand (operands[1], HImode))
1607 = gen_unaligned_extendhidi (operands[0],
1608 get_unaligned_address (operands[1], 2));
1610 alpha_set_memflags (seq, operands[1]);
1615 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1616 operands[2] = gen_reg_rtx (DImode);
1619 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1620 ;; as a pattern saves one instruction. The code is similar to that for
1621 ;; the unaligned loads (see below).
1623 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1624 (define_expand "unaligned_extendqidi"
1625 [(use (match_operand:QI 0 "register_operand" ""))
1626 (use (match_operand:DI 1 "address_operand" ""))]
1629 if (WORDS_BIG_ENDIAN)
1630 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1632 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1636 (define_expand "unaligned_extendqidi_le"
1637 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1639 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1642 (ashift:DI (match_dup 3)
1643 (minus:DI (const_int 64)
1645 (and:DI (match_dup 2) (const_int 7))
1647 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1648 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1649 "! WORDS_BIG_ENDIAN"
1651 operands[2] = gen_reg_rtx (DImode);
1652 operands[3] = gen_reg_rtx (DImode);
1653 operands[4] = gen_reg_rtx (DImode);
1656 (define_expand "unaligned_extendqidi_be"
1657 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1658 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1660 (mem:DI (and:DI (match_dup 3)
1662 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1664 (ashift:DI (match_dup 4)
1667 (plus:DI (match_dup 5) (const_int 1))
1670 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1671 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1674 operands[2] = gen_reg_rtx (DImode);
1675 operands[3] = gen_reg_rtx (DImode);
1676 operands[4] = gen_reg_rtx (DImode);
1677 operands[5] = gen_reg_rtx (DImode);
1678 operands[6] = gen_reg_rtx (DImode);
1681 (define_expand "unaligned_extendhidi"
1682 [(use (match_operand:QI 0 "register_operand" ""))
1683 (use (match_operand:DI 1 "address_operand" ""))]
1686 operands[0] = gen_lowpart (DImode, operands[0]);
1687 emit_insn ((WORDS_BIG_ENDIAN
1688 ? gen_unaligned_extendhidi_be
1689 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1693 (define_expand "unaligned_extendhidi_le"
1694 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1696 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1699 (ashift:DI (match_dup 3)
1700 (minus:DI (const_int 64)
1702 (and:DI (match_dup 2) (const_int 7))
1704 (set (match_operand:DI 0 "register_operand" "")
1705 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1706 "! WORDS_BIG_ENDIAN"
1708 operands[2] = gen_reg_rtx (DImode);
1709 operands[3] = gen_reg_rtx (DImode);
1710 operands[4] = gen_reg_rtx (DImode);
1713 (define_expand "unaligned_extendhidi_be"
1714 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1715 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1717 (mem:DI (and:DI (match_dup 3)
1719 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1721 (ashift:DI (match_dup 4)
1724 (plus:DI (match_dup 5) (const_int 1))
1727 (set (match_operand:DI 0 "register_operand" "")
1728 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1731 operands[2] = gen_reg_rtx (DImode);
1732 operands[3] = gen_reg_rtx (DImode);
1733 operands[4] = gen_reg_rtx (DImode);
1734 operands[5] = gen_reg_rtx (DImode);
1735 operands[6] = gen_reg_rtx (DImode);
1738 (define_insn "*extxl_const"
1739 [(set (match_operand:DI 0 "register_operand" "=r")
1740 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1741 (match_operand:DI 2 "mode_width_operand" "n")
1742 (match_operand:DI 3 "mul8_operand" "I")))]
1744 "ext%M2l %r1,%s3,%0"
1745 [(set_attr "type" "shift")])
1747 (define_insn "extxl_le"
1748 [(set (match_operand:DI 0 "register_operand" "=r")
1749 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1750 (match_operand:DI 2 "mode_width_operand" "n")
1751 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1753 "! WORDS_BIG_ENDIAN"
1755 [(set_attr "type" "shift")])
1757 (define_insn "extxl_be"
1758 [(set (match_operand:DI 0 "register_operand" "=r")
1759 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1760 (match_operand:DI 2 "mode_width_operand" "n")
1764 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1768 [(set_attr "type" "shift")])
1770 ;; Combine has some strange notion of preserving existing undefined behavior
1771 ;; in shifts larger than a word size. So capture these patterns that it
1772 ;; should have turned into zero_extracts.
1774 (define_insn "*extxl_1_le"
1775 [(set (match_operand:DI 0 "register_operand" "=r")
1776 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1777 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1779 (match_operand:DI 3 "mode_mask_operand" "n")))]
1780 "! WORDS_BIG_ENDIAN"
1782 [(set_attr "type" "shift")])
1784 (define_insn "*extxl_1_be"
1785 [(set (match_operand:DI 0 "register_operand" "=r")
1786 (and:DI (lshiftrt:DI
1787 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1788 (minus:DI (const_int 56)
1789 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1791 (match_operand:DI 3 "mode_mask_operand" "n")))]
1794 [(set_attr "type" "shift")])
1796 (define_insn "*extql_2_le"
1797 [(set (match_operand:DI 0 "register_operand" "=r")
1798 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1799 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1801 "! WORDS_BIG_ENDIAN"
1803 [(set_attr "type" "shift")])
1805 (define_insn "*extql_2_be"
1806 [(set (match_operand:DI 0 "register_operand" "=r")
1808 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1809 (minus:DI (const_int 56)
1811 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1815 [(set_attr "type" "shift")])
1817 (define_insn "extqh_le"
1818 [(set (match_operand:DI 0 "register_operand" "=r")
1820 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1821 (minus:DI (const_int 64)
1824 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1827 "! WORDS_BIG_ENDIAN"
1829 [(set_attr "type" "shift")])
1831 (define_insn "extqh_be"
1832 [(set (match_operand:DI 0 "register_operand" "=r")
1834 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1837 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1843 [(set_attr "type" "shift")])
1845 (define_insn "extlh_le"
1846 [(set (match_operand:DI 0 "register_operand" "=r")
1848 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1849 (const_int 2147483647))
1850 (minus:DI (const_int 64)
1853 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1856 "! WORDS_BIG_ENDIAN"
1858 [(set_attr "type" "shift")])
1860 (define_insn "extlh_be"
1861 [(set (match_operand:DI 0 "register_operand" "=r")
1864 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1868 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1872 (const_int 2147483647)))]
1875 [(set_attr "type" "shift")])
1877 (define_insn "extwh_le"
1878 [(set (match_operand:DI 0 "register_operand" "=r")
1880 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1882 (minus:DI (const_int 64)
1885 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1888 "! WORDS_BIG_ENDIAN"
1890 [(set_attr "type" "shift")])
1892 (define_insn "extwh_be"
1893 [(set (match_operand:DI 0 "register_operand" "=r")
1895 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1899 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1903 (const_int 65535)))]
1906 [(set_attr "type" "shift")])
1908 ;; This converts an extXl into an extXh with an appropriate adjustment
1909 ;; to the address calculation.
1912 ;; [(set (match_operand:DI 0 "register_operand" "")
1913 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1914 ;; (match_operand:DI 2 "mode_width_operand" "")
1915 ;; (ashift:DI (match_operand:DI 3 "" "")
1917 ;; (match_operand:DI 4 "const_int_operand" "")))
1918 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1919 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1920 ;; [(set (match_dup 5) (match_dup 6))
1921 ;; (set (match_dup 0)
1922 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1923 ;; (ashift:DI (plus:DI (match_dup 5)
1929 ;; operands[6] = plus_constant (operands[3],
1930 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1931 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1934 (define_insn "*insbl_const"
1935 [(set (match_operand:DI 0 "register_operand" "=r")
1936 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1937 (match_operand:DI 2 "mul8_operand" "I")))]
1940 [(set_attr "type" "shift")])
1942 (define_insn "*inswl_const"
1943 [(set (match_operand:DI 0 "register_operand" "=r")
1944 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1945 (match_operand:DI 2 "mul8_operand" "I")))]
1948 [(set_attr "type" "shift")])
1950 (define_insn "*insll_const"
1951 [(set (match_operand:DI 0 "register_operand" "=r")
1952 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1953 (match_operand:DI 2 "mul8_operand" "I")))]
1956 [(set_attr "type" "shift")])
1958 (define_insn "insbl_le"
1959 [(set (match_operand:DI 0 "register_operand" "=r")
1960 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1961 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1963 "! WORDS_BIG_ENDIAN"
1965 [(set_attr "type" "shift")])
1967 (define_insn "insbl_be"
1968 [(set (match_operand:DI 0 "register_operand" "=r")
1969 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1970 (minus:DI (const_int 56)
1971 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1975 [(set_attr "type" "shift")])
1977 (define_insn "inswl_le"
1978 [(set (match_operand:DI 0 "register_operand" "=r")
1979 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1980 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1982 "! WORDS_BIG_ENDIAN"
1984 [(set_attr "type" "shift")])
1986 (define_insn "inswl_be"
1987 [(set (match_operand:DI 0 "register_operand" "=r")
1988 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1989 (minus:DI (const_int 56)
1990 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1994 [(set_attr "type" "shift")])
1996 (define_insn "insll_le"
1997 [(set (match_operand:DI 0 "register_operand" "=r")
1998 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1999 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2001 "! WORDS_BIG_ENDIAN"
2003 [(set_attr "type" "shift")])
2005 (define_insn "insll_be"
2006 [(set (match_operand:DI 0 "register_operand" "=r")
2007 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2008 (minus:DI (const_int 56)
2009 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2013 [(set_attr "type" "shift")])
2015 (define_insn "insql_le"
2016 [(set (match_operand:DI 0 "register_operand" "=r")
2017 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2018 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2020 "! WORDS_BIG_ENDIAN"
2022 [(set_attr "type" "shift")])
2024 (define_insn "insql_be"
2025 [(set (match_operand:DI 0 "register_operand" "=r")
2026 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2027 (minus:DI (const_int 56)
2028 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2032 [(set_attr "type" "shift")])
2034 ;; Combine has this sometimes habit of moving the and outside of the
2035 ;; shift, making life more interesting.
2037 (define_insn "*insxl"
2038 [(set (match_operand:DI 0 "register_operand" "=r")
2039 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2040 (match_operand:DI 2 "mul8_operand" "I"))
2041 (match_operand:DI 3 "immediate_operand" "i")))]
2042 "HOST_BITS_PER_WIDE_INT == 64
2043 && GET_CODE (operands[3]) == CONST_INT
2044 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2045 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2046 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2047 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2048 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2049 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2051 #if HOST_BITS_PER_WIDE_INT == 64
2052 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2053 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2054 return "insbl %1,%s2,%0";
2055 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2056 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2057 return "inswl %1,%s2,%0";
2058 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2059 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2060 return "insll %1,%s2,%0";
2064 [(set_attr "type" "shift")])
2066 ;; We do not include the insXh insns because they are complex to express
2067 ;; and it does not appear that we would ever want to generate them.
2069 ;; Since we need them for block moves, though, cop out and use unspec.
2071 (define_insn "insxh"
2072 [(set (match_operand:DI 0 "register_operand" "=r")
2073 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2074 (match_operand:DI 2 "mode_width_operand" "n")
2075 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2079 [(set_attr "type" "shift")])
2081 (define_insn "mskxl_le"
2082 [(set (match_operand:DI 0 "register_operand" "=r")
2083 (and:DI (not:DI (ashift:DI
2084 (match_operand:DI 2 "mode_mask_operand" "n")
2086 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2088 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2089 "! WORDS_BIG_ENDIAN"
2091 [(set_attr "type" "shift")])
2093 (define_insn "mskxl_be"
2094 [(set (match_operand:DI 0 "register_operand" "=r")
2095 (and:DI (not:DI (ashift:DI
2096 (match_operand:DI 2 "mode_mask_operand" "n")
2097 (minus:DI (const_int 56)
2099 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2101 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2104 [(set_attr "type" "shift")])
2106 ;; We do not include the mskXh insns because it does not appear we would
2107 ;; ever generate one.
2109 ;; Again, we do for block moves and we use unspec again.
2111 (define_insn "mskxh"
2112 [(set (match_operand:DI 0 "register_operand" "=r")
2113 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2114 (match_operand:DI 2 "mode_width_operand" "n")
2115 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2119 [(set_attr "type" "shift")])
2121 ;; Prefer AND + NE over LSHIFTRT + AND.
2123 (define_insn_and_split "*ze_and_ne"
2124 [(set (match_operand:DI 0 "register_operand" "=r")
2125 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2127 (match_operand 2 "const_int_operand" "I")))]
2128 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2130 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2132 (and:DI (match_dup 1) (match_dup 3)))
2134 (ne:DI (match_dup 0) (const_int 0)))]
2135 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2137 ;; Floating-point operations. All the double-precision insns can extend
2138 ;; from single, so indicate that. The exception are the ones that simply
2139 ;; play with the sign bits; it's not clear what to do there.
2141 (define_insn "abssf2"
2142 [(set (match_operand:SF 0 "register_operand" "=f")
2143 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2146 [(set_attr "type" "fcpys")])
2148 (define_insn "*nabssf2"
2149 [(set (match_operand:SF 0 "register_operand" "=f")
2150 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2153 [(set_attr "type" "fadd")])
2155 (define_insn "absdf2"
2156 [(set (match_operand:DF 0 "register_operand" "=f")
2157 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2160 [(set_attr "type" "fcpys")])
2162 (define_insn "*nabsdf2"
2163 [(set (match_operand:DF 0 "register_operand" "=f")
2164 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2167 [(set_attr "type" "fadd")])
2169 (define_expand "abstf2"
2170 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2171 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2172 (use (match_dup 2))])]
2173 "TARGET_HAS_XFLOATING_LIBS"
2175 #if HOST_BITS_PER_WIDE_INT >= 64
2176 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2178 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2182 (define_insn_and_split "*abstf_internal"
2183 [(set (match_operand:TF 0 "register_operand" "=r")
2184 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2185 (use (match_operand:DI 2 "register_operand" "r"))]
2186 "TARGET_HAS_XFLOATING_LIBS"
2188 "&& reload_completed"
2190 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2192 (define_insn "negsf2"
2193 [(set (match_operand:SF 0 "register_operand" "=f")
2194 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2197 [(set_attr "type" "fadd")])
2199 (define_insn "negdf2"
2200 [(set (match_operand:DF 0 "register_operand" "=f")
2201 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2204 [(set_attr "type" "fadd")])
2206 (define_expand "negtf2"
2207 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2208 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2209 (use (match_dup 2))])]
2210 "TARGET_HAS_XFLOATING_LIBS"
2212 #if HOST_BITS_PER_WIDE_INT >= 64
2213 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2215 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2219 (define_insn_and_split "*negtf_internal"
2220 [(set (match_operand:TF 0 "register_operand" "=r")
2221 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2222 (use (match_operand:DI 2 "register_operand" "r"))]
2223 "TARGET_HAS_XFLOATING_LIBS"
2225 "&& reload_completed"
2227 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2229 (define_insn "*addsf_ieee"
2230 [(set (match_operand:SF 0 "register_operand" "=&f")
2231 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2232 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2233 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2234 "add%,%/ %R1,%R2,%0"
2235 [(set_attr "type" "fadd")
2236 (set_attr "trap" "yes")
2237 (set_attr "round_suffix" "normal")
2238 (set_attr "trap_suffix" "u_su_sui")])
2240 (define_insn "addsf3"
2241 [(set (match_operand:SF 0 "register_operand" "=f")
2242 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2243 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2245 "add%,%/ %R1,%R2,%0"
2246 [(set_attr "type" "fadd")
2247 (set_attr "trap" "yes")
2248 (set_attr "round_suffix" "normal")
2249 (set_attr "trap_suffix" "u_su_sui")])
2251 (define_insn "*adddf_ieee"
2252 [(set (match_operand:DF 0 "register_operand" "=&f")
2253 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2254 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2255 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2256 "add%-%/ %R1,%R2,%0"
2257 [(set_attr "type" "fadd")
2258 (set_attr "trap" "yes")
2259 (set_attr "round_suffix" "normal")
2260 (set_attr "trap_suffix" "u_su_sui")])
2262 (define_insn "adddf3"
2263 [(set (match_operand:DF 0 "register_operand" "=f")
2264 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2265 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2267 "add%-%/ %R1,%R2,%0"
2268 [(set_attr "type" "fadd")
2269 (set_attr "trap" "yes")
2270 (set_attr "round_suffix" "normal")
2271 (set_attr "trap_suffix" "u_su_sui")])
2273 (define_insn "*adddf_ext1"
2274 [(set (match_operand:DF 0 "register_operand" "=f")
2275 (plus:DF (float_extend:DF
2276 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2277 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2278 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2279 "add%-%/ %R1,%R2,%0"
2280 [(set_attr "type" "fadd")
2281 (set_attr "trap" "yes")
2282 (set_attr "round_suffix" "normal")
2283 (set_attr "trap_suffix" "u_su_sui")])
2285 (define_insn "*adddf_ext2"
2286 [(set (match_operand:DF 0 "register_operand" "=f")
2287 (plus:DF (float_extend:DF
2288 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2290 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2291 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2292 "add%-%/ %R1,%R2,%0"
2293 [(set_attr "type" "fadd")
2294 (set_attr "trap" "yes")
2295 (set_attr "round_suffix" "normal")
2296 (set_attr "trap_suffix" "u_su_sui")])
2298 (define_expand "addtf3"
2299 [(use (match_operand 0 "register_operand" ""))
2300 (use (match_operand 1 "general_operand" ""))
2301 (use (match_operand 2 "general_operand" ""))]
2302 "TARGET_HAS_XFLOATING_LIBS"
2303 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2305 ;; Define conversion operators between DFmode and SImode, using the cvtql
2306 ;; instruction. To allow combine et al to do useful things, we keep the
2307 ;; operation as a unit until after reload, at which point we split the
2310 ;; Note that we (attempt to) only consider this optimization when the
2311 ;; ultimate destination is memory. If we will be doing further integer
2312 ;; processing, it is cheaper to do the truncation in the int regs.
2314 (define_insn "*cvtql"
2315 [(set (match_operand:SI 0 "register_operand" "=f")
2316 (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2320 [(set_attr "type" "fadd")
2321 (set_attr "trap" "yes")
2322 (set_attr "trap_suffix" "v_sv")])
2324 (define_insn_and_split "*fix_truncdfsi_ieee"
2325 [(set (match_operand:SI 0 "memory_operand" "=m")
2326 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2327 (clobber (match_scratch:DI 2 "=&f"))
2328 (clobber (match_scratch:SI 3 "=&f"))]
2329 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2331 "&& reload_completed"
2332 [(set (match_dup 2) (fix:DI (match_dup 1)))
2333 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2334 (set (match_dup 0) (match_dup 3))]
2336 [(set_attr "type" "fadd")
2337 (set_attr "trap" "yes")])
2339 (define_insn_and_split "*fix_truncdfsi_internal"
2340 [(set (match_operand:SI 0 "memory_operand" "=m")
2341 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
2342 (clobber (match_scratch:DI 2 "=f"))]
2343 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2345 "&& reload_completed"
2346 [(set (match_dup 2) (fix:DI (match_dup 1)))
2347 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2348 (set (match_dup 0) (match_dup 3))]
2349 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2350 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2351 [(set_attr "type" "fadd")
2352 (set_attr "trap" "yes")])
2354 (define_insn "*fix_truncdfdi_ieee"
2355 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2356 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2357 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2359 [(set_attr "type" "fadd")
2360 (set_attr "trap" "yes")
2361 (set_attr "round_suffix" "c")
2362 (set_attr "trap_suffix" "v_sv_svi")])
2364 (define_insn "fix_truncdfdi2"
2365 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2366 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2369 [(set_attr "type" "fadd")
2370 (set_attr "trap" "yes")
2371 (set_attr "round_suffix" "c")
2372 (set_attr "trap_suffix" "v_sv_svi")])
2374 ;; Likewise between SFmode and SImode.
2376 (define_insn_and_split "*fix_truncsfsi_ieee"
2377 [(set (match_operand:SI 0 "memory_operand" "=m")
2378 (subreg:SI (fix:DI (float_extend:DF
2379 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2380 (clobber (match_scratch:DI 2 "=&f"))
2381 (clobber (match_scratch:SI 3 "=&f"))]
2382 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2384 "&& reload_completed"
2385 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2386 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2387 (set (match_dup 0) (match_dup 3))]
2389 [(set_attr "type" "fadd")
2390 (set_attr "trap" "yes")])
2392 (define_insn_and_split "*fix_truncsfsi_internal"
2393 [(set (match_operand:SI 0 "memory_operand" "=m")
2394 (subreg:SI (fix:DI (float_extend:DF
2395 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
2396 (clobber (match_scratch:DI 2 "=f"))]
2397 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2399 "&& reload_completed"
2400 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2401 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2402 (set (match_dup 0) (match_dup 3))]
2403 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2404 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2405 [(set_attr "type" "fadd")
2406 (set_attr "trap" "yes")])
2408 (define_insn "*fix_truncsfdi_ieee"
2409 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2410 (fix:DI (float_extend:DF
2411 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2412 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2414 [(set_attr "type" "fadd")
2415 (set_attr "trap" "yes")
2416 (set_attr "round_suffix" "c")
2417 (set_attr "trap_suffix" "v_sv_svi")])
2419 (define_insn "fix_truncsfdi2"
2420 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2421 (fix:DI (float_extend:DF
2422 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2425 [(set_attr "type" "fadd")
2426 (set_attr "trap" "yes")
2427 (set_attr "round_suffix" "c")
2428 (set_attr "trap_suffix" "v_sv_svi")])
2430 (define_expand "fix_trunctfdi2"
2431 [(use (match_operand:DI 0 "register_operand" ""))
2432 (use (match_operand:TF 1 "general_operand" ""))]
2433 "TARGET_HAS_XFLOATING_LIBS"
2434 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2436 (define_insn "*floatdisf_ieee"
2437 [(set (match_operand:SF 0 "register_operand" "=&f")
2438 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2439 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2441 [(set_attr "type" "fadd")
2442 (set_attr "trap" "yes")
2443 (set_attr "round_suffix" "normal")
2444 (set_attr "trap_suffix" "sui")])
2446 (define_insn "floatdisf2"
2447 [(set (match_operand:SF 0 "register_operand" "=f")
2448 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2451 [(set_attr "type" "fadd")
2452 (set_attr "trap" "yes")
2453 (set_attr "round_suffix" "normal")
2454 (set_attr "trap_suffix" "sui")])
2456 (define_insn "*floatdidf_ieee"
2457 [(set (match_operand:DF 0 "register_operand" "=&f")
2458 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2459 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2461 [(set_attr "type" "fadd")
2462 (set_attr "trap" "yes")
2463 (set_attr "round_suffix" "normal")
2464 (set_attr "trap_suffix" "sui")])
2466 (define_insn "floatdidf2"
2467 [(set (match_operand:DF 0 "register_operand" "=f")
2468 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2471 [(set_attr "type" "fadd")
2472 (set_attr "trap" "yes")
2473 (set_attr "round_suffix" "normal")
2474 (set_attr "trap_suffix" "sui")])
2476 (define_expand "floatditf2"
2477 [(use (match_operand:TF 0 "register_operand" ""))
2478 (use (match_operand:DI 1 "general_operand" ""))]
2479 "TARGET_HAS_XFLOATING_LIBS"
2480 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2482 (define_expand "floatunsdisf2"
2483 [(use (match_operand:SF 0 "register_operand" ""))
2484 (use (match_operand:DI 1 "register_operand" ""))]
2486 "alpha_emit_floatuns (operands); DONE;")
2488 (define_expand "floatunsdidf2"
2489 [(use (match_operand:DF 0 "register_operand" ""))
2490 (use (match_operand:DI 1 "register_operand" ""))]
2492 "alpha_emit_floatuns (operands); DONE;")
2494 (define_expand "floatunsditf2"
2495 [(use (match_operand:TF 0 "register_operand" ""))
2496 (use (match_operand:DI 1 "general_operand" ""))]
2497 "TARGET_HAS_XFLOATING_LIBS"
2498 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2500 (define_expand "extendsfdf2"
2501 [(set (match_operand:DF 0 "register_operand" "")
2502 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2505 if (alpha_fptm >= ALPHA_FPTM_SU)
2506 operands[1] = force_reg (SFmode, operands[1]);
2509 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2510 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2512 (define_insn "*extendsfdf2_ieee"
2513 [(set (match_operand:DF 0 "register_operand" "=&f")
2514 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2515 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2517 [(set_attr "type" "fadd")
2518 (set_attr "trap" "yes")])
2520 (define_insn "*extendsfdf2_internal"
2521 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2522 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2523 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2528 [(set_attr "type" "fcpys,fld,fst")])
2530 (define_expand "extendsftf2"
2531 [(use (match_operand:TF 0 "register_operand" ""))
2532 (use (match_operand:SF 1 "general_operand" ""))]
2533 "TARGET_HAS_XFLOATING_LIBS"
2535 rtx tmp = gen_reg_rtx (DFmode);
2536 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2537 emit_insn (gen_extenddftf2 (operands[0], tmp));
2541 (define_expand "extenddftf2"
2542 [(use (match_operand:TF 0 "register_operand" ""))
2543 (use (match_operand:DF 1 "general_operand" ""))]
2544 "TARGET_HAS_XFLOATING_LIBS"
2545 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2547 (define_insn "*truncdfsf2_ieee"
2548 [(set (match_operand:SF 0 "register_operand" "=&f")
2549 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2550 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2552 [(set_attr "type" "fadd")
2553 (set_attr "trap" "yes")
2554 (set_attr "round_suffix" "normal")
2555 (set_attr "trap_suffix" "u_su_sui")])
2557 (define_insn "truncdfsf2"
2558 [(set (match_operand:SF 0 "register_operand" "=f")
2559 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2562 [(set_attr "type" "fadd")
2563 (set_attr "trap" "yes")
2564 (set_attr "round_suffix" "normal")
2565 (set_attr "trap_suffix" "u_su_sui")])
2567 (define_expand "trunctfdf2"
2568 [(use (match_operand:DF 0 "register_operand" ""))
2569 (use (match_operand:TF 1 "general_operand" ""))]
2570 "TARGET_HAS_XFLOATING_LIBS"
2571 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2573 (define_expand "trunctfsf2"
2574 [(use (match_operand:SF 0 "register_operand" ""))
2575 (use (match_operand:TF 1 "general_operand" ""))]
2576 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2578 rtx tmpf, sticky, arg, lo, hi;
2580 tmpf = gen_reg_rtx (DFmode);
2581 sticky = gen_reg_rtx (DImode);
2582 arg = copy_to_mode_reg (TFmode, operands[1]);
2583 lo = gen_lowpart (DImode, arg);
2584 hi = gen_highpart (DImode, arg);
2586 /* Convert the low word of the TFmode value into a sticky rounding bit,
2587 then or it into the low bit of the high word. This leaves the sticky
2588 bit at bit 48 of the fraction, which is representable in DFmode,
2589 which prevents rounding error in the final conversion to SFmode. */
2591 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2592 gen_rtx_NE (DImode, lo, const0_rtx)));
2593 emit_insn (gen_iordi3 (hi, hi, sticky));
2594 emit_insn (gen_trunctfdf2 (tmpf, arg));
2595 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2599 (define_insn "*divsf3_ieee"
2600 [(set (match_operand:SF 0 "register_operand" "=&f")
2601 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2602 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2603 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2604 "div%,%/ %R1,%R2,%0"
2605 [(set_attr "type" "fdiv")
2606 (set_attr "opsize" "si")
2607 (set_attr "trap" "yes")
2608 (set_attr "round_suffix" "normal")
2609 (set_attr "trap_suffix" "u_su_sui")])
2611 (define_insn "divsf3"
2612 [(set (match_operand:SF 0 "register_operand" "=f")
2613 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2614 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2616 "div%,%/ %R1,%R2,%0"
2617 [(set_attr "type" "fdiv")
2618 (set_attr "opsize" "si")
2619 (set_attr "trap" "yes")
2620 (set_attr "round_suffix" "normal")
2621 (set_attr "trap_suffix" "u_su_sui")])
2623 (define_insn "*divdf3_ieee"
2624 [(set (match_operand:DF 0 "register_operand" "=&f")
2625 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2626 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2627 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2628 "div%-%/ %R1,%R2,%0"
2629 [(set_attr "type" "fdiv")
2630 (set_attr "trap" "yes")
2631 (set_attr "round_suffix" "normal")
2632 (set_attr "trap_suffix" "u_su_sui")])
2634 (define_insn "divdf3"
2635 [(set (match_operand:DF 0 "register_operand" "=f")
2636 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2637 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2639 "div%-%/ %R1,%R2,%0"
2640 [(set_attr "type" "fdiv")
2641 (set_attr "trap" "yes")
2642 (set_attr "round_suffix" "normal")
2643 (set_attr "trap_suffix" "u_su_sui")])
2645 (define_insn "*divdf_ext1"
2646 [(set (match_operand:DF 0 "register_operand" "=f")
2647 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2648 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2649 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2650 "div%-%/ %R1,%R2,%0"
2651 [(set_attr "type" "fdiv")
2652 (set_attr "trap" "yes")
2653 (set_attr "round_suffix" "normal")
2654 (set_attr "trap_suffix" "u_su_sui")])
2656 (define_insn "*divdf_ext2"
2657 [(set (match_operand:DF 0 "register_operand" "=f")
2658 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2660 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2661 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2662 "div%-%/ %R1,%R2,%0"
2663 [(set_attr "type" "fdiv")
2664 (set_attr "trap" "yes")
2665 (set_attr "round_suffix" "normal")
2666 (set_attr "trap_suffix" "u_su_sui")])
2668 (define_insn "*divdf_ext3"
2669 [(set (match_operand:DF 0 "register_operand" "=f")
2670 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2671 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2672 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2673 "div%-%/ %R1,%R2,%0"
2674 [(set_attr "type" "fdiv")
2675 (set_attr "trap" "yes")
2676 (set_attr "round_suffix" "normal")
2677 (set_attr "trap_suffix" "u_su_sui")])
2679 (define_expand "divtf3"
2680 [(use (match_operand 0 "register_operand" ""))
2681 (use (match_operand 1 "general_operand" ""))
2682 (use (match_operand 2 "general_operand" ""))]
2683 "TARGET_HAS_XFLOATING_LIBS"
2684 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2686 (define_insn "*mulsf3_ieee"
2687 [(set (match_operand:SF 0 "register_operand" "=&f")
2688 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2689 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2690 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2691 "mul%,%/ %R1,%R2,%0"
2692 [(set_attr "type" "fmul")
2693 (set_attr "trap" "yes")
2694 (set_attr "round_suffix" "normal")
2695 (set_attr "trap_suffix" "u_su_sui")])
2697 (define_insn "mulsf3"
2698 [(set (match_operand:SF 0 "register_operand" "=f")
2699 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2700 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2702 "mul%,%/ %R1,%R2,%0"
2703 [(set_attr "type" "fmul")
2704 (set_attr "trap" "yes")
2705 (set_attr "round_suffix" "normal")
2706 (set_attr "trap_suffix" "u_su_sui")])
2708 (define_insn "*muldf3_ieee"
2709 [(set (match_operand:DF 0 "register_operand" "=&f")
2710 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2711 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2712 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2713 "mul%-%/ %R1,%R2,%0"
2714 [(set_attr "type" "fmul")
2715 (set_attr "trap" "yes")
2716 (set_attr "round_suffix" "normal")
2717 (set_attr "trap_suffix" "u_su_sui")])
2719 (define_insn "muldf3"
2720 [(set (match_operand:DF 0 "register_operand" "=f")
2721 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2722 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2724 "mul%-%/ %R1,%R2,%0"
2725 [(set_attr "type" "fmul")
2726 (set_attr "trap" "yes")
2727 (set_attr "round_suffix" "normal")
2728 (set_attr "trap_suffix" "u_su_sui")])
2730 (define_insn "*muldf_ext1"
2731 [(set (match_operand:DF 0 "register_operand" "=f")
2732 (mult:DF (float_extend:DF
2733 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2734 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2735 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2736 "mul%-%/ %R1,%R2,%0"
2737 [(set_attr "type" "fmul")
2738 (set_attr "trap" "yes")
2739 (set_attr "round_suffix" "normal")
2740 (set_attr "trap_suffix" "u_su_sui")])
2742 (define_insn "*muldf_ext2"
2743 [(set (match_operand:DF 0 "register_operand" "=f")
2744 (mult:DF (float_extend:DF
2745 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2747 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2748 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2749 "mul%-%/ %R1,%R2,%0"
2750 [(set_attr "type" "fmul")
2751 (set_attr "trap" "yes")
2752 (set_attr "round_suffix" "normal")
2753 (set_attr "trap_suffix" "u_su_sui")])
2755 (define_expand "multf3"
2756 [(use (match_operand 0 "register_operand" ""))
2757 (use (match_operand 1 "general_operand" ""))
2758 (use (match_operand 2 "general_operand" ""))]
2759 "TARGET_HAS_XFLOATING_LIBS"
2760 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2762 (define_insn "*subsf3_ieee"
2763 [(set (match_operand:SF 0 "register_operand" "=&f")
2764 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2765 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2766 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2767 "sub%,%/ %R1,%R2,%0"
2768 [(set_attr "type" "fadd")
2769 (set_attr "trap" "yes")
2770 (set_attr "round_suffix" "normal")
2771 (set_attr "trap_suffix" "u_su_sui")])
2773 (define_insn "subsf3"
2774 [(set (match_operand:SF 0 "register_operand" "=f")
2775 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2776 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2778 "sub%,%/ %R1,%R2,%0"
2779 [(set_attr "type" "fadd")
2780 (set_attr "trap" "yes")
2781 (set_attr "round_suffix" "normal")
2782 (set_attr "trap_suffix" "u_su_sui")])
2784 (define_insn "*subdf3_ieee"
2785 [(set (match_operand:DF 0 "register_operand" "=&f")
2786 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2787 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2788 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2789 "sub%-%/ %R1,%R2,%0"
2790 [(set_attr "type" "fadd")
2791 (set_attr "trap" "yes")
2792 (set_attr "round_suffix" "normal")
2793 (set_attr "trap_suffix" "u_su_sui")])
2795 (define_insn "subdf3"
2796 [(set (match_operand:DF 0 "register_operand" "=f")
2797 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2798 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2800 "sub%-%/ %R1,%R2,%0"
2801 [(set_attr "type" "fadd")
2802 (set_attr "trap" "yes")
2803 (set_attr "round_suffix" "normal")
2804 (set_attr "trap_suffix" "u_su_sui")])
2806 (define_insn "*subdf_ext1"
2807 [(set (match_operand:DF 0 "register_operand" "=f")
2808 (minus:DF (float_extend:DF
2809 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2810 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2811 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2812 "sub%-%/ %R1,%R2,%0"
2813 [(set_attr "type" "fadd")
2814 (set_attr "trap" "yes")
2815 (set_attr "round_suffix" "normal")
2816 (set_attr "trap_suffix" "u_su_sui")])
2818 (define_insn "*subdf_ext2"
2819 [(set (match_operand:DF 0 "register_operand" "=f")
2820 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2822 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2823 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2824 "sub%-%/ %R1,%R2,%0"
2825 [(set_attr "type" "fadd")
2826 (set_attr "trap" "yes")
2827 (set_attr "round_suffix" "normal")
2828 (set_attr "trap_suffix" "u_su_sui")])
2830 (define_insn "*subdf_ext3"
2831 [(set (match_operand:DF 0 "register_operand" "=f")
2832 (minus:DF (float_extend:DF
2833 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2835 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2836 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2837 "sub%-%/ %R1,%R2,%0"
2838 [(set_attr "type" "fadd")
2839 (set_attr "trap" "yes")
2840 (set_attr "round_suffix" "normal")
2841 (set_attr "trap_suffix" "u_su_sui")])
2843 (define_expand "subtf3"
2844 [(use (match_operand 0 "register_operand" ""))
2845 (use (match_operand 1 "general_operand" ""))
2846 (use (match_operand 2 "general_operand" ""))]
2847 "TARGET_HAS_XFLOATING_LIBS"
2848 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2850 (define_insn "*sqrtsf2_ieee"
2851 [(set (match_operand:SF 0 "register_operand" "=&f")
2852 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2853 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2855 [(set_attr "type" "fsqrt")
2856 (set_attr "opsize" "si")
2857 (set_attr "trap" "yes")
2858 (set_attr "round_suffix" "normal")
2859 (set_attr "trap_suffix" "u_su_sui")])
2861 (define_insn "sqrtsf2"
2862 [(set (match_operand:SF 0 "register_operand" "=f")
2863 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2864 "TARGET_FP && TARGET_FIX"
2866 [(set_attr "type" "fsqrt")
2867 (set_attr "opsize" "si")
2868 (set_attr "trap" "yes")
2869 (set_attr "round_suffix" "normal")
2870 (set_attr "trap_suffix" "u_su_sui")])
2872 (define_insn "*sqrtdf2_ieee"
2873 [(set (match_operand:DF 0 "register_operand" "=&f")
2874 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2875 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2877 [(set_attr "type" "fsqrt")
2878 (set_attr "trap" "yes")
2879 (set_attr "round_suffix" "normal")
2880 (set_attr "trap_suffix" "u_su_sui")])
2882 (define_insn "sqrtdf2"
2883 [(set (match_operand:DF 0 "register_operand" "=f")
2884 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2885 "TARGET_FP && TARGET_FIX"
2887 [(set_attr "type" "fsqrt")
2888 (set_attr "trap" "yes")
2889 (set_attr "round_suffix" "normal")
2890 (set_attr "trap_suffix" "u_su_sui")])
2892 ;; Next are all the integer comparisons, and conditional moves and branches
2893 ;; and some of the related define_expand's and define_split's.
2895 (define_insn "*setcc_internal"
2896 [(set (match_operand 0 "register_operand" "=r")
2897 (match_operator 1 "alpha_comparison_operator"
2898 [(match_operand:DI 2 "register_operand" "r")
2899 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2900 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2901 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2902 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2904 [(set_attr "type" "icmp")])
2906 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2907 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2909 (define_insn "*setcc_swapped_internal"
2910 [(set (match_operand 0 "register_operand" "=r")
2911 (match_operator 1 "alpha_swapped_comparison_operator"
2912 [(match_operand:DI 2 "register_operand" "r")
2913 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2914 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2915 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2916 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2918 [(set_attr "type" "icmp")])
2920 ;; Use match_operator rather than ne directly so that we can match
2921 ;; multiple integer modes.
2922 (define_insn "*setne_internal"
2923 [(set (match_operand 0 "register_operand" "=r")
2924 (match_operator 1 "signed_comparison_operator"
2925 [(match_operand:DI 2 "register_operand" "r")
2927 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2928 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2929 && GET_CODE (operands[1]) == NE
2930 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2932 [(set_attr "type" "icmp")])
2934 ;; The mode folding trick can't be used with const_int operands, since
2935 ;; reload needs to know the proper mode.
2937 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2938 ;; in order to create more pairs of constants. As long as we're allowing
2939 ;; two constants at the same time, and will have to reload one of them...
2941 (define_insn "*movqicc_internal"
2942 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2944 (match_operator 2 "signed_comparison_operator"
2945 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2946 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2947 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2948 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2949 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2955 [(set_attr "type" "icmov")])
2957 (define_insn "*movhicc_internal"
2958 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2960 (match_operator 2 "signed_comparison_operator"
2961 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2962 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2963 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2964 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2965 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2971 [(set_attr "type" "icmov")])
2973 (define_insn "*movsicc_internal"
2974 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2976 (match_operator 2 "signed_comparison_operator"
2977 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2978 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2979 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2980 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2981 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2987 [(set_attr "type" "icmov")])
2989 (define_insn "*movdicc_internal"
2990 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2992 (match_operator 2 "signed_comparison_operator"
2993 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2994 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2995 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2996 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2997 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3003 [(set_attr "type" "icmov")])
3005 (define_insn "*movqicc_lbc"
3006 [(set (match_operand:QI 0 "register_operand" "=r,r")
3008 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3012 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3013 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3018 [(set_attr "type" "icmov")])
3020 (define_insn "*movhicc_lbc"
3021 [(set (match_operand:HI 0 "register_operand" "=r,r")
3023 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3027 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3028 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3033 [(set_attr "type" "icmov")])
3035 (define_insn "*movsicc_lbc"
3036 [(set (match_operand:SI 0 "register_operand" "=r,r")
3038 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3042 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3043 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3048 [(set_attr "type" "icmov")])
3050 (define_insn "*movdicc_lbc"
3051 [(set (match_operand:DI 0 "register_operand" "=r,r")
3053 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3057 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3058 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3063 [(set_attr "type" "icmov")])
3065 (define_insn "*movqicc_lbs"
3066 [(set (match_operand:QI 0 "register_operand" "=r,r")
3068 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3072 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3073 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3078 [(set_attr "type" "icmov")])
3080 (define_insn "*movhicc_lbs"
3081 [(set (match_operand:HI 0 "register_operand" "=r,r")
3083 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3087 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3088 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3093 [(set_attr "type" "icmov")])
3095 (define_insn "*movsicc_lbs"
3096 [(set (match_operand:SI 0 "register_operand" "=r,r")
3098 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3102 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3103 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3108 [(set_attr "type" "icmov")])
3110 (define_insn "*movdicc_lbs"
3111 [(set (match_operand:DI 0 "register_operand" "=r,r")
3113 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3117 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3118 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3123 [(set_attr "type" "icmov")])
3125 ;; For ABS, we have two choices, depending on whether the input and output
3126 ;; registers are the same or not.
3127 (define_expand "absdi2"
3128 [(set (match_operand:DI 0 "register_operand" "")
3129 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3132 if (rtx_equal_p (operands[0], operands[1]))
3133 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3135 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3139 (define_expand "absdi2_same"
3140 [(set (match_operand:DI 1 "register_operand" "")
3141 (neg:DI (match_operand:DI 0 "register_operand" "")))
3143 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3149 (define_expand "absdi2_diff"
3150 [(set (match_operand:DI 0 "register_operand" "")
3151 (neg:DI (match_operand:DI 1 "register_operand" "")))
3153 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3160 [(set (match_operand:DI 0 "register_operand" "")
3161 (abs:DI (match_dup 0)))
3162 (clobber (match_operand:DI 1 "register_operand" ""))]
3164 [(set (match_dup 1) (neg:DI (match_dup 0)))
3165 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3166 (match_dup 0) (match_dup 1)))]
3170 [(set (match_operand:DI 0 "register_operand" "")
3171 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3172 "! rtx_equal_p (operands[0], operands[1])"
3173 [(set (match_dup 0) (neg:DI (match_dup 1)))
3174 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3175 (match_dup 0) (match_dup 1)))]
3179 [(set (match_operand:DI 0 "register_operand" "")
3180 (neg:DI (abs:DI (match_dup 0))))
3181 (clobber (match_operand:DI 1 "register_operand" ""))]
3183 [(set (match_dup 1) (neg:DI (match_dup 0)))
3184 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3185 (match_dup 0) (match_dup 1)))]
3189 [(set (match_operand:DI 0 "register_operand" "")
3190 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3191 "! rtx_equal_p (operands[0], operands[1])"
3192 [(set (match_dup 0) (neg:DI (match_dup 1)))
3193 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3194 (match_dup 0) (match_dup 1)))]
3197 (define_insn "sminqi3"
3198 [(set (match_operand:QI 0 "register_operand" "=r")
3199 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3200 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3203 [(set_attr "type" "mvi")])
3205 (define_insn "uminqi3"
3206 [(set (match_operand:QI 0 "register_operand" "=r")
3207 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3208 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3211 [(set_attr "type" "mvi")])
3213 (define_insn "smaxqi3"
3214 [(set (match_operand:QI 0 "register_operand" "=r")
3215 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3216 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3219 [(set_attr "type" "mvi")])
3221 (define_insn "umaxqi3"
3222 [(set (match_operand:QI 0 "register_operand" "=r")
3223 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3224 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3227 [(set_attr "type" "mvi")])
3229 (define_insn "sminhi3"
3230 [(set (match_operand:HI 0 "register_operand" "=r")
3231 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3232 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3235 [(set_attr "type" "mvi")])
3237 (define_insn "uminhi3"
3238 [(set (match_operand:HI 0 "register_operand" "=r")
3239 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3240 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3243 [(set_attr "type" "mvi")])
3245 (define_insn "smaxhi3"
3246 [(set (match_operand:HI 0 "register_operand" "=r")
3247 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3248 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3251 [(set_attr "type" "mvi")])
3253 (define_insn "umaxhi3"
3254 [(set (match_operand:HI 0 "register_operand" "=r")
3255 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3256 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3259 [(set_attr "type" "mvi")])
3261 (define_expand "smaxdi3"
3263 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3264 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3265 (set (match_operand:DI 0 "register_operand" "")
3266 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3267 (match_dup 1) (match_dup 2)))]
3269 { operands[3] = gen_reg_rtx (DImode); })
3272 [(set (match_operand:DI 0 "register_operand" "")
3273 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3274 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3275 (clobber (match_operand:DI 3 "register_operand" ""))]
3276 "operands[2] != const0_rtx"
3277 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3278 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3279 (match_dup 1) (match_dup 2)))]
3282 (define_insn "*smax_const0"
3283 [(set (match_operand:DI 0 "register_operand" "=r")
3284 (smax:DI (match_operand:DI 1 "register_operand" "0")
3288 [(set_attr "type" "icmov")])
3290 (define_expand "smindi3"
3292 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3293 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3294 (set (match_operand:DI 0 "register_operand" "")
3295 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3296 (match_dup 1) (match_dup 2)))]
3298 { operands[3] = gen_reg_rtx (DImode); })
3301 [(set (match_operand:DI 0 "register_operand" "")
3302 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3303 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3304 (clobber (match_operand:DI 3 "register_operand" ""))]
3305 "operands[2] != const0_rtx"
3306 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3307 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3308 (match_dup 1) (match_dup 2)))]
3311 (define_insn "*smin_const0"
3312 [(set (match_operand:DI 0 "register_operand" "=r")
3313 (smin:DI (match_operand:DI 1 "register_operand" "0")
3317 [(set_attr "type" "icmov")])
3319 (define_expand "umaxdi3"
3321 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3322 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3323 (set (match_operand:DI 0 "register_operand" "")
3324 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3325 (match_dup 1) (match_dup 2)))]
3327 "operands[3] = gen_reg_rtx (DImode);")
3330 [(set (match_operand:DI 0 "register_operand" "")
3331 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3332 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3333 (clobber (match_operand:DI 3 "register_operand" ""))]
3334 "operands[2] != const0_rtx"
3335 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3336 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3337 (match_dup 1) (match_dup 2)))]
3340 (define_expand "umindi3"
3342 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3343 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3344 (set (match_operand:DI 0 "register_operand" "")
3345 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3346 (match_dup 1) (match_dup 2)))]
3348 "operands[3] = gen_reg_rtx (DImode);")
3351 [(set (match_operand:DI 0 "register_operand" "")
3352 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3353 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3354 (clobber (match_operand:DI 3 "register_operand" ""))]
3355 "operands[2] != const0_rtx"
3356 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3357 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3358 (match_dup 1) (match_dup 2)))]
3361 (define_insn "*bcc_normal"
3364 (match_operator 1 "signed_comparison_operator"
3365 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3367 (label_ref (match_operand 0 "" ""))
3371 [(set_attr "type" "ibr")])
3373 (define_insn "*bcc_reverse"
3376 (match_operator 1 "signed_comparison_operator"
3377 [(match_operand:DI 2 "register_operand" "r")
3381 (label_ref (match_operand 0 "" ""))))]
3384 [(set_attr "type" "ibr")])
3386 (define_insn "*blbs_normal"
3389 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3393 (label_ref (match_operand 0 "" ""))
3397 [(set_attr "type" "ibr")])
3399 (define_insn "*blbc_normal"
3402 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3406 (label_ref (match_operand 0 "" ""))
3410 [(set_attr "type" "ibr")])
3416 (match_operator 1 "comparison_operator"
3417 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3419 (match_operand:DI 3 "const_int_operand" ""))
3421 (label_ref (match_operand 0 "" ""))
3423 (clobber (match_operand:DI 4 "register_operand" ""))])]
3424 "INTVAL (operands[3]) != 0"
3426 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3428 (if_then_else (match_op_dup 1
3429 [(zero_extract:DI (match_dup 4)
3433 (label_ref (match_dup 0))
3437 ;; The following are the corresponding floating-point insns. Recall
3438 ;; we need to have variants that expand the arguments from SFmode
3441 (define_insn "*cmpdf_ieee"
3442 [(set (match_operand:DF 0 "register_operand" "=&f")
3443 (match_operator:DF 1 "alpha_fp_comparison_operator"
3444 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3445 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3446 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3447 "cmp%-%C1%/ %R2,%R3,%0"
3448 [(set_attr "type" "fadd")
3449 (set_attr "trap" "yes")
3450 (set_attr "trap_suffix" "su")])
3452 (define_insn "*cmpdf_internal"
3453 [(set (match_operand:DF 0 "register_operand" "=f")
3454 (match_operator:DF 1 "alpha_fp_comparison_operator"
3455 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3456 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3457 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3458 "cmp%-%C1%/ %R2,%R3,%0"
3459 [(set_attr "type" "fadd")
3460 (set_attr "trap" "yes")
3461 (set_attr "trap_suffix" "su")])
3463 (define_insn "*cmpdf_ieee_ext1"
3464 [(set (match_operand:DF 0 "register_operand" "=&f")
3465 (match_operator:DF 1 "alpha_fp_comparison_operator"
3467 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3468 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3469 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3470 "cmp%-%C1%/ %R2,%R3,%0"
3471 [(set_attr "type" "fadd")
3472 (set_attr "trap" "yes")
3473 (set_attr "trap_suffix" "su")])
3475 (define_insn "*cmpdf_ext1"
3476 [(set (match_operand:DF 0 "register_operand" "=f")
3477 (match_operator:DF 1 "alpha_fp_comparison_operator"
3479 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3480 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3481 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3482 "cmp%-%C1%/ %R2,%R3,%0"
3483 [(set_attr "type" "fadd")
3484 (set_attr "trap" "yes")
3485 (set_attr "trap_suffix" "su")])
3487 (define_insn "*cmpdf_ieee_ext2"
3488 [(set (match_operand:DF 0 "register_operand" "=&f")
3489 (match_operator:DF 1 "alpha_fp_comparison_operator"
3490 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3492 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3493 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3494 "cmp%-%C1%/ %R2,%R3,%0"
3495 [(set_attr "type" "fadd")
3496 (set_attr "trap" "yes")
3497 (set_attr "trap_suffix" "su")])
3499 (define_insn "*cmpdf_ext2"
3500 [(set (match_operand:DF 0 "register_operand" "=f")
3501 (match_operator:DF 1 "alpha_fp_comparison_operator"
3502 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3504 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3505 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3506 "cmp%-%C1%/ %R2,%R3,%0"
3507 [(set_attr "type" "fadd")
3508 (set_attr "trap" "yes")
3509 (set_attr "trap_suffix" "su")])
3511 (define_insn "*cmpdf_ieee_ext3"
3512 [(set (match_operand:DF 0 "register_operand" "=&f")
3513 (match_operator:DF 1 "alpha_fp_comparison_operator"
3515 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3517 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3518 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3519 "cmp%-%C1%/ %R2,%R3,%0"
3520 [(set_attr "type" "fadd")
3521 (set_attr "trap" "yes")
3522 (set_attr "trap_suffix" "su")])
3524 (define_insn "*cmpdf_ext3"
3525 [(set (match_operand:DF 0 "register_operand" "=f")
3526 (match_operator:DF 1 "alpha_fp_comparison_operator"
3528 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3530 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3531 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3532 "cmp%-%C1%/ %R2,%R3,%0"
3533 [(set_attr "type" "fadd")
3534 (set_attr "trap" "yes")
3535 (set_attr "trap_suffix" "su")])
3537 (define_insn "*movdfcc_internal"
3538 [(set (match_operand:DF 0 "register_operand" "=f,f")
3540 (match_operator 3 "signed_comparison_operator"
3541 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3542 (match_operand:DF 2 "const0_operand" "G,G")])
3543 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3544 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3548 fcmov%D3 %R4,%R5,%0"
3549 [(set_attr "type" "fcmov")])
3551 (define_insn "*movsfcc_internal"
3552 [(set (match_operand:SF 0 "register_operand" "=f,f")
3554 (match_operator 3 "signed_comparison_operator"
3555 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3556 (match_operand:DF 2 "const0_operand" "G,G")])
3557 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3558 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3562 fcmov%D3 %R4,%R5,%0"
3563 [(set_attr "type" "fcmov")])
3565 (define_insn "*movdfcc_ext1"
3566 [(set (match_operand:DF 0 "register_operand" "=f,f")
3568 (match_operator 3 "signed_comparison_operator"
3569 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3570 (match_operand:DF 2 "const0_operand" "G,G")])
3571 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3572 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3576 fcmov%D3 %R4,%R5,%0"
3577 [(set_attr "type" "fcmov")])
3579 (define_insn "*movdfcc_ext2"
3580 [(set (match_operand:DF 0 "register_operand" "=f,f")
3582 (match_operator 3 "signed_comparison_operator"
3584 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3585 (match_operand:DF 2 "const0_operand" "G,G")])
3586 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3587 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3591 fcmov%D3 %R4,%R5,%0"
3592 [(set_attr "type" "fcmov")])
3594 (define_insn "*movdfcc_ext3"
3595 [(set (match_operand:SF 0 "register_operand" "=f,f")
3597 (match_operator 3 "signed_comparison_operator"
3599 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3600 (match_operand:DF 2 "const0_operand" "G,G")])
3601 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3602 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3606 fcmov%D3 %R4,%R5,%0"
3607 [(set_attr "type" "fcmov")])
3609 (define_insn "*movdfcc_ext4"
3610 [(set (match_operand:DF 0 "register_operand" "=f,f")
3612 (match_operator 3 "signed_comparison_operator"
3614 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3615 (match_operand:DF 2 "const0_operand" "G,G")])
3616 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3617 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3621 fcmov%D3 %R4,%R5,%0"
3622 [(set_attr "type" "fcmov")])
3624 (define_expand "maxdf3"
3626 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3627 (match_operand:DF 2 "reg_or_0_operand" "")))
3628 (set (match_operand:DF 0 "register_operand" "")
3629 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3630 (match_dup 1) (match_dup 2)))]
3633 operands[3] = gen_reg_rtx (DFmode);
3634 operands[4] = CONST0_RTX (DFmode);
3637 (define_expand "mindf3"
3639 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3640 (match_operand:DF 2 "reg_or_0_operand" "")))
3641 (set (match_operand:DF 0 "register_operand" "")
3642 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3643 (match_dup 1) (match_dup 2)))]
3646 operands[3] = gen_reg_rtx (DFmode);
3647 operands[4] = CONST0_RTX (DFmode);
3650 (define_expand "maxsf3"
3652 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3653 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3654 (set (match_operand:SF 0 "register_operand" "")
3655 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3656 (match_dup 1) (match_dup 2)))]
3659 operands[3] = gen_reg_rtx (DFmode);
3660 operands[4] = CONST0_RTX (DFmode);
3663 (define_expand "minsf3"
3665 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3666 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3667 (set (match_operand:SF 0 "register_operand" "")
3668 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3669 (match_dup 1) (match_dup 2)))]
3672 operands[3] = gen_reg_rtx (DFmode);
3673 operands[4] = CONST0_RTX (DFmode);
3676 (define_insn "*fbcc_normal"
3679 (match_operator 1 "signed_comparison_operator"
3680 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3681 (match_operand:DF 3 "const0_operand" "G")])
3682 (label_ref (match_operand 0 "" ""))
3686 [(set_attr "type" "fbr")])
3688 (define_insn "*fbcc_ext_normal"
3691 (match_operator 1 "signed_comparison_operator"
3693 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3694 (match_operand:DF 3 "const0_operand" "G")])
3695 (label_ref (match_operand 0 "" ""))
3699 [(set_attr "type" "fbr")])
3701 ;; These are the main define_expand's used to make conditional branches
3704 (define_expand "cmpdf"
3705 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3706 (match_operand:DF 1 "reg_or_0_operand" "")))]
3709 alpha_compare.op0 = operands[0];
3710 alpha_compare.op1 = operands[1];
3711 alpha_compare.fp_p = 1;
3715 (define_expand "cmptf"
3716 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3717 (match_operand:TF 1 "general_operand" "")))]
3718 "TARGET_HAS_XFLOATING_LIBS"
3720 alpha_compare.op0 = operands[0];
3721 alpha_compare.op1 = operands[1];
3722 alpha_compare.fp_p = 1;
3726 (define_expand "cmpdi"
3727 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3728 (match_operand:DI 1 "general_operand" "")))]
3731 alpha_compare.op0 = operands[0];
3732 alpha_compare.op1 = operands[1];
3733 alpha_compare.fp_p = 0;
3737 (define_expand "beq"
3739 (if_then_else (match_dup 1)
3740 (label_ref (match_operand 0 "" ""))
3743 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3745 (define_expand "bne"
3747 (if_then_else (match_dup 1)
3748 (label_ref (match_operand 0 "" ""))
3751 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3753 (define_expand "blt"
3755 (if_then_else (match_dup 1)
3756 (label_ref (match_operand 0 "" ""))
3759 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3761 (define_expand "ble"
3763 (if_then_else (match_dup 1)
3764 (label_ref (match_operand 0 "" ""))
3767 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3769 (define_expand "bgt"
3771 (if_then_else (match_dup 1)
3772 (label_ref (match_operand 0 "" ""))
3775 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3777 (define_expand "bge"
3779 (if_then_else (match_dup 1)
3780 (label_ref (match_operand 0 "" ""))
3783 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3785 (define_expand "bltu"
3787 (if_then_else (match_dup 1)
3788 (label_ref (match_operand 0 "" ""))
3791 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3793 (define_expand "bleu"
3795 (if_then_else (match_dup 1)
3796 (label_ref (match_operand 0 "" ""))
3799 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3801 (define_expand "bgtu"
3803 (if_then_else (match_dup 1)
3804 (label_ref (match_operand 0 "" ""))
3807 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3809 (define_expand "bgeu"
3811 (if_then_else (match_dup 1)
3812 (label_ref (match_operand 0 "" ""))
3815 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3817 (define_expand "bunordered"
3819 (if_then_else (match_dup 1)
3820 (label_ref (match_operand 0 "" ""))
3823 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3825 (define_expand "bordered"
3827 (if_then_else (match_dup 1)
3828 (label_ref (match_operand 0 "" ""))
3831 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3833 (define_expand "seq"
3834 [(set (match_operand:DI 0 "register_operand" "")
3837 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3839 (define_expand "sne"
3840 [(set (match_operand:DI 0 "register_operand" "")
3843 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3845 (define_expand "slt"
3846 [(set (match_operand:DI 0 "register_operand" "")
3849 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3851 (define_expand "sle"
3852 [(set (match_operand:DI 0 "register_operand" "")
3855 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3857 (define_expand "sgt"
3858 [(set (match_operand:DI 0 "register_operand" "")
3861 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3863 (define_expand "sge"
3864 [(set (match_operand:DI 0 "register_operand" "")
3867 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3869 (define_expand "sltu"
3870 [(set (match_operand:DI 0 "register_operand" "")
3873 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3875 (define_expand "sleu"
3876 [(set (match_operand:DI 0 "register_operand" "")
3879 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3881 (define_expand "sgtu"
3882 [(set (match_operand:DI 0 "register_operand" "")
3885 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3887 (define_expand "sgeu"
3888 [(set (match_operand:DI 0 "register_operand" "")
3891 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3893 (define_expand "sunordered"
3894 [(set (match_operand:DI 0 "register_operand" "")
3897 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3899 (define_expand "sordered"
3900 [(set (match_operand:DI 0 "register_operand" "")
3903 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3905 ;; These are the main define_expand's used to make conditional moves.
3907 (define_expand "movsicc"
3908 [(set (match_operand:SI 0 "register_operand" "")
3909 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3910 (match_operand:SI 2 "reg_or_8bit_operand" "")
3911 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3914 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3918 (define_expand "movdicc"
3919 [(set (match_operand:DI 0 "register_operand" "")
3920 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3921 (match_operand:DI 2 "reg_or_8bit_operand" "")
3922 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3925 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3929 (define_expand "movsfcc"
3930 [(set (match_operand:SF 0 "register_operand" "")
3931 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3932 (match_operand:SF 2 "reg_or_8bit_operand" "")
3933 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3936 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3940 (define_expand "movdfcc"
3941 [(set (match_operand:DF 0 "register_operand" "")
3942 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3943 (match_operand:DF 2 "reg_or_8bit_operand" "")
3944 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3947 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3951 ;; These define_split definitions are used in cases when comparisons have
3952 ;; not be stated in the correct way and we need to reverse the second
3953 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3954 ;; comparison that tests the result being reversed. We have one define_split
3955 ;; for each use of a comparison. They do not match valid insns and need
3956 ;; not generate valid insns.
3958 ;; We can also handle equality comparisons (and inequality comparisons in
3959 ;; cases where the resulting add cannot overflow) by doing an add followed by
3960 ;; a comparison with zero. This is faster since the addition takes one
3961 ;; less cycle than a compare when feeding into a conditional move.
3962 ;; For this case, we also have an SImode pattern since we can merge the add
3963 ;; and sign extend and the order doesn't matter.
3965 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3966 ;; operation could have been generated.
3969 [(set (match_operand:DI 0 "register_operand" "")
3971 (match_operator 1 "comparison_operator"
3972 [(match_operand:DI 2 "reg_or_0_operand" "")
3973 (match_operand:DI 3 "reg_or_cint_operand" "")])
3974 (match_operand:DI 4 "reg_or_cint_operand" "")
3975 (match_operand:DI 5 "reg_or_cint_operand" "")))
3976 (clobber (match_operand:DI 6 "register_operand" ""))]
3977 "operands[3] != const0_rtx"
3978 [(set (match_dup 6) (match_dup 7))
3980 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3982 enum rtx_code code = GET_CODE (operands[1]);
3983 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3985 /* If we are comparing for equality with a constant and that constant
3986 appears in the arm when the register equals the constant, use the
3987 register since that is more likely to match (and to produce better code
3990 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3991 && rtx_equal_p (operands[4], operands[3]))
3992 operands[4] = operands[2];
3994 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3995 && rtx_equal_p (operands[5], operands[3]))
3996 operands[5] = operands[2];
3998 if (code == NE || code == EQ
3999 || (extended_count (operands[2], DImode, unsignedp) >= 1
4000 && extended_count (operands[3], DImode, unsignedp) >= 1))
4002 if (GET_CODE (operands[3]) == CONST_INT)
4003 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4004 GEN_INT (- INTVAL (operands[3])));
4006 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4008 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4011 else if (code == EQ || code == LE || code == LT
4012 || code == LEU || code == LTU)
4014 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4015 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4019 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4020 operands[2], operands[3]);
4021 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4026 [(set (match_operand:DI 0 "register_operand" "")
4028 (match_operator 1 "comparison_operator"
4029 [(match_operand:SI 2 "reg_or_0_operand" "")
4030 (match_operand:SI 3 "reg_or_cint_operand" "")])
4031 (match_operand:DI 4 "reg_or_8bit_operand" "")
4032 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4033 (clobber (match_operand:DI 6 "register_operand" ""))]
4034 "operands[3] != const0_rtx
4035 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4036 [(set (match_dup 6) (match_dup 7))
4038 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4040 enum rtx_code code = GET_CODE (operands[1]);
4041 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4044 if ((code != NE && code != EQ
4045 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4046 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4049 if (GET_CODE (operands[3]) == CONST_INT)
4050 tem = gen_rtx_PLUS (SImode, operands[2],
4051 GEN_INT (- INTVAL (operands[3])));
4053 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4055 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4056 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4057 operands[6], const0_rtx);
4063 (match_operator 1 "comparison_operator"
4064 [(match_operand:DI 2 "reg_or_0_operand" "")
4065 (match_operand:DI 3 "reg_or_cint_operand" "")])
4066 (label_ref (match_operand 0 "" ""))
4068 (clobber (match_operand:DI 4 "register_operand" ""))]
4069 "operands[3] != const0_rtx"
4070 [(set (match_dup 4) (match_dup 5))
4071 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4073 enum rtx_code code = GET_CODE (operands[1]);
4074 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4076 if (code == NE || code == EQ
4077 || (extended_count (operands[2], DImode, unsignedp) >= 1
4078 && extended_count (operands[3], DImode, unsignedp) >= 1))
4080 if (GET_CODE (operands[3]) == CONST_INT)
4081 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4082 GEN_INT (- INTVAL (operands[3])));
4084 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4086 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4089 else if (code == EQ || code == LE || code == LT
4090 || code == LEU || code == LTU)
4092 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4093 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4097 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4098 operands[2], operands[3]);
4099 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4106 (match_operator 1 "comparison_operator"
4107 [(match_operand:SI 2 "reg_or_0_operand" "")
4108 (match_operand:SI 3 "const_int_operand" "")])
4109 (label_ref (match_operand 0 "" ""))
4111 (clobber (match_operand:DI 4 "register_operand" ""))]
4112 "operands[3] != const0_rtx
4113 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4114 [(set (match_dup 4) (match_dup 5))
4115 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4119 if (GET_CODE (operands[3]) == CONST_INT)
4120 tem = gen_rtx_PLUS (SImode, operands[2],
4121 GEN_INT (- INTVAL (operands[3])));
4123 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4125 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4126 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4127 operands[4], const0_rtx);
4130 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4131 ;; This eliminates one, and sometimes two, insns when the AND can be done
4134 [(set (match_operand:DI 0 "register_operand" "")
4135 (match_operator:DI 1 "comparison_operator"
4136 [(match_operand:DI 2 "register_operand" "")
4137 (match_operand:DI 3 "const_int_operand" "")]))
4138 (clobber (match_operand:DI 4 "register_operand" ""))]
4139 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4140 && (GET_CODE (operands[1]) == GTU
4141 || GET_CODE (operands[1]) == LEU
4142 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4143 && extended_count (operands[2], DImode, 1) > 0))"
4144 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4145 (set (match_dup 0) (match_dup 6))]
4147 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4148 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4149 || GET_CODE (operands[1]) == GT)
4151 DImode, operands[4], const0_rtx);
4154 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4157 [(set (match_operand 0 "register_operand" "")
4158 (if_then_else (match_operator 1 "signed_comparison_operator"
4159 [(match_operand:DI 2 "reg_or_0_operand" "")
4161 (match_operand 3 "const_int_operand" "")
4162 (match_operand 4 "const_int_operand" "")))]
4166 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4167 operands[2], operands[3], operands[4]))
4173 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4174 ;; Oh well, we match it in movcc, so it must be partially our fault.
4176 [(set (match_operand 0 "register_operand" "")
4177 (if_then_else (match_operator 1 "signed_comparison_operator"
4179 (match_operand:DI 2 "reg_or_0_operand" "")])
4180 (match_operand 3 "const_int_operand" "")
4181 (match_operand 4 "const_int_operand" "")))]
4185 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4186 operands[0], operands[2], operands[3],
4193 (define_insn_and_split "*cmp_sadd_di"
4194 [(set (match_operand:DI 0 "register_operand" "=r")
4195 (plus:DI (if_then_else:DI
4196 (match_operator 1 "alpha_zero_comparison_operator"
4197 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4199 (match_operand:DI 3 "const48_operand" "I")
4201 (match_operand:DI 4 "sext_add_operand" "rIO")))
4202 (clobber (match_scratch:DI 5 "=r"))]
4205 "! no_new_pseudos || reload_completed"
4207 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4209 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4212 if (! no_new_pseudos)
4213 operands[5] = gen_reg_rtx (DImode);
4214 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4215 operands[5] = operands[0];
4218 (define_insn_and_split "*cmp_sadd_si"
4219 [(set (match_operand:SI 0 "register_operand" "=r")
4220 (plus:SI (if_then_else:SI
4221 (match_operator 1 "alpha_zero_comparison_operator"
4222 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4224 (match_operand:SI 3 "const48_operand" "I")
4226 (match_operand:SI 4 "sext_add_operand" "rIO")))
4227 (clobber (match_scratch:SI 5 "=r"))]
4230 "! no_new_pseudos || reload_completed"
4232 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4234 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4237 if (! no_new_pseudos)
4238 operands[5] = gen_reg_rtx (DImode);
4239 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4240 operands[5] = operands[0];
4243 (define_insn_and_split "*cmp_sadd_sidi"
4244 [(set (match_operand:DI 0 "register_operand" "=r")
4246 (plus:SI (if_then_else:SI
4247 (match_operator 1 "alpha_zero_comparison_operator"
4248 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4250 (match_operand:SI 3 "const48_operand" "I")
4252 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4253 (clobber (match_scratch:SI 5 "=r"))]
4256 "! no_new_pseudos || reload_completed"
4258 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4260 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4263 if (! no_new_pseudos)
4264 operands[5] = gen_reg_rtx (DImode);
4265 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4266 operands[5] = operands[0];
4269 (define_insn_and_split "*cmp_ssub_di"
4270 [(set (match_operand:DI 0 "register_operand" "=r")
4271 (minus:DI (if_then_else:DI
4272 (match_operator 1 "alpha_zero_comparison_operator"
4273 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4275 (match_operand:DI 3 "const48_operand" "I")
4277 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4278 (clobber (match_scratch:DI 5 "=r"))]
4281 "! no_new_pseudos || reload_completed"
4283 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4285 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4288 if (! no_new_pseudos)
4289 operands[5] = gen_reg_rtx (DImode);
4290 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4291 operands[5] = operands[0];
4294 (define_insn_and_split "*cmp_ssub_si"
4295 [(set (match_operand:SI 0 "register_operand" "=r")
4296 (minus:SI (if_then_else:SI
4297 (match_operator 1 "alpha_zero_comparison_operator"
4298 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4300 (match_operand:SI 3 "const48_operand" "I")
4302 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4303 (clobber (match_scratch:SI 5 "=r"))]
4306 "! no_new_pseudos || reload_completed"
4308 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4310 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4313 if (! no_new_pseudos)
4314 operands[5] = gen_reg_rtx (DImode);
4315 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4316 operands[5] = operands[0];
4319 (define_insn_and_split "*cmp_ssub_sidi"
4320 [(set (match_operand:DI 0 "register_operand" "=r")
4322 (minus:SI (if_then_else:SI
4323 (match_operator 1 "alpha_zero_comparison_operator"
4324 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4326 (match_operand:SI 3 "const48_operand" "I")
4328 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4329 (clobber (match_scratch:SI 5 "=r"))]
4332 "! no_new_pseudos || reload_completed"
4334 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4336 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4339 if (! no_new_pseudos)
4340 operands[5] = gen_reg_rtx (DImode);
4341 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4342 operands[5] = operands[0];
4345 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4346 ;; work differently, so we have different patterns for each.
4348 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4349 ;; call. The CIW contains information about arguments passed in registers
4350 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4351 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4352 ;; in the presence of inlining since the CIWs for calls performed by the
4353 ;; inlined function must be stored in the SSIB of the function it is inlined
4354 ;; into as well. We encode the CIW in an unspec and append it to the list
4355 ;; of the CIWs for the current function only when the instruction for loading
4356 ;; $25 is generated.
4358 (define_expand "call"
4359 [(use (match_operand:DI 0 "" ""))
4360 (use (match_operand 1 "" ""))
4361 (use (match_operand 2 "" ""))
4362 (use (match_operand 3 "" ""))]
4365 if (TARGET_ABI_WINDOWS_NT)
4366 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4367 else if (TARGET_ABI_OPEN_VMS)
4368 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4369 else if (TARGET_ABI_UNICOSMK)
4370 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4372 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4376 (define_expand "sibcall"
4377 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4378 (match_operand 1 "" ""))
4379 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4382 if (GET_CODE (operands[0]) != MEM)
4384 operands[0] = XEXP (operands[0], 0);
4387 (define_expand "call_osf"
4388 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4389 (match_operand 1 "" ""))
4391 (clobber (reg:DI 26))])]
4394 if (GET_CODE (operands[0]) != MEM)
4397 operands[0] = XEXP (operands[0], 0);
4398 if (! call_operand (operands[0], Pmode))
4399 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4402 (define_expand "call_nt"
4403 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4404 (match_operand 1 "" ""))
4405 (clobber (reg:DI 26))])]
4408 if (GET_CODE (operands[0]) != MEM)
4411 operands[0] = XEXP (operands[0], 0);
4412 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4413 operands[0] = force_reg (DImode, operands[0]);
4416 ;; Calls on Unicos/Mk are always indirect.
4417 ;; op 0: symbol ref for called function
4418 ;; op 1: CIW for $25 represented by an unspec
4420 (define_expand "call_umk"
4421 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4422 (match_operand 1 "" ""))
4424 (clobber (reg:DI 26))])]
4427 if (GET_CODE (operands[0]) != MEM)
4430 /* Always load the address of the called function into a register;
4431 load the CIW in $25. */
4433 operands[0] = XEXP (operands[0], 0);
4434 if (GET_CODE (operands[0]) != REG)
4435 operands[0] = force_reg (DImode, operands[0]);
4437 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4441 ;; call openvms/alpha
4442 ;; op 0: symbol ref for called function
4443 ;; op 1: next_arg_reg (argument information value for R25)
4445 (define_expand "call_vms"
4446 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4447 (match_operand 1 "" ""))
4451 (clobber (reg:DI 27))])]
4454 if (GET_CODE (operands[0]) != MEM)
4457 operands[0] = XEXP (operands[0], 0);
4459 /* Always load AI with argument information, then handle symbolic and
4460 indirect call differently. Load RA and set operands[2] to PV in
4463 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4464 if (GET_CODE (operands[0]) == SYMBOL_REF)
4466 alpha_need_linkage (XSTR (operands[0], 0), 0);
4468 operands[2] = const0_rtx;
4472 emit_move_insn (gen_rtx_REG (Pmode, 26),
4473 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4474 operands[2] = operands[0];
4479 (define_expand "call_value"
4480 [(use (match_operand 0 "" ""))
4481 (use (match_operand:DI 1 "" ""))
4482 (use (match_operand 2 "" ""))
4483 (use (match_operand 3 "" ""))
4484 (use (match_operand 4 "" ""))]
4487 if (TARGET_ABI_WINDOWS_NT)
4488 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4489 else if (TARGET_ABI_OPEN_VMS)
4490 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4492 else if (TARGET_ABI_UNICOSMK)
4493 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4496 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4501 (define_expand "sibcall_value"
4502 [(parallel [(set (match_operand 0 "" "")
4503 (call (mem:DI (match_operand 1 "" ""))
4504 (match_operand 2 "" "")))
4505 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4508 if (GET_CODE (operands[1]) != MEM)
4510 operands[1] = XEXP (operands[1], 0);
4513 (define_expand "call_value_osf"
4514 [(parallel [(set (match_operand 0 "" "")
4515 (call (mem:DI (match_operand 1 "" ""))
4516 (match_operand 2 "" "")))
4518 (clobber (reg:DI 26))])]
4521 if (GET_CODE (operands[1]) != MEM)
4524 operands[1] = XEXP (operands[1], 0);
4525 if (! call_operand (operands[1], Pmode))
4526 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4529 (define_expand "call_value_nt"
4530 [(parallel [(set (match_operand 0 "" "")
4531 (call (mem:DI (match_operand 1 "" ""))
4532 (match_operand 2 "" "")))
4533 (clobber (reg:DI 26))])]
4536 if (GET_CODE (operands[1]) != MEM)
4539 operands[1] = XEXP (operands[1], 0);
4540 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4541 operands[1] = force_reg (DImode, operands[1]);
4544 (define_expand "call_value_vms"
4545 [(parallel [(set (match_operand 0 "" "")
4546 (call (mem:DI (match_operand:DI 1 "" ""))
4547 (match_operand 2 "" "")))
4551 (clobber (reg:DI 27))])]
4554 if (GET_CODE (operands[1]) != MEM)
4557 operands[1] = XEXP (operands[1], 0);
4559 /* Always load AI with argument information, then handle symbolic and
4560 indirect call differently. Load RA and set operands[3] to PV in
4563 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4564 if (GET_CODE (operands[1]) == SYMBOL_REF)
4566 alpha_need_linkage (XSTR (operands[1], 0), 0);
4568 operands[3] = const0_rtx;
4572 emit_move_insn (gen_rtx_REG (Pmode, 26),
4573 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4574 operands[3] = operands[1];
4578 (define_expand "call_value_umk"
4579 [(parallel [(set (match_operand 0 "" "")
4580 (call (mem:DI (match_operand 1 "" ""))
4581 (match_operand 2 "" "")))
4583 (clobber (reg:DI 26))])]
4586 if (GET_CODE (operands[1]) != MEM)
4589 operands[1] = XEXP (operands[1], 0);
4590 if (GET_CODE (operands[1]) != REG)
4591 operands[1] = force_reg (DImode, operands[1]);
4593 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4596 (define_insn "*call_osf_1_er"
4597 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4598 (match_operand 1 "" ""))
4600 (clobber (reg:DI 26))]
4601 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4603 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4604 bsr $26,%0\t\t!samegp
4605 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4606 [(set_attr "type" "jsr")
4607 (set_attr "length" "12,*,16")])
4609 ;; We must use peep2 instead of a split because we need accurate life
4610 ;; information for $gp. Consider the case of { bar(); while (1); }.
4612 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4613 (match_operand 1 "" ""))
4615 (clobber (reg:DI 26))])]
4616 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4617 && ! samegp_function_operand (operands[0], Pmode)
4618 && peep2_regno_dead_p (1, 29)"
4619 [(parallel [(call (mem:DI (match_dup 2))
4621 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4622 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4624 (use (match_dup 3))])]
4626 if (CONSTANT_P (operands[0]))
4628 operands[2] = gen_rtx_REG (Pmode, 27);
4629 operands[3] = GEN_INT (alpha_next_sequence_number++);
4630 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4631 operands[0], operands[3]));
4635 operands[2] = operands[0];
4636 operands[0] = const0_rtx;
4637 operands[3] = const0_rtx;
4642 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4643 (match_operand 1 "" ""))
4645 (clobber (reg:DI 26))])]
4646 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4647 && ! samegp_function_operand (operands[0], Pmode)
4648 && ! peep2_regno_dead_p (1, 29)"
4649 [(parallel [(call (mem:DI (match_dup 2))
4651 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4652 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4654 (use (match_dup 4))])
4656 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4658 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4660 if (CONSTANT_P (operands[0]))
4662 operands[2] = gen_rtx_REG (Pmode, 27);
4663 operands[4] = GEN_INT (alpha_next_sequence_number++);
4664 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4665 operands[0], operands[4]));
4669 operands[2] = operands[0];
4670 operands[0] = const0_rtx;
4671 operands[4] = const0_rtx;
4673 operands[3] = GEN_INT (alpha_next_sequence_number++);
4676 ;; We add a blockage unspec_volatile to prevent insns from moving down
4677 ;; from above the call to in between the call and the ldah gpdisp.
4679 (define_insn "*call_osf_2_er"
4680 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4681 (match_operand 1 "" ""))
4682 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4683 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4684 (use (match_operand 2 "" ""))
4685 (use (match_operand 3 "const_int_operand" ""))]
4686 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4687 "jsr $26,(%0),%2%J3"
4688 [(set_attr "type" "jsr")])
4690 ;; We output a nop after noreturn calls at the very end of the function to
4691 ;; ensure that the return address always remains in the caller's code range,
4692 ;; as not doing so might confuse unwinding engines.
4694 ;; The potential change in insn length is not reflected in the length
4695 ;; attributes at this stage. Since the extra space is only actually added at
4696 ;; the very end of the compilation process (via final/print_operand), it
4697 ;; really seems harmless and not worth the trouble of some extra computation
4698 ;; cost and complexity.
4700 (define_insn "*call_osf_1_noreturn"
4701 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4702 (match_operand 1 "" ""))
4704 (clobber (reg:DI 26))]
4705 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4706 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4711 [(set_attr "type" "jsr")
4712 (set_attr "length" "*,*,8")])
4714 (define_insn "*call_osf_1"
4715 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4716 (match_operand 1 "" ""))
4718 (clobber (reg:DI 26))]
4719 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4721 jsr $26,($27),0\;ldgp $29,0($26)
4723 jsr $26,%0\;ldgp $29,0($26)"
4724 [(set_attr "type" "jsr")
4725 (set_attr "length" "12,*,16")])
4727 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4728 ;; doesn't do what we want.
4729 (define_insn "*sibcall_osf_1_er"
4730 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4731 (match_operand 1 "" ""))
4732 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4733 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4735 br $31,%0\t\t!samegp
4736 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4737 [(set_attr "type" "jsr")
4738 (set_attr "length" "*,8")])
4740 (define_insn "*sibcall_osf_1"
4741 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4742 (match_operand 1 "" ""))
4743 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4744 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4747 lda $27,%0\;jmp $31,($27),%0"
4748 [(set_attr "type" "jsr")
4749 (set_attr "length" "*,8")])
4751 (define_insn "*call_nt_1"
4752 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4753 (match_operand 1 "" ""))
4754 (clobber (reg:DI 26))]
4755 "TARGET_ABI_WINDOWS_NT"
4760 [(set_attr "type" "jsr")
4761 (set_attr "length" "*,*,12")])
4763 ; GAS relies on the order and position of instructions output below in order
4764 ; to generate relocs for VMS link to potentially optimize the call.
4765 ; Please do not molest.
4766 (define_insn "*call_vms_1"
4767 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4768 (match_operand 1 "" ""))
4769 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4772 (clobber (reg:DI 27))]
4773 "TARGET_ABI_OPEN_VMS"
4775 switch (which_alternative)
4778 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4780 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4781 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4782 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4787 [(set_attr "type" "jsr")
4788 (set_attr "length" "12,16")])
4790 (define_insn "*call_umk_1"
4791 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4792 (match_operand 1 "" ""))
4794 (clobber (reg:DI 26))]
4795 "TARGET_ABI_UNICOSMK"
4797 [(set_attr "type" "jsr")])
4799 ;; Call subroutine returning any type.
4801 (define_expand "untyped_call"
4802 [(parallel [(call (match_operand 0 "" "")
4804 (match_operand 1 "" "")
4805 (match_operand 2 "" "")])]
4810 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4812 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4814 rtx set = XVECEXP (operands[2], 0, i);
4815 emit_move_insn (SET_DEST (set), SET_SRC (set));
4818 /* The optimizer does not know that the call sets the function value
4819 registers we stored in the result block. We avoid problems by
4820 claiming that all hard registers are used and clobbered at this
4822 emit_insn (gen_blockage ());
4827 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4828 ;; all of memory. This blocks insns from being moved across this point.
4830 (define_insn "blockage"
4831 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4834 [(set_attr "length" "0")
4835 (set_attr "type" "none")])
4839 (label_ref (match_operand 0 "" "")))]
4842 [(set_attr "type" "ibr")])
4844 (define_expand "return"
4849 (define_insn "*return_internal"
4853 [(set_attr "type" "ibr")])
4855 (define_insn "indirect_jump"
4856 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4859 [(set_attr "type" "ibr")])
4861 (define_expand "tablejump"
4862 [(parallel [(set (pc)
4863 (match_operand 0 "register_operand" ""))
4864 (use (label_ref:DI (match_operand 1 "" "")))])]
4867 if (TARGET_ABI_WINDOWS_NT)
4869 rtx dest = gen_reg_rtx (DImode);
4870 emit_insn (gen_extendsidi2 (dest, operands[0]));
4873 else if (TARGET_ABI_OSF)
4875 rtx dest = gen_reg_rtx (DImode);
4876 emit_insn (gen_extendsidi2 (dest, operands[0]));
4877 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4882 (define_insn "*tablejump_osf_nt_internal"
4884 (match_operand:DI 0 "register_operand" "r"))
4885 (use (label_ref:DI (match_operand 1 "" "")))]
4886 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4887 && alpha_tablejump_addr_vec (insn)"
4889 operands[2] = alpha_tablejump_best_label (insn);
4890 return "jmp $31,(%0),%2";
4892 [(set_attr "type" "ibr")])
4894 (define_insn "*tablejump_internal"
4896 (match_operand:DI 0 "register_operand" "r"))
4897 (use (label_ref (match_operand 1 "" "")))]
4900 [(set_attr "type" "ibr")])
4902 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4903 ;; want to have to include pal.h in our .s file.
4905 ;; Technically the type for call_pal is jsr, but we use that for determining
4906 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4909 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4912 [(set_attr "type" "callpal")])
4914 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4915 ;; NT does not document anything at 0x81 -- presumably it would generate
4916 ;; the equivalent of SIGILL, but this isn't that important.
4917 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4919 [(trap_if (const_int 1) (const_int 0))]
4920 "!TARGET_ABI_WINDOWS_NT"
4922 [(set_attr "type" "callpal")])
4924 ;; For userland, we load the thread pointer from the TCB.
4925 ;; For the kernel, we load the per-cpu private value.
4927 (define_insn "load_tp"
4928 [(set (match_operand:DI 0 "register_operand" "=v")
4929 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4932 if (TARGET_TLS_KERNEL)
4933 return "call_pal 0x32";
4935 return "call_pal 0x9e";
4937 [(set_attr "type" "callpal")])
4939 ;; For completeness, and possibly a __builtin function, here's how to
4940 ;; set the thread pointer. Since we don't describe enough of this
4941 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4942 ;; not much point in creating an R16_REG register class.
4944 (define_expand "set_tp"
4945 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4946 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4950 (define_insn "*set_tp"
4951 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4954 if (TARGET_TLS_KERNEL)
4955 return "call_pal 0x31";
4957 return "call_pal 0x9f";
4959 [(set_attr "type" "callpal")])
4961 ;; Finally, we have the basic data motion insns. The byte and word insns
4962 ;; are done via define_expand. Start with the floating-point insns, since
4963 ;; they are simpler.
4965 (define_insn "*movsf_nofix"
4966 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4967 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4968 "TARGET_FPREGS && ! TARGET_FIX
4969 && (register_operand (operands[0], SFmode)
4970 || reg_or_0_operand (operands[1], SFmode))"
4978 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4980 (define_insn "*movsf_fix"
4981 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4982 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4983 "TARGET_FPREGS && TARGET_FIX
4984 && (register_operand (operands[0], SFmode)
4985 || reg_or_0_operand (operands[1], SFmode))"
4995 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4997 (define_insn "*movsf_nofp"
4998 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4999 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5001 && (register_operand (operands[0], SFmode)
5002 || reg_or_0_operand (operands[1], SFmode))"
5007 [(set_attr "type" "ilog,ild,ist")])
5009 (define_insn "*movdf_nofix"
5010 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5011 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5012 "TARGET_FPREGS && ! TARGET_FIX
5013 && (register_operand (operands[0], DFmode)
5014 || reg_or_0_operand (operands[1], DFmode))"
5022 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5024 (define_insn "*movdf_fix"
5025 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5026 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5027 "TARGET_FPREGS && TARGET_FIX
5028 && (register_operand (operands[0], DFmode)
5029 || reg_or_0_operand (operands[1], DFmode))"
5039 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5041 (define_insn "*movdf_nofp"
5042 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5043 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5045 && (register_operand (operands[0], DFmode)
5046 || reg_or_0_operand (operands[1], DFmode))"
5051 [(set_attr "type" "ilog,ild,ist")])
5053 ;; Subregs suck for register allocation. Pretend we can move TFmode
5054 ;; data between general registers until after reload.
5056 (define_insn_and_split "*movtf_internal"
5057 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5058 (match_operand:TF 1 "input_operand" "roG,rG"))]
5059 "register_operand (operands[0], TFmode)
5060 || reg_or_0_operand (operands[1], TFmode)"
5063 [(set (match_dup 0) (match_dup 2))
5064 (set (match_dup 1) (match_dup 3))]
5066 alpha_split_tfmode_pair (operands);
5067 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5070 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5071 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5075 (define_expand "movsf"
5076 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5077 (match_operand:SF 1 "general_operand" ""))]
5080 if (GET_CODE (operands[0]) == MEM
5081 && ! reg_or_0_operand (operands[1], SFmode))
5082 operands[1] = force_reg (SFmode, operands[1]);
5085 (define_expand "movdf"
5086 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5087 (match_operand:DF 1 "general_operand" ""))]
5090 if (GET_CODE (operands[0]) == MEM
5091 && ! reg_or_0_operand (operands[1], DFmode))
5092 operands[1] = force_reg (DFmode, operands[1]);
5095 (define_expand "movtf"
5096 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5097 (match_operand:TF 1 "general_operand" ""))]
5100 if (GET_CODE (operands[0]) == MEM
5101 && ! reg_or_0_operand (operands[1], TFmode))
5102 operands[1] = force_reg (TFmode, operands[1]);
5105 (define_insn "*movsi_nofix"
5106 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5107 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5108 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5109 && (register_operand (operands[0], SImode)
5110 || reg_or_0_operand (operands[1], SImode))"
5120 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5122 (define_insn "*movsi_fix"
5123 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5124 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5125 "TARGET_ABI_OSF && TARGET_FIX
5126 && (register_operand (operands[0], SImode)
5127 || reg_or_0_operand (operands[1], SImode))"
5139 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5141 (define_insn "*movsi_nt_vms_nofix"
5142 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5143 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5144 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5146 && (register_operand (operands[0], SImode)
5147 || reg_or_0_operand (operands[1], SImode))"
5158 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5160 (define_insn "*movsi_nt_vms_fix"
5161 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5162 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5163 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5165 && (register_operand (operands[0], SImode)
5166 || reg_or_0_operand (operands[1], SImode))"
5179 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5181 (define_insn "*movhi_nobwx"
5182 [(set (match_operand:HI 0 "register_operand" "=r,r")
5183 (match_operand:HI 1 "input_operand" "rJ,n"))]
5185 && (register_operand (operands[0], HImode)
5186 || register_operand (operands[1], HImode))"
5190 [(set_attr "type" "ilog,iadd")])
5192 (define_insn "*movhi_bwx"
5193 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5194 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5196 && (register_operand (operands[0], HImode)
5197 || reg_or_0_operand (operands[1], HImode))"
5203 [(set_attr "type" "ilog,iadd,ild,ist")])
5205 (define_insn "*movqi_nobwx"
5206 [(set (match_operand:QI 0 "register_operand" "=r,r")
5207 (match_operand:QI 1 "input_operand" "rJ,n"))]
5209 && (register_operand (operands[0], QImode)
5210 || register_operand (operands[1], QImode))"
5214 [(set_attr "type" "ilog,iadd")])
5216 (define_insn "*movqi_bwx"
5217 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5218 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5220 && (register_operand (operands[0], QImode)
5221 || reg_or_0_operand (operands[1], QImode))"
5227 [(set_attr "type" "ilog,iadd,ild,ist")])
5229 ;; We do two major things here: handle mem->mem and construct long
5232 (define_expand "movsi"
5233 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5234 (match_operand:SI 1 "general_operand" ""))]
5237 if (alpha_expand_mov (SImode, operands))
5241 ;; Split a load of a large constant into the appropriate two-insn
5245 [(set (match_operand:SI 0 "register_operand" "")
5246 (match_operand:SI 1 "const_int_operand" ""))]
5247 "! add_operand (operands[1], SImode)"
5248 [(set (match_dup 0) (match_dup 2))
5249 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5252 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5254 if (tem == operands[0])
5260 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5261 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5262 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5263 ;; notes and update LABEL_NUSES because this is not done automatically.
5264 ;; Labels may be incorrectly deleted if we don't do this.
5266 ;; Describing what the individual instructions do correctly is too complicated
5267 ;; so use UNSPECs for each of the three parts of an address.
5270 [(set (match_operand:DI 0 "register_operand" "")
5271 (match_operand:DI 1 "symbolic_operand" ""))]
5272 "TARGET_ABI_UNICOSMK && reload_completed"
5275 rtx insn1, insn2, insn3;
5277 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5278 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5279 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5280 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5281 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5283 if (GET_CODE (operands[1]) == LABEL_REF)
5287 label = XEXP (operands[1], 0);
5288 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5290 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5292 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5294 LABEL_NUSES (label) += 3;
5299 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5301 (define_insn "umk_laum"
5302 [(set (match_operand:DI 0 "register_operand" "=r")
5303 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5305 "TARGET_ABI_UNICOSMK"
5307 [(set_attr "type" "iadd")])
5309 (define_insn "umk_lalm"
5310 [(set (match_operand:DI 0 "register_operand" "=r")
5311 (plus:DI (match_operand:DI 1 "register_operand" "r")
5312 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5314 "TARGET_ABI_UNICOSMK"
5316 [(set_attr "type" "iadd")])
5318 (define_insn "umk_lal"
5319 [(set (match_operand:DI 0 "register_operand" "=r")
5320 (plus:DI (match_operand:DI 1 "register_operand" "r")
5321 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5323 "TARGET_ABI_UNICOSMK"
5325 [(set_attr "type" "iadd")])
5327 ;; Add a new call information word to the current function's list of CIWs
5328 ;; and load its index into $25. Doing it here ensures that the CIW will be
5329 ;; associated with the correct function even in the presence of inlining.
5331 (define_insn "*umk_load_ciw"
5333 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5334 "TARGET_ABI_UNICOSMK"
5336 operands[0] = unicosmk_add_call_info_word (operands[0]);
5337 return "lda $25,%0";
5339 [(set_attr "type" "iadd")])
5341 (define_insn "*movdi_er_low_l"
5342 [(set (match_operand:DI 0 "register_operand" "=r")
5343 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5344 (match_operand:DI 2 "local_symbolic_operand" "")))]
5345 "TARGET_EXPLICIT_RELOCS"
5347 if (true_regnum (operands[1]) == 29)
5348 return "lda %0,%2(%1)\t\t!gprel";
5350 return "lda %0,%2(%1)\t\t!gprellow";
5352 [(set_attr "usegp" "yes")])
5355 [(set (match_operand:DI 0 "register_operand" "")
5356 (match_operand:DI 1 "small_symbolic_operand" ""))]
5357 "TARGET_EXPLICIT_RELOCS && reload_completed"
5359 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5360 "operands[2] = pic_offset_table_rtx;")
5363 [(set (match_operand:DI 0 "register_operand" "")
5364 (match_operand:DI 1 "local_symbolic_operand" ""))]
5365 "TARGET_EXPLICIT_RELOCS && reload_completed"
5367 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5369 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5370 "operands[2] = pic_offset_table_rtx;")
5373 [(match_operand 0 "some_small_symbolic_operand" "")]
5374 "TARGET_EXPLICIT_RELOCS && reload_completed"
5376 "operands[0] = split_small_symbolic_operand (operands[0]);")
5378 ;; Accepts any symbolic, not just global, since function calls that
5379 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5380 (define_insn "movdi_er_high_g"
5381 [(set (match_operand:DI 0 "register_operand" "=r")
5382 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5383 (match_operand:DI 2 "symbolic_operand" "")
5384 (match_operand 3 "const_int_operand" "")]
5386 "TARGET_EXPLICIT_RELOCS"
5388 if (INTVAL (operands[3]) == 0)
5389 return "ldq %0,%2(%1)\t\t!literal";
5391 return "ldq %0,%2(%1)\t\t!literal!%3";
5393 [(set_attr "type" "ldsym")])
5396 [(set (match_operand:DI 0 "register_operand" "")
5397 (match_operand:DI 1 "global_symbolic_operand" ""))]
5398 "TARGET_EXPLICIT_RELOCS && reload_completed"
5400 (unspec:DI [(match_dup 2)
5402 (const_int 0)] UNSPEC_LITERAL))]
5403 "operands[2] = pic_offset_table_rtx;")
5405 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5406 ;; compiled at the end of compilation. In the meantime, someone can
5407 ;; re-encode-section-info on some symbol changing it e.g. from global
5408 ;; to local-not-small. If this happens, we'd have emitted a plain
5409 ;; load rather than a high+losum load and not recognize the insn.
5411 ;; So if rtl inlining is in effect, we delay the global/not-global
5412 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5414 (define_insn_and_split "movdi_er_maybe_g"
5415 [(set (match_operand:DI 0 "register_operand" "=r")
5416 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5418 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5421 [(set (match_dup 0) (match_dup 1))]
5423 if (local_symbolic_operand (operands[1], Pmode)
5424 && !small_symbolic_operand (operands[1], Pmode))
5426 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5429 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5430 if (reload_completed)
5431 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5432 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5434 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5435 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5440 (define_insn "movdi_er_tlsgd"
5441 [(set (match_operand:DI 0 "register_operand" "=r")
5442 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5443 (match_operand:DI 2 "symbolic_operand" "")
5444 (match_operand 3 "const_int_operand" "")]
5448 if (INTVAL (operands[3]) == 0)
5449 return "lda %0,%2(%1)\t\t!tlsgd";
5451 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5454 (define_insn "movdi_er_tlsldm"
5455 [(set (match_operand:DI 0 "register_operand" "=r")
5456 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5457 (match_operand 2 "const_int_operand" "")]
5461 if (INTVAL (operands[2]) == 0)
5462 return "lda %0,%&(%1)\t\t!tlsldm";
5464 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5467 (define_insn "*movdi_er_gotdtp"
5468 [(set (match_operand:DI 0 "register_operand" "=r")
5469 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5470 (match_operand:DI 2 "symbolic_operand" "")]
5473 "ldq %0,%2(%1)\t\t!gotdtprel"
5474 [(set_attr "type" "ild")
5475 (set_attr "usegp" "yes")])
5478 [(set (match_operand:DI 0 "register_operand" "")
5479 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5480 "HAVE_AS_TLS && reload_completed"
5482 (unspec:DI [(match_dup 2)
5483 (match_dup 1)] UNSPEC_DTPREL))]
5485 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5486 operands[2] = pic_offset_table_rtx;
5489 (define_insn "*movdi_er_gottp"
5490 [(set (match_operand:DI 0 "register_operand" "=r")
5491 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5492 (match_operand:DI 2 "symbolic_operand" "")]
5495 "ldq %0,%2(%1)\t\t!gottprel"
5496 [(set_attr "type" "ild")
5497 (set_attr "usegp" "yes")])
5500 [(set (match_operand:DI 0 "register_operand" "")
5501 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5502 "HAVE_AS_TLS && reload_completed"
5504 (unspec:DI [(match_dup 2)
5505 (match_dup 1)] UNSPEC_TPREL))]
5507 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5508 operands[2] = pic_offset_table_rtx;
5511 (define_insn "*movdi_er_nofix"
5512 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5513 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5514 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5515 && (register_operand (operands[0], DImode)
5516 || reg_or_0_operand (operands[1], DImode))"
5528 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")
5529 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")])
5531 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5532 ;; have been split up by the rules above but we shouldn't reject the
5533 ;; possibility of them getting through.
5535 (define_insn "*movdi_nofix"
5536 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5537 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5539 && (register_operand (operands[0], DImode)
5540 || reg_or_0_operand (operands[1], DImode))"
5545 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5552 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5553 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5555 (define_insn "*movdi_er_fix"
5556 [(set (match_operand:DI 0 "nonimmediate_operand"
5557 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5558 (match_operand:DI 1 "input_operand"
5559 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5560 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5561 && (register_operand (operands[0], DImode)
5562 || reg_or_0_operand (operands[1], DImode))"
5576 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
5577 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")])
5579 (define_insn "*movdi_fix"
5580 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5581 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5582 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5583 && (register_operand (operands[0], DImode)
5584 || reg_or_0_operand (operands[1], DImode))"
5597 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5599 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5600 ;; often appears dead to the life analysis code, at which point we
5601 ;; abort for emitting dead prologue instructions. Force this live.
5603 (define_insn "force_movdi"
5604 [(set (match_operand:DI 0 "register_operand" "=r")
5605 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5606 UNSPECV_FORCE_MOV))]
5609 [(set_attr "type" "ilog")])
5611 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5612 ;; memory, and construct long 32-bit constants.
5614 (define_expand "movdi"
5615 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5616 (match_operand:DI 1 "general_operand" ""))]
5619 if (alpha_expand_mov (DImode, operands))
5623 ;; Split a load of a large constant into the appropriate two-insn
5627 [(set (match_operand:DI 0 "register_operand" "")
5628 (match_operand:DI 1 "const_int_operand" ""))]
5629 "! add_operand (operands[1], DImode)"
5630 [(set (match_dup 0) (match_dup 2))
5631 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5634 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5636 if (tem == operands[0])
5642 ;; These are the partial-word cases.
5644 ;; First we have the code to load an aligned word. Operand 0 is the register
5645 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5646 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5647 ;; number of bits within the word that the value is. Operand 3 is an SImode
5648 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5649 ;; same register. It is allowed to conflict with operand 1 as well.
5651 (define_expand "aligned_loadqi"
5652 [(set (match_operand:SI 3 "register_operand" "")
5653 (match_operand:SI 1 "memory_operand" ""))
5654 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5655 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5657 (match_operand:DI 2 "const_int_operand" "")))]
5662 (define_expand "aligned_loadhi"
5663 [(set (match_operand:SI 3 "register_operand" "")
5664 (match_operand:SI 1 "memory_operand" ""))
5665 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5666 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5668 (match_operand:DI 2 "const_int_operand" "")))]
5673 ;; Similar for unaligned loads, where we use the sequence from the
5674 ;; Alpha Architecture manual. We have to distinguish between little-endian
5675 ;; and big-endian systems as the sequences are different.
5677 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5678 ;; operand 3 can overlap the input and output registers.
5680 (define_expand "unaligned_loadqi"
5681 [(use (match_operand:QI 0 "register_operand" ""))
5682 (use (match_operand:DI 1 "address_operand" ""))
5683 (use (match_operand:DI 2 "register_operand" ""))
5684 (use (match_operand:DI 3 "register_operand" ""))]
5687 if (WORDS_BIG_ENDIAN)
5688 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5689 operands[2], operands[3]));
5691 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5692 operands[2], operands[3]));
5696 (define_expand "unaligned_loadqi_le"
5697 [(set (match_operand:DI 2 "register_operand" "")
5698 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5700 (set (match_operand:DI 3 "register_operand" "")
5702 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5703 (zero_extract:DI (match_dup 2)
5705 (ashift:DI (match_dup 3) (const_int 3))))]
5706 "! WORDS_BIG_ENDIAN"
5709 (define_expand "unaligned_loadqi_be"
5710 [(set (match_operand:DI 2 "register_operand" "")
5711 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5713 (set (match_operand:DI 3 "register_operand" "")
5715 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5716 (zero_extract:DI (match_dup 2)
5720 (ashift:DI (match_dup 3) (const_int 3)))))]
5724 (define_expand "unaligned_loadhi"
5725 [(use (match_operand:QI 0 "register_operand" ""))
5726 (use (match_operand:DI 1 "address_operand" ""))
5727 (use (match_operand:DI 2 "register_operand" ""))
5728 (use (match_operand:DI 3 "register_operand" ""))]
5731 if (WORDS_BIG_ENDIAN)
5732 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5733 operands[2], operands[3]));
5735 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5736 operands[2], operands[3]));
5740 (define_expand "unaligned_loadhi_le"
5741 [(set (match_operand:DI 2 "register_operand" "")
5742 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5744 (set (match_operand:DI 3 "register_operand" "")
5746 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5747 (zero_extract:DI (match_dup 2)
5749 (ashift:DI (match_dup 3) (const_int 3))))]
5750 "! WORDS_BIG_ENDIAN"
5753 (define_expand "unaligned_loadhi_be"
5754 [(set (match_operand:DI 2 "register_operand" "")
5755 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5757 (set (match_operand:DI 3 "register_operand" "")
5758 (plus:DI (match_dup 1) (const_int 1)))
5759 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5760 (zero_extract:DI (match_dup 2)
5764 (ashift:DI (match_dup 3) (const_int 3)))))]
5768 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5769 ;; aligned SImode MEM. Operand 1 is the register containing the
5770 ;; byte or word to store. Operand 2 is the number of bits within the word that
5771 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5773 (define_expand "aligned_store"
5774 [(set (match_operand:SI 3 "register_operand" "")
5775 (match_operand:SI 0 "memory_operand" ""))
5776 (set (subreg:DI (match_dup 3) 0)
5777 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5778 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5779 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5780 (match_operand:DI 2 "const_int_operand" "")))
5781 (set (subreg:DI (match_dup 4) 0)
5782 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5783 (set (match_dup 0) (match_dup 4))]
5786 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5787 << INTVAL (operands[2])));
5790 ;; For the unaligned byte and halfword cases, we use code similar to that
5791 ;; in the ;; Architecture book, but reordered to lower the number of registers
5792 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5793 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5794 ;; be the same temporary, if desired. If the address is in a register,
5795 ;; operand 2 can be that register.
5797 (define_expand "unaligned_storeqi"
5798 [(use (match_operand:DI 0 "address_operand" ""))
5799 (use (match_operand:QI 1 "register_operand" ""))
5800 (use (match_operand:DI 2 "register_operand" ""))
5801 (use (match_operand:DI 3 "register_operand" ""))
5802 (use (match_operand:DI 4 "register_operand" ""))]
5805 if (WORDS_BIG_ENDIAN)
5806 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5807 operands[2], operands[3],
5810 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5811 operands[2], operands[3],
5816 (define_expand "unaligned_storeqi_le"
5817 [(set (match_operand:DI 3 "register_operand" "")
5818 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5820 (set (match_operand:DI 2 "register_operand" "")
5823 (and:DI (not:DI (ashift:DI (const_int 255)
5824 (ashift:DI (match_dup 2) (const_int 3))))
5826 (set (match_operand:DI 4 "register_operand" "")
5827 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5828 (ashift:DI (match_dup 2) (const_int 3))))
5829 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5830 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5832 "! WORDS_BIG_ENDIAN"
5835 (define_expand "unaligned_storeqi_be"
5836 [(set (match_operand:DI 3 "register_operand" "")
5837 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5839 (set (match_operand:DI 2 "register_operand" "")
5842 (and:DI (not:DI (ashift:DI (const_int 255)
5843 (minus:DI (const_int 56)
5844 (ashift:DI (match_dup 2) (const_int 3)))))
5846 (set (match_operand:DI 4 "register_operand" "")
5847 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5848 (minus:DI (const_int 56)
5849 (ashift:DI (match_dup 2) (const_int 3)))))
5850 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5851 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5856 (define_expand "unaligned_storehi"
5857 [(use (match_operand:DI 0 "address_operand" ""))
5858 (use (match_operand:HI 1 "register_operand" ""))
5859 (use (match_operand:DI 2 "register_operand" ""))
5860 (use (match_operand:DI 3 "register_operand" ""))
5861 (use (match_operand:DI 4 "register_operand" ""))]
5864 if (WORDS_BIG_ENDIAN)
5865 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5866 operands[2], operands[3],
5869 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5870 operands[2], operands[3],
5875 (define_expand "unaligned_storehi_le"
5876 [(set (match_operand:DI 3 "register_operand" "")
5877 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5879 (set (match_operand:DI 2 "register_operand" "")
5882 (and:DI (not:DI (ashift:DI (const_int 65535)
5883 (ashift:DI (match_dup 2) (const_int 3))))
5885 (set (match_operand:DI 4 "register_operand" "")
5886 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5887 (ashift:DI (match_dup 2) (const_int 3))))
5888 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5889 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5891 "! WORDS_BIG_ENDIAN"
5894 (define_expand "unaligned_storehi_be"
5895 [(set (match_operand:DI 3 "register_operand" "")
5896 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5898 (set (match_operand:DI 2 "register_operand" "")
5899 (plus:DI (match_dup 0) (const_int 1)))
5901 (and:DI (not:DI (ashift:DI
5903 (minus:DI (const_int 56)
5904 (ashift:DI (match_dup 2) (const_int 3)))))
5906 (set (match_operand:DI 4 "register_operand" "")
5907 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5908 (minus:DI (const_int 56)
5909 (ashift:DI (match_dup 2) (const_int 3)))))
5910 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5911 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5916 ;; Here are the define_expand's for QI and HI moves that use the above
5917 ;; patterns. We have the normal sets, plus the ones that need scratch
5918 ;; registers for reload.
5920 (define_expand "movqi"
5921 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5922 (match_operand:QI 1 "general_operand" ""))]
5926 ? alpha_expand_mov (QImode, operands)
5927 : alpha_expand_mov_nobwx (QImode, operands))
5931 (define_expand "movhi"
5932 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5933 (match_operand:HI 1 "general_operand" ""))]
5937 ? alpha_expand_mov (HImode, operands)
5938 : alpha_expand_mov_nobwx (HImode, operands))
5942 ;; Here are the versions for reload. Note that in the unaligned cases
5943 ;; we know that the operand must not be a pseudo-register because stack
5944 ;; slots are always aligned references.
5946 (define_expand "reload_inqi"
5947 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5948 (match_operand:QI 1 "any_memory_operand" "m")
5949 (match_operand:TI 2 "register_operand" "=&r")])]
5954 if (GET_CODE (operands[1]) != MEM)
5957 if (aligned_memory_operand (operands[1], QImode))
5959 seq = gen_reload_inqi_help (operands[0], operands[1],
5960 gen_rtx_REG (SImode, REGNO (operands[2])));
5966 /* It is possible that one of the registers we got for operands[2]
5967 might coincide with that of operands[0] (which is why we made
5968 it TImode). Pick the other one to use as our scratch. */
5969 if (REGNO (operands[0]) == REGNO (operands[2]))
5970 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5972 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5974 addr = get_unaligned_address (operands[1], 0);
5975 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5976 gen_rtx_REG (DImode, REGNO (operands[0])));
5977 alpha_set_memflags (seq, operands[1]);
5983 (define_expand "reload_inhi"
5984 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5985 (match_operand:HI 1 "any_memory_operand" "m")
5986 (match_operand:TI 2 "register_operand" "=&r")])]
5991 if (GET_CODE (operands[1]) != MEM)
5994 if (aligned_memory_operand (operands[1], HImode))
5996 seq = gen_reload_inhi_help (operands[0], operands[1],
5997 gen_rtx_REG (SImode, REGNO (operands[2])));
6003 /* It is possible that one of the registers we got for operands[2]
6004 might coincide with that of operands[0] (which is why we made
6005 it TImode). Pick the other one to use as our scratch. */
6006 if (REGNO (operands[0]) == REGNO (operands[2]))
6007 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6009 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6011 addr = get_unaligned_address (operands[1], 0);
6012 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
6013 gen_rtx_REG (DImode, REGNO (operands[0])));
6014 alpha_set_memflags (seq, operands[1]);
6020 (define_expand "reload_outqi"
6021 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6022 (match_operand:QI 1 "register_operand" "r")
6023 (match_operand:TI 2 "register_operand" "=&r")])]
6026 if (GET_CODE (operands[0]) != MEM)
6029 if (aligned_memory_operand (operands[0], QImode))
6031 emit_insn (gen_reload_outqi_help
6032 (operands[0], operands[1],
6033 gen_rtx_REG (SImode, REGNO (operands[2])),
6034 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6038 rtx addr = get_unaligned_address (operands[0], 0);
6039 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6040 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6041 rtx scratch3 = scratch1;
6044 if (GET_CODE (addr) == REG)
6047 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6048 scratch2, scratch3);
6049 alpha_set_memflags (seq, operands[0]);
6055 (define_expand "reload_outhi"
6056 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6057 (match_operand:HI 1 "register_operand" "r")
6058 (match_operand:TI 2 "register_operand" "=&r")])]
6061 if (GET_CODE (operands[0]) != MEM)
6064 if (aligned_memory_operand (operands[0], HImode))
6066 emit_insn (gen_reload_outhi_help
6067 (operands[0], operands[1],
6068 gen_rtx_REG (SImode, REGNO (operands[2])),
6069 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6073 rtx addr = get_unaligned_address (operands[0], 0);
6074 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6075 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6076 rtx scratch3 = scratch1;
6079 if (GET_CODE (addr) == REG)
6082 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6083 scratch2, scratch3);
6084 alpha_set_memflags (seq, operands[0]);
6090 ;; Helpers for the above. The way reload is structured, we can't
6091 ;; always get a proper address for a stack slot during reload_foo
6092 ;; expansion, so we must delay our address manipulations until after.
6094 (define_insn "reload_inqi_help"
6095 [(set (match_operand:QI 0 "register_operand" "=r")
6096 (match_operand:QI 1 "memory_operand" "m"))
6097 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6098 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6101 (define_insn "reload_inhi_help"
6102 [(set (match_operand:HI 0 "register_operand" "=r")
6103 (match_operand:HI 1 "memory_operand" "m"))
6104 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6105 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6108 (define_insn "reload_outqi_help"
6109 [(set (match_operand:QI 0 "memory_operand" "=m")
6110 (match_operand:QI 1 "register_operand" "r"))
6111 (clobber (match_operand:SI 2 "register_operand" "=r"))
6112 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6113 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6116 (define_insn "reload_outhi_help"
6117 [(set (match_operand:HI 0 "memory_operand" "=m")
6118 (match_operand:HI 1 "register_operand" "r"))
6119 (clobber (match_operand:SI 2 "register_operand" "=r"))
6120 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6121 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6125 [(set (match_operand:QI 0 "register_operand" "")
6126 (match_operand:QI 1 "memory_operand" ""))
6127 (clobber (match_operand:SI 2 "register_operand" ""))]
6128 "! TARGET_BWX && reload_completed"
6131 rtx aligned_mem, bitnum;
6132 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6134 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6140 [(set (match_operand:HI 0 "register_operand" "")
6141 (match_operand:HI 1 "memory_operand" ""))
6142 (clobber (match_operand:SI 2 "register_operand" ""))]
6143 "! TARGET_BWX && reload_completed"
6146 rtx aligned_mem, bitnum;
6147 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6149 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6155 [(set (match_operand:QI 0 "memory_operand" "")
6156 (match_operand:QI 1 "register_operand" ""))
6157 (clobber (match_operand:SI 2 "register_operand" ""))
6158 (clobber (match_operand:SI 3 "register_operand" ""))]
6159 "! TARGET_BWX && reload_completed"
6162 rtx aligned_mem, bitnum;
6163 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6164 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6165 operands[2], operands[3]));
6170 [(set (match_operand:HI 0 "memory_operand" "")
6171 (match_operand:HI 1 "register_operand" ""))
6172 (clobber (match_operand:SI 2 "register_operand" ""))
6173 (clobber (match_operand:SI 3 "register_operand" ""))]
6174 "! TARGET_BWX && reload_completed"
6177 rtx aligned_mem, bitnum;
6178 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6179 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6180 operands[2], operands[3]));
6184 ;; Vector operations
6186 (define_expand "movv8qi"
6187 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
6188 (match_operand:V8QI 1 "general_operand" ""))]
6191 if (alpha_expand_mov (V8QImode, operands))
6195 (define_insn "*movv8qi_fix"
6196 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6197 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6199 && (register_operand (operands[0], V8QImode)
6200 || reg_or_0_operand (operands[1], V8QImode))"
6210 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6212 (define_insn "*movv8qi_nofix"
6213 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6214 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6216 && (register_operand (operands[0], V8QImode)
6217 || reg_or_0_operand (operands[1], V8QImode))"
6225 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6227 (define_expand "movv4hi"
6228 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
6229 (match_operand:V4HI 1 "general_operand" ""))]
6232 if (alpha_expand_mov (V4HImode, operands))
6236 (define_insn "*movv4hi_fix"
6237 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6238 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6240 && (register_operand (operands[0], V4HImode)
6241 || reg_or_0_operand (operands[1], V4HImode))"
6251 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6253 (define_insn "*movv4hi_nofix"
6254 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6255 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6257 && (register_operand (operands[0], V4HImode)
6258 || reg_or_0_operand (operands[1], V4HImode))"
6266 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6268 (define_expand "movv2si"
6269 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
6270 (match_operand:V2SI 1 "general_operand" ""))]
6273 if (alpha_expand_mov (V2SImode, operands))
6277 (define_insn "*movv2si_fix"
6278 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6279 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6281 && (register_operand (operands[0], V2SImode)
6282 || reg_or_0_operand (operands[1], V2SImode))"
6292 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6294 (define_insn "*movv2si_nofix"
6295 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6296 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6298 && (register_operand (operands[0], V2SImode)
6299 || reg_or_0_operand (operands[1], V2SImode))"
6307 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6309 (define_insn "uminv8qi3"
6310 [(set (match_operand:V8QI 0 "register_operand" "=r")
6311 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6312 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6315 [(set_attr "type" "mvi")])
6317 (define_insn "sminv8qi3"
6318 [(set (match_operand:V8QI 0 "register_operand" "=r")
6319 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6320 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6323 [(set_attr "type" "mvi")])
6325 (define_insn "uminv4hi3"
6326 [(set (match_operand:V4HI 0 "register_operand" "=r")
6327 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6328 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6331 [(set_attr "type" "mvi")])
6333 (define_insn "sminv4hi3"
6334 [(set (match_operand:V4HI 0 "register_operand" "=r")
6335 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6336 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6339 [(set_attr "type" "mvi")])
6341 (define_insn "umaxv8qi3"
6342 [(set (match_operand:V8QI 0 "register_operand" "=r")
6343 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6344 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6347 [(set_attr "type" "mvi")])
6349 (define_insn "smaxv8qi3"
6350 [(set (match_operand:V8QI 0 "register_operand" "=r")
6351 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6352 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6355 [(set_attr "type" "mvi")])
6357 (define_insn "umaxv4hi3"
6358 [(set (match_operand:V4HI 0 "register_operand" "=r")
6359 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6360 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6363 [(set_attr "type" "mvi")])
6365 (define_insn "smaxv4hi3"
6366 [(set (match_operand:V4HI 0 "register_operand" "=r")
6367 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6368 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6371 [(set_attr "type" "mvi")])
6373 ;; Bit field extract patterns which use ext[wlq][lh]
6375 (define_expand "extv"
6376 [(set (match_operand:DI 0 "register_operand" "")
6377 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6378 (match_operand:DI 2 "immediate_operand" "")
6379 (match_operand:DI 3 "immediate_operand" "")))]
6384 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6385 if (INTVAL (operands[3]) % 8 != 0
6386 || (INTVAL (operands[2]) != 16
6387 && INTVAL (operands[2]) != 32
6388 && INTVAL (operands[2]) != 64))
6391 /* From mips.md: extract_bit_field doesn't verify that our source
6392 matches the predicate, so we force it to be a MEM here. */
6393 if (GET_CODE (operands[1]) != MEM)
6396 /* The bit number is relative to the mode of operand 1 which is
6397 usually QImode (this might actually be a bug in expmed.c). Note
6398 that the bit number is negative in big-endian mode in this case.
6399 We have to convert that to the offset. */
6400 if (WORDS_BIG_ENDIAN)
6401 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6402 - INTVAL (operands[2]) - INTVAL (operands[3]);
6404 ofs = INTVAL (operands[3]);
6408 alpha_expand_unaligned_load (operands[0], operands[1],
6409 INTVAL (operands[2]) / 8,
6414 (define_expand "extzv"
6415 [(set (match_operand:DI 0 "register_operand" "")
6416 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6417 (match_operand:DI 2 "immediate_operand" "")
6418 (match_operand:DI 3 "immediate_operand" "")))]
6421 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6422 if (INTVAL (operands[3]) % 8 != 0
6423 || (INTVAL (operands[2]) != 8
6424 && INTVAL (operands[2]) != 16
6425 && INTVAL (operands[2]) != 32
6426 && INTVAL (operands[2]) != 64))
6429 if (GET_CODE (operands[1]) == MEM)
6433 /* Fail 8 bit fields, falling back on a simple byte load. */
6434 if (INTVAL (operands[2]) == 8)
6437 /* The bit number is relative to the mode of operand 1 which is
6438 usually QImode (this might actually be a bug in expmed.c). Note
6439 that the bit number is negative in big-endian mode in this case.
6440 We have to convert that to the offset. */
6441 if (WORDS_BIG_ENDIAN)
6442 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6443 - INTVAL (operands[2]) - INTVAL (operands[3]);
6445 ofs = INTVAL (operands[3]);
6449 alpha_expand_unaligned_load (operands[0], operands[1],
6450 INTVAL (operands[2]) / 8,
6456 (define_expand "insv"
6457 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6458 (match_operand:DI 1 "immediate_operand" "")
6459 (match_operand:DI 2 "immediate_operand" ""))
6460 (match_operand:DI 3 "register_operand" ""))]
6465 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6466 if (INTVAL (operands[2]) % 8 != 0
6467 || (INTVAL (operands[1]) != 16
6468 && INTVAL (operands[1]) != 32
6469 && INTVAL (operands[1]) != 64))
6472 /* From mips.md: store_bit_field doesn't verify that our source
6473 matches the predicate, so we force it to be a MEM here. */
6474 if (GET_CODE (operands[0]) != MEM)
6477 /* The bit number is relative to the mode of operand 1 which is
6478 usually QImode (this might actually be a bug in expmed.c). Note
6479 that the bit number is negative in big-endian mode in this case.
6480 We have to convert that to the offset. */
6481 if (WORDS_BIG_ENDIAN)
6482 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6483 - INTVAL (operands[1]) - INTVAL (operands[2]);
6485 ofs = INTVAL (operands[2]);
6489 alpha_expand_unaligned_store (operands[0], operands[3],
6490 INTVAL (operands[1]) / 8, ofs);
6494 ;; Block move/clear, see alpha.c for more details.
6495 ;; Argument 0 is the destination
6496 ;; Argument 1 is the source
6497 ;; Argument 2 is the length
6498 ;; Argument 3 is the alignment
6500 (define_expand "movstrqi"
6501 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6502 (match_operand:BLK 1 "memory_operand" ""))
6503 (use (match_operand:DI 2 "immediate_operand" ""))
6504 (use (match_operand:DI 3 "immediate_operand" ""))])]
6507 if (alpha_expand_block_move (operands))
6513 (define_expand "movstrdi"
6514 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6515 (match_operand:BLK 1 "memory_operand" ""))
6516 (use (match_operand:DI 2 "immediate_operand" ""))
6517 (use (match_operand:DI 3 "immediate_operand" ""))
6519 (clobber (reg:DI 25))
6520 (clobber (reg:DI 16))
6521 (clobber (reg:DI 17))
6522 (clobber (reg:DI 18))
6523 (clobber (reg:DI 19))
6524 (clobber (reg:DI 20))
6525 (clobber (reg:DI 26))
6526 (clobber (reg:DI 27))])]
6527 "TARGET_ABI_OPEN_VMS"
6529 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6530 alpha_need_linkage (XSTR (operands[4], 0), 0);
6533 (define_insn "*movstrdi_1"
6534 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6535 (match_operand:BLK 1 "memory_operand" "m,m"))
6536 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6537 (use (match_operand:DI 3 "immediate_operand" ""))
6538 (use (match_operand:DI 4 "call_operand" "i,i"))
6539 (clobber (reg:DI 25))
6540 (clobber (reg:DI 16))
6541 (clobber (reg:DI 17))
6542 (clobber (reg:DI 18))
6543 (clobber (reg:DI 19))
6544 (clobber (reg:DI 20))
6545 (clobber (reg:DI 26))
6546 (clobber (reg:DI 27))]
6547 "TARGET_ABI_OPEN_VMS"
6549 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6550 switch (which_alternative)
6553 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6555 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6560 [(set_attr "type" "multi")
6561 (set_attr "length" "28")])
6563 (define_expand "clrstrqi"
6564 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6566 (use (match_operand:DI 1 "immediate_operand" ""))
6567 (use (match_operand:DI 2 "immediate_operand" ""))])]
6570 if (alpha_expand_block_clear (operands))
6576 (define_expand "clrstrdi"
6577 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6579 (use (match_operand:DI 1 "immediate_operand" ""))
6580 (use (match_operand:DI 2 "immediate_operand" ""))
6582 (clobber (reg:DI 25))
6583 (clobber (reg:DI 16))
6584 (clobber (reg:DI 17))
6585 (clobber (reg:DI 26))
6586 (clobber (reg:DI 27))])]
6587 "TARGET_ABI_OPEN_VMS"
6589 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6590 alpha_need_linkage (XSTR (operands[3], 0), 0);
6593 (define_insn "*clrstrdi_1"
6594 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6596 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6597 (use (match_operand:DI 2 "immediate_operand" ""))
6598 (use (match_operand:DI 3 "call_operand" "i,i"))
6599 (clobber (reg:DI 25))
6600 (clobber (reg:DI 16))
6601 (clobber (reg:DI 17))
6602 (clobber (reg:DI 26))
6603 (clobber (reg:DI 27))]
6604 "TARGET_ABI_OPEN_VMS"
6606 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6607 switch (which_alternative)
6610 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6612 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6617 [(set_attr "type" "multi")
6618 (set_attr "length" "24")])
6621 ;; Subroutine of stack space allocation. Perform a stack probe.
6622 (define_expand "probe_stack"
6623 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6626 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6627 INTVAL (operands[0])));
6628 MEM_VOLATILE_P (operands[1]) = 1;
6630 operands[0] = const0_rtx;
6633 ;; This is how we allocate stack space. If we are allocating a
6634 ;; constant amount of space and we know it is less than 4096
6635 ;; bytes, we need do nothing.
6637 ;; If it is more than 4096 bytes, we need to probe the stack
6639 (define_expand "allocate_stack"
6641 (plus:DI (reg:DI 30)
6642 (match_operand:DI 1 "reg_or_cint_operand" "")))
6643 (set (match_operand:DI 0 "register_operand" "=r")
6647 if (GET_CODE (operands[1]) == CONST_INT
6648 && INTVAL (operands[1]) < 32768)
6650 if (INTVAL (operands[1]) >= 4096)
6652 /* We do this the same way as in the prologue and generate explicit
6653 probes. Then we update the stack by the constant. */
6657 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6658 while (probed + 8192 < INTVAL (operands[1]))
6659 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6661 if (probed + 4096 < INTVAL (operands[1]))
6662 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6665 operands[1] = GEN_INT (- INTVAL (operands[1]));
6666 operands[2] = virtual_stack_dynamic_rtx;
6671 rtx loop_label = gen_label_rtx ();
6672 rtx want = gen_reg_rtx (Pmode);
6673 rtx tmp = gen_reg_rtx (Pmode);
6676 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6677 force_reg (Pmode, operands[1])));
6678 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6680 if (GET_CODE (operands[1]) != CONST_INT)
6682 out_label = gen_label_rtx ();
6683 emit_insn (gen_cmpdi (want, tmp));
6684 emit_jump_insn (gen_bgeu (out_label));
6687 emit_label (loop_label);
6688 memref = gen_rtx_MEM (DImode, tmp);
6689 MEM_VOLATILE_P (memref) = 1;
6690 emit_move_insn (memref, const0_rtx);
6691 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6692 emit_insn (gen_cmpdi (tmp, want));
6693 emit_jump_insn (gen_bgtu (loop_label));
6695 memref = gen_rtx_MEM (DImode, want);
6696 MEM_VOLATILE_P (memref) = 1;
6697 emit_move_insn (memref, const0_rtx);
6700 emit_label (out_label);
6702 emit_move_insn (stack_pointer_rtx, want);
6703 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6708 ;; This is used by alpha_expand_prolog to do the same thing as above,
6709 ;; except we cannot at that time generate new basic blocks, so we hide
6710 ;; the loop in this one insn.
6712 (define_insn "prologue_stack_probe_loop"
6713 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6714 (match_operand:DI 1 "register_operand" "r")]
6718 operands[2] = gen_label_rtx ();
6719 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6720 CODE_LABEL_NUMBER (operands[2]));
6722 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6724 [(set_attr "length" "16")
6725 (set_attr "type" "multi")])
6727 (define_expand "prologue"
6728 [(clobber (const_int 0))]
6731 alpha_expand_prologue ();
6735 ;; These take care of emitting the ldgp insn in the prologue. This will be
6736 ;; an lda/ldah pair and we want to align them properly. So we have two
6737 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6738 ;; and the second of which emits nothing. However, both are marked as type
6739 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6742 (define_expand "prologue_ldgp"
6744 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6746 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6749 operands[0] = pic_offset_table_rtx;
6750 operands[1] = gen_rtx_REG (Pmode, 27);
6751 operands[2] = (TARGET_EXPLICIT_RELOCS
6752 ? GEN_INT (alpha_next_sequence_number++)
6756 (define_insn "*ldgp_er_1"
6757 [(set (match_operand:DI 0 "register_operand" "=r")
6758 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6759 (match_operand 2 "const_int_operand" "")]
6761 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6762 "ldah %0,0(%1)\t\t!gpdisp!%2")
6764 (define_insn "*ldgp_er_2"
6765 [(set (match_operand:DI 0 "register_operand" "=r")
6766 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6767 (match_operand 2 "const_int_operand" "")]
6769 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6770 "lda %0,0(%1)\t\t!gpdisp!%2")
6772 (define_insn "*prologue_ldgp_er_2"
6773 [(set (match_operand:DI 0 "register_operand" "=r")
6774 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6775 (match_operand 2 "const_int_operand" "")]
6777 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6778 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6780 (define_insn "*prologue_ldgp_1"
6781 [(set (match_operand:DI 0 "register_operand" "=r")
6782 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6783 (match_operand 2 "const_int_operand" "")]
6786 "ldgp %0,0(%1)\n$%~..ng:")
6788 (define_insn "*prologue_ldgp_2"
6789 [(set (match_operand:DI 0 "register_operand" "=r")
6790 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6791 (match_operand 2 "const_int_operand" "")]
6796 ;; The _mcount profiling hook has special calling conventions, and
6797 ;; does not clobber all the registers that a normal call would. So
6798 ;; hide the fact this is a call at all.
6800 (define_insn "prologue_mcount"
6801 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6804 if (TARGET_EXPLICIT_RELOCS)
6805 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6806 cannot be called via the PLT. */
6807 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6809 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6811 [(set_attr "type" "multi")
6812 (set_attr "length" "8")])
6814 (define_insn "init_fp"
6815 [(set (match_operand:DI 0 "register_operand" "=r")
6816 (match_operand:DI 1 "register_operand" "r"))
6817 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6821 (define_expand "epilogue"
6825 alpha_expand_epilogue ();
6828 (define_expand "sibcall_epilogue"
6832 alpha_expand_epilogue ();
6836 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6837 ;; the frame size into a register. We use this pattern to ensure
6838 ;; we get lda instead of addq.
6839 (define_insn "nt_lda"
6840 [(set (match_operand:DI 0 "register_operand" "=r")
6841 (unspec:DI [(match_dup 0)
6842 (match_operand:DI 1 "const_int_operand" "n")]
6847 (define_expand "builtin_longjmp"
6848 [(use (match_operand:DI 0 "register_operand" "r"))]
6851 /* The elements of the buffer are, in order: */
6852 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6853 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6854 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6855 rtx pv = gen_rtx_REG (Pmode, 27);
6857 /* This bit is the same as expand_builtin_longjmp. */
6858 emit_move_insn (hard_frame_pointer_rtx, fp);
6859 emit_move_insn (pv, lab);
6860 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6861 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6862 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6864 /* Load the label we are jumping through into $27 so that we know
6865 where to look for it when we get back to setjmp's function for
6866 restoring the gp. */
6867 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6872 ;; This is effectively a copy of indirect_jump, but constrained such
6873 ;; that register renaming cannot foil our cunning plan with $27.
6874 (define_insn "builtin_longjmp_internal"
6876 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6880 [(set_attr "type" "ibr")])
6882 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6883 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6884 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6885 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6887 (define_insn "*builtin_setjmp_receiver_er_1"
6888 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6889 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6890 "br $27,$LSJ%=\n$LSJ%=:"
6891 [(set_attr "type" "ibr")])
6894 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6895 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6896 && prev_nonnote_insn (insn) == operands[0]"
6900 emit_note (NULL, NOTE_INSN_DELETED);
6904 (define_insn "*builtin_setjmp_receiver_1"
6905 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6907 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6908 [(set_attr "length" "12")
6909 (set_attr "type" "multi")])
6911 (define_expand "builtin_setjmp_receiver_er"
6912 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6914 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6916 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6919 operands[1] = pic_offset_table_rtx;
6920 operands[2] = gen_rtx_REG (Pmode, 27);
6921 operands[3] = GEN_INT (alpha_next_sequence_number++);
6924 (define_expand "builtin_setjmp_receiver"
6925 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6928 if (TARGET_EXPLICIT_RELOCS)
6930 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6935 (define_expand "exception_receiver_er"
6937 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6939 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6942 operands[0] = pic_offset_table_rtx;
6943 operands[1] = gen_rtx_REG (Pmode, 26);
6944 operands[2] = GEN_INT (alpha_next_sequence_number++);
6947 (define_expand "exception_receiver"
6948 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6951 if (TARGET_LD_BUGGY_LDGP)
6952 operands[0] = alpha_gp_save_rtx ();
6953 else if (TARGET_EXPLICIT_RELOCS)
6955 emit_insn (gen_exception_receiver_er ());
6959 operands[0] = const0_rtx;
6962 (define_insn "*exception_receiver_1"
6963 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6964 "! TARGET_LD_BUGGY_LDGP"
6966 [(set_attr "length" "8")
6967 (set_attr "type" "multi")])
6969 (define_insn "*exception_receiver_2"
6970 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6971 "TARGET_LD_BUGGY_LDGP"
6973 [(set_attr "type" "ild")])
6975 (define_expand "nonlocal_goto_receiver"
6976 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6977 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6978 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6980 "TARGET_ABI_OPEN_VMS"
6983 (define_insn "arg_home"
6984 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6999 (clobber (mem:BLK (const_int 0)))
7000 (clobber (reg:DI 24))
7001 (clobber (reg:DI 25))
7002 (clobber (reg:DI 0))]
7003 "TARGET_ABI_OPEN_VMS"
7004 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7005 [(set_attr "length" "16")
7006 (set_attr "type" "multi")])
7008 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7010 (define_expand "umk_mismatch_args"
7011 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7012 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7013 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7014 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7017 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7018 "TARGET_ABI_UNICOSMK"
7020 operands[1] = gen_reg_rtx (DImode);
7021 operands[2] = gen_reg_rtx (DImode);
7022 operands[3] = gen_reg_rtx (DImode);
7025 (define_insn "arg_home_umk"
7026 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7041 (clobber (mem:BLK (const_int 0)))
7043 (clobber (reg:DI 22))
7044 (clobber (reg:DI 23))
7045 (clobber (reg:DI 24))
7046 (clobber (reg:DI 0))
7047 (clobber (reg:DI 1))
7048 (clobber (reg:DI 2))
7049 (clobber (reg:DI 3))
7050 (clobber (reg:DI 4))
7051 (clobber (reg:DI 5))
7052 (clobber (reg:DI 6))
7053 (clobber (reg:DI 7))
7054 (clobber (reg:DI 8))])]
7055 "TARGET_ABI_UNICOSMK"
7056 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7057 [(set_attr "length" "16")
7058 (set_attr "type" "multi")])
7062 ;; On EV4, these instructions are nops -- no load occurs.
7064 ;; On EV5, these instructions act as a normal load, and thus can trap
7065 ;; if the address is invalid. The OS may (or may not) handle this in
7066 ;; the entMM fault handler and suppress the fault. If so, then this
7067 ;; has the effect of a read prefetch instruction.
7069 ;; On EV6, these become official prefetch instructions.
7071 (define_insn "prefetch"
7072 [(prefetch (match_operand:DI 0 "address_operand" "p")
7073 (match_operand:DI 1 "const_int_operand" "n")
7074 (match_operand:DI 2 "const_int_operand" "n"))]
7075 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
7077 /* Interpret "no temporal locality" as this data should be evicted once
7078 it is used. The "evict next" alternatives load the data into the cache
7079 and leave the LRU eviction counter pointing to that block. */
7080 static const char * const alt[2][2] = {
7082 "ldq $31,%a0", /* read, evict next */
7083 "ldl $31,%a0", /* read, evict last */
7086 "ldt $f31,%a0", /* write, evict next */
7087 "lds $f31,%a0", /* write, evict last */
7091 bool write = INTVAL (operands[1]) != 0;
7092 bool lru = INTVAL (operands[2]) != 0;
7094 return alt[write][lru];
7096 [(set_attr "type" "ild")])
7098 ;; Close the trap shadow of preceding instructions. This is generated
7101 (define_insn "trapb"
7102 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7105 [(set_attr "type" "misc")])
7107 ;; No-op instructions used by machine-dependent reorg to preserve
7108 ;; alignment for instruction issue.
7109 ;; The Unicos/Mk assembler does not support these opcodes.
7115 [(set_attr "type" "ilog")])
7120 "cpys $f31,$f31,$f31"
7121 [(set_attr "type" "fcpys")])
7128 ;; On Unicos/Mk we use a macro for aligning code.
7130 (define_insn "realign"
7131 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7135 if (TARGET_ABI_UNICOSMK)
7136 return "gcc@code@align %0";
7138 return ".align %0 #realign";
7141 ;; Instructions to be emitted from __builtins.
7143 (define_insn "builtin_cmpbge"
7144 [(set (match_operand:DI 0 "register_operand" "=r")
7145 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7146 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7150 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7151 ;; actually differentiate between ILOG and ICMP in the schedule.
7152 [(set_attr "type" "icmp")])
7154 (define_expand "builtin_extbl"
7155 [(match_operand:DI 0 "register_operand" "")
7156 (match_operand:DI 1 "reg_or_0_operand" "")
7157 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7160 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7161 if (WORDS_BIG_ENDIAN)
7165 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7169 (define_expand "builtin_extwl"
7170 [(match_operand:DI 0 "register_operand" "")
7171 (match_operand:DI 1 "reg_or_0_operand" "")
7172 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7175 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7176 if (WORDS_BIG_ENDIAN)
7180 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7184 (define_expand "builtin_extll"
7185 [(match_operand:DI 0 "register_operand" "")
7186 (match_operand:DI 1 "reg_or_0_operand" "")
7187 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7190 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7191 if (WORDS_BIG_ENDIAN)
7195 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7199 (define_expand "builtin_extql"
7200 [(match_operand:DI 0 "register_operand" "")
7201 (match_operand:DI 1 "reg_or_0_operand" "")
7202 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7205 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7206 if (WORDS_BIG_ENDIAN)
7210 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7214 (define_expand "builtin_extwh"
7215 [(match_operand:DI 0 "register_operand" "")
7216 (match_operand:DI 1 "reg_or_0_operand" "")
7217 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7220 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7221 if (WORDS_BIG_ENDIAN)
7225 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7229 (define_expand "builtin_extlh"
7230 [(match_operand:DI 0 "register_operand" "")
7231 (match_operand:DI 1 "reg_or_0_operand" "")
7232 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7235 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7236 if (WORDS_BIG_ENDIAN)
7240 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7244 (define_expand "builtin_extqh"
7245 [(match_operand:DI 0 "register_operand" "")
7246 (match_operand:DI 1 "reg_or_0_operand" "")
7247 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7250 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7251 if (WORDS_BIG_ENDIAN)
7255 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7259 (define_expand "builtin_insbl"
7260 [(match_operand:DI 0 "register_operand" "")
7261 (match_operand:DI 1 "reg_or_0_operand" "")
7262 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7265 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7266 if (WORDS_BIG_ENDIAN)
7270 operands[1] = gen_lowpart (QImode, operands[1]);
7271 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7275 (define_expand "builtin_inswl"
7276 [(match_operand:DI 0 "register_operand" "")
7277 (match_operand:DI 1 "reg_or_0_operand" "")
7278 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7281 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7282 if (WORDS_BIG_ENDIAN)
7286 operands[1] = gen_lowpart (HImode, operands[1]);
7287 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7291 (define_expand "builtin_insll"
7292 [(match_operand:DI 0 "register_operand" "")
7293 (match_operand:DI 1 "reg_or_0_operand" "")
7294 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7297 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7298 if (WORDS_BIG_ENDIAN)
7302 operands[1] = gen_lowpart (SImode, operands[1]);
7303 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7304 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7308 (define_expand "builtin_insql"
7309 [(match_operand:DI 0 "register_operand" "")
7310 (match_operand:DI 1 "reg_or_0_operand" "")
7311 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7314 rtx (*gen) PARAMS ((rtx, rtx, rtx));
7315 if (WORDS_BIG_ENDIAN)
7319 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7323 (define_expand "builtin_inswh"
7324 [(match_operand:DI 0 "register_operand" "")
7325 (match_operand:DI 1 "register_operand" "")
7326 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7329 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7333 (define_expand "builtin_inslh"
7334 [(match_operand:DI 0 "register_operand" "")
7335 (match_operand:DI 1 "register_operand" "")
7336 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7339 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7343 (define_expand "builtin_insqh"
7344 [(match_operand:DI 0 "register_operand" "")
7345 (match_operand:DI 1 "register_operand" "")
7346 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7349 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7353 (define_expand "builtin_mskbl"
7354 [(match_operand:DI 0 "register_operand" "")
7355 (match_operand:DI 1 "reg_or_0_operand" "")
7356 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7359 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7361 if (WORDS_BIG_ENDIAN)
7365 mask = GEN_INT (0xff);
7366 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7370 (define_expand "builtin_mskwl"
7371 [(match_operand:DI 0 "register_operand" "")
7372 (match_operand:DI 1 "reg_or_0_operand" "")
7373 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7376 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7378 if (WORDS_BIG_ENDIAN)
7382 mask = GEN_INT (0xffff);
7383 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7387 (define_expand "builtin_mskll"
7388 [(match_operand:DI 0 "register_operand" "")
7389 (match_operand:DI 1 "reg_or_0_operand" "")
7390 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7393 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7395 if (WORDS_BIG_ENDIAN)
7399 mask = immed_double_const (0xffffffff, 0, DImode);
7400 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7404 (define_expand "builtin_mskql"
7405 [(match_operand:DI 0 "register_operand" "")
7406 (match_operand:DI 1 "reg_or_0_operand" "")
7407 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7410 rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
7412 if (WORDS_BIG_ENDIAN)
7417 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7421 (define_expand "builtin_mskwh"
7422 [(match_operand:DI 0 "register_operand" "")
7423 (match_operand:DI 1 "register_operand" "")
7424 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7427 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7431 (define_expand "builtin_msklh"
7432 [(match_operand:DI 0 "register_operand" "")
7433 (match_operand:DI 1 "register_operand" "")
7434 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7437 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7441 (define_expand "builtin_mskqh"
7442 [(match_operand:DI 0 "register_operand" "")
7443 (match_operand:DI 1 "register_operand" "")
7444 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7447 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7451 (define_expand "builtin_zap"
7452 [(set (match_operand:DI 0 "register_operand" "")
7454 [(match_operand:DI 2 "reg_or_const_int_operand" "")]
7456 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7459 if (GET_CODE (operands[2]) == CONST_INT)
7461 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7463 if (mask == const0_rtx)
7465 emit_move_insn (operands[0], const0_rtx);
7468 if (mask == constm1_rtx)
7470 emit_move_insn (operands[0], operands[1]);
7474 operands[1] = force_reg (DImode, operands[1]);
7475 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7479 operands[1] = force_reg (DImode, operands[1]);
7480 operands[2] = gen_lowpart (QImode, operands[2]);
7483 (define_insn "*builtin_zap_1"
7484 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7486 [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")]
7488 (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))]
7495 [(set_attr "type" "shift,shift,ilog,shift")])
7498 [(set (match_operand:DI 0 "register_operand" "")
7500 [(match_operand:QI 2 "const_int_operand" "")]
7502 (match_operand:DI 1 "const_int_operand" "")))]
7506 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7507 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7508 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7511 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7512 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7513 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7514 c_hi & CONST_DOUBLE_HIGH (mask),
7517 emit_move_insn (operands[0], operands[1]);
7522 [(set (match_operand:DI 0 "register_operand" "")
7524 [(match_operand:QI 2 "const_int_operand" "")]
7526 (match_operand:DI 1 "register_operand" "")))]
7529 (and:DI (match_dup 1) (match_dup 2)))]
7531 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7532 if (operands[2] == const0_rtx)
7534 emit_move_insn (operands[0], const0_rtx);
7537 if (operands[2] == constm1_rtx)
7539 emit_move_insn (operands[0], operands[1]);
7544 (define_expand "builtin_zapnot"
7545 [(set (match_operand:DI 0 "register_operand" "")
7547 [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))]
7549 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7552 if (GET_CODE (operands[2]) == CONST_INT)
7554 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7556 if (mask == const0_rtx)
7558 emit_move_insn (operands[0], const0_rtx);
7561 if (mask == constm1_rtx)
7563 emit_move_insn (operands[0], operands[1]);
7567 operands[1] = force_reg (DImode, operands[1]);
7568 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7572 operands[1] = force_reg (DImode, operands[1]);
7573 operands[2] = gen_lowpart (QImode, operands[2]);
7576 (define_insn "*builtin_zapnot_1"
7577 [(set (match_operand:DI 0 "register_operand" "=r")
7579 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7581 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7584 [(set_attr "type" "shift")])
7586 (define_insn "builtin_amask"
7587 [(set (match_operand:DI 0 "register_operand" "=r")
7588 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7592 [(set_attr "type" "ilog")])
7594 (define_insn "builtin_implver"
7595 [(set (match_operand:DI 0 "register_operand" "=r")
7596 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7599 [(set_attr "type" "ilog")])
7601 (define_insn "builtin_rpcc"
7602 [(set (match_operand:DI 0 "register_operand" "=r")
7603 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7606 [(set_attr "type" "ilog")])
7608 (define_expand "builtin_minub8"
7609 [(match_operand:DI 0 "register_operand" "")
7610 (match_operand:DI 1 "reg_or_0_operand" "")
7611 (match_operand:DI 2 "reg_or_0_operand" "")]
7614 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7615 operands[1], operands[2]);
7619 (define_expand "builtin_minsb8"
7620 [(match_operand:DI 0 "register_operand" "")
7621 (match_operand:DI 1 "reg_or_0_operand" "")
7622 (match_operand:DI 2 "reg_or_0_operand" "")]
7625 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7626 operands[1], operands[2]);
7630 (define_expand "builtin_minuw4"
7631 [(match_operand:DI 0 "register_operand" "")
7632 (match_operand:DI 1 "reg_or_0_operand" "")
7633 (match_operand:DI 2 "reg_or_0_operand" "")]
7636 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7637 operands[1], operands[2]);
7641 (define_expand "builtin_minsw4"
7642 [(match_operand:DI 0 "register_operand" "")
7643 (match_operand:DI 1 "reg_or_0_operand" "")
7644 (match_operand:DI 2 "reg_or_0_operand" "")]
7647 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7648 operands[1], operands[2]);
7652 (define_expand "builtin_maxub8"
7653 [(match_operand:DI 0 "register_operand" "")
7654 (match_operand:DI 1 "reg_or_0_operand" "")
7655 (match_operand:DI 2 "reg_or_0_operand" "")]
7658 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7659 operands[1], operands[2]);
7663 (define_expand "builtin_maxsb8"
7664 [(match_operand:DI 0 "register_operand" "")
7665 (match_operand:DI 1 "reg_or_0_operand" "")
7666 (match_operand:DI 2 "reg_or_0_operand" "")]
7669 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7670 operands[1], operands[2]);
7674 (define_expand "builtin_maxuw4"
7675 [(match_operand:DI 0 "register_operand" "")
7676 (match_operand:DI 1 "reg_or_0_operand" "")
7677 (match_operand:DI 2 "reg_or_0_operand" "")]
7680 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7681 operands[1], operands[2]);
7685 (define_expand "builtin_maxsw4"
7686 [(match_operand:DI 0 "register_operand" "")
7687 (match_operand:DI 1 "reg_or_0_operand" "")
7688 (match_operand:DI 2 "reg_or_0_operand" "")]
7691 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7692 operands[1], operands[2]);
7696 (define_insn "builtin_perr"
7697 [(set (match_operand:DI 0 "register_operand" "=r")
7698 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7699 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7703 [(set_attr "type" "mvi")])
7705 (define_expand "builtin_pklb"
7706 [(set (match_operand:DI 0 "register_operand" "")
7709 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7714 operands[0] = gen_lowpart (V8QImode, operands[0]);
7715 operands[1] = gen_lowpart (V2SImode, operands[1]);
7716 operands[2] = CONST0_RTX (V2QImode);
7717 operands[3] = CONST0_RTX (V4QImode);
7720 (define_insn "*pklb"
7721 [(set (match_operand:V8QI 0 "register_operand" "=r")
7724 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7725 (match_operand:V2QI 2 "const0_operand" ""))
7726 (match_operand:V4QI 3 "const0_operand" "")))]
7729 [(set_attr "type" "mvi")])
7731 (define_expand "builtin_pkwb"
7732 [(set (match_operand:DI 0 "register_operand" "")
7734 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7738 operands[0] = gen_lowpart (V8QImode, operands[0]);
7739 operands[1] = gen_lowpart (V4HImode, operands[1]);
7740 operands[2] = CONST0_RTX (V4QImode);
7743 (define_insn "*pkwb"
7744 [(set (match_operand:V8QI 0 "register_operand" "=r")
7746 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7747 (match_operand:V4QI 2 "const0_operand" "")))]
7750 [(set_attr "type" "mvi")])
7752 (define_expand "builtin_unpkbl"
7753 [(set (match_operand:DI 0 "register_operand" "")
7755 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7756 (parallel [(const_int 0) (const_int 1)]))))]
7759 operands[0] = gen_lowpart (V2SImode, operands[0]);
7760 operands[1] = gen_lowpart (V8QImode, operands[1]);
7763 (define_insn "*unpkbl"
7764 [(set (match_operand:V2SI 0 "register_operand" "=r")
7766 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7767 (parallel [(const_int 0) (const_int 1)]))))]
7770 [(set_attr "type" "mvi")])
7772 (define_expand "builtin_unpkbw"
7773 [(set (match_operand:DI 0 "register_operand" "")
7775 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7776 (parallel [(const_int 0)
7782 operands[0] = gen_lowpart (V4HImode, operands[0]);
7783 operands[1] = gen_lowpart (V8QImode, operands[1]);
7786 (define_insn "*unpkbw"
7787 [(set (match_operand:V4HI 0 "register_operand" "=r")
7789 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7790 (parallel [(const_int 0)
7796 [(set_attr "type" "mvi")])
7798 (define_expand "builtin_cttz"
7799 [(set (match_operand:DI 0 "register_operand" "")
7800 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7805 (define_insn "builtin_ctlz"
7806 [(set (match_operand:DI 0 "register_operand" "=r")
7807 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7811 [(set_attr "type" "mvi")])
7813 (define_insn "builtin_ctpop"
7814 [(set (match_operand:DI 0 "register_operand" "=r")
7815 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7819 [(set_attr "type" "mvi")])
7821 ;; The call patterns are at the end of the file because their
7822 ;; wildcard operand0 interferes with nice recognition.
7824 (define_insn "*call_value_osf_1_er"
7825 [(set (match_operand 0 "" "")
7826 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7827 (match_operand 2 "" "")))
7829 (clobber (reg:DI 26))]
7830 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7832 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7833 bsr $26,%1\t\t!samegp
7834 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7835 [(set_attr "type" "jsr")
7836 (set_attr "length" "12,*,16")])
7838 ;; We must use peep2 instead of a split because we need accurate life
7839 ;; information for $gp. Consider the case of { bar(); while (1); }.
7841 [(parallel [(set (match_operand 0 "" "")
7842 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7843 (match_operand 2 "" "")))
7845 (clobber (reg:DI 26))])]
7846 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7847 && ! samegp_function_operand (operands[1], Pmode)
7848 && peep2_regno_dead_p (1, 29)"
7849 [(parallel [(set (match_dup 0)
7850 (call (mem:DI (match_dup 3))
7852 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7853 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7855 (use (match_dup 4))])]
7857 if (CONSTANT_P (operands[1]))
7859 operands[3] = gen_rtx_REG (Pmode, 27);
7860 operands[4] = GEN_INT (alpha_next_sequence_number++);
7861 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7862 operands[1], operands[4]));
7866 operands[3] = operands[1];
7867 operands[1] = const0_rtx;
7868 operands[4] = const0_rtx;
7873 [(parallel [(set (match_operand 0 "" "")
7874 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7875 (match_operand 2 "" "")))
7877 (clobber (reg:DI 26))])]
7878 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7879 && ! samegp_function_operand (operands[1], Pmode)
7880 && ! peep2_regno_dead_p (1, 29)"
7881 [(parallel [(set (match_dup 0)
7882 (call (mem:DI (match_dup 3))
7884 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7885 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7887 (use (match_dup 5))])
7889 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7891 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7893 if (CONSTANT_P (operands[1]))
7895 operands[3] = gen_rtx_REG (Pmode, 27);
7896 operands[5] = GEN_INT (alpha_next_sequence_number++);
7897 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7898 operands[1], operands[5]));
7902 operands[3] = operands[1];
7903 operands[1] = const0_rtx;
7904 operands[5] = const0_rtx;
7906 operands[4] = GEN_INT (alpha_next_sequence_number++);
7909 ;; We add a blockage unspec_volatile to prevent insns from moving down
7910 ;; from above the call to in between the call and the ldah gpdisp.
7911 (define_insn "*call_value_osf_2_er"
7912 [(set (match_operand 0 "" "")
7913 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7914 (match_operand 2 "" "")))
7916 (plus:DI (pc) (const_int 4)))
7917 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7918 (use (match_operand 3 "" ""))
7919 (use (match_operand 4 "" ""))]
7920 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7921 "jsr $26,(%1),%3%J4"
7922 [(set_attr "type" "jsr")])
7924 (define_insn "*call_value_osf_1_noreturn"
7925 [(set (match_operand 0 "" "")
7926 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7927 (match_operand 2 "" "")))
7929 (clobber (reg:DI 26))]
7930 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7931 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7936 [(set_attr "type" "jsr")
7937 (set_attr "length" "*,*,8")])
7939 (define_insn_and_split "call_value_osf_tlsgd"
7940 [(set (match_operand 0 "" "")
7941 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7943 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7945 (clobber (reg:DI 26))]
7948 "&& reload_completed"
7950 (unspec:DI [(match_dup 5)
7952 (match_dup 2)] UNSPEC_LITERAL))
7953 (parallel [(set (match_dup 0)
7954 (call (mem:DI (match_dup 3))
7956 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7957 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7959 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7961 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7963 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7965 operands[3] = gen_rtx_REG (Pmode, 27);
7966 operands[4] = GEN_INT (alpha_next_sequence_number++);
7967 operands[5] = pic_offset_table_rtx;
7969 [(set_attr "type" "multi")])
7971 (define_insn_and_split "call_value_osf_tlsldm"
7972 [(set (match_operand 0 "" "")
7973 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7975 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7977 (clobber (reg:DI 26))]
7980 "&& reload_completed"
7982 (unspec:DI [(match_dup 5)
7984 (match_dup 2)] UNSPEC_LITERAL))
7985 (parallel [(set (match_dup 0)
7986 (call (mem:DI (match_dup 3))
7988 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7989 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7991 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7993 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7995 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7997 operands[3] = gen_rtx_REG (Pmode, 27);
7998 operands[4] = GEN_INT (alpha_next_sequence_number++);
7999 operands[5] = pic_offset_table_rtx;
8001 [(set_attr "type" "multi")])
8003 (define_insn "*call_value_osf_1"
8004 [(set (match_operand 0 "" "")
8005 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8006 (match_operand 2 "" "")))
8008 (clobber (reg:DI 26))]
8009 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8011 jsr $26,($27),0\;ldgp $29,0($26)
8013 jsr $26,%1\;ldgp $29,0($26)"
8014 [(set_attr "type" "jsr")
8015 (set_attr "length" "12,*,16")])
8017 (define_insn "*sibcall_value_osf_1_er"
8018 [(set (match_operand 0 "" "")
8019 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8020 (match_operand 2 "" "")))
8021 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8022 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8024 br $31,%1\t\t!samegp
8025 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8026 [(set_attr "type" "jsr")
8027 (set_attr "length" "*,8")])
8029 (define_insn "*sibcall_value_osf_1"
8030 [(set (match_operand 0 "" "")
8031 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8032 (match_operand 2 "" "")))
8033 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8034 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8037 lda $27,%1\;jmp $31,($27),%1"
8038 [(set_attr "type" "jsr")
8039 (set_attr "length" "*,8")])
8041 (define_insn "*call_value_nt_1"
8042 [(set (match_operand 0 "" "")
8043 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8044 (match_operand 2 "" "")))
8045 (clobber (reg:DI 26))]
8046 "TARGET_ABI_WINDOWS_NT"
8051 [(set_attr "type" "jsr")
8052 (set_attr "length" "*,*,12")])
8054 ; GAS relies on the order and position of instructions output below in order
8055 ; to generate relocs for VMS link to potentially optimize the call.
8056 ; Please do not molest.
8057 (define_insn "*call_value_vms_1"
8058 [(set (match_operand 0 "" "")
8059 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8060 (match_operand 2 "" "")))
8061 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8064 (clobber (reg:DI 27))]
8065 "TARGET_ABI_OPEN_VMS"
8067 switch (which_alternative)
8070 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8072 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8073 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8074 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8079 [(set_attr "type" "jsr")
8080 (set_attr "length" "12,16")])
8082 (define_insn "*call_value_umk"
8083 [(set (match_operand 0 "" "")
8084 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8085 (match_operand 2 "" "")))
8087 (clobber (reg:DI 26))]
8088 "TARGET_ABI_UNICOSMK"
8090 [(set_attr "type" "jsr")])