1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
48 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
49 (UNSPECV_LONGJMP 3) ; builtin_longjmp
51 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
53 (UNSPECV_EHR 7) ; exception_receiver
57 (UNSPECV_PLDGP2 11) ; prologue ldgp
60 ;; Where necessary, the suffixes _le and _be are used to distinguish between
61 ;; little-endian and big-endian patterns.
63 ;; Note that the Unicos/Mk assembler does not support the following
64 ;; opcodes: mov, fmov, nop, fnop, unop.
66 ;; Processor type -- this attribute must exactly match the processor_type
67 ;; enumeration in alpha.h.
69 (define_attr "cpu" "ev4,ev5,ev6"
70 (const (symbol_ref "alpha_cpu")))
72 ;; Define an insn type attribute. This is used in function unit delay
73 ;; computations, among other purposes. For the most part, we use the names
74 ;; defined in the EV4 documentation, but add a few that we have to know about
78 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
79 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
80 (const_string "iadd"))
82 ;; Describe a user's asm statement.
83 (define_asm_attributes
84 [(set_attr "type" "multi")])
86 ;; Define the operand size an insn operates on. Used primarily by mul
87 ;; and div operations that have size dependant timings.
89 (define_attr "opsize" "si,di,udi"
92 ;; The TRAP attribute marks instructions that may generate traps
93 ;; (which are imprecise and may need a trapb if software completion
96 (define_attr "trap" "no,yes"
99 ;; The ROUND_SUFFIX attribute marks which instructions require a
100 ;; rounding-mode suffix. The value NONE indicates no suffix,
101 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
103 (define_attr "round_suffix" "none,normal,c"
104 (const_string "none"))
106 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
108 ;; SU accepts only /su (cmpt et al)
109 ;; SUI accepts only /sui (cvtqt and cvtqs)
110 ;; V_SV accepts /v and /sv (cvtql only)
111 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
112 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
114 ;; The actual suffix emitted is controled by alpha_fptm.
116 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
117 (const_string "none"))
119 ;; The length of an instruction sequence in bytes.
121 (define_attr "length" ""
124 ;; On EV4 there are two classes of resources to consider: resources needed
125 ;; to issue, and resources needed to execute. IBUS[01] are in the first
126 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
127 ;; (There are a few other register-like resources, but ...)
129 ; First, describe all of the issue constraints with single cycle delays.
130 ; All insns need a bus, but all except loads require one or the other.
131 (define_function_unit "ev4_ibus0" 1 0
132 (and (eq_attr "cpu" "ev4")
133 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
136 (define_function_unit "ev4_ibus1" 1 0
137 (and (eq_attr "cpu" "ev4")
138 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
141 ; Memory delivers its result in three cycles. Actually return one and
142 ; take care of this in adjust_cost, since we want to handle user-defined
144 (define_function_unit "ev4_abox" 1 0
145 (and (eq_attr "cpu" "ev4")
146 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
149 ; Branches have no delay cost, but do tie up the unit for two cycles.
150 (define_function_unit "ev4_bbox" 1 1
151 (and (eq_attr "cpu" "ev4")
152 (eq_attr "type" "ibr,fbr,jsr"))
155 ; Arithmetic insns are normally have their results available after
156 ; two cycles. There are a number of exceptions. They are encoded in
157 ; ADJUST_COST. Some of the other insns have similar exceptions.
158 (define_function_unit "ev4_ebox" 1 0
159 (and (eq_attr "cpu" "ev4")
160 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
163 (define_function_unit "imul" 1 0
164 (and (eq_attr "cpu" "ev4")
165 (and (eq_attr "type" "imul")
166 (eq_attr "opsize" "si")))
169 (define_function_unit "imul" 1 0
170 (and (eq_attr "cpu" "ev4")
171 (and (eq_attr "type" "imul")
172 (eq_attr "opsize" "!si")))
175 (define_function_unit "ev4_fbox" 1 0
176 (and (eq_attr "cpu" "ev4")
177 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
180 (define_function_unit "fdiv" 1 0
181 (and (eq_attr "cpu" "ev4")
182 (and (eq_attr "type" "fdiv")
183 (eq_attr "opsize" "si")))
186 (define_function_unit "fdiv" 1 0
187 (and (eq_attr "cpu" "ev4")
188 (and (eq_attr "type" "fdiv")
189 (eq_attr "opsize" "di")))
192 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
194 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
195 ;; with the combined resource EBOX.
197 (define_function_unit "ev5_ebox" 2 0
198 (and (eq_attr "cpu" "ev5")
199 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
202 ; Memory takes at least 2 clocks. Return one from here and fix up with
203 ; user-defined latencies in adjust_cost.
204 (define_function_unit "ev5_ebox" 2 0
205 (and (eq_attr "cpu" "ev5")
206 (eq_attr "type" "ild,fld,ldsym"))
209 ; Loads can dual issue with one another, but loads and stores do not mix.
210 (define_function_unit "ev5_e0" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (eq_attr "type" "ild,fld,ldsym"))
214 [(eq_attr "type" "ist,fst")])
216 ; Stores, shifts, multiplies can only issue to E0
217 (define_function_unit "ev5_e0" 1 0
218 (and (eq_attr "cpu" "ev5")
219 (eq_attr "type" "ist,fst,shift,imul"))
222 ; Motion video insns also issue only to E0, and take two ticks.
223 (define_function_unit "ev5_e0" 1 0
224 (and (eq_attr "cpu" "ev5")
225 (eq_attr "type" "mvi"))
228 ; Conditional moves always take 2 ticks.
229 (define_function_unit "ev5_ebox" 2 0
230 (and (eq_attr "cpu" "ev5")
231 (eq_attr "type" "icmov"))
234 ; Branches can only issue to E1
235 (define_function_unit "ev5_e1" 1 0
236 (and (eq_attr "cpu" "ev5")
237 (eq_attr "type" "ibr,jsr"))
240 ; Multiplies also use the integer multiplier.
241 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
242 ; cycles before an integer multiplication completes."
243 (define_function_unit "imul" 1 0
244 (and (eq_attr "cpu" "ev5")
245 (and (eq_attr "type" "imul")
246 (eq_attr "opsize" "si")))
249 (define_function_unit "imul" 1 0
250 (and (eq_attr "cpu" "ev5")
251 (and (eq_attr "type" "imul")
252 (eq_attr "opsize" "di")))
255 (define_function_unit "imul" 1 0
256 (and (eq_attr "cpu" "ev5")
257 (and (eq_attr "type" "imul")
258 (eq_attr "opsize" "udi")))
261 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
262 ;; on either so we have to play the game again.
264 (define_function_unit "ev5_fbox" 2 0
265 (and (eq_attr "cpu" "ev5")
266 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
269 (define_function_unit "ev5_fm" 1 0
270 (and (eq_attr "cpu" "ev5")
271 (eq_attr "type" "fmul"))
274 ; Add and cmov as you would expect; fbr never produces a result;
275 ; fdiv issues through fa to the divider,
276 (define_function_unit "ev5_fa" 1 0
277 (and (eq_attr "cpu" "ev5")
278 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
281 ; ??? How to: "No instruction can be issued to pipe FA exactly five
282 ; cycles before a floating point divide completes."
283 (define_function_unit "fdiv" 1 0
284 (and (eq_attr "cpu" "ev5")
285 (and (eq_attr "type" "fdiv")
286 (eq_attr "opsize" "si")))
287 15 15) ; 15 to 31 data dependant
289 (define_function_unit "fdiv" 1 0
290 (and (eq_attr "cpu" "ev5")
291 (and (eq_attr "type" "fdiv")
292 (eq_attr "opsize" "di")))
293 22 22) ; 22 to 60 data dependant
295 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
297 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
298 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
300 ;; Conditional moves decompose into two independant primitives, each
301 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
303 (define_function_unit "ev6_ebox" 4 0
304 (and (eq_attr "cpu" "ev6")
305 (eq_attr "type" "icmov"))
308 (define_function_unit "ev6_ebox" 4 0
309 (and (eq_attr "cpu" "ev6")
310 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
313 ;; Integer loads take at least 3 clocks, and only issue to lower units.
314 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
315 (define_function_unit "ev6_l" 2 0
316 (and (eq_attr "cpu" "ev6")
317 (eq_attr "type" "ild,ldsym,ist,fst"))
320 ;; FP loads take at least 4 clocks. Return two from here...
321 (define_function_unit "ev6_l" 2 0
322 (and (eq_attr "cpu" "ev6")
323 (eq_attr "type" "fld"))
326 ;; Motion video insns also issue only to U0, and take three ticks.
327 (define_function_unit "ev6_u0" 1 0
328 (and (eq_attr "cpu" "ev6")
329 (eq_attr "type" "mvi"))
332 (define_function_unit "ev6_u" 2 0
333 (and (eq_attr "cpu" "ev6")
334 (eq_attr "type" "mvi"))
337 ;; Shifts issue to either upper pipe.
338 (define_function_unit "ev6_u" 2 0
339 (and (eq_attr "cpu" "ev6")
340 (eq_attr "type" "shift"))
343 ;; Multiplies issue only to U1, and all take 7 ticks.
344 ;; Rather than create a new function unit just for U1, reuse IMUL
345 (define_function_unit "imul" 1 0
346 (and (eq_attr "cpu" "ev6")
347 (eq_attr "type" "imul"))
350 (define_function_unit "ev6_u" 2 0
351 (and (eq_attr "cpu" "ev6")
352 (eq_attr "type" "imul"))
355 ;; Branches issue to either upper pipe
356 (define_function_unit "ev6_u" 2 0
357 (and (eq_attr "cpu" "ev6")
358 (eq_attr "type" "ibr"))
361 ;; Calls only issue to L0.
362 (define_function_unit "ev6_l0" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (eq_attr "type" "jsr"))
367 (define_function_unit "ev6_l" 2 0
368 (and (eq_attr "cpu" "ev6")
369 (eq_attr "type" "jsr"))
372 ;; Ftoi/itof only issue to lower pipes
373 (define_function_unit "ev6_l" 2 0
374 (and (eq_attr "cpu" "ev6")
375 (eq_attr "type" "ftoi"))
378 (define_function_unit "ev6_l" 2 0
379 (and (eq_attr "cpu" "ev6")
380 (eq_attr "type" "itof"))
383 ;; For the FPU we are very similar to EV5, except there's no insn that
384 ;; can issue to fm & fa, so we get to leave that out.
386 (define_function_unit "ev6_fm" 1 0
387 (and (eq_attr "cpu" "ev6")
388 (eq_attr "type" "fmul"))
391 (define_function_unit "ev6_fa" 1 0
392 (and (eq_attr "cpu" "ev6")
393 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
396 (define_function_unit "ev6_fa" 1 0
397 (and (eq_attr "cpu" "ev6")
398 (eq_attr "type" "fcmov"))
401 (define_function_unit "fdiv" 1 0
402 (and (eq_attr "cpu" "ev6")
403 (and (eq_attr "type" "fdiv")
404 (eq_attr "opsize" "si")))
407 (define_function_unit "fdiv" 1 0
408 (and (eq_attr "cpu" "ev6")
409 (and (eq_attr "type" "fdiv")
410 (eq_attr "opsize" "di")))
413 (define_function_unit "fsqrt" 1 0
414 (and (eq_attr "cpu" "ev6")
415 (and (eq_attr "type" "fsqrt")
416 (eq_attr "opsize" "si")))
419 (define_function_unit "fsqrt" 1 0
420 (and (eq_attr "cpu" "ev6")
421 (and (eq_attr "type" "fsqrt")
422 (eq_attr "opsize" "di")))
425 ; ??? The FPU communicates with memory and the integer register file
426 ; via two fp store units. We need a slot in the fst immediately, and
427 ; a slot in LOW after the operand data is ready. At which point the
428 ; data may be moved either to the store queue or the integer register
429 ; file and the insn retired.
432 ;; First define the arithmetic insns. Note that the 32-bit forms also
435 ;; Handle 32-64 bit extension from memory to a floating point register
436 ;; specially, since this ocurrs frequently in int->double conversions.
438 ;; Note that while we must retain the =f case in the insn for reload's
439 ;; benefit, it should be eliminated after reload, so we should never emit
440 ;; code for that case. But we don't reject the possibility.
442 (define_expand "extendsidi2"
443 [(set (match_operand:DI 0 "register_operand" "")
444 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
448 (define_insn "*extendsidi2_nofix"
449 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
451 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
457 lds %0,%1\;cvtlq %0,%0"
458 [(set_attr "type" "iadd,ild,fadd,fld")
459 (set_attr "length" "*,*,*,8")])
461 (define_insn "*extendsidi2_fix"
462 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
464 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
471 lds %0,%1\;cvtlq %0,%0"
472 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
473 (set_attr "length" "*,*,*,*,8")])
475 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
477 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
478 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
480 [(set (match_dup 2) (match_dup 1))
481 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
482 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
484 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
485 ;; reload when converting fp->int.
488 [(set (match_operand:SI 0 "hard_int_register_operand" "")
489 (match_operand:SI 1 "memory_operand" ""))
490 (set (match_operand:DI 2 "hard_int_register_operand" "")
491 (sign_extend:DI (match_dup 0)))]
492 "true_regnum (operands[0]) == true_regnum (operands[2])
493 || peep2_reg_dead_p (2, operands[0])"
495 (sign_extend:DI (match_dup 1)))]
499 [(set (match_operand:SI 0 "hard_int_register_operand" "")
500 (match_operand:SI 1 "hard_fp_register_operand" ""))
501 (set (match_operand:DI 2 "hard_int_register_operand" "")
502 (sign_extend:DI (match_dup 0)))]
504 && (true_regnum (operands[0]) == true_regnum (operands[2])
505 || peep2_reg_dead_p (2, operands[0]))"
507 (sign_extend:DI (match_dup 1)))]
511 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
512 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
513 (set (match_operand:DI 2 "hard_int_register_operand" "")
515 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
517 (sign_extend:DI (match_dup 1)))]
520 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
521 ;; generates better code. We have the anonymous addsi3 pattern below in
522 ;; case combine wants to make it.
523 (define_expand "addsi3"
524 [(set (match_operand:SI 0 "register_operand" "")
525 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
526 (match_operand:SI 2 "add_operand" "")))]
531 rtx op1 = gen_lowpart (DImode, operands[1]);
532 rtx op2 = gen_lowpart (DImode, operands[2]);
534 if (! cse_not_expected)
536 rtx tmp = gen_reg_rtx (DImode);
537 emit_insn (gen_adddi3 (tmp, op1, op2));
538 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
541 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
546 (define_insn "*addsi_internal"
547 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
548 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
549 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
558 [(set (match_operand:SI 0 "register_operand" "")
559 (plus:SI (match_operand:SI 1 "register_operand" "")
560 (match_operand:SI 2 "const_int_operand" "")))]
561 "! add_operand (operands[2], SImode)"
562 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
563 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
565 HOST_WIDE_INT val = INTVAL (operands[2]);
566 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
567 HOST_WIDE_INT rest = val - low;
569 operands[3] = GEN_INT (rest);
570 operands[4] = GEN_INT (low);
573 (define_insn "*addsi_se"
574 [(set (match_operand:DI 0 "register_operand" "=r,r")
576 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
577 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
584 [(set (match_operand:DI 0 "register_operand" "")
586 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
587 (match_operand:SI 2 "const_int_operand" ""))))
588 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
589 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
590 && INTVAL (operands[2]) % 4 == 0"
591 [(set (match_dup 3) (match_dup 4))
592 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
596 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
602 operands[4] = GEN_INT (val);
603 operands[5] = GEN_INT (mult);
607 [(set (match_operand:DI 0 "register_operand" "")
609 (plus:SI (match_operator:SI 1 "comparison_operator"
610 [(match_operand 2 "" "")
611 (match_operand 3 "" "")])
612 (match_operand:SI 4 "add_operand" ""))))
613 (clobber (match_operand:DI 5 "register_operand" ""))]
615 [(set (match_dup 5) (match_dup 6))
616 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
618 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
619 operands[2], operands[3]);
620 operands[7] = gen_lowpart (SImode, operands[5]);
623 (define_insn "addvsi3"
624 [(set (match_operand:SI 0 "register_operand" "=r,r")
625 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
626 (match_operand:SI 2 "sext_add_operand" "rI,O")))
627 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
628 (sign_extend:DI (match_dup 2)))
629 (sign_extend:DI (plus:SI (match_dup 1)
637 (define_expand "adddi3"
638 [(set (match_operand:DI 0 "register_operand" "")
639 (plus:DI (match_operand:DI 1 "register_operand" "")
640 (match_operand:DI 2 "add_operand" "")))]
644 (define_insn "*adddi_er_high_l"
645 [(set (match_operand:DI 0 "register_operand" "=r")
646 (plus:DI (match_operand:DI 1 "register_operand" "r")
647 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
648 "TARGET_EXPLICIT_RELOCS"
649 "ldah %0,%2(%1)\t\t!gprelhigh")
651 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
652 ;; With complications like
654 ;; The NT stack unwind code can't handle a subq to adjust the stack
655 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
656 ;; the exception handling code will loop if a subq is used and an
659 ;; The 19980616 change to emit prologues as RTL also confused some
660 ;; versions of GDB, which also interprets prologues. This has been
661 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
664 ;; and the fact that the three insns schedule exactly the same, it's
665 ;; just not worth the effort.
667 (define_insn "*adddi_internal"
668 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
669 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
670 (match_operand:DI 2 "add_operand" "r,K,L")))]
677 ;; ??? Allow large constants when basing off the frame pointer or some
678 ;; virtual register that may eliminate to the frame pointer. This is
679 ;; done because register elimination offsets will change the hi/lo split,
680 ;; and if we split before reload, we will require additional instructions.
682 (define_insn "*adddi_fp_hack"
683 [(set (match_operand:DI 0 "register_operand" "=r")
684 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
685 (match_operand:DI 2 "const_int_operand" "n")))]
686 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
687 && INTVAL (operands[2]) >= 0
688 /* This is the largest constant an lda+ldah pair can add, minus
689 an upper bound on the displacement between SP and AP during
690 register elimination. See INITIAL_ELIMINATION_OFFSET. */
691 && INTVAL (operands[2])
693 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
694 - ALPHA_ROUND(current_function_outgoing_args_size)
695 - (ALPHA_ROUND (get_frame_size ()
696 + max_reg_num () * UNITS_PER_WORD
697 + current_function_pretend_args_size)
698 - current_function_pretend_args_size))"
701 ;; Don't do this if we are adjusting SP since we don't want to do it
702 ;; in two steps. Don't split FP sources for the reason listed above.
704 [(set (match_operand:DI 0 "register_operand" "")
705 (plus:DI (match_operand:DI 1 "register_operand" "")
706 (match_operand:DI 2 "const_int_operand" "")))]
707 "! add_operand (operands[2], DImode)
708 && operands[0] != stack_pointer_rtx
709 && operands[1] != frame_pointer_rtx
710 && operands[1] != arg_pointer_rtx"
711 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
712 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
714 HOST_WIDE_INT val = INTVAL (operands[2]);
715 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
716 HOST_WIDE_INT rest = val - low;
718 operands[4] = GEN_INT (low);
719 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
720 operands[3] = GEN_INT (rest);
721 else if (! no_new_pseudos)
723 operands[3] = gen_reg_rtx (DImode);
724 emit_move_insn (operands[3], operands[2]);
725 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
732 (define_insn "*saddl"
733 [(set (match_operand:SI 0 "register_operand" "=r,r")
734 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
735 (match_operand:SI 2 "const48_operand" "I,I"))
736 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
742 (define_insn "*saddl_se"
743 [(set (match_operand:DI 0 "register_operand" "=r,r")
745 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
746 (match_operand:SI 2 "const48_operand" "I,I"))
747 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
754 [(set (match_operand:DI 0 "register_operand" "")
756 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
757 [(match_operand 2 "" "")
758 (match_operand 3 "" "")])
759 (match_operand:SI 4 "const48_operand" ""))
760 (match_operand:SI 5 "sext_add_operand" ""))))
761 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
763 [(set (match_dup 6) (match_dup 7))
765 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
768 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
769 operands[2], operands[3]);
770 operands[8] = gen_lowpart (SImode, operands[6]);
773 (define_insn "*saddq"
774 [(set (match_operand:DI 0 "register_operand" "=r,r")
775 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
776 (match_operand:DI 2 "const48_operand" "I,I"))
777 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
783 (define_insn "addvdi3"
784 [(set (match_operand:DI 0 "register_operand" "=r,r")
785 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
786 (match_operand:DI 2 "sext_add_operand" "rI,O")))
787 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
788 (sign_extend:TI (match_dup 2)))
789 (sign_extend:TI (plus:DI (match_dup 1)
797 (define_insn "negsi2"
798 [(set (match_operand:SI 0 "register_operand" "=r")
799 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
803 (define_insn "*negsi_se"
804 [(set (match_operand:DI 0 "register_operand" "=r")
805 (sign_extend:DI (neg:SI
806 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
810 (define_insn "negvsi2"
811 [(set (match_operand:SI 0 "register_operand" "=r")
812 (neg:SI (match_operand:SI 1 "register_operand" "r")))
813 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
814 (sign_extend:DI (neg:SI (match_dup 1))))
819 (define_insn "negdi2"
820 [(set (match_operand:DI 0 "register_operand" "=r")
821 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
825 (define_insn "negvdi2"
826 [(set (match_operand:DI 0 "register_operand" "=r")
827 (neg:DI (match_operand:DI 1 "register_operand" "r")))
828 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
829 (sign_extend:TI (neg:DI (match_dup 1))))
834 (define_expand "subsi3"
835 [(set (match_operand:SI 0 "register_operand" "")
836 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
837 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
842 rtx op1 = gen_lowpart (DImode, operands[1]);
843 rtx op2 = gen_lowpart (DImode, operands[2]);
845 if (! cse_not_expected)
847 rtx tmp = gen_reg_rtx (DImode);
848 emit_insn (gen_subdi3 (tmp, op1, op2));
849 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
852 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
857 (define_insn "*subsi_internal"
858 [(set (match_operand:SI 0 "register_operand" "=r")
859 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
860 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
864 (define_insn "*subsi_se"
865 [(set (match_operand:DI 0 "register_operand" "=r")
866 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
867 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
871 (define_insn "subvsi3"
872 [(set (match_operand:SI 0 "register_operand" "=r")
873 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
874 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
875 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
876 (sign_extend:DI (match_dup 2)))
877 (sign_extend:DI (minus:SI (match_dup 1)
883 (define_insn "subdi3"
884 [(set (match_operand:DI 0 "register_operand" "=r")
885 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
886 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
890 (define_insn "*ssubl"
891 [(set (match_operand:SI 0 "register_operand" "=r")
892 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
893 (match_operand:SI 2 "const48_operand" "I"))
894 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
898 (define_insn "*ssubl_se"
899 [(set (match_operand:DI 0 "register_operand" "=r")
901 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
902 (match_operand:SI 2 "const48_operand" "I"))
903 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
907 (define_insn "*ssubq"
908 [(set (match_operand:DI 0 "register_operand" "=r")
909 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
910 (match_operand:DI 2 "const48_operand" "I"))
911 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
915 (define_insn "subvdi3"
916 [(set (match_operand:DI 0 "register_operand" "=r")
917 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
918 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
919 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
920 (sign_extend:TI (match_dup 2)))
921 (sign_extend:TI (minus:DI (match_dup 1)
927 ;; The Unicos/Mk assembler doesn't support mull.
929 (define_insn "mulsi3"
930 [(set (match_operand:SI 0 "register_operand" "=r")
931 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
932 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
933 "!TARGET_ABI_UNICOSMK"
935 [(set_attr "type" "imul")
936 (set_attr "opsize" "si")])
938 (define_insn "*mulsi_se"
939 [(set (match_operand:DI 0 "register_operand" "=r")
941 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
942 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
943 "!TARGET_ABI_UNICOSMK"
945 [(set_attr "type" "imul")
946 (set_attr "opsize" "si")])
948 (define_insn "mulvsi3"
949 [(set (match_operand:SI 0 "register_operand" "=r")
950 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
951 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
952 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
953 (sign_extend:DI (match_dup 2)))
954 (sign_extend:DI (mult:SI (match_dup 1)
957 "!TARGET_ABI_UNICOSMK"
959 [(set_attr "type" "imul")
960 (set_attr "opsize" "si")])
962 (define_insn "muldi3"
963 [(set (match_operand:DI 0 "register_operand" "=r")
964 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
965 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
968 [(set_attr "type" "imul")])
970 (define_insn "mulvdi3"
971 [(set (match_operand:DI 0 "register_operand" "=r")
972 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
973 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
974 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
975 (sign_extend:TI (match_dup 2)))
976 (sign_extend:TI (mult:DI (match_dup 1)
981 [(set_attr "type" "imul")])
983 (define_insn "umuldi3_highpart"
984 [(set (match_operand:DI 0 "register_operand" "=r")
987 (mult:TI (zero_extend:TI
988 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
990 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
994 [(set_attr "type" "imul")
995 (set_attr "opsize" "udi")])
997 (define_insn "*umuldi3_highpart_const"
998 [(set (match_operand:DI 0 "register_operand" "=r")
1001 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
1002 (match_operand:TI 2 "cint8_operand" "I"))
1006 [(set_attr "type" "imul")
1007 (set_attr "opsize" "udi")])
1009 ;; The divide and remainder operations take their inputs from r24 and
1010 ;; r25, put their output in r27, and clobber r23 and r28 on all
1011 ;; systems except Unicos/Mk. On Unicos, the standard library provides
1012 ;; subroutines which use the standard calling convention and work on
1015 ;; ??? Force sign-extension here because some versions of OSF/1 and
1016 ;; Interix/NT don't do the right thing if the inputs are not properly
1017 ;; sign-extended. But Linux, for instance, does not have this
1018 ;; problem. Is it worth the complication here to eliminate the sign
1021 (define_expand "divsi3"
1023 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1025 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1026 (parallel [(set (reg:DI 27)
1027 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
1028 (clobber (reg:DI 23))
1029 (clobber (reg:DI 28))])
1030 (set (match_operand:SI 0 "nonimmediate_operand" "")
1031 (subreg:SI (reg:DI 27) 0))]
1032 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1035 (define_expand "udivsi3"
1037 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1039 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1040 (parallel [(set (reg:DI 27)
1041 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
1042 (clobber (reg:DI 23))
1043 (clobber (reg:DI 28))])
1044 (set (match_operand:SI 0 "nonimmediate_operand" "")
1045 (subreg:SI (reg:DI 27) 0))]
1046 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1049 (define_expand "modsi3"
1051 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1053 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1054 (parallel [(set (reg:DI 27)
1055 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
1056 (clobber (reg:DI 23))
1057 (clobber (reg:DI 28))])
1058 (set (match_operand:SI 0 "nonimmediate_operand" "")
1059 (subreg:SI (reg:DI 27) 0))]
1060 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1063 (define_expand "umodsi3"
1065 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1067 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1068 (parallel [(set (reg:DI 27)
1069 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
1070 (clobber (reg:DI 23))
1071 (clobber (reg:DI 28))])
1072 (set (match_operand:SI 0 "nonimmediate_operand" "")
1073 (subreg:SI (reg:DI 27) 0))]
1074 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1077 (define_expand "divdi3"
1078 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1079 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1080 (parallel [(set (reg:DI 27)
1083 (clobber (reg:DI 23))
1084 (clobber (reg:DI 28))])
1085 (set (match_operand:DI 0 "nonimmediate_operand" "")
1087 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1090 (define_expand "udivdi3"
1091 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1092 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1093 (parallel [(set (reg:DI 27)
1094 (udiv:DI (reg:DI 24)
1096 (clobber (reg:DI 23))
1097 (clobber (reg:DI 28))])
1098 (set (match_operand:DI 0 "nonimmediate_operand" "")
1100 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1103 (define_expand "moddi3"
1104 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1105 (use (match_operand:DI 1 "input_operand" ""))
1106 (use (match_operand:DI 2 "input_operand" ""))]
1107 "!TARGET_ABI_OPEN_VMS"
1109 if (TARGET_ABI_UNICOSMK)
1110 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
1112 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
1116 (define_expand "moddi3_dft"
1117 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1118 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1119 (parallel [(set (reg:DI 27)
1122 (clobber (reg:DI 23))
1123 (clobber (reg:DI 28))])
1124 (set (match_operand:DI 0 "nonimmediate_operand" "")
1126 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1129 ;; On Unicos/Mk, we do as the system's C compiler does:
1130 ;; compute the quotient, multiply and subtract.
1132 (define_expand "moddi3_umk"
1133 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1134 (use (match_operand:DI 1 "input_operand" ""))
1135 (use (match_operand:DI 2 "input_operand" ""))]
1136 "TARGET_ABI_UNICOSMK"
1140 mul = gen_reg_rtx (DImode);
1141 tmp = gen_reg_rtx (DImode);
1142 operands[1] = force_reg (DImode, operands[1]);
1143 operands[2] = force_reg (DImode, operands[2]);
1145 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
1146 NULL_RTX, 0, OPTAB_LIB);
1147 div = force_reg (DImode, div);
1148 emit_insn (gen_muldi3 (mul, operands[2], div));
1149 emit_insn (gen_subdi3 (tmp, operands[1], mul));
1150 emit_move_insn (operands[0], tmp);
1154 (define_expand "umoddi3"
1155 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1156 (use (match_operand:DI 1 "input_operand" ""))
1157 (use (match_operand:DI 2 "input_operand" ""))]
1158 "! TARGET_ABI_OPEN_VMS"
1160 if (TARGET_ABI_UNICOSMK)
1161 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
1163 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
1167 (define_expand "umoddi3_dft"
1168 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1169 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1170 (parallel [(set (reg:DI 27)
1171 (umod:DI (reg:DI 24)
1173 (clobber (reg:DI 23))
1174 (clobber (reg:DI 28))])
1175 (set (match_operand:DI 0 "nonimmediate_operand" "")
1177 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1180 (define_expand "umoddi3_umk"
1181 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1182 (use (match_operand:DI 1 "input_operand" ""))
1183 (use (match_operand:DI 2 "input_operand" ""))]
1184 "TARGET_ABI_UNICOSMK"
1188 mul = gen_reg_rtx (DImode);
1189 tmp = gen_reg_rtx (DImode);
1190 operands[1] = force_reg (DImode, operands[1]);
1191 operands[2] = force_reg (DImode, operands[2]);
1193 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
1194 NULL_RTX, 1, OPTAB_LIB);
1195 div = force_reg (DImode, div);
1196 emit_insn (gen_muldi3 (mul, operands[2], div));
1197 emit_insn (gen_subdi3 (tmp, operands[1], mul));
1198 emit_move_insn (operands[0], tmp);
1202 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1203 ;; expanded by the assembler.
1205 (define_insn "*divmodsi_internal_er"
1207 (sign_extend:DI (match_operator:SI 0 "divmod_operator"
1208 [(reg:DI 24) (reg:DI 25)])))
1209 (clobber (reg:DI 23))
1210 (clobber (reg:DI 28))]
1211 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1212 "ldq $27,__%E0($29)\t\t!literal!%#\;jsr $23,($27),__%E0\t\t!lituse_jsr!%#"
1213 [(set_attr "type" "jsr")
1214 (set_attr "length" "8")])
1216 (define_insn "*divmodsi_internal"
1218 (sign_extend:DI (match_operator:SI 0 "divmod_operator"
1219 [(reg:DI 24) (reg:DI 25)])))
1220 (clobber (reg:DI 23))
1221 (clobber (reg:DI 28))]
1222 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1224 [(set_attr "type" "jsr")
1225 (set_attr "length" "8")])
1227 (define_insn "*divmoddi_internal_er"
1229 (match_operator:DI 0 "divmod_operator"
1230 [(reg:DI 24) (reg:DI 25)]))
1231 (clobber (reg:DI 23))
1232 (clobber (reg:DI 28))]
1233 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1234 "ldq $27,__%E0($29)\t\t!literal!%#\;jsr $23,($27),__%E0\t\t!lituse_jsr!%#"
1235 [(set_attr "type" "jsr")
1236 (set_attr "length" "8")])
1238 (define_insn "*divmoddi_internal"
1240 (match_operator:DI 0 "divmod_operator"
1241 [(reg:DI 24) (reg:DI 25)]))
1242 (clobber (reg:DI 23))
1243 (clobber (reg:DI 28))]
1244 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1246 [(set_attr "type" "jsr")
1247 (set_attr "length" "8")])
1249 ;; Next are the basic logical operations. These only exist in DImode.
1251 (define_insn "anddi3"
1252 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1253 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1254 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1260 [(set_attr "type" "ilog,ilog,shift")])
1262 ;; There are times when we can split an AND into two AND insns. This occurs
1263 ;; when we can first clear any bytes and then clear anything else. For
1264 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1265 ;; Only do this when running on 64-bit host since the computations are
1266 ;; too messy otherwise.
1269 [(set (match_operand:DI 0 "register_operand" "")
1270 (and:DI (match_operand:DI 1 "register_operand" "")
1271 (match_operand:DI 2 "const_int_operand" "")))]
1272 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1273 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1274 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1276 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1277 unsigned HOST_WIDE_INT mask2 = mask1;
1280 /* For each byte that isn't all zeros, make it all ones. */
1281 for (i = 0; i < 64; i += 8)
1282 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1283 mask1 |= (HOST_WIDE_INT) 0xff << i;
1285 /* Now turn on any bits we've just turned off. */
1288 operands[3] = GEN_INT (mask1);
1289 operands[4] = GEN_INT (mask2);
1292 (define_expand "zero_extendqihi2"
1293 [(set (match_operand:HI 0 "register_operand" "")
1294 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1298 operands[1] = force_reg (QImode, operands[1]);
1301 (define_insn "*zero_extendqihi2_bwx"
1302 [(set (match_operand:HI 0 "register_operand" "=r,r")
1303 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1308 [(set_attr "type" "ilog,ild")])
1310 (define_insn "*zero_extendqihi2_nobwx"
1311 [(set (match_operand:HI 0 "register_operand" "=r")
1312 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1315 [(set_attr "type" "ilog")])
1317 (define_expand "zero_extendqisi2"
1318 [(set (match_operand:SI 0 "register_operand" "")
1319 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1323 operands[1] = force_reg (QImode, operands[1]);
1326 (define_insn "*zero_extendqisi2_bwx"
1327 [(set (match_operand:SI 0 "register_operand" "=r,r")
1328 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1333 [(set_attr "type" "ilog,ild")])
1335 (define_insn "*zero_extendqisi2_nobwx"
1336 [(set (match_operand:SI 0 "register_operand" "=r")
1337 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1340 [(set_attr "type" "ilog")])
1342 (define_expand "zero_extendqidi2"
1343 [(set (match_operand:DI 0 "register_operand" "")
1344 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1348 operands[1] = force_reg (QImode, operands[1]);
1351 (define_insn "*zero_extendqidi2_bwx"
1352 [(set (match_operand:DI 0 "register_operand" "=r,r")
1353 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1358 [(set_attr "type" "ilog,ild")])
1360 (define_insn "*zero_extendqidi2_nobwx"
1361 [(set (match_operand:DI 0 "register_operand" "=r")
1362 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1365 [(set_attr "type" "ilog")])
1367 (define_expand "zero_extendhisi2"
1368 [(set (match_operand:SI 0 "register_operand" "")
1369 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1373 operands[1] = force_reg (HImode, operands[1]);
1376 (define_insn "*zero_extendhisi2_bwx"
1377 [(set (match_operand:SI 0 "register_operand" "=r,r")
1378 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1383 [(set_attr "type" "shift,ild")])
1385 (define_insn "*zero_extendhisi2_nobwx"
1386 [(set (match_operand:SI 0 "register_operand" "=r")
1387 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1390 [(set_attr "type" "shift")])
1392 (define_expand "zero_extendhidi2"
1393 [(set (match_operand:DI 0 "register_operand" "")
1394 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1398 operands[1] = force_reg (HImode, operands[1]);
1401 (define_insn "*zero_extendhidi2_bwx"
1402 [(set (match_operand:DI 0 "register_operand" "=r,r")
1403 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1408 [(set_attr "type" "shift,ild")])
1410 (define_insn "*zero_extendhidi2_nobwx"
1411 [(set (match_operand:DI 0 "register_operand" "=r")
1412 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1415 [(set_attr "type" "shift")])
1417 (define_insn "zero_extendsidi2"
1418 [(set (match_operand:DI 0 "register_operand" "=r")
1419 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1422 [(set_attr "type" "shift")])
1424 (define_insn "andnotdi3"
1425 [(set (match_operand:DI 0 "register_operand" "=r")
1426 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1427 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1430 [(set_attr "type" "ilog")])
1432 (define_insn "iordi3"
1433 [(set (match_operand:DI 0 "register_operand" "=r,r")
1434 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1435 (match_operand:DI 2 "or_operand" "rI,N")))]
1440 [(set_attr "type" "ilog")])
1442 (define_insn "one_cmpldi2"
1443 [(set (match_operand:DI 0 "register_operand" "=r")
1444 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1447 [(set_attr "type" "ilog")])
1449 (define_insn "*iornot"
1450 [(set (match_operand:DI 0 "register_operand" "=r")
1451 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1452 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1455 [(set_attr "type" "ilog")])
1457 (define_insn "xordi3"
1458 [(set (match_operand:DI 0 "register_operand" "=r,r")
1459 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1460 (match_operand:DI 2 "or_operand" "rI,N")))]
1465 [(set_attr "type" "ilog")])
1467 (define_insn "*xornot"
1468 [(set (match_operand:DI 0 "register_operand" "=r")
1469 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1470 (match_operand:DI 2 "register_operand" "rI"))))]
1473 [(set_attr "type" "ilog")])
1475 ;; Handle the FFS insn iff we support CIX.
1477 (define_expand "ffsdi2"
1479 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1481 (plus:DI (match_dup 2) (const_int 1)))
1482 (set (match_operand:DI 0 "register_operand" "")
1483 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1484 (const_int 0) (match_dup 3)))]
1487 operands[2] = gen_reg_rtx (DImode);
1488 operands[3] = gen_reg_rtx (DImode);
1491 (define_insn "*cttz"
1492 [(set (match_operand:DI 0 "register_operand" "=r")
1493 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1496 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1497 ; reuse the existing type name.
1498 [(set_attr "type" "mvi")])
1500 ;; Next come the shifts and the various extract and insert operations.
1502 (define_insn "ashldi3"
1503 [(set (match_operand:DI 0 "register_operand" "=r,r")
1504 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1505 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1508 switch (which_alternative)
1511 if (operands[2] == const1_rtx)
1512 return "addq %r1,%r1,%0";
1514 return "s%P2addq %r1,0,%0";
1516 return "sll %r1,%2,%0";
1521 [(set_attr "type" "iadd,shift")])
1523 ;; ??? The following pattern is made by combine, but earlier phases
1524 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1525 ;; with this in a better way at some point.
1527 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1529 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1530 ;; (match_operand:DI 2 "const_int_operand" "P"))
1532 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1534 ;; if (operands[2] == const1_rtx)
1535 ;; return "addl %r1,%r1,%0";
1537 ;; return "s%P2addl %r1,0,%0";
1539 ;; [(set_attr "type" "iadd")])
1541 (define_insn "lshrdi3"
1542 [(set (match_operand:DI 0 "register_operand" "=r")
1543 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1544 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1547 [(set_attr "type" "shift")])
1549 (define_insn "ashrdi3"
1550 [(set (match_operand:DI 0 "register_operand" "=r")
1551 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1552 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1555 [(set_attr "type" "shift")])
1557 (define_expand "extendqihi2"
1559 (ashift:DI (match_operand:QI 1 "some_operand" "")
1561 (set (match_operand:HI 0 "register_operand" "")
1562 (ashiftrt:DI (match_dup 2)
1568 emit_insn (gen_extendqihi2x (operands[0],
1569 force_reg (QImode, operands[1])));
1573 /* If we have an unaligned MEM, extend to DImode (which we do
1574 specially) and then copy to the result. */
1575 if (unaligned_memory_operand (operands[1], HImode))
1577 rtx temp = gen_reg_rtx (DImode);
1579 emit_insn (gen_extendqidi2 (temp, operands[1]));
1580 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1584 operands[0] = gen_lowpart (DImode, operands[0]);
1585 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1586 operands[2] = gen_reg_rtx (DImode);
1589 (define_insn "extendqidi2x"
1590 [(set (match_operand:DI 0 "register_operand" "=r")
1591 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1594 [(set_attr "type" "shift")])
1596 (define_insn "extendhidi2x"
1597 [(set (match_operand:DI 0 "register_operand" "=r")
1598 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1601 [(set_attr "type" "shift")])
1603 (define_insn "extendqisi2x"
1604 [(set (match_operand:SI 0 "register_operand" "=r")
1605 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1608 [(set_attr "type" "shift")])
1610 (define_insn "extendhisi2x"
1611 [(set (match_operand:SI 0 "register_operand" "=r")
1612 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1615 [(set_attr "type" "shift")])
1617 (define_insn "extendqihi2x"
1618 [(set (match_operand:HI 0 "register_operand" "=r")
1619 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1622 [(set_attr "type" "shift")])
1624 (define_expand "extendqisi2"
1626 (ashift:DI (match_operand:QI 1 "some_operand" "")
1628 (set (match_operand:SI 0 "register_operand" "")
1629 (ashiftrt:DI (match_dup 2)
1635 emit_insn (gen_extendqisi2x (operands[0],
1636 force_reg (QImode, operands[1])));
1640 /* If we have an unaligned MEM, extend to a DImode form of
1641 the result (which we do specially). */
1642 if (unaligned_memory_operand (operands[1], QImode))
1644 rtx temp = gen_reg_rtx (DImode);
1646 emit_insn (gen_extendqidi2 (temp, operands[1]));
1647 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1651 operands[0] = gen_lowpart (DImode, operands[0]);
1652 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1653 operands[2] = gen_reg_rtx (DImode);
1656 (define_expand "extendqidi2"
1658 (ashift:DI (match_operand:QI 1 "some_operand" "")
1660 (set (match_operand:DI 0 "register_operand" "")
1661 (ashiftrt:DI (match_dup 2)
1667 emit_insn (gen_extendqidi2x (operands[0],
1668 force_reg (QImode, operands[1])));
1672 if (unaligned_memory_operand (operands[1], QImode))
1675 = gen_unaligned_extendqidi (operands[0],
1676 get_unaligned_address (operands[1], 1));
1678 alpha_set_memflags (seq, operands[1]);
1683 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1684 operands[2] = gen_reg_rtx (DImode);
1687 (define_expand "extendhisi2"
1689 (ashift:DI (match_operand:HI 1 "some_operand" "")
1691 (set (match_operand:SI 0 "register_operand" "")
1692 (ashiftrt:DI (match_dup 2)
1698 emit_insn (gen_extendhisi2x (operands[0],
1699 force_reg (HImode, operands[1])));
1703 /* If we have an unaligned MEM, extend to a DImode form of
1704 the result (which we do specially). */
1705 if (unaligned_memory_operand (operands[1], HImode))
1707 rtx temp = gen_reg_rtx (DImode);
1709 emit_insn (gen_extendhidi2 (temp, operands[1]));
1710 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1714 operands[0] = gen_lowpart (DImode, operands[0]);
1715 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1716 operands[2] = gen_reg_rtx (DImode);
1719 (define_expand "extendhidi2"
1721 (ashift:DI (match_operand:HI 1 "some_operand" "")
1723 (set (match_operand:DI 0 "register_operand" "")
1724 (ashiftrt:DI (match_dup 2)
1730 emit_insn (gen_extendhidi2x (operands[0],
1731 force_reg (HImode, operands[1])));
1735 if (unaligned_memory_operand (operands[1], HImode))
1738 = gen_unaligned_extendhidi (operands[0],
1739 get_unaligned_address (operands[1], 2));
1741 alpha_set_memflags (seq, operands[1]);
1746 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1747 operands[2] = gen_reg_rtx (DImode);
1750 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1751 ;; as a pattern saves one instruction. The code is similar to that for
1752 ;; the unaligned loads (see below).
1754 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1755 (define_expand "unaligned_extendqidi"
1756 [(use (match_operand:QI 0 "register_operand" ""))
1757 (use (match_operand:DI 1 "address_operand" ""))]
1760 if (WORDS_BIG_ENDIAN)
1761 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1763 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1767 (define_expand "unaligned_extendqidi_le"
1768 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1770 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1773 (ashift:DI (match_dup 3)
1774 (minus:DI (const_int 64)
1776 (and:DI (match_dup 2) (const_int 7))
1778 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1779 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1780 "! WORDS_BIG_ENDIAN"
1782 operands[2] = gen_reg_rtx (DImode);
1783 operands[3] = gen_reg_rtx (DImode);
1784 operands[4] = gen_reg_rtx (DImode);
1787 (define_expand "unaligned_extendqidi_be"
1788 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1789 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1791 (mem:DI (and:DI (match_dup 3)
1793 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1795 (ashift:DI (match_dup 4)
1798 (plus:DI (match_dup 5) (const_int 1))
1801 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1802 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1805 operands[2] = gen_reg_rtx (DImode);
1806 operands[3] = gen_reg_rtx (DImode);
1807 operands[4] = gen_reg_rtx (DImode);
1808 operands[5] = gen_reg_rtx (DImode);
1809 operands[6] = gen_reg_rtx (DImode);
1812 (define_expand "unaligned_extendhidi"
1813 [(use (match_operand:QI 0 "register_operand" ""))
1814 (use (match_operand:DI 1 "address_operand" ""))]
1817 if (WORDS_BIG_ENDIAN)
1818 emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
1820 emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
1824 (define_expand "unaligned_extendhidi_le"
1825 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1827 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1830 (ashift:DI (match_dup 3)
1831 (minus:DI (const_int 64)
1833 (and:DI (match_dup 2) (const_int 7))
1835 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1836 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1837 "! WORDS_BIG_ENDIAN"
1839 operands[2] = gen_reg_rtx (DImode);
1840 operands[3] = gen_reg_rtx (DImode);
1841 operands[4] = gen_reg_rtx (DImode);
1844 (define_expand "unaligned_extendhidi_be"
1845 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1846 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1848 (mem:DI (and:DI (match_dup 3)
1850 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1852 (ashift:DI (match_dup 4)
1855 (plus:DI (match_dup 5) (const_int 1))
1858 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1859 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1862 operands[2] = gen_reg_rtx (DImode);
1863 operands[3] = gen_reg_rtx (DImode);
1864 operands[4] = gen_reg_rtx (DImode);
1865 operands[5] = gen_reg_rtx (DImode);
1866 operands[6] = gen_reg_rtx (DImode);
1869 (define_insn "*extxl_const"
1870 [(set (match_operand:DI 0 "register_operand" "=r")
1871 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1872 (match_operand:DI 2 "mode_width_operand" "n")
1873 (match_operand:DI 3 "mul8_operand" "I")))]
1875 "ext%M2l %r1,%s3,%0"
1876 [(set_attr "type" "shift")])
1878 (define_insn "extxl_le"
1879 [(set (match_operand:DI 0 "register_operand" "=r")
1880 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1881 (match_operand:DI 2 "mode_width_operand" "n")
1882 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1884 "! WORDS_BIG_ENDIAN"
1886 [(set_attr "type" "shift")])
1888 (define_insn "extxl_be"
1889 [(set (match_operand:DI 0 "register_operand" "=r")
1890 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1891 (match_operand:DI 2 "mode_width_operand" "n")
1895 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1899 [(set_attr "type" "shift")])
1901 ;; Combine has some strange notion of preserving existing undefined behaviour
1902 ;; in shifts larger than a word size. So capture these patterns that it
1903 ;; should have turned into zero_extracts.
1905 (define_insn "*extxl_1_le"
1906 [(set (match_operand:DI 0 "register_operand" "=r")
1907 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1908 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1910 (match_operand:DI 3 "mode_mask_operand" "n")))]
1911 "! WORDS_BIG_ENDIAN"
1913 [(set_attr "type" "shift")])
1915 (define_insn "*extxl_1_be"
1916 [(set (match_operand:DI 0 "register_operand" "=r")
1917 (and:DI (lshiftrt:DI
1918 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1919 (minus:DI (const_int 56)
1920 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1922 (match_operand:DI 3 "mode_mask_operand" "n")))]
1925 [(set_attr "type" "shift")])
1927 (define_insn "*extql_2_le"
1928 [(set (match_operand:DI 0 "register_operand" "=r")
1929 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1930 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1932 "! WORDS_BIG_ENDIAN"
1934 [(set_attr "type" "shift")])
1936 (define_insn "*extql_2_be"
1937 [(set (match_operand:DI 0 "register_operand" "=r")
1939 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1940 (minus:DI (const_int 56)
1942 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1946 [(set_attr "type" "shift")])
1948 (define_insn "extqh_le"
1949 [(set (match_operand:DI 0 "register_operand" "=r")
1951 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1952 (minus:DI (const_int 64)
1955 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1958 "! WORDS_BIG_ENDIAN"
1960 [(set_attr "type" "shift")])
1962 (define_insn "extqh_be"
1963 [(set (match_operand:DI 0 "register_operand" "=r")
1965 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1968 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1974 [(set_attr "type" "shift")])
1976 (define_insn "extlh_le"
1977 [(set (match_operand:DI 0 "register_operand" "=r")
1979 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1980 (const_int 2147483647))
1981 (minus:DI (const_int 64)
1984 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1987 "! WORDS_BIG_ENDIAN"
1989 [(set_attr "type" "shift")])
1991 (define_insn "extlh_be"
1992 [(set (match_operand:DI 0 "register_operand" "=r")
1995 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1999 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2003 (const_int 2147483647)))]
2006 [(set_attr "type" "shift")])
2008 (define_insn "extwh_le"
2009 [(set (match_operand:DI 0 "register_operand" "=r")
2011 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2013 (minus:DI (const_int 64)
2016 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2019 "! WORDS_BIG_ENDIAN"
2021 [(set_attr "type" "shift")])
2023 (define_insn "extwh_be"
2024 [(set (match_operand:DI 0 "register_operand" "=r")
2026 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2030 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2034 (const_int 65535)))]
2037 [(set_attr "type" "shift")])
2039 ;; This converts an extXl into an extXh with an appropriate adjustment
2040 ;; to the address calculation.
2043 ;; [(set (match_operand:DI 0 "register_operand" "")
2044 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2045 ;; (match_operand:DI 2 "mode_width_operand" "")
2046 ;; (ashift:DI (match_operand:DI 3 "" "")
2048 ;; (match_operand:DI 4 "const_int_operand" "")))
2049 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2050 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2051 ;; [(set (match_dup 5) (match_dup 6))
2052 ;; (set (match_dup 0)
2053 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2054 ;; (ashift:DI (plus:DI (match_dup 5)
2060 ;; operands[6] = plus_constant (operands[3],
2061 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2062 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2065 (define_insn "*insbl_const"
2066 [(set (match_operand:DI 0 "register_operand" "=r")
2067 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2068 (match_operand:DI 2 "mul8_operand" "I")))]
2071 [(set_attr "type" "shift")])
2073 (define_insn "*inswl_const"
2074 [(set (match_operand:DI 0 "register_operand" "=r")
2075 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2076 (match_operand:DI 2 "mul8_operand" "I")))]
2079 [(set_attr "type" "shift")])
2081 (define_insn "*insll_const"
2082 [(set (match_operand:DI 0 "register_operand" "=r")
2083 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2084 (match_operand:DI 2 "mul8_operand" "I")))]
2087 [(set_attr "type" "shift")])
2089 (define_insn "insbl_le"
2090 [(set (match_operand:DI 0 "register_operand" "=r")
2091 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2092 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2094 "! WORDS_BIG_ENDIAN"
2096 [(set_attr "type" "shift")])
2098 (define_insn "insbl_be"
2099 [(set (match_operand:DI 0 "register_operand" "=r")
2100 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2101 (minus:DI (const_int 56)
2102 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2106 [(set_attr "type" "shift")])
2108 (define_insn "inswl_le"
2109 [(set (match_operand:DI 0 "register_operand" "=r")
2110 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2111 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2113 "! WORDS_BIG_ENDIAN"
2115 [(set_attr "type" "shift")])
2117 (define_insn "inswl_be"
2118 [(set (match_operand:DI 0 "register_operand" "=r")
2119 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2120 (minus:DI (const_int 56)
2121 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2125 [(set_attr "type" "shift")])
2127 (define_insn "insll_le"
2128 [(set (match_operand:DI 0 "register_operand" "=r")
2129 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2130 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2132 "! WORDS_BIG_ENDIAN"
2134 [(set_attr "type" "shift")])
2136 (define_insn "insll_be"
2137 [(set (match_operand:DI 0 "register_operand" "=r")
2138 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2139 (minus:DI (const_int 56)
2140 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2144 [(set_attr "type" "shift")])
2146 (define_insn "insql_le"
2147 [(set (match_operand:DI 0 "register_operand" "=r")
2148 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2149 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2151 "! WORDS_BIG_ENDIAN"
2153 [(set_attr "type" "shift")])
2155 (define_insn "insql_be"
2156 [(set (match_operand:DI 0 "register_operand" "=r")
2157 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2158 (minus:DI (const_int 56)
2159 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2163 [(set_attr "type" "shift")])
2165 ;; Combine has this sometimes habit of moving the and outside of the
2166 ;; shift, making life more interesting.
2168 (define_insn "*insxl"
2169 [(set (match_operand:DI 0 "register_operand" "=r")
2170 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2171 (match_operand:DI 2 "mul8_operand" "I"))
2172 (match_operand:DI 3 "immediate_operand" "i")))]
2173 "HOST_BITS_PER_WIDE_INT == 64
2174 && GET_CODE (operands[3]) == CONST_INT
2175 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2176 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2177 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2178 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2179 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2180 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2182 #if HOST_BITS_PER_WIDE_INT == 64
2183 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2184 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2185 return "insbl %1,%s2,%0";
2186 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2187 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2188 return "inswl %1,%s2,%0";
2189 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2190 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2191 return "insll %1,%s2,%0";
2195 [(set_attr "type" "shift")])
2197 ;; We do not include the insXh insns because they are complex to express
2198 ;; and it does not appear that we would ever want to generate them.
2200 ;; Since we need them for block moves, though, cop out and use unspec.
2202 (define_insn "insxh"
2203 [(set (match_operand:DI 0 "register_operand" "=r")
2204 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2205 (match_operand:DI 2 "mode_width_operand" "n")
2206 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2210 [(set_attr "type" "shift")])
2212 (define_insn "mskxl_le"
2213 [(set (match_operand:DI 0 "register_operand" "=r")
2214 (and:DI (not:DI (ashift:DI
2215 (match_operand:DI 2 "mode_mask_operand" "n")
2217 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2219 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2220 "! WORDS_BIG_ENDIAN"
2222 [(set_attr "type" "shift")])
2224 (define_insn "mskxl_be"
2225 [(set (match_operand:DI 0 "register_operand" "=r")
2226 (and:DI (not:DI (ashift:DI
2227 (match_operand:DI 2 "mode_mask_operand" "n")
2228 (minus:DI (const_int 56)
2230 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2232 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2235 [(set_attr "type" "shift")])
2237 ;; We do not include the mskXh insns because it does not appear we would
2238 ;; ever generate one.
2240 ;; Again, we do for block moves and we use unspec again.
2242 (define_insn "mskxh"
2243 [(set (match_operand:DI 0 "register_operand" "=r")
2244 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2245 (match_operand:DI 2 "mode_width_operand" "n")
2246 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2250 [(set_attr "type" "shift")])
2252 ;; Prefer AND + NE over LSHIFTRT + AND.
2254 (define_insn_and_split "*ze_and_ne"
2255 [(set (match_operand:DI 0 "register_operand" "=r")
2256 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2258 (match_operand 2 "const_int_operand" "I")))]
2259 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2261 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2263 (and:DI (match_dup 1) (match_dup 3)))
2265 (ne:DI (match_dup 0) (const_int 0)))]
2266 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2268 ;; Floating-point operations. All the double-precision insns can extend
2269 ;; from single, so indicate that. The exception are the ones that simply
2270 ;; play with the sign bits; it's not clear what to do there.
2272 (define_insn "abssf2"
2273 [(set (match_operand:SF 0 "register_operand" "=f")
2274 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2277 [(set_attr "type" "fcpys")])
2279 (define_insn "*nabssf2"
2280 [(set (match_operand:SF 0 "register_operand" "=f")
2281 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2284 [(set_attr "type" "fadd")])
2286 (define_insn "absdf2"
2287 [(set (match_operand:DF 0 "register_operand" "=f")
2288 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2291 [(set_attr "type" "fcpys")])
2293 (define_insn "*nabsdf2"
2294 [(set (match_operand:DF 0 "register_operand" "=f")
2295 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2298 [(set_attr "type" "fadd")])
2300 (define_expand "abstf2"
2301 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2302 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2303 (use (match_dup 2))])]
2304 "TARGET_HAS_XFLOATING_LIBS"
2306 #if HOST_BITS_PER_WIDE_INT >= 64
2307 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2309 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2313 (define_insn_and_split "*abstf_internal"
2314 [(set (match_operand:TF 0 "register_operand" "=r")
2315 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2316 (use (match_operand:DI 2 "register_operand" "r"))]
2317 "TARGET_HAS_XFLOATING_LIBS"
2319 "&& reload_completed"
2321 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2323 (define_insn "negsf2"
2324 [(set (match_operand:SF 0 "register_operand" "=f")
2325 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2328 [(set_attr "type" "fadd")])
2330 (define_insn "negdf2"
2331 [(set (match_operand:DF 0 "register_operand" "=f")
2332 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2335 [(set_attr "type" "fadd")])
2337 (define_expand "negtf2"
2338 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2339 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2340 (use (match_dup 2))])]
2341 "TARGET_HAS_XFLOATING_LIBS"
2343 #if HOST_BITS_PER_WIDE_INT >= 64
2344 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2346 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2350 (define_insn_and_split "*negtf_internal"
2351 [(set (match_operand:TF 0 "register_operand" "=r")
2352 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2353 (use (match_operand:DI 2 "register_operand" "r"))]
2354 "TARGET_HAS_XFLOATING_LIBS"
2356 "&& reload_completed"
2358 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2360 (define_insn "*addsf_ieee"
2361 [(set (match_operand:SF 0 "register_operand" "=&f")
2362 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2363 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2364 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2365 "add%,%/ %R1,%R2,%0"
2366 [(set_attr "type" "fadd")
2367 (set_attr "trap" "yes")
2368 (set_attr "round_suffix" "normal")
2369 (set_attr "trap_suffix" "u_su_sui")])
2371 (define_insn "addsf3"
2372 [(set (match_operand:SF 0 "register_operand" "=f")
2373 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2374 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2376 "add%,%/ %R1,%R2,%0"
2377 [(set_attr "type" "fadd")
2378 (set_attr "trap" "yes")
2379 (set_attr "round_suffix" "normal")
2380 (set_attr "trap_suffix" "u_su_sui")])
2382 (define_insn "*adddf_ieee"
2383 [(set (match_operand:DF 0 "register_operand" "=&f")
2384 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2385 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2386 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2387 "add%-%/ %R1,%R2,%0"
2388 [(set_attr "type" "fadd")
2389 (set_attr "trap" "yes")
2390 (set_attr "round_suffix" "normal")
2391 (set_attr "trap_suffix" "u_su_sui")])
2393 (define_insn "adddf3"
2394 [(set (match_operand:DF 0 "register_operand" "=f")
2395 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2396 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2398 "add%-%/ %R1,%R2,%0"
2399 [(set_attr "type" "fadd")
2400 (set_attr "trap" "yes")
2401 (set_attr "round_suffix" "normal")
2402 (set_attr "trap_suffix" "u_su_sui")])
2404 (define_insn "*adddf_ext1"
2405 [(set (match_operand:DF 0 "register_operand" "=f")
2406 (plus:DF (float_extend:DF
2407 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2408 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2409 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2410 "add%-%/ %R1,%R2,%0"
2411 [(set_attr "type" "fadd")
2412 (set_attr "trap" "yes")
2413 (set_attr "round_suffix" "normal")
2414 (set_attr "trap_suffix" "u_su_sui")])
2416 (define_insn "*adddf_ext2"
2417 [(set (match_operand:DF 0 "register_operand" "=f")
2418 (plus:DF (float_extend:DF
2419 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2421 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2422 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2423 "add%-%/ %R1,%R2,%0"
2424 [(set_attr "type" "fadd")
2425 (set_attr "trap" "yes")
2426 (set_attr "round_suffix" "normal")
2427 (set_attr "trap_suffix" "u_su_sui")])
2429 (define_expand "addtf3"
2430 [(use (match_operand 0 "register_operand" ""))
2431 (use (match_operand 1 "general_operand" ""))
2432 (use (match_operand 2 "general_operand" ""))]
2433 "TARGET_HAS_XFLOATING_LIBS"
2434 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2436 ;; Define conversion operators between DFmode and SImode, using the cvtql
2437 ;; instruction. To allow combine et al to do useful things, we keep the
2438 ;; operation as a unit until after reload, at which point we split the
2441 ;; Note that we (attempt to) only consider this optimization when the
2442 ;; ultimate destination is memory. If we will be doing further integer
2443 ;; processing, it is cheaper to do the truncation in the int regs.
2445 (define_insn "*cvtql"
2446 [(set (match_operand:SI 0 "register_operand" "=f")
2447 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2451 [(set_attr "type" "fadd")
2452 (set_attr "trap" "yes")
2453 (set_attr "trap_suffix" "v_sv")])
2455 (define_insn_and_split "*fix_truncdfsi_ieee"
2456 [(set (match_operand:SI 0 "memory_operand" "=m")
2457 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2458 (clobber (match_scratch:DI 2 "=&f"))
2459 (clobber (match_scratch:SI 3 "=&f"))]
2460 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2462 "&& reload_completed"
2463 [(set (match_dup 2) (fix:DI (match_dup 1)))
2464 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2465 (set (match_dup 0) (match_dup 3))]
2467 [(set_attr "type" "fadd")
2468 (set_attr "trap" "yes")])
2470 (define_insn_and_split "*fix_truncdfsi_internal"
2471 [(set (match_operand:SI 0 "memory_operand" "=m")
2472 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2473 (clobber (match_scratch:DI 2 "=f"))]
2474 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2476 "&& reload_completed"
2477 [(set (match_dup 2) (fix:DI (match_dup 1)))
2478 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2479 (set (match_dup 0) (match_dup 3))]
2480 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2481 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2482 [(set_attr "type" "fadd")
2483 (set_attr "trap" "yes")])
2485 (define_insn "*fix_truncdfdi_ieee"
2486 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2487 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2488 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2490 [(set_attr "type" "fadd")
2491 (set_attr "trap" "yes")
2492 (set_attr "round_suffix" "c")
2493 (set_attr "trap_suffix" "v_sv_svi")])
2495 (define_insn "fix_truncdfdi2"
2496 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2497 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2500 [(set_attr "type" "fadd")
2501 (set_attr "trap" "yes")
2502 (set_attr "round_suffix" "c")
2503 (set_attr "trap_suffix" "v_sv_svi")])
2505 ;; Likewise between SFmode and SImode.
2507 (define_insn_and_split "*fix_truncsfsi_ieee"
2508 [(set (match_operand:SI 0 "memory_operand" "=m")
2509 (subreg:SI (fix:DI (float_extend:DF
2510 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2511 (clobber (match_scratch:DI 2 "=&f"))
2512 (clobber (match_scratch:SI 3 "=&f"))]
2513 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2515 "&& reload_completed"
2516 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2517 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2518 (set (match_dup 0) (match_dup 3))]
2520 [(set_attr "type" "fadd")
2521 (set_attr "trap" "yes")])
2523 (define_insn_and_split "*fix_truncsfsi_internal"
2524 [(set (match_operand:SI 0 "memory_operand" "=m")
2525 (subreg:SI (fix:DI (float_extend:DF
2526 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2527 (clobber (match_scratch:DI 2 "=f"))]
2528 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2530 "&& reload_completed"
2531 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2532 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2533 (set (match_dup 0) (match_dup 3))]
2534 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2535 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2536 [(set_attr "type" "fadd")
2537 (set_attr "trap" "yes")])
2539 (define_insn "*fix_truncsfdi_ieee"
2540 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2541 (fix:DI (float_extend:DF
2542 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2543 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2545 [(set_attr "type" "fadd")
2546 (set_attr "trap" "yes")
2547 (set_attr "round_suffix" "c")
2548 (set_attr "trap_suffix" "v_sv_svi")])
2550 (define_insn "fix_truncsfdi2"
2551 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2552 (fix:DI (float_extend:DF
2553 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2556 [(set_attr "type" "fadd")
2557 (set_attr "trap" "yes")
2558 (set_attr "round_suffix" "c")
2559 (set_attr "trap_suffix" "v_sv_svi")])
2561 (define_expand "fix_trunctfdi2"
2562 [(use (match_operand:DI 0 "register_operand" ""))
2563 (use (match_operand:TF 1 "general_operand" ""))]
2564 "TARGET_HAS_XFLOATING_LIBS"
2565 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2567 (define_insn "*floatdisf_ieee"
2568 [(set (match_operand:SF 0 "register_operand" "=&f")
2569 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2570 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2572 [(set_attr "type" "fadd")
2573 (set_attr "trap" "yes")
2574 (set_attr "round_suffix" "normal")
2575 (set_attr "trap_suffix" "sui")])
2577 (define_insn "floatdisf2"
2578 [(set (match_operand:SF 0 "register_operand" "=f")
2579 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2582 [(set_attr "type" "fadd")
2583 (set_attr "trap" "yes")
2584 (set_attr "round_suffix" "normal")
2585 (set_attr "trap_suffix" "sui")])
2587 (define_insn "*floatdidf_ieee"
2588 [(set (match_operand:DF 0 "register_operand" "=&f")
2589 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2590 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2592 [(set_attr "type" "fadd")
2593 (set_attr "trap" "yes")
2594 (set_attr "round_suffix" "normal")
2595 (set_attr "trap_suffix" "sui")])
2597 (define_insn "floatdidf2"
2598 [(set (match_operand:DF 0 "register_operand" "=f")
2599 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2602 [(set_attr "type" "fadd")
2603 (set_attr "trap" "yes")
2604 (set_attr "round_suffix" "normal")
2605 (set_attr "trap_suffix" "sui")])
2607 (define_expand "floatditf2"
2608 [(use (match_operand:TF 0 "register_operand" ""))
2609 (use (match_operand:DI 1 "general_operand" ""))]
2610 "TARGET_HAS_XFLOATING_LIBS"
2611 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2613 (define_expand "floatunsdisf2"
2614 [(use (match_operand:SF 0 "register_operand" ""))
2615 (use (match_operand:DI 1 "register_operand" ""))]
2617 "alpha_emit_floatuns (operands); DONE;")
2619 (define_expand "floatunsdidf2"
2620 [(use (match_operand:DF 0 "register_operand" ""))
2621 (use (match_operand:DI 1 "register_operand" ""))]
2623 "alpha_emit_floatuns (operands); DONE;")
2625 (define_expand "floatunsditf2"
2626 [(use (match_operand:TF 0 "register_operand" ""))
2627 (use (match_operand:DI 1 "general_operand" ""))]
2628 "TARGET_HAS_XFLOATING_LIBS"
2629 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2631 (define_expand "extendsfdf2"
2632 [(set (match_operand:DF 0 "register_operand" "")
2633 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2636 if (alpha_fptm >= ALPHA_FPTM_SU)
2637 operands[1] = force_reg (SFmode, operands[1]);
2640 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2641 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2643 (define_insn "*extendsfdf2_ieee"
2644 [(set (match_operand:DF 0 "register_operand" "=&f")
2645 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2646 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2648 [(set_attr "type" "fadd")
2649 (set_attr "trap" "yes")])
2651 (define_insn "*extendsfdf2_internal"
2652 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2653 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2654 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2659 [(set_attr "type" "fcpys,fld,fst")])
2661 (define_expand "extendsftf2"
2662 [(use (match_operand:TF 0 "register_operand" ""))
2663 (use (match_operand:SF 1 "general_operand" ""))]
2664 "TARGET_HAS_XFLOATING_LIBS"
2666 rtx tmp = gen_reg_rtx (DFmode);
2667 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2668 emit_insn (gen_extenddftf2 (operands[0], tmp));
2672 (define_expand "extenddftf2"
2673 [(use (match_operand:TF 0 "register_operand" ""))
2674 (use (match_operand:DF 1 "general_operand" ""))]
2675 "TARGET_HAS_XFLOATING_LIBS"
2676 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2678 (define_insn "*truncdfsf2_ieee"
2679 [(set (match_operand:SF 0 "register_operand" "=&f")
2680 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2681 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2683 [(set_attr "type" "fadd")
2684 (set_attr "trap" "yes")
2685 (set_attr "round_suffix" "normal")
2686 (set_attr "trap_suffix" "u_su_sui")])
2688 (define_insn "truncdfsf2"
2689 [(set (match_operand:SF 0 "register_operand" "=f")
2690 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2693 [(set_attr "type" "fadd")
2694 (set_attr "trap" "yes")
2695 (set_attr "round_suffix" "normal")
2696 (set_attr "trap_suffix" "u_su_sui")])
2698 (define_expand "trunctfdf2"
2699 [(use (match_operand:DF 0 "register_operand" ""))
2700 (use (match_operand:TF 1 "general_operand" ""))]
2701 "TARGET_HAS_XFLOATING_LIBS"
2702 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2704 (define_expand "trunctfsf2"
2705 [(use (match_operand:SF 0 "register_operand" ""))
2706 (use (match_operand:TF 1 "general_operand" ""))]
2707 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2709 rtx tmpf, sticky, arg, lo, hi;
2711 tmpf = gen_reg_rtx (DFmode);
2712 sticky = gen_reg_rtx (DImode);
2713 arg = copy_to_mode_reg (TFmode, operands[1]);
2714 lo = gen_lowpart (DImode, arg);
2715 hi = gen_highpart (DImode, arg);
2717 /* Convert the low word of the TFmode value into a sticky rounding bit,
2718 then or it into the low bit of the high word. This leaves the sticky
2719 bit at bit 48 of the fraction, which is representable in DFmode,
2720 which prevents rounding error in the final conversion to SFmode. */
2722 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2723 gen_rtx_NE (DImode, lo, const0_rtx)));
2724 emit_insn (gen_iordi3 (hi, hi, sticky));
2725 emit_insn (gen_trunctfdf2 (tmpf, arg));
2726 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2730 (define_insn "*divsf3_ieee"
2731 [(set (match_operand:SF 0 "register_operand" "=&f")
2732 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2733 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2734 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2735 "div%,%/ %R1,%R2,%0"
2736 [(set_attr "type" "fdiv")
2737 (set_attr "opsize" "si")
2738 (set_attr "trap" "yes")
2739 (set_attr "round_suffix" "normal")
2740 (set_attr "trap_suffix" "u_su_sui")])
2742 (define_insn "divsf3"
2743 [(set (match_operand:SF 0 "register_operand" "=f")
2744 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2745 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2747 "div%,%/ %R1,%R2,%0"
2748 [(set_attr "type" "fdiv")
2749 (set_attr "opsize" "si")
2750 (set_attr "trap" "yes")
2751 (set_attr "round_suffix" "normal")
2752 (set_attr "trap_suffix" "u_su_sui")])
2754 (define_insn "*divdf3_ieee"
2755 [(set (match_operand:DF 0 "register_operand" "=&f")
2756 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2757 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2758 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2759 "div%-%/ %R1,%R2,%0"
2760 [(set_attr "type" "fdiv")
2761 (set_attr "trap" "yes")
2762 (set_attr "round_suffix" "normal")
2763 (set_attr "trap_suffix" "u_su_sui")])
2765 (define_insn "divdf3"
2766 [(set (match_operand:DF 0 "register_operand" "=f")
2767 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2768 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2770 "div%-%/ %R1,%R2,%0"
2771 [(set_attr "type" "fdiv")
2772 (set_attr "trap" "yes")
2773 (set_attr "round_suffix" "normal")
2774 (set_attr "trap_suffix" "u_su_sui")])
2776 (define_insn "*divdf_ext1"
2777 [(set (match_operand:DF 0 "register_operand" "=f")
2778 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2779 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2780 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2781 "div%-%/ %R1,%R2,%0"
2782 [(set_attr "type" "fdiv")
2783 (set_attr "trap" "yes")
2784 (set_attr "round_suffix" "normal")
2785 (set_attr "trap_suffix" "u_su_sui")])
2787 (define_insn "*divdf_ext2"
2788 [(set (match_operand:DF 0 "register_operand" "=f")
2789 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2791 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2792 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2793 "div%-%/ %R1,%R2,%0"
2794 [(set_attr "type" "fdiv")
2795 (set_attr "trap" "yes")
2796 (set_attr "round_suffix" "normal")
2797 (set_attr "trap_suffix" "u_su_sui")])
2799 (define_insn "*divdf_ext3"
2800 [(set (match_operand:DF 0 "register_operand" "=f")
2801 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2802 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2803 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2804 "div%-%/ %R1,%R2,%0"
2805 [(set_attr "type" "fdiv")
2806 (set_attr "trap" "yes")
2807 (set_attr "round_suffix" "normal")
2808 (set_attr "trap_suffix" "u_su_sui")])
2810 (define_expand "divtf3"
2811 [(use (match_operand 0 "register_operand" ""))
2812 (use (match_operand 1 "general_operand" ""))
2813 (use (match_operand 2 "general_operand" ""))]
2814 "TARGET_HAS_XFLOATING_LIBS"
2815 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2817 (define_insn "*mulsf3_ieee"
2818 [(set (match_operand:SF 0 "register_operand" "=&f")
2819 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2820 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2821 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2822 "mul%,%/ %R1,%R2,%0"
2823 [(set_attr "type" "fmul")
2824 (set_attr "trap" "yes")
2825 (set_attr "round_suffix" "normal")
2826 (set_attr "trap_suffix" "u_su_sui")])
2828 (define_insn "mulsf3"
2829 [(set (match_operand:SF 0 "register_operand" "=f")
2830 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2831 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2833 "mul%,%/ %R1,%R2,%0"
2834 [(set_attr "type" "fmul")
2835 (set_attr "trap" "yes")
2836 (set_attr "round_suffix" "normal")
2837 (set_attr "trap_suffix" "u_su_sui")])
2839 (define_insn "*muldf3_ieee"
2840 [(set (match_operand:DF 0 "register_operand" "=&f")
2841 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2842 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2843 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2844 "mul%-%/ %R1,%R2,%0"
2845 [(set_attr "type" "fmul")
2846 (set_attr "trap" "yes")
2847 (set_attr "round_suffix" "normal")
2848 (set_attr "trap_suffix" "u_su_sui")])
2850 (define_insn "muldf3"
2851 [(set (match_operand:DF 0 "register_operand" "=f")
2852 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2853 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2855 "mul%-%/ %R1,%R2,%0"
2856 [(set_attr "type" "fmul")
2857 (set_attr "trap" "yes")
2858 (set_attr "round_suffix" "normal")
2859 (set_attr "trap_suffix" "u_su_sui")])
2861 (define_insn "*muldf_ext1"
2862 [(set (match_operand:DF 0 "register_operand" "=f")
2863 (mult:DF (float_extend:DF
2864 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2865 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2866 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2867 "mul%-%/ %R1,%R2,%0"
2868 [(set_attr "type" "fmul")
2869 (set_attr "trap" "yes")
2870 (set_attr "round_suffix" "normal")
2871 (set_attr "trap_suffix" "u_su_sui")])
2873 (define_insn "*muldf_ext2"
2874 [(set (match_operand:DF 0 "register_operand" "=f")
2875 (mult:DF (float_extend:DF
2876 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2878 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2879 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2880 "mul%-%/ %R1,%R2,%0"
2881 [(set_attr "type" "fmul")
2882 (set_attr "trap" "yes")
2883 (set_attr "round_suffix" "normal")
2884 (set_attr "trap_suffix" "u_su_sui")])
2886 (define_expand "multf3"
2887 [(use (match_operand 0 "register_operand" ""))
2888 (use (match_operand 1 "general_operand" ""))
2889 (use (match_operand 2 "general_operand" ""))]
2890 "TARGET_HAS_XFLOATING_LIBS"
2891 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2893 (define_insn "*subsf3_ieee"
2894 [(set (match_operand:SF 0 "register_operand" "=&f")
2895 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2896 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2897 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2898 "sub%,%/ %R1,%R2,%0"
2899 [(set_attr "type" "fadd")
2900 (set_attr "trap" "yes")
2901 (set_attr "round_suffix" "normal")
2902 (set_attr "trap_suffix" "u_su_sui")])
2904 (define_insn "subsf3"
2905 [(set (match_operand:SF 0 "register_operand" "=f")
2906 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2907 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2909 "sub%,%/ %R1,%R2,%0"
2910 [(set_attr "type" "fadd")
2911 (set_attr "trap" "yes")
2912 (set_attr "round_suffix" "normal")
2913 (set_attr "trap_suffix" "u_su_sui")])
2915 (define_insn "*subdf3_ieee"
2916 [(set (match_operand:DF 0 "register_operand" "=&f")
2917 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2918 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2919 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2920 "sub%-%/ %R1,%R2,%0"
2921 [(set_attr "type" "fadd")
2922 (set_attr "trap" "yes")
2923 (set_attr "round_suffix" "normal")
2924 (set_attr "trap_suffix" "u_su_sui")])
2926 (define_insn "subdf3"
2927 [(set (match_operand:DF 0 "register_operand" "=f")
2928 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2929 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2931 "sub%-%/ %R1,%R2,%0"
2932 [(set_attr "type" "fadd")
2933 (set_attr "trap" "yes")
2934 (set_attr "round_suffix" "normal")
2935 (set_attr "trap_suffix" "u_su_sui")])
2937 (define_insn "*subdf_ext1"
2938 [(set (match_operand:DF 0 "register_operand" "=f")
2939 (minus:DF (float_extend:DF
2940 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2941 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2942 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2943 "sub%-%/ %R1,%R2,%0"
2944 [(set_attr "type" "fadd")
2945 (set_attr "trap" "yes")
2946 (set_attr "round_suffix" "normal")
2947 (set_attr "trap_suffix" "u_su_sui")])
2949 (define_insn "*subdf_ext2"
2950 [(set (match_operand:DF 0 "register_operand" "=f")
2951 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2953 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2954 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2955 "sub%-%/ %R1,%R2,%0"
2956 [(set_attr "type" "fadd")
2957 (set_attr "trap" "yes")
2958 (set_attr "round_suffix" "normal")
2959 (set_attr "trap_suffix" "u_su_sui")])
2961 (define_insn "*subdf_ext3"
2962 [(set (match_operand:DF 0 "register_operand" "=f")
2963 (minus:DF (float_extend:DF
2964 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2966 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2967 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2968 "sub%-%/ %R1,%R2,%0"
2969 [(set_attr "type" "fadd")
2970 (set_attr "trap" "yes")
2971 (set_attr "round_suffix" "normal")
2972 (set_attr "trap_suffix" "u_su_sui")])
2974 (define_expand "subtf3"
2975 [(use (match_operand 0 "register_operand" ""))
2976 (use (match_operand 1 "general_operand" ""))
2977 (use (match_operand 2 "general_operand" ""))]
2978 "TARGET_HAS_XFLOATING_LIBS"
2979 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2981 (define_insn "*sqrtsf2_ieee"
2982 [(set (match_operand:SF 0 "register_operand" "=&f")
2983 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2984 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2986 [(set_attr "type" "fsqrt")
2987 (set_attr "opsize" "si")
2988 (set_attr "trap" "yes")
2989 (set_attr "round_suffix" "normal")
2990 (set_attr "trap_suffix" "u_su_sui")])
2992 (define_insn "sqrtsf2"
2993 [(set (match_operand:SF 0 "register_operand" "=f")
2994 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2995 "TARGET_FP && TARGET_FIX"
2997 [(set_attr "type" "fsqrt")
2998 (set_attr "opsize" "si")
2999 (set_attr "trap" "yes")
3000 (set_attr "round_suffix" "normal")
3001 (set_attr "trap_suffix" "u_su_sui")])
3003 (define_insn "*sqrtdf2_ieee"
3004 [(set (match_operand:DF 0 "register_operand" "=&f")
3005 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3006 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3008 [(set_attr "type" "fsqrt")
3009 (set_attr "trap" "yes")
3010 (set_attr "round_suffix" "normal")
3011 (set_attr "trap_suffix" "u_su_sui")])
3013 (define_insn "sqrtdf2"
3014 [(set (match_operand:DF 0 "register_operand" "=f")
3015 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3016 "TARGET_FP && TARGET_FIX"
3018 [(set_attr "type" "fsqrt")
3019 (set_attr "trap" "yes")
3020 (set_attr "round_suffix" "normal")
3021 (set_attr "trap_suffix" "u_su_sui")])
3023 ;; Next are all the integer comparisons, and conditional moves and branches
3024 ;; and some of the related define_expand's and define_split's.
3026 (define_insn "*setcc_internal"
3027 [(set (match_operand 0 "register_operand" "=r")
3028 (match_operator 1 "alpha_comparison_operator"
3029 [(match_operand:DI 2 "register_operand" "r")
3030 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3031 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3032 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3033 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3035 [(set_attr "type" "icmp")])
3037 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3038 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3040 (define_insn "*setcc_swapped_internal"
3041 [(set (match_operand 0 "register_operand" "=r")
3042 (match_operator 1 "alpha_swapped_comparison_operator"
3043 [(match_operand:DI 2 "register_operand" "r")
3044 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3045 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3046 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3047 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3049 [(set_attr "type" "icmp")])
3051 ;; Use match_operator rather than ne directly so that we can match
3052 ;; multiple integer modes.
3053 (define_insn "*setne_internal"
3054 [(set (match_operand 0 "register_operand" "=r")
3055 (match_operator 1 "signed_comparison_operator"
3056 [(match_operand:DI 2 "register_operand" "r")
3058 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3059 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3060 && GET_CODE (operands[1]) == NE
3061 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3063 [(set_attr "type" "icmp")])
3065 ;; The mode folding trick can't be used with const_int operands, since
3066 ;; reload needs to know the proper mode.
3068 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3069 ;; in order to create more pairs of constants. As long as we're allowing
3070 ;; two constants at the same time, and will have to reload one of them...
3072 (define_insn "*movqicc_internal"
3073 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3075 (match_operator 2 "signed_comparison_operator"
3076 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3077 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3078 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3079 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3080 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3086 [(set_attr "type" "icmov")])
3088 (define_insn "*movhicc_internal"
3089 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3091 (match_operator 2 "signed_comparison_operator"
3092 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3093 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3094 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3095 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3096 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3102 [(set_attr "type" "icmov")])
3104 (define_insn "*movsicc_internal"
3105 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3107 (match_operator 2 "signed_comparison_operator"
3108 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3109 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3110 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3111 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3112 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3118 [(set_attr "type" "icmov")])
3120 (define_insn "*movdicc_internal"
3121 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3123 (match_operator 2 "signed_comparison_operator"
3124 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3125 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3126 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3127 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3128 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3134 [(set_attr "type" "icmov")])
3136 (define_insn "*movqicc_lbc"
3137 [(set (match_operand:QI 0 "register_operand" "=r,r")
3139 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3143 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3144 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3149 [(set_attr "type" "icmov")])
3151 (define_insn "*movhicc_lbc"
3152 [(set (match_operand:HI 0 "register_operand" "=r,r")
3154 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3158 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3159 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3164 [(set_attr "type" "icmov")])
3166 (define_insn "*movsicc_lbc"
3167 [(set (match_operand:SI 0 "register_operand" "=r,r")
3169 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3173 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3174 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3179 [(set_attr "type" "icmov")])
3181 (define_insn "*movdicc_lbc"
3182 [(set (match_operand:DI 0 "register_operand" "=r,r")
3184 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3188 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3189 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3194 [(set_attr "type" "icmov")])
3196 (define_insn "*movqicc_lbs"
3197 [(set (match_operand:QI 0 "register_operand" "=r,r")
3199 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3203 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3204 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3209 [(set_attr "type" "icmov")])
3211 (define_insn "*movhicc_lbs"
3212 [(set (match_operand:HI 0 "register_operand" "=r,r")
3214 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3218 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3219 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3224 [(set_attr "type" "icmov")])
3226 (define_insn "*movsicc_lbs"
3227 [(set (match_operand:SI 0 "register_operand" "=r,r")
3229 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3233 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3234 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3239 [(set_attr "type" "icmov")])
3241 (define_insn "*movdicc_lbs"
3242 [(set (match_operand:DI 0 "register_operand" "=r,r")
3244 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3248 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3249 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3254 [(set_attr "type" "icmov")])
3256 ;; For ABS, we have two choices, depending on whether the input and output
3257 ;; registers are the same or not.
3258 (define_expand "absdi2"
3259 [(set (match_operand:DI 0 "register_operand" "")
3260 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3263 if (rtx_equal_p (operands[0], operands[1]))
3264 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3266 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3270 (define_expand "absdi2_same"
3271 [(set (match_operand:DI 1 "register_operand" "")
3272 (neg:DI (match_operand:DI 0 "register_operand" "")))
3274 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3280 (define_expand "absdi2_diff"
3281 [(set (match_operand:DI 0 "register_operand" "")
3282 (neg:DI (match_operand:DI 1 "register_operand" "")))
3284 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3291 [(set (match_operand:DI 0 "register_operand" "")
3292 (abs:DI (match_dup 0)))
3293 (clobber (match_operand:DI 1 "register_operand" ""))]
3295 [(set (match_dup 1) (neg:DI (match_dup 0)))
3296 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3297 (match_dup 0) (match_dup 1)))]
3301 [(set (match_operand:DI 0 "register_operand" "")
3302 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3303 "! rtx_equal_p (operands[0], operands[1])"
3304 [(set (match_dup 0) (neg:DI (match_dup 1)))
3305 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3306 (match_dup 0) (match_dup 1)))]
3310 [(set (match_operand:DI 0 "register_operand" "")
3311 (neg:DI (abs:DI (match_dup 0))))
3312 (clobber (match_operand:DI 1 "register_operand" ""))]
3314 [(set (match_dup 1) (neg:DI (match_dup 0)))
3315 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3316 (match_dup 0) (match_dup 1)))]
3320 [(set (match_operand:DI 0 "register_operand" "")
3321 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3322 "! rtx_equal_p (operands[0], operands[1])"
3323 [(set (match_dup 0) (neg:DI (match_dup 1)))
3324 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3325 (match_dup 0) (match_dup 1)))]
3328 (define_insn "sminqi3"
3329 [(set (match_operand:QI 0 "register_operand" "=r")
3330 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3331 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3334 [(set_attr "type" "mvi")])
3336 (define_insn "uminqi3"
3337 [(set (match_operand:QI 0 "register_operand" "=r")
3338 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3339 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3342 [(set_attr "type" "mvi")])
3344 (define_insn "smaxqi3"
3345 [(set (match_operand:QI 0 "register_operand" "=r")
3346 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3347 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3350 [(set_attr "type" "mvi")])
3352 (define_insn "umaxqi3"
3353 [(set (match_operand:QI 0 "register_operand" "=r")
3354 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3355 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3358 [(set_attr "type" "mvi")])
3360 (define_insn "sminhi3"
3361 [(set (match_operand:HI 0 "register_operand" "=r")
3362 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3363 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3366 [(set_attr "type" "mvi")])
3368 (define_insn "uminhi3"
3369 [(set (match_operand:HI 0 "register_operand" "=r")
3370 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3371 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3374 [(set_attr "type" "mvi")])
3376 (define_insn "smaxhi3"
3377 [(set (match_operand:HI 0 "register_operand" "=r")
3378 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3379 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3382 [(set_attr "type" "mvi")])
3384 (define_insn "umaxhi3"
3385 [(set (match_operand:HI 0 "register_operand" "=r")
3386 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3387 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3390 [(set_attr "type" "shift")])
3392 (define_expand "smaxdi3"
3394 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3395 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3396 (set (match_operand:DI 0 "register_operand" "")
3397 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3398 (match_dup 1) (match_dup 2)))]
3400 { operands[3] = gen_reg_rtx (DImode); })
3403 [(set (match_operand:DI 0 "register_operand" "")
3404 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3405 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3406 (clobber (match_operand:DI 3 "register_operand" ""))]
3407 "operands[2] != const0_rtx"
3408 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3409 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3410 (match_dup 1) (match_dup 2)))]
3413 (define_insn "*smax_const0"
3414 [(set (match_operand:DI 0 "register_operand" "=r")
3415 (smax:DI (match_operand:DI 1 "register_operand" "0")
3419 [(set_attr "type" "icmov")])
3421 (define_expand "smindi3"
3423 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3424 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3425 (set (match_operand:DI 0 "register_operand" "")
3426 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3427 (match_dup 1) (match_dup 2)))]
3429 { operands[3] = gen_reg_rtx (DImode); })
3432 [(set (match_operand:DI 0 "register_operand" "")
3433 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3434 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3435 (clobber (match_operand:DI 3 "register_operand" ""))]
3436 "operands[2] != const0_rtx"
3437 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3438 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3439 (match_dup 1) (match_dup 2)))]
3442 (define_insn "*smin_const0"
3443 [(set (match_operand:DI 0 "register_operand" "=r")
3444 (smin:DI (match_operand:DI 1 "register_operand" "0")
3448 [(set_attr "type" "icmov")])
3450 (define_expand "umaxdi3"
3452 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3453 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3454 (set (match_operand:DI 0 "register_operand" "")
3455 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3456 (match_dup 1) (match_dup 2)))]
3458 "operands[3] = gen_reg_rtx (DImode);")
3461 [(set (match_operand:DI 0 "register_operand" "")
3462 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3463 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3464 (clobber (match_operand:DI 3 "register_operand" ""))]
3465 "operands[2] != const0_rtx"
3466 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3467 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3468 (match_dup 1) (match_dup 2)))]
3471 (define_expand "umindi3"
3473 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3474 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3475 (set (match_operand:DI 0 "register_operand" "")
3476 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3477 (match_dup 1) (match_dup 2)))]
3479 "operands[3] = gen_reg_rtx (DImode);")
3482 [(set (match_operand:DI 0 "register_operand" "")
3483 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3484 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3485 (clobber (match_operand:DI 3 "register_operand" ""))]
3486 "operands[2] != const0_rtx"
3487 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3488 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3489 (match_dup 1) (match_dup 2)))]
3492 (define_insn "*bcc_normal"
3495 (match_operator 1 "signed_comparison_operator"
3496 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3498 (label_ref (match_operand 0 "" ""))
3502 [(set_attr "type" "ibr")])
3504 (define_insn "*bcc_reverse"
3507 (match_operator 1 "signed_comparison_operator"
3508 [(match_operand:DI 2 "register_operand" "r")
3512 (label_ref (match_operand 0 "" ""))))]
3515 [(set_attr "type" "ibr")])
3517 (define_insn "*blbs_normal"
3520 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3524 (label_ref (match_operand 0 "" ""))
3528 [(set_attr "type" "ibr")])
3530 (define_insn "*blbc_normal"
3533 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3537 (label_ref (match_operand 0 "" ""))
3541 [(set_attr "type" "ibr")])
3547 (match_operator 1 "comparison_operator"
3548 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3550 (match_operand:DI 3 "const_int_operand" ""))
3552 (label_ref (match_operand 0 "" ""))
3554 (clobber (match_operand:DI 4 "register_operand" ""))])]
3555 "INTVAL (operands[3]) != 0"
3557 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3559 (if_then_else (match_op_dup 1
3560 [(zero_extract:DI (match_dup 4)
3564 (label_ref (match_dup 0))
3568 ;; The following are the corresponding floating-point insns. Recall
3569 ;; we need to have variants that expand the arguments from SFmode
3572 (define_insn "*cmpdf_ieee"
3573 [(set (match_operand:DF 0 "register_operand" "=&f")
3574 (match_operator:DF 1 "alpha_fp_comparison_operator"
3575 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3576 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3577 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3578 "cmp%-%C1%/ %R2,%R3,%0"
3579 [(set_attr "type" "fadd")
3580 (set_attr "trap" "yes")
3581 (set_attr "trap_suffix" "su")])
3583 (define_insn "*cmpdf_internal"
3584 [(set (match_operand:DF 0 "register_operand" "=f")
3585 (match_operator:DF 1 "alpha_fp_comparison_operator"
3586 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3587 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3588 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3589 "cmp%-%C1%/ %R2,%R3,%0"
3590 [(set_attr "type" "fadd")
3591 (set_attr "trap" "yes")
3592 (set_attr "trap_suffix" "su")])
3594 (define_insn "*cmpdf_ieee_ext1"
3595 [(set (match_operand:DF 0 "register_operand" "=&f")
3596 (match_operator:DF 1 "alpha_fp_comparison_operator"
3598 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3599 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3600 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3601 "cmp%-%C1%/ %R2,%R3,%0"
3602 [(set_attr "type" "fadd")
3603 (set_attr "trap" "yes")
3604 (set_attr "trap_suffix" "su")])
3606 (define_insn "*cmpdf_ext1"
3607 [(set (match_operand:DF 0 "register_operand" "=f")
3608 (match_operator:DF 1 "alpha_fp_comparison_operator"
3610 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3611 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3612 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3613 "cmp%-%C1%/ %R2,%R3,%0"
3614 [(set_attr "type" "fadd")
3615 (set_attr "trap" "yes")
3616 (set_attr "trap_suffix" "su")])
3618 (define_insn "*cmpdf_ieee_ext2"
3619 [(set (match_operand:DF 0 "register_operand" "=&f")
3620 (match_operator:DF 1 "alpha_fp_comparison_operator"
3621 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3623 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3624 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3625 "cmp%-%C1%/ %R2,%R3,%0"
3626 [(set_attr "type" "fadd")
3627 (set_attr "trap" "yes")
3628 (set_attr "trap_suffix" "su")])
3630 (define_insn "*cmpdf_ext2"
3631 [(set (match_operand:DF 0 "register_operand" "=f")
3632 (match_operator:DF 1 "alpha_fp_comparison_operator"
3633 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3635 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3636 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3637 "cmp%-%C1%/ %R2,%R3,%0"
3638 [(set_attr "type" "fadd")
3639 (set_attr "trap" "yes")
3640 (set_attr "trap_suffix" "su")])
3642 (define_insn "*cmpdf_ieee_ext3"
3643 [(set (match_operand:DF 0 "register_operand" "=&f")
3644 (match_operator:DF 1 "alpha_fp_comparison_operator"
3646 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3648 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3649 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3650 "cmp%-%C1%/ %R2,%R3,%0"
3651 [(set_attr "type" "fadd")
3652 (set_attr "trap" "yes")
3653 (set_attr "trap_suffix" "su")])
3655 (define_insn "*cmpdf_ext3"
3656 [(set (match_operand:DF 0 "register_operand" "=f")
3657 (match_operator:DF 1 "alpha_fp_comparison_operator"
3659 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3661 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3662 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3663 "cmp%-%C1%/ %R2,%R3,%0"
3664 [(set_attr "type" "fadd")
3665 (set_attr "trap" "yes")
3666 (set_attr "trap_suffix" "su")])
3668 (define_insn "*movdfcc_internal"
3669 [(set (match_operand:DF 0 "register_operand" "=f,f")
3671 (match_operator 3 "signed_comparison_operator"
3672 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3673 (match_operand:DF 2 "fp0_operand" "G,G")])
3674 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3675 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3679 fcmov%D3 %R4,%R5,%0"
3680 [(set_attr "type" "fcmov")])
3682 (define_insn "*movsfcc_internal"
3683 [(set (match_operand:SF 0 "register_operand" "=f,f")
3685 (match_operator 3 "signed_comparison_operator"
3686 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3687 (match_operand:DF 2 "fp0_operand" "G,G")])
3688 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3689 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3693 fcmov%D3 %R4,%R5,%0"
3694 [(set_attr "type" "fcmov")])
3696 (define_insn "*movdfcc_ext1"
3697 [(set (match_operand:DF 0 "register_operand" "=f,f")
3699 (match_operator 3 "signed_comparison_operator"
3700 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3701 (match_operand:DF 2 "fp0_operand" "G,G")])
3702 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3703 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3707 fcmov%D3 %R4,%R5,%0"
3708 [(set_attr "type" "fcmov")])
3710 (define_insn "*movdfcc_ext2"
3711 [(set (match_operand:DF 0 "register_operand" "=f,f")
3713 (match_operator 3 "signed_comparison_operator"
3715 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3716 (match_operand:DF 2 "fp0_operand" "G,G")])
3717 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3718 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3722 fcmov%D3 %R4,%R5,%0"
3723 [(set_attr "type" "fcmov")])
3725 (define_insn "*movdfcc_ext3"
3726 [(set (match_operand:SF 0 "register_operand" "=f,f")
3728 (match_operator 3 "signed_comparison_operator"
3730 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3731 (match_operand:DF 2 "fp0_operand" "G,G")])
3732 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3733 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3737 fcmov%D3 %R4,%R5,%0"
3738 [(set_attr "type" "fcmov")])
3740 (define_insn "*movdfcc_ext4"
3741 [(set (match_operand:DF 0 "register_operand" "=f,f")
3743 (match_operator 3 "signed_comparison_operator"
3745 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3746 (match_operand:DF 2 "fp0_operand" "G,G")])
3747 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3748 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3752 fcmov%D3 %R4,%R5,%0"
3753 [(set_attr "type" "fcmov")])
3755 (define_expand "maxdf3"
3757 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3758 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3759 (set (match_operand:DF 0 "register_operand" "")
3760 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3761 (match_dup 1) (match_dup 2)))]
3764 operands[3] = gen_reg_rtx (DFmode);
3765 operands[4] = CONST0_RTX (DFmode);
3768 (define_expand "mindf3"
3770 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3771 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3772 (set (match_operand:DF 0 "register_operand" "")
3773 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3774 (match_dup 1) (match_dup 2)))]
3777 operands[3] = gen_reg_rtx (DFmode);
3778 operands[4] = CONST0_RTX (DFmode);
3781 (define_expand "maxsf3"
3783 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3784 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3785 (set (match_operand:SF 0 "register_operand" "")
3786 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3787 (match_dup 1) (match_dup 2)))]
3790 operands[3] = gen_reg_rtx (DFmode);
3791 operands[4] = CONST0_RTX (DFmode);
3794 (define_expand "minsf3"
3796 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3797 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3798 (set (match_operand:SF 0 "register_operand" "")
3799 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3800 (match_dup 1) (match_dup 2)))]
3803 operands[3] = gen_reg_rtx (DFmode);
3804 operands[4] = CONST0_RTX (DFmode);
3807 (define_insn "*fbcc_normal"
3810 (match_operator 1 "signed_comparison_operator"
3811 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3812 (match_operand:DF 3 "fp0_operand" "G")])
3813 (label_ref (match_operand 0 "" ""))
3817 [(set_attr "type" "fbr")])
3819 (define_insn "*fbcc_ext_normal"
3822 (match_operator 1 "signed_comparison_operator"
3824 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3825 (match_operand:DF 3 "fp0_operand" "G")])
3826 (label_ref (match_operand 0 "" ""))
3830 [(set_attr "type" "fbr")])
3832 ;; These are the main define_expand's used to make conditional branches
3835 (define_expand "cmpdf"
3836 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3837 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3840 alpha_compare.op0 = operands[0];
3841 alpha_compare.op1 = operands[1];
3842 alpha_compare.fp_p = 1;
3846 (define_expand "cmptf"
3847 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3848 (match_operand:TF 1 "general_operand" "")))]
3849 "TARGET_HAS_XFLOATING_LIBS"
3851 alpha_compare.op0 = operands[0];
3852 alpha_compare.op1 = operands[1];
3853 alpha_compare.fp_p = 1;
3857 (define_expand "cmpdi"
3858 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3859 (match_operand:DI 1 "general_operand" "")))]
3862 alpha_compare.op0 = operands[0];
3863 alpha_compare.op1 = operands[1];
3864 alpha_compare.fp_p = 0;
3868 (define_expand "beq"
3870 (if_then_else (match_dup 1)
3871 (label_ref (match_operand 0 "" ""))
3874 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3876 (define_expand "bne"
3878 (if_then_else (match_dup 1)
3879 (label_ref (match_operand 0 "" ""))
3882 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3884 (define_expand "blt"
3886 (if_then_else (match_dup 1)
3887 (label_ref (match_operand 0 "" ""))
3890 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3892 (define_expand "ble"
3894 (if_then_else (match_dup 1)
3895 (label_ref (match_operand 0 "" ""))
3898 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3900 (define_expand "bgt"
3902 (if_then_else (match_dup 1)
3903 (label_ref (match_operand 0 "" ""))
3906 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3908 (define_expand "bge"
3910 (if_then_else (match_dup 1)
3911 (label_ref (match_operand 0 "" ""))
3914 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3916 (define_expand "bltu"
3918 (if_then_else (match_dup 1)
3919 (label_ref (match_operand 0 "" ""))
3922 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3924 (define_expand "bleu"
3926 (if_then_else (match_dup 1)
3927 (label_ref (match_operand 0 "" ""))
3930 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3932 (define_expand "bgtu"
3934 (if_then_else (match_dup 1)
3935 (label_ref (match_operand 0 "" ""))
3938 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3940 (define_expand "bgeu"
3942 (if_then_else (match_dup 1)
3943 (label_ref (match_operand 0 "" ""))
3946 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3948 (define_expand "bunordered"
3950 (if_then_else (match_dup 1)
3951 (label_ref (match_operand 0 "" ""))
3954 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3956 (define_expand "bordered"
3958 (if_then_else (match_dup 1)
3959 (label_ref (match_operand 0 "" ""))
3962 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3964 (define_expand "seq"
3965 [(set (match_operand:DI 0 "register_operand" "")
3968 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3970 (define_expand "sne"
3971 [(set (match_operand:DI 0 "register_operand" "")
3974 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3976 (define_expand "slt"
3977 [(set (match_operand:DI 0 "register_operand" "")
3980 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3982 (define_expand "sle"
3983 [(set (match_operand:DI 0 "register_operand" "")
3986 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3988 (define_expand "sgt"
3989 [(set (match_operand:DI 0 "register_operand" "")
3992 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3994 (define_expand "sge"
3995 [(set (match_operand:DI 0 "register_operand" "")
3998 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4000 (define_expand "sltu"
4001 [(set (match_operand:DI 0 "register_operand" "")
4004 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4006 (define_expand "sleu"
4007 [(set (match_operand:DI 0 "register_operand" "")
4010 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4012 (define_expand "sgtu"
4013 [(set (match_operand:DI 0 "register_operand" "")
4016 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4018 (define_expand "sgeu"
4019 [(set (match_operand:DI 0 "register_operand" "")
4022 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4024 (define_expand "sunordered"
4025 [(set (match_operand:DI 0 "register_operand" "")
4028 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4030 (define_expand "sordered"
4031 [(set (match_operand:DI 0 "register_operand" "")
4034 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4036 ;; These are the main define_expand's used to make conditional moves.
4038 (define_expand "movsicc"
4039 [(set (match_operand:SI 0 "register_operand" "")
4040 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4041 (match_operand:SI 2 "reg_or_8bit_operand" "")
4042 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4045 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4049 (define_expand "movdicc"
4050 [(set (match_operand:DI 0 "register_operand" "")
4051 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4052 (match_operand:DI 2 "reg_or_8bit_operand" "")
4053 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4056 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4060 (define_expand "movsfcc"
4061 [(set (match_operand:SF 0 "register_operand" "")
4062 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4063 (match_operand:SF 2 "reg_or_8bit_operand" "")
4064 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4067 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4071 (define_expand "movdfcc"
4072 [(set (match_operand:DF 0 "register_operand" "")
4073 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4074 (match_operand:DF 2 "reg_or_8bit_operand" "")
4075 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4078 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4082 ;; These define_split definitions are used in cases when comparisons have
4083 ;; not be stated in the correct way and we need to reverse the second
4084 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4085 ;; comparison that tests the result being reversed. We have one define_split
4086 ;; for each use of a comparison. They do not match valid insns and need
4087 ;; not generate valid insns.
4089 ;; We can also handle equality comparisons (and inequality comparisons in
4090 ;; cases where the resulting add cannot overflow) by doing an add followed by
4091 ;; a comparison with zero. This is faster since the addition takes one
4092 ;; less cycle than a compare when feeding into a conditional move.
4093 ;; For this case, we also have an SImode pattern since we can merge the add
4094 ;; and sign extend and the order doesn't matter.
4096 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4097 ;; operation could have been generated.
4100 [(set (match_operand:DI 0 "register_operand" "")
4102 (match_operator 1 "comparison_operator"
4103 [(match_operand:DI 2 "reg_or_0_operand" "")
4104 (match_operand:DI 3 "reg_or_cint_operand" "")])
4105 (match_operand:DI 4 "reg_or_cint_operand" "")
4106 (match_operand:DI 5 "reg_or_cint_operand" "")))
4107 (clobber (match_operand:DI 6 "register_operand" ""))]
4108 "operands[3] != const0_rtx"
4109 [(set (match_dup 6) (match_dup 7))
4111 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4113 enum rtx_code code = GET_CODE (operands[1]);
4114 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4116 /* If we are comparing for equality with a constant and that constant
4117 appears in the arm when the register equals the constant, use the
4118 register since that is more likely to match (and to produce better code
4121 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4122 && rtx_equal_p (operands[4], operands[3]))
4123 operands[4] = operands[2];
4125 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4126 && rtx_equal_p (operands[5], operands[3]))
4127 operands[5] = operands[2];
4129 if (code == NE || code == EQ
4130 || (extended_count (operands[2], DImode, unsignedp) >= 1
4131 && extended_count (operands[3], DImode, unsignedp) >= 1))
4133 if (GET_CODE (operands[3]) == CONST_INT)
4134 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4135 GEN_INT (- INTVAL (operands[3])));
4137 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4139 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4142 else if (code == EQ || code == LE || code == LT
4143 || code == LEU || code == LTU)
4145 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4146 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4150 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4151 operands[2], operands[3]);
4152 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4157 [(set (match_operand:DI 0 "register_operand" "")
4159 (match_operator 1 "comparison_operator"
4160 [(match_operand:SI 2 "reg_or_0_operand" "")
4161 (match_operand:SI 3 "reg_or_cint_operand" "")])
4162 (match_operand:DI 4 "reg_or_8bit_operand" "")
4163 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4164 (clobber (match_operand:DI 6 "register_operand" ""))]
4165 "operands[3] != const0_rtx
4166 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4167 [(set (match_dup 6) (match_dup 7))
4169 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4171 enum rtx_code code = GET_CODE (operands[1]);
4172 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4175 if ((code != NE && code != EQ
4176 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4177 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4180 if (GET_CODE (operands[3]) == CONST_INT)
4181 tem = gen_rtx_PLUS (SImode, operands[2],
4182 GEN_INT (- INTVAL (operands[3])));
4184 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4186 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4187 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4188 operands[6], const0_rtx);
4194 (match_operator 1 "comparison_operator"
4195 [(match_operand:DI 2 "reg_or_0_operand" "")
4196 (match_operand:DI 3 "reg_or_cint_operand" "")])
4197 (label_ref (match_operand 0 "" ""))
4199 (clobber (match_operand:DI 4 "register_operand" ""))]
4200 "operands[3] != const0_rtx"
4201 [(set (match_dup 4) (match_dup 5))
4202 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4204 enum rtx_code code = GET_CODE (operands[1]);
4205 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4207 if (code == NE || code == EQ
4208 || (extended_count (operands[2], DImode, unsignedp) >= 1
4209 && extended_count (operands[3], DImode, unsignedp) >= 1))
4211 if (GET_CODE (operands[3]) == CONST_INT)
4212 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4213 GEN_INT (- INTVAL (operands[3])));
4215 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4217 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4220 else if (code == EQ || code == LE || code == LT
4221 || code == LEU || code == LTU)
4223 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4224 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4228 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4229 operands[2], operands[3]);
4230 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4237 (match_operator 1 "comparison_operator"
4238 [(match_operand:SI 2 "reg_or_0_operand" "")
4239 (match_operand:SI 3 "const_int_operand" "")])
4240 (label_ref (match_operand 0 "" ""))
4242 (clobber (match_operand:DI 4 "register_operand" ""))]
4243 "operands[3] != const0_rtx
4244 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4245 [(set (match_dup 4) (match_dup 5))
4246 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4250 if (GET_CODE (operands[3]) == CONST_INT)
4251 tem = gen_rtx_PLUS (SImode, operands[2],
4252 GEN_INT (- INTVAL (operands[3])));
4254 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4256 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4257 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4258 operands[4], const0_rtx);
4261 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4262 ;; This eliminates one, and sometimes two, insns when the AND can be done
4265 [(set (match_operand:DI 0 "register_operand" "")
4266 (match_operator:DI 1 "comparison_operator"
4267 [(match_operand:DI 2 "register_operand" "")
4268 (match_operand:DI 3 "const_int_operand" "")]))
4269 (clobber (match_operand:DI 4 "register_operand" ""))]
4270 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4271 && (GET_CODE (operands[1]) == GTU
4272 || GET_CODE (operands[1]) == LEU
4273 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4274 && extended_count (operands[2], DImode, 1) > 0))"
4275 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4276 (set (match_dup 0) (match_dup 6))]
4278 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4279 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4280 || GET_CODE (operands[1]) == GT)
4282 DImode, operands[4], const0_rtx);
4285 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4288 [(set (match_operand 0 "register_operand" "")
4289 (if_then_else (match_operator 1 "signed_comparison_operator"
4290 [(match_operand:DI 2 "reg_or_0_operand" "")
4292 (match_operand 3 "const_int_operand" "")
4293 (match_operand 4 "const_int_operand" "")))]
4297 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4298 operands[2], operands[3], operands[4]))
4304 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4305 ;; Oh well, we match it in movcc, so it must be partially our fault.
4307 [(set (match_operand 0 "register_operand" "")
4308 (if_then_else (match_operator 1 "signed_comparison_operator"
4310 (match_operand:DI 2 "reg_or_0_operand" "")])
4311 (match_operand 3 "const_int_operand" "")
4312 (match_operand 4 "const_int_operand" "")))]
4316 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4317 operands[0], operands[2], operands[3],
4324 (define_insn_and_split "*cmp_sadd_di"
4325 [(set (match_operand:DI 0 "register_operand" "=r")
4326 (plus:DI (if_then_else:DI
4327 (match_operator 1 "alpha_zero_comparison_operator"
4328 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4330 (match_operand:DI 3 "const48_operand" "I")
4332 (match_operand:DI 4 "sext_add_operand" "rIO")))
4333 (clobber (match_scratch:DI 5 "=r"))]
4336 "! no_new_pseudos || reload_completed"
4338 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4340 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4343 if (! no_new_pseudos)
4344 operands[5] = gen_reg_rtx (DImode);
4345 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4346 operands[5] = operands[0];
4349 (define_insn_and_split "*cmp_sadd_si"
4350 [(set (match_operand:SI 0 "register_operand" "=r")
4351 (plus:SI (if_then_else:SI
4352 (match_operator 1 "alpha_zero_comparison_operator"
4353 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4355 (match_operand:SI 3 "const48_operand" "I")
4357 (match_operand:SI 4 "sext_add_operand" "rIO")))
4358 (clobber (match_scratch:SI 5 "=r"))]
4361 "! no_new_pseudos || reload_completed"
4363 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4365 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4368 if (! no_new_pseudos)
4369 operands[5] = gen_reg_rtx (DImode);
4370 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4371 operands[5] = operands[0];
4374 (define_insn_and_split "*cmp_sadd_sidi"
4375 [(set (match_operand:DI 0 "register_operand" "=r")
4377 (plus:SI (if_then_else:SI
4378 (match_operator 1 "alpha_zero_comparison_operator"
4379 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4381 (match_operand:SI 3 "const48_operand" "I")
4383 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4384 (clobber (match_scratch:SI 5 "=r"))]
4387 "! no_new_pseudos || reload_completed"
4389 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4391 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4394 if (! no_new_pseudos)
4395 operands[5] = gen_reg_rtx (DImode);
4396 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4397 operands[5] = operands[0];
4400 (define_insn_and_split "*cmp_ssub_di"
4401 [(set (match_operand:DI 0 "register_operand" "=r")
4402 (minus:DI (if_then_else:DI
4403 (match_operator 1 "alpha_zero_comparison_operator"
4404 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4406 (match_operand:DI 3 "const48_operand" "I")
4408 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4409 (clobber (match_scratch:DI 5 "=r"))]
4412 "! no_new_pseudos || reload_completed"
4414 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4416 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4419 if (! no_new_pseudos)
4420 operands[5] = gen_reg_rtx (DImode);
4421 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4422 operands[5] = operands[0];
4425 (define_insn_and_split "*cmp_ssub_si"
4426 [(set (match_operand:SI 0 "register_operand" "=r")
4427 (minus:SI (if_then_else:SI
4428 (match_operator 1 "alpha_zero_comparison_operator"
4429 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4431 (match_operand:SI 3 "const48_operand" "I")
4433 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4434 (clobber (match_scratch:SI 5 "=r"))]
4437 "! no_new_pseudos || reload_completed"
4439 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4441 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4444 if (! no_new_pseudos)
4445 operands[5] = gen_reg_rtx (DImode);
4446 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4447 operands[5] = operands[0];
4450 (define_insn_and_split "*cmp_ssub_sidi"
4451 [(set (match_operand:DI 0 "register_operand" "=r")
4453 (minus:SI (if_then_else:SI
4454 (match_operator 1 "alpha_zero_comparison_operator"
4455 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4457 (match_operand:SI 3 "const48_operand" "I")
4459 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4460 (clobber (match_scratch:SI 5 "=r"))]
4463 "! no_new_pseudos || reload_completed"
4465 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4467 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4470 if (! no_new_pseudos)
4471 operands[5] = gen_reg_rtx (DImode);
4472 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4473 operands[5] = operands[0];
4476 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4477 ;; work differently, so we have different patterns for each.
4479 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4480 ;; call. The CIW contains information about arguments passed in registers
4481 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4482 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4483 ;; in the presence of inlining since the CIWs for calls performed by the
4484 ;; inlined function must be stored in the SSIB of the function it is inlined
4485 ;; into as well. We encode the CIW in an unspec and append it to the list
4486 ;; of the CIWs for the current function only when the instruction for loading
4487 ;; $25 is generated.
4489 (define_expand "call"
4490 [(use (match_operand:DI 0 "" ""))
4491 (use (match_operand 1 "" ""))
4492 (use (match_operand 2 "" ""))
4493 (use (match_operand 3 "" ""))]
4496 if (TARGET_ABI_WINDOWS_NT)
4497 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4498 else if (TARGET_ABI_OPEN_VMS)
4499 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4500 else if (TARGET_ABI_UNICOSMK)
4501 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4503 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4507 (define_expand "sibcall"
4508 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4509 (match_operand 1 "" ""))
4510 (use (reg:DI 29))])]
4513 if (GET_CODE (operands[0]) != MEM)
4515 operands[0] = XEXP (operands[0], 0);
4518 (define_expand "call_osf"
4519 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4520 (match_operand 1 "" ""))
4522 (clobber (reg:DI 26))])]
4525 if (GET_CODE (operands[0]) != MEM)
4528 operands[0] = XEXP (operands[0], 0);
4529 if (! call_operand (operands[0], Pmode))
4531 rtx pv = gen_rtx_REG (Pmode, 27);
4532 emit_move_insn (pv, operands[0]);
4537 (define_expand "call_nt"
4538 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4539 (match_operand 1 "" ""))
4540 (clobber (reg:DI 26))])]
4543 if (GET_CODE (operands[0]) != MEM)
4546 operands[0] = XEXP (operands[0], 0);
4547 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4548 operands[0] = force_reg (DImode, operands[0]);
4551 ;; Calls on Unicos/Mk are always indirect.
4552 ;; op 0: symbol ref for called function
4553 ;; op 1: CIW for $25 represented by an unspec
4555 (define_expand "call_umk"
4556 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4557 (match_operand 1 "" ""))
4559 (clobber (reg:DI 26))])]
4562 if (GET_CODE (operands[0]) != MEM)
4565 /* Always load the address of the called function into a register;
4566 load the CIW in $25. */
4568 operands[0] = XEXP (operands[0], 0);
4569 if (GET_CODE (operands[0]) != REG)
4570 operands[0] = force_reg (DImode, operands[0]);
4572 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4576 ;; call openvms/alpha
4577 ;; op 0: symbol ref for called function
4578 ;; op 1: next_arg_reg (argument information value for R25)
4580 (define_expand "call_vms"
4581 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4582 (match_operand 1 "" ""))
4586 (clobber (reg:DI 27))])]
4589 if (GET_CODE (operands[0]) != MEM)
4592 operands[0] = XEXP (operands[0], 0);
4594 /* Always load AI with argument information, then handle symbolic and
4595 indirect call differently. Load RA and set operands[2] to PV in
4598 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4599 if (GET_CODE (operands[0]) == SYMBOL_REF)
4601 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4603 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4605 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4609 emit_move_insn (gen_rtx_REG (Pmode, 26),
4610 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4611 operands[2] = operands[0];
4616 (define_expand "call_value"
4617 [(use (match_operand 0 "" ""))
4618 (use (match_operand:DI 1 "" ""))
4619 (use (match_operand 2 "" ""))
4620 (use (match_operand 3 "" ""))
4621 (use (match_operand 4 "" ""))]
4624 if (TARGET_ABI_WINDOWS_NT)
4625 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4626 else if (TARGET_ABI_OPEN_VMS)
4627 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4629 else if (TARGET_ABI_UNICOSMK)
4630 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4633 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4638 (define_expand "sibcall_value"
4639 [(parallel [(set (match_operand 0 "" "")
4640 (call (mem:DI (match_operand 1 "" ""))
4641 (match_operand 2 "" "")))
4642 (use (reg:DI 29))])]
4645 if (GET_CODE (operands[1]) != MEM)
4647 operands[1] = XEXP (operands[1], 0);
4650 (define_expand "call_value_osf"
4651 [(parallel [(set (match_operand 0 "" "")
4652 (call (mem:DI (match_operand 1 "" ""))
4653 (match_operand 2 "" "")))
4655 (clobber (reg:DI 26))])]
4658 if (GET_CODE (operands[1]) != MEM)
4661 operands[1] = XEXP (operands[1], 0);
4662 if (! call_operand (operands[1], Pmode))
4664 rtx pv = gen_rtx_REG (Pmode, 27);
4665 emit_move_insn (pv, operands[1]);
4670 (define_expand "call_value_nt"
4671 [(parallel [(set (match_operand 0 "" "")
4672 (call (mem:DI (match_operand 1 "" ""))
4673 (match_operand 2 "" "")))
4674 (clobber (reg:DI 26))])]
4677 if (GET_CODE (operands[1]) != MEM)
4680 operands[1] = XEXP (operands[1], 0);
4681 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4682 operands[1] = force_reg (DImode, operands[1]);
4685 (define_expand "call_value_vms"
4686 [(parallel [(set (match_operand 0 "" "")
4687 (call (mem:DI (match_operand:DI 1 "" ""))
4688 (match_operand 2 "" "")))
4692 (clobber (reg:DI 27))])]
4695 if (GET_CODE (operands[1]) != MEM)
4698 operands[1] = XEXP (operands[1], 0);
4700 /* Always load AI with argument information, then handle symbolic and
4701 indirect call differently. Load RA and set operands[3] to PV in
4704 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4705 if (GET_CODE (operands[1]) == SYMBOL_REF)
4707 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4709 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4711 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4715 emit_move_insn (gen_rtx_REG (Pmode, 26),
4716 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4717 operands[3] = operands[1];
4721 (define_expand "call_value_umk"
4722 [(parallel [(set (match_operand 0 "" "")
4723 (call (mem:DI (match_operand 1 "" ""))
4724 (match_operand 2 "" "")))
4726 (clobber (reg:DI 26))])]
4729 if (GET_CODE (operands[1]) != MEM)
4732 operands[1] = XEXP (operands[1], 0);
4733 if (GET_CODE (operands[1]) != REG)
4734 operands[1] = force_reg (DImode, operands[1]);
4736 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4739 (define_insn "*call_osf_1_er"
4740 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4741 (match_operand 1 "" ""))
4743 (clobber (reg:DI 26))]
4744 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4746 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4748 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4749 [(set_attr "type" "jsr")
4750 (set_attr "length" "12,*,16")])
4752 ;; We must use peep2 instead of a split because we need accurate life
4753 ;; information for $gp. Consider the case of { bar(); while (1); }.
4755 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4756 (match_operand 1 "" ""))
4758 (clobber (reg:DI 26))])]
4759 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4760 && ! current_file_function_operand (operands[0], Pmode)
4761 && peep2_regno_dead_p (1, 29)"
4762 [(parallel [(call (mem:DI (match_dup 2))
4764 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4765 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4766 (use (match_dup 0))])]
4768 if (CONSTANT_P (operands[0]))
4770 operands[2] = gen_rtx_REG (Pmode, 27);
4771 emit_move_insn (operands[2], operands[0]);
4775 operands[2] = operands[0];
4776 operands[0] = const0_rtx;
4781 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4782 (match_operand 1 "" ""))
4784 (clobber (reg:DI 26))])]
4785 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4786 && ! current_file_function_operand (operands[0], Pmode)
4787 && ! peep2_regno_dead_p (1, 29)"
4788 [(parallel [(call (mem:DI (match_dup 2))
4790 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4791 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4792 (use (match_dup 0))])
4794 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4796 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4798 if (CONSTANT_P (operands[0]))
4800 operands[2] = gen_rtx_REG (Pmode, 27);
4801 emit_move_insn (operands[2], operands[0]);
4805 operands[2] = operands[0];
4806 operands[0] = const0_rtx;
4808 operands[3] = GEN_INT (alpha_next_sequence_number++);
4811 ;; We add a blockage unspec_volatile to prevent insns from moving down
4812 ;; from above the call to in between the call and the ldah gpdisp.
4814 (define_insn "*call_osf_2_er"
4815 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4816 (match_operand 1 "" ""))
4817 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4818 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4819 (use (match_operand 2 "" ""))]
4820 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4822 [(set_attr "type" "jsr")])
4824 (define_insn "*call_osf_1_noreturn"
4825 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4826 (match_operand 1 "" ""))
4828 (clobber (reg:DI 26))]
4829 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4830 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4835 [(set_attr "type" "jsr")
4836 (set_attr "length" "*,*,8")])
4838 (define_insn "*call_osf_1"
4839 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4840 (match_operand 1 "" ""))
4842 (clobber (reg:DI 26))]
4843 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4845 jsr $26,($27),0\;ldgp $29,0($26)
4847 jsr $26,%0\;ldgp $29,0($26)"
4848 [(set_attr "type" "jsr")
4849 (set_attr "length" "12,*,16")])
4851 (define_insn "*sibcall_osf_1"
4852 [(call (mem:DI (match_operand:DI 0 "current_file_function_operand" "R"))
4853 (match_operand 1 "" ""))
4857 [(set_attr "type" "jsr")])
4859 (define_insn "*call_nt_1"
4860 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4861 (match_operand 1 "" ""))
4862 (clobber (reg:DI 26))]
4863 "TARGET_ABI_WINDOWS_NT"
4868 [(set_attr "type" "jsr")
4869 (set_attr "length" "*,*,12")])
4871 (define_insn "*call_vms_1"
4872 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4873 (match_operand 1 "" ""))
4874 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4877 (clobber (reg:DI 27))]
4878 "TARGET_ABI_OPEN_VMS"
4880 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4881 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4882 [(set_attr "type" "jsr")
4883 (set_attr "length" "12,16")])
4885 (define_insn "*call_umk_1"
4886 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4887 (match_operand 1 "" ""))
4889 (clobber (reg:DI 26))]
4890 "TARGET_ABI_UNICOSMK"
4892 [(set_attr "type" "jsr")])
4894 ;; Call subroutine returning any type.
4896 (define_expand "untyped_call"
4897 [(parallel [(call (match_operand 0 "" "")
4899 (match_operand 1 "" "")
4900 (match_operand 2 "" "")])]
4905 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4907 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4909 rtx set = XVECEXP (operands[2], 0, i);
4910 emit_move_insn (SET_DEST (set), SET_SRC (set));
4913 /* The optimizer does not know that the call sets the function value
4914 registers we stored in the result block. We avoid problems by
4915 claiming that all hard registers are used and clobbered at this
4917 emit_insn (gen_blockage ());
4922 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4923 ;; all of memory. This blocks insns from being moved across this point.
4925 (define_insn "blockage"
4926 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4929 [(set_attr "length" "0")])
4933 (label_ref (match_operand 0 "" "")))]
4936 [(set_attr "type" "ibr")])
4938 (define_expand "return"
4943 (define_insn "*return_internal"
4947 [(set_attr "type" "ibr")])
4949 (define_insn "indirect_jump"
4950 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4953 [(set_attr "type" "ibr")])
4955 (define_expand "tablejump"
4956 [(parallel [(set (pc)
4957 (match_operand 0 "register_operand" ""))
4958 (use (label_ref:DI (match_operand 1 "" "")))])]
4961 if (TARGET_ABI_WINDOWS_NT)
4963 rtx dest = gen_reg_rtx (DImode);
4964 emit_insn (gen_extendsidi2 (dest, operands[0]));
4967 else if (TARGET_ABI_OSF)
4969 rtx dest = gen_reg_rtx (DImode);
4970 emit_insn (gen_extendsidi2 (dest, operands[0]));
4971 emit_insn (gen_adddi3 (dest, gen_rtx_REG (DImode, 29), dest));
4976 (define_insn "*tablejump_osf_nt_internal"
4978 (match_operand:DI 0 "register_operand" "r"))
4979 (use (label_ref:DI (match_operand 1 "" "")))]
4980 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4981 && alpha_tablejump_addr_vec (insn)"
4983 operands[2] = alpha_tablejump_best_label (insn);
4984 return "jmp $31,(%0),%2";
4986 [(set_attr "type" "ibr")])
4988 (define_insn "*tablejump_internal"
4990 (match_operand:DI 0 "register_operand" "r"))
4991 (use (label_ref (match_operand 1 "" "")))]
4994 [(set_attr "type" "ibr")])
4996 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4997 ;; want to have to include pal.h in our .s file.
4999 ;; Technically the type for call_pal is jsr, but we use that for determining
5000 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5003 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5006 [(set_attr "type" "ibr")])
5008 ;; Finally, we have the basic data motion insns. The byte and word insns
5009 ;; are done via define_expand. Start with the floating-point insns, since
5010 ;; they are simpler.
5012 (define_insn "*movsf_nofix"
5013 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5014 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5015 "TARGET_FPREGS && ! TARGET_FIX
5016 && (register_operand (operands[0], SFmode)
5017 || reg_or_fp0_operand (operands[1], SFmode))"
5025 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5027 (define_insn "*movsf_fix"
5028 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5029 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5030 "TARGET_FPREGS && TARGET_FIX
5031 && (register_operand (operands[0], SFmode)
5032 || reg_or_fp0_operand (operands[1], SFmode))"
5042 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5044 (define_insn "*movsf_nofp"
5045 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5046 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5048 && (register_operand (operands[0], SFmode)
5049 || reg_or_fp0_operand (operands[1], SFmode))"
5054 [(set_attr "type" "ilog,ild,ist")])
5056 (define_insn "*movdf_nofix"
5057 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5058 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5059 "TARGET_FPREGS && ! TARGET_FIX
5060 && (register_operand (operands[0], DFmode)
5061 || reg_or_fp0_operand (operands[1], DFmode))"
5069 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5071 (define_insn "*movdf_fix"
5072 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5073 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5074 "TARGET_FPREGS && TARGET_FIX
5075 && (register_operand (operands[0], DFmode)
5076 || reg_or_fp0_operand (operands[1], DFmode))"
5086 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5088 (define_insn "*movdf_nofp"
5089 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5090 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5092 && (register_operand (operands[0], DFmode)
5093 || reg_or_fp0_operand (operands[1], DFmode))"
5098 [(set_attr "type" "ilog,ild,ist")])
5100 ;; Subregs suck for register allocation. Pretend we can move TFmode
5101 ;; data between general registers until after reload.
5103 (define_insn_and_split "*movtf_internal"
5104 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5105 (match_operand:TF 1 "input_operand" "roG,rG"))]
5106 "register_operand (operands[0], TFmode)
5107 || reg_or_fp0_operand (operands[1], TFmode)"
5110 [(set (match_dup 0) (match_dup 2))
5111 (set (match_dup 1) (match_dup 3))]
5113 alpha_split_tfmode_pair (operands);
5114 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5117 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5118 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5122 (define_expand "movsf"
5123 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5124 (match_operand:SF 1 "general_operand" ""))]
5127 if (GET_CODE (operands[0]) == MEM
5128 && ! reg_or_fp0_operand (operands[1], SFmode))
5129 operands[1] = force_reg (SFmode, operands[1]);
5132 (define_expand "movdf"
5133 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5134 (match_operand:DF 1 "general_operand" ""))]
5137 if (GET_CODE (operands[0]) == MEM
5138 && ! reg_or_fp0_operand (operands[1], DFmode))
5139 operands[1] = force_reg (DFmode, operands[1]);
5142 (define_expand "movtf"
5143 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5144 (match_operand:TF 1 "general_operand" ""))]
5147 if (GET_CODE (operands[0]) == MEM
5148 && ! reg_or_fp0_operand (operands[1], TFmode))
5149 operands[1] = force_reg (TFmode, operands[1]);
5152 (define_insn "*movsi_nofix"
5153 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5154 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5155 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5156 && (register_operand (operands[0], SImode)
5157 || reg_or_0_operand (operands[1], SImode))"
5167 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5169 (define_insn "*movsi_fix"
5170 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5171 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5172 "TARGET_ABI_OSF && TARGET_FIX
5173 && (register_operand (operands[0], SImode)
5174 || reg_or_0_operand (operands[1], SImode))"
5186 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5188 (define_insn "*movsi_nt_vms"
5189 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5190 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5191 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5192 && (register_operand (operands[0], SImode)
5193 || reg_or_0_operand (operands[1], SImode))"
5204 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5206 (define_insn "*movhi_nobwx"
5207 [(set (match_operand:HI 0 "register_operand" "=r,r")
5208 (match_operand:HI 1 "input_operand" "rJ,n"))]
5210 && (register_operand (operands[0], HImode)
5211 || register_operand (operands[1], HImode))"
5215 [(set_attr "type" "ilog,iadd")])
5217 (define_insn "*movhi_bwx"
5218 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5219 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5221 && (register_operand (operands[0], HImode)
5222 || reg_or_0_operand (operands[1], HImode))"
5228 [(set_attr "type" "ilog,iadd,ild,ist")])
5230 (define_insn "*movqi_nobwx"
5231 [(set (match_operand:QI 0 "register_operand" "=r,r")
5232 (match_operand:QI 1 "input_operand" "rJ,n"))]
5234 && (register_operand (operands[0], QImode)
5235 || register_operand (operands[1], QImode))"
5239 [(set_attr "type" "ilog,iadd")])
5241 (define_insn "*movqi_bwx"
5242 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5243 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5245 && (register_operand (operands[0], QImode)
5246 || reg_or_0_operand (operands[1], QImode))"
5252 [(set_attr "type" "ilog,iadd,ild,ist")])
5254 ;; We do two major things here: handle mem->mem and construct long
5257 (define_expand "movsi"
5258 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5259 (match_operand:SI 1 "general_operand" ""))]
5262 if (alpha_expand_mov (SImode, operands))
5266 ;; Split a load of a large constant into the appropriate two-insn
5270 [(set (match_operand:SI 0 "register_operand" "")
5271 (match_operand:SI 1 "const_int_operand" ""))]
5272 "! add_operand (operands[1], SImode)"
5273 [(set (match_dup 0) (match_dup 2))
5274 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5277 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5279 if (tem == operands[0])
5285 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5286 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5287 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5288 ;; notes and update LABEL_NUSES because this is not done automatically.
5289 ;; Labels may be incorrectly deleted if we don't do this.
5291 ;; Describing what the individual instructions do correctly is too complicated
5292 ;; so use UNSPECs for each of the three parts of an address.
5295 [(set (match_operand:DI 0 "register_operand" "")
5296 (match_operand:DI 1 "symbolic_operand" ""))]
5297 "TARGET_ABI_UNICOSMK && reload_completed"
5300 rtx insn1, insn2, insn3;
5302 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5303 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5304 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5305 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5306 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5308 if (GET_CODE (operands[1]) == LABEL_REF)
5312 label = XEXP (operands[1], 0);
5313 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5315 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5317 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5319 LABEL_NUSES (label) += 3;
5324 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5326 (define_insn "umk_laum"
5327 [(set (match_operand:DI 0 "register_operand" "=r")
5328 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5330 "TARGET_ABI_UNICOSMK"
5332 [(set_attr "type" "iadd")])
5334 (define_insn "umk_lalm"
5335 [(set (match_operand:DI 0 "register_operand" "=r")
5336 (plus:DI (match_operand:DI 1 "register_operand" "r")
5337 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5339 "TARGET_ABI_UNICOSMK"
5341 [(set_attr "type" "iadd")])
5343 (define_insn "umk_lal"
5344 [(set (match_operand:DI 0 "register_operand" "=r")
5345 (plus:DI (match_operand:DI 1 "register_operand" "r")
5346 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5348 "TARGET_ABI_UNICOSMK"
5350 [(set_attr "type" "iadd")])
5352 ;; Add a new call information word to the current function's list of CIWs
5353 ;; and load its index into $25. Doing it here ensures that the CIW will be
5354 ;; associated with the correct function even in the presence of inlining.
5356 (define_insn "*umk_load_ciw"
5358 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5359 "TARGET_ABI_UNICOSMK"
5361 operands[0] = unicosmk_add_call_info_word (operands[0]);
5362 return "lda $25,%0";
5364 [(set_attr "type" "iadd")])
5366 (define_insn "*movdi_er_low_l"
5367 [(set (match_operand:DI 0 "register_operand" "=r")
5368 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5369 (match_operand:DI 2 "local_symbolic_operand" "")))]
5370 "TARGET_EXPLICIT_RELOCS"
5372 if (true_regnum (operands[1]) == 29)
5373 return "lda %0,%2(%1)\t\t!gprel";
5375 return "lda %0,%2(%1)\t\t!gprellow";
5378 (define_insn "movdi_er_high_g"
5379 [(set (match_operand:DI 0 "register_operand" "=r")
5380 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5381 (match_operand:DI 2 "global_symbolic_operand" "")
5382 (match_operand 3 "const_int_operand" "")]
5384 "TARGET_EXPLICIT_RELOCS"
5385 "ldq %0,%2(%1)\t\t!literal"
5386 [(set_attr "type" "ldsym")])
5388 (define_insn "*movdi_er_nofix"
5389 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
5390 (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f"))]
5391 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5392 && (register_operand (operands[0], DImode)
5393 || reg_or_0_operand (operands[1], DImode))"
5404 [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst")])
5406 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5407 ;; have been split up by the rules above but we shouldn't reject the
5408 ;; possibility of them getting through.
5410 (define_insn "*movdi_nofix"
5411 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5412 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5414 && (register_operand (operands[0], DImode)
5415 || reg_or_0_operand (operands[1], DImode))"
5420 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5427 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5428 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5430 (define_insn "*movdi_er_fix"
5431 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5432 (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f,*f,r"))]
5433 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5434 && (register_operand (operands[0], DImode)
5435 || reg_or_0_operand (operands[1], DImode))"
5448 [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5450 (define_insn "*movdi_fix"
5451 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5452 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5453 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5454 && (register_operand (operands[0], DImode)
5455 || reg_or_0_operand (operands[1], DImode))"
5468 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5470 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5471 ;; often appears dead to the life analysis code, at which point we
5472 ;; abort for emitting dead prologue instructions. Force this live.
5474 (define_insn "force_movdi"
5475 [(set (match_operand:DI 0 "register_operand" "=r")
5476 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5477 UNSPECV_FORCE_MOV))]
5480 [(set_attr "type" "ilog")])
5482 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5483 ;; memory, and construct long 32-bit constants.
5485 (define_expand "movdi"
5486 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5487 (match_operand:DI 1 "general_operand" ""))]
5490 if (alpha_expand_mov (DImode, operands))
5494 ;; Split a load of a large constant into the appropriate two-insn
5498 [(set (match_operand:DI 0 "register_operand" "")
5499 (match_operand:DI 1 "const_int_operand" ""))]
5500 "! add_operand (operands[1], DImode)"
5501 [(set (match_dup 0) (match_dup 2))
5502 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5505 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5507 if (tem == operands[0])
5513 ;; These are the partial-word cases.
5515 ;; First we have the code to load an aligned word. Operand 0 is the register
5516 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5517 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5518 ;; number of bits within the word that the value is. Operand 3 is an SImode
5519 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5520 ;; same register. It is allowed to conflict with operand 1 as well.
5522 (define_expand "aligned_loadqi"
5523 [(set (match_operand:SI 3 "register_operand" "")
5524 (match_operand:SI 1 "memory_operand" ""))
5525 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5526 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5528 (match_operand:DI 2 "const_int_operand" "")))]
5533 (define_expand "aligned_loadhi"
5534 [(set (match_operand:SI 3 "register_operand" "")
5535 (match_operand:SI 1 "memory_operand" ""))
5536 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5537 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5539 (match_operand:DI 2 "const_int_operand" "")))]
5544 ;; Similar for unaligned loads, where we use the sequence from the
5545 ;; Alpha Architecture manual. We have to distinguish between little-endian
5546 ;; and big-endian systems as the sequences are different.
5548 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5549 ;; operand 3 can overlap the input and output registers.
5551 (define_expand "unaligned_loadqi"
5552 [(use (match_operand:QI 0 "register_operand" ""))
5553 (use (match_operand:DI 1 "address_operand" ""))
5554 (use (match_operand:DI 2 "register_operand" ""))
5555 (use (match_operand:DI 3 "register_operand" ""))]
5558 if (WORDS_BIG_ENDIAN)
5559 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5560 operands[2], operands[3]));
5562 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5563 operands[2], operands[3]));
5567 (define_expand "unaligned_loadqi_le"
5568 [(set (match_operand:DI 2 "register_operand" "")
5569 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5571 (set (match_operand:DI 3 "register_operand" "")
5573 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5574 (zero_extract:DI (match_dup 2)
5576 (ashift:DI (match_dup 3) (const_int 3))))]
5577 "! WORDS_BIG_ENDIAN"
5580 (define_expand "unaligned_loadqi_be"
5581 [(set (match_operand:DI 2 "register_operand" "")
5582 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5584 (set (match_operand:DI 3 "register_operand" "")
5586 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5587 (zero_extract:DI (match_dup 2)
5591 (ashift:DI (match_dup 3) (const_int 3)))))]
5595 (define_expand "unaligned_loadhi"
5596 [(use (match_operand:QI 0 "register_operand" ""))
5597 (use (match_operand:DI 1 "address_operand" ""))
5598 (use (match_operand:DI 2 "register_operand" ""))
5599 (use (match_operand:DI 3 "register_operand" ""))]
5602 if (WORDS_BIG_ENDIAN)
5603 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5604 operands[2], operands[3]));
5606 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5607 operands[2], operands[3]));
5611 (define_expand "unaligned_loadhi_le"
5612 [(set (match_operand:DI 2 "register_operand" "")
5613 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5615 (set (match_operand:DI 3 "register_operand" "")
5617 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5618 (zero_extract:DI (match_dup 2)
5620 (ashift:DI (match_dup 3) (const_int 3))))]
5621 "! WORDS_BIG_ENDIAN"
5624 (define_expand "unaligned_loadhi_be"
5625 [(set (match_operand:DI 2 "register_operand" "")
5626 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5628 (set (match_operand:DI 3 "register_operand" "")
5629 (plus:DI (match_dup 1) (const_int 1)))
5630 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5631 (zero_extract:DI (match_dup 2)
5635 (ashift:DI (match_dup 3) (const_int 3)))))]
5639 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5640 ;; aligned SImode MEM. Operand 1 is the register containing the
5641 ;; byte or word to store. Operand 2 is the number of bits within the word that
5642 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5644 (define_expand "aligned_store"
5645 [(set (match_operand:SI 3 "register_operand" "")
5646 (match_operand:SI 0 "memory_operand" ""))
5647 (set (subreg:DI (match_dup 3) 0)
5648 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5649 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5650 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5651 (match_operand:DI 2 "const_int_operand" "")))
5652 (set (subreg:DI (match_dup 4) 0)
5653 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5654 (set (match_dup 0) (match_dup 4))]
5657 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5658 << INTVAL (operands[2])));
5661 ;; For the unaligned byte and halfword cases, we use code similar to that
5662 ;; in the ;; Architecture book, but reordered to lower the number of registers
5663 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5664 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5665 ;; be the same temporary, if desired. If the address is in a register,
5666 ;; operand 2 can be that register.
5668 (define_expand "unaligned_storeqi"
5669 [(use (match_operand:DI 0 "address_operand" ""))
5670 (use (match_operand:QI 1 "register_operand" ""))
5671 (use (match_operand:DI 2 "register_operand" ""))
5672 (use (match_operand:DI 3 "register_operand" ""))
5673 (use (match_operand:DI 4 "register_operand" ""))]
5676 if (WORDS_BIG_ENDIAN)
5677 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5678 operands[2], operands[3],
5681 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5682 operands[2], operands[3],
5687 (define_expand "unaligned_storeqi_le"
5688 [(set (match_operand:DI 3 "register_operand" "")
5689 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5691 (set (match_operand:DI 2 "register_operand" "")
5694 (and:DI (not:DI (ashift:DI (const_int 255)
5695 (ashift:DI (match_dup 2) (const_int 3))))
5697 (set (match_operand:DI 4 "register_operand" "")
5698 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5699 (ashift:DI (match_dup 2) (const_int 3))))
5700 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5701 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5703 "! WORDS_BIG_ENDIAN"
5706 (define_expand "unaligned_storeqi_be"
5707 [(set (match_operand:DI 3 "register_operand" "")
5708 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5710 (set (match_operand:DI 2 "register_operand" "")
5713 (and:DI (not:DI (ashift:DI (const_int 255)
5714 (minus:DI (const_int 56)
5715 (ashift:DI (match_dup 2) (const_int 3)))))
5717 (set (match_operand:DI 4 "register_operand" "")
5718 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5719 (minus:DI (const_int 56)
5720 (ashift:DI (match_dup 2) (const_int 3)))))
5721 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5722 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5727 (define_expand "unaligned_storehi"
5728 [(use (match_operand:DI 0 "address_operand" ""))
5729 (use (match_operand:HI 1 "register_operand" ""))
5730 (use (match_operand:DI 2 "register_operand" ""))
5731 (use (match_operand:DI 3 "register_operand" ""))
5732 (use (match_operand:DI 4 "register_operand" ""))]
5735 if (WORDS_BIG_ENDIAN)
5736 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5737 operands[2], operands[3],
5740 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5741 operands[2], operands[3],
5746 (define_expand "unaligned_storehi_le"
5747 [(set (match_operand:DI 3 "register_operand" "")
5748 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5750 (set (match_operand:DI 2 "register_operand" "")
5753 (and:DI (not:DI (ashift:DI (const_int 65535)
5754 (ashift:DI (match_dup 2) (const_int 3))))
5756 (set (match_operand:DI 4 "register_operand" "")
5757 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5758 (ashift:DI (match_dup 2) (const_int 3))))
5759 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5760 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5762 "! WORDS_BIG_ENDIAN"
5765 (define_expand "unaligned_storehi_be"
5766 [(set (match_operand:DI 3 "register_operand" "")
5767 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5769 (set (match_operand:DI 2 "register_operand" "")
5770 (plus:DI (match_dup 0) (const_int 1)))
5772 (and:DI (not:DI (ashift:DI
5774 (minus:DI (const_int 56)
5775 (ashift:DI (match_dup 2) (const_int 3)))))
5777 (set (match_operand:DI 4 "register_operand" "")
5778 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5779 (minus:DI (const_int 56)
5780 (ashift:DI (match_dup 2) (const_int 3)))))
5781 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5782 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5787 ;; Here are the define_expand's for QI and HI moves that use the above
5788 ;; patterns. We have the normal sets, plus the ones that need scratch
5789 ;; registers for reload.
5791 (define_expand "movqi"
5792 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5793 (match_operand:QI 1 "general_operand" ""))]
5797 ? alpha_expand_mov (QImode, operands)
5798 : alpha_expand_mov_nobwx (QImode, operands))
5802 (define_expand "movhi"
5803 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5804 (match_operand:HI 1 "general_operand" ""))]
5808 ? alpha_expand_mov (HImode, operands)
5809 : alpha_expand_mov_nobwx (HImode, operands))
5813 ;; Here are the versions for reload. Note that in the unaligned cases
5814 ;; we know that the operand must not be a pseudo-register because stack
5815 ;; slots are always aligned references.
5817 (define_expand "reload_inqi"
5818 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5819 (match_operand:QI 1 "any_memory_operand" "m")
5820 (match_operand:TI 2 "register_operand" "=&r")])]
5825 if (GET_CODE (operands[1]) != MEM)
5828 if (aligned_memory_operand (operands[1], QImode))
5830 seq = gen_reload_inqi_help (operands[0], operands[1],
5831 gen_rtx_REG (SImode, REGNO (operands[2])));
5837 /* It is possible that one of the registers we got for operands[2]
5838 might coincide with that of operands[0] (which is why we made
5839 it TImode). Pick the other one to use as our scratch. */
5840 if (REGNO (operands[0]) == REGNO (operands[2]))
5841 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5843 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5845 addr = get_unaligned_address (operands[1], 0);
5846 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5847 gen_rtx_REG (DImode, REGNO (operands[0])));
5848 alpha_set_memflags (seq, operands[1]);
5854 (define_expand "reload_inhi"
5855 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5856 (match_operand:HI 1 "any_memory_operand" "m")
5857 (match_operand:TI 2 "register_operand" "=&r")])]
5862 if (GET_CODE (operands[1]) != MEM)
5865 if (aligned_memory_operand (operands[1], HImode))
5867 seq = gen_reload_inhi_help (operands[0], operands[1],
5868 gen_rtx_REG (SImode, REGNO (operands[2])));
5874 /* It is possible that one of the registers we got for operands[2]
5875 might coincide with that of operands[0] (which is why we made
5876 it TImode). Pick the other one to use as our scratch. */
5877 if (REGNO (operands[0]) == REGNO (operands[2]))
5878 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5880 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5882 addr = get_unaligned_address (operands[1], 0);
5883 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5884 gen_rtx_REG (DImode, REGNO (operands[0])));
5885 alpha_set_memflags (seq, operands[1]);
5891 (define_expand "reload_outqi"
5892 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5893 (match_operand:QI 1 "register_operand" "r")
5894 (match_operand:TI 2 "register_operand" "=&r")])]
5897 if (GET_CODE (operands[0]) != MEM)
5900 if (aligned_memory_operand (operands[0], QImode))
5902 emit_insn (gen_reload_outqi_help
5903 (operands[0], operands[1],
5904 gen_rtx_REG (SImode, REGNO (operands[2])),
5905 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5909 rtx addr = get_unaligned_address (operands[0], 0);
5910 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5911 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5912 rtx scratch3 = scratch1;
5915 if (GET_CODE (addr) == REG)
5918 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5919 scratch2, scratch3);
5920 alpha_set_memflags (seq, operands[0]);
5926 (define_expand "reload_outhi"
5927 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5928 (match_operand:HI 1 "register_operand" "r")
5929 (match_operand:TI 2 "register_operand" "=&r")])]
5932 if (GET_CODE (operands[0]) != MEM)
5935 if (aligned_memory_operand (operands[0], HImode))
5937 emit_insn (gen_reload_outhi_help
5938 (operands[0], operands[1],
5939 gen_rtx_REG (SImode, REGNO (operands[2])),
5940 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5944 rtx addr = get_unaligned_address (operands[0], 0);
5945 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5946 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5947 rtx scratch3 = scratch1;
5950 if (GET_CODE (addr) == REG)
5953 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5954 scratch2, scratch3);
5955 alpha_set_memflags (seq, operands[0]);
5961 ;; Helpers for the above. The way reload is structured, we can't
5962 ;; always get a proper address for a stack slot during reload_foo
5963 ;; expansion, so we must delay our address manipulations until after.
5965 (define_insn "reload_inqi_help"
5966 [(set (match_operand:QI 0 "register_operand" "=r")
5967 (match_operand:QI 1 "memory_operand" "m"))
5968 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5969 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5972 (define_insn "reload_inhi_help"
5973 [(set (match_operand:HI 0 "register_operand" "=r")
5974 (match_operand:HI 1 "memory_operand" "m"))
5975 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5976 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5979 (define_insn "reload_outqi_help"
5980 [(set (match_operand:QI 0 "memory_operand" "=m")
5981 (match_operand:QI 1 "register_operand" "r"))
5982 (clobber (match_operand:SI 2 "register_operand" "=r"))
5983 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5984 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5987 (define_insn "reload_outhi_help"
5988 [(set (match_operand:HI 0 "memory_operand" "=m")
5989 (match_operand:HI 1 "register_operand" "r"))
5990 (clobber (match_operand:SI 2 "register_operand" "=r"))
5991 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5992 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5996 [(set (match_operand:QI 0 "register_operand" "")
5997 (match_operand:QI 1 "memory_operand" ""))
5998 (clobber (match_operand:SI 2 "register_operand" ""))]
5999 "! TARGET_BWX && reload_completed"
6002 rtx aligned_mem, bitnum;
6003 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6005 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6011 [(set (match_operand:HI 0 "register_operand" "")
6012 (match_operand:HI 1 "memory_operand" ""))
6013 (clobber (match_operand:SI 2 "register_operand" ""))]
6014 "! TARGET_BWX && reload_completed"
6017 rtx aligned_mem, bitnum;
6018 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6020 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6026 [(set (match_operand:QI 0 "memory_operand" "")
6027 (match_operand:QI 1 "register_operand" ""))
6028 (clobber (match_operand:SI 2 "register_operand" ""))
6029 (clobber (match_operand:SI 3 "register_operand" ""))]
6030 "! TARGET_BWX && reload_completed"
6033 rtx aligned_mem, bitnum;
6034 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6035 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6036 operands[2], operands[3]));
6041 [(set (match_operand:HI 0 "memory_operand" "")
6042 (match_operand:HI 1 "register_operand" ""))
6043 (clobber (match_operand:SI 2 "register_operand" ""))
6044 (clobber (match_operand:SI 3 "register_operand" ""))]
6045 "! TARGET_BWX && reload_completed"
6048 rtx aligned_mem, bitnum;
6049 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6050 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6051 operands[2], operands[3]));
6055 ;; Bit field extract patterns which use ext[wlq][lh]
6057 (define_expand "extv"
6058 [(set (match_operand:DI 0 "register_operand" "")
6059 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6060 (match_operand:DI 2 "immediate_operand" "")
6061 (match_operand:DI 3 "immediate_operand" "")))]
6066 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6067 if (INTVAL (operands[3]) % 8 != 0
6068 || (INTVAL (operands[2]) != 16
6069 && INTVAL (operands[2]) != 32
6070 && INTVAL (operands[2]) != 64))
6073 /* From mips.md: extract_bit_field doesn't verify that our source
6074 matches the predicate, so we force it to be a MEM here. */
6075 if (GET_CODE (operands[1]) != MEM)
6078 /* The bit number is relative to the mode of operand 1 which is
6079 usually QImode (this might actually be a bug in expmed.c). Note
6080 that the bit number is negative in big-endian mode in this case.
6081 We have to convert that to the offset. */
6082 if (WORDS_BIG_ENDIAN)
6083 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6084 - INTVAL (operands[2]) - INTVAL (operands[3]);
6086 ofs = INTVAL (operands[3]);
6090 alpha_expand_unaligned_load (operands[0], operands[1],
6091 INTVAL (operands[2]) / 8,
6096 (define_expand "extzv"
6097 [(set (match_operand:DI 0 "register_operand" "")
6098 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6099 (match_operand:DI 2 "immediate_operand" "")
6100 (match_operand:DI 3 "immediate_operand" "")))]
6103 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6104 if (INTVAL (operands[3]) % 8 != 0
6105 || (INTVAL (operands[2]) != 8
6106 && INTVAL (operands[2]) != 16
6107 && INTVAL (operands[2]) != 32
6108 && INTVAL (operands[2]) != 64))
6111 if (GET_CODE (operands[1]) == MEM)
6115 /* Fail 8 bit fields, falling back on a simple byte load. */
6116 if (INTVAL (operands[2]) == 8)
6119 /* The bit number is relative to the mode of operand 1 which is
6120 usually QImode (this might actually be a bug in expmed.c). Note
6121 that the bit number is negative in big-endian mode in this case.
6122 We have to convert that to the offset. */
6123 if (WORDS_BIG_ENDIAN)
6124 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6125 - INTVAL (operands[2]) - INTVAL (operands[3]);
6127 ofs = INTVAL (operands[3]);
6131 alpha_expand_unaligned_load (operands[0], operands[1],
6132 INTVAL (operands[2]) / 8,
6138 (define_expand "insv"
6139 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6140 (match_operand:DI 1 "immediate_operand" "")
6141 (match_operand:DI 2 "immediate_operand" ""))
6142 (match_operand:DI 3 "register_operand" ""))]
6147 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6148 if (INTVAL (operands[2]) % 8 != 0
6149 || (INTVAL (operands[1]) != 16
6150 && INTVAL (operands[1]) != 32
6151 && INTVAL (operands[1]) != 64))
6154 /* From mips.md: store_bit_field doesn't verify that our source
6155 matches the predicate, so we force it to be a MEM here. */
6156 if (GET_CODE (operands[0]) != MEM)
6159 /* The bit number is relative to the mode of operand 1 which is
6160 usually QImode (this might actually be a bug in expmed.c). Note
6161 that the bit number is negative in big-endian mode in this case.
6162 We have to convert that to the offset. */
6163 if (WORDS_BIG_ENDIAN)
6164 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6165 - INTVAL (operands[1]) - INTVAL (operands[2]);
6167 ofs = INTVAL (operands[2]);
6171 alpha_expand_unaligned_store (operands[0], operands[3],
6172 INTVAL (operands[1]) / 8, ofs);
6176 ;; Block move/clear, see alpha.c for more details.
6177 ;; Argument 0 is the destination
6178 ;; Argument 1 is the source
6179 ;; Argument 2 is the length
6180 ;; Argument 3 is the alignment
6182 (define_expand "movstrqi"
6183 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6184 (match_operand:BLK 1 "memory_operand" ""))
6185 (use (match_operand:DI 2 "immediate_operand" ""))
6186 (use (match_operand:DI 3 "immediate_operand" ""))])]
6189 if (alpha_expand_block_move (operands))
6195 (define_expand "clrstrqi"
6196 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6198 (use (match_operand:DI 1 "immediate_operand" ""))
6199 (use (match_operand:DI 2 "immediate_operand" ""))])]
6202 if (alpha_expand_block_clear (operands))
6208 ;; Subroutine of stack space allocation. Perform a stack probe.
6209 (define_expand "probe_stack"
6210 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6213 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6214 INTVAL (operands[0])));
6215 MEM_VOLATILE_P (operands[1]) = 1;
6217 operands[0] = const0_rtx;
6220 ;; This is how we allocate stack space. If we are allocating a
6221 ;; constant amount of space and we know it is less than 4096
6222 ;; bytes, we need do nothing.
6224 ;; If it is more than 4096 bytes, we need to probe the stack
6226 (define_expand "allocate_stack"
6228 (plus:DI (reg:DI 30)
6229 (match_operand:DI 1 "reg_or_cint_operand" "")))
6230 (set (match_operand:DI 0 "register_operand" "=r")
6234 if (GET_CODE (operands[1]) == CONST_INT
6235 && INTVAL (operands[1]) < 32768)
6237 if (INTVAL (operands[1]) >= 4096)
6239 /* We do this the same way as in the prologue and generate explicit
6240 probes. Then we update the stack by the constant. */
6244 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6245 while (probed + 8192 < INTVAL (operands[1]))
6246 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6248 if (probed + 4096 < INTVAL (operands[1]))
6249 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6252 operands[1] = GEN_INT (- INTVAL (operands[1]));
6253 operands[2] = virtual_stack_dynamic_rtx;
6258 rtx loop_label = gen_label_rtx ();
6259 rtx want = gen_reg_rtx (Pmode);
6260 rtx tmp = gen_reg_rtx (Pmode);
6263 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6264 force_reg (Pmode, operands[1])));
6265 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6267 if (GET_CODE (operands[1]) != CONST_INT)
6269 out_label = gen_label_rtx ();
6270 emit_insn (gen_cmpdi (want, tmp));
6271 emit_jump_insn (gen_bgeu (out_label));
6274 emit_label (loop_label);
6275 memref = gen_rtx_MEM (DImode, tmp);
6276 MEM_VOLATILE_P (memref) = 1;
6277 emit_move_insn (memref, const0_rtx);
6278 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6279 emit_insn (gen_cmpdi (tmp, want));
6280 emit_jump_insn (gen_bgtu (loop_label));
6282 memref = gen_rtx_MEM (DImode, want);
6283 MEM_VOLATILE_P (memref) = 1;
6284 emit_move_insn (memref, const0_rtx);
6287 emit_label (out_label);
6289 emit_move_insn (stack_pointer_rtx, want);
6290 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6295 ;; This is used by alpha_expand_prolog to do the same thing as above,
6296 ;; except we cannot at that time generate new basic blocks, so we hide
6297 ;; the loop in this one insn.
6299 (define_insn "prologue_stack_probe_loop"
6300 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6301 (match_operand:DI 1 "register_operand" "r")]
6305 operands[2] = gen_label_rtx ();
6306 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6307 CODE_LABEL_NUMBER (operands[2]));
6309 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6311 [(set_attr "length" "16")
6312 (set_attr "type" "multi")])
6314 (define_expand "prologue"
6315 [(clobber (const_int 0))]
6318 alpha_expand_prologue ();
6322 ;; These take care of emitting the ldgp insn in the prologue. This will be
6323 ;; an lda/ldah pair and we want to align them properly. So we have two
6324 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6325 ;; and the second of which emits nothing. However, both are marked as type
6326 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6329 (define_expand "prologue_ldgp"
6331 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6333 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6336 operands[0] = pic_offset_table_rtx;
6337 operands[1] = gen_rtx_REG (Pmode, 27);
6338 operands[2] = (TARGET_EXPLICIT_RELOCS
6339 ? GEN_INT (alpha_next_sequence_number++)
6343 (define_insn "*ldgp_er_1"
6344 [(set (match_operand:DI 0 "register_operand" "=r")
6345 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6346 (match_operand 2 "const_int_operand" "")]
6348 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6349 "ldah %0,0(%1)\t\t!gpdisp!%2")
6351 (define_insn "*ldgp_er_2"
6352 [(set (match_operand:DI 0 "register_operand" "=r")
6353 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6354 (match_operand 2 "const_int_operand" "")]
6356 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6357 "lda %0,0(%1)\t\t!gpdisp!%2")
6359 (define_insn "*prologue_ldgp_er_2"
6360 [(set (match_operand:DI 0 "register_operand" "=r")
6361 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6362 (match_operand 2 "const_int_operand" "")]
6364 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6365 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6367 (define_insn "*prologue_ldgp_1"
6368 [(set (match_operand:DI 0 "register_operand" "=r")
6369 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6370 (match_operand 2 "const_int_operand" "")]
6373 "ldgp %0,0(%1)\n$%~..ng:")
6375 (define_insn "*prologue_ldgp_2"
6376 [(set (match_operand:DI 0 "register_operand" "=r")
6377 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6378 (match_operand 2 "const_int_operand" "")]
6383 ;; The _mcount profiling hook has special calling conventions, and
6384 ;; does not clobber all the registers that a normal call would. So
6385 ;; hide the fact this is a call at all.
6387 (define_insn "prologue_mcount"
6388 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6390 "lda $28,_mcount\;jsr $28,($28),_mcount"
6391 [(set_attr "type" "multi")
6392 (set_attr "length" "8")])
6394 (define_insn "init_fp"
6395 [(set (match_operand:DI 0 "register_operand" "=r")
6396 (match_operand:DI 1 "register_operand" "r"))
6397 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6401 (define_expand "epilogue"
6405 alpha_expand_epilogue ();
6408 (define_expand "sibcall_epilogue"
6412 alpha_expand_epilogue ();
6416 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6417 ;; the frame size into a register. We use this pattern to ensure
6418 ;; we get lda instead of addq.
6419 (define_insn "nt_lda"
6420 [(set (match_operand:DI 0 "register_operand" "=r")
6421 (unspec:DI [(match_dup 0)
6422 (match_operand:DI 1 "const_int_operand" "n")]
6427 (define_expand "builtin_longjmp"
6428 [(use (match_operand:DI 0 "register_operand" "r"))]
6431 /* The elements of the buffer are, in order: */
6432 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6433 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6434 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6435 rtx pv = gen_rtx_REG (Pmode, 27);
6437 /* This bit is the same as expand_builtin_longjmp. */
6438 emit_move_insn (hard_frame_pointer_rtx, fp);
6439 emit_move_insn (pv, lab);
6440 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6441 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6442 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6444 /* Load the label we are jumping through into $27 so that we know
6445 where to look for it when we get back to setjmp's function for
6446 restoring the gp. */
6447 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6452 ;; This is effectively a copy of indirect_jump, but constrained such
6453 ;; that register renaming cannot foil our cunning plan with $27.
6454 (define_insn "builtin_longjmp_internal"
6456 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6460 [(set_attr "type" "ibr")])
6462 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6463 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6464 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6465 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6467 (define_insn "*builtin_setjmp_receiver_er_1"
6468 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6469 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6470 "br $27,$LSJ%=\n$LSJ%=:"
6471 [(set_attr "type" "ibr")])
6474 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6475 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6476 && prev_nonnote_insn (insn) == operands[0]"
6480 (define_insn "*builtin_setjmp_receiver_1"
6481 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6483 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6484 [(set_attr "length" "12")
6485 (set_attr "type" "multi")])
6487 (define_expand "builtin_setjmp_receiver_er"
6488 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6490 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6492 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6495 operands[1] = pic_offset_table_rtx;
6496 operands[2] = gen_rtx_REG (Pmode, 27);
6497 operands[3] = GEN_INT (alpha_next_sequence_number++);
6500 (define_expand "builtin_setjmp_receiver"
6501 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6504 if (TARGET_EXPLICIT_RELOCS)
6506 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6511 (define_expand "exception_receiver_er"
6513 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6515 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6518 operands[0] = pic_offset_table_rtx;
6519 operands[1] = gen_rtx_REG (Pmode, 26);
6520 operands[2] = GEN_INT (alpha_next_sequence_number++);
6523 (define_expand "exception_receiver"
6524 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6527 if (TARGET_LD_BUGGY_LDGP)
6528 operands[0] = alpha_gp_save_rtx ();
6529 else if (TARGET_EXPLICIT_RELOCS)
6531 emit_insn (gen_exception_receiver_er ());
6535 operands[0] = const0_rtx;
6538 (define_insn "*exception_receiver_1"
6539 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6540 "! TARGET_LD_BUGGY_LDGP"
6542 [(set_attr "length" "8")
6543 (set_attr "type" "multi")])
6545 (define_insn "*exception_receiver_2"
6546 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
6548 "TARGET_LD_BUGGY_LDGP"
6552 [(set_attr "type" "ilog,ild")])
6554 (define_expand "nonlocal_goto_receiver"
6555 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6556 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6557 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6559 "TARGET_ABI_OPEN_VMS"
6562 (define_insn "arg_home"
6563 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6578 (clobber (mem:BLK (const_int 0)))
6579 (clobber (reg:DI 24))
6580 (clobber (reg:DI 25))
6581 (clobber (reg:DI 0))]
6582 "TARGET_ABI_OPEN_VMS"
6583 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6584 [(set_attr "length" "16")
6585 (set_attr "type" "multi")])
6587 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6589 (define_expand "umk_mismatch_args"
6590 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6591 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6592 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6593 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6596 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6597 "TARGET_ABI_UNICOSMK"
6599 operands[1] = gen_reg_rtx (DImode);
6600 operands[2] = gen_reg_rtx (DImode);
6601 operands[3] = gen_reg_rtx (DImode);
6604 (define_insn "arg_home_umk"
6605 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6620 (clobber (mem:BLK (const_int 0)))
6622 (clobber (reg:DI 22))
6623 (clobber (reg:DI 23))
6624 (clobber (reg:DI 24))
6625 (clobber (reg:DI 0))
6626 (clobber (reg:DI 1))
6627 (clobber (reg:DI 2))
6628 (clobber (reg:DI 3))
6629 (clobber (reg:DI 4))
6630 (clobber (reg:DI 5))
6631 (clobber (reg:DI 6))
6632 (clobber (reg:DI 7))
6633 (clobber (reg:DI 8))])]
6634 "TARGET_ABI_UNICOSMK"
6635 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6636 [(set_attr "length" "16")
6637 (set_attr "type" "multi")])
6639 ;; Close the trap shadow of preceeding instructions. This is generated
6642 (define_insn "trapb"
6643 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6646 [(set_attr "type" "misc")])
6648 ;; No-op instructions used by machine-dependant reorg to preserve
6649 ;; alignment for instruction issue.
6650 ;; The Unicos/Mk assembler does not support these opcodes.
6656 [(set_attr "type" "ilog")])
6661 "cpys $f31,$f31,$f31"
6662 [(set_attr "type" "fcpys")])
6669 ;; On Unicos/Mk we use a macro for aligning code.
6671 (define_insn "realign"
6672 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6676 if (TARGET_ABI_UNICOSMK)
6677 return "gcc@code@align %0";
6679 return ".align %0 #realign";
6682 ;; The call patterns are at the end of the file because their
6683 ;; wildcard operand0 interferes with nice recognition.
6685 (define_insn "*call_value_osf_1_er"
6686 [(set (match_operand 0 "" "")
6687 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6688 (match_operand 2 "" "")))
6690 (clobber (reg:DI 26))]
6691 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6693 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6695 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6696 [(set_attr "type" "jsr")
6697 (set_attr "length" "12,*,16")])
6699 ;; We must use peep2 instead of a split because we need accurate life
6700 ;; information for $gp. Consider the case of { bar(); while (1); }.
6702 [(parallel [(set (match_operand 0 "" "")
6703 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6704 (match_operand 2 "" "")))
6706 (clobber (reg:DI 26))])]
6707 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6708 && ! current_file_function_operand (operands[0], Pmode)
6709 && peep2_regno_dead_p (1, 29)"
6710 [(parallel [(set (match_dup 0)
6711 (call (mem:DI (match_dup 3))
6713 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6714 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6715 (use (match_dup 1))])]
6717 if (CONSTANT_P (operands[1]))
6719 operands[3] = gen_rtx_REG (Pmode, 27);
6720 emit_move_insn (operands[3], operands[1]);
6724 operands[3] = operands[1];
6725 operands[1] = const0_rtx;
6730 [(parallel [(set (match_operand 0 "" "")
6731 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6732 (match_operand 2 "" "")))
6734 (clobber (reg:DI 26))])]
6735 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6736 && ! current_file_function_operand (operands[0], Pmode)
6737 && ! peep2_regno_dead_p (1, 29)"
6738 [(parallel [(set (match_dup 0)
6739 (call (mem:DI (match_dup 3))
6741 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6742 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6743 (use (match_dup 1))])
6745 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6747 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6749 if (CONSTANT_P (operands[1]))
6751 operands[3] = gen_rtx_REG (Pmode, 27);
6752 emit_move_insn (operands[3], operands[1]);
6756 operands[3] = operands[1];
6757 operands[1] = const0_rtx;
6759 operands[4] = GEN_INT (alpha_next_sequence_number++);
6762 ;; We add a blockage unspec_volatile to prevent insns from moving down
6763 ;; from above the call to in between the call and the ldah gpdisp.
6764 (define_insn "*call_value_osf_2_er"
6765 [(set (match_operand 0 "" "")
6766 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6767 (match_operand 2 "" "")))
6769 (plus:DI (pc) (const_int 4)))
6770 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6771 (use (match_operand 3 "" ""))]
6772 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6774 [(set_attr "type" "jsr")])
6776 (define_insn "*call_value_osf_1_noreturn"
6777 [(set (match_operand 0 "" "")
6778 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6779 (match_operand 2 "" "")))
6781 (clobber (reg:DI 26))]
6782 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6783 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6788 [(set_attr "type" "jsr")
6789 (set_attr "length" "*,*,8")])
6791 (define_insn "*call_value_osf_1"
6792 [(set (match_operand 0 "" "")
6793 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6794 (match_operand 2 "" "")))
6796 (clobber (reg:DI 26))]
6797 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6799 jsr $26,($27),0\;ldgp $29,0($26)
6801 jsr $26,%1\;ldgp $29,0($26)"
6802 [(set_attr "type" "jsr")
6803 (set_attr "length" "12,*,16")])
6805 (define_insn "*sibcall_value_osf_1"
6806 [(set (match_operand 0 "" "")
6807 (call (mem:DI (match_operand:DI 1 "current_file_function_operand" "R"))
6808 (match_operand 2 "" "")))
6812 [(set_attr "type" "jsr")])
6814 (define_insn "*call_value_nt_1"
6815 [(set (match_operand 0 "" "")
6816 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
6817 (match_operand 2 "" "")))
6818 (clobber (reg:DI 26))]
6819 "TARGET_ABI_WINDOWS_NT"
6824 [(set_attr "type" "jsr")
6825 (set_attr "length" "*,*,12")])
6827 (define_insn "*call_value_vms_1"
6828 [(set (match_operand 0 "" "")
6829 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
6830 (match_operand 2 "" "")))
6831 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6834 (clobber (reg:DI 27))]
6835 "TARGET_ABI_OPEN_VMS"
6837 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6838 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6839 [(set_attr "type" "jsr")
6840 (set_attr "length" "12,16")])
6842 (define_insn "*call_value_umk"
6843 [(set (match_operand 0 "" "")
6844 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
6845 (match_operand 2 "" "")))
6847 (clobber (reg:DI 26))]
6848 "TARGET_ABI_UNICOSMK"
6850 [(set_attr "type" "jsr")])